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2024-03-22qemuriscv: Fix kbd and mouse emulation for qemuriscv64Khem Raj
Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2023-11-05qemuriscv: Add to common MACHINE_FEATURES instead of overriding themKhem Raj
machine features like vfat are needed for ptests to pass ( e..g. parted) This brings it closer to what x86 qemu config looks like as well. Signed-off-by: Khem Raj <raj.khem@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2023-10-11meta/conf/machine: remove SERIAL_CONSOLES_CHECKRoss Burton
There's no need for this variable anymore, as all consoles listed in SERIAL_CONSOLES are checked for their existence before a getty is started. Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2023-10-10runqemu/qemurunner: Use nodelay with tcp serial connectionsRichard Purdie
This disables Nagle's algorithm for our tcp serial connections which may be causing data transfer issues. Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2023-02-24tune-riscv.inc: Add riscv64nc to available tunes listKhem Raj
This was missed when riscv64nc was added Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2023-02-23QB_SMP: allow user modificationTrevor Woerner
Allow a user to override the QM_SMP value giving them the opportunity to select for themselves the number of CPUs to use in qemu. Signed-off-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2022-04-19riscv: Add tunes for rv64 without compressed instructionsKhem Raj
Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2022-03-20qemuriscv: Use virtio-tablet-pci for mouseKhem Raj
This helps in making mouse response better where transition between host and guest mouse is abrupt and not precise and as a result its difficult to access stuff near the edges. Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2021-07-30Convert to new override syntaxRichard Purdie
This is the result of automated script conversion: scripts/contrib/convert-overrides.py <oe-core directory> converting the metadata to use ":" as the override character instead of "_". Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2021-06-12qemuriscv: Enable 4 core emulationKhem Raj
Helps in running tests a bit faster Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2021-04-05conf/machine: Enable keyboard and mouse on RISC-V machinesAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2021-04-05conf/machine: Enable bochs-display on RISC-V machinesAlistair Francis
Enable the bochs-display as q QEMU argument when running on RISC-V machines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2020-12-18qemuriscv: check serial consoles w.r.t. /proc/consolesKhem Raj
qemuriscv enables hvc0 along with ttyS0, however its not enabled in /proc/consoles, getty tries to enable it in inittab and erroring out Fixes below message with sysvinit INIT: Id "hvc0" respawning too fast: disabled for 5 minutes Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2020-11-17arch-riscv: Enable qemu-usermode on rv32Khem Raj
Current version of Qemu in OE-core now works fine in rv32/user-mode the said nvalid instruction errors are gone, so we can enable it now Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2020-10-17tune-riscv.inc: use nf suffix also for TUNE_PKGARCHMartin Jansa
* broken since introduction: commit 5263b2ebc57fe289d64c74bfb10da39ed7c98828 Author: Alistair Francis <alistair.francis@wdc.com> Date: Thu Dec 19 13:24:10 2019 -0800 tune-riscv: Add support for no float * fixes: scripts/tune/log.fake-riscv.riscv32nf: Error, the PACKAGE_ARCHS variable (all any noarch riscv32nf fake_riscv) for DEFAULTTUNE (riscv32nf) does not contain TUNE_PKGARCH (riscv32). scripts/tune/log.fake-riscv.riscv64nf: Error, the PACKAGE_ARCHS variable (all any noarch riscv64nf fake_riscv) for DEFAULTTUNE (riscv64nf) does not contain TUNE_PKGARCH (riscv64). Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2020-09-24qemuboot: Add QB_RNG variableKhem Raj
RNG passthru has been enabled on all qemu machines but its being added to each one of them, with this patch its turned into QB variables which defaults to host passthru, yet it can be overridden if needed via machine or config metadata if needed. Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2020-06-28opensbi: Update to OpenSBI v0.8 releaseAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-12-30tune-riscv: Add support for no floatAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-11-29machine/arch-riscv: Fix newlib and baremetal buildsAlistair Francis
Fix the following errors for newlib and baremetal libcs: ld: unrecognized option '--hash-style=sysv' ld: unrecognized option '--hash-style=gnu' Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Ross Burton <ross.burton@intel.com>
2019-09-27qemuriscv: Do not blacklist clang anymoreKhem Raj
clang 9.x ( which is now default in meta-clang ) supports riscv Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-09-01qemuriscv: Generate a wic rootFS with a larger filesystemAlistair Francis
This allows us to generate a rootFS with a large filesystem for use with QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-09-01tune-riscv: Drop littleendian and introduce bigendian tuneKhem Raj
Default riscv is little-endian moreover most of other arches define bigendian as tune and treats absense as litteendian, this make risc-v fall in line Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-08-29qemu: set default RAM to 256M for all machinesAlexander Kanavin
There was a discussion about what amount of RAM is appropriate for a default; the outcome was that for now it is still 256M. Some qemu machine definitions have however set this to 512M so for the sake of treating all architectures fairly, they are reset back to 256M. Also runqemu is adjusted to use 256M if QB_MEM is not set at all. http://lists.openembedded.org/pipermail/openembedded-core/2019-August/285900.html Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-08-21qemuriscv64: Specify the firmware as a bios instead of kernelAlistair Francis
Now that we have a -bios option for the RISC-V virt machine in QEMU we can pass OpenSBI in via -bios and the kernel in via -kernel. We no longer need to pass the kernel in via -device loader so let's remove that. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-06-20qemuriscv: Build uImage for RISC-V machinesAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
2019-06-19qemuriscv64: Add the QEMU RISC-V 64-bit machineAlistair Francis
The include is split ready to add the 32-bit RISC-V machine as soon as glibc supports 32-bit RISC-V. This is based on the work in the meta-riscv layer, thanks to Khem for starting this. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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