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authorKhem Raj <raj.khem@gmail.com>2021-09-30 21:54:27 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2021-10-11 18:41:02 +0100
commit269133fed2854cdfe9c23a17a86fb1f1ea7e11cb (patch)
tree122f057be31268dc87da8a5bdbce4f54aca1661e /meta/recipes-support/libseccomp/files/0001-arch-Add-riscv32-architecture-support.patch
parent97a2f406635f51bad1ab070f018a6466209f257b (diff)
downloadopenembedded-core-269133fed2854cdfe9c23a17a86fb1f1ea7e11cb.tar.gz
libseccomp: Upgrade to 2.5.2 and beyond
Forward port the rv32 port Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'meta/recipes-support/libseccomp/files/0001-arch-Add-riscv32-architecture-support.patch')
-rw-r--r--meta/recipes-support/libseccomp/files/0001-arch-Add-riscv32-architecture-support.patch162
1 files changed, 78 insertions, 84 deletions
diff --git a/meta/recipes-support/libseccomp/files/0001-arch-Add-riscv32-architecture-support.patch b/meta/recipes-support/libseccomp/files/0001-arch-Add-riscv32-architecture-support.patch
index 62bd61fb56..2fd22b1aa2 100644
--- a/meta/recipes-support/libseccomp/files/0001-arch-Add-riscv32-architecture-support.patch
+++ b/meta/recipes-support/libseccomp/files/0001-arch-Add-riscv32-architecture-support.patch
@@ -1,18 +1,18 @@
-From 6d127a0463ea2d7bb5021562678324e28e0407e5 Mon Sep 17 00:00:00 2001
+From e99b00a78acaf80236cba8b3fabaebdb3ef1987b Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Tue, 8 Jun 2021 19:45:34 -0700
-Subject: [PATCH 1/2] arch: Add riscv32 architecture support
+Subject: [PATCH 1/4] arch: Add riscv32 architecture support
Support for rv32 was upstreamed into 5.4+ kernel
-
Upstream-Status: Submitted [https://github.com/seccomp/libseccomp/pull/327]
+
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
CREDITS | 1 +
README.md | 1 +
doc/man/man1/scmp_sys_resolver.1 | 2 +-
doc/man/man3/seccomp_arch_add.3 | 1 +
- include/seccomp-syscalls.h | 31 ++++++++++++++++++
+ include/seccomp-syscalls.h | 32 +++++++++++++++++++
include/seccomp.h.in | 9 ++++++
src/Makefile.am | 1 +
src/arch-riscv32.c | 31 ++++++++++++++++++
@@ -24,7 +24,6 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
src/python/libseccomp.pxd | 1 +
src/python/seccomp.pyx | 2 ++
src/syscalls.c | 1 +
- src/syscalls.csv | 2 +-
src/syscalls.h | 2 ++
src/system.c | 1 +
tests/15-basic-resolver.c | 1 +
@@ -40,12 +39,12 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
tools/scmp_bpf_sim.c | 2 ++
tools/util.c | 6 +++-
tools/util.h | 7 ++++
- 32 files changed, 208 insertions(+), 7 deletions(-)
+ 31 files changed, 208 insertions(+), 6 deletions(-)
create mode 100644 src/arch-riscv32.c
create mode 100644 src/arch-riscv32.h
diff --git a/CREDITS b/CREDITS
-index d6bbc2a..ad2f7e0 100644
+index b685712..c1ffdb3 100644
--- a/CREDITS
+++ b/CREDITS
@@ -33,6 +33,7 @@ John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
@@ -55,9 +54,9 @@ index d6bbc2a..ad2f7e0 100644
+Khem Raj <raj.khem@gmail.com>
Kyle R. Conway <kyle.r.conway@gmail.com>
Kenta Tada <Kenta.Tada@sony.com>
- Luca Bruno <lucab@debian.org>
+ Kir Kolyshkin <kolyshkin@gmail.com>
diff --git a/README.md b/README.md
-index ba02186..2cd718f 100644
+index 579f226..8199a71 100644
--- a/README.md
+++ b/README.md
@@ -54,6 +54,7 @@ The libseccomp library currently supports the architectures listed below:
@@ -67,7 +66,7 @@ index ba02186..2cd718f 100644
+* 32-bit RISC-V (riscv32)
* 32-bit SuperH big endian (sheb)
* 32-bit SuperH (sh)
-
+
diff --git a/doc/man/man1/scmp_sys_resolver.1 b/doc/man/man1/scmp_sys_resolver.1
index 267187b..fc68d18 100644
--- a/doc/man/man1/scmp_sys_resolver.1
@@ -94,93 +93,94 @@ index 7baa21e..8966b3a 100644
.sp
.BI "uint32_t seccomp_arch_resolve_name(const char *" arch_name ");"
diff --git a/include/seccomp-syscalls.h b/include/seccomp-syscalls.h
-index c694db1..c6ea5ca 100644
+index 476f953..4ff814c 100644
--- a/include/seccomp-syscalls.h
+++ b/include/seccomp-syscalls.h
-@@ -275,6 +275,13 @@
- #define __PNR_ppoll -10241
+@@ -276,6 +276,14 @@
#define __PNR_renameat -10242
#define __PNR_riscv_flush_icache -10243
-+#define __PNR_fstat -10244
-+#define __PNR_futex -10245
-+#define __PNR_nanosleep -10246
-+#define __PNR_lseek -10247
-+#define __PNR_clock_gettime -10248
-+#define __PNR_clock_nanosleep -10249
-+#define __PNR_gettimeofday -10250
-
+ #define __PNR_memfd_secret -10244
++#define __PNR_fstat -10245
++#define __PNR_futex -10246
++#define __PNR_nanosleep -10247
++#define __PNR_lseek -10248
++#define __PNR_clock_gettime -10249
++#define __PNR_clock_nanosleep -10250
++#define __PNR_gettimeofday -10251
++#define __PNR_fcntl -10252
+
/*
* libseccomp syscall definitions
-@@ -442,7 +449,11 @@
+@@ -443,7 +451,11 @@
#define __SNR_clock_getres_time64 __PNR_clock_getres_time64
#endif
-
+
+#ifdef __NR_clock_gettime
#define __SNR_clock_gettime __NR_clock_gettime
+#else
+#define __SNR_clock_gettime __PNR_clock_gettime
+#endif
-
+
#ifdef __NR_clock_gettime64
#define __SNR_clock_gettime64 __NR_clock_gettime64
-@@ -450,7 +461,11 @@
+@@ -451,7 +463,11 @@
#define __SNR_clock_gettime64 __PNR_clock_gettime64
#endif
-
+
+#ifdef __NR_clock_nanosleep
#define __SNR_clock_nanosleep __NR_clock_nanosleep
+#else
+#define __SNR_clock_nanosleep __PNR_clock_nanosleep
+#endif
-
+
#ifdef __NR_clock_nanosleep_time64
#define __SNR_clock_nanosleep_time64 __NR_clock_nanosleep_time64
-@@ -710,7 +725,11 @@
+@@ -713,7 +729,11 @@
#define __SNR_ftruncate64 __PNR_ftruncate64
#endif
-
+
+#ifdef __NR_futex
#define __SNR_futex __NR_futex
+#else
+#define __SNR_futex __PNR_futex
+#endif
-
+
#ifdef __NR_futex_time64
#define __SNR_futex_time64 __NR_futex_time64
-@@ -896,7 +915,11 @@
-
+@@ -899,7 +919,11 @@
+
#define __SNR_gettid __NR_gettid
-
+
+#ifdef __NR_gettimeofday
#define __SNR_gettimeofday __NR_gettimeofday
+#else
+#define __SNR_gettimeofday __PNR_gettimeofday
+#endif
-
+
#ifdef __NR_getuid
#define __SNR_getuid __NR_getuid
-@@ -1046,7 +1069,11 @@
-
+@@ -1049,7 +1073,11 @@
+
#define __SNR_lremovexattr __NR_lremovexattr
-
+
+#ifdef __NR_lseek
#define __SNR_lseek __NR_lseek
+#else
+#define __SNR_lseek __PNR_lseek
+#endif
-
+
#define __SNR_lsetxattr __NR_lsetxattr
-
-@@ -1218,7 +1245,11 @@
-
+
+@@ -1227,7 +1255,11 @@
+
#define __SNR_name_to_handle_at __NR_name_to_handle_at
-
+
+#ifdef __NR_nanosleep
#define __SNR_nanosleep __NR_nanosleep
+#else
+#define __SNR_nanosleep __PNR_nanosleep
+#endif
-
+
#ifdef __NR_newfstatat
#define __SNR_newfstatat __NR_newfstatat
diff --git a/include/seccomp.h.in b/include/seccomp.h.in
@@ -201,14 +201,14 @@ index 333a89c..2e911db 100644
+
#define SCMP_ARCH_RISCV64 AUDIT_ARCH_RISCV64
+#define SCMP_ARCH_RISCV32 AUDIT_ARCH_RISCV32
-
+
/**
* The SuperH architecture tokens
diff --git a/src/Makefile.am b/src/Makefile.am
-index 7b59810..7961925 100644
+index 04e7ba5..a30bbc0 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
-@@ -44,6 +44,7 @@ SOURCES_ALL = \
+@@ -40,6 +40,7 @@ SOURCES_ALL = \
arch-ppc.h arch-ppc.c \
arch-ppc64.h arch-ppc64.c \
arch-riscv64.h arch-riscv64.c \
@@ -218,7 +218,7 @@ index 7b59810..7961925 100644
arch-sh.h arch-sh.c \
diff --git a/src/arch-riscv32.c b/src/arch-riscv32.c
new file mode 100644
-index 0000000..53b3126
+index 0000000..10418f4
--- /dev/null
+++ b/src/arch-riscv32.c
@@ -0,0 +1,31 @@
@@ -248,8 +248,8 @@ index 0000000..53b3126
+ .token_bpf = AUDIT_ARCH_RISCV32,
+ .size = ARCH_SIZE_32,
+ .endian = ARCH_ENDIAN_LITTLE,
-+ .syscall_resolve_name = riscv32_syscall_resolve_name,
-+ .syscall_resolve_num = riscv32_syscall_resolve_num,
++ .syscall_resolve_name_raw = riscv32_syscall_resolve_name,
++ .syscall_resolve_num_raw = riscv32_syscall_resolve_num,
+ .syscall_rewrite = NULL,
+ .rule_add = NULL,
+};
@@ -310,7 +310,7 @@ index 68bebef..85c7f3d 100755
@@ -519,6 +519,49 @@ function dump_lib_riscv64() {
dump_lib_arch riscv64 | mangle_lib_syscall riscv64
}
-
+
+#
+# Dump the riscv32 system syscall table
+#
@@ -385,9 +385,9 @@ index 68bebef..85c7f3d 100755
+ abi_list+=" riscv32 riscv64"
abi_list+=" s390 s390x"
abi_list+=" sh"
-
+
diff --git a/src/arch.c b/src/arch.c
-index 6ab922f..acf80af 100644
+index 921e455..07935a9 100644
--- a/src/arch.c
+++ b/src/arch.c
@@ -43,6 +43,7 @@
@@ -453,10 +453,10 @@ index 0629bf1..000d503 100644
SCMP_ARCH_S390X
+ SCMP_ARCH_RISCV32
SCMP_ARCH_RISCV64
-
+
cdef enum scmp_filter_attr:
diff --git a/src/python/seccomp.pyx b/src/python/seccomp.pyx
-index 1a9eb24..c94ad1d 100644
+index 2eeabc1..2895d78 100644
--- a/src/python/seccomp.pyx
+++ b/src/python/seccomp.pyx
@@ -214,6 +214,7 @@ cdef class Arch:
@@ -466,36 +466,29 @@ index 1a9eb24..c94ad1d 100644
+ RISCV32 - 32-bit RISC-V
RISCV64 - 64-bit RISC-V
"""
-
+
@@ -238,6 +239,7 @@ cdef class Arch:
PPC64LE = libseccomp.SCMP_ARCH_PPC64LE
S390 = libseccomp.SCMP_ARCH_S390
S390X = libseccomp.SCMP_ARCH_S390X
+ RISCV32 = libseccomp.SCMP_ARCH_RISCV32
RISCV64 = libseccomp.SCMP_ARCH_RISCV64
-
+
def __cinit__(self, arch=libseccomp.SCMP_ARCH_NATIVE):
diff --git a/src/syscalls.c b/src/syscalls.c
-index ddb84fa..34e08d9 100644
+index faddff0..15952ce 100644
--- a/src/syscalls.c
+++ b/src/syscalls.c
-@@ -55,3 +55,4 @@ ARCH_DEF(sh)
+@@ -59,6 +59,7 @@ ARCH_DEF(sh)
ARCH_DEF(x32)
ARCH_DEF(x86)
ARCH_DEF(riscv64)
+ARCH_DEF(riscv32)
-diff --git a/src/syscalls.csv b/src/syscalls.csv
-index fbd1058..0ee6c15 100644
---- a/src/syscalls.csv
-+++ b/src/syscalls.csv
-@@ -1,4 +1,4 @@
--#syscall (v5.12.0-rc7 2021-04-17),x86,x86_64,x32,arm,aarch64,mips,mips64,mips64n32,parisc,parisc64,ppc,ppc64,riscv64,s390,s390x,sh
-+#syscall (v5.12.0-rc7 2021-04-17),x86,x86_64,x32,arm,aarch64,mips,mips64,mips64n32,parisc,parisc64,ppc,ppc64,riscv32,riscv64,s390,s390x,sh
- accept,PNR,43,43,285,202,168,42,42,35,35,330,330,202,PNR,PNR,344
- accept4,364,288,288,366,242,334,293,297,320,320,344,344,242,364,364,358
- access,33,21,21,33,PNR,33,20,20,33,33,33,33,PNR,33,33,33
+
+ /**
+ * Resolve a syscall name to a number
diff --git a/src/syscalls.h b/src/syscalls.h
-index 4f959af..49887ba 100644
+index 58a788c..c6b5db5 100644
--- a/src/syscalls.h
+++ b/src/syscalls.h
@@ -28,6 +28,7 @@
@@ -503,7 +496,7 @@ index 4f959af..49887ba 100644
#include "arch-x86.h"
#include "arch-riscv64.h"
+#include "arch-riscv32.h"
-
+
/* NOTE: changes to the arch_syscall_table layout may require changes to the
* generate_syscalls_perf.sh and arch-syscall-validate scripts */
@@ -49,6 +50,7 @@ struct arch_syscall_table {
@@ -527,7 +520,7 @@ index ae445bf..063e6be 100644
break;
default:
diff --git a/tests/15-basic-resolver.c b/tests/15-basic-resolver.c
-index 2679270..57092f3 100644
+index c759dd1..fd94dbf 100644
--- a/tests/15-basic-resolver.c
+++ b/tests/15-basic-resolver.c
@@ -45,6 +45,7 @@ unsigned int arch_list[] = {
@@ -536,8 +529,8 @@ index 2679270..57092f3 100644
SCMP_ARCH_PARISC64,
+ SCMP_ARCH_RISCV32,
SCMP_ARCH_RISCV64,
+ SCMP_ARCH_SH,
-1
- };
diff --git a/tests/16-sim-arch_basic.c b/tests/16-sim-arch_basic.c
index 4fcbb5c..662e081 100644
--- a/tests/16-sim-arch_basic.c
@@ -587,7 +580,7 @@ index 08f030c..ec73224 100644
+ rc = seccomp_arch_add(ctx, seccomp_arch_resolve_name("riscv32"));
if (rc != 0)
goto out;
-
+
diff --git a/tests/23-sim-arch_all_le_basic.py b/tests/23-sim-arch_all_le_basic.py
index 12bb243..1eebc20 100755
--- a/tests/23-sim-arch_all_le_basic.py
@@ -622,10 +615,10 @@ index 77a5b89..2e860bf 100755
"ppc64le",
+ "riscv32",
"riscv64"]
-
+
def test_arch(arch, init):
diff --git a/tests/regression b/tests/regression
-index 53dab75..2869629 100755
+index d28b848..057ff67 100755
--- a/tests/regression
+++ b/tests/regression
@@ -26,7 +26,7 @@ GLBL_ARCH_LE_SUPPORT=" \
@@ -644,9 +637,9 @@ index 53dab75..2869629 100755
+ riscv32 \
s390 \
sheb sh"
-
-@@ -785,7 +786,7 @@ function run_test_live() {
-
+
+@@ -801,7 +802,7 @@ function run_test_live() {
+
# setup the arch specific return values
case "$arch" in
- x86|x86_64|x32|arm|aarch64|parisc|parisc64|ppc|ppc64|ppc64le|ppc|s390|s390x|riscv64|sh|sheb)
@@ -669,10 +662,10 @@ index b6bd2bb..7789970 100644
printf("unknown\n");
}
diff --git a/tools/scmp_bpf_disasm.c b/tools/scmp_bpf_disasm.c
-index b95cdeb..49a89c7 100644
+index b682de7..4f759fc 100644
--- a/tools/scmp_bpf_disasm.c
+++ b/tools/scmp_bpf_disasm.c
-@@ -510,6 +510,8 @@ int main(int argc, char *argv[])
+@@ -508,6 +508,8 @@ int main(int argc, char *argv[])
arch = AUDIT_ARCH_S390X;
else if (strcmp(optarg, "riscv64") == 0)
arch = AUDIT_ARCH_RISCV64;
@@ -719,7 +712,7 @@ index 6c2ca33..4d16e38 100644
@@ -79,6 +79,13 @@
#define AUDIT_ARCH_RISCV64 (EM_RISCV|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
#endif /* AUDIT_ARCH_RISCV64 */
-
+
+#ifndef AUDIT_ARCH_RISCV32
+#ifndef EM_RISCV
+#define EM_RISCV 243
@@ -728,7 +721,8 @@ index 6c2ca33..4d16e38 100644
+#endif /* AUDIT_ARCH_RISCV32 */
+
extern uint32_t arch;
-
+
uint16_t ttoh16(uint32_t arch, uint16_t val);
---
-2.32.0
+--
+2.33.0
+