diff options
Diffstat (limited to 'meta/classes-recipe/rust-target-config.bbclass')
| -rw-r--r-- | meta/classes-recipe/rust-target-config.bbclass | 91 |
1 files changed, 70 insertions, 21 deletions
diff --git a/meta/classes-recipe/rust-target-config.bbclass b/meta/classes-recipe/rust-target-config.bbclass index 9e1d81bf5c..330ad8a3f5 100644 --- a/meta/classes-recipe/rust-target-config.bbclass +++ b/meta/classes-recipe/rust-target-config.bbclass @@ -21,16 +21,21 @@ def llvm_features_from_tune(d): if 'vfpv4' in feat: f.append("+vfp4") - if 'vfpv3' in feat: + elif 'vfpv4d16' in feat: + f.append("+vfp4") + f.append("-d32") + elif 'vfpv3' in feat: f.append("+vfp3") - if 'vfpv3d16' in feat: - f.append("+d16") - - if 'vfpv2' in feat or 'vfp' in feat: + elif 'vfpv3d16' in feat: + f.append("+vfp3") + f.append("-d32") + elif 'vfpv2' in feat or 'vfp' in feat: f.append("+vfp2") if 'neon' in feat: f.append("+neon") + elif target_is_armv7(d): + f.append("-neon") if 'mips32' in feat: f.append("+mips32") @@ -114,7 +119,7 @@ def llvm_features_from_target_fpu(d): # TARGET_FPU can be hard or soft. +soft-float tell llvm to use soft float # ABI. There is no option for hard. - fpu = d.getVar('TARGET_FPU', True) + fpu = d.getVar('TARGET_FPU') return ["+soft-float"] if fpu == "soft" else [] def llvm_features(d): @@ -231,19 +236,27 @@ TARGET_POINTER_WIDTH[powerpc64le] = "64" TARGET_C_INT_WIDTH[powerpc64le] = "64" MAX_ATOMIC_WIDTH[powerpc64le] = "64" -## riscv32-unknown-linux-{gnu, musl} -DATA_LAYOUT[riscv32] = "e-m:e-p:32:32-i64:64-n32-S128" -TARGET_ENDIAN[riscv32] = "little" -TARGET_POINTER_WIDTH[riscv32] = "32" -TARGET_C_INT_WIDTH[riscv32] = "32" -MAX_ATOMIC_WIDTH[riscv32] = "32" - -## riscv64-unknown-linux-{gnu, musl} -DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" -TARGET_ENDIAN[riscv64] = "little" -TARGET_POINTER_WIDTH[riscv64] = "64" -TARGET_C_INT_WIDTH[riscv64] = "64" -MAX_ATOMIC_WIDTH[riscv64] = "64" +## riscv32gc-unknown-linux-{gnu, musl} +DATA_LAYOUT[riscv32gc] = "e-m:e-p:32:32-i64:64-n32-S128" +TARGET_ENDIAN[riscv32gc] = "little" +TARGET_POINTER_WIDTH[riscv32gc] = "32" +TARGET_C_INT_WIDTH[riscv32gc] = "32" +MAX_ATOMIC_WIDTH[riscv32gc] = "32" + +## riscv64gc-unknown-linux-{gnu, musl} +DATA_LAYOUT[riscv64gc] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" +TARGET_ENDIAN[riscv64gc] = "little" +TARGET_POINTER_WIDTH[riscv64gc] = "64" +TARGET_C_INT_WIDTH[riscv64gc] = "64" +MAX_ATOMIC_WIDTH[riscv64gc] = "64" + +## loongarch64-unknown-linux-{gnu, musl} +DATA_LAYOUT[loongarch64] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" +TARGET_ENDIAN[loongarch64] = "little" +TARGET_POINTER_WIDTH[loongarch64] = "64" +TARGET_C_INT_WIDTH[loongarch64] = "32" +MAX_ATOMIC_WIDTH[loongarch64] = "64" +FEATURES[loongarch64] = "+d" # Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something # rust's internals won't choke on. @@ -258,9 +271,21 @@ def arch_to_rust_target_arch(arch): return "arm" elif arch == "powerpc64le": return "powerpc64" + elif arch == "riscv32gc": + return "riscv32" + elif arch == "riscv64gc": + return "riscv64" else: return arch +# Convert a rust target string to a llvm-compatible triplet +def rust_sys_to_llvm_target(sys): + if sys.startswith('riscv32gc-'): + return sys.replace('riscv32gc-', 'riscv32-', 1) + if sys.startswith('riscv64gc-'): + return sys.replace('riscv64gc-', 'riscv64-', 1) + return sys + # generates our target CPU value def llvm_cpu(d): cpu = d.getVar('PACKAGE_ARCH') @@ -274,8 +299,11 @@ def llvm_cpu(d): trans['i586'] = "i586" trans['mips64'] = "mips64" trans['mips64el'] = "mips64" + trans['powerpc64le'] = "ppc64le" + trans['powerpc64'] = "ppc64" trans['riscv64'] = "generic-rv64" trans['riscv32'] = "generic-rv32" + trans['loongarch64'] = "la464" if target in ["mips", "mipsel", "powerpc"]: feat = frozenset(d.getVar('TUNE_FEATURES').split()) @@ -334,7 +362,7 @@ def rust_gen_target(d, thing, wd, arch): # build tspec tspec = {} - tspec['llvm-target'] = rustsys + tspec['llvm-target'] = rust_sys_to_llvm_target(rustsys) tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch_abi) if tspec['data-layout'] is None: bb.fatal("No rust target defined for %s" % arch_abi) @@ -343,7 +371,10 @@ def rust_gen_target(d, thing, wd, arch): tspec['target-c-int-width'] = d.getVarFlag('TARGET_C_INT_WIDTH', arch_abi) tspec['target-endian'] = d.getVarFlag('TARGET_ENDIAN', arch_abi) tspec['arch'] = arch_to_rust_target_arch(rust_arch) - tspec['os'] = "linux" + if "baremetal" in d.getVar('TCLIBC'): + tspec['os'] = "none" + else: + tspec['os'] = "linux" if "musl" in tspec['llvm-target']: tspec['env'] = "musl" else: @@ -352,6 +383,8 @@ def rust_gen_target(d, thing, wd, arch): tspec['llvm-abiname'] = "lp64d" if "riscv32" in tspec['llvm-target']: tspec['llvm-abiname'] = "ilp32d" + if "loongarch64" in tspec['llvm-target']: + tspec['llvm-abiname'] = "lp64d" tspec['vendor'] = "unknown" tspec['target-family'] = "unix" tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix) @@ -389,3 +422,19 @@ python do_rust_gen_targets () { addtask rust_gen_targets after do_patch before do_compile do_rust_gen_targets[dirs] += "${RUST_TARGETS_DIR}" +# For building target C dependecies use only compiler parameters defined in OE +# and ignore the CC crate defaults which conflicts with OE ones in some cases. +# https://github.com/rust-lang/cc-rs#external-configuration-via-environment-variables +# Some CC crate compiler flags are still required. +# We apply them conditionally in rust wrappers. + +CRATE_CC_FLAGS:class-native = "" +CRATE_CC_FLAGS:class-nativesdk = "" +CRATE_CC_FLAGS:class-target = " -ffunction-sections -fdata-sections -fPIC" + +do_compile:prepend:class-target() { + export CRATE_CC_NO_DEFAULTS=1 +} +do_install:prepend:class-target() { + export CRATE_CC_NO_DEFAULTS=1 +} |