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author | 2022-06-26 20:15:19 +0200 | |
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committer | 2022-06-27 23:10:52 +0100 | |
commit | 337da2a521b060c72375279dac20bc8e3878926e (patch) | |
tree | 0e4d78f9b08c141f92f7f64079bb3c0a0a75600c | |
parent | 3ad994d95815eefed2a72b675c7a323b3ed38191 (diff) | |
download | openembedded-core-contrib-337da2a521b060c72375279dac20bc8e3878926e.tar.gz |
opensbi: Update to v1.1
This release has:
* SBI PMU improvements
* RISC-V AIA v0.3.0 draft support
* Simple external interrupt handling framework
* Xilinx UART-Lite driver
* RISC-V privilege specification v1.12 support
* RISC-V Svpbmt extension support
* RISC-V Smstateen extension support
* RISC-V Sstc extension support
* RISC-V privilege specification version detection
* Platform callback to populate HART extensions
* Compile time C arrays support
* Probing FDT based drivers using compile time C arrays
* SBI HSM improvements
* Allwinner D1 platform support
* Trap redirection improvements related to [m|h]tinst CSR
* SBI v1.0 specification support
Overall, this release mainly adds support for various RISC-V ISA
extensions ratified in December 2021 along with other improvements.
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
-rw-r--r-- | meta/recipes-bsp/opensbi/opensbi_1.1.bb (renamed from meta/recipes-bsp/opensbi/opensbi_1.0.bb) | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/meta/recipes-bsp/opensbi/opensbi_1.0.bb b/meta/recipes-bsp/opensbi/opensbi_1.1.bb index 8430f62543..d3a6296533 100644 --- a/meta/recipes-bsp/opensbi/opensbi_1.0.bb +++ b/meta/recipes-bsp/opensbi/opensbi_1.1.bb @@ -8,9 +8,8 @@ require opensbi-payloads.inc inherit autotools-brokensep deploy -SRCREV = "ce4c0188d96b2c20c2e08d24646a5e517fe15a4b" -SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https \ - " +SRCREV = "4489876e933d8ba0d8bc6c64bae71e295d45faac" +SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https" S = "${WORKDIR}/git" |