From aad8fd3187b1d3549ea1cdcbcb7ddb4997da108c Mon Sep 17 00:00:00 2001 From: Sergey Lapin Date: Sat, 27 Sep 2008 01:34:12 +0400 Subject: [PATCH] AFEB9260 board support Signed-off-by: Sergey Lapin --- Makefile | 19 +++ board/afeb9260/afeb9260.c | 240 +++++++++++++++++++++++++++++++++ board/afeb9260/afeb9260.mk | 8 + board/afeb9260/dataflash/afeb9260.h | 127 +++++++++++++++++ board/afeb9260/nandflash/afeb9260ek.h | 151 +++++++++++++++++++++ board/afeb9260/pll.h | 35 +++++ include/part.h | 10 ++ 7 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 board/afeb9260/afeb9260.c create mode 100644 board/afeb9260/afeb9260.mk create mode 100644 board/afeb9260/dataflash/afeb9260.h create mode 100644 board/afeb9260/nandflash/afeb9260ek.h create mode 100644 board/afeb9260/pll.h diff --git a/Makefile b/Makefile index 475784e..805de99 100644 --- a/Makefile +++ b/Makefile @@ -142,6 +142,25 @@ at91sam9263ek_defconfig: clean echo SPI_BOOT=SPI_BOOT_CS0 >> .config echo SPI_CLK=$(CONFIG_SPI_CLK) >> .config +afeb9260_defconfig: clean + echo BOARDNAME=afeb9260 > .config + echo BOARD=afeb9260 >> .config + echo PROJECT=$(MEMORY) >> .config + echo CONFIG_$(CFG_MEMORY)=y >> .config + echo SPI_MODE=$(CONFIG_SPI_MODE) >> .config + echo SPI_BOOT=SPI_BOOT_CS1 >> .config + echo SPI_CLK=$(CONFIG_SPI_CLK) >> .config + +afeb9260-133_defconfig: clean + echo BOARDNAME=afeb9260-133 > .config + echo BOARD=afeb9260-133 >> .config + echo PROJECT=$(MEMORY) >> .config + echo CONFIG_$(CFG_MEMORY)=y >> .config + echo SPI_MODE=$(CONFIG_SPI_MODE) >> .config + echo SPI_BOOT=SPI_BOOT_CS1 >> .config + echo SPI_CLK=$(CONFIG_SPI_CLK) >> .config + + ../buildroot: (cd .. ; svn co svn://uclibc.org/trunk/buildroot) diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c new file mode 100644 index 0000000..81c0919 --- /dev/null +++ b/board/afeb9260/afeb9260.c @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + * File Name : at91sam9260ek.c + * Object : + * Creation : NLe Jul 13th 2006 + * ODi Nov 9th : dstp #3507 "Bad PIO descriptors in at91samxxxek.c" + *----------------------------------------------------------------------------- + */ +#include "../../include/part.h" +#include "../../include/gpio.h" +#include "../../include/pmc.h" +#include "../../include/debug.h" +#include "../../include/sdramc.h" +#include "../../include/main.h" +#ifdef CFG_NANDFLASH +#include "../../include/nandflash.h" +#endif +#ifdef CFG_DATAFLASH +#include "../../include/dataflash.h" +#endif +#ifdef CFG_FLASH +#include "../../include/flash.h" +#endif + +/* We init NAND regardless of whatever */ +/*------------------------------------------------------------------------------*/ +/* \fn nandflash_hw_init */ +/* \brief NandFlash HW init */ +/*------------------------------------------------------------------------------*/ +void nandflash_hw_init(void) +{ + /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */ + writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA); + + /* Configure SMC CS3 */ + writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3); + writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3); + writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE) , AT91C_BASE_SMC + SMC_CYCLE3); + writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF) , AT91C_BASE_SMC + SMC_CTRL3); + + /* Configure the PIO controller */ + writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC); + + writel(1 << 13, AT91C_BASE_PIOC + PIO_IFDR(0)); + writel(1 << 13, AT91C_BASE_PIOC + PIO_PPUER(0)); + writel(1 << 13, AT91C_BASE_PIOC + PIO_ODR(0)); + writel(1 << 14, AT91C_BASE_PIOC + PIO_CODR(0)); + writel(1 << 14, AT91C_BASE_PIOC + PIO_MDDR(0)); + writel(1 << 14, AT91C_BASE_PIOC + PIO_PPUDR(0)); + writel(1 << 14, AT91C_BASE_PIOC + PIO_OER(0)); + writel(3 << 13, AT91C_BASE_PIOC + PIO_IDR(0)); + writel(3 << 13, AT91C_BASE_PIOC + PIO_PER(0)); +} + + +#ifdef CFG_HW_INIT +/*----------------------------------------------------------------------------*/ +/* \fn hw_init */ +/* \brief This function performs very low level HW initialization */ +/* This function is invoked as soon as possible during the c_startup */ +/* The bss segment must be initialized */ +/*----------------------------------------------------------------------------*/ +void hw_init(void) +{ + /* Disable watchdog */ + writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); + + /* At this stage the main oscillator is supposed to be enabled + * PCK = MCK = MOSC */ + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); + + /* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */ + pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); + + /* Configure PLLB */ + pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); + + /* Configure the PIO controller */ + writel(3 << 14, AT91C_BASE_PIOB + PIO_ASR(0)); + writel(3 << 14, AT91C_BASE_PIOB + PIO_PDR(0)); + +#ifdef CFG_DEBUG + /* Enable Debug messages on the DBGU */ + dbg_init(BAUDRATE(MASTER_CLOCK, 115200)); + + dbg_print("AT91 bootstrap loading from 0x8400\n\r"); +#endif /* CFG_DEBUG */ + +#ifdef CFG_SDRAM + /* Initialize the matrix */ + writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA); + + /* Configure SDRAM Controller */ + +#define HYNIX + +//#define MICRON +#ifdef MICRON +#define MICRON_REFRESH 1420 /* 15.625 us / 11 ns @ 180 Mhz*/ + sdram_init( AT91C_SDRAMC_NC_9 | + AT91C_SDRAMC_NR_12 | + AT91C_SDRAMC_CAS_2 | + AT91C_SDRAMC_NB_4_BANKS | + AT91C_SDRAMC_DBW_32_BITS | + AT91C_SDRAMC_TWR_2 | // 1 CLK+7ns + AT91C_SDRAMC_TRC_7 | // 60 ns + AT91C_SDRAMC_TRP_3 | // 15 ns + AT91C_SDRAMC_TRCD_3 | // 15 ns + AT91C_SDRAMC_TRAS_7 | // 37-120 ns + AT91C_SDRAMC_TXSR_7, /* 67ns */ /* Control Register */ + /* 600 700 735 */ MICRON_REFRESH /* 740 1536*/ ); /* Refresh Timer Register */ + +#endif +/* +HY57V561620BT-H + *CAS lat *tRCD *tRAS *tRC *tRP tAC tOH +133 2 2 6 8 2 5.4ns 2.7ns +125 3 3 6 9 3 6ns 3ns +100 2 2 5 7 2 6ns 3ns + +*/ +#ifdef HYNIX +#if defined(PLLA_180MHz) +/* CLK= 11ns */ +/* TWR = tDPL = 2 2CLK always */ +/* TRC = tRC = 65ns = 6 clk */ +/* TRP = tRP = 20ns = 2 clk */ +/* TRCD = tRCD = 20ns = 2 clk */ +/* TRAS = tRAS = 45ns = 5 clk */ +/* TXSR = tRRC = 65ns = 6 clk */ + + sdram_init( AT91C_SDRAMC_NC_9 | + AT91C_SDRAMC_NR_13 | + AT91C_SDRAMC_CAS_2 | + AT91C_SDRAMC_NB_4_BANKS | + AT91C_SDRAMC_DBW_32_BITS | + AT91C_SDRAMC_TWR_2 | + AT91C_SDRAMC_TRC_6 | /* *7 */ + AT91C_SDRAMC_TRP_2 | + AT91C_SDRAMC_TRCD_2 | + AT91C_SDRAMC_TRAS_5 | /* *5 */ + AT91C_SDRAMC_TXSR_6, /* *8 */ /* Control Register */ + 710); /* Refresh Timer Register */ + +#elif defined(PLLA_120MHz) +/* CLK= 16ns, MCLK=60MHz */ +/* TWR = tDPL = 2 2CLK always */ +/* TRC = tRC = 65ns = 4 clk */ +/* TRP = tRP = 20ns = 2 clk */ +/* TRCD = tRCD = 20ns = 2 clk */ +/* TRAS = tRAS = 45ns = 3 clk */ +/* TXSR = tRRC = 65ns = 4 clk */ + + sdram_init( AT91C_SDRAMC_NC_9 | + AT91C_SDRAMC_NR_13 | + AT91C_SDRAMC_CAS_2 | + AT91C_SDRAMC_NB_4_BANKS | + AT91C_SDRAMC_DBW_32_BITS | + AT91C_SDRAMC_TWR_2 | + AT91C_SDRAMC_TRC_4 | + AT91C_SDRAMC_TRP_2 | + AT91C_SDRAMC_TRCD_2 | + AT91C_SDRAMC_TRAS_3 | /* *5 */ + AT91C_SDRAMC_TXSR_4, /* *8 */ /* Control Register */ + 1032); /* Refresh Timer Register */ +#else +#error define PLLA180MHz +#endif +#endif /* HYNIX */ +#endif /* CFG_SDRAM */ + +#ifdef CFG_FLASH + flash_hw_init(); +#endif + nandflash_hw_init(); +} +#endif /* CFG_HW_INIT */ + +#ifdef CFG_SDRAM +/*------------------------------------------------------------------------------*/ +/* \fn sdramc_hw_init */ +/* \brief This function performs SDRAMC HW initialization */ +/*------------------------------------------------------------------------------*/ +void sdramc_hw_init(void) +{ + writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0)); + writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0)); + +} +#endif /* CFG_SDRAM */ + +#ifdef CFG_DATAFLASH + +/*------------------------------------------------------------------------------*/ +/* \fn df_hw_init */ +/* \brief This function performs DataFlash HW initialization */ +/*------------------------------------------------------------------------------*/ +void df_hw_init(void) +{ + writel(0xf, 0xfffff444); + writel(0xf, 0xfffff460); + writel(0xf, 0xfffff470); + writel(0xf, 0xfffff404); + writel(1 << 11, AT91C_BASE_PIOC + PIO_BSR(0)); + writel(1 << 11, AT91C_BASE_PIOC + PIO_PDR(0)); +} +#endif /* CFG_DATAFLASH */ + diff --git a/board/afeb9260/afeb9260.mk b/board/afeb9260/afeb9260.mk new file mode 100644 index 0000000..88c2f64 --- /dev/null +++ b/board/afeb9260/afeb9260.mk @@ -0,0 +1,8 @@ +# Target name (case sensitive!!!) +TARGET=AFEB9260 +# Board name (case sensitive!!!) +BOARD=afeb9260 +# Link Address and Top_of_Memory +LINK_ADDR=0x200000 +TOP_OF_MEMORY=0x301000 + diff --git a/board/afeb9260/dataflash/afeb9260.h b/board/afeb9260/dataflash/afeb9260.h new file mode 100644 index 0000000..8e60faa --- /dev/null +++ b/board/afeb9260/dataflash/afeb9260.h @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + * File Name : at91sam9260ek.h + * Object : + * Creation : NLe Jul 13th 2006 + *----------------------------------------------------------------------------- + */ +#ifndef _AFEB9260_H +#define _AFEB9260_H +#include "spi.h" +#include "pll.h" + +/* ******************************************************************* */ +/* DataFlash Settings */ +/* */ +/* ******************************************************************* */ +#define AT91C_BASE_SPI AT91C_BASE_SPI0 +#define AT91C_ID_SPI AT91C_ID_SPI0 + +/* SPI CLOCK */ +#define AT91C_SPI_CLK 5000000 +/* AC characteristics */ +/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0x1a << 16) /* 250ns min (tCSS) <=> 12/48000000 = 250ns */ +#define DATAFLASH_TCHS (0x1 << 24) /* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */ + +#define DF_CS_SETTINGS ((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8)) + + +/* ******************************************************************* */ +/* BootStrap Settings */ +/* */ +/* ******************************************************************* */ +#define MACH_TYPE 0x44B /* AT91SAM9260-EK */ + +#define IMG_ADDRESS 0x8400 /* Image Address in DataFlash */ + +#if defined(IMG_SIZE) +#warning "IMG_SIZE redefined" +#else +#define IMG_SIZE 0x39000 /* Image Size in DataFlash */ +#endif + +#if defined(JUMP_ADDR) +#warning "JUMP_ADDR redefined" +#else +#define JUMP_ADDR 0x21F00000 /* Final Jump Address */ +#endif + +/* ******************************************************************* */ +/* NandFlash Settings */ +/* */ +/* ******************************************************************* */ +#define AT91C_SMARTMEDIA_BASE 0x40000000 + +#define AT91_SMART_MEDIA_ALE (1 << 21) /* our ALE is AD21 */ +#define AT91_SMART_MEDIA_CLE (1 << 22) /* our CLE is AD22 */ + +#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0) +#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0) + +#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13)) + + +/* ******************************************************************** */ +/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/ +/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000. */ +/* Please refer to SMC section in AT91SAM9261 datasheet to learn how */ +/* to generate these values. */ +/* ******************************************************************** */ + +#define AT91C_SM_NWE_SETUP (2 << 0) +#define AT91C_SM_NCS_WR_SETUP (2 << 8) +#define AT91C_SM_NRD_SETUP (2 << 16) +#define AT91C_SM_NCS_RD_SETUP (2 << 24) + +#define AT91C_SM_NWE_PULSE (4 << 0) +#define AT91C_SM_NCS_WR_PULSE (4 << 8) +#define AT91C_SM_NRD_PULSE (4 << 16) +#define AT91C_SM_NCS_RD_PULSE (4 << 24) + +#define AT91C_SM_NWE_CYCLE (8 << 0) +#define AT91C_SM_NRD_CYCLE (8 << 16) + +#define AT91C_SM_TDF (2 << 16) + + + +/* ******************************************************************* */ +/* Application Settings */ +/* ******************************************************************* */ +#define CFG_DEBUG +#define CFG_DATAFLASH +#define CFG_SDRAM +#define CFG_HW_INIT + + +#endif /* _AT91SAM9260EK_H */ diff --git a/board/afeb9260/nandflash/afeb9260ek.h b/board/afeb9260/nandflash/afeb9260ek.h new file mode 100644 index 0000000..752ae0a --- /dev/null +++ b/board/afeb9260/nandflash/afeb9260ek.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + * File Name : at91sam9260ek.h + * Object : + * Creation : NLe Sep 28th 2006 + *----------------------------------------------------------------------------- + */ +#ifndef _AFEB9260_H +#define _AFEB9260_H +#include "spi.h" +#include "pll.h" + +/* ******************************************************************* */ +/* DataFlash Settings */ +/* */ +/* ******************************************************************* */ +#define AT91C_BASE_SPI AT91C_BASE_SPI0 +#define AT91C_ID_SPI AT91C_ID_SPI0 + +/* SPI CLOCK */ +#define AT91C_SPI_CLK 5000000 +/* AC characteristics */ +/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0x1a << 16) /* 250ns min (tCSS) <=> 12/48000000 = 250ns */ +#define DATAFLASH_TCHS (0x1 << 24) /* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */ + +#define DF_CS_SETTINGS ((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8)) + + +/* ******************************************************************* */ +/* NandFlash Settings */ +/* */ +/* ******************************************************************* */ +#define AT91C_SMARTMEDIA_BASE 0x40000000 + +#define AT91_SMART_MEDIA_ALE (1 << 21) /* our ALE is AD21 */ +#define AT91_SMART_MEDIA_CLE (1 << 22) /* our CLE is AD22 */ + +#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0) +#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0) + +#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13)) + + +/* ******************************************************************** */ +/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/ +/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000. */ +/* Please refer to SMC section in AT91SAM9261 datasheet to learn how */ +/* to generate these values. */ +/* ******************************************************************** */ + +#define AT91C_SM_NWE_SETUP (2 << 0) +#define AT91C_SM_NCS_WR_SETUP (2 << 8) +#define AT91C_SM_NRD_SETUP (2 << 16) +#define AT91C_SM_NCS_RD_SETUP (2 << 24) + +#define AT91C_SM_NWE_PULSE (4 << 0) +#define AT91C_SM_NCS_WR_PULSE (4 << 8) +#define AT91C_SM_NRD_PULSE (4 << 16) +#define AT91C_SM_NCS_RD_PULSE (4 << 24) + +#define AT91C_SM_NWE_CYCLE (8 << 0) +#define AT91C_SM_NRD_CYCLE (8 << 16) + +#define AT91C_SM_TDF (2 << 16) + + +/* ******************************************************************** */ +/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/ +/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000. */ +/* Please refer to SMC section in AT91SAM9261 datasheet to learn how */ +/* to generate these values. */ +/* ******************************************************************** */ +/*#define AT91C_SM_NWE_SETUP (0 << 0) +#define AT91C_SM_NCS_WR_SETUP (0 << 8) +#define AT91C_SM_NRD_SETUP (0 << 16) +#define AT91C_SM_NCS_RD_SETUP (0 << 24) + +#define AT91C_SM_NWE_PULSE (2 << 0) +#define AT91C_SM_NCS_WR_PULSE (3 << 8) +#define AT91C_SM_NRD_PULSE (2 << 16) +#define AT91C_SM_NCS_RD_PULSE (3 << 24) + +#define AT91C_SM_NWE_CYCLE (3 << 0) +#define AT91C_SM_NRD_CYCLE (3 << 16) + +#define AT91C_SM_TDF (1 << 16) +*/ + +/* ******************************************************************* */ +/* BootStrap Settings */ +/* */ +/* ******************************************************************* */ +#define MACH_TYPE 0x44B /* AT91SAM9260-EK */ + +#define IMG_ADDRESS 0x20000 /* Image Address in NandFlash */ + +#if defined(IMG_SIZE) +#warning "IMG_SIZE redefined" +#else +#define IMG_SIZE 0x30000 /* Image Size in NandFlash */ +#endif + +#if defined(JUMP_ADDR) +#warning "JUMP_ADDR redefined" +#else +#define JUMP_ADDR 0x23F00000 /* Final Jump Address */ +#endif + +/* ******************************************************************* */ +/* Application Settings */ +/* ******************************************************************* */ +#define CFG_DEBUG +#undef CFG_DATAFLASH + +#define CFG_NANDFLASH +#undef NANDFLASH_SMALL_BLOCKS /* NANDFLASH_LARGE_BLOCKS used instead */ + +#define CFG_HW_INIT +#define CFG_SDRAM + +#endif /* _AT91SAM9260EK_H */ diff --git a/board/afeb9260/pll.h b/board/afeb9260/pll.h new file mode 100644 index 0000000..6d20299 --- /dev/null +++ b/board/afeb9260/pll.h @@ -0,0 +1,35 @@ +/* ******************************************************************* */ +/* PMC Settings */ +/* */ +/* The main oscillator is enabled as soon as possible in the c_startup */ +/* and MCK is switched on the main oscillator. */ +/* PLL initialization is done later in the hw_init() function */ +/* ******************************************************************* */ +#define PLL_LOCK_TIMEOUT 1000000 + +#define PLLA_180MHz + +#ifdef PLLA_200MHz +#define PLLA_SETTINGS 0x2060BF09 +#define MASTER_CLOCK (198656000/2) +#endif + +#ifdef PLLA_180MHz +#define PLLA_SETTINGS 0x2125BF1E /* 180MHz */ +#define MASTER_CLOCK (179999198/2) /* 180MHz MCK=90MHz */ +#endif + +#ifdef PLLA_120MHz +//#define PLLA_SETTINGS 0x2125BF2d /* 120MHz */ +//#define MASTER_CLOCK (119999322) /* 120MHz MCK=60MHz*/ +#define PLLA_SETTINGS 0x2125BF2d /* 120MHz */ +#define MASTER_CLOCK (119999465/2) /* 120MHz MCK=60MHz*/ +#endif + +#if !defined(PLLA_180MHz) && !defined(PLLA_120MHz) +#error Define PLLA frequency +#endif +#define PLLB_SETTINGS 0x10483F0E + +/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */ +#define MCKR_SETTINGS (AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2) diff --git a/include/part.h b/include/part.h index ec717d6..48e41e1 100644 --- a/include/part.h +++ b/include/part.h @@ -52,4 +52,14 @@ #include "at91sam9263ek.h" #endif +#ifdef AFEB9260 +#include "AT91SAM9260_inc.h" +#include "afeb9260.h" +#endif + +#ifdef AFEB9260_133 +#include "AT91SAM9260_inc.h" +#include "afeb9260-133.h" +#endif + #endif /* _PART_H */ -- 1.5.6.5