diff options
Diffstat (limited to 'recipes/u-boot/u-boot-2009.11/at91/0004-Support-selecting-SPI-mode-in-dataflash-driver.patch')
| -rw-r--r-- | recipes/u-boot/u-boot-2009.11/at91/0004-Support-selecting-SPI-mode-in-dataflash-driver.patch | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/recipes/u-boot/u-boot-2009.11/at91/0004-Support-selecting-SPI-mode-in-dataflash-driver.patch b/recipes/u-boot/u-boot-2009.11/at91/0004-Support-selecting-SPI-mode-in-dataflash-driver.patch new file mode 100644 index 0000000000..ec075d8ffb --- /dev/null +++ b/recipes/u-boot/u-boot-2009.11/at91/0004-Support-selecting-SPI-mode-in-dataflash-driver.patch @@ -0,0 +1,116 @@ +From 33f977f42bfb2f62dff2b2441c06eb5265c61293 Mon Sep 17 00:00:00 2001 +From: Ulf Samuelsson <ulf.samuelsson@atmel.com> +Date: Sat, 27 Feb 2010 09:49:43 +0100 +Subject: [PATCH] Support selecting SPI mode in dataflash driver + +By setting AT91_SPI_MODE in the config to +AT91_SPI_MODE[3..0] you can select the SPI mode. +when the dataflash driver is used. + +I.E +.#define AT91_SPI_MODE AT91_SPI_MODE0 + +Signed-off-by: Ulf Samuelsson <ulf.samuelsson@atmel.com> +--- + drivers/spi/atmel_dataflash_spi.c | 26 ++++++++++++++++++++++---- + include/asm-arm/arch-at91/at91_spi.h | 8 ++++++++ + 2 files changed, 30 insertions(+), 4 deletions(-) + +diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c +index 3a648e6..5307e34 100644 +--- a/drivers/spi/atmel_dataflash_spi.c ++++ b/drivers/spi/atmel_dataflash_spi.c +@@ -34,8 +34,15 @@ + #define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */ + #define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ + ++#ifndef AT91_SPI_MODE ++#define AT91_SPI_MODE AT91_SPI_MODE0 ++#endif ++ + void AT91F_SpiInit(void) + { ++ unsigned int mr,sr,imr; ++ unsigned int csr0, csr1, csr2, csr3; ++ + /* Reset the SPI */ + writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR); + +@@ -44,7 +51,7 @@ void AT91F_SpiInit(void) + AT91_BASE_SPI + AT91_SPI_MR); + + /* Configure CS0 */ +- writel(AT91_SPI_NCPHA | ++ writel(AT91_SPI_MODE | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), +@@ -52,7 +59,7 @@ void AT91F_SpiInit(void) + + #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + /* Configure CS1 */ +- writel(AT91_SPI_NCPHA | ++ writel(AT91_SPI_MODE | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), +@@ -60,7 +67,7 @@ void AT91F_SpiInit(void) + #endif + #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 + /* Configure CS2 */ +- writel(AT91_SPI_NCPHA | ++ writel(AT91_SPI_MODE | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), +@@ -68,7 +75,7 @@ void AT91F_SpiInit(void) + #endif + #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + /* Configure CS3 */ +- writel(AT91_SPI_NCPHA | ++ writel(AT91_SPI_MODE | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), +@@ -84,7 +91,18 @@ void AT91F_SpiInit(void) + * Add tempo to get SPI in a safe state. + * Should not be needed for new silicon (Rev B) + */ ++ printf("CPU running at %d Hz\n",get_cpu_clk_rate()); ++ printf("MCK running at %d Hz\n",get_mck_clk_rate()); ++ printf("SPI_MR 0x%08x\n",mr=readl(AT91_BASE_SPI + AT91_SPI_MR)); ++ printf("SPI_SR 0x%08x\n",sr=readl(AT91_BASE_SPI + AT91_SPI_SR)); ++ printf("SPI_IMR 0x%08x\n",imr=readl(AT91_BASE_SPI + AT91_SPI_IMR)); ++ printf("SPI_CSR0 0x%08x\n",csr0=readl(AT91_BASE_SPI + AT91_SPI_CSR(0))); ++ printf("SPI_CSR1 0x%08x\n",csr1=readl(AT91_BASE_SPI + AT91_SPI_CSR(1))); ++ printf("SPI_CSR2 0x%08x\n",csr2=readl(AT91_BASE_SPI + AT91_SPI_CSR(2))); ++ printf("SPI_CSR3 0x%08x\n",csr3=readl(AT91_BASE_SPI + AT91_SPI_CSR(3))); ++ printf("SPI SPEED = %d Hz\n", get_mck_clk_rate()/ ((csr0 >> 8) & 0xff)); + udelay(500000); ++ + readl(AT91_BASE_SPI + AT91_SPI_SR); + readl(AT91_BASE_SPI + AT91_SPI_RDR); + +diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h +index 30643c6..8924996 100644 +--- a/include/asm-arm/arch-at91/at91_spi.h ++++ b/include/asm-arm/arch-at91/at91_spi.h +@@ -62,7 +62,15 @@ + + #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ + #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ ++#define AT91_SPI_NCPOL (0 << 0) /* Clock Polarity */ + #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ ++#define AT91_SPI_CPHA (0 << 1) /* Clock Phase */ ++ ++#define AT91_SPI_MODE0 (AT91_SPI_NCPOL | AT91_SPI_NCPHA) ++#define AT91_SPI_MODE1 (AT91_SPI_NCPOL | AT91_SPI_CPHA) ++#define AT91_SPI_MODE2 (AT91_SPI_CPOL | AT91_SPI_NCPHA) ++#define AT91_SPI_MODE3 (AT91_SPI_CPOL | AT91_SPI_CPHA) ++ + #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ + #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ + #define AT91_SPI_BITS_8 (0 << 4) +-- +1.6.0.2 + |