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authorKoen Kooi <koen@openembedded.org>2009-11-26 13:45:32 +0100
committerKoen Kooi <koen@openembedded.org>2009-11-26 13:45:32 +0100
commit8af5e0ed1a7c79cd97ac5c58a7663c56b7f11621 (patch)
tree39c6c19e441e1dc48a671a96e81d6c9aa3ebad63 /recipes/linux/linux-2.6.24
parent39e66d2f9b322ea7f8711bdcfa9b251b614e60fa (diff)
downloadopenembedded-8af5e0ed1a7c79cd97ac5c58a7663c56b7f11621.tar.gz
linux 2.6.24: add support for smartq5 device (machine.conf will follow later)
* also fix task ordering due to kernel.bbclass changes
Diffstat (limited to 'recipes/linux/linux-2.6.24')
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/base/0001-Apply-samsung-kernel-patch.patch336089
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/base/0002-Apply-smartq-patch.patch94756
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/defconfig1624
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0001-Mer-keymappings-change.patch66
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0002-no-DM9000.patch25
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0003-Mer-WPA-fix.patch27
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0004-Mer-hardwire-USB-OTG-gadget-type.patch25
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0005-backlight-parameter-and-fixes.patch67
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0006-tv-encoder.patch2624
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0007-make-tv-encoder-scaler-compile.patch5208
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0008-build-TV-by-default.patch136
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0009-Apply-cpufreq-patch-from-gqwang.patch113
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0010-Better-compatibility-with-some-memory-chips.patch77
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0011-Only-reserve-memory-for-TV-if-CONFIG_VIDEO_SAMSUNG_T.patch32
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/mer/0012-Disable-TV-out-to-save-RAM.patch100
-rw-r--r--recipes/linux/linux-2.6.24/smartq5/smartq-gitupdate.diff8974
16 files changed, 449943 insertions, 0 deletions
diff --git a/recipes/linux/linux-2.6.24/smartq5/base/0001-Apply-samsung-kernel-patch.patch b/recipes/linux/linux-2.6.24/smartq5/base/0001-Apply-samsung-kernel-patch.patch
new file mode 100644
index 0000000000..2274bd0024
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/base/0001-Apply-samsung-kernel-patch.patch
@@ -0,0 +1,336089 @@
+From 9b253055c73de146ed220dc94700f89a1e93c1b0 Mon Sep 17 00:00:00 2001
+From: YouSheng <david.ysh@gmail.com>
+Date: Tue, 21 Jul 2009 14:54:59 +0800
+Subject: [PATCH 1/4] Apply samsung kernel patch
+
+---
+ Changelog | 1383 +
+ Makefile | 19 +-
+ RELEASENOTE | 130 +
+ arch/arm/Kconfig | 21 +-
+ arch/arm/Makefile | 9 +-
+ arch/arm/boot/rootfs.cpio.gz | Bin 0 -> 3753247 bytes
+ arch/arm/boot/rootfs.uboot | Bin 0 -> 3753311 bytes
+ arch/arm/configs/fpgac100_defconfig | 936 +
+ arch/arm/configs/smdk2416mtd_defconfig | 1447 +
+ arch/arm/configs/smdk2416nfs_defconfig | 1397 +
+ arch/arm/configs/smdk2416ramdisk_defconfig | 1447 +
+ arch/arm/configs/smdk2443mtd_defconfig | 1439 +
+ arch/arm/configs/smdk2443nfs_defconfig | 1400 +
+ arch/arm/configs/smdk2450mtd_defconfig | 1495 +
+ arch/arm/configs/smdk2450nfs_defconfig | 1461 +
+ arch/arm/configs/smdk2450ramdisk_defconfig | 1495 +
+ arch/arm/configs/smdk6400mtd_defconfig | 1423 +
+ arch/arm/configs/smdk6400nfs_defconfig | 1384 +
+ arch/arm/configs/smdk6410mtd_defconfig | 1513 +
+ arch/arm/configs/smdk6410nfs_defconfig | 1349 +
+ arch/arm/configs/smdk6410onenand_defconfig | 1354 +
+ arch/arm/configs/smdk6410ramdisk_defconfig | 1513 +
+ arch/arm/configs/smdk6430mtd_defconfig | 1521 +
+ arch/arm/configs/smdk6430nfs_defconfig | 1332 +
+ arch/arm/configs/smdk6430ramdisk_defconfig | 1521 +
+ arch/arm/kernel/entry-common.S | 5 +
+ arch/arm/mach-s3c2410/Makefile.boot | 9 +-
+ arch/arm/mach-s3c2416/Kconfig | 28 +
+ arch/arm/mach-s3c2416/Makefile | 20 +
+ arch/arm/mach-s3c2416/clock.c | 1006 +
+ arch/arm/mach-s3c2416/mach-smdk2416.c | 544 +
+ arch/arm/mach-s3c2416/s3c2416.c | 113 +
+ arch/arm/mach-s3c2443/clock.c | 68 +-
+ arch/arm/mach-s3c2443/dma.c | 10 +
+ arch/arm/mach-s3c2443/irq.c | 6 +
+ arch/arm/mach-s3c2443/mach-smdk2443.c | 183 +-
+ arch/arm/mach-s3c2443/s3c2443.c | 11 +
+ arch/arm/mach-s3c2450/Kconfig | 28 +
+ arch/arm/mach-s3c2450/Makefile | 20 +
+ arch/arm/mach-s3c2450/clock.c | 1095 +
+ arch/arm/mach-s3c2450/mach-smdk2450.c | 565 +
+ arch/arm/mach-s3c2450/s3c2450.c | 113 +
+ arch/arm/mach-s3c6400/Kconfig | 44 +
+ arch/arm/mach-s3c6400/Makefile | 25 +
+ arch/arm/mach-s3c6400/clock.c | 698 +
+ arch/arm/mach-s3c6400/dma-sysfs.c | 276 +
+ arch/arm/mach-s3c6400/dma.c | 312 +
+ arch/arm/mach-s3c6400/irq.c | 48 +
+ arch/arm/mach-s3c6400/kdpmd.c | 208 +
+ arch/arm/mach-s3c6400/leds-s3c6400.c | 117 +
+ arch/arm/mach-s3c6400/leds.c | 89 +
+ arch/arm/mach-s3c6400/leds.h | 1 +
+ arch/arm/mach-s3c6400/mach-smdk6400.c | 637 +
+ arch/arm/mach-s3c6400/pm-s3c6400.c | 794 +
+ arch/arm/mach-s3c6400/pm-s3c6400.h | 67 +
+ arch/arm/mach-s3c6400/pm.c | 116 +
+ arch/arm/mach-s3c6400/s3c6400.c | 139 +
+ arch/arm/mach-s3c6410/Kconfig | 52 +
+ arch/arm/mach-s3c6410/Makefile | 29 +
+ arch/arm/mach-s3c6410/clock.c | 825 +
+ arch/arm/mach-s3c6410/dma-sysfs.c | 276 +
+ arch/arm/mach-s3c6410/dma.c | 329 +
+ arch/arm/mach-s3c6410/irq.c | 48 +
+ arch/arm/mach-s3c6410/leds-s3c6410.c | 117 +
+ arch/arm/mach-s3c6410/leds.c | 89 +
+ arch/arm/mach-s3c6410/leds.h | 1 +
+ arch/arm/mach-s3c6410/mach-smdk6410.c | 868 +
+ arch/arm/mach-s3c6410/pm.c | 116 +
+ arch/arm/mach-s3c6410/pwm/Kconfig | 27 +
+ arch/arm/mach-s3c6410/pwm/Makefile | 8 +
+ arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c | 379 +
+ arch/arm/mach-s3c6410/pwm/pwm-s3c6410.h | 125 +
+ arch/arm/mach-s3c6410/s3c6410.c | 148 +
+ arch/arm/mach-s5pc100/Kconfig | 25 +
+ arch/arm/mach-s5pc100/Makefile | 26 +
+ arch/arm/mach-s5pc100/clock.c | 841 +
+ arch/arm/mach-s5pc100/irq.c | 48 +
+ arch/arm/mach-s5pc100/mach-smdkc100.c | 205 +
+ arch/arm/mach-s5pc100/s5pc100.c | 141 +
+ arch/arm/mm/Kconfig | 13 +-
+ arch/arm/mm/fault.c | 9 +-
+ arch/arm/plat-s3c/Kconfig | 12 +
+ arch/arm/plat-s3c24xx/Kconfig | 15 +-
+ arch/arm/plat-s3c24xx/Makefile | 6 +-
+ arch/arm/plat-s3c24xx/adc-s3c24xx.c | 314 +
+ arch/arm/plat-s3c24xx/clock.c | 3 +
+ arch/arm/plat-s3c24xx/common-smdk.c | 69 +-
+ arch/arm/plat-s3c24xx/cpu.c | 111 +-
+ arch/arm/plat-s3c24xx/devs.c | 890 +-
+ arch/arm/plat-s3c24xx/dma.c | 15 +
+ arch/arm/plat-s3c24xx/gpio.c | 222 +
+ arch/arm/plat-s3c24xx/irq.c | 79 +
+ arch/arm/plat-s3c24xx/s3c244x.c | 1 +
+ arch/arm/plat-s3c24xx/s3c24xx-dvfs.c | 585 +
+ arch/arm/plat-s3c24xx/s3c24xx-dvfs.h | 70 +
+ arch/arm/plat-s3c64xx/Kconfig | 32 +
+ arch/arm/plat-s3c64xx/Makefile | 31 +
+ arch/arm/plat-s3c64xx/adc-s3c64xx.c | 336 +
+ arch/arm/plat-s3c64xx/clock.c | 501 +
+ arch/arm/plat-s3c64xx/dma-pl080.c | 1672 +
+ arch/arm/plat-s3c64xx/irq-pl192.c | 619 +
+ arch/arm/plat-s3c64xx/ltc3714.c | 153 +
+ arch/arm/plat-s3c64xx/pm.c | 787 +
+ arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c | 202 +
+ arch/arm/plat-s3c64xx/s3c64xx-dvfs.c | 547 +
+ arch/arm/plat-s3c64xx/s3c64xx-dvfs.h | 66 +
+ arch/arm/plat-s3c64xx/sleep.S | 165 +
+ arch/arm/plat-s3c64xx/time-s3c64xx.c | 259 +
+ arch/arm/plat-s5pc1xx/Kconfig | 24 +
+ arch/arm/plat-s5pc1xx/Makefile | 26 +
+ arch/arm/plat-s5pc1xx/clock.c | 467 +
+ arch/arm/plat-s5pc1xx/dma-pl330-microcode.c | 278 +
+ arch/arm/plat-s5pc1xx/dma-pl330.c | 1601 +
+ arch/arm/plat-s5pc1xx/gpio.c | 241 +
+ arch/arm/plat-s5pc1xx/irq-pl192.c | 642 +
+ arch/arm/plat-s5pc1xx/time-s5pc1xx.c | 392 +
+ arch/arm/tools/mach-types | 481 +-
+ drivers/Kconfig | 3 +-
+ drivers/char/Kconfig | 15 +
+ drivers/char/Makefile | 2 +
+ drivers/char/mem.c | 18 +
+ drivers/char/s3c_mem.c | 287 +
+ drivers/char/s3c_mem.h | 42 +
+ drivers/i2c/busses/Kconfig | 9 +-
+ drivers/i2c/busses/Makefile | 1 +
+ drivers/i2c/busses/i2c-s3c2410.c | 9 +
+ drivers/i2c/busses/i2c-s3c64xx.c | 908 +
+ drivers/ide/Kconfig | 35 +-
+ drivers/ide/arm/Makefile | 1 +
+ drivers/ide/arm/s3c-ide.c | 1223 +
+ drivers/ide/arm/s3c-ide.h | 113 +
+ drivers/ide/ide-dma.c | 5 +
+ drivers/ide/ide-io.c | 7 +
+ drivers/input/Kconfig | 22 +
+ drivers/input/Makefile | 1 +
+ drivers/input/keyboard/Kconfig | 10 +
+ drivers/input/keyboard/Makefile | 1 +
+ drivers/input/keyboard/s3c-keypad.c | 337 +
+ drivers/input/keyboard/s3c-keypad.h | 61 +
+ drivers/input/touchscreen/Kconfig | 24 +
+ drivers/input/touchscreen/Makefile | 1 +
+ drivers/input/touchscreen/s3c-ts.c | 468 +
+ drivers/input/tsdev.c | 533 +
+ drivers/media/video/Kconfig | 41 +
+ drivers/media/video/Makefile | 1 +
+ drivers/media/video/s3c_camera_driver.c | 2041 +
+ drivers/media/video/s3c_camif.c | 1871 +
+ drivers/media/video/s3c_camif.h | 404 +
+ drivers/media/video/samsung/3xa_sensor.c | 442 +
+ drivers/media/video/samsung/3xa_sensor.h | 3298 ++
+ drivers/media/video/samsung/4xa_sensor.c | 349 +
+ drivers/media/video/samsung/4xa_sensor.h | 2377 +
+ drivers/media/video/samsung/Makefile | 9 +
+ drivers/media/video/samsung/adv7180.c | 421 +
+ drivers/media/video/samsung/adv7180.h | 71 +
+ drivers/media/video/samsung/mt9p012.c | 268 +
+ drivers/media/video/samsung/mt9p012.h | 758 +
+ drivers/media/video/videodev2_s3c.h | 210 +
+ drivers/mmc/core/bus.c | 1 +
+ drivers/mmc/core/mmc.c | 10 +-
+ drivers/mmc/host/Kconfig | 47 +
+ drivers/mmc/host/Makefile | 3 +-
+ drivers/mmc/host/s3c-hsmmc.c | 1398 +
+ drivers/mmc/host/s3c-hsmmc.h | 101 +
+ drivers/mmc/host/s3cmci.c | 893 +
+ drivers/mmc/host/s3cmci.h | 52 +
+ drivers/mtd/nand/Kconfig | 48 +-
+ drivers/mtd/nand/Makefile | 3 +-
+ drivers/mtd/nand/s3c_nand.c | 930 +
+ drivers/mtd/onenand/Makefile | 10 +-
+ drivers/mtd/onenand/onenand_bbt.c | 10 +-
+ drivers/mtd/onenand/s3c_onenand.c | 2636 ++
+ drivers/mtd/onenand/s3c_onenand.h | 158 +
+ drivers/net/Kconfig | 2 +-
+ drivers/net/cs89x0.c | 48 +-
+ drivers/net/irda/Kconfig | 6 +
+ drivers/net/irda/Makefile | 1 +
+ drivers/net/irda/s3c-sir.c | 1166 +
+ drivers/net/smc911x.c | 11 +
+ drivers/net/smc911x.h | 2 +-
+ drivers/rtc/rtc-s3c.c | 103 +-
+ drivers/serial/21285.c | 6 +-
+ drivers/serial/Kconfig | 63 +-
+ drivers/serial/Makefile | 4 +-
+ drivers/serial/s3c2410.c | 19 +-
+ drivers/serial/s3c6400.c | 1676 +
+ drivers/serial/s5pc100.c | 1643 +
+ drivers/spi/Kconfig | 51 +
+ drivers/spi/Makefile | 12 +
+ drivers/spi/hspi-s3c24xx.c | 773 +
+ drivers/spi/hspi-s3c24xx.h | 95 +
+ drivers/spi/hspi-s3c64xx.c | 789 +
+ drivers/spi/hspi-s3c64xx.h | 95 +
+ drivers/spi/spi-dev.c | 379 +
+ drivers/spi/spi-dev.h | 138 +
+ drivers/spi/spi_s3c24xx.c | 2 +-
+ drivers/usb/Makefile | 1 +
+ drivers/usb/gadget/Kconfig | 73 +
+ drivers/usb/gadget/Makefile | 3 +
+ drivers/usb/gadget/epautoconf.c | 18 +
+ drivers/usb/gadget/ether.c | 90 +-
+ drivers/usb/gadget/gadget_chips.h | 8 +
+ drivers/usb/gadget/s3c-udc-fs.c | 1875 +
+ drivers/usb/gadget/s3c-udc-hs.c | 1959 +
+ drivers/usb/gadget/s3c-udc-otg-hs.c | 1091 +
+ drivers/usb/gadget/s3c-udc-otg-xfer-dma.c | 947 +
+ drivers/usb/gadget/s3c-udc-otg-xfer-slave.c | 957 +
+ drivers/usb/gadget/s3c-udc.h | 136 +
+ drivers/usb/host/Kconfig | 5 +
+ drivers/usb/host/Makefile | 2 +-
+ drivers/usb/host/ohci-s3c2410.c | 95 +-
+ drivers/usb/host/s3c-otg/Makefile | 18 +
+ drivers/usb/host/s3c-otg/s3c-otg-common-common.h | 50 +
+ drivers/usb/host/s3c-otg/s3c-otg-common-const.h | 167 +
+ .../usb/host/s3c-otg/s3c-otg-common-datastruct.h | 870 +
+ .../usb/host/s3c-otg/s3c-otg-common-errorcode.h | 114 +
+ drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h | 317 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h | 96 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c | 256 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h | 73 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c | 651 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h | 144 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h | 420 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h | 225 +
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h | 180 +
+ drivers/usb/host/s3c-otg/s3c-otg-isr.c | 283 +
+ drivers/usb/host/s3c-otg/s3c-otg-isr.h | 72 +
+ drivers/usb/host/s3c-otg/s3c-otg-oci.c | 792 +
+ drivers/usb/host/s3c-otg/s3c-otg-oci.h | 83 +
+ drivers/usb/host/s3c-otg/s3c-otg-roothub.c | 467 +
+ drivers/usb/host/s3c-otg/s3c-otg-roothub.h | 84 +
+ .../host/s3c-otg/s3c-otg-scheduler-ischeduler.c | 427 +
+ .../usb/host/s3c-otg/s3c-otg-scheduler-readyq.c | 253 +
+ .../usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c | 449 +
+ .../usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h | 103 +
+ drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c | 838 +
+ .../host/s3c-otg/s3c-otg-transfer-nonperiodic.c | 147 +
+ .../usb/host/s3c-otg/s3c-otg-transfer-periodic.c | 131 +
+ .../usb/host/s3c-otg/s3c-otg-transfer-transfer.h | 147 +
+ .../host/s3c-otg/s3c-otg-transferchecker-bulk.c | 673 +
+ .../host/s3c-otg/s3c-otg-transferchecker-bulk.h | 88 +
+ .../host/s3c-otg/s3c-otg-transferchecker-checker.h | 66 +
+ .../host/s3c-otg/s3c-otg-transferchecker-common.c | 256 +
+ .../host/s3c-otg/s3c-otg-transferchecker-common.h | 79 +
+ .../host/s3c-otg/s3c-otg-transferchecker-control.c | 791 +
+ .../host/s3c-otg/s3c-otg-transferchecker-control.h | 100 +
+ .../s3c-otg/s3c-otg-transferchecker-interrupt.c | 582 +
+ .../s3c-otg/s3c-otg-transferchecker-interrupt.h | 97 +
+ drivers/video/Kconfig | 87 +
+ drivers/video/Makefile | 2 +
+ drivers/video/backlight/Kconfig | 8 +
+ drivers/video/backlight/Makefile | 1 +
+ drivers/video/backlight/smdk_bl.c | 166 +
+ drivers/video/cfbimgblt.c | 6 +
+ drivers/video/logo/Kconfig | 5 +
+ drivers/video/logo/Makefile | 1 +
+ drivers/video/logo/logo.c | 5 +
+ drivers/video/logo/logo_linux_clut224.ppm |11443 ++++-
+ .../video/logo/logo_linux_landscaped_clut224.ppm |48483 ++++++++++++++++++++
+ drivers/video/s3c/Makefile | 12 +
+ drivers/video/s3c/s3cfb.c | 991 +
+ drivers/video/s3c/s3cfb.h | 505 +
+ drivers/video/s3c/s3cfb_fimd3x.c | 840 +
+ drivers/video/s3c/s3cfb_fimd4x.c | 1295 +
+ drivers/video/s3c/s3cfb_lte480wv.c | 98 +
+ drivers/video/s3c/s3cfb_lts222qv.c | 311 +
+ drivers/video/s3c/s3cfb_ltv350qv.c | 288 +
+ drivers/video/s3c/s3cfb_spi.c | 129 +
+ drivers/video/s3c/s5pfb_fimd5x.c | 1259 +
+ drivers/video/s3c2410fb.c | 2 +-
+ fs/jffs2/scan.c | 8 +-
+ include/asm-arm/arch-s3c2410/dma.h | 282 +-
+ include/asm-arm/arch-s3c2410/entry-macro.S | 39 +
+ include/asm-arm/arch-s3c2410/gpio.h | 122 +-
+ include/asm-arm/arch-s3c2410/hardware.h | 162 +
+ include/asm-arm/arch-s3c2410/hsmmc.h | 51 +
+ include/asm-arm/arch-s3c2410/irqs-s5pc100.h | 132 +
+ include/asm-arm/arch-s3c2410/irqs.h | 152 +-
+ include/asm-arm/arch-s3c2410/map.h | 402 +-
+ include/asm-arm/arch-s3c2410/memory.h | 17 +
+ include/asm-arm/arch-s3c2410/regs-camif.h | 460 +
+ include/asm-arm/arch-s3c2410/regs-clock.h | 3 +-
+ include/asm-arm/arch-s3c2410/regs-gpio.h | 1566 +-
+ include/asm-arm/arch-s3c2410/regs-gpioj.h | 119 +-
+ include/asm-arm/arch-s3c2410/regs-hsmmc.h | 210 +
+ include/asm-arm/arch-s3c2410/regs-ide.h | 58 +
+ include/asm-arm/arch-s3c2410/regs-irq.h | 91 +-
+ include/asm-arm/arch-s3c2410/regs-keypad.h | 49 +
+ include/asm-arm/arch-s3c2410/regs-lcd.h | 482 +-
+ include/asm-arm/arch-s3c2410/regs-mem.h | 120 +-
+ include/asm-arm/arch-s3c2410/regs-onenand.h | 358 +
+ include/asm-arm/arch-s3c2410/regs-pp.h | 80 +
+ include/asm-arm/arch-s3c2410/regs-s3c-clock.h | 13 +
+ include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h | 61 +-
+ include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h | 268 +
+ include/asm-arm/arch-s3c2410/regs-s5pc100-clock.h | 323 +
+ include/asm-arm/arch-s3c2410/regs-serial.h | 415 +
+ include/asm-arm/arch-s3c2410/regs-tvenc.h | 198 +
+ include/asm-arm/arch-s3c2410/regs-tvscaler.h | 78 +
+ include/asm-arm/arch-s3c2410/regs-udc-hs.h | 153 +
+ include/asm-arm/arch-s3c2410/regs-udc.h | 157 +
+ include/asm-arm/arch-s3c2410/regs-usb-otg-hs.h | 307 +
+ include/asm-arm/arch-s3c2410/reserved_mem.h | 89 +
+ include/asm-arm/arch-s3c2410/system.h | 26 +
+ include/asm-arm/arch-s3c2410/timex.h | 11 +
+ include/asm-arm/irq.h | 4 +
+ include/asm-arm/memory.h | 2 +-
+ include/asm-arm/plat-s3c/adc.h | 29 +
+ include/asm-arm/plat-s3c/iic.h | 3 +
+ include/asm-arm/plat-s3c/map.h | 25 +-
+ include/asm-arm/plat-s3c/nand.h | 6 +
+ include/asm-arm/plat-s3c/regs-adc.h | 12 +
+ include/asm-arm/plat-s3c/regs-iic.h | 44 +
+ include/asm-arm/plat-s3c/regs-nand.h | 18 +-
+ include/asm-arm/plat-s3c/regs-rtc.h | 16 +
+ include/asm-arm/plat-s3c/regs-serial.h | 163 +-
+ include/asm-arm/plat-s3c/regs-timer.h | 106 +-
+ include/asm-arm/plat-s3c/ts.h | 31 +
+ include/asm-arm/plat-s3c/uncompress.h | 4 +
+ include/asm-arm/plat-s3c24xx/clock.h | 2 +
+ include/asm-arm/plat-s3c24xx/common-smdk.h | 6 +
+ include/asm-arm/plat-s3c24xx/cpu.h | 25 +
+ include/asm-arm/plat-s3c24xx/devs.h | 46 +-
+ include/asm-arm/plat-s3c24xx/dma.h | 3 +
+ include/asm-arm/plat-s3c24xx/pm.h | 7 +
+ include/asm-arm/plat-s3c24xx/regs-iis.h | 96 +-
+ include/asm-arm/plat-s3c24xx/regs-spi.h | 221 +-
+ include/asm-arm/plat-s3c24xx/s3c2416.h | 30 +
+ include/asm-arm/plat-s3c24xx/s3c2443.h | 4 +-
+ include/asm-arm/plat-s3c24xx/s3c2450.h | 30 +
+ include/asm-arm/plat-s3c64xx/clock.h | 65 +
+ include/asm-arm/plat-s3c64xx/regs-iis.h | 126 +
+ include/asm-arm/plat-s3c64xx/s3c6400.h | 27 +
+ include/asm-arm/plat-s3c64xx/s3c6410.h | 31 +
+ include/asm-arm/plat-s5p/clock.h | 67 +
+ include/asm-arm/plat-s5p/regs-gpio.h | 2115 +
+ include/asm-arm/plat-s5p/regs-iis.h | 126 +
+ include/asm-arm/plat-s5p/s5pc100.h | 31 +
+ include/linux/i2c-id.h | 8 +-
+ include/linux/i2c.h | 1 +
+ include/linux/ide.h | 7 +-
+ include/linux/interrupt.h | 20 +-
+ include/linux/mmc/card.h | 1 +
+ include/linux/mmc/host.h | 2 +
+ include/linux/mmzone.h | 3 +-
+ include/linux/usb/ch9.h | 1 +
+ include/sound/soc-dapm.h | 9 +
+ include/sound/soc.h | 7 +
+ kernel/power/Kconfig | 13 +
+ sound/soc/Kconfig | 6 +-
+ sound/soc/Makefile | 2 +-
+ sound/soc/codecs/Kconfig | 12 +
+ sound/soc/codecs/Makefile | 29 +
+ sound/soc/codecs/wm8580.c | 963 +
+ sound/soc/codecs/wm8580.h | 165 +
+ sound/soc/codecs/wm8753.c | 40 +
+ sound/soc/codecs/wm8990.c | 1657 +
+ sound/soc/codecs/wm8990.h | 904 +
+ sound/soc/codecs/wm9713.c | 1224 +
+ sound/soc/codecs/wm9713.h | 51 +
+ sound/soc/s3c24xx/Kconfig | 66 +-
+ sound/soc/s3c24xx/Makefile | 15 +-
+ sound/soc/s3c24xx/neo1973_wm8753.c | 2 +-
+ sound/soc/s3c24xx/s3c-i2s.c | 619 +
+ sound/soc/s3c24xx/s3c-i2s.h | 43 +
+ sound/soc/s3c24xx/s3c-pcm.c | 544 +
+ sound/soc/s3c24xx/s3c-pcm.h | 40 +
+ sound/soc/s3c24xx/s3c2443-ac97.c | 2 +-
+ sound/soc/s3c24xx/s3c2450-ac97.c | 561 +
+ sound/soc/s3c24xx/s3c2450-i2s.c | 556 +
+ sound/soc/s3c24xx/s3c24xx-ac97.h | 2 +
+ sound/soc/s3c24xx/s3c24xx-i2s.c | 2 +-
+ sound/soc/s3c24xx/smdk2443_wm9710.c | 2 +-
+ sound/soc/s3c24xx/smdk2450_wm8580.c | 395 +
+ sound/soc/s3c24xx/smdk2450_wm9713.c | 88 +
+ sound/soc/s3c64xx/Kconfig | 110 +
+ sound/soc/s3c64xx/Makefile | 18 +
+ sound/soc/s3c64xx/s3c6410-i2s-v32.c | 528 +
+ sound/soc/s3c64xx/s3c6410-i2s-v40.c | 604 +
+ sound/soc/s3c64xx/s3c64xx-ac97.c | 487 +
+ sound/soc/s3c64xx/s3c64xx-ac97.h | 25 +
+ sound/soc/s3c64xx/smdk6400_wm8753.c | 436 +
+ sound/soc/s3c64xx/smdk6410_wm8580.c | 365 +
+ sound/soc/s3c64xx/smdk6410_wm8990.c | 439 +
+ sound/soc/s3c64xx/smdk64xx_wm9713.c | 88 +
+ 385 files changed, 184748 insertions(+), 1907 deletions(-)
+ create mode 100644 Changelog
+ create mode 100644 RELEASENOTE
+ create mode 100644 arch/arm/boot/rootfs.cpio.gz
+ create mode 100644 arch/arm/boot/rootfs.uboot
+ create mode 100644 arch/arm/configs/fpgac100_defconfig
+ create mode 100644 arch/arm/configs/smdk2416mtd_defconfig
+ create mode 100644 arch/arm/configs/smdk2416nfs_defconfig
+ create mode 100644 arch/arm/configs/smdk2416ramdisk_defconfig
+ create mode 100644 arch/arm/configs/smdk2443mtd_defconfig
+ create mode 100644 arch/arm/configs/smdk2443nfs_defconfig
+ create mode 100644 arch/arm/configs/smdk2450mtd_defconfig
+ create mode 100644 arch/arm/configs/smdk2450nfs_defconfig
+ create mode 100644 arch/arm/configs/smdk2450ramdisk_defconfig
+ create mode 100644 arch/arm/configs/smdk6400mtd_defconfig
+ create mode 100644 arch/arm/configs/smdk6400nfs_defconfig
+ create mode 100644 arch/arm/configs/smdk6410mtd_defconfig
+ create mode 100644 arch/arm/configs/smdk6410nfs_defconfig
+ create mode 100644 arch/arm/configs/smdk6410onenand_defconfig
+ create mode 100644 arch/arm/configs/smdk6410ramdisk_defconfig
+ create mode 100644 arch/arm/configs/smdk6430mtd_defconfig
+ create mode 100644 arch/arm/configs/smdk6430nfs_defconfig
+ create mode 100644 arch/arm/configs/smdk6430ramdisk_defconfig
+ create mode 100644 arch/arm/mach-s3c2416/Kconfig
+ create mode 100644 arch/arm/mach-s3c2416/Makefile
+ create mode 100644 arch/arm/mach-s3c2416/clock.c
+ create mode 100644 arch/arm/mach-s3c2416/mach-smdk2416.c
+ create mode 100644 arch/arm/mach-s3c2416/s3c2416.c
+ create mode 100644 arch/arm/mach-s3c2450/Kconfig
+ create mode 100644 arch/arm/mach-s3c2450/Makefile
+ create mode 100644 arch/arm/mach-s3c2450/clock.c
+ create mode 100644 arch/arm/mach-s3c2450/mach-smdk2450.c
+ create mode 100644 arch/arm/mach-s3c2450/s3c2450.c
+ create mode 100644 arch/arm/mach-s3c6400/Kconfig
+ create mode 100644 arch/arm/mach-s3c6400/Makefile
+ create mode 100644 arch/arm/mach-s3c6400/clock.c
+ create mode 100644 arch/arm/mach-s3c6400/dma-sysfs.c
+ create mode 100644 arch/arm/mach-s3c6400/dma.c
+ create mode 100644 arch/arm/mach-s3c6400/irq.c
+ create mode 100644 arch/arm/mach-s3c6400/kdpmd.c
+ create mode 100644 arch/arm/mach-s3c6400/leds-s3c6400.c
+ create mode 100644 arch/arm/mach-s3c6400/leds.c
+ create mode 100644 arch/arm/mach-s3c6400/leds.h
+ create mode 100644 arch/arm/mach-s3c6400/mach-smdk6400.c
+ create mode 100644 arch/arm/mach-s3c6400/pm-s3c6400.c
+ create mode 100644 arch/arm/mach-s3c6400/pm-s3c6400.h
+ create mode 100644 arch/arm/mach-s3c6400/pm.c
+ create mode 100644 arch/arm/mach-s3c6400/s3c6400.c
+ create mode 100644 arch/arm/mach-s3c6410/Kconfig
+ create mode 100644 arch/arm/mach-s3c6410/Makefile
+ create mode 100644 arch/arm/mach-s3c6410/clock.c
+ create mode 100644 arch/arm/mach-s3c6410/dma-sysfs.c
+ create mode 100644 arch/arm/mach-s3c6410/dma.c
+ create mode 100644 arch/arm/mach-s3c6410/irq.c
+ create mode 100644 arch/arm/mach-s3c6410/leds-s3c6410.c
+ create mode 100644 arch/arm/mach-s3c6410/leds.c
+ create mode 100644 arch/arm/mach-s3c6410/leds.h
+ create mode 100644 arch/arm/mach-s3c6410/mach-smdk6410.c
+ create mode 100644 arch/arm/mach-s3c6410/pm.c
+ create mode 100644 arch/arm/mach-s3c6410/pwm/Kconfig
+ create mode 100644 arch/arm/mach-s3c6410/pwm/Makefile
+ create mode 100644 arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c
+ create mode 100644 arch/arm/mach-s3c6410/pwm/pwm-s3c6410.h
+ create mode 100644 arch/arm/mach-s3c6410/s3c6410.c
+ create mode 100644 arch/arm/mach-s5pc100/Kconfig
+ create mode 100644 arch/arm/mach-s5pc100/Makefile
+ create mode 100644 arch/arm/mach-s5pc100/clock.c
+ create mode 100644 arch/arm/mach-s5pc100/irq.c
+ create mode 100644 arch/arm/mach-s5pc100/mach-smdkc100.c
+ create mode 100644 arch/arm/mach-s5pc100/s5pc100.c
+ create mode 100644 arch/arm/plat-s3c24xx/adc-s3c24xx.c
+ create mode 100644 arch/arm/plat-s3c24xx/s3c24xx-dvfs.c
+ create mode 100644 arch/arm/plat-s3c24xx/s3c24xx-dvfs.h
+ create mode 100644 arch/arm/plat-s3c64xx/Kconfig
+ create mode 100644 arch/arm/plat-s3c64xx/Makefile
+ create mode 100644 arch/arm/plat-s3c64xx/adc-s3c64xx.c
+ create mode 100644 arch/arm/plat-s3c64xx/clock.c
+ create mode 100644 arch/arm/plat-s3c64xx/dma-pl080.c
+ create mode 100644 arch/arm/plat-s3c64xx/irq-pl192.c
+ create mode 100644 arch/arm/plat-s3c64xx/ltc3714.c
+ create mode 100644 arch/arm/plat-s3c64xx/pm.c
+ create mode 100644 arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
+ create mode 100644 arch/arm/plat-s3c64xx/s3c64xx-dvfs.c
+ create mode 100644 arch/arm/plat-s3c64xx/s3c64xx-dvfs.h
+ create mode 100644 arch/arm/plat-s3c64xx/sleep.S
+ create mode 100644 arch/arm/plat-s3c64xx/time-s3c64xx.c
+ create mode 100644 arch/arm/plat-s5pc1xx/Kconfig
+ create mode 100644 arch/arm/plat-s5pc1xx/Makefile
+ create mode 100644 arch/arm/plat-s5pc1xx/clock.c
+ create mode 100644 arch/arm/plat-s5pc1xx/dma-pl330-microcode.c
+ create mode 100644 arch/arm/plat-s5pc1xx/dma-pl330.c
+ create mode 100644 arch/arm/plat-s5pc1xx/gpio.c
+ create mode 100644 arch/arm/plat-s5pc1xx/irq-pl192.c
+ create mode 100644 arch/arm/plat-s5pc1xx/time-s5pc1xx.c
+ create mode 100644 drivers/char/s3c_mem.c
+ create mode 100644 drivers/char/s3c_mem.h
+ create mode 100644 drivers/i2c/busses/i2c-s3c64xx.c
+ create mode 100644 drivers/ide/arm/s3c-ide.c
+ create mode 100644 drivers/ide/arm/s3c-ide.h
+ create mode 100644 drivers/input/keyboard/s3c-keypad.c
+ create mode 100644 drivers/input/keyboard/s3c-keypad.h
+ create mode 100644 drivers/input/touchscreen/s3c-ts.c
+ create mode 100644 drivers/input/tsdev.c
+ create mode 100644 drivers/media/video/s3c_camera_driver.c
+ create mode 100644 drivers/media/video/s3c_camif.c
+ create mode 100644 drivers/media/video/s3c_camif.h
+ create mode 100644 drivers/media/video/samsung/3xa_sensor.c
+ create mode 100644 drivers/media/video/samsung/3xa_sensor.h
+ create mode 100644 drivers/media/video/samsung/4xa_sensor.c
+ create mode 100644 drivers/media/video/samsung/4xa_sensor.h
+ create mode 100644 drivers/media/video/samsung/Makefile
+ create mode 100644 drivers/media/video/samsung/adv7180.c
+ create mode 100644 drivers/media/video/samsung/adv7180.h
+ create mode 100644 drivers/media/video/samsung/mt9p012.c
+ create mode 100644 drivers/media/video/samsung/mt9p012.h
+ create mode 100644 drivers/media/video/videodev2_s3c.h
+ create mode 100644 drivers/mmc/host/s3c-hsmmc.c
+ create mode 100644 drivers/mmc/host/s3c-hsmmc.h
+ create mode 100644 drivers/mmc/host/s3cmci.c
+ create mode 100644 drivers/mmc/host/s3cmci.h
+ create mode 100644 drivers/mtd/nand/s3c_nand.c
+ create mode 100644 drivers/mtd/onenand/s3c_onenand.c
+ create mode 100644 drivers/mtd/onenand/s3c_onenand.h
+ create mode 100644 drivers/net/irda/s3c-sir.c
+ create mode 100644 drivers/serial/s3c6400.c
+ create mode 100644 drivers/serial/s5pc100.c
+ create mode 100644 drivers/spi/hspi-s3c24xx.c
+ create mode 100644 drivers/spi/hspi-s3c24xx.h
+ create mode 100644 drivers/spi/hspi-s3c64xx.c
+ create mode 100644 drivers/spi/hspi-s3c64xx.h
+ create mode 100644 drivers/spi/spi-dev.c
+ create mode 100644 drivers/spi/spi-dev.h
+ create mode 100644 drivers/usb/gadget/s3c-udc-fs.c
+ create mode 100644 drivers/usb/gadget/s3c-udc-hs.c
+ create mode 100644 drivers/usb/gadget/s3c-udc-otg-hs.c
+ create mode 100644 drivers/usb/gadget/s3c-udc-otg-xfer-dma.c
+ create mode 100644 drivers/usb/gadget/s3c-udc-otg-xfer-slave.c
+ create mode 100644 drivers/usb/gadget/s3c-udc.h
+ create mode 100644 drivers/usb/host/s3c-otg/Makefile
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-common-common.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-common-const.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-isr.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-isr.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-oci.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-oci.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-roothub.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-roothub.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c
+ create mode 100644 drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h
+ create mode 100644 drivers/video/backlight/smdk_bl.c
+ create mode 100644 drivers/video/logo/logo_linux_landscaped_clut224.ppm
+ create mode 100644 drivers/video/s3c/Makefile
+ create mode 100644 drivers/video/s3c/s3cfb.c
+ create mode 100644 drivers/video/s3c/s3cfb.h
+ create mode 100644 drivers/video/s3c/s3cfb_fimd3x.c
+ create mode 100644 drivers/video/s3c/s3cfb_fimd4x.c
+ create mode 100644 drivers/video/s3c/s3cfb_lte480wv.c
+ create mode 100644 drivers/video/s3c/s3cfb_lts222qv.c
+ create mode 100644 drivers/video/s3c/s3cfb_ltv350qv.c
+ create mode 100644 drivers/video/s3c/s3cfb_spi.c
+ create mode 100644 drivers/video/s3c/s5pfb_fimd5x.c
+ create mode 100644 include/asm-arm/arch-s3c2410/hsmmc.h
+ create mode 100644 include/asm-arm/arch-s3c2410/irqs-s5pc100.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-camif.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-hsmmc.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-ide.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-keypad.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-onenand.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-pp.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-s3c-clock.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-s5pc100-clock.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-serial.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-tvenc.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-tvscaler.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-udc-hs.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-udc.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-usb-otg-hs.h
+ create mode 100644 include/asm-arm/arch-s3c2410/reserved_mem.h
+ create mode 100644 include/asm-arm/plat-s3c/adc.h
+ create mode 100644 include/asm-arm/plat-s3c/ts.h
+ create mode 100644 include/asm-arm/plat-s3c24xx/s3c2416.h
+ create mode 100644 include/asm-arm/plat-s3c24xx/s3c2450.h
+ create mode 100644 include/asm-arm/plat-s3c64xx/clock.h
+ create mode 100644 include/asm-arm/plat-s3c64xx/regs-iis.h
+ create mode 100644 include/asm-arm/plat-s3c64xx/s3c6400.h
+ create mode 100644 include/asm-arm/plat-s3c64xx/s3c6410.h
+ create mode 100644 include/asm-arm/plat-s5p/clock.h
+ create mode 100644 include/asm-arm/plat-s5p/regs-gpio.h
+ create mode 100644 include/asm-arm/plat-s5p/regs-iis.h
+ create mode 100644 include/asm-arm/plat-s5p/s5pc100.h
+ create mode 100644 sound/soc/codecs/wm8580.c
+ create mode 100644 sound/soc/codecs/wm8580.h
+ create mode 100644 sound/soc/codecs/wm8990.c
+ create mode 100644 sound/soc/codecs/wm8990.h
+ create mode 100644 sound/soc/codecs/wm9713.c
+ create mode 100644 sound/soc/codecs/wm9713.h
+ create mode 100644 sound/soc/s3c24xx/s3c-i2s.c
+ create mode 100644 sound/soc/s3c24xx/s3c-i2s.h
+ create mode 100644 sound/soc/s3c24xx/s3c-pcm.c
+ create mode 100644 sound/soc/s3c24xx/s3c-pcm.h
+ create mode 100644 sound/soc/s3c24xx/s3c2450-ac97.c
+ create mode 100644 sound/soc/s3c24xx/s3c2450-i2s.c
+ create mode 100644 sound/soc/s3c24xx/smdk2450_wm8580.c
+ create mode 100644 sound/soc/s3c24xx/smdk2450_wm9713.c
+ create mode 100644 sound/soc/s3c64xx/Kconfig
+ create mode 100644 sound/soc/s3c64xx/Makefile
+ create mode 100644 sound/soc/s3c64xx/s3c6410-i2s-v32.c
+ create mode 100644 sound/soc/s3c64xx/s3c6410-i2s-v40.c
+ create mode 100644 sound/soc/s3c64xx/s3c64xx-ac97.c
+ create mode 100644 sound/soc/s3c64xx/s3c64xx-ac97.h
+ create mode 100644 sound/soc/s3c64xx/smdk6400_wm8753.c
+ create mode 100644 sound/soc/s3c64xx/smdk6410_wm8580.c
+ create mode 100644 sound/soc/s3c64xx/smdk6410_wm8990.c
+ create mode 100644 sound/soc/s3c64xx/smdk64xx_wm9713.c
+
+diff --git a/Changelog b/Changelog
+new file mode 100644
+index 0000000..9238d10
+--- /dev/null
++++ b/Changelog
+@@ -0,0 +1,1383 @@
++rel-0-0-0 : Ilho Lee
++dev-0-0-0 : Ilho Lee
++ This linux kernel version is "linux-2.6.24.2" gotten from kernel.org.
++ Release tag starts with rel-0-0-0 which is identical to open kernel
++ "linux-2.6.24.2".
++
++dev-0-0-1 : Ilho Lee
++ Samsung SoC's integration will be implemented into this kernel.
++ Vender tag starts with dev-0-0-1.
++ Modified files
++ Makefile
++
++ Added files
++ .cross_compile
++ arch/arm/configs/smdk2443mtd_defconfig
++dev-0-0-2 : Ilho Lee
++dev-0-0-3 : Ilho Lee
++ Some files for a LCD and a NAND on SMDK S3C2443 added & modified.
++
++dev-0-0-4 : Ilho Lee
++ Some files for a LCD and a NAND on SMDK S3C6400 added & modified.
++ arch/arm/configs/smdk6400mtd_defconfig
++
++dev-0-0-5 : Ilho Lee
++ To s3c6400, some codes causing unhandled fault fixed.
++ Modified files
++ arch/arm/kernel/entry-common.S
++ arch/arm/plat-s3c24xx/common-smdk.c
++ arch/arm/mach-s3c2443/s3c2443.c
++ arch/arm/mach-s3c2443/mach-smdk2443.c
++ arch/arm/mach-s3c6400/s3c6400.c
++ arch/arm/mach-s3c6400/mach-smdk6400.c
++
++dev-0-0-6: Jinsung Yang
++ - fixed devs.c, map.h and mach-smdkxxxx.c for 2443 and 6400
++
++dev-0-0-7: Ilho Lee
++ - Added an MMU exception handler for ARM1176
++ Modified files
++ arch/arm/mm/fault.c
++dev-0-0-8: Ilho Lee
++ - The chip ID of S3C6400 changed
++ Modified files
++ arch/arm/plat-s3c24xx/cpu.c
++
++dev-0-0-9: Ilho Lee
++ - clock.c for S3C64xx added
++ Modified files
++ arch/arm/plat-s3c24xx/clock.c
++ include/asm-arm/plat-s3c24xx/clock.h
++
++ Added files
++ arch/arm/plat-s3c64xx/clock.c
++ include/asm-arm/plat-s3c64xx/clock.h
++dev-0-0-10: Laputa
++ - DVFS feature of S3C64xx added
++ Modified files
++ drvier/char/Makefile --> in order to compile
++ driver/char/Kconfig --> in order to menu
++ Added files
++ drvier/char/s3c-dvfs --> feature driver
++
++dev-0-0-11: Ilho Lee
++ - Support(LCD, NAND, UART) for S3c6410 added
++ Added files
++ arch/arm/mach-s3c6410/Makefile
++ arch/arm/mach-s3c6410/Kconfig
++ arch/arm/mach-s3c6410/clock.c
++ arch/arm/mach-s3c6410/s3c6410.c
++ arch/arm/mach-s3c6410/mach-smdk6410.c
++
++dev-0-0-12: Ilho Lee
++ - Support(LCD, NAND) for S3c2450 added
++ Added files
++ arch/arm/mach-s3c2450/Makefile
++ arch/arm/mach-s3c2450/Kconfig
++ arch/arm/mach-s3c2450/clock.c
++ arch/arm/mach-s3c2450/s3c2450.c
++ arch/arm/mach-s3c2450/mach-smdk2450.c
++
++dev-0-0-13: Ilho Lee
++ - Support(UART) for S3c2450 added
++ Modified files
++ drivers/serial/s3c2410.c
++
++dev-0-0-14: Laputa
++ -DVFS make condition changed and GPIO debug.
++ -DVFS had been upgraded and modified DVS and DFS mode in order to power .
++ -GPIO bug patch : offse value wrong calcuration GPK,GPH,GPL
++ Modified files
++ kernel/power/kconfig
++ driver/char/Makefile
++ driver/char/s3c-dvfs/s3c-dvfs.c
++ arch/arm/plat-s3c24xx/gpio.c
++ void s3c_gpio_cfgpin(unsigned int pin, unsigned int function)....
++
++dev-0-0-15: Ilho Lee
++ - HS-MMC driver for S3c2450/2443/6400/6410 added
++ Added files
++ drivers/mmc/host/s3c-hsmmc.[ch]
++
++dev-0-0-16: Ilho Lee
++ - HS-MMC movinand driver for S3c2450/2443/6400/6410 added
++ Added files
++ drivers/mmc/host/s3c-hsmmc.[ch]
++
++dev-0-0-17: laputa
++ - arch/arm/plat-s3c24xx/gpio.c gpio configuration calcuration path
++ changed : only for 6400's 4bit definition
++
++dev-0-0-18: Ilho Lee
++ - Camera for S3c2450/2443/6400/6410 added
++ Modified files
++ arch/arm/mach-s3c2443/clock.c
++ arch/arm/mach-s3c2450/clock.c
++ arch/arm/mach-s3c6400/clock.c
++ arch/arm/mach-s3c6410/clock.c
++
++ Added files
++ drivers/media/video/s3c_camera_driver.c
++ drivers/media/video/s3c_camif.[ch]
++ drivers/media/video/s3c_camif_fsm.c
++
++dev-0-0-19: Ilho Lee
++ - A patch for HS-MMC driver over S3C6410 applied.
++ Modified files
++ arch/arm/mach-s3c6410/mach-smdk6410.c
++
++dev-0-0-20: Ilho Lee
++ - A USB-OTG driver for S3C6410 added
++ Added files
++ drivers/usb/gadet/s3c-udc-otg-hs.c
++
++dev-0-0-21: Ilho Lee
++ - Some bugs on the HS-MMC driver fixed.
++ Modified files
++ drivers/mmc/host/s3c-hsmmc.c
++
++dev-0-0-22: Ilho Lee
++ - Some unused clock sources deleted.
++ Modified files
++ arch/arm/mach-s3c6400/clock.c
++ arch/arm/mach-s3c6410/clock.c
++ arch/arm/plat-s3c64xx/clock.c
++ include/asm-arm/plat-s3c64xx/clock.h
++dev-0-0-23: Laputa
++ - changed to set default duplex from half to full duplex
++ Modified file
++ M driver/net/cs89x0.c
++
++dev-0-0-24: Ilho Lee
++ - Touchscreen interface using TSDEV api added
++ Added files
++ drivers/input/tsdev.c
++
++ Modified files
++ drivers/input/Kconfig
++ drivers/input/Makefile
++
++dev-0-0-25: Ilho Lee
++ - SMDK2450 code added
++ Modified files
++ arch/arm/mach-s3c2450/clock.c
++ arch/arm/mach-s3c2450/s3c2450.c
++ drivers/video/s3c_lte480wv.c
++
++dev-0-0-26: Ilho Lee
++ - NAND, LCD, touchscreen and UART drivers confirmed on
++ SMDK2443/2450/6400/6410
++
++dev-0-0-27: Jongpill Lee
++ -Added CLKUART on Uart Clock Source
++ Modified File:
++ M drivers/serial/s3c6400.c
++
++dev-0-0-28: Ilho Lee
++ - 12-bit resolution touchscreen drivers for S3C2450/6410 added
++ Modified File:
++ M drivers/input/touchscreen/s3c-ts.c
++
++dev-0-0-29: Ilho Lee
++ - Some codes for S3C2416 are being added.
++ Added Files:
++ A arch/arm/mach-s3c2416/clock.c
++ A arch/arm/mach-s3c2416/mach-smdk2416.c
++ A arch/arm/mach-s3c2416/s3c2416.c
++ A arch/arm/mach-s3c2416/Makefile
++ A arch/arm/mach-s3c2416/Kconfig
++
++ Modified File:
++ M arch/arm/Makefile
++ M arch/arm/Kconfig
++ M arch/arm/plat-s3c24xx/cpu.c
++
++dev-0-0-30: Ilho Lee
++ - 2-channel HS-MMC driver for S3C2450 is being added. (1 channel
++ confirmed)
++ Modified File:
++ M arch/arm/plat-s3c24xx/devs.c
++ M arch/arm/mach-s3c2450/s3c2450.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++ M include/asm-arm/arch-s3c2410/irqs.h
++ M include/asm-arm/arch-s3c2410/map.h
++
++dev-0-0-31: Ilho Lee
++ - 2-channel HS-MMC driver for S3C2450 has been added.
++ Modified File:
++ M arch/arm/plat-s3c24xx/devs.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++ M include/asm-arm/arch-s3c2410/irqs.h
++ M drivers/mmc/host/s3c-hsmmc.c
++
++dev-0-0-32: Ilho Lee
++ - 4BA CIS module added.
++ Modified File:
++ M drivers/media/video/s3c-camera-driver.c
++ M drivers/media/video/samsung/Makefile
++ M drivers/media/video/samsung/Kconfig
++
++ Add Files :
++ A drivers/media/video/4xa_sensor.h
++ A drivers/media/video/4xa_sensor.c
++
++dev-0-0-33: Ilho Lee
++ - 2-channel HS-MMC driver for S3C6410 has been added.
++ Modified File:
++ M arch/arm/plat-s3c24xx/devs.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M drivers/mmc/host/s3c-hsmmc.c
++
++dev-0-0-34: Ilho Lee
++ - 100Mbit ethernet drivers over SMC9115 for S3C6410/S3C2450 have been added.
++ Modified File:
++ M arch/arm/plat-s3c24xx/devs.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++ M drivers/net/Kconfig
++ M drivers/net/smc911x.c
++ M drivers/net/smc911x.h
++
++dev-0-0-35: Ilho Lee
++ - Centerwise cropping V4L2 interface added
++ Modified File:
++ M drivers/media/video/s3c-camera-driver.c
++
++dev-0-0-36: Ilho Lee
++ - Codes for s3c2416 added.
++ Added Files:
++ A arch/arm/mach-s3c2416/clock.c
++ A arch/arm/mach-s3c2416/s3c2416.c
++ A arch/arm/mach-s3c2416/mach-smdk2416.c
++
++dev-0-0-37: Ilho Lee
++ - DOUTmpll gets adopted for the SD clock source of the HS-MMC
++ controller.
++ Modified Files:
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/mach-s3c6410/clock.c
++
++dev-0-0-38: Ilho Lee
++ - Feedback delay value for the HS-MMC driver modified.
++ Modified Files:
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++ M arch/arm/mach-s3c2416/mach-smdk2416.c
++ M drivers/mmc/host/s3c-hsmmc.c
++
++dev-0-0-39: Ilho Lee
++ - A bug of s3c touchscreen D/D on s3c6400 fixed
++ Modified File:
++ M drivers/input/touchscreen/s3c-ts.c
++
++dev-0-0-40: Jinsung Yang
++ - Finalize with old s3c frambuffer driver
++
++dev-0-0-41: Jinsung Yang
++ - Display driver refactoring: 1st phase complete
++
++ Added files:
++ A drivers/video/Kconfig
++ A drivers/video/Makefile
++ A drivers/video/s3c/s3c24xxfb.c
++ A drivers/video/s3c/s3c24xxfb_spi.c
++ A drivers/video/s3c/s3c64xxfb.c
++ A drivers/video/s3c/s3c64xxfb_spi.c
++ A drivers/video/s3c/s3cfb.c
++ A drivers/video/s3c/s3cfb_lts222qv.c
++ A drivers/video/s3c/s3cfb_ltv350qv.c
++ A drivers/video/s3c/s3cfb_lte480wv.c
++
++ Removed Files:
++ R drivers/video/s3cfb.c
++ R drivers/video/s3cfb.h
++
++dev-0-0-42: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (Phase-1)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-43: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (Phase-2)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-44: Kyoungil Kim
++ - Keypad driver porting and Qwerty Keyboard mapping at SMDK6410
++
++ Added files:
++ A drivers/input/keyboard/s3c-keypad.c
++ A drivers/input/keyboard/s3c-keypad.h
++ A include/asm-arm/arch-s3c2410/regs-keypad.h
++
++ Modified File:
++ M drivers/input/keyboard/Kconfig
++ M drivers/input/keyboard/Makefile
++
++dev-0-0-45: Kyoungil Kim
++ - Keypad driver warning is fixed.
++
++ Modified File:
++ M drivers/input/keyboard/s3c-keypad.c
++
++dev-0-0-46: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (Phase-3)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-47: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (Enumeration done)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-48: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-1)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-49: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-2)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-50: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-2)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-51: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-2)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-52: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-3)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-53: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-3)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-54: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-3)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-55: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-4)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-0-0-56: Ilho Lee
++ - OTG DMA mode is being implemented on S3C6410 (UMS Phase-4)
++ Modified File:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++rel-0-1-0 : Ryu Euiyoul
++ - release to SISO (June 18th 2008)
++
++dev-0-0-57: jongpill Lee
++ - Support UBI(Unsourted Block Image) on SMDK Board
++
++ Modified Files:
++ M drivers/mtd/ubi/build.c
++ M include/mtd/ubi-header.h
++
++dev-0-0-58: Jongpill Lee
++ - Support RTC on SMDK6410
++
++ Modified Files:
++ M drivers/rtc/rtc-s3c.c
++
++dev-0-0-59: Ryu Euiyoul
++ - Supports smdk6410 wm9713 AC97 interface device driver
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/dma-pl080.c
++ M sound/soc/codecs/wm8753.c
++ M sound/soc/s3c/s3c-pcm.c
++ M sound/soc/s3c/s3c-pcm.h
++ Added Files:
++ A sound/soc/s3c/smdk64xx_wm9713.c
++ A sound/soc/s3c/s3c64xx-ac97.h
++ A sound/soc/s3c/s3c64xx-ac97.c
++ A sound/soc/codecs/wm9713.c
++ A sound/soc/codecs/wm9713.h
++
++dev-0-0-60: Ilho Lee
++ - Some files added into mach-s3c6410 directory
++ Added File:
++ A arch/arm/mach-s3c6410/dma.c
++ A arch/arm/mach-s3c6410/irq.c
++ A arch/arm/mach-s3c6410/pm.c
++ A arch/arm/mach-s3c6410/leds.c
++
++rel-1-0-0: Kyoungil Kim
++ - Official Release: SMDK6410 alpha version (08.06.30)
++
++dev-1-0-0: Kyoungil Kim
++
++dev-1-0-1: Jongpill Lee
++ - Support DVFS on SMDK6410
++
++ Modified Files:
++ M drivers/char/Makefile
++ M drivers/char/s3c-dvfs/s3c-dvfs.c
++ M drivers/char/s3c-dvfs/s3c-dvfs.h
++
++dev-1-0-2: Jongpill Lee
++ - Support HS-SPI on SMDK6410
++
++ Added Files:
++ A drivers/spi/hspi-s3c24xx.c
++ A drivers/spi/hspi-s3c24xx.h
++ A drivers/spi/hspi-s3c64xx.c
++ A drivers/spi/hspi-s3c64xx.h
++ A drivers/spi/spi-dev.c
++ A drivers/spi/spi-dev.h
++
++ Modified Files:
++ M arch/arm/plat-s3c24xx/devs.c
++ M drivers/char/s3c-dvfs/s3c-dvfs.h
++ M drivers/spi/Kconfig
++ M drivers/spi/Makefile
++ M include/asm-arm/plat-s3c24xx/regs-spi.h
++ M include/linux/interrupt.h
++
++dev-1-0-3: jongpill Lee
++ - HS-SPI bug fixed
++
++ Modified Files:
++ M drivers/spi/hspi-s3c64xx.c
++
++dev-1-0-4: jongpill Lee
++ - SPI is deleted in default config
++
++ Modified Files:
++ M arch/arm/configs/smdk2450mtd_defconfig
++ M arch/arm/configs/smdk2450nfs_defconfig
++ M include/asm-arm/arch-s3c2410/map.h
++
++dev-1-0-5: Jongpill Lee
++ - Support IrDA on smdk6410
++
++ Added Files:
++ A drivers/net/irda/s3c-sir.c
++
++ Modified Files:
++ M drivers/net/irda/Kconfig
++ M drivers/net/irda/Makefile
++
++dev-1-0-6: Jongpill Lee
++ - Support APM on SMDK6410
++
++ Added Files:
++ A arch/arm/plat-s3c64xx/pm.c
++ A arch/arm/plat-s3c64xx/sleep.S
++ A include/asm-arm/arch-s3c2410/regs-adc.h
++ A include/asm-arm/arch-s3c2410/regs-serial.h
++
++ Modified Files:
++ M arch/arm/configs/smdk6410mtd_defconfig
++ M arch/arm/configs/smdk6410nfs_defconfig
++ M arch/arm/mach-s3c6410/leds.c
++ M arch/arm/plat-s3c64xx/Makefile
++ M drivers/serial/s3c6400.c
++
++dev-1-0-7: Ilho Lee
++ - Support the ADC function for S3C6410
++
++ Added File:
++ A drivers/char/s3c-adc.c
++
++ Modified File:
++ M arch/arm/plat-s3c24xx/devs.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++
++dev-1-0-8: Byungjae Lee
++ - Support USB Host1.1 for SMDK6410
++ Changed default configuration to enable USB Host1.1
++
++ Modified File:
++ M arch/arm/configs/smdk6410mtd_defconfig
++ M drivers/usb/host/ohci-s3c2410.c
++
++dev-1-0-9: Ilho Lee
++ - OneNAND D/D for S3C6410 added
++
++ Added File:
++ A drivers/mtd/onenand/s3c-onenand.c
++
++dev-1-0-10: Byungjae Lee
++ - Support Ethernet gadget on Slave mode for SMDK6410
++
++ Modified Files:
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M drivers/usb/gadget/Kconfig
++ M drivers/usb/gadget/epautoconf.c
++ M drivers/usb/gadget/ether.c
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++ M drivers/usb/gadget/s3c-udc.h
++ M include/asm-arm/arch-s3c2410/regs-usb-otg-hs.h
++
++dev-1-0-11: Byungjae Lee
++ - Added OTGPHY enbale at clcok.c for SMDK6410 USB Host
++
++ Modified Files:
++ M arch/arm/mach-s3c6410/clock.c
++ M drivers/usb/host/ohci-s3c2410.c
++
++dev-1-0-12: Ilho Lee
++ - OneNAND D/D for S3C6410 changed
++
++ Added File:
++ A drivers/mtd/onenand/s3c-onenand.c
++
++dev-1-0-13: Jongpill Lee
++ - Support PWM on SMDK6410
++
++ Modified Files:
++ M arch/arm/Kconfig
++ M arch/arm/mach-s3c6400/s3c6400.c
++ M arch/arm/mach-s3c6410/s3c6410.c
++ M drivers/video/s3c/s3cfb.h
++ M drivers/video/s3c/s3cfb_fimd4x.c
++ M drivers/Kconfig
++ M drivers/Makefile
++
++ Added Files:
++ A drivers/pwm/Kconfig
++ A drivers/pwm/Makefile
++ A drivers/pwm/pwm-s3c2450.c
++ A drivers/pwm/pwm-s3c2450.h
++ A drivers/pwm/pwm-s3c6410.c
++ A drivers/pwm/pwm-s3c6410.h
++
++rel-2-0-0: Kyoungil Kim
++ - Official Release: SMDK6410 beta version (08.08.08)
++
++dev-2-0-0: Kyoungil Kim
++
++dev-2-0-1: Jinsung Yang
++ - Bug fix for SMDK64xx UART
++
++ Modified files:
++ include/asm-arm/plat-s3c/uncompress.h
++
++dev-2-0-2: Ilho Lee
++ - 12 bit mode for ADC added
++
++ Modified files:
++ drivers/char/s3c-adc.c
++
++rel-2-0-1: Kyoungil Kim
++ - Official Release(08.08.12)
++
++dev-2-0-3: Jongpill Lee
++ - Modified NAND partition Information
++
++ Modified Files:
++ arch/arm/plat-s3c24xx/common-smdk.c
++
++dev-2-0-4: Ilho Lee
++ - regs-adc.h in pm.c deleted
++
++ Modified Files:
++ arch/arm/plat-s3c64xx/pm.c
++
++dev-2-0-5: Jongpill Lee
++ - delete PM support from default smdk6410 NFS default configuration
++
++ Modified Files:
++ M arch/arm/configs/smdk6410nfs_defconfig
++
++rel-2-0-2: Jongpill Lee
++ -Official Release(08.08.13)
++
++dev-2-0-6: Jongpill Lee
++ - bug fixed for s3c6410 idle mode
++
++ Modified File:
++ M arch/arm/mach-s3c6410/s3c6410.c
++
++dev-2-0-7: Ilho Lee
++ - A bug fixed for non-MTD partitions
++
++ Modified File:
++ M arch/arm/plat-s3c24xx/common-smdk.c
++
++dev-2-0-8: Jiun Yu
++ - Support module drivers
++
++ Modified Files:
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M include/asm-arm/arch-s3c2410/reserved_mem.h
++
++ Added Files:
++ A include/asm-arm/arch-s3c2410/regs-pp.h
++ A include/asm-arm/arch-s3c2410/regs-tvenc.h
++ A include/asm-arm/arch-s3c2410/regs-tvscaler.h
++
++rel-2-1-0: Jongpill Lee
++ - Official Release(08.08.20)
++
++dev-2-1-0: Jongpill Lee
++
++dev-2-1-1: Jongpill Lee
++
++ -Fixed SPI Prevent Defect
++
++ MOdified Files:
++ M drivers/spi/spi_s3c24xx.c
++
++rel-2-1-1: Kyoungil Kim
++ - Official Release(08.08.29)
++
++rel-2-1-2: Jinsung Yang
++ - Official Release(08.08.29 2nd)
++
++dev-2-1-2: Jongpill Lee
++ - Temporary update for Dynamic Timer on SMDK6410
++
++ Modified Files:
++
++ M arch/arm/plat-s3c64xx/time-s3c64xx.ci
++
++dev-2-1-3: jongpill Lee
++ - Set default time for rtc initial value.
++
++ M drivers/rtc/rtc-s3c.c
++
++dev-2.1.4: SungJun Bae
++ ./sound/soc/s3c24xx directory was restored.
++
++ Modified Files:
++
++ M sound/soc/Kconfig sound/soc/Makefile
++
++ Added Files:
++
++ A sound/soc/s3c24xx/Kconfig sound/soc/s3c24xx/Makefile
++ A sound/soc/s3c24xx/lm4857.h
++ A sound/soc/s3c24xx/neo1973_wm8753.c
++ A sound/soc/s3c24xx/s3c-i2s.c
++ A sound/soc/s3c24xx/s3c-i2s.h
++ A sound/soc/s3c24xx/s3c-pcm.c
++ A sound/soc/s3c24xx/s3c-pcm.h
++ A sound/soc/s3c24xx/s3c2443-ac97.c
++ A sound/soc/s3c24xx/s3c2450-i2s.c
++ A sound/soc/s3c24xx/s3c24xx-ac97.h
++ A sound/soc/s3c24xx/s3c24xx-i2s.h
++ A sound/soc/s3c24xx/s3c6410-i2s-v40.c
++ A sound/soc/s3c24xx/s3c64xx-ac97.c
++ A sound/soc/s3c24xx/s3c64xx-ac97.h
++ A sound/soc/s3c24xx/smdk2443_wm9710.c
++ A sound/soc/s3c24xx/smdk2450_wm8580.c
++ A sound/soc/s3c24xx/smdk2450_wm9713.c
++ A sound/soc/s3c24xx/smdk6400_wm8753.c
++ A sound/soc/s3c24xx/smdk6410_wm8580.c
++ A sound/soc/s3c24xx/smdk64xx_wm9713.c
++
++ Delete Files:
++
++ D sound/soc/s3c/Kconfig
++ D sound/soc/s3c/Makefile
++ D sound/soc/s3c/lm4857.h
++ D sound/soc/s3c/s3c-i2s.h
++ D sound/soc/s3c/s3c-pcm.h
++ D sound/soc/s3c/s3c24xx-ac97.h
++ D sound/soc/s3c/s3c24xx-i2s.h
++ D sound/soc/s3c/s3c64xx-ac97.h
++ D sound/soc/s3c/neo1973_wm8753.c
++ D sound/soc/s3c/s3c2443-ac97.c
++ D sound/soc/s3c/s3c2450-i2s.c
++ D sound/soc/s3c/s3c24xx-i2s.c
++ D sound/soc/s3c/s3c6410-i2s-v40.c
++ D sound/soc/s3c/s3c64xx-ac97.c
++ D sound/soc/s3c/s3c-i2s.c
++ D sound/soc/s3c/s3c-pcm.c
++ D sound/soc/s3c/smdk2443_wm9710.c
++ D sound/soc/s3c/smdk2450_wm9713.c
++ D sound/soc/s3c/smdk6400_wm8753.c
++ D sound/soc/s3c/smdk6410_wm8580.c
++ D sound/soc/s3c/smdk64xx_wm9713.c
++
++dev-2-1-5: Jongpill Lee
++
++ - RTC Set time function is erased
++
++ Modified files:
++ M drivers/rtc/rtc-s3c.c
++
++dev-2-1-6: Jongpill Lee
++
++ - Support Tickless Timer on SMDK6410
++
++ Modified Files:
++ M arch/arm/mach-s3c6410/s3c6410.c
++ M arch/arm/plat-s3c64xx/time-s3c64xx.c
++
++dev-2-1-7: Byungjae Lee
++ - Support USB OTG Host for SMDK6410
++ Support Device Classes are only HID(Keyboard, Mouse), UMS and Card
++ Reader.
++
++ Modified Files
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/plat-s3c24xx/devs.c
++ M drivers/usb/Makefile
++ M drivers/usb/gadget/Kconfig
++ M drivers/usb/host/Kconfig
++ M drivers/usb/host/Makefile
++ M include/asm-arm/plat-s3c24xx/devs.h
++ Addef Files
++ A drivers/usb/host/s3c-otg/*
++
++rel-2-1-3: Jinsung Yang
++ - Official Release (08.09.05)
++
++dev-2-1-8: Jinsung Yang
++ - Finalize tagging before kernel merge with C100 tree
++
++dev-2-1-9: Euiyoul Ryu
++ - Merge with C100 tree
++
++dev-2-1-10: Jongpill Lee
++ - delete include/asm-arm/arch-s3c2410/regs-serial.h file
++
++ Modified Files
++ M arch/arm/plat-s3c64xx/pm.c
++ Removed Files
++ R include/asm-arm/arch-s3c2410/regs-serial.h
++
++dev-2-1-11: Ilho Lee
++ - Modified 3D D/D to support kmalloc and lock API
++
++ Modified Files
++ M drivers/video/g3d/s3c_g3d.c
++
++dev-2-1-12: Jongpill Lee
++ - Bug fixed in DVFS code
++
++ Modified Files
++ M drivers/char/s3c-dvfs/s3c-dvfs.h
++
++dev-2-1-13: Jinsung Yang
++ - QoS configuration optimized to resolve mfc underrun
++ - Some bugs fixed and misc changes for display driver
++
++ Modified files:
++ drivers/video/s3c/*
++ arch/arm/mach-s3c6410/mach-smdk6410.c
++ include/asm-arm/arch-s3c2410/map.h
++
++rel-2-1-4: Kyoungil Kim
++ - Official Release (08.09.17)
++
++dev-2-1-14: Jongpill Lee
++ - Modified Some function(modify HS-SPI driver strength)
++
++ Modified Files:
++ M drivers/spi/hspi-s3c64xx.c
++
++
++dev-2-1-15: Ilho Lee
++ - Modified 3D D/D to support memory-sharing
++
++ Modified Files
++ M drivers/video/g3d/s3c_g3d.c
++
++dev-2-1-16: Jinsung Yang
++ [Display Con.] 28 bpp with pixel alpha blending support
++
++ Modified files:
++ M drivers/video/s3c/s3cfb.c
++ M include/asm-arm/arch-s3c2410/regs-lcd.h
++
++dev-2-1-17: Kyoungil Kim
++ - Modified Kconfig for SMDK6431
++
++ Modified Files
++ M arch/arm/mach-s3c6410/Kconfig
++
++dev-2-1-18: Kyoungil Kim
++ - Modified Touchscreen x,y position for SMDK6431
++
++ Modified Files
++ M drivers/input/touchscreen/s3c-ts.c
++
++rel-2-2-0: Kyoungil Kim
++ - Official Release for SMDK6431 (08.09.23)
++
++dev-2-2-0: Kyoungil Kim
++
++dev-2-2-1: Kyoungil Kim
++ - Modified Kconfig support new touchscreen version
++
++ Modified Files
++ M drivers/input/touchscreen/Kconfig
++ M drivers/input/touchscreen/s3c-ts.c
++
++rel-2-2-1: Kyoungil Kim
++ - Official Release for SMDK6431 (08.09.29)
++
++dev-2-2-2: Ilho Lee
++ - Modified PL080 DMA D/D to support scatter&gather DMA
++
++ Modified Files
++ M arch/arm/plat-s3c64xx/dma-pl080.c
++
++rel-2-2-2: Jongpill Lee
++ - Official Release for SMDK6410 final(08.10.13)
++
++dev-2-2-3: Jongpill Lee
++ - Bug fixed in getting clock source
++
++ Modified Files:
++ M arch/arm/configs/smdk6410mtd_defconfig
++ M arch/arm/mach-s3c6400/clock.c
++ M arch/arm/mach-s3c6410/clock.c
++
++dev-2-2-4: Jinsung Yang
++ - Improvements of fimd4x/5x color key
++
++rel-2-2-3: Jinsung Yang
++ - Official Release (08.10.17)
++
++dev-2-2-5: Ilho Lee
++ - Modified s3c6410onenand_defconfig
++
++ Modified Files
++ M arch/arm/configs/smdk6410onenand_defconfig
++
++rel-2-2-4: Kyoungil Kim
++ - Official Release (08.10.20)
++
++dev-2-2-6: SungJun Bae
++ - Support Non Multichannel I2S (I2S0)
++ - Support I2S wm8990
++
++rel-2-2-5: Kyoungil Kim
++ - Official Release (08.10.24)
++
++dev-2-2-7: SungJun Bae
++ - "sound/soc/s3c24xx/s3c6410-i2s-v32.c" added.
++
++rel-2-2-6: SungJun Bae
++ - Official Release (08.10.27)
++
++dev-2-2-8: Jongpill Lee
++ - Add function for save and restore for pm
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/pm.c
++ M include/asm-arm/plat-s3c24xx/pm.h
++
++dev-2-2-9: Jongpill Lee
++ - Modified suspend and resume function
++
++ Modified Files:
++ M drivers/media/video/s3c_camera_driver.c
++
++dev-2-2-10: Byungjae Lee
++ - Support DMA mode for s3c6410 File-backed Storage Gadget.
++
++ Modefied File
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++rel-3-0-0: Jinsung Yang
++ - Official Release (08.11.04)
++ - Patch Baseline
++
++dev-3-0-0: Jinsung Yang
++
++dev-3-0-1: Jongpill Lee
++ - Modified UBI to use dynamic device node
++
++ MOdified Files
++ M drivers/mtd/ubi/build.c
++ M include/mtd/ubi-header.h
++
++dev-3-0-2: Jinsung Yang
++ - Generic GPIO Interface support
++
++ Modified files:
++ M arch/arm/mach-s3c6400/leds-s3c6400.c
++ M arch/arm/mach-s3c6400/leds.c
++ M arch/arm/mach-s3c6410/leds-s3c6410.c
++ M arch/arm/mach-s3c6410/leds.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/mach-s3c6410/s3c6410.c
++ M arch/arm/plat-s3c64xx/irq-pl192.c
++ M arch/arm/plat-s3c64xx/pm.c
++ M arch/arm/plat-s3c64xx/time-s3c64xx.c
++ M arch/arm/plat-s5pc1xx/irq-pl192.c
++ M arch/arm/plat-s5pc1xx/time-s5pc1xx.c
++ M drivers/char/s3c-dvfs/s3c-dvfs.h
++ M drivers/i2c/busses/i2c-s3c2410.c
++ M drivers/media/video/s3c_camera_driver.c
++ M drivers/media/video/s3c_camif.c
++ M drivers/mmc/host/s3c-hsmmc.c
++ M drivers/mmc/host/s3cmci.c
++ M drivers/net/irda/s3c-sir.c
++ M drivers/pwm/pwm-s3c6410.c
++ M drivers/serial/s3c6400.c
++ M drivers/serial/s5pc100.c
++ M drivers/spi/hspi-s3c64xx.c
++ M drivers/video/s3c/s3cfb_fimd4x.c
++ M drivers/video/s3c/s3cfb_lts222qv.c
++ M drivers/video/s3c/s3cfb_spi.c
++
++dev-3-0-3: Jongpill Lee
++ - Gerneric driver support for RTC
++
++ Modified Files:
++
++ M arch/arm/mach-s3c2410/mach-smdk2410.c
++ M arch/arm/mach-s3c2412/mach-smdk2413.c
++ M arch/arm/mach-s3c2416/mach-smdk2416.c
++ M arch/arm/mach-s3c2440/mach-smdk2440.c
++ M arch/arm/mach-s3c2443/mach-smdk2443.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M drivers/rtc/rtc-s3c.c
++ M include/asm-arm/plat-s3c/regs-rtc.h
++ M drivers/video/s3c/s5pfb_fimd5x.c
++ M include/asm-arm/arch-s3c2410/gpio.h
++ M include/asm-arm/arch-s3c2410/hardware.h
++ M include/asm-arm/arch-s3c2410/regs-gpio.h
++ M include/asm-arm/plat-s5p/regs-gpio.h
++ M sound/soc/s3c24xx/s3c-i2s.c
++ M sound/soc/s3c24xx/s3c6410-i2s-v32.c
++ M sound/soc/s3c24xx/s3c6410-i2s-v40.c
++ M sound/soc/s3c24xx/s3c64xx-ac97.c
++ M sound/soc/s3c24xx/smdk6410_wm8580.c
++
++dev-3-0-4: Ilho Lee
++ - SDIO supported
++
++ Modified Files:
++ M drivers/mmc/core/core.c
++ M drivers/mmc/host/s3c-hsmmc.c
++
++dev-3-0-5: Ilho Lee
++ - Physical memory interfaces(/dev/mem) for S3C added
++
++ Modified Files:
++ M drivers/char/Makefile
++ M drivers/char/Kconfig
++
++ Added Files:
++ M drivers/char/s3c_mem.c
++ M drivers/char/s3c_mem.h
++
++dev-3-0-6: Jongpill lee
++ - Change pwm location from drivers/pwm to arch/arm/mach-s3c6410/pwm
++
++ Removed Files:
++ R drivers/pwm/Kconfig
++ R drivers/pwm/Makefile
++ R drivers/pwm/pwm-s3c2450.c
++ R drivers/pwm/pwm-s3c2450.h
++ R drivers/pwm/pwm-s3c6410.c
++ R drivers/pwm/pwm-s3c6410.h
++
++ Added Files:
++ A arch/arm/mach-s3c6410/pwm/Kconfig
++ A arch/arm/mach-s3c6410/pwm/Makefile
++ A arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c
++ A arch/arm/mach-s3c6410/pwm/pwm-s3c6410.h
++
++ Modified files
++ M arch/arm/Kconfig
++ M arch/arm/mach-s3c6410/Makefile
++ M drivers/Kconfig
++ M drivers/Makefile
++ M drivers/video/s3c/s3cfb.h
++
++dev-3-0-7: Jongpill Lee
++ - modify some code
++
++ MOdified Files:
++ M arch/arm/mach-s3c2416/mach-smdk2416.c
++ M arch/arm/mach-s3c2440/mach-smdk2440.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++
++dev-3-0-8: Jongpill Lee
++ -bug fixed for S3C24XX
++
++ Modofied Files:
++ M arch/arm/mach-s3c2410/mach-smdk2410.c
++ M arch/arm/mach-s3c2412/mach-smdk2413.c
++ M arch/arm/mach-s3c2443/mach-smdk2443.c
++
++dev-3-0-9: Jongpill Lee
++ - bug fixed RTC drivers
++
++ Modified Files:
++ M arch/arm/mach-s3c2410/mach-smdk2410.c
++ M arch/arm/mach-s3c2412/mach-smdk2413.c
++ M arch/arm/mach-s3c2440/mach-smdk2440.c
++ M arch/arm/mach-s3c2443/mach-smdk2443.c
++
++dev-3-0-10: Ilho Lee
++ - The ADC device driver moved.
++
++ Added Files:
++ A arch/arm/plat-s3c64xx/adc-s3c64xx.c
++ A arch/arm/plat-s3c24xx/adc-s3c24xx.c
++
++ Removed Files:
++ R drivers/char/s3c-adc.c
++
++rel-3-0-1: Jongpill Lee
++ - Offcial Release(08.11.07)
++
++dev-3-0-11: Byungjae Lee
++ - Moved USB OTG PHY init and USB Host Clock setting codes
++ to mach-s3c64xx.c for s3c64xx
++
++ Modified Files :
++ M arch/arm/mach-s3c6400/clock.c
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/clock.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++ M drivers/usb/host/ohci-s3c2410.c
++
++dev-3-0-12: Byungjae Lee
++ - Fixed compile error on smdk6400
++
++ Modified Files :
++ M arch/arm/mach-s3c6400/s3c6400.c
++ M include/asm-arm/plat-s3c24xx/devs.h
++
++dev-3-0-13: Jongpill Lee
++ - add LCD backlight for SMDK board
++
++ Added Files:
++ A drivers/video/backlight/smdk_bl.c
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/pm.c
++ M drivers/video/backlight/Kconfig
++ M drivers/video/backlight/Makefile
++ M drivers/video/s3c/s3cfb.h
++ M drivers/video/s3c/s3cfb_fimd4x.c
++
++dev-3-0-14: Jongpill Lee
++ - modified code for common driver
++
++ Modified Files
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/plat-s3c64xx/Makefile
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.c
++ M drivers/char/Makefile
++ M include/asm-arm/plat-s3c/regs-adc.h
++
++dev-3-0-15: Jongpill Lee
++ - Add new interface on ADC driver
++
++ Added Files:
++ A arch/arm/plat-s3c64xx/adc-s3c64xx.h
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.c
++ M include/asm-arm/plat-s3c/regs-adc.h
++
++dev-3-0-16: Jongpill Lee
++ - Modified for ADC driver
++
++ Modified Files:
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/plat-s3c24xx/devs.c
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.c
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.h
++ M include/asm-arm/plat-s3c/regs-adc.h
++
++dev-3-0-17: Jongpill Lee
++ - Add Error routine on probe function
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.c
++
++dev-3-0-18: Ilho Lee
++ - Touchscreen D/D changed.
++
++ Modified Files:
++ M arch/arm/plat-s3c24xx/devs.c
++ M drivers/input/touchscreen/s3c-ts.c
++
++ Added Files:
++ A include/asm-arm/plat-s3c/ts.h
++
++dev-3-0-19: Jongpill Lee
++ - Bug fixed on ADC driver
++
++ Modified Files:
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/plat-s3c24xx/devs.c
++ M drivers/char/Kconfig
++ M include/asm-arm/plat-s3c/regs-adc.h
++
++dev-3-0-20: Jongpill Lee
++ - Recommit this files
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.c
++
++dev-3-0-21: Jongpill Lee
++ - moved header file for adc and modified for ts
++
++ Added Files:
++ A include/asm-arm/plat-s3c/adc.h
++
++ Modified Files:
++ M arch/arm/mach-s3c6400/mach-smdk6400.c
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.c
++ M include/asm-arm/plat-s3c/regs-adc.h
++
++dev-3-0-22: Jongpill Lee
++ - Added adc function for s3c2416 and s3c2450
++
++ Modofied Files:
++ M arch/arm/mach-s3c2416/mach-smdk2416.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++
++rel-3-0-2: Kyoungil Kim
++ - Offcial Release(08.11.28)
++
++
++dev-3-0-23: Ilho Lee
++ - /dev/mem interface D/D changed.
++
++ Modofied Files:
++ M drivers/char/s3c_mem.c
++ M drivers/char/s3c_mem.h
++
++dev-3-0-24: Ilho Lee
++ - 2D -> G2D renamed.
++
++ Modofied Files:
++ M arch/arm/plat-s3c24xx/devs.c
++ M include/asm-arm/plat-s3c24xx/devs.h
++
++
++dev-3-0-25: Jonghun Han
++ - Added FIMD function(fb release)
++
++ Modified Files:
++ M drivers/video/s3c/s3cfb.c
++ M drivers/video/s3c/s3cfb.h
++ M drivers/video/s3c/s3cfb_fimd4x.c
++
++dev-3-0-26: Jinsung Yang
++ - Patch for s3c gpio routine
++
++ Modified files:
++ M arch/arm/plat-s3c24xx/gpio.c
++
++rel-3-0-3: Jinsung Yang
++ - Official Release (08.12.09)
++
++dev-3-0-27: Jinsung Yang
++ - Multi-channel i2c driver support for s3c64xx
++
++ Added files:
++ A drivers/i2c/busses/i2c-s3c64xx.c
++
++ Modified files:
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M arch/arm/plat-s3c24xx/devs.c
++ M drivers/i2c/busses/Kconfig
++ M drivers/i2c/busses/Makefile
++ M include/asm-arm/arch-s3c2410/irqs.h
++ M include/asm-arm/arch-s3c2410/map.h
++ M include/asm-arm/arch-s3c2410/regs-gpio.h
++ M include/asm-arm/plat-s3c/iic.h
++ M include/asm-arm/plat-s3c/regs-iic.h
++
++dev-3-0-28: jongpill Lee
++ - Added initial time setting function
++
++ Modified Files:
++ M drivers/rtc/rtc-s3c.c
++
++dev-3-0-29: Jongpill Lee
++ - Patch for Break detection
++
++ Modofied Files:
++ M drivers/serial/s3c6400.c
++
++dev-3-0-30: Jongpill Lee
++ - Remove not useable files
++
++ Remove Files:
++ R arch/arm/mach-s3c6410/pm-s3c6410.c
++ R arch/arm/mach-s3c6410/pm-s3c6410.h
++ Modified Files:
++ M arch/arm/plat-s3c64xx/pm.c
++
++dev-3-0-31: Jongpill Lee
++ - bug fixed about RTC on SMDK6410
++
++ Modified Files:
++ M drivers/rtc/rtc-s3c.c
++
++dev-3-0-32: Jongpill Lee
++ - Remove dvfs file to arch/arm/plat-s3cxxxx
++
++ Added Files:
++ A arch/arm/plat-s3c24xx/s3c24xx-dvfs.c
++ A arch/arm/plat-s3c24xx/s3c24xx-dvfs.h
++ A arch/arm/plat-s3c64xx/s3c64xx-dvfs.c
++ A arch/arm/plat-s3c64xx/s3c64xx-dvfs.h
++
++ Removed Files:
++ R drivers/char/s3c-dvfs/Kconfig
++ R drivers/char/s3c-dvfs/Makefile
++ R drivers/char/s3c-dvfs/s3c-dvfs.c
++ R drivers/char/s3c-dvfs/s3c-dvfs.h
++
++ Modified Files:
++ M arch/arm/plat-s3c24xx/Kconfig
++ M arch/arm/plat-s3c24xx/Makefile
++ M arch/arm/plat-s3c64xx/Makefile
++
++
++dev-3-0-33: Jongpill Lee
++ - Bug fixed on DVFS
++
++ Modified Files:
++ M drivers/char/Makefile
++ M kernel/power/Kconfig
++
++rel-3-0-4: Kyoungil Kim
++ - Offcial Release(08.12.24)
++
++dev-3-0-34: Jongpill Lee
++ - Support CPU FREQ Driver on SMDK64XX
++
++ Added Files:
++ A arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
++
++ Modified Files:
++ M arch/arm/Kconfig
++ M arch/arm/plat-s3c64xx/Makefile
++ M arch/arm/plat-s3c64xx/clock.c
++
++dev-3-0-35: Jongpill Lee
++ - Bug fixed on CPU FREQ Driver
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/clock.c
++
++dev-3-0-36: Jongpill Lee
++ - Bug Fixed on APM
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/pm.c
++ M drivers/media/video/s3c_camera_driver.c
++ M include/asm-arm/plat-s3c24xx/pm.h
++
++dev-3-0-37: Jongpill Lee
++ - Modified ADc driver for dual channel
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/adc-s3c64xx.c
++
++dev-3-0-38: Byungjae Lee
++ - Improved SMDK6410 USB OTG Host role for mass storage detection
++
++ Modified files:
++ M drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c
++
++dev-3-0-39: Jongpill Lee
++ - Bug fixed on ADC
++
++ Modified Files:
++ M arch/arm/mach-s3c2416/mach-smdk2416.c
++ M arch/arm/mach-s3c2450/mach-smdk2450.c
++
++dev-3-0-40: Byungjae Lee
++ - Bug fixed SMDK6410 USB OTG Host role for mass storage detection
++
++ Modified files:
++ M drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c
++ M drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c
++ M drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h
++
++dev-3-0-41: Kyoungil Kim
++ - Modified SYS Clock SYNC, ASYNC check bit
++
++ Modified files:
++ M arch/arm/mach-s3c6410/clock.c
++
++dev-3-0-42: Byungjae Lee
++ - Support USB OTG device role module
++ called 's3c-udc-otg-hs.ko' for SMDK6410
++
++ Modified files:
++ M arch/arm/mach-s3c6410/mach-smdk6410.c
++ M drivers/usb/gadget/Kconfig
++ M drivers/usb/gadget/Makefile
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++
++dev-3-0-43: Byungjae Lee
++ - Support Ethernet Gadget(CDC, RNDIS) on DMA mode
++ Seperate files for DMA and Salve mode
++
++ Modified files:
++ M drivers/usb/gadget/Kconfig
++ M drivers/usb/gadget/epautoconf.c
++ M drivers/usb/gadget/ether.c
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++ M drivers/usb/gadget/s3c-udc.h
++ M include/asm-arm/arch-s3c2410/regs-usb-otg-hs.h
++ Added files:
++ A drivers/usb/gadget/s3c-udc-otg-xfer-dma.c
++ A drivers/usb/gadget/s3c-udc-otg-xfer-slave.c
++
++dev-3-0-44: Byungjae Lee
++ - Modified SMDK6410 OTG Device role driver
++ to move comman function to s3c-udc-otg-hs.c
++
++ Modified files:
++ M drivers/usb/gadget/s3c-udc-otg-hs.c
++ M drivers/usb/gadget/s3c-udc-otg-xfer-dma.c
++ M drivers/usb/gadget/s3c-udc-otg-xfer-slave.c
++
++dev-3-0-45: Jongpill Lee
++ - Add DVS on cpufreq driver
++
++ Added files:
++ A arch/arm/plat-s3c64xx/ltc3714.c
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/Makefile
++ M arch/arm/plat-s3c64xx/clock.c
++ M arch/arm/plat-s3c64xx/pm.c
++ M arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
++ M arch/arm/plat-s3c64xx/s3c64xx-dvfs.c
++
++dev-3-0-46: Jongpill Lee
++ - Bug fixed on ltc3714.c
++
++ Modified Files:
++ M arch/arm/plat-s3c64xx/ltc3714.c
++
++rel-3-0-5: Kyoungil Kim
++ - Offcial Release(09.02.03)
++
+diff --git a/Makefile b/Makefile
+index 5023d04..21bd152 100644
+--- a/Makefile
++++ b/Makefile
+@@ -2,6 +2,9 @@ VERSION = 2
+ PATCHLEVEL = 6
+ SUBLEVEL = 24
+ EXTRAVERSION = .7
++EXTRAVERSION += $(shell echo ''; \
++ sed -n '/[dr][e][vl]-*[0-9]-*[0-9]-*[0-9]/p' Changelog | \
++ awk 'BEGIN {FS=":"} {last=$$1} END {print last}')
+ NAME = Err Metey! A Heury Beelge-a Ret!
+
+ # *DOCUMENTATION*
+@@ -189,9 +192,11 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
+ # Alternatively CROSS_COMPILE can be set in the environment.
+ # Default value for CROSS_COMPILE is not to prefix executables
+ # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
+-export KBUILD_BUILDHOST := $(SUBARCH)
+-ARCH ?= mips
+-CROSS_COMPILE ?=
++
++ARCH := arm
++CROSS_COMPILE := $(shell if [ -f .cross_compile ]; then \
++ cat .cross_compile; \
++ fi)
+
+ # Architecture as present in compile.h
+ UTS_MACHINE := $(ARCH)
+@@ -552,10 +557,10 @@ ifneq ($(KCFLAGS),)
+ endif
+
+ # Use --build-id when available.
+-LDFLAGS_BUILD_ID = $(patsubst -Wl$(comma)%,%,\
+- $(call ld-option, -Wl$(comma)--build-id,))
+-LDFLAGS_MODULE += $(LDFLAGS_BUILD_ID)
+-LDFLAGS_vmlinux += $(LDFLAGS_BUILD_ID)
++#LDFLAGS_BUILD_ID = $(patsubst -Wl$(comma)%,%,\
++# $(call ld-option, -Wl$(comma)--build-id,))
++#LDFLAGS_MODULE += $(LDFLAGS_BUILD_ID)
++#LDFLAGS_vmlinux += $(LDFLAGS_BUILD_ID)
+
+ # Default kernel image to build when no specific target is given.
+ # KBUILD_IMAGE may be overruled on the command line or
+diff --git a/RELEASENOTE b/RELEASENOTE
+new file mode 100644
+index 0000000..f891fb8
+--- /dev/null
++++ b/RELEASENOTE
+@@ -0,0 +1,130 @@
++
++*****************************************************************
++* *
++* Release Note for Samsung Linux Kernel *
++* *
++*****************************************************************
++
++Confidential Proprietary of Samsung Electronics Co., Ltd
++Copyright (c) 2008 Samsung Electronics, Inc. All Rights Reserved
++
++==================================================================
++* Important Notice
++==================================================================
++The information in this publication has been carefully checked and is
++believed to be entirely accurate at the time of publication.
++Samsung assumes no responsibility, however, for possible errors or
++omissions, or for any consequences resulting from the use of
++the information contained herein.
++
++Samsung reserves the right to make changes in its products or
++product specifications with the intent to improve function or
++design at any time and without notice and is not required to
++update this documentation to reflect such changes.
++
++This publication does not convey to a purchaser of semiconductor
++devices described herein any license under the patent rights of
++Samsung or others.
++
++Samsung makes no warranty, representation, or guarantee regarding
++the suitability of its products for any particular purpose,
++nor does Samsung assume any liability arising out of the application or
++use of any product or circuit and specifically disclaims any and
++all liability, including without limitation any consequential or
++incidental damages.
++
++"Typical" parameters can and do vary in different applications.
++All operating parameters, including "Typicals" must be validated for
++each customer application by the customer's technical experts.
++
++Samsung products are not designed, intended, or authorized for
++use as components in systems intended for surgical implant into the body,
++for other applications intended to support or sustain life, or for
++any other application in which the failure of the Samsung product
++could create a situation where personal injury or death may occur.
++
++Should the Buyer purchase or use a Samsung product for any such
++unintended or unauthorized application, the Buyer shall indemnify and
++hold Samsung and its officers, employees, subsidiaries, affiliates, and
++distributors harmless against all claims, costs, damages, expenses, and
++reasonable attorney fees arising out of, either directly or indirectly,
++any claim of personal injury or death that may be associated with such
++unintended or unauthorized use, even if such claim alleges that
++Samsung was negligent regarding the design or manufacture of said product
++
++Copyright (c) 2007-2008 Samsung Electronics Co.,Ltd.
++All rights reserved. No part of this publication may be reproduced,
++stored in a retrieval system, or transmitted in any form or by any means,
++electric or mechanical, by photocopying, recording, or otherwise, without
++the prior written consent of Samsung Electronics Co.,Ltd.
++
++Samsung Electronics Co., Ltd.
++San #24 Nongseo-Dong, Giheung-Gu
++Yongin-City Gyeonggi-Do, Korea
++446-711
++
++Home Page: http://www.samsungsemi.com/
++E-Mail: mobilesol.cs@samsung.com
++
++Printed in the Republic of Korea
++
++
++==================================================================
++* Basic Information
++==================================================================
++Kernel Version: 2.6.24
++Base Kernel: 2.6.24.2 from kernel.org
++Package Name: s3c-linux-2.6.24
++Latest Release: rel-3-0-1 (2008-11-07)
++Latest Tarball: s3c-linux-2.6.24_rel-3-0-1_081107.tar.bz2
++
++
++==================================================================
++* Revision History
++==================================================================
++Rev Date Description of Change
++--------- ---------- ----------------------------------
++rel-2-2-5 2008-10-04 WM8990 support
++rel-2-2-6 2008-10-27 2 Ch I2S support
++rel-3-0-1 2008-11-07 G3D changes
++
++
++==================================================================
++* rel-3-0-1
++==================================================================
++* What's New?
++ - G3D device driver removed from built-in source
++ - Physical memory management interface support for G3D driver
++ - DMA mode for S3C6410 File-backed storage gadget support
++ - Save and Restore function support for Power Management
++
++* Fixes made in this update
++ -
++
++* Known Issues
++ -
++
++==================================================================
++* rel-2-2-6
++==================================================================
++* What's New?
++ - 2 Ch. I2S support for S3C6410
++
++* Fixes made in this update
++ -
++
++* Known Issues
++ -
++
++==================================================================
++* rel-2-2-5
++==================================================================
++* What's New?
++ - Non-multichannel I2S (I2S0) support for S3C6410
++ - I2S wm8990 codec support for S3C6410
++
++* Fixes made in this update
++ -
++
++* Known Issues
++ -
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index a04f507..03b1918 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -370,8 +370,10 @@ config ARCH_SA1100
+ Support for StrongARM 11x0 based boards.
+
+ config ARCH_S3C2410
+- bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
++ bool "Samsung S3C24xx, S3C64xx"
+ select GENERIC_GPIO
++ select ISA
++
+ help
+ Samsung S3C2410X CPU based systems, such as the Simtec Electronics
+ BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
+@@ -442,6 +444,8 @@ source "arch/arm/mach-omap1/Kconfig"
+ source "arch/arm/mach-omap2/Kconfig"
+
+ source "arch/arm/plat-s3c24xx/Kconfig"
++source "arch/arm/plat-s3c64xx/Kconfig"
++source "arch/arm/plat-s5pc1xx/Kconfig"
+ source "arch/arm/plat-s3c/Kconfig"
+
+ if ARCH_S3C2410
+@@ -451,6 +455,11 @@ source "arch/arm/mach-s3c2412/Kconfig"
+ source "arch/arm/mach-s3c2440/Kconfig"
+ source "arch/arm/mach-s3c2442/Kconfig"
+ source "arch/arm/mach-s3c2443/Kconfig"
++source "arch/arm/mach-s3c2450/Kconfig"
++source "arch/arm/mach-s3c2416/Kconfig"
++source "arch/arm/mach-s3c6400/Kconfig"
++source "arch/arm/mach-s3c6410/Kconfig"
++source "arch/arm/mach-s5pc100/Kconfig"
+ endif
+
+ source "arch/arm/mach-lh7a40x/Kconfig"
+@@ -716,7 +725,7 @@ config LEDS
+ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
+ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
+ ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
+- ARCH_KS8695
++ ARCH_KS8695 || MACH_SMDK6400 || MACH_SMDK6410 || MACH_SMDK6430
+ help
+ If you say Y here, the LEDs on your machine will be used
+ to provide useful information about your current system status.
+@@ -731,7 +740,7 @@ config LEDS
+ config LEDS_TIMER
+ bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
+ OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
+- || MACH_OMAP_PERSEUS2
++ || MACH_OMAP_PERSEUS2 || MACH_SMDK6400 || MACH_SMDK6410 || MACH_SMDK6430
+ depends on LEDS
+ depends on !GENERIC_CLOCKEVENTS
+ default y if ARCH_EBSA110
+@@ -750,7 +759,7 @@ config LEDS_CPU
+ bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
+ !ARCH_OMAP) \
+ || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
+- || MACH_OMAP_PERSEUS2
++ || MACH_OMAP_PERSEUS2 || MACH_SMDK6400 || MACH_SMDK6410 || MACH_SMDK6430
+ depends on LEDS
+ help
+ If you say Y here, the red LED will be used to give a good real
+@@ -867,7 +876,7 @@ config KEXEC
+
+ endmenu
+
+-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX )
++if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || CPU_S3C6410)
+
+ menu "CPU Frequency scaling"
+
+@@ -1070,6 +1079,8 @@ source "drivers/leds/Kconfig"
+
+ source "drivers/rtc/Kconfig"
+
++source "arch/arm/mach-s3c6410/pwm/Kconfig"
++
+ source "drivers/dma/Kconfig"
+
+ source "drivers/dca/Kconfig"
+diff --git a/arch/arm/Makefile b/arch/arm/Makefile
+index 35e56c9..d19cd22 100644
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -177,6 +177,11 @@ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2412/
+ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2440/
+ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2442/
+ core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2443/
++core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2450/
++core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c2416/
++core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c6400/
++core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s3c6410/
++core-$(CONFIG_ARCH_S3C2410) += arch/arm/mach-s5pc100/
+ core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/
+ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ)
+ core-$(CONFIG_VFP) += arch/arm/vfp/
+@@ -184,7 +189,9 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
+ # If we have a common platform directory, then include it in the build.
+ core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
+ core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
+-core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
++core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
++core-$(CONFIG_PLAT_S3C64XX) += arch/arm/plat-s3c64xx/
++core-$(CONFIG_PLAT_S5PC1XX) += arch/arm/plat-s5pc1xx/
+ core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/
+
+ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
+diff --git a/arch/arm/boot/rootfs.cpio.gz b/arch/arm/boot/rootfs.cpio.gz
+new file mode 100644
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+
+diff --git a/arch/arm/configs/fpgac100_defconfig b/arch/arm/configs/fpgac100_defconfig
+new file mode 100644
+index 0000000..1cb1f8a
+--- /dev/null
++++ b/arch/arm/configs/fpgac100_defconfig
+@@ -0,0 +1,936 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Wed Oct 15 14:38:38 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S5PC1XX=y
++CONFIG_S5PC1XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_SMDK6430 is not set
++
++#
++# S5PC100 Machines
++#
++CONFIG_MACH_SMDKC100=y
++CONFIG_CPU_S5PC100=y
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_HAS_TLS_REG=y
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC0,115200 init=/linuxrc"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++# CONFIG_MTD is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MISC_DEVICES is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_NETDEVICES is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S5PC100=y
++CONFIG_SERIAL_S5PC1XX_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++# CONFIG_I2C is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++# CONFIG_WATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTE480WV is not set
++CONFIG_FB_S3C_LTV350QV=y
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_LOGO_LINUX_CLUT224=y
++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set
++
++#
++# G3D Support
++#
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++# CONFIG_HID_SUPPORT is not set
++# CONFIG_USB_SUPPORT is not set
++# CONFIG_MMC is not set
++# CONFIG_NEW_LEDS is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# SPI RTC drivers
++#
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_S3C is not set
++
++#
++# Pulse Width Modulation Timer
++#
++# CONFIG_PWM is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2416mtd_defconfig b/arch/arm/configs/smdk2416mtd_defconfig
+new file mode 100644
+index 0000000..55ce4ce
+--- /dev/null
++++ b/arch/arm/configs/smdk2416mtd_defconfig
+@@ -0,0 +1,1447 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Mon Apr 7 10:09:55 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++CONFIG_CPU_S3C2416=y
++CONFIG_S3C2416_DMA=y
++
++#
++# S3C2416 Machines
++#
++CONFIG_MACH_SMDK2416=y
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++# CONFIG_CPU_ARM920T is not set
++CONFIG_CPU_ARM926T=y
++CONFIG_CPU_32v5=y
++CONFIG_CPU_ABRT_EV5TJ=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++# CONFIG_MMC_S3C is not set
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2416nfs_defconfig b/arch/arm/configs/smdk2416nfs_defconfig
+new file mode 100644
+index 0000000..d41ff30
+--- /dev/null
++++ b/arch/arm/configs/smdk2416nfs_defconfig
+@@ -0,0 +1,1397 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Fri Apr 4 13:58:59 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++CONFIG_CPU_S3C2416=y
++CONFIG_S3C2416_DMA=y
++
++#
++# S3C2416 Machines
++#
++CONFIG_MACH_SMDK2416=y
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++# CONFIG_CPU_ARM920T is not set
++
++#
++# Processor Features
++#
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="nfsroot=12.23.106.52:/opt/small_root_eabi ip=192.168.0.20:12.23.106.52:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++# CONFIG_MMC is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++# CONFIG_NLS_CODEPAGE_437 is not set
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++# CONFIG_NLS_ISO8859_1 is not set
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2416ramdisk_defconfig b/arch/arm/configs/smdk2416ramdisk_defconfig
+new file mode 100644
+index 0000000..4ec53a8
+--- /dev/null
++++ b/arch/arm/configs/smdk2416ramdisk_defconfig
+@@ -0,0 +1,1447 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Mon Apr 7 10:09:55 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++CONFIG_CPU_S3C2416=y
++CONFIG_S3C2416_DMA=y
++
++#
++# S3C2416 Machines
++#
++CONFIG_MACH_SMDK2416=y
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++# CONFIG_CPU_ARM920T is not set
++CONFIG_CPU_ARM926T=y
++CONFIG_CPU_32v5=y
++CONFIG_CPU_ABRT_EV5TJ=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x30800000,8M console=ttySAC0,115200 init=/linuxrc"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++# CONFIG_MMC_S3C is not set
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2443mtd_defconfig b/arch/arm/configs/smdk2443mtd_defconfig
+new file mode 100644
+index 0000000..280f3f0
+--- /dev/null
++++ b/arch/arm/configs/smdk2443mtd_defconfig
+@@ -0,0 +1,1439 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Tue Mar 18 18:12:43 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++CONFIG_CPU_S3C2443=y
++CONFIG_S3C2443_DMA=y
++
++#
++# S3C2443 Machines
++#
++CONFIG_MACH_SMDK2443=y
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_ARM920T=y
++CONFIG_CPU_32v4T=y
++CONFIG_CPU_ABRT_EV4T=y
++CONFIG_CPU_CACHE_V4WT=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++CONFIG_DM9000=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_LOGO_LINUX_CLUT224=y
++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++# CONFIG_MMC_S3C is not set
++CONFIG_HSMMC_S3C=y
++CONFIG_USE_MMC_AS_ROOT=y
++CONFIG_HSMMC_S3C_IRQ_WORKAROUND=y
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2443nfs_defconfig b/arch/arm/configs/smdk2443nfs_defconfig
+new file mode 100644
+index 0000000..fe2e93a
+--- /dev/null
++++ b/arch/arm/configs/smdk2443nfs_defconfig
+@@ -0,0 +1,1400 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Tue Feb 26 09:15:10 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++CONFIG_CPU_S3C2443=y
++CONFIG_S3C2443_DMA=y
++
++#
++# S3C2443 Machines
++#
++CONFIG_MACH_SMDK2443=y
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_ARM920T=y
++CONFIG_CPU_32v4T=y
++CONFIG_CPU_ABRT_EV4T=y
++CONFIG_CPU_CACHE_V4WT=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="noinitrd root=/dev/nfs rw nfsroot=192.168.0.10:/tftpboot/rootfs/ ip=192.168.0.20:192.168.0.10:192.168.0.1:255.255.255.0::eth0:off init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++CONFIG_DM9000=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++# CONFIG_MMC is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++# CONFIG_NLS_CODEPAGE_437 is not set
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++# CONFIG_NLS_ISO8859_1 is not set
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2450mtd_defconfig b/arch/arm/configs/smdk2450mtd_defconfig
+new file mode 100644
+index 0000000..9f50dea
+--- /dev/null
++++ b/arch/arm/configs/smdk2450mtd_defconfig
+@@ -0,0 +1,1495 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Wed Apr 2 13:49:45 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++CONFIG_CPU_S3C2450=y
++CONFIG_S3C2450_DMA=y
++
++#
++# S3C2450 Machines
++#
++CONFIG_MACH_SMDK2450=y
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++# CONFIG_CPU_ARM920T is not set
++CONFIG_CPU_ARM926T=y
++CONFIG_CPU_32v5=y
++CONFIG_CPU_ABRT_EV5TJ=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC=y
++
++#
++# SoC Audio for the Atmel AT91
++#
++
++#
++# SoC Audio for the Intel PXA2xx
++#
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C_SOC=y
++# CONFIG_SND_S3C24XX_SOC_SMDK2450_WM9713 is not set
++CONFIG_SND_S3C2450_SOC_I2S=y
++CONFIG_SND_SOC_I2S_V40=y
++CONFIG_SND_S3C24XX_SOC_SMDK2450_WM8580=y
++# CONFIG_SND_S3C24XX_SOC_SMDK2450_WM8753 is not set
++CONFIG_SND_SOC_WM8580=y
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++# CONFIG_MMC_S3C is not set
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2450nfs_defconfig b/arch/arm/configs/smdk2450nfs_defconfig
+new file mode 100644
+index 0000000..c376572
+--- /dev/null
++++ b/arch/arm/configs/smdk2450nfs_defconfig
+@@ -0,0 +1,1461 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Tue Apr 1 15:30:55 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++CONFIG_CPU_S3C2450=y
++CONFIG_S3C2450_DMA=y
++
++#
++# S3C2450 Machines
++#
++CONFIG_MACH_SMDK2450=y
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++# CONFIG_CPU_ARM920T is not set
++CONFIG_CPU_ARM926T=y
++CONFIG_CPU_32v5=y
++CONFIG_CPU_ABRT_EV5TJ=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="nfsroot=12.23.106.52:/opt/small_root_eabi ip=192.168.0.20:12.23.106.52:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC=y
++
++#
++# SoC Audio for the Atmel AT91
++#
++
++#
++# SoC Audio for the Intel PXA2xx
++#
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C_SOC=y
++# CONFIG_SND_S3C24XX_SOC_SMDK2450_WM9713 is not set
++CONFIG_SND_S3C2450_SOC_I2S=y
++CONFIG_SND_SOC_I2S_V40=y
++CONFIG_SND_S3C24XX_SOC_SMDK2450_WM8580=y
++# CONFIG_SND_S3C24XX_SOC_SMDK2450_WM8753 is not set
++CONFIG_SND_SOC_WM8580=y
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++# CONFIG_MMC is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++# CONFIG_NLS_CODEPAGE_437 is not set
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++# CONFIG_NLS_ISO8859_1 is not set
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk2450ramdisk_defconfig b/arch/arm/configs/smdk2450ramdisk_defconfig
+new file mode 100644
+index 0000000..233daa2
+--- /dev/null
++++ b/arch/arm/configs/smdk2450ramdisk_defconfig
+@@ -0,0 +1,1495 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Wed Apr 2 13:49:45 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C24XX=y
++CONFIG_CPU_S3C244X=y
++CONFIG_S3C2410_DMA=y
++# CONFIG_S3C2410_DMA_DEBUG is not set
++CONFIG_PLAT_S3C=y
++CONFIG_CPU_LLSERIAL_S3C2410=y
++CONFIG_CPU_LLSERIAL_S3C2440=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++CONFIG_CPU_S3C2410=y
++CONFIG_CPU_S3C2410_DMA=y
++CONFIG_S3C2410_PM=y
++CONFIG_S3C2410_GPIO=y
++CONFIG_S3C2410_CLOCK=y
++
++#
++# S3C2410 Machines
++#
++CONFIG_ARCH_SMDK2410=y
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++CONFIG_CPU_S3C2440=y
++CONFIG_S3C2440_DMA=y
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++CONFIG_ARCH_S3C2440=y
++# CONFIG_MACH_NEXCODER_2440 is not set
++CONFIG_SMDK2440_CPU2440=y
++
++#
++# S3C2442 Machines
++#
++# CONFIG_SMDK2440_CPU2442 is not set
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++CONFIG_CPU_S3C2450=y
++CONFIG_S3C2450_DMA=y
++
++#
++# S3C2450 Machines
++#
++CONFIG_MACH_SMDK2450=y
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++# CONFIG_CPU_ARM920T is not set
++CONFIG_CPU_ARM926T=y
++CONFIG_CPU_32v5=y
++CONFIG_CPU_ABRT_EV5TJ=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_COPY_V4WB=y
++CONFIG_CPU_TLB_V4WBI=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
++# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x30800000,8M console=ttySAC0,115200 init=/linuxrc"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++# CONFIG_APM_EMULATION is not set
++
++#
++# DVFS support
++#
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++CONFIG_ATA_OVER_ETH=m
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_S3C2410=y
++CONFIG_SERIAL_S3C2410_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=m
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC=y
++
++#
++# SoC Audio for the Atmel AT91
++#
++
++#
++# SoC Audio for the Intel PXA2xx
++#
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C_SOC=y
++# CONFIG_SND_S3C24XX_SOC_SMDK2450_WM9713 is not set
++CONFIG_SND_S3C2450_SOC_I2S=y
++CONFIG_SND_SOC_I2S_V40=y
++CONFIG_SND_S3C24XX_SOC_SMDK2450_WM8580=y
++# CONFIG_SND_S3C24XX_SOC_SMDK2450_WM8753 is not set
++CONFIG_SND_SOC_WM8580=y
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++# CONFIG_MMC_S3C is not set
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6400mtd_defconfig b/arch/arm/configs/smdk6400mtd_defconfig
+new file mode 100644
+index 0000000..bd056dc
+--- /dev/null
++++ b/arch/arm/configs/smdk6400mtd_defconfig
+@@ -0,0 +1,1423 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Mon Mar 17 09:02:58 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C6400 Machines
++#
++CONFIG_MACH_SMDK6400=y
++# CONFIG_S3C6400_PDFW is not set
++CONFIG_CPU_S3C6400=y
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++# CONFIG_MII is not set
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++CONFIG_HSMMC_S3C_IRQ_WORKAROUND=y
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6400nfs_defconfig b/arch/arm/configs/smdk6400nfs_defconfig
+new file mode 100644
+index 0000000..9ab1c31
+--- /dev/null
++++ b/arch/arm/configs/smdk6400nfs_defconfig
+@@ -0,0 +1,1384 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Tue Feb 26 10:39:03 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C6400 Machines
++#
++CONFIG_MACH_SMDK6400=y
++# CONFIG_S3C6400_PDFW is not set
++CONFIG_CPU_S3C6400=y
++
++#
++# S3C6410 Machines
++#
++# CONFIG_MACH_SMDK6410 is not set
++# CONFIG_MACH_FPGA6410 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="noinitrd root=/dev/nfs rw nfsroot=192.168.0.10:/tftpboot/rootfs/ ip=192.168.0.20:192.168.0.10:192.168.0.1:255.255.255.0::eth0:off init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++CONFIG_IDE=y
++CONFIG_BLK_DEV_IDE=y
++
++#
++# Please see Documentation/ide.txt for help/info on IDE drives
++#
++# CONFIG_BLK_DEV_IDE_SATA is not set
++CONFIG_BLK_DEV_IDEDISK=y
++# CONFIG_IDEDISK_MULTI_MODE is not set
++CONFIG_BLK_DEV_IDECD=y
++CONFIG_BLK_DEV_IDETAPE=m
++CONFIG_BLK_DEV_IDEFLOPPY=m
++# CONFIG_IDE_TASK_IOCTL is not set
++CONFIG_IDE_PROC_FS=y
++
++#
++# IDE chipset support/bugfixes
++#
++CONFIG_IDE_GENERIC=y
++# CONFIG_BLK_DEV_PLATFORM is not set
++# CONFIG_IDE_ARM is not set
++
++#
++# Other IDE chipsets support
++#
++
++#
++# Note: most of these also require special kernel boot parameters
++#
++# CONFIG_BLK_DEV_4DRIVES is not set
++# CONFIG_BLK_DEV_ALI14XX is not set
++# CONFIG_BLK_DEV_DTC2278 is not set
++# CONFIG_BLK_DEV_HT6560B is not set
++# CONFIG_BLK_DEV_QD65XX is not set
++# CONFIG_BLK_DEV_UMC8672 is not set
++# CONFIG_BLK_DEV_IDEDMA is not set
++CONFIG_IDE_ARCH_OBSOLETE_INIT=y
++# CONFIG_BLK_DEV_HD is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++# CONFIG_MII is not set
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++CONFIG_DAB=y
++# CONFIG_USB_DABUSB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTV350QV is not set
++CONFIG_FB_S3C_LTE480WV=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++# CONFIG_USB_HID is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++# CONFIG_MMC is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++# CONFIG_NLS_CODEPAGE_437 is not set
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++# CONFIG_NLS_ISO8859_1 is not set
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6410mtd_defconfig b/arch/arm/configs/smdk6410mtd_defconfig
+new file mode 100644
+index 0000000..c54c2b2
+--- /dev/null
++++ b/arch/arm/configs/smdk6410mtd_defconfig
+@@ -0,0 +1,1513 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Thu Aug 21 14:56:25 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++# CONFIG_MACH_SMDK6430 is not set
++# CONFIG_S3C6410_PDFW is not set
++CONFIG_CPU_S3C6410=y
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=y
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_AHA152X is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_IN2000 is not set
++# CONFIG_SCSI_DTC3280 is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_GENERIC_NCR5380 is not set
++# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
++# CONFIG_SCSI_NCR53C406A is not set
++# CONFIG_SCSI_PAS16 is not set
++# CONFIG_SCSI_PSI240I is not set
++# CONFIG_SCSI_QLOGIC_FAS is not set
++# CONFIG_SCSI_SYM53C416 is not set
++# CONFIG_SCSI_T128 is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYPAD_S3C is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++CONFIG_FB_S3C_LTE480WV=y
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# G3D Support
++#
++# CONFIG_G3D is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_AC97_CODEC=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# SPI devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++# CONFIG_SND_USB_CAIAQ is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_SOC=y
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C_SOC=y
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y
++CONFIG_SOUND_WM9713_INPUT_STREAM_LINE=y
++# CONFIG_SOUND_WM9713_INPUT_STREAM_MIC is not set
++CONFIG_SND_S3C6410_SOC_AC97=y
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_SOC_WM9713=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++# CONFIG_USB_HIDINPUT_POWERBOOK is not set
++# CONFIG_HID_FF is not set
++# CONFIG_USB_HIDDEV is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# Pulse Width Modulation Timer
++#
++# CONFIG_PWM is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6410nfs_defconfig b/arch/arm/configs/smdk6410nfs_defconfig
+new file mode 100644
+index 0000000..e822427
+--- /dev/null
++++ b/arch/arm/configs/smdk6410nfs_defconfig
+@@ -0,0 +1,1349 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Thu Aug 21 14:55:51 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++# CONFIG_MACH_SMDK6430 is not set
++# CONFIG_S3C6410_PDFW is not set
++CONFIG_CPU_S3C6410=y
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs rw nfsroot=12.23.106.154:/opt/small_root_eabi ip=192.168.0.20:12.23.106.154:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYPAD_S3C is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++# CONFIG_HS_SPI_S3C6410 is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++CONFIG_FB_S3C_LTE480WV=y
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# G3D Support
++#
++# CONFIG_G3D is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_AC97_CODEC=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# SPI devices
++#
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_SOC=y
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C_SOC=y
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y
++CONFIG_SOUND_WM9713_INPUT_STREAM_LINE=y
++# CONFIG_SOUND_WM9713_INPUT_STREAM_MIC is not set
++CONFIG_SND_S3C6410_SOC_AC97=y
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_SOC_WM9713=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_USB_SUPPORT is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# Pulse Width Modulation Timer
++#
++# CONFIG_PWM is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6410onenand_defconfig b/arch/arm/configs/smdk6410onenand_defconfig
+new file mode 100644
+index 0000000..ffa6d25
+--- /dev/null
++++ b/arch/arm/configs/smdk6410onenand_defconfig
+@@ -0,0 +1,1354 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Mon Oct 20 13:00:04 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++# CONFIG_MACH_SMDK6430 is not set
++# CONFIG_S3C6410_PDFW is not set
++CONFIG_CPU_S3C6410=y
++
++#
++# S5PC100 Machines
++#
++# CONFIG_MACH_SMDKC100 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mtdblock2 rw rootfstype=jffs2 init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++# CONFIG_MTD_NAND is not set
++CONFIG_MTD_ONENAND=y
++CONFIG_MTD_ONENAND_VERIFY_WRITE=y
++CONFIG_MTD_ONENAND_GENERIC=y
++# CONFIG_MTD_ONENAND_OTP is not set
++# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
++# CONFIG_MTD_ONENAND_SIM is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYPAD_S3C is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++CONFIG_TOUCHSCREEN_NEW=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++# CONFIG_HS_SPI_S3C6410 is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++CONFIG_FB_S3C_LTE480WV=y
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# G3D Support
++#
++# CONFIG_G3D is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_AC97_CODEC=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# SPI devices
++#
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_SOC=y
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C_SOC=y
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y
++CONFIG_SOUND_WM9713_INPUT_STREAM_LINE=y
++# CONFIG_SOUND_WM9713_INPUT_STREAM_MIC is not set
++CONFIG_SND_S3C6410_SOC_AC97=y
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_SOC_WM9713=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_USB_SUPPORT is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# Pulse Width Modulation Timer
++#
++# CONFIG_PWM is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++CONFIG_JFFS2_LZO=y
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_JFFS2_CMODE_NONE is not set
++CONFIG_JFFS2_CMODE_PRIORITY=y
++# CONFIG_JFFS2_CMODE_SIZE is not set
++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6410ramdisk_defconfig b/arch/arm/configs/smdk6410ramdisk_defconfig
+new file mode 100644
+index 0000000..4fc214e
+--- /dev/null
++++ b/arch/arm/configs/smdk6410ramdisk_defconfig
+@@ -0,0 +1,1513 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Thu Aug 21 14:56:25 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++# CONFIG_MACH_SMDK6430 is not set
++# CONFIG_S3C6410_PDFW is not set
++CONFIG_CPU_S3C6410=y
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x50800000,8M console=ttySAC0,115200 init=/linuxrc"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=y
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_AHA152X is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_IN2000 is not set
++# CONFIG_SCSI_DTC3280 is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_GENERIC_NCR5380 is not set
++# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
++# CONFIG_SCSI_NCR53C406A is not set
++# CONFIG_SCSI_PAS16 is not set
++# CONFIG_SCSI_PSI240I is not set
++# CONFIG_SCSI_QLOGIC_FAS is not set
++# CONFIG_SCSI_SYM53C416 is not set
++# CONFIG_SCSI_T128 is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++CONFIG_CS89x0=y
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYPAD_S3C is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++CONFIG_FB_S3C_LTE480WV=y
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# G3D Support
++#
++# CONFIG_G3D is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_AC97_CODEC=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# SPI devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++# CONFIG_SND_USB_CAIAQ is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_SOC=y
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C_SOC=y
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y
++CONFIG_SOUND_WM9713_INPUT_STREAM_LINE=y
++# CONFIG_SOUND_WM9713_INPUT_STREAM_MIC is not set
++CONFIG_SND_S3C6410_SOC_AC97=y
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_SOC_WM9713=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++# CONFIG_USB_HIDINPUT_POWERBOOK is not set
++# CONFIG_HID_FF is not set
++# CONFIG_USB_HIDDEV is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# Pulse Width Modulation Timer
++#
++# CONFIG_PWM is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6430mtd_defconfig b/arch/arm/configs/smdk6430mtd_defconfig
+new file mode 100644
+index 0000000..95a9a4d
+--- /dev/null
++++ b/arch/arm/configs/smdk6430mtd_defconfig
+@@ -0,0 +1,1521 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Thu Jul 31 10:40:33 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++CONFIG_MACH_SMDK6430=y
++# CONFIG_S3C6410_PDFW is not set
++CONFIG_CPU_S3C6410=y
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=y
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_AHA152X is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_IN2000 is not set
++# CONFIG_SCSI_DTC3280 is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_GENERIC_NCR5380 is not set
++# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
++# CONFIG_SCSI_NCR53C406A is not set
++# CONFIG_SCSI_PAS16 is not set
++# CONFIG_SCSI_PSI240I is not set
++# CONFIG_SCSI_QLOGIC_FAS is not set
++# CONFIG_SCSI_SYM53C416 is not set
++# CONFIG_SCSI_T128 is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYPAD_S3C is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++# CONFIG_HS_SPI_S3C6410 is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++CONFIG_FB_S3C_LTE480WV=y
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# G3D Support
++#
++# CONFIG_G3D is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_AC97_CODEC=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# SPI devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++# CONFIG_SND_USB_CAIAQ is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_SOC=y
++CONFIG_SND_S3C_SOC=y
++CONFIG_SND_S3C6410_SOC_AC97=y
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y
++CONFIG_SOUND_WM9713_INPUT_STREAM_LINE=y
++# CONFIG_SOUND_WM9713_INPUT_STREAM_MIC is not set
++CONFIG_SND_SOC_WM9713=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++# CONFIG_USB_HIDINPUT_POWERBOOK is not set
++# CONFIG_HID_FF is not set
++# CONFIG_USB_HIDDEV is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6430nfs_defconfig b/arch/arm/configs/smdk6430nfs_defconfig
+new file mode 100644
+index 0000000..cc725d9
+--- /dev/null
++++ b/arch/arm/configs/smdk6430nfs_defconfig
+@@ -0,0 +1,1332 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Mon Jun 30 15:41:57 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6430 Machines
++#
++CONFIG_MACH_SMDK6430=y
++CONFIG_MACH_SMDK6410=y
++CONFIG_CPU_S3C6410=y
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/nfs nfsroot=12.23.106.154:/opt/small_root_eabi ip=192.168.0.20:12.23.106.154:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++# CONFIG_SCSI_DMA is not set
++# CONFIG_SCSI_NETLINK is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYPAD_S3C is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++CONFIG_FB_S3C_LTE480WV=y
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_AC97_CODEC=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# SPI devices
++#
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_SOC=y
++CONFIG_SND_S3C_SOC=y
++CONFIG_SND_S3C6410_SOC_AC97=y
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y
++CONFIG_SOUND_WM9713_INPUT_STREAM_LINE=y
++# CONFIG_SOUND_WM9713_INPUT_STREAM_MIC is not set
++CONFIG_SND_SOC_WM9713=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++# CONFIG_USB_SUPPORT is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/smdk6430ramdisk_defconfig b/arch/arm/configs/smdk6430ramdisk_defconfig
+new file mode 100644
+index 0000000..73a4629
+--- /dev/null
++++ b/arch/arm/configs/smdk6430ramdisk_defconfig
+@@ -0,0 +1,1521 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.2
++# Thu Jul 31 10:40:33 2008
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=16
++# CONFIG_CGROUPS is not set
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_FAIR_USER_SCHED=y
++# CONFIG_FAIR_CGROUP_SCHED is not set
++CONFIG_SYSFS_DEPRECATED=y
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++# CONFIG_EMBEDDED is not set
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++# CONFIG_S3C_BOOT_ERROR_RESET is not set
++
++#
++# Power management
++#
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_SPLIT_ROOT_FILESYSTEM=y
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++CONFIG_MACH_SMDK6430=y
++# CONFIG_S3C6410_PDFW is not set
++CONFIG_CPU_S3C6410=y
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++# CONFIG_CPU_32v6K is not set
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_THUMB is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_PREEMPT is not set
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=200
++CONFIG_AEABI=y
++CONFIG_OABI_COMPAT=y
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x50800000,8M console=ttySAC0,115200 init=/linuxrc"
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_AOUT=y
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++# CONFIG_PM is not set
++CONFIG_SUSPEND_UP_POSSIBLE=y
++
++#
++# DVFS support
++#
++# CONFIG_DVFS is not set
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_PACKET is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++# CONFIG_INET_LRO is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++# CONFIG_CFG80211 is not set
++# CONFIG_WIRELESS_EXT is not set
++# CONFIG_MAC80211 is not set
++# CONFIG_IEEE80211 is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD_REDBOOT_PARTS=y
++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++CONFIG_MTD_ROM=y
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++# CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_DATAFLASH is not set
++# CONFIG_MTD_M25P80 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_S3C2410 is not set
++CONFIG_MTD_NAND_S3C=y
++# CONFIG_MTD_NAND_S3C_DEBUG is not set
++CONFIG_MTD_NO_ECC_WARNING=y
++CONFIG_MTD_NAND_S3C_HWECC=y
++CONFIG_S3C_LARGEPAGE_NAND=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_PARPORT=y
++# CONFIG_PARPORT_PC is not set
++# CONFIG_PARPORT_GSC is not set
++# CONFIG_PARPORT_AX88796 is not set
++CONFIG_PARPORT_1284=y
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=y
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=y
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_SCSI_AHA152X is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_IN2000 is not set
++# CONFIG_SCSI_DTC3280 is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_GENERIC_NCR5380 is not set
++# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
++# CONFIG_SCSI_NCR53C406A is not set
++# CONFIG_SCSI_PAS16 is not set
++# CONFIG_SCSI_PSI240I is not set
++# CONFIG_SCSI_QLOGIC_FAS is not set
++# CONFIG_SCSI_SYM53C416 is not set
++# CONFIG_SCSI_T128 is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
++CONFIG_SMC911X=y
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_B44 is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++CONFIG_NETDEV_1000=y
++CONFIG_NETDEV_10000=y
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_WAN is not set
++# CONFIG_PLIP is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=480
++CONFIG_INPUT_TSDEV_SCREEN_Y=640
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYPAD_S3C is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_LIFEBOOK=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_ADS7846 is not set
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_PARKBD is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_SERIAL_NONSTANDARD=y
++# CONFIG_COMPUTONE is not set
++# CONFIG_ROCKETPORT is not set
++# CONFIG_CYCLADES is not set
++# CONFIG_DIGIEPCA is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_MOXA_SMARTIO_NEW is not set
++# CONFIG_N_HDLC is not set
++# CONFIG_RISCOM8 is not set
++# CONFIG_SPECIALIX is not set
++# CONFIG_SX is not set
++# CONFIG_RIO is not set
++# CONFIG_STALDRV is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++# CONFIG_SERIAL_8250_FOURPORT is not set
++# CONFIG_SERIAL_8250_ACCENT is not set
++# CONFIG_SERIAL_8250_BOCA is not set
++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
++# CONFIG_SERIAL_8250_HUB6 is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++CONFIG_PRINTER=y
++# CONFIG_LP_CONSOLE is not set
++CONFIG_PPDEV=y
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++CONFIG_I2C_ALGOBIT=y
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C2410=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_EEPROM=m
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++CONFIG_SPI_BITBANG=m
++# CONFIG_SPI_BUTTERFLY is not set
++# CONFIG_SPI_LM70_LLP is not set
++CONFIG_SPI_S3C24XX=m
++CONFIG_SPI_S3C24XX_GPIO=m
++# CONFIG_HS_SPI_S3C6410 is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_AT25 is not set
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++CONFIG_HWMON=y
++CONFIG_HWMON_VID=m
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM70 is not set
++CONFIG_SENSORS_LM75=m
++# CONFIG_SENSORS_LM77 is not set
++CONFIG_SENSORS_LM78=m
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++CONFIG_SENSORS_LM85=m
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++CONFIG_FB_S3C_LTE480WV=y
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# G3D Support
++#
++# CONFIG_G3D is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_AC97_CODEC=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_MTS64 is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_PORTMAN2X4 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# SPI devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++# CONFIG_SND_USB_CAIAQ is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC_AC97_BUS=y
++CONFIG_SND_SOC=y
++CONFIG_SND_S3C_SOC=y
++CONFIG_SND_S3C6410_SOC_AC97=y
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y
++CONFIG_SOUND_WM9713_INPUT_STREAM_LINE=y
++# CONFIG_SOUND_WM9713_INPUT_STREAM_MIC is not set
++CONFIG_SND_SOC_WM9713=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++# CONFIG_HIDRAW is not set
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++# CONFIG_USB_HIDINPUT_POWERBOOK is not set
++# CONFIG_HID_FF is not set
++# CONFIG_USB_HIDDEV is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++# CONFIG_USB_USS720 is not set
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++# CONFIG_MMC_UNSAFE_RESUME is not set
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++# CONFIG_SDIO_UART is not set
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++# CONFIG_USE_MMC_AS_ROOT is not set
++# CONFIG_HSMMC_S3C_IRQ_WORKAROUND is not set
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++# CONFIG_MMC_SPI is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++CONFIG_LEDS_S3C24XX=m
++# CONFIG_LEDS_GPIO is not set
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++# CONFIG_RTC_DRV_RS5C348 is not set
++# CONFIG_RTC_DRV_MAX6902 is not set
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++CONFIG_ROMFS_FS=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_TMPFS_POSIX_ACL is not set
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++CONFIG_SOLARIS_X86_PARTITION=y
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_DETECT_SOFTLOCKUP=y
++CONFIG_SCHED_DEBUG=y
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_SLAB is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++CONFIG_DEBUG_MUTEXES=y
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_SG is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_SAMPLES is not set
++CONFIG_DEBUG_USER=y
++# CONFIG_DEBUG_ERRORS is not set
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++CONFIG_DEBUG_S3C_PORT=y
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++# CONFIG_CRYPTO is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
+index 33e6cc2..d452dbf 100644
+--- a/arch/arm/kernel/entry-common.S
++++ b/arch/arm/kernel/entry-common.S
+@@ -32,7 +32,9 @@ ret_fast_syscall:
+ @ fast_restore_user_regs
+ ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr
+ ldr lr, [sp, #S_OFF + S_PC]! @ get pc
++
+ msr spsr_cxsf, r1 @ save in spsr_svc
++
+ ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
+ mov r0, r0
+ add sp, sp, #S_FRAME_SIZE - S_PC
+@@ -71,11 +73,14 @@ no_work_pending:
+ @ slow_restore_user_regs
+ ldr r1, [sp, #S_PSR] @ get calling cpsr
+ ldr lr, [sp, #S_PC]! @ get pc
++
+ msr spsr_cxsf, r1 @ save in spsr_svc
++
+ ldmdb sp, {r0 - lr}^ @ get calling r1 - lr
+ mov r0, r0
+ add sp, sp, #S_FRAME_SIZE - S_PC
+ movs pc, lr @ return & move spsr_svc into cpsr
++
+
+ /*
+ * This is how we return from a fork.
+diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot
+index 7dab2a0..3facee4 100644
+--- a/arch/arm/mach-s3c2410/Makefile.boot
++++ b/arch/arm/mach-s3c2410/Makefile.boot
+@@ -1,3 +1,6 @@
+- zreladdr-y := 0x30008000
+-params_phys-y := 0x30000100
+-
++ zreladdr-$(CONFIG_PLAT_S3C24XX) := 0x30008000
++params_phys-$(CONFIG_PLAT_S3C24XX) := 0x30000100
++ zreladdr-$(CONFIG_PLAT_S3C64XX) := 0x50008000
++params_phys-$(CONFIG_PLAT_S3C64XX) := 0x50000100
++ zreladdr-$(CONFIG_PLAT_S5PC1XX) := 0x20008000
++params_phys-$(CONFIG_PLAT_S5PC1XX) := 0x20000100
+diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
+new file mode 100644
+index 0000000..f779e41
+--- /dev/null
++++ b/arch/arm/mach-s3c2416/Kconfig
+@@ -0,0 +1,28 @@
++# arch/arm/mach-s3c2416/Kconfig
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++config CPU_S3C2416
++ bool
++ depends on ARCH_S3C2410
++ select S3C2416_DMA if S3C2410_DMA
++ help
++ Support for the S3C2416 SoC from the S3C24XX line
++
++config S3C2416_DMA
++ bool
++ depends on CPU_S3C2416
++ help
++ Internal config node for S3C2416 DMA support
++
++menu "S3C2416 Machines"
++
++config MACH_SMDK2416
++ bool "SMDK2416"
++ select CPU_S3C2416
++ select MACH_SMDK
++ help
++ Say Y here if you are using an SMDK2416
++endmenu
+diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
+new file mode 100644
+index 0000000..1df4f5f
+--- /dev/null
++++ b/arch/arm/mach-s3c2416/Makefile
+@@ -0,0 +1,20 @@
++# arch/arm/mach-s3c2416/Makefile
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++obj-y :=
++obj-m :=
++obj-n :=
++obj- :=
++
++obj-$(CONFIG_CPU_S3C2416) += s3c2416.o
++obj-$(CONFIG_CPU_S3C2416) += ../mach-s3c2443/irq.o
++obj-$(CONFIG_CPU_S3C2416) += clock.o
++
++obj-$(CONFIG_S3C2416_DMA) += ../mach-s3c2443/dma.o
++
++# Machine support
++
++obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o
+diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
+new file mode 100644
+index 0000000..8f54c2a
+--- /dev/null
++++ b/arch/arm/mach-s3c2416/clock.c
+@@ -0,0 +1,1006 @@
++/* linux/arch/arm/mach-s3c2416/clock.c
++ *
++ * Copyright (c) 2007 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2416 Clock control support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/sysdev.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/serial_core.h>
++
++#include <asm/mach/map.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++
++#include <asm/plat-s3c24xx/s3c2416.h>
++#include <asm/plat-s3c24xx/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++/* We currently have to assume that the system is running
++ * from the XTPll input, and that all ***REFCLKs are being
++ * fed from it, as we cannot read the state of OM[4] from
++ * software.
++ *
++ * It would be possible for each board initialisation to
++ * set the correct muxing at initialisation
++*/
++
++static int s3c2416_clkcon_enable_h(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C2443_HCLKCON);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C2443_HCLKCON);
++
++ return 0;
++}
++
++static int s3c2416_clkcon_enable_p(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C2443_PCLKCON);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C2443_HCLKCON);
++
++ return 0;
++}
++
++static int s3c2416_clkcon_enable_s(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C2443_SCLKCON);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C2443_SCLKCON);
++
++ return 0;
++}
++
++static unsigned long s3c2416_roundrate_clksrc(struct clk *clk,
++ unsigned long rate,
++ unsigned int max)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ int div;
++
++ if (rate > parent_rate)
++ return parent_rate;
++
++ /* note, we remove the +/- 1 calculations as they cancel out */
++
++ div = (rate / parent_rate);
++
++ if (div < 1)
++ div = 1;
++ else if (div > max)
++ div = max;
++
++ return parent_rate / div;
++}
++
++static unsigned long s3c2416_roundrate_clksrc4(struct clk *clk,
++ unsigned long rate)
++{
++ return s3c2416_roundrate_clksrc(clk, rate, 4);
++}
++
++static unsigned long s3c2416_roundrate_clksrc16(struct clk *clk,
++ unsigned long rate)
++{
++ return s3c2416_roundrate_clksrc(clk, rate, 16);
++}
++
++static unsigned long s3c2416_roundrate_clksrc256(struct clk *clk,
++ unsigned long rate)
++{
++ return s3c2416_roundrate_clksrc(clk, rate, 256);
++}
++
++/* clock selections */
++
++/* CPU EXTCLK input */
++static struct clk clk_ext = {
++ .name = "ext",
++ .id = -1,
++};
++
++static struct clk clk_mpllref = {
++ .name = "mpllref",
++ .parent = &clk_xtal,
++ .id = -1,
++};
++
++#if 0
++static struct clk clk_mpll = {
++ .name = "mpll",
++ .parent = &clk_mpllref,
++ .id = -1,
++};
++#endif
++
++static struct clk clk_epllref;
++
++static struct clk clk_epll = {
++ .name = "epll",
++ .parent = &clk_epllref,
++ .id = -1,
++};
++
++static struct clk clk_i2s_ext = {
++ .name = "i2s-ext",
++ .id = -1,
++};
++
++static int s3c2416_setparent_epllref(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK;
++
++ if (parent == &clk_xtal)
++ clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL;
++ else if (parent == &clk_ext)
++ clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK;
++ else if (parent != &clk_mpllref)
++ return -EINVAL;
++
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++ clk->parent = parent;
++
++ return 0;
++}
++
++static struct clk clk_epllref = {
++ .name = "epllref",
++ .id = -1,
++ .set_parent = s3c2416_setparent_epllref,
++};
++
++static unsigned long s3c2416_getrate_mdivclk(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV0);
++
++ div &= S3C2443_CLKDIV0_EXTDIV_MASK;
++ div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
++
++ return parent_rate / (div + 1);
++}
++
++static struct clk clk_mdivclk = {
++ .name = "mdivclk",
++ .parent = &clk_mpllref,
++ .id = -1,
++ .get_rate = s3c2416_getrate_mdivclk,
++};
++
++
++static int s3c2416_setparent_msysclk(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL |
++ S3C2443_CLKSRC_EXTCLK_DIV);
++
++ if (parent == &clk_mpll)
++ clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL;
++ else if (parent == &clk_mdivclk)
++ clksrc |= S3C2443_CLKSRC_EXTCLK_DIV;
++ else if (parent != &clk_mpllref)
++ return -EINVAL;
++
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++ clk->parent = parent;
++
++ return 0;
++}
++
++static struct clk clk_msysclk = {
++ .name = "msysclk",
++ .parent = &clk_xtal,
++ .id = -1,
++ .set_parent = s3c2416_setparent_msysclk,
++};
++
++
++/* esysclk
++ *
++ * this is sourced from either the EPLL or the EPLLref clock
++*/
++
++static int s3c2416_setparent_esysclk(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ if (parent == &clk_epll)
++ clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL;
++ else if (parent == &clk_epllref)
++ clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL;
++ else
++ return -EINVAL;
++
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++ clk->parent = parent;
++
++ return 0;
++}
++
++static struct clk clk_esysclk = {
++ .name = "esysclk",
++ .parent = &clk_epll,
++ .id = -1,
++ .set_parent = s3c2416_setparent_esysclk,
++};
++
++/* uartclk
++ *
++ * UART baud-rate clock sourced from esysclk via a divisor
++*/
++
++static unsigned long s3c2416_getrate_uart(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_UARTDIV_MASK;
++ div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++
++static int s3c2416_setrate_uart(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2416_roundrate_clksrc16(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_uart = {
++ .name = "uartclk",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .get_rate = s3c2416_getrate_uart,
++ .set_rate = s3c2416_setrate_uart,
++ .round_rate = s3c2416_roundrate_clksrc16,
++};
++
++/* hsspi
++ *
++ * high-speed spi clock, sourced from esysclk
++*/
++
++static unsigned long s3c2416_getrate_hsspi(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_HSSPIDIV_MASK;
++ div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++
++static int s3c2416_setrate_hsspi(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2416_roundrate_clksrc4(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_hsspi = {
++ .name = "hsspi",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
++ .enable = s3c2416_clkcon_enable_s,
++ .get_rate = s3c2416_getrate_hsspi,
++ .set_rate = s3c2416_setrate_hsspi,
++ .round_rate = s3c2416_roundrate_clksrc4,
++};
++
++/* usbhost
++ *
++ * usb host bus-clock, usually 48MHz to provide USB bus clock timing
++*/
++
++static unsigned long s3c2416_getrate_usbhost(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK;
++ div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2416_setrate_usbhost(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2416_roundrate_clksrc4(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_usb_bus_host = {
++ .name = "usb-bus-host-parent",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .ctrlbit = S3C2443_SCLKCON_USBHOST,
++ .enable = s3c2416_clkcon_enable_s,
++ .get_rate = s3c2416_getrate_usbhost,
++ .set_rate = s3c2416_setrate_usbhost,
++ .round_rate = s3c2416_roundrate_clksrc4,
++};
++
++/* clk_hsmcc_div
++ *
++ * this clock is sourced from epll, and is fed through a divider,
++ * to a mux controlled by sclkcon where either it or a extclk can
++ * be fed to the hsmmc block
++*/
++
++static unsigned long s3c2416_getrate_hsmmc_div(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_HSMMCDIV_MASK;
++ div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2416_setrate_hsmmc_div(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2416_roundrate_clksrc4(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_hsmmc_div = {
++ .name = "hsmmc-div",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .get_rate = s3c2416_getrate_hsmmc_div,
++ .set_rate = s3c2416_setrate_hsmmc_div,
++ .round_rate = s3c2416_roundrate_clksrc4,
++};
++
++static int s3c2416_setparent_hsmmc(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
++
++ clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
++ S3C2443_SCLKCON_HSMMCCLK_EPLL);
++
++ if (parent == &clk_epll)
++ clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
++ else if (parent == &clk_ext)
++ clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
++ else
++ return -EINVAL;
++
++ if (clk->usage > 0) {
++ __raw_writel(clksrc, S3C2443_SCLKCON);
++ }
++
++ clk->parent = parent;
++ return 0;
++}
++
++static int s3c2416_enable_hsmmc(struct clk *clk, int enable)
++{
++ return s3c2416_setparent_hsmmc(clk, clk->parent);
++}
++
++static struct clk clk_hsmmc = {
++ .name = "hsmmc-if",
++ .id = -1,
++ .parent = &clk_hsmmc_div,
++ .enable = s3c2416_enable_hsmmc,
++ .set_parent = s3c2416_setparent_hsmmc,
++};
++
++/* i2s_eplldiv
++ *
++ * this clock is the output from the i2s divisor of esysclk
++*/
++
++static unsigned long s3c2416_getrate_i2s_eplldiv(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_I2SDIV_MASK;
++ div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2416_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2416_roundrate_clksrc16(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_i2s_eplldiv = {
++ .name = "i2s-eplldiv",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .get_rate = s3c2416_getrate_i2s_eplldiv,
++ .set_rate = s3c2416_setrate_i2s_eplldiv,
++ .round_rate = s3c2416_roundrate_clksrc16,
++};
++
++/* i2s-ref
++ *
++ * i2s bus reference clock, selectable from external, esysclk or epllref
++*/
++
++static int s3c2416_setparent_i2s(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ clksrc &= ~S3C2443_CLKSRC_I2S_MASK;
++
++ if (parent == &clk_epllref)
++ clksrc |= S3C2443_CLKSRC_I2S_EPLLREF;
++ else if (parent == &clk_i2s_ext)
++ clksrc |= S3C2443_CLKSRC_I2S_EXT;
++ else if (parent != &clk_i2s_eplldiv)
++ return -EINVAL;
++
++ clk->parent = parent;
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++
++ return 0;
++}
++
++static struct clk clk_i2s = {
++ .name = "i2s-if",
++ .id = -1,
++ .parent = &clk_i2s_eplldiv,
++ .ctrlbit = S3C2443_SCLKCON_I2SCLK,
++ .enable = s3c2416_clkcon_enable_s,
++ .set_parent = s3c2416_setparent_i2s,
++};
++
++
++/* display-if
++ *
++ * display interface clock, divided from esysclk
++*/
++
++static unsigned long s3c2416_getrate_display(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_DISPDIV_MASK;
++ div >>= S3C2443_CLKDIV1_DISPDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2416_setrate_display(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2416_roundrate_clksrc256(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_display = {
++ .name = "display-if",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .ctrlbit = S3C2443_SCLKCON_DISPCLK,
++ .enable = s3c2416_clkcon_enable_s,
++ .get_rate = s3c2416_getrate_display,
++ .set_rate = s3c2416_setrate_display,
++ .round_rate = s3c2416_roundrate_clksrc256,
++};
++
++/* standard clock definitions */
++
++static struct clk init_clocks_disable[] = {
++ {
++ .name = "nand",
++ .id = -1,
++ .parent = &clk_h,
++ }, {
++ .name = "sdi",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_SDI,
++ }, {
++ .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_ADC,
++ }, {
++ .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_IIC,
++ }, {
++ .name = "iis",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_IIS,
++ }, {
++ .name = "spi",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_SPI0,
++ }, {
++ .name = "spi",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_SPI1,
++ }
++};
++
++static struct clk init_clocks[] = {
++ {
++ .name = "dma",
++ .id = 0,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA0,
++ }, {
++ .name = "dma",
++ .id = 1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA1,
++ }, {
++ .name = "dma",
++ .id = 2,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA2,
++ }, {
++ .name = "dma",
++ .id = 3,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA3,
++ }, {
++ .name = "dma",
++ .id = 4,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA4,
++ }, {
++ .name = "dma",
++ .id = 5,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA5,
++ }, {
++ .name = "lcd",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_LCDC,
++ }, {
++ .name = "gpio",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_GPIO,
++ }, {
++ .name = "usb-host",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_USBH,
++ }, {
++ .name = "usb-device",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_USBD,
++ }, {
++ .name = "hsmmc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_HSMMC,
++ }, {
++ .name = "cfc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_CFC,
++ }, {
++ .name = "ssmc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_SSMC,
++ }, {
++ .name = "timers",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_PWMT,
++ }, {
++ .name = "uart",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART0,
++ }, {
++ .name = "uart",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART1,
++ }, {
++ .name = "uart",
++ .id = 2,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART2,
++ }, {
++ .name = "uart",
++ .id = 3,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART3,
++ }, {
++ .name = "rtc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2416_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_RTC,
++ }, {
++ .name = "watchdog",
++ .id = -1,
++ .parent = &clk_p,
++ .ctrlbit = S3C2443_PCLKCON_WDT,
++ }, {
++ .name = "usb-bus-host",
++ .id = -1,
++ .parent = &clk_usb_bus_host,
++ }, {
++ .name = "ac97",
++ .id = -1,
++ .parent = &clk_p,
++ .ctrlbit = S3C2443_PCLKCON_AC97,
++ }, {
++ .name = "hsmmc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2416_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_HSMMC
++ }, {
++ .name = "hsmmc-epll",
++ .id = -1,
++ .parent = &clk_epll,
++ }, {
++ .name = "hsmmc-ext",
++ .id = -1,
++ .parent = &clk_ext,
++ .enable = s3c2416_clkcon_enable_s,
++ .ctrlbit = S3C2443_SCLKCON_HSMMCCLK_EXT,
++ .rate = 12 * 1000 * 1000
++ },
++};
++
++/* clocks to add where we need to check their parentage */
++
++/* s3c2416_clk_initparents
++ *
++ * Initialise the parents for the clocks that we get at start-time
++*/
++
++static int __init clk_init_set_parent(struct clk *clk, struct clk *parent)
++{
++ printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name);
++ return clk_set_parent(clk, parent);
++}
++
++static void __init s3c2416_clk_initparents(void)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++ struct clk *parent;
++
++ switch (clksrc & S3C2443_CLKSRC_EPLLREF_MASK) {
++ case S3C2443_CLKSRC_EPLLREF_EXTCLK:
++ parent = &clk_ext;
++ break;
++
++ case S3C2443_CLKSRC_EPLLREF_XTAL:
++ default:
++ parent = &clk_xtal;
++ break;
++
++ case S3C2443_CLKSRC_EPLLREF_MPLLREF:
++ case S3C2443_CLKSRC_EPLLREF_MPLLREF2:
++ parent = &clk_mpllref;
++ break;
++ }
++
++ clk_init_set_parent(&clk_epllref, parent);
++
++ switch (clksrc & S3C2443_CLKSRC_I2S_MASK) {
++ case S3C2443_CLKSRC_I2S_EXT:
++ parent = &clk_i2s_ext;
++ break;
++
++ case S3C2443_CLKSRC_I2S_EPLLDIV:
++ default:
++ parent = &clk_i2s_eplldiv;
++ break;
++
++ case S3C2443_CLKSRC_I2S_EPLLREF:
++ case S3C2443_CLKSRC_I2S_EPLLREF3:
++ parent = &clk_epllref;
++ }
++
++ clk_init_set_parent(&clk_i2s, &clk_epllref);
++
++ /* esysclk source */
++
++ parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ?
++ &clk_epll : &clk_epllref;
++
++ clk_init_set_parent(&clk_esysclk, parent);
++
++ /* msysclk source */
++
++ if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) {
++ parent = &clk_mpll;
++ } else {
++ parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ?
++ &clk_mdivclk : &clk_mpllref;
++ }
++
++ clk_init_set_parent(&clk_msysclk, parent);
++}
++
++/* armdiv divisor table */
++
++static unsigned int armdiv[16] = {
++ [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
++ [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
++ [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
++ [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
++ [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
++ [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
++ [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
++ [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
++};
++
++static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
++{
++ clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
++
++ return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
++}
++
++static inline unsigned long s3c2416_get_prediv(unsigned long clkcon0)
++{
++ clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
++ clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
++
++ return clkcon0 + 1;
++}
++
++/* clocks to add straight away */
++
++static struct clk *clks[] __initdata = {
++ &clk_ext,
++ &clk_epll,
++ &clk_usb_bus_host,
++ &clk_usb_bus,
++ &clk_esysclk,
++ &clk_epllref,
++ &clk_mpllref,
++ &clk_msysclk,
++ &clk_uart,
++ &clk_display,
++ &clk_i2s_eplldiv,
++ &clk_i2s,
++ &clk_hsspi,
++ &clk_hsmmc_div,
++ &clk_hsmmc,
++};
++
++void __init s3c2416_init_clocks(int xtal)
++{
++ unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
++ unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
++ unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
++ unsigned long pll;
++ unsigned long fclk;
++ unsigned long hclk;
++ unsigned long pclk;
++ struct clk *clkp;
++ int ret;
++ int ptr;
++
++ pll = s3c2443_get_mpll(mpllcon, xtal);
++
++ fclk = pll / s3c2416_fclk_div(clkdiv0);
++ hclk = pll / s3c2416_get_prediv(clkdiv0);
++ hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
++ pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
++
++ s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
++
++ printk("S3C2416: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
++ (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
++ print_mhz(pll), print_mhz(fclk),
++ print_mhz(hclk), print_mhz(pclk));
++
++ s3c2416_clk_initparents();
++
++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
++ clkp = clks[ptr];
++
++ ret = s3c24xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to register clock %s (%d)\n",
++ clkp->name, ret);
++ }
++ }
++
++ clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
++
++ clk_usb_bus.parent = &clk_usb_bus_host;
++
++ /* ensure usb bus clock is within correct rate of 48MHz */
++
++ if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) {
++ printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
++ clk_set_rate(&clk_usb_bus_host, 48*1000*1000);
++ }
++
++ printk("S3C2416: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
++ (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
++ print_mhz(clk_get_rate(&clk_epll)),
++ print_mhz(clk_get_rate(&clk_usb_bus)));
++
++ /* register clocks from clock array */
++
++ clkp = init_clocks;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
++ ret = s3c24xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to register clock %s (%d)\n",
++ clkp->name, ret);
++ }
++ }
++
++ /* We must be careful disabling the clocks we are not intending to
++ * be using at boot time, as subsystems such as the LCD which do
++ * their own DMA requests to the bus can cause the system to lockup
++ * if they where in the middle of requesting bus access.
++ *
++ * Disabling the LCD clock if the LCD is active is very dangerous,
++ * and therefore the bootloader should be careful to not enable
++ * the LCD clock if it is not needed.
++ */
++
++ /* install (and disable) the clocks we do not need immediately */
++
++ clkp = init_clocks_disable;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
++
++ ret = s3c24xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to register clock %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ (clkp->enable)(clkp, 0);
++ }
++}
++
+diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
+new file mode 100644
+index 0000000..d04be2f
+--- /dev/null
++++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
+@@ -0,0 +1,544 @@
++/* linux/arch/arm/mach-s3c2416/mach-smdk2416.c
++ *
++ * Copyright (c) 2007 Samsung Electronics
++ *
++ *
++ * Thanks to Samsung for the loan of an SMDK2416
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/serial_core.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <asm/setup.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/plat-s3c/nand.h>
++#include <asm/plat-s3c/adc.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
++#include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-mem.h>
++
++#include <asm/arch/idle.h>
++#include <asm/arch/fb.h>
++
++#include <asm/plat-s3c24xx/clock.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++#include <asm/plat-s3c24xx/common-smdk.h>
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/arch/hsmmc.h>
++
++#if defined(CONFIG_RTC_DRV_S3C)
++#include <asm/plat-s3c/regs-rtc.h>
++#endif
++
++#include <asm/plat-s3c/regs-adc.h>
++#include <asm/plat-s3c/ts.h>
++
++static struct map_desc smdk2416_iodesc[] __initdata = {
++
++ /* ISA IO Space map (memory space selected by A24) */
++
++ {
++ .virtual = (u32)S3C24XX_VA_ISA_WORD,
++ .pfn = __phys_to_pfn(S3C2410_CS2),
++ .length = 0x10000,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
++ .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
++ .length = SZ_4M,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = (u32)S3C24XX_VA_ISA_BYTE,
++ .pfn = __phys_to_pfn(S3C2410_CS2),
++ .length = 0x10000,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
++ .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
++ .length = SZ_4M,
++ .type = MT_DEVICE,
++ }
++};
++
++#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
++#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
++#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
++
++static struct s3c24xx_uart_clksrc smdk2416_serial_clocks[] = {
++ [0] = {
++ .name = "pclk",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ },
++ [1] = {
++ .name = "esysclk",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ }
++
++};
++
++static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
++ [0] = {
++ .hwport = 0,
++ .flags = 0,
++ .ucon = 0x3c5,
++ .ulcon = 0x03,
++ .ufcon = 0x51,
++ },
++ [1] = {
++ .hwport = 1,
++ .flags = 0,
++ .ucon = 0xfc5,
++ .ulcon = 0x03,
++ .ufcon = 0x51,
++ .clocks = smdk2416_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk2416_serial_clocks),
++ },
++ /* IR port */
++ [2] = {
++ .hwport = 2,
++ .flags = 0,
++ .ucon = 0xfc5,
++ .ulcon = 0x43,
++ .ufcon = 0x51,
++ .clocks = smdk2416_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk2416_serial_clocks),
++ }
++};
++
++static struct platform_device *smdk2416_devices[] __initdata = {
++ &s3c_device_spi0,
++ &s3c_device_spi1,
++ &s3c_device_wdt,
++ &s3c_device_i2c,
++ &s3c_device_rtc,
++ &s3c_device_adc,
++ &s3c_device_ts,
++ &s3c_device_iis,
++ &s3c_device_usbgadget,
++ &s3c_device_usb,
++ &s3c_device_hsmmc0,
++ &s3c_device_hsmmc1,
++ &s3c_device_smc911x,
++};
++
++static void __init smdk2416_map_io(void)
++{
++ s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
++ s3c24xx_init_clocks(12000000);
++ s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
++}
++
++static void smdk2416_cs89x0_set(void)
++{
++ u32 val;
++
++ val = readl(S3C_BANK_CFG);
++ val &= ~((1<<8)|(1<<9)|(1<<10));
++ writel(val, S3C_BANK_CFG);
++
++ /* Bank1 Idle cycle ctrl. */
++ writel(0xf, S3C_SSMC_SMBIDCYR1);
++
++ /* Bank1 Read Wait State cont. = 14 clk Tacc? */
++ writel(12, S3C_SSMC_SMBWSTRDR1);
++
++ /* Bank1 Write Wait State ctrl. */
++ writel(12, S3C_SSMC_SMBWSTWRR1);
++
++ /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
++ writel(2, S3C_SSMC_SMBWSTOENR1);
++
++ /* Bank1 Write Enable Assertion Delay ctrl. */
++ writel(2, S3C_SSMC_SMBWSTWENR1);
++
++ /* SMWAIT active High, Read Byte Lane Enabl WS1? */
++ val = readl(S3C_SSMC_SMBCR1);
++
++ val |= ((1<<15)|(1<<7));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val |= ((1<<2)|(1<<0));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val &= ~((3<<20)|(3<<12));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val &= ~(3<<4);
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val |= (1<<4);
++
++ writel(val, S3C_SSMC_SMBCR1);
++
++}
++
++static void smdk2416_smc911x_set(void)
++{
++ u32 val;
++
++ /* Bank1 Idle cycle ctrl. */
++ writel(0xf, S3C_SSMC_SMBIDCYR4);
++
++ /* Bank1 Read Wait State cont. = 14 clk Tacc? */
++ writel(12, S3C_SSMC_SMBWSTRDR4);
++
++ /* Bank1 Write Wait State ctrl. */
++ writel(12, S3C_SSMC_SMBWSTWRR4);
++
++ /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
++ writel(2, S3C_SSMC_SMBWSTOENR4);
++
++ /* Bank1 Write Enable Assertion Delay ctrl. */
++ writel(2, S3C_SSMC_SMBWSTWENR4);
++
++ /* SMWAIT active High, Read Byte Lane Enabl WS1? */
++ val = readl(S3C_SSMC_SMBCR4);
++
++ val |= ((1<<15)|(1<<7));
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val |= ((1<<2)|(1<<0));
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val &= ~((3<<20)|(3<<12));
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val &= ~(3<<4);
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val |= (1<<4);
++
++ writel(val, S3C_SSMC_SMBCR4);
++
++}
++
++static void smdk2416_hsmmc_init (void)
++{
++ /* GPIO E (external interrupt) : Chip detect */
++ s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_EINT1); /* GPF1 to EINT1 */
++}
++
++static void __init smdk2416_machine_init(void)
++{
++ smdk2416_smc911x_set();
++ platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
++ smdk_machine_init();
++ smdk2416_hsmmc_init();
++}
++
++static void __init smdk2416_fixup (struct machine_desc *desc, struct tag *tags,
++ char **cmdline, struct meminfo *mi)
++{
++ /*
++ * Bank start addresses are not present in the information
++ * passed in from the boot loader. We could potentially
++ * detect them, but instead we hard-code them.
++ */
++ mi->bank[0].start = PHYS_OFFSET;
++
++#if defined(CONFIG_VIDEO_SAMSUNG)
++ mi->bank[0].size = 49*1024*1024;
++#else
++ mi->bank[0].size = 64*1024*1024;
++#endif
++ mi->bank[0].node = 0;
++
++ mi->nr_banks = 1;
++}
++
++
++MACHINE_START(SMDK2416, "SMDK2416")
++ /* Maintainer: Ben Dooks <ben@fluff.org> */
++ .phys_io = S3C2410_PA_UART,
++ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
++ .boot_params = S3C2410_SDRAM_PA + 0x100,
++
++ .init_irq = s3c24xx_init_irq,
++ .map_io = smdk2416_map_io,
++ .fixup = smdk2416_fixup,
++ .init_machine = smdk2416_machine_init,
++ .timer = &s3c24xx_timer,
++MACHINE_END
++
++
++void hsmmc_set_gpio (uint channel, uint width)
++{
++ switch (channel) {
++
++ /* can supports 1 and 4 bit bus */
++ case 0:
++ /* GPIO E : Command, Clock */
++ s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2450_GPE5_SD0_CLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2450_GPE6_SD0_CMD);
++
++ if (width == 1) {
++ /* GPIO E : MMC DATA0[0] */
++ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
++ }
++ else if (width == 4) {
++ /* GPIO E : MMC DATA0[0:3] */
++ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
++ s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2450_GPE8_SD0_DAT1);
++ s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2450_GPE9_SD0_DAT2);
++ s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2450_GPE10_SD0_DAT3);
++ }
++ break;
++
++ /* can supports 1, 4, and 8 bit bus */
++ case 1:
++ /* GPIO L : Command, Clock */
++ s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2450_GPL8_SD1CMD);
++ s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2450_GPL9_SD1CLK);
++
++ if (width == 1) {
++ /* GPIO L : MMC DATA1[0] */
++ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
++ }
++ else if (width == 4) {
++ /* GPIO L : MMC DATA1[0:3] */
++ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
++ s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
++ s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
++ s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
++ }
++ break;
++
++ default:
++ break;
++ }
++}
++
++
++#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
++ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
++
++/* Channel 0 : added HS-MMC channel */
++struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
++ .hwport = 0,
++ .enabled = 1,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ .clocks[0] = {
++ .name = "hsmmc",
++ .src = 0x1,
++ },
++
++ .clocks[1] = {
++ .name = "esysclk",
++ .src = 0x2,
++ },
++
++ .clocks[2] = {
++ .name = "hsmmc-ext",
++ .src = 0x3,
++ },
++};
++
++/* Channel 1 : default HS-MMC channel */
++struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
++ .hwport = 1, /* H/W Channel 1 */
++ .enabled = 1,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ .clocks[0] = {
++ .name = "hsmmc",
++ .src = 0x1,
++ },
++
++ .clocks[1] = {
++ .name = "esysclk",
++ .src = 0x2,
++ },
++
++ .clocks[2] = {
++ .name = "hsmmc-ext",
++ .src = 0x3,
++ },
++};
++
++#if defined(CONFIG_RTC_DRV_S3C)
++/* rtc function */
++unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val)
++{
++ return 0;
++}
++
++unsigned int s3c_rtc_read_alarm_status(void __iomem *base)
++{
++ return (readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN);
++}
++
++void s3c_rtc_set_pie(void __iomem *base, uint to)
++{
++ unsigned int tmp;
++
++ tmp = readb(base + S3C2410_TICNT) & ~S3C2410_TICNT_ENABLE;
++
++ if (to)
++ tmp |= S3C2410_TICNT_ENABLE;
++
++ writeb(tmp, base + S3C2410_TICNT);
++
++}
++
++void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint *s3c_freq)
++{
++ unsigned int tmp;
++
++ tmp = readb(base + S3C2410_TICNT) & S3C2410_TICNT_ENABLE;
++ writew(readw(base + S3C2410_RTCCON) & (~(1<<8)),base + S3C2410_RTCCON);
++ *s3c_freq = freq;
++ tmp |= (128 / freq)-1;
++ writeb(tmp, base + S3C2410_TICNT);
++}
++
++void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en)
++{
++ unsigned int tmp;
++
++ if (!en) {
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp & ~S3C2410_RTCCON_RTCEN, base + S3C2410_RTCCON);
++
++ tmp = readb(base + S3C2410_TICNT);
++ writeb(tmp & ~S3C2410_TICNT_ENABLE, base + S3C2410_TICNT);
++ } else {
++ /* re-enable the device, and check it is ok */
++ if ((readb(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){
++ dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
++
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON);
++ }
++
++ if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){
++ dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
++
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON);
++ }
++
++ if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){
++ dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
++
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON);
++ }
++ }
++}
++#endif
++
++struct s3c_adc_cfg s3c_adc_platform={
++ /* s3c2450 support 12-bit resolution */
++ .delay = 10000,
++ .presc = 49,
++ .resolution = 12,
++};
++
++#if defined(CONFIG_S3C_ADC)
++unsigned int s3c_adc_convert(void __iomem *reg_base,unsigned int s3c_adc_port)
++{
++ unsigned int adc_return;
++ unsigned long data0;
++ unsigned long data1;
++
++ writel(S3C2443_ADCCON_SELMUX(s3c_adc_port), reg_base+S3C2443_ADCMUX);
++
++ udelay(10);
++
++ writel(readl(reg_base+S3C2410_ADCCON)|S3C2410_ADCCON_ENABLE_START, reg_base+S3C2410_ADCCON);
++
++ do {
++ data0 = readl(reg_base+S3C2410_ADCCON);
++ } while(!(data0 & S3C2410_ADCCON_ECFLG));
++
++ data1 = readl(reg_base+S3C2410_ADCDAT0);
++
++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT;
++
++ return adc_return;
++}
++#endif
++
++
++struct s3c_ts_mach_info s3c_ts_platform = {
++ .delay = 10000,
++ .presc = 49,
++ .oversampling_shift = 2,
++ .resol_bit = 12,
++};
++
+diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
+new file mode 100644
+index 0000000..64105e7
+--- /dev/null
++++ b/arch/arm/mach-s3c2416/s3c2416.c
+@@ -0,0 +1,113 @@
++/* linux/arch/arm/mach-s3c2416/s3c2416.c
++ *
++ * Copyright (c) 2007 Samsung Electronics
++ *
++ *
++ * Samsung S3C2450 Mobile CPU support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/serial_core.h>
++#include <linux/sysdev.h>
++#include <linux/clk.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/arch/reset.h>
++
++#include <asm/plat-s3c24xx/s3c2416.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/common-smdk.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++static struct map_desc s3c2416_iodesc[] __initdata = {
++ IODESC_ENT(WATCHDOG),
++ IODESC_ENT(CLKPWR),
++ IODESC_ENT(TIMER),
++ IODESC_ENT(LCD),
++ IODESC_ENT(EBI),
++ IODESC_ENT(SROMC),
++ IODESC_ENT(CS8900),
++ IODESC_ENT(USBDEV),
++};
++
++struct sysdev_class s3c2416_sysclass = {
++ set_kset_name("s3c2416-core"),
++};
++
++static struct sys_device s3c2416_sysdev = {
++ .cls = &s3c2416_sysclass,
++};
++
++static void s3c2416_hard_reset(void)
++{
++ __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
++}
++
++int __init s3c2416_init(void)
++{
++ printk("S3C2416: Initialising architecture\n");
++
++ s3c24xx_reset_hook = s3c2416_hard_reset;
++
++#if !defined (CONFIG_MTD_NAND_S3C)
++ s3c_device_nand.name = "s3c2412-nand";
++#else
++ s3c_device_nand.name = "s3c-nand";
++#endif
++ /* Rename devices that are specific to s3c2416 */
++ s3c_device_lcd.name = "s3c-lcd";
++
++ /* change WDT IRQ number */
++ s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
++ s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
++
++ return sysdev_register(&s3c2416_sysdev);
++}
++
++void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
++{
++ s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
++}
++
++/* s3c2416_map_io
++ *
++ * register the standard cpu IO areas, and any passed in from the
++ * machine specific initialisation.
++ */
++
++void __init s3c2416_map_io(struct map_desc *mach_desc, int mach_size)
++{
++ iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
++ iotable_init(mach_desc, mach_size);
++}
++
++/* need to register class before we actually register the device, and
++ * we also need to ensure that it has been initialised before any of the
++ * drivers even try to use it (even if not on an s3c2416 based system)
++ * as a driver which may support both 2450 and 2440 may try and use it.
++*/
++
++static int __init s3c2416_core_init(void)
++{
++ return sysdev_class_register(&s3c2416_sysclass);
++}
++
++core_initcall(s3c2416_core_init);
+diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
+index b42f956..084f575 100644
+--- a/arch/arm/mach-s3c2443/clock.c
++++ b/arch/arm/mach-s3c2443/clock.c
+@@ -597,6 +597,44 @@ static struct clk clk_cam = {
+ .round_rate = s3c2443_roundrate_clksrc16,
+ };
+
++static struct clk clk_cam_h = {
++ .name = "camif-hclk",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2443_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_CAMIF,
++};
++
++#define CAMDIV_val 26
++
++static int s3c2443_setrate_camera(struct clk *clk, unsigned long rate)
++{
++ unsigned int camclk_div, val, hclkcon;
++ unsigned long src_clk = clk_get_rate(clk->parent);
++
++ if (rate == 4800000) {
++ printk(KERN_INFO "External camera clock is set to 48MHz\n");
++ }
++ else if (rate > 48000000) {
++ printk(KERN_ERR "Invalid camera clock\n");
++ }
++
++ writel(readl(S3C2443_CLKSRC) | (1 << 20), S3C2443_CLKSRC);
++
++ camclk_div = src_clk / rate;
++ printk("Parent clock for Camera = %ld, CAMDIV = %d\n", src_clk, camclk_div);
++
++ val = readl(S3C2443_CLKDIV1);
++ val &= ~(0xf<<CAMDIV_val);
++ writel(val, S3C2443_CLKDIV1);
++
++ val |= ((camclk_div -1) << CAMDIV_val);
++ writel(val, S3C2443_CLKDIV1);
++ val = readl(S3C2443_CLKDIV1);
++
++ return 0;
++}
++
+ /* display-if
+ *
+ * display interface clock, divided from esysclk
+@@ -814,7 +852,32 @@ static struct clk init_clocks[] = {
+ .id = -1,
+ .parent = &clk_p,
+ .ctrlbit = S3C2443_PCLKCON_AC97,
+- }
++ }, {
++ .name = "hsmmc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2443_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_HSMMC
++ }, {
++ .name = "hsmmc-epll",
++ .id = -1,
++ .parent = &clk_epll,
++ }, {
++ .name = "hsmmc-ext",
++ .id = -1,
++ .parent = &clk_ext,
++ .enable = s3c2443_clkcon_enable_s,
++ .ctrlbit = S3C2443_SCLKCON_HSMMCCLK_EXT,
++ .rate = 12 * 1000 * 1000
++ },
++ {
++ .name = "camera",
++ .id = -1,
++ .parent = &clk_cam_h,
++ .enable = s3c2443_clkcon_enable_s,
++ .ctrlbit = S3C2443_SCLKCON_CAMCLK,
++ .set_rate = s3c2443_setrate_camera,
++ },
+ };
+
+ /* clocks to add where we need to check their parentage */
+@@ -936,6 +999,7 @@ static struct clk *clks[] __initdata = {
+ &clk_hsspi,
+ &clk_hsmmc_div,
+ &clk_hsmmc,
++ &clk_cam_h,
+ };
+
+ void __init s3c2443_init_clocks(int xtal)
+@@ -1028,3 +1092,5 @@ void __init s3c2443_init_clocks(int xtal)
+ (clkp->enable)(clkp, 0);
+ }
+ }
++
++
+diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
+index f6c006d..a09b4c3 100644
+--- a/arch/arm/mach-s3c2443/dma.c
++++ b/arch/arm/mach-s3c2443/dma.c
+@@ -164,7 +164,11 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
+
+ static int __init s3c2443_dma_add(struct sys_device *sysdev)
+ {
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ s3c24xx_dma_init(8, IRQ_S3C2443_DMA0, 0x100);
++#else
+ s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
++#endif
+ return s3c24xx_dma_init_map(&s3c2443_dma_sel);
+ }
+
+@@ -174,7 +178,13 @@ static struct sysdev_driver s3c2443_dma_driver = {
+
+ static int __init s3c2443_dma_init(void)
+ {
++#if defined(CONFIG_CPU_S3C2443)
+ return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_dma_driver);
++#elif defined(CONFIG_CPU_S3C2450)
++ return sysdev_driver_register(&s3c2450_sysclass, &s3c2443_dma_driver);
++#elif defined(CONFIG_CPU_S3C2416)
++ return sysdev_driver_register(&s3c2416_sysclass, &s3c2443_dma_driver);
++#endif
+ }
+
+ arch_initcall(s3c2443_dma_init);
+diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
+index f9ad498..9cfc6a3 100644
+--- a/arch/arm/mach-s3c2443/irq.c
++++ b/arch/arm/mach-s3c2443/irq.c
+@@ -282,7 +282,13 @@ static struct sysdev_driver s3c2443_irq_driver = {
+
+ static int __init s3c2443_irq_init(void)
+ {
++#if defined(CONFIG_CPU_S3C2443)
+ return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver);
++#elif defined(CONFIG_CPU_S3C2450)
++ return sysdev_driver_register(&s3c2450_sysclass, &s3c2443_irq_driver);
++#elif defined(CONFIG_CPU_S3C2416)
++ return sysdev_driver_register(&s3c2416_sysclass, &s3c2443_irq_driver);
++#endif
+ }
+
+ arch_initcall(s3c2443_irq_init);
+diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
+index 8cd9313..0f1d42f 100644
+--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
++++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
+@@ -26,14 +26,18 @@
+ #include <asm/mach/map.h>
+ #include <asm/mach/irq.h>
+
++#include <asm/setup.h>
+ #include <asm/hardware.h>
+ #include <asm/io.h>
+ #include <asm/irq.h>
+ #include <asm/mach-types.h>
+
+ #include <asm/plat-s3c/regs-serial.h>
++#include <asm/plat-s3c/nand.h>
+ #include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
+ #include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-mem.h>
+
+ #include <asm/arch/idle.h>
+ #include <asm/arch/fb.h>
+@@ -46,7 +50,14 @@
+
+ #include <asm/plat-s3c24xx/common-smdk.h>
+
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/arch/hsmmc.h>
++
+ static struct map_desc smdk2443_iodesc[] __initdata = {
++ IODESC_ENT(CS8900),
++
+ /* ISA IO Space map (memory space selected by A24) */
+
+ {
+@@ -76,6 +87,22 @@ static struct map_desc smdk2443_iodesc[] __initdata = {
+ #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+ #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
++static struct s3c24xx_uart_clksrc smdk2443_serial_clocks[] = {
++ [0] = {
++ .name = "pclk",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ },
++ [1] = {
++ .name = "esysclk",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ }
++
++};
++
+ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+@@ -87,24 +114,37 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+- .ucon = 0x3c5,
++ .ucon = 0xfc5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
++ .clocks = smdk2443_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk2443_serial_clocks),
+ },
+ /* IR port */
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+- .ucon = 0x3c5,
++ .ucon = 0xfc5,
+ .ulcon = 0x43,
+ .ufcon = 0x51,
++ .clocks = smdk2443_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk2443_serial_clocks),
+ }
+ };
+
+ static struct platform_device *smdk2443_devices[] __initdata = {
++ &s3c_device_spi0,
++ &s3c_device_spi1,
+ &s3c_device_wdt,
+ &s3c_device_i2c,
++ &s3c_device_rtc,
++ &s3c_device_adc,
++ &s3c_device_ts,
++ &s3c_device_iis,
++ &s3c_device_usbgadget,
++ &s3c_device_usb,
+ &s3c_device_hsmmc,
++ &s3c_device_camif,
+ };
+
+ static void __init smdk2443_map_io(void)
+@@ -114,12 +154,84 @@ static void __init smdk2443_map_io(void)
+ s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
+ }
+
++static void smdk2443_cs89x0_set(void)
++{
++ u32 val;
++
++ val = readl(S3C_BANK_CFG);
++ val &= ~((1<<8)|(1<<9)|(1<<10));
++ writel(val, S3C_BANK_CFG);
++
++ /* Bank1 Idle cycle ctrl. */
++ writel(0xf, S3C_SSMC_SMBIDCYR1);
++
++ /* Bank1 Read Wait State cont. = 14 clk Tacc? */
++ writel(12, S3C_SSMC_SMBWSTRDR1);
++
++ /* Bank1 Write Wait State ctrl. */
++ writel(12, S3C_SSMC_SMBWSTWRR1);
++
++ /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
++ writel(2, S3C_SSMC_SMBWSTOENR1);
++
++ /* Bank1 Write Enable Assertion Delay ctrl. */
++ writel(2, S3C_SSMC_SMBWSTWENR1);
++
++ /* SMWAIT active High, Read Byte Lane Enabl WS1? */
++ val = readl(S3C_SSMC_SMBCR1);
++
++ val |= ((1<<15)|(1<<7));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val |= ((1<<2)|(1<<0));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val &= ~((3<<20)|(3<<12));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val &= ~(3<<4);
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val |= (1<<4);
++
++ writel(val, S3C_SSMC_SMBCR1);
++
++}
++
+ static void __init smdk2443_machine_init(void)
+ {
++ smdk2443_cs89x0_set();
+ platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
+ smdk_machine_init();
+ }
+
++static void __init smdk2443_fixup (struct machine_desc *desc, struct tag *tags,
++ char **cmdline, struct meminfo *mi)
++{
++ /*
++ * Bank start addresses are not present in the information
++ * passed in from the boot loader. We could potentially
++ * detect them, but instead we hard-code them.
++ */
++ mi->bank[0].start = PHYS_OFFSET;
++
++#if defined(CONFIG_VIDEO_SAMSUNG)
++ mi->bank[0].size = 49*1024*1024;
++#elif defined(CONFIG_PP_S3C2443)
++ mi->bank[0].size = 60*1024*1024;
++#else
++ mi->bank[0].size = 64*1024*1024;
++#endif
++ mi->bank[0].node = 0;
++
++ mi->nr_banks = 1;
++}
++
++
+ MACHINE_START(SMDK2443, "SMDK2443")
+ /* Maintainer: Ben Dooks <ben@fluff.org> */
+ .phys_io = S3C2410_PA_UART,
+@@ -128,6 +240,73 @@ MACHINE_START(SMDK2443, "SMDK2443")
+
+ .init_irq = s3c24xx_init_irq,
+ .map_io = smdk2443_map_io,
++ .fixup = smdk2443_fixup,
+ .init_machine = smdk2443_machine_init,
+ .timer = &s3c24xx_timer,
+ MACHINE_END
++
++void hsmmc_set_gpio (uint channel, uint width)
++{
++ /* GPIO L */
++ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2443_GPL0_SD0DAT0);
++ s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2443_GPL1_SD0DAT1);
++
++ s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2443_GPL2_SD0DAT2);
++ s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2443_GPL3_SD0DAT3);
++
++ s3c2410_gpio_cfgpin(S3C2443_GPL4, S3C2443_GPL4_SD0DAT4);
++ s3c2410_gpio_cfgpin(S3C2443_GPL5, S3C2443_GPL5_SD0DAT5);
++
++ s3c2410_gpio_cfgpin(S3C2443_GPL6, S3C2443_GPL6_SD0DAT6);
++ s3c2410_gpio_cfgpin(S3C2443_GPL7, S3C2443_GPL7_SD0DAT7);
++
++ s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2443_GPL8_SD0CMD);
++ s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2443_GPL9_SD0CLK);
++
++ /* GPIO J */
++ s3c2410_gpio_cfgpin(S3C2443_GPJ13, S3C2443_GPJ13_SD0LED);
++ s3c2410_gpio_cfgpin(S3C2443_GPJ14, S3C2443_GPJ14_nSD0CD);
++#if 0
++ s3c2410_gpio_cfgpin(S3C2443_GPJ15, S3C2443_GPJ15_OUTP);
++#endif
++ s3c2410_gpio_cfgpin(S3C2443_GPJ15, S3C2443_GPJ15_nSD0WP); /* write protect enable */
++
++
++ s3c2410_gpio_setpin(S3C2443_GPJ15, 1);
++}
++
++#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | \
++ MMC_CAP_MULTIWRITE | \
++ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
++
++
++struct s3c_hsmmc_cfg s3c_hsmmc_platform = {
++ .hwport = 0,
++ .enabled = 1,
++ .host_caps = HOST_CAPS,
++ .bus_width = 8,
++ .highspeed = 1,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0x4000C100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0x00800080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00800080, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0x4000C100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0x00800080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00800080, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ .clocks[0] = "hsmmc", /* 1st clock source */
++ .clocks[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
++ //.clk_name[1] = "hsmmc-epll", /* 2nd clock source hsmmc-epll */
++ .clocks[2] = "hsmmc-ext", /* 3rd clock source */
++};
++
++
+diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
+index 8d81171..1c2bc8b 100644
+--- a/arch/arm/mach-s3c2443/s3c2443.c
++++ b/arch/arm/mach-s3c2443/s3c2443.c
+@@ -34,12 +34,17 @@
+
+ #include <asm/plat-s3c24xx/s3c2443.h>
+ #include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/common-smdk.h>
+ #include <asm/plat-s3c24xx/cpu.h>
+
+ static struct map_desc s3c2443_iodesc[] __initdata = {
+ IODESC_ENT(WATCHDOG),
+ IODESC_ENT(CLKPWR),
+ IODESC_ENT(TIMER),
++ IODESC_ENT(LCD),
++ IODESC_ENT(EBI),
++ IODESC_ENT(SROMC),
++ IODESC_ENT(CS8900),
+ };
+
+ struct sysdev_class s3c2443_sysclass = {
+@@ -61,7 +66,13 @@ int __init s3c2443_init(void)
+
+ s3c24xx_reset_hook = s3c2443_hard_reset;
+
++#if !defined (CONFIG_MTD_NAND_S3C)
+ s3c_device_nand.name = "s3c2412-nand";
++#else
++ s3c_device_nand.name = "s3c-nand";
++#endif
++ /* Rename devices that are specific to s3c2443 */
++ s3c_device_lcd.name = "s3c-lcd";
+
+ /* change WDT IRQ number */
+ s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
+diff --git a/arch/arm/mach-s3c2450/Kconfig b/arch/arm/mach-s3c2450/Kconfig
+new file mode 100644
+index 0000000..0afef7a
+--- /dev/null
++++ b/arch/arm/mach-s3c2450/Kconfig
+@@ -0,0 +1,28 @@
++# arch/arm/mach-s3c2450/Kconfig
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++config CPU_S3C2450
++ bool
++ depends on ARCH_S3C2410
++ select S3C2450_DMA if S3C2410_DMA
++ help
++ Support for the S3C2450 SoC from the S3C24XX line
++
++config S3C2450_DMA
++ bool
++ depends on CPU_S3C2450
++ help
++ Internal config node for S3C2450 DMA support
++
++menu "S3C2450 Machines"
++
++config MACH_SMDK2450
++ bool "SMDK2450"
++ select CPU_S3C2450
++ select MACH_SMDK
++ help
++ Say Y here if you are using an SMDK2450
++endmenu
+diff --git a/arch/arm/mach-s3c2450/Makefile b/arch/arm/mach-s3c2450/Makefile
+new file mode 100644
+index 0000000..1871a5e
+--- /dev/null
++++ b/arch/arm/mach-s3c2450/Makefile
+@@ -0,0 +1,20 @@
++# arch/arm/mach-s3c2450/Makefile
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++obj-y :=
++obj-m :=
++obj-n :=
++obj- :=
++
++obj-$(CONFIG_CPU_S3C2450) += s3c2450.o
++obj-$(CONFIG_CPU_S3C2450) += ../mach-s3c2443/irq.o
++obj-$(CONFIG_CPU_S3C2450) += clock.o
++
++obj-$(CONFIG_S3C2450_DMA) += ../mach-s3c2443/dma.o
++
++# Machine support
++
++obj-$(CONFIG_MACH_SMDK2450) += mach-smdk2450.o
+diff --git a/arch/arm/mach-s3c2450/clock.c b/arch/arm/mach-s3c2450/clock.c
+new file mode 100644
+index 0000000..2c41cd6
+--- /dev/null
++++ b/arch/arm/mach-s3c2450/clock.c
+@@ -0,0 +1,1095 @@
++/* linux/arch/arm/mach-s3c2450/clock.c
++ *
++ * Copyright (c) 2007 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2450 Clock control support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/sysdev.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/serial_core.h>
++
++#include <asm/mach/map.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++
++#include <asm/plat-s3c24xx/s3c2450.h>
++#include <asm/plat-s3c24xx/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++/* We currently have to assume that the system is running
++ * from the XTPll input, and that all ***REFCLKs are being
++ * fed from it, as we cannot read the state of OM[4] from
++ * software.
++ *
++ * It would be possible for each board initialisation to
++ * set the correct muxing at initialisation
++*/
++
++static int s3c2450_clkcon_enable_h(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C2443_HCLKCON);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C2443_HCLKCON);
++
++ return 0;
++}
++
++static int s3c2450_clkcon_enable_p(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C2443_PCLKCON);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C2443_HCLKCON);
++
++ return 0;
++}
++
++static int s3c2450_clkcon_enable_s(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C2443_SCLKCON);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C2443_SCLKCON);
++
++ return 0;
++}
++
++static unsigned long s3c2450_roundrate_clksrc(struct clk *clk,
++ unsigned long rate,
++ unsigned int max)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ int div;
++
++ if (rate > parent_rate)
++ return parent_rate;
++
++ /* note, we remove the +/- 1 calculations as they cancel out */
++
++ div = (rate / parent_rate);
++
++ if (div < 1)
++ div = 1;
++ else if (div > max)
++ div = max;
++
++ return parent_rate / div;
++}
++
++static unsigned long s3c2450_roundrate_clksrc4(struct clk *clk,
++ unsigned long rate)
++{
++ return s3c2450_roundrate_clksrc(clk, rate, 4);
++}
++
++static unsigned long s3c2450_roundrate_clksrc16(struct clk *clk,
++ unsigned long rate)
++{
++ return s3c2450_roundrate_clksrc(clk, rate, 16);
++}
++
++static unsigned long s3c2450_roundrate_clksrc256(struct clk *clk,
++ unsigned long rate)
++{
++ return s3c2450_roundrate_clksrc(clk, rate, 256);
++}
++
++/* clock selections */
++
++/* CPU EXTCLK input */
++static struct clk clk_ext = {
++ .name = "ext",
++ .id = -1,
++};
++
++static struct clk clk_mpllref = {
++ .name = "mpllref",
++ .parent = &clk_xtal,
++ .id = -1,
++};
++
++#if 0
++static struct clk clk_mpll = {
++ .name = "mpll",
++ .parent = &clk_mpllref,
++ .id = -1,
++};
++#endif
++
++static struct clk clk_epllref;
++
++static struct clk clk_epll = {
++ .name = "epll",
++ .parent = &clk_epllref,
++ .id = -1,
++};
++
++static struct clk clk_i2s_ext = {
++ .name = "i2s-ext",
++ .id = -1,
++};
++
++static int s3c2450_setparent_epllref(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK;
++
++ if (parent == &clk_xtal)
++ clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL;
++ else if (parent == &clk_ext)
++ clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK;
++ else if (parent != &clk_mpllref)
++ return -EINVAL;
++
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++ clk->parent = parent;
++
++ return 0;
++}
++
++static struct clk clk_epllref = {
++ .name = "epllref",
++ .id = -1,
++ .set_parent = s3c2450_setparent_epllref,
++};
++
++static unsigned long s3c2450_getrate_mdivclk(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV0);
++
++ div &= S3C2443_CLKDIV0_EXTDIV_MASK;
++ div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
++
++ return parent_rate / (div + 1);
++}
++
++static struct clk clk_mdivclk = {
++ .name = "mdivclk",
++ .parent = &clk_mpllref,
++ .id = -1,
++ .get_rate = s3c2450_getrate_mdivclk,
++};
++
++
++static int s3c2450_setparent_msysclk(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL |
++ S3C2443_CLKSRC_EXTCLK_DIV);
++
++ if (parent == &clk_mpll)
++ clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL;
++ else if (parent == &clk_mdivclk)
++ clksrc |= S3C2443_CLKSRC_EXTCLK_DIV;
++ else if (parent != &clk_mpllref)
++ return -EINVAL;
++
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++ clk->parent = parent;
++
++ return 0;
++}
++
++static struct clk clk_msysclk = {
++ .name = "msysclk",
++ .parent = &clk_xtal,
++ .id = -1,
++ .set_parent = s3c2450_setparent_msysclk,
++};
++
++
++/* esysclk
++ *
++ * this is sourced from either the EPLL or the EPLLref clock
++*/
++
++static int s3c2450_setparent_esysclk(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ if (parent == &clk_epll)
++ clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL;
++ else if (parent == &clk_epllref)
++ clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL;
++ else
++ return -EINVAL;
++
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++ clk->parent = parent;
++
++ return 0;
++}
++
++static struct clk clk_esysclk = {
++ .name = "esysclk",
++ .parent = &clk_epll,
++ .id = -1,
++ .set_parent = s3c2450_setparent_esysclk,
++};
++
++/* uartclk
++ *
++ * UART baud-rate clock sourced from esysclk via a divisor
++*/
++
++static unsigned long s3c2450_getrate_uart(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_UARTDIV_MASK;
++ div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++
++static int s3c2450_setrate_uart(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2450_roundrate_clksrc16(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_uart = {
++ .name = "uartclk",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .get_rate = s3c2450_getrate_uart,
++ .set_rate = s3c2450_setrate_uart,
++ .round_rate = s3c2450_roundrate_clksrc16,
++};
++
++/* hsspi
++ *
++ * high-speed spi clock, sourced from esysclk
++*/
++
++static unsigned long s3c2450_getrate_hsspi(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_HSSPIDIV_MASK;
++ div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++
++static int s3c2450_setrate_hsspi(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2450_roundrate_clksrc4(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_hsspi = {
++ .name = "hsspi",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
++ .enable = s3c2450_clkcon_enable_s,
++ .get_rate = s3c2450_getrate_hsspi,
++ .set_rate = s3c2450_setrate_hsspi,
++ .round_rate = s3c2450_roundrate_clksrc4,
++};
++
++/* usbhost
++ *
++ * usb host bus-clock, usually 48MHz to provide USB bus clock timing
++*/
++
++static unsigned long s3c2450_getrate_usbhost(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK;
++ div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2450_setrate_usbhost(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2450_roundrate_clksrc4(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_usb_bus_host = {
++ .name = "usb-bus-host-parent",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .ctrlbit = S3C2443_SCLKCON_USBHOST,
++ .enable = s3c2450_clkcon_enable_s,
++ .get_rate = s3c2450_getrate_usbhost,
++ .set_rate = s3c2450_setrate_usbhost,
++ .round_rate = s3c2450_roundrate_clksrc4,
++};
++
++/* clk_hsmcc_div
++ *
++ * this clock is sourced from epll, and is fed through a divider,
++ * to a mux controlled by sclkcon where either it or a extclk can
++ * be fed to the hsmmc block
++*/
++
++static unsigned long s3c2450_getrate_hsmmc_div(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_HSMMCDIV_MASK;
++ div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2450_setrate_hsmmc_div(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2450_roundrate_clksrc4(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_hsmmc_div = {
++ .name = "hsmmc-div",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .get_rate = s3c2450_getrate_hsmmc_div,
++ .set_rate = s3c2450_setrate_hsmmc_div,
++ .round_rate = s3c2450_roundrate_clksrc4,
++};
++
++static int s3c2450_setparent_hsmmc(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
++
++ clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
++ S3C2443_SCLKCON_HSMMCCLK_EPLL);
++
++ if (parent == &clk_epll)
++ clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
++ else if (parent == &clk_ext)
++ clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
++ else
++ return -EINVAL;
++
++ if (clk->usage > 0) {
++ __raw_writel(clksrc, S3C2443_SCLKCON);
++ }
++
++ clk->parent = parent;
++ return 0;
++}
++
++static int s3c2450_enable_hsmmc(struct clk *clk, int enable)
++{
++ return s3c2450_setparent_hsmmc(clk, clk->parent);
++}
++
++static struct clk clk_hsmmc = {
++ .name = "hsmmc-if",
++ .id = -1,
++ .parent = &clk_hsmmc_div,
++ .enable = s3c2450_enable_hsmmc,
++ .set_parent = s3c2450_setparent_hsmmc,
++};
++
++/* i2s_eplldiv
++ *
++ * this clock is the output from the i2s divisor of esysclk
++*/
++
++static unsigned long s3c2450_getrate_i2s_eplldiv(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_I2SDIV_MASK;
++ div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2450_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2450_roundrate_clksrc16(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_i2s_eplldiv = {
++ .name = "i2s-eplldiv",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .get_rate = s3c2450_getrate_i2s_eplldiv,
++ .set_rate = s3c2450_setrate_i2s_eplldiv,
++ .round_rate = s3c2450_roundrate_clksrc16,
++};
++
++/* i2s-ref
++ *
++ * i2s bus reference clock, selectable from external, esysclk or epllref
++*/
++
++static int s3c2450_setparent_i2s(struct clk *clk, struct clk *parent)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++
++ clksrc &= ~S3C2443_CLKSRC_I2S_MASK;
++
++ if (parent == &clk_epllref)
++ clksrc |= S3C2443_CLKSRC_I2S_EPLLREF;
++ else if (parent == &clk_i2s_ext)
++ clksrc |= S3C2443_CLKSRC_I2S_EXT;
++ else if (parent != &clk_i2s_eplldiv)
++ return -EINVAL;
++
++ clk->parent = parent;
++ __raw_writel(clksrc, S3C2443_CLKSRC);
++
++ return 0;
++}
++
++static struct clk clk_i2s = {
++ .name = "i2s-if",
++ .id = -1,
++ .parent = &clk_i2s_eplldiv,
++ .ctrlbit = S3C2443_SCLKCON_I2SCLK,
++ .enable = s3c2450_clkcon_enable_s,
++ .set_parent = s3c2450_setparent_i2s,
++};
++
++/* cam-if
++ *
++ * camera interface bus-clock, divided down from esysclk
++*/
++
++static unsigned long s3c2450_getrate_cam(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_CAMDIV_MASK;
++ div >>= S3C2443_CLKDIV1_CAMDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2450_setrate_cam(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdiv1 = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2450_roundrate_clksrc16(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdiv1 &= ~S3C2443_CLKDIV1_CAMDIV_MASK;
++ clkdiv1 |= (rate - 1) << S3C2443_CLKDIV1_CAMDIV_SHIFT;
++
++ __raw_writel(clkdiv1, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_cam = {
++ .name = "camif-upll", /* same as 2440 name */
++ .id = -1,
++ .parent = &clk_esysclk,
++ .ctrlbit = S3C2443_SCLKCON_CAMCLK,
++ .enable = s3c2450_clkcon_enable_s,
++ .get_rate = s3c2450_getrate_cam,
++ .set_rate = s3c2450_setrate_cam,
++ .round_rate = s3c2450_roundrate_clksrc16,
++};
++
++static struct clk clk_cam_h = {
++ .name = "camif-hclk",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_CAMIF,
++};
++
++#define CAMDIV_val 26
++
++static int s3c2450_setrate_camera(struct clk *clk, unsigned long rate)
++{
++ unsigned int camclk_div, val, hclkcon;
++ unsigned long src_clk = clk_get_rate(clk->parent);
++
++ if (rate == 4800000) {
++ printk(KERN_INFO "External camera clock is set to 48MHz\n");
++ }
++ else if (rate > 48000000) {
++ printk(KERN_ERR "Invalid camera clock\n");
++ }
++
++ writel(readl(S3C2443_CLKSRC) | (1 << 20), S3C2443_CLKSRC);
++
++ camclk_div = src_clk / rate;
++ printk("Parent clock for Camera = %ld, CAMDIV = %d\n", src_clk, camclk_div);
++
++ val = readl(S3C2443_CLKDIV1);
++ val &= ~(0xf<<CAMDIV_val);
++ writel(val, S3C2443_CLKDIV1);
++
++ val |= ((camclk_div -1) << CAMDIV_val);
++ writel(val, S3C2443_CLKDIV1);
++ val = readl(S3C2443_CLKDIV1);
++
++ return 0;
++}
++
++/* display-if
++ *
++ * display interface clock, divided from esysclk
++*/
++
++static unsigned long s3c2450_getrate_display(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = __raw_readl(S3C2443_CLKDIV1);
++
++ div &= S3C2443_CLKDIV1_DISPDIV_MASK;
++ div >>= S3C2443_CLKDIV1_DISPDIV_SHIFT;
++
++ return parent_rate / (div + 1);
++}
++
++static int s3c2450_setrate_display(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
++
++ rate = s3c2450_roundrate_clksrc256(clk, rate);
++ rate = parent_rate / rate;
++
++ clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
++ clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
++
++ __raw_writel(clkdivn, S3C2443_CLKDIV1);
++ return 0;
++}
++
++static struct clk clk_display = {
++ .name = "display-if",
++ .id = -1,
++ .parent = &clk_esysclk,
++ .ctrlbit = S3C2443_SCLKCON_DISPCLK,
++ .enable = s3c2450_clkcon_enable_s,
++ .get_rate = s3c2450_getrate_display,
++ .set_rate = s3c2450_setrate_display,
++ .round_rate = s3c2450_roundrate_clksrc256,
++};
++
++/* standard clock definitions */
++
++static struct clk init_clocks_disable[] = {
++ {
++ .name = "nand",
++ .id = -1,
++ .parent = &clk_h,
++ }, {
++ .name = "sdi",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_SDI,
++ }, {
++ .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_ADC,
++ }, {
++ .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_IIC,
++ }, {
++ .name = "iis",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_IIS,
++ }, {
++ .name = "spi",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_SPI0,
++ }, {
++ .name = "spi",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_SPI1,
++ }
++};
++
++static struct clk init_clocks[] = {
++ {
++ .name = "dma",
++ .id = 0,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA0,
++ }, {
++ .name = "dma",
++ .id = 1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA1,
++ }, {
++ .name = "dma",
++ .id = 2,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA2,
++ }, {
++ .name = "dma",
++ .id = 3,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA3,
++ }, {
++ .name = "dma",
++ .id = 4,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA4,
++ }, {
++ .name = "dma",
++ .id = 5,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_DMA5,
++ }, {
++ .name = "lcd",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_LCDC,
++ }, {
++ .name = "gpio",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_GPIO,
++ }, {
++ .name = "usb-host",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_USBH,
++ }, {
++ .name = "usb-device",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_USBD,
++ }, {
++ .name = "hsmmc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_HSMMC,
++ }, {
++ .name = "cfc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_CFC,
++ }, {
++ .name = "ssmc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_SSMC,
++ }, {
++ .name = "timers",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_PWMT,
++ }, {
++ .name = "uart",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART0,
++ }, {
++ .name = "uart",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART1,
++ }, {
++ .name = "uart",
++ .id = 2,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART2,
++ }, {
++ .name = "uart",
++ .id = 3,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_UART3,
++ }, {
++ .name = "rtc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c2450_clkcon_enable_p,
++ .ctrlbit = S3C2443_PCLKCON_RTC,
++ }, {
++ .name = "watchdog",
++ .id = -1,
++ .parent = &clk_p,
++ .ctrlbit = S3C2443_PCLKCON_WDT,
++ }, {
++ .name = "usb-bus-host",
++ .id = -1,
++ .parent = &clk_usb_bus_host,
++ }, {
++ .name = "ac97",
++ .id = -1,
++ .parent = &clk_p,
++ .ctrlbit = S3C2443_PCLKCON_AC97,
++ }, {
++ .name = "hsmmc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c2450_clkcon_enable_h,
++ .ctrlbit = S3C2443_HCLKCON_HSMMC
++ }, {
++ .name = "hsmmc-epll",
++ .id = -1,
++ .parent = &clk_epll,
++ }, {
++ .name = "hsmmc-ext",
++ .id = -1,
++ .parent = &clk_ext,
++ .enable = s3c2450_clkcon_enable_s,
++ .ctrlbit = S3C2443_SCLKCON_HSMMCCLK_EXT,
++ .rate = 12 * 1000 * 1000
++ },
++ {
++ .name = "camera",
++ .id = -1,
++ .parent = &clk_cam_h,
++ .enable = s3c2450_clkcon_enable_s,
++ .ctrlbit = S3C2443_SCLKCON_CAMCLK,
++ .set_rate = s3c2450_setrate_camera,
++ },
++};
++
++/* clocks to add where we need to check their parentage */
++
++/* s3c2450_clk_initparents
++ *
++ * Initialise the parents for the clocks that we get at start-time
++*/
++
++static int __init clk_init_set_parent(struct clk *clk, struct clk *parent)
++{
++ printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name);
++ return clk_set_parent(clk, parent);
++}
++
++static void __init s3c2450_clk_initparents(void)
++{
++ unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
++ struct clk *parent;
++
++ switch (clksrc & S3C2443_CLKSRC_EPLLREF_MASK) {
++ case S3C2443_CLKSRC_EPLLREF_EXTCLK:
++ parent = &clk_ext;
++ break;
++
++ case S3C2443_CLKSRC_EPLLREF_XTAL:
++ default:
++ parent = &clk_xtal;
++ break;
++
++ case S3C2443_CLKSRC_EPLLREF_MPLLREF:
++ case S3C2443_CLKSRC_EPLLREF_MPLLREF2:
++ parent = &clk_mpllref;
++ break;
++ }
++
++ clk_init_set_parent(&clk_epllref, parent);
++
++ switch (clksrc & S3C2443_CLKSRC_I2S_MASK) {
++ case S3C2443_CLKSRC_I2S_EXT:
++ parent = &clk_i2s_ext;
++ break;
++
++ case S3C2443_CLKSRC_I2S_EPLLDIV:
++ default:
++ parent = &clk_i2s_eplldiv;
++ break;
++
++ case S3C2443_CLKSRC_I2S_EPLLREF:
++ case S3C2443_CLKSRC_I2S_EPLLREF3:
++ parent = &clk_epllref;
++ }
++
++ clk_init_set_parent(&clk_i2s, &clk_epllref);
++
++ /* esysclk source */
++
++ parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ?
++ &clk_epll : &clk_epllref;
++
++ clk_init_set_parent(&clk_esysclk, parent);
++
++ /* msysclk source */
++
++ if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) {
++ parent = &clk_mpll;
++ } else {
++ parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ?
++ &clk_mdivclk : &clk_mpllref;
++ }
++
++ clk_init_set_parent(&clk_msysclk, parent);
++}
++
++/* armdiv divisor table */
++
++static unsigned int armdiv[16] = {
++ [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
++ [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
++ [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
++ [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
++ [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
++ [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
++ [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
++ [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
++};
++
++static inline unsigned int s3c2450_fclk_div(unsigned long clkcon0)
++{
++ clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
++
++ return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
++}
++
++static inline unsigned long s3c2450_get_prediv(unsigned long clkcon0)
++{
++ clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
++ clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
++
++ return clkcon0 + 1;
++}
++
++/* clocks to add straight away */
++
++static struct clk *clks[] __initdata = {
++ &clk_ext,
++ &clk_epll,
++ &clk_usb_bus_host,
++ &clk_usb_bus,
++ &clk_esysclk,
++ &clk_epllref,
++ &clk_mpllref,
++ &clk_msysclk,
++ &clk_uart,
++ &clk_display,
++ &clk_cam,
++ &clk_i2s_eplldiv,
++ &clk_i2s,
++ &clk_hsspi,
++ &clk_hsmmc_div,
++ &clk_hsmmc,
++ &clk_cam_h,
++};
++
++void __init s3c2450_init_clocks(int xtal)
++{
++ unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
++ unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
++ unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
++ unsigned long pll;
++ unsigned long fclk;
++ unsigned long hclk;
++ unsigned long pclk;
++ struct clk *clkp;
++ int ret;
++ int ptr;
++
++ pll = s3c2443_get_mpll(mpllcon, xtal);
++
++ fclk = pll / s3c2450_fclk_div(clkdiv0);
++ hclk = pll / s3c2450_get_prediv(clkdiv0);
++ hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
++ pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
++
++ s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
++
++ printk("S3C2450: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
++ (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
++ print_mhz(pll), print_mhz(fclk),
++ print_mhz(hclk), print_mhz(pclk));
++
++ s3c2450_clk_initparents();
++
++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
++ clkp = clks[ptr];
++
++ ret = s3c24xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to register clock %s (%d)\n",
++ clkp->name, ret);
++ }
++ }
++
++ clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
++
++ clk_usb_bus.parent = &clk_usb_bus_host;
++
++ /* ensure usb bus clock is within correct rate of 48MHz */
++
++ if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) {
++ printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
++ clk_set_rate(&clk_usb_bus_host, 48*1000*1000);
++ }
++
++ printk("S3C2450: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
++ (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
++ print_mhz(clk_get_rate(&clk_epll)),
++ print_mhz(clk_get_rate(&clk_usb_bus)));
++
++ /* register clocks from clock array */
++
++ clkp = init_clocks;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
++ ret = s3c24xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to register clock %s (%d)\n",
++ clkp->name, ret);
++ }
++ }
++
++ /* We must be careful disabling the clocks we are not intending to
++ * be using at boot time, as subsystems such as the LCD which do
++ * their own DMA requests to the bus can cause the system to lockup
++ * if they where in the middle of requesting bus access.
++ *
++ * Disabling the LCD clock if the LCD is active is very dangerous,
++ * and therefore the bootloader should be careful to not enable
++ * the LCD clock if it is not needed.
++ */
++
++ /* install (and disable) the clocks we do not need immediately */
++
++ clkp = init_clocks_disable;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
++
++ ret = s3c24xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to register clock %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ (clkp->enable)(clkp, 0);
++ }
++}
++
+diff --git a/arch/arm/mach-s3c2450/mach-smdk2450.c b/arch/arm/mach-s3c2450/mach-smdk2450.c
+new file mode 100644
+index 0000000..589089a
+--- /dev/null
++++ b/arch/arm/mach-s3c2450/mach-smdk2450.c
+@@ -0,0 +1,565 @@
++/* linux/arch/arm/mach-s3c2450/mach-smdk2450.c
++ *
++ * Copyright (c) 2007 Samsung Electronics
++ *
++ *
++ * Thanks to Samsung for the loan of an SMDK2450
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/serial_core.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <asm/setup.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/plat-s3c/nand.h>
++#include <asm/plat-s3c/adc.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
++#include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-mem.h>
++
++#include <asm/arch/idle.h>
++#include <asm/arch/fb.h>
++
++#include <asm/plat-s3c24xx/clock.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++#include <asm/plat-s3c24xx/common-smdk.h>
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/arch/hsmmc.h>
++
++#if defined(CONFIG_RTC_DRV_S3C)
++#include <asm/plat-s3c/regs-rtc.h>
++#endif
++
++#include <asm/plat-s3c/regs-adc.h>
++#include <asm/plat-s3c/ts.h>
++
++static struct map_desc smdk2450_iodesc[] __initdata = {
++
++ /* ISA IO Space map (memory space selected by A24) */
++
++ {
++ .virtual = (u32)S3C24XX_VA_ISA_WORD,
++ .pfn = __phys_to_pfn(S3C2410_CS2),
++ .length = 0x10000,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
++ .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
++ .length = SZ_4M,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = (u32)S3C24XX_VA_ISA_BYTE,
++ .pfn = __phys_to_pfn(S3C2410_CS2),
++ .length = 0x10000,
++ .type = MT_DEVICE,
++ }, {
++ .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
++ .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
++ .length = SZ_4M,
++ .type = MT_DEVICE,
++ }
++};
++
++#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
++#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
++#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
++
++static struct s3c24xx_uart_clksrc smdk2450_serial_clocks[] = {
++ [0] = {
++ .name = "pclk",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ },
++ [1] = {
++ .name = "esysclk",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ }
++
++};
++
++static struct s3c2410_uartcfg smdk2450_uartcfgs[] __initdata = {
++ [0] = {
++ .hwport = 0,
++ .flags = 0,
++ .ucon = 0x3c5,
++ .ulcon = 0x03,
++ .ufcon = 0x51,
++ },
++ [1] = {
++ .hwport = 1,
++ .flags = 0,
++ .ucon = 0xfc5,
++ .ulcon = 0x03,
++ .ufcon = 0x51,
++ .clocks = smdk2450_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk2450_serial_clocks),
++ },
++ /* IR port */
++ [2] = {
++ .hwport = 2,
++ .flags = 0,
++ .ucon = 0xfc5,
++ .ulcon = 0x43,
++ .ufcon = 0x51,
++ .clocks = smdk2450_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk2450_serial_clocks),
++ }
++};
++
++static struct platform_device *smdk2450_devices[] __initdata = {
++ &s3c_device_spi0,
++ &s3c_device_spi1,
++ &s3c_device_wdt,
++ &s3c_device_i2c,
++ &s3c_device_rtc,
++ &s3c_device_adc,
++ &s3c_device_ts,
++ &s3c_device_iis,
++ &s3c_device_usbgadget,
++ &s3c_device_usb,
++ &s3c_device_hsmmc0,
++ &s3c_device_hsmmc1,
++ &s3c_device_camif,
++ &s3c_device_smc911x,
++};
++
++static void __init smdk2450_map_io(void)
++{
++ s3c24xx_init_io(smdk2450_iodesc, ARRAY_SIZE(smdk2450_iodesc));
++ s3c24xx_init_clocks(12000000);
++ s3c24xx_init_uarts(smdk2450_uartcfgs, ARRAY_SIZE(smdk2450_uartcfgs));
++}
++
++static void smdk2450_cs89x0_set(void)
++{
++ u32 val;
++
++ val = readl(S3C_BANK_CFG);
++ val &= ~((1<<8)|(1<<9)|(1<<10));
++ writel(val, S3C_BANK_CFG);
++
++ /* Bank1 Idle cycle ctrl. */
++ writel(0xf, S3C_SSMC_SMBIDCYR1);
++
++ /* Bank1 Read Wait State cont. = 14 clk Tacc? */
++ writel(12, S3C_SSMC_SMBWSTRDR1);
++
++ /* Bank1 Write Wait State ctrl. */
++ writel(12, S3C_SSMC_SMBWSTWRR1);
++
++ /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
++ writel(2, S3C_SSMC_SMBWSTOENR1);
++
++ /* Bank1 Write Enable Assertion Delay ctrl. */
++ writel(2, S3C_SSMC_SMBWSTWENR1);
++
++ /* SMWAIT active High, Read Byte Lane Enabl WS1? */
++ val = readl(S3C_SSMC_SMBCR1);
++
++ val |= ((1<<15)|(1<<7));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val |= ((1<<2)|(1<<0));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val &= ~((3<<20)|(3<<12));
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val &= ~(3<<4);
++ writel(val, S3C_SSMC_SMBCR1);
++
++ val = readl(S3C_SSMC_SMBCR1);
++ val |= (1<<4);
++
++ writel(val, S3C_SSMC_SMBCR1);
++
++}
++
++static void smdk2450_smc911x_set(void)
++{
++ u32 val;
++
++ /* Bank1 Idle cycle ctrl. */
++ writel(0xf, S3C_SSMC_SMBIDCYR4);
++
++ /* Bank1 Read Wait State cont. = 14 clk Tacc? */
++ writel(12, S3C_SSMC_SMBWSTRDR4);
++
++ /* Bank1 Write Wait State ctrl. */
++ writel(12, S3C_SSMC_SMBWSTWRR4);
++
++ /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
++ writel(2, S3C_SSMC_SMBWSTOENR4);
++
++ /* Bank1 Write Enable Assertion Delay ctrl. */
++ writel(2, S3C_SSMC_SMBWSTWENR4);
++
++ /* SMWAIT active High, Read Byte Lane Enabl WS1? */
++ val = readl(S3C_SSMC_SMBCR4);
++
++ val |= ((1<<15)|(1<<7));
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val |= ((1<<2)|(1<<0));
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val &= ~((3<<20)|(3<<12));
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val &= ~(3<<4);
++ writel(val, S3C_SSMC_SMBCR4);
++
++ val = readl(S3C_SSMC_SMBCR4);
++ val |= (1<<4);
++
++ writel(val, S3C_SSMC_SMBCR4);
++
++}
++
++
++static void smdk2450_hsmmc_init (void)
++{
++ /* GPIO E (external interrupt) : Chip detect */
++ s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_EINT1); /* GPF1 to EINT1 */
++}
++
++static void __init smdk2450_machine_init(void)
++{
++ smdk2450_smc911x_set();
++ platform_add_devices(smdk2450_devices, ARRAY_SIZE(smdk2450_devices));
++ smdk_machine_init();
++ smdk2450_hsmmc_init();
++}
++
++static void __init smdk2450_fixup (struct machine_desc *desc, struct tag *tags,
++ char **cmdline, struct meminfo *mi)
++{
++ /*
++ * Bank start addresses are not present in the information
++ * passed in from the boot loader. We could potentially
++ * detect them, but instead we hard-code them.
++ */
++ mi->bank[0].start = PHYS_OFFSET;
++
++#if defined(CONFIG_VIDEO_SAMSUNG)
++ mi->bank[0].size = 49*1024*1024;
++#else
++ mi->bank[0].size = 64*1024*1024;
++#endif
++ mi->bank[0].node = 0;
++
++ mi->nr_banks = 1;
++}
++
++
++MACHINE_START(SMDK2450, "SMDK2450")
++ /* Maintainer: Ben Dooks <ben@fluff.org> */
++ .phys_io = S3C2410_PA_UART,
++ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
++ .boot_params = S3C2410_SDRAM_PA + 0x100,
++
++ .init_irq = s3c24xx_init_irq,
++ .map_io = smdk2450_map_io,
++ .fixup = smdk2450_fixup,
++ .init_machine = smdk2450_machine_init,
++ .timer = &s3c24xx_timer,
++MACHINE_END
++
++
++void hsmmc_set_gpio (uint channel, uint width)
++{
++ switch (channel) {
++
++ /* can supports 1 and 4 bit bus */
++ case 0:
++ /* GPIO E : Command, Clock */
++ s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2450_GPE5_SD0_CLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2450_GPE6_SD0_CMD);
++
++ if (width == 1) {
++ /* GPIO E : MMC DATA0[0] */
++ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
++ }
++ else if (width == 4) {
++ /* GPIO E : MMC DATA0[0:3] */
++ s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
++ s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2450_GPE8_SD0_DAT1);
++ s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2450_GPE9_SD0_DAT2);
++ s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2450_GPE10_SD0_DAT3);
++ }
++ break;
++
++ /* can supports 1, 4, and 8 bit bus */
++ case 1:
++ /* GPIO L : Command, Clock */
++ s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2450_GPL8_SD1CMD);
++ s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2450_GPL9_SD1CLK);
++
++ /* GPIO J : Chip detect, LED, Write Protect */
++ s3c2410_gpio_cfgpin(S3C2443_GPJ13, S3C2450_GPJ13_SD1LED);
++ s3c2410_gpio_cfgpin(S3C2443_GPJ14, S3C2450_GPJ14_nSD1CD);
++
++ s3c2410_gpio_cfgpin(S3C2443_GPJ15, S3C2450_GPJ15_nSD1WP); /* write protect enable */
++ s3c2410_gpio_setpin(S3C2443_GPJ15, 1);
++
++ if (width == 1) {
++ /* GPIO L : MMC DATA1[0] */
++ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
++ }
++ else if (width == 4) {
++ /* GPIO L : MMC DATA1[0:3] */
++ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
++ s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
++ s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
++ s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
++ }
++ else if (width == 8) {
++ /* GPIO L : MMC DATA1[0:7] */
++ s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
++ s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
++ s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
++ s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
++
++ s3c2410_gpio_cfgpin(S3C2443_GPL4, S3C2450_GPL4_SD1DAT4);
++ s3c2410_gpio_cfgpin(S3C2443_GPL5, S3C2450_GPL5_SD1DAT5);
++ s3c2410_gpio_cfgpin(S3C2443_GPL6, S3C2450_GPL6_SD1DAT6);
++ s3c2410_gpio_cfgpin(S3C2443_GPL7, S3C2450_GPL7_SD1DAT7);
++ }
++ break;
++
++ default:
++ break;
++ }
++}
++
++
++#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
++ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
++
++/* Channel 0 : added HS-MMC channel */
++struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
++ .hwport = 0,
++ .enabled = 1,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ .clocks[0] = {
++ .name = "hsmmc",
++ .src = 0x1,
++ },
++
++ .clocks[1] = {
++ .name = "esysclk",
++ .src = 0x2,
++ },
++
++ .clocks[2] = {
++ .name = "hsmmc-ext",
++ .src = 0x3,
++ },
++};
++
++/* Channel 1 : default HS-MMC channel */
++struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
++ .hwport = 1, /* H/W Channel 1 */
++ .enabled = 1,
++ .host_caps = HOST_CAPS | MMC_CAP_8_BIT_DATA,
++ .bus_width = 8,
++ //.host_caps = HOST_CAPS,
++ //.bus_width = 4,
++
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ .clocks[0] = {
++ .name = "hsmmc",
++ .src = 0x1,
++ },
++
++ .clocks[1] = {
++ .name = "esysclk",
++ .src = 0x2,
++ },
++
++ .clocks[2] = {
++ .name = "hsmmc-ext",
++ .src = 0x3,
++ },
++};
++
++#if defined(CONFIG_RTC_DRV_S3C)
++/* rtc function */
++unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val)
++{
++ return 0;
++}
++
++unsigned int s3c_rtc_read_alarm_status(void __iomem *base)
++{
++ return (readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN);
++}
++
++void s3c_rtc_set_pie(void __iomem *base, uint to)
++{
++ unsigned int tmp;
++
++ tmp = readb(base + S3C2410_TICNT) & ~S3C2410_TICNT_ENABLE;
++
++ if (to)
++ tmp |= S3C2410_TICNT_ENABLE;
++
++ writeb(tmp, base + S3C2410_TICNT);
++
++}
++
++void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint *s3c_freq)
++{
++ unsigned int tmp;
++
++ tmp = readb(base + S3C2410_TICNT) & S3C2410_TICNT_ENABLE;
++ writew(readw(base + S3C2410_RTCCON) & (~(1<<8)),base + S3C2410_RTCCON);
++ *s3c_freq = freq;
++ tmp |= (128 / freq)-1;
++ writeb(tmp, base + S3C2410_TICNT);
++}
++
++void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en)
++{
++ unsigned int tmp;
++
++ if (!en) {
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp & ~S3C2410_RTCCON_RTCEN, base + S3C2410_RTCCON);
++
++ tmp = readb(base + S3C2410_TICNT);
++ writeb(tmp & ~S3C2410_TICNT_ENABLE, base + S3C2410_TICNT);
++ } else {
++ /* re-enable the device, and check it is ok */
++ if ((readb(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){
++ dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
++
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON);
++ }
++
++ if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){
++ dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
++
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON);
++ }
++
++ if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){
++ dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
++
++ tmp = readb(base + S3C2410_RTCCON);
++ writeb(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON);
++ }
++ }
++}
++#endif
++
++struct s3c_adc_cfg s3c_adc_platform={
++ /* s3c2450 support 12-bit resolution */
++ .delay = 10000,
++ .presc = 49,
++ .resolution = 12,
++};
++
++#if defined(CONFIG_S3C_ADC)
++unsigned int s3c_adc_convert(void __iomem *reg_base,unsigned int s3c_adc_port)
++{
++ unsigned int adc_return;
++ unsigned long data0;
++ unsigned long data1;
++
++ writel(S3C2443_ADCCON_SELMUX(s3c_adc_port), reg_base+S3C2443_ADCMUX);
++
++ writel(readl(reg_base+S3C2410_ADCCON)|S3C2410_ADCCON_ENABLE_START, reg_base+S3C2410_ADCCON);
++
++ do {
++ data0 = readl(reg_base+S3C2410_ADCCON);
++ } while(!(data0 & S3C2410_ADCCON_ECFLG));
++
++ data1 = readl(reg_base+S3C2410_ADCDAT0);
++
++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT;
++
++ return adc_return;
++}
++#endif
++
++struct s3c_ts_mach_info s3c_ts_platform = {
++ .delay = 10000,
++ .presc = 49,
++ .oversampling_shift = 2,
++ .resol_bit = 12,
++};
++
+diff --git a/arch/arm/mach-s3c2450/s3c2450.c b/arch/arm/mach-s3c2450/s3c2450.c
+new file mode 100644
+index 0000000..153c96e
+--- /dev/null
++++ b/arch/arm/mach-s3c2450/s3c2450.c
+@@ -0,0 +1,113 @@
++/* linux/arch/arm/mach-s3c2450/s3c2450.c
++ *
++ * Copyright (c) 2007 Samsung Electronics
++ *
++ *
++ * Samsung S3C2450 Mobile CPU support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/serial_core.h>
++#include <linux/sysdev.h>
++#include <linux/clk.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/arch/reset.h>
++
++#include <asm/plat-s3c24xx/s3c2450.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/common-smdk.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++static struct map_desc s3c2450_iodesc[] __initdata = {
++ IODESC_ENT(WATCHDOG),
++ IODESC_ENT(CLKPWR),
++ IODESC_ENT(TIMER),
++ IODESC_ENT(LCD),
++ IODESC_ENT(EBI),
++ IODESC_ENT(SROMC),
++ IODESC_ENT(CS8900),
++ IODESC_ENT(USBDEV),
++};
++
++struct sysdev_class s3c2450_sysclass = {
++ set_kset_name("s3c2450-core"),
++};
++
++static struct sys_device s3c2450_sysdev = {
++ .cls = &s3c2450_sysclass,
++};
++
++static void s3c2450_hard_reset(void)
++{
++ __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
++}
++
++int __init s3c2450_init(void)
++{
++ printk("S3C2450: Initialising architecture\n");
++
++ s3c24xx_reset_hook = s3c2450_hard_reset;
++
++#if !defined (CONFIG_MTD_NAND_S3C)
++ s3c_device_nand.name = "s3c2412-nand";
++#else
++ s3c_device_nand.name = "s3c-nand";
++#endif
++ /* Rename devices that are specific to s3c2450 */
++ s3c_device_lcd.name = "s3c-lcd";
++
++ /* change WDT IRQ number */
++ s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
++ s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
++
++ return sysdev_register(&s3c2450_sysdev);
++}
++
++void __init s3c2450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
++{
++ s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
++}
++
++/* s3c2450_map_io
++ *
++ * register the standard cpu IO areas, and any passed in from the
++ * machine specific initialisation.
++ */
++
++void __init s3c2450_map_io(struct map_desc *mach_desc, int mach_size)
++{
++ iotable_init(s3c2450_iodesc, ARRAY_SIZE(s3c2450_iodesc));
++ iotable_init(mach_desc, mach_size);
++}
++
++/* need to register class before we actually register the device, and
++ * we also need to ensure that it has been initialised before any of the
++ * drivers even try to use it (even if not on an s3c2450 based system)
++ * as a driver which may support both 2450 and 2440 may try and use it.
++*/
++
++static int __init s3c2450_core_init(void)
++{
++ return sysdev_class_register(&s3c2450_sysclass);
++}
++
++core_initcall(s3c2450_core_init);
+diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig
+new file mode 100644
+index 0000000..17223cf
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/Kconfig
+@@ -0,0 +1,44 @@
++# arch/arm/mach-s3c6400/Kconfig
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++menu "S3C6400 Machines"
++
++config MACH_SMDK6400
++ bool "SMDK6400"
++ select CPU_S3C6400
++ help
++ Say Y here if you are using the SMDK6400
++
++config S3C6400_PDFW
++ tristate "S3C6400 Power Domain Framework"
++ depends on CPU_S3C6400
++ help
++ Install power domain framework for S3C6400
++
++config S3C6400_PDFW_PROC
++ bool "/proc filesystem support for pdfw"
++ depends on CPU_S3C6400 && S3C6400_PDFW
++ help
++ proc file system for S3C6400 Power Domain Framework
++
++config S3C6400_KDPMD
++ tristate "S3C6400 Kernel Dynamic Power Management Daemon"
++ depends on CPU_S3C6400 && S3C6400_PDFW
++ help
++ Install kernel dynamic power management daemon
++endmenu
++
++config CPU_S3C6400
++ bool
++ depends on ARCH_S3C2410
++ select S3C6400_PM if PM
++ help
++ Support for S3C6400 Samsung Mobile CPU based systems.
++
++config S3C6400_PM
++ bool
++ help
++ Internal config node to apply S3C6400 power management
+diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile
+new file mode 100644
+index 0000000..8319eb1
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/Makefile
+@@ -0,0 +1,25 @@
++
++#
++# Makefile for the linux kernel.
++#
++
++# Object file lists.
++obj-y :=
++led-y := leds.o
++obj-n :=
++obj- :=
++
++# S3C6400 support files
++obj-$(CONFIG_CPU_S3C6400) += s3c6400.o clock.o irq.o dma.o
++obj-$(CONFIG_S3C64XX_DMA_SYSFS) += dma-sysfs.o
++obj-$(CONFIG_S3C6400_PM) += pm.o
++
++# Power Management support
++
++# smdk6400 machine specific support
++obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
++
++# LEDs support
++led-$(CONFIG_MACH_SMDK6400) += leds-s3c6400.o
++obj-$(CONFIG_LEDS) += $(led-y)
++
+diff --git a/arch/arm/mach-s3c6400/clock.c b/arch/arm/mach-s3c6400/clock.c
+new file mode 100644
+index 0000000..49c54eb
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/clock.c
+@@ -0,0 +1,698 @@
++/* linux/arch/arm/mach-s3c64xx/clock_s3c6400.c
++ *
++ * Copyright (c) 2004 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2412 Clock control support
++ *
++ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
++ **
++ ** Copyright (C) 2004 ARM Limited.
++ ** Written by Deep Blue Solutions Limited.
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/delay.h>
++
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/mach/map.h>
++
++#include <asm/hardware.h>
++#include <asm/atomic.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/plat-s3c64xx/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++
++#define HCLK_GATING_ON_LIST S3C_CLKCON_HCLK_BUS | S3C_CLKCON_HCLK_DDR1 | S3C_CLKCON_HCLK_DDR0 |\
++ S3C_CLKCON_HCLK_MEM1 | S3C_CLKCON_HCLK_MEM0 | S3C_CLKCON_HCLK_DMA0 |\
++ S3C_CLKCON_HCLK_DMA1 | S3C_CLKCON_HCLK_INTC | S3C_CLKCON_HCLK_LCD |\
++ S3C_CLKCON_HCLK_DHOST | S3C_CLKCON_HCLK_POST0 | S3C_CLKCON_HCLK_MFC
++
++#define PCLK_GATING_ON_LIST S3C_CLKCON_PCLK_GPIO | S3C_CLKCON_PCLK_UART0 | S3C_CLKCON_PCLK_UART1 | S3C_CLKCON_PCLK_MFC
++
++#define SCLK_GATING_ON_LIST S3C_CLKCON_SCLK_UART | S3C_CLKCON_SCLK_LCD27 | S3C_CLKCON_SCLK_LCD | S3C_CLKCON_SCLK_POST1_27 | \
++ S3C_CLKCON_SCLK_POST0_27 | S3C_CLKCON_SCLK_POST1 | S3C_CLKCON_SCLK_POST0 | S3C_CLKCON_SCLK_MFC
++
++/* Select the source clock of USB Host. 0:48MHz, 1:FoutEpll */
++#define S3C_USB_CLKSRC_EPLL 0
++
++
++static int s3c6400_clkcon_enable_h(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_HCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_HCLK_GATE);
++
++ return 0;
++}
++
++static int s3c6400_clkcon_enable_p(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_PCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_PCLK_GATE);
++
++ return 0;
++}
++
++static int s3c6400_clkcon_enable_s(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_SCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_SCLK_GATE);
++
++ return 0;
++}
++
++
++static int s3c6400_clkcon_enable_others(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_OTHERS);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_OTHERS);
++
++ return 0;
++}
++
++static unsigned long s3c6400_clk_getrate(struct clk *clk)
++{
++ /* set clock rate to use in drivers */
++ if (!clk->rate) {
++ if (clk->parent) {
++ clk->rate = clk->parent->rate;
++ }
++ }
++ return clk->rate;
++}
++
++
++static int s3c6400_epll_clk_uart_enable (struct clk *clk, int enable)
++{
++ s3c6400_clkcon_enable_s(clk, enable);
++
++ /* MUXepll : FOUTepll */
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++
++ /* UARTsel : MOUTepll */
++ writel((readl(S3C_CLK_SRC) & ~(0x1 << 13)) | (0 << 13), S3C_CLK_SRC);
++
++ return 0;
++}
++
++
++static int s3c6400_setrate_epll_clk_192m(struct clk *clk, unsigned long rate)
++{
++ writel(S3C_EPLL_EN|S3C_EPLLVAL(32,1,1), S3C_EPLL_CON0);
++ writel(0, S3C_EPLL_CON1);
++ mdelay(5);
++
++ return 0;
++}
++
++static unsigned long s3c6400_getrate_epll_clk_192m(struct clk *clk)
++{
++ s3c6400_setrate_epll_clk_192m(clk, 192000000);
++ clk->rate = 192000000;
++ return clk->rate;
++}
++
++
++static struct clk clk_epll_uart_192m = {
++ .name = "epll_clk_uart_192m",
++ .id = -1,
++ .parent = &clk_epll,
++ .enable = s3c6400_epll_clk_uart_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_UART,
++ .set_rate = s3c6400_setrate_epll_clk_192m,
++ .get_rate = s3c6400_getrate_epll_clk_192m,
++};
++
++
++static unsigned long s3c6400_mpll_get_clk(struct clk *clk)
++{
++ unsigned long mpll_con;
++ unsigned long m = 0;
++ unsigned long p = 0;
++ unsigned long s = 0;
++ unsigned long ret;
++
++ mpll_con = (readl(S3C_MPLL_CON));
++
++ m = (mpll_con >> 16) & 0x3ff;
++ p = (mpll_con >> 8) & 0x3f;
++ s = mpll_con & 0x3;
++
++ ret = (m * (12000000 / (p * (1 << s))));
++
++ return (((readl(S3C_CLK_DIV0) >> 4 ) & 0x1) ? (ret / 2) : ret );
++}
++
++static int s3c6400_mpll_clk_uart_enable (struct clk *clk, int enable)
++{
++ s3c6400_clkcon_enable_s(clk, enable);
++
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++
++ writel((readl(S3C_CLK_SRC) & ~(0x1 << 13)) | (1 << 13), S3C_CLK_SRC);
++
++ return 0;
++}
++
++
++static int s3c6400_setrate_mpll_clk(struct clk *clk, unsigned long rate)
++{
++ writel(readl(S3C_CLK_DIV2) & ~(0xf << 16) , S3C_CLK_DIV2);
++ return 0;
++}
++
++static unsigned long s3c6400_getrate_mpll_clk(struct clk *clk)
++{
++ s3c6400_setrate_mpll_clk(clk,0);
++
++ return s3c6400_mpll_get_clk(clk);
++}
++
++static struct clk clk_mpll_uart = {
++ .name = "mpll_clk_uart",
++ .id = -1,
++ .parent = &clk_mpll,
++ .enable = s3c6400_mpll_clk_uart_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_UART,
++ .set_rate = s3c6400_setrate_mpll_clk,
++ .get_rate = s3c6400_getrate_mpll_clk,
++};
++
++/* For Camera interface */
++static struct clk clk_cam_h = {
++ .name = "camif-hclk",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_CAMIF,
++};
++
++
++#define CAMDIV_val 20
++
++static int s3c6400_setrate_camera(struct clk *clk, unsigned long rate)
++{
++ unsigned int camclk_div, val;
++ unsigned long src_clk = clk_get_rate(clk->parent);
++
++ if (rate == 4800000) {
++ printk(KERN_INFO "External camera clock is set to 48MHz\n");
++ }
++ else if (rate > 48000000) {
++ printk(KERN_ERR "Invalid camera clock\n");
++ }
++
++ camclk_div = src_clk / rate;
++ printk("Parent clock for Camera = %ld, CAMDIV = %d\n", src_clk, camclk_div);
++
++ val = readl(S3C_CLK_DIV0);
++ val &= ~(0xf<<CAMDIV_val);
++ writel(val, S3C_CLK_DIV0);
++
++ /* CAM CLK DIVider Ratio = (EPLL clk)/(camclk_div) */
++ val |= ((camclk_div -1 ) << CAMDIV_val);
++ writel(val, S3C_CLK_DIV0);
++ val = readl(S3C_CLK_DIV0);
++
++ return 0;
++}
++
++
++/* clocks to add straight away */
++
++static struct clk *clks[] __initdata = {
++ &clk_epll_uart_192m,
++ &clk_cam_h,
++ &clk_mpll_uart,
++};
++
++
++static struct clk init_clocks_disable[] = {
++ {
++ .name = "nand",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ //.ctrlbit = S3C_CLKCON_HCLK_NAND,
++ },
++ {
++ .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_TSADC,
++ },
++ {
++ .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIC,
++ },
++ {
++ .name = "iis",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIS0,
++ },
++ {
++ .name = "iis",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIS1,
++ },
++ {
++ .name = "spi",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI0,
++ },
++ {
++ .name = "spi",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI1,
++ }
++};
++
++
++/* standard clock definitions */
++static struct clk init_clocks[] = {
++ /* AHB devices */
++ { .name = "dma 1",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_DMA1,
++ },
++ { .name = "dma 0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_DMA0,
++ },
++ { .name = "lcd",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_LCD,
++ },
++ { .name = "TZIC",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_TZIC,
++ },
++ { .name = "INTC",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_INTC,
++ },
++ { .name = "usb-host",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_UHOST,
++ },
++ { .name = "otg",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_USB
++ },
++ { .name = "hsmmc0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .get_rate = s3c6400_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC0
++ },
++ { .name = "hsmmc1",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .get_rate = s3c6400_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC1
++ },
++ { .name = "hsmmc2",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .get_rate = s3c6400_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC2
++ },
++ { .name = "hclk_mfc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_MFC
++ },
++ { .name = "hclk_post0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_POST0
++ },
++ { .name = "hclk_jpeg",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_JPEG
++ },
++ { .name = "tv_encoder",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_TV
++ },
++ { .name = "tv_scaler",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_SCALER
++ },
++
++ /* register to use HS-MMC clock */
++ { .name = "sclk_48m",
++ .id = -1,
++ .parent = &clk_48m,
++ .enable = s3c6400_clkcon_enable_others,
++ .ctrlbit = 1<<16, /* USB SIG Mask */
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc0",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6400_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc1",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6400_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc2",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6400_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_mfc",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6400_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MFC,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_jpeg",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6400_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_JPEG,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "cfata",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6400_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_IHOST
++ },
++
++ /* APB Devices */
++ { .name = "RTC",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_RTC,
++ },
++ { .name = "GPIO",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_GPIO,
++ },
++ { .name = "UART2",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART2,
++ },
++ { .name = "UART1",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART1,
++ },
++ { .name = "UART0",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART0,
++ },
++ { .name = "timers",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_PWM,
++ },
++ { .name = "watchdog",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_WDT,
++ },
++ { .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIC,
++ },
++ { .name = "spi0",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI0,
++ },
++ { .name = "spi1",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI1,
++ },
++ { .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_TSADC,
++ },
++ { .name = "pclk_mfc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6400_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_MFC,
++ },
++ {
++ .name = "camera",
++ .id = -1,
++ .parent = &clk_cam_h,
++ .enable = s3c6400_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_CAM,
++ .set_rate = s3c6400_setrate_camera,
++ },
++};
++
++void __init s3c6400_init_clocks(int xtal)
++{
++ unsigned long clkdiv0;
++ unsigned long fclk, fclk_org;
++ unsigned long hclkx2;
++ unsigned long hclk;
++ unsigned long pclk;
++ unsigned long epll_clk;
++
++ struct clk *clkp;
++ int ret;
++ int ptr;
++
++ clk_xtal.rate = xtal;
++
++ /* now we've got our machine bits initialised, work out what
++ * clocks we've got */
++
++ /* Changed below lines to support s3c6400 - JaeCheol Lee */
++ fclk = s3c6400_get_pll(__raw_readl(S3C_APLL_CON), xtal);
++
++ clkdiv0 = __raw_readl(S3C_CLK_DIV0);
++
++ fclk /= ((clkdiv0 & S3C_CLKDIVN_APLL_MASK)+1);
++ fclk_org = fclk;
++
++ if(!(__raw_readl(S3C_OTHERS) & 0x80)) {
++ /* Synchronous mode */
++ fclk = s3c6400_get_pll(__raw_readl(S3C_MPLL_CON), xtal);
++ }
++
++ hclkx2 = fclk / (((clkdiv0 & S3C_CLKDIVN_HCLKX2_MASK)>>9)+1);
++
++ hclk = hclkx2 / (((clkdiv0 & S3C_CLKDIVN_HCLK_MASK)>>8)+1);
++
++ /* It should get the divisor from register and then sets the pclk properly */
++ pclk = hclkx2 / (((clkdiv0 & S3C_CLKDIVN_PCLK_MASK)>>12)+1);
++
++ /* print brief summary of clocks, etc */
++ printk("S3C6400: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
++ print_mhz(fclk_org), print_mhz(hclk),
++ print_mhz(pclk));
++
++ /* Default EPLL frequency : 192Mhz */
++ writel(S3C_EPLL_EN|S3C_EPLLVAL(32,1,1), S3C_EPLL_CON0);
++ writel(0, S3C_EPLL_CON1);
++ mdelay(50);
++
++ epll_clk = s3c6400_get_epll(xtal);
++ clk_epll.rate = epll_clk;
++ printk("S3C6400: EPLL %ld.%03ld MHz\n", print_mhz(epll_clk));
++
++ /* initialize hclkx2 by jsgood */
++ clk_hx2.rate = hclkx2;
++
++ /* initialise the clocks here, to allow other things like the
++ * console to use them, and to add new ones after the initialisation
++ */
++
++ s3c64xx_setup_clocks(xtal, fclk_org, hclk, pclk);
++
++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
++ clkp = clks[ptr];
++
++ ret = s3c64xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6400: Failed to register clks : %s (%d)\n",
++ clkp->name, ret);
++ }
++ }
++
++ /* register clocks from clock array */
++ clkp = init_clocks;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
++ ret = s3c64xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6400:Failed to register init_clocks : %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ /* set clock rate to use in drivers */
++ if (!clkp->rate) {
++ if (clkp->parent) {
++ clkp->rate = clkp->parent->rate;
++ }
++ }
++
++ }
++
++ /* We must be careful disabling the clocks we are not intending to
++ * be using at boot time, as subsytems such as the LCD which do
++ * their own DMA requests to the bus can cause the system to lockup
++ * if they where in the middle of requesting bus access.
++ *
++ * Disabling the LCD clock if the LCD is active is very dangerous,
++ * and therefore the bootloader should be careful to not enable
++ * the LCD clock if it is not needed.
++ */
++
++ /* install (and disable) the clocks we do not need immediately */
++
++ clkp = init_clocks_disable;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
++
++ ret = s3c64xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6400: Failed to register init_clocks_disable: %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ (clkp->enable)(clkp, 0);
++ }
++}
++
+diff --git a/arch/arm/mach-s3c6400/dma-sysfs.c b/arch/arm/mach-s3c6400/dma-sysfs.c
+new file mode 100644
+index 0000000..d320ec0
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/dma-sysfs.c
+@@ -0,0 +1,276 @@
++/* linux/arch/arm/mach-bast/dma-sysfs.c
++ *
++ * (c) 2005 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2440 DMA core sysfs interface
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/sysdev.h>
++#include <linux/config.h>
++
++#include <asm/system.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm/mach/dma.h>
++#include <asm/arch/map.h>
++
++
++extern struct sysdev_class dma_sysclass;
++extern s3c24xx_dma_chan_t s3c24xx_chans[S3C24XX_DMA_CHANNELS];
++
++#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
++
++static const char *s3c24xx_dma_decode_state(s3c24xx_dma_state_t state)
++{
++ switch (state) {
++ case S3C24XX_DMA_IDLE:
++ return "Idle";
++ case S3C24XX_DMA_RUNNING:
++ return "Running";
++ case S3C24XX_DMA_PAUSED:
++ return "Paused";
++ default:
++ return "Invalid";
++ }
++
++ return NULL;
++}
++
++static const char *s3c24xx_dma_decode_loadstate(s3c24xx_dma_loadst_t state)
++{
++ switch (state) {
++ case S3C24XX_DMALOAD_NONE:
++ return "Nothing Loaded";
++ case S3C24XX_DMALOAD_1LOADED:
++ return "1 Loaded";
++ case S3C24XX_DMALOAD_1RUNNING:
++ return "1 Running";
++ case S3C24XX_DMALOAD_1LOADED_1RUNNING:
++ return "1 Loaded, 1 Running";
++ default:
++ return "Invalid Load State";
++ }
++
++ return NULL;
++}
++
++static const char *s3c24xx_dma_decode_source(s3c24xx_dmasrc_t source)
++{
++ switch (source) {
++ case S3C24XX_DMASRC_HW:
++ return "Hardware";
++ case S3C24XX_DMASRC_MEM:
++ return "Memory";
++ default:
++ return "Unknown Source";
++ }
++
++ return NULL;
++}
++
++
++struct outbuff {
++ char *buff;
++ int offset;
++ int size;
++};
++
++static inline void outbuf_init(struct outbuff *ob, char *buf, int size)
++{
++ ob->buff = buf;
++ ob->offset = 0;
++ ob->size = size;
++}
++
++static void outbuf_pf(struct outbuff *ob, const char *fmt, ...)
++{
++ va_list va;
++
++ va_start(va, fmt);
++
++ ob->offset += vsnprintf(ob->buff + ob->offset,
++ ob->size - ob->offset,
++ fmt, va);
++ va_end(va);
++}
++
++static void dma_sysfs_showregs(s3c24xx_dma_chan_t *chan, struct outbuff *buf)
++{
++ outbuf_pf(buf, "Hardware Registers:\n\n");
++
++ outbuf_pf(buf, " DISRC \t\t\t%08lx\n", readl(chan->regs + 0x00));
++ outbuf_pf(buf, " DISRCC\t\t\t%08lx\n", readl(chan->regs + 0x04));
++ outbuf_pf(buf, " DIDST \t\t\t%08lx\n", readl(chan->regs + 0x08));
++ outbuf_pf(buf, " DIDSTC\t\t\t%08lx\n", readl(chan->regs + 0x0C));
++ outbuf_pf(buf, " DCON \t\t\t%08lx\n", readl(chan->regs + 0x10));
++ outbuf_pf(buf, " DSTAT \t\t\t%08lx\n", readl(chan->regs + 0x14));
++ outbuf_pf(buf, " DCSRC \t\t\t%08lx\n", readl(chan->regs + 0x18));
++ outbuf_pf(buf, " DCDST \t\t\t%08lx\n", readl(chan->regs + 0x1c));
++ outbuf_pf(buf, " DMTRG \t\t\t%08lx\n", readl(chan->regs + 0x20));
++}
++
++static void dma_sysfs_showbuf(s3c24xx_dma_chan_t *chan,
++ struct outbuff *buf,
++ s3c24xx_dma_buf_t *ptr)
++{
++ if (ptr == NULL)
++ return;
++
++ outbuf_pf(buf, " buff %p: data=%08x, size=%08x, id=%08x\n",
++ ptr, ptr->data, ptr->size, ptr->id);
++}
++
++static void dma_sysfs_showbuffers(s3c24xx_dma_chan_t *chan, struct outbuff *buf)
++{
++ s3c24xx_dma_buf_t *ptr = chan->next;
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ outbuf_pf(buf, "Current Buffer:\n");
++ dma_sysfs_showbuf(chan, buf, chan->curr);
++
++ outbuf_pf(buf, "\nBuffer Queue: %p -> %p\n", chan->next, chan->end);
++
++ for (; ptr != NULL; ptr = ptr->next)
++ dma_sysfs_showbuf(chan, buf, ptr);
++
++ local_irq_restore(flags);
++}
++
++static void dma_sysfs_showstate(s3c24xx_dma_chan_t *chan, struct outbuff *buf)
++{
++ outbuf_pf(buf, "IRQ:\t\t\t\t%d\n", chan->irq);
++ outbuf_pf(buf, "Register Base:\t\t\t0x%08x\n", chan->regs);
++ outbuf_pf(buf, "Address Register:\t\t0x%08lx\n", chan->addr_reg);
++ outbuf_pf(buf, "Hardware Register:\t\t0x%08lx\n", chan->dev_addr);
++ outbuf_pf(buf, "Load Timeout:\t\t\t0x%08x\n", chan->load_timeout);
++ outbuf_pf(buf, "Data Source:\t\t\t%s\n",
++ s3c24xx_dma_decode_source(chan->source));
++
++ outbuf_pf(buf, "Channel State:\t\t\t%s (%d)\n",
++ s3c24xx_dma_decode_state(chan->state), chan->state);
++ outbuf_pf(buf, "Load State:\t\t\t%s (%d)\n",
++ s3c24xx_dma_decode_loadstate(chan->load_state),
++ chan->load_state);
++
++ if (chan->client != NULL) {
++ outbuf_pf(buf, "Claimed by:\t\t\t%s\n",
++ chan->client->name);
++ } else {
++ outbuf_pf(buf, "Claimed by:\t\t\tNo-one\n");
++ }
++}
++
++static inline s3c24xx_dma_chan_t *dev_to_chan(struct sys_device *dev)
++{
++ return &s3c24xx_chans[dev->id];
++}
++
++static ssize_t dma_sysfs_show_regs(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++ dma_sysfs_showregs(cp, &buff);
++
++ return buff.offset;
++}
++
++static ssize_t dma_sysfs_show_state(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++ dma_sysfs_showstate(cp, &buff);
++
++ return buff.offset;
++}
++
++static ssize_t dma_sysfs_show_buffers(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++ dma_sysfs_showbuffers(cp, &buff);
++
++ return buff.offset;
++}
++
++static ssize_t dma_sysfs_show_all(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++
++ dma_sysfs_showstate(cp, &buff);
++ dma_sysfs_showregs(cp, &buff);
++ dma_sysfs_showbuffers(cp, &buff);
++
++ return buff.offset;
++}
++
++static SYSDEV_ATTR(all, S_IRUGO, dma_sysfs_show_all, NULL);
++static SYSDEV_ATTR(regs, S_IRUGO, dma_sysfs_show_regs, NULL);
++static SYSDEV_ATTR(state, S_IRUGO, dma_sysfs_show_state, NULL);
++static SYSDEV_ATTR(buffers, S_IRUGO, dma_sysfs_show_buffers, NULL);
++
++static struct sysdev_attribute *attrs[] = {
++ &attr_all,
++ &attr_regs,
++ &attr_state,
++ &attr_buffers,
++};
++
++static int dma_sysfs_attach(struct sys_device *dev)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(attrs); i++)
++ sysdev_create_file(dev, attrs[i]);
++
++ return 0;
++}
++
++static int dma_sysfs_remove(struct sys_device *dev)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(attrs); i++)
++ sysdev_create_file(dev, attrs[i]);
++
++ return 0;
++}
++
++static struct sysdev_driver dma_sysfs_driver = {
++ .add = dma_sysfs_attach,
++ .remove = dma_sysfs_remove,
++};
++
++static int __init s3c24xx_init_dma_sysfs(void)
++{
++ printk("S3C24XX DMA sysfs support, (c) 2005 Simtec Electronics\n");
++
++ return sysdev_driver_register(&dma_sysclass, &dma_sysfs_driver);
++}
++
++__initcall(s3c24xx_init_dma_sysfs);
++
+diff --git a/arch/arm/mach-s3c6400/dma.c b/arch/arm/mach-s3c6400/dma.c
+new file mode 100644
+index 0000000..179731a
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/dma.c
+@@ -0,0 +1,312 @@
++/* linux/arch/arm/mach-s3c6400/dma.c
++ *
++ * Copyright (c) 2003-2005,2006 Samsung Electronics
++ *
++ * S3C6400 DMA selection
++ *
++ * http://www.samsung.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/sysdev.h>
++#include <linux/serial_core.h>
++
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++#include <asm/io.h>
++
++#include <asm/plat-s3c24xx/dma.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++
++/* DMAC-0 */
++#define MAP0(x) { \
++ [0] = (x) | DMA_CH_VALID, \
++ [1] = (x) | DMA_CH_VALID, \
++ [2] = (x) | DMA_CH_VALID, \
++ [3] = (x) | DMA_CH_VALID, \
++ [4] = (x) | DMA_CH_VALID, \
++ [5] = (x) | DMA_CH_VALID, \
++ [6] = (x) | DMA_CH_VALID, \
++ [7] = (x) | DMA_CH_VALID, \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x), \
++ [19] = (x), \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++/* DMAC-1 */
++#define MAP1(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x), \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x) | DMA_CH_VALID, \
++ [9] = (x) | DMA_CH_VALID, \
++ [10] = (x) | DMA_CH_VALID, \
++ [11] = (x) | DMA_CH_VALID, \
++ [12] = (x) | DMA_CH_VALID, \
++ [13] = (x) | DMA_CH_VALID, \
++ [14] = (x) | DMA_CH_VALID, \
++ [15] = (x) | DMA_CH_VALID, \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x), \
++ [19] = (x), \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++/* SDMAC-0 */
++#define MAP2(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x), \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x) | DMA_CH_VALID, \
++ [17] = (x) | DMA_CH_VALID, \
++ [18] = (x) | DMA_CH_VALID, \
++ [19] = (x) | DMA_CH_VALID, \
++ [20] = (x) | DMA_CH_VALID, \
++ [21] = (x) | DMA_CH_VALID, \
++ [22] = (x) | DMA_CH_VALID, \
++ [23] = (x) | DMA_CH_VALID, \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++/* SDMAC-1 */
++#define MAP3(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x), \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x), \
++ [19] = (x), \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x) | DMA_CH_VALID, \
++ [25] = (x) | DMA_CH_VALID, \
++ [26] = (x) | DMA_CH_VALID, \
++ [27] = (x) | DMA_CH_VALID, \
++ [28] = (x) | DMA_CH_VALID, \
++ [29] = (x) | DMA_CH_VALID, \
++ [30] = (x) | DMA_CH_VALID, \
++ [31] = (x) | DMA_CH_VALID, \
++ }
++
++/* SDMAC-0 */
++#define MAP2_ONENAND(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x) , \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x) , \
++ [19] = (x) | DMA_CH_VALID, \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++static struct s3c24xx_dma_map __initdata s3c6400_dma_mappings[] = {
++
++ [DMACH_I2S_IN] = {
++ .name = "i2s0-in",
++ .channels = MAP0(S3C_DMA0_I2S0_RX),
++ .hw_addr.from = S3C_DMA0_I2S0_RX,
++ .sdma_sel = 1 << S3C_DMA0_I2S0_RX,
++ },
++ [DMACH_I2S_OUT] = {
++ .name = "i2s0-out",
++ .channels = MAP0(S3C_DMA0_I2S0_TX),
++ .hw_addr.to = S3C_DMA0_I2S0_TX,
++ .sdma_sel = 1 << S3C_DMA0_I2S0_TX,
++ },
++ [DMACH_I2S1_IN] = {
++ .name = "i2s1-in",
++ .channels = MAP1(S3C_DMA1_I2S1_RX),
++ .hw_addr.from = S3C_DMA1_I2S1_RX,
++ .sdma_sel = 1 << (S3C_DMA1_I2S1_RX+S3C_DMA1),
++ },
++ [DMACH_I2S1_OUT] = {
++ .name = "i2s1-out",
++ .channels = MAP1(S3C_DMA1_I2S1_TX),
++ .hw_addr.to = S3C_DMA1_I2S1_TX,
++ .sdma_sel = 1 << (S3C_DMA1_I2S1_TX+S3C_DMA1),
++ },
++ [DMACH_SPI0_IN] = {
++ .name = "spi0-in",
++ .channels = MAP0(S3C_DMA0_SPI0_RX),
++ .hw_addr.from = S3C_DMA0_SPI0_RX,
++ .sdma_sel = 1 << S3C_DMA0_SPI0_RX,
++ },
++ [DMACH_SPI0_OUT] = {
++ .name = "spi0-out",
++ .channels = MAP0(S3C_DMA0_SPI0_TX),
++ .hw_addr.to = S3C_DMA0_SPI0_TX,
++ .sdma_sel = 1 << S3C_DMA0_SPI0_TX,
++ },
++ [DMACH_SPI1_IN] = {
++ .name = "spi1-in",
++ .channels = MAP1(S3C_DMA1_SPI1_RX),
++ .hw_addr.from = S3C_DMA1_SPI1_RX,
++ .sdma_sel = 1 << (S3C_DMA1_SPI1_RX+S3C_DMA1),
++ },
++ [DMACH_SPI1_OUT] = {
++ .name = "spi1-out",
++ .channels = MAP1(S3C_DMA1_SPI1_TX),
++ .hw_addr.to = S3C_DMA1_SPI1_TX,
++ .sdma_sel = 1 << (S3C_DMA1_SPI1_TX+S3C_DMA1),
++ },
++ [DMACH_AC97_PCM_OUT] = {
++ .name = "ac97-pcm-out",
++ .channels = MAP1(S3C_DMA1_AC97_PCMOUT),
++ .hw_addr.to = S3C_DMA1_AC97_PCMOUT,
++ .sdma_sel = 1 << (S3C_DMA1_AC97_PCMOUT+S3C_DMA1),
++ },
++ [DMACH_AC97_PCM_IN] = {
++ .name = "ac97-pcm-in",
++ .channels = MAP1(S3C_DMA1_AC97_PCMIN),
++ .hw_addr.from = S3C_DMA1_AC97_PCMIN,
++ .sdma_sel = 1 << (S3C_DMA1_AC97_PCMIN+S3C_DMA1),
++ },
++ [DMACH_AC97_MIC_IN] = {
++ .name = "ac97-mic-in",
++ .channels = MAP1(S3C_DMA1_AC97_MICIN),
++ .hw_addr.from = S3C_DMA1_AC97_MICIN,
++ .sdma_sel = 1 << (S3C_DMA1_AC97_MICIN+S3C_DMA1),
++ },
++ [DMACH_ONENAND_IN] = {
++ .name = "onenand-in",
++ .channels = MAP2_ONENAND(S3C_DMA0_ONENAND_RX),
++ .hw_addr.from = S3C_DMA0_ONENAND_RX,
++ },
++};
++
++static void s3c6400_dma_select(struct s3c2410_dma_chan *chan,
++ struct s3c24xx_dma_map *map)
++{
++ chan->map = map;
++}
++
++static struct s3c24xx_dma_selection __initdata s3c6400_dma_sel = {
++ .select = s3c6400_dma_select,
++ .dcon_mask = 0,
++ .map = s3c6400_dma_mappings,
++ .map_size = ARRAY_SIZE(s3c6400_dma_mappings),
++};
++
++static int __init s3c6400_dma_add(struct sys_device *sysdev)
++{
++ s3c24xx_dma_init(S3C2410_DMA_CHANNELS, IRQ_DMA0, 0x20);
++ return s3c24xx_dma_init_map(&s3c6400_dma_sel);
++}
++
++static struct sysdev_driver s3c6400_dma_driver = {
++ .add = s3c6400_dma_add,
++};
++
++static int __init s3c6400_dma_init(void)
++{
++ return sysdev_driver_register(&s3c6400_sysclass, &s3c6400_dma_driver);
++}
++
++arch_initcall(s3c6400_dma_init);
++
++
+diff --git a/arch/arm/mach-s3c6400/irq.c b/arch/arm/mach-s3c6400/irq.c
+new file mode 100644
+index 0000000..4c3bc3a
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/irq.c
+@@ -0,0 +1,48 @@
++/* linux/arch/arm/mach-s3c6400/irq.c
++ *
++ * Copyright (c) 2006 Samsung Electronics
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++*/
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/ptrace.h>
++#include <linux/sysdev.h>
++
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/plat-s3c24xx/pm.h>
++
++static int s3c6400_irq_add(struct sys_device *sysdev)
++{
++ return 0;
++}
++
++static struct sysdev_driver s3c6400_irq_driver = {
++ .add = s3c6400_irq_add,
++ .suspend = s3c24xx_irq_suspend,
++ .resume = s3c24xx_irq_resume,
++};
++
++static int s3c6400_irq_init(void)
++{
++ return sysdev_driver_register(&s3c6400_sysclass, &s3c6400_irq_driver);
++}
++
++arch_initcall(s3c6400_irq_init);
+diff --git a/arch/arm/mach-s3c6400/kdpmd.c b/arch/arm/mach-s3c6400/kdpmd.c
+new file mode 100644
+index 0000000..632285e
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/kdpmd.c
+@@ -0,0 +1,208 @@
++#include <linux/version.h>
++#include <linux/module.h>
++#if defined(MODVERSIONS)
++#include <linux/modversions.h>
++#endif
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/kthread.h>
++#include <linux/wait.h>
++#include <asm/arch/kdpmd.h>
++#include <asm/arch/pd.h>
++
++#define _DEBUG 1
++//#undef _DEBUG
++
++#ifdef _DEBUG
++#include <linux/time.h>
++#endif
++
++/* global variables for kdpmd */
++DECLARE_MUTEX(kdpmd_sem);
++unsigned int kdpmd_ev;
++wait_queue_head_t kdpmd_wq;
++unsigned int dd_ev;
++wait_queue_head_t dd_wq;
++unsigned int wakeup_source;
++
++struct task_struct *kp;
++
++void handle_timeout(void)
++{
++ printk(KERN_INFO "kdpmd timeout\n");
++ /* dvfs code should go here */
++}
++
++/* this function should be called before device drivers turn on
++ their clocks */
++void handle_drvopen(struct pm_pdtype *pd)
++{
++ if (pd->state == PDSTATE_OFF) {
++ printk("Turning on %s pd\n", pd->name);
++ /* power on and device initializaion */
++ pd_on(pd);
++ }
++ /* clock control is done by the device driver */
++}
++
++/* this function should be called after device drivers turn off
++ their clocks and update pm_devtype->state value
++
++ If this function takes too much time, we may employ separate
++ lists for RUNNING devices and IDLE devices in a power domain */
++void handle_drvclose(struct pm_pdtype *pd)
++{
++ struct list_head *temp;
++ struct pm_devtype *pdev;
++
++ /* check this power domain */
++ list_for_each(temp, &pd->devhead) {
++ pdev = list_entry(temp, struct pm_devtype, entry);
++ if (pdev->state == DEV_RUNNING)
++ return;
++ }
++ /* if all devices under this power domain are not RUNNING */
++ pd_off(pd);
++}
++
++/* this is the thread function that we are executing */
++static int kdpmd_thread(void *data)
++{
++ struct pm_pdtype *pd;
++ unsigned int i = 0;
++#ifdef _DEBUG
++ struct timeval tv1, tv2;
++#endif
++
++ printk("Kernel DPM daemon thread started\n");
++
++ init_waitqueue_head(&kdpmd_wq);
++ init_waitqueue_head(&dd_wq);
++
++ /* an endless loop in which we are doing our work */
++ for (;;) {
++ i++;
++ /* fall asleep, wait for other processes to write to kdpmd_ev */
++ if (wait_event_interruptible(kdpmd_wq, kdpmd_ev != 0) < 0) {
++ printk(KERN_INFO "kdpmd wait returned -\n");
++ return -ERESTARTSYS;
++ }
++
++#ifdef _DEBUG
++ do_gettimeofday(&tv1);
++#endif
++
++ /* What if some other device opens up while servicing other */
++ kdpmd_lock();
++
++ /* We need to do a memory barrier here to be sure that
++ the flags are visible on all CPUs.
++ */
++ mb();
++
++ /* here we are back from sleep, either due to the timeout
++ (2 seconds), or because we caught a signal.
++ */
++ if (kthread_should_stop())
++ break;
++
++ printk(KERN_INFO "kdpmd woke up: %3d\n", i);
++
++ /* find out who woke me up */
++ pd = pd_hashtbl[kdpmd_ev];
++
++ /* find out why woke me up */
++ switch (wakeup_source) {
++ case KDPMD_TIMEOUT :
++ handle_timeout();
++ goto sleepagain;
++ case KDPMD_DRVOPEN :
++ handle_drvopen(pd);
++ break;
++ case KDPMD_DRVCLOSE :
++ handle_drvclose(pd);
++ break;
++ case KDPMD_REMOVE : // handle rmmod call
++ /* wait for 2 sec hoping that kthread_should_stop()
++ will evaluate to true */
++ wait_event_timeout(kdpmd_wq, kdpmd_ev != 0, 2 * HZ);
++ goto sleepagain;
++ default :
++ break;
++ }
++ dd_ev = kdpmd_ev;
++ wake_up_interruptible(&dd_wq);
++sleepagain:
++ kdpmd_ev = 0;
++ kdpmd_unlock();
++
++#ifdef _DEBUG
++ do_gettimeofday(&tv2);
++ printk(KERN_DEBUG " %d sec %d usec\n\n",
++ (int)tv2.tv_sec - (int)tv1.tv_sec,
++ (int)tv2.tv_usec - (int)tv1.tv_usec);
++#endif
++ }
++ /* here we go only in case of termination of the thread */
++ /* returning from the thread here calls the exit functions */
++ return (0);
++}
++
++void kdpmd_set_event(unsigned int devid, unsigned int drv_op)
++{
++ kdpmd_lock();
++ wakeup_source = drv_op;
++ kdpmd_ev = devid;
++ kdpmd_unlock();
++}
++
++void kdpmd_wakeup(void)
++{
++ wake_up_interruptible(&kdpmd_wq);
++}
++
++int kdpmd_wait(unsigned int devid)
++{
++ int ret;
++
++ ret = wait_event_interruptible(dd_wq, dd_ev==devid);
++ dd_ev = 0;
++
++ return ret;
++}
++
++int __init kdpmd_init(void)
++{
++ init_MUTEX(&kdpmd_sem);
++ kp = kthread_run(kdpmd_thread, NULL, "kdpmd");
++ printk(KERN_INFO "kdpmd created\n");
++
++ return (0);
++}
++
++void __exit kdpmd_exit(void)
++{
++ printk(KERN_INFO "kdpmd being destroyed\n");
++ kdpmd_set_event(KDPMD_REMOVE, KDPMD_REMOVE);
++ kdpmd_wakeup();
++ /* terminate the kernel thread */
++ kthread_stop(kp);
++
++ return;
++}
++
++#ifdef MODULE
++module_init(kdpmd_init);
++module_exit(kdpmd_exit);
++#else
++__initcall(kdpmd_init);
++#endif
++
++EXPORT_SYMBOL(kdpmd_set_event);
++EXPORT_SYMBOL(kdpmd_wakeup);
++EXPORT_SYMBOL(kdpmd_wait);
++
++MODULE_AUTHOR("Ikhwan Lee");
++MODULE_LICENSE("Dual BSD/GPL");
++
+diff --git a/arch/arm/mach-s3c6400/leds-s3c6400.c b/arch/arm/mach-s3c6400/leds-s3c6400.c
+new file mode 100644
+index 0000000..96e7774
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/leds-s3c6400.c
+@@ -0,0 +1,117 @@
++/*
++ * linux/arch/arm/mach-s3c6400/leds-s3c6400.c
++ *
++ * Copyright 2008 by Samsung Electronics Incorporated
++ *
++ * There are 16 LEDs on the debug board (all green); four may be used
++ * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
++ *
++ * The "surfer" expansion board and H2 sample board also have two-color
++ * green+red LEDs (in parallel), used here for timer and idle indicators.
++ */
++#include <linux/init.h>
++#include <linux/kernel_stat.h>
++#include <linux/sched.h>
++
++#include <asm/io.h>
++#include <asm/hardware.h>
++#include <asm/leds.h>
++#include <asm/system.h>
++#include <asm/mach-types.h>
++
++#include <asm/arch/regs-gpio.h>
++
++#include "leds.h"
++
++#define LED0 S3C_GPN12
++#define LED1 S3C_GPN13
++#define LED2 S3C_GPN14
++#define LED3 S3C_GPN15
++
++#define LED_STATE_ENABLED 1<<0
++#define LED_STATE_CLAIMED 1<<1
++#define LED_TIMER_ON 1<<2
++#define LED_IDLE 1<<3
++
++
++void smdk6400_leds_event(led_event_t evt)
++{
++ unsigned long flags;
++
++ static u16 led_state, hw_led_state;
++
++ local_irq_save(flags);
++
++ if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
++ goto done;
++
++ switch (evt) {
++ case led_start:
++ led_state |= LED_STATE_ENABLED;
++ break;
++
++ case led_stop:
++ case led_halted:
++ /* all leds off during suspend or shutdown */
++ led_state &= ~LED_STATE_ENABLED;
++ break;
++
++ case led_claim:
++ led_state |= LED_STATE_CLAIMED;
++ hw_led_state = 0;
++ break;
++
++ case led_release:
++ led_state &= ~LED_STATE_CLAIMED;
++ break;
++
++#ifdef CONFIG_LEDS_TIMER
++ case led_timer:
++ led_state ^= LED_TIMER_ON;
++
++ if (led_state & LED_TIMER_ON)
++ gpio_set_value(LED0, 1);
++ else {
++ gpio_set_value(LED0, 0);
++ }
++
++ break;
++#endif
++
++#ifdef CONFIG_LEDS_CPU
++ case led_idle_start:
++ gpio_set_value(LED1, 1);
++ break;
++
++ case led_idle_end:
++ gpio_set_value(LED1, 0);
++ break;
++#endif
++
++ case led_green_on:
++ break;
++ case led_green_off:
++ break;
++
++ case led_amber_on:
++ break;
++ case led_amber_off:
++ break;
++
++ case led_red_on:
++ break;
++ case led_red_off:
++ break;
++
++ case led_blue_on:
++ break;
++ case led_blue_off:
++ break;
++
++ default:
++ break;
++ }
++
++done:
++ local_irq_restore(flags);
++}
+diff --git a/arch/arm/mach-s3c6400/leds.c b/arch/arm/mach-s3c6400/leds.c
+new file mode 100644
+index 0000000..557bd42
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/leds.c
+@@ -0,0 +1,89 @@
++/*
++ * linux/arch/arm/mach-s3c6400/leds.c
++ *
++ * S3C6400 LEDs dispatcher
++ */
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/leds.h>
++#include <asm/mach-types.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/irqs.h>
++#include <asm/mach/irq.h>
++#include "leds.h"
++
++static irqreturn_t eint9_switch(int irq, void *dev_id, struct pt_regs *regs)
++{
++
++ printk("EINT9 interrupt occures!!!\n");
++ return IRQ_HANDLED;
++}
++
++
++static int __init
++s3c6400_leds_init(void)
++{
++ if (machine_is_smdk6400())
++ leds_event = smdk6400_leds_event;
++ else
++ return -1;
++
++ if (machine_is_smdk6400())
++ {
++ /*GPN12~15 used for LED*/
++ /*Set GPN12~15 to output mode */
++ gpio_direction_output(S3C_GPN12);
++ if (gpio_get_pin(S3C_GPN12) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN12 output mode\n");
++ }
++
++ gpio_direction_output(S3C_GPN13);
++ if (gpio_get_pin(S3C_GPN13) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN13 output mode\n");
++ }
++
++ gpio_direction_output(S3C_GPN14);
++ if (gpio_get_pin(S3C_GPN14) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN14 output mode\n");
++ }
++
++ gpio_direction_output(S3C_GPN15);
++ if (gpio_get_pin(S3C_GPN15) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN15 output mode\n");
++ }
++
++ }
++
++ /* Get irqs */
++ set_irq_type(IRQ_EINT9, IRQT_FALLING);
++ gpio_pullup(S3C_GPN9, 0x0);
++ if (request_irq(IRQ_EINT9, eint9_switch, SA_TRIGGER_FALLING, "EINT9", NULL)) {
++ printk(KERN_ERR "leds.c: Could not allocate EINT9 !\n");
++ return -EIO;
++ }
++
++
++ leds_event(led_start);
++ return 0;
++}
++
++__initcall(s3c6400_leds_init);
+diff --git a/arch/arm/mach-s3c6400/leds.h b/arch/arm/mach-s3c6400/leds.h
+new file mode 100644
+index 0000000..8940781
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/leds.h
+@@ -0,0 +1 @@
++extern void smdk6400_leds_event(led_event_t evt);
+diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c6400/mach-smdk6400.c
+new file mode 100644
+index 0000000..6284fd7
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/mach-smdk6400.c
+@@ -0,0 +1,637 @@
++/***********************************************************************
++ *
++ * linux/arch/arm/mach-s3c64xx/smdk6400.c
++ *
++ * $Id: mach-smdk6400.c,v 1.22 2008/08/20 05:52:26 yujiun Exp $
++ *
++ * Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
++ * All rights reserved
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * derived from linux/arch/arm/mach-s3c2410/devs.c, written by
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ ***********************************************************************/
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/setup.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++#include <asm/mach/flash.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++
++#include <asm/arch/regs-mem.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c/nand.h>
++#include <asm/plat-s3c/adc.h>
++
++#include <asm/plat-s3c64xx/s3c6400.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/arch/hsmmc.h>
++
++#include <asm/plat-s3c24xx/common-smdk.h>
++#include <asm/arch-s3c2410/reserved_mem.h>
++
++#if defined(CONFIG_RTC_DRV_S3C)
++#include <asm/plat-s3c/regs-rtc.h>
++#endif
++
++#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS) || defined(CONFIG_USB_OHCI_HCD)
++#include <asm/arch-s3c2410/regs-usb-otg-hs.h>
++#endif
++
++#include <asm/plat-s3c/regs-adc.h>
++#include <asm/plat-s3c/ts.h>
++
++extern struct sys_timer s3c_timer;
++
++static struct map_desc smdk6400_iodesc[] __initdata = {
++ IODESC_ENT(CS8900),
++};
++
++#define DEF_UCON S3C_UCON_DEFAULT
++#define DEF_ULCON S3C_LCON_CS8 | S3C_LCON_PNONE
++#define DEF_UFCON S3C_UFCON_RXTRIG8 | S3C_UFCON_FIFOMODE
++
++
++static struct s3c24xx_uart_clksrc smdk6400_serial_clocks[] = {
++ [0] = {
++ .name = "mpll_clk_uart",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ },
++#if defined (CONFIG_SERIAL_S3C64XX_HS_UART)
++ [1] = {
++ .name = "epll_clk_uart_192m",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 4000000,
++ }
++#endif
++};
++
++
++
++static struct s3c2410_uartcfg smdk6400_uartcfgs[] = {
++ [0] = {
++ .hwport = 0,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6400_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
++ },
++ [1] = {
++ .hwport = 1,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6400_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
++ },
++ [2] = {
++ .hwport = 2,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6400_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
++ },
++ [3] = {
++ .hwport = 3,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6400_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6400_serial_clocks),
++ }
++
++};
++
++
++
++/*add devices as drivers are integrated*/
++static struct platform_device *smdk6400_devices[] __initdata = {
++ &s3c_device_rtc,
++ &s3c_device_ac97,
++ &s3c_device_iis,
++ &s3c_device_adc,
++ &s3c_device_ts,
++ &s3c_device_i2c,
++ &s3c_device_usb,
++ &s3c_device_usbgadget,
++ &s3c_device_usb_otghcd,
++ &s3c_device_tvenc,
++ &s3c_device_tvscaler,
++ &s3c_device_hsmmc0,
++ &s3c_device_hsmmc1,
++ &s3c_device_hsmmc2,
++ &s3c_device_wdt,
++ &s3c_device_jpeg,
++ &s3c_device_vpp,
++ &s3c_device_ide,
++ &s3c_device_mfc,
++ &s3c_device_spi0,
++ &s3c_device_spi1,
++ &s3c_device_camif,
++ &s3c_device_g2d,
++ &s3c_device_keypad,
++};
++
++
++static void __init smdk6400_map_io(void)
++{
++ s3c24xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
++ s3c24xx_init_clocks(0);
++ s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
++}
++
++void smdk6400_cs89x0_set(void)
++{
++ unsigned int tmp;
++
++ tmp = __raw_readl(S3C_SROM_BW);
++ tmp &=~(0xF<<4);
++ tmp |= (1<<7) | (1<<6) | (1<<4);
++ __raw_writel(tmp, S3C_SROM_BW);
++
++ __raw_writel((0x0<<28)|(0x4<<24)|(0xd<<16)|(0x1<<12)|(0x4<<8)|(0x6<<4)|(0x0<<0), S3C_SROM_BC1);
++}
++
++static void __init smdk6400_fixup (struct machine_desc *desc, struct tag *tags,
++ char **cmdline, struct meminfo *mi)
++{
++ /*
++ * Bank start addresses are not present in the information
++ * passed in from the boot loader. We could potentially
++ * detect them, but instead we hard-code them.
++ */
++ mi->bank[0].start = PHYS_OFFSET;
++
++#if defined(CONFIG_RESERVED_MEM_JPEG)
++ mi->bank[0].size = 120*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_POST)
++ mi->bank[0].size = 112*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC)
++ mi->bank[0].size = 122*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC_POST)
++ mi->bank[0].size = 114*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST)
++ mi->bank[0].size = 106*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_CAMERA)
++ mi->bank[0].size = 105*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_POST_CAMERA)
++ mi->bank[0].size = 97*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC_CAMERA)
++ mi->bank[0].size = 107*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC_POST_CAMERA)
++ mi->bank[0].size = 99*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA)
++ mi->bank[0].size = 91*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_CMM_MFC_POST)
++ mi->bank[0].size = 106*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA)
++ mi->bank[0].size = 83*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA)
++ mi->bank[0].size = 91*1024*1024;
++#elif defined(CONFIG_VIDEO_SAMSUNG)
++ mi->bank[0].size = 113*1024*1024;
++#else
++ mi->bank[0].size = 128*1024*1024;
++#endif
++ mi->bank[0].node = 0;
++
++ mi->nr_banks = 1;
++}
++
++
++static void __init smdk6400_machine_init (void)
++{
++ smdk6400_cs89x0_set();
++ platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
++ smdk_machine_init();
++
++ /* jsgood: hsmmc0/1 card detect pin should be high before setup gpio. (GPG6 to Input) */
++ writel(readl(S3C_GPGCON) & 0xf0ffffff, S3C_GPGCON);
++}
++
++MACHINE_START(SMDK6400, "SMDK6400")
++ /* Maintainer: Samsung Electronics */
++ .phys_io = S3C24XX_PA_UART,
++ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
++ .boot_params = S3C_SDRAM_PA + 0x100,
++
++ .init_irq = s3c_init_irq,
++ .map_io = smdk6400_map_io,
++ .fixup = smdk6400_fixup,
++ .timer = &s3c_timer,
++ .init_machine = smdk6400_machine_init,
++MACHINE_END
++
++/*--------------------------------------------------------------
++ * HS-MMC GPIO Set function
++ * the location of this function must be re-considered.
++ * by scsuh
++ *--------------------------------------------------------------*/
++void hsmmc_set_gpio (uint channel, uint width)
++{
++ u32 reg;
++
++ switch (channel) {
++ /* can supports 1 and 4 bit bus */
++ case 0:
++ if (width == 1) {
++ /* MMC CLK0, MMC CMD0, MMC DATA0[0], MMC CDn0 0~2,6 */
++ reg = readl(S3C_GPGCON) & 0xf0fff000;
++ writel(reg | 0x02000222, S3C_GPGCON);
++ reg = readl(S3C_GPGPU) & 0xffffcfc0;
++ writel(reg, S3C_GPGPU);
++ }
++ else if (width == 4) {
++ /* MMC CLK0, MMC CMD0, MMC DATA0[0-3], MMC CDn0 0~6 */
++ reg = readl(S3C_GPGCON) & 0xf0000000;
++ writel(reg | 0x02222222, S3C_GPGCON);
++ reg = readl(S3C_GPGPU) & 0xfffff000;
++ writel(reg, S3C_GPGPU);
++ }
++ break;
++
++ /* can supports 1, 4, and 8 bit bus */
++ case 1:
++ /* MMC CDn1 - 6 */
++ reg = readl(S3C_GPGCON) & 0xf0ffffff;
++ writel(reg | 0x03000000, S3C_GPGCON);
++ reg = readl(S3C_GPGPU) & 0xffffcfff;
++ writel(reg, S3C_GPGPU);
++
++ if (width == 1) {
++ /* MMC CLK1, MMC CMD1, MMC DATA1[0] - 0~2 */
++ reg = readl(S3C_GPH0CON) & 0xfffff000;
++ writel(reg | 0x222, S3C_GPH0CON);
++ reg = readl(S3C_GPHPU) & 0xffffffc0;
++ writel(reg, S3C_GPHPU);
++ }
++ else if (width == 4) {
++ /* MMC CLK1, MMC CMD1, MMC DATA1[0-3] - 0~5 */
++ reg = readl(S3C_GPH0CON) & 0xff000000;
++ writel(reg | 0x00222222, S3C_GPH0CON);
++ reg = readl(S3C_GPHPU) & 0xfffff000;
++ writel(reg, S3C_GPHPU);
++ }
++ else if (width == 8) {
++ /* MMC CLK1, MMC CMD1, MMC DATA1[0-5] - 0~7 */
++ writel(0x22222222, S3C_GPH0CON);
++
++ /* MMC DATA1[6-7] 8~9 */
++ writel(0x00000022, S3C_GPH1CON);
++
++ reg = readl(S3C_GPHPU) & 0xfff00000;
++ writel(reg, S3C_GPHPU);
++ }
++ break;
++
++ /* can supports 1 and 4 bit bus, no irq_cd */
++ case 2:
++ /* MMC CLK2, MMC CMD2 */
++ reg = readl(S3C_GPCCON) & 0xff00ffff;
++ writel(reg | 0x00330000, S3C_GPCCON);
++ reg = readl(S3C_GPCPU) & 0xfffffc3f;
++ writel(reg, S3C_GPCPU);
++
++ if (width == 1) {
++ /* MMC DATA2[0] */
++ reg = readl(S3C_GPH0CON) & 0xf0ffffff;
++ writel(reg | 0x03000000, S3C_GPH0CON);
++ reg = readl(S3C_GPHPU) & 0xfffff3ff;
++ writel(reg, S3C_GPHPU);
++ }
++ else if (width == 4) {
++ /* MMC DATA2[1] */
++ reg = readl(S3C_GPH0CON) & 0x00ffffff;
++ writel(reg | 0x33000000, S3C_GPH0CON);
++
++ /* MMC DATA2[2-3] */
++ writel(0x00000033, S3C_GPH1CON);
++
++ reg = readl(S3C_GPHPU) & 0xfff00fff;
++ writel(reg, S3C_GPHPU);
++ }
++ break;
++
++ default:
++ break;
++ }
++}
++
++/* For host controller's capabilities */
++#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
++ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
++
++struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
++ .hwport = 0,
++ .enabled = 0,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ .clocks[0] = {
++ .name = "hsmmc0",
++ .src = 0x1,
++ },
++
++ .clocks[1] = {
++ .name = "sclk_48m_mmc0",
++ .src = 0x3,
++ },
++};
++
++struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
++ .hwport = 1,
++ .enabled = 1,
++ .host_caps = HOST_CAPS | MMC_CAP_8_BIT_DATA,
++ .bus_width = 8,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ .clocks[0] = {
++ .name = "hsmmc1",
++ .src = 0x1,
++ },
++
++ .clocks[1] = {
++ .name = "sclk_48m_mmc1",
++ .src = 0x3,
++ },
++};
++
++struct s3c_hsmmc_cfg s3c_hsmmc2_platform = {
++ .hwport = 2,
++ .enabled = 0,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00000080, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ .clocks[0] = {
++ .name = "hsmmc2",
++ .src = 0x1,
++ },
++
++ .clocks[1] = {
++ .name = "sclk_48m_mmc2",
++ .src = 0x3,
++ },
++};
++
++#if defined(CONFIG_RTC_DRV_S3C)
++/* rtc function */
++unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val)
++{
++ writeb(val, base + offset);
++
++ return 0;
++}
++
++unsigned int s3c_rtc_read_alarm_status(void __iomem *base)
++{
++ return 1;
++}
++
++void s3c_rtc_set_pie(void __iomem *base, uint to)
++{
++ unsigned int tmp;
++
++ tmp = readw(base + S3C2410_RTCCON) & ~S3C_RTCCON_TICEN;
++
++ if (to)
++ tmp |= S3C_RTCCON_TICEN;
++
++ writew(tmp, base + S3C2410_RTCCON);
++
++}
++
++void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint *s3c_freq)
++{
++ unsigned int tmp;
++
++ tmp = readw(base + S3C2410_RTCCON) & (S3C_RTCCON_TICEN | S3C2410_RTCCON_RTCEN );
++ writew(tmp, base + S3C2410_RTCCON);
++ *s3c_freq = freq;
++ tmp = (32768 / freq)-1;
++ writew(tmp, base + S3C2410_TICNT);
++}
++
++void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en)
++{
++ unsigned int tmp;
++
++ if (!en) {
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp & ~ (S3C2410_RTCCON_RTCEN | S3C_RTCCON_TICEN), base + S3C2410_RTCCON);
++ } else {
++ /* re-enable the device, and check it is ok */
++ if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){
++ dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
++
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON);
++ }
++
++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){
++ dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
++
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON);
++ }
++
++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){
++ dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
++
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON);
++ }
++ }
++}
++#endif
++
++#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS) || defined(CONFIG_USB_OHCI_HCD)
++/* Initializes OTG Phy. */
++void otg_phy_init(u32 otg_phy_clk) {
++
++ writel(readl(S3C_OTHERS)|S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS);
++ writel(0x0, S3C_USBOTG_PHYPWR); /* Power up */
++ writel(otg_phy_clk, S3C_USBOTG_PHYCLK);
++ writel(0x1, S3C_USBOTG_RSTCON);
++
++ udelay(50);
++ writel(0x0, S3C_USBOTG_RSTCON);
++ udelay(50);
++}
++#endif
++
++#ifdef CONFIG_USB_GADGET_S3C_OTGD_HS
++/* OTG PHY Power Off */
++void otg_phy_off(void) {
++ writel(readl(S3C_USBOTG_PHYPWR)|(0x1F<<1), S3C_USBOTG_PHYPWR);
++ writel(readl(S3C_OTHERS)&~S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS);
++}
++#endif
++
++#ifdef CONFIG_USB_OHCI_HCD
++void usb_host_clk_en(int usb_host_clksrc, u32 otg_phy_clk) {
++ switch (usb_host_clksrc) {
++ case 0: /* epll clk */
++ writel((readl(S3C_CLK_SRC)& ~S3C_CLKSRC_UHOST_MASK)
++ |S3C_CLKSRC_EPLL_CLKSEL|S3C_CLKSRC_UHOST_EPLL,
++ S3C_CLK_SRC);
++
++ /* USB host colock divider ratio is 2 */
++ writel((readl(S3C_CLK_DIV1)& ~S3C_CLKDIVN_UHOST_MASK)
++ |S3C_CLKDIV1_USBDIV2, S3C_CLK_DIV1);
++ break;
++ case 1: /* oscillator 48M clk */
++ writel(readl(S3C_CLK_SRC)& ~S3C_CLKSRC_UHOST_MASK, S3C_CLK_SRC);
++ otg_phy_init(otg_phy_clk);
++
++ /* USB host colock divider ratio is 1 */
++ writel(readl(S3C_CLK_DIV1)& ~S3C_CLKDIVN_UHOST_MASK, S3C_CLK_DIV1);
++ break;
++ default:
++ printk(KERN_INFO "Unknown USB Host Clock Source\n");
++ BUG();
++ break;
++ }
++
++ writel(readl(S3C_HCLK_GATE)|S3C_CLKCON_HCLK_UHOST|S3C_CLKCON_HCLK_SECUR,
++ S3C_HCLK_GATE);
++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_UHOST, S3C_SCLK_GATE);
++
++}
++#endif
++
++/* smdk6410 adc common function */
++
++struct s3c_adc_cfg s3c_adc_platform={
++ /* s3c6410 support 12-bit resolution */
++ .delay = 10000,
++ .presc = 49,
++ .resolution = 10,
++};
++
++#if defined(CONFIG_S3C_ADC)
++unsigned int s3c_adc_convert(void __iomem *reg_base,unsigned int s3c_adc_port)
++{
++ unsigned int adc_return;
++ unsigned long data0;
++ unsigned long data1;
++
++ writel(readl(reg_base+S3C2410_ADCCON)|S3C2410_ADCCON_SELMUX(s3c_adc_port), reg_base+S3C2410_ADCCON);
++
++ udelay(10);
++
++ writel(readl(reg_base+S3C2410_ADCCON)|S3C2410_ADCCON_ENABLE_START, reg_base+S3C2410_ADCCON);
++
++ do {
++ data0 = readl(reg_base+S3C2410_ADCCON);
++ } while(!(data0 & S3C2410_ADCCON_ECFLG));
++
++ data1 = readl(reg_base+S3C2410_ADCDAT0);
++
++ adc_return = data1 & S3C2410_ADCDAT0_XPDATA_MASK;
++
++ return adc_return;
++}
++#endif
++
++struct s3c_ts_mach_info s3c_ts_platform = {
++ .delay = 10000,
++ .presc = 49,
++ .oversampling_shift = 2,
++ .resol_bit = 12,
++};
++
++
+diff --git a/arch/arm/mach-s3c6400/pm-s3c6400.c b/arch/arm/mach-s3c6400/pm-s3c6400.c
+new file mode 100644
+index 0000000..d38f507
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/pm-s3c6400.c
+@@ -0,0 +1,794 @@
++/* linux/arch/arm/mach-s3c6400/pm-s3c6400.c
++ *
++ * Copyright (c) 2004 Samsung Electronics
++ *
++ *
++ * S3C Power Manager (Suspend-To-RAM) support
++ *
++ * 2007.04.19 - Modified by JaeCheol Lee <jc.lee@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * Parts based on arch/arm/mach-pxa/pm.c
++ *
++ * Thanks to Dimitry Andric for debugging
++*/
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/suspend.h>
++#include <linux/errno.h>
++#include <linux/time.h>
++#include <linux/interrupt.h>
++#include <linux/crc32.h>
++#include <linux/ioport.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/spinlock.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++
++#include <asm/arch/registers.h>
++#include <asm/mach/time.h>
++
++#include "pm-s3c6400.h"
++
++/* cache functions from arch/arm/mm/cache-v6.S */
++extern void v6_flush_kern_cache_all(void);
++/* for external use */
++unsigned long s3c_pm_flags;
++
++#define PFX "s3c-pm: "
++
++
++static struct sleep_save core_save[] = {
++ SAVE_ITEM(S3C_SDMA_SEL),
++};
++
++/* this lot should be really saved by the IRQ code */
++/* VICXADDRESSXX initilaization to be needed */
++static struct sleep_save irq_save[] = {
++ SAVE_ITEM(S3C_VIC0INTSELECT),
++ SAVE_ITEM(S3C_VIC1INTSELECT),
++ SAVE_ITEM(S3C_VIC0INTENABLE),
++ SAVE_ITEM(S3C_VIC1INTENABLE),
++ SAVE_ITEM(S3C_VIC0SOFTINT),
++ SAVE_ITEM(S3C_VIC1SOFTINT),
++};
++
++static struct sleep_save sromc_save[] = {
++ SAVE_ITEM(S3C_SROM_BW),
++ SAVE_ITEM(S3C_SROM_BC0),
++ SAVE_ITEM(S3C_SROM_BC1),
++ SAVE_ITEM(S3C_SROM_BC2),
++ SAVE_ITEM(S3C_SROM_BC3),
++ SAVE_ITEM(S3C_SROM_BC4),
++ SAVE_ITEM(S3C_SROM_BC5),
++};
++static struct sleep_save gpio_save[] = {
++
++ SAVE_ITEM(S3C_GPK0CON),
++ SAVE_ITEM(S3C_GPK1CON),
++ SAVE_ITEM(S3C_GPKDAT),
++ SAVE_ITEM(S3C_GPKPU),
++
++ SAVE_ITEM(S3C_GPL0CON),
++ SAVE_ITEM(S3C_GPL1CON),
++ SAVE_ITEM(S3C_GPLDAT),
++ SAVE_ITEM(S3C_GPLPU),
++
++ SAVE_ITEM(S3C_GPMCON),
++ SAVE_ITEM(S3C_GPMDAT),
++ SAVE_ITEM(S3C_GPMPU),
++
++ SAVE_ITEM(S3C_GPNCON),
++ SAVE_ITEM(S3C_GPNDAT),
++ SAVE_ITEM(S3C_GPNPU),
++
++ /* External interrupt */
++ SAVE_ITEM(S3C_EINTCON0),
++ SAVE_ITEM(S3C_EINTCON1),
++ SAVE_ITEM(S3C_EINTFLTCON0),
++ SAVE_ITEM(S3C_EINTFLTCON1),
++ SAVE_ITEM(S3C_EINTFLTCON2),
++ SAVE_ITEM(S3C_EINTFLTCON3),
++ SAVE_ITEM(S3C_EINTMASK),
++ SAVE_ITEM(S3C_EINT12CON),
++ SAVE_ITEM(S3C_EINT34CON),
++ SAVE_ITEM(S3C_EINT56CON),
++ SAVE_ITEM(S3C_EINT78CON),
++ SAVE_ITEM(S3C_EINT9CON),
++ SAVE_ITEM(S3C_EINT12FLTCON),
++ SAVE_ITEM(S3C_EINT34FLTCON),
++ SAVE_ITEM(S3C_EINT56FLTCON),
++ SAVE_ITEM(S3C_EINT78FLTCON),
++ SAVE_ITEM(S3C_EINT9FLTCON),
++ SAVE_ITEM(S3C_EINT12MASK),
++ SAVE_ITEM(S3C_EINT34MASK),
++ SAVE_ITEM(S3C_EINT56MASK),
++ SAVE_ITEM(S3C_EINT78MASK),
++ SAVE_ITEM(S3C_EINT9MASK),
++ SAVE_ITEM(S3C_EINT34FLTCON),
++ SAVE_ITEM(S3C_EINT56FLTCON),
++ SAVE_ITEM(S3C_EINT78FLTCON),
++ SAVE_ITEM(S3C_EINT9FLTCON),
++ SAVE_ITEM(S3C_PRIORITY),
++
++ /* GPIO memory map bug in EVT0 */
++ SAVE_ITEM(S3C_GPACON),
++ SAVE_ITEM(S3C_GPADAT),
++ SAVE_ITEM(S3C_GPAPU),
++
++ SAVE_ITEM(S3C_GPBCON),
++ SAVE_ITEM(S3C_GPBDAT),
++ SAVE_ITEM(S3C_GPBPU),
++
++ SAVE_ITEM(S3C_GPCCON),
++ SAVE_ITEM(S3C_GPCDAT),
++ SAVE_ITEM(S3C_GPCPU),
++
++ SAVE_ITEM(S3C_GPDCON),
++ SAVE_ITEM(S3C_GPDDAT),
++ SAVE_ITEM(S3C_GPDPU),
++
++ SAVE_ITEM(S3C_GPECON),
++ SAVE_ITEM(S3C_GPEDAT),
++ SAVE_ITEM(S3C_GPEPU),
++
++ SAVE_ITEM(S3C_GPFCON),
++ SAVE_ITEM(S3C_GPFDAT),
++ SAVE_ITEM(S3C_GPFPU),
++
++ SAVE_ITEM(S3C_GPGCON),
++ SAVE_ITEM(S3C_GPGDAT),
++ SAVE_ITEM(S3C_GPGPU),
++
++ SAVE_ITEM(S3C_GPH0CON),
++ SAVE_ITEM(S3C_GPH1CON),
++ SAVE_ITEM(S3C_GPHDAT),
++ SAVE_ITEM(S3C_GPHPU),
++
++ SAVE_ITEM(S3C_GPICON),
++ SAVE_ITEM(S3C_GPIDAT),
++ SAVE_ITEM(S3C_GPIPU),
++
++ SAVE_ITEM(S3C_GPJCON),
++ SAVE_ITEM(S3C_GPJDAT),
++ SAVE_ITEM(S3C_GPJPU),
++
++
++ SAVE_ITEM(S3C_GPOCON),
++ SAVE_ITEM(S3C_GPODAT),
++ SAVE_ITEM(S3C_GPOPU),
++
++ SAVE_ITEM(S3C_GPPCON),
++ SAVE_ITEM(S3C_GPPDAT),
++ SAVE_ITEM(S3C_GPPPU),
++
++ SAVE_ITEM(S3C_GPQCON),
++ SAVE_ITEM(S3C_GPQDAT),
++ SAVE_ITEM(S3C_GPQPU),
++
++ /* Special register*/
++ SAVE_ITEM(S3C_SPCON),
++
++ /* Memory port control */
++ SAVE_ITEM(S3C_MEM0CONSTOP),
++ SAVE_ITEM(S3C_MEM1CONSTOP),
++ SAVE_ITEM(S3C_MEM0CONSLP0),
++ SAVE_ITEM(S3C_MEM0CONSLP1),
++ SAVE_ITEM(S3C_MEM1CONSLP),
++ SAVE_ITEM(S3C_MEM0DRVCON),
++ SAVE_ITEM(S3C_MEM1DRVCON),
++
++};
++
++static struct sleep_save ts_save[] = {
++ /* Touch Screen */
++ SAVE_ITEM(S3C_ADCDLY),
++ SAVE_ITEM(S3C_ADCTSC),
++ SAVE_ITEM(S3C_ADCCON),
++};
++
++static struct sleep_save lcd_save[] = {
++
++};
++
++
++#define SAVE_UART(va) \
++ SAVE_ITEM((va) + S3C_ULCON), \
++ SAVE_ITEM((va) + S3C_UCON), \
++ SAVE_ITEM((va) + S3C_UFCON), \
++ SAVE_ITEM((va) + S3C_UMCON), \
++ SAVE_ITEM((va) + S3C_UBRDIV), \
++ SAVE_ITEM((va) + S3C_UDIVSLOT), \
++ SAVE_ITEM((va) + S3C_UINTMSK)
++
++
++static struct sleep_save uart_save[] = {
++ SAVE_UART(S3C24XX_VA_UART0),
++ SAVE_UART(S3C24XX_VA_UART1),
++ SAVE_UART(S3C24XX_VA_UART2),
++ SAVE_UART(S3C24XX_VA_UART3),
++};
++
++#if 1
++
++
++/* debug
++ *
++ * we send the debug to printascii() to allow it to be seen if the
++ * system never wakes up from the sleep
++*/
++
++extern void printascii(const char *);
++
++static void pm_dbg(const char *fmt, ...)
++{
++ va_list va;
++ char buff[256];
++
++ va_start(va, fmt);
++ vsprintf(buff, fmt, va);
++ va_end(va);
++
++ printascii(buff);
++}
++
++static void s3c6400_pm_debug_init(void)
++{
++ unsigned long tmp = __raw_readl(S3C_PCLK_GATE);
++
++ /* re-start uart clocks */
++ tmp |= S3C_CLKCON_PCLK_UART0;
++ tmp |= S3C_CLKCON_PCLK_UART1;
++ tmp |= S3C_CLKCON_PCLK_UART2;
++
++ __raw_writel(tmp, S3C_PCLK_GATE);
++ udelay(10);
++}
++
++#define DBG(fmt...) pm_dbg(fmt)
++#else
++#define DBG(fmt...) printk(KERN_DEBUG fmt)
++
++#define s3c6400_pm_debug_init() do { } while(0)
++
++#endif
++
++
++#if defined(CONFIG_S3C6400_PM_CHECK) && CONFIG_S3C6400_PM_CHECK_CHUNKSIZE != 0
++
++/* suspend checking code...
++ *
++ * this next area does a set of crc checks over all the installed
++ * memory, so the system can verify if the resume was ok.
++ *
++ * CONFIG_S3C6400_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
++ * increasing it will mean that the area corrupted will be less easy to spot,
++ * and reducing the size will cause the CRC save area to grow
++*/
++
++#define CHECK_CHUNKSIZE (CONFIG_S3C6400_PM_CHECK_CHUNKSIZE * 1024)
++
++static u32 crc_size; /* size needed for the crc block */
++static u32 *crcs; /* allocated over suspend/resume */
++
++typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
++
++/* s3c6400_pm_run_res
++ *
++ * go thorugh the given resource list, and look for system ram
++*/
++
++static void s3c6400_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
++{
++ while (ptr != NULL) {
++ if (ptr->child != NULL)
++ s3c6400_pm_run_res(ptr->child, fn, arg);
++
++ if ((ptr->flags & IORESOURCE_MEM) &&
++ strcmp(ptr->name, "System RAM") == 0) {
++ DBG("Found system RAM at %08lx..%08lx\n",
++ ptr->start, ptr->end);
++ arg = (fn)(ptr, arg);
++ }
++
++ ptr = ptr->sibling;
++ }
++}
++
++static void s3c6400_pm_run_sysram(run_fn_t fn, u32 *arg)
++{
++ s3c6400_pm_run_res(&iomem_resource, fn, arg);
++}
++
++static u32 *s3c6400_pm_countram(struct resource *res, u32 *val)
++{
++ u32 size = (u32)(res->end - res->start)+1;
++
++ size += CHECK_CHUNKSIZE-1;
++ size /= CHECK_CHUNKSIZE;
++
++ DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
++
++ *val += size * sizeof(u32);
++ return val;
++}
++
++/* s3c6400_pm_prepare_check
++ *
++ * prepare the necessary information for creating the CRCs. This
++ * must be done before the final save, as it will require memory
++ * allocating, and thus touching bits of the kernel we do not
++ * know about.
++*/
++
++static void s3c6400_pm_check_prepare(void)
++{
++ crc_size = 0;
++
++ s3c6400_pm_run_sysram(s3c6400_pm_countram, &crc_size);
++
++ DBG("s3c6400_pm_prepare_check: %u checks needed\n", crc_size);
++
++ crcs = kmalloc(crc_size+4, GFP_KERNEL);
++ if (crcs == NULL)
++ printk(KERN_ERR "Cannot allocated CRC save area\n");
++}
++
++static u32 *s3c6400_pm_makecheck(struct resource *res, u32 *val)
++{
++ unsigned long addr, left;
++
++ for (addr = res->start; addr < res->end;
++ addr += CHECK_CHUNKSIZE) {
++ left = res->end - addr;
++
++ if (left > CHECK_CHUNKSIZE)
++ left = CHECK_CHUNKSIZE;
++
++ *val = crc32_le(~0, phys_to_virt(addr), left);
++ val++;
++ }
++
++ return val;
++}
++
++/* s3c6400_pm_check_store
++ *
++ * compute the CRC values for the memory blocks before the final
++ * sleep.
++*/
++
++static void s3c6400_pm_check_store(void)
++{
++ if (crcs != NULL)
++ s3c6400_pm_run_sysram(s3c6400_pm_makecheck, crcs);
++}
++
++/* in_region
++ *
++ * return TRUE if the area defined by ptr..ptr+size contatins the
++ * what..what+whatsz
++*/
++
++static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
++{
++ if ((what+whatsz) < ptr)
++ return 0;
++
++ if (what > (ptr+size))
++ return 0;
++
++ return 1;
++}
++
++static u32 *s3c6400_pm_runcheck(struct resource *res, u32 *val)
++{
++ void *save_at = phys_to_virt(s3c6400_sleep_save_phys);
++ unsigned long addr;
++ unsigned long left;
++ void *ptr;
++ u32 calc;
++
++ for (addr = res->start; addr < res->end;
++ addr += CHECK_CHUNKSIZE) {
++ left = res->end - addr;
++
++ if (left > CHECK_CHUNKSIZE)
++ left = CHECK_CHUNKSIZE;
++
++ ptr = phys_to_virt(addr);
++
++ if (in_region(ptr, left, crcs, crc_size)) {
++ DBG("skipping %08lx, has crc block in\n", addr);
++ goto skip_check;
++ }
++
++ if (in_region(ptr, left, save_at, 32*4 )) {
++ DBG("skipping %08lx, has save block in\n", addr);
++ goto skip_check;
++ }
++
++ /* calculate and check the checksum */
++ calc = crc32_le(~0, ptr, left);
++ if (calc != *val) {
++ printk(KERN_ERR PFX "Restore CRC error at "
++ "%08lx (%08x vs %08x)\n", addr, calc, *val);
++
++ DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
++ addr, calc, *val);
++ }
++
++ skip_check:
++ val++;
++ }
++
++ return val;
++}
++
++/* s3c6400_pm_check_restore
++ *
++ * check the CRCs after the restore event and free the memory used
++ * to hold them
++*/
++
++static void s3c6400_pm_check_restore(void)
++{
++ if (crcs != NULL) {
++ s3c6400_pm_run_sysram(s3c6400_pm_runcheck, crcs);
++ kfree(crcs);
++ crcs = NULL;
++ }
++}
++
++#else
++
++#define s3c6400_pm_check_prepare() do { } while(0)
++#define s3c6400_pm_check_restore() do { } while(0)
++#define s3c6400_pm_check_store() do { } while(0)
++#endif
++
++/* helper functions to save and restore register state */
++
++void s3c6400_pm_do_save(struct sleep_save *ptr, int count)
++{
++ for (; count > 0; count--, ptr++) {
++ ptr->val = __raw_readl(ptr->reg);
++// DBG("saved %08lx value %08lx\n", ptr->reg, ptr->val);
++ }
++}
++
++/* s3c6400_pm_do_restore
++ *
++ * restore the system from the given list of saved registers
++ *
++ * Note, we do not use DBG() in here, as the system may not have
++ * restore the UARTs state yet
++*/
++
++void s3c6400_pm_do_restore(struct sleep_save *ptr, int count)
++{
++ for (; count > 0; count--, ptr++) {
++// printk(KERN_DEBUG "restore %08lx (restore %08lx, was %08x)\n",
++// ptr->reg, ptr->val, __raw_readl(ptr->reg));
++
++ __raw_writel(ptr->val, ptr->reg);
++ }
++}
++
++/* s3c6400_pm_do_restore_core
++ *
++ * similar to s3c6400_pm_do_restore_core
++ *
++ * WARNING: Do not put any debug in here that may effect memory or use
++ * peripherals, as things may be changing!
++*/
++
++static void s3c6400_pm_do_restore_core(struct sleep_save *ptr, int count)
++{
++ for (; count > 0; count--, ptr++) {
++ __raw_writel(ptr->val, ptr->reg);
++ }
++}
++
++/* s3c6400_pm_show_resume_irqs
++ *
++ * print any IRQs asserted at resume time (ie, we woke from)
++*/
++
++static void s3c6400_pm_show_resume_irqs(int start, unsigned long which,
++ unsigned long mask)
++{
++
++}
++
++/* s3c6400_pm_check_resume_pin
++ *
++ * check to see if the pin is configured correctly for sleep mode, and
++ * make any necessary adjustments if it is not
++*/
++
++static void s3c6400_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
++{
++
++}
++
++/* s3c6400_pm_configure_extint
++ *
++ * configure all external interrupt pins
++*/
++
++static void s3c6400_pm_configure_extint(void)
++{
++ __raw_writel(0xfffffff, S3C_EINTMASK);
++
++// __raw_writel(0xaaaaaaaa, S3C_GPNCON); // Set EINT configuration
++// __raw_writel(0x0, S3C_EINTCON0); // Low level detecting (EINT0~15)
++// __raw_writel(0x0, S3C_EINTCON1); // Low level detecting (EINT16~27)
++
++#if 0
++ __raw_writel(__raw_readl(S3C_EINTPEND), S3C_EINTPEND); // All EINT pending clear
++ do {
++ __raw_writel(__raw_readl(S3C_EINTPEND), S3C_EINTPEND); // All EINT pending clear
++ } while(__raw_readl(S3C_EINTPEND));
++#endif
++}
++
++static void s3c6400_pm_config_gpio(void)
++{
++ /* To reset HS-MMC GPIO */
++ __raw_writel(0x0, S3C_GPGCON);
++}
++
++static inline void s3c6400_poweroff_misc(void)
++{
++ unsigned int temp;
++
++ __raw_writel(0x0, S3C_RTCCON);
++
++ temp = __raw_readl(S3C_ADCCON);
++ __raw_writel(temp |(1<<2), S3C_ADCCON);
++
++ // USB Power Control
++ temp = __raw_readl(S3C_SPCON);
++ __raw_writel(temp|(1<<3), S3C_SPCON);
++
++ temp = __raw_readl(S3C_OTHERS);
++ __raw_writel(temp|(1<<14), S3C_OTHERS);
++}
++
++void s3c6400_setup_keypad_wakeup(void)
++{
++
++}
++
++
++void s3c6400_setup_rtc_wakeup(void)
++{
++#define TESTYEAR (0x5)
++#define TESTMONTH (0x12)
++#define TESTDATE (0x31)
++#define TESTDAY (0x7)
++#define TESTHOUR (0x23)
++#define TESTMIN (0x59)
++#define TESTSEC (0x59)
++
++#define TESTYEAR2 (0x6)
++#define TESTMONTH2 (0x1)
++#define TESTDATE2 (0x1)
++#define TESTHOUR2 (0x0)
++#define TESTMIN2 (0x0)
++#define TESTSEC2 (0x0)
++
++ __raw_writel(1,S3C_RTCCON);
++ __raw_writel(TESTYEAR,S3C_RTCYEAR);
++ __raw_writel(TESTMONTH,S3C_RTCMON);
++ __raw_writel(TESTDATE,S3C_RTCDATE);
++ __raw_writel(TESTDAY,S3C_RTCDAY);
++ __raw_writel(TESTHOUR,S3C_RTCHOUR);
++ __raw_writel(TESTMIN,S3C_RTCMIN);
++ __raw_writel(TESTSEC,S3C_RTCSEC);
++
++ __raw_writel(TESTYEAR2,S3C_ALMYEAR);
++ __raw_writel(TESTMONTH2,S3C_ALMMON);
++ __raw_writel(TESTDATE2,S3C_ALMDATE);
++ __raw_writel(TESTHOUR2,S3C_ALMHOUR);
++ __raw_writel(TESTMIN2,S3C_ALMMIN);
++ __raw_writel((TESTSEC2 + 0x10),S3C_ALMSEC);
++
++ __raw_writel(0x7f,S3C_RTCALM);
++ __raw_writel(0,S3C_RTCCON);
++}
++
++unsigned long sleep_phys_sp(void *sp)
++{
++ return virt_to_phys(sp);
++}
++
++
++#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
++
++
++/* s3c6400_pm_enter
++ *
++ * central control for sleep/resume process
++ */
++static int s3c6400_pm_enter(suspend_state_t state)
++{
++ unsigned long regs_save[16];
++ unsigned long clkcon, irqindex = 0;
++ unsigned int pwr_cfg, sleep_cfg, normal_cfg, hclk_gate, temp, irqno;
++
++ /* ensure the debug is initialised (if enabled) */
++
++// s3c6400_pm_debug_init();
++
++ if (state != PM_SUSPEND_MEM) {
++ printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
++ return -EINVAL;
++ }
++
++ /* prepare check area if configured */
++ s3c6400_pm_check_prepare();
++
++ /* store the physical address of the register recovery block */
++ s3c6400_sleep_save_phys = virt_to_phys(regs_save);
++
++ printk("s3c6400_sleep_save_phys=0x%08lx\n", s3c6400_sleep_save_phys);
++
++ /* save all necessary core registers not covered by the drivers */
++ s3c6400_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
++ s3c6400_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
++ s3c6400_pm_do_save(core_save, ARRAY_SIZE(core_save));
++ s3c6400_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save));
++ s3c6400_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
++ s3c6400_pm_do_save(lcd_save, ARRAY_SIZE(lcd_save));
++ s3c6400_pm_do_save(ts_save, ARRAY_SIZE(ts_save));
++
++ /* ensure INF_REG0 has the resume address */
++ __raw_writel(virt_to_phys(s3c6400_cpu_resume), S3C_INFORM0);
++
++ /* set the irq configuration for wake */
++ s3c6400_pm_configure_extint();
++
++ s3c6400_poweroff_misc();
++ s3c6400_pm_config_gpio();
++
++ s3c6400_pm_check_store();
++
++ __raw_writel(0xffffffff, S3C_VIC0INTENCLEAR);
++ __raw_writel(0xffffffff, S3C_VIC1INTENCLEAR);
++ __raw_writel(0xffffffff, S3C_VIC0SOFTINTCLEAR);
++ __raw_writel(0xffffffff, S3C_VIC1SOFTINTCLEAR);
++
++
++ s3c6400_setup_keypad_wakeup();
++
++// s3c6400_setup_rtc_wakeup();
++
++ __raw_writel(1, S3C_OSC_STABLE);
++ __raw_writel(1, S3C_PWR_STABLE);
++
++ /* Set WFI instruction to SLEEP mode */
++
++ pwr_cfg = __raw_readl(S3C_PWR_CFG);
++ pwr_cfg &= ~(0x60<<0);
++ pwr_cfg |= (0x3<<5);
++ __raw_writel(pwr_cfg, S3C_PWR_CFG);
++
++ sleep_cfg = __raw_readl(S3C_SLEEP_CFG);
++ sleep_cfg &= ~(0x61<<0);
++ __raw_writel(sleep_cfg, S3C_SLEEP_CFG);
++
++
++ __raw_writel((0x0fffffff&~(1<<9)), S3C_EINT_MASK);
++
++ __raw_writel(0x2, S3C_SLPEN);
++
++
++ /* ALL sub block "ON" before enterring sleep mode - EVT0 bug*/
++ __raw_writel(0xffffff00, S3C_NORMAL_CFG);
++
++ /* Open all clock gate to enter sleep mode - EVT0 bug*/
++ __raw_writel(0xffffffff, S3C_HCLK_GATE);
++ __raw_writel(0xffffffff, S3C_PCLK_GATE);
++ __raw_writel(0xffffffff, S3C_SCLK_GATE);
++
++
++ s3c6400_cpu_suspend(regs_save);
++
++ /* restore the cpu state */
++ cpu_init();
++
++ /* restore the system state */
++ s3c6400_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
++ s3c6400_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save));
++ s3c6400_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
++ s3c6400_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
++ s3c6400_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
++ s3c6400_pm_do_restore(lcd_save, ARRAY_SIZE(lcd_save));
++ s3c6400_pm_do_restore(ts_save, ARRAY_SIZE(ts_save));
++
++ temp = __raw_readl(S3C_EINTPEND);
++ __raw_writel(temp, S3C_EINTPEND);
++
++ /* For writing the IRQ number into the VICVECTADDR */
++ for (irqno = IRQ_EINT0_3; irqno <= IRQ_LCD_SYSTEM; irqno++) {
++ __raw_writel(irqno, S3C_VIC0VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ irqindex = 0;
++ for (irqno = IRQ_EINT12_19; irqno <= IRQ_ADC; irqno++) {
++ __raw_writel(irqno, S3C_VIC1VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ s3c6400_pm_debug_init();
++
++ DBG("post sleep, preparing to return\n");
++
++ s3c6400_pm_check_restore();
++
++ /* ok, let's return from sleep */
++ DBG("S3C6400 PM Resume (post-restore)\n");
++
++ return 0;
++
++}
++
++/*
++ * Called after processes are frozen, but before we shut down devices.
++ */
++static int s3c6400_pm_prepare(suspend_state_t state)
++{
++ printk(" preparing for pwrdown\n");
++ return 0;
++}
++
++/*
++ * Called after devices are re-setup, but before processes are thawed.
++ */
++static int s3c6400_pm_finish(suspend_state_t state)
++{
++ return 0;
++}
++
++/*
++ * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
++ */
++static struct pm_ops s3c6400_pm_ops = {
++ .pm_disk_mode = PM_DISK_FIRMWARE,
++ .prepare = s3c6400_pm_prepare,
++ .enter = s3c6400_pm_enter,
++ .finish = s3c6400_pm_finish,
++};
++
++int __init s3c6400_pm_init(void)
++{
++ printk("S3C6400 Power Management, (c) 2006 Samsung Electronics\n");
++
++ enable_irq_wake(IRQ_EINT9);
++ enable_irq_wake(IRQ_RTC_ALARM);
++
++ pm_set_ops(&s3c6400_pm_ops);
++
++ return 0;
++}
++
++module_init(s3c6400_pm_init);
+diff --git a/arch/arm/mach-s3c6400/pm-s3c6400.h b/arch/arm/mach-s3c6400/pm-s3c6400.h
+new file mode 100644
+index 0000000..b5e907a
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/pm-s3c6400.h
+@@ -0,0 +1,67 @@
++/* linux/arch/arm/mach-s3c6400/pm.h
++ *
++ * Copyright (c) 2006 Samsung Electronics
++ * Ryu Euiyoul <steven.ryu@samsung.com>
++ *
++ * Copyright (c) 2004 Simtec Electronics
++ * Written by Ben Dooks, <ben@simtec.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++/* s3c6400_pm_init
++ *
++ * called from board at initialisation time to setup the power
++ * management
++*/
++
++#ifdef CONFIG_PM
++
++extern __init int s3c6400_pm_init(void);
++
++#else
++
++static inline int s3c6400_pm_init(void)
++{
++ return 0;
++}
++#endif
++
++#if 0
++/* configuration for the IRQ mask over sleep */
++extern unsigned long s3c_irqwake_intmask0;
++extern unsigned long s3c_irqwake_intmask1;
++extern unsigned long s3c_irqwake_eintmask;
++
++/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
++extern unsigned long s3c_irqwake_intallow0;
++extern unsigned long s3c_irqwake_intallow1;
++extern unsigned long s3c_irqwake_eintallow;
++
++#endif
++
++/* Flags for PM Control */
++
++extern unsigned long s3c_pm_flags;
++
++/* from sleep.S */
++
++extern void s3c6400_cpu_suspend(unsigned long *saveblk);
++extern void s3c6400_cpu_resume(void);
++
++extern unsigned long s3c6400_sleep_save_phys;
++
++/* sleep save info */
++
++struct sleep_save {
++ unsigned long reg;
++ unsigned long val;
++};
++
++#define SAVE_ITEM(x) \
++ { .reg = (unsigned long)(x) }
++
++extern void s3c6400_pm_do_save(struct sleep_save *ptr, int count);
++extern void s3c6400_pm_do_restore(struct sleep_save *ptr, int count);
+diff --git a/arch/arm/mach-s3c6400/pm.c b/arch/arm/mach-s3c6400/pm.c
+new file mode 100644
+index 0000000..74910d5
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/pm.c
+@@ -0,0 +1,116 @@
++/* linux/arch/arm/mach-s3c6400/pm.c
++ *
++ * Copyright (c) 2006 Samsung Electronics
++ *
++ *
++ * S3C6400 (and compatible) Power Manager (Suspend-To-RAM) support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/init.h>
++#include <linux/suspend.h>
++#include <linux/errno.h>
++#include <linux/time.h>
++#include <linux/sysdev.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++
++#include <asm/mach-types.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c/regs-rtc.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/plat-s3c24xx/pm.h>
++
++#ifdef CONFIG_S3C2410_PM_DEBUG
++extern void pm_dbg(const char *fmt, ...);
++#define DBG(fmt...) pm_dbg(fmt)
++#else
++#define DBG(fmt...) printk(KERN_DEBUG fmt)
++#endif
++
++static void s3c6400_cpu_suspend(void)
++{
++ unsigned long tmp;
++
++ /* issue the standby signal into the pm unit. Note, we
++ * issue a write-buffer drain just in case */
++
++ tmp = 0;
++
++ asm("b 1f\n\t"
++ ".align 5\n\t"
++ "1:\n\t"
++ "mcr p15, 0, %0, c7, c10, 5\n\t"
++ "mcr p15, 0, %0, c7, c10, 4\n\t"
++ "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
++
++ /* we should never get past here */
++
++ panic("sleep resumed to originator?");
++}
++
++static void s3c6400_pm_prepare(void)
++{
++
++}
++
++static int s3c6400_pm_add(struct sys_device *sysdev)
++{
++ pm_cpu_prep = s3c6400_pm_prepare;
++ pm_cpu_sleep = s3c6400_cpu_suspend;
++
++ return 0;
++}
++
++static struct sleep_save s3c6400_sleep[] = {
++
++};
++
++static int s3c6400_pm_suspend(struct sys_device *dev, pm_message_t state)
++{
++ s3c2410_pm_do_save(s3c6400_sleep, ARRAY_SIZE(s3c6400_sleep));
++ return 0;
++}
++
++static int s3c6400_pm_resume(struct sys_device *dev)
++{
++ unsigned long tmp;
++#if 0
++ tmp = __raw_readl(S3C_PWR_CFG);
++ tmp &= ~(0x60<<0);
++ tmp |= (0x1<<5);
++ __raw_writel(tmp, S3C_PWR_CFG);
++#endif
++ s3c2410_pm_do_restore(s3c6400_sleep, ARRAY_SIZE(s3c6400_sleep));
++ return 0;
++}
++
++static struct sysdev_driver s3c6400_pm_driver = {
++ .add = s3c6400_pm_add,
++ .suspend = s3c6400_pm_suspend,
++ .resume = s3c6400_pm_resume,
++};
++
++static __init int s3c6400_pm_init(void)
++{
++ return sysdev_driver_register(&s3c6400_sysclass, &s3c6400_pm_driver);
++}
++
++arch_initcall(s3c6400_pm_init);
++
+diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
+new file mode 100644
+index 0000000..b95f504
+--- /dev/null
++++ b/arch/arm/mach-s3c6400/s3c6400.c
+@@ -0,0 +1,139 @@
++
++/* linux/arch/arm/mach-s3c64xx/s3c6400.c
++ *
++ * Copyright (c) 2006, Samsung Electronics
++ * All rights reserved.
++ *
++ * Samsung S3C6400 Mobile CPU support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * derived from linux/arch/arm/mach-s3c2410/devs.c, written by
++ * Ben Dooks <ben@simtec.co.uk>
++ */
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/clk.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <asm/proc-fns.h>
++#include <asm/arch/idle.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/map.h>
++#include <asm/plat-s3c/nand.h>
++
++//#include <asm/plat-s3c24xx/clock.h>
++#include <asm/plat-s3c64xx/s3c6400.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/common-smdk.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include "pm-s3c6400.h"
++
++/* Serial port registrations */
++
++static struct map_desc s3c6400_iodesc[] __initdata = {
++ IODESC_ENT(SROMC),
++ IODESC_ENT(TIMER),
++ IODESC_ENT(LCD),
++ IODESC_ENT(HOSTIFB),
++};
++
++/* s3c6400_idle
++ *
++ * use the standard idle call by ensuring the idle mode
++ * in power config, then issuing the idle co-processor
++ * instruction
++*/
++
++static void s3c6400_idle(void)
++{
++ unsigned long tmp;
++
++ /* ensure our idle mode is to go to idle */
++
++ /* Set WFI instruction to SLEEP mode */
++
++ tmp = __raw_readl(S3C_PWR_CFG);
++ tmp &= ~(0x1<<5);
++ tmp |= (0x1<<5);
++ __raw_writel(tmp, S3C_PWR_CFG);
++
++ cpu_do_idle();
++}
++
++
++void __init s3c6400_init_uarts(struct s3c2410_uartcfg *cfg, int no)
++{
++ s3c24xx_init_uartdevs("s3c-uart", s3c2410_uart_resources, cfg, no);
++}
++
++struct sysdev_class s3c6400_sysclass = {
++ set_kset_name("s3c6400-core"),
++};
++
++static struct sys_device s3c6400_sysdev = {
++ .cls = &s3c6400_sysclass,
++};
++
++
++static int __init s3c6400_core_init(void)
++{
++ return sysdev_class_register(&s3c6400_sysclass);
++}
++
++core_initcall(s3c6400_core_init);
++
++void __init s3c6400_map_io(struct map_desc *mach_desc, int size)
++{
++ /* register our io-tables */
++ iotable_init(s3c6400_iodesc, ARRAY_SIZE(s3c6400_iodesc));
++ iotable_init(mach_desc, size);
++ /* rename any peripherals used differing from the s3c2412 */
++
++ /* set our idle function */
++
++ s3c24xx_idle = s3c6400_idle;
++}
++
++int __init s3c6400_init(void)
++{
++ int ret;
++
++ printk("s3c6400: Initialising architecture\n");
++
++ ret = sysdev_register(&s3c6400_sysdev);
++
++ if (ret != 0)
++ printk(KERN_ERR "failed to register sysdev for s3c6400\n");
++
++ /* Rename devices that are specific to S3C6400 */
++
++#if defined (CONFIG_S3C_SIR)
++ s3c24xx_uart_src[3]->name = "s3c-irda";
++#endif
++ s3c_device_lcd.name = "s3c-lcd";
++ s3c_device_nand.name = "s3c-nand";
++
++ return ret;
++}
++
+diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
+new file mode 100644
+index 0000000..6b66aa0
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/Kconfig
+@@ -0,0 +1,52 @@
++# arch/arm/mach-s3c6400/Kconfig
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++menu "S3C6410 Machines"
++
++config MACH_SMDK6410
++ bool "SMDK6410"
++ select CPU_S3C6410
++ select MACH_SMDK
++ help
++ Say Y here if you are using the SMDK6410
++
++config MACH_SMDK6430
++ bool "SMDK6430/6431"
++ select CPU_S3C6410
++ select MACH_SMDK
++ help
++ Say Y here if you are using the SMDK6430
++
++config S3C6410_PDFW
++ tristate "S3C6410 Power Domain Framework"
++ depends on CPU_S3C6410
++ help
++ Install power domain framework for S3C6410
++
++config S3C6410_PDFW_PROC
++ bool "/proc filesystem support for pdfw"
++ depends on CPU_S3C6410 && S3C6410_PDFW
++ help
++ proc file system for S3C6410 Power Domain Framework
++
++config S3C6410_KDPMD
++ tristate "S3C6410 Kernel Dynamic Power Management Daemon"
++ depends on CPU_S3C6410 && S3C6410_PDFW
++ help
++ Install kernel dynamic power management daemon
++endmenu
++
++config CPU_S3C6410
++ bool
++ depends on ARCH_S3C2410
++ select S3C6410_PM if PM
++ help
++ Support for S3C6410 Samsung Mobile CPU based systems.
++
++config S3C6410_PM
++ bool
++ help
++ Internal config node to apply S3C6410 power management
+diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
+new file mode 100644
+index 0000000..7e65ecb
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/Makefile
+@@ -0,0 +1,29 @@
++
++#
++# Makefile for the linux kernel.
++#
++
++# Object file lists.
++obj-y :=
++led-y := leds.o
++obj-n :=
++obj- :=
++
++# smdk6410 machine-specific support
++obj-$(CONFIG_CPU_S3C6410) += s3c6410.o clock.o
++obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
++
++obj-$(CONFIG_CPU_S3C6410) += irq.o dma.o
++obj-$(CONFIG_S3C64XX_DMA_SYSFS) += dma-sysfs.o
++obj-$(CONFIG_S3C6410_PM) += pm.o
++
++# Power Management support
++
++# LEDs support
++led-$(CONFIG_MACH_SMDK6410) += leds-s3c6410.o
++obj-$(CONFIG_LEDS) += $(led-y)
++
++# PWM Support
++
++obj-$(CONFIG_PWM) += pwm/
++
+diff --git a/arch/arm/mach-s3c6410/clock.c b/arch/arm/mach-s3c6410/clock.c
+new file mode 100644
+index 0000000..235c07a
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/clock.c
+@@ -0,0 +1,825 @@
++/* linux/arch/arm/mach-s3c6410/clock.c
++ *
++ * Copyright (c) 2004 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2412 Clock control support
++ *
++ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
++ **
++ ** Copyright (C) 2004 ARM Limited.
++ ** Written by Deep Blue Solutions Limited.
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/delay.h>
++
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/mach/map.h>
++
++#include <asm/hardware.h>
++#include <asm/atomic.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/plat-s3c64xx/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#ifdef CONFIG_USB_OHCI_HCD
++#include <asm/arch/regs-usb-otg-hs.h>
++#endif
++
++#define HCLK_GATING_ON_LIST S3C_CLKCON_HCLK_BUS | S3C_CLKCON_HCLK_DDR1 | S3C_CLKCON_HCLK_DDR0 |\
++ S3C_CLKCON_HCLK_MEM1 | S3C_CLKCON_HCLK_MEM0 | S3C_CLKCON_HCLK_DMA0 |\
++ S3C_CLKCON_HCLK_DMA1 | S3C_CLKCON_HCLK_INTC | S3C_CLKCON_HCLK_LCD |\
++ S3C_CLKCON_HCLK_DHOST | S3C_CLKCON_HCLK_POST0 | S3C_CLKCON_HCLK_MFC
++
++#define PCLK_GATING_ON_LIST S3C_CLKCON_PCLK_GPIO | S3C_CLKCON_PCLK_UART0 | S3C_CLKCON_PCLK_UART1 | S3C_CLKCON_PCLK_MFC
++
++#define SCLK_GATING_ON_LIST S3C_CLKCON_SCLK_UART | S3C_CLKCON_SCLK_LCD27 | S3C_CLKCON_SCLK_LCD | S3C_CLKCON_SCLK_POST1_27 | \
++ S3C_CLKCON_SCLK_POST0_27 | S3C_CLKCON_SCLK_POST1 | S3C_CLKCON_SCLK_POST0 | S3C_CLKCON_SCLK_MFC
++
++/* Select the source clock of USB Host. 0:48MHz, 1:FoutEpll */
++#define S3C_USB_CLKSRC_EPLL 0
++
++
++static int s3c6410_clkcon_enable_h(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_HCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_HCLK_GATE);
++
++ return 0;
++}
++
++static int s3c6410_clkcon_enable_p(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_PCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_PCLK_GATE);
++
++ return 0;
++}
++
++static int s3c6410_clkcon_enable_s(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_SCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_SCLK_GATE);
++
++ return 0;
++}
++
++
++static int s3c6410_clkcon_enable_others(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_OTHERS);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_OTHERS);
++
++ return 0;
++}
++
++/*This function returns the virtual address of gating register*/
++ulong clk_get_gate_reg (struct clk *clk)
++{
++ struct clk *parent_clk = clk_get_parent(clk) ;
++
++ if (strcmp(parent_clk->name, "hclk") == 0)
++ return (unsigned long) S3C_HCLK_GATE;
++ else if (strcmp(parent_clk->name, "pclk") == 0)
++ return (unsigned long) S3C_PCLK_GATE;
++ else if (strcmp(parent_clk->name, "clk48m") == 0)
++ return (unsigned long) S3C_OTHERS;
++ else
++ return (unsigned long) S3C_SCLK_GATE;
++}
++
++int s3c_clkcon_enable (struct clk *clk, int enable)
++{
++ unsigned long gate_reg;
++
++ gate_reg = clk_get_gate_reg(clk);
++ s3c_clk_enable(clk->ctrlbit, enable, gate_reg);
++ return 0;
++}
++
++static unsigned long s3c6410_clk_getrate(struct clk *clk)
++{
++ /* set clock rate to use in drivers */
++ if (!clk->rate) {
++ if (clk->parent) {
++ clk->rate = clk->parent->rate;
++ }
++ }
++ return clk->rate;
++}
++
++
++static int s3c6410_epll_clk_uart_enable (struct clk *clk, int enable)
++{
++ s3c6410_clkcon_enable_s(clk, enable);
++
++ /* MUXepll : FOUTepll */
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++
++ /* UARTsel : MOUTepll */
++ writel((readl(S3C_CLK_SRC) & ~(0x1 << 13)) | (0 << 13), S3C_CLK_SRC);
++
++ return 0;
++}
++
++
++static int s3c6410_setrate_epll_clk_192m(struct clk *clk, unsigned long rate)
++{
++ writel(S3C_EPLL_EN|S3C_EPLLVAL(32,1,1), S3C_EPLL_CON0);
++ writel(0, S3C_EPLL_CON1);
++ mdelay(5);
++
++ return 0;
++}
++
++static unsigned long s3c6410_getrate_epll_clk_192m(struct clk *clk)
++{
++ s3c6410_setrate_epll_clk_192m(clk, 192000000);
++ clk->rate = 192000000;
++ return clk->rate;
++}
++
++
++static struct clk clk_epll_uart_192m = {
++ .name = "epll_clk_uart_192m",
++ .id = -1,
++ .parent = &clk_epll,
++ .enable = s3c6410_epll_clk_uart_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_UART,
++ .set_rate = s3c6410_setrate_epll_clk_192m,
++ .get_rate = s3c6410_getrate_epll_clk_192m,
++};
++
++
++static unsigned long s3c6410_mpll_get_clk(struct clk *clk)
++{
++ unsigned long mpll_con;
++ unsigned long m = 0;
++ unsigned long p = 0;
++ unsigned long s = 0;
++ unsigned long ret;
++
++ mpll_con = readl(S3C_MPLL_CON);
++
++ m = (mpll_con >> 16) & 0x3ff;
++ p = (mpll_con >> 8) & 0x3f;
++ s = mpll_con & 0x3;
++
++ ret = (m * (12000000 / (p * (1 << s))));
++
++ return (((readl(S3C_CLK_DIV0) >> 4 ) & 0x1) ? (ret / 2) : ret);
++}
++
++static int s3c6410_clk_mpll_dout_enable(struct clk *clk, int enable)
++{
++ writel(readl(S3C_CLK_SRC) | (0x1 << 1), S3C_CLK_SRC);
++
++ return 0;
++}
++
++static int s3c6410_setrate_clk_mpll_dout(struct clk *clk, unsigned long rate)
++{
++ /* To get 266Mhz */
++ writel((readl(S3C_CLK_DIV0) & ~(0x1 << 4)) | (rate << 4) , S3C_CLK_DIV0);
++
++ return 0;
++}
++
++static unsigned long s3c6410_getrate_clk_mpll_dout(struct clk *clk)
++{
++ s3c6410_setrate_clk_mpll_dout(clk, 1);
++
++ return s3c6410_mpll_get_clk(clk);
++}
++
++static struct clk clk_mpll_dout = {
++ .name = "DOUTmpll",
++ .id = -1,
++ .parent = &clk_mpll,
++ .enable = s3c6410_clk_mpll_dout_enable,
++ .ctrlbit = 0,
++ .set_rate = s3c6410_setrate_clk_mpll_dout,
++ .get_rate = s3c6410_getrate_clk_mpll_dout,
++};
++
++static int s3c6410_clk_mpll_uart_enable(struct clk *clk, int enable)
++{
++ s3c6410_clkcon_enable_s(clk, enable);
++ writel(readl(S3C_CLK_SRC) | (0x1 << 13) | S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++
++ return 0;
++}
++
++static int s3c6410_setrate_clk_mpll_uart(struct clk *clk, unsigned long rate)
++{
++ writel(readl(S3C_CLK_DIV2) & ~(0xf << 16) , S3C_CLK_DIV2);
++
++ return 0;
++}
++
++static unsigned long s3c6410_getrate_clk_mpll_uart(struct clk *clk)
++{
++ s3c6410_setrate_clk_mpll_uart(clk, 0);
++
++ return s3c6410_mpll_get_clk(clk);
++}
++
++static struct clk clk_mpll_uart = {
++ .name = "mpll_clk_uart",
++ .id = -1,
++ .parent = &clk_mpll,
++ .enable = s3c6410_clk_mpll_uart_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_UART,
++ .set_rate = s3c6410_setrate_clk_mpll_uart,
++ .get_rate = s3c6410_getrate_clk_mpll_uart,
++};
++
++
++/* For Camera interface */
++static struct clk clk_cam_h = {
++ .name = "camif-hclk",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_CAMIF,
++};
++
++#define CAMDIV_val 20
++
++static int s3c6410_setrate_camera(struct clk *clk, unsigned long rate)
++{
++ unsigned int camclk_div, val;
++ unsigned long src_clk = clk_get_rate(clk->parent);
++
++ if (rate == 4800000) {
++ printk(KERN_INFO "External camera clock is set to 48MHz\n");
++ }
++ else if (rate > 48000000) {
++ printk(KERN_ERR "Invalid camera clock\n");
++ }
++
++ camclk_div = src_clk / rate;
++
++ val = readl(S3C_CLK_DIV0);
++ val &= ~(0xf<<CAMDIV_val);
++ writel(val, S3C_CLK_DIV0);
++
++ if (camclk_div > 0x10)
++ camclk_div = 0x10;
++
++ printk("Parent clock for Camera = %ld, CAMDIV = %d\n", src_clk, camclk_div);
++
++ /* CAM CLK DIVider Ratio = (EPLL clk)/(camclk_div) */
++ val |= ((camclk_div - 1) << CAMDIV_val);
++ writel(val, S3C_CLK_DIV0);
++ val = readl(S3C_CLK_DIV0);
++
++ return 0;
++}
++
++
++/* For HS-MMC controller */
++static unsigned long s3c6410_getrate_DOUTmpll_hsmmc_clk(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = readl(S3C_CLK_DIV1);
++ div &= ~S3C_CLKDIV1_HSMMCDIV_MASK;
++
++ /* MMC_RATIO = 2+1 */
++ div |= 0x2;
++
++ writel(div, S3C_CLK_DIV1);
++
++ return parent_rate / (0x2 + 1);
++}
++
++static unsigned long s3c6410_getrate_DOUTmpll_hsmmc1_clk(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = readl(S3C_CLK_DIV1);
++ div &= ~S3C_CLKDIV1_HSMMCDIV1_MASK;
++
++ /* MMC1_RATIO = 2+1 */
++ div |= (0x2<<S3C_CLKDIV1_HSMMCDIV1_SHIFT);
++
++ writel(div, S3C_CLK_DIV1);
++
++ return parent_rate / (0x2 + 1);
++}
++
++static struct clk clk_hsmmc_DOUTmpll_mmc0 = {
++ .name = "sclk_DOUTmpll_mmc0",
++ .id = -1,
++ .parent = &clk_mpll_dout,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC0,
++ .get_rate = s3c6410_getrate_DOUTmpll_hsmmc_clk,
++ .usage = 0,
++};
++
++static struct clk clk_hsmmc_DOUTmpll_mmc1 = {
++ .name = "sclk_DOUTmpll_mmc1",
++ .id = -1,
++ .parent = &clk_mpll_dout,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC1,
++ .get_rate = s3c6410_getrate_DOUTmpll_hsmmc1_clk,
++ .usage = 0,
++};
++
++static struct clk clk_hsmmc_DOUTmpll_mmc2 = {
++ .name = "sclk_DOUTmpll_mmc2",
++ .id = -1,
++ .parent = &clk_mpll_dout,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC2,
++ .get_rate = s3c6410_getrate_DOUTmpll_hsmmc_clk,
++ .usage = 0,
++};
++
++
++
++/* clocks to add straight away */
++
++static struct clk *clks[] __initdata = {
++ &clk_epll_uart_192m,
++ &clk_cam_h,
++ &clk_mpll_dout,
++ &clk_mpll_uart,
++ &clk_hsmmc_DOUTmpll_mmc0,
++ &clk_hsmmc_DOUTmpll_mmc1,
++ &clk_hsmmc_DOUTmpll_mmc2,
++};
++
++
++static struct clk init_clocks_disable[] = {
++ {
++ .name = "nand",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ //.ctrlbit = S3C_CLKCON_HCLK_NAND,
++ },
++ {
++ .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_TSADC,
++ },
++ {
++ .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIC,
++ },
++ {
++ .name = "iis",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIS0,
++ },
++ {
++ .name = "iis",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIS1,
++ },
++ {
++ .name = "spi",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI0,
++ },
++ {
++ .name = "spi",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI1,
++ }
++};
++
++
++/* standard clock definitions */
++static struct clk init_clocks[] = {
++ /* AHB devices */
++ { .name = "dma 1",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_DMA1,
++ },
++ { .name = "dma 0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_DMA0,
++ },
++ { .name = "lcd",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_LCD,
++ },
++ { .name = "TZIC",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_TZIC,
++ },
++ { .name = "INTC",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_INTC,
++ },
++ { .name = "usb-host",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_UHOST,
++ },
++ { .name = "otg",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_USB
++ },
++ { .name = "hsmmc0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .get_rate = s3c6410_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC0
++ },
++ { .name = "hsmmc1",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .get_rate = s3c6410_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC1
++ },
++ { .name = "hsmmc2",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .get_rate = s3c6410_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC2
++ },
++ { .name = "hclk_mfc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_MFC
++ },
++ { .name = "hclk_post0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_POST0
++ },
++ { .name = "hclk_jpeg",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_JPEG
++ },
++ { .name = "tv_encoder",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_TV
++ },
++ { .name = "tv_scaler",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_SCALER
++ },
++
++ /* register to use HS-MMC clock */
++ { .name = "sclk_48m",
++ .id = -1,
++ .parent = &clk_48m,
++ .enable = s3c6410_clkcon_enable_others,
++ .ctrlbit = 1<<16, /* USB SIG Mask */
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc0",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc1",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc2",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_mfc",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MFC,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_jpeg",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_JPEG,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "cfata",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_IHOST
++ },
++
++ /* APB Devices */
++ { .name = "RTC",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_RTC,
++ },
++ { .name = "GPIO",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_GPIO,
++ },
++ { .name = "UART2",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART2,
++ },
++ { .name = "UART1",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART1,
++ },
++ { .name = "UART0",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART0,
++ },
++ { .name = "timers",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_PWM,
++ },
++ { .name = "watchdog",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_WDT,
++ },
++ { .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIC,
++ },
++ { .name = "spi0",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI0,
++ },
++ { .name = "spi1",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI1,
++ },
++ { .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_TSADC,
++ },
++ { .name = "pclk_mfc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_MFC,
++ },
++ {
++ .name = "camera",
++ .id = -1,
++ .parent = &clk_hx2,
++ .enable = s3c_clkcon_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_CAM,
++ .set_rate = s3c6410_setrate_camera,
++ },
++};
++
++void __init s3c6410_init_clocks(int xtal)
++{
++ unsigned long clkdiv0;
++ unsigned long fclk, fclk_org;
++ unsigned long hclkx2;
++ unsigned long hclk;
++ unsigned long pclk;
++ unsigned long epll_clk;
++
++ struct clk *clkp;
++ int ret;
++ int ptr;
++
++ clk_xtal.rate = xtal;
++
++ /* now we've got our machine bits initialised, work out what
++ * clocks we've got */
++
++ /* Changed below lines to support s3c6400 - JaeCheol Lee */
++ fclk = s3c6400_get_pll(__raw_readl(S3C_APLL_CON), xtal);
++
++ clkdiv0 = __raw_readl(S3C_CLK_DIV0);
++
++ fclk /= ((clkdiv0 & S3C_CLKDIVN_APLL_MASK)+1);
++ fclk_org = fclk;
++
++ if(!(__raw_readl(S3C_OTHERS) & 0x40)) {
++ /* Synchronous mode */
++ fclk = s3c6400_get_pll(__raw_readl(S3C_MPLL_CON), xtal);
++ }
++
++ hclkx2 = fclk / (((clkdiv0 & S3C_CLKDIVN_HCLKX2_MASK)>>9)+1);
++
++ hclk = hclkx2 / (((clkdiv0 & S3C_CLKDIVN_HCLK_MASK)>>8)+1);
++
++ /* It should get the divisor from register and then sets the pclk properly */
++ pclk = hclkx2 / (((clkdiv0 & S3C_CLKDIVN_PCLK_MASK)>>12)+1);
++
++ /* print brief summary of clocks, etc */
++ printk("S3C6410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
++ print_mhz(fclk_org), print_mhz(hclk),
++ print_mhz(pclk));
++
++ /* Default EPLL frequency : 192Mhz */
++ writel(S3C_EPLL_EN|S3C_EPLLVAL(32,1,1), S3C_EPLL_CON0);
++ writel(0, S3C_EPLL_CON1);
++ mdelay(50);
++
++ epll_clk = s3c6400_get_epll(xtal);
++ clk_epll.rate = epll_clk;
++ printk("S3C6410: EPLL %ld.%03ld MHz\n", print_mhz(epll_clk));
++
++ /* initialize hclkx2 by jsgood */
++ clk_hx2.rate = hclkx2;
++
++ /* initialise the clocks here, to allow other things like the
++ * console to use them, and to add new ones after the initialisation
++ */
++
++ s3c64xx_setup_clocks(xtal, fclk_org, hclk, pclk);
++
++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
++ clkp = clks[ptr];
++
++ ret = s3c64xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6410: Failed to register clks : %s (%d)\n",
++ clkp->name, ret);
++ }
++ }
++
++ /* register clocks from clock array */
++ clkp = init_clocks;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
++ ret = s3c64xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6410: Failed to register init_clocks : %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ /* set clock rate to use in drivers */
++ if (!clkp->rate) {
++ if (clkp->parent) {
++ clkp->rate = clkp->parent->rate;
++ }
++ }
++
++ }
++
++ /* We must be careful disabling the clocks we are not intending to
++ * be using at boot time, as subsytems such as the LCD which do
++ * their own DMA requests to the bus can cause the system to lockup
++ * if they where in the middle of requesting bus access.
++ *
++ * Disabling the LCD clock if the LCD is active is very dangerous,
++ * and therefore the bootloader should be careful to not enable
++ * the LCD clock if it is not needed.
++ */
++
++ /* install (and disable) the clocks we do not need immediately */
++
++ clkp = init_clocks_disable;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
++
++ ret = s3c64xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6410: Failed to register init_clocks_disable: %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ (clkp->enable)(clkp, 0);
++ }
++}
++
++
++
+diff --git a/arch/arm/mach-s3c6410/dma-sysfs.c b/arch/arm/mach-s3c6410/dma-sysfs.c
+new file mode 100644
+index 0000000..d320ec0
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/dma-sysfs.c
+@@ -0,0 +1,276 @@
++/* linux/arch/arm/mach-bast/dma-sysfs.c
++ *
++ * (c) 2005 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2440 DMA core sysfs interface
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++*/
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/sysdev.h>
++#include <linux/config.h>
++
++#include <asm/system.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm/mach/dma.h>
++#include <asm/arch/map.h>
++
++
++extern struct sysdev_class dma_sysclass;
++extern s3c24xx_dma_chan_t s3c24xx_chans[S3C24XX_DMA_CHANNELS];
++
++#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
++
++static const char *s3c24xx_dma_decode_state(s3c24xx_dma_state_t state)
++{
++ switch (state) {
++ case S3C24XX_DMA_IDLE:
++ return "Idle";
++ case S3C24XX_DMA_RUNNING:
++ return "Running";
++ case S3C24XX_DMA_PAUSED:
++ return "Paused";
++ default:
++ return "Invalid";
++ }
++
++ return NULL;
++}
++
++static const char *s3c24xx_dma_decode_loadstate(s3c24xx_dma_loadst_t state)
++{
++ switch (state) {
++ case S3C24XX_DMALOAD_NONE:
++ return "Nothing Loaded";
++ case S3C24XX_DMALOAD_1LOADED:
++ return "1 Loaded";
++ case S3C24XX_DMALOAD_1RUNNING:
++ return "1 Running";
++ case S3C24XX_DMALOAD_1LOADED_1RUNNING:
++ return "1 Loaded, 1 Running";
++ default:
++ return "Invalid Load State";
++ }
++
++ return NULL;
++}
++
++static const char *s3c24xx_dma_decode_source(s3c24xx_dmasrc_t source)
++{
++ switch (source) {
++ case S3C24XX_DMASRC_HW:
++ return "Hardware";
++ case S3C24XX_DMASRC_MEM:
++ return "Memory";
++ default:
++ return "Unknown Source";
++ }
++
++ return NULL;
++}
++
++
++struct outbuff {
++ char *buff;
++ int offset;
++ int size;
++};
++
++static inline void outbuf_init(struct outbuff *ob, char *buf, int size)
++{
++ ob->buff = buf;
++ ob->offset = 0;
++ ob->size = size;
++}
++
++static void outbuf_pf(struct outbuff *ob, const char *fmt, ...)
++{
++ va_list va;
++
++ va_start(va, fmt);
++
++ ob->offset += vsnprintf(ob->buff + ob->offset,
++ ob->size - ob->offset,
++ fmt, va);
++ va_end(va);
++}
++
++static void dma_sysfs_showregs(s3c24xx_dma_chan_t *chan, struct outbuff *buf)
++{
++ outbuf_pf(buf, "Hardware Registers:\n\n");
++
++ outbuf_pf(buf, " DISRC \t\t\t%08lx\n", readl(chan->regs + 0x00));
++ outbuf_pf(buf, " DISRCC\t\t\t%08lx\n", readl(chan->regs + 0x04));
++ outbuf_pf(buf, " DIDST \t\t\t%08lx\n", readl(chan->regs + 0x08));
++ outbuf_pf(buf, " DIDSTC\t\t\t%08lx\n", readl(chan->regs + 0x0C));
++ outbuf_pf(buf, " DCON \t\t\t%08lx\n", readl(chan->regs + 0x10));
++ outbuf_pf(buf, " DSTAT \t\t\t%08lx\n", readl(chan->regs + 0x14));
++ outbuf_pf(buf, " DCSRC \t\t\t%08lx\n", readl(chan->regs + 0x18));
++ outbuf_pf(buf, " DCDST \t\t\t%08lx\n", readl(chan->regs + 0x1c));
++ outbuf_pf(buf, " DMTRG \t\t\t%08lx\n", readl(chan->regs + 0x20));
++}
++
++static void dma_sysfs_showbuf(s3c24xx_dma_chan_t *chan,
++ struct outbuff *buf,
++ s3c24xx_dma_buf_t *ptr)
++{
++ if (ptr == NULL)
++ return;
++
++ outbuf_pf(buf, " buff %p: data=%08x, size=%08x, id=%08x\n",
++ ptr, ptr->data, ptr->size, ptr->id);
++}
++
++static void dma_sysfs_showbuffers(s3c24xx_dma_chan_t *chan, struct outbuff *buf)
++{
++ s3c24xx_dma_buf_t *ptr = chan->next;
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ outbuf_pf(buf, "Current Buffer:\n");
++ dma_sysfs_showbuf(chan, buf, chan->curr);
++
++ outbuf_pf(buf, "\nBuffer Queue: %p -> %p\n", chan->next, chan->end);
++
++ for (; ptr != NULL; ptr = ptr->next)
++ dma_sysfs_showbuf(chan, buf, ptr);
++
++ local_irq_restore(flags);
++}
++
++static void dma_sysfs_showstate(s3c24xx_dma_chan_t *chan, struct outbuff *buf)
++{
++ outbuf_pf(buf, "IRQ:\t\t\t\t%d\n", chan->irq);
++ outbuf_pf(buf, "Register Base:\t\t\t0x%08x\n", chan->regs);
++ outbuf_pf(buf, "Address Register:\t\t0x%08lx\n", chan->addr_reg);
++ outbuf_pf(buf, "Hardware Register:\t\t0x%08lx\n", chan->dev_addr);
++ outbuf_pf(buf, "Load Timeout:\t\t\t0x%08x\n", chan->load_timeout);
++ outbuf_pf(buf, "Data Source:\t\t\t%s\n",
++ s3c24xx_dma_decode_source(chan->source));
++
++ outbuf_pf(buf, "Channel State:\t\t\t%s (%d)\n",
++ s3c24xx_dma_decode_state(chan->state), chan->state);
++ outbuf_pf(buf, "Load State:\t\t\t%s (%d)\n",
++ s3c24xx_dma_decode_loadstate(chan->load_state),
++ chan->load_state);
++
++ if (chan->client != NULL) {
++ outbuf_pf(buf, "Claimed by:\t\t\t%s\n",
++ chan->client->name);
++ } else {
++ outbuf_pf(buf, "Claimed by:\t\t\tNo-one\n");
++ }
++}
++
++static inline s3c24xx_dma_chan_t *dev_to_chan(struct sys_device *dev)
++{
++ return &s3c24xx_chans[dev->id];
++}
++
++static ssize_t dma_sysfs_show_regs(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++ dma_sysfs_showregs(cp, &buff);
++
++ return buff.offset;
++}
++
++static ssize_t dma_sysfs_show_state(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++ dma_sysfs_showstate(cp, &buff);
++
++ return buff.offset;
++}
++
++static ssize_t dma_sysfs_show_buffers(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++ dma_sysfs_showbuffers(cp, &buff);
++
++ return buff.offset;
++}
++
++static ssize_t dma_sysfs_show_all(struct sys_device *dev, char *buf)
++{
++ s3c24xx_dma_chan_t *cp = dev_to_chan(dev);
++ struct outbuff buff;
++
++ outbuf_init(&buff, buf, PAGE_SIZE);
++
++ dma_sysfs_showstate(cp, &buff);
++ dma_sysfs_showregs(cp, &buff);
++ dma_sysfs_showbuffers(cp, &buff);
++
++ return buff.offset;
++}
++
++static SYSDEV_ATTR(all, S_IRUGO, dma_sysfs_show_all, NULL);
++static SYSDEV_ATTR(regs, S_IRUGO, dma_sysfs_show_regs, NULL);
++static SYSDEV_ATTR(state, S_IRUGO, dma_sysfs_show_state, NULL);
++static SYSDEV_ATTR(buffers, S_IRUGO, dma_sysfs_show_buffers, NULL);
++
++static struct sysdev_attribute *attrs[] = {
++ &attr_all,
++ &attr_regs,
++ &attr_state,
++ &attr_buffers,
++};
++
++static int dma_sysfs_attach(struct sys_device *dev)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(attrs); i++)
++ sysdev_create_file(dev, attrs[i]);
++
++ return 0;
++}
++
++static int dma_sysfs_remove(struct sys_device *dev)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(attrs); i++)
++ sysdev_create_file(dev, attrs[i]);
++
++ return 0;
++}
++
++static struct sysdev_driver dma_sysfs_driver = {
++ .add = dma_sysfs_attach,
++ .remove = dma_sysfs_remove,
++};
++
++static int __init s3c24xx_init_dma_sysfs(void)
++{
++ printk("S3C24XX DMA sysfs support, (c) 2005 Simtec Electronics\n");
++
++ return sysdev_driver_register(&dma_sysclass, &dma_sysfs_driver);
++}
++
++__initcall(s3c24xx_init_dma_sysfs);
++
+diff --git a/arch/arm/mach-s3c6410/dma.c b/arch/arm/mach-s3c6410/dma.c
+new file mode 100644
+index 0000000..461c68d
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/dma.c
+@@ -0,0 +1,329 @@
++/* linux/arch/arm/mach-s3c6410/dma.c
++ *
++ * Copyright (c) 2003-2005,2006 Samsung Electronics
++ *
++ * S3C6410 DMA selection
++ *
++ * http://www.samsung.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/sysdev.h>
++#include <linux/serial_core.h>
++
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++#include <asm/io.h>
++
++#include <asm/plat-s3c24xx/dma.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++
++/* DMAC-0 */
++#define MAP0(x) { \
++ [0] = (x) | DMA_CH_VALID, \
++ [1] = (x) | DMA_CH_VALID, \
++ [2] = (x) | DMA_CH_VALID, \
++ [3] = (x) | DMA_CH_VALID, \
++ [4] = (x) | DMA_CH_VALID, \
++ [5] = (x) | DMA_CH_VALID, \
++ [6] = (x) | DMA_CH_VALID, \
++ [7] = (x) | DMA_CH_VALID, \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x), \
++ [19] = (x), \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++/* DMAC-1 */
++#define MAP1(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x), \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x) | DMA_CH_VALID, \
++ [9] = (x) | DMA_CH_VALID, \
++ [10] = (x) | DMA_CH_VALID, \
++ [11] = (x) | DMA_CH_VALID, \
++ [12] = (x) | DMA_CH_VALID, \
++ [13] = (x) | DMA_CH_VALID, \
++ [14] = (x) | DMA_CH_VALID, \
++ [15] = (x) | DMA_CH_VALID, \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x), \
++ [19] = (x), \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++/* SDMAC-0 */
++#define MAP2(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x), \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x) | DMA_CH_VALID, \
++ [17] = (x) | DMA_CH_VALID, \
++ [18] = (x) | DMA_CH_VALID, \
++ [19] = (x) | DMA_CH_VALID, \
++ [20] = (x) | DMA_CH_VALID, \
++ [21] = (x) | DMA_CH_VALID, \
++ [22] = (x) | DMA_CH_VALID, \
++ [23] = (x) | DMA_CH_VALID, \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++/* SDMAC-1 */
++#define MAP3(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x), \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x), \
++ [19] = (x), \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x) | DMA_CH_VALID, \
++ [25] = (x) | DMA_CH_VALID, \
++ [26] = (x) | DMA_CH_VALID, \
++ [27] = (x) | DMA_CH_VALID, \
++ [28] = (x) | DMA_CH_VALID, \
++ [29] = (x) | DMA_CH_VALID, \
++ [30] = (x) | DMA_CH_VALID, \
++ [31] = (x) | DMA_CH_VALID, \
++ }
++
++/* SDMAC-0 */
++#define MAP2_ONENAND(x) { \
++ [0] = (x), \
++ [1] = (x), \
++ [2] = (x), \
++ [3] = (x) , \
++ [4] = (x), \
++ [5] = (x), \
++ [6] = (x), \
++ [7] = (x), \
++ [8] = (x), \
++ [9] = (x), \
++ [10] = (x), \
++ [11] = (x), \
++ [12] = (x), \
++ [13] = (x), \
++ [14] = (x), \
++ [15] = (x), \
++ [16] = (x), \
++ [17] = (x), \
++ [18] = (x) , \
++ [19] = (x) | DMA_CH_VALID, \
++ [20] = (x), \
++ [21] = (x), \
++ [22] = (x), \
++ [23] = (x), \
++ [24] = (x), \
++ [25] = (x), \
++ [26] = (x), \
++ [27] = (x), \
++ [28] = (x), \
++ [29] = (x), \
++ [30] = (x), \
++ [31] = (x), \
++ }
++
++static struct s3c24xx_dma_map __initdata s3c6410_dma_mappings[] = {
++
++ [DMACH_I2S_IN] = {
++ .name = "i2s0-in",
++ .channels = MAP0(S3C_DMA0_I2S0_RX),
++ .hw_addr.from = S3C_DMA0_I2S0_RX,
++ .sdma_sel = 1 << S3C_DMA0_I2S0_RX,
++ },
++ [DMACH_I2S_OUT] = {
++ .name = "i2s0-out",
++ .channels = MAP0(S3C_DMA0_I2S0_TX),
++ .hw_addr.to = S3C_DMA0_I2S0_TX,
++ .sdma_sel = 1 << S3C_DMA0_I2S0_TX,
++ },
++ [DMACH_I2S1_IN] = {
++ .name = "i2s1-in",
++ .channels = MAP1(S3C_DMA1_I2S1_RX),
++ .hw_addr.from = S3C_DMA1_I2S1_RX,
++ .sdma_sel = 1 << (S3C_DMA1_I2S1_RX+S3C_DMA1),
++ },
++ [DMACH_I2S1_OUT] = {
++ .name = "i2s1-out",
++ .channels = MAP1(S3C_DMA1_I2S1_TX),
++ .hw_addr.to = S3C_DMA1_I2S1_TX,
++ .sdma_sel = 1 << (S3C_DMA1_I2S1_TX+S3C_DMA1),
++ },
++ [DMACH_SPI0_IN] = {
++ .name = "spi0-in",
++ .channels = MAP0(S3C_DMA0_SPI0_RX),
++ .hw_addr.from = S3C_DMA0_SPI0_RX,
++ .sdma_sel = 1 << S3C_DMA0_SPI0_RX,
++ },
++ [DMACH_SPI0_OUT] = {
++ .name = "spi0-out",
++ .channels = MAP0(S3C_DMA0_SPI0_TX),
++ .hw_addr.to = S3C_DMA0_SPI0_TX,
++ .sdma_sel = 1 << S3C_DMA0_SPI0_TX,
++ },
++ [DMACH_SPI1_IN] = {
++ .name = "spi1-in",
++ .channels = MAP1(S3C_DMA1_SPI1_RX),
++ .hw_addr.from = S3C_DMA1_SPI1_RX,
++ .sdma_sel = 1 << (S3C_DMA1_SPI1_RX+S3C_DMA1),
++ },
++ [DMACH_SPI1_OUT] = {
++ .name = "spi1-out",
++ .channels = MAP1(S3C_DMA1_SPI1_TX),
++ .hw_addr.to = S3C_DMA1_SPI1_TX,
++ .sdma_sel = 1 << (S3C_DMA1_SPI1_TX+S3C_DMA1),
++ },
++ [DMACH_AC97_PCM_OUT] = {
++ .name = "ac97-pcm-out",
++ .channels = MAP1(S3C_DMA1_AC97_PCMOUT),
++ .hw_addr.to = S3C_DMA1_AC97_PCMOUT,
++ .sdma_sel = 1 << (S3C_DMA1_AC97_PCMOUT+S3C_DMA1),
++ },
++ [DMACH_AC97_PCM_IN] = {
++ .name = "ac97-pcm-in",
++ .channels = MAP1(S3C_DMA1_AC97_PCMIN),
++ .hw_addr.from = S3C_DMA1_AC97_PCMIN,
++ .sdma_sel = 1 << (S3C_DMA1_AC97_PCMIN+S3C_DMA1),
++ },
++ [DMACH_AC97_MIC_IN] = {
++ .name = "ac97-mic-in",
++ .channels = MAP1(S3C_DMA1_AC97_MICIN),
++ .hw_addr.from = S3C_DMA1_AC97_MICIN,
++ .sdma_sel = 1 << (S3C_DMA1_AC97_MICIN+S3C_DMA1),
++ },
++ [DMACH_ONENAND_IN] = {
++ .name = "onenand-in",
++ .channels = MAP2_ONENAND(S3C_DMA0_ONENAND_RX),
++ .hw_addr.from = S3C_DMA0_ONENAND_RX,
++ },
++ [DMACH_3D_M2M] = {
++ .name = "3D-M2M",
++ .channels = MAP1(S3C_DMA1_EXT),
++ .hw_addr.from = S3C_DMA1_EXT,
++ },
++ [DMACH_I2S_V40_IN] = {
++ .name = "i2s-v40-in",
++ .channels = MAP0(S3C_DMA0_HSI_RX),
++ .hw_addr.from = S3C_DMA0_HSI_RX,
++ .sdma_sel = 1 << S3C_DMA0_HSI_RX,
++ },
++ [DMACH_I2S_V40_OUT] = {
++ .name = "i2s-v40-out",
++ .channels = MAP0(S3C_DMA0_HSI_TX),
++ .hw_addr.to = S3C_DMA0_HSI_TX,
++ .sdma_sel = 1 << S3C_DMA0_HSI_TX,
++ },
++};
++
++static void s3c6410_dma_select(struct s3c2410_dma_chan *chan,
++ struct s3c24xx_dma_map *map)
++{
++ chan->map = map;
++}
++
++static struct s3c24xx_dma_selection __initdata s3c6410_dma_sel = {
++ .select = s3c6410_dma_select,
++ .dcon_mask = 0,
++ .map = s3c6410_dma_mappings,
++ .map_size = ARRAY_SIZE(s3c6410_dma_mappings),
++};
++
++static int __init s3c6410_dma_add(struct sys_device *sysdev)
++{
++ s3c24xx_dma_init(S3C2410_DMA_CHANNELS, IRQ_DMA0, 0x20);
++ return s3c24xx_dma_init_map(&s3c6410_dma_sel);
++}
++
++static struct sysdev_driver s3c6410_dma_driver = {
++ .add = s3c6410_dma_add,
++};
++
++static int __init s3c6410_dma_init(void)
++{
++ return sysdev_driver_register(&s3c6410_sysclass, &s3c6410_dma_driver);
++}
++
++arch_initcall(s3c6410_dma_init);
++
++
+diff --git a/arch/arm/mach-s3c6410/irq.c b/arch/arm/mach-s3c6410/irq.c
+new file mode 100644
+index 0000000..9266bc5
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/irq.c
+@@ -0,0 +1,48 @@
++/* linux/arch/arm/mach-s3c6410/irq.c
++ *
++ * Copyright (c) 2006 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++*/
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/ptrace.h>
++#include <linux/sysdev.h>
++
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/plat-s3c24xx/pm.h>
++
++static int s3c6410_irq_add(struct sys_device *sysdev)
++{
++ return 0;
++}
++
++static struct sysdev_driver s3c6410_irq_driver = {
++ .add = s3c6410_irq_add,
++ .suspend = s3c24xx_irq_suspend,
++ .resume = s3c24xx_irq_resume,
++};
++
++static int s3c6410_irq_init(void)
++{
++ return sysdev_driver_register(&s3c6410_sysclass, &s3c6410_irq_driver);
++}
++
++arch_initcall(s3c6410_irq_init);
+diff --git a/arch/arm/mach-s3c6410/leds-s3c6410.c b/arch/arm/mach-s3c6410/leds-s3c6410.c
+new file mode 100644
+index 0000000..bc1347f
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/leds-s3c6410.c
+@@ -0,0 +1,117 @@
++/*
++ * linux/arch/arm/mach-s3c6410/leds-s3c6410.c
++ *
++ * Copyright 2008 by Samsung Electronics Inc
++ *
++ * There are 16 LEDs on the debug board (all green); four may be used
++ * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
++ *
++ * The "surfer" expansion board and H2 sample board also have two-color
++ * green+red LEDs (in parallel), used here for timer and idle indicators.
++ */
++#include <linux/init.h>
++#include <linux/kernel_stat.h>
++#include <linux/sched.h>
++
++#include <asm/io.h>
++#include <asm/hardware.h>
++#include <asm/leds.h>
++#include <asm/system.h>
++#include <asm/mach-types.h>
++
++#include <asm/arch/regs-gpio.h>
++
++#include "leds.h"
++
++#define LED0 S3C_GPN12
++#define LED1 S3C_GPN13
++#define LED2 S3C_GPN14
++#define LED3 S3C_GPN15
++
++#define LED_STATE_ENABLED 1<<0
++#define LED_STATE_CLAIMED 1<<1
++#define LED_TIMER_ON 1<<2
++#define LED_IDLE 1<<3
++
++
++void smdk6410_leds_event(led_event_t evt)
++{
++ unsigned long flags;
++
++ static u16 led_state, hw_led_state;
++
++ local_irq_save(flags);
++
++ if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
++ goto done;
++
++ switch (evt) {
++ case led_start:
++ led_state |= LED_STATE_ENABLED;
++ break;
++
++ case led_stop:
++ case led_halted:
++ /* all leds off during suspend or shutdown */
++ led_state &= ~LED_STATE_ENABLED;
++ break;
++
++ case led_claim:
++ led_state |= LED_STATE_CLAIMED;
++ hw_led_state = 0;
++ break;
++
++ case led_release:
++ led_state &= ~LED_STATE_CLAIMED;
++ break;
++
++#ifdef CONFIG_LEDS_TIMER
++ case led_timer:
++ led_state ^= LED_TIMER_ON;
++
++ if (led_state & LED_TIMER_ON)
++ gpio_set_value(LED0, 1);
++ else {
++ gpio_set_value(LED0, 0);
++ }
++
++ break;
++#endif
++
++#ifdef CONFIG_LEDS_CPU
++ case led_idle_start:
++ gpio_set_value(LED1, 1);
++ break;
++
++ case led_idle_end:
++ gpio_set_value(LED1, 0);
++ break;
++#endif
++
++ case led_green_on:
++ break;
++ case led_green_off:
++ break;
++
++ case led_amber_on:
++ break;
++ case led_amber_off:
++ break;
++
++ case led_red_on:
++ break;
++ case led_red_off:
++ break;
++
++ case led_blue_on:
++ break;
++ case led_blue_off:
++ break;
++
++ default:
++ break;
++ }
++
++done:
++ local_irq_restore(flags);
++}
+diff --git a/arch/arm/mach-s3c6410/leds.c b/arch/arm/mach-s3c6410/leds.c
+new file mode 100644
+index 0000000..8113540
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/leds.c
+@@ -0,0 +1,89 @@
++/*
++ * linux/arch/arm/mach-s3c6410/leds.c
++ *
++ * S3C6410 LEDs dispatcher
++ */
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/leds.h>
++#include <asm/mach-types.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/irqs.h>
++#include <asm/mach/irq.h>
++#include "leds.h"
++
++static irqreturn_t eint9_switch(int irq, void *dev_id, struct pt_regs *regs)
++{
++
++ printk("EINT9 interrupt occures!!!\n");
++ return IRQ_HANDLED;
++}
++
++
++static int __init
++s3c6410_leds_init(void)
++{
++ if (machine_is_smdk6410())
++ leds_event = smdk6410_leds_event;
++ else
++ return -1;
++
++ if (machine_is_smdk6410())
++ {
++ /*GPN12~15 used for LED*/
++ /*Set GPN12~15 to output mode */
++ gpio_direction_output(S3C_GPN12);
++ if(gpio_get_pin(S3C_GPN12) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN12 output mode\n");
++ }
++
++ gpio_direction_output(S3C_GPN13);
++ if(gpio_get_pin(S3C_GPN13) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN13 output mode\n");
++ }
++
++ gpio_direction_output(S3C_GPN14);
++ if(gpio_get_pin(S3C_GPN14) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN14 output mode\n");
++ }
++
++ gpio_direction_output(S3C_GPN15);
++ if(gpio_get_pin(S3C_GPN15) == 0)
++ {
++ printk(KERN_WARNING "LED: can't set GPN15 output mode\n");
++ }
++
++ }
++
++ /* Get irqs */
++ set_irq_type(IRQ_EINT9, IRQT_FALLING);
++ gpio_pullup(S3C_GPN9, 0x0);
++ if (request_irq(IRQ_EINT9, eint9_switch, SA_TRIGGER_FALLING, "EINT9", NULL)) {
++ printk(KERN_ERR "leds.c: Could not allocate EINT9 !\n");
++ return -EIO;
++ }
++
++
++ leds_event(led_start);
++ return 0;
++}
++
++__initcall(s3c6410_leds_init);
+diff --git a/arch/arm/mach-s3c6410/leds.h b/arch/arm/mach-s3c6410/leds.h
+new file mode 100644
+index 0000000..e868666
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/leds.h
+@@ -0,0 +1 @@
++extern void smdk6410_leds_event(led_event_t evt);
+diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
+new file mode 100644
+index 0000000..ec86f3e
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
+@@ -0,0 +1,868 @@
++/***********************************************************************
++ *
++ * linux/arch/arm/mach-s3c6410/smdk6410.c
++ *
++ * $Id: mach-smdk6410.c,v 1.56 2008/09/10 01:40:15 jsgood Exp $
++ *
++ * Copyright (C) 2005, Samsung Electronics <@samsung.com>
++ * All rights reserved
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ *
++ ***********************************************************************/
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/i2c.h>
++
++#include <asm/setup.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++#include <asm/mach/flash.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++
++#include <asm/plat-s3c/iic.h>
++#include <asm/plat-s3c/regs-iic.h>
++
++#include <asm/arch/gpio.h>
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++
++#include <asm/arch/regs-mem.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c/nand.h>
++#include <asm/plat-s3c/adc.h>
++
++#include <asm/plat-s3c64xx/s3c6410.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/arch/hsmmc.h>
++
++#include <asm/plat-s3c24xx/common-smdk.h>
++#include <asm/arch-s3c2410/reserved_mem.h>
++
++#if defined(CONFIG_RTC_DRV_S3C) || defined(CONFIG_RTC_DRV_S3C_MODULE)
++#include <asm/plat-s3c/regs-rtc.h>
++#endif
++
++#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS) || \
++ defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++#include <asm/arch-s3c2410/regs-usb-otg-hs.h>
++#include <linux/usb/ch9.h>
++#endif
++
++#include <asm/plat-s3c/regs-adc.h>
++#include <asm/plat-s3c/ts.h>
++
++extern struct sys_timer s3c_timer;
++
++static struct map_desc smdk6410_iodesc[] __initdata = {
++ IODESC_ENT(CS8900),
++};
++
++#define DEF_UCON S3C_UCON_DEFAULT
++#define DEF_ULCON S3C_LCON_CS8 | S3C_LCON_PNONE
++#define DEF_UFCON S3C_UFCON_RXTRIG8 | S3C_UFCON_FIFOMODE
++
++
++static struct s3c24xx_uart_clksrc smdk6410_serial_clocks[] = {
++ [0] = {
++ .name = "mpll_clk_uart",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ },
++#if defined (CONFIG_SERIAL_S3C64XX_HS_UART)
++ [2] = {
++ .name = "epll_clk_uart_192m",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 4000000,
++ }
++#endif
++};
++
++
++
++static struct s3c2410_uartcfg smdk6410_uartcfgs[] = {
++ [0] = {
++ .hwport = 0,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6410_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
++ },
++ [1] = {
++ .hwport = 1,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6410_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
++ },
++ [2] = {
++ .hwport = 2,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6410_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
++ },
++ [3] = {
++ .hwport = 3,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdk6410_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdk6410_serial_clocks),
++ }
++
++};
++
++static struct resource s3c64xx_i2c0_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_IIC0,
++ .end = S3C6400_PA_IIC0 + S3C24XX_SZ_IIC - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_IIC0,
++ .end = IRQ_IIC0,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device s3c64xx_device_i2c0 = {
++ .name = "s3c64xx-i2c",
++ .id = 0, /* This is so the driver gets forced to use bus 0. */
++ .num_resources = ARRAY_SIZE(s3c64xx_i2c0_resource),
++ .resource = s3c64xx_i2c0_resource,
++};
++
++static struct resource s3c64xx_i2c1_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_IIC1,
++ .end = S3C6400_PA_IIC1 + S3C24XX_SZ_IIC - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_IIC1,
++ .end = IRQ_IIC1,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device s3c64xx_device_i2c1 = {
++ .name = "s3c64xx-i2c",
++ .id = 1, /* This is so the driver gets forced to use bus 0. */
++ .num_resources = ARRAY_SIZE(s3c64xx_i2c1_resource),
++ .resource = s3c64xx_i2c1_resource,
++};
++
++static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
++ .flags = 0,
++ .slave_addr = 0x10,
++ .bus_freq = 100*1000,
++ .max_freq = 400*1000,
++ .sda_delay = S3C64XX_IICLC_SDA_DELAY5 | S3C64XX_IICLC_FILTER_ON,
++};
++
++void s3c_i2c0_cfg_gpio(struct platform_device *dev)
++{
++ s3c_gpio_cfgpin(S3C_GPB5, S3C_GPB5_I2C_SCL0);
++ s3c_gpio_cfgpin(S3C_GPB6, S3C_GPB6_I2C_SDA0);
++ s3c_gpio_pullup(S3C_GPB5, 2);
++ s3c_gpio_pullup(S3C_GPB6, 2);
++}
++
++void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
++{
++ struct s3c2410_platform_i2c *npd;
++
++ if (!pd)
++ pd = &default_i2c_data0;
++
++ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
++ if (!npd)
++ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
++ else if (!npd->cfg_gpio)
++ npd->cfg_gpio = s3c_i2c0_cfg_gpio;
++
++ s3c64xx_device_i2c0.dev.platform_data = npd;
++}
++
++static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
++ .flags = 0,
++ .bus_num = 1,
++ .slave_addr = 0x10,
++ .bus_freq = 100*1000,
++ .max_freq = 400*1000,
++ .sda_delay = S3C64XX_IICLC_SDA_DELAY5 | S3C64XX_IICLC_FILTER_ON,
++};
++
++void s3c_i2c1_cfg_gpio(struct platform_device *dev)
++{
++ s3c_gpio_cfgpin(S3C_GPB2, S3C_GPB2_I2C_SCL1);
++ s3c_gpio_cfgpin(S3C_GPB3, S3C_GPB3_I2C_SDA1);
++ s3c_gpio_pullup(S3C_GPB2, 2);
++ s3c_gpio_pullup(S3C_GPB3, 2);
++}
++
++void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
++{
++ struct s3c2410_platform_i2c *npd;
++
++ if (!pd)
++ pd = &default_i2c_data1;
++
++ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
++ if (!npd)
++ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
++ else if (!npd->cfg_gpio)
++ npd->cfg_gpio = s3c_i2c1_cfg_gpio;
++
++ s3c64xx_device_i2c1.dev.platform_data = npd;
++}
++
++static struct i2c_board_info i2c_devs0[] __initdata = {
++ { I2C_BOARD_INFO("24c08", 0x50), },
++};
++
++static struct i2c_board_info i2c_devs1[] __initdata = {
++ { I2C_BOARD_INFO("24c128", 0x57), },
++};
++
++/* Add devices as drivers are integrated */
++static struct platform_device *smdk6410_devices[] __initdata = {
++ &s3c_device_rtc,
++ &s3c_device_ac97,
++ &s3c_device_iis,
++ &s3c_device_ts,
++ &s3c_device_adc,
++ &s3c64xx_device_i2c0,
++ &s3c64xx_device_i2c1,
++ &s3c_device_usb,
++ &s3c_device_usbgadget,
++ &s3c_device_usb_otghcd,
++ &s3c_device_tvenc,
++ &s3c_device_tvscaler,
++ &s3c_device_hsmmc0,
++ &s3c_device_hsmmc1,
++ &s3c_device_hsmmc2,
++ &s3c_device_wdt,
++ &s3c_device_jpeg,
++ &s3c_device_vpp,
++ &s3c_device_ide,
++ &s3c_device_spi0,
++ &s3c_device_spi1,
++ &s3c_device_g2d,
++ &s3c_device_keypad,
++ &s3c_device_smc911x,
++ &s3c_device_camif,
++ &s3c_device_mfc,
++ &s3c_device_g3d,
++ &s3c_device_rotator,
++};
++
++
++static void __init smdk6410_map_io(void)
++{
++ s3c24xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
++ s3c24xx_init_clocks(0);
++ s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
++}
++
++void smdk6410_smc911x_set(void)
++{
++ unsigned int tmp;
++
++ tmp = __raw_readl(S3C_SROM_BW);
++ tmp &=~(0xF<<4);
++ tmp |= (1<<7) | (1<<6) | (1<<4);
++ __raw_writel(tmp, S3C_SROM_BW);
++
++ __raw_writel((0x0<<28)|(0x4<<24)|(0xd<<16)|(0x1<<12)|(0x4<<8)|(0x6<<4)|(0x0<<0), S3C_SROM_BC1);
++}
++
++static void __init smdk6410_fixup (struct machine_desc *desc, struct tag *tags,
++ char **cmdline, struct meminfo *mi)
++{
++ /*
++ * Bank start addresses are not present in the information
++ * passed in from the boot loader. We could potentially
++ * detect them, but instead we hard-code them.
++ */
++ mi->bank[0].start = PHYS_OFFSET;
++
++#if defined(CONFIG_RESERVED_MEM_JPEG)
++ mi->bank[0].size = 120*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_POST)
++ mi->bank[0].size = 112*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC)
++ mi->bank[0].size = 122*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC_POST)
++ mi->bank[0].size = 114*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST)
++ mi->bank[0].size = 106*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_CAMERA)
++ mi->bank[0].size = 105*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_POST_CAMERA)
++ mi->bank[0].size = 97*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC_CAMERA)
++ mi->bank[0].size = 107*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_MFC_POST_CAMERA)
++ mi->bank[0].size = 99*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA)
++ mi->bank[0].size = 91*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_CMM_MFC_POST)
++ mi->bank[0].size = 106*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA)
++ mi->bank[0].size = 83*1024*1024;
++#elif defined(CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA)
++ mi->bank[0].size = 91*1024*1024;
++#elif defined(CONFIG_VIDEO_SAMSUNG)
++ mi->bank[0].size = 113*1024*1024;
++#else
++ mi->bank[0].size = 128*1024*1024;
++#endif
++ mi->bank[0].node = 0;
++
++ mi->nr_banks = 1;
++}
++
++
++static void smdk6410_hsmmc_init (void)
++{
++ /* hsmmc data strength */
++ writel(readl(S3C_SPCON) | (0x3 << 26), S3C_SPCON);
++
++ /* jsgood: hsmmc0/1 card detect pin should be high before setup gpio. (GPG6 to Input) */
++ writel(readl(S3C_GPGCON) & 0xf0ffffff, S3C_GPGCON);
++
++ /* GPIO N 13 (external interrupt) : Chip detect */
++ gpio_set_pin(S3C_GPN13, S3C_GPN13_EXTINT13); /* GPN13 to EINT13 */
++ gpio_pullup(S3C_GPN13, 0x2); /* Pull-up Enable */
++
++ /* jsgood: MUXmmc# to DOUTmpll for MPLL Clock Source */
++ writel((readl(S3C_CLK_SRC) & ~(0x3f << 18)) | (0x15 << 18), S3C_CLK_SRC);
++}
++
++#define IS_SMDK6430_CHK15 (1<<15)
++
++static unsigned int is_smdk6430(void)
++{
++ u32 reg, ret;
++
++ reg = (u32)ioremap((unsigned long)S3C64XX_PA_CHIP_ID, 0x1);
++
++ if((__raw_readl(reg + 0x4)& IS_SMDK6430_CHK15) == IS_SMDK6430_CHK15)
++ ret = 1; /* SMDK6430 */
++ else
++ ret = 0; /* SMDK6410 */
++
++ iounmap((void*)reg);
++
++ return ret;
++}
++
++static void smdk6410_set_qos(void)
++{
++ u32 reg;
++
++ /* AXI sfr */
++ reg = (u32) ioremap((unsigned long) S3C6410_PA_AXI_SYS, SZ_4K);
++
++ /* QoS override: FIMD min. latency */
++ writel(0x2, S3C24XX_VA_SYSCON + 0x128);
++
++ /* AXI QoS */
++ writel(0x7, reg + 0x460); /* (8 - MFC ch.) */
++ writel(0x7ff7, reg + 0x464);
++
++ /* Bus cacheable */
++ writel(0x8ff, S3C24XX_VA_SYSCON + 0x838);
++}
++
++static void __init smdk6410_machine_init (void)
++{
++ smdk6410_smc911x_set();
++
++ s3c_i2c0_set_platdata(NULL);
++ s3c_i2c1_set_platdata(NULL);
++
++ i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
++ i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
++
++ platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
++
++ if(is_smdk6430()) {
++ platform_device_del(&s3c_device_mfc);
++ platform_device_del(&s3c_device_g3d);
++ }
++
++ smdk_machine_init();
++
++ smdk6410_hsmmc_init();
++ smdk6410_set_qos();
++}
++
++#if !defined(CONFIG_MACH_SMDK6430)
++MACHINE_START(SMDK6410, "SMDK6410")
++#else
++MACHINE_START(SMDK6430, "SMDK6430")
++#endif
++ /* Maintainer: Samsung Electronics */
++ .phys_io = S3C24XX_PA_UART,
++ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
++ .boot_params = S3C_SDRAM_PA + 0x100,
++
++ .init_irq = s3c_init_irq,
++ .map_io = smdk6410_map_io,
++ .fixup = smdk6410_fixup,
++ .timer = &s3c_timer,
++ .init_machine = smdk6410_machine_init,
++MACHINE_END
++
++/*--------------------------------------------------------------
++ * HS-MMC GPIO Set function
++ * the location of this function must be re-considered.
++ * by scsuh
++ *--------------------------------------------------------------*/
++void hsmmc_set_gpio (uint channel, uint width)
++{
++ switch (channel) {
++ /* can supports 1 and 4 bit bus */
++ case 0:
++ /* GPIO G : Command, Clock */
++ gpio_set_pin(S3C_GPG0, S3C_GPG0_MMC_CLK0);
++ gpio_set_pin(S3C_GPG1, S3C_GPG1_MMC_CMD0);
++
++ gpio_pullup(S3C_GPG0, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPG1, 0x0); /* Pull-up/down disable */
++
++ /* GPIO G : Chip detect + LED */
++ gpio_set_pin(S3C_GPG6, S3C_GPG6_MMC_CD1);
++ gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
++
++ if (width == 1) {
++ /* GPIO G : MMC DATA1[0] */
++ gpio_set_pin(S3C_GPG2, S3C_GPG2_MMC_DATA0_0);
++
++ gpio_pullup(S3C_GPG2, 0x0); /* Pull-up/down disable */
++ }
++ else if (width == 4) {
++ /* GPIO G : MMC DATA1[0:3] */
++ gpio_set_pin(S3C_GPG2, S3C_GPG2_MMC_DATA0_0);
++ gpio_set_pin(S3C_GPG3, S3C_GPG3_MMC_DATA0_1);
++ gpio_set_pin(S3C_GPG4, S3C_GPG4_MMC_DATA0_2);
++ gpio_set_pin(S3C_GPG5, S3C_GPG5_MMC_DATA0_3);
++
++ gpio_pullup(S3C_GPG2, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPG3, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPG4, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPG5, 0x0); /* Pull-up/down disable */
++ }
++ break;
++
++ /* can supports 1, 4, and 8 bit bus */
++ case 1:
++ /* GPIO H : Command, Clock */
++ gpio_set_pin(S3C_GPH0, S3C_GPH0_MMC_CLK1);
++ gpio_set_pin(S3C_GPH1, S3C_GPH1_MMC_CMD1);
++
++ gpio_pullup(S3C_GPH0, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH1, 0x0); /* Pull-up/down disable */
++
++ /* GPIO G : Chip detect + LED */
++ gpio_set_pin(S3C_GPG6, S3C_GPG6_MMC_CD1);
++ gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
++
++ if (width == 1) {
++ /* GPIO H : MMC DATA1[0] */
++ gpio_set_pin(S3C_GPH2, S3C_GPH2_MMC_DATA1_0);
++
++ gpio_pullup(S3C_GPH2, 0x0); /* Pull-up/down disable */
++ }
++ else if (width == 4) {
++ /* GPIO H : MMC DATA1[0:3] */
++ gpio_set_pin(S3C_GPH2, S3C_GPH2_MMC_DATA1_0);
++ gpio_set_pin(S3C_GPH3, S3C_GPH3_MMC_DATA1_1);
++ gpio_set_pin(S3C_GPH4, S3C_GPH4_MMC_DATA1_2);
++ gpio_set_pin(S3C_GPH5, S3C_GPH5_MMC_DATA1_3);
++
++ gpio_pullup(S3C_GPH2, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH3, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH4, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH5, 0x0); /* Pull-up/down disable */
++ }
++ else if (width == 8) {
++ /* GPIO H : MMC DATA1[0:7] */
++ gpio_set_pin(S3C_GPH2, S3C_GPH2_MMC_DATA1_0);
++ gpio_set_pin(S3C_GPH3, S3C_GPH3_MMC_DATA1_1);
++ gpio_set_pin(S3C_GPH4, S3C_GPH4_MMC_DATA1_2);
++ gpio_set_pin(S3C_GPH5, S3C_GPH5_MMC_DATA1_3);
++ gpio_set_pin(S3C_GPH6, S3C_GPH6_MMC_DATA1_4);
++ gpio_set_pin(S3C_GPH7, S3C_GPH7_MMC_DATA1_5);
++ gpio_set_pin(S3C_GPH8, S3C_GPH8_MMC_DATA1_6);
++ gpio_set_pin(S3C_GPH9, S3C_GPH9_MMC_DATA1_7);
++
++ gpio_pullup(S3C_GPH2, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH3, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH4, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH5, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH6, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH7, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH8, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH9, 0x0); /* Pull-up/down disable */
++ }
++ break;
++
++ /* can supports 1 and 4 bit bus, no irq_cd */
++ case 2:
++ /* GPIO H : Command, Clock */
++ gpio_set_pin(S3C_GPH0, S3C_GPH0_MMC_CLK1);
++ gpio_set_pin(S3C_GPH1, S3C_GPH1_MMC_CMD1);
++
++ gpio_pullup(S3C_GPH0, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH1, 0x0); /* Pull-up/down disable */
++
++ /* GPIO G : Chip detect + LED */
++ gpio_set_pin(S3C_GPG6, S3C_GPG6_MMC_CD1);
++ gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
++
++ if (width == 1) {
++ /* GPIO H : MMC DATA1[0] */
++ gpio_set_pin(S3C_GPH6, S3C_GPH6_MMC_DATA2_0);
++
++ gpio_pullup(S3C_GPH6, 0x0); /* Pull-up/down disable */
++ }
++ else if (width == 4) {
++ /* GPIO H : MMC DATA1[0:3] */
++ gpio_set_pin(S3C_GPH6, S3C_GPH6_MMC_DATA2_0);
++ gpio_set_pin(S3C_GPH7, S3C_GPH7_MMC_DATA2_1);
++ gpio_set_pin(S3C_GPH8, S3C_GPH8_MMC_DATA2_2);
++ gpio_set_pin(S3C_GPH9, S3C_GPH9_MMC_DATA2_3);
++
++ gpio_pullup(S3C_GPH6, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH7, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH8, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPH9, 0x0); /* Pull-up/down disable */
++ }
++
++ break;
++
++ default:
++ break;
++ }
++}
++EXPORT_SYMBOL(hsmmc_set_gpio);
++
++/* For host controller's capabilities */
++#define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
++ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
++
++
++struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
++ .hwport = 0,
++ .enabled = 0,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ .clocks[0] = {
++ .name = "sclk_DOUTmpll_mmc0",
++ .src = 0x2,
++ },
++};
++
++struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
++ .hwport = 1,
++ .enabled = 1,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ //.host_caps = HOST_CAPS | MMC_CAP_8_BIT_DATA,
++ //.bus_width = 8,
++
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ .clocks[0] = {
++ .name = "sclk_DOUTmpll_mmc1",
++ .src = 0x2,
++ },
++};
++
++struct s3c_hsmmc_cfg s3c_hsmmc2_platform = {
++ .hwport = 2,
++ .enabled = 0,
++ .host_caps = HOST_CAPS,
++ .bus_width = 4,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[MMC_TYPE_MMC] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[MMC_TYPE_SD] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for sd */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
++ .clocks[0] = {
++ .name = "sclk_DOUTmpll_mmc2",
++ .src = 0x2,
++ },
++};
++
++#if defined(CONFIG_RTC_DRV_S3C) || defined(CONFIG_RTC_DRV_S3C_MODULE)
++/* RTC common Function for samsung APs*/
++unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val)
++{
++ writeb(val, base + offset);
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c_rtc_set_bit_byte);
++
++unsigned int s3c_rtc_read_alarm_status(void __iomem *base)
++{
++ return 1;
++}
++EXPORT_SYMBOL(s3c_rtc_read_alarm_status);
++
++void s3c_rtc_set_pie(void __iomem *base, uint to)
++{
++ unsigned int tmp;
++
++ tmp = readw(base + S3C2410_RTCCON) & ~S3C_RTCCON_TICEN;
++
++ if (to)
++ tmp |= S3C_RTCCON_TICEN;
++
++ writew(tmp, base + S3C2410_RTCCON);
++}
++EXPORT_SYMBOL(s3c_rtc_set_pie);
++
++void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint *s3c_freq)
++{
++ unsigned int tmp;
++
++ tmp = readw(base + S3C2410_RTCCON) & (S3C_RTCCON_TICEN | S3C2410_RTCCON_RTCEN );
++ writew(tmp, base + S3C2410_RTCCON);
++ *s3c_freq = freq;
++ tmp = (32768 / freq)-1;
++ writel(tmp, base + S3C2410_TICNT);
++}
++EXPORT_SYMBOL(s3c_rtc_set_freq_regs);
++
++void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en)
++{
++ unsigned int tmp;
++
++ if (!en) {
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp & ~ (S3C2410_RTCCON_RTCEN | S3C_RTCCON_TICEN), base + S3C2410_RTCCON);
++ } else {
++ /* re-enable the device, and check it is ok */
++ if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){
++ dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
++
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON);
++ }
++
++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){
++ dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
++
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON);
++ }
++
++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){
++ dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
++
++ tmp = readw(base + S3C2410_RTCCON);
++ writew(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON);
++ }
++ }
++}
++EXPORT_SYMBOL(s3c_rtc_enable_set);
++#endif
++
++#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS) || \
++ defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++
++/* Initializes OTG Phy. */
++void otg_phy_init(u32 otg_phy_clk) {
++
++ writel(readl(S3C_OTHERS)|S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS);
++ writel(0x0, S3C_USBOTG_PHYPWR); /* Power up */
++ writel(otg_phy_clk, S3C_USBOTG_PHYCLK);
++ writel(0x1, S3C_USBOTG_RSTCON);
++
++ udelay(50);
++ writel(0x0, S3C_USBOTG_RSTCON);
++ udelay(50);
++}
++
++EXPORT_SYMBOL(otg_phy_init);
++
++/* USB Control request data struct must be located here for DMA transfer */
++struct usb_ctrlrequest usb_ctrl;
++EXPORT_SYMBOL(usb_ctrl);
++
++/* OTG PHY Power Off */
++void otg_phy_off(void) {
++ writel(readl(S3C_USBOTG_PHYPWR)|(0x1F<<1), S3C_USBOTG_PHYPWR);
++ writel(readl(S3C_OTHERS)&~S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS);
++}
++
++EXPORT_SYMBOL(otg_phy_off);
++#endif
++
++#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++void usb_host_clk_en(int usb_host_clksrc, u32 otg_phy_clk) {
++ switch (usb_host_clksrc) {
++ case 0: /* epll clk */
++ writel((readl(S3C_CLK_SRC)& ~S3C_CLKSRC_UHOST_MASK)
++ |S3C_CLKSRC_EPLL_CLKSEL|S3C_CLKSRC_UHOST_EPLL,
++ S3C_CLK_SRC);
++
++ /* USB host colock divider ratio is 2 */
++ writel((readl(S3C_CLK_DIV1)& ~S3C_CLKDIVN_UHOST_MASK)
++ |S3C_CLKDIV1_USBDIV2, S3C_CLK_DIV1);
++ break;
++ case 1: /* oscillator 48M clk */
++ writel(readl(S3C_CLK_SRC)& ~S3C_CLKSRC_UHOST_MASK, S3C_CLK_SRC);
++ otg_phy_init(otg_phy_clk);
++
++ /* USB host colock divider ratio is 1 */
++ writel(readl(S3C_CLK_DIV1)& ~S3C_CLKDIVN_UHOST_MASK, S3C_CLK_DIV1);
++ break;
++ default:
++ printk(KERN_INFO "Unknown USB Host Clock Source\n");
++ BUG();
++ break;
++ }
++
++ writel(readl(S3C_HCLK_GATE)|S3C_CLKCON_HCLK_UHOST|S3C_CLKCON_HCLK_SECUR,
++ S3C_HCLK_GATE);
++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_UHOST, S3C_SCLK_GATE);
++
++}
++EXPORT_SYMBOL(usb_host_clk_en);
++#endif
++
++/* smdk6410 adc common function */
++
++struct s3c_adc_cfg s3c_adc_platform={
++ /* s3c6410 support 12-bit resolution */
++ .delay = 10000,
++ .presc = 49,
++ .resolution = 12,
++};
++
++#if defined(CONFIG_S3C_ADC) || defined(CONFIG_S3C_ADC_MODULE)
++unsigned int s3c_adc_convert(void __iomem *reg_base,unsigned int s3c_adc_port)
++{
++ unsigned int adc_return;
++ unsigned long data0;
++ unsigned long data1;
++
++ writel(readl(reg_base+S3C2410_ADCCON)|S3C2410_ADCCON_SELMUX(s3c_adc_port), reg_base+S3C2410_ADCCON);
++
++ udelay(10);
++
++ writel(readl(reg_base+S3C2410_ADCCON)|S3C2410_ADCCON_ENABLE_START, reg_base+S3C2410_ADCCON);
++
++ do {
++ data0 = readl(reg_base+S3C2410_ADCCON);
++ } while(!(data0 & S3C2410_ADCCON_ECFLG));
++
++ data1 = readl(reg_base+S3C2410_ADCDAT0);
++
++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT;
++
++ return adc_return;
++}
++EXPORT_SYMBOL(s3c_adc_convert);
++#endif
++
++
++struct s3c_ts_mach_info s3c_ts_platform = {
++ .delay = 10000,
++ .presc = 49,
++ .oversampling_shift = 2,
++ .resol_bit = 12,
++};
++
+diff --git a/arch/arm/mach-s3c6410/pm.c b/arch/arm/mach-s3c6410/pm.c
+new file mode 100644
+index 0000000..af53fdc
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/pm.c
+@@ -0,0 +1,116 @@
++/* linux/arch/arm/mach-s3c6410/pm.c
++ *
++ * Copyright (c) 2006 Samsung Electronics
++ *
++ *
++ * S3C6410 (and compatible) Power Manager (Suspend-To-RAM) support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/init.h>
++#include <linux/suspend.h>
++#include <linux/errno.h>
++#include <linux/time.h>
++#include <linux/sysdev.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++
++#include <asm/mach-types.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c/regs-rtc.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/plat-s3c24xx/pm.h>
++
++#ifdef CONFIG_S3C2410_PM_DEBUG
++extern void pm_dbg(const char *fmt, ...);
++#define DBG(fmt...) pm_dbg(fmt)
++#else
++#define DBG(fmt...) printk(KERN_DEBUG fmt)
++#endif
++
++static void s3c6410_cpu_suspend(void)
++{
++ unsigned long tmp;
++
++ /* issue the standby signal into the pm unit. Note, we
++ * issue a write-buffer drain just in case */
++
++ tmp = 0;
++
++ asm("b 1f\n\t"
++ ".align 5\n\t"
++ "1:\n\t"
++ "mcr p15, 0, %0, c7, c10, 5\n\t"
++ "mcr p15, 0, %0, c7, c10, 4\n\t"
++ "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
++
++ /* we should never get past here */
++
++ panic("sleep resumed to originator?");
++}
++
++static void s3c6410_pm_prepare(void)
++{
++
++}
++
++static int s3c6410_pm_add(struct sys_device *sysdev)
++{
++ pm_cpu_prep = s3c6410_pm_prepare;
++ pm_cpu_sleep = s3c6410_cpu_suspend;
++
++ return 0;
++}
++
++static struct sleep_save s3c6410_sleep[] = {
++
++};
++
++static int s3c6410_pm_suspend(struct sys_device *dev, pm_message_t state)
++{
++ s3c2410_pm_do_save(s3c6410_sleep, ARRAY_SIZE(s3c6410_sleep));
++ return 0;
++}
++
++static int s3c6410_pm_resume(struct sys_device *dev)
++{
++ unsigned long tmp;
++#if 0
++ tmp = __raw_readl(S3C_PWR_CFG);
++ tmp &= ~(0x60<<0);
++ tmp |= (0x1<<5);
++ __raw_writel(tmp, S3C_PWR_CFG);
++#endif
++ s3c2410_pm_do_restore(s3c6410_sleep, ARRAY_SIZE(s3c6410_sleep));
++ return 0;
++}
++
++static struct sysdev_driver s3c6410_pm_driver = {
++ .add = s3c6410_pm_add,
++ .suspend = s3c6410_pm_suspend,
++ .resume = s3c6410_pm_resume,
++};
++
++static __init int s3c6410_pm_init(void)
++{
++ return sysdev_driver_register(&s3c6410_sysclass, &s3c6410_pm_driver);
++}
++
++arch_initcall(s3c6410_pm_init);
++
+diff --git a/arch/arm/mach-s3c6410/pwm/Kconfig b/arch/arm/mach-s3c6410/pwm/Kconfig
+new file mode 100644
+index 0000000..24b7d6e
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/pwm/Kconfig
+@@ -0,0 +1,27 @@
++#
++# PWM Timer configuration
++#
++
++menu "Pulse Width Modulation Timer"
++
++config PWM
++ tristate "Pulse Width Modulation (PWM) Timer support"
++
++#config S3C2450_PWM
++# bool "S3C2450 PWM support"
++# depends on CPU_S3C2450 && PWM
++# help
++# S3C2450 PWM support.
++
++#config S3C2416_PWM
++# bool "S3C2416 PWM support"
++# depends on CPU_S3C2416 && PWM
++# help
++# S3C2416 PWM support.
++
++config S3C6410_PWM
++ bool "S3C6410/30 PWM support"
++ depends on CPU_S3C6410 && PWM
++ help
++ S3C6410 PWM support.
++endmenu
+diff --git a/arch/arm/mach-s3c6410/pwm/Makefile b/arch/arm/mach-s3c6410/pwm/Makefile
+new file mode 100644
+index 0000000..7141ea2
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/pwm/Makefile
+@@ -0,0 +1,8 @@
++#
++# Makefile for PWM drivers.
++#
++
++obj-$(CONFIG_S3C6410_PWM) += pwm-s3c6410.o
++#obj-$(CONFIG_S3C2450_PWM) += pwm-s3c2450.o
++#obj-$(CONFIG_S3C2416_PWM) += pwm-s3c2450.o
++
+diff --git a/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c b/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c
+new file mode 100644
+index 0000000..f6203ce
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c
+@@ -0,0 +1,379 @@
++/* linux/arch/arm/mach-s3c64xx/pwm.c
++ *
++ * (c) 2003-2005 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C64XX PWM core
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Changelog:
++ * This file is based on the Sangwook Lee/Samsung patches, re-written due
++ * to various ommisions from the code (such as flexible pwm configuration)
++ * for use with the BAST system board.
++ *
++ *
++ */
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++
++#include <asm/plat-s3c/regs-timer.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/irqs.h>
++#include "pwm-s3c6410.h"
++
++
++s3c6410_pwm_chan_t s3c_chans[S3C_PWM_CHANNELS];
++
++
++static inline void
++s3c6410_pwm_buffdone(s3c6410_pwm_chan_t *chan, void *dev)
++{
++
++ if (chan->callback_fn != NULL) {
++ (chan->callback_fn)( dev);
++ }
++}
++
++
++static int s3c6410_pwm_start (int channel)
++{
++ unsigned long tcon;
++ tcon = __raw_readl(S3C_TCON);
++ switch(channel)
++ {
++ case 0:
++ tcon |= S3C_TCON_T0START;
++ tcon &= ~S3C_TCON_T0MANUALUPD;
++ break;
++ case 1:
++ tcon |= S3C_TCON_T1START;
++ tcon &= ~S3C_TCON_T1MANUALUPD;
++ break;
++ case 2:
++ tcon |= S3C_TCON_T2START;
++ tcon &= ~S3C_TCON_T2MANUALUPD;
++ break;
++ case 3:
++ tcon |= S3C_TCON_T3START;
++ tcon &= ~S3C_TCON_T3MANUALUPD;
++ break;
++
++ }
++ __raw_writel(tcon, S3C_TCON);
++
++ return 0;
++}
++
++
++int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned long g_tcmp)
++{
++ unsigned long tcon;
++ unsigned long tcnt;
++ unsigned long tcmp;
++ unsigned long tcfg1;
++ unsigned long tcfg0;
++ unsigned long pclk;
++ struct clk *clk;
++
++ printk("PWM channel %d set g_tcnt = %ld, g_tcmp = %ld \n", channel, g_tcnt, g_tcmp);
++
++ tcnt = 0xffffffff; /* default value for tcnt */
++
++ /* read the current timer configuration bits */
++ tcon = __raw_readl(S3C_TCON);
++ tcfg1 = __raw_readl(S3C_TCFG1);
++ tcfg0 = __raw_readl(S3C_TCFG0);
++
++ clk = clk_get(NULL, "timers");
++ if (IS_ERR(clk))
++ panic("failed to get clock for pwm timer");
++
++ clk_enable(clk);
++
++ pclk = clk_get_rate(clk);
++
++ /* configure clock tick */
++ switch(channel)
++ {
++ case 0:
++ /* set gpio as PWM TIMER0 to signal output*/
++ s3c_gpio_cfgpin(S3C_GPF14, S3C_GPF14_PWM_TOUT0);
++ s3c_gpio_setpin(S3C_GPF14, 0);
++ tcfg1 &= ~S3C_TCFG1_MUX0_MASK;
++ tcfg1 |= S3C_TCFG1_MUX0_DIV2;
++
++ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK;
++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER0_SHIFT;
++ tcon &= ~(7<<0);
++ tcon |= S3C_TCON_T0RELOAD;
++ break;
++
++ case 1:
++ /* set gpio as PWM TIMER1 to signal output*/
++ s3c_gpio_cfgpin(S3C_GPF15, S3C_GPF15_PWM_TOUT1);
++ s3c_gpio_setpin(S3C_GPF15, 0);
++ tcfg1 &= ~S3C_TCFG1_MUX1_MASK;
++ tcfg1 |= S3C_TCFG1_MUX1_DIV2;
++
++ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK;
++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER0_SHIFT;
++
++ tcon &= ~(7<<8);
++ tcon |= S3C_TCON_T1RELOAD;
++ break;
++ case 2:
++ tcfg1 &= ~S3C_TCFG1_MUX2_MASK;
++ tcfg1 |= S3C_TCFG1_MUX2_DIV2;
++
++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK;
++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT;
++
++ tcon &= ~(7<<12);
++ tcon |= S3C_TCON_T2RELOAD;
++ break;
++ case 3:
++ tcfg1 &= ~S3C_TCFG1_MUX3_MASK;
++ tcfg1 |= S3C_TCFG1_MUX3_DIV2;
++
++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK;
++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT;
++ tcon &= ~(7<<16);
++ tcon |= S3C_TCON_T3RELOAD;
++ break;
++ }
++
++#if 0
++
++ tcnt = (pclk / ((PRESCALER)*DIVIDER)) / usec;
++
++ printk("s3c6410 pwm timer tcnt=0x%08lx, pclk=0x%08lx, PRESCALER=%d, DIVIDER=%d, usec=%d\n",
++ tcnt, pclk, PRESCALER, DIVIDER, usec);
++
++ /* timers reload after counting zero, so reduce the count by 1 */
++
++ tcnt--;
++#endif
++
++ __raw_writel(tcfg1, S3C_TCFG1);
++ __raw_writel(tcfg0, S3C_TCFG0);
++
++
++ __raw_writel(tcon, S3C_TCON);
++ tcnt = 160;
++#if 0
++ if (tcnt > 0xffffffff) {
++ panic("setup_timer: HZ is too small, cannot configure timer!");
++ return 0;
++ }
++#endif
++ __raw_writel(tcnt, S3C_TCNTB(channel));
++ tcmp = 110;
++ __raw_writel(tcmp, S3C_TCMPB(channel));
++
++ switch(channel)
++ {
++ case 0:
++ tcon |= S3C_TCON_T0MANUALUPD;
++ break;
++ case 1:
++ tcon |= S3C_TCON_T1MANUALUPD;
++ break;
++ case 2:
++ tcon |= S3C_TCON_T2MANUALUPD;
++ break;
++ case 3:
++ tcon |= S3C_TCON_T3MANUALUPD;
++ break;
++ }
++ __raw_writel(tcon, S3C_TCON);
++
++ tcnt = g_tcnt;
++ __raw_writel(tcnt, S3C_TCNTB(channel));
++
++ tcmp = g_tcmp;
++ __raw_writel(tcmp, S3C_TCMPB(channel));
++
++ /* start the timer running */
++ s3c6410_pwm_start ( channel);
++
++ return 0;
++}
++
++
++static irqreturn_t s3c6410_pwm_irq(int irq, void *devpw)
++{
++ s3c6410_pwm_chan_t *chan = (s3c6410_pwm_chan_t *)devpw;
++ void *dev=chan->dev;
++
++ /* modify the channel state */
++ s3c6410_pwm_buffdone(chan, dev);
++
++ return IRQ_HANDLED;
++}
++
++
++int s3c6410_pwm_request(pwmch_t channel, s3c_pwm_client_t *client, void *dev)
++{
++ s3c6410_pwm_chan_t *chan = &s3c_chans[channel];
++ unsigned long flags;
++ int err;
++
++ pr_debug("pwm%d: s3c_request_pwm: client=%s, dev=%p\n",
++ channel, client->name, dev);
++
++
++ local_irq_save(flags);
++
++
++ if (chan->in_use) {
++ if (client != chan->client) {
++ printk(KERN_ERR "pwm%d: already in use\n", channel);
++ local_irq_restore(flags);
++ return -EBUSY;
++ } else {
++ printk(KERN_ERR "pwm%d: client already has channel\n", channel);
++ }
++ }
++
++ chan->client = client;
++ chan->in_use = 1;
++ chan->dev = dev;
++
++ if (!chan->irq_claimed) {
++ pr_debug("pwm%d: %s : requesting irq %d\n",
++ channel, __FUNCTION__, chan->irq);
++
++ err = request_irq(chan->irq, s3c6410_pwm_irq, SA_INTERRUPT,
++ client->name, (void *)chan);
++
++ if (err) {
++ chan->in_use = 0;
++ local_irq_restore(flags);
++
++ printk(KERN_ERR "%s: cannot get IRQ %d for PWM %d\n",
++ client->name, chan->irq, chan->number);
++ return err;
++ }
++
++ chan->irq_claimed = 1;
++ chan->irq_enabled = 1;
++ }
++
++ local_irq_restore(flags);
++
++ /* need to setup */
++
++ pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
++
++ return 0;
++}
++
++int s3c6410_pwm_free (pwmch_t channel, s3c_pwm_client_t *client)
++{
++ s3c6410_pwm_chan_t *chan = &s3c_chans[channel];
++ unsigned long flags;
++
++
++ local_irq_save(flags);
++
++ if (chan->client != client) {
++ printk(KERN_WARNING "pwm%d: possible free from different client (channel %p, passed %p)\n",
++ channel, chan->client, client);
++ }
++
++ /* sort out stopping and freeing the channel */
++
++
++ chan->client = NULL;
++ chan->in_use = 0;
++
++ if (chan->irq_claimed)
++ free_irq(chan->irq, (void *)chan);
++ chan->irq_claimed = 0;
++
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++
++int s3c6410_pwm_set_buffdone_fn(pwmch_t channel, s3c_pwm_cbfn_t rtn)
++{
++ s3c6410_pwm_chan_t *chan = &s3c_chans[channel];
++
++
++ pr_debug("%s: chan=%d, callback rtn=%p\n", __FUNCTION__, channel, rtn);
++
++ chan->callback_fn = rtn;
++
++ return 0;
++}
++
++
++#define s3c6410_pwm_suspend NULL
++#define s3c6410_pwm_resume NULL
++
++struct sysdev_class pwm_sysclass = {
++ set_kset_name("s3c-pwm"),
++ .suspend = s3c6410_pwm_suspend,
++ .resume = s3c6410_pwm_resume,
++};
++
++
++/* initialisation code */
++
++static int __init s3c6410_init_pwm(void)
++{
++ s3c6410_pwm_chan_t *cp;
++ int channel;
++ int ret;
++
++ printk("S3C PWM Driver, (c) 2006-2007 Samsung Electronics\n");
++
++ ret = sysdev_class_register(&pwm_sysclass);
++ if (ret != 0) {
++ printk(KERN_ERR "pwm sysclass registration failed\n");
++ return -ENODEV;
++ }
++
++ for (channel = 0; channel < S3C_PWM_CHANNELS; channel++) {
++ cp = &s3c_chans[channel];
++
++ memset(cp, 0, sizeof(s3c6410_pwm_chan_t));
++
++ cp->number = channel;
++ /* pwm channel irqs are in order.. */
++ cp->irq = channel + IRQ_TIMER0;
++
++ /* register system device */
++
++ ret = sysdev_register(&cp->sysdev);
++
++ pr_debug("PWM channel %d , irq %d\n",
++ cp->number, cp->irq);
++ }
++#ifdef PWM_using_sample
++ s3c6410_timer_setup(1,10,1000,10);
++#endif
++
++ return ret;
++}
++__initcall(s3c6410_init_pwm);
+diff --git a/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.h b/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.h
+new file mode 100644
+index 0000000..984bcd7
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.h
+@@ -0,0 +1,125 @@
++/* linux/include/asm-arm/arch-bast/dma.h
++ *
++ * Copyright (C) 2003,2004 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * Samsung S3C PWM support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Changelog:
++ * ??-May-2003 BJD Created file
++ * ??-Jun-2003 BJD Added more dma functionality to go with arch
++ * 10-Nov-2004 BJD Added sys_device support
++*/
++
++#ifndef __ASM_ARCH_DMA_H
++#define __ASM_ARCH_DMA_H __FILE__
++
++#include <linux/sysdev.h>
++#include <asm/plat-s3c/regs-timer.h>
++
++
++#define pwmch_t int
++
++/* we have 4 pwm channels */
++#define S3C_PWM_CHANNELS 4
++
++
++struct s3c_pwm_client {
++ char *name;
++};
++
++typedef struct s3c_pwm_client s3c_pwm_client_t;
++
++
++typedef struct s3c_pwm_chan_s s3c6410_pwm_chan_t;
++
++/* s3c_pwm_cbfn_t
++ *
++ * buffer callback routine type
++*/
++
++typedef void (*s3c_pwm_cbfn_t)(void *buf);
++
++
++
++/* struct s3c_pwm_chan_s
++ *
++ * full state information for each DMA channel
++*/
++
++struct s3c_pwm_chan_s {
++ /* channel state flags and information */
++ unsigned char number; /* number of this dma channel */
++ unsigned char in_use; /* channel allocated */
++ unsigned char irq_claimed; /* irq claimed for channel */
++ unsigned char irq_enabled; /* irq enabled for channel */
++
++ /* channel state */
++
++ s3c_pwm_client_t *client;
++ void *dev;
++ /* channel configuration */
++ unsigned int flags; /* channel flags */
++
++ /* channel's hardware position and configuration */
++ unsigned int irq; /* channel irq */
++
++ /* driver handles */
++ s3c_pwm_cbfn_t callback_fn; /* buffer done callback */
++
++ /* system device */
++ struct sys_device sysdev;
++};
++
++/* the currently allocated channel information */
++extern s3c6410_pwm_chan_t s3c_chans[];
++
++
++/* functions --------------------------------------------------------------- */
++
++/* s3c6410_pwm_request
++ *
++ * request a pwm channel exclusivley
++*/
++
++extern int s3c6410_pwm_request(pwmch_t channel, s3c_pwm_client_t *, void *dev);
++
++
++/* s3c_dma_ctrl
++ *
++ * change the state of the dma channel
++*/
++
++//extern int s3c_dma_ctrl(dmach_t channel, s3c_chan_op_t op);
++
++/* s3c_dma_setflags
++ *
++ * set the channel's flags to a given state
++*/
++
++
++/* s3c6410_pwm_free
++ *
++ * free the dma channel (will also abort any outstanding operations)
++*/
++
++extern int s3c6410_pwm_free(pwmch_t channel, s3c_pwm_client_t *);
++
++
++/* s3c_dma_config
++ *
++ * configure the dma channel
++*/
++
++
++
++
++extern int s3c6410_pwm_set_buffdone_fn(pwmch_t, s3c_pwm_cbfn_t rtn);
++
++extern int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned long g_tcmp);
++
++#endif /* __ASM_ARCH_DMA_H */
+diff --git a/arch/arm/mach-s3c6410/s3c6410.c b/arch/arm/mach-s3c6410/s3c6410.c
+new file mode 100644
+index 0000000..d73c929
+--- /dev/null
++++ b/arch/arm/mach-s3c6410/s3c6410.c
+@@ -0,0 +1,148 @@
++
++/* linux/arch/arm/mach-s3c6410/s3c6410.c
++ *
++ * Copyright (c) 2006, Samsung Electronics
++ * All rights reserved.
++ *
++ * Samsung S3C6410 Mobile CPU support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * derived from linux/arch/arm/mach-s3c2410/devs.c, written by
++ * Ben Dooks <ben@simtec.co.uk>
++ */
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/clk.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <asm/proc-fns.h>
++#include <asm/arch/idle.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/map.h>
++#include <asm/plat-s3c/nand.h>
++
++#include <asm/plat-s3c64xx/s3c6410.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/common-smdk.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++//#define T32_PROBE_TEST
++
++/* Serial port registrations */
++
++static struct map_desc s3c6410_iodesc[] __initdata = {
++ IODESC_ENT(SROMC),
++ IODESC_ENT(TIMER),
++ IODESC_ENT(LCD),
++ IODESC_ENT(HOSTIFB),
++ IODESC_ENT(OTGSFR),
++ IODESC_ENT(OTG),
++};
++
++/* s3c6410_idle
++ *
++ * use the standard idle call by ensuring the idle mode
++ * in power config, then issuing the idle co-processor
++ * instruction
++*/
++
++static void s3c6410_idle(void)
++{
++ unsigned long tmp;
++
++ /* ensure our idle mode is to go to idle */
++
++ /* Set WFI instruction to SLEEP mode */
++
++#ifdef T32_PROBE_TEST
++ gpio_direction_output(S3C_GPF13);
++ gpio_set_value(S3C_GPF13, 0);
++#endif
++
++ tmp = __raw_readl(S3C_PWR_CFG);
++ tmp &= ~(0x3<<5);
++ tmp |= (0x1<<5);
++ __raw_writel(tmp, S3C_PWR_CFG);
++
++ cpu_do_idle();
++
++#ifdef T32_PROBE_TEST
++ gpio_set_value(S3C_GPF13, 1);
++#endif
++}
++
++
++void __init s3c6410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
++{
++ s3c24xx_init_uartdevs("s3c-uart", s3c2410_uart_resources, cfg, no);
++}
++
++struct sysdev_class s3c6410_sysclass = {
++ set_kset_name("s3c6410-core"),
++};
++
++static struct sys_device s3c6410_sysdev = {
++ .cls = &s3c6410_sysclass,
++};
++
++
++static int __init s3c6410_core_init(void)
++{
++ return sysdev_class_register(&s3c6410_sysclass);
++}
++
++core_initcall(s3c6410_core_init);
++
++void __init s3c6410_map_io(struct map_desc *mach_desc, int size)
++{
++ /* register our io-tables */
++ iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
++ iotable_init(mach_desc, size);
++
++ /* set our idle function */
++ s3c24xx_idle = s3c6410_idle;
++}
++
++int __init s3c6410_init(void)
++{
++ int ret;
++
++ printk("s3c6410: Initialising architecture\n");
++
++ ret = sysdev_register(&s3c6410_sysdev);
++
++ if (ret != 0)
++ printk(KERN_ERR "failed to register sysdev for s3c6410\n");
++
++ /* Rename devices that are specific to S3C6410 */
++
++#if defined (CONFIG_S3C_SIR)
++ s3c24xx_uart_src[3]->name = "s3c-irda";
++#endif
++ s3c_device_lcd.name = "s3c-lcd";
++ s3c_device_nand.name = "s3c-nand";
++
++ return ret;
++}
++
+diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
+new file mode 100644
+index 0000000..e9ab834
+--- /dev/null
++++ b/arch/arm/mach-s5pc100/Kconfig
+@@ -0,0 +1,25 @@
++# arch/arm/mach-s5pc100/Kconfig
++#
++# Licensed under GPLv2
++
++menu "S5PC100 Machines"
++
++config MACH_SMDKC100
++ bool "SMDKC100"
++ select CPU_S5PC100
++ select MACH_SMDK
++ help
++ Say Y here if you are using the S5PC100
++endmenu
++
++config CPU_S5PC100
++ bool
++ depends on ARCH_S3C2410
++ select S5PC100_PM if PM
++ help
++ Support for S5PC100 Samsung Mobile CPU based systems.
++
++config S5PC100_PM
++ bool
++ help
++ Internal config node to apply S5PC100 power management
+diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
+new file mode 100644
+index 0000000..0490da5
+--- /dev/null
++++ b/arch/arm/mach-s5pc100/Makefile
+@@ -0,0 +1,26 @@
++
++#
++# Makefile for the linux kernel.
++#
++
++# Object file lists.
++obj-y :=
++led-y := leds.o
++obj-n :=
++obj- :=
++
++# smdk6410 machine-specific support
++obj-$(CONFIG_CPU_S5PC100) += s5pc100.o clock.o irq.o
++
++obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
++
++#obj-$(CONFIG_CPU_S3C6410) += irq.o dma.o
++#obj-$(CONFIG_S3C64XX_DMA_SYSFS) += dma-sysfs.o
++#obj-$(CONFIG_S3C6410_PM) += pm.o
++
++# Power Management support
++
++# LEDs support
++#led-$(CONFIG_MACH_SMDK6410) += leds-s3c6410.o
++#obj-$(CONFIG_LEDS) += $(led-y)
++
+diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
+new file mode 100644
+index 0000000..2526d6a
+--- /dev/null
++++ b/arch/arm/mach-s5pc100/clock.c
+@@ -0,0 +1,841 @@
++/* linux/arch/arm/mach-s5pc100/clock.c
++ *
++ * Copyright (c) 2004 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2412 Clock control support
++ *
++ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
++ **
++ ** Copyright (C) 2004 ARM Limited.
++ ** Written by Deep Blue Solutions Limited.
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/delay.h>
++
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/mach/map.h>
++
++#include <asm/hardware.h>
++#include <asm/atomic.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/plat-s5p/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#if 0
++#define HCLK_GATING_ON_LIST S3C_CLKCON_HCLK_BUS | S3C_CLKCON_HCLK_DDR1 | S3C_CLKCON_HCLK_DDR0 |\
++ S3C_CLKCON_HCLK_MEM1 | S3C_CLKCON_HCLK_MEM0 | S3C_CLKCON_HCLK_DMA0 |\
++ S3C_CLKCON_HCLK_DMA1 | S3C_CLKCON_HCLK_INTC | S3C_CLKCON_HCLK_LCD |\
++ S3C_CLKCON_HCLK_DHOST | S3C_CLKCON_HCLK_POST0 | S3C_CLKCON_HCLK_MFC
++
++#define PCLK_GATING_ON_LIST S3C_CLKCON_PCLK_GPIO | S3C_CLKCON_PCLK_UART0 | S3C_CLKCON_PCLK_UART1 | S3C_CLKCON_PCLK_MFC
++
++#define SCLK_GATING_ON_LIST S3C_CLKCON_SCLK_UART | S3C_CLKCON_SCLK_LCD27 | S3C_CLKCON_SCLK_LCD | S3C_CLKCON_SCLK_POST1_27 | \
++ S3C_CLKCON_SCLK_POST0_27 | S3C_CLKCON_SCLK_POST1 | S3C_CLKCON_SCLK_POST0 | S3C_CLKCON_SCLK_MFC
++
++/* Select the source clock of USB Host. 0:48MHz, 1:FoutEpll */
++#define S3C_USB_CLKSRC_EPLL 0
++
++static int s3c6410_clkcon_enable_h(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_HCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_HCLK_GATE);
++
++ return 0;
++}
++
++static int s3c6410_clkcon_enable_p(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_PCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_PCLK_GATE);
++
++ return 0;
++}
++
++static int s3c6410_clkcon_enable_s(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_SCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_SCLK_GATE);
++
++ return 0;
++}
++
++
++static int s3c6410_clkcon_enable_others(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_OTHERS);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_OTHERS);
++
++ return 0;
++}
++
++/*This function returns the virtual address of gating register*/
++ulong clk_get_gate_reg (struct clk *clk)
++{
++ struct clk *parent_clk = clk_get_parent(clk) ;
++
++ if (strcmp(parent_clk->name, "hclk") == 0)
++ return (unsigned long) S3C_HCLK_GATE;
++ else if (strcmp(parent_clk->name, "pclk") == 0)
++ return (unsigned long) S3C_PCLK_GATE;
++ else if (strcmp(parent_clk->name, "clk48m") == 0)
++ return (unsigned long) S3C_OTHERS;
++ else
++ return (unsigned long) S3C_SCLK_GATE;
++}
++
++int s3c_clkcon_enable (struct clk *clk, int enable)
++{
++ unsigned long gate_reg;
++
++ gate_reg = clk_get_gate_reg(clk);
++ s3c_clk_enable(clk->ctrlbit, enable, gate_reg);
++ return 0;
++}
++
++static unsigned long s3c6410_clk_getrate(struct clk *clk)
++{
++ /* set clock rate to use in drivers */
++ if (!clk->rate) {
++ if (clk->parent) {
++ clk->rate = clk->parent->rate;
++ }
++ }
++ return clk->rate;
++}
++
++
++static int s3c6410_epll_clk_uart_enable (struct clk *clk, int enable)
++{
++ s3c6410_clkcon_enable_s(clk, enable);
++
++ /* MUXepll : FOUTepll */
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++
++ /* UARTsel : MOUTepll */
++ writel((readl(S3C_CLK_SRC) & ~(0x1 << 13)) | (0 << 13), S3C_CLK_SRC);
++
++ return 0;
++}
++
++
++static int s3c6410_setrate_epll_clk_192m(struct clk *clk, unsigned long rate)
++{
++ writel(S3C_EPLL_EN|S3C_EPLLVAL(32,1,1), S3C_EPLL_CON0);
++ writel(0, S3C_EPLL_CON1);
++ mdelay(5);
++
++ return 0;
++}
++
++static unsigned long s3c6410_getrate_epll_clk_192m(struct clk *clk)
++{
++ s3c6410_setrate_epll_clk_192m(clk, 192000000);
++ clk->rate = 192000000;
++ return clk->rate;
++}
++
++
++static struct clk clk_epll_uart_192m = {
++ .name = "epll_clk_uart_192m",
++ .id = -1,
++ .parent = &clk_epll,
++ .enable = s3c6410_epll_clk_uart_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_UART,
++ .set_rate = s3c6410_setrate_epll_clk_192m,
++ .get_rate = s3c6410_getrate_epll_clk_192m,
++};
++
++
++static unsigned long s3c6410_mpll_get_clk(struct clk *clk)
++{
++ unsigned long mpll_con;
++ unsigned long m = 0;
++ unsigned long p = 0;
++ unsigned long s = 0;
++ unsigned long ret;
++
++ mpll_con = readl(S3C_MPLL_CON);
++
++ m = (mpll_con >> 16) & 0x3ff;
++ p = (mpll_con >> 8) & 0x3f;
++ s = mpll_con & 0x3;
++
++ ret = (m * (12000000 / (p * (1 << s))));
++
++ return (((readl(S3C_CLK_DIV0) >> 13 ) & 0x1) ? (ret / 2) : ret);
++}
++
++static int s3c6410_clk_mpll_dout_enable(struct clk *clk, int enable)
++{
++ writel(readl(S3C_CLK_SRC) | (0x1 << 1), S3C_CLK_SRC);
++
++ return 0;
++}
++
++static int s3c6410_setrate_clk_mpll_dout(struct clk *clk, unsigned long rate)
++{
++ /* To get 266Mhz */
++ writel((readl(S3C_CLK_DIV0) & ~(0x1 << 4)) | (rate << 4) , S3C_CLK_DIV0);
++
++ return 0;
++}
++
++static unsigned long s3c6410_getrate_clk_mpll_dout(struct clk *clk)
++{
++ s3c6410_setrate_clk_mpll_dout(clk, 1);
++
++ return s3c6410_mpll_get_clk(clk);
++}
++
++static struct clk clk_mpll_dout = {
++ .name = "DOUTmpll",
++ .id = -1,
++ .parent = &clk_mpll,
++ .enable = s3c6410_clk_mpll_dout_enable,
++ .ctrlbit = 0,
++ .set_rate = s3c6410_setrate_clk_mpll_dout,
++ .get_rate = s3c6410_getrate_clk_mpll_dout,
++};
++
++static int s3c6410_clk_mpll_uart_enable(struct clk *clk, int enable)
++{
++ s3c6410_clkcon_enable_s(clk, enable);
++ writel(readl(S3C_CLK_SRC) | (0x1 << 13) | S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++
++ return 0;
++}
++
++static int s3c6410_setrate_clk_mpll_uart(struct clk *clk, unsigned long rate)
++{
++ writel(readl(S3C_CLK_DIV2) & ~(0xf << 16) , S3C_CLK_DIV2);
++
++ return 0;
++}
++
++static unsigned long s3c6410_getrate_clk_mpll_uart(struct clk *clk)
++{
++ s3c6410_setrate_clk_mpll_uart(clk, 0);
++
++ return s3c6410_mpll_get_clk(clk);
++}
++
++static struct clk clk_mpll_uart = {
++ .name = "mpll_clk_uart",
++ .id = -1,
++ .parent = &clk_mpll,
++ .enable = s3c6410_clk_mpll_uart_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_UART,
++ .set_rate = s3c6410_setrate_clk_mpll_uart,
++ .get_rate = s3c6410_getrate_clk_mpll_uart,
++};
++
++
++/* For Camera interface */
++static struct clk clk_cam_h = {
++ .name = "camif-hclk",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_CAMIF,
++};
++
++#define CAMDIV_val 20
++
++static int s3c6410_setrate_camera(struct clk *clk, unsigned long rate)
++{
++ unsigned int camclk_div, val;
++ unsigned long src_clk = clk_get_rate(clk->parent);
++
++ if (rate == 4800000) {
++ printk(KERN_INFO "External camera clock is set to 48MHz\n");
++ }
++ else if (rate > 48000000) {
++ printk(KERN_ERR "Invalid camera clock\n");
++ }
++
++ camclk_div = src_clk / rate;
++ printk("Parent clock for Camera = %ld, CAMDIV = %d\n", src_clk, camclk_div);
++
++ val = readl(S3C_CLK_DIV0);
++ val &= ~(0xf<<CAMDIV_val);
++ writel(val, S3C_CLK_DIV0);
++
++ /* CAM CLK DIVider Ratio = (EPLL clk)/(camclk_div) */
++ val |= ((camclk_div -1 ) << CAMDIV_val);
++ writel(val, S3C_CLK_DIV0);
++ val = readl(S3C_CLK_DIV0);
++
++ return 0;
++}
++
++
++/* For HS-MMC controller */
++static unsigned long s3c6410_getrate_DOUTmpll_hsmmc_clk(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = readl(S3C_CLK_DIV1);
++ div &= ~S3C_CLKDIV1_HSMMCDIV_MASK;
++
++ /* MMC_RATIO = 2+1 */
++ div |= 0x2;
++
++ writel(div, S3C_CLK_DIV1);
++
++ return parent_rate / (0x2 + 1);
++}
++
++static unsigned long s3c6410_getrate_DOUTmpll_hsmmc1_clk(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = readl(S3C_CLK_DIV1);
++ div &= ~S3C_CLKDIV1_HSMMCDIV1_MASK;
++
++ /* MMC1_RATIO = 2+1 */
++ div |= (0x2<<S3C_CLKDIV1_HSMMCDIV1_SHIFT);
++
++ writel(div, S3C_CLK_DIV1);
++
++ return parent_rate / (0x2 + 1);
++}
++
++static struct clk clk_hsmmc_DOUTmpll_mmc0 = {
++ .name = "sclk_DOUTmpll_mmc0",
++ .id = -1,
++ .parent = &clk_mpll_dout,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC0,
++ .get_rate = s3c6410_getrate_DOUTmpll_hsmmc_clk,
++ .usage = 0,
++};
++
++static struct clk clk_hsmmc_DOUTmpll_mmc1 = {
++ .name = "sclk_DOUTmpll_mmc1",
++ .id = -1,
++ .parent = &clk_mpll_dout,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC1,
++ .get_rate = s3c6410_getrate_DOUTmpll_hsmmc1_clk,
++ .usage = 0,
++};
++
++static struct clk clk_hsmmc_DOUTmpll_mmc2 = {
++ .name = "sclk_DOUTmpll_mmc2",
++ .id = -1,
++ .parent = &clk_mpll_dout,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC2,
++ .get_rate = s3c6410_getrate_DOUTmpll_hsmmc_clk,
++ .usage = 0,
++};
++
++
++
++/* clocks to add straight away */
++
++static struct clk *clks[] __initdata = {
++ &clk_epll_uart_192m,
++ &clk_cam_h,
++ &clk_mpll_dout,
++ &clk_mpll_uart,
++ &clk_hsmmc_DOUTmpll_mmc0,
++ &clk_hsmmc_DOUTmpll_mmc1,
++ &clk_hsmmc_DOUTmpll_mmc2,
++};
++
++
++static struct clk init_clocks_disable[] = {
++ {
++ .name = "nand",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ //.ctrlbit = S3C_CLKCON_HCLK_NAND,
++ },
++ {
++ .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_TSADC,
++ },
++ {
++ .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIC,
++ },
++ {
++ .name = "iis",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIS0,
++ },
++ {
++ .name = "iis",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIS1,
++ },
++ {
++ .name = "spi",
++ .id = 0,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI0,
++ },
++ {
++ .name = "spi",
++ .id = 1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI1,
++ }
++};
++
++
++/* standard clock definitions */
++static struct clk init_clocks[] = {
++ /* AHB devices */
++ { .name = "dma 1",
++ .id = -1,
++ .parent = &clk_hd0,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_DMA1,
++ },
++ { .name = "dma 0",
++ .id = -1,
++ .parent = &clk_hd0,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_DMA0,
++ },
++ { .name = "lcd",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_LCD,
++ },
++ { .name = "TZIC",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_TZIC,
++ },
++ { .name = "INTC",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_INTC,
++ },
++ { .name = "usb-host",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_UHOST,
++ },
++ { .name = "otg",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_USB
++ },
++ { .name = "hsmmc0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .get_rate = s3c6410_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC0
++ },
++ { .name = "hsmmc1",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .get_rate = s3c6410_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC1
++ },
++ { .name = "hsmmc2",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .get_rate = s3c6410_clk_getrate,
++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC2
++ },
++ { .name = "hclk_mfc",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_MFC
++ },
++ { .name = "hclk_post0",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_POST0
++ },
++ { .name = "hclk_jpeg",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_JPEG
++ },
++ { .name = "tv_encoder",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_TV
++ },
++ { .name = "tv_scaler",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_SCALER
++ },
++
++ /* register to use HS-MMC clock */
++ { .name = "sclk_48m",
++ .id = -1,
++ .parent = &clk_48m,
++ .enable = s3c6410_clkcon_enable_others,
++ .ctrlbit = 1<<16, /* USB SIG Mask */
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc0",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc1",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_48m_mmc2",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_mfc",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_MFC,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "sclk_jpeg",
++ .id = -1,
++ .parent = &clk_s,
++ .enable = s3c6410_clkcon_enable_s,
++ .ctrlbit = S3C_CLKCON_SCLK_JPEG,
++ .usage = 0,
++ .rate = 48*1000*1000,
++ },
++ { .name = "cfata",
++ .id = -1,
++ .parent = &clk_h,
++ .enable = s3c6410_clkcon_enable_h,
++ .ctrlbit = S3C_CLKCON_HCLK_IHOST
++ },
++
++ /* APB Devices */
++ { .name = "RTC",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_RTC,
++ },
++ { .name = "GPIO",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_GPIO,
++ },
++ { .name = "UART2",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART2,
++ },
++ { .name = "UART1",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART1,
++ },
++ { .name = "UART0",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_UART0,
++ },
++ { .name = "timers",
++ .id = -1,
++ .parent = &clk_pd1,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_PWM,
++ },
++ { .name = "watchdog",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_WDT,
++ },
++ { .name = "i2c",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_IIC,
++ },
++ { .name = "spi0",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI0,
++ },
++ { .name = "spi1",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_SPI1,
++ },
++ { .name = "adc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_TSADC,
++ },
++ { .name = "pclk_mfc",
++ .id = -1,
++ .parent = &clk_p,
++ .enable = s3c6410_clkcon_enable_p,
++ .ctrlbit = S3C_CLKCON_PCLK_MFC,
++ },
++ {
++ .name = "camera",
++ .id = -1,
++ .parent = &clk_hx2,
++ .enable = s3c_clkcon_enable,
++ .ctrlbit = S3C_CLKCON_SCLK_CAM,
++ .set_rate = s3c6410_setrate_camera,
++ },
++};
++#endif
++
++#if 0
++static int s5pc100_clkcon_enable_pd1(struct clk *clk, int enable)
++{
++ unsigned int clocks = clk->ctrlbit;
++ unsigned long clkcon;
++
++ clkcon = __raw_readl(S3C_PCLK_GATE);
++
++ if (enable)
++ clkcon |= clocks;
++ else
++ clkcon &= ~clocks;
++
++ __raw_writel(clkcon, S3C_PCLK_GATE);
++
++ return 0;
++}
++#endif
++
++
++static struct clk init_clocks[] = {
++ { .name = "timers",
++ .id = -1,
++ .parent = &clk_pd1,
++// .enable = s5pc100_clkcon_enable_pd1,
++// .ctrlbit = S3C_CLKCON_PCLK_PWM,
++ },
++};
++
++void __init s5pc100_init_clocks(int xtal)
++{
++ unsigned long mout_apll, dout_apll, dout_arm;
++ unsigned long mout_mpll, dout_d1;
++ unsigned long armclk, hclkd0, pclkd0, hclkd0_secss;
++ unsigned long hclkd1, pclkd1;
++ unsigned long clk_div0, clk_div1;
++#if 0
++ unsigned long hclkx2;
++ unsigned long hclk;
++ unsigned long pclk;
++ unsigned long epll_clk;
++
++#endif
++ struct clk *clkp;
++ int ptr;
++ int ret;
++
++ clk_xtal.rate = xtal;
++
++ /* now we've got our machine bits initialised, work out what
++ * clocks we've got */
++
++ mout_apll = s5p_get_apll(__raw_readl(S5P_APLL_CON), xtal);
++
++ clk_div0 = __raw_readl(S5P_CLK_DIV0);
++
++ dout_apll = mout_apll / ((clk_div0 & S5P_CLKDIV0_APLL_MASK)+1);
++ dout_arm = dout_apll / (((clk_div0 & S5P_CLKDIV0_ARM_MASK)>>4)+1);
++
++ armclk = dout_arm;
++
++ hclkd0 = dout_arm / (((clk_div0 & S5P_CLKDIV0_D0_MASK)>>8)+1);
++ pclkd0 = hclkd0 / (((clk_div0 & S5P_CLKDIV0_PCLKD0_MASK)>>12)+1);
++ hclkd0_secss = hclkd0 / (((clk_div0 & S5P_CLKDIV0_SECSS_MASK)>>16)+1);
++
++ mout_mpll = s5p_get_mpll(__raw_readl(S5P_MPLL_CON), xtal);
++
++ clk_div1 = __raw_readl(S5P_CLK_DIV1);
++
++ dout_d1 = mout_mpll / (((clk_div1 & S5P_CLKDIV1_D1_MASK)>>12)+1);
++ hclkd1 = dout_d1;
++ pclkd1 = dout_d1 / (((clk_div1 & S5P_CLKDIV1_PCLKD1_MASK)>>16)+1);
++
++ printk("S5PC100: arm %ld.%03ld MHz, hclkd0 %ld.%03ld MHz, pclkd0 %ld.%03ld MHz, hclkd1 %ld.%03ld MHz, pclkd1 %ld.%03ld MHz\n",
++ print_mhz(armclk), print_mhz(hclkd0),print_mhz(pclkd0),print_mhz(hclkd1),print_mhz(pclkd1));
++
++ /* initialise the clocks here, to allow other things like the
++ * console to use them, and to add new ones after the initialisation
++ */
++
++ s5pc1xx_setup_clocks(xtal, armclk, hclkd0, pclkd0, hclkd1, pclkd1);
++
++ /* register clocks from clock array */
++ clkp = init_clocks;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
++ ret = s5pc1xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6410: Failed to register init_clocks : %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ /* set clock rate to use in drivers */
++ if (!clkp->rate) {
++ if (clkp->parent) {
++ clkp->rate = clkp->parent->rate;
++ }
++ }
++
++ }
++#if 0
++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
++ clkp = clks[ptr];
++
++ ret = s5pc1xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6410: Failed to register clks : %s (%d)\n",
++ clkp->name, ret);
++ }
++ }
++
++
++ /* We must be careful disabling the clocks we are not intending to
++ * be using at boot time, as subsytems such as the LCD which do
++ * their own DMA requests to the bus can cause the system to lockup
++ * if they where in the middle of requesting bus access.
++ *
++ * Disabling the LCD clock if the LCD is active is very dangerous,
++ * and therefore the bootloader should be careful to not enable
++ * the LCD clock if it is not needed.
++ */
++
++ /* install (and disable) the clocks we do not need immediately */
++
++ clkp = init_clocks_disable;
++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
++
++ ret = s5pc1xx_register_clock(clkp);
++ if (ret < 0) {
++ printk(KERN_ERR "S3C6410: Failed to register init_clocks_disable: %s (%d)\n",
++ clkp->name, ret);
++ }
++
++ (clkp->enable)(clkp, 0);
++ }
++#endif
++}
++
++
++
+diff --git a/arch/arm/mach-s5pc100/irq.c b/arch/arm/mach-s5pc100/irq.c
+new file mode 100644
+index 0000000..136e050
+--- /dev/null
++++ b/arch/arm/mach-s5pc100/irq.c
+@@ -0,0 +1,48 @@
++/* linux/arch/arm/mach-s3c6410/irq.c
++ *
++ * Copyright (c) 2006 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++*/
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/ptrace.h>
++#include <linux/sysdev.h>
++
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/plat-s3c24xx/pm.h>
++
++static int s5pc100_irq_add(struct sys_device *sysdev)
++{
++ return 0;
++}
++
++static struct sysdev_driver s5pc100_irq_driver = {
++ .add = s5pc100_irq_add,
++ .suspend = s3c24xx_irq_suspend,
++ .resume = s3c24xx_irq_resume,
++};
++
++static int s5pc100_irq_init(void)
++{
++ return sysdev_driver_register(&s5pc100_sysclass, &s5pc100_irq_driver);
++}
++
++arch_initcall(s5pc100_irq_init);
+diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
+new file mode 100644
+index 0000000..60cd807
+--- /dev/null
++++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
+@@ -0,0 +1,205 @@
++/***********************************************************************
++ *
++ * linux/arch/arm/mach-s3c6410/smdk6410.c
++ *
++ * $Id: mach-smdkc100.c,v 1.5 2008/08/27 01:04:36 jsgood Exp $
++ *
++ * Copyright (C) 2005, Samsung Electronics <@samsung.com>
++ * All rights reserved
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ *
++ ***********************************************************************/
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/setup.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++#include <asm/mach/flash.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++
++#include <asm/arch/regs-mem.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/arch/regs-usb-otg-hs.h>
++#include <asm/plat-s3c/nand.h>
++
++#include <asm/plat-s5p/s5pc100.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/arch/hsmmc.h>
++
++#include <asm/plat-s3c24xx/common-smdk.h>
++#include <asm/arch-s3c2410/reserved_mem.h>
++
++extern struct sys_timer s3c_timer;
++
++static struct map_desc smdkc100_iodesc[] __initdata = {
++// IODESC_ENT(CS8900),
++};
++
++#define DEF_UCON S3C_UCON_DEFAULT
++#define DEF_ULCON S3C_LCON_CS8 | S3C_LCON_PNONE
++#define DEF_UFCON S3C_UFCON_RXTRIG8 | S3C_UFCON_FIFOMODE
++
++static struct s3c24xx_uart_clksrc smdkc100_serial_clocks[] = {
++ [0] = {
++ .name = "pclkd1",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ },
++ [1] = {
++ .name = "pclkd0",
++ .divisor = 1,
++ .min_baud = 0,
++ .max_baud = 0,
++ }
++
++};
++
++static struct s3c2410_uartcfg smdkc100_uartcfgs[] = {
++ [0] = {
++ .hwport = 0,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdkc100_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks),
++ },
++ [1] = {
++ .hwport = 1,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdkc100_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks),
++ },
++ [2] = {
++ .hwport = 2,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdkc100_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks),
++ },
++ [3] = {
++ .hwport = 3,
++ .flags = 0,
++ .ucon = DEF_UCON,
++ .ulcon = DEF_ULCON,
++ .ufcon = DEF_UFCON,
++ .clocks = smdkc100_serial_clocks,
++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks),
++ }
++
++};
++
++/*add devices as drivers are integrated*/
++static struct platform_device *smdkc100_devices[] __initdata = {
++#if 0
++ &s3c_device_rtc,
++ &s3c_device_ac97,
++ &s3c_device_iis,
++ &s3c_device_adc,
++ &s3c_device_i2c,
++ &s3c_device_usb,
++ &s3c_device_usbgadget,
++ &s3c_device_tvenc,
++ &s3c_device_tvscaler,
++ &s3c_device_hsmmc0,
++ &s3c_device_hsmmc1,
++ &s3c_device_hsmmc2,
++ &s3c_device_wdt,
++ &s3c_device_jpeg,
++ &s3c_device_vpp,
++ &s3c_device_ide,
++ &s3c_device_mfc,
++ &s3c_device_spi0,
++ &s3c_device_spi1,
++ &s3c_device_g2d,
++ &s3c_device_keypad,
++ &s3c_device_smc911x,
++ &s3c_device_camif,
++ &s3c_device_g3d,
++#endif
++};
++
++
++static void __init smdkc100_map_io(void)
++{
++ s3c24xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc));
++ s3c24xx_init_clocks(0);
++ s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
++}
++
++static void __init smdkc100_fixup (struct machine_desc *desc, struct tag *tags,
++ char **cmdline, struct meminfo *mi)
++{
++ /*
++ * Bank start addresses are not present in the information
++ * passed in from the boot loader. We could potentially
++ * detect them, but instead we hard-code them.
++ */
++ mi->bank[0].start = PHYS_OFFSET;
++
++ mi->bank[0].size = 128*1024*1024;
++
++ mi->bank[0].node = 0;
++
++ mi->nr_banks = 1;
++}
++
++static void __init smdkc100_machine_init (void)
++{
++ platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
++ smdk_machine_init();
++}
++
++MACHINE_START(SMDKC100, "SMDKC100")
++ /* Maintainer: Samsung Electronics */
++ .phys_io = S3C24XX_PA_UART,
++ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
++ .boot_params = S5PC1XX_SDRAM_PA + 0x100,
++
++ .init_irq = s3c_init_irq,
++ .map_io = smdkc100_map_io,
++ .fixup = smdkc100_fixup,
++ .timer = &s3c_timer,
++ .init_machine = smdkc100_machine_init,
++MACHINE_END
++
+diff --git a/arch/arm/mach-s5pc100/s5pc100.c b/arch/arm/mach-s5pc100/s5pc100.c
+new file mode 100644
+index 0000000..d7c74cd
+--- /dev/null
++++ b/arch/arm/mach-s5pc100/s5pc100.c
+@@ -0,0 +1,141 @@
++
++/* linux/arch/arm/mach-s3c6410/s3c6410.c
++ *
++ * Copyright (c) 2006, Samsung Electronics
++ * All rights reserved.
++ *
++ * Samsung S3C6410 Mobile CPU support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * derived from linux/arch/arm/mach-s3c2410/devs.c, written by
++ * Ben Dooks <ben@simtec.co.uk>
++ */
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/list.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/clk.h>
++
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/mach/irq.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <asm/proc-fns.h>
++#include <asm/arch/idle.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/map.h>
++#include <asm/plat-s3c/nand.h>
++
++#include <asm/plat-s3c64xx/s3c6410.h>
++#include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/cpu.h>
++//#include "pm-s3c6400.h"
++
++/* Serial port registrations */
++
++static struct map_desc s5pc100_iodesc[] __initdata = {
++// IODESC_ENT(SROMC),
++// IODESC_ENT(TIMER),
++ IODESC_ENT(LCD),
++// IODESC_ENT(HOSTIFB),
++// IODESC_ENT(OTGSFR),
++// IODESC_ENT(OTG),
++};
++
++/* s5pc100_idle
++ *
++ * use the standard idle call by ensuring the idle mode
++ * in power config, then issuing the idle co-processor
++ * instruction
++*/
++
++static void s5pc100_idle(void)
++{
++#if 0
++ unsigned long tmp;
++
++ /* ensure our idle mode is to go to idle */
++
++ /* Set WFI instruction to SLEEP mode */
++
++ tmp = __raw_readl(S3C_PWR_CFG);
++ tmp &= ~(0x60<<0);
++ tmp |= (0x1<<5);
++ __raw_writel(tmp, S3C_PWR_CFG);
++
++ cpu_do_idle();
++#endif
++}
++
++
++void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
++{
++ s3c24xx_init_uartdevs("s3c-uart", s3c2410_uart_resources, cfg, no);
++}
++
++struct sysdev_class s5pc100_sysclass = {
++ set_kset_name("s5pc100-core"),
++};
++
++static struct sys_device s5pc100_sysdev = {
++ .cls = &s5pc100_sysclass,
++};
++
++
++static int __init s5pc100_core_init(void)
++{
++ return sysdev_class_register(&s5pc100_sysclass);
++}
++
++core_initcall(s5pc100_core_init);
++
++void __init s5pc100_map_io(struct map_desc *mach_desc, int size)
++{
++ /* register our io-tables */
++ iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
++ iotable_init(mach_desc, size);
++
++ /* set our idle function */
++ s3c24xx_idle = s5pc100_idle;
++}
++
++int __init s5pc100_init(void)
++{
++ int ret;
++
++ printk("s5pc100: Initialising architecture\n");
++
++ ret = sysdev_register(&s5pc100_sysdev);
++
++ if (ret != 0)
++ printk(KERN_ERR "failed to register sysdev for s3c6410\n");
++
++ /* Rename devices that are specific to S3C6410 */
++
++#if defined (CONFIG_S3C_SIR)
++ s3c24xx_uart_src[3]->name = "s3c-irda";
++#endif
++#if 0
++ s3c_device_lcd.name = "s3c-lcd";
++ s3c_device_nand.name = "s3c-nand";
++#endif
++
++ return ret;
++}
++
+diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
+index 7868f4d..bd0f705 100644
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -110,7 +110,7 @@ config CPU_ARM9TDMI
+ config CPU_ARM920T
+ bool "Support ARM920T processor"
+ depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
+- default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
++ default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 || CPU_S3C2443
+ select CPU_32v4T
+ select CPU_ABRT_EV4T
+ select CPU_CACHE_V4WT
+@@ -171,8 +171,8 @@ config CPU_ARM925T
+ # ARM926T
+ config CPU_ARM926T
+ bool "Support ARM926T processor"
+- depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
+- default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
++ depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI || CPU_S3C2450 || CPU_S3C2416
++ default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI || CPU_S3C2450 || CPU_S3C2416
+ select CPU_32v5
+ select CPU_ABRT_EV5TJ
+ select CPU_CACHE_VIVT
+@@ -345,8 +345,8 @@ config CPU_XSC3
+ # ARMv6
+ config CPU_V6
+ bool "Support ARM V6 processor"
+- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
+- default y if ARCH_MX3
++ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || CPU_S3C6400 || CPU_S3C6410
++ default y if ARCH_MX3 || CPU_S3C6400 || CPU_S3C6410
+ select CPU_32v6
+ select CPU_ABRT_EV6
+ select CPU_CACHE_V6
+@@ -371,7 +371,8 @@ config CPU_32v6K
+ # ARMv7
+ config CPU_V7
+ bool "Support ARM V7 processor"
+- depends on ARCH_INTEGRATOR
++ depends on ARCH_INTEGRATOR || CPU_S5PC100
++ default y if CPU_S5PC100
+ select CPU_32v6K
+ select CPU_32v7
+ select CPU_ABRT_EV7
+diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
+index a8a7dab..05bc917 100644
+--- a/arch/arm/mm/fault.c
++++ b/arch/arm/mm/fault.c
+@@ -361,6 +361,13 @@ do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+ return 0;
+ }
+
++/* When an MMU exception happens, just do skip. */
++static int
++do_bad_skip(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
++{
++ return 0;
++}
++
+ /*
+ * This abort handler always returns "fault".
+ */
+@@ -386,7 +393,7 @@ static struct fsr_info {
+ { do_bad, SIGILL, BUS_ADRALN, "alignment exception" },
+ { do_bad, SIGBUS, 0, "external abort on linefetch" },
+ { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" },
+- { do_bad, SIGBUS, 0, "external abort on linefetch" },
++ { do_bad_skip, SIGBUS, 0, "external abort on linefetch" },
+ { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" },
+ { do_bad, SIGBUS, 0, "external abort on non-linefetch" },
+ { do_bad, SIGSEGV, SEGV_ACCERR, "section domain fault" },
+diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
+index 31656c3..a1e728e 100644
+--- a/arch/arm/plat-s3c/Kconfig
++++ b/arch/arm/plat-s3c/Kconfig
+@@ -102,3 +102,15 @@ config S3C_LOWLEVEL_UART_PORT
+ such as the `Uncompressing...` at start time. The value of
+ this configuration should be between zero and two. The port
+ must have been initialised by the boot-loader before use.
++
++config SPLIT_ROOT_FILESYSTEM
++ bool "S3C MTD has 4 partitions"
++ depends on ARCH_S3C2410 && MTD
++ help
++ Testing now
++
++config MACH_SMDK
++ bool "S3C MACHINE SMDK"
++ depends on ARCH_S3C2410
++ help
++ Common machine code for SMDK2410 and SMDK2440
+diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
+index b66fb3c..779e6e6 100644
+--- a/arch/arm/plat-s3c24xx/Kconfig
++++ b/arch/arm/plat-s3c24xx/Kconfig
+@@ -6,14 +6,13 @@
+
+ config PLAT_S3C24XX
+ bool
+- depends on ARCH_S3C2410
++ depends on ARCH_S3C2410 && (CPU_S3C2443 || CPU_S3C2450 || CPU_S3C2416)
+ default y if ARCH_S3C2410
+ select NO_IOPORT
+ help
+ Base platform code for any Samsung S3C24XX device
+
+ if PLAT_S3C24XX
+-
+ config CPU_S3C244X
+ bool
+ depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
+@@ -41,9 +40,13 @@ config S3C2410_DMA_DEBUG
+ Enable debugging output for the DMA code. This option sends info
+ to the kernel log, at priority KERN_DEBUG.
+
+-config MACH_SMDK
+- bool
+- help
+- Common machine code for SMDK2410 and SMDK2440
++config S3C24XX_ADC
++ bool "S3C24XX ADC Driver"
++ depends on CPU_S3C2443 || CPU_S3C2450 || CPU_S3C2416
++ help
++ ADC (A/D Conversion) driver for Samsung S3C2443/2450.
+
+ endif
++
++
++
+diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
+index 8e5ccaa..6d76ea7 100644
+--- a/arch/arm/plat-s3c24xx/Makefile
++++ b/arch/arm/plat-s3c24xx/Makefile
+@@ -13,10 +13,10 @@ obj- :=
+ # Core files
+
+ obj-y += cpu.o
+-obj-y += irq.o
++obj-$(CONFIG_PLAT_S3C24XX) += irq.o
+ obj-y += devs.o
+ obj-y += gpio.o
+-obj-y += time.o
++obj-$(CONFIG_PLAT_S3C24XX) += time.o
+ obj-y += clock.o
+
+ # Architecture dependant builds
+@@ -28,3 +28,5 @@ obj-$(CONFIG_PM) += pm.o
+ obj-$(CONFIG_PM) += sleep.o
+ obj-$(CONFIG_S3C2410_DMA) += dma.o
+ obj-$(CONFIG_MACH_SMDK) += common-smdk.o
++obj-$(CONFIG_S3C24XX_ADC) += adc-s3c24xx.o
++obj-$(CONFIG_S3C24XX_DVFS) += s3c24xx-dvfs.o
+diff --git a/arch/arm/plat-s3c24xx/adc-s3c24xx.c b/arch/arm/plat-s3c24xx/adc-s3c24xx.c
+new file mode 100644
+index 0000000..21646f5
+--- /dev/null
++++ b/arch/arm/plat-s3c24xx/adc-s3c24xx.c
+@@ -0,0 +1,314 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
++ * iPAQ H1940 touchscreen support
++ *
++ * ChangeLog
++ *
++ * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
++ * - added clock (de-)allocation code
++ *
++ * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org>
++ * - h1940_ -> s3c24xx (this driver is now also used on the n30
++ * machines :P)
++ * - Debug messages are now enabled with the config option
++ * TOUCHSCREEN_S3C_DEBUG
++ * - Changed the way the value are read
++ * - Input subsystem should now work
++ * - Use ioremap and readl/writel
++ *
++ * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org>
++ * - Make use of some undocumented features of the touchscreen
++ * controller
++ *
++ */
++
++
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++
++#include <asm/plat-s3c/regs-adc.h>
++#include <asm/arch/irqs.h>
++
++
++#define ADC_MINOR 131
++#define ADC_INPUT_PIN _IOW('S', 0x0c, unsigned long)
++
++#undef ADC_WITH_TOUCHSCREEN
++
++struct s3c_adc_mach_info {
++ int delay;
++ int presc;
++ int resol_bit;
++};
++
++
++/* ADC default configuration */
++struct s3c_adc_mach_info s3c_adc_cfg __initdata = {
++ .delay = 10000,
++ .presc = 49,
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ .resol_bit = 12,
++#else
++ .resol_bit = 10,
++#endif
++};
++
++
++static struct clk *adc_clock;
++static void __iomem *base_addr;
++static int adc_port = 0;
++
++#ifdef ADC_WITH_TOUCHSCREEN
++static DEFINE_MUTEX(adc_mutex);
++
++static unsigned long data_for_ADCCON;
++static unsigned long data_for_ADCTSC;
++
++static void s3c_adc_save_SFR_on_ADC(void) {
++
++ data_for_ADCCON = readl(base_addr+S3C2410_ADCCON);
++ data_for_ADCTSC = readl(base_addr+S3C2410_ADCTSC);
++}
++
++static void s3c_adc_restore_SFR_on_ADC(void) {
++
++ writel(data_for_ADCCON, base_addr+S3C2410_ADCCON);
++ writel(data_for_ADCTSC, base_addr+S3C2410_ADCTSC);
++}
++#endif
++
++static int s3c_adc_open(struct inode *inode, struct file *file)
++{
++ printk(KERN_INFO " s3c_adc_open() entered\n");
++ return 0;
++}
++
++static ssize_t
++s3c_adc_read(struct file *file, char __user * buffer,
++ size_t size, loff_t * pos)
++{
++ unsigned long data0;
++ unsigned long data1;
++ int adc_value = 0;
++
++ printk(KERN_INFO " s3c_adc_read() entered\n");
++
++#ifdef ADC_WITH_TOUCHSCREEN
++ mutex_lock(&adc_mutex);
++ s3c_adc_save_SFR_on_ADC();
++#endif
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++ writel(S3C2443_ADCCON_SELMUX(adc_port), base_addr+S3C2443_ADCMUX);
++#else
++ writel(readl(base_addr+S3C2410_ADCCON)|S3C2410_ADCCON_SELMUX(adc_port), base_addr+S3C2410_ADCCON);
++#endif
++
++ udelay(10);
++
++ writel(readl(base_addr+S3C2410_ADCCON)|S3C2410_ADCCON_ENABLE_START, base_addr+S3C2410_ADCCON);
++
++ do {
++ data0 = readl(base_addr+S3C2410_ADCCON);
++ } while(!(data0 & S3C2410_ADCCON_ECFLG));
++
++ data1 = readl(base_addr+S3C2410_ADCDAT0);
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ adc_value = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT;
++#else
++ adc_value = data1 & S3C2410_ADCDAT0_XPDATA_MASK;
++#endif
++
++#ifdef ADC_WITH_TOUCHSCREEN
++ s3c_adc_restore_SFR_on_ADC();
++ mutex_unlock(&adc_mutex);
++#endif
++
++ printk(KERN_INFO " Converted Value: %03d\n", adc_value);
++
++ if (copy_to_user(buffer, &adc_value, sizeof(unsigned int))) {
++ return -EFAULT;
++ }
++ return sizeof(unsigned int);
++}
++
++
++static int s3c_adc_ioctl(struct inode *inode, struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++
++ printk(KERN_INFO " s3c_adc_ioctl(cmd:: %d) entered\n", cmd);
++
++ switch (cmd) {
++
++ case ADC_INPUT_PIN:
++ adc_port = (unsigned int) arg;
++
++ if (adc_port >= 4)
++ printk(" %d is already reserved for TouchScreen\n", adc_port);
++ return 0;
++
++ default:
++ return -ENOIOCTLCMD;
++
++ }
++}
++
++static struct file_operations s3c_adc_fops = {
++ .owner = THIS_MODULE,
++ .read = s3c_adc_read,
++ .open = s3c_adc_open,
++ .ioctl = s3c_adc_ioctl,
++};
++
++static struct miscdevice s3c_adc_miscdev = {
++ .minor = ADC_MINOR,
++ .name = "adc",
++ .fops = &s3c_adc_fops,
++};
++
++
++/*
++ * The functions for inserting/removing us as a module.
++ */
++
++static int __init s3c_adc_probe(struct platform_device *pdev)
++{
++ int ret;
++
++ adc_clock = clk_get(NULL, "adc");
++ if (!adc_clock) {
++ printk(KERN_ERR "failed to get adc clock source\n");
++ return -ENOENT;
++ }
++ clk_enable(adc_clock);
++
++ base_addr=ioremap(S3C24XX_PA_ADC, 0x20);
++
++ if (base_addr == NULL) {
++ printk(KERN_ERR "Failed to remap register block\n");
++ return -ENOMEM;
++ }
++
++ if ((s3c_adc_cfg.presc&0xff) > 0)
++ writel(S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(s3c_adc_cfg.presc&0xFF), base_addr+S3C2410_ADCCON);
++ else
++ writel(0, base_addr+S3C2410_ADCCON);
++
++
++ /* Initialise registers */
++ if ((s3c_adc_cfg.delay&0xffff) > 0)
++ writel(s3c_adc_cfg.delay & 0xffff, base_addr+S3C2410_ADCDLY);
++
++ if (s3c_adc_cfg.resol_bit == 12) {
++ writel(readl(base_addr+S3C2410_ADCCON)|S3C2450_ADCCON_RESSEL_12BIT, base_addr+S3C2410_ADCCON);
++ }
++
++ ret = misc_register(&s3c_adc_miscdev);
++ if (ret) {
++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n",
++ ADC_MINOR, ret);
++ return ret;
++ }
++
++ printk(KERN_INFO "S3C24XX ADC driver successfully probed !\n");
++
++ return 0;
++}
++
++
++static int s3c_adc_remove(struct platform_device *dev)
++{
++ printk(KERN_INFO "s3c_adc_remove() of TS called !\n");
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static unsigned int adccon, adctsc, adcdly;
++
++static int s3c_adc_suspend(struct platform_device *dev, pm_message_t state)
++{
++ adccon = readl(base_addr+S3C2410_ADCCON);
++ adctsc = readl(base_addr+S3C2410_ADCTSC);
++ adcdly = readl(base_addr+S3C2410_ADCDLY);
++
++ clk_disable(adc_clock);
++
++ return 0;
++}
++
++static int s3c_adc_resume(struct platform_device *pdev)
++{
++ clk_enable(adc_clock);
++
++ writel(adccon, base_addr+S3C2410_ADCCON);
++ writel(adctsc, base_addr+S3C2410_ADCTSC);
++ writel(adcdly, base_addr+S3C2410_ADCDLY);
++
++ return 0;
++}
++#else
++#define s3c_adc_suspend NULL
++#define s3c_adc_resume NULL
++#endif
++
++static struct platform_driver s3c_adc_driver = {
++ .probe = s3c_adc_probe,
++ .remove = s3c_adc_remove,
++ .suspend = s3c_adc_suspend,
++ .resume = s3c_adc_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-adc",
++ },
++};
++
++static char banner[] __initdata = KERN_INFO "S3C24XX ADC driver, (c) 2007 Samsung Electronics\n";
++
++int __init s3c_adc_init(void)
++{
++ printk(banner);
++ return platform_driver_register(&s3c_adc_driver);
++}
++
++void __exit s3c_adc_exit(void)
++{
++ platform_driver_unregister(&s3c_adc_driver);
++}
++
++module_init(s3c_adc_init);
++module_exit(s3c_adc_exit);
++
++MODULE_AUTHOR("alinuxguy@samsung.com>");
++MODULE_DESCRIPTION("S3C24XX adc driver");
++MODULE_LICENSE("GPL");
+diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
+index 79cda0f..4c7145b 100644
+--- a/arch/arm/plat-s3c24xx/clock.c
++++ b/arch/arm/plat-s3c24xx/clock.c
+@@ -233,6 +233,7 @@ struct clk clk_upll = {
+ .ctrlbit = 0,
+ };
+
++
+ struct clk clk_f = {
+ .name = "fclk",
+ .id = -1,
+@@ -264,6 +265,7 @@ struct clk clk_usb_bus = {
+ .parent = &clk_upll,
+ };
+
++
+ /* clocks that could be registered by external code */
+
+ static int s3c24xx_dclk_enable(struct clk *clk, int enable)
+@@ -428,6 +430,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
+ /* initialise the main system clocks */
+
+ clk_xtal.rate = xtal;
++
+ clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
+
+ clk_mpll.rate = fclk;
+diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
+index 398c7ac..ac7a428 100644
+--- a/arch/arm/plat-s3c24xx/common-smdk.c
++++ b/arch/arm/plat-s3c24xx/common-smdk.c
+@@ -44,6 +44,8 @@
+ #include <asm/plat-s3c24xx/devs.h>
+ #include <asm/plat-s3c24xx/pm.h>
+
++#include <asm/mach/flash.h>
++
+ /* LED devices */
+
+ static struct s3c24xx_led_platdata smdk_pdata_led4 = {
+@@ -105,7 +107,7 @@ static struct platform_device smdk_led7 = {
+ };
+
+ /* NAND parititon from 2.4.18-swl5 */
+-
++#if defined(CONFIG_MTD_NAND_S3C2410)
+ static struct mtd_partition smdk_default_nand_part[] = {
+ [0] = {
+ .name = "Boot Agent",
+@@ -161,7 +163,6 @@ static struct s3c2410_nand_set smdk_nand_sets[] = {
+ /* choose a set of timings which should suit most 512Mbit
+ * chips and beyond.
+ */
+-
+ static struct s3c2410_platform_nand smdk_nand_info = {
+ .tacls = 20,
+ .twrph0 = 60,
+@@ -170,10 +171,60 @@ static struct s3c2410_platform_nand smdk_nand_info = {
+ .sets = smdk_nand_sets,
+ };
+
+-/* devices we initialise */
++/* ----------------S3C NAND partition information ---------------------*/
++#else /* CONFIG_MTD_NAND_S3C */
++struct mtd_partition s3c_partition_info[] = {
++ {
++ .name = "Bootloader",
++ .offset = 0,
++ .size = (256*SZ_1K),
++ .mask_flags = MTD_CAP_NANDFLASH,
++ },
++ {
++ .name = "Kernel",
++ .offset = (256*SZ_1K), /* Block number is 0x10 */
++ .size = (4*SZ_1M) - (256*SZ_1K),
++ .mask_flags = MTD_CAP_NANDFLASH,
++ },
++#if defined(CONFIG_SPLIT_ROOT_FILESYSTEM)
++ {
++ .name = "Root - Cramfs",
++ .offset = (4*SZ_1M), /* Block number is 0x80 */
++ .size = (48*SZ_1M),
++ },
++#endif
++ {
++ .name = "File System",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL,
++ }
++};
++
++struct s3c_nand_mtd_info s3c_nand_mtd_part_info = {
++ .chip_nr = 1,
++ .mtd_part_nr = ARRAY_SIZE(s3c_partition_info),
++ .partition = s3c_partition_info,
++};
++
++struct s3c_nand_mtd_info * get_board_nand_mtd_info (void)
++{
++ return &s3c_nand_mtd_part_info;
++}
++#endif
++
++struct flash_platform_data s3c_onenand_data = {
++ .parts = s3c_partition_info,
++ .nr_parts = ARRAY_SIZE(s3c_partition_info),
++};
++
++
++/* ---------------------------------------------------------------------*/
+
++/* devices we initialise */
+ static struct platform_device __initdata *smdk_devs[] = {
+ &s3c_device_nand,
++ &s3c_device_onenand,
++ &s3c_device_lcd,
+ &smdk_led4,
+ &smdk_led5,
+ &smdk_led6,
+@@ -183,7 +234,6 @@ static struct platform_device __initdata *smdk_devs[] = {
+ void __init smdk_machine_init(void)
+ {
+ /* Configure the LEDs (even if we have no LED support)*/
+-
+ s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP);
+ s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP);
+ s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP);
+@@ -194,11 +244,20 @@ void __init smdk_machine_init(void)
+ s3c2410_gpio_setpin(S3C2410_GPF6, 1);
+ s3c2410_gpio_setpin(S3C2410_GPF7, 1);
+
++#if !defined(CONFIG_MTD_ONENAND)
++#if defined(CONFIG_MTD_NAND_S3C)
++ /* For s3c nand partition */
++ s3c_device_nand.dev.platform_data = &s3c_nand_mtd_part_info;
++
++#elif defined(CONFIG_MTD_NAND_S3C2410)
+ if (machine_is_smdk2443())
+ smdk_nand_info.twrph0 = 50;
+
+ s3c_device_nand.dev.platform_data = &smdk_nand_info;
+-
++#else
++ /* No MTD NAND device */
++#endif
++#endif
+ platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
+
+ s3c2410_pm_init();
+diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
+index f513ab0..44ad1af 100644
+--- a/arch/arm/plat-s3c24xx/cpu.c
++++ b/arch/arm/plat-s3c24xx/cpu.c
+@@ -4,7 +4,7 @@
+ * http://www.simtec.co.uk/products/SWLINUX/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+- * S3C24XX CPU Support
++ * S3C24XX/S3C64XX CPU Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+@@ -50,6 +50,11 @@
+ #include <asm/plat-s3c24xx/s3c2440.h>
+ #include <asm/plat-s3c24xx/s3c2442.h>
+ #include <asm/plat-s3c24xx/s3c2443.h>
++#include <asm/plat-s3c24xx/s3c2450.h>
++#include <asm/plat-s3c24xx/s3c2416.h>
++#include <asm/plat-s3c64xx/s3c6400.h>
++#include <asm/plat-s3c64xx/s3c6410.h>
++#include <asm/plat-s5p/s5pc100.h>
+
+ struct cpu_table {
+ unsigned long idcode;
+@@ -69,8 +74,13 @@ static const char name_s3c2412[] = "S3C2412";
+ static const char name_s3c2440[] = "S3C2440";
+ static const char name_s3c2442[] = "S3C2442";
+ static const char name_s3c2443[] = "S3C2443";
++static const char name_s3c2450[] = "S3C2450";
++static const char name_s3c2416[] = "S3C2416";
+ static const char name_s3c2410a[] = "S3C2410A";
+ static const char name_s3c2440a[] = "S3C2440A";
++static const char name_s3c6400[] = "S3C6400";
++static const char name_s3c6410[] = "S3C6410";
++static const char name_s5pc100[] = "S5PC100";
+
+ static struct cpu_table cpu_ids[] __initdata = {
+ {
+@@ -145,8 +155,29 @@ static struct cpu_table cpu_ids[] __initdata = {
+ .init = s3c2443_init,
+ .name = name_s3c2443,
+ },
++#if defined(CONFIG_CPU_S3C2416)
++ { /* same with s3c2450 */
++ .idcode = 0x32450001,
++ .idmask = 0xffffffff,
++ .map_io = s3c2416_map_io,
++ .init_clocks = s3c2416_init_clocks,
++ .init_uarts = s3c2416_init_uarts,
++ .init = s3c2416_init,
++ .name = name_s3c2416,
++ },
++#elif defined(CONFIG_CPU_S3C2450)
++ { /* almost same as s3c2443 */
++ .idcode = 0x32450000,
++ .idmask = 0xfffffff0,
++ .map_io = s3c2450_map_io,
++ .init_clocks = s3c2450_init_clocks,
++ .init_uarts = s3c2450_init_uarts,
++ .init = s3c2450_init,
++ .name = name_s3c2450,
++ },
++#endif
+ {
+- .idcode = 0x0, /* S3C2400 doesn't have an idcode */
++ .idcode = 0x0, /* S3C2400 doesn't have an idcode */
+ .idmask = 0xffffffff,
+ .map_io = s3c2400_map_io,
+ .init_clocks = s3c2400_init_clocks,
+@@ -154,6 +185,33 @@ static struct cpu_table cpu_ids[] __initdata = {
+ .init = s3c2400_init,
+ .name = name_s3c2400
+ },
++ {
++ .idcode = 0x36400100,
++ .idmask = 0xffffffff,
++ .map_io = s3c6400_map_io,
++ .init_clocks = s3c6400_init_clocks,
++ .init_uarts = s3c6400_init_uarts,
++ .init = s3c6400_init,
++ .name = name_s3c6400
++ },
++ {
++ .idcode = 0x36410100,
++ .idmask = 0xfffffff0,
++ .map_io = s3c6410_map_io,
++ .init_clocks = s3c6410_init_clocks,
++ .init_uarts = s3c6410_init_uarts,
++ .init = s3c6410_init,
++ .name = name_s3c6410
++ },
++ {
++ .idcode = 0x43100000,
++ .idmask = 0xfffffff0,
++ .map_io = s5pc100_map_io,
++ .init_clocks = s5pc100_init_clocks,
++ .init_uarts = s5pc100_init_uarts,
++ .init = s5pc100_init,
++ .name = name_s5pc100
++ },
+ };
+
+ /* minimal IO mapping */
+@@ -161,8 +219,22 @@ static struct cpu_table cpu_ids[] __initdata = {
+ static struct map_desc s3c_iodesc[] __initdata = {
+ IODESC_ENT(GPIO),
+ IODESC_ENT(IRQ),
++ IODESC_ENT(UART),
++
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ IODESC_ENT(MEMCTRL),
+- IODESC_ENT(UART)
++#else
++ IODESC_ENT(DMC0),
++#if !defined(CONFIG_PLAT_S5PC1XX)
++ IODESC_ENT(DMC1),
++#endif
++ IODESC_ENT(SYSCON),
++#endif
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++ IODESC_ENT(CHIP_ID),
++ IODESC_ENT(TIMER),
++#endif
+ };
+
+
+@@ -185,10 +257,13 @@ s3c_lookup_cpu(unsigned long idcode)
+
+ static struct cpu_table *cpu;
+
++
+ static unsigned long s3c24xx_read_idcode_v5(void)
+ {
+ #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+ return __raw_readl(S3C2412_GSTATUS1);
++#elif defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ return __raw_readl(S3C2410_GSTATUS1);
+ #else
+ return 1UL; /* don't look like an 2400 */
+ #endif
+@@ -203,19 +278,41 @@ static unsigned long s3c24xx_read_idcode_v4(void)
+ #endif
+ }
+
++
++/* For S3C6400 EVT1/S3C6410 */
++static unsigned long s3c64xx_read_idcode_v6(void)
++{
++ return __raw_readl(S3C24XX_VA_SYSCON+0x118);
++}
++
++/* For S5PC100 */
++static unsigned long s5pc1xx_read_idcode_v7(void)
++{
++ return (__raw_readl(S3C24XX_VA_CHIP_ID));
++}
++
+ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
+ {
+ unsigned long idcode = 0x0;
+
+ /* initialise the io descriptors we need for initialisation */
+ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
+-
+- if (cpu_architecture() >= CPU_ARCH_ARMv5) {
++ if (cpu_architecture() >= CPU_ARCH_ARMv6) {
++#if defined(CONFIG_PLAT_S5PC1XX)
++ idcode = s5pc1xx_read_idcode_v7();
++#else
++ idcode = s3c64xx_read_idcode_v6();
++#endif
++ } else if (cpu_architecture() >= CPU_ARCH_ARMv5) {
+ idcode = s3c24xx_read_idcode_v5();
+- } else {
++ } else if (cpu_architecture() >= CPU_ARCH_ARMv4) {
+ idcode = s3c24xx_read_idcode_v4();
++ } else {
++ panic("Unknown CPU Architecture");
++ idcode = 1UL; /* Unknown and error */
+ }
+
++
+ cpu = s3c_lookup_cpu(idcode);
+
+ if (cpu == NULL) {
+@@ -260,7 +357,7 @@ void __init s3c24xx_init_clocks(int xtal)
+
+ static int nr_uarts __initdata = 0;
+
+-static struct s3c2410_uartcfg uart_cfgs[3];
++static struct s3c2410_uartcfg uart_cfgs[4];
+
+ /* s3c24xx_init_uartdevs
+ *
+diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
+index e546e93..10007c8 100644
+--- a/arch/arm/plat-s3c24xx/devs.c
++++ b/arch/arm/plat-s3c24xx/devs.c
+@@ -32,50 +32,107 @@
+ #include <asm/plat-s3c24xx/udc.h>
+
+ #include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/common-smdk.h>
+ #include <asm/plat-s3c24xx/cpu.h>
+ #include <asm/plat-s3c24xx/regs-spi.h>
+
++/****************************************************************************
++ * common
++ ***************************************************************************/
++
+ /* Serial port registrations */
+
+ static struct resource s3c2410_uart0_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_UART0,
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ .end = S3C2410_PA_UART0 + 0x3fff,
++#else
++ .end = S3C2410_PA_UART0 + 0x3ff,
++#endif
+ .flags = IORESOURCE_MEM,
+ },
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ [1] = {
+ .start = IRQ_S3CUART_RX0,
+ .end = IRQ_S3CUART_ERR0,
+ .flags = IORESOURCE_IRQ,
+ }
++#else
++ [1] = {
++ .start = IRQ_UART0,
++ .end = IRQ_UART0,
++ .flags = IORESOURCE_IRQ,
++ }
++#endif
+ };
+
+ static struct resource s3c2410_uart1_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_UART1,
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ .end = S3C2410_PA_UART1 + 0x3fff,
++#else
++ .end = S3C2410_PA_UART1 + 0x3ff,
++#endif
+ .flags = IORESOURCE_MEM,
+ },
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ [1] = {
+ .start = IRQ_S3CUART_RX1,
+ .end = IRQ_S3CUART_ERR1,
+ .flags = IORESOURCE_IRQ,
+ }
++#else
++ [1] = {
++ .start = IRQ_UART1,
++ .end = IRQ_UART1,
++ .flags = IORESOURCE_IRQ,
++ }
++#endif
+ };
+
+ static struct resource s3c2410_uart2_resource[] = {
+ [0] = {
+ .start = S3C2410_PA_UART2,
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ .end = S3C2410_PA_UART2 + 0x3fff,
++#else
++ .end = S3C2410_PA_UART2 + 0x3ff,
++#endif
+ .flags = IORESOURCE_MEM,
+ },
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ [1] = {
+ .start = IRQ_S3CUART_RX2,
+ .end = IRQ_S3CUART_ERR2,
+ .flags = IORESOURCE_IRQ,
+ }
++#else
++ [1] = {
++ .start = IRQ_UART2,
++ .end = IRQ_UART2,
++ .flags = IORESOURCE_IRQ,
++ }
++#endif
+ };
+
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++static struct resource s3c_uart3_resource[] = {
++ [0] = {
++ .start = S3C2443_PA_UART3,
++ .end = S3C2443_PA_UART3 + 0x3ff,
++ .flags = IORESOURCE_MEM,
++ },
++
++ [1] = {
++ .start = IRQ_UART3,
++ .end = IRQ_UART3,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#endif
++
+ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
+ [0] = {
+ .resources = s3c2410_uart0_resource,
+@@ -89,9 +146,15 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
+ .resources = s3c2410_uart2_resource,
+ .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
+ },
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++ [3] = {
++ .resources = s3c_uart3_resource,
++ .nr_resources = ARRAY_SIZE(s3c_uart3_resource),
++ },
++#endif
+ };
+
+-/* yart devices */
++/* uart devices */
+
+ static struct platform_device s3c24xx_uart_device0 = {
+ .id = 0,
+@@ -105,13 +168,22 @@ static struct platform_device s3c24xx_uart_device2 = {
+ .id = 2,
+ };
+
+-struct platform_device *s3c24xx_uart_src[3] = {
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++static struct platform_device s3c24xx_uart_device3 = {
++ .id = 3,
++};
++#endif
++
++struct platform_device *s3c24xx_uart_src[] = {
+ &s3c24xx_uart_device0,
+ &s3c24xx_uart_device1,
+ &s3c24xx_uart_device2,
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++ &s3c24xx_uart_device3,
++#endif
+ };
+
+-struct platform_device *s3c24xx_uart_devs[3] = {
++struct platform_device *s3c24xx_uart_devs[] = {
+ };
+
+ /* USB Host Controller */
+@@ -122,11 +194,19 @@ static struct resource s3c_usb_resource[] = {
+ .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
+ .flags = IORESOURCE_MEM,
+ },
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ [1] = {
+ .start = IRQ_USBH,
+ .end = IRQ_USBH,
+ .flags = IORESOURCE_IRQ,
+ }
++#else
++ [1] = {
++ .start = IRQ_UHOST,
++ .end = IRQ_UHOST,
++ .flags = IORESOURCE_IRQ,
++ }
++#endif
+ };
+
+ static u64 s3c_device_usb_dmamask = 0xffffffffUL;
+@@ -153,8 +233,16 @@ static struct resource s3c_lcd_resource[] = {
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ .start = IRQ_LCD_VSYNC ,
++ .end = IRQ_LCD_SYSTEM,
++#elif defined(CONFIG_PLAT_S3C24XX)
+ .start = IRQ_LCD,
+ .end = IRQ_LCD,
++#elif defined(CONFIG_PLAT_S5PC1XX)
++ .start = IRQ_LCD0,
++ .end = IRQ_LCD3,
++#endif
+ .flags = IORESOURCE_IRQ,
+ }
+
+@@ -192,8 +280,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
+
+ static struct resource s3c_nand_resource[] = {
+ [0] = {
+- .start = S3C2410_PA_NAND,
+- .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
++ .start = S3C24XX_PA_NAND,
++ .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
+ .flags = IORESOURCE_MEM,
+ }
+ };
+@@ -207,9 +295,42 @@ struct platform_device s3c_device_nand = {
+
+ EXPORT_SYMBOL(s3c_device_nand);
+
++/* OneNAND Controller */
++static struct resource s3c_onenand_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_ONENAND,
++ .end = S3C6400_PA_ONENAND + S3C_SZ_ONENAND - 1,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++struct platform_device s3c_device_onenand = {
++ .name = "onenand",
++ .id = -1,
++ .dev = {
++ .platform_data = &s3c_onenand_data,
++ },
++ .num_resources = ARRAY_SIZE(s3c_onenand_resource),
++ .resource = s3c_onenand_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_onenand);
++
+ /* USB Device (Gadget)*/
+
+ static struct resource s3c_usbgadget_resource[] = {
++#if defined(CONFIG_PLAT_S3C64XX)
++ [0] = {
++ .start = S3C24XX_PA_OTG,
++ .end = S3C24XX_PA_OTG+S3C24XX_SZ_OTG-1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_OTG,
++ .end = IRQ_OTG,
++ .flags = IORESOURCE_IRQ,
++ }
++#elif defined(CONFIG_PLAT_S3C24XX)
+ [0] = {
+ .start = S3C24XX_PA_USBDEV,
+ .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
+@@ -220,7 +341,7 @@ static struct resource s3c_usbgadget_resource[] = {
+ .end = IRQ_USBD,
+ .flags = IORESOURCE_IRQ,
+ }
+-
++#endif
+ };
+
+ struct platform_device s3c_device_usbgadget = {
+@@ -232,6 +353,32 @@ struct platform_device s3c_device_usbgadget = {
+
+ EXPORT_SYMBOL(s3c_device_usbgadget);
+
++#ifdef CONFIG_PLAT_S3C64XX
++/* USB Device (OTG hcd)*/
++
++static struct resource s3c_usb_otghcd_resource[] = {
++ [0] = {
++ .start = S3C24XX_PA_OTG,
++ .end = S3C24XX_PA_OTG + S3C24XX_SZ_OTG - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_OTG,
++ .end = IRQ_OTG,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_usb_otghcd = {
++ .name = "s3c6410_OTGHCD",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_usb_otghcd_resource),
++ .resource = s3c_usb_otghcd_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_usb_otghcd);
++#endif
++
+ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
+ {
+ struct s3c2410_udc_mach_info *npd;
+@@ -254,12 +401,20 @@ static struct resource s3c_wdt_resource[] = {
+ .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
+ .flags = IORESOURCE_MEM,
+ },
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ [1] = {
++ .start = IRQ_S3C2443_WDT,
++ .end = IRQ_S3C2443_WDT,
++ .flags = IORESOURCE_IRQ,
++ }
++
++#else
+ [1] = {
+ .start = IRQ_WDT,
+ .end = IRQ_WDT,
+ .flags = IORESOURCE_IRQ,
+ }
+-
++#endif
+ };
+
+ struct platform_device s3c_device_wdt = {
+@@ -272,7 +427,7 @@ struct platform_device s3c_device_wdt = {
+ EXPORT_SYMBOL(s3c_device_wdt);
+
+ /* I2C */
+-
++#ifndef CONFIG_PLAT_S3C64XX
+ static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C24XX_PA_IIC,
+@@ -284,7 +439,6 @@ static struct resource s3c_i2c_resource[] = {
+ .end = IRQ_IIC,
+ .flags = IORESOURCE_IRQ,
+ }
+-
+ };
+
+ struct platform_device s3c_device_i2c = {
+@@ -295,6 +449,7 @@ struct platform_device s3c_device_i2c = {
+ };
+
+ EXPORT_SYMBOL(s3c_device_i2c);
++#endif
+
+ /* IIS */
+
+@@ -303,7 +458,14 @@ static struct resource s3c_iis_resource[] = {
+ .start = S3C24XX_PA_IIS,
+ .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
+ .flags = IORESOURCE_MEM,
++ },
++#if defined(CONFIG_CPU_S3C6410)
++ [1] = {
++ .start = IRQ_IIS,
++ .end = IRQ_IIS,
++ .flags = IORESOURCE_IRQ,
+ }
++#endif
+ };
+
+ static u64 s3c_device_iis_dmamask = 0xffffffffUL;
+@@ -321,6 +483,31 @@ struct platform_device s3c_device_iis = {
+
+ EXPORT_SYMBOL(s3c_device_iis);
+
++/* AC97 */
++
++static struct resource s3c_ac97_resource[] = {
++ [0] = {
++ .start = S3C24XX_PA_AC97,
++ .end = S3C24XX_PA_AC97 + S3C24XX_SZ_AC97 -1,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
++
++struct platform_device s3c_device_ac97 = {
++ .name = "s3c-ac97",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_ac97_resource),
++ .resource = s3c_ac97_resource,
++ .dev = {
++ .dma_mask = &s3c_device_ac97_dmamask,
++ .coherent_dma_mask = 0xffffffffUL
++ }
++};
++
++EXPORT_SYMBOL(s3c_device_ac97);
++
+ /* RTC */
+
+ static struct resource s3c_rtc_resource[] = {
+@@ -329,6 +516,7 @@ static struct resource s3c_rtc_resource[] = {
+ .end = S3C24XX_PA_RTC + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ [1] = {
+ .start = IRQ_RTC,
+ .end = IRQ_RTC,
+@@ -339,6 +527,18 @@ static struct resource s3c_rtc_resource[] = {
+ .end = IRQ_TICK,
+ .flags = IORESOURCE_IRQ
+ }
++#else
++ [1] = {
++ .start = IRQ_RTC_ALARM,
++ .end = IRQ_RTC_ALARM,
++ .flags = IORESOURCE_IRQ,
++ },
++ [2] = {
++ .start = IRQ_RTC_TIC,
++ .end = IRQ_RTC_TIC,
++ .flags = IORESOURCE_IRQ
++ }
++#endif
+ };
+
+ struct platform_device s3c_device_rtc = {
+@@ -351,6 +551,7 @@ struct platform_device s3c_device_rtc = {
+ EXPORT_SYMBOL(s3c_device_rtc);
+
+ /* ADC */
++extern struct s3c_adc_cfg s3c_adc_platform;
+
+ static struct resource s3c_adc_resource[] = {
+ [0] = {
+@@ -372,10 +573,39 @@ static struct resource s3c_adc_resource[] = {
+ };
+
+ struct platform_device s3c_device_adc = {
+- .name = "s3c2410-adc",
++ .name = "s3c-adc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_adc_resource),
+ .resource = s3c_adc_resource,
++ .dev ={
++ .platform_data = &s3c_adc_platform,
++ }
++};
++EXPORT_SYMBOL(s3c_device_adc);
++
++/* Touch srcreen */
++extern struct s3c_ts_mach_info s3c_ts_platform;
++static struct resource s3c_ts_resource[] = {
++ [0] = {
++ .start = S3C24XX_PA_ADC,
++ .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_TC,
++ .end = IRQ_ADC,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_ts = {
++ .name = "s3c-ts",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_ts_resource),
++ .resource = s3c_ts_resource,
++ .dev ={
++ .platform_data = &s3c_ts_platform,
++ }
+ };
+
+ /* SDI */
+@@ -386,12 +616,13 @@ static struct resource s3c_sdi_resource[] = {
+ .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
+ .flags = IORESOURCE_MEM,
+ },
++#if !defined(CONFIG_PLAT_S3C64XX) && !defined(CONFIG_PLAT_S5PC1XX)
+ [1] = {
+ .start = IRQ_SDI,
+ .end = IRQ_SDI,
+ .flags = IORESOURCE_IRQ,
+ }
+-
++#endif
+ };
+
+ struct platform_device s3c_device_sdi = {
+@@ -403,42 +634,72 @@ struct platform_device s3c_device_sdi = {
+
+ EXPORT_SYMBOL(s3c_device_sdi);
+
+-/* High-speed MMC/SD */
+
+-static struct resource s3c_hsmmc_resource[] = {
++/* SPI (0) */
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++
++static struct resource s3c_spi0_resource[] = {
+ [0] = {
+- .start = S3C2443_PA_HSMMC,
+- .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
++ .start = S3C_PA_SPI_0,
++ .end = S3C_PA_SPI_0 + S3C_SZ_SPI_0,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+- .start = IRQ_S3C2443_HSMMC,
+- .end = IRQ_S3C2443_HSMMC,
++ .start = IRQ_SPI0,
++ .end = IRQ_SPI0,
+ .flags = IORESOURCE_IRQ,
+ }
++
+ };
+
+-static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
++static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
+
+-struct platform_device s3c_device_hsmmc = {
+- .name = "s3c-sdhci",
+- .id = -1,
+- .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
+- .resource = s3c_hsmmc_resource,
+- .dev = {
+- .dma_mask = &s3c_device_hsmmc_dmamask,
+- .coherent_dma_mask = 0xffffffffUL
++struct platform_device s3c_device_spi0 = {
++ .name = "s3c2410-spi",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(s3c_spi0_resource),
++ .resource = s3c_spi0_resource,
++ .dev = {
++ .dma_mask = &s3c_device_spi0_dmamask,
++ .coherent_dma_mask = 0xffffffffUL
++ }
++};
++
++EXPORT_SYMBOL(s3c_device_spi0);
++
++static struct resource s3c_spi1_resource[] = {
++ [0] = {
++ .start = S3C_PA_SPI_0,
++ .end = S3C_PA_SPI_0 + S3C_SZ_SPI_0,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_SPI1,
++ .end = IRQ_SPI1,
++ .flags = IORESOURCE_IRQ,
+ }
++
+ };
+
++struct platform_device s3c_device_spi1 = {
++ .name = "s3c-spi",
++ .id = 1,
++ .num_resources = ARRAY_SIZE(s3c_spi1_resource),
++ .resource = s3c_spi1_resource,
++};
+
++EXPORT_SYMBOL(s3c_device_spi1);
+
+-/* SPI (0) */
++#else
+
+ static struct resource s3c_spi0_resource[] = {
+ [0] = {
+ .start = S3C24XX_PA_SPI,
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
+ .end = S3C24XX_PA_SPI + 0x1f,
++#else
++ .end = S3C24XX_PA_SPI + S3C24XX_SZ_SPI - 1,
++#endif
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+@@ -464,12 +725,18 @@ struct platform_device s3c_device_spi0 = {
+
+ EXPORT_SYMBOL(s3c_device_spi0);
+
++
+ /* SPI (1) */
+
+ static struct resource s3c_spi1_resource[] = {
+ [0] = {
+- .start = S3C24XX_PA_SPI + S3C2410_SPI1,
+- .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ .start = S3C24XX_PA_SPI + 0x20,
++ .end = S3C24XX_PA_SPI + 0x20 + 0x1f,
++#else
++ .start = S3C24XX_PA_SPI + S3C24XX_SZ_SPI,
++ .end = S3C24XX_PA_SPI + S3C24XX_SZ_SPI + 0xff,
++#endif
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+@@ -495,6 +762,8 @@ struct platform_device s3c_device_spi1 = {
+
+ EXPORT_SYMBOL(s3c_device_spi1);
+
++#endif
++
+ /* pwm timer blocks */
+
+ static struct resource s3c_timer0_resource[] = {
+@@ -595,10 +864,12 @@ struct platform_device s3c_device_timer3 = {
+
+ EXPORT_SYMBOL(s3c_device_timer3);
+
+-#ifdef CONFIG_CPU_S3C2440
++/****************************************************************************
++ * S3C2440 only: camif
++ ***************************************************************************/
++#if defined(CONFIG_CPU_S3C2440) && (!defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2450))
+
+ /* Camif Controller */
+-
+ static struct resource s3c_camif_resource[] = {
+ [0] = {
+ .start = S3C2440_PA_CAMIF,
+@@ -628,4 +899,559 @@ struct platform_device s3c_device_camif = {
+
+ EXPORT_SYMBOL(s3c_device_camif);
+
+-#endif // CONFIG_CPU_S32440
++#endif /* End of S3C2440 only */
++
++/****************************************************************************
++ * S3C2443, S3C2450 common
++ ***************************************************************************/
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#if !defined(CONFIG_CPU_S3C2416)
++/* Camif controller */
++static struct resource s3c_camif_resource[] = {
++ [0] = {
++ .start = S3C2443_PA_CAMIF,
++ .end = S3C2443_PA_CAMIF + S3C2443_SZ_CAMIF - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_S3C2440_CAM_C,
++ .end = IRQ_S3C2440_CAM_C,
++ .flags = IORESOURCE_IRQ,
++ },
++ [2] = {
++ .start = IRQ_S3C2440_CAM_P,
++ .end = IRQ_S3C2440_CAM_P,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static u64 s3c_device_camif_dmamask = 0xffffffffUL;
++
++struct platform_device s3c_device_camif = {
++ .name = "s3c-camif",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_camif_resource),
++ .resource = s3c_camif_resource,
++ .dev = {
++ .dma_mask = &s3c_device_camif_dmamask,
++ .coherent_dma_mask = 0xffffffffUL
++ }
++};
++
++EXPORT_SYMBOL(s3c_device_camif);
++
++/* Ide controller */
++static struct resource s3c_ide_resource[] = {
++ [0] = {
++ .start = S3C_PA_CFATA,
++ .end = S3C_PA_CFATA+ S3C_SZ_CFATA,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_CFCON,
++ .end = IRQ_CFCON,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_ide = {
++ .name = "s3c-ide",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(s3c_ide_resource),
++ .resource = s3c_ide_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_ide);
++#endif
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++/* HS-MMC Controller */
++extern struct s3c_hsmmc_cfg s3c_hsmmc0_platform;
++extern struct s3c_hsmmc_cfg s3c_hsmmc1_platform;
++
++static struct resource s3c_hsmmc0_resource[] = {
++ [0] = {
++ .start = S3C_PA_HSMMC+0x400000,
++ .end = S3C_PA_HSMMC+0x400000+S3C_SZ_HSMMC,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_SDI_0,
++ .end = IRQ_SDI_0,
++ .flags = IORESOURCE_IRQ,
++ },
++ /* To detect a card inserted, use an external interrupt */
++ [2] = {
++ .start = IRQ_EINT1,
++ .end = IRQ_EINT1,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource s3c_hsmmc1_resource[] = {
++ [0] = {
++ .start = S3C_PA_HSMMC,
++ .end = S3C_PA_HSMMC+S3C_SZ_HSMMC,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_SDI_1,
++ .end = IRQ_SDI_1,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_hsmmc0 = {
++ .name = "s3c-hsmmc",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(s3c_hsmmc0_resource),
++ .resource = s3c_hsmmc0_resource,
++ .dev = {
++ .platform_data = &s3c_hsmmc0_platform,
++ }
++};
++
++
++struct platform_device s3c_device_hsmmc1 = {
++ .name = "s3c-hsmmc",
++ .id = 1,
++ .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
++ .resource = s3c_hsmmc1_resource,
++ .dev = {
++ .platform_data = &s3c_hsmmc1_platform,
++ }
++};
++
++EXPORT_SYMBOL(s3c_device_hsmmc0);
++EXPORT_SYMBOL(s3c_device_hsmmc1);
++
++#else
++/* HS-MMC controller */
++extern struct s3c_hsmmc_cfg s3c_hsmmc_platform;
++
++static struct resource s3c_hsmmc_resource[] = {
++ [0] = {
++ .start = S3C_PA_HSMMC,
++ .end = S3C_PA_HSMMC+ S3C_SZ_HSMMC,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_SDI_1,
++ .end = IRQ_SDI_1,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_hsmmc = {
++ .name = "s3c-hsmmc",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
++ .resource = s3c_hsmmc_resource,
++ .dev = {
++ .platform_data = &s3c_hsmmc_platform,
++ }
++};
++
++EXPORT_SYMBOL(s3c_device_hsmmc);
++#endif
++
++#endif /* End of S3C2443, S3C2450 common */
++
++/****************************************************************************
++ * S3C6400, S3C6410 common
++ ***************************************************************************/
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++
++/* HS-MMC controller */
++extern struct s3c_hsmmc_cfg s3c_hsmmc0_platform;
++extern struct s3c_hsmmc_cfg s3c_hsmmc1_platform;
++extern struct s3c_hsmmc_cfg s3c_hsmmc2_platform;
++
++static struct resource s3c_hsmmc0_resource[] = {
++ [0] = {
++ .start = S3C_PA_HSMMC,
++ .end = S3C_PA_HSMMC+S3C_SZ_HSMMC-1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_HSMMC0,
++ .end = IRQ_HSMMC0,
++ .flags = IORESOURCE_IRQ,
++ },
++ /* To detect a card inserted, use an external interrupt */
++ [2] = {
++ .start = IRQ_EINT13,
++ .end = IRQ_EINT13,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource s3c_hsmmc1_resource[] = {
++ [0] = {
++ .start = S3C_PA_HSMMC+0x100000,
++ .end = S3C_PA_HSMMC+0x100000+S3C_SZ_HSMMC-1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_HSMMC1,
++ .end = IRQ_HSMMC1,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource s3c_hsmmc2_resource[] = {
++ [0] = {
++ .start = S3C_PA_HSMMC+0x200000,
++ .end = S3C_PA_HSMMC+0x200000+S3C_SZ_HSMMC-1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_HSMMC2,
++ .end = IRQ_HSMMC2,
++ .flags = IORESOURCE_IRQ,
++ },
++ [2] = {
++ .start = IRQ_EINT15,
++ .end = IRQ_EINT15,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_hsmmc0 = {
++ .name = "s3c-hsmmc",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(s3c_hsmmc0_resource),
++ .resource = s3c_hsmmc0_resource,
++ .dev = {
++ .platform_data = &s3c_hsmmc0_platform,
++ }
++};
++
++struct platform_device s3c_device_hsmmc1 = {
++ .name = "s3c-hsmmc",
++ .id = 1,
++ .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
++ .resource = s3c_hsmmc1_resource,
++ .dev = {
++ .platform_data = &s3c_hsmmc1_platform,
++ }
++};
++
++struct platform_device s3c_device_hsmmc2 = {
++ .name = "s3c-hsmmc",
++ .id = 2,
++ .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
++ .resource = s3c_hsmmc2_resource,
++ .dev = {
++ .platform_data = &s3c_hsmmc2_platform,
++ }
++};
++
++EXPORT_SYMBOL(s3c_device_hsmmc0);
++EXPORT_SYMBOL(s3c_device_hsmmc1);
++EXPORT_SYMBOL(s3c_device_hsmmc2);
++
++/* 2D interface */
++static struct resource s3c_g2d_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_G2D,
++ .end = S3C6400_PA_G2D + S3C_SZ_G2D - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_2D,
++ .end = IRQ_2D,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_g2d = {
++ .name = "s3c-g2d",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_g2d_resource),
++ .resource = s3c_g2d_resource
++};
++
++EXPORT_SYMBOL(s3c_device_g2d);
++
++/* rotator interface */
++static struct resource s3c_rotator_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_ROTATOR,
++ .end = S3C6400_PA_ROTATOR + S3C_SZ_ROTATOR - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_ROTATOR,
++ .end = IRQ_ROTATOR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_rotator = {
++ .name = "s3c-rotator",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_rotator_resource),
++ .resource = s3c_rotator_resource
++};
++
++EXPORT_SYMBOL(s3c_device_rotator);
++
++/* TV encoder */
++static struct resource s3c_tvenc_resource[] = {
++ [0] = {
++ .start = S3C24XX_PA_TVENC,
++ .end = S3C24XX_PA_TVENC + S3C_SZ_TVENC - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_TVENC,
++ .end = IRQ_TVENC,
++ .flags = IORESOURCE_IRQ,
++ }
++
++};
++
++struct platform_device s3c_device_tvenc = {
++ .name = "s3c-tvenc",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_tvenc_resource),
++ .resource = s3c_tvenc_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_tvenc);
++
++/* TV scaler */
++static struct resource s3c_tvscaler_resource[] = {
++ [0] = {
++ .start = S3C24XX_PA_TVSCALER,
++ .end = S3C24XX_PA_TVSCALER + S3C_SZ_TVSCALER - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_SCALER,
++ .end = IRQ_SCALER,
++ .flags = IORESOURCE_IRQ,
++ }
++
++};
++
++struct platform_device s3c_device_tvscaler = {
++ .name = "s3c-tvscaler",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_tvscaler_resource),
++ .resource = s3c_tvscaler_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_tvscaler);
++
++/* Camif controller */
++static struct resource s3c_camif_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_CAMIF,
++ .end = S3C6400_PA_CAMIF + S3C24XX_SZ_CAMIF - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_CAMIF_C,
++ .end = IRQ_CAMIF_C,
++ .flags = IORESOURCE_IRQ,
++ },
++ [2] = {
++ .start = IRQ_CAMIF_P,
++ .end = IRQ_CAMIF_P,
++ .flags = IORESOURCE_IRQ,
++ }
++
++};
++
++static u64 s3c_device_camif_dmamask = 0xffffffffUL;
++
++struct platform_device s3c_device_camif = {
++ .name = "s3c-camif",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_camif_resource),
++ .resource = s3c_camif_resource,
++ .dev = {
++ .dma_mask = &s3c_device_camif_dmamask,
++ .coherent_dma_mask = 0xffffffffUL
++ }
++};
++
++EXPORT_SYMBOL(s3c_device_camif);
++
++/* JPEG controller */
++static struct resource s3c_jpeg_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_JPEG,
++ .end = S3C6400_PA_JPEG + S3C_SZ_JPEG - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_JPEG,
++ .end = IRQ_JPEG,
++ .flags = IORESOURCE_IRQ,
++ }
++
++};
++
++struct platform_device s3c_device_jpeg = {
++ .name = "s3c-jpeg",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_jpeg_resource),
++ .resource = s3c_jpeg_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_jpeg);
++
++/* MFC controller */
++static struct resource s3c_mfc_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_MFC,
++ .end = S3C6400_PA_MFC + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_MFC,
++ .end = IRQ_MFC,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_mfc = {
++ .name = "s3c-mfc",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_mfc_resource),
++ .resource = s3c_mfc_resource
++};
++
++EXPORT_SYMBOL(s3c_device_mfc);
++
++/* VPP controller */
++static struct resource s3c_vpp_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_VPP,
++ .end = S3C6400_PA_VPP + S3C_SZ_VPP - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_POST0,
++ .end = IRQ_POST0,
++ .flags = IORESOURCE_IRQ,
++ }
++
++};
++
++struct platform_device s3c_device_vpp = {
++ .name = "s3c-vpp",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_vpp_resource),
++ .resource = s3c_vpp_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_vpp);
++
++/* IDE controller */
++static struct resource s3c_ide_resource[] = {
++ [0] = {
++ .start = S3C24XX_PA_CFATA,
++ .end = S3C24XX_PA_CFATA + S3C_SZ_CFATA - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_CFCON,
++ .end = IRQ_CFCON,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_ide = {
++ .name = "s3c-ide",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(s3c_ide_resource),
++ .resource = s3c_ide_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_ide);
++
++/* Keypad interface */
++static struct resource s3c_keypad_resource[] = {
++ [0] = {
++ .start = S3C24XX_PA_KEYPAD,
++ .end = S3C24XX_PA_KEYPAD+ S3C24XX_SZ_KEYPAD - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_KEYPAD,
++ .end = IRQ_KEYPAD,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_keypad = {
++ .name = "s3c-keypad",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_keypad_resource),
++ .resource = s3c_keypad_resource,
++};
++
++EXPORT_SYMBOL(s3c_device_keypad);
++
++#if defined(CONFIG_CPU_S3C6410) /* S3C6410 only */
++
++/* Add here for 6410 only devices */
++/* 3D interface */
++static struct resource s3c_g3d_resource[] = {
++ [0] = {
++ .start = S3C6410_PA_G3D,
++ .end = S3C6410_PA_G3D + S3C6410_SZ_G3D - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_3D,
++ .end = IRQ_3D,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device s3c_device_g3d = {
++ .name = "s3c-g3d",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_g3d_resource),
++ .resource = s3c_g3d_resource
++};
++
++EXPORT_SYMBOL(s3c_device_g3d);
++
++#endif /* End of S3C6410 only */
++
++#endif /* End of S3C6400, S3C6410 common */
++
++#if defined (CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++static struct resource s3c_smc911x_resources[] = {
++ [0] = {
++ .start = S3C_PA_SMC9115,
++ .end = S3C_PA_SMC9115 + 0x1fffffff,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++#if defined(CONFIG_CPU_S3C6410)
++ .start = IRQ_EINT10,
++ .end = IRQ_EINT10,
++#elif defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ .start = IRQ_EINT4,
++ .end = IRQ_EINT4,
++#endif
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++struct platform_device s3c_device_smc911x = {
++ .name = "smc911x",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(s3c_smc911x_resources),
++ .resource = s3c_smc911x_resources,
++};
++EXPORT_SYMBOL(s3c_device_smc911x);
++#endif
++
+diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
+index 29696e4..2fa1332 100644
+--- a/arch/arm/plat-s3c24xx/dma.c
++++ b/arch/arm/plat-s3c24xx/dma.c
+@@ -526,6 +526,8 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id,
+ } else if (chan->state == S3C2410_DMA_IDLE) {
+ if (chan->flags & S3C2410_DMAF_AUTOSTART) {
+ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
++ } else {
++ printk(KERN_DEBUG "loading onto stopped channel\n");
+ }
+ }
+
+@@ -1196,6 +1198,10 @@ int s3c2410_dma_devconfig(int channel,
+
+ chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
+ return 0;
++
++ case S3C_DMA_MEM2MEM:
++ case S3C_DMA_PER2PER:
++ return 0;
+ }
+
+ printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
+@@ -1348,7 +1354,16 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
+
+ /* dma channel irqs are in order.. */
+ cp->number = channel;
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ if(channel == 6){
++ irq = irq + 5;
++ cp->irq = channel + irq;
++ }
++ else
++ cp->irq = channel + irq;
++#else
+ cp->irq = channel + irq;
++#endif
+ cp->regs = dma_base + (channel * stride);
+
+ /* point current stats somewhere */
+diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
+index ec3a09c..28f1dc0 100644
+--- a/arch/arm/plat-s3c24xx/gpio.c
++++ b/arch/arm/plat-s3c24xx/gpio.c
+@@ -69,6 +69,7 @@ void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
+ /* modify the specified register wwith IRQs off */
+
+ local_irq_save(flags);
++ local_irq_disable();
+
+ con = __raw_readl(base + 0x00);
+ con &= ~mask;
+@@ -100,6 +101,28 @@ unsigned int s3c2410_gpio_getcfg(unsigned int pin)
+
+ EXPORT_SYMBOL(s3c2410_gpio_getcfg);
+
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = S3C24XX_GPIO_BASE(pin);
++ unsigned long offs = S3C2410_GPIO_OFFSET(pin)*2;
++ unsigned long flags;
++ unsigned long up;
++
++ if (pin < S3C2410_GPIO_BANKB)
++ return;
++
++ local_irq_save(flags);
++ local_irq_disable();
++
++ up = __raw_readl(base + 0x08);
++ up &= ~(0x3 << offs);
++ up |= to << offs;
++ __raw_writel(up, base + 0x08);
++
++ local_irq_restore(flags);
++}
++#else
+ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
+ {
+ void __iomem *base = S3C24XX_GPIO_BASE(pin);
+@@ -111,6 +134,7 @@ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
+ return;
+
+ local_irq_save(flags);
++ local_irq_disable();
+
+ up = __raw_readl(base + 0x08);
+ up &= ~(1L << offs);
+@@ -119,6 +143,7 @@ void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
+
+ local_irq_restore(flags);
+ }
++#endif
+
+ EXPORT_SYMBOL(s3c2410_gpio_pullup);
+
+@@ -130,6 +155,7 @@ void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
+ unsigned long dat;
+
+ local_irq_save(flags);
++ local_irq_disable();
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offs);
+@@ -157,6 +183,7 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
+ unsigned long misccr;
+
+ local_irq_save(flags);
++ local_irq_disable();
+ misccr = __raw_readl(S3C24XX_MISCCR);
+ misccr &= ~clear;
+ misccr ^= change;
+@@ -186,3 +213,198 @@ int s3c2410_gpio_getirq(unsigned int pin)
+ }
+
+ EXPORT_SYMBOL(s3c2410_gpio_getirq);
++
++
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++/* --------------------------------------------------------------
++ * Set up GPIOs
++ *-------------------------------------------------------------*/
++static void __iomem *gpio_base_offset[]=
++{
++ S3C24XX_VA_GPIO + 0x00, //GPA ,4bit
++ S3C24XX_VA_GPIO + 0x20, //GPB ,4bit
++ S3C24XX_VA_GPIO + 0x40, //GPC ,4bit
++ S3C24XX_VA_GPIO + 0x60, //GPD ,4bit
++ S3C24XX_VA_GPIO + 0x80, //GPE ,4bit
++ S3C24XX_VA_GPIO + 0xA0, //GPF ,2bit
++ S3C24XX_VA_GPIO + 0xC0, //GPG ,4bit
++ S3C24XX_VA_GPIO + 0xE0, //GPH ,4bit
++ S3C24XX_VA_GPIO + 0x100, //GPI ,2bit
++ S3C24XX_VA_GPIO + 0x120, //GPJ ,2bit
++ S3C24XX_VA_GPIO + 0x140, //GPO ,2bit
++ S3C24XX_VA_GPIO + 0x160, //GPP ,2bit
++ S3C24XX_VA_GPIO + 0x180, //GPQ ,2bit
++ S3C24XX_VA_GPIO + 0x800, //GPK ,4bit
++ S3C24XX_VA_GPIO + 0x810, //GPL ,4bit
++ S3C24XX_VA_GPIO + 0x820, //GPM ,4bit
++ S3C24XX_VA_GPIO + 0x830 //GPN ,2bit
++};
++
++void s3c_gpio_cfgpin(unsigned int pin, unsigned int function)
++{
++ void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
++ unsigned long mask;
++ unsigned long con;
++ unsigned long flags;
++ unsigned long offs = S3C_GPIO_OFFSET(pin);
++
++ if ((pin < S3C_GPIO_BANKF)||((pin >=S3C_GPIO_BANKG)&&\
++ (pin<S3C_GPIO_BANKI))||((pin>=S3C_GPIO_BANKK)&&\
++ (pin<S3C_GPIO_BANKN)))
++ {
++ offs = (offs) *4;
++
++ if((pin == S3C_GPH8)||(pin==S3C_GPH9)||\
++ (pin>=S3C_GPK8&&pin<=S3C_GPK15)||\
++ (pin>=S3C_GPL8&&pin<=S3C_GPL14))
++ {
++ base = base + 0x04;
++ /* only for con1:8~14 or 15 regiter configuratio nvalue change ...*/
++ offs = offs - 32;
++ }
++ mask = 0xF << offs;
++ }
++ else
++ {
++ offs = offs*2;
++ mask = 0x3 << offs;
++ }
++
++ local_irq_save(flags);
++ local_irq_disable();
++
++ con = __raw_readl(base + 0x00);
++ con &= ~mask;
++ con |= (function << offs);
++
++ __raw_writel(con, base + 0x00);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s3c_gpio_cfgpin);
++
++unsigned int s3c_gpio_getcfg(unsigned int pin)
++{
++ void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
++ unsigned long mask;
++ unsigned long shift=0;
++
++ if ((pin < S3C_GPIO_BANKF)||((pin >=S3C_GPIO_BANKG)&&\
++ (pin<S3C_GPIO_BANKI))||((pin>=S3C_GPIO_BANKK)&&\
++ (pin<S3C_GPIO_BANKN)))
++ {
++ mask = 0xF << S3C_GPIO_OFFSET(pin)*4;
++ if((pin == S3C_GPH8)||(pin==S3C_GPH9)||\
++ (pin>=S3C_GPK8&&pin<=S3C_GPK15)||\
++ (pin>=S3C_GPL8&&pin<=S3C_GPL14))
++ {
++ base = base + 0x04;
++ shift = S3C_GPIO_OFFSET(pin)*4 - 32;
++ mask = 0xF << shift;
++ }
++
++ }
++ else
++ {
++ shift = S3C_GPIO_OFFSET(pin)*2;
++ mask = 0x3 << shift;
++ }
++
++ return ((__raw_readl(base) & mask) >> shift);
++}
++
++EXPORT_SYMBOL(s3c_gpio_getcfg);
++
++void s3c_gpio_pullup(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
++ unsigned long offs = S3C_GPIO_OFFSET(pin)*2;
++ unsigned long flags;
++ unsigned long up;
++ unsigned long mask;
++
++ mask = 0x3 << offs;
++
++ if((pin>=S3C_GPH0 && pin<=S3C_GPH9)||\
++ (pin>=S3C_GPK0 && pin<=S3C_GPK15)||\
++ (pin>=S3C_GPL0 && pin<=S3C_GPL14))
++ {
++ base = base+0x04;
++ }
++
++ local_irq_save(flags);
++ local_irq_disable();
++
++ up = __raw_readl(base + 0x08);
++ up &= ~mask;
++ up |= to << offs;
++ __raw_writel(up, base + 0x08);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s3c_gpio_pullup);
++
++void s3c_gpio_setpin(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
++ unsigned long offs = S3C_GPIO_OFFSET(pin);
++ unsigned long flags;
++ unsigned long dat;
++
++ if((pin>=S3C_GPH0 && pin<=S3C_GPH9)||\
++ (pin>=S3C_GPK0 && pin<=S3C_GPK15)||\
++ (pin>=S3C_GPL0 && pin<=S3C_GPL14))
++ {
++ base = base+0x04;
++ }
++
++ local_irq_save(flags);
++ local_irq_disable();
++
++ dat = __raw_readl(base + 0x04);
++ dat &= ~(1 << offs);
++ dat |= to << offs;
++ __raw_writel(dat, base + 0x04);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s3c_gpio_setpin);
++
++unsigned int s3c_gpio_getpin(unsigned int pin)
++{
++ void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
++ unsigned long offs = S3C_GPIO_OFFSET(pin);
++
++ if((pin>=S3C_GPH0 && pin<=S3C_GPH9)||\
++ (pin>=S3C_GPK0 && pin<=S3C_GPK15)||\
++ (pin>=S3C_GPL0 && pin<=S3C_GPL14))
++ {
++ base = base+0x04;
++ }
++ return __raw_readl(base + 0x04) & (1<< offs);
++}
++
++EXPORT_SYMBOL(s3c_gpio_getpin);
++
++int s3c_gpio_getirq(unsigned int pin)
++{
++
++/* mandatory */
++/* Implement this function */
++ return 0;
++}
++
++EXPORT_SYMBOL(s3c_gpio_getirq);
++
++int s3c_gpio_irqfilter(unsigned int pin, unsigned int on,
++ unsigned int config)
++{
++
++ return 0;
++}
++
++EXPORT_SYMBOL(s3c_gpio_irqfilter);
++#endif
+diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
+index 8fbc884..9116196 100644
+--- a/arch/arm/plat-s3c24xx/irq.c
++++ b/arch/arm/plat-s3c24xx/irq.c
+@@ -195,6 +195,77 @@ static struct irq_chip s3c_irq_chip = {
+ .set_wake = s3c_irq_wake
+ };
+
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++/*--- For additional interrupt sources on S3C2450/S3C2416 ----*/
++static void
++s3c2450_irq_mask(unsigned int irqno)
++{
++ unsigned long mask;
++
++ irqno -= IRQ_S3C2450_2D;
++
++ mask = __raw_readl(S3C2450_INTMSK);
++ mask |= 1UL << irqno;
++ __raw_writel(mask, S3C2450_INTMSK);
++}
++
++static inline void
++s3c2450_irq_ack(unsigned int irqno)
++{
++ unsigned long bitval = 1UL << (irqno - IRQ_S3C2450_2D);
++
++ __raw_writel(bitval, S3C2450_SRCPND);
++ __raw_writel(bitval, S3C2450_INTPND);
++}
++
++static inline void
++s3c2450_irq_maskack(unsigned int irqno)
++{
++ unsigned long bitval = 1UL << (irqno - IRQ_S3C2450_2D);
++ unsigned long mask;
++
++ mask = __raw_readl(S3C2450_INTMSK);
++ __raw_writel(mask|bitval, S3C2450_INTMSK);
++
++ __raw_writel(bitval, S3C2450_SRCPND);
++ __raw_writel(bitval, S3C2450_INTPND);
++}
++
++
++static void
++s3c2450_irq_unmask(unsigned int irqno)
++{
++ unsigned long mask;
++
++ irqno -= IRQ_S3C2450_2D;
++
++ mask = __raw_readl(S3C2450_INTMSK);
++ mask &= ~(1UL << irqno);
++ __raw_writel(mask, S3C2450_INTMSK);
++}
++
++
++
++struct irq_chip s3c2450_irq_level_chip = {
++ .name = "s3c2450-level",
++ .ack = s3c2450_irq_maskack,
++ .mask = s3c2450_irq_mask,
++ .unmask = s3c2450_irq_unmask,
++ //.set_wake = s3c2450_irq_wake
++};
++
++static struct irq_chip s3c2450_edge_irq_chip = {
++ .name = "s3c2450-edge",
++ .ack = s3c2450_irq_ack,
++ .mask = s3c2450_irq_mask,
++ .unmask = s3c2450_irq_unmask,
++ //.set_wake = s3c2450_irq_wake
++};
++/*--------------------------------------------------------------*/
++#endif
++
++
+ static void
+ s3c_irqext_mask(unsigned int irqno)
+ {
+@@ -796,5 +867,13 @@ void __init s3c24xx_init_irq(void)
+ set_irq_flags(irqno, IRQF_VALID);
+ }
+
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ for (irqno = IRQ_S3C2450_2D; irqno <= IRQ_S3C2450_I2S1; irqno++) {
++ set_irq_chip(irqno, &s3c2450_irq_level_chip);
++ set_irq_handler(irqno, handle_level_irq);
++ set_irq_flags(irqno, IRQF_VALID);
++ }
++#endif
++
+ irqdbf("s3c2410: registered interrupt handlers\n");
+ }
+diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
+index 3444b13..9b3adec 100644
+--- a/arch/arm/plat-s3c24xx/s3c244x.c
++++ b/arch/arm/plat-s3c24xx/s3c244x.c
+@@ -40,6 +40,7 @@
+ #include "s3c244x.h"
+ #include <asm/plat-s3c24xx/clock.h>
+ #include <asm/plat-s3c24xx/devs.h>
++#include <asm/plat-s3c24xx/common-smdk.h>
+ #include <asm/plat-s3c24xx/cpu.h>
+ #include <asm/plat-s3c24xx/pm.h>
+
+diff --git a/arch/arm/plat-s3c24xx/s3c24xx-dvfs.c b/arch/arm/plat-s3c24xx/s3c24xx-dvfs.c
+new file mode 100644
+index 0000000..1d6dd82
+--- /dev/null
++++ b/arch/arm/plat-s3c24xx/s3c24xx-dvfs.c
+@@ -0,0 +1,585 @@
++/*
++ * Copyright (c) 2008 Samsung Electronics
++ * Kwanghyun.La <nala.la@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C64xx DVFS interface with LTC3714 DCDC convertor power
++ * 2008.02.28. basic scheme update to here
++*/
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/fcntl.h>
++
++#include <asm/uaccess.h>
++#include <asm/io.h>
++
++#include <linux/stat.h>
++#include <linux/proc_fs.h>
++
++#include <linux/delay.h> // For loops_per_jiffy
++#include <asm/arch/regs-gpio.h>
++
++#include "s3c24xx-dvfs.h"
++
++#define DEV_NAME "s3c24xx-dvfs"
++#define DEV_MAJOR 240
++
++
++
++#define XTAL 12*1000*1000 /* Clock source 12Mhz */
++#define MAX_APLL_RATIO 7 /* See S3C6400 user manual 3-7 */
++#define MAX_HCLK2_RATIO 7 /* See S3C6400 user manual 0-1 */
++#define Mhz 1000*1000
++
++#define SUPPORT_PROC_FS
++
++#ifdef SUPPORT_PROC_FS
++struct proc_dir_entry *proc_root_fp = NULL;
++struct proc_dir_entry *proc_voltage_fp = NULL;
++struct proc_dir_entry *proc_freq_fp = NULL;
++struct proc_dir_entry *proc_step_fp = NULL;
++
++char proc_voltage_str[PAGE_SIZE-80] = { 0,};
++char proc_freq_str[PAGE_SIZE-80] = { 0,};
++char proc_step_str[PAGE_SIZE-80] = { 0,};
++#endif
++
++
++/* it's depend on DCDC regurator specification
++ * if change parts, you must be change table and configuration*/
++static const unsigned int voltage_table[32] = {
++ 1750, 1700, 1650, 1600, 1550, 1500, 1450, 1400,
++ 1350, 1300, 1250, 1200, 1150, 1100, 1050, 1000,
++ 975, 950, 925, 900, 875, 850, 825, 800,
++ 775, 750, 725, 700, 675, 650, 625, 600,
++};
++
++#define NUMBER_OF_STEP 4
++
++/*Frequency step define section */
++#define MDIV 0
++#define PDIV 1
++#define SDIV 2
++#define ARM_RATIO 3
++#define HCLK_RATIO 4
++#define DVFS MDIV /* for S3C2443,2416 and S3C2450*/
++
++#define ARM_VOLT_STEP 0
++#define INT_VOLT_STEP 1
++#define FREQ_STEP 2
++
++static const unsigned int pll_mps_table[][5] = {
++ {0, 0, 0, 0, 1}, /* step 0 DVS OFF, ARM:534MHz ,HCLK:133MHz*/
++ {0, 0, 0, 1, 1}, /* step 1 DVS OFF, ARM:266MHz ,HCLK:133MHz*/
++ {0, 0, 0, 3, 1}, /* step 2 DVS OFF, ARM:133MHz ,HCLK:133MHz*/
++ {1, 0, 0, 3, 1}, /* step 3 DVS ON , ARM:133MHz ,HCLK:133MHz careful the linked devices*/
++/* {DVS_ON, NA, NA, ARM RATIO, HCLK RATIO } */
++/* S3C24xx case , when HCLK is changed , UART signal is fragle, so must need to re setting the uart div
++ and the ARM Clock must be over than HCLK or same, it'can not support under HCLK*/
++};
++
++static const unsigned int pll_mps_table400[][5] = {
++ {0, 0, 0, 1, 1}, /* step 0 DVS OFF, ARM:400MHz ,HCLK:133MHz*/
++ {0, 0, 0, 2, 1}, /* step 1 DVS OFF, ARM:266MHz ,HCLK:133MHz*/
++ {0, 0, 0, 4, 1}, /* step 2 DVS OFF, ARM:160Hz ,HCLK:133MHz*/
++ {1, 0, 0, 4, 1}, /* step 3 DVS ON , ARM:160MHz ,HCLK:133MHz careful the linked devices*/
++/* {DVS_ON, NA, NA, ARM RATIO, HCLK RATIO } */
++/* S3C24xx case , when HCLK is changed , UART signal is fragle, so must need to re setting the uart div
++ and the ARM Clock must be over than HCLK or same, it'can not support under HCLK*/
++};
++
++static const unsigned int dvfs_step[NUMBER_OF_STEP][3] = {
++ { 1200 , 1200, 0}, /* ARM 1.2Volt, INT 1.2V, pll mode 0 533-133*/
++ { 1100 , 1100, 1}, /* ARM 1.0Volt, INT 1.0V, pll mode 2 200-133*/
++ { 975 , 1100, 2}, /* ARM 1.0Volt, INT 1.0V, pll mode 2 200-133*/
++ { 955 , 1000, 3}, /* ARM 1.0Volt, INT 1.0V, pll mode 3 100- 66*/
++/* {ARM Voltage,INT ARM Voltage, Frequency_STEP} */
++};
++
++static int previous_dvfs_step;
++
++static s3c_dvfs_info dvfs_info;
++
++static void set_dvfs_gpio(void)
++{
++ /* We can control the voltage of ARM core and Internal block by setting GPIO */
++ /* GPN(11~15). First of all, we should set these gpio to output mode. */
++ /* GPIO configuration */
++ GPIO_CFG(LTC3714_DATA1, LTC3714_OUTP1);
++ GPIO_CFG(LTC3714_DATA2, LTC3714_OUTP2);
++ GPIO_CFG(LTC3714_DATA3, LTC3714_OUTP3);
++ GPIO_CFG(LTC3714_DATA4, LTC3714_OUTP4);
++ GPIO_CFG(LTC3714_DATA5, LTC3714_OUTP5);
++
++ /* Pull-up/down disable */
++ GPIO_PULLUP(LTC3714_DATA1, 0x0);
++ GPIO_PULLUP(LTC3714_DATA2, 0x0);
++ GPIO_PULLUP(LTC3714_DATA3, 0x0);
++ GPIO_PULLUP(LTC3714_DATA4, 0x0);
++ GPIO_PULLUP(LTC3714_DATA5, 0x0);
++
++
++ /* Latch control signal*/
++ /* CORE_REG_OE: GPL9, ARM_REG_OE: GPL8, INT_REG_LE: GPL10*/
++ GPIO_CFG(ARM_LE , ARM_LE_OUTP);
++ GPIO_CFG(DVS_OE , DVS_OE_OUTP);
++ GPIO_CFG(INT_LE , INT_LE_OUTP);
++
++ GPIO_PULLUP(ARM_LE , 0x0);
++ GPIO_PULLUP(DVS_OE , 0x0);
++ GPIO_PULLUP(INT_LE , 0x0);
++
++
++}
++
++/* Set LTC3714 voltage regulator */
++/* Input : pwr : 1(ARM), 2(Internal), 3(Both) */
++/* voltage : 1mV step */
++static int set_ltc3714(unsigned int pwr, unsigned int voltage)
++{
++ int position = 0;
++ unsigned int val;
++
++
++ if(voltage > voltage_table[0] || voltage < voltage_table[31]) {
++ printk("[ERROR]: voltage value over limits!!!");
++ return -EINVAL;
++ }
++
++ if(voltage > voltage_table[16]) { // 1750 ~ 1000 mV
++ for(position = 15; position >= 0; position --) {
++ if(voltage_table[position] == voltage) break;
++ }
++
++ }
++ else if(voltage >= voltage_table[31]) { //975 ~ 600 mV
++ for(position = 31; position >= 16; position --) {
++ if(voltage_table[position] == voltage) break;
++ }
++ }
++ else {
++ printk("[error]: Can't find adquate voltage table list value\n");
++ return -EINVAL;
++ }
++
++ printk("Founded postion :[%d] \n",position);
++
++ position &=0x1f;
++
++ /* It's depend on schematic and assigned GPIO pin */
++ val = __raw_readl(S3C2410_GPCDAT) &~(0x1<<7|0x1<<6|0x1<<5|0x1<<0);
++ val |= ((((position & 0xe)>>1)<<5)|(position & 0x1));
++ __raw_writel(val, S3C2410_GPCDAT);
++
++ val = __raw_readl(S3C2410_GPBDAT) &~(0x1<<2);
++ val |= (position & 0x10)<<2;
++ __raw_writel(val,S3C2410_GPBDAT);
++
++ if(pwr == ARM_VOLT_STEP) { //ARM Voltage Control => ARM_REG_LE => Output H => Data Changed
++
++ CONTROl_SET(ARM_LE, 0x1);
++ udelay(10);
++ CONTROl_SET(ARM_LE, 0x0);
++ } else if(pwr == INT_VOLT_STEP) { // INT Voltage Control
++ CONTROl_SET(INT_LE, 0x1);
++ udelay(10);
++ CONTROl_SET(INT_LE, 0x0);
++ } else {
++ printk("[error]: set_ltc3714, check mode [pwr] value\n");
++ return -EINVAL;
++ }
++
++
++ return 0;
++
++}
++
++/* Set CLK_DIV0 register with specific APLL divider value*/
++static int set_freq_divider(unsigned int clk_source , unsigned int val)
++{
++ unsigned int tmp;
++
++ if (clk_source == ARM_RATIO){
++ if(val > MAX_APLL_RATIO) {
++ printk(KERN_ERR "Freq divider value(APLL_RATIO) is out of spec\n");
++ printk(KERN_ERR "APLL_RATIO : 0~7\n");
++ return -EINVAL;
++ }
++ dvfs_info.freq_divider = (val + 1);
++ tmp = __raw_readl(ARM_CLK_DIV)&~ARM_DIV_MASK;
++ tmp |= val<<ARM_DIV_RATIO_BIT;
++ __raw_writel(tmp, ARM_CLK_DIV);
++ } else if (clk_source == HCLK_RATIO){
++ if(val > MAX_HCLK2_RATIO) {
++ printk(KERN_ERR "Freq divider value is out of spec\n");
++ printk(KERN_ERR "HCLK_PostDivider RATIO : 0,1 \n");
++ return -EINVAL;
++ }
++ /* it's only for setting the HCLK or system Clock */
++ tmp = __raw_readl(ARM_CLK_DIV) & ~HCLK_DIV_MASK;
++ tmp |= (val<<HCLK_DIV_RATIO_BIT);
++ __raw_writel(tmp, ARM_CLK_DIV);
++ } else {
++ printk(KERN_ERR " It's wrong clock post divider path \n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* Set APLL P,M,S value to make specific CPU frequency*/
++/* Only support Async mode */
++static int set_pll(unsigned int freq_level)
++{
++ unsigned int val,err;
++
++ if (freq_level < NUMBER_OF_STEP ){
++
++ val = ((__raw_readl(MPLL_CON)>>14)&0x3ff);
++
++ if (val == 267){
++ err = set_freq_divider(ARM_RATIO, pll_mps_table[freq_level][ARM_RATIO]);
++ if(err)
++ return err;
++
++ err = set_freq_divider(HCLK_RATIO, pll_mps_table[freq_level][HCLK_RATIO]);
++ if(err)
++ return err;
++ }
++ else{
++ err = set_freq_divider(ARM_RATIO, pll_mps_table400[freq_level][ARM_RATIO]);
++ if(err)
++ return err;
++
++ err = set_freq_divider(HCLK_RATIO, pll_mps_table400[freq_level][HCLK_RATIO]);
++ if(err)
++ return err;
++ }
++
++ val = __raw_readl(ARM_CLK_DIV) & ~(DVFS_MASK);
++ val |= (pll_mps_table[freq_level][DVFS] << 13) ;
++ __raw_writel(val, ARM_CLK_DIV);
++ }
++ else{
++ printk("It's wrong DFS %d range \n",freq_level);
++ }
++
++ return 0;
++}
++
++/* Other modules can use this function to change power status */
++/* Especially, ARM Dynamic power interface can control DVFS by accessing this */
++int set_dvfs_step(unsigned int step)
++{
++ int err;
++
++ if(step >= NUMBER_OF_STEP) {
++ printk(KERN_ERR "DVFS step is out of range(0 ~ %2d)\n",NUMBER_OF_STEP-1);
++ return -EINVAL;
++ }
++
++ if(previous_dvfs_step < step) { // decreasing CPU freq & Voltage
++ /* CPU Frequency control */
++ err = set_pll(dvfs_step[step][FREQ_STEP]);
++
++ /* CPU voltage control */
++ dvfs_info.pwr_type = ARM_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][ARM_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ }
++
++
++ dvfs_info.pwr_type = INT_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][INT_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ }
++
++ } else if(previous_dvfs_step > step) { // increasing CPU freq & Voltage
++
++ /* CPU voltage control */
++ dvfs_info.pwr_type = ARM_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][ARM_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ }
++
++ dvfs_info.pwr_type = INT_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][INT_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ }
++
++ /* CPU Frequency control */
++ err = set_pll(dvfs_step[step][FREQ_STEP]);
++
++ } else {
++ }
++ previous_dvfs_step = step;
++
++ return 0;
++}
++
++EXPORT_SYMBOL(set_dvfs_step);
++
++int s3c_dvfs_open(struct inode *inode, struct file *filp)
++{
++ int num = MINOR(inode->i_rdev);
++
++ printk("s3c_dvfs_open -> minor : %d\n", num);
++
++ return 0;
++}
++
++ssize_t s3c_dvfs_read(struct file *filp, char *buf, size_t count,
++ loff_t *f_pos)
++{
++ return 0;
++}
++
++ssize_t s3c_dvfs_write(struct file *filp, const char *buf, size_t count,
++ loff_t *f_pos)
++{
++ return 0;
++}
++
++int s3c_dvfs_ioctl(struct inode *inode, struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ int err, size;
++
++ if(_IOC_TYPE(cmd) != DVFS_IOCTL_MAGIC) return -EINVAL;
++ if(_IOC_NR(cmd) >= DVFS_MAXNR) return -EINVAL;
++
++ size = _IOC_SIZE(cmd);
++
++ switch(cmd) {
++ case DVFS_ON:
++ break;
++ case DVFS_OFF:
++ break;
++ case DVFS_GET_STATUS:
++ err=copy_to_user((void *) arg, (const void *) &dvfs_info, (unsigned long) size);
++ break;
++ case DVFS_SET_STATUS:
++ err=copy_from_user((void *) &dvfs_info, (const void *) arg, size);
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++
++ if(err != 0) return err;
++
++ if(dvfs_info.pwr_type == ARM_VOLT_STEP) {
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ } else if(dvfs_info.pwr_type == INT_VOLT_STEP) {
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ } else {
++ }
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++int s3c_dvfs_release(struct inode *inode, struct file *filp)
++{
++ printk("s3c_dvfs_release \n");
++ return 0;
++}
++
++struct file_operations s3c_dvfs_fops =
++{
++ .owner = THIS_MODULE,
++ .read = s3c_dvfs_read,
++ .write = s3c_dvfs_write,
++ .ioctl = s3c_dvfs_ioctl,
++ .open = s3c_dvfs_open,
++ .release = s3c_dvfs_release,
++};
++
++#ifdef SUPPORT_PROC_FS
++int read_proc_voltage(char *page, char **start, off_t off,
++ int count, int *eof, void *data_unused)
++{
++ char *buf;
++
++ buf = page;
++ buf += sprintf(buf, "ARM = [%d]mV, Internal = [%d]mV\n", dvfs_info.curr_voltage_arm,dvfs_info.curr_voltage_internal);
++
++ return buf - page;
++}
++
++int write_proc_voltage(struct file *file, const char __user *buffer,
++ unsigned long count, void *data)
++{
++ int len, err;
++ char *realdata;
++
++ realdata = (char *) data;
++
++ if(copy_from_user(realdata, buffer, count))
++ return -EFAULT;
++
++ realdata[count] = '\0';
++ len = strlen(realdata);
++ if(realdata[len - 1] == '\n')
++ realdata[--len] = 0;
++
++ dvfs_info.new_voltage = simple_strtoul(realdata, NULL, 10);
++
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++
++ if(err == 0) {
++ if(dvfs_info.pwr_type == ARM_VOLT_STEP) {
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ } else if(dvfs_info.pwr_type == INT_VOLT_STEP) {
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ } else {
++ }
++ }
++
++ return count;
++}
++
++int read_proc_freq(char *page, char **start, off_t off,
++ int count, int *eof, void *data_unused)
++{
++ char *buf;
++ unsigned int arm_freq,tmp;
++
++ arm_freq = GET_ARM_CLOCK(XTAL);
++ dvfs_info.freq_divider = READ_ARM_DIV;
++ dvfs_info.curr_freq = arm_freq/dvfs_info.freq_divider;
++
++ tmp=__raw_readl(ARM_CLK_DIV) ;
++ if((tmp&DVFS_MASK)){ /* if DVFS set, HCLK use for ARMCLK*/
++ dvfs_info.curr_freq = arm_freq/(((tmp & HCLK_DIV_MASK)+1)<<((tmp&0x8)>>3));
++ }
++
++ buf = page;
++ buf += sprintf(buf, "Freq = [%d]MHz\n", dvfs_info.curr_freq/1000000);
++
++ return buf - page;
++}
++
++int write_proc_freq(struct file *file, const char __user *buffer,
++ unsigned long count, void *data)
++{
++ int len, tmp, err;
++ char *realdata;
++
++ realdata = (char *) data;
++
++ if(copy_from_user(realdata, buffer, count))
++ return -EFAULT;
++
++ realdata[count] = '\0';
++ len = strlen(realdata);
++ if(realdata[len - 1] == '\n')
++ realdata[--len] = 0;
++ tmp = simple_strtoul(realdata, NULL, 10);
++
++ printk("level %d \n",tmp);
++
++ err = set_freq_divider(ARM_RATIO, tmp);
++ if(err){
++ printk("level err %d \n",err);
++ return err;
++ }
++
++ return count;
++}
++
++int write_proc_step(struct file *file, const char __user *buffer, unsigned long count, void *data)
++{
++ int len, tmp, err;
++ char *realdata;
++
++ realdata = (char *) data;
++
++ if(copy_from_user(realdata, buffer, count))
++ return -EFAULT;
++ realdata[count] = '\0';
++ len = strlen(realdata);
++ if(realdata[len - 1] == '\n')
++ realdata[--len] = 0;
++ tmp = simple_strtoul(realdata, NULL, 10);
++
++ err = set_dvfs_step(tmp);
++
++ return count;
++}
++
++#endif
++
++int s3c_dvfs_init(void)
++{
++ int result;
++
++ /* Initialize structure */
++ previous_dvfs_step = -1; /* 1st initial operating*/
++ set_dvfs_gpio();
++ set_dvfs_step(0); // Set Maximum or default initial performance set
++ CONTROl_SET(DVS_OE, 0x1); /* Just open target power voltage*/
++
++ result = register_chrdev(DEV_MAJOR, DEV_NAME, &s3c_dvfs_fops);
++
++ if(result < 0)
++ return result;
++
++
++
++#ifdef SUPPORT_PROC_FS
++ proc_root_fp = proc_mkdir("dvfs", 0);
++
++ proc_voltage_fp = create_proc_entry("voltage", S_IFREG | S_IRWXU, proc_root_fp);
++ if(proc_voltage_fp) {
++ proc_voltage_fp->data = proc_voltage_str;
++ proc_voltage_fp->read_proc = read_proc_voltage;
++ proc_voltage_fp->write_proc = write_proc_voltage;
++ }
++
++ proc_freq_fp = create_proc_entry("frequency", S_IFREG | S_IRWXU, proc_root_fp);
++ if(proc_freq_fp) {
++ proc_freq_fp->data = proc_freq_str;
++ proc_freq_fp->read_proc = read_proc_freq;
++ proc_freq_fp->write_proc = write_proc_freq;
++ }
++
++ proc_step_fp = create_proc_entry("step", S_IFREG | S_IWUSR, proc_root_fp);
++ if(proc_step_fp) {
++ proc_step_fp->data = proc_step_str;
++ proc_step_fp->read_proc = NULL;
++ proc_step_fp->write_proc = write_proc_step;
++ }
++#endif
++
++ return 0;
++}
++
++void s3c_dvfs_exit(void)
++{
++ unregister_chrdev(DEV_MAJOR, DEV_NAME);
++ remove_proc_entry("voltage", proc_root_fp);
++ remove_proc_entry("frequency", proc_root_fp);
++ remove_proc_entry("step", proc_root_fp);
++ remove_proc_entry("dvfs", 0);
++}
++
++module_init(s3c_dvfs_init);
++module_exit(s3c_dvfs_exit);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("S3C24xx DVFS Driver");
++MODULE_AUTHOR("Jongpill.Lee, <boyko.lee@samsung.com>");
+diff --git a/arch/arm/plat-s3c24xx/s3c24xx-dvfs.h b/arch/arm/plat-s3c24xx/s3c24xx-dvfs.h
+new file mode 100644
+index 0000000..37e4d21
+--- /dev/null
++++ b/arch/arm/plat-s3c24xx/s3c24xx-dvfs.h
+@@ -0,0 +1,70 @@
++/*
++ 2008.04.14. All of AP are merged single application and definitin
++ in order to be matcing dvs and dfs concept
++ These are confirm on SMDK2450, SMDK2416
++*/
++#ifndef __S3C24XXDVFS_H_
++#define __S3C24XXDVFS_H_
++
++#define DVFS_IOCTL_MAGIC 'd'
++
++typedef struct {
++ unsigned int pwr_type; //ARM:ARMV_STEP, INT:INTV_STEP
++ unsigned int curr_voltage_arm; //ARM core voltage
++ unsigned int curr_voltage_internal; //Internal block voltage
++ unsigned int new_voltage;
++ unsigned int curr_freq;
++ unsigned int freq_divider; // APLL_RATIO + 1
++ unsigned int size;
++} s3c_dvfs_info;
++
++#define DVFS_ON _IO(DVFS_IOCTL_MAGIC, 0)
++#define DVFS_OFF _IO(DVFS_IOCTL_MAGIC, 1)
++#define DVFS_GET_STATUS _IOR(DVFS_IOCTL_MAGIC, 2, s3c_dvfs_info)
++#define DVFS_SET_STATUS _IOW(DVFS_IOCTL_MAGIC, 3, s3c_dvfs_info)
++
++#define DVFS_MAXNR 4
++
++/* Board dependency SIGNAL and GPIO configuration */
++#include <asm/arch-s3c2410/regs-s3c-clock.h>
++
++#define ARM_LE S3C2410_GPF5
++#define DVS_OE S3C2410_GPF6
++#define INT_LE S3C2410_GPF7
++
++#define CONTROl_SET(pin,to) s3c2410_gpio_setpin(pin, to);
++#define ARM_LE_OUTP S3C2410_GPF5_OUTP
++#define DVS_OE_OUTP S3C2410_GPF6_OUTP
++#define INT_LE_OUTP S3C2410_GPF7_OUTP
++
++#define LTC3714_DATA1 S3C2410_GPC0
++#define LTC3714_DATA2 S3C2410_GPC5
++#define LTC3714_DATA3 S3C2410_GPC6
++#define LTC3714_DATA4 S3C2410_GPC7
++#define LTC3714_DATA5 S3C2410_GPB2
++
++#define LTC3714_OUTP1 S3C2410_GPC0_OUTP
++#define LTC3714_OUTP2 S3C2410_GPC5_OUTP
++#define LTC3714_OUTP3 S3C2410_GPC6_OUTP
++#define LTC3714_OUTP4 S3C2410_GPC7_OUTP
++#define LTC3714_OUTP5 S3C2410_GPB2_OUTP
++
++#define GPIO_CFG(pin, fnc) s3c2410_gpio_cfgpin((pin),(fnc))
++#define GPIO_PULLUP(pin, to) s3c2410_gpio_pullup((pin),(to))
++
++#define ARM_PLL_CON S3C2443_MPLLCON
++#define ARM_CLK_DIV S3C2443_CLKDIV0
++#define MPLL_CON S3C2443_MPLLCON
++#define ARM_DIV_RATIO_BIT 9
++#define ARM_DIV_MASK (0xf<<ARM_DIV_RATIO_BIT)
++#define HCLK_DIV_RATIO_BIT 0
++#define HCLK_DIV_MASK (0x3<<HCLK_DIV_RATIO_BIT)
++#define DVFS_MASK (0x1<<13)
++
++#define READ_ARM_DIV (((__raw_readl(ARM_CLK_DIV)&ARM_DIV_MASK)>>9) + 1)
++#define PLL_CALC_VAL(MDIV,PDIV,SDIV) ((MDIV)<<14 |(PDIV)<<5 |(SDIV))
++#define GET_ARM_CLOCK(baseclk) s3c2443_get_mpll(__raw_readl(S3C2443_MPLLCON),baseclk)
++
++
++
++#endif //__S3C24XXDVS_H_
+diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
+new file mode 100644
+index 0000000..9ee835c
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/Kconfig
+@@ -0,0 +1,32 @@
++# arch/arm/plat-s3c64xx/Kconfig
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++config PLAT_S3C64XX
++ bool "S3C64XX Platform support"
++ depends on ARCH_S3C2410 && (CPU_S3C6400 || CPU_S3C6410)
++ default y if CPU_S3C6400
++ help
++ Support for S3C6400 and S3C64XX series Samsung Mobile CPU based systems.
++
++if PLAT_S3C64XX
++config S3C64XX_DMA
++ bool "S3C64XX DMA support"
++ depends on CPU_S3C6400 || CPU_S3C6410
++ help
++ S3C6400(6410) DMA support. This is needed for drivers like sound which
++ use the S3C6400(6410)'s DMA system to move data to and from the
++ peripheral blocks.
++
++config S3C64XX_ADC
++ bool "S3C64XX ADC Driver"
++ depends on CPU_S3C6400 || CPU_S3C6410
++ help
++ ADC (A/D Conversion) driver for Samsung S3C6400/6410.
++endif
++
++
++
++
+diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
+new file mode 100644
+index 0000000..bce4072
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/Makefile
+@@ -0,0 +1,31 @@
++# arch/arm/plat-s3c64xx/Makefile
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++obj-y :=
++obj-m :=
++obj-n :=
++obj- :=
++
++
++# Core files
++
++obj-y += ../plat-s3c24xx/cpu.o
++obj-$(CONFIG_PLAT_S3C64XX) += irq-pl192.o
++obj-y += ../plat-s3c24xx/devs.o
++obj-y += ../plat-s3c24xx/gpio.o
++obj-$(CONFIG_PLAT_S3C64XX) += time-s3c64xx.o
++obj-y += clock.o
++
++# Architecture dependant builds
++
++obj-$(CONFIG_S3C64XX_DMA) += dma-pl080.o
++obj-$(CONFIG_S3C_ADC) += adc-s3c64xx.o
++obj-$(CONFIG_MACH_SMDK) += ../plat-s3c24xx/common-smdk.o
++obj-$(CONFIG_PM) += pm.o
++obj-$(CONFIG_PM) += sleep.o
++obj-$(CONFIG_S3C64XX_DVFS) += s3c64xx-dvfs.o
++obj-$(CONFIG_CPU_FREQ) += s3c64xx-cpufreq.o
++obj-$(CONFIG_CPU_FREQ) += ltc3714.o
+diff --git a/arch/arm/plat-s3c64xx/adc-s3c64xx.c b/arch/arm/plat-s3c64xx/adc-s3c64xx.c
+new file mode 100644
+index 0000000..f77700f
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/adc-s3c64xx.c
+@@ -0,0 +1,336 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
++ * iPAQ H1940 touchscreen support
++ *
++ * ChangeLog
++ *
++ * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
++ * - added clock (de-)allocation code
++ *
++ * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org>
++ * - h1940_ -> s3c24xx (this driver is now also used on the n30
++ * machines :P)
++ * - Debug messages are now enabled with the config option
++ * TOUCHSCREEN_S3C_DEBUG
++ * - Changed the way the value are read
++ * - Input subsystem should now work
++ * - Use ioremap and readl/writel
++ *
++ * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org>
++ * - Make use of some undocumented features of the touchscreen
++ * controller
++ *
++ */
++
++
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++
++#include <asm/plat-s3c/regs-adc.h>
++#include <asm/plat-s3c/adc.h>
++#include <asm/arch/irqs.h>
++
++#define ADC_MINOR 131
++#define ADC_INPUT_PIN _IOW('S', 0x0c, unsigned long)
++
++#define ADC_WITH_TOUCHSCREEN
++
++static struct clk *adc_clock;
++static struct resource *adc_mem;
++static void __iomem *base_addr;
++static int adc_port = 0;
++
++#ifdef ADC_WITH_TOUCHSCREEN
++static DEFINE_MUTEX(adc_mutex);
++
++static unsigned long data_for_ADCCON;
++static unsigned long data_for_ADCTSC;
++
++static void s3c_adc_save_SFR_on_ADC(void) {
++
++ data_for_ADCCON = readl(base_addr+S3C2410_ADCCON);
++ data_for_ADCTSC = readl(base_addr+S3C2410_ADCTSC);
++}
++
++static void s3c_adc_restore_SFR_on_ADC(void) {
++
++ writel(data_for_ADCCON, base_addr+S3C2410_ADCCON);
++ writel(data_for_ADCTSC, base_addr+S3C2410_ADCTSC);
++}
++#endif
++
++static int s3c_adc_open(struct inode *inode, struct file *file)
++{
++ printk(KERN_INFO " s3c_adc_open() entered\n");
++ return 0;
++}
++
++static int s3c_adc_get(struct s3c_adc_request *req)
++{
++ unsigned adc_channel = req->channel;
++ int adc_value_ret = 0;
++
++ adc_value_ret = s3c_adc_convert(base_addr, adc_channel);
++
++ req->callback(adc_channel,req->param,adc_value_ret);
++
++ return 0;
++}
++
++static ssize_t
++s3c_adc_read(struct file *file, char __user * buffer,
++ size_t size, loff_t * pos)
++{
++ int adc_value = 0;
++
++ printk(KERN_INFO " s3c_adc_read() entered\n");
++
++#ifdef ADC_WITH_TOUCHSCREEN
++ mutex_lock(&adc_mutex);
++ s3c_adc_save_SFR_on_ADC();
++#endif
++
++ adc_value = s3c_adc_convert(base_addr, adc_port);
++
++#ifdef ADC_WITH_TOUCHSCREEN
++ s3c_adc_restore_SFR_on_ADC();
++ mutex_unlock(&adc_mutex);
++#endif
++
++ printk(KERN_INFO " Converted Value: %03d\n", adc_value);
++
++ if (copy_to_user(buffer, &adc_value, sizeof(unsigned int))) {
++ return -EFAULT;
++ }
++ return sizeof(unsigned int);
++}
++
++
++static int s3c_adc_ioctl(struct inode *inode, struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++
++ printk(KERN_INFO " s3c_adc_ioctl(cmd:: %d) entered\n", cmd);
++
++ switch (cmd) {
++
++ case ADC_INPUT_PIN:
++ adc_port = (unsigned int) arg;
++
++ if (adc_port >= 4)
++ printk(" %d is already reserved for TouchScreen\n", adc_port);
++ return 0;
++
++ default:
++ return -ENOIOCTLCMD;
++
++ }
++}
++
++static struct file_operations s3c_adc_fops = {
++ .owner = THIS_MODULE,
++ .read = s3c_adc_read,
++ .open = s3c_adc_open,
++ .ioctl = s3c_adc_ioctl,
++};
++
++static struct miscdevice s3c_adc_miscdev = {
++ .minor = ADC_MINOR,
++ .name = "adc",
++ .fops = &s3c_adc_fops,
++};
++
++static struct s3c_adc_cfg *s3c_adc_get_platdata(struct device *dev)
++{
++ if(dev->platform_data != NULL)
++ {
++ printk(KERN_INFO "ADC platform data read\n");
++ return (struct s3c_adc_cfg*)dev->platform_data;
++ }
++
++ return &s3c_adc_platform;
++}
++
++/*
++ * The functions for inserting/removing us as a module.
++ */
++
++static int __init s3c_adc_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ struct s3c_adc_cfg *plat_data;
++ struct device *dev;
++ int ret;
++ int size;
++
++ res = platform_get_resource(pdev,IORESOURCE_MEM,0);
++ dev = &pdev->dev;
++
++ if(res == NULL){
++ dev_err(dev,"no memory resource specified\n");
++ return -ENOENT;
++ }
++
++ size = (res->end - res->start) + 1;
++
++#if !defined(ADC_WITH_TOUCHSCREEN)
++ adc_mem = request_mem_region(res->start, size, pdev->name);
++ if(adc_mem == NULL){
++ dev_err(dev, "failed to get memory region\n");
++ ret = -ENOENT;
++ goto err_req;
++ }
++#endif
++
++ base_addr = ioremap(res->start,size);
++ if(base_addr == NULL){
++ dev_err(dev,"fail to ioremap() region\n");
++ ret = -ENOENT;
++ goto err_map;
++ }
++
++ adc_clock = clk_get(&pdev->dev, "adc");
++
++ if(IS_ERR(adc_clock)){
++ dev_err(dev,"failed to fine adc clock wource\n");
++ ret = PTR_ERR(adc_clock);
++ goto err_clk;
++ }
++
++ clk_enable(adc_clock);
++
++ /* read platform data from device struct */
++ plat_data = s3c_adc_get_platdata(&pdev->dev);
++
++ if ((plat_data->presc&0xff) > 0)
++ writel(S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(plat_data->presc&0xFF), base_addr+S3C2410_ADCCON);
++ else
++ writel(0, base_addr+S3C2410_ADCCON);
++
++ /* Initialise registers */
++ if ((plat_data->delay&0xffff) > 0)
++ writel(plat_data->delay & 0xffff, base_addr+S3C2410_ADCDLY);
++
++ if (plat_data->resolution== 12) {
++ writel(readl(base_addr+S3C2410_ADCCON)|S3C6410_ADCCON_RESSEL_12BIT, base_addr+S3C2410_ADCCON);
++ }
++
++ ret = misc_register(&s3c_adc_miscdev);
++ if (ret) {
++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n",
++ ADC_MINOR, ret);
++ goto err_clk;
++ }
++
++ printk(KERN_INFO "S3C64XX ADC driver successfully probed !\n");
++
++ return 0;
++err_clk:
++ clk_disable(adc_clock);
++ clk_put(adc_clock);
++
++err_map:
++ iounmap(base_addr);
++
++err_req:
++ release_resource(adc_mem);
++ kfree(adc_mem);
++
++ return ret;
++}
++
++
++static int s3c_adc_remove(struct platform_device *dev)
++{
++ printk(KERN_INFO "s3c_adc_remove() of TS called !\n");
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static unsigned int adccon, adctsc, adcdly;
++
++static int s3c_adc_suspend(struct platform_device *dev, pm_message_t state)
++{
++ adccon = readl(base_addr+S3C2410_ADCCON);
++ adctsc = readl(base_addr+S3C2410_ADCTSC);
++ adcdly = readl(base_addr+S3C2410_ADCDLY);
++
++ clk_disable(adc_clock);
++
++ return 0;
++}
++
++static int s3c_adc_resume(struct platform_device *pdev)
++{
++ clk_enable(adc_clock);
++
++ writel(adccon, base_addr+S3C2410_ADCCON);
++ writel(adctsc, base_addr+S3C2410_ADCTSC);
++ writel(adcdly, base_addr+S3C2410_ADCDLY);
++
++ return 0;
++}
++#else
++#define s3c_adc_suspend NULL
++#define s3c_adc_resume NULL
++#endif
++
++static struct platform_driver s3c_adc_driver = {
++ .probe = s3c_adc_probe,
++ .remove = s3c_adc_remove,
++ .suspend = s3c_adc_suspend,
++ .resume = s3c_adc_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-adc",
++ },
++};
++
++static char banner[] __initdata = KERN_INFO "S3C64XX ADC driver, (c) 2007 Samsung Electronics\n";
++
++int __init s3c_adc_init(void)
++{
++ printk(banner);
++ return platform_driver_register(&s3c_adc_driver);
++}
++
++void __exit s3c_adc_exit(void)
++{
++ platform_driver_unregister(&s3c_adc_driver);
++}
++
++module_init(s3c_adc_init);
++module_exit(s3c_adc_exit);
++
++MODULE_AUTHOR("boyko.lee@samsung.com>");
++MODULE_DESCRIPTION("S3C64XX adc driver");
++MODULE_LICENSE("GPL");
+diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
+new file mode 100644
+index 0000000..a776437
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/clock.c
+@@ -0,0 +1,501 @@
++/* linux/arch/arm/plat-s3c64xx/clock.c
++ *
++ * Copyright (c) 2004-2005 Samsung Electronics
++ *
++ *
++ * S3C64XX Core clock control support
++ *
++ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
++ **
++ ** Copyright (C) 2004 ARM Limited.
++ ** Written by Deep Blue Solutions Limited.
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++//#include <asm/arch/regs-clock.h>
++#include <asm/arch/regs-gpio.h>
++
++#include <asm/plat-s3c64xx/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/arch-s3c2410/regs-s3c-clock.h>
++
++#define ARM_PLL_CON S3C_APLL_CON
++#define ARM_CLK_DIV S3C_CLK_DIV0
++
++#define ARM_DIV_RATIO_BIT 0
++#define ARM_DIV_MASK (0xf<<ARM_DIV_RATIO_BIT)
++#define HCLK_DIV_RATIO_BIT 9
++#define HCLK_DIV_MASK (0x7<<HCLK_DIV_RATIO_BIT)
++
++#define READ_ARM_DIV ((__raw_readl(ARM_CLK_DIV)&ARM_DIV_MASK) + 1)
++#define PLL_CALC_VAL(MDIV,PDIV,SDIV) ((1<<31)|(MDIV)<<16 |(PDIV)<<8 |(SDIV))
++#define GET_ARM_CLOCK(baseclk) s3c6400_get_pll(__raw_readl(S3C_APLL_CON),baseclk)
++
++#define MHZ 1000*1000
++#define INIT_XTAL 12 * MHZ
++
++/* enable and disable calls for use with the clk struct */
++static const u32 s3c_cpu_clock_table[][6] = {
++ {532*MHZ, 266, 3, 1, 0, 0},
++ {266*MHZ, 266, 3, 1, 0, 1},
++ {133*MHZ, 266, 3, 1, 0, 3},
++};
++
++/* clock information */
++
++static LIST_HEAD(clocks);
++
++DEFINE_MUTEX(clocks_mutex);
++
++/* enable and disable calls for use with the clk struct */
++
++static int clk_null_enable(struct clk *clk, int enable)
++{
++ return 0;
++}
++
++/* Clock API calls */
++
++struct clk *clk_get(struct device *dev, const char *id)
++{
++ struct clk *p;
++ struct clk *clk = ERR_PTR(-ENOENT);
++ int idno;
++
++ if (dev == NULL || dev->bus != &platform_bus_type)
++ idno = -1;
++ else
++ idno = to_platform_device(dev)->id;
++
++ mutex_lock(&clocks_mutex);
++
++ list_for_each_entry(p, &clocks, list) {
++ if (p->id == idno &&
++ strcmp(id, p->name) == 0 &&
++ try_module_get(p->owner)) {
++ clk = p;
++ break;
++ }
++ }
++
++ /* check for the case where a device was supplied, but the
++ * clock that was being searched for is not device specific */
++
++ if (IS_ERR(clk)) {
++ list_for_each_entry(p, &clocks, list) {
++ if (p->id == -1 && strcmp(id, p->name) == 0 &&
++ try_module_get(p->owner)) {
++ clk = p;
++ break;
++ }
++ }
++ }
++
++ mutex_unlock(&clocks_mutex);
++ return clk;
++}
++
++void clk_put(struct clk *clk)
++{
++ module_put(clk->owner);
++}
++
++int clk_enable(struct clk *clk)
++{
++ if (IS_ERR(clk) || clk == NULL)
++ return -EINVAL;
++
++ clk_enable(clk->parent);
++
++ mutex_lock(&clocks_mutex);
++
++ if ((clk->usage++) == 0)
++ (clk->enable)(clk, 1);
++
++ mutex_unlock(&clocks_mutex);
++ return 0;
++}
++
++void clk_disable(struct clk *clk)
++{
++ if (IS_ERR(clk) || clk == NULL)
++ return;
++
++ mutex_lock(&clocks_mutex);
++
++ if ((--clk->usage) == 0)
++ (clk->enable)(clk, 0);
++
++ mutex_unlock(&clocks_mutex);
++ clk_disable(clk->parent);
++}
++
++
++unsigned long clk_get_rate(struct clk *clk)
++{
++ if (IS_ERR(clk))
++ return 0;
++
++ if (clk->rate != 0)
++ return clk->rate;
++
++ if (clk->get_rate != NULL)
++ return (clk->get_rate)(clk);
++
++ if (clk->parent != NULL)
++ return clk_get_rate(clk->parent);
++
++ return clk->rate;
++}
++
++long clk_round_rate(struct clk *clk, unsigned long rate)
++{
++ if (!IS_ERR(clk) && clk->round_rate)
++ return (clk->round_rate)(clk, rate);
++
++ return rate;
++}
++
++int clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ int ret;
++
++ if (IS_ERR(clk))
++ return -EINVAL;
++
++ mutex_lock(&clocks_mutex);
++ ret = (clk->set_rate)(clk, rate);
++ mutex_unlock(&clocks_mutex);
++
++ return ret;
++}
++
++struct clk *clk_get_parent(struct clk *clk)
++{
++ return clk->parent;
++}
++
++int clk_set_parent(struct clk *clk, struct clk *parent)
++{
++ int ret = 0;
++
++ if (IS_ERR(clk))
++ return -EINVAL;
++
++ mutex_lock(&clocks_mutex);
++
++ if (clk->set_parent)
++ ret = (clk->set_parent)(clk, parent);
++
++ mutex_unlock(&clocks_mutex);
++
++ return ret;
++}
++
++EXPORT_SYMBOL(clk_get);
++EXPORT_SYMBOL(clk_put);
++EXPORT_SYMBOL(clk_enable);
++EXPORT_SYMBOL(clk_disable);
++EXPORT_SYMBOL(clk_get_rate);
++EXPORT_SYMBOL(clk_round_rate);
++EXPORT_SYMBOL(clk_set_rate);
++EXPORT_SYMBOL(clk_get_parent);
++EXPORT_SYMBOL(clk_set_parent);
++
++
++void inline s3c_clk_enable (uint clocks, uint enable, ulong gate_reg)
++{
++ unsigned long clkcon;
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ clkcon = __raw_readl(gate_reg);
++ clkcon &= ~clocks;
++
++ if (enable)
++ clkcon |= clocks;
++
++ __raw_writel(clkcon, gate_reg);
++
++ local_irq_restore(flags);
++}
++
++unsigned long s3c_fclk_get_rate(void)
++{
++ unsigned long apll_con;
++ unsigned long clk_div0_tmp;
++ unsigned long m = 0;
++ unsigned long p = 0;
++ unsigned long s = 0;
++ unsigned long ret;
++
++ apll_con = __raw_readl(S3C_APLL_CON);
++ clk_div0_tmp = __raw_readl(S3C_CLK_DIV0) & 0xf;
++
++ m = (apll_con >> 16) & 0x3ff;
++ p = (apll_con >> 8) & 0x3f;
++ s = apll_con & 0x3;
++
++ ret = (m * (INIT_XTAL / (p * (1 << s))));
++
++ return (ret / (clk_div0_tmp + 1));
++}
++
++unsigned long s3c_fclk_round_rate(struct clk *clk, unsigned long rate)
++{
++ u32 iter;
++
++ for(iter = 1 ; iter < ARRAY_SIZE(s3c_cpu_clock_table) ; iter++){
++ if(rate > s3c_cpu_clock_table[iter][0])
++ return s3c_cpu_clock_table[iter-1][0];
++ }
++
++ return s3c_cpu_clock_table[ARRAY_SIZE(s3c_cpu_clock_table) - 1][0];
++}
++
++int s3c_fclk_set_rate(struct clk *clk, unsigned long rate)
++{
++ u32 ret = -EINVAL;
++ u32 round_tmp;
++ u32 iter;
++ u32 apll_con_tmp;
++ u32 clk_div0_tmp;
++
++ round_tmp = s3c_fclk_round_rate(clk,rate);
++
++ if(round_tmp == (int)s3c_fclk_get_rate())
++ return 0;
++
++ for (iter = 0 ; iter < ARRAY_SIZE(s3c_cpu_clock_table) ; iter++){
++ if(round_tmp == s3c_cpu_clock_table[iter][0])
++ break;
++ }
++
++ clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
++ clk_div0_tmp |= s3c_cpu_clock_table[iter][5];
++
++ __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
++
++ if (__raw_readl(ARM_CLK_DIV) == clk_div0_tmp)
++ ret = 0;
++
++ clk->rate = s3c_cpu_clock_table[iter][0];
++
++ return ret;
++}
++
++/* base clocks */
++
++struct clk clk_xtal = {
++ .name = "xtal",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_mpll = {
++ .name = "mpll",
++ .id = -1,
++};
++
++
++struct clk clk_epll = {
++ .name = "epll",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++
++};
++
++struct clk clk_f = {
++ .name = "fclk",
++ .id = -1,
++ .rate = 0,
++ .parent = &clk_mpll,
++ .ctrlbit = 0,
++ .set_rate = s3c_fclk_set_rate,
++ .round_rate = s3c_fclk_round_rate,
++};
++
++struct clk clk_h = {
++ .name = "hclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_p = {
++ .name = "pclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++
++struct clk clk_hx2 = {
++ .name = "hclkx2",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_s = {
++ .name = "sclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_u = {
++ .name = "uclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_48m = {
++ .name = "clk48m",
++ .id = -1,
++ .rate = 48*1000*1000,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_27m = {
++ .name = "clk27m",
++ .id = -1,
++ .rate = 27*1000*1000,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++
++
++/* initialise the clock system */
++
++int s3c64xx_register_clock(struct clk *clk)
++{
++ clk->owner = THIS_MODULE;
++
++ if (clk->enable == NULL)
++ clk->enable = clk_null_enable;
++
++ /* add to the list of available clocks */
++
++ mutex_lock(&clocks_mutex);
++ list_add(&clk->list, &clocks);
++ mutex_unlock(&clocks_mutex);
++
++ return 0;
++}
++
++int s3c64xx_register_clocks(struct clk **clks, int nr_clks)
++{
++ int fails = 0;
++
++ for (; nr_clks > 0; nr_clks--, clks++) {
++ if (s3c64xx_register_clock(*clks) < 0)
++ fails++;
++ }
++
++ return fails;
++}
++
++/* initalise all the clocks */
++
++int __init s3c64xx_setup_clocks(unsigned long xtal,
++ unsigned long fclk,
++ unsigned long hclk,
++ unsigned long pclk)
++{
++ printk(KERN_INFO "S3C64XX Clocks, (c) 2007 Samssung Electronics\n");
++
++ /* initialise the main system clocks */
++
++ clk_xtal.rate = xtal;
++ clk_mpll.rate = fclk;
++ clk_h.rate = hclk;
++ clk_p.rate = pclk;
++ clk_f.rate = fclk;
++
++ /* assume uart clocks are correctly setup */
++
++ /* register our clocks */
++
++ if (s3c64xx_register_clock(&clk_xtal) < 0)
++ printk(KERN_ERR "failed to register master xtal\n");
++
++ if (s3c64xx_register_clock(&clk_mpll) < 0)
++ printk(KERN_ERR "failed to register mpll clock\n");
++
++ if (s3c64xx_register_clock(&clk_f) < 0)
++ printk(KERN_ERR "failed to register cpu fclk\n");
++
++ if (s3c64xx_register_clock(&clk_h) < 0)
++ printk(KERN_ERR "failed to register cpu hclk\n");
++
++ if (s3c64xx_register_clock(&clk_p) < 0)
++ printk(KERN_ERR "failed to register cpu pclk\n");
++
++ if (s3c64xx_register_clock(&clk_epll) < 0)
++ printk(KERN_ERR "failed to register epll clock\n");
++
++ /* register hclkx2 */
++ if (s3c64xx_register_clock(&clk_hx2) < 0)
++ printk(KERN_ERR "failed to register cpu hclkx2\n");
++
++ if (s3c64xx_register_clock(&clk_s) < 0)
++ printk(KERN_ERR "failed to register cpu pclk\n");
++
++ if (s3c64xx_register_clock(&clk_u) < 0)
++ printk(KERN_ERR "failed to register cpu uclk\n");
++
++ if (s3c64xx_register_clock(&clk_48m) < 0)
++ printk(KERN_ERR "failed to register cpu uclk\n");
++
++ if (s3c64xx_register_clock(&clk_27m) < 0)
++ printk(KERN_ERR "failed to register cpu uclk\n");
++
++ return 0;
++}
++
+diff --git a/arch/arm/plat-s3c64xx/dma-pl080.c b/arch/arm/plat-s3c64xx/dma-pl080.c
+new file mode 100644
+index 0000000..a71a3ad
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/dma-pl080.c
+@@ -0,0 +1,1672 @@
++/* linux/arch/arm/plat-s3c24xx/dma-pl080.c
++ *
++ * Copyright (c) 2003-2005,2006 Samsung Electronics
++ *
++ * S3C6400 DMA core
++ *
++ * http://www.samsung.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#ifdef CONFIG_S3C_DMA_DEBUG
++#define DEBUG
++#endif
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/sysdev.h>
++#include <linux/slab.h>
++#include <linux/errno.h>
++#include <linux/delay.h>
++
++#include <asm/system.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/mach/dma.h>
++#include <asm/arch/map.h>
++#include <asm/plat-s3c24xx/dma.h>
++
++
++/* io map for dma */
++static void __iomem *dma_base;
++static struct kmem_cache *dma_kmem;
++
++static int dma_channels;
++struct s3c24xx_dma_selection dma_sel;
++static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
++
++/* dma channel state information */
++struct s3c2410_dma_chan s3c_dma_chans[S3C2410_DMA_CHANNELS];
++s3c_dma_controller_t s3c_dma_cntlrs[S3C_DMA_CONTROLLERS];
++
++#undef pr_debug
++//#define dma_dbg
++
++#ifdef dma_dbg
++#define sh_printk(fmt...) printk( fmt)
++#define pr_debug(fmt...) printk( fmt)
++#else
++#define sh_printk(fmt...)
++#define pr_debug(fmt...)
++#endif
++
++/* debugging functions */
++
++#define BUF_MAGIC (0xcafebabe)
++
++#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
++
++#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
++#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
++#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
++
++#define dbg_showregs(chan) do { } while(0)
++#define dbg_showchan(chan) do { } while(0)
++
++void s3c_dma_dump(int dcon_num, int channel)
++{
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_STATUS);
++ printk("%d dcon_num %d subchnnel INT_STATUS %lx\n", dcon_num, channel, tmp);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS);
++ printk("%d dcon_num %d subchnnel INT_TCSTATUS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_ENBLD_CHANNELS);
++ printk("%d dcon_num %d subchnnel ENBLD_CHANNELS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
++ printk("%d dcon_num %d subchnnel DMAC_CONFIGUARATION %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CSRCADDR(channel));
++ printk("%d dcon_num %d subchnnel SRCADDRESS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CDESTADDR(channel));
++ printk("%d dcon_num %d subchnnel DESTADDRESS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CLLI(channel));
++ printk("%d dcon_num %d subchnnel LLI %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel));
++ printk("%d dcon_num %d subchnnel CCONTROL0 %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL1(channel));
++ printk("%d dcon_num %d subchnnel CCONTROL1 %lx\n", dcon_num, channel, tmp);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel));
++
++ printk("%d dcon_num %d subchnnel CH CONFIGUARATION %lx\n", dcon_num, channel, tmp);
++}
++
++
++/* lookup_dma_channel
++ *
++ * change the dma channel number given into a real dma channel id
++*/
++
++static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
++{
++ if (channel & DMACH_LOW_LEVEL)
++ return &s3c_dma_chans[channel & ~DMACH_LOW_LEVEL];
++ else
++ return dma_chan_map[channel];
++}
++
++/* s3c_dma_stats_timeout
++ *
++ * Update DMA stats from timeout info
++ */
++static void s3c_dma_stats_timeout(struct s3c2410_dma_stats * stats, int val)
++{
++ if (stats == NULL)
++ return;
++
++ if (val > stats->timeout_longest)
++ stats->timeout_longest = val;
++ if (val < stats->timeout_shortest)
++ stats->timeout_shortest = val;
++
++ stats->timeout_avg += val;
++}
++
++void s3c_enable_dmac(unsigned int dcon_num)
++{
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE);
++}
++
++void s3c_disable_dmac(unsigned int dcon_num)
++{
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
++ tmp &= ~S3C_DMA_CONTROLLER_ENABLE;
++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, tmp);
++}
++
++void s3c_clear_interrupts (int dcon_num, int channel)
++{
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCCLEAR);
++ tmp |= (1 << channel);
++ dma_wrreg(dma_controller, S3C_DMAC_INT_TCCLEAR, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR);
++ tmp |= (1 << channel);
++ dma_wrreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR, tmp);
++}
++
++/* s3c_dma_waitforload
++ *
++ * wait for the DMA engine to load a buffer, and update the state accordingly
++ */
++static int s3c_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
++{
++ int timeout = chan->load_timeout;
++ int took;
++
++ pr_debug("%s channel number : %d\n", __FUNCTION__, chan->number);
++
++ if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
++ printk(KERN_ERR
++ "dma%d: s3c_dma_waitforload() called in loadstate %d from line %d\n",
++ chan->number, chan->load_state, line);
++ return 0;
++ }
++
++ if (chan->stats != NULL)
++ chan->stats->loads++;
++
++ while (--timeout > 0) {
++ if ((dma_rdreg(chan->dma_con, S3C_DMAC_ENBLD_CHANNELS)) & (0x1 << chan->number)) {
++ took = chan->load_timeout - timeout;
++ s3c_dma_stats_timeout(chan->stats, took);
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_1LOADED:
++ chan->load_state = S3C2410_DMALOAD_1RUNNING;
++ break;
++
++ default:
++ printk(KERN_ERR
++ "dma%d: unknown load_state in s3c_dma_waitforload() %d\n",
++ chan->number, chan->load_state);
++ }
++
++ return 1;
++ }
++ }
++
++ if (chan->stats != NULL) {
++ chan->stats->timeout_failed++;
++ }
++
++ return 0;
++}
++
++
++/* s3c_dma_loadbuffer
++ *
++ * load a buffer, and update the channel state
++ */
++static inline int s3c_dma_loadbuffer(struct s3c2410_dma_chan *chan,
++ struct s3c2410_dma_buf *buf)
++{
++ unsigned long reload;
++
++ pr_debug("s3c_chan_loadbuffer: loading buffer %p (0x%08lx,0x%06x)\n",
++ buf, (unsigned long) buf->data, buf->size);
++
++ if (buf == NULL) {
++ dmawarn("buffer is NULL\n");
++ return -EINVAL;
++ }
++
++ /* check the state of the channel before we do anything */
++
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
++ dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
++ reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
++ }
++
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
++ dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
++ reload = S3C2410_DCON_AUTORELOAD;
++ }
++
++ writel(buf->data, chan->addr_reg);
++
++ pr_debug("%s: DMA control0 - %08x\n", __FUNCTION__, chan->dcon);
++ pr_debug("%s: DMA control1 - %08x\n", __FUNCTION__, (buf->size / chan->xfer_unit));
++
++ dma_wrreg(chan, S3C_DMAC_CxCONTROL0, chan->dcon);
++ dma_wrreg(chan, S3C_DMAC_CxCONTROL1, (buf->size / chan->xfer_unit));
++
++ chan->next = buf->next;
++
++ /* update the state of the channel */
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_NONE:
++ chan->load_state = S3C2410_DMALOAD_1LOADED;
++ break;
++
++ case S3C2410_DMALOAD_1RUNNING:
++ chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
++ break;
++
++ default:
++ dmawarn("dmaload: unknown state %d in loadbuffer\n", chan->load_state);
++ break;
++ }
++
++ return 0;
++}
++
++
++/* s3c_dma_call_op
++ *
++ * small routine to call the o routine with the given op if it has been
++ * registered
++ */
++static void s3c_dma_call_op(struct s3c2410_dma_chan * chan, enum s3c2410_chan_op op)
++{
++ if (chan->op_fn != NULL) {
++ (chan->op_fn) (chan, op);
++ }
++}
++
++/* s3c_dma_buffdone
++ *
++ * small wrapper to check if callback routine needs to be called, and
++ * if so, call it
++ */
++static inline void s3c_dma_buffdone(struct s3c2410_dma_chan * chan,
++ struct s3c2410_dma_buf * buf,
++ enum s3c2410_dma_buffresult result)
++{
++ pr_debug("callback_fn will be called=%p, buf=%p, id=%p, size=%d, result=%d\n",
++ chan->callback_fn, buf, buf->id, buf->size, result);
++
++ if (chan->callback_fn != NULL) {
++ (chan->callback_fn) (chan, buf->id, buf->size, result);
++ }
++}
++
++/* s3c_dma_start
++ *
++ * start a dma channel going
++ */
++static int s3c_dma_start(struct s3c2410_dma_chan *chan)
++{
++ unsigned long flags;
++
++ pr_debug("s3c_start_dma: channel number=%d, index=%d\n", chan->number, chan->index);
++
++ local_irq_save(flags);
++
++ if (chan->state == S3C2410_DMA_RUNNING) {
++ pr_debug("s3c_start_dma: already running (%d)\n", chan->state);
++ local_irq_restore(flags);
++ return 0;
++ }
++
++ chan->state = S3C2410_DMA_RUNNING;
++
++ /* check wether there is anything to load, and if not, see
++ * if we can find anything to load
++ */
++
++ if (chan->load_state == S3C2410_DMALOAD_NONE) {
++ if (chan->next == NULL) {
++ printk(KERN_ERR "dma%d: dcon_num has nothing loaded\n", chan->number);
++ chan->state = S3C2410_DMA_IDLE;
++ local_irq_restore(flags);
++ return -EINVAL;
++ }
++
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++
++ dbg_showchan(chan);
++
++ /* enable the channel */
++
++ if (!chan->irq_enabled) {
++ enable_irq(chan->irq);
++ chan->irq_enabled = 1;
++ }
++
++ /* Get the DMA channel started ...*/
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags);
++
++ pr_debug("%s:wrote %08lx to S3C_DMAC_CxCONFIGURATION.\n",__FUNCTION__, chan->config_flags);
++
++ /* Start the DMA operation on Peripheral */
++ s3c_dma_call_op(chan, S3C2410_DMAOP_START);
++
++ dbg_showchan(chan);
++
++ /* if we've only loaded one buffer onto the channel, then chec
++ * to see if we have another, and if so, try and load it so when
++ * the first buffer is finished, the new one will be loaded onto
++ * the channel */
++#if 0
++ if (chan->next != NULL) {
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
++
++ if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
++ pr_debug("%s: buff not yet loaded, no more todo\n",
++ __FUNCTION__);
++ } else {
++ chan->load_state = S3C2410_DMALOAD_1RUNNING;
++ s3c2410_dma_loadbuffer(chan, chan->next);
++ }
++
++ } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
++ s3c2410_dma_loadbuffer(chan, chan->next);
++ }
++ }
++#endif
++ local_irq_restore(flags);
++ return 0;
++}
++
++
++/* s3c_dma_canload
++ *
++ * work out if we can queue another buffer into the DMA engine
++ */
++
++#if 0
++static int s3c_dma_canload(struct s3c2410_dma_chan * chan)
++{
++ if (chan->load_state == S3C2410_DMALOAD_NONE || chan->load_state == S3C2410_DMALOAD_1RUNNING)
++ return 1;
++
++ return 0;
++}
++#endif
++
++
++/* s3c2410_dma_enqueue
++ *
++ * queue an given buffer for dma transfer.
++ *
++ * id the device driver's id information for this buffer
++ * data the physical address of the buffer data
++ * size the size of the buffer in bytes
++ *
++ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
++ * is checked, and if set, the channel is started. If this flag isn't set,
++ * then an error will be returned.
++ *
++ * It is possible to queue more than one DMA buffer onto a channel at
++ * once, and the code will deal with the re-loading of the next buffer
++ * when necessary.
++ */
++int s3c2410_dma_enqueue(unsigned int channel, void *id,
++ dma_addr_t data, int size)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++ struct s3c2410_dma_buf *buf;
++ unsigned long flags;
++
++ pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int) data, size);
++
++ buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
++ if (buf == NULL) {
++ printk(KERN_ERR "dma<%d> no memory for buffer\n", channel);
++ return -ENOMEM;
++ }
++
++ pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
++
++ //dbg_showchan(chan);
++
++ buf->next = NULL;
++ buf->data = buf->ptr = data;
++ buf->size = size;
++ buf->id = id;
++ buf->magic = BUF_MAGIC;
++
++ local_irq_save(flags);
++
++ if (chan->curr == NULL) {
++ /* we've got nothing loaded... */
++ pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf);
++
++ chan->curr = buf;
++ chan->end = buf;
++ chan->next = NULL;
++ } else {
++ pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
++ chan->number, __FUNCTION__, buf);
++
++ if (chan->end == NULL) /* In case of flushing */
++ pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
++ chan->number, __FUNCTION__, chan);
++ else {
++ chan->end->next = buf;
++ chan->end = buf;
++ }
++ }
++
++ /* if necessary, update the next buffer field */
++ if (chan->next == NULL)
++ chan->next = buf;
++
++ /* check to see if we can load a buffer */
++ if (chan->state == S3C2410_DMA_RUNNING) {
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ printk(KERN_ERR "dma%d: loadbuffer:"
++ "timeout loading buffer\n", chan->number);
++ dbg_showchan(chan);
++ local_irq_restore(flags);
++ return -EINVAL;
++ }
++ }
++#if 0
++ while (s3c_dma_canload(chan) && chan->next != NULL) {
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++#endif
++ } else if (chan->state == S3C2410_DMA_IDLE) {
++ if (chan->flags & S3C2410_DMAF_AUTOSTART) {
++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START);
++ } else {
++ pr_debug("loading onto stopped channel\n");
++ }
++ }
++
++ local_irq_restore(flags);
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_enqueue);
++
++/* s3c2410_dma_enqueue_sg
++ *
++ * queue an given buffer for dma transfer.
++ *
++ * id the device driver's id information for this buffer
++ * data the physical address of the buffer data
++ * size the size of the buffer in bytes
++ * sg_reg the scatter&gather list
++ *
++ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
++ * is checked, and if set, the channel is started. If this flag isn't set,
++ * then an error will be returned.
++ *
++ * It is possible to queue more than one DMA buffer onto a channel at
++ * once, and the code will deal with the re-loading of the next buffer
++ * when necessary.
++ */
++int s3c2410_dma_enqueue_sg(unsigned int channel, void *id,
++ dma_addr_t data, int size, struct s3c_pl080_sg_list *sg_list)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++ struct s3c2410_dma_buf *buf;
++ unsigned long flags;
++
++ pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int) data, size);
++
++ buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
++ if (buf == NULL) {
++ printk(KERN_ERR "dma<%d> no memory for buffer\n", channel);
++ return -ENOMEM;
++ }
++
++ pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
++
++ //dbg_showchan(chan);
++
++ buf->next = NULL;
++ buf->data = buf->ptr = data;
++ buf->size = size;
++ buf->id = id;
++ buf->magic = BUF_MAGIC;
++
++ local_irq_save(flags);
++
++ if (chan->curr == NULL) {
++ /* we've got nothing loaded... */
++ pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf);
++
++ chan->curr = buf;
++ chan->end = buf;
++ chan->next = NULL;
++ } else {
++ pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
++ chan->number, __FUNCTION__, buf);
++
++ if (chan->end == NULL) /* In case of flushing */
++ pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
++ chan->number, __FUNCTION__, chan);
++ else {
++ chan->end->next = buf;
++ chan->end = buf;
++ }
++ }
++
++ /* if necessary, update the next buffer field */
++ if (chan->next == NULL)
++ chan->next = buf;
++
++ /* check to see if we can load a buffer */
++ if (chan->state == S3C2410_DMA_RUNNING) {
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ printk(KERN_ERR "dma%d: loadbuffer:"
++ "timeout loading buffer\n", chan->number);
++ dbg_showchan(chan);
++ local_irq_restore(flags);
++ return -EINVAL;
++ }
++ }
++#if 0
++ while (s3c_dma_canload(chan) && chan->next != NULL) {
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++#endif
++ } else if (chan->state == S3C2410_DMA_IDLE) {
++ dma_wrreg(chan, S3C_DMAC_CxLLI, virt_to_phys(&sg_list));
++
++ if (chan->flags & S3C2410_DMAF_AUTOSTART) {
++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START);
++ } else {
++ pr_debug("loading onto stopped channel\n");
++ }
++ }
++
++ local_irq_restore(flags);
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_enqueue_sg);
++
++
++static inline void s3c_dma_freebuf(struct s3c2410_dma_buf * buf)
++{
++ int magicok = (buf->magic == BUF_MAGIC);
++
++ buf->magic = -1;
++
++ if (magicok) {
++ kmem_cache_free(dma_kmem, buf);
++ } else {
++ printk("s3c_dma_freebuf: buff %p with bad magic\n", buf);
++ }
++}
++
++/* s3c_dma_lastxfer
++ *
++ * called when the system is out of buffers, to ensure that the channel
++ * is prepared for shutdown.
++ */
++static inline void s3c_dma_lastxfer(struct s3c2410_dma_chan *chan)
++{
++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state %d\n", chan->number, chan->load_state);
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_NONE:
++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state : S3C2410_DMALOAD_NONE%d\n", chan->number);
++ break;
++
++ case S3C2410_DMALOAD_1LOADED:
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ /* flag error? */
++ printk(KERN_ERR "dma%d: timeout waiting for load\n", chan->number);
++ return;
++ }
++ break;
++
++ default:
++ pr_debug("dma%d: lastxfer: unhandled load_state %d with no next",
++ chan->number, chan->load_state);
++ return;
++
++ }
++
++}
++
++
++#define dmadbg2(x...)
++
++static irqreturn_t s3c_dma_irq(int irq, void *devpw)
++{
++ unsigned int channel = 0, dcon_num, i;
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = (s3c_dma_controller_t *) devpw;
++
++ struct s3c2410_dma_chan *chan=NULL;
++ struct s3c2410_dma_buf *buf;
++
++ dcon_num = dma_controller->number;
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS);
++ pr_debug("# s3c_dma_irq: TC status : 0x%x\n", tmp);
++
++ if(tmp==0) {
++ return IRQ_HANDLED;
++ }
++
++ for (i = 0; i < S3C_CHANNELS_PER_DMA; i++) {
++ if (tmp & 0x01) {
++
++ pr_debug("# DMA Controller %d: requestor %d\n", dcon_num, i);
++
++ channel = i;
++ chan = &s3c_dma_chans[channel + dcon_num * S3C_CHANNELS_PER_DMA];
++ pr_debug("# DMA channel number : %d, index : %d\n", chan->number, chan->index);
++
++ buf = chan->curr;
++
++ dbg_showchan(chan);
++
++ /* modify the channel state */
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_1RUNNING:
++ /* TODO - if we are running only one buffer, we probably
++ * want to reload here, and then worry about the buffer
++ * callback */
++
++ chan->load_state = S3C2410_DMALOAD_NONE;
++ break;
++
++ case S3C2410_DMALOAD_1LOADED:
++ /* iirc, we should go back to NONE loaded here, we
++ * had a buffer, and it was never verified as being
++ * loaded.
++ */
++
++ chan->load_state = S3C2410_DMALOAD_NONE;
++ break;
++
++ case S3C2410_DMALOAD_1LOADED_1RUNNING:
++ /* we'll worry about checking to see if another buffer is
++ * ready after we've called back the owner. This should
++ * ensure we do not wait around too long for the DMA
++ * engine to start the next transfer
++ */
++
++ chan->load_state = S3C2410_DMALOAD_1LOADED;
++ break;
++
++ case S3C2410_DMALOAD_NONE:
++ printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
++ chan->number);
++ break;
++
++ default:
++ printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
++ chan->number, chan->load_state);
++ break;
++ }
++
++ if (buf != NULL) {
++ /* update the chain to make sure that if we load any more
++ * buffers when we call the callback function, things should
++ * work properly */
++
++ chan->curr = buf->next;
++ buf->next = NULL;
++
++ if (buf->magic != BUF_MAGIC) {
++ printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
++ chan->number, __FUNCTION__, buf);
++ goto next_channel;
++ }
++
++ s3c_dma_buffdone(chan, buf, S3C2410_RES_OK);
++
++ /* free resouces */
++ s3c_dma_freebuf(buf);
++ } else {
++
++ }
++
++ if (chan->next != NULL) {
++ unsigned long flags;
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_1RUNNING:
++ /* don't need to do anything for this state */
++ break;
++
++ case S3C2410_DMALOAD_NONE:
++ /* can load buffer immediately */
++ break;
++
++ case S3C2410_DMALOAD_1LOADED:
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ /* flag error? */
++ printk(KERN_ERR "dma%d: timeout waiting for load\n",
++ chan->number);
++ goto next_channel;
++ }
++
++ break;
++
++ case S3C2410_DMALOAD_1LOADED_1RUNNING:
++ goto next_channel;
++
++ default:
++ printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
++ chan->number, chan->load_state);
++ goto next_channel;
++ }
++
++ local_irq_save(flags);
++ s3c_dma_loadbuffer(chan, chan->next);
++
++ //shaju added for dbg
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags);
++
++ local_irq_restore(flags);
++
++ } else {
++ s3c_dma_lastxfer(chan);
++
++ /* see if we can stop this channel.. */
++ if (chan->load_state == S3C2410_DMALOAD_NONE) {
++ pr_debug("# DMA CH %d(index:%d): end of transfer, stopping channel (%ld)\n",
++ chan->number, chan->index, jiffies);
++ s3c2410_dma_ctrl(chan->index | DMACH_LOW_LEVEL, S3C2410_DMAOP_STOP);
++ }
++ }
++ }
++
++next_channel:
++ tmp >>= 1;
++
++ }
++
++ s3c_clear_interrupts(chan->dma_con->number, chan->number);
++
++ return IRQ_HANDLED;
++}
++
++static struct s3c2410_dma_chan *s3c_dma_map_channel(int channel);
++
++/* s3c_request_dma
++ *
++ * get control of an dma channel
++*/
++
++int s3c2410_dma_request(unsigned int channel,
++ struct s3c2410_dma_client *client,
++ void *dev)
++{
++ struct s3c2410_dma_chan *chan;
++ unsigned long flags;
++ int err;
++
++ pr_debug("DMA CH %d: s3c2410_request_dma: client=%s, dev=%p\n",
++ channel, client->name, dev);
++
++ local_irq_save(flags);
++
++ chan = s3c_dma_map_channel(channel);
++ if (chan == NULL) {
++ local_irq_restore(flags);
++ return -EBUSY;
++ }
++
++ dbg_showchan(chan);
++
++ chan->client = client;
++ chan->in_use = 1;
++
++ chan->dma_con->in_use++;
++
++ if (!chan->irq_claimed) {
++ pr_debug("DMA CH %d: %s : requesting irq %d\n",
++ channel, __FUNCTION__, chan->irq);
++
++ chan->irq_claimed = 1;
++ local_irq_restore(flags);
++
++ err = request_irq(chan->irq, s3c_dma_irq, IRQF_DISABLED|IRQF_SHARED,
++ client->name, (void *) chan->dma_con);
++
++ local_irq_save(flags);
++
++ if (err) {
++ chan->in_use = 0;
++ chan->irq_claimed = 0;
++ chan->dma_con->in_use--;
++ local_irq_restore(flags);
++
++ printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
++ client->name, chan->irq, chan->number);
++ return err;
++ }
++
++ chan->irq_enabled = 1;
++
++ /* enable the main dma.. this can be disabled
++ * when main channel use count is 0 */
++ s3c_enable_dmac(chan->dma_con->number);
++ }
++
++ s3c_clear_interrupts(chan->dma_con->number, chan->number);
++ local_irq_restore(flags);
++
++ /* need to setup */
++
++ pr_debug("%s: channel initialised, %p, number:%d, index:%d\n", __FUNCTION__, chan, chan->number, chan->index);
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_request);
++
++/* s3c_dma_free
++ *
++ * release the given channel back to the system, will stop and flush
++ * any outstanding transfers, and ensure the channel is ready for the
++ * next claimant.
++ *
++ * Note, although a warning is currently printed if the freeing client
++ * info is not the same as the registrant's client info, the free is still
++ * allowed to go through.
++ */
++int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
++{
++ unsigned long flags;
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++ pr_debug("%s: DMA channel %d will be stopped\n", __FUNCTION__, chan->number);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ local_irq_save(flags);
++
++ if (chan->client != client) {
++ printk(KERN_WARNING
++ "DMA CH %d: possible free from different client (channel %p, passed %p)\n",
++ channel, chan->client, client);
++ }
++
++ /* sort out stopping and freeing the channel */
++
++ if (chan->state != S3C2410_DMA_IDLE) {
++ pr_debug("%s: need to stop dma channel %p\n", __FUNCTION__, chan);
++
++ /* possibly flush the channel */
++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
++ }
++
++ chan->client = NULL;
++ chan->in_use = 0;
++
++ chan->dma_con->in_use--;
++
++ if (chan->irq_claimed)
++ free_irq(chan->irq, (void *)chan->dma_con);
++
++ chan->irq_claimed = 0;
++
++ if (!(channel & DMACH_LOW_LEVEL))
++ dma_chan_map[channel] = NULL;
++
++ local_irq_restore(flags);
++
++ pr_debug("--------------------------------------------\n");
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_free);
++
++/*actively polling for the A bit can block the cpu*/
++void s3c_dma_flush_fifo(struct s3c2410_dma_chan *chan)
++{
++ unsigned long tmp;
++
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++ tmp |= S3C_DMACONFIG_HALT;
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp);
++
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++
++ /*this while loop can be very dangerous..may be put the process to sleep rather than waiting till fifo is drained */
++ while (tmp & S3C_DMACONFIG_ACTIVE) {
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++ }
++}
++
++static int s3c_dma_dostop(struct s3c2410_dma_chan *chan)
++{
++ unsigned long tmp;
++ unsigned long flags;
++
++ pr_debug("%s: DMA Channel No : %d\n", __FUNCTION__, chan->number);
++
++ dbg_showchan(chan);
++
++ local_irq_save(flags);
++
++ s3c_dma_flush_fifo(chan);
++
++ s3c_dma_call_op(chan, S3C2410_DMAOP_STOP);
++
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++
++ tmp &= ~S3C_DMACONFIG_CHANNEL_ENABLE;
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp);
++
++ pr_debug("%s: S3C_DMAC_CxCONFIGURATION : %08x\n", __FUNCTION__, tmp);
++
++ chan->state = S3C2410_DMA_IDLE;
++ chan->load_state = S3C2410_DMALOAD_NONE;
++
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++static void s3c_dma_showchan(struct s3c2410_dma_chan * chan)
++{
++#if 0
++ printk(KERN_DEBUG "dma[%d]: st %d, lst %d, cli %p, dcon %08lx\n",
++ chan->number, chan->state, chan->load_state, chan->client, chan->dcon);
++ printk(KERN_DEBUG "dma[%d]: CSRC=%x, ISRC=%x, STAT=%x, CON=%x, MT=%x\n",
++ chan->number,
++#endif
++}
++
++/* s3c_dma_flush
++ *
++ * stop the channel, and remove all current and pending transfers
++ */
++
++void s3c_waitforstop(struct s3c2410_dma_chan *chan)
++{
++ #if 0
++ unsigned long tmp;
++ unsigned int timeout = 0x10000;
++
++ while (timeout-- > 0) {
++ tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
++
++ if (!(tmp & S3C2410_DMASKTRIG_ON))
++ return;
++ }
++
++ pr_debug("dma%d: failed to stop?\n", chan->number);
++ #endif
++}
++
++static int s3c_dma_flush(struct s3c2410_dma_chan *chan)
++{
++ struct s3c2410_dma_buf *buf, *next;
++ unsigned long flags;
++
++ pr_debug("%s:\n", __FUNCTION__);
++
++ local_irq_save(flags);
++
++ s3c_dma_showchan(chan);
++
++ if (chan->state != S3C2410_DMA_IDLE) {
++ pr_debug("%s: stopping channel...\n", __FUNCTION__);
++ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
++ }
++
++ buf = chan->curr;
++ if (buf == NULL)
++ buf = chan->next;
++
++ chan->curr = chan->next = chan->end = NULL;
++ chan->load_state = S3C2410_DMALOAD_NONE;
++
++ if (buf != NULL) {
++ for (; buf != NULL; buf = next) {
++ next = buf->next;
++
++ pr_debug("%s: free buffer %p, next %p\n", __FUNCTION__, buf, buf->next);
++
++ s3c_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
++ s3c_dma_freebuf(buf);
++ }
++ }
++ //s3c_dma_waitforstop(chan);
++
++ s3c_dma_showchan(chan);
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++int s3c_dma_started(struct s3c2410_dma_chan *chan)
++{
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ dbg_showchan(chan);
++
++ /* if we've only loaded one buffer onto the channel, then chec
++ * to see if we have another, and if so, try and load it so when
++ * the first buffer is finished, the new one will be loaded onto
++ * the channel */
++
++ if (chan->next != NULL) {
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
++
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ pr_debug("%s: buff not yet loaded, no more todo\n",
++ __FUNCTION__);
++ } else {
++ chan->load_state = S3C2410_DMALOAD_1RUNNING;
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++
++ } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++ }
++
++ local_irq_restore(flags);
++
++ return 0;
++
++}
++
++int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ switch (op) {
++ case S3C2410_DMAOP_START:
++ return s3c_dma_start(chan);
++
++ case S3C2410_DMAOP_STOP:
++ return s3c_dma_dostop(chan);
++
++ case S3C2410_DMAOP_PAUSE:
++ case S3C2410_DMAOP_RESUME:
++ return -ENOENT;
++
++ case S3C2410_DMAOP_FLUSH:
++ return s3c_dma_flush(chan);
++
++ case S3C2410_DMAOP_STARTED:
++ return s3c_dma_started(chan);
++
++ case S3C2410_DMAOP_TIMEOUT:
++ return 0;
++
++ }
++
++ return -ENOENT; /* unknown, don't bother */
++}
++EXPORT_SYMBOL(s3c2410_dma_ctrl);
++
++
++/* s3c_dma_config
++ *
++ * xfersize: size of unit in bytes (1,2,4)
++ * dcon: base value of the DCONx register
++ */
++int s3c2410_dma_config(dmach_t channel,
++ int xferunit,
++ int dcon)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
++ __FUNCTION__, channel, xferunit, dcon);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
++
++ dcon |= chan->dcon & dma_sel.dcon_mask;
++
++ pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
++
++ switch (xferunit) {
++ case 1:
++ dcon |= S3C_DMACONTROL_SRC_WIDTH_BYTE;
++ dcon |= S3C_DMACONTROL_DEST_WIDTH_BYTE;
++ break;
++
++ case 2:
++ dcon |= S3C_DMACONTROL_SRC_WIDTH_HWORD;
++ dcon |= S3C_DMACONTROL_DEST_WIDTH_HWORD;
++ break;
++
++ case 4:
++ dcon |= S3C_DMACONTROL_SRC_WIDTH_WORD;
++ dcon |= S3C_DMACONTROL_DEST_WIDTH_WORD;
++ break;
++
++ default:
++ pr_debug("%s: Bad transfer size %d\n", __FUNCTION__, xferunit);
++ return -EINVAL;
++ }
++
++ pr_debug("%s: DMA Channel control : %08x\n", __FUNCTION__, dcon);
++
++ dcon |= S3C_DMACONTROL_TC_INT_ENABLE;
++ dcon |= chan->control_flags;
++ pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
++
++ /* For DMCCxControl 0 */
++ chan->dcon = dcon;
++
++ /* For DMACCxControl 1 : xferunit means transfer width.*/
++ chan->xfer_unit = xferunit;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_config);
++
++
++int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
++
++ chan->flags = flags;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_setflags);
++
++
++/* do we need to protect the settings of the fields from
++ * irq?
++ */
++
++int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
++
++ chan->op_fn = rtn;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_set_opfn);
++
++
++int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
++
++ chan->callback_fn = rtn;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
++
++
++/* s3c2410_dma_devconfig
++ *
++ * configure the dma source/destination hardware type and address
++ *
++ * flowctrl: direction of dma flow
++ *
++ * src_per dst_per: dma channel number of src and dst periphreal,
++ *
++ * devaddr: physical address of the source
++ */
++
++int s3c2410_dma_devconfig(int channel,
++ enum s3c2410_dmasrc source,
++ int hwcfg,
++ unsigned long devaddr)
++{
++ unsigned long tmp;
++
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
++ __FUNCTION__, (int)source, hwcfg, devaddr);
++
++ chan->source = source;
++ chan->dev_addr = devaddr;
++
++ switch (source) {
++ case S3C2410_DMASRC_MEM:
++ /* source is Memory : Mem-to-Peri ( Write into FIFO) */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2PER | (chan->map->hw_addr.to) <<
++ S3C_DEST_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ chan->config_flags = tmp;
++
++ /* TODO : Now, Scatter&Gather DMA NOT supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : Periperal address (destination) */
++ dma_wrreg(chan, S3C_DMAC_CxDESTADDR, devaddr);
++
++ /* source address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxSRCADDR);
++
++ chan->control_flags = S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI ;
++ //chan->control_flags = hwcfg;
++ return 0;
++
++ case S3C2410_DMASRC_HW:
++ /* source is peripheral : Peri-to-Mem ( Read from FIFO) */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_PER2MEM | (chan->map->hw_addr.from) <<
++ S3C_SRC_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ chan->config_flags = tmp;
++
++ /* TODO : Now, Scatter&Gather DMA NOT supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : Periperal address (source) */
++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
++
++ /* destination address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
++
++ chan->control_flags = S3C_DMACONTROL_DEST_INC | S3C_DMACONTROL_SRC_AXI_PERI;
++ //chan->control_flags = hwcfg;
++
++ return 0;
++
++ case S3C_DMA_MEM2MEM:
++ /* this is temporary for G3D */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ chan->config_flags = tmp;
++
++ /* TODO : Now, Scatter&Gather DMA NOT YET supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : memory/onenand address (source) */
++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
++
++ /* destination address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
++
++ chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI
++ | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4);
++ //chan->control_flags = hwcfg;
++
++ return 0;
++
++ case S3C_DMA_MEM2MEM_P:
++ /* source is memory : Memory-to-Mem ( Read/Write) */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ if(chan->map->hw_addr.from == S3C_DMA0_ONENAND_RX) {
++ tmp |= S3C_DMACONFIG_ONENANDMODESRC;
++ }
++
++ chan->config_flags = tmp;
++
++ /* TODO : Now, Scatter&Gather DMA NOT YET supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : memory/onenand address (source) */
++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
++
++ /* destination address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
++
++ chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_INC
++ | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4);
++ //chan->control_flags = hwcfg;
++
++ return 0;
++
++ case S3C_DMA_PER2PER:
++ printk("Peripheral-to-Peripheral DMA NOT YET implemented !! \n");
++ return -EINVAL;
++
++ default:
++ printk(KERN_ERR "DMA CH :%d - invalid source type ()\n", channel);
++ printk("Unsupported DMA configuration from the device driver using DMA driver \n");
++ return -EINVAL;
++ }
++
++}
++
++EXPORT_SYMBOL(s3c2410_dma_devconfig);
++
++
++/*
++ * s3c_dma_getposition
++ * returns the current transfer points for the dma source and destination
++ */
++int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ if (src != NULL)
++ *src = dma_rdreg(chan, S3C_DMAC_CxSRCADDR);
++
++ if (dst != NULL)
++ *dst = dma_rdreg(chan, S3C_DMAC_CxDESTADDR);
++
++ return 0;
++}
++
++EXPORT_SYMBOL(s3c2410_dma_getposition);
++
++
++/* system device class */
++#ifdef CONFIG_PM
++static int s3c_dma_suspend (struct sys_device *dev, pm_message_t state)
++{
++ return 0;
++}
++
++static int s3c_dma_resume (struct sys_device *dev)
++{
++ return 0;
++}
++#else
++#define s3c_dma_suspend NULL
++#define s3c_dma_resume NULL
++#endif /* CONFIG_PM */
++
++struct sysdev_class dma_sysclass = {
++ set_kset_name("s3c64xx-dma"),
++ .suspend = s3c_dma_suspend,
++ .resume = s3c_dma_resume,
++};
++
++/* kmem cache implementation */
++
++static void s3c_dma_cache_ctor(struct kmem_cache *c, void *p)
++{
++ memset(p, 0, sizeof(struct s3c2410_dma_buf));
++}
++
++
++void dma_test (int dcon_num, int channel)
++{
++ int tmp;
++
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++#if 0
++ sh_printk("writing to channel %d subch %d \n", dcon_num, channel);
++ sh_printk("main channel %d irq %d regs_base %x\n", dma_controller->number, dma_controller->irq,
++ dma_controller->regs);
++ sh_printk("sub channel %d irq %d regs_base %x\n", chan->number, chan->irq,
++ chan->regs);
++#endif
++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
++ printk("reg val %d\n", tmp);
++ dma_wrreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel), 0x01);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel));
++
++ printk("reg conf %x\n", tmp);
++ dma_wrreg(dma_controller, S3C_DMAC_CCONTROL0(channel), 0x8ff02064);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel));
++ printk("reg ctrl %x\n", tmp);
++}
++
++
++/* initialisation code */
++
++int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
++ unsigned int stride)
++{
++ struct s3c2410_dma_chan *cp;
++ s3c_dma_controller_t *dconp;
++ int channel, controller;
++ int ret;
++
++ printk("S3C DMA-pl080 Controller Driver, (c) 2006-2007 Samsung Electronics\n");
++
++ dma_channels = channels;
++ printk("Total %d DMA channels will be initialized.\n", channels);
++
++ ret = sysdev_class_register(&dma_sysclass);
++ if (ret != 0) {
++ printk(KERN_ERR "dma sysclass registration failed.\n");
++ goto err;
++ }
++
++ dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0,
++ SLAB_HWCACHE_ALIGN, s3c_dma_cache_ctor);
++
++ if (dma_kmem == NULL) {
++ printk(KERN_ERR "DMA failed to make kmem cache\n");
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ for (controller = 0; controller < S3C_DMA_CONTROLLERS; controller++) {
++ dconp = &s3c_dma_cntlrs[controller];
++
++ memset(dconp, 0, sizeof(s3c_dma_controller_t));
++
++ if(controller < 2) {
++ dma_base = ioremap((S3C24XX_PA_DMA + (controller * 0x100000)), 0x200);
++ if (dma_base == NULL) {
++ printk(KERN_ERR "DMA failed to ioremap register block\n");
++ return -ENOMEM;
++ }
++
++ /* dma controller's irqs are in order.. */
++ dconp->irq = controller + IRQ_DMA0;
++ }
++ else {
++ dma_base = ioremap(((S3C24XX_PA_DMA + 0x8B00000) + ((controller%2) * 0x100000)), 0x200);
++ if (dma_base == NULL) {
++ printk(KERN_ERR "SDMA failed to ioremap register block\n");
++ return -ENOMEM;
++ }
++
++ /* dma controller's irqs are in order.. */
++ dconp->irq = (controller%2) + IRQ_SDMA0;
++ }
++
++ dconp->number = controller;
++ dconp->regs = dma_base;
++ sh_printk("DMA controller : %d irq %d regs_base %x\n", dconp->number, dconp->irq,
++ dconp->regs);
++ }
++
++ for (channel = 0; channel < channels; channel++) {
++ controller = channel / S3C_CHANNELS_PER_DMA;
++ cp = &s3c_dma_chans[channel];
++
++ memset(cp, 0, sizeof(struct s3c2410_dma_chan));
++
++ cp->dma_con = &s3c_dma_cntlrs[controller];
++
++ /* dma channel irqs are in order.. */
++ cp->index = channel;
++ cp->number = channel%S3C_CHANNELS_PER_DMA;
++
++ cp->irq = s3c_dma_cntlrs[controller].irq;
++
++ cp->regs = s3c_dma_cntlrs[controller].regs + ((channel%S3C_CHANNELS_PER_DMA)*stride) + 0x100;
++
++ /* point current stats somewhere */
++ cp->stats = &cp->stats_store;
++ cp->stats_store.timeout_shortest = LONG_MAX;
++
++ /* basic channel configuration */
++ cp->load_timeout = 1 << 18;
++
++ /* register system device */
++ cp->dev.cls = &dma_sysclass;
++ cp->dev.id = channel;
++ //ret = sysdev_register(&cp->dev);
++
++ sh_printk("DMA channel %d at %p, irq %d\n", cp->number, cp->regs, cp->irq);
++ }
++
++ return 0;
++
++err:
++ kmem_cache_destroy(dma_kmem);
++ iounmap(dma_base);
++ dma_base = NULL;
++ return ret;
++}
++
++
++
++static inline int is_channel_valid(unsigned int channel)
++{
++ return (channel & DMA_CH_VALID);
++}
++
++static struct s3c24xx_dma_order *dma_order;
++
++
++/* s3c_dma_map_channel()
++ *
++ * turn the virtual channel number into a real, and un-used hardware
++ * channel.
++ *
++ * first, try the dma ordering given to us by either the relevant
++ * dma code, or the board. Then just find the first usable free
++ * channel
++*/
++
++struct s3c2410_dma_chan *s3c_dma_map_channel(int channel)
++{
++ struct s3c24xx_dma_order_ch *ord = NULL;
++ struct s3c24xx_dma_map *ch_map;
++ struct s3c2410_dma_chan *dmach;
++ int ch;
++
++ if (dma_sel.map == NULL || channel > dma_sel.map_size)
++ return NULL;
++
++ ch_map = dma_sel.map + channel;
++
++ /* first, try the board mapping */
++
++ if (dma_order) {
++ ord = &dma_order->channels[channel];
++
++ for (ch = 0; ch < dma_channels; ch++) {
++ if (!is_channel_valid(ord->list[ch]))
++ continue;
++
++ if (s3c_dma_chans[ord->list[ch]].in_use == 0) {
++ ch = ord->list[ch] & ~DMA_CH_VALID;
++ goto found;
++ }
++ }
++
++ if (ord->flags & DMA_CH_NEVER)
++ return NULL;
++ }
++
++ /* second, search the channel map for first free */
++
++ for (ch = 0; ch < dma_channels; ch++) {
++ if (!is_channel_valid(ch_map->channels[ch]))
++ continue;
++
++ if (s3c_dma_chans[ch].in_use == 0) {
++ pr_debug("mapped channel %d to %d\n", channel, ch);
++ break;
++ }
++ }
++
++ if (ch >= dma_channels)
++ return NULL;
++
++ /* update our channel mapping */
++
++ found:
++ dmach = &s3c_dma_chans[ch];
++ dma_chan_map[channel] = dmach;
++
++ /* select the channel */
++ (dma_sel.select)(dmach, ch_map);
++
++ return dmach;
++}
++
++static int s3c_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
++{
++ unsigned long tmp = __raw_readl(S3C_SDMA_SEL);
++
++ tmp |= map->sdma_sel;
++ __raw_writel(tmp, S3C_SDMA_SEL);
++
++ return 0;
++}
++
++int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
++{
++ struct s3c24xx_dma_map *nmap;
++ size_t map_sz = sizeof(*nmap) * sel->map_size;
++ int ptr;
++
++ nmap = kmalloc(map_sz, GFP_KERNEL);
++ if (nmap == NULL)
++ return -ENOMEM;
++
++ memcpy(nmap, sel->map, map_sz);
++ memcpy(&dma_sel, sel, sizeof(*sel));
++
++ dma_sel.map = nmap;
++
++ for (ptr = 0; ptr < sel->map_size; ptr++)
++ s3c_dma_check_entry(nmap+ptr, ptr);
++
++ return 0;
++}
++
++int __init s3c_dma_order_set(struct s3c24xx_dma_order *ord)
++{
++ struct s3c24xx_dma_order *nord = dma_order;
++
++ if (nord == NULL)
++ nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
++
++ if (nord == NULL) {
++ printk(KERN_ERR "no memory to store dma channel order\n");
++ return -ENOMEM;
++ }
++
++ dma_order = nord;
++ memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
++ return 0;
++}
++
++
+diff --git a/arch/arm/plat-s3c64xx/irq-pl192.c b/arch/arm/plat-s3c64xx/irq-pl192.c
+new file mode 100644
+index 0000000..52d0234
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/irq-pl192.c
+@@ -0,0 +1,619 @@
++/* linux/arch/arm/mach-s3c64xx/irq-pl192.c
++ *
++ *
++ * S3C64XX interrupt functions.
++ * Added by JaeCheol Lee(jc.lee@samsung.com)
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/ptrace.h>
++#include <linux/sysdev.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/mach/irq.h>
++
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-irq.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/plat-s3c24xx/pm.h>
++
++#define irqdbf(x...)
++#define irqdbf2(x...)
++
++
++/* "irqno" interrupt acked */
++static inline void
++s3c_irq_ack (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ } else if (irqno < 64) {
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ __raw_writel(irqno, S3C_VIC1ADDRESS);
++ } else {
++ /* External interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++/* "irqno" interrupt disabled */
++static inline void
++s3c_irq_mask (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(1<<irqno, S3C_VIC0INTENCLEAR);
++ } else if (irqno < 64) {
++ __raw_writel(1<<(irqno-32), S3C_VIC1INTENCLEAR);
++ } else {
++ /* External interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++/* "irqno" interrupt disabled and acked */
++static inline void
++s3c_irq_maskack (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(1<<irqno, S3C_VIC0INTENCLEAR);
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ } else if (irqno < 64) {
++ __raw_writel(1<<(irqno-32), S3C_VIC1INTENCLEAR);
++ /* XXX: can explain why this code is here by scsuh */
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ __raw_writel(irqno, S3C_VIC1ADDRESS);
++ } else {
++ /* External interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++/* "irqno" interrupt enabled */
++static inline void
++s3c_irq_unmask (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(1<<irqno, S3C_VIC0INTENABLE);
++ } else if (irqno < 64) {
++ __raw_writel(1<<(irqno-32), S3C_VIC1INTENABLE);
++ } else {
++ /* External Interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++static inline void
++s3c_irq_unmaskack(unsigned int irqno)
++{
++ unsigned long unmask;
++
++ /* It is common for all interrupt sources */
++ __raw_writel(1, S3C_VIC0ADDRESS);
++
++ if (irqno < 32) {
++ unmask = __raw_readl(S3C_VIC0INTENABLE);
++ unmask |= (1UL << irqno);
++ __raw_writel(unmask, S3C_VIC0INTENABLE);
++ } else if (irqno < 64) {
++ unmask = __raw_readl(S3C_VIC1INTENABLE);
++ unmask |= (1UL << (irqno - 32));
++ __raw_writel(unmask, S3C_VIC1INTENABLE);
++ __raw_writel(1, S3C_VIC1ADDRESS);
++ } else {
++ /* External Interrupt */
++ printk("ext irq %d\n", irqno);
++
++ }
++}
++
++static int
++s3c_irq_wake(unsigned int irqno, unsigned int flag)
++{
++ unsigned int pwr_cfg,bit_position;
++
++ pwr_cfg = __raw_readl(S3C_PWR_CFG);
++
++ switch(irqno) {
++ case IRQ_RTC_TIC:
++ bit_position = 11;
++ break;
++ case IRQ_TC:
++ bit_position = 12;
++ break;
++ case IRQ_RTC_ALARM:
++ bit_position = 10;
++ break;
++ case IRQ_KEYPAD:
++ bit_position = 8;
++ break;
++ default:
++ printk("irq %d : Not supporting wakeup \n", irqno);
++ return -1;
++ }
++
++ if(flag) {
++ pwr_cfg &=~(1 << bit_position);
++ } else {
++ pwr_cfg |= (1 << bit_position);
++ }
++ __raw_writel(pwr_cfg, S3C_PWR_CFG);
++
++ return 0;
++}
++
++//static struct irqchip s3c_irq_level_chip = {
++static struct irq_chip s3c_irq_level_chip = {
++ .ack = s3c_irq_maskack,
++ .mask = s3c_irq_mask,
++ .unmask = s3c_irq_unmask,
++ .set_wake = s3c_irq_wake
++};
++
++#if 0 /* XXX: when you want to use it, unmask it. by scsuh */
++static struct irqchip s3c_irq_chip = {
++ .ack = s3c_irq_mask,
++ .mask = s3c_irq_mask,
++ .unmask = s3c_irq_unmask,
++ .set_wake = s3c_irq_wake
++};
++#endif
++
++static inline void
++s3c_irqext_mask(unsigned int irqno)
++{
++ unsigned long gpjcon; // Workaround
++ unsigned long mask;
++
++ if (irqno >= 64) {
++ gpjcon = __raw_readl(S3C_GPJCON);
++ irqno -= 64;
++ mask = __raw_readl(S3C_EINTMASK);
++ mask |= (1UL << irqno);
++ __raw_writel(mask, S3C_EINTMASK);
++ __raw_writel(gpjcon, S3C_GPJCON);
++ } else {
++ printk("Invalid ext irq %d\n", irqno);
++ }
++}
++
++static inline void
++s3c_irqext_maskack(unsigned int irqno)
++{
++ s3c_irqext_mask(irqno);
++
++ if (irqno <= IRQ_EINT3) {
++ s3c_irq_mask(IRQ_EINT0_3);
++ } else if (irqno <= IRQ_EINT11) {
++ s3c_irq_mask(IRQ_EINT4_11);
++ } else if (irqno <= IRQ_EINT19) {
++ s3c_irq_mask(IRQ_EINT12_19);
++ } else if (irqno <= IRQ_EINT27) {
++ s3c_irq_mask(IRQ_EINT20_27);
++ } else if (irqno > IRQ_EINT27) {
++ panic("Wrong IRQ number %d \n ", irqno);
++ }
++
++}
++
++static inline void
++s3c_irqext_unmaskack(unsigned int irqno)
++{
++ unsigned long mask;
++
++ if (irqno <= IRQ_EINT3) {
++ s3c_irq_unmaskack(IRQ_EINT0_3);
++ } else if (irqno <= IRQ_EINT11) {
++ s3c_irq_unmaskack(IRQ_EINT4_11);
++ } else if (irqno <= IRQ_EINT19) {
++ s3c_irq_unmaskack(IRQ_EINT12_19);
++ } else if (irqno <= IRQ_EINT27) {
++ s3c_irq_unmaskack(IRQ_EINT20_27);
++ }
++ if (irqno >= 64) {
++ irqno -= 64;
++ __raw_writel(1UL << irqno, S3C_EINTPEND);
++ mask = __raw_readl(S3C_EINTMASK);
++ mask &= ~(1UL << irqno);
++ __raw_writel(mask, S3C_EINTMASK);
++ } else {
++ printk("Invalid ext irq %d\n", irqno);
++ }
++
++}
++
++
++static int
++s3c_irqext_type(unsigned int irq, unsigned int type)
++{
++
++ unsigned long newvalue = 0;
++
++
++ /* Set the external interrupt to pointed trigger type */
++ switch (type) {
++ case IRQT_NOEDGE:
++ printk(KERN_WARNING "No edge setting!\n");
++ break;
++
++ case IRQT_RISING:
++ newvalue = S3C_EXTINT_RISEEDGE;
++ break;
++
++ case IRQT_FALLING:
++ newvalue = S3C_EXTINT_FALLEDGE;
++ break;
++
++ case IRQT_BOTHEDGE:
++ newvalue = S3C_EXTINT_BOTHEDGE;
++ break;
++
++ case IRQT_LOW:
++ newvalue = S3C_EXTINT_LOWLEV;
++ break;
++
++ case IRQT_HIGH:
++ newvalue = S3C_EXTINT_HILEV;
++ break;
++
++ default:
++ printk(KERN_ERR "No such irq type %d", type);
++ return -1;
++ }
++
++ switch (irq) {
++ case IRQ_EINT9:
++ gpio_set_pin(S3C_GPN9, S3C_GPN9_EXTINT9);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 16)) |
++ (newvalue << 16), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT10:
++ gpio_set_pin(S3C_GPN10, S3C_GPN10_EXTINT10);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 20)) |
++ (newvalue << 20), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT11:
++ gpio_set_pin(S3C_GPN11, S3C_GPN11_EXTINT11);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 20)) |
++ (newvalue << 20), S3C_EINTCON0);
++ break;
++ case IRQ_EINT12:
++ gpio_set_pin(S3C_GPN12, S3C_GPN12_EXTINT12);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 24)) |
++ (newvalue << 24), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT13:
++ gpio_set_pin(S3C_GPN13, S3C_GPN13_EXTINT13);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 24)) |
++ (newvalue << 24), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT14:
++ gpio_set_pin(S3C_GPN14, S3C_GPN14_EXTINT14);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 28)) |
++ (newvalue << 28), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT15:
++ gpio_set_pin(S3C_GPN15, S3C_GPN15_EXTINT15);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 28)) |
++ (newvalue << 28), S3C_EINTCON0);
++ break;
++ default:
++ printk(KERN_ERR
++ "s3c_irqext_type : Only support EINT9,10,11,12,13,14,15 interrupt.\n");
++ break;
++
++ }
++
++ return 0;
++}
++
++static int s3c_irqext_wake(unsigned int irqno, unsigned int flag)
++{
++ unsigned int eint_mask;
++
++ if(irqno < IRQ_EINT0)
++ printk(KERN_ERR "Check external wake-up source\n");
++
++ eint_mask = __raw_readl(S3C_EINT_MASK);
++
++ if(flag) {
++ eint_mask &= ~(1 << (irqno - IRQ_EINT0));
++ } else {
++ eint_mask |= (1 << (irqno - IRQ_EINT0));
++ }
++
++ __raw_writel(eint_mask, S3C_EINT_MASK);
++
++ return 0;
++}
++
++//static struct irqchip s3c_irqext_chip = {
++static struct irq_chip s3c_irqext_chip = {
++ .mask = s3c_irqext_mask,
++ .unmask = s3c_irqext_unmaskack,
++ .ack = s3c_irqext_maskack,
++ .set_type = s3c_irqext_type,
++ .set_wake = s3c_irqext_wake
++};
++
++
++/* irq demux for EINT0_3 */
++static inline void
++s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
++{
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT0;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = (eintpend & 0xf);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++
++}
++
++/* irq demux for EINT4_11 */
++static void
++s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
++{
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT4;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = ((eintpend >> 4) & 0xff);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++}
++
++/* irq demux for EINT12_19 */
++static void
++s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
++{
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT12;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = ((eintpend >> 12) & 0xff);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++
++}
++
++/* irq demux for EINT20_27 */
++static void
++s3c_irq_demux_eint20_27 (unsigned int irq, struct irq_desc *desc)
++{
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT20;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = ((eintpend >> 20) & 0xff);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++}
++
++#ifdef CONFIG_PM
++
++static struct sleep_save irq_save[] = {
++ SAVE_ITEM(S3C_VIC0INTSELECT),
++ SAVE_ITEM(S3C_VIC1INTSELECT),
++ SAVE_ITEM(S3C_VIC0INTENABLE),
++ SAVE_ITEM(S3C_VIC1INTENABLE),
++ SAVE_ITEM(S3C_VIC0SOFTINT),
++ SAVE_ITEM(S3C_VIC1SOFTINT),
++};
++
++static struct sleep_save extirq_save[] = {
++ SAVE_ITEM(S3C_EINTCON0),
++ SAVE_ITEM(S3C_EINTCON1),
++ SAVE_ITEM(S3C_EINTFLTCON0),
++ SAVE_ITEM(S3C_EINTFLTCON1),
++ SAVE_ITEM(S3C_EINTFLTCON2),
++ SAVE_ITEM(S3C_EINTFLTCON3),
++ SAVE_ITEM(S3C_EINTMASK),
++ SAVE_ITEM(S3C_EINT12CON),
++ SAVE_ITEM(S3C_EINT34CON),
++ SAVE_ITEM(S3C_EINT56CON),
++ SAVE_ITEM(S3C_EINT78CON),
++ SAVE_ITEM(S3C_EINT9CON),
++ SAVE_ITEM(S3C_EINT12FLTCON),
++ SAVE_ITEM(S3C_EINT34FLTCON),
++ SAVE_ITEM(S3C_EINT56FLTCON),
++ SAVE_ITEM(S3C_EINT78FLTCON),
++ SAVE_ITEM(S3C_EINT9FLTCON),
++ SAVE_ITEM(S3C_EINT12MASK),
++ SAVE_ITEM(S3C_EINT34MASK),
++ SAVE_ITEM(S3C_EINT56MASK),
++ SAVE_ITEM(S3C_EINT78MASK),
++ SAVE_ITEM(S3C_EINT9MASK),
++ SAVE_ITEM(S3C_EINT34FLTCON),
++ SAVE_ITEM(S3C_EINT56FLTCON),
++ SAVE_ITEM(S3C_EINT78FLTCON),
++ SAVE_ITEM(S3C_EINT9FLTCON),
++};
++
++int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
++{
++ s3c2410_pm_do_save(extirq_save, ARRAY_SIZE(extirq_save));
++ s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
++ return 0;
++}
++
++int s3c24xx_irq_resume(struct sys_device *dev)
++{
++ int irqno;
++ int irqindex = 0;
++
++ s3c2410_pm_do_restore(extirq_save, ARRAY_SIZE(extirq_save));
++ s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
++
++ /* For writing the IRQ number into the VICVECTADDR */
++ for (irqno = IRQ_EINT0_3; irqno <= IRQ_LCD_SYSTEM; irqno++) {
++ __raw_writel(irqno, S3C_VIC0VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ irqindex = 0;
++ for (irqno = IRQ_EINT12_19; irqno <= IRQ_ADC; irqno++) {
++ __raw_writel(irqno, S3C_VIC1VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++ return 0;
++}
++
++#else
++#define s3c24xx_irq_suspend NULL
++#define s3c24xx_irq_resume NULL
++#endif
++
++
++/* --------------------------------------------------
++ * s3c_init_irq
++ *
++ * Initialise s3c6400 IRQ system
++ * --------------------------------------------------
++ */
++
++void __init s3c_init_irq(void)
++{
++ int irqno;
++ int irqindex = 0;
++
++ irqdbf("s3c_init_irq: clearing interrupt status flags\n");
++
++ /* first, clear all interrupts pending... */
++
++ /* clear external interrupts */
++ __raw_writel(0xFFFFFFFF, S3C_EINTPEND);
++
++ /* clear all vector interrupts */
++ __raw_writel(0x00000000, S3C_VIC0ADDRESS);
++ __raw_writel(0x00000000, S3C_VIC1ADDRESS);
++
++
++ /* For writing the IRQ number into the VICVECTADDR */
++ for (irqno = IRQ_EINT0_3; irqno <= IRQ_LCD_SYSTEM; irqno++) {
++ __raw_writel(irqno, S3C_VIC0VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ irqindex = 0;
++ for (irqno = IRQ_EINT12_19; irqno <= IRQ_ADC; irqno++) {
++ __raw_writel(irqno, S3C_VIC1VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ /* register the main interrupts */
++ irqdbf("s3c_init_irq: registering S3C64XX interrupt handlers\n");
++
++ for (irqno = IRQ_EINT0_3; irqno <= IRQ_ADC; irqno++) {
++ switch (irqno) {
++ /* deal with the special IRQs in ext (cascaded) */
++ case IRQ_EINT0_3:
++ set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
++ break;
++
++ case IRQ_EINT4_11:
++ set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
++ break;
++
++ case IRQ_EINT12_19:
++ set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
++ break;
++
++ case IRQ_EINT20_27:
++ set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
++ break;
++
++ default:
++ irqdbf("registering irq %d (s3c irq)\n", irqno);
++ set_irq_chip(irqno, &s3c_irq_level_chip);
++ //set_irq_handler(irqno, do_level_IRQ);
++ set_irq_handler(irqno, handle_level_irq);
++ set_irq_flags(irqno, IRQF_VALID);
++ break;
++ }
++ }
++
++ for (irqno = IRQ_EINT0; irqno <= IRQ_EINT27; irqno++) {
++ irqdbf("registering irq %d (extended s3c irq)\n", irqno);
++ set_irq_chip(irqno, &s3c_irqext_chip);
++ //set_irq_handler(irqno, do_level_IRQ);
++ set_irq_handler(irqno, handle_level_irq);
++ set_irq_flags(irqno, IRQF_VALID);
++ }
++
++ irqdbf("s3c64XX: registered interrupt handlers\n");
++}
+diff --git a/arch/arm/plat-s3c64xx/ltc3714.c b/arch/arm/plat-s3c64xx/ltc3714.c
+new file mode 100644
+index 0000000..0b4d5ba
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/ltc3714.c
+@@ -0,0 +1,153 @@
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/fcntl.h>
++
++#include <asm/uaccess.h>
++#include <asm/io.h>
++
++#include <linux/stat.h>
++
++#include <linux/delay.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/gpio.h>
++
++#define ARM_LE 0
++#define INT_LE 1
++
++/* ltc3714 voltage table */
++static const unsigned int voltage_table[32] = {
++ 1750, 1700, 1650, 1600, 1550, 1500, 1450, 1400,
++ 1350, 1300, 1250, 1200, 1150, 1100, 1050, 1000,
++ 975, 950, 925, 900, 875, 850, 825, 800,
++ 775, 750, 725, 700, 675, 650, 625, 600,
++};
++
++/* frequency voltage matching table */
++static const unsigned int frequency_match[][3] = {
++/* frequency, Mathced VDD ARM voltage , Matched VDD INT*/
++ {667000, 1200, 1300},
++ {333000, 1100, 1200},
++ {222000, 1050, 1200},
++ {133000, 1000, 1200},
++ {66000, 1000, 1000},
++};
++
++/* LTC3714 Setting Routine */
++static int ltc3714_gpio_setting(void)
++{
++ gpio_direction_output(S3C_GPN11, 0);
++ gpio_direction_output(S3C_GPN12, 0);
++ gpio_direction_output(S3C_GPN13, 0);
++ gpio_direction_output(S3C_GPN14, 0);
++ gpio_direction_output(S3C_GPN15, 0);
++ gpio_direction_output(S3C_GPL8, 0);
++ gpio_direction_output(S3C_GPL9, 0);
++ gpio_direction_output(S3C_GPL10, 0);
++
++ gpio_pullup(S3C_GPN11, 0x0);
++ gpio_pullup(S3C_GPN12, 0x0);
++ gpio_pullup(S3C_GPN13, 0x0);
++ gpio_pullup(S3C_GPN14, 0x0);
++ gpio_pullup(S3C_GPN15, 0x0);
++ gpio_pullup(S3C_GPL8, 0x0);
++ gpio_pullup(S3C_GPL9, 0x0);
++ gpio_pullup(S3C_GPL10, 0x0);
++
++ return 0;
++}
++
++static int set_ltc3714(unsigned int pwr, unsigned int index)
++{
++ int position = 0;
++
++ int voltage = frequency_match[index][pwr + 1];
++
++ if(voltage > voltage_table[0] || voltage < voltage_table[31]) {
++ printk("[ERROR]: voltage value over limits!!!");
++ return -EINVAL;
++ }
++
++ if(voltage > voltage_table[16]) { // 1750 ~ 1000 mV
++ for(position = 15; position >= 0; position --) {
++ if(voltage_table[position] == voltage) break;
++ }
++
++ }
++ else if(voltage >= voltage_table[31]) { //975 ~ 600 mV
++ for(position = 31; position >= 16; position --) {
++ if(voltage_table[position] == voltage) break;
++ }
++ }
++ else {
++ printk("[error]: Can't find adquate voltage table list value\n");
++ return -EINVAL;
++ }
++
++ position &=0x1f;
++
++ gpio_set_value(S3C_GPN11,(position >> 0)&0x1);
++ gpio_set_value(S3C_GPN12,(position >> 1)&0x1);
++ gpio_set_value(S3C_GPN13,(position >> 2)&0x1);
++ gpio_set_value(S3C_GPN14,(position >> 3)&0x1);
++ gpio_set_value(S3C_GPN15,(position >> 4)&0x1);
++
++ if(pwr == ARM_LE) {
++ gpio_set_value(S3C_GPL8, 1);
++ udelay(10);
++ gpio_set_value(S3C_GPL8, 0);
++ } else if(pwr == INT_LE) {
++ gpio_set_value(S3C_GPL10, 1);
++ udelay(10);
++ gpio_set_value(S3C_GPL10, 0);
++ } else {
++ printk("[error]: set_power, check mode [pwr] value\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int find_voltage(int freq)
++{
++ int index = 0;
++
++ if(freq > frequency_match[0][0]){
++ printk(KERN_ERR "frequecy is over then support frequency\n");
++ return 0;
++ }
++
++ for(index = 0 ; index < ARRAY_SIZE(frequency_match) ; index++){
++ if(freq >= frequency_match[index][0])
++ return index;
++ }
++
++ printk("Cannot find matched voltage on table\n");
++
++ return 0;
++}
++
++int set_power(unsigned int freq)
++{
++ int index;
++
++ index = find_voltage(freq);
++
++ set_ltc3714(ARM_LE, index);
++
++ return 0;
++}
++
++EXPORT_SYMBOL(set_power);
++
++int ltc3714_init(void)
++{
++ ltc3714_gpio_setting();
++ set_power(532000);
++ gpio_set_value(S3C_GPL9, 1);
++}
++
++EXPORT_SYMBOL(ltc3714_init);
+diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c
+new file mode 100644
+index 0000000..08efe07
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/pm.c
+@@ -0,0 +1,787 @@
++/* linux/arch/arm/plat-s3c24xx/pm.c
++ *
++ * Copyright (c) 2004,2006 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C24XX Power Manager (Suspend-To-RAM) support
++ *
++ * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * Parts based on arch/arm/mach-pxa/pm.c
++ *
++ * Thanks to Dimitry Andric for debugging
++*/
++
++#include <linux/init.h>
++#include <linux/suspend.h>
++#include <linux/errno.h>
++#include <linux/time.h>
++#include <linux/interrupt.h>
++#include <linux/crc32.h>
++#include <linux/ioport.h>
++#include <linux/delay.h>
++#include <linux/serial_core.h>
++#include <linux/platform_device.h>
++
++#include <asm/cacheflush.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
++#include <asm/arch/regs-dsc.h>
++#include <asm/arch/regs-mem.h>
++#include <asm/arch/regs-irq.h>
++#include <asm/arch/gpio.h>
++
++#include <asm/mach/time.h>
++
++#include <asm/plat-s3c24xx/pm.h>
++#include <asm/mach/irq.h>
++
++/* for external use */
++
++unsigned long s3c_pm_flags;
++
++#define PFX "s3c24xx-pm: "
++
++static struct sleep_save core_save[] = {
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++ SAVE_ITEM(S3C_SDMA_SEL),
++#else
++ SAVE_ITEM(S3C2410_LOCKTIME),
++ SAVE_ITEM(S3C2410_CLKCON),
++
++ /* we restore the timings here, with the proviso that the board
++ * brings the system up in an slower, or equal frequency setting
++ * to the original system.
++ *
++ * if we cannot guarantee this, then things are going to go very
++ * wrong here, as we modify the refresh and both pll settings.
++ */
++
++ SAVE_ITEM(S3C2410_BWSCON),
++ SAVE_ITEM(S3C2410_BANKCON0),
++ SAVE_ITEM(S3C2410_BANKCON1),
++ SAVE_ITEM(S3C2410_BANKCON2),
++ SAVE_ITEM(S3C2410_BANKCON3),
++ SAVE_ITEM(S3C2410_BANKCON4),
++ SAVE_ITEM(S3C2410_BANKCON5),
++
++ SAVE_ITEM(S3C2410_CLKDIVN),
++ SAVE_ITEM(S3C2410_MPLLCON),
++ SAVE_ITEM(S3C2410_UPLLCON),
++ SAVE_ITEM(S3C2410_CLKSLOW),
++ SAVE_ITEM(S3C2410_REFRESH),
++#endif
++};
++
++static struct sleep_save gpio_save[] = {
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++
++ SAVE_ITEM(S3C_GPACON),
++ SAVE_ITEM(S3C_GPADAT),
++ SAVE_ITEM(S3C_GPAPU),
++
++ SAVE_ITEM(S3C_GPBCON),
++ SAVE_ITEM(S3C_GPBDAT),
++ SAVE_ITEM(S3C_GPBPU),
++
++ SAVE_ITEM(S3C_GPCCON),
++ SAVE_ITEM(S3C_GPCDAT),
++ SAVE_ITEM(S3C_GPCPU),
++
++ SAVE_ITEM(S3C_GPDCON),
++ SAVE_ITEM(S3C_GPDDAT),
++ SAVE_ITEM(S3C_GPDPU),
++
++ SAVE_ITEM(S3C_GPECON),
++ SAVE_ITEM(S3C_GPEDAT),
++ SAVE_ITEM(S3C_GPEPU),
++
++ SAVE_ITEM(S3C_GPFCON),
++ SAVE_ITEM(S3C_GPFDAT),
++ SAVE_ITEM(S3C_GPFPU),
++
++ SAVE_ITEM(S3C_GPGCON),
++ SAVE_ITEM(S3C_GPGDAT),
++ SAVE_ITEM(S3C_GPGPU),
++
++ SAVE_ITEM(S3C_GPH0CON),
++ SAVE_ITEM(S3C_GPH1CON),
++ SAVE_ITEM(S3C_GPHDAT),
++ SAVE_ITEM(S3C_GPHPU),
++
++ SAVE_ITEM(S3C_GPICON),
++ SAVE_ITEM(S3C_GPIDAT),
++ SAVE_ITEM(S3C_GPIPU),
++
++ SAVE_ITEM(S3C_GPJCON),
++ SAVE_ITEM(S3C_GPJDAT),
++ SAVE_ITEM(S3C_GPJPU),
++
++ SAVE_ITEM(S3C_GPK0CON),
++ SAVE_ITEM(S3C_GPK1CON),
++ SAVE_ITEM(S3C_GPKDAT),
++ SAVE_ITEM(S3C_GPKPU),
++
++ SAVE_ITEM(S3C_GPL0CON),
++ SAVE_ITEM(S3C_GPL1CON),
++ SAVE_ITEM(S3C_GPLDAT),
++ SAVE_ITEM(S3C_GPLPU),
++
++ SAVE_ITEM(S3C_GPMCON),
++ SAVE_ITEM(S3C_GPMDAT),
++ SAVE_ITEM(S3C_GPMPU),
++
++ SAVE_ITEM(S3C_GPNCON),
++ SAVE_ITEM(S3C_GPNDAT),
++ SAVE_ITEM(S3C_GPNPU),
++
++ SAVE_ITEM(S3C_GPOCON),
++ SAVE_ITEM(S3C_GPODAT),
++ SAVE_ITEM(S3C_GPOPU),
++
++ SAVE_ITEM(S3C_GPPCON),
++ SAVE_ITEM(S3C_GPPDAT),
++ SAVE_ITEM(S3C_GPPPU),
++
++ SAVE_ITEM(S3C_GPQCON),
++ SAVE_ITEM(S3C_GPQDAT),
++ SAVE_ITEM(S3C_GPQPU),
++
++
++ SAVE_ITEM(S3C_PRIORITY),
++
++ /* Special register*/
++ SAVE_ITEM(S3C_SPCON),
++
++ /* Memory port control */
++ SAVE_ITEM(S3C_MEM0CONSTOP),
++ SAVE_ITEM(S3C_MEM1CONSTOP),
++ SAVE_ITEM(S3C_MEM0CONSLP0),
++ SAVE_ITEM(S3C_MEM0CONSLP1),
++ SAVE_ITEM(S3C_MEM1CONSLP),
++ SAVE_ITEM(S3C_MEM0DRVCON),
++ SAVE_ITEM(S3C_MEM1DRVCON),
++#else
++ SAVE_ITEM(S3C2410_GPACON),
++ SAVE_ITEM(S3C2410_GPADAT),
++
++ SAVE_ITEM(S3C2410_GPBCON),
++ SAVE_ITEM(S3C2410_GPBDAT),
++ SAVE_ITEM(S3C2410_GPBUP),
++
++ SAVE_ITEM(S3C2410_GPCCON),
++ SAVE_ITEM(S3C2410_GPCDAT),
++ SAVE_ITEM(S3C2410_GPCUP),
++
++ SAVE_ITEM(S3C2410_GPDCON),
++ SAVE_ITEM(S3C2410_GPDDAT),
++ SAVE_ITEM(S3C2410_GPDUP),
++
++ SAVE_ITEM(S3C2410_GPECON),
++ SAVE_ITEM(S3C2410_GPEDAT),
++ SAVE_ITEM(S3C2410_GPEUP),
++
++ SAVE_ITEM(S3C2410_GPFCON),
++ SAVE_ITEM(S3C2410_GPFDAT),
++ SAVE_ITEM(S3C2410_GPFUP),
++
++ SAVE_ITEM(S3C2410_GPGCON),
++ SAVE_ITEM(S3C2410_GPGDAT),
++ SAVE_ITEM(S3C2410_GPGUP),
++
++ SAVE_ITEM(S3C2410_GPHCON),
++ SAVE_ITEM(S3C2410_GPHDAT),
++ SAVE_ITEM(S3C2410_GPHUP),
++
++ SAVE_ITEM(S3C2410_DCLKCON),
++#endif
++};
++
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++/* this lot should be really saved by the IRQ code */
++/* VICXADDRESSXX initilaization to be needed */
++static struct sleep_save irq_save[] = {
++ SAVE_ITEM(S3C_VIC0INTSELECT),
++ SAVE_ITEM(S3C_VIC1INTSELECT),
++ SAVE_ITEM(S3C_VIC0INTENABLE),
++ SAVE_ITEM(S3C_VIC1INTENABLE),
++ SAVE_ITEM(S3C_VIC0SOFTINT),
++ SAVE_ITEM(S3C_VIC1SOFTINT),
++};
++
++static struct sleep_save sromc_save[] = {
++ SAVE_ITEM(S3C_SROM_BW),
++ SAVE_ITEM(S3C_SROM_BC0),
++ SAVE_ITEM(S3C_SROM_BC1),
++ SAVE_ITEM(S3C_SROM_BC2),
++ SAVE_ITEM(S3C_SROM_BC3),
++ SAVE_ITEM(S3C_SROM_BC4),
++ SAVE_ITEM(S3C_SROM_BC5),
++};
++
++#endif
++
++#ifdef CONFIG_S3C2410_PM_DEBUG
++
++#define SAVE_UART(va) \
++ SAVE_ITEM((va) + S3C2410_ULCON), \
++ SAVE_ITEM((va) + S3C2410_UCON), \
++ SAVE_ITEM((va) + S3C2410_UFCON), \
++ SAVE_ITEM((va) + S3C2410_UMCON), \
++ SAVE_ITEM((va) + S3C2410_UBRDIV)
++
++static struct sleep_save uart_save[] = {
++ SAVE_UART(S3C24XX_VA_UART0),
++ SAVE_UART(S3C24XX_VA_UART1),
++#ifndef CONFIG_CPU_S3C2400
++ SAVE_UART(S3C24XX_VA_UART2),
++#endif
++};
++
++/* debug
++ *
++ * we send the debug to printascii() to allow it to be seen if the
++ * system never wakes up from the sleep
++*/
++
++extern void printascii(const char *);
++
++void pm_dbg(const char *fmt, ...)
++{
++ va_list va;
++ char buff[256];
++
++ va_start(va, fmt);
++ vsprintf(buff, fmt, va);
++ va_end(va);
++
++ printascii(buff);
++}
++
++static void s3c2410_pm_debug_init(void)
++{
++ unsigned long tmp = __raw_readl(S3C2410_CLKCON);
++
++ /* re-start uart clocks */
++ tmp |= S3C2410_CLKCON_UART0;
++ tmp |= S3C2410_CLKCON_UART1;
++ tmp |= S3C2410_CLKCON_UART2;
++
++ __raw_writel(tmp, S3C2410_CLKCON);
++ udelay(10);
++}
++
++#define DBG(fmt...) pm_dbg(fmt)
++#else
++#define DBG(fmt...)
++
++#define s3c2410_pm_debug_init() do { } while(0)
++
++static struct sleep_save uart_save[] = {};
++#endif
++
++#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
++
++/* suspend checking code...
++ *
++ * this next area does a set of crc checks over all the installed
++ * memory, so the system can verify if the resume was ok.
++ *
++ * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
++ * increasing it will mean that the area corrupted will be less easy to spot,
++ * and reducing the size will cause the CRC save area to grow
++*/
++
++#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
++
++static u32 crc_size; /* size needed for the crc block */
++static u32 *crcs; /* allocated over suspend/resume */
++
++typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
++
++/* s3c2410_pm_run_res
++ *
++ * go thorugh the given resource list, and look for system ram
++*/
++
++static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
++{
++ while (ptr != NULL) {
++ if (ptr->child != NULL)
++ s3c2410_pm_run_res(ptr->child, fn, arg);
++
++ if ((ptr->flags & IORESOURCE_MEM) &&
++ strcmp(ptr->name, "System RAM") == 0) {
++ DBG("Found system RAM at %08lx..%08lx\n",
++ ptr->start, ptr->end);
++ arg = (fn)(ptr, arg);
++ }
++
++ ptr = ptr->sibling;
++ }
++}
++
++static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
++{
++ s3c2410_pm_run_res(&iomem_resource, fn, arg);
++}
++
++static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
++{
++ u32 size = (u32)(res->end - res->start)+1;
++
++ size += CHECK_CHUNKSIZE-1;
++ size /= CHECK_CHUNKSIZE;
++
++ DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
++
++ *val += size * sizeof(u32);
++ return val;
++}
++
++/* s3c2410_pm_prepare_check
++ *
++ * prepare the necessary information for creating the CRCs. This
++ * must be done before the final save, as it will require memory
++ * allocating, and thus touching bits of the kernel we do not
++ * know about.
++*/
++
++static void s3c2410_pm_check_prepare(void)
++{
++ crc_size = 0;
++
++ s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
++
++ DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
++
++ crcs = kmalloc(crc_size+4, GFP_KERNEL);
++ if (crcs == NULL)
++ printk(KERN_ERR "Cannot allocated CRC save area\n");
++}
++
++static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
++{
++ unsigned long addr, left;
++
++ for (addr = res->start; addr < res->end;
++ addr += CHECK_CHUNKSIZE) {
++ left = res->end - addr;
++
++ if (left > CHECK_CHUNKSIZE)
++ left = CHECK_CHUNKSIZE;
++
++ *val = crc32_le(~0, phys_to_virt(addr), left);
++ val++;
++ }
++
++ return val;
++}
++
++/* s3c2410_pm_check_store
++ *
++ * compute the CRC values for the memory blocks before the final
++ * sleep.
++*/
++
++static void s3c2410_pm_check_store(void)
++{
++ if (crcs != NULL)
++ s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
++}
++
++/* in_region
++ *
++ * return TRUE if the area defined by ptr..ptr+size contatins the
++ * what..what+whatsz
++*/
++
++static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
++{
++ if ((what+whatsz) < ptr)
++ return 0;
++
++ if (what > (ptr+size))
++ return 0;
++
++ return 1;
++}
++
++static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
++{
++ void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
++ unsigned long addr;
++ unsigned long left;
++ void *ptr;
++ u32 calc;
++
++ for (addr = res->start; addr < res->end;
++ addr += CHECK_CHUNKSIZE) {
++ left = res->end - addr;
++
++ if (left > CHECK_CHUNKSIZE)
++ left = CHECK_CHUNKSIZE;
++
++ ptr = phys_to_virt(addr);
++
++ if (in_region(ptr, left, crcs, crc_size)) {
++ DBG("skipping %08lx, has crc block in\n", addr);
++ goto skip_check;
++ }
++
++ if (in_region(ptr, left, save_at, 32*4 )) {
++ DBG("skipping %08lx, has save block in\n", addr);
++ goto skip_check;
++ }
++
++ /* calculate and check the checksum */
++
++ calc = crc32_le(~0, ptr, left);
++ if (calc != *val) {
++ printk(KERN_ERR PFX "Restore CRC error at "
++ "%08lx (%08x vs %08x)\n", addr, calc, *val);
++
++ DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
++ addr, calc, *val);
++ }
++
++ skip_check:
++ val++;
++ }
++
++ return val;
++}
++
++/* s3c2410_pm_check_restore
++ *
++ * check the CRCs after the restore event and free the memory used
++ * to hold them
++*/
++
++static void s3c2410_pm_check_restore(void)
++{
++ if (crcs != NULL) {
++ s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
++ kfree(crcs);
++ crcs = NULL;
++ }
++}
++
++#else
++
++#define s3c2410_pm_check_prepare() do { } while(0)
++#define s3c2410_pm_check_restore() do { } while(0)
++#define s3c2410_pm_check_store() do { } while(0)
++
++#endif
++
++/* helper functions to save and restore register state */
++
++void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
++{
++ for (; count > 0; count--, ptr++) {
++ ptr->val = __raw_readl(ptr->reg);
++ }
++}
++
++/* s3c2410_pm_do_restore
++ *
++ * restore the system from the given list of saved registers
++ *
++ * Note, we do not use DBG() in here, as the system may not have
++ * restore the UARTs state yet
++*/
++
++void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
++{
++ for (; count > 0; count--, ptr++) {
++ __raw_writel(ptr->val, ptr->reg);
++ }
++}
++
++/* s3c2410_pm_do_save_phy
++ *
++ * save register of system
++ *
++ * Note, I made this function to support driver with ioremap.
++ * If you want to use this function, you should to input as first parameter
++ * struct sleep_save_phy type
++*/
++
++void s3c2410_pm_do_save_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count)
++{
++ void __iomem *target_reg;
++ struct resource *res;
++ u32 reg_size;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ reg_size = res->end - res->start + 1;
++ target_reg = ioremap(res->start,reg_size);
++
++ for (; count > 0; count--, ptr++) {
++ ptr->val = readl(target_reg + (ptr->reg));
++ }
++}
++
++/* s3c2410_pm_do_restore_phy
++ *
++ * restore register of system
++ *
++ * Note, I made this function to support driver with ioremap.
++ * If you want to use this function, you should to input as first parameter
++ * struct sleep_save_phy type
++*/
++
++void s3c2410_pm_do_restore_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count)
++{
++ void __iomem *target_reg;
++ struct resource *res;
++ u32 reg_size;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ reg_size = res->end - res->start + 1;
++ target_reg = ioremap(res->start,reg_size);
++
++ for (; count > 0; count--, ptr++) {
++ writel(ptr->val, (target_reg + ptr->reg));
++ }
++}
++
++/* s3c2410_pm_do_restore_core
++ *
++ * similar to s3c2410_pm_do_restore_core
++ *
++ * WARNING: Do not put any debug in here that may effect memory or use
++ * peripherals, as things may be changing!
++*/
++
++static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
++{
++ for (; count > 0; count--, ptr++) {
++ __raw_writel(ptr->val, ptr->reg);
++ }
++}
++
++/* s3c2410_pm_show_resume_irqs
++ *
++ * print any IRQs asserted at resume time (ie, we woke from)
++*/
++
++static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
++ unsigned long mask)
++{
++ int i;
++
++ which &= ~mask;
++
++ for (i = 0; i <= 31; i++) {
++ if ((which) & (1L<<i)) {
++ DBG("IRQ %d asserted at resume\n", start+i);
++ }
++ }
++}
++
++#if 0
++extern int s3c_irqext_type(unsigned int irq, unsigned int type);
++extern void s3c_irqext_unmaskack(unsigned int irqno);
++#endif
++
++static void s3c6410_pm_configure_extint(void)
++{
++
++ /* for each of the external interrupts (EINT0..EINT15) we
++ * need to check wether it is an external interrupt source,
++ * and then configure it as an input if it is not
++ */
++
++ gpio_set_pin(S3C_GPN10, S3C_GPN10_EXTINT10);
++ gpio_pullup(S3C_GPN10, 2);
++ udelay(50);
++
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 20)) |
++ (S3C_EXTINT_FALLEDGE << 20), S3C_EINTCON0);
++
++ __raw_writel(1UL << (IRQ_EINT10 - IRQ_EINT0), S3C_EINTPEND);
++ __raw_writel(__raw_readl(S3C_EINTMASK)&~(1UL << (IRQ_EINT10 - IRQ_EINT0)), S3C_EINTMASK);
++
++ __raw_writel((0x0fffffff&~(3<<9)), S3C_EINT_MASK);
++}
++
++void (*pm_cpu_prep)(void);
++void (*pm_cpu_sleep)(void);
++
++#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
++
++/* s3c2410_pm_enter
++ *
++ * central control for sleep/resume process
++*/
++
++static int s3c6410_pm_enter(suspend_state_t state)
++{
++ unsigned long regs_save[16];
++ unsigned int tmp;
++
++ /* ensure the debug is initialised (if enabled) */
++
++ if (state != PM_SUSPEND_MEM) {
++ printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
++ return -EINVAL;
++ }
++
++ /* prepare check area if configured */
++ s3c2410_pm_check_prepare();
++
++ /* store the physical address of the register recovery block */
++ s3c2410_sleep_save_phys = virt_to_phys(regs_save);
++
++ /* save all necessary core registers not covered by the drivers */
++ s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
++ s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
++ s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
++ s3c2410_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save));
++
++ /* ensure INF_REG0 has the resume address */
++ __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C_INFORM0);
++
++ /* set the irq configuration for wake */
++ s3c6410_pm_configure_extint();
++
++ /* call cpu specific preperation */
++
++ pm_cpu_prep();
++
++ /* flush cache back to ram */
++
++ flush_cache_all();
++
++ s3c2410_pm_check_store();
++
++ __raw_writel(0xffffffff, S3C_VIC0INTENCLEAR);
++ __raw_writel(0xffffffff, S3C_VIC1INTENCLEAR);
++ __raw_writel(0xffffffff, S3C_VIC0SOFTINTCLEAR);
++ __raw_writel(0xffffffff, S3C_VIC1SOFTINTCLEAR);
++
++ __raw_writel(1, S3C_OSC_STABLE);
++ __raw_writel(1, S3C_PWR_STABLE);
++
++ /* Set WFI instruction to SLEEP mode */
++
++ tmp = __raw_readl(S3C_PWR_CFG);
++ tmp &= ~(0x60<<0);
++ tmp |= (0x3<<5);
++ __raw_writel(tmp, S3C_PWR_CFG);
++
++ tmp = __raw_readl(S3C_SLEEP_CFG);
++ tmp &= ~(0x61<<0);
++ __raw_writel(tmp, S3C_SLEEP_CFG);
++
++ /* Clear WAKEUP_STAT register for next wakeup -jc.lee */
++ /* If this register do not be cleared, Wakeup will be failed */
++ tmp = __raw_readl(S3C_WAKEUP_STAT);
++ __raw_writel(tmp, S3C_WAKEUP_STAT);
++
++ /* ALL sub block "ON" before enterring sleep mode - EVT0 bug*/
++ __raw_writel(0xffffff00, S3C_NORMAL_CFG);
++
++ /* Open all clock gate to enter sleep mode - EVT0 bug*/
++ __raw_writel(0xffffffff, S3C_HCLK_GATE);
++ __raw_writel(0xffffffff, S3C_PCLK_GATE);
++ __raw_writel(0xffffffff, S3C_SCLK_GATE);
++
++
++ /* s3c2410_cpu_save will also act as our return point from when
++ * we resume as it saves its own register state, so use the return
++ * code to differentiate return from save and return from sleep */
++
++ if (s3c2410_cpu_save(regs_save) == 0) {
++ flush_cache_all();
++ pm_cpu_sleep();
++ }
++
++ /* restore the cpu state */
++ cpu_init();
++
++ /* restore the system state */
++ s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
++ s3c2410_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save));
++ s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
++ s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
++
++ tmp = __raw_readl(S3C_EINTPEND);
++ __raw_writel(tmp, S3C_EINTPEND);
++
++ DBG("post sleep, preparing to return\n");
++
++ s3c2410_pm_check_restore();
++
++ /* ok, let's return from sleep */
++ DBG("S3C6400 PM Resume (post-restore)\n");
++ return 0;
++}
++
++
++/*
++ * Called after processes are frozen, but before we shut down devices.
++ */
++static int s3c6410_pm_prepare(suspend_state_t state)
++{
++ return 0;
++}
++
++/*
++ * Called after devices are re-setup, but before processes are thawed.
++ */
++static int s3c6410_pm_finish(suspend_state_t state)
++{
++ return 0;
++}
++
++static int s3c6410_pm_set_target(suspend_state_t state)
++{
++ return 0;
++}
++
++/*
++ * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
++ */
++static struct platform_suspend_ops s3c6410_pm_ops = {
++ .set_target = s3c6410_pm_set_target,
++ .prepare = s3c6410_pm_prepare,
++ .enter = s3c6410_pm_enter,
++ .finish = s3c6410_pm_finish,
++ .valid = suspend_valid_only_mem,
++};
++
++/* s3c2410_pm_init
++ *
++ * Attach the power management functions. This should be called
++ * from the board specific initialisation if the board supports
++ * it.
++*/
++
++int __init s3c2410_pm_init(void)
++{
++ printk("S3C6410 Power Management, (c) 2008 Samsung Electronics\n");
++
++ suspend_set_ops(&s3c6410_pm_ops);
++ return 0;
++}
+diff --git a/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c b/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
+new file mode 100644
+index 0000000..2e10ea9
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
+@@ -0,0 +1,202 @@
++/*
++ * linux/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
++ *
++ * CPU frequency scaling for S3C64XX
++ *
++ * Copyright (C) 2008 Samsung Electronics
++ *
++ * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/cpufreq.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/system.h>
++
++#define USE_FREQ_TABLE
++#define USE_DVS
++#define VERY_HI_RATE 532*1000*1000
++#define APLL_GEN_CLK 532*1000 //khz
++#define KHZ_T 1000
++
++#define MPU_CLK "fclk"
++
++/* definition for power setting function */
++extern int set_power(unsigned int freq);
++extern int ltc3714_init(void);
++
++#define ARM_LE 0
++#define INT_LE 1
++
++/* frequency */
++static struct cpufreq_frequency_table s3c6410_freq_table[] = {
++ {APLL_GEN_CLK, APLL_GEN_CLK},
++ {APLL_GEN_CLK, APLL_GEN_CLK/2},
++ {APLL_GEN_CLK, APLL_GEN_CLK/4},
++ {0, CPUFREQ_TABLE_END},
++};
++
++int s3c6410_verify_speed(struct cpufreq_policy *policy)
++{
++ struct clk * mpu_clk;
++
++ if (policy->cpu)
++ return -EINVAL;
++#ifdef USE_FREQ_TABLE
++ return cpufreq_frequency_table_verify(policy, s3c6410_freq_table);
++#else
++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
++ policy->cpuinfo.max_freq);
++ mpu_clk = clk_get(NULL, MPU_CLK);
++ if (IS_ERR(mpu_clk))
++ return PTR_ERR(mpu_clk);
++
++ policy->min = clk_round_rate(mpu_clk, policy->min * KHZ_T) / KHZ_T;
++ policy->max = clk_round_rate(mpu_clk, policy->max * KHZ_T) / KHZ_T;
++
++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
++ policy->cpuinfo.max_freq);
++
++ clk_put(mpu_clk);
++
++ return 0;
++#endif
++}
++
++unsigned int s3c6410_getspeed(unsigned int cpu)
++{
++ struct clk * mpu_clk;
++ unsigned long rate;
++
++ if (cpu)
++ return 0;
++
++ mpu_clk = clk_get(NULL, MPU_CLK);
++ if (IS_ERR(mpu_clk))
++ return 0;
++ rate = clk_get_rate(mpu_clk) / KHZ_T;
++
++ clk_put(mpu_clk);
++
++ return rate;
++}
++
++static int s3c6410_target(struct cpufreq_policy *policy,
++ unsigned int target_freq,
++ unsigned int relation)
++{
++ struct clk * mpu_clk;
++ struct cpufreq_freqs freqs;
++ int ret = 0;
++ unsigned long arm_clk;
++ unsigned int index;
++
++ mpu_clk = clk_get(NULL, MPU_CLK);
++ if (IS_ERR(mpu_clk))
++ return PTR_ERR(mpu_clk);
++
++ freqs.old = s3c6410_getspeed(0);
++#ifdef USE_FREQ_TABLE
++ if (cpufreq_frequency_table_target(policy, s3c6410_freq_table, target_freq, relation, &index))
++ return -EINVAL;
++
++ arm_clk = s3c6410_freq_table[index].frequency;
++ freqs.new = arm_clk;
++#else
++ freqs.new = clk_round_rate(mpu_clk, target_freq * KHZ_T) / KHZ_T;
++#endif
++ freqs.cpu = 0;
++
++ if(freqs.new == freqs.old)
++ return 0;
++
++ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
++#ifdef USE_DVS
++ if(freqs.new < freqs.old){
++ /* frequency scaling */
++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T);
++ if(ret != 0)
++ printk("frequency scaling error\n");
++ /* voltage scaling */
++ set_power(freqs.new);
++ }else{
++ /* voltage scaling */
++ set_power(freqs.new);
++
++ /* frequency scaling */
++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T);
++ if(ret != 0)
++ printk("frequency scaling error\n");
++ }
++
++
++#else
++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T);
++ if(ret != 0)
++ printk("frequency scaling error\n");
++
++#endif
++ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
++ clk_put(mpu_clk);
++ return ret;
++}
++
++static int __init s3c6410_cpu_init(struct cpufreq_policy *policy)
++{
++#ifdef USE_DVS
++ ltc3714_init();
++#endif
++ struct clk* mpu_clk;
++
++ mpu_clk = clk_get(NULL, MPU_CLK);
++ if (IS_ERR(mpu_clk))
++ return PTR_ERR(mpu_clk);
++
++ if (policy->cpu != 0)
++ return -EINVAL;
++ policy->cur = policy->min = policy->max = s3c6410_getspeed(0);
++#ifdef USE_FREQ_TABLE
++ cpufreq_frequency_table_get_attr(s3c6410_freq_table, policy->cpu);
++#else
++ policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / KHZ_T;
++ policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / KHZ_T;
++#endif
++ policy->cpuinfo.transition_latency = KHZ_T; //1us
++
++
++ clk_put(mpu_clk);
++#ifdef USE_FREQ_TABLE
++ return cpufreq_frequency_table_cpuinfo(policy, s3c6410_freq_table);
++#else
++ return 0;
++#endif
++}
++
++static struct cpufreq_driver s3c6410_driver = {
++ .flags = CPUFREQ_STICKY,
++ .verify = s3c6410_verify_speed,
++ .target = s3c6410_target,
++ .get = s3c6410_getspeed,
++ .init = s3c6410_cpu_init,
++ .name = "s3c6410",
++};
++
++static int __init s3c6410_cpufreq_init(void)
++{
++ return cpufreq_register_driver(&s3c6410_driver);
++}
++
++arch_initcall(s3c6410_cpufreq_init);
+diff --git a/arch/arm/plat-s3c64xx/s3c64xx-dvfs.c b/arch/arm/plat-s3c64xx/s3c64xx-dvfs.c
+new file mode 100644
+index 0000000..06c4b75
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/s3c64xx-dvfs.c
+@@ -0,0 +1,547 @@
++/*
++ * Copyright (c) 2008 Samsung Electronics
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C64xx DVFS interface with LTC3714 DCDC convertor power
++ * 2008.02.28. basic scheme update to here
++*/
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/fcntl.h>
++
++#include <asm/uaccess.h>
++#include <asm/io.h>
++
++#include <linux/stat.h>
++#include <linux/proc_fs.h>
++
++#include <linux/delay.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/gpio.h>
++#include "s3c64xx-dvfs.h"
++
++#define DEV_NAME "s3c64xx-dvfs"
++#define DEV_MAJOR 240
++
++#define XTAL 12*1000*1000 /* Clock source 12Mhz */
++#define MAX_APLL_RATIO 7 /* See S3C6400 user manual 3-7 */
++#define MAX_HCLK2_RATIO 7 /* See S3C6400 user manual 0-1 */
++#define Mhz 1000*1000
++
++#define SUPPORT_PROC_FS
++
++#ifdef SUPPORT_PROC_FS
++struct proc_dir_entry *proc_root_fp = NULL;
++struct proc_dir_entry *proc_voltage_fp = NULL;
++struct proc_dir_entry *proc_freq_fp = NULL;
++struct proc_dir_entry *proc_step_fp = NULL;
++
++char proc_voltage_str[PAGE_SIZE-80] = { 0,};
++char proc_freq_str[PAGE_SIZE-80] = { 0,};
++char proc_step_str[PAGE_SIZE-80] = { 0,};
++#endif
++
++/* it's depend on DCDC regurator specification
++ * if change parts, you must be change table and configuration*/
++static const unsigned int voltage_table[32] = {
++ 1750, 1700, 1650, 1600, 1550, 1500, 1450, 1400,
++ 1350, 1300, 1250, 1200, 1150, 1100, 1050, 1000,
++ 975, 950, 925, 900, 875, 850, 825, 800,
++ 775, 750, 725, 700, 675, 650, 625, 600,
++};
++
++#define NUMBER_OF_STEP 4
++
++/*Frequency step define section */
++#define MDIV 0
++#define PDIV 1
++#define SDIV 2
++#define ARM_RATIO 3
++#define HCLK_RATIO 4
++#define DVFS MDIV
++
++#define ARM_VOLT_STEP 0
++#define INT_VOLT_STEP 1
++#define FREQ_STEP 2
++
++static const unsigned int pll_mps_table[][5] = {
++ {533, 6, 1, 0, 1}, /* step 0 ARM:(533 / 1)=533 MHz ,HCLKx2:266 HCLK: 133*/
++ {400, 6, 1, 0, 1}, /* step 1 ARM:(400 / 1)=400 MHz ,HCLKx2:266 HCLK: 133*/
++ {400, 6, 1, 1, 1}, /* step 2 ARM:(400 / 2)=200 MHz ,HCLKx2:266 HCLK: 133*/
++ {400, 6, 1, 3, 2}, /* step 3 ARM:(400 / 4)=100 MHz ,HCLKx2:133 HCLK: 66 ==> careful linked device*/
++/* {MDIV, PDIV, SDIV, ARM RATIO, HCLKx2 RATIO } */
++};
++
++static const unsigned int dvfs_step[NUMBER_OF_STEP][3] = {
++ { 1200 , 1200, 0}, /* ARM 1.2Volt, INT 1.2V, pll mode 0 533-133*/
++ { 1000 , 1000, 1}, /* ARM 1.2Volt, INT 1.2V, pll mode 2 200-133*/
++ { 950 , 1000, 2}, /* ARM 1.2Volt, INT 1.2V, pll mode 2 200-133*/
++ { 900 , 1000, 2}, /* ARM 1.2Volt, INT 1.2V, pll mode 3 100- 66*/
++/* {Voltage, Frequency_STEP} */
++};
++
++static int previous_dvfs_step;
++
++static s3c_dvfs_info dvfs_info;
++
++static void set_dvfs_gpio(void)
++{
++ /* We can control the voltage of ARM core and Internal block by setting GPIO */
++ /* GPN(11~15). First of all, we should set these gpio to output mode. */
++ /* GPIO configuration */
++ GPIO_CFG(LTC3714_DATA1, LTC3714_OUTP1);
++ GPIO_CFG(LTC3714_DATA2, LTC3714_OUTP2);
++ GPIO_CFG(LTC3714_DATA3, LTC3714_OUTP3);
++ GPIO_CFG(LTC3714_DATA4, LTC3714_OUTP4);
++ GPIO_CFG(LTC3714_DATA5, LTC3714_OUTP5);
++
++ /* Pull-up/down disable */
++ GPIO_PULLUP(LTC3714_DATA1, 0x0);
++ GPIO_PULLUP(LTC3714_DATA2, 0x0);
++ GPIO_PULLUP(LTC3714_DATA3, 0x0);
++ GPIO_PULLUP(LTC3714_DATA4, 0x0);
++ GPIO_PULLUP(LTC3714_DATA5, 0x0);
++
++
++ /* Latch control signal*/
++ /* CORE_REG_OE: GPL9, ARM_REG_OE: GPL8, INT_REG_LE: GPL10*/
++ GPIO_CFG(ARM_LE , ARM_LE_OUTP);
++ GPIO_CFG(DVS_OE , DVS_OE_OUTP);
++ GPIO_CFG(INT_LE , INT_LE_OUTP);
++
++ GPIO_PULLUP(ARM_LE, 0x0);
++ GPIO_PULLUP(DVS_OE, 0x0);
++ GPIO_PULLUP(INT_LE, 0x0);
++
++}
++
++/* Set LTC3714 voltage regulator */
++/* Input : pwr : 1(ARM), 2(Internal), 3(Both) */
++/* voltage : 1mV step */
++static int set_ltc3714(unsigned int pwr, unsigned int voltage)
++{
++ int position = 0;
++
++ if(voltage > voltage_table[0] || voltage < voltage_table[31]) {
++ printk("[ERROR]: voltage value over limits!!!");
++ return -EINVAL;
++ }
++
++ if(voltage > voltage_table[16]) { // 1750 ~ 1000 mV
++ for(position = 15; position >= 0; position --) {
++ if(voltage_table[position] == voltage) break;
++ }
++
++ }
++ else if(voltage >= voltage_table[31]) { //975 ~ 600 mV
++ for(position = 31; position >= 16; position --) {
++ if(voltage_table[position] == voltage) break;
++ }
++ }
++ else {
++ printk("[error]: Can't find adquate voltage table list value\n");
++ return -EINVAL;
++ }
++
++ printk("Founded postion :[%d] \n",position);
++
++ position &=0x1f;
++
++ __raw_writel((__raw_readl(S3C_GPNDAT)&~(0x1f<<11))|(position<<11), S3C_GPNDAT);
++
++ if(pwr == ARM_VOLT_STEP) { //ARM Voltage Control => ARM_REG_LE => Output H => Data Changed
++
++ CONTROl_SET(ARM_LE, 0x1);
++ udelay(10);
++ CONTROl_SET(ARM_LE, 0x0);
++ } else if(pwr == INT_VOLT_STEP) { // INT Voltage Control
++ CONTROl_SET(INT_LE, 0x1);
++ udelay(10);
++ CONTROl_SET(INT_LE, 0x0);
++ } else {
++ printk("[error]: set_ltc3714, check mode [pwr] value\n");
++ return -EINVAL;
++ }
++
++ return 0;
++
++}
++
++/* Set CLK_DIV0 register with specific APLL divider value*/
++static int set_freq_divider(unsigned int clk_source , unsigned int val)
++{
++ unsigned int tmp;
++
++ if (clk_source == ARM_RATIO){
++ if(val > MAX_APLL_RATIO) {
++ printk(KERN_ERR "Freq divider value(APLL_RATIO) is out of spec\n");
++ printk(KERN_ERR "APLL_RATIO : 0~7\n");
++ return -EINVAL;
++ }
++ dvfs_info.freq_divider = (val + 1);
++ tmp = __raw_readl(ARM_CLK_DIV)&~ARM_DIV_MASK;
++ tmp |= val<<ARM_DIV_RATIO_BIT;
++ __raw_writel(tmp, ARM_CLK_DIV);
++ } else if (clk_source == HCLK_RATIO){
++ if(val > MAX_HCLK2_RATIO) {
++ printk(KERN_ERR "Freq divider value is out of spec\n");
++ printk(KERN_ERR "HCLK_PostDivider RATIO : 0,1 \n");
++ return -EINVAL;
++ }
++ /* it's only for setting the HCLK or system Clock */
++ tmp = __raw_readl(ARM_CLK_DIV) & ~HCLK_DIV_MASK;
++ tmp |= (val<<HCLK_DIV_RATIO_BIT);
++ __raw_writel(tmp, ARM_CLK_DIV);
++ } else {
++ printk(KERN_ERR " It's wrong clock post divider path \n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* Set APLL P,M,S value to make specific CPU frequency*/
++/* Only support Async mode */
++static int set_pll(unsigned int freq_level)
++{
++ unsigned int val,err;
++
++ if (freq_level < NUMBER_OF_STEP ){
++
++ err = set_freq_divider(ARM_RATIO, pll_mps_table[freq_level][ARM_RATIO]);
++ if(err)
++ return err;
++
++ err = set_freq_divider(HCLK_RATIO, pll_mps_table[freq_level][HCLK_RATIO]);
++ if(err)
++ return err;
++/*
++ it's only guarantee for chaiging PLL on S3C64xx
++ if you want to change dynamic freq. you must check stability of system
++*/
++ val = PLL_CALC_VAL(pll_mps_table[freq_level][MDIV],\
++ pll_mps_table[freq_level][PDIV],\
++ pll_mps_table[freq_level][SDIV]);
++ __raw_writel(val, ARM_PLL_CON);
++/*
++ it does not guarantee for chaiging PLL on S3C2443,S3C2450 and S3C2416
++ but we guide to set DVFS or divide arm clock output
++*/
++
++ }
++ else{
++ printk("It's wrong DFS %d range \n",freq_level);
++ }
++
++ return 0;
++}
++
++/* Other modules can use this function to change power status */
++/* Especially, ARM Dynamic power interface can control DVFS by accessing this */
++int set_dvfs_step(unsigned int step)
++{
++ int err;
++
++ if(step >= NUMBER_OF_STEP) {
++ printk(KERN_ERR "DVFS step is out of range(0 ~ %2d)\n",NUMBER_OF_STEP-1);
++ return -EINVAL;
++ }
++ //printk("set_dvfs_step[%d]\n",step);
++
++ if(previous_dvfs_step < step) { // decreasing CPU freq & Voltage
++ /* CPU Frequency control */
++ err = set_pll(dvfs_step[step][FREQ_STEP]);
++
++ /* CPU voltage control */
++ dvfs_info.pwr_type = ARM_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][ARM_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ }
++
++
++ dvfs_info.pwr_type = INT_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][INT_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ }
++
++ } else if(previous_dvfs_step > step) { // increasing CPU freq & Voltage
++
++ /* CPU voltage control */
++ dvfs_info.pwr_type = ARM_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][ARM_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ }
++
++ dvfs_info.pwr_type = INT_VOLT_STEP;
++ dvfs_info.new_voltage = dvfs_step[step][INT_VOLT_STEP];
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++ if(err == 0){
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ }
++
++ /* CPU Frequency control */
++ err = set_pll(dvfs_step[step][FREQ_STEP]);
++
++ } else {
++ }
++ previous_dvfs_step = step;
++
++ return 0;
++}
++
++EXPORT_SYMBOL(set_dvfs_step);
++
++int s3c_dvfs_open(struct inode *inode, struct file *filp)
++{
++ int num = MINOR(inode->i_rdev);
++
++ printk("s3c_dvfs_open -> minor : %d\n", num);
++
++ return 0;
++}
++
++ssize_t s3c_dvfs_read(struct file *filp, char *buf, size_t count,
++ loff_t *f_pos)
++{
++ return 0;
++}
++
++ssize_t s3c_dvfs_write(struct file *filp, const char *buf, size_t count,
++ loff_t *f_pos)
++{
++ return 0;
++}
++
++int s3c_dvfs_ioctl(struct inode *inode, struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ int err, size;
++
++ if(_IOC_TYPE(cmd) != DVFS_IOCTL_MAGIC) return -EINVAL;
++ if(_IOC_NR(cmd) >= DVFS_MAXNR) return -EINVAL;
++
++ size = _IOC_SIZE(cmd);
++
++ switch(cmd) {
++ case DVFS_ON:
++ break;
++ case DVFS_OFF:
++ break;
++ case DVFS_GET_STATUS:
++ err=copy_to_user((void *) arg, (const void *) &dvfs_info, (unsigned long) size);
++ break;
++ case DVFS_SET_STATUS:
++ err=copy_from_user((void *) &dvfs_info, (const void *) arg, size);
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++
++ if(err != 0) return err;
++
++ if(dvfs_info.pwr_type == ARM_VOLT_STEP) {
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ } else if(dvfs_info.pwr_type == INT_VOLT_STEP) {
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ } else {
++ }
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++int s3c_dvfs_release(struct inode *inode, struct file *filp)
++{
++ printk("s3c_dvfs_release \n");
++ return 0;
++}
++
++struct file_operations s3c_dvfs_fops =
++{
++ .owner = THIS_MODULE,
++ .read = s3c_dvfs_read,
++ .write = s3c_dvfs_write,
++ .ioctl = s3c_dvfs_ioctl,
++ .open = s3c_dvfs_open,
++ .release = s3c_dvfs_release,
++};
++
++#ifdef SUPPORT_PROC_FS
++int read_proc_voltage(char *page, char **start, off_t off,
++ int count, int *eof, void *data_unused)
++{
++ char *buf;
++
++ buf = page;
++ buf += sprintf(buf, "ARM = [%d]mV, Internal = [%d]mV\n", dvfs_info.curr_voltage_arm,dvfs_info.curr_voltage_internal);
++
++ return buf - page;
++}
++
++int write_proc_voltage(struct file *file, const char __user *buffer,
++ unsigned long count, void *data)
++{
++ int len, err;
++ char *realdata;
++
++ realdata = (char *) data;
++
++ if(copy_from_user(realdata, buffer, count))
++ return -EFAULT;
++
++ realdata[count] = '\0';
++ len = strlen(realdata);
++ if(realdata[len - 1] == '\n')
++ realdata[--len] = 0;
++
++ dvfs_info.new_voltage = simple_strtoul(realdata, NULL, 10);
++
++ err = set_ltc3714(dvfs_info.pwr_type, dvfs_info.new_voltage);
++
++ if(err == 0) {
++ if(dvfs_info.pwr_type == ARM_VOLT_STEP) {
++ dvfs_info.curr_voltage_arm = dvfs_info.new_voltage;
++ } else if(dvfs_info.pwr_type == INT_VOLT_STEP) {
++ dvfs_info.curr_voltage_internal = dvfs_info.new_voltage;
++ } else {
++ }
++ }
++
++ return count;
++}
++
++int read_proc_freq(char *page, char **start, off_t off,
++ int count, int *eof, void *data_unused)
++{
++ char *buf;
++ unsigned int arm_freq;
++
++ arm_freq = GET_ARM_CLOCK(XTAL);
++ dvfs_info.freq_divider = READ_ARM_DIV;
++ dvfs_info.curr_freq = arm_freq/dvfs_info.freq_divider;
++
++ buf = page;
++ buf += sprintf(buf, "Freq = [%d]MHz\n", dvfs_info.curr_freq/1000000);
++
++ return buf - page;
++}
++
++int write_proc_freq(struct file *file, const char __user *buffer,
++ unsigned long count, void *data)
++{
++ int len, tmp, err;
++ char *realdata;
++
++ realdata = (char *) data;
++
++ if(copy_from_user(realdata, buffer, count))
++ return -EFAULT;
++
++ realdata[count] = '\0';
++ len = strlen(realdata);
++ if(realdata[len - 1] == '\n')
++ realdata[--len] = 0;
++ tmp = simple_strtoul(realdata, NULL, 10);
++
++ printk("level %d \n",tmp);
++
++ err = set_freq_divider(ARM_RATIO, tmp);
++ if(err){
++ printk("level err %d \n",err);
++ return err;
++ }
++
++ return count;
++}
++
++int write_proc_step(struct file *file, const char __user *buffer, unsigned long count, void *data)
++{
++ int len, tmp, err;
++ char *realdata;
++
++ realdata = (char *) data;
++
++ if(copy_from_user(realdata, buffer, count))
++ return -EFAULT;
++ realdata[count] = '\0';
++ len = strlen(realdata);
++ if(realdata[len - 1] == '\n')
++ realdata[--len] = 0;
++ tmp = simple_strtoul(realdata, NULL, 10);
++
++ err = set_dvfs_step(tmp);
++
++ return count;
++}
++
++#endif
++
++int s3c_dvfs_init(void)
++{
++ int result;
++
++ /* Initialize structure */
++ previous_dvfs_step = -1; /* 1st initial operating*/
++ set_dvfs_gpio();
++ set_dvfs_step(0); // Set Maximum or default initial performance set
++ CONTROl_SET(DVS_OE, 0x1); /* Just open target power voltage*/
++ result = register_chrdev(DEV_MAJOR, DEV_NAME, &s3c_dvfs_fops);
++
++ if(result < 0)
++ return result;
++
++#ifdef SUPPORT_PROC_FS
++ proc_root_fp = proc_mkdir("dvfs", 0);
++
++ proc_voltage_fp = create_proc_entry("voltage", S_IFREG | S_IRWXU, proc_root_fp);
++ if(proc_voltage_fp) {
++ proc_voltage_fp->data = proc_voltage_str;
++ proc_voltage_fp->read_proc = read_proc_voltage;
++ proc_voltage_fp->write_proc = write_proc_voltage;
++ }
++
++ proc_freq_fp = create_proc_entry("frequency", S_IFREG | S_IRWXU, proc_root_fp);
++ if(proc_freq_fp) {
++ proc_freq_fp->data = proc_freq_str;
++ proc_freq_fp->read_proc = read_proc_freq;
++ proc_freq_fp->write_proc = write_proc_freq;
++ }
++
++ proc_step_fp = create_proc_entry("step", S_IFREG | S_IWUSR, proc_root_fp);
++ if(proc_step_fp) {
++ proc_step_fp->data = proc_step_str;
++ proc_step_fp->read_proc = NULL;
++ proc_step_fp->write_proc = write_proc_step;
++ }
++#endif
++
++ return 0;
++}
++
++void s3c_dvfs_exit(void)
++{
++ unregister_chrdev(DEV_MAJOR, DEV_NAME);
++ remove_proc_entry("voltage", proc_root_fp);
++ remove_proc_entry("frequency", proc_root_fp);
++ remove_proc_entry("step", proc_root_fp);
++ remove_proc_entry("dvfs", 0);
++}
++
++module_init(s3c_dvfs_init);
++module_exit(s3c_dvfs_exit);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("S3C64xx DVFS Driver");
++MODULE_AUTHOR("Jongpill.Lee, <boyko.lee@samsung.com>");
+diff --git a/arch/arm/plat-s3c64xx/s3c64xx-dvfs.h b/arch/arm/plat-s3c64xx/s3c64xx-dvfs.h
+new file mode 100644
+index 0000000..2c37236
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/s3c64xx-dvfs.h
+@@ -0,0 +1,66 @@
++/*
++ 2008.04.14. All of AP are merged single application and definitin
++ in order to be matcing dvs and dfs concept
++ These are confirm on SMDK2450, SMDK2416,SMDK6400,SMDK6410
++*/
++#ifndef __S3C64XXDVFS_H_
++#define __S3C64XXDVFS_H_
++
++#define DVFS_IOCTL_MAGIC 'd'
++
++typedef struct {
++ unsigned int pwr_type; //ARM:ARMV_STEP, INT:INTV_STEP
++ unsigned int curr_voltage_arm; //ARM core voltage
++ unsigned int curr_voltage_internal; //Internal block voltage
++ unsigned int new_voltage;
++ unsigned int curr_freq;
++ unsigned int freq_divider; // APLL_RATIO + 1
++ unsigned int size;
++} s3c_dvfs_info;
++
++#define DVFS_ON _IO(DVFS_IOCTL_MAGIC, 0)
++#define DVFS_OFF _IO(DVFS_IOCTL_MAGIC, 1)
++#define DVFS_GET_STATUS _IOR(DVFS_IOCTL_MAGIC, 2, s3c_dvfs_info)
++#define DVFS_SET_STATUS _IOW(DVFS_IOCTL_MAGIC, 3, s3c_dvfs_info)
++
++#define DVFS_MAXNR 4
++
++/* Board dependency SIGNAL and GPIO configuration */
++#include <asm/arch-s3c2410/regs-s3c-clock.h>
++
++#define ARM_LE S3C_GPL8
++#define DVS_OE S3C_GPL9
++#define INT_LE S3C_GPL10
++
++#define CONTROl_SET(pin,to) gpio_set_value(pin, to);
++#define ARM_LE_OUTP S3C_GPL8_OUTP
++#define DVS_OE_OUTP S3C_GPL9_OUTP
++#define INT_LE_OUTP S3C_GPL10_OUTP
++
++#define LTC3714_DATA1 S3C_GPN11
++#define LTC3714_DATA2 S3C_GPN12
++#define LTC3714_DATA3 S3C_GPN13
++#define LTC3714_DATA4 S3C_GPN14
++#define LTC3714_DATA5 S3C_GPN15
++
++#define LTC3714_OUTP1 S3C_GPN11_OUTP
++#define LTC3714_OUTP2 S3C_GPN12_OUTP
++#define LTC3714_OUTP3 S3C_GPN13_OUTP
++#define LTC3714_OUTP4 S3C_GPN14_OUTP
++#define LTC3714_OUTP5 S3C_GPN15_OUTP
++
++#define GPIO_CFG(pin,to) gpio_set_pin((pin),(to))
++#define GPIO_PULLUP(pin,to) gpio_pullup((pin),(to))
++
++#define ARM_PLL_CON S3C_APLL_CON
++#define ARM_CLK_DIV S3C_CLK_DIV0
++#define ARM_DIV_RATIO_BIT 0
++#define ARM_DIV_MASK (0xf<<ARM_DIV_RATIO_BIT)
++#define HCLK_DIV_RATIO_BIT 9
++#define HCLK_DIV_MASK (0x7<<HCLK_DIV_RATIO_BIT)
++
++#define READ_ARM_DIV ((__raw_readl(ARM_CLK_DIV)&ARM_DIV_MASK) + 1)
++#define PLL_CALC_VAL(MDIV,PDIV,SDIV) ((1<<31)|(MDIV)<<16 |(PDIV)<<8 |(SDIV))
++#define GET_ARM_CLOCK(baseclk) s3c6400_get_pll(__raw_readl(S3C_APLL_CON),baseclk)
++
++#endif //__S3CDVS_H_
+diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/plat-s3c64xx/sleep.S
+new file mode 100644
+index 0000000..a646cbe
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/sleep.S
+@@ -0,0 +1,165 @@
++/* linux/arch/arm/plat-s3c24xx/sleep.S
++ *
++ * Copyright (c) 2004 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C2410 Power Manager (Suspend-To-RAM) support
++ *
++ * Based on PXA/SA1100 sleep code by:
++ * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
++ * Cliff Brake, (c) 2001
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/linkage.h>
++#include <asm/assembler.h>
++#include <asm/hardware.h>
++#include <asm/arch/map.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-clock.h>
++#include <asm/arch/regs-mem.h>
++#include <asm/plat-s3c/regs-serial.h>
++
++/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
++ * reset the UART configuration, only enable if you really need this!
++*/
++//#define CONFIG_DEBUG_RESUME
++
++ .text
++
++ /* s3c2410_cpu_save
++ *
++ * save enough of the CPU state to allow us to re-start
++ * pm.c code. as we store items like the sp/lr, we will
++ * end up returning from this function when the cpu resumes
++ * so the return value is set to mark this.
++ *
++ * This arangement means we avoid having to flush the cache
++ * from this code.
++ *
++ * entry:
++ * r0 = pointer to save block
++ *
++ * exit:
++ * r0 = 0 => we stored everything
++ * 1 => resumed from sleep
++ */
++
++ENTRY(s3c2410_cpu_save)
++ stmfd sp!, { r4 - r12, lr }
++
++ @@ store co-processor registers
++
++ mrc p15, 0, r4, c13, c0, 0 @ PID
++ mrc p15, 0, r5, c3, c0, 0 @ Domain ID
++ mrc p15, 0, r6, c2, c0, 0 @ translation table base address
++ mrc p15, 0, r7, c1, c0, 0 @ control register
++
++ stmia r0, { r4 - r13 }
++
++ mov r0, #0
++ ldmfd sp, { r4 - r12, pc }
++
++ @@ return to the caller, after having the MMU
++ @@ turned on, this restores the last bits from the
++ @@ stack
++resume_with_mmu:
++ mov r0, #1
++ ldmfd sp!, { r4 - r12, pc }
++
++ .ltorg
++
++ @@ the next bits sit in the .data segment, even though they
++ @@ happen to be code... the s3c2410_sleep_save_phys needs to be
++ @@ accessed by the resume code before it can restore the MMU.
++ @@ This means that the variable has to be close enough for the
++ @@ code to read it... since the .text segment needs to be RO,
++ @@ the data segment can be the only place to put this code.
++
++ .data
++
++ .global s3c2410_sleep_save_phys
++s3c2410_sleep_save_phys:
++ .word 0
++
++
++ /* sleep magic, to allow the bootloader to check for an valid
++ * image to resume to. Must be the first word before the
++ * s3c2410_cpu_resume entry.
++ */
++
++ .word 0x2bedf00d
++
++ /* s3c2410_cpu_resume
++ *
++ * resume code entry for bootloader to call
++ *
++ * we must put this code here in the data segment as we have no
++ * other way of restoring the stack pointer after sleep, and we
++ * must not write to the code segment (code is read-only)
++ */
++
++ENTRY(s3c2410_cpu_resume)
++ mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
++ msr cpsr_c, r0
++
++ @@ load UART to allow us to print the two characters for
++ @@ resume debug
++
++ mov r2, #S3C24XX_PA_UART & 0xff000000
++ orr r2, r2, #S3C24XX_PA_UART & 0xff000
++
++#if 0
++ /* SMDK2440 LED set */
++ mov r14, #S3C24XX_PA_GPIO
++ ldr r12, [ r14, #0x54 ]
++ bic r12, r12, #3<<4
++ orr r12, r12, #1<<7
++ str r12, [ r14, #0x54 ]
++#endif
++
++#ifdef CONFIG_DEBUG_RESUME
++ mov r3, #'L'
++ strb r3, [ r2, #S3C2410_UTXH ]
++1001:
++ ldrb r14, [ r3, #S3C2410_UTRSTAT ]
++ tst r14, #S3C2410_UTRSTAT_TXE
++ beq 1001b
++#endif /* CONFIG_DEBUG_RESUME */
++
++ mov r1, #0
++ mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
++ mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
++
++ ldr r0, s3c2410_sleep_save_phys @ address of restore block
++ ldmia r0, { r4 - r13 }
++
++ mcr p15, 0, r4, c13, c0, 0 @ PID
++ mcr p15, 0, r5, c3, c0, 0 @ Domain ID
++ mcr p15, 0, r6, c2, c0, 0 @ translation table base
++
++#ifdef CONFIG_DEBUG_RESUME
++ mov r3, #'R'
++ strb r3, [ r2, #S3C2410_UTXH ]
++#endif
++
++ ldr r2, =resume_with_mmu
++ mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc
++ nop @ second-to-last before mmu
++ mov pc, r2 @ go back to virtual address
++
++ .ltorg
+diff --git a/arch/arm/plat-s3c64xx/time-s3c64xx.c b/arch/arm/plat-s3c64xx/time-s3c64xx.c
+new file mode 100644
+index 0000000..55a463a
+--- /dev/null
++++ b/arch/arm/plat-s3c64xx/time-s3c64xx.c
+@@ -0,0 +1,259 @@
++/* linux/arch/arm/mach-s3c64xx/time.c
++ *
++ * Copyright (C) 2006 Samsung Electronics
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++
++#include <asm/system.h>
++#include <asm/leds.h>
++#include <asm/mach-types.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/arch/map.h>
++#include <asm/plat-s3c/regs-timer.h>
++#include <asm/arch/regs-irq.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/mach/time.h>
++
++#include <asm/plat-s3c24xx/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++static unsigned long timer_startval;
++static unsigned long timer_usec_ticks;
++static unsigned long max_buffer_cnt;
++unsigned long timerclock;
++unsigned long s3c_latch;
++
++//#define T32_PROBE_TEST
++
++#define TIMER_USEC_SHIFT 16
++#define DEFAULT_TIMER_VAL 0xffffffff
++#define REPROGRAM_SET_FLAG 1
++#define REPROGRAM_UNSET_FLAG 0
++
++/* Global variable for Dynamic Tick */
++
++#ifdef CONFIG_NO_IDLE_HZ
++static unsigned long initial_match;
++static int match_postponed;
++#endif
++
++/* we use the shifted arithmetic to work out the ratio of timer ticks
++ * to usecs, as often the peripheral clock is not a nice even multiple
++ * of 1MHz.
++ *
++ * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
++ * for the current HZ value of 200 without producing overflows.
++ *
++ * Original patch by Dimitry Andric, updated by Ben Dooks
++*/
++
++static inline unsigned long
++timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
++{
++ unsigned long den = pclk / 1000;
++
++ return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
++}
++
++static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
++{
++ unsigned long res;
++
++ res = ticks * timer_usec_ticks;
++ res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
++
++ return res >> TIMER_USEC_SHIFT;
++}
++
++static unsigned long s3c_gettimeoffset (void)
++{
++ unsigned long timer_val;
++ unsigned long tdone;
++ timer_val = __raw_readl(S3C_TCNTO(4));
++ tdone = timer_startval - timer_val;
++
++ return timer_ticks_to_usec(tdone);
++}
++
++static inline irqreturn_t _s3c_timer_interrupt(int irq, void *dev_id)
++{
++ write_seqlock(&xtime_lock);
++#ifdef CONFIG_NO_IDLE_HZ
++ if(match_postponed){
++ match_postponed = REPROGRAM_UNSET_FLAG;
++ __raw_writel(initial_match, S3C_TCNTB(4));
++ }
++#endif
++ timer_tick();
++ write_sequnlock(&xtime_lock);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t
++s3c_timer_interrupt(int irq, void *dev_id)
++{
++
++ _s3c_timer_interrupt(irq, dev_id);
++ __raw_writel((0x1f & __raw_readl(S3C_TINT_CSTAT)) | S3C_TINT_CSTAT_T4INT, S3C_TINT_CSTAT);
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction s3c_timer_irq = {
++ .name = "S3C Timer Tick",
++ .flags = IRQF_DISABLED | IRQF_TIMER,
++ .handler = s3c_timer_interrupt,
++};
++
++static void s3c_timer_setup (void)
++{
++ unsigned long tcon;
++ unsigned long tcnt;
++ unsigned long tcfg1;
++ unsigned long tcfg0;
++ unsigned long pclk;
++
++ struct clk *clk;
++
++#ifdef T32_PROBE_TEST
++ gpio_direction_output(S3C_GPF13);
++#endif
++
++ tcnt = DEFAULT_TIMER_VAL; /* default value for tcnt */
++
++ tcfg1 = __raw_readl(S3C_TCFG1);
++ tcfg0 = __raw_readl(S3C_TCFG0);
++
++ clk = clk_get(NULL, "timers");
++ if (IS_ERR(clk))
++ panic("failed to get clock for system timer");
++
++ clk_enable(clk);
++
++ pclk = clk_get_rate(clk);
++ timerclock = (pclk / ((PRESCALER + 1)*DIVIDER));
++ s3c_latch = ((timerclock + HZ / 2) / HZ);
++
++ timer_usec_ticks = timer_mask_usec_ticks(((PRESCALER + 1)*DIVIDER), pclk);
++
++ tcfg1 &= ~S3C_TCFG1_MUX4_MASK;
++ tcfg1 |= S3C_TCFG1_MUX4_DIV1;
++
++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK;
++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT;
++
++ max_buffer_cnt = (unsigned long)(DEFAULT_TIMER_VAL / s3c_latch);
++
++ tcnt = (timerclock / HZ) - 1;
++
++ __raw_writel(tcfg1, S3C_TCFG1);
++ __raw_writel(tcfg0, S3C_TCFG0);
++
++ timer_startval = tcnt;
++ __raw_writel(tcnt, S3C_TCNTB(4));
++
++ /* ensure timer is stopped... */
++
++ tcon = __raw_readl(S3C_TCON);
++ tcon &= ~(7<<20);
++ tcon |= S3C_TCON_T4RELOAD;
++ tcon |= S3C_TCON_T4MANUALUPD;
++
++ __raw_writel(tcon, S3C_TCON);
++ __raw_writel(tcnt, S3C_TCNTB(4));
++
++ printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
++ tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
++
++ /* start the timer running */
++ tcon |= S3C_TCON_T4START;
++ tcon &= ~S3C_TCON_T4MANUALUPD;
++
++ __raw_writel(tcon, S3C_TCON);
++
++ /* timer4 interrupt enable */
++ __raw_writel(__raw_readl(S3C_TINT_CSTAT) | S3C_TINT_CSTAT_T4INTEN, S3C_TINT_CSTAT);
++
++}
++
++#ifdef CONFIG_NO_IDLE_HZ
++static int s3c_dyn_tick_enable_disable(void)
++{
++ /* nothing to do*/
++ return 0;
++}
++
++static void s3c_dyn_tick_reprogram(unsigned long ticks)
++{
++ unsigned long timer_buff_val;
++
++ if(ticks > 1){
++ initial_match = __raw_readl(S3C_TCNTB(4));
++ timer_buff_val = (initial_match + (ticks * s3c_latch));
++ if(timer_buff_val & ~(DEFAULT_TIMER_VAL))
++ timer_buff_val = max_buffer_cnt;
++ __raw_writel(timer_buff_val,S3C_TCNTB(4));
++
++ match_postponed = REPROGRAM_SET_FLAG;
++ }
++}
++
++static irqreturn_t s3c_dyn_tick_handler(int irq, void *dev_id)
++{
++ if (match_postponed){
++ match_postponed = REPROGRAM_UNSET_FLAG;
++ __raw_writel(initial_match,S3C_TCNTB(4));
++ if((unsigned long)(initial_match - __raw_readl(S3C_TCNTB(4))) <= 0)
++ return s3c_timer_interrupt(irq,dev_id);
++ }
++
++ return IRQ_NONE;
++}
++
++static struct dyn_tick_timer s3c_dyn_tick = {
++ .enable = s3c_dyn_tick_enable_disable,
++ .disable = s3c_dyn_tick_enable_disable,
++ .reprogram = s3c_dyn_tick_reprogram,
++ .handler = s3c_dyn_tick_handler,
++};
++
++#endif
++
++static void __init s3c_timer_init (void)
++{
++ s3c_timer_setup();
++ setup_irq(IRQ_TIMER4, &s3c_timer_irq);
++}
++
++struct sys_timer s3c_timer = {
++ .init = s3c_timer_init,
++ .offset = s3c_gettimeoffset,
++ .resume = s3c_timer_setup,
++#ifdef CONFIG_NO_IDLE_HZ
++ .dyn_tick = &s3c_dyn_tick,
++#endif
++};
+diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
+new file mode 100644
+index 0000000..b2de828
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/Kconfig
+@@ -0,0 +1,24 @@
++# arch/arm/plat-s5pc1xx/Kconfig
++#
++# Licensed under GPLv2
++
++config PLAT_S5PC1XX
++ bool "S5PC1XX Platform support"
++ depends on ARCH_S3C2410 && CPU_S5PC100
++ default y if CPU_S5PC100
++ help
++ Support for S5PC100 Samsung Mobile CPU based systems.
++
++if PLAT_S5PC1XX
++config S5PC1XX_DMA
++ bool "S5PC1XX DMA support"
++ depends on CPU_S5PC100
++ help
++ S5PC100 DMA support. This is needed for drivers like sound which
++ use the S5PC100's DMA system to move data to and from the
++ peripheral blocks.
++endif
++
++
++
++
+diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
+new file mode 100644
+index 0000000..80bbff5
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/Makefile
+@@ -0,0 +1,26 @@
++# arch/arm/plat-s3c64xx/Makefile
++#
++# Copyright 2007 Simtec Electronics
++#
++# Licensed under GPLv2
++
++obj-y :=
++obj-m :=
++obj-n :=
++obj- :=
++
++
++# Core files
++
++obj-y += ../plat-s3c24xx/cpu.o
++obj-$(CONFIG_PLAT_S5PC1XX) += irq-pl192.o
++obj-y += ../plat-s3c24xx/devs.o
++obj-$(CONFIG_PLAT_S5PC1XX) += time-s5pc1xx.o
++obj-y += clock.o
++obj-y += ../plat-s3c24xx/gpio.o
++obj-$(CONFIG_PLAT_S5PC1XX) += gpio.o
++
++# Architecture dependant builds
++
++#obj-$(CONFIG_S5PC1XX_DMA) += dma-pl330.o dma-pl330-microcode.c
++obj-$(CONFIG_MACH_SMDK) += ../plat-s3c24xx/common-smdk.o
+diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
+new file mode 100644
+index 0000000..b778d32
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/clock.c
+@@ -0,0 +1,467 @@
++/* linux/arch/arm/plat-s5pc1xx/clock.c
++ *
++ * Copyright (c) 2008-2009 Samsung Electronics
++ *
++ * S5PC1XX Core clock control support
++ *
++ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
++ **
++ ** Copyright (C) 2004 ARM Limited.
++ ** Written by Deep Blue Solutions Limited.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/sysdev.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/clk.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/arch/regs-clock.h>
++#include <asm/arch/regs-gpio.h>
++
++#include <asm/plat-s5p/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++/* clock information */
++
++static LIST_HEAD(clocks);
++
++DEFINE_MUTEX(clocks_mutex);
++
++/* enable and disable calls for use with the clk struct */
++
++static int clk_null_enable(struct clk *clk, int enable)
++{
++ return 0;
++}
++
++/* Clock API calls */
++
++struct clk *clk_get(struct device *dev, const char *id)
++{
++ struct clk *p;
++ struct clk *clk = ERR_PTR(-ENOENT);
++ int idno;
++
++ if (dev == NULL || dev->bus != &platform_bus_type)
++ idno = -1;
++ else
++ idno = to_platform_device(dev)->id;
++
++ mutex_lock(&clocks_mutex);
++
++ list_for_each_entry(p, &clocks, list) {
++ if (p->id == idno &&
++ strcmp(id, p->name) == 0 &&
++ try_module_get(p->owner)) {
++ clk = p;
++ break;
++ }
++ }
++
++ /* check for the case where a device was supplied, but the
++ * clock that was being searched for is not device specific */
++
++ if (IS_ERR(clk)) {
++ list_for_each_entry(p, &clocks, list) {
++ if (p->id == -1 && strcmp(id, p->name) == 0 &&
++ try_module_get(p->owner)) {
++ clk = p;
++ break;
++ }
++ }
++ }
++
++ mutex_unlock(&clocks_mutex);
++ return clk;
++}
++
++void clk_put(struct clk *clk)
++{
++ module_put(clk->owner);
++}
++
++int clk_enable(struct clk *clk)
++{
++ if (IS_ERR(clk) || clk == NULL)
++ return -EINVAL;
++
++ clk_enable(clk->parent);
++
++ mutex_lock(&clocks_mutex);
++
++ if ((clk->usage++) == 0)
++ (clk->enable)(clk, 1);
++
++ mutex_unlock(&clocks_mutex);
++ return 0;
++}
++
++void clk_disable(struct clk *clk)
++{
++ if (IS_ERR(clk) || clk == NULL)
++ return;
++
++ mutex_lock(&clocks_mutex);
++
++ if ((--clk->usage) == 0)
++ (clk->enable)(clk, 0);
++
++ mutex_unlock(&clocks_mutex);
++ clk_disable(clk->parent);
++}
++
++
++unsigned long clk_get_rate(struct clk *clk)
++{
++ if (IS_ERR(clk))
++ return 0;
++
++ if (clk->rate != 0)
++ return clk->rate;
++
++ if (clk->get_rate != NULL)
++ return (clk->get_rate)(clk);
++
++ if (clk->parent != NULL)
++ return clk_get_rate(clk->parent);
++
++ return clk->rate;
++}
++
++long clk_round_rate(struct clk *clk, unsigned long rate)
++{
++ if (!IS_ERR(clk) && clk->round_rate)
++ return (clk->round_rate)(clk, rate);
++
++ return rate;
++}
++
++int clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ int ret;
++
++ if (IS_ERR(clk))
++ return -EINVAL;
++
++ mutex_lock(&clocks_mutex);
++ ret = (clk->set_rate)(clk, rate);
++ mutex_unlock(&clocks_mutex);
++
++ return ret;
++}
++
++struct clk *clk_get_parent(struct clk *clk)
++{
++ return clk->parent;
++}
++
++int clk_set_parent(struct clk *clk, struct clk *parent)
++{
++ int ret = 0;
++
++ if (IS_ERR(clk))
++ return -EINVAL;
++
++ mutex_lock(&clocks_mutex);
++
++ if (clk->set_parent)
++ ret = (clk->set_parent)(clk, parent);
++
++ mutex_unlock(&clocks_mutex);
++
++ return ret;
++}
++
++EXPORT_SYMBOL(clk_get);
++EXPORT_SYMBOL(clk_put);
++EXPORT_SYMBOL(clk_enable);
++EXPORT_SYMBOL(clk_disable);
++EXPORT_SYMBOL(clk_get_rate);
++EXPORT_SYMBOL(clk_round_rate);
++EXPORT_SYMBOL(clk_set_rate);
++EXPORT_SYMBOL(clk_get_parent);
++EXPORT_SYMBOL(clk_set_parent);
++
++
++void inline s3c_clk_enable (uint clocks, uint enable, ulong gate_reg)
++{
++ unsigned long clkcon;
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ clkcon = __raw_readl(gate_reg);
++ clkcon &= ~clocks;
++
++ if (enable)
++ clkcon |= clocks;
++
++ __raw_writel(clkcon, gate_reg);
++
++ local_irq_restore(flags);
++}
++
++
++
++/* base clocks */
++
++struct clk clk_xtal = {
++ .name = "xtal",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_arm= {
++ .name = "armclk",
++ .id = -1,
++};
++
++struct clk clk_hd0 = {
++ .name = "hclkd0",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_pd0 = {
++ .name = "pclkd0",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_hd1 = {
++ .name = "hclkd1",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_pd1 = {
++ .name = "pclkd1",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++#if 0
++
++struct clk clk_xtal = {
++ .name = "xtal",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_mpll = {
++ .name = "mpll",
++ .id = -1,
++};
++
++
++struct clk clk_epll = {
++ .name = "epll",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++
++};
++
++struct clk clk_f = {
++ .name = "fclk",
++ .id = -1,
++ .rate = 0,
++ .parent = &clk_mpll,
++ .ctrlbit = 0,
++};
++
++struct clk clk_h = {
++ .name = "hclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_p = {
++ .name = "pclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++
++struct clk clk_hx2 = {
++ .name = "hclkx2",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_s = {
++ .name = "sclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_u = {
++ .name = "uclk",
++ .id = -1,
++ .rate = 0,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_48m = {
++ .name = "clk48m",
++ .id = -1,
++ .rate = 48*1000*1000,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++struct clk clk_27m = {
++ .name = "clk27m",
++ .id = -1,
++ .rate = 27*1000*1000,
++ .parent = NULL,
++ .ctrlbit = 0,
++};
++
++#endif
++
++
++/* initialise the clock system */
++
++int s5pc1xx_register_clock(struct clk *clk)
++{
++ clk->owner = THIS_MODULE;
++
++ if (clk->enable == NULL)
++ clk->enable = clk_null_enable;
++
++ /* add to the list of available clocks */
++
++ mutex_lock(&clocks_mutex);
++ list_add(&clk->list, &clocks);
++ mutex_unlock(&clocks_mutex);
++
++ return 0;
++}
++
++int s5pc1xx_register_clocks(struct clk **clks, int nr_clks)
++{
++ int fails = 0;
++
++ for (; nr_clks > 0; nr_clks--, clks++) {
++ if (s5pc1xx_register_clock(*clks) < 0)
++ fails++;
++ }
++
++ return fails;
++}
++
++/* initalise all the clocks */
++
++int __init s5pc1xx_setup_clocks(unsigned long xtal,
++ unsigned long armclk,
++ unsigned long hclkd0,
++ unsigned long pclkd0,
++ unsigned long hclkd1,
++ unsigned long pclkd1)
++{
++ printk(KERN_INFO "S5PC1XX Clocks, (c) 2008 Samssung Electronics\n");
++
++ /* initialise the main system clocks */
++ clk_xtal.rate = xtal;
++ clk_arm.rate = armclk;
++ clk_hd0.rate = hclkd0;
++ clk_pd0.rate = pclkd0;
++ clk_hd1.rate = hclkd1;
++ clk_pd1.rate = pclkd1;
++
++ /* assume uart clocks are correctly setup */
++
++ /* register our clocks */
++
++ if (s5pc1xx_register_clock(&clk_xtal) < 0)
++ printk(KERN_ERR "failed to register master xtal\n");
++
++ if (s5pc1xx_register_clock(&clk_arm) < 0)
++ printk(KERN_ERR "failed to register arm clock\n");
++
++ if (s5pc1xx_register_clock(&clk_hd0) < 0)
++ printk(KERN_ERR "failed to register cpu hclkd0\n");
++
++ if (s5pc1xx_register_clock(&clk_pd0) < 0)
++ printk(KERN_ERR "failed to register cpu pclkd0\n");
++
++ if (s5pc1xx_register_clock(&clk_hd1) < 0)
++ printk(KERN_ERR "failed to register cpu hclkd1\n");
++
++ if (s5pc1xx_register_clock(&clk_pd1) < 0)
++ printk(KERN_ERR "failed to register cpu pclkd1\n");
++#if 0
++
++ if (s5pc1xx_register_clock(&clk_epll) < 0)
++ printk(KERN_ERR "failed to register epll clock\n");
++
++ /* register hclkx2 */
++ if (s5pc1xx_register_clock(&clk_hx2) < 0)
++ printk(KERN_ERR "failed to register cpu hclkx2\n");
++
++ if (s5pc1xx_register_clock(&clk_s) < 0)
++ printk(KERN_ERR "failed to register cpu pclk\n");
++
++ if (s5pc1xx_register_clock(&clk_u) < 0)
++ printk(KERN_ERR "failed to register cpu uclk\n");
++
++ if (s5pc1xx_register_clock(&clk_48m) < 0)
++ printk(KERN_ERR "failed to register cpu uclk\n");
++
++ if (s5pc1xx_register_clock(&clk_27m) < 0)
++ printk(KERN_ERR "failed to register cpu uclk\n");
++
++#endif
++ return 0;
++}
++
+diff --git a/arch/arm/plat-s5pc1xx/dma-pl330-microcode.c b/arch/arm/plat-s5pc1xx/dma-pl330-microcode.c
+new file mode 100644
+index 0000000..0ac5dc3
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/dma-pl330-microcode.c
+@@ -0,0 +1,278 @@
++
++
++/*---------------------- Primitive functions -------------*/
++/* DMAMOV CCR, ... */
++static void encodeDmaMoveChCtrl(void)
++{
++
++}
++
++/* DMAMOV SAR, uStAddr
++ * DMAMOV DAR, uStAddr */
++static void encodeDmaMove(bool bSrcDir, u32 uStAddr)
++{
++
++}
++
++/* DMAMOV SAR, uStAddr */
++static void encodeDmaMoveSRC(u32 uStAddr)
++{
++
++}
++
++/* DMAMOV DAR, uStAddr */
++static void encodeDmaMoveDST(u32 uStAddr)
++{
++
++}
++
++/* DMAMOV CCR, ... */
++static void encodeDmaMoveCCR(u32 uStAddr)
++{
++
++}
++
++/* DMALD, DMALDS, DMALDB */
++static void encodeDmaLoad(void)
++{
++
++}
++
++/* DMALDPS, DMALDPB (Load Peripheral) */
++static void encodeDmaLoadPeri(void)
++{
++
++}
++
++/* DMAST, DMASTS, DMASTB */
++static void encodeDmaStore(void)
++{
++
++}
++
++/* DMASTPS, DMASTPB (Store and notify Peripheral) */
++static void encodeDmaStorePeri(void)
++{
++
++}
++
++/* DMASTZ */
++static void encodeDmaStoreZero(void)
++{
++
++}
++
++/* DMALP */
++static void encodeDmaLoop(u8 uLoopCnt, u8 uIteration)
++{
++
++}
++
++/* DMALPFE */
++static void encodeDmaLoopForever(u8 uLoopCnt)
++{
++
++}
++
++/* DMALPEND, DMALPENDS, DMALPENDB */
++static void encodeDmaLoopEnd(u8 uLoopCnt)
++{
++
++}
++
++/* DMAWFP, DMAWFPS, DMAWFPB (Wait For Peripheral) */
++static void encodeDmaWaitForPeri(void)
++{
++
++}
++
++/* DMAWFE (Wait For Event) */
++static void encodeDmaWaitForEvent(u8 uEventNum) // 0~31
++{
++
++}
++
++/* DMAFLUSHP (Flush and notify Peripheral) */
++static void encodeDmaFlushPeri(void)
++{
++
++}
++
++/* DMAEND */
++static void encodeDmaEnd(void)
++{
++
++}
++
++/* DMAADDH (Add Halfword) */
++static void encodeDmaAddHalfword(bool bSrcDir, u16 uStAddr)
++{
++
++}
++
++/* DMAKILL (Kill) */
++static void encodeDmaKill(void)
++{
++
++}
++
++/* DMANOP (No operation) */
++static void encodeDmaNop(void)
++{
++
++}
++
++
++/* DMARMB (Read Memory Barrier) */
++static void encodeDmaReadMemBarrier(void)
++{
++
++}
++
++/* DMASEV (Send Event) */
++static void encodeDmaSendEvent(u8 uEventNum) // 0~31
++{
++
++}
++
++
++
++/* DMAWMB (Write Memory Barrier) */
++static void encodeDmaWriteMemBarrier(void)
++{
++
++}
++
++/* DMAGO (Go) */
++static void encodeDmaGo(void)
++{
++
++}
++
++/*---------------------- Feature functions -------------*/
++
++/* start_DMA_controller
++ * - start the DMA controller
++ *
++ */
++void start_DMA_controller()
++{
++
++}
++
++
++/* stop_DMA_controller
++ * - stop the DMA controller
++ *
++ */
++void stop_DMA_controller()
++{
++
++}
++
++
++/* start_DMA_channel
++ * - get the DMA channel started
++ *
++ * chanNum the number to be started
++ * sStAddr the address to be set to PC of the DMAC
++ */
++u32 start_DMA_channel(u8 chanNum, u32 uStAddr)
++{
++ return encodeDmaGo(chanNum, uStAddr);
++}
++
++
++/* stop_DMA_channel
++ * - get the DMA channel stopped
++ *
++ * chanNum the number to be stopped
++ */
++void stop_DMA_channel(u8 chanNum)
++{
++
++}
++
++
++/* setup_DMA_start_address
++ * - set the DMA start address
++ *
++ * uStAddr the DMA start address
++ */
++void setup_DMA_start_address(u32 uStAddr)
++{
++ encodeDmaMoveSRC(uStAddr);
++}
++
++
++/* setup_DMA_destination_address
++ * - set the DMA destination address
++ *
++ * uStAddr the DMA destination address
++ */
++void setup_DMA_destination_address(u32 uStAddr)
++{
++ encodeDmaMoveDST(uStAddr);
++}
++
++
++/* setup_DMA_transfer_size
++ * - set the transfer size
++ *
++ * dmaDir the DMA direction
++ * transferSize the size to be transfered
++ */
++void setup_DMA_transfer_size(u8 dmaDir, u32 transferSize)
++{
++
++ encodeDmaLoop(uLoopCnt, uIteration);
++
++ switch(dmaDir) {
++ case DMA_M2M:]
++ encodeDmaLoad();
++ encodeDmaStore();
++ break;
++
++ case DMA_M2P:
++ encodeDmaWaitForPeri();
++ encodeDmaLoad();
++ encodeDmaStorePeri();
++ break;
++
++ case DMA_P2M:
++ encodeDmaWaitForPeri();
++ encodeDmaLoadPeri();
++ encodeDmaStore();
++ break;
++
++ case DMA_P2P:
++ break;
++
++ default:
++ break;
++ }
++
++ encodeDmaLoopEnd(uLoopCnt);
++}
++
++
++/* setup_DMA_control
++ * - set the burst length, burst size, source and destination increment/fixed field
++ *
++ * dcon the value for channel control register
++ */
++void setup_DMA_control(u32 dcon)
++{
++ encodeDmaMoveCCR(dcon);
++}
++
++
++/* register_irq_to_DMA_channel
++ * - register an event with the DMA channel
++ *
++ * uEventNum the event number
++ */
++void register_irq_to_DMA_channel(u8 uEventNum)
++{
++ encodeDmaSendEvent(uEventNum);
++}
+diff --git a/arch/arm/plat-s5pc1xx/dma-pl330.c b/arch/arm/plat-s5pc1xx/dma-pl330.c
+new file mode 100644
+index 0000000..e63134d
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/dma-pl330.c
+@@ -0,0 +1,1601 @@
++/* linux/arch/arm/plat-s3c24xx/dma-pl080.c
++ *
++ * Copyright (c) 2003-2005,2006 Samsung Electronics
++ *
++ * S3C6400 DMA core
++ *
++ * http://www.samsung.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#ifdef CONFIG_S3C_DMA_DEBUG
++#define DEBUG
++#endif
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/sysdev.h>
++#include <linux/slab.h>
++#include <linux/errno.h>
++#include <linux/delay.h>
++
++#include <asm/system.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/mach/dma.h>
++#include <asm/arch/map.h>
++#include <asm/plat-s3c24xx/dma.h>
++
++/* io map for dma */
++static void __iomem *dma_base;
++static struct kmem_cache *dma_kmem;
++
++static int dma_channels;
++struct s3c24xx_dma_selection dma_sel;
++static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
++
++/* dma channel state information */
++struct s3c2410_dma_chan s3c_dma_chans[S3C2410_DMA_CHANNELS];
++s3c_dma_controller_t s3c_dma_cntlrs[S3C_DMA_CONTROLLERS];
++
++#undef pr_debug
++//#define dma_dbg
++
++#ifdef dma_dbg
++#define sh_printk(fmt...) printk( fmt)
++#define pr_debug(fmt...) printk( fmt)
++#else
++#define sh_printk(fmt...)
++#define pr_debug(fmt...)
++#endif
++
++/* debugging functions */
++
++#define BUF_MAGIC (0xcafebabe)
++
++#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
++
++#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
++#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
++#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
++
++#define dbg_showregs(chan) do { } while(0)
++#define dbg_showchan(chan) do { } while(0)
++
++void s3c_dma_dump(int dcon_num, int channel)
++{
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_STATUS);
++ printk("%d dcon_num %d subchnnel INT_STATUS %lx\n", dcon_num, channel, tmp);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS);
++ printk("%d dcon_num %d subchnnel INT_TCSTATUS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_ENBLD_CHANNELS);
++ printk("%d dcon_num %d subchnnel ENBLD_CHANNELS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
++ printk("%d dcon_num %d subchnnel DMAC_CONFIGUARATION %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CSRCADDR(channel));
++ printk("%d dcon_num %d subchnnel SRCADDRESS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CDESTADDR(channel));
++ printk("%d dcon_num %d subchnnel DESTADDRESS %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CLLI(channel));
++ printk("%d dcon_num %d subchnnel LLI %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel));
++ printk("%d dcon_num %d subchnnel CCONTROL0 %lx\n", dcon_num, channel, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL1(channel));
++ printk("%d dcon_num %d subchnnel CCONTROL1 %lx\n", dcon_num, channel, tmp);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel));
++
++ printk("%d dcon_num %d subchnnel CH CONFIGUARATION %lx\n", dcon_num, channel, tmp);
++}
++
++
++/* lookup_dma_channel
++ *
++ * change the dma channel number given into a real dma channel id
++*/
++
++static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
++{
++ if (channel & DMACH_LOW_LEVEL)
++ return &s3c_dma_chans[channel & ~DMACH_LOW_LEVEL];
++ else
++ return dma_chan_map[channel];
++}
++
++/* s3c_dma_stats_timeout
++ *
++ * Update DMA stats from timeout info
++ */
++static void s3c_dma_stats_timeout(struct s3c2410_dma_stats * stats, int val)
++{
++ if (stats == NULL)
++ return;
++
++ if (val > stats->timeout_longest)
++ stats->timeout_longest = val;
++ if (val < stats->timeout_shortest)
++ stats->timeout_shortest = val;
++
++ stats->timeout_avg += val;
++}
++
++void s3c_enable_dmac(unsigned int dcon_num)
++{
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++
++#if DMA_PL330
++ start_DMA_controller();
++#else
++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE);
++#endif
++}
++
++void s3c_disable_dmac(unsigned int dcon_num)
++{
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++
++#if DMA_PL330
++ dma_wrreg(DMA_DBGINST0, (0<<24)|(1<<16)|(m_uChNum<<8)|(0<<0));
++ dma_wrreg(DMA_DBGINST1, 0);
++ dma_wrreg(DMA_DBGCMD, 0); // execute the instruction that the DBGINST0,1 registers contain
++#else
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
++ tmp &= ~S3C_DMA_CONTROLLER_ENABLE;
++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, tmp);
++#endif
++}
++
++void s3c_clear_interrupts (int dcon_num, int channel)
++{
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCCLEAR);
++ tmp |= (1 << channel);
++ dma_wrreg(dma_controller, S3C_DMAC_INT_TCCLEAR, tmp);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR);
++ tmp |= (1 << channel);
++ dma_wrreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR, tmp);
++}
++
++/* s3c_dma_waitforload
++ *
++ * wait for the DMA engine to load a buffer, and update the state accordingly
++ */
++static int s3c_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
++{
++ int timeout = chan->load_timeout;
++ int took;
++
++ pr_debug("%s channel number : %d\n", __FUNCTION__, chan->number);
++
++ if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
++ printk(KERN_ERR
++ "dma%d: s3c_dma_waitforload() called in loadstate %d from line %d\n",
++ chan->number, chan->load_state, line);
++ return 0;
++ }
++
++ if (chan->stats != NULL)
++ chan->stats->loads++;
++
++ while (--timeout > 0) {
++ if ((dma_rdreg(chan->dma_con, S3C_DMAC_ENBLD_CHANNELS)) & (0x1 << chan->number)) {
++ took = chan->load_timeout - timeout;
++ s3c_dma_stats_timeout(chan->stats, took);
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_1LOADED:
++ chan->load_state = S3C2410_DMALOAD_1RUNNING;
++ break;
++
++ default:
++ printk(KERN_ERR
++ "dma%d: unknown load_state in s3c_dma_waitforload() %d\n",
++ chan->number, chan->load_state);
++ }
++
++ return 1;
++ }
++ }
++
++ if (chan->stats != NULL) {
++ chan->stats->timeout_failed++;
++ }
++
++ return 0;
++}
++
++
++/* s3c_dma_loadbuffer
++ *
++ * load a buffer, and update the channel state
++ */
++static inline int s3c_dma_loadbuffer(struct s3c2410_dma_chan *chan,
++ struct s3c2410_dma_buf *buf)
++{
++ unsigned long reload;
++
++ pr_debug("s3c_chan_loadbuffer: loading buffer %p (0x%08lx,0x%06x)\n",
++ buf, (unsigned long) buf->data, buf->size);
++
++ if (buf == NULL) {
++ dmawarn("buffer is NULL\n");
++ return -EINVAL;
++ }
++
++ /* check the state of the channel before we do anything */
++
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
++ dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
++ reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
++ }
++
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
++ dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
++ reload = S3C2410_DCON_AUTORELOAD;
++ }
++
++ writel(buf->data, chan->addr_reg);
++
++ pr_debug("%s: DMA control0 - %08x\n", __FUNCTION__, chan->dcon);
++ pr_debug("%s: DMA control1 - %08x\n", __FUNCTION__, (buf->size / chan->xfer_unit));
++
++#if DMA_PL330
++ setup_DMA_control(chan->dcon);
++ setup_DMA_transfer_size(chan->source, (buf->size / chan->xfer_unit));
++#else
++ dma_wrreg(chan, S3C_DMAC_CxCONTROL0, chan->dcon);
++ dma_wrreg(chan, S3C_DMAC_CxCONTROL1, (buf->size / chan->xfer_unit));
++#endif
++
++ chan->next = buf->next;
++
++ /* update the state of the channel */
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_NONE:
++ chan->load_state = S3C2410_DMALOAD_1LOADED;
++ break;
++
++ case S3C2410_DMALOAD_1RUNNING:
++ chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
++ break;
++
++ default:
++ dmawarn("dmaload: unknown state %d in loadbuffer\n", chan->load_state);
++ break;
++ }
++
++ return 0;
++}
++
++
++/* s3c_dma_call_op
++ *
++ * small routine to call the o routine with the given op if it has been
++ * registered
++ */
++static void s3c_dma_call_op(struct s3c2410_dma_chan * chan, enum s3c2410_chan_op op)
++{
++ if (chan->op_fn != NULL) {
++ (chan->op_fn) (chan, op);
++ }
++}
++
++/* s3c_dma_buffdone
++ *
++ * small wrapper to check if callback routine needs to be called, and
++ * if so, call it
++ */
++static inline void s3c_dma_buffdone(struct s3c2410_dma_chan * chan,
++ struct s3c2410_dma_buf * buf,
++ enum s3c2410_dma_buffresult result)
++{
++ pr_debug("callback_fn will be called=%p, buf=%p, id=%p, size=%d, result=%d\n",
++ chan->callback_fn, buf, buf->id, buf->size, result);
++
++ if (chan->callback_fn != NULL) {
++ (chan->callback_fn) (chan, buf->id, buf->size, result);
++ }
++}
++
++/* s3c_dma_start
++ *
++ * start a dma channel going
++ */
++static int s3c_dma_start(struct s3c2410_dma_chan *chan)
++{
++ unsigned long flags;
++
++ pr_debug("s3c_start_dma: channel number=%d, index=%d\n", chan->number, chan->index);
++
++ local_irq_save(flags);
++
++ if (chan->state == S3C2410_DMA_RUNNING) {
++ pr_debug("s3c_start_dma: already running (%d)\n", chan->state);
++ local_irq_restore(flags);
++ return 0;
++ }
++
++ chan->state = S3C2410_DMA_RUNNING;
++
++ /* check wether there is anything to load, and if not, see
++ * if we can find anything to load
++ */
++
++ if (chan->load_state == S3C2410_DMALOAD_NONE) {
++ if (chan->next == NULL) {
++ printk(KERN_ERR "dma%d: dcon_num has nothing loaded\n", chan->number);
++ chan->state = S3C2410_DMA_IDLE;
++ local_irq_restore(flags);
++ return -EINVAL;
++ }
++
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++
++ dbg_showchan(chan);
++
++ /* enable the channel */
++
++ if (!chan->irq_enabled) {
++ enable_irq(chan->irq);
++ chan->irq_enabled = 1;
++ }
++
++#if DMA_PL330
++ start_DMA_channel();
++#else
++ /* Get the DMA channel started ...*/
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags);
++#endif
++
++ pr_debug("%s:wrote %08lx to S3C_DMAC_CxCONFIGURATION.\n",__FUNCTION__, chan->config_flags);
++
++ /* Start the DMA operation on Peripheral */
++ s3c_dma_call_op(chan, S3C2410_DMAOP_START);
++
++ dbg_showchan(chan);
++
++ /* if we've only loaded one buffer onto the channel, then chec
++ * to see if we have another, and if so, try and load it so when
++ * the first buffer is finished, the new one will be loaded onto
++ * the channel */
++#if 0
++ if (chan->next != NULL) {
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
++
++ if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
++ pr_debug("%s: buff not yet loaded, no more todo\n",
++ __FUNCTION__);
++ } else {
++ chan->load_state = S3C2410_DMALOAD_1RUNNING;
++ s3c2410_dma_loadbuffer(chan, chan->next);
++ }
++
++ } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
++ s3c2410_dma_loadbuffer(chan, chan->next);
++ }
++ }
++#endif
++ local_irq_restore(flags);
++ return 0;
++}
++
++
++/* s3c_dma_canload
++ *
++ * work out if we can queue another buffer into the DMA engine
++ */
++
++#if 0
++static int s3c_dma_canload(struct s3c2410_dma_chan * chan)
++{
++ if (chan->load_state == S3C2410_DMALOAD_NONE || chan->load_state == S3C2410_DMALOAD_1RUNNING)
++ return 1;
++
++ return 0;
++}
++#endif
++
++
++/* s3c2410_dma_enqueue
++ *
++ * queue an given buffer for dma transfer.
++ *
++ * id the device driver's id information for this buffer
++ * data the physical address of the buffer data
++ * size the size of the buffer in bytes
++ *
++ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
++ * is checked, and if set, the channel is started. If this flag isn't set,
++ * then an error will be returned.
++ *
++ * It is possible to queue more than one DMA buffer onto a channel at
++ * once, and the code will deal with the re-loading of the next buffer
++ * when necessary.
++ */
++int s3c2410_dma_enqueue(unsigned int channel, void *id,
++ dma_addr_t data, int size)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++ struct s3c2410_dma_buf *buf;
++ unsigned long flags;
++
++ pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int) data, size);
++
++ buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
++ if (buf == NULL) {
++ printk(KERN_ERR "dma<%d> no memory for buffer\n", channel);
++ return -ENOMEM;
++ }
++
++ pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
++
++ //dbg_showchan(chan);
++
++ buf->next = NULL;
++ buf->data = buf->ptr = data;
++ buf->size = size;
++ buf->id = id;
++ buf->magic = BUF_MAGIC;
++
++ local_irq_save(flags);
++
++ if (chan->curr == NULL) {
++ /* we've got nothing loaded... */
++ pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf);
++
++ chan->curr = buf;
++ chan->end = buf;
++ chan->next = NULL;
++ } else {
++ pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
++ chan->number, __FUNCTION__, buf);
++
++ if (chan->end == NULL) /* In case of flushing */
++ pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
++ chan->number, __FUNCTION__, chan);
++ else {
++ chan->end->next = buf;
++ chan->end = buf;
++ }
++ }
++
++ /* if necessary, update the next buffer field */
++ if (chan->next == NULL)
++ chan->next = buf;
++
++ /* check to see if we can load a buffer */
++ if (chan->state == S3C2410_DMA_RUNNING) {
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ printk(KERN_ERR "dma%d: loadbuffer:"
++ "timeout loading buffer\n", chan->number);
++ dbg_showchan(chan);
++ local_irq_restore(flags);
++ return -EINVAL;
++ }
++ }
++#if 0
++ while (s3c_dma_canload(chan) && chan->next != NULL) {
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++#endif
++ } else if (chan->state == S3C2410_DMA_IDLE) {
++ if (chan->flags & S3C2410_DMAF_AUTOSTART) {
++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START);
++ } else {
++ pr_debug("loading onto stopped channel\n");
++ }
++ }
++
++ local_irq_restore(flags);
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_enqueue);
++
++static inline void s3c_dma_freebuf(struct s3c2410_dma_buf * buf)
++{
++ int magicok = (buf->magic == BUF_MAGIC);
++
++ buf->magic = -1;
++
++ if (magicok) {
++ kmem_cache_free(dma_kmem, buf);
++ } else {
++ printk("s3c_dma_freebuf: buff %p with bad magic\n", buf);
++ }
++}
++
++/* s3c_dma_lastxfer
++ *
++ * called when the system is out of buffers, to ensure that the channel
++ * is prepared for shutdown.
++ */
++static inline void s3c_dma_lastxfer(struct s3c2410_dma_chan *chan)
++{
++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state %d\n", chan->number, chan->load_state);
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_NONE:
++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state : S3C2410_DMALOAD_NONE%d\n", chan->number);
++ break;
++
++ case S3C2410_DMALOAD_1LOADED:
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ /* flag error? */
++ printk(KERN_ERR "dma%d: timeout waiting for load\n", chan->number);
++ return;
++ }
++ break;
++
++ default:
++ pr_debug("dma%d: lastxfer: unhandled load_state %d with no next",
++ chan->number, chan->load_state);
++ return;
++
++ }
++
++ /* hopefully this'll shut the damned thing up after the transfer... */
++ //dma_wrreg(chan, S3C_DMA_DCON, chan->dcon | S3C_DCON_NORELOAD);
++}
++
++
++#define dmadbg2(x...)
++
++static irqreturn_t s3c_dma_irq(int irq, void *devpw)
++{
++ unsigned int channel = 0, dcon_num, i;
++ unsigned long tmp;
++ s3c_dma_controller_t *dma_controller = (s3c_dma_controller_t *) devpw;
++
++ struct s3c2410_dma_chan *chan=NULL;
++ struct s3c2410_dma_buf *buf;
++
++ dcon_num = dma_controller->number;
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS);
++ pr_debug("# s3c_dma_irq: TC status : 0x%x\n", tmp);
++
++ for (i = 0; i < S3C_CHANNELS_PER_DMA; i++) {
++ if (tmp & 0x01) {
++
++ pr_debug("# DMA Controller %d: requestor %d\n", dcon_num, i);
++
++ channel = i;
++ chan = &s3c_dma_chans[channel + dcon_num * S3C_CHANNELS_PER_DMA];
++ pr_debug("# DMA channel number : %d, index : %d\n", chan->number, chan->index);
++
++ buf = chan->curr;
++
++ dbg_showchan(chan);
++
++ /* modify the channel state */
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_1RUNNING:
++ /* TODO - if we are running only one buffer, we probably
++ * want to reload here, and then worry about the buffer
++ * callback */
++
++ chan->load_state = S3C2410_DMALOAD_NONE;
++ break;
++
++ case S3C2410_DMALOAD_1LOADED:
++ /* iirc, we should go back to NONE loaded here, we
++ * had a buffer, and it was never verified as being
++ * loaded.
++ */
++
++ chan->load_state = S3C2410_DMALOAD_NONE;
++ break;
++
++ case S3C2410_DMALOAD_1LOADED_1RUNNING:
++ /* we'll worry about checking to see if another buffer is
++ * ready after we've called back the owner. This should
++ * ensure we do not wait around too long for the DMA
++ * engine to start the next transfer
++ */
++
++ chan->load_state = S3C2410_DMALOAD_1LOADED;
++ break;
++
++ case S3C2410_DMALOAD_NONE:
++ printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
++ chan->number);
++ break;
++
++ default:
++ printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
++ chan->number, chan->load_state);
++ break;
++ }
++
++ if (buf != NULL) {
++ /* update the chain to make sure that if we load any more
++ * buffers when we call the callback function, things should
++ * work properly */
++
++ chan->curr = buf->next;
++ buf->next = NULL;
++
++ if (buf->magic != BUF_MAGIC) {
++ printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
++ chan->number, __FUNCTION__, buf);
++ goto next_channel;
++ }
++
++ s3c_dma_buffdone(chan, buf, S3C2410_RES_OK);
++
++ /* free resouces */
++ s3c_dma_freebuf(buf);
++ } else {
++
++ }
++
++ if (chan->next != NULL) {
++ unsigned long flags;
++
++ switch (chan->load_state) {
++ case S3C2410_DMALOAD_1RUNNING:
++ /* don't need to do anything for this state */
++ break;
++
++ case S3C2410_DMALOAD_NONE:
++ /* can load buffer immediately */
++ break;
++
++ case S3C2410_DMALOAD_1LOADED:
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ /* flag error? */
++ printk(KERN_ERR "dma%d: timeout waiting for load\n",
++ chan->number);
++ goto next_channel;
++ }
++
++ break;
++
++ case S3C2410_DMALOAD_1LOADED_1RUNNING:
++ goto next_channel;
++
++ default:
++ printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
++ chan->number, chan->load_state);
++ goto next_channel;
++ }
++
++ local_irq_save(flags);
++ s3c_dma_loadbuffer(chan, chan->next);
++
++ //shaju added for dbg
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags);
++
++ local_irq_restore(flags);
++
++ } else {
++ s3c_dma_lastxfer(chan);
++
++ /* see if we can stop this channel.. */
++ if (chan->load_state == S3C2410_DMALOAD_NONE) {
++ pr_debug("# DMA CH %d(index:%d): end of transfer, stopping channel (%ld)\n",
++ chan->number, chan->index, jiffies);
++ s3c2410_dma_ctrl(chan->index | DMACH_LOW_LEVEL, S3C2410_DMAOP_STOP);
++ }
++ }
++ }
++
++next_channel:
++ tmp >>= 1;
++
++ }
++
++ s3c_clear_interrupts(chan->dma_con->number, chan->number);
++
++ return IRQ_HANDLED;
++}
++
++static struct s3c2410_dma_chan *s3c_dma_map_channel(int channel);
++
++/* s3c2410_dma_request
++ *
++ * get control of an dma channel
++*/
++
++int s3c2410_dma_request(unsigned int channel,
++ struct s3c2410_dma_client *client,
++ void *dev)
++{
++ struct s3c2410_dma_chan *chan;
++ unsigned long flags;
++ int err;
++
++ pr_debug("DMA CH %d: s3c2410_request_dma: client=%s, dev=%p\n",
++ channel, client->name, dev);
++
++ local_irq_save(flags);
++
++ chan = s3c_dma_map_channel(channel);
++ if (chan == NULL) {
++ local_irq_restore(flags);
++ return -EBUSY;
++ }
++
++ dbg_showchan(chan);
++
++ chan->client = client;
++ chan->in_use = 1;
++
++ chan->dma_con->in_use++;
++
++ if (!chan->irq_claimed) {
++ pr_debug("DMA CH %d: %s : requesting irq %d\n",
++ channel, __FUNCTION__, chan->irq);
++
++ chan->irq_claimed = 1;
++ local_irq_restore(flags);
++
++ err = request_irq(chan->irq, s3c_dma_irq, IRQF_DISABLED,
++ client->name, (void *) chan->dma_con);
++
++ local_irq_save(flags);
++
++ if (err) {
++ chan->in_use = 0;
++ chan->irq_claimed = 0;
++ chan->dma_con->in_use--;
++ local_irq_restore(flags);
++
++ printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
++ client->name, chan->irq, chan->number);
++ return err;
++ }
++
++ chan->irq_enabled = 1;
++
++ /* enable the main dma.. this can be disabled
++ * when main channel use count is 0 */
++ s3c_enable_dmac(chan->dma_con->number);
++ }
++
++ s3c_clear_interrupts(chan->dma_con->number, chan->number);
++ local_irq_restore(flags);
++
++ /* need to setup */
++
++ pr_debug("%s: channel initialised, %p, number:%d, index:%d\n", __FUNCTION__, chan, chan->number, chan->index);
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_request);
++
++/* s3c2410_dma_free
++ *
++ * release the given channel back to the system, will stop and flush
++ * any outstanding transfers, and ensure the channel is ready for the
++ * next claimant.
++ *
++ * Note, although a warning is currently printed if the freeing client
++ * info is not the same as the registrant's client info, the free is still
++ * allowed to go through.
++ */
++int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
++{
++ unsigned long flags;
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++ pr_debug("%s: DMA channel %d will be stopped\n", __FUNCTION__, chan->number);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ local_irq_save(flags);
++
++ if (chan->client != client) {
++ printk(KERN_WARNING
++ "DMA CH %d: possible free from different client (channel %p, passed %p)\n",
++ channel, chan->client, client);
++ }
++
++ /* sort out stopping and freeing the channel */
++
++ if (chan->state != S3C2410_DMA_IDLE) {
++ pr_debug("%s: need to stop dma channel %p\n", __FUNCTION__, chan);
++
++ /* possibly flush the channel */
++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
++ }
++
++ chan->client = NULL;
++ chan->in_use = 0;
++
++ chan->dma_con->in_use--;
++
++ if (chan->irq_claimed)
++ free_irq(chan->irq, (void *)chan->dma_con);
++
++ chan->irq_claimed = 0;
++
++ if (!(channel & DMACH_LOW_LEVEL))
++ dma_chan_map[channel] = NULL;
++
++ local_irq_restore(flags);
++
++ pr_debug("--------------------------------------------\n");
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_free);
++
++/* actively polling for the A bit can block the cpu*/
++void s3c_dma_flush_fifo(struct s3c2410_dma_chan *chan)
++{
++ unsigned long tmp;
++
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++ tmp |= S3C_DMACONFIG_HALT;
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp);
++
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++
++ /*this while loop can be very dangerous..may be put the process to sleep rather than waiting till fifo is drained */
++ while (tmp & S3C_DMACONFIG_ACTIVE) {
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++ }
++}
++
++static int s3c_dma_dostop(struct s3c2410_dma_chan *chan)
++{
++ unsigned long tmp;
++ unsigned long flags;
++
++ pr_debug("%s: DMA Channel No : %d\n", __FUNCTION__, chan->number);
++
++ dbg_showchan(chan);
++
++ local_irq_save(flags);
++
++ s3c_dma_flush_fifo(chan);
++
++ s3c_dma_call_op(chan, S3C2410_DMAOP_STOP);
++
++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
++
++ tmp &= ~S3C_DMACONFIG_CHANNEL_ENABLE;
++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp);
++
++ pr_debug("%s: S3C_DMAC_CxCONFIGURATION : %08x\n", __FUNCTION__, tmp);
++
++ chan->state = S3C2410_DMA_IDLE;
++ chan->load_state = S3C2410_DMALOAD_NONE;
++
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++static void s3c_dma_showchan(struct s3c2410_dma_chan * chan)
++{
++#if 0
++ printk(KERN_DEBUG "dma[%d]: st %d, lst %d, cli %p, dcon %08lx\n",
++ chan->number, chan->state, chan->load_state, chan->client, chan->dcon);
++ printk(KERN_DEBUG "dma[%d]: CSRC=%x, ISRC=%x, STAT=%x, CON=%x, MT=%x\n",
++ chan->number,
++ dma_rdreg(chan, S3C2410_DMA_DCSRC),
++ dma_rdreg(chan, S3C2410_DMA_DISRC),
++ dma_rdreg(chan, S3C2410_DMA_DSTAT),
++ dma_rdreg(chan, S3C2410_DMA_DCON), dma_rdreg(chan, S3C2410_DMA_DMASKTRIG));
++#endif
++}
++
++/* s3c_dma_flush
++ *
++ * stop the channel, and remove all current and pending transfers
++ */
++
++void s3c_waitforstop(struct s3c2410_dma_chan *chan)
++{
++#if 0
++ unsigned long tmp;
++ unsigned int timeout = 0x10000;
++
++ while (timeout-- > 0) {
++ tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
++
++ if (!(tmp & S3C2410_DMASKTRIG_ON))
++ return;
++ }
++
++ pr_debug("dma%d: failed to stop?\n", chan->number);
++#endif
++}
++
++static int s3c_dma_flush(struct s3c2410_dma_chan *chan)
++{
++ struct s3c2410_dma_buf *buf, *next;
++ unsigned long flags;
++
++ pr_debug("%s:\n", __FUNCTION__);
++
++ local_irq_save(flags);
++
++ s3c_dma_showchan(chan);
++
++ if (chan->state != S3C2410_DMA_IDLE) {
++ pr_debug("%s: stopping channel...\n", __FUNCTION__);
++ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
++ }
++
++ buf = chan->curr;
++ if (buf == NULL)
++ buf = chan->next;
++
++ chan->curr = chan->next = chan->end = NULL;
++ chan->load_state = S3C2410_DMALOAD_NONE;
++
++ if (buf != NULL) {
++ for (; buf != NULL; buf = next) {
++ next = buf->next;
++
++ pr_debug("%s: free buffer %p, next %p\n", __FUNCTION__, buf, buf->next);
++
++ s3c_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
++ s3c_dma_freebuf(buf);
++ }
++ }
++ //s3c_dma_waitforstop(chan);
++
++ s3c_dma_showchan(chan);
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++int s3c_dma_started(struct s3c2410_dma_chan *chan)
++{
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ dbg_showchan(chan);
++
++ /* if we've only loaded one buffer onto the channel, then chec
++ * to see if we have another, and if so, try and load it so when
++ * the first buffer is finished, the new one will be loaded onto
++ * the channel */
++
++ if (chan->next != NULL) {
++ if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
++
++ if (s3c_dma_waitforload(chan, __LINE__) == 0) {
++ pr_debug("%s: buff not yet loaded, no more todo\n",
++ __FUNCTION__);
++ } else {
++ chan->load_state = S3C2410_DMALOAD_1RUNNING;
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++
++ } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
++ s3c_dma_loadbuffer(chan, chan->next);
++ }
++ }
++
++ local_irq_restore(flags);
++
++ return 0;
++
++}
++
++int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ switch (op) {
++ case S3C2410_DMAOP_START:
++ return s3c_dma_start(chan);
++
++ case S3C2410_DMAOP_STOP:
++ return s3c_dma_dostop(chan);
++
++ case S3C2410_DMAOP_PAUSE:
++ case S3C2410_DMAOP_RESUME:
++ return -ENOENT;
++
++ case S3C2410_DMAOP_FLUSH:
++ return s3c_dma_flush(chan);
++
++ case S3C2410_DMAOP_STARTED:
++ return s3c_dma_started(chan);
++
++ case S3C2410_DMAOP_TIMEOUT:
++ return 0;
++
++ }
++
++ return -ENOENT; /* unknown, don't bother */
++}
++EXPORT_SYMBOL(s3c2410_dma_ctrl);
++
++
++/* s3c2410_dma_config
++ *
++ * xfersize: size of unit in bytes (1,2,4)
++ * dcon: base value of the DCONx register
++ */
++int s3c2410_dma_config(dmach_t channel,
++ int xferunit,
++ int dcon)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
++ __FUNCTION__, channel, xferunit, dcon);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
++
++ dcon |= chan->dcon & dma_sel.dcon_mask;
++
++ pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
++
++ switch (xferunit) {
++ case 1:
++ dcon |= S3C_DMACONTROL_SRC_WIDTH_BYTE;
++ dcon |= S3C_DMACONTROL_DEST_WIDTH_BYTE;
++ break;
++
++ case 2:
++ dcon |= S3C_DMACONTROL_SRC_WIDTH_HWORD;
++ dcon |= S3C_DMACONTROL_DEST_WIDTH_HWORD;
++ break;
++
++ case 4:
++ dcon |= S3C_DMACONTROL_SRC_WIDTH_WORD;
++ dcon |= S3C_DMACONTROL_DEST_WIDTH_WORD;
++ break;
++
++ default:
++ pr_debug("%s: Bad transfer size %d\n", __FUNCTION__, xferunit);
++ return -EINVAL;
++ }
++
++ pr_debug("%s: DMA Channel control : %08x\n", __FUNCTION__, dcon);
++
++ dcon |= S3C_DMACONTROL_TC_INT_ENABLE;
++ dcon |= chan->control_flags;
++ pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
++
++ /* For DMCCxControl 0 */
++ chan->dcon = dcon;
++
++ /* For DMACCxControl 1 : xferunit means transfer width.*/
++ chan->xfer_unit = xferunit;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_config);
++
++int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
++
++ chan->flags = flags;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_setflags);
++
++
++/* do we need to protect the settings of the fields from
++ * irq?
++ */
++
++int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
++
++ chan->op_fn = rtn;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_set_opfn);
++
++
++int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
++
++ chan->callback_fn = rtn;
++
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
++
++
++/* s3c2410_dma_devconfig
++ *
++ * configure the dma source/destination hardware type and address
++ *
++ * flowctrl: direction of dma flow
++ *
++ * src_per dst_per: dma channel number of src and dst periphreal,
++ *
++ * devaddr: physical address of the source
++ */
++
++int s3c2410_dma_devconfig(int channel,
++ enum s3c2410_dmasrc source,
++ int hwcfg,
++ unsigned long devaddr)
++{
++ unsigned long tmp;
++
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
++ __FUNCTION__, (int)source, hwcfg, devaddr);
++
++ chan->source = source;
++ chan->dev_addr = devaddr;
++
++ switch (source) {
++ case S3C2410_DMASRC_MEM:
++ /* source is Memory : Mem-to-Peri ( Write into FIFO) */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2PER | (chan->map->hw_addr.to) <<
++ S3C_DEST_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ chan->config_flags = tmp;
++
++#if DMA_PL330
++ setup_DMA_destination_address(2, devaddr);
++#else
++ /* TODO : Now, Scatter&Gather DMA NOT supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : Periperal address (destination) */
++ dma_wrreg(chan, S3C_DMAC_CxDESTADDR, devaddr);
++#endif
++ /* source address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxSRCADDR);
++
++ chan->control_flags = S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI ;
++ //chan->control_flags = hwcfg;
++ return 0;
++
++ case S3C2410_DMASRC_HW:
++ /* source is peripheral : Peri-to-Mem ( Read from FIFO) */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_PER2MEM | (chan->map->hw_addr.from) <<
++ S3C_SRC_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ chan->config_flags = tmp;
++
++#if DMA_PL330
++ setup_DMA_start_address(1, devaddr);
++#else
++ /* TODO : Now, Scatter&Gather DMA NOT supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : Periperal address (source) */
++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
++#endif
++ /* destination address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
++
++ chan->control_flags = S3C_DMACONTROL_DEST_INC | S3C_DMACONTROL_SRC_AXI_PERI;
++ //chan->control_flags = hwcfg;
++
++ return 0;
++
++#if 0
++ case S3C_DMA_MEM2MEM:
++ /* source is memory : Memory-to-Mem ( Read/Write) */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ if(chan->map->hw_addr.from == S3C_DMA0_ONENAND_RX) {
++ tmp |= S3C_DMACONFIG_ONENANDMODESRC;
++ }
++
++ chan->config_flags = tmp;
++
++ /* TODO : Now, Scatter&Gather DMA NOT YET supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : memory/onenand address (source) */
++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
++
++ /* destination address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
++
++ chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_INC
++ | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4);
++ //chan->control_flags = hwcfg;
++
++ return 0;
++#else
++ case S3C_DMA_MEM2MEM:
++ /* this is temporary for G3D */
++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE;
++
++ chan->config_flags = tmp;
++
++ /* TODO : Now, Scatter&Gather DMA NOT YET supported */
++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
++
++ /* devaddr : memory/onenand address (source) */
++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
++
++ /* destination address : memory(buffer) address */
++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
++
++ chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI
++ | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4);
++ //chan->control_flags = hwcfg;
++
++ return 0;
++#endif
++
++ case S3C_DMA_PER2PER:
++ printk("Peripheral-to-Peripheral DMA NOT YET implemented !! \n");
++ return -EINVAL;
++
++ default:
++ printk(KERN_ERR "DMA CH :%d - invalid source type ()\n", channel);
++ printk("Unsupported DMA configuration from the device driver using DMA driver \n");
++ return -EINVAL;
++ }
++
++}
++
++EXPORT_SYMBOL(s3c2410_dma_devconfig);
++
++
++/*
++ * s3c2410_dma_getposition
++ * returns the current transfer points for the dma source and destination
++ */
++int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
++{
++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
++
++ if (chan == NULL)
++ return -EINVAL;
++
++ if (src != NULL)
++ *src = dma_rdreg(chan, S3C_DMAC_CxSRCADDR);
++
++ if (dst != NULL)
++ *dst = dma_rdreg(chan, S3C_DMAC_CxDESTADDR);
++
++ return 0;
++}
++
++EXPORT_SYMBOL(s3c2410_dma_getposition);
++
++
++/* system device class */
++#ifdef CONFIG_PM
++static int s3c_dma_suspend (struct sys_device *dev, pm_message_t state)
++{
++ return 0;
++}
++
++static int s3c_dma_resume (struct sys_device *dev)
++{
++ return 0;
++}
++#else
++#define s3c_dma_suspend NULL
++#define s3c_dma_resume NULL
++#endif /* CONFIG_PM */
++
++struct sysdev_class dma_sysclass = {
++ set_kset_name("s3c24xx-dma"),
++ .suspend = s3c_dma_suspend,
++ .resume = s3c_dma_resume,
++};
++
++/* kmem cache implementation */
++
++static void s3c_dma_cache_ctor(struct kmem_cache *c, void *p)
++{
++ memset(p, 0, sizeof(struct s3c2410_dma_buf));
++}
++
++
++void dma_test (int dcon_num, int channel)
++{
++ int tmp;
++
++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
++#if 0
++ sh_printk("writing to channel %d subch %d \n", dcon_num, channel);
++ sh_printk("main channel %d irq %d regs_base %x\n", dma_controller->number, dma_controller->irq,
++ dma_controller->regs);
++ sh_printk("sub channel %d irq %d regs_base %x\n", chan->number, chan->irq,
++ chan->regs);
++#endif
++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
++ printk("reg val %d\n", tmp);
++ dma_wrreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel), 0x01);
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel));
++
++ printk("reg conf %x\n", tmp);
++ dma_wrreg(dma_controller, S3C_DMAC_CCONTROL0(channel), 0x8ff02064);
++
++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel));
++ printk("reg ctrl %x\n", tmp);
++}
++
++
++/* initialisation code */
++
++int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
++ unsigned int stride)
++{
++ struct s3c2410_dma_chan *cp;
++ s3c_dma_controller_t *dconp;
++ int channel, controller;
++ int ret;
++
++ printk("S3C DMA-pl080 Controller Driver, (c) 2006-2007 Samsung Electronics\n");
++
++ dma_channels = channels;
++ printk("Total %d DMA channels will be initialized.\n", channels);
++
++ ret = sysdev_class_register(&dma_sysclass);
++ if (ret != 0) {
++ printk(KERN_ERR "dma sysclass registration failed.\n");
++ goto err;
++ }
++
++ dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0,
++ SLAB_HWCACHE_ALIGN, s3c_dma_cache_ctor);
++
++ if (dma_kmem == NULL) {
++ printk(KERN_ERR "DMA failed to make kmem cache\n");
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ for (controller = 0; controller < S3C_DMA_CONTROLLERS; controller++) {
++ dconp = &s3c_dma_cntlrs[controller];
++
++ memset(dconp, 0, sizeof(s3c_dma_controller_t));
++
++ if(controller < 2) {
++ dma_base = ioremap((S3C24XX_PA_DMA + (controller * 0x100000)), 0x200);
++ if (dma_base == NULL) {
++ printk(KERN_ERR "DMA failed to ioremap register block\n");
++ return -ENOMEM;
++ }
++
++ /* dma controller's irqs are in order.. */
++ dconp->irq = controller + IRQ_DMA0;
++ }
++ else {
++ dma_base = ioremap(((S3C24XX_PA_DMA + 0x8B00000) + ((controller%2) * 0x100000)), 0x200);
++ if (dma_base == NULL) {
++ printk(KERN_ERR "SDMA failed to ioremap register block\n");
++ return -ENOMEM;
++ }
++
++ /* dma controller's irqs are in order.. */
++ dconp->irq = (controller%2) + IRQ_SDMA0;
++ }
++
++ dconp->number = controller;
++ dconp->regs = dma_base;
++ sh_printk("DMA controller : %d irq %d regs_base %x\n", dconp->number, dconp->irq,
++ dconp->regs);
++ }
++
++ for (channel = 0; channel < channels; channel++) {
++ controller = channel / S3C_CHANNELS_PER_DMA;
++ cp = &s3c_dma_chans[channel];
++
++ memset(cp, 0, sizeof(struct s3c2410_dma_chan));
++
++ cp->dma_con = &s3c_dma_cntlrs[controller];
++
++ /* dma channel irqs are in order.. */
++ cp->index = channel;
++ cp->number = channel%S3C_CHANNELS_PER_DMA;
++
++ cp->irq = s3c_dma_cntlrs[controller].irq;
++
++ cp->regs = s3c_dma_cntlrs[controller].regs + ((channel%S3C_CHANNELS_PER_DMA)*stride) + 0x100;
++
++ /* point current stats somewhere */
++ cp->stats = &cp->stats_store;
++ cp->stats_store.timeout_shortest = LONG_MAX;
++
++ /* basic channel configuration */
++ cp->load_timeout = 1 << 18;
++
++ /* register system device */
++ cp->dev.cls = &dma_sysclass;
++ cp->dev.id = channel;
++ //ret = sysdev_register(&cp->dev);
++
++ sh_printk("DMA channel %d at %p, irq %d\n", cp->number, cp->regs, cp->irq);
++ }
++
++ return 0;
++
++err:
++ kmem_cache_destroy(dma_kmem);
++ iounmap(dma_base);
++ dma_base = NULL;
++ return ret;
++}
++
++
++
++static inline int is_channel_valid(unsigned int channel)
++{
++ return (channel & DMA_CH_VALID);
++}
++
++static struct s3c24xx_dma_order *dma_order;
++
++
++/* s3c_dma_map_channel()
++ *
++ * turn the virtual channel number into a real, and un-used hardware
++ * channel.
++ *
++ * first, try the dma ordering given to us by either the relevant
++ * dma code, or the board. Then just find the first usable free
++ * channel
++*/
++
++struct s3c2410_dma_chan *s3c_dma_map_channel(int channel)
++{
++ struct s3c24xx_dma_order_ch *ord = NULL;
++ struct s3c24xx_dma_map *ch_map;
++ struct s3c2410_dma_chan *dmach;
++ int ch;
++
++ if (dma_sel.map == NULL || channel > dma_sel.map_size)
++ return NULL;
++
++ ch_map = dma_sel.map + channel;
++
++ /* first, try the board mapping */
++
++ if (dma_order) {
++ ord = &dma_order->channels[channel];
++
++ for (ch = 0; ch < dma_channels; ch++) {
++ if (!is_channel_valid(ord->list[ch]))
++ continue;
++
++ if (s3c_dma_chans[ord->list[ch]].in_use == 0) {
++ ch = ord->list[ch] & ~DMA_CH_VALID;
++ goto found;
++ }
++ }
++
++ if (ord->flags & DMA_CH_NEVER)
++ return NULL;
++ }
++
++ /* second, search the channel map for first free */
++
++ for (ch = 0; ch < dma_channels; ch++) {
++ if (!is_channel_valid(ch_map->channels[ch]))
++ continue;
++
++ if (s3c_dma_chans[ch].in_use == 0) {
++ pr_debug("mapped channel %d to %d\n", channel, ch);
++ break;
++ }
++ }
++
++ if (ch >= dma_channels)
++ return NULL;
++
++ /* update our channel mapping */
++
++ found:
++ dmach = &s3c_dma_chans[ch];
++ dma_chan_map[channel] = dmach;
++
++ /* select the channel */
++ (dma_sel.select)(dmach, ch_map);
++
++ return dmach;
++}
++
++static int s3c_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
++{
++ unsigned long tmp = __raw_readl(S3C_SDMA_SEL);
++
++ tmp |= map->sdma_sel;
++ __raw_writel(tmp, S3C_SDMA_SEL);
++
++ return 0;
++}
++
++int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
++{
++ struct s3c24xx_dma_map *nmap;
++ size_t map_sz = sizeof(*nmap) * sel->map_size;
++ int ptr;
++
++ nmap = kmalloc(map_sz, GFP_KERNEL);
++ if (nmap == NULL)
++ return -ENOMEM;
++
++ memcpy(nmap, sel->map, map_sz);
++ memcpy(&dma_sel, sel, sizeof(*sel));
++
++ dma_sel.map = nmap;
++
++ for (ptr = 0; ptr < sel->map_size; ptr++)
++ s3c_dma_check_entry(nmap+ptr, ptr);
++
++ return 0;
++}
++
++int __init s3c_dma_order_set(struct s3c24xx_dma_order *ord)
++{
++ struct s3c24xx_dma_order *nord = dma_order;
++
++ if (nord == NULL)
++ nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
++
++ if (nord == NULL) {
++ printk(KERN_ERR "no memory to store dma channel order\n");
++ return -ENOMEM;
++ }
++
++ dma_order = nord;
++ memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
++ return 0;
++}
++
++
+diff --git a/arch/arm/plat-s5pc1xx/gpio.c b/arch/arm/plat-s5pc1xx/gpio.c
+new file mode 100644
+index 0000000..dc9e0d6
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/gpio.c
+@@ -0,0 +1,241 @@
++/* linux/arch/arm/plat-s5p/gpio.c
++ *
++ * Copyright (c) 2008 Samsung Electronics
++ *
++ * S5PC1XX GPIO support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/plat-s5p/regs-gpio.h>
++
++/* GPIO bank list */
++static void __iomem *gpio_base_offset[] = {
++ S3C24XX_VA_GPIO + 0x00, /* GPA0 */
++ S3C24XX_VA_GPIO + 0x20, /* GPA1 */
++ S3C24XX_VA_GPIO + 0x40, /* GPB */
++ S3C24XX_VA_GPIO + 0x60, /* GPC */
++ S3C24XX_VA_GPIO + 0x80, /* GPD */
++ S3C24XX_VA_GPIO + 0xA0, /* GPE0 */
++ S3C24XX_VA_GPIO + 0xC0, /* GPE1 */
++ S3C24XX_VA_GPIO + 0xE0, /* GPF0 */
++ S3C24XX_VA_GPIO + 0x100, /* GPF1 */
++ S3C24XX_VA_GPIO + 0x120, /* GPF2 */
++ S3C24XX_VA_GPIO + 0x140, /* GPF3 */
++ S3C24XX_VA_GPIO + 0x160, /* GPG0 */
++ S3C24XX_VA_GPIO + 0x180, /* GPG1 */
++ S3C24XX_VA_GPIO + 0x1A0, /* GPG2 */
++ S3C24XX_VA_GPIO + 0x1C0, /* GPG3 */
++ S3C24XX_VA_GPIO + 0xC00, /* GPH0 */
++ S3C24XX_VA_GPIO + 0xC20, /* GPH1 */
++ S3C24XX_VA_GPIO + 0xC40, /* GPH1 */
++ S3C24XX_VA_GPIO + 0xC60, /* GPH1 */
++ S3C24XX_VA_GPIO + 0x1E0, /* GPI */
++ S3C24XX_VA_GPIO + 0x200, /* GPJ0 */
++ S3C24XX_VA_GPIO + 0x220, /* GPJ1 */
++ S3C24XX_VA_GPIO + 0x240, /* GPJ2 */
++ S3C24XX_VA_GPIO + 0x260, /* GPJ3 */
++ S3C24XX_VA_GPIO + 0x280, /* GPJ4 */
++ S3C24XX_VA_GPIO + 0x2A0, /* GPK0 */
++ S3C24XX_VA_GPIO + 0x2C0, /* GPK1 */
++ S3C24XX_VA_GPIO + 0x2E0, /* GPK2 */
++ S3C24XX_VA_GPIO + 0x300, /* GPK3 */
++ S3C24XX_VA_GPIO + 0x320, /* MP0_0 */
++ S3C24XX_VA_GPIO + 0x340, /* MP0_1 */
++ S3C24XX_VA_GPIO + 0x360, /* MP0_2 */
++ S3C24XX_VA_GPIO + 0x380, /* MP0_3 */
++ S3C24XX_VA_GPIO + 0x3A0, /* MP0_4 */
++
++ /* followings do not have con register */
++ S3C24XX_VA_GPIO + 0x3C8, /* MP1_0 */
++ S3C24XX_VA_GPIO + 0x3E8, /* MP1_1 */
++ S3C24XX_VA_GPIO + 0x408, /* MP1_2 */
++ S3C24XX_VA_GPIO + 0x428, /* MP1_3 */
++ S3C24XX_VA_GPIO + 0x448, /* MP1_4 */
++ S3C24XX_VA_GPIO + 0x468, /* MP1_5 */
++ S3C24XX_VA_GPIO + 0x488, /* MP1_6 */
++ S3C24XX_VA_GPIO + 0x4A8, /* MP1_7 */
++ S3C24XX_VA_GPIO + 0x4C8, /* MP1_8 */
++ S3C24XX_VA_GPIO + 0x4E8, /* ETC0 */
++ S3C24XX_VA_GPIO + 0x508, /* ETC1 */
++ S3C24XX_VA_GPIO + 0x528, /* ETC2 */
++ S3C24XX_VA_GPIO + 0x548, /* ETC3 */
++ S3C24XX_VA_GPIO + 0x568, /* ETC4 */
++};
++
++void s5p_gpio_cfgpin(unsigned int pin, unsigned int function)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long offs = S5P_GPIO_OFFSET(pin) * 4;
++ unsigned long con, flags;
++
++ local_irq_save(flags);
++
++ con = __raw_readl(base);
++ con &= ~(0xf << offs);
++ con |= (function << offs);
++ __raw_writel(con, base);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s5p_gpio_cfgpin);
++
++unsigned int s5p_gpio_getcfg(unsigned int pin)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long mask;
++
++ mask = 0xf << (S5P_GPIO_OFFSET(pin) * 4);
++
++ return __raw_readl(base) & mask;
++}
++
++EXPORT_SYMBOL(s5p_gpio_getcfg);
++
++void s5p_gpio_setpin(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long offs = S5P_GPIO_OFFSET(pin);
++ unsigned long dat, flags;
++
++ local_irq_save(flags);
++
++ dat = __raw_readl(base + 0x4);
++ dat &= ~(0x1 << offs);
++ dat |= (to << offs);
++ __raw_writel(dat, base + 0x4);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s5p_gpio_setpin);
++
++unsigned int s5p_gpio_getpin(unsigned int pin)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long offs = S5P_GPIO_OFFSET(pin);
++
++ return __raw_readl(base + 0x4) & (0x1 << offs);
++}
++
++EXPORT_SYMBOL(s5p_gpio_getpin);
++
++void s5p_gpio_pullup(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long offs = S5P_GPIO_OFFSET(pin) * 2;
++ unsigned long up, mask, flags;
++
++ mask = 0x3 << offs;
++
++ local_irq_save(flags);
++
++ up = __raw_readl(base + 0x8);
++ up &= ~mask;
++ up |= (to << offs);
++ __raw_writel(up, base + 0x8);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s5p_gpio_pullup);
++
++void s5p_gpio_drv(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long offs = S5P_GPIO_OFFSET(pin) * 2;
++ unsigned long up, mask, flags;
++
++ mask = 0x3 << offs;
++
++ local_irq_save(flags);
++
++ up = __raw_readl(base + 0xc);
++ up &= ~mask;
++ up |= (to << offs);
++ __raw_writel(up, base + 0xc);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s5p_gpio_drv);
++
++void s5p_gpio_pdn_con(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long offs = S5P_GPIO_OFFSET(pin) * 2;
++ unsigned long con, mask, flags;
++
++ mask = 0x3 << offs;
++
++ local_irq_save(flags);
++
++ con = __raw_readl(base + 0x10);
++ con &= ~mask;
++ con |= (to << offs);
++ __raw_writel(con, base + 0x10);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s5p_gpio_pdn_con);
++
++void s5p_gpio_pdn_pullup(unsigned int pin, unsigned int to)
++{
++ void __iomem *base = gpio_base_offset[S5P_GPIO_BASE(pin)];
++ unsigned long offs = S5P_GPIO_OFFSET(pin) * 2;
++ unsigned long up, mask, flags;
++
++ mask = 0x3 << offs;
++
++ local_irq_save(flags);
++
++ up = __raw_readl(base + 0x14);
++ up &= ~mask;
++ up |= (to << offs);
++ __raw_writel(up, base + 0x14);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s5p_gpio_pdn_pullup);
++
++void s5p_gpio_eint_cfg(unsigned int reg, unsigned int num, unsigned int to)
++{
++ unsigned long con, flags;
++
++ local_irq_save(flags);
++
++ con = __raw_readl(reg);
++ con &= ~(0x7 << (num * 4));
++ con |= (to << (num * 4));
++ __raw_writel(con, reg);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s5p_gpio_eint_cfg);
++
+diff --git a/arch/arm/plat-s5pc1xx/irq-pl192.c b/arch/arm/plat-s5pc1xx/irq-pl192.c
+new file mode 100644
+index 0000000..42dd90e
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/irq-pl192.c
+@@ -0,0 +1,642 @@
++/* linux/arch/arm/mach-s3c64xx/irq-pl192.c
++ *
++ *
++ * S3C64XX interrupt functions.
++ * Added by JaeCheol Lee(jc.lee@samsung.com)
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/ptrace.h>
++#include <linux/sysdev.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/mach/irq.h>
++
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-irq.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++#include <asm/plat-s3c24xx/pm.h>
++
++#define irqdbf(x...)
++#define irqdbf2(x...)
++
++
++/* "irqno" interrupt acked */
++static inline void
++s3c_irq_ack (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ } else if (irqno < 64) {
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ __raw_writel(irqno, S3C_VIC1ADDRESS);
++ } else {
++ /* External interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++/* "irqno" interrupt disabled */
++static inline void
++s3c_irq_mask (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(1<<irqno, S3C_VIC0INTENCLEAR);
++ } else if (irqno < 64) {
++ __raw_writel(1<<(irqno-32), S3C_VIC1INTENCLEAR);
++ } else {
++ /* External interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++/* "irqno" interrupt disabled and acked */
++static inline void
++s3c_irq_maskack (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(1<<irqno, S3C_VIC0INTENCLEAR);
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ } else if (irqno < 64) {
++ __raw_writel(1<<(irqno-32), S3C_VIC1INTENCLEAR);
++ /* XXX: can explain why this code is here by scsuh */
++ __raw_writel(irqno, S3C_VIC0ADDRESS);
++ __raw_writel(irqno, S3C_VIC1ADDRESS);
++ } else {
++ /* External interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++/* "irqno" interrupt enabled */
++static inline void
++s3c_irq_unmask (unsigned int irqno)
++{
++ if (irqno < 32) {
++ __raw_writel(1<<irqno, S3C_VIC0INTENABLE);
++ } else if (irqno < 64) {
++ __raw_writel(1<<(irqno-32), S3C_VIC1INTENABLE);
++ } else {
++ /* External Interrupt */
++ printk("ext irq %d\n", irqno);
++ }
++}
++
++static inline void
++s3c_irq_unmaskack(unsigned int irqno)
++{
++ unsigned long unmask;
++
++ /* It is common for all interrupt sources */
++ __raw_writel(1, S3C_VIC0ADDRESS);
++
++ if (irqno < 32) {
++ unmask = __raw_readl(S3C_VIC0INTENABLE);
++ unmask |= (1UL << irqno);
++ __raw_writel(unmask, S3C_VIC0INTENABLE);
++ } else if (irqno < 64) {
++ unmask = __raw_readl(S3C_VIC1INTENABLE);
++ unmask |= (1UL << (irqno - 32));
++ __raw_writel(unmask, S3C_VIC1INTENABLE);
++ __raw_writel(1, S3C_VIC1ADDRESS);
++ } else {
++ /* External Interrupt */
++ printk("ext irq %d\n", irqno);
++
++ }
++}
++
++static int
++s3c_irq_wake(unsigned int irqno, unsigned int flag)
++{
++#if 0
++ unsigned int pwr_cfg,bit_position;
++ pwr_cfg = __raw_readl(S3C_PWR_CFG);
++
++ switch(irqno) {
++ case IRQ_RTC_TIC:
++ bit_position = 11;
++ break;
++ case IRQ_TC:
++ bit_position = 12;
++ break;
++ case IRQ_RTC_ALARM:
++ bit_position = 10;
++ break;
++ case IRQ_KEYPAD:
++ bit_position = 8;
++ break;
++ default:
++ printk("irq %d : Not supporting wakeup \n", irqno);
++ return -1;
++ }
++
++ if(flag) {
++ pwr_cfg &=~(1 << bit_position);
++ } else {
++ pwr_cfg |= (1 << bit_position);
++ }
++ __raw_writel(pwr_cfg, S3C_PWR_CFG);
++#endif
++
++ return 0;
++}
++
++//static struct irqchip s3c_irq_level_chip = {
++static struct irq_chip s3c_irq_level_chip = {
++ .ack = s3c_irq_maskack,
++ .mask = s3c_irq_mask,
++ .unmask = s3c_irq_unmask,
++ .set_wake = s3c_irq_wake
++};
++
++#if 0 /* XXX: when you want to use it, unmask it. by scsuh */
++static struct irqchip s3c_irq_chip = {
++ .ack = s3c_irq_mask,
++ .mask = s3c_irq_mask,
++ .unmask = s3c_irq_unmask,
++ .set_wake = s3c_irq_wake
++};
++#endif
++
++static inline void
++s3c_irqext_mask(unsigned int irqno)
++{
++ unsigned long gpjcon; // Workaround
++ unsigned long mask;
++
++ if (irqno >= 64) {
++ gpjcon = __raw_readl(S3C_GPJCON);
++ irqno -= 64;
++ mask = __raw_readl(S3C_EINTMASK);
++ mask |= (1UL << irqno);
++ __raw_writel(mask, S3C_EINTMASK);
++ __raw_writel(gpjcon, S3C_GPJCON);
++ } else {
++ printk("Invalid ext irq %d\n", irqno);
++ }
++}
++
++static inline void
++s3c_irqext_maskack(unsigned int irqno)
++{
++ s3c_irqext_mask(irqno);
++#if 0
++ if (irqno <= IRQ_EINT3) {
++ s3c_irq_mask(IRQ_EINT0_3);
++ } else if (irqno <= IRQ_EINT11) {
++ s3c_irq_mask(IRQ_EINT4_11);
++ } else if (irqno <= IRQ_EINT19) {
++ s3c_irq_mask(IRQ_EINT12_19);
++ } else if (irqno <= IRQ_EINT27) {
++ s3c_irq_mask(IRQ_EINT20_27);
++ } else if (irqno > IRQ_EINT27) {
++ panic("Wrong IRQ number %d \n ", irqno);
++ }
++#endif
++
++}
++
++static inline void
++s3c_irqext_unmaskack(unsigned int irqno)
++{
++#if 0
++ unsigned long mask;
++
++ if (irqno <= IRQ_EINT3) {
++ s3c_irq_unmaskack(IRQ_EINT0_3);
++ } else if (irqno <= IRQ_EINT11) {
++ s3c_irq_unmaskack(IRQ_EINT4_11);
++ } else if (irqno <= IRQ_EINT19) {
++ s3c_irq_unmaskack(IRQ_EINT12_19);
++ } else if (irqno <= IRQ_EINT27) {
++ s3c_irq_unmaskack(IRQ_EINT20_27);
++ }
++ if (irqno >= 64) {
++ irqno -= 64;
++ __raw_writel(1UL << irqno, S3C_EINTPEND);
++ mask = __raw_readl(S3C_EINTMASK);
++ mask &= ~(1UL << irqno);
++ __raw_writel(mask, S3C_EINTMASK);
++ } else {
++ printk("Invalid ext irq %d\n", irqno);
++ }
++#endif
++}
++
++
++static int
++s3c_irqext_type(unsigned int irq, unsigned int type)
++{
++
++ unsigned long newvalue = 0;
++
++
++ /* Set the external interrupt to pointed trigger type */
++ switch (type) {
++ case IRQT_NOEDGE:
++ printk(KERN_WARNING "No edge setting!\n");
++ break;
++
++ case IRQT_RISING:
++ newvalue = S3C_EXTINT_RISEEDGE;
++ break;
++
++ case IRQT_FALLING:
++ newvalue = S3C_EXTINT_FALLEDGE;
++ break;
++
++ case IRQT_BOTHEDGE:
++ newvalue = S3C_EXTINT_BOTHEDGE;
++ break;
++
++ case IRQT_LOW:
++ newvalue = S3C_EXTINT_LOWLEV;
++ break;
++
++ case IRQT_HIGH:
++ newvalue = S3C_EXTINT_HILEV;
++ break;
++
++ default:
++ printk(KERN_ERR "No such irq type %d", type);
++ return -1;
++ }
++
++ switch (irq) {
++ case IRQ_EINT9:
++ gpio_set_pin(S3C_GPN9, S3C_GPN9_EXTINT9);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 16)) |
++ (newvalue << 16), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT10:
++ gpio_set_pin(S3C_GPN10, S3C_GPN10_EXTINT10);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 20)) |
++ (newvalue << 20), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT11:
++ gpio_set_pin(S3C_GPN11, S3C_GPN11_EXTINT11);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 20)) |
++ (newvalue << 20), S3C_EINTCON0);
++ break;
++ case IRQ_EINT12:
++ gpio_set_pin(S3C_GPN12, S3C_GPN12_EXTINT12);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 24)) |
++ (newvalue << 24), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT13:
++ gpio_set_pin(S3C_GPN13, S3C_GPN13_EXTINT13);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 24)) |
++ (newvalue << 24), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT14:
++ gpio_set_pin(S3C_GPN14, S3C_GPN14_EXTINT14);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 28)) |
++ (newvalue << 28), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT15:
++ gpio_set_pin(S3C_GPN15, S3C_GPN15_EXTINT15);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 28)) |
++ (newvalue << 28), S3C_EINTCON0);
++ break;
++ default:
++ printk(KERN_ERR
++ "s3c_irqext_type : Only support EINT9,10,11,12,13,14,15 interrupt.\n");
++ break;
++
++ }
++
++ return 0;
++}
++
++static int s3c_irqext_wake(unsigned int irqno, unsigned int flag)
++{
++#if 0
++ unsigned int eint_mask;
++
++ if(irqno < IRQ_EINT0)
++ printk(KERN_ERR "Check external wake-up source\n");
++
++ eint_mask = __raw_readl(S3C_EINT_MASK);
++
++ if(flag) {
++ eint_mask &= ~(1 << (irqno - IRQ_EINT0));
++ } else {
++ eint_mask |= (1 << (irqno - IRQ_EINT0));
++ }
++
++ __raw_writel(eint_mask, S3C_EINT_MASK);
++#endif
++ return 0;
++}
++
++//static struct irqchip s3c_irqext_chip = {
++static struct irq_chip s3c_irqext_chip = {
++ .mask = s3c_irqext_mask,
++ .unmask = s3c_irqext_unmaskack,
++ .ack = s3c_irqext_maskack,
++ .set_type = s3c_irqext_type,
++ .set_wake = s3c_irqext_wake
++};
++
++
++/* irq demux for EINT0_3 */
++static inline void
++s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
++{
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT0;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = (eintpend & 0xf);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++
++}
++
++/* irq demux for EINT4_11 */
++static void
++s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
++{
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT4;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = ((eintpend >> 4) & 0xff);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++}
++
++/* irq demux for EINT12_19 */
++static void
++s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
++{
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT12;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = ((eintpend >> 12) & 0xff);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++
++}
++
++/* irq demux for EINT20_27 */
++static void
++s3c_irq_demux_eint20_27 (unsigned int irq, struct irq_desc *desc)
++{
++#if 0
++ unsigned int eintpend, eintmsk;
++ unsigned int irqnr = IRQ_EINT20;
++ unsigned char interruptPending = 0, count = 0;
++ struct irq_desc *mydesc;
++
++ /* read the current pending interrupts, and the mask
++ * for what it is available */
++ eintpend = __raw_readl(S3C_EINTPEND);
++ eintmsk = __raw_readl(S3C_EINTMASK);
++
++ eintpend &= ~eintmsk;
++
++ interruptPending = ((eintpend >> 20) & 0xff);
++ while (interruptPending != 0) {
++ if (interruptPending & 0x1) {
++ mydesc = irq_desc + (irqnr + count);
++ //mydesc->handle((irqnr + count), mydesc, regs);
++ desc_handle_irq((irqnr + count), mydesc);
++ }
++ interruptPending >>= 1;
++ count++;
++ }
++#endif
++}
++
++#ifdef CONFIG_PM
++
++static struct sleep_save irq_save[] = {
++ SAVE_ITEM(S3C_VIC0INTSELECT),
++ SAVE_ITEM(S3C_VIC1INTSELECT),
++ SAVE_ITEM(S3C_VIC0INTENABLE),
++ SAVE_ITEM(S3C_VIC1INTENABLE),
++ SAVE_ITEM(S3C_VIC0SOFTINT),
++ SAVE_ITEM(S3C_VIC1SOFTINT),
++};
++
++static struct sleep_save extirq_save[] = {
++ SAVE_ITEM(S3C_EINTCON0),
++ SAVE_ITEM(S3C_EINTCON1),
++ SAVE_ITEM(S3C_EINTFLTCON0),
++ SAVE_ITEM(S3C_EINTFLTCON1),
++ SAVE_ITEM(S3C_EINTFLTCON2),
++ SAVE_ITEM(S3C_EINTFLTCON3),
++ SAVE_ITEM(S3C_EINTMASK),
++ SAVE_ITEM(S3C_EINT12CON),
++ SAVE_ITEM(S3C_EINT34CON),
++ SAVE_ITEM(S3C_EINT56CON),
++ SAVE_ITEM(S3C_EINT78CON),
++ SAVE_ITEM(S3C_EINT9CON),
++ SAVE_ITEM(S3C_EINT12FLTCON),
++ SAVE_ITEM(S3C_EINT34FLTCON),
++ SAVE_ITEM(S3C_EINT56FLTCON),
++ SAVE_ITEM(S3C_EINT78FLTCON),
++ SAVE_ITEM(S3C_EINT9FLTCON),
++ SAVE_ITEM(S3C_EINT12MASK),
++ SAVE_ITEM(S3C_EINT34MASK),
++ SAVE_ITEM(S3C_EINT56MASK),
++ SAVE_ITEM(S3C_EINT78MASK),
++ SAVE_ITEM(S3C_EINT9MASK),
++ SAVE_ITEM(S3C_EINT34FLTCON),
++ SAVE_ITEM(S3C_EINT56FLTCON),
++ SAVE_ITEM(S3C_EINT78FLTCON),
++ SAVE_ITEM(S3C_EINT9FLTCON),
++};
++
++int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
++{
++ s3c2410_pm_do_save(extirq_save, ARRAY_SIZE(extirq_save));
++ s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
++ return 0;
++}
++
++int s3c24xx_irq_resume(struct sys_device *dev)
++{
++#if 0
++ int irqno;
++ int irqindex = 0;
++
++ s3c2410_pm_do_restore(extirq_save, ARRAY_SIZE(extirq_save));
++ s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
++
++ /* For writing the IRQ number into the VICVECTADDR */
++ for (irqno = IRQ_EINT0_3; irqno <= IRQ_LCD_SYSTEM; irqno++) {
++ __raw_writel(irqno, S3C_VIC0VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ irqindex = 0;
++ for (irqno = IRQ_EINT12_19; irqno <= IRQ_ADC; irqno++) {
++ __raw_writel(irqno, S3C_VIC1VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++#endif
++ return 0;
++}
++
++#else
++#define s3c24xx_irq_suspend NULL
++#define s3c24xx_irq_resume NULL
++#endif
++
++
++/* --------------------------------------------------
++ * s3c_init_irq
++ *
++ * Initialise s3c6400 IRQ system
++ * --------------------------------------------------
++ */
++
++void __init s3c_init_irq(void)
++{
++ int irqno;
++ int irqindex = 0;
++
++ irqdbf("s3c_init_irq: clearing interrupt status flags\n");
++
++ /* first, clear all interrupts pending... */
++
++ /* clear external interrupts */
++ __raw_writel(0xFFFFFFFF, S3C_EINTPEND);
++
++ /* clear all vector interrupts */
++ __raw_writel(0x00000000, S3C_VIC0ADDRESS);
++ __raw_writel(0x00000000, S3C_VIC1ADDRESS);
++
++
++ /* For writing the IRQ number into the VICVECTADDR */
++ for (irqno = IRQ_EINT0; irqno <= IRQ_GPIOINT; irqno++) {
++ __raw_writel(irqno, S3C_VIC0VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ irqindex = 0;
++ for (irqno = IRQ_CORTEX0; irqno <= IRQ_MIPIDSI; irqno++) {
++ __raw_writel(irqno, S3C_VIC1VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ irqindex = 0;
++ for (irqno = IRQ_LCD0; irqno <= IRQ_SDMFIQ; irqno++) {
++ __raw_writel(irqno, S3C_VIC2VECTADDR0 + irqindex);
++ irqindex = irqindex + 4;
++ }
++
++ /* register the main interrupts */
++ irqdbf("s3c_init_irq: registering S5PC1XX interrupt handlers\n");
++
++ for (irqno = IRQ_EINT0; irqno <= IRQ_SDMFIQ; irqno++) {
++#if 0
++ switch (irqno) {
++ /* deal with the special IRQs in ext (cascaded) */
++ case IRQ_EINT0_3:
++ set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
++ break;
++
++ case IRQ_EINT4_11:
++ set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
++ break;
++
++ case IRQ_EINT12_19:
++ set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
++ break;
++
++ case IRQ_EINT20_27:
++ set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
++ break;
++
++ default:
++ irqdbf("registering irq %d (s3c irq)\n", irqno);
++ set_irq_chip(irqno, &s3c_irq_level_chip);
++ //set_irq_handler(irqno, do_level_IRQ);
++ set_irq_handler(irqno, handle_level_irq);
++ set_irq_flags(irqno, IRQF_VALID);
++ break;
++ }
++#endif
++ irqdbf("registering irq %d (s3c irq)\n", irqno);
++ set_irq_chip(irqno, &s3c_irq_level_chip);
++ //set_irq_handler(irqno, do_level_IRQ);
++ set_irq_handler(irqno, handle_level_irq);
++ set_irq_flags(irqno, IRQF_VALID);
++
++ }
++#if 0
++ for (irqno = IRQ_EINT0; irqno <= IRQ_EINT27; irqno++) {
++ irqdbf("registering irq %d (extended s3c irq)\n", irqno);
++ set_irq_chip(irqno, &s3c_irqext_chip);
++ //set_irq_handler(irqno, do_level_IRQ);
++ set_irq_handler(irqno, handle_level_irq);
++ set_irq_flags(irqno, IRQF_VALID);
++ }
++#endif
++
++ irqdbf("s5pc100: registered interrupt handlers\n");
++}
+diff --git a/arch/arm/plat-s5pc1xx/time-s5pc1xx.c b/arch/arm/plat-s5pc1xx/time-s5pc1xx.c
+new file mode 100644
+index 0000000..02992a6
+--- /dev/null
++++ b/arch/arm/plat-s5pc1xx/time-s5pc1xx.c
+@@ -0,0 +1,392 @@
++/* linux/arch/arm/mach-s3c64xx/time.c
++ *
++ * Copyright (C) 2006 Samsung Electronics
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++
++#include <asm/system.h>
++#include <asm/leds.h>
++#include <asm/mach-types.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/arch/map.h>
++#include <asm/plat-s3c/regs-timer.h>
++#include <asm/arch/regs-irq.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/mach/time.h>
++
++#include <asm/plat-s3c24xx/clock.h>
++#include <asm/plat-s3c24xx/cpu.h>
++
++static unsigned long timer_startval;
++static unsigned long timer_usec_ticks;
++
++#ifdef CONFIG_NO_IDLE_HZ
++static unsigned long s3c_timer_cnt_per_tick;
++static unsigned long previous_dyn_ticks;
++static unsigned long last_dyn_ticks;
++static unsigned long sync_timer_startval;
++static unsigned long last_sync_timer_count;
++static unsigned long last_tick_count;
++#define JIFFIES_TO_HW_TICKS(nr_jiffies, timer_cnt_per_tick)\
++ ((nr_jiffies) * timer_cnt_per_tick)
++
++
++#endif
++
++//#define T32_PROBE_TEST
++
++#define TIMER_USEC_SHIFT 16
++
++/* we use the shifted arithmetic to work out the ratio of timer ticks
++ * to usecs, as often the peripheral clock is not a nice even multiple
++ * of 1MHz.
++ *
++ * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
++ * for the current HZ value of 200 without producing overflows.
++ *
++ * Original patch by Dimitry Andric, updated by Ben Dooks
++*/
++
++#ifdef CONFIG_NO_IDLE_HZ
++
++static inline unsigned long s3c_sync_timer_read(void)
++{
++ return __raw_readl(S3C_TCNTO(3));
++}
++
++static inline void s3c_init_sync_timer(void)
++{
++ unsigned long tcon;
++ unsigned long tcfg1;
++ unsigned long tcfg0;
++
++ sync_timer_startval = 0xffffffff;
++
++ tcon = __raw_readl(S3C_TCON);
++ tcfg1 = __raw_readl(S3C_TCFG1);
++ tcfg0 = __raw_readl(S3C_TCFG0);
++
++ /* Sync timer setting */
++ tcfg1 &= ~S3C_TCFG1_MUX3_MASK;
++ tcfg1 |= S3C_TCFG1_MUX3_DIV1;
++ __raw_writel(tcfg1, S3C_TCFG1);
++
++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK;
++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT;
++
++ __raw_writel(0xffffffff, S3C_TCNTB(3));
++ tcon &= ~(0xf<<16);
++ tcon |= S3C_TCON_T3RELOAD;
++ tcon |= S3C_TCON_T3MANUALUPD;
++ __raw_writel(tcon, S3C_TCON);
++
++
++}
++#endif
++
++/* timer_mask_usec_ticks
++ *
++ * given a clock and divisor, make the value to pass into timer_ticks_to_usec
++ * to scale the ticks into usecs
++*/
++
++static inline unsigned long
++timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
++{
++ unsigned long den = pclk / 1000;
++
++ return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
++}
++
++/* timer_ticks_to_usec
++ *
++ * convert timer ticks to usec.
++*/
++
++static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
++{
++ unsigned long res;
++
++ res = ticks * timer_usec_ticks;
++ res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
++
++ return res >> TIMER_USEC_SHIFT;
++}
++
++/***
++ * Returns microsecond since last clock interrupt. Note that interrupts
++ * will have been disabled by do_gettimeoffset()
++ * IRQs are disabled before entering here from do_gettimeofday()
++ */
++
++static unsigned long s3c_gettimeoffset (void)
++{
++
++ unsigned long tval;
++ unsigned long tdone;
++#ifdef CONFIG_NO_IDLE_HZ
++ tval = s3c_sync_timer_read();
++ if(last_tick_count >= tval)
++ tdone = last_tick_count - tval;
++ else
++ tdone = 0xffffffff - tval + last_tick_count + 1;
++#else
++ tval = __raw_readl(S3C_TCNTO(4));
++
++ tdone = timer_startval - tval;
++#endif
++ return timer_ticks_to_usec(tdone);
++
++}
++
++static inline irqreturn_t _s3c_timer_interrupt(int irq, void *dev_id)
++{
++#ifdef CONFIG_NO_IDLE_HZ
++ unsigned long now,tmp;
++ now = s3c_sync_timer_read();
++ if(now <= last_tick_count) {
++ tmp = last_tick_count - now;
++ } else {
++ tmp = 0xffffffff - now + last_tick_count + 1;
++ }
++ while(tmp >= s3c_timer_cnt_per_tick) {
++ tmp -= s3c_timer_cnt_per_tick;
++ if(last_tick_count > s3c_timer_cnt_per_tick)
++ last_tick_count -= s3c_timer_cnt_per_tick;
++ else
++ last_tick_count = (0xffffffff - s3c_timer_cnt_per_tick + last_tick_count + 1);
++ timer_tick();
++ }
++ //printk("z=0x%x\n",__raw_readl(S3C_TCNTO(4)));
++#else
++ timer_tick();
++#endif
++ return IRQ_HANDLED;
++}
++/*
++ * IRQ handler for the timer
++ */
++static irqreturn_t
++s3c_timer_interrupt(int irq, void *dev_id)
++{
++
++
++#ifdef T32_PROBE_TEST
++ gpio_set_value(S3C_GPN14, 1);
++#endif
++ write_seqlock(&xtime_lock);
++ _s3c_timer_interrupt(irq, dev_id);
++ write_sequnlock(&xtime_lock);
++
++ __raw_writel((0x1f & __raw_readl(S3C_TINT_CSTAT)) | S3C_TINT_CSTAT_T4INT, S3C_TINT_CSTAT);
++// __raw_writel((0x1f & __raw_readl(S3C_TINT_CSTAT)) | S3C_TINT_CSTAT_T4INTEN, S3C_TINT_CSTAT);
++#ifdef T32_PROBE_TEST
++ gpio_set_value(S3C_GPN14, 0);
++#endif
++ return IRQ_HANDLED;
++}
++
++static struct irqaction s3c_timer_irq = {
++ .name = "S3C Timer Tick",
++ .flags = IRQF_DISABLED | IRQF_TIMER,
++ .handler = s3c_timer_interrupt,
++};
++
++#ifdef CONFIG_NO_IDLE_HZ
++/*
++ * Programs the next timer interrupt needed. Called when dynamic tick is
++ * enabled, and to reprogram the ticks to skip from pm_idle. Note that
++ * we can keep the timer continuous, and don't need to set it to run in
++ * one-shot mode. This is because the timer will get reprogrammed again
++ * after next interrupt.
++ */
++void s3c_timer_reprogram(unsigned long next_tick)
++{
++ unsigned long tcnt;
++#ifdef T32_PROBE_TEST
++ gpio_set_value(S3C_GPN15, 1);
++#endif
++ //printk("next_tick=%d\n",next_tick);
++ if(next_tick == 0)
++ next_tick = 1;
++ last_dyn_ticks = next_tick;
++ tcnt = JIFFIES_TO_HW_TICKS(next_tick, s3c_timer_cnt_per_tick);
++ //printk("tcnt=0x%x\n",tcnt);
++ __raw_writel((tcnt - 1), S3C_TCNTB(4));
++
++
++#ifdef T32_PROBE_TEST
++ gpio_set_value(S3C_GPN15, 0);
++#endif
++
++}
++
++static int s3c_timer_enable_dyn_tick(void)
++{
++ return 0;
++}
++
++static int s3c_timer_disable_dyn_tick(void)
++{
++ unsigned long tcnt;
++
++ last_dyn_ticks = 1;
++ tcnt = JIFFIES_TO_HW_TICKS(1, s3c_timer_cnt_per_tick);
++
++ __raw_writel((tcnt - 1), S3C_TCNTB(0));
++
++ return 0;
++}
++
++static irqreturn_t s3c_dyn_tick_handler(int irq, void *dev_id)
++{
++ //printk("dyntick irq%d\n",irq);
++ return _s3c_timer_interrupt(irq, dev_id);
++}
++
++static struct dyn_tick_timer s3c_dyn_tick_timer = {
++ .enable = s3c_timer_enable_dyn_tick,
++ .disable = s3c_timer_disable_dyn_tick,
++ .reprogram = s3c_timer_reprogram,
++ .handler = s3c_dyn_tick_handler,
++};
++#endif
++
++/*
++ * Set up timer interrupt, and return the current time in seconds.
++ *
++ * Currently we only use timer4, as it is the only timer which has no
++ * other function that can be exploited externally
++ */
++static void s3c_timer_setup (void)
++{
++ unsigned long tcon;
++ unsigned long tcnt;
++ unsigned long tcfg1;
++ unsigned long tcfg0;
++ unsigned long pclk;
++ unsigned long timerclock;
++ struct clk *clk;
++
++#ifdef T32_PROBE_TEST
++
++ gpio_direction_output(S3C_GPN14);
++ gpio_direction_output(S3C_GPN15);
++ gpio_set_value(S3C_GPN14, 0);
++ gpio_set_value(S3C_GPN15, 0);
++ /* read the current timer configuration bits */
++#endif
++
++ tcnt = 0xffffffff; /* default value for tcnt */
++
++ /* read the current timer configuration bits */
++
++ tcfg1 = __raw_readl(S3C_TCFG1);
++ tcfg0 = __raw_readl(S3C_TCFG0);
++
++ /* this is used as default if no other timer can be found */
++
++ clk = clk_get(NULL, "timers");
++ if (IS_ERR(clk))
++ panic("failed to get clock for system timer");
++
++ clk_enable(clk);
++
++ pclk = clk_get_rate(clk);
++ timerclock = (pclk / ((PRESCALER + 1)*DIVIDER));
++
++ /* configure clock tick */
++
++ timer_usec_ticks = timer_mask_usec_ticks(((PRESCALER + 1)*DIVIDER), pclk);
++
++ tcfg1 &= ~S3C_TCFG1_MUX4_MASK;
++ tcfg1 |= S3C_TCFG1_MUX4_DIV1;
++
++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK;
++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT;
++
++ tcnt = timerclock / HZ;
++ /* timers reload after counting zero, so reduce the count by 1 */
++
++ tcnt--;
++
++ __raw_writel(tcfg1, S3C_TCFG1);
++ __raw_writel(tcfg0, S3C_TCFG0);
++
++ timer_startval = tcnt;
++ __raw_writel(tcnt, S3C_TCNTB(4));
++
++ /* ensure timer is stopped... */
++#ifdef CONFIG_NO_IDLE_HZ
++ s3c_timer_cnt_per_tick = (timerclock/HZ);
++ previous_dyn_ticks = 1;
++ last_dyn_ticks = 1;
++ last_sync_timer_count = 0xffffffff;
++ last_tick_count = 0xffffffff;
++ s3c_init_sync_timer();
++#endif
++ tcon = __raw_readl(S3C_TCON);
++
++ tcon &= ~(7<<20);
++ tcon |= S3C_TCON_T4RELOAD;
++ tcon |= S3C_TCON_T4MANUALUPD;
++
++ __raw_writel(tcon, S3C_TCON);
++ __raw_writel(tcnt, S3C_TCNTB(4));
++ //__raw_writel(tcnt, S3C_TCMPB(4));
++
++ printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
++ tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
++
++ /* start the timer running */
++#ifdef CONFIG_NO_IDLE_HZ
++ tcon |= S3C_TCON_T4START|S3C_TCON_T3START;
++ tcon &= ~(S3C_TCON_T4MANUALUPD|S3C_TCON_T3MANUALUPD);
++#else
++ tcon |= S3C_TCON_T4START;
++ tcon &= ~S3C_TCON_T4MANUALUPD;
++#endif
++ __raw_writel(tcon, S3C_TCON);
++
++ /* timer4 interrupt enable */
++ __raw_writel(__raw_readl(S3C_TINT_CSTAT) | S3C_TINT_CSTAT_T4INTEN, S3C_TINT_CSTAT);
++
++}
++
++static void __init s3c_timer_init (void)
++{
++ s3c_timer_setup();
++ setup_irq(IRQ_TIMER4, &s3c_timer_irq);
++}
++
++struct sys_timer s3c_timer = {
++ .init = s3c_timer_init,
++ .offset = s3c_gettimeoffset,
++ .resume = s3c_timer_setup,
++#ifdef CONFIG_NO_IDLE_HZ
++ .dyn_tick = &s3c_dyn_tick_timer,
++#endif
++};
+diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
+index 0a9a5e7..357382a 100644
+--- a/arch/arm/tools/mach-types
++++ b/arch/arm/tools/mach-types
+@@ -12,7 +12,7 @@
+ #
+ # http://www.arm.linux.org.uk/developer/machines/?action=new
+ #
+-# Last update: Fri May 11 19:53:41 2007
++# Last update: Wed Jul 9 02:34:54 2008
+ #
+ # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
+ #
+@@ -266,7 +266,7 @@ stork_egg ARCH_STORK_EGG STORK_EGG 248
+ wismo SA1100_WISMO WISMO 249
+ ezlinx ARCH_EZLINX EZLINX 250
+ at91rm9200 ARCH_AT91RM9200 AT91RM9200 251
+-orion ARCH_ORION ORION 252
++adtech_orion ARCH_ADTECH_ORION ADTECH_ORION 252
+ neptune ARCH_NEPTUNE NEPTUNE 253
+ hackkit SA1100_HACKKIT HACKKIT 254
+ pxa_wins30 ARCH_PXA_WINS30 PXA_WINS30 255
+@@ -381,13 +381,13 @@ ks8695p ARCH_KS8695P KS8695P 363
+ se4000 ARCH_SE4000 SE4000 364
+ quadriceps ARCH_QUADRICEPS QUADRICEPS 365
+ bronco ARCH_BRONCO BRONCO 366
+-esl_wireless_tab ARCH_ESL_WIRELESS_TABLETESL_WIRELESS_TABLET 367
++esl_wireless_tab ARCH_ESL_WIRELESS_TAB ESL_WIRELESS_TAB 367
+ esl_sofcomp ARCH_ESL_SOFCOMP ESL_SOFCOMP 368
+ s5c7375 ARCH_S5C7375 S5C7375 369
+ spearhead ARCH_SPEARHEAD SPEARHEAD 370
+ pantera ARCH_PANTERA PANTERA 371
+ prayoglite ARCH_PRAYOGLITE PRAYOGLITE 372
+-gumstix ARCH_GUMSTIK GUMSTIK 373
++gumstix ARCH_GUMSTIX GUMSTIX 373
+ rcube ARCH_RCUBE RCUBE 374
+ rea_olv ARCH_REA_OLV REA_OLV 375
+ pxa_iphone ARCH_PXA_IPHONE PXA_IPHONE 376
+@@ -560,7 +560,6 @@ husky MACH_HUSKY HUSKY 543
+ boxer MACH_BOXER BOXER 544
+ shepherd MACH_SHEPHERD SHEPHERD 545
+ aml42800aa MACH_AML42800AA AML42800AA 546
+-ml674001 MACH_MACH_TYPE_ML674001 MACH_TYPE_ML674001 547
+ lpc2294 MACH_LPC2294 LPC2294 548
+ switchgrass MACH_SWITCHGRASS SWITCHGRASS 549
+ ens_cmu MACH_ENS_CMU ENS_CMU 550
+@@ -661,7 +660,6 @@ a9200ec MACH_A9200EC A9200EC 645
+ pnx0105 MACH_PNX0105 PNX0105 646
+ adcpoecpu MACH_ADCPOECPU ADCPOECPU 647
+ csb637 MACH_CSB637 CSB637 648
+-ml69q6203 MACH_ML69Q6203 ML69Q6203 649
+ mb9200 MACH_MB9200 MB9200 650
+ kulun MACH_KULUN KULUN 651
+ snapper MACH_SNAPPER SNAPPER 652
+@@ -749,7 +747,6 @@ anubis MACH_ANUBIS ANUBIS 734
+ ite8152 MACH_ITE8152 ITE8152 735
+ lpc3xxx MACH_LPC3XXX LPC3XXX 736
+ puppeteer MACH_PUPPETEER PUPPETEER 737
+-vt001 MACH_MACH_VADATECH MACH_VADATECH 738
+ e570 MACH_E570 E570 739
+ x50 MACH_X50 X50 740
+ recon MACH_RECON RECON 741
+@@ -840,7 +837,7 @@ ccxp270 MACH_CCXP CCXP 825
+ omap_gsample MACH_OMAP_GSAMPLE OMAP_GSAMPLE 826
+ realview_eb MACH_REALVIEW_EB REALVIEW_EB 827
+ samoa MACH_SAMOA SAMOA 828
+-t3xscale MACH_T3XSCALE T3XSCALE 829
++palmt3 MACH_PALMT3 PALMT3 829
+ i878 MACH_I878 I878 830
+ borzoi MACH_BORZOI BORZOI 831
+ gecko MACH_GECKO GECKO 832
+@@ -896,7 +893,7 @@ mio8390 MACH_MIO8390 MIO8390 881
+ omi_board MACH_OMI_BOARD OMI_BOARD 882
+ mx21civ MACH_MX21CIV MX21CIV 883
+ mahi_cdac MACH_MAHI_CDAC MAHI_CDAC 884
+-xscale_palmtx MACH_XSCALE_PALMTX XSCALE_PALMTX 885
++palmtx MACH_PALMTX PALMTX 885
+ s3c2413 MACH_S3C2413 S3C2413 887
+ samsys_ep0 MACH_SAMSYS_EP0 SAMSYS_EP0 888
+ wg302v1 MACH_WG302V1 WG302V1 889
+@@ -919,7 +916,7 @@ nxdb500 MACH_NXDB500 NXDB500 905
+ apf9328 MACH_APF9328 APF9328 906
+ omap_wipoq MACH_OMAP_WIPOQ OMAP_WIPOQ 907
+ omap_twip MACH_OMAP_TWIP OMAP_TWIP 908
+-xscale_treo650 MACH_XSCALE_PALMTREO650 XSCALE_PALMTREO650 909
++palmtreo650 MACH_PALMTREO650 PALMTREO650 909
+ acumen MACH_ACUMEN ACUMEN 910
+ xp100 MACH_XP100 XP100 911
+ fs2410 MACH_FS2410 FS2410 912
+@@ -927,8 +924,8 @@ pxa270_cerf MACH_PXA270_CERF PXA270_CERF 913
+ sq2ftlpalm MACH_SQ2FTLPALM SQ2FTLPALM 914
+ bsemserver MACH_BSEMSERVER BSEMSERVER 915
+ netclient MACH_NETCLIENT NETCLIENT 916
+-xscale_palmtt5 MACH_XSCALE_PALMTT5 XSCALE_PALMTT5 917
+-xscale_palmtc MACH_OMAP_PALMTC OMAP_PALMTC 918
++palmt5 MACH_PALMT5 PALMT5 917
++palmtc MACH_PALMTC PALMTC 918
+ omap_apollon MACH_OMAP_APOLLON OMAP_APOLLON 919
+ mxc30030evb MACH_MXC30030EVB MXC30030EVB 920
+ rea_2d MACH_REA_2D REA_2D 921
+@@ -953,7 +950,6 @@ fred_jack MACH_FRED_JACK FRED_JACK 939
+ ttg_color1 MACH_TTG_COLOR1 TTG_COLOR1 940
+ nxeb500hmi MACH_NXEB500HMI NXEB500HMI 941
+ netdcu8 MACH_NETDCU8 NETDCU8 942
+-ml675050_cpu_boa MACH_ML675050_CPU_BOA ML675050_CPU_BOA 943
+ ng_fvx538 MACH_NG_FVX538 NG_FVX538 944
+ ng_fvs338 MACH_NG_FVS338 NG_FVS338 945
+ pnx4103 MACH_PNX4103 PNX4103 946
+@@ -1148,7 +1144,7 @@ aidx270 MACH_AIDX270 AIDX270 1134
+ rema MACH_REMA REMA 1135
+ bps1000 MACH_BPS1000 BPS1000 1136
+ hw90350 MACH_HW90350 HW90350 1137
+-omap_sdp3430 MACH_OMAP_SDP3430 OMAP_SDP3430 1138
++omap_3430sdp MACH_OMAP_3430SDP OMAP_3430SDP 1138
+ bluetouch MACH_BLUETOUCH BLUETOUCH 1139
+ vstms MACH_VSTMS VSTMS 1140
+ xsbase270 MACH_XSBASE270 XSBASE270 1141
+@@ -1214,7 +1210,7 @@ osstbox MACH_OSSTBOX OSSTBOX 1203
+ kbat9261 MACH_KBAT9261 KBAT9261 1204
+ ct1100 MACH_CT1100 CT1100 1205
+ akcppxa MACH_AKCPPXA AKCPPXA 1206
+-zevio_1020 MACH_ZEVIO_1020 ZEVIO_1020 1207
++ochaya1020 MACH_OCHAYA1020 OCHAYA1020 1207
+ hitrack MACH_HITRACK HITRACK 1208
+ syme1 MACH_SYME1 SYME1 1209
+ syhl1 MACH_SYHL1 SYHL1 1210
+@@ -1222,7 +1218,6 @@ empca400 MACH_EMPCA400 EMPCA400 1211
+ em7210 MACH_EM7210 EM7210 1212
+ htchermes MACH_HTCHERMES HTCHERMES 1213
+ eti_c1 MACH_ETI_C1 ETI_C1 1214
+-mach_dep2410 MACH_MACH_DEP2410 MACH_DEP2410 1215
+ ac100 MACH_AC100 AC100 1216
+ sneetch MACH_SNEETCH SNEETCH 1217
+ studentmate MACH_STUDENTMATE STUDENTMATE 1218
+@@ -1299,7 +1294,7 @@ xp179 MACH_XP179 XP179 1290
+ h4300 MACH_H4300 H4300 1291
+ goramo_mlr MACH_GORAMO_MLR GORAMO_MLR 1292
+ mxc30020evb MACH_MXC30020EVB MXC30020EVB 1293
+-adsbitsymx MACH_ADSBITSIMX ADSBITSIMX 1294
++adsbitsyg5 MACH_ADSBITSYG5 ADSBITSYG5 1294
+ adsportalplus MACH_ADSPORTALPLUS ADSPORTALPLUS 1295
+ mmsp2plus MACH_MMSP2PLUS MMSP2PLUS 1296
+ em_x270 MACH_EM_X270 EM_X270 1297
+@@ -1367,3 +1362,455 @@ db88f5281 MACH_DB88F5281 DB88F5281 1358
+ csb726 MACH_CSB726 CSB726 1359
+ tik27 MACH_TIK27 TIK27 1360
+ mx_uc7420 MACH_MX_UC7420 MX_UC7420 1361
++rirm3 MACH_RIRM3 RIRM3 1362
++pelco_odyssey MACH_PELCO_ODYSSEY PELCO_ODYSSEY 1363
++adx_abox MACH_ADX_ABOX ADX_ABOX 1365
++adx_tpid MACH_ADX_TPID ADX_TPID 1366
++minicheck MACH_MINICHECK MINICHECK 1367
++idam MACH_IDAM IDAM 1368
++mario_mx MACH_MARIO_MX MARIO_MX 1369
++vi1888 MACH_VI1888 VI1888 1370
++zr4230 MACH_ZR4230 ZR4230 1371
++t1_ix_blue MACH_T1_IX_BLUE T1_IX_BLUE 1372
++syhq2 MACH_SYHQ2 SYHQ2 1373
++computime_r3 MACH_COMPUTIME_R3 COMPUTIME_R3 1374
++oratis MACH_ORATIS ORATIS 1375
++mikko MACH_MIKKO MIKKO 1376
++holon MACH_HOLON HOLON 1377
++olip8 MACH_OLIP8 OLIP8 1378
++ghi270hg MACH_GHI270HG GHI270HG 1379
++davinci_dm6467_evm MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM 1380
++davinci_dm355_evm MACH_DAVINCI_DM350_EVM DAVINCI_DM350_EVM 1381
++blackriver MACH_BLACKRIVER BLACKRIVER 1383
++sandgate_wp MACH_SANDGATEWP SANDGATEWP 1384
++cdotbwsg MACH_CDOTBWSG CDOTBWSG 1385
++quark963 MACH_QUARK963 QUARK963 1386
++csb735 MACH_CSB735 CSB735 1387
++littleton MACH_LITTLETON LITTLETON 1388
++mio_p550 MACH_MIO_P550 MIO_P550 1389
++motion2440 MACH_MOTION2440 MOTION2440 1390
++imm500 MACH_IMM500 IMM500 1391
++homematic MACH_HOMEMATIC HOMEMATIC 1392
++ermine MACH_ERMINE ERMINE 1393
++kb9202b MACH_KB9202B KB9202B 1394
++hs1xx MACH_HS1XX HS1XX 1395
++studentmate2440 MACH_STUDENTMATE2440 STUDENTMATE2440 1396
++arvoo_l1_z1 MACH_ARVOO_L1_Z1 ARVOO_L1_Z1 1397
++dep2410k MACH_DEP2410K DEP2410K 1398
++xxsvideo MACH_XXSVIDEO XXSVIDEO 1399
++im4004 MACH_IM4004 IM4004 1400
++ochaya1050 MACH_OCHAYA1050 OCHAYA1050 1401
++lep9261 MACH_LEP9261 LEP9261 1402
++svenmeb MACH_SVENMEB SVENMEB 1403
++fortunet2ne MACH_FORTUNET2NE FORTUNET2NE 1404
++nxhx MACH_NXHX NXHX 1406
++realview_pb11mp MACH_REALVIEW_PB11MP REALVIEW_PB11MP 1407
++ids500 MACH_IDS500 IDS500 1408
++ors_n725 MACH_ORS_N725 ORS_N725 1409
++hsdarm MACH_HSDARM HSDARM 1410
++sha_pon003 MACH_SHA_PON003 SHA_PON003 1411
++sha_pon004 MACH_SHA_PON004 SHA_PON004 1412
++sha_pon007 MACH_SHA_PON007 SHA_PON007 1413
++sha_pon011 MACH_SHA_PON011 SHA_PON011 1414
++h6042 MACH_H6042 H6042 1415
++h6043 MACH_H6043 H6043 1416
++looxc550 MACH_LOOXC550 LOOXC550 1417
++cnty_titan MACH_CNTY_TITAN CNTY_TITAN 1418
++app3xx MACH_APP3XX APP3XX 1419
++sideoatsgrama MACH_SIDEOATSGRAMA SIDEOATSGRAMA 1420
++palmtreo700p MACH_PALMTREO700P PALMTREO700P 1421
++palmtreo700w MACH_PALMTREO700W PALMTREO700W 1422
++palmtreo750 MACH_PALMTREO750 PALMTREO750 1423
++palmtreo755p MACH_PALMTREO755P PALMTREO755P 1424
++ezreganut9200 MACH_EZREGANUT9200 EZREGANUT9200 1425
++sarge MACH_SARGE SARGE 1426
++a696 MACH_A696 A696 1427
++turtle1916 MACH_TURTLE TURTLE 1428
++mx27_3ds MACH_MX27_3DS MX27_3DS 1430
++bishop MACH_BISHOP BISHOP 1431
++pxx MACH_PXX PXX 1432
++redwood MACH_REDWOOD REDWOOD 1433
++omap_2430dlp MACH_OMAP_2430DLP OMAP_2430DLP 1436
++omap_2430osk MACH_OMAP_2430OSK OMAP_2430OSK 1437
++sardine MACH_SARDINE SARDINE 1438
++halibut MACH_HALIBUT HALIBUT 1439
++trout MACH_TROUT TROUT 1440
++goldfish MACH_GOLDFISH GOLDFISH 1441
++gesbc2440 MACH_GESBC2440 GESBC2440 1442
++nomad MACH_NOMAD NOMAD 1443
++rosalind MACH_ROSALIND ROSALIND 1444
++cc9p9215 MACH_CC9P9215 CC9P9215 1445
++cc9p9210 MACH_CC9P9210 CC9P9210 1446
++cc9p9215js MACH_CC9P9215JS CC9P9215JS 1447
++cc9p9210js MACH_CC9P9210JS CC9P9210JS 1448
++nasffe MACH_NASFFE NASFFE 1449
++tn2x0bd MACH_TN2X0BD TN2X0BD 1450
++gwmpxa MACH_GWMPXA GWMPXA 1451
++exyplus MACH_EXYPLUS EXYPLUS 1452
++jadoo21 MACH_JADOO21 JADOO21 1453
++looxn560 MACH_LOOXN560 LOOXN560 1454
++bonsai MACH_BONSAI BONSAI 1455
++adsmilgato MACH_ADSMILGATO ADSMILGATO 1456
++gba MACH_GBA GBA 1457
++h6044 MACH_H6044 H6044 1458
++app MACH_APP APP 1459
++tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460
++herald MACH_HERMES HERMES 1461
++artemis MACH_ARTEMIS ARTEMIS 1462
++htctitan MACH_HTCTITAN HTCTITAN 1463
++qranium MACH_QRANIUM QRANIUM 1464
++adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465
++adx_medcom MACH_ADX_MEDCOM ADX_MEDCOM 1466
++bboard MACH_BBOARD BBOARD 1467
++cambria MACH_CAMBRIA CAMBRIA 1468
++mt7xxx MACH_MT7XXX MT7XXX 1469
++matrix512 MACH_MATRIX512 MATRIX512 1470
++matrix522 MACH_MATRIX522 MATRIX522 1471
++ipac5010 MACH_IPAC5010 IPAC5010 1472
++sakura MACH_SAKURA SAKURA 1473
++grocx MACH_GROCX GROCX 1474
++pm9263 MACH_PM9263 PM9263 1475
++sim_one MACH_SIM_ONE SIM_ONE 1476
++acq132 MACH_ACQ132 ACQ132 1477
++datr MACH_DATR DATR 1478
++actux1 MACH_ACTUX1 ACTUX1 1479
++actux2 MACH_ACTUX2 ACTUX2 1480
++actux3 MACH_ACTUX3 ACTUX3 1481
++flexit MACH_FLEXIT FLEXIT 1482
++bh2x0bd MACH_BH2X0BD BH2X0BD 1483
++atb2002 MACH_ATB2002 ATB2002 1484
++xenon MACH_XENON XENON 1485
++fm607 MACH_FM607 FM607 1486
++matrix514 MACH_MATRIX514 MATRIX514 1487
++matrix524 MACH_MATRIX524 MATRIX524 1488
++inpod MACH_INPOD INPOD 1489
++jive MACH_JIVE JIVE 1490
++tll_mx21 MACH_TLL_MX21 TLL_MX21 1491
++sbc2800 MACH_SBC2800 SBC2800 1492
++cc7ucamry MACH_CC7UCAMRY CC7UCAMRY 1493
++ubisys_p9_sc15 MACH_UBISYS_P9_SC15 UBISYS_P9_SC15 1494
++ubisys_p9_ssc2d10 MACH_UBISYS_P9_SSC2D10 UBISYS_P9_SSC2D10 1495
++ubisys_p9_rcu3 MACH_UBISYS_P9_RCU3 UBISYS_P9_RCU3 1496
++aml_m8000 MACH_AML_M8000 AML_M8000 1497
++snapper_270 MACH_SNAPPER_270 SNAPPER_270 1498
++omap_bbx MACH_OMAP_BBX OMAP_BBX 1499
++ucn2410 MACH_UCN2410 UCN2410 1500
++sam9_l9260 MACH_SAM9_L9260 SAM9_L9260 1501
++eti_c2 MACH_ETI_C2 ETI_C2 1502
++avalanche MACH_AVALANCHE AVALANCHE 1503
++realview_pb1176 MACH_REALVIEW_PB1176 REALVIEW_PB1176 1504
++dp1500 MACH_DP1500 DP1500 1505
++apple_iphone MACH_APPLE_IPHONE APPLE_IPHONE 1506
++yl9200 MACH_YL9200 YL9200 1507
++rd88f5182 MACH_RD88F5182 RD88F5182 1508
++kurobox_pro MACH_KUROBOX_PRO KUROBOX_PRO 1509
++se_poet MACH_SE_POET SE_POET 1510
++mx31_3ds MACH_MX31_3DS MX31_3DS 1511
++r270 MACH_R270 R270 1512
++armour21 MACH_ARMOUR21 ARMOUR21 1513
++dt2 MACH_DT2 DT2 1514
++vt4 MACH_VT4 VT4 1515
++tyco320 MACH_TYCO320 TYCO320 1516
++adma MACH_ADMA ADMA 1517
++wp188 MACH_WP188 WP188 1518
++corsica MACH_CORSICA CORSICA 1519
++bigeye MACH_BIGEYE BIGEYE 1520
++tll5000 MACH_TLL5000 TLL5000 1522
++bebot MACH_BEBOT BEBOT 1523
++qong MACH_QONG QONG 1524
++tcompact MACH_TCOMPACT TCOMPACT 1525
++puma5 MACH_PUMA5 PUMA5 1526
++elara MACH_ELARA ELARA 1527
++ellington MACH_ELLINGTON ELLINGTON 1528
++xda_atom MACH_XDA_ATOM XDA_ATOM 1529
++energizer2 MACH_ENERGIZER2 ENERGIZER2 1530
++odin MACH_ODIN ODIN 1531
++actux4 MACH_ACTUX4 ACTUX4 1532
++esl_omap MACH_ESL_OMAP ESL_OMAP 1533
++omap2evm MACH_OMAP2EVM OMAP2EVM 1534
++omap3evm MACH_OMAP3EVM OMAP3EVM 1535
++adx_pcu57 MACH_ADX_PCU57 ADX_PCU57 1536
++monaco MACH_MONACO MONACO 1537
++levante MACH_LEVANTE LEVANTE 1538
++tmxipx425 MACH_TMXIPX425 TMXIPX425 1539
++leep MACH_LEEP LEEP 1540
++raad MACH_RAAD RAAD 1541
++dns323 MACH_DNS323 DNS323 1542
++ap1000 MACH_AP1000 AP1000 1543
++a9sam6432 MACH_A9SAM6432 A9SAM6432 1544
++shiny MACH_SHINY SHINY 1545
++omap3_beagle MACH_OMAP3_BEAGLE OMAP3_BEAGLE 1546
++csr_bdb2 MACH_CSR_BDB2 CSR_BDB2 1547
++nokia_n810 MACH_NOKIA_N810 NOKIA_N810 1548
++c270 MACH_C270 C270 1549
++sentry MACH_SENTRY SENTRY 1550
++pcm038 MACH_PCM038 PCM038 1551
++anc300 MACH_ANC300 ANC300 1552
++htckaiser MACH_HTCKAISER HTCKAISER 1553
++sbat100 MACH_SBAT100 SBAT100 1554
++modunorm MACH_MODUNORM MODUNORM 1555
++pelos_twarm MACH_PELOS_TWARM PELOS_TWARM 1556
++flank MACH_FLANK FLANK 1557
++sirloin MACH_SIRLOIN SIRLOIN 1558
++brisket MACH_BRISKET BRISKET 1559
++chuck MACH_CHUCK CHUCK 1560
++otter MACH_OTTER OTTER 1561
++davinci_ldk MACH_DAVINCI_LDK DAVINCI_LDK 1562
++phreedom MACH_PHREEDOM PHREEDOM 1563
++sg310 MACH_SG310 SG310 1564
++ts_x09 MACH_TS209 TS209 1565
++at91cap9adk MACH_AT91CAP9ADK AT91CAP9ADK 1566
++tion9315 MACH_TION9315 TION9315 1567
++mast MACH_MAST MAST 1568
++pfw MACH_PFW PFW 1569
++yl_p2440 MACH_YL_P2440 YL_P2440 1570
++zsbc32 MACH_ZSBC32 ZSBC32 1571
++omap_pace2 MACH_OMAP_PACE2 OMAP_PACE2 1572
++imx_pace2 MACH_IMX_PACE2 IMX_PACE2 1573
++mx31moboard MACH_MX31MOBOARD MX31MOBOARD 1574
++mx37_3ds MACH_MX37_3DS MX37_3DS 1575
++rcc MACH_RCC RCC 1576
++dmp MACH_ARM9 ARM9 1577
++vision_ep9307 MACH_VISION_EP9307 VISION_EP9307 1578
++scly1000 MACH_SCLY1000 SCLY1000 1579
++fontel_ep MACH_FONTEL_EP FONTEL_EP 1580
++voiceblue3g MACH_VOICEBLUE3G VOICEBLUE3G 1581
++tt9200 MACH_TT9200 TT9200 1582
++digi2410 MACH_DIGI2410 DIGI2410 1583
++terastation_pro2 MACH_TERASTATION_PRO2 TERASTATION_PRO2 1584
++linkstation_pro MACH_LINKSTATION_PRO LINKSTATION_PRO 1585
++motorola_a780 MACH_MOTOROLA_A780 MOTOROLA_A780 1587
++motorola_e6 MACH_MOTOROLA_E6 MOTOROLA_E6 1588
++motorola_e2 MACH_MOTOROLA_E2 MOTOROLA_E2 1589
++motorola_e680 MACH_MOTOROLA_E680 MOTOROLA_E680 1590
++ur2410 MACH_UR2410 UR2410 1591
++tas9261 MACH_TAS9261 TAS9261 1592
++davinci_hermes_hd MACH_HERMES_HD HERMES_HD 1593
++davinci_perseo_hd MACH_PERSEO_HD PERSEO_HD 1594
++stargazer2 MACH_STARGAZER2 STARGAZER2 1595
++e350 MACH_E350 E350 1596
++wpcm450 MACH_WPCM450 WPCM450 1597
++cartesio MACH_CARTESIO CARTESIO 1598
++toybox MACH_TOYBOX TOYBOX 1599
++tx27 MACH_TX27 TX27 1600
++ts409 MACH_TS409 TS409 1601
++p300 MACH_P300 P300 1602
++xdacomet MACH_XDACOMET XDACOMET 1603
++dexflex2 MACH_DEXFLEX2 DEXFLEX2 1604
++ow MACH_OW OW 1605
++armebs3 MACH_ARMEBS3 ARMEBS3 1606
++u3 MACH_U3 U3 1607
++smdk2450 MACH_SMDK2450 SMDK2450 1608
++rsi_ews MACH_RSI_EWS RSI_EWS 1609
++tnb MACH_TNB TNB 1610
++toepath MACH_TOEPATH TOEPATH 1611
++kb9263 MACH_KB9263 KB9263 1612
++mt7108 MACH_MT7108 MT7108 1613
++smtr2440 MACH_SMTR2440 SMTR2440 1614
++manao MACH_MANAO MANAO 1615
++cm_x300 MACH_CM_X300 CM_X300 1616
++gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617
++lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618
++arma37 MACH_ARMA37 ARMA37 1619
++mendel MACH_MENDEL MENDEL 1620
++pelco_iliad MACH_PELCO_ILIAD PELCO_ILIAD 1621
++unit2p MACH_UNIT2P UNIT2P 1622
++inc20otter MACH_INC20OTTER INC20OTTER 1623
++at91sam9g20ek MACH_AT91SAM9G20EK AT91SAM9G20EK 1624
++sc_ge2 MACH_STORCENTER STORCENTER 1625
++smdk6410 MACH_SMDK6410 SMDK6410 1626
++u300 MACH_U300 U300 1627
++u500 MACH_U500 U500 1628
++ds9260 MACH_DS9260 DS9260 1629
++riverrock MACH_RIVERROCK RIVERROCK 1630
++scibath MACH_SCIBATH SCIBATH 1631
++at91sam7se MACH_AT91SAM7SE512EK AT91SAM7SE512EK 1632
++wrt350n_v2 MACH_WRT350N_V2 WRT350N_V2 1633
++multimedia MACH_MULTIMEDIA MULTIMEDIA 1634
++marvin MACH_MARVIN MARVIN 1635
++x500 MACH_X500 X500 1636
++awlug4lcu MACH_AWLUG4LCU AWLUG4LCU 1637
++palermoc MACH_PALERMOC PALERMOC 1638
++omap_ldp MACH_OMAP_LDP OMAP_LDP 1639
++ip500 MACH_IP500 IP500 1640
++ase2 MACH_ASE2 ASE2 1642
++mx35evb MACH_MX35EVB MX35EVB 1643
++aml_m8050 MACH_AML_M8050 AML_M8050 1644
++mx35_3ds MACH_MX35_3DS MX35_3DS 1645
++mars MACH_MARS MARS 1646
++ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647
++badger MACH_BADGER BADGER 1648
++trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649
++trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650
++marlin MACH_MARLIN MARLIN 1651
++ts78xx MACH_TS78XX TS78XX 1652
++hpipaq214 MACH_HPIPAQ214 HPIPAQ214 1653
++at572d940dcm MACH_AT572D940DCM AT572D940DCM 1654
++ne1board MACH_NE1BOARD NE1BOARD 1655
++zante MACH_ZANTE ZANTE 1656
++sffsdr MACH_SFFSDR SFFSDR 1657
++tw2662 MACH_TW2662 TW2662 1658
++vf10xx MACH_VF10XX VF10XX 1659
++zoran43xx MACH_ZORAN43XX ZORAN43XX 1660
++sonix926 MACH_SONIX926 SONIX926 1661
++celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662
++cc9m2443 MACH_CC9M2443 CC9M2443 1663
++tw5334 MACH_TW5334 TW5334 1664
++omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665
++nal_hlite MACH_NAL_HLITE NAL_HLITE 1666
++htcvogue MACH_HTCVOGUE HTCVOGUE 1667
++smartweb MACH_SMARTWEB SMARTWEB 1668
++mv86xx MACH_MV86XX MV86XX 1669
++mv87xx MACH_MV87XX MV87XX 1670
++songyoungho MACH_SONGYOUNGHO SONGYOUNGHO 1671
++younghotema MACH_YOUNGHOTEMA YOUNGHOTEMA 1672
++pcm037 MACH_PCM037 PCM037 1673
++mmvp MACH_MMVP MMVP 1674
++mmap MACH_MMAP MMAP 1675
++ptid2410 MACH_PTID2410 PTID2410 1676
++james_926 MACH_JAMES_926 JAMES_926 1677
++fm6000 MACH_FM6000 FM6000 1678
++db88f6281_bp MACH_DB88F6281_BP DB88F6281_BP 1680
++rd88f6192_nas MACH_RD88F6192_NAS RD88F6192_NAS 1681
++rd88f6281 MACH_RD88F6281 RD88F6281 1682
++db78x00_bp MACH_DB78X00_BP DB78X00_BP 1683
++smdk2416 MACH_SMDK2416 SMDK2416 1685
++oce_spider_si MACH_OCE_SPIDER_SI OCE_SPIDER_SI 1686
++oce_spider_sk MACH_OCE_SPIDER_SK OCE_SPIDER_SK 1687
++rovern6 MACH_ROVERN6 ROVERN6 1688
++pelco_evolution MACH_PELCO_EVOLUTION PELCO_EVOLUTION 1689
++wbd111 MACH_WBD111 WBD111 1690
++elaracpe MACH_ELARACPE ELARACPE 1691
++mabv3 MACH_MABV3 MABV3 1692
++mv2120 MACH_MV2120 MV2120 1693
++csb737 MACH_CSB737 CSB737 1695
++mx51_3ds MACH_MX51_3DS MX51_3DS 1696
++g900 MACH_G900 G900 1697
++apf27 MACH_APF27 APF27 1698
++ggus2000 MACH_GGUS2000 GGUS2000 1699
++omap_2430_mimic MACH_OMAP_2430_MIMIC OMAP_2430_MIMIC 1700
++imx27lite MACH_IMX27LITE IMX27LITE 1701
++almex MACH_ALMEX ALMEX 1702
++control MACH_CONTROL CONTROL 1703
++mba2410 MACH_MBA2410 MBA2410 1704
++volcano MACH_VOLCANO VOLCANO 1705
++zenith MACH_ZENITH ZENITH 1706
++muchip MACH_MUCHIP MUCHIP 1707
++magellan MACH_MAGELLAN MAGELLAN 1708
++usb_a9260 MACH_USB_A9260 USB_A9260 1709
++usb_a9263 MACH_USB_A9263 USB_A9263 1710
++qil_a9260 MACH_QIL_A9260 QIL_A9260 1711
++cme9210 MACH_CME9210 CME9210 1712
++hczh4 MACH_HCZH4 HCZH4 1713
++spearbasic MACH_SPEARBASIC SPEARBASIC 1714
++dep2440 MACH_DEP2440 DEP2440 1715
++hdl_gxr MACH_HDL_GXR HDL_GXR 1716
++hdl_gt MACH_HDL_GT HDL_GT 1717
++hdl_4g MACH_HDL_4G HDL_4G 1718
++s3c6000 MACH_S3C6000 S3C6000 1719
++mmsp2_mdk MACH_MMSP2_MDK MMSP2_MDK 1720
++mpx220 MACH_MPX220 MPX220 1721
++kzm_arm11_01 MACH_KZM_ARM11_01 KZM_ARM11_01 1722
++htc_polaris MACH_HTC_POLARIS HTC_POLARIS 1723
++htc_kaiser MACH_HTC_KAISER HTC_KAISER 1724
++lg_ks20 MACH_LG_KS20 LG_KS20 1725
++hhgps MACH_HHGPS HHGPS 1726
++nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727
++insight MACH_INSIGHT INSIGHT 1728
++sapphire MACH_SAPPHIRE SAPPHIRE 1729
++csb637xo MACH_CSB637XO CSB637XO 1730
++evisiong MACH_EVISIONG EVISIONG 1731
++stmp37xx MACH_STMP37XX STMP37XX 1732
++stmp378x MACH_STMP38XX STMP38XX 1733
++tnt MACH_TNT TNT 1734
++tbxt MACH_TBXT TBXT 1735
++playmate MACH_PLAYMATE PLAYMATE 1736
++pns10 MACH_PNS10 PNS10 1737
++eznavi MACH_EZNAVI EZNAVI 1738
++ps4000 MACH_PS4000 PS4000 1739
++ezx_a780 MACH_EZX_A780 EZX_A780 1740
++ezx_e680 MACH_EZX_E680 EZX_E680 1741
++ezx_a1200 MACH_EZX_A1200 EZX_A1200 1742
++ezx_e6 MACH_EZX_E6 EZX_E6 1743
++ezx_e2 MACH_EZX_E2 EZX_E2 1744
++ezx_a910 MACH_EZX_A910 EZX_A910 1745
++cwmx31 MACH_CWMX31 CWMX31 1746
++sl2312 MACH_SL2312 SL2312 1747
++blenny MACH_BLENNY BLENNY 1748
++ds107 MACH_DS107 DS107 1749
++dsx07 MACH_DSX07 DSX07 1750
++picocom1 MACH_PICOCOM1 PICOCOM1 1751
++lynx_wolverine MACH_LYNX_WOLVERINE LYNX_WOLVERINE 1752
++ubisys_p9_sc19 MACH_UBISYS_P9_SC19 UBISYS_P9_SC19 1753
++kratos_low MACH_KRATOS_LOW KRATOS_LOW 1754
++m700 MACH_M700 M700 1755
++edmini_v2 MACH_EDMINI_V2 EDMINI_V2 1756
++zipit2 MACH_ZIPIT2 ZIPIT2 1757
++hslfemtocell MACH_HSLFEMTOCELL HSLFEMTOCELL 1758
++daintree_at91 MACH_DAINTREE_AT91 DAINTREE_AT91 1759
++sg560usb MACH_SG560USB SG560USB 1760
++omap3_pandora MACH_OMAP3_PANDORA OMAP3_PANDORA 1761
++usr8200 MACH_USR8200 USR8200 1762
++s1s65k MACH_S1S65K S1S65K 1763
++s2s65a MACH_S2S65A S2S65A 1764
++icore MACH_ICORE ICORE 1765
++mss2 MACH_MSS2 MSS2 1766
++belmont MACH_BELMONT BELMONT 1767
++asusp525 MACH_ASUSP525 ASUSP525 1768
++lb88rc8480 MACH_LB88RC8480 LB88RC8480 1769
++hipxa MACH_HIPXA HIPXA 1770
++mx25_3ds MACH_MX25_3DS MX25_3DS 1771
++m800 MACH_M800 M800 1772
++omap3530_lv_som MACH_OMAP3530_LV_SOM OMAP3530_LV_SOM 1773
++prima_evb MACH_PRIMA_EVB PRIMA_EVB 1774
++mx31bt1 MACH_MX31BT1 MX31BT1 1775
++atlas4_evb MACH_ATLAS4_EVB ATLAS4_EVB 1776
++mx31cicada MACH_MX31CICADA MX31CICADA 1777
++mi424wr MACH_MI424WR MI424WR 1778
++axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779
++at572d940deb MACH_AT572D940DEB AT572D940DEB 1780
++davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781
++ep9302 MACH_EP9302 EP9302 1782
++at572d940hfeb MACH_AT572D940HFEB AT572D940HFEB 1783
++cybook3 MACH_CYBOOK3 CYBOOK3 1784
++wdg002 MACH_WDG002 WDG002 1785
++sg560adsl MACH_SG560ADSL SG560ADSL 1786
++nextio_n2800_ica MACH_NEXTIO_N2800_ICA NEXTIO_N2800_ICA 1787
++marvell_newdb MACH_MARVELL_NEWDB MARVELL_NEWDB 1789
++vandihud MACH_VANDIHUD VANDIHUD 1790
++magx_e8 MACH_MAGX_E8 MAGX_E8 1791
++magx_z6 MACH_MAGX_Z6 MAGX_Z6 1792
++magx_v8 MACH_MAGX_V8 MAGX_V8 1793
++magx_u9 MACH_MAGX_U9 MAGX_U9 1794
++toughcf08 MACH_TOUGHCF08 TOUGHCF08 1795
++zw4400 MACH_ZW4400 ZW4400 1796
++marat91 MACH_MARAT91 MARAT91 1797
++overo MACH_OVERO OVERO 1798
++at2440evb MACH_AT2440EVB AT2440EVB 1799
++neocore926 MACH_NEOCORE926 NEOCORE926 1800
++wnr854t MACH_WNR854T WNR854T 1801
++imx27 MACH_IMX27 IMX27 1802
++moose_db MACH_MOOSE_DB MOOSE_DB 1803
++fab4 MACH_FAB4 FAB4 1804
++htcdiamond MACH_HTCDIAMOND HTCDIAMOND 1805
++fiona MACH_FIONA FIONA 1806
++mxc30030_x MACH_MXC30030_X MXC30030_X 1807
++bmp1000 MACH_BMP1000 BMP1000 1808
++logi9200 MACH_LOGI9200 LOGI9200 1809
++tqma31 MACH_TQMA31 TQMA31 1810
++ccw9p9215js MACH_CCW9P9215JS CCW9P9215JS 1811
++rd88f5181l_ge MACH_RD88F5181L_GE RD88F5181L_GE 1812
++sifmain MACH_SIFMAIN SIFMAIN 1813
++sam9_l9261 MACH_SAM9_L9261 SAM9_L9261 1814
++cc9m2443js MACH_CC9M2443JS CC9M2443JS 1815
++xaria300 MACH_XARIA300 XARIA300 1816
++it9200 MACH_IT9200 IT9200 1817
++rd88f5181l_fxo MACH_RD88F5181L_FXO RD88F5181L_FXO 1818
++kriss_sensor MACH_KRISS_SENSOR KRISS_SENSOR 1819
++pilz_pmi5 MACH_PILZ_PMI5 PILZ_PMI5 1820
++jade MACH_JADE JADE 1821
++ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822
++gprisc4 MACH_GPRISC4 GPRISC4 1823
++stamp9260 MACH_STAMP9260 STAMP9260 1824
++smdk6430 MACH_SMDK6430 SMDK6430 1825
++smdkc100 MACH_SMDKC100 SMDKC100 1826
+diff --git a/drivers/Kconfig b/drivers/Kconfig
+index f4076d9..2645689 100644
+--- a/drivers/Kconfig
++++ b/drivers/Kconfig
+@@ -1,4 +1,4 @@
+-# drivers/Kconfig
++#drivers/Kconfig
+
+ menu "Device Drivers"
+
+@@ -95,4 +95,5 @@ source "drivers/kvm/Kconfig"
+ source "drivers/uio/Kconfig"
+
+ source "drivers/virtio/Kconfig"
++
+ endmenu
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index 2e3a0d4..5696162 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -813,6 +813,12 @@ config DS1302
+ will get access to the real time clock (or hardware clock) built
+ into your computer.
+
++config S3C_ADC
++ bool "S3C ADC Driver"
++ depends on ARCH_S3C2410
++ help
++ ADC (A/D Conversion) driver for Samsung S3C2450/2416, S3C6400/6410.
++
+ config COBALT_LCD
+ bool "Support for Cobalt LCD"
+ depends on MIPS_COBALT
+@@ -1040,5 +1046,14 @@ config DEVPORT
+
+ source "drivers/s390/char/Kconfig"
+
++config S3C_MEM
++ bool "Support for /dev/s3c-mem"
++ default y
++ ---help---
++ If you do say Y here, you can allocate physically linear memories from system memory.
++ And you can share the memory at the other process using re-allocation ioctl.
++
++ If unsure, say Y.
++
+ endmenu
+
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index 07304d5..8846ea7 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -111,6 +111,8 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o
+ obj-$(CONFIG_JS_RTC) += js-rtc.o
+ js-rtc-y = rtc.o
+
++obj-$(CONFIG_S3C_MEM) += s3c_mem.o
++
+ # Files generated that shall be removed upon make clean
+ clean-files := consolemap_deftbl.c defkeymap.c
+
+diff --git a/drivers/char/mem.c b/drivers/char/mem.c
+index 20070b7..8b15542 100644
+--- a/drivers/char/mem.c
++++ b/drivers/char/mem.c
+@@ -787,6 +787,16 @@ static const struct file_operations oldmem_fops = {
+ };
+ #endif
+
++#ifdef CONFIG_S3C_MEM
++extern int s3c_mem_mmap(struct file* filp, struct vm_area_struct *vma);
++extern int s3c_mem_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
++
++static const struct file_operations s3c_mem_fops = {
++ .ioctl = s3c_mem_ioctl,
++ .mmap = s3c_mem_mmap,
++};
++#endif
++
+ static ssize_t kmsg_write(struct file * file, const char __user * buf,
+ size_t count, loff_t *ppos)
+ {
+@@ -854,6 +864,11 @@ static int memory_open(struct inode * inode, struct file * filp)
+ filp->f_op = &oldmem_fops;
+ break;
+ #endif
++#ifdef CONFIG_S3C_MEM
++ case 13:
++ filp->f_op = &s3c_mem_fops;
++ break;
++#endif
+ default:
+ return -ENXIO;
+ }
+@@ -886,6 +901,9 @@ static const struct {
+ #ifdef CONFIG_CRASH_DUMP
+ {12,"oldmem", S_IRUSR | S_IWUSR | S_IRGRP, &oldmem_fops},
+ #endif
++#ifdef CONFIG_S3C_MEM
++ {13,"s3c-mem", S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH, &s3c_mem_fops},
++#endif
+ };
+
+ static struct class *mem_class;
+diff --git a/drivers/char/s3c_mem.c b/drivers/char/s3c_mem.c
+new file mode 100644
+index 0000000..9e31836
+--- /dev/null
++++ b/drivers/char/s3c_mem.c
+@@ -0,0 +1,287 @@
++/*
++ * drivers/char/s3c_mem.c
++ *
++ * Revision 1.0
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C MEM driver
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h> /* error codes */
++#include <asm/div64.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++#include <asm/arch/map.h>
++#include <linux/mman.h>
++
++#include <linux/unistd.h>
++
++#include <linux/version.h>
++#include <asm/dma.h>
++
++#include <asm/mach/dma.h>
++#include <asm/plat-s3c24xx/dma.h>
++#include <linux/dma-mapping.h>
++
++#include "s3c_mem.h"
++
++static int flag = 0;
++
++static unsigned int physical_address;
++
++int s3c_mem_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
++{
++
++ u32 val;
++
++ u_int virt_addr;
++ struct mm_struct *mm = current->mm;
++ struct s3c_mem_alloc param;
++
++ switch (cmd) {
++ case S3C_MEM_ALLOC:
++ mutex_lock(&mem_alloc_lock);
++ if(copy_from_user(&param, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_alloc_lock);
++ return -EFAULT;
++ }
++ flag = MEM_ALLOC;
++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0);
++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__);
++ if(param.vir_addr == -EINVAL) {
++ printk("S3C_MEM_ALLOC FAILED\n");
++ flag = 0;
++ mutex_unlock(&mem_alloc_lock);
++ return -EFAULT;
++ }
++ param.phy_addr = physical_address;
++ DEBUG("KERNEL MALLOC : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__);
++
++ if(copy_to_user((struct s3c_mem_alloc *)arg, &param, sizeof(struct s3c_mem_alloc))){
++ flag = 0;
++ mutex_unlock(&mem_alloc_lock);
++ return -EFAULT;
++ }
++ flag = 0;
++ mutex_unlock(&mem_alloc_lock);
++
++ break;
++
++ case S3C_MEM_CACHEABLE_ALLOC:
++ mutex_lock(&mem_cacheable_alloc_lock);
++ if(copy_from_user(&param, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_cacheable_alloc_lock);
++ return -EFAULT;
++ }
++ flag = MEM_ALLOC_CACHEABLE;
++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0);
++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__);
++ if(param.vir_addr == -EINVAL) {
++ printk("S3C_MEM_ALLOC FAILED\n");
++ flag = 0;
++ mutex_unlock(&mem_cacheable_alloc_lock);
++ return -EFAULT;
++ }
++ param.phy_addr = physical_address;
++ DEBUG("KERNEL MALLOC : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__);
++
++ if(copy_to_user((struct s3c_mem_alloc *)arg, &param, sizeof(struct s3c_mem_alloc))){
++ flag = 0;
++ mutex_unlock(&mem_cacheable_alloc_lock);
++ return -EFAULT;
++ }
++ flag = 0;
++ mutex_unlock(&mem_cacheable_alloc_lock);
++
++ break;
++
++ case S3C_MEM_SHARE_ALLOC:
++ mutex_lock(&mem_share_alloc_lock);
++ if(copy_from_user(&param, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_share_alloc_lock);
++ return -EFAULT;
++ }
++ flag = MEM_ALLOC_SHARE;
++ physical_address = param.phy_addr;
++ DEBUG("param.phy_addr = %08x, %d\n", physical_address, __LINE__);
++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0);
++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__);
++ if(param.vir_addr == -EINVAL) {
++ printk("S3C_MEM_SHARE_ALLOC FAILED\n");
++ flag = 0;
++ mutex_unlock(&mem_share_alloc_lock);
++ return -EFAULT;
++ }
++ DEBUG("MALLOC_SHARE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__);
++
++ if(copy_to_user((struct s3c_mem_alloc *)arg, &param, sizeof(struct s3c_mem_alloc))){
++ flag = 0;
++ mutex_unlock(&mem_share_alloc_lock);
++ return -EFAULT;
++ }
++ flag = 0;
++ mutex_unlock(&mem_share_alloc_lock);
++
++ break;
++
++ case S3C_MEM_CACHEABLE_SHARE_ALLOC:
++ mutex_lock(&mem_cacheable_share_alloc_lock);
++ if(copy_from_user(&param, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_cacheable_share_alloc_lock);
++ return -EFAULT;
++ }
++ flag = MEM_ALLOC_CACHEABLE_SHARE;
++ physical_address = param.phy_addr;
++ DEBUG("param.phy_addr = %08x, %d\n", physical_address, __LINE__);
++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0);
++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__);
++ if(param.vir_addr == -EINVAL) {
++ printk("S3C_MEM_SHARE_ALLOC FAILED\n");
++ flag = 0;
++ mutex_unlock(&mem_cacheable_share_alloc_lock);
++ return -EFAULT;
++ }
++ DEBUG("MALLOC_SHARE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__);
++
++ if(copy_to_user((struct s3c_mem_alloc *)arg, &param, sizeof(struct s3c_mem_alloc))){
++ flag = 0;
++ mutex_unlock(&mem_cacheable_share_alloc_lock);
++ return -EFAULT;
++ }
++ flag = 0;
++ mutex_unlock(&mem_cacheable_share_alloc_lock);
++
++ break;
++
++ case S3C_MEM_FREE:
++ mutex_lock(&mem_free_lock);
++ if(copy_from_user(&param, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_free_lock);
++ return -EFAULT;
++ }
++
++ DEBUG("KERNEL FREE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__);
++
++ if (do_munmap(mm, param.vir_addr, param.size) < 0) {
++ printk("do_munmap() failed !!\n");
++ mutex_unlock(&mem_free_lock);
++ return -EINVAL;
++ }
++ virt_addr = phys_to_virt(param.phy_addr);
++
++ kfree(virt_addr);
++ param.size = 0;
++ DEBUG("do_munmap() succeed !!\n");
++
++ if(copy_to_user((struct s3c_mem_alloc *)arg, &param, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_free_lock);
++ return -EFAULT;
++ }
++
++ mutex_unlock(&mem_free_lock);
++
++ break;
++
++ case S3C_MEM_SHARE_FREE:
++ mutex_lock(&mem_share_free_lock);
++ if(copy_from_user(&param, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_share_free_lock);
++ return -EFAULT;
++ }
++
++ DEBUG("MEM_SHARE_FREE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__);
++
++ if (do_munmap(mm, param.vir_addr, param.size) < 0) {
++ printk("do_munmap() failed - MEM_SHARE_FREE!!\n");
++ mutex_unlock(&mem_share_free_lock);
++ return -EINVAL;
++ }
++
++ param.vir_addr = 0;
++ DEBUG("do_munmap() succeed !! - MEM_SHARE_FREE\n");
++
++ if(copy_to_user((struct s3c_mem_alloc *)arg, &param, sizeof(struct s3c_mem_alloc))){
++ mutex_unlock(&mem_share_free_lock);
++ return -EFAULT;
++ }
++
++ mutex_unlock(&mem_share_free_lock);
++
++ break;
++
++ default:
++ DEBUG("s3c_mem_ioctl() : default !!\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++int s3c_mem_mmap(struct file* filp, struct vm_area_struct *vma)
++{
++ unsigned long pageFrameNo, size, virt_addr, phys_addr;
++
++ size = vma->vm_end - vma->vm_start;
++
++ switch (flag) {
++ case MEM_ALLOC :
++ case MEM_ALLOC_CACHEABLE :
++ virt_addr = kmalloc(size, GFP_DMA|GFP_ATOMIC);
++
++ if (virt_addr == NULL) {
++ printk("kmalloc() failed !\n");
++ return -EINVAL;
++ }
++ DEBUG("MMAP_KMALLOC : virt addr = 0x%08x, size = %d, %d\n", virt_addr, size, __LINE__);
++ phys_addr = virt_to_phys(virt_addr);
++ physical_address = (unsigned int)phys_addr;
++
++ pageFrameNo = __phys_to_pfn(phys_addr);
++ break;
++
++ case MEM_ALLOC_SHARE :
++ case MEM_ALLOC_CACHEABLE_SHARE :
++ DEBUG("MMAP_KMALLOC_SHARE : phys addr = 0x%08x, %d\n", physical_address, __LINE__);
++
++ // page frame number of the address for the physical_address to be shared.
++ pageFrameNo = __phys_to_pfn(physical_address);
++ DEBUG("MMAP_KMALLOC_SHARE : vma->end = 0x%08x, vma->start = 0x%08x, size = %d, %d\n", vma->vm_end, vma->vm_start, size, __LINE__);
++ break;
++
++ default :
++ break;
++ }
++
++ if( (flag == MEM_ALLOC) || (flag == MEM_ALLOC_SHARE) )
++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++
++ vma->vm_flags |= VM_RESERVED;
++
++ if (remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, vma->vm_page_prot)) {
++ printk("s3c_mem_mmap() : remap_pfn_range() failed !\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++EXPORT_SYMBOL(s3c_mem_ioctl);
++EXPORT_SYMBOL(s3c_mem_mmap);
+\ No newline at end of file
+diff --git a/drivers/char/s3c_mem.h b/drivers/char/s3c_mem.h
+new file mode 100644
+index 0000000..7cc7fa8
+--- /dev/null
++++ b/drivers/char/s3c_mem.h
+@@ -0,0 +1,42 @@
++#define DEBUG_S3C_MEM
++#undef DEBUG_S3C_MEM
++
++#ifdef DEBUG_S3C_MEM
++#define DEBUG(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG(fmt,args...) do {} while(0)
++#endif
++
++#define MEM_IOCTL_MAGIC 'M'
++
++#define S3C_MEM_ALLOC _IOWR(MEM_IOCTL_MAGIC, 310, struct s3c_mem_alloc)
++#define S3C_MEM_FREE _IOWR(MEM_IOCTL_MAGIC, 311, struct s3c_mem_alloc)
++
++#define S3C_MEM_SHARE_ALLOC _IOWR(MEM_IOCTL_MAGIC, 314, struct s3c_mem_alloc)
++#define S3C_MEM_SHARE_FREE _IOWR(MEM_IOCTL_MAGIC, 315, struct s3c_mem_alloc)
++
++#define S3C_MEM_CACHEABLE_ALLOC _IOWR(MEM_IOCTL_MAGIC, 316, struct s3c_mem_alloc)
++#define S3C_MEM_CACHEABLE_SHARE_ALLOC _IOWR(MEM_IOCTL_MAGIC, 317, struct s3c_mem_alloc)
++
++#define MEM_ALLOC 1
++#define MEM_ALLOC_SHARE 2
++#define MEM_ALLOC_CACHEABLE 3
++#define MEM_ALLOC_CACHEABLE_SHARE 4
++
++#define S3C_MEM_MINOR 13
++
++static DEFINE_MUTEX(mem_alloc_lock);
++static DEFINE_MUTEX(mem_free_lock);
++
++static DEFINE_MUTEX(mem_share_alloc_lock);
++static DEFINE_MUTEX(mem_share_free_lock);
++
++static DEFINE_MUTEX(mem_cacheable_alloc_lock);
++static DEFINE_MUTEX(mem_cacheable_share_alloc_lock);
++
++struct s3c_mem_alloc {
++ int size;
++ unsigned int vir_addr;
++ unsigned int phy_addr;
++};
++
+diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
+index c466c6c..1986372 100644
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -412,11 +412,18 @@ config I2C_PROSAVAGE
+
+ config I2C_S3C2410
+ tristate "S3C2410 I2C Driver"
+- depends on ARCH_S3C2410
++ depends on ARCH_S3C2410 && !PLAT_S3C64XX
+ help
+ Say Y here to include support for I2C controller in the
+ Samsung S3C2410 based System-on-Chip devices.
+
++config I2C_S3C64XX
++ tristate "S3C64XX I2C Driver"
++ depends on PLAT_S3C64XX
++ help
++ Say Y here to include support for I2C controller in the
++ Samsung S3C64XX based System-on-Chip devices.
++
+ config I2C_SAVAGE4
+ tristate "S3 Savage 4"
+ depends on PCI && EXPERIMENTAL
+diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
+index 81d43c2..4b4e3e0 100644
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -37,6 +37,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
+ obj-$(CONFIG_I2C_PROSAVAGE) += i2c-prosavage.o
+ obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
+ obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
++obj-$(CONFIG_I2C_S3C64XX) += i2c-s3c64xx.o
+ obj-$(CONFIG_I2C_SAVAGE4) += i2c-savage4.o
+ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
+ obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
+diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
+index c44ada5..51ba983 100644
+--- a/drivers/i2c/busses/i2c-s3c2410.c
++++ b/drivers/i2c/busses/i2c-s3c2410.c
+@@ -38,6 +38,7 @@
+ #include <asm/irq.h>
+ #include <asm/io.h>
+
++#include <asm/arch/gpio.h>
+ #include <asm/arch/regs-gpio.h>
+ #include <asm/plat-s3c/regs-iic.h>
+ #include <asm/plat-s3c/iic.h>
+@@ -709,10 +710,18 @@ static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
+
+ pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
+
++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410)
+ /* inititalise the gpio */
+
+ s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
+ s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
++#else
++ /*Set I2C port to controll WM8753 codec*/
++ gpio_pullup(S3C_GPB5, 0);
++ gpio_pullup(S3C_GPB6, 0);
++ gpio_set_pin(S3C_GPB5, S3C_GPB5_I2C_SCL);
++ gpio_set_pin(S3C_GPB6, S3C_GPB6_I2C_SDA);
++#endif
+
+ /* write slave address */
+
+diff --git a/drivers/i2c/busses/i2c-s3c64xx.c b/drivers/i2c/busses/i2c-s3c64xx.c
+new file mode 100644
+index 0000000..dee1fc7
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-s3c64xx.c
+@@ -0,0 +1,908 @@
++/* linux/drivers/i2c/busses/i2c-s3c64xx.c
++ *
++ * Copyright (C) 2004,2005 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * S3C64XX I2C Controller
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++
++#include <linux/i2c.h>
++#include <linux/i2c-id.h>
++#include <linux/init.h>
++#include <linux/time.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/plat-s3c/regs-iic.h>
++#include <asm/plat-s3c/iic.h>
++
++/* i2c controller state */
++
++enum s3c64xx_i2c_state {
++ STATE_IDLE,
++ STATE_START,
++ STATE_READ,
++ STATE_WRITE,
++ STATE_STOP
++};
++
++struct s3c64xx_i2c {
++ spinlock_t lock;
++ wait_queue_head_t wait;
++
++ struct i2c_msg *msg;
++ unsigned int msg_num;
++ unsigned int msg_idx;
++ unsigned int msg_ptr;
++
++ unsigned int tx_setup;
++
++ enum s3c64xx_i2c_state state;
++ unsigned long clkrate;
++
++ void __iomem *regs;
++ struct clk *clk;
++ struct device *dev;
++ struct resource *irq;
++ struct resource *ioarea;
++ struct i2c_adapter adap;
++};
++
++/* s3c64xx_i2c_master_complete
++ *
++ * complete the message and wake up the caller, using the given return code,
++ * or zero to mean ok.
++*/
++
++static inline void s3c64xx_i2c_master_complete(struct s3c64xx_i2c *i2c, int ret)
++{
++ dev_dbg(i2c->dev, "master_complete %d\n", ret);
++
++ i2c->msg_ptr = 0;
++ i2c->msg = NULL;
++ i2c->msg_idx++;
++ i2c->msg_num = 0;
++ if (ret)
++ i2c->msg_idx = ret;
++
++ wake_up(&i2c->wait);
++}
++
++static inline void s3c64xx_i2c_disable_ack(struct s3c64xx_i2c *i2c)
++{
++ unsigned long tmp;
++
++ tmp = readl(i2c->regs + S3C64XX_IICCON);
++ writel(tmp & ~S3C64XX_IICCON_ACKEN, i2c->regs + S3C64XX_IICCON);
++
++}
++
++static inline void s3c64xx_i2c_enable_ack(struct s3c64xx_i2c *i2c)
++{
++ unsigned long tmp;
++
++ tmp = readl(i2c->regs + S3C64XX_IICCON);
++ writel(tmp | S3C64XX_IICCON_ACKEN, i2c->regs + S3C64XX_IICCON);
++
++}
++
++/* irq enable/disable functions */
++
++static inline void s3c64xx_i2c_disable_irq(struct s3c64xx_i2c *i2c)
++{
++ unsigned long tmp;
++
++ tmp = readl(i2c->regs + S3C64XX_IICCON);
++ writel(tmp & ~S3C64XX_IICCON_IRQEN, i2c->regs + S3C64XX_IICCON);
++}
++
++static inline void s3c64xx_i2c_enable_irq(struct s3c64xx_i2c *i2c)
++{
++ unsigned long tmp;
++
++ tmp = readl(i2c->regs + S3C64XX_IICCON);
++ writel(tmp | S3C64XX_IICCON_IRQEN, i2c->regs + S3C64XX_IICCON);
++}
++
++
++/* s3c64xx_i2c_message_start
++ *
++ * put the start of a message onto the bus
++*/
++
++static void s3c64xx_i2c_message_start(struct s3c64xx_i2c *i2c,
++ struct i2c_msg *msg)
++{
++ unsigned int addr = (msg->addr & 0x7f) << 1;
++ unsigned long stat;
++ unsigned long iiccon;
++
++ stat = 0;
++ stat |= S3C64XX_IICSTAT_TXRXEN;
++
++ if (msg->flags & I2C_M_RD) {
++ stat |= S3C64XX_IICSTAT_MASTER_RX;
++ addr |= 1;
++ } else
++ stat |= S3C64XX_IICSTAT_MASTER_TX;
++
++ if (msg->flags & I2C_M_REV_DIR_ADDR)
++ addr ^= 1;
++
++ // todo - check for wether ack wanted or not
++ s3c64xx_i2c_enable_ack(i2c);
++
++ iiccon = readl(i2c->regs + S3C64XX_IICCON);
++ writel(stat, i2c->regs + S3C64XX_IICSTAT);
++
++ dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
++ writeb(addr, i2c->regs + S3C64XX_IICDS);
++
++ /* delay here to ensure the data byte has gotten onto the bus
++ * before the transaction is started */
++
++ ndelay(i2c->tx_setup);
++
++ dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
++ writel(iiccon, i2c->regs + S3C64XX_IICCON);
++
++ stat |= S3C64XX_IICSTAT_START;
++ writel(stat, i2c->regs + S3C64XX_IICSTAT);
++}
++
++static inline void s3c64xx_i2c_stop(struct s3c64xx_i2c *i2c, int ret)
++{
++ unsigned long iicstat = readl(i2c->regs + S3C64XX_IICSTAT);
++
++ dev_dbg(i2c->dev, "STOP\n");
++
++ /* stop the transfer */
++ iicstat &= ~ S3C64XX_IICSTAT_START;
++ writel(iicstat, i2c->regs + S3C64XX_IICSTAT);
++
++ i2c->state = STATE_STOP;
++
++ s3c64xx_i2c_master_complete(i2c, ret);
++ s3c64xx_i2c_disable_irq(i2c);
++}
++
++/* helper functions to determine the current state in the set of
++ * messages we are sending */
++
++/* is_lastmsg()
++ *
++ * returns TRUE if the current message is the last in the set
++*/
++
++static inline int is_lastmsg(struct s3c64xx_i2c *i2c)
++{
++ return i2c->msg_idx >= (i2c->msg_num - 1);
++}
++
++/* is_msglast
++ *
++ * returns TRUE if we this is the last byte in the current message
++*/
++
++static inline int is_msglast(struct s3c64xx_i2c *i2c)
++{
++ return i2c->msg_ptr == i2c->msg->len-1;
++}
++
++/* is_msgend
++ *
++ * returns TRUE if we reached the end of the current message
++*/
++
++static inline int is_msgend(struct s3c64xx_i2c *i2c)
++{
++ return i2c->msg_ptr >= i2c->msg->len;
++}
++
++/* i2s_s3c_irq_nextbyte
++ *
++ * process an interrupt and work out what to do
++ */
++
++static int i2s_s3c_irq_nextbyte(struct s3c64xx_i2c *i2c, unsigned long iicstat)
++{
++ unsigned long tmp;
++ unsigned char byte;
++ int ret = 0;
++
++ switch (i2c->state) {
++
++ case STATE_IDLE:
++ dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __FUNCTION__);
++ goto out;
++ break;
++
++ case STATE_STOP:
++ dev_err(i2c->dev, "%s: called in STATE_STOP\n", __FUNCTION__);
++ s3c64xx_i2c_disable_irq(i2c);
++ goto out_ack;
++
++ case STATE_START:
++ /* last thing we did was send a start condition on the
++ * bus, or started a new i2c message
++ */
++
++ if (iicstat & S3C64XX_IICSTAT_LASTBIT &&
++ !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
++ /* ack was not received... */
++
++ dev_dbg(i2c->dev, "ack was not received\n");
++ s3c64xx_i2c_stop(i2c, -EREMOTEIO);
++ goto out_ack;
++ }
++
++ if (i2c->msg->flags & I2C_M_RD)
++ i2c->state = STATE_READ;
++ else
++ i2c->state = STATE_WRITE;
++
++ /* terminate the transfer if there is nothing to do
++ * (used by the i2c probe to find devices */
++
++ if (is_lastmsg(i2c) && i2c->msg->len == 0) {
++ s3c64xx_i2c_stop(i2c, 0);
++ goto out_ack;
++ }
++
++ if (i2c->state == STATE_READ)
++ goto prepare_read;
++
++ /* fall through to the write state, as we will need to
++ * send a byte as well */
++
++ case STATE_WRITE:
++ /* we are writing data to the device... check for the
++ * end of the message, and if so, work out what to do
++ */
++ if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
++ if (iicstat & S3C64XX_IICSTAT_LASTBIT) {
++ dev_dbg(i2c->dev, "WRITE: No Ack\n");
++
++ s3c64xx_i2c_stop(i2c, -ECONNREFUSED);
++ goto out_ack;
++ }
++ }
++
++ retry_write:
++ if (!is_msgend(i2c)) {
++ byte = i2c->msg->buf[i2c->msg_ptr++];
++ writeb(byte, i2c->regs + S3C64XX_IICDS);
++
++ /* delay after writing the byte to allow the
++ * data setup time on the bus, as writing the
++ * data to the register causes the first bit
++ * to appear on SDA, and SCL will change as
++ * soon as the interrupt is acknowledged */
++
++ ndelay(i2c->tx_setup);
++
++ } else if (!is_lastmsg(i2c)) {
++ /* we need to go to the next i2c message */
++
++ dev_dbg(i2c->dev, "WRITE: Next Message\n");
++
++ i2c->msg_ptr = 0;
++ i2c->msg_idx++;
++ i2c->msg++;
++
++ /* check to see if we need to do another message */
++ if (i2c->msg->flags & I2C_M_NOSTART) {
++
++ if (i2c->msg->flags & I2C_M_RD) {
++ /* cannot do this, the controller
++ * forces us to send a new START
++ * when we change direction */
++
++ s3c64xx_i2c_stop(i2c, -EINVAL);
++ }
++
++ goto retry_write;
++ } else {
++
++ /* send the new start */
++ s3c64xx_i2c_message_start(i2c, i2c->msg);
++ i2c->state = STATE_START;
++ }
++
++ } else {
++ /* send stop */
++
++ s3c64xx_i2c_stop(i2c, 0);
++ }
++ break;
++
++ case STATE_READ:
++ /* we have a byte of data in the data register, do
++ * something with it, and then work out wether we are
++ * going to do any more read/write
++ */
++
++ byte = readb(i2c->regs + S3C64XX_IICDS);
++ i2c->msg->buf[i2c->msg_ptr++] = byte;
++
++ prepare_read:
++ if (is_msglast(i2c)) {
++ /* last byte of buffer */
++
++ if (is_lastmsg(i2c))
++ s3c64xx_i2c_disable_ack(i2c);
++
++ } else if (is_msgend(i2c)) {
++ /* ok, we've read the entire buffer, see if there
++ * is anything else we need to do */
++
++ if (is_lastmsg(i2c)) {
++ /* last message, send stop and complete */
++ dev_dbg(i2c->dev, "READ: Send Stop\n");
++
++ s3c64xx_i2c_stop(i2c, 0);
++ } else {
++ /* go to the next transfer */
++ dev_dbg(i2c->dev, "READ: Next Transfer\n");
++
++ i2c->msg_ptr = 0;
++ i2c->msg_idx++;
++ i2c->msg++;
++ }
++ }
++
++ break;
++ }
++
++ /* acknowlegde the IRQ and get back on with the work */
++
++ out_ack:
++ tmp = readl(i2c->regs + S3C64XX_IICCON);
++ tmp &= ~S3C64XX_IICCON_IRQPEND;
++ writel(tmp, i2c->regs + S3C64XX_IICCON);
++ out:
++ return ret;
++}
++
++/* s3c64xx_i2c_irq
++ *
++ * top level IRQ servicing routine
++*/
++
++static irqreturn_t s3c64xx_i2c_irq(int irqno, void *dev_id)
++{
++ struct s3c64xx_i2c *i2c = dev_id;
++ unsigned long status;
++ unsigned long tmp;
++
++ status = readl(i2c->regs + S3C64XX_IICSTAT);
++
++ if (status & S3C64XX_IICSTAT_ARBITR) {
++ // deal with arbitration loss
++ dev_err(i2c->dev, "deal with arbitration loss\n");
++ }
++
++ if (i2c->state == STATE_IDLE) {
++ dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
++
++ tmp = readl(i2c->regs + S3C64XX_IICCON);
++ tmp &= ~S3C64XX_IICCON_IRQPEND;
++ writel(tmp, i2c->regs + S3C64XX_IICCON);
++ goto out;
++ }
++
++ /* pretty much this leaves us with the fact that we've
++ * transmitted or received whatever byte we last sent */
++
++ i2s_s3c_irq_nextbyte(i2c, status);
++
++ out:
++ return IRQ_HANDLED;
++}
++
++
++/* s3c64xx_i2c_set_master
++ *
++ * get the i2c bus for a master transaction
++*/
++
++static int s3c64xx_i2c_set_master(struct s3c64xx_i2c *i2c)
++{
++ unsigned long iicstat;
++ int timeout = 400;
++
++ while (timeout-- > 0) {
++ iicstat = readl(i2c->regs + S3C64XX_IICSTAT);
++
++ if (!(iicstat & S3C64XX_IICSTAT_BUSBUSY))
++ return 0;
++
++ msleep(1);
++ }
++
++ return -ETIMEDOUT;
++}
++
++/* s3c64xx_i2c_doxfer
++ *
++ * this starts an i2c transfer
++*/
++
++static int s3c64xx_i2c_doxfer(struct s3c64xx_i2c *i2c, struct i2c_msg *msgs, int num)
++{
++ unsigned long timeout;
++ int ret;
++
++ ret = s3c64xx_i2c_set_master(i2c);
++ if (ret != 0) {
++ dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
++ ret = -EAGAIN;
++ goto out;
++ }
++
++ spin_lock_irq(&i2c->lock);
++
++ i2c->msg = msgs;
++ i2c->msg_num = num;
++ i2c->msg_ptr = 0;
++ i2c->msg_idx = 0;
++ i2c->state = STATE_START;
++
++ s3c64xx_i2c_enable_irq(i2c);
++ s3c64xx_i2c_message_start(i2c, msgs);
++ spin_unlock_irq(&i2c->lock);
++
++ timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
++
++ ret = i2c->msg_idx;
++
++ /* having these next two as dev_err() makes life very
++ * noisy when doing an i2cdetect */
++
++ if (timeout == 0)
++ dev_dbg(i2c->dev, "timeout\n");
++ else if (ret != num)
++ dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
++
++ /* ensure the stop has been through the bus */
++
++ msleep(1);
++
++ out:
++ return ret;
++}
++
++/* s3c64xx_i2c_xfer
++ *
++ * first port of call from the i2c bus code when an message needs
++ * transferring across the i2c bus.
++*/
++
++static int s3c64xx_i2c_xfer(struct i2c_adapter *adap,
++ struct i2c_msg *msgs, int num)
++{
++ struct s3c64xx_i2c *i2c = (struct s3c64xx_i2c *)adap->algo_data;
++ int retry;
++ int ret;
++
++ for (retry = 0; retry < adap->retries; retry++) {
++
++ ret = s3c64xx_i2c_doxfer(i2c, msgs, num);
++
++ if (ret != -EAGAIN)
++ return ret;
++
++ dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
++
++ udelay(100);
++ }
++
++ return -EREMOTEIO;
++}
++
++/* declare our i2c functionality */
++static u32 s3c64xx_i2c_func(struct i2c_adapter *adap)
++{
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
++}
++
++/* i2c bus registration info */
++
++static const struct i2c_algorithm s3c64xx_i2c_algorithm = {
++ .master_xfer = s3c64xx_i2c_xfer,
++ .functionality = s3c64xx_i2c_func,
++};
++
++/* s3c64xx_i2c_calcdivisor
++ *
++ * return the divisor settings for a given frequency
++*/
++
++static int s3c64xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
++ unsigned int *div1, unsigned int *divs)
++{
++ unsigned int calc_divs = clkin / wanted;
++ unsigned int calc_div1;
++
++ if (calc_divs > (16*16))
++ calc_div1 = 512;
++ else
++ calc_div1 = 16;
++
++ calc_divs += calc_div1-1;
++ calc_divs /= calc_div1;
++
++ if (calc_divs == 0)
++ calc_divs = 1;
++ if (calc_divs > 17)
++ calc_divs = 17;
++
++ *divs = calc_divs;
++ *div1 = calc_div1;
++
++ return clkin / (calc_divs * calc_div1);
++}
++
++/* freq_acceptable
++ *
++ * test wether a frequency is within the acceptable range of error
++*/
++
++static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
++{
++ int diff = freq - wanted;
++
++ return (diff >= -2 && diff <= 2);
++}
++
++/* s3c64xx_i2c_getdivisor
++ *
++ * work out a divisor for the user requested frequency setting,
++ * either by the requested frequency, or scanning the acceptable
++ * range of frequencies until something is found
++*/
++
++static int s3c64xx_i2c_clockrate(struct s3c64xx_i2c *i2c, unsigned int *got)
++{
++ struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
++ unsigned long clkin = clk_get_rate(i2c->clk);
++ unsigned int divs, div1;
++ u32 iiccon;
++ int freq;
++ int start, end;
++
++ i2c->clkrate = clkin;
++ clkin /= 1000; /* clkin now in KHz */
++
++ dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
++ pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
++
++ if (pdata->bus_freq != 0) {
++ freq = s3c64xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
++ &div1, &divs);
++ if (freq_acceptable(freq, pdata->bus_freq/1000))
++ goto found;
++ }
++
++ /* ok, we may have to search for something suitable... */
++
++ start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
++ end = pdata->min_freq;
++
++ start /= 1000;
++ end /= 1000;
++
++ /* search loop... */
++
++ for (; start > end; start--) {
++ freq = s3c64xx_i2c_calcdivisor(clkin, start, &div1, &divs);
++ if (freq_acceptable(freq, start))
++ goto found;
++ }
++
++ /* cannot find frequency spec */
++
++ return -EINVAL;
++
++ found:
++ *got = freq;
++
++ iiccon = readl(i2c->regs + S3C64XX_IICCON);
++ iiccon &= ~(S3C64XX_IICCON_SCALEMASK | S3C64XX_IICCON_TXDIV_512);
++ iiccon |= (divs-1);
++
++ if (div1 == 512)
++ iiccon |= S3C64XX_IICCON_TXDIV_512;
++
++ writel(iiccon, i2c->regs + S3C64XX_IICCON);
++
++ return 0;
++}
++
++/* s3c64xx_i2c_init
++ *
++ * initialise the controller, set the IO lines and frequency
++*/
++
++static int s3c64xx_i2c_init(struct s3c64xx_i2c *i2c)
++{
++ unsigned long iicon = S3C64XX_IICCON_IRQEN | S3C64XX_IICCON_ACKEN;
++ struct s3c2410_platform_i2c *pdata;
++ unsigned int freq;
++
++ /* get the plafrom data */
++
++ pdata = i2c->dev->platform_data;
++
++ if (pdata->cfg_gpio)
++ pdata->cfg_gpio(to_platform_device(i2c->dev));
++
++ /* write slave address */
++
++ writeb(pdata->slave_addr, i2c->regs + S3C64XX_IICADD);
++
++ dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
++
++ writel(iicon, i2c->regs + S3C64XX_IICCON);
++
++ /* we need to work out the divisors for the clock... */
++
++ if (s3c64xx_i2c_clockrate(i2c, &freq) != 0) {
++ writel(0, i2c->regs + S3C64XX_IICCON);
++ dev_err(i2c->dev, "cannot meet bus frequency required\n");
++ return -EINVAL;
++ }
++
++ /* todo - check that the i2c lines aren't being dragged anywhere */
++
++ dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
++ dev_dbg(i2c->dev, "S3C64XX_IICCON=0x%02lx\n", iicon);
++
++ return 0;
++}
++
++/* s3c64xx_i2c_probe
++ *
++ * called by the bus driver when a suitable device is found
++*/
++
++static int s3c64xx_i2c_probe(struct platform_device *pdev)
++{
++ struct s3c64xx_i2c *i2c;
++ struct s3c2410_platform_i2c *pdata;
++ struct resource *res;
++ int ret;
++
++ pdata = pdev->dev.platform_data;
++ if (!pdata) {
++ dev_err(&pdev->dev, "no platform data\n");
++ return -EINVAL;
++ }
++
++ i2c = kzalloc(sizeof(struct s3c64xx_i2c), GFP_KERNEL);
++ if (!i2c) {
++ dev_err(&pdev->dev, "no memory for state\n");
++ return -ENOMEM;
++ }
++
++ strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
++ i2c->adap.owner = THIS_MODULE;
++ i2c->adap.algo = &s3c64xx_i2c_algorithm;
++ i2c->adap.retries = 2;
++ i2c->adap.class = I2C_CLASS_HWMON;
++ i2c->tx_setup = 50;
++
++ spin_lock_init(&i2c->lock);
++ init_waitqueue_head(&i2c->wait);
++
++ /* find the clock and enable it */
++
++ i2c->dev = &pdev->dev;
++ i2c->clk = clk_get(&pdev->dev, "i2c");
++ if (IS_ERR(i2c->clk)) {
++ dev_err(&pdev->dev, "cannot get clock\n");
++ ret = -ENOENT;
++ goto err_noclk;
++ }
++
++ dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
++
++ clk_enable(i2c->clk);
++
++ /* map the registers */
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res == NULL) {
++ dev_err(&pdev->dev, "cannot find IO resource\n");
++ ret = -ENOENT;
++ goto err_clk;
++ }
++
++ i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
++ pdev->name);
++
++ if (i2c->ioarea == NULL) {
++ dev_err(&pdev->dev, "cannot request IO\n");
++ ret = -ENXIO;
++ goto err_clk;
++ }
++
++ i2c->regs = ioremap(res->start, (res->end-res->start)+1);
++
++ if (i2c->regs == NULL) {
++ dev_err(&pdev->dev, "cannot map IO\n");
++ ret = -ENXIO;
++ goto err_ioarea;
++ }
++
++ dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
++
++ /* setup info block for the i2c core */
++
++ i2c->adap.algo_data = i2c;
++ i2c->adap.dev.parent = &pdev->dev;
++
++ /* initialise the i2c controller */
++
++ ret = s3c64xx_i2c_init(i2c);
++ if (ret != 0)
++ goto err_iomap;
++
++ /* find the IRQ for this unit (note, this relies on the init call to
++ * ensure no current IRQs pending
++ */
++
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (res == NULL) {
++ dev_err(&pdev->dev, "cannot find IRQ\n");
++ ret = -ENOENT;
++ goto err_iomap;
++ }
++
++ ret = request_irq(res->start, s3c64xx_i2c_irq, IRQF_DISABLED,
++ pdev->name, i2c);
++
++ if (ret != 0) {
++ dev_err(&pdev->dev, "cannot claim IRQ\n");
++ goto err_iomap;
++ }
++
++ i2c->irq = res;
++
++ dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
++ (unsigned long)res->start);
++
++ /* Note, previous versions of the driver used i2c_add_adapter()
++ * to add the bus at any number. We now pass the bus number via
++ * the platform data, so if unset it will now default to always
++ * being bus 0.
++ */
++
++ i2c->adap.nr = pdata->bus_num;
++
++ ret = i2c_add_numbered_adapter(&i2c->adap);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to add bus to i2c core\n");
++ goto err_irq;
++ }
++
++ platform_set_drvdata(pdev, i2c);
++
++ dev_info(&pdev->dev, "%s: S3C64XX I2C adapter\n", i2c->adap.dev.bus_id);
++ return 0;
++
++ err_irq:
++ free_irq(i2c->irq->start, i2c);
++
++ err_iomap:
++ iounmap(i2c->regs);
++
++ err_ioarea:
++ release_resource(i2c->ioarea);
++ kfree(i2c->ioarea);
++
++ err_clk:
++ clk_disable(i2c->clk);
++ clk_put(i2c->clk);
++
++ err_noclk:
++ return ret;
++}
++
++/* s3c64xx_i2c_remove
++ *
++ * called when device is removed from the bus
++*/
++
++static int s3c64xx_i2c_remove(struct platform_device *pdev)
++{
++ struct s3c64xx_i2c *i2c = platform_get_drvdata(pdev);
++
++ i2c_del_adapter(&i2c->adap);
++ free_irq(i2c->irq->start, i2c);
++
++ clk_disable(i2c->clk);
++ clk_put(i2c->clk);
++
++ iounmap(i2c->regs);
++
++ release_resource(i2c->ioarea);
++ kfree(i2c->ioarea);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c64xx_i2c_resume(struct platform_device *dev)
++{
++ struct s3c64xx_i2c *i2c = platform_get_drvdata(dev);
++
++ if (i2c != NULL)
++ s3c64xx_i2c_init(i2c);
++
++ return 0;
++}
++
++#else
++#define s3c64xx_i2c_resume NULL
++#endif
++
++/* device driver for platform bus bits */
++
++static struct platform_driver s3c64xx_i2c_driver = {
++ .probe = s3c64xx_i2c_probe,
++ .remove = s3c64xx_i2c_remove,
++ .resume = s3c64xx_i2c_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c64xx-i2c",
++ },
++};
++
++static int __init i2c_adap_s3c_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&s3c64xx_i2c_driver);
++
++ return ret;
++}
++
++static void __exit i2c_adap_s3c_exit(void)
++{
++ platform_driver_unregister(&s3c64xx_i2c_driver);
++}
++
++module_init(i2c_adap_s3c_init);
++module_exit(i2c_adap_s3c_exit);
++
++MODULE_DESCRIPTION("S3C64XX I2C Bus driver");
++MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
+index fb06555..3993702 100644
+--- a/drivers/ide/Kconfig
++++ b/drivers/ide/Kconfig
+@@ -887,6 +887,39 @@ config BLK_DEV_IDE_BAST
+ Say Y here if you want to support the onboard IDE channels on the
+ Simtec BAST or the Thorcom VR1000
+
++config BLK_DEV_IDE_S3C
++ tristate "Samsung S3C IDE Controller"
++ depends on ARM
++ help
++ Say Y here if you want to support the onboard IDE channels on the
++ Simtec BAST or the Thorcom VR1000
++
++config BLK_DEV_IDE_S3C_DIRECT
++ bool "Use DIRECT Mode"
++ default y
++ depends on BLK_DEV_IDE_S3C && (!ARCH_S3C2443)
++ help
++ Say Y here if you want to use DIRECT Mode.
++
++config BLK_DEV_IDE_S3C_PDMA
++ bool "Use DMA in PIO Mode"
++ depends on BLK_DEV_IDE_S3C
++ help
++ Say Y here if you want to support the DMA in PIO Mode.
++
++config BLK_DEV_IDE_S3C_UDMA
++ bool "Use UDMA Mode"
++ depends on BLK_DEV_IDE_S3C && (!ARCH_S3C2443)
++ help
++ Say Y here if you want to support the UDMA.
++
++config IDE_HOOK_IRQ
++ bool "Hooking ATA Interrupt to manage Device"
++ default y
++ depends on BLK_DEV_IDE_S3C
++ help
++ Say Y here if you want to use ATA device.
++
+ config ETRAX_IDE
+ bool "ETRAX IDE support"
+ depends on CRIS && BROKEN
+@@ -1111,7 +1144,7 @@ config BLK_DEV_UMC8672
+ endif
+
+ config BLK_DEV_IDEDMA
+- def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
++ def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA || BLK_DEV_IDE_S3C_UDMA
+
+ config IDE_ARCH_OBSOLETE_INIT
+ def_bool ALPHA || (ARM && !ARCH_L7200) || BLACKFIN || X86 || IA64 || M32R || MIPS || PARISC || PPC || (SUPERH64 && BLK_DEV_IDEPCI) || SPARC
+diff --git a/drivers/ide/arm/Makefile b/drivers/ide/arm/Makefile
+index 6a78f07..e8d4d9b 100644
+--- a/drivers/ide/arm/Makefile
++++ b/drivers/ide/arm/Makefile
+@@ -2,5 +2,6 @@
+ obj-$(CONFIG_BLK_DEV_IDE_ICSIDE) += icside.o
+ obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapide.o
+ obj-$(CONFIG_BLK_DEV_IDE_BAST) += bast-ide.o
++obj-$(CONFIG_BLK_DEV_IDE_S3C) += s3c-ide.o
+
+ EXTRA_CFLAGS := -Idrivers/ide
+diff --git a/drivers/ide/arm/s3c-ide.c b/drivers/ide/arm/s3c-ide.c
+new file mode 100644
+index 0000000..be6af3c
+--- /dev/null
++++ b/drivers/ide/arm/s3c-ide.c
+@@ -0,0 +1,1223 @@
++/*
++ * $Id: s3c-ide.c,v 1.9 2008/06/11 01:00:33 scsuh Exp $
++ *
++ * linux/drivers/ide/arm/s3c-ide.c
++ * Copyright(C) Samsung Electronics 2006
++ * Seung-Chull, Suh <sc.suh@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it under
++ * the terms of the GNU General Public License as published by the Free Software
++ * Foundation; either version 2 of the License, or (at your option) any later
++ * version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
++ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
++ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/types.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++
++#include <linux/init.h>
++#include <linux/ide.h>
++#include <linux/sysdev.h>
++#include <linux/scatterlist.h>
++
++#include <linux/dma-mapping.h>
++#include <linux/proc_fs.h>
++#include <linux/clk.h>
++
++#include "../ide-timing.h"
++
++#include <asm/dma.h>
++#include <asm/dma-mapping.h>
++
++#include <asm/arch/regs-ide.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c6400-clock.h>
++
++#include <asm/io.h>
++#include "s3c-ide.h"
++
++#define DRV_NAME "s3c-ide"
++#define DRV_VERSION "0.7"
++#define DRV_AUTHOR "Seung-Chull, Suh <sc.suh@samsung.com>"
++
++#undef DBG_ATA
++#ifdef DBG_ATA
++#define DbgAta(x...) printk(x)
++#else
++#define DbgAta(x...) do {} while(0);
++#endif
++
++static s3c_ide_hwif_t s3c_ide_hwif;
++
++static void __iomem *ata_base;
++/*=========================================================================
++ * ata controller register functions
++ *=========================================================================
++ */
++static inline int ata_status_check (ide_drive_t * drive, u8 startend)
++{
++ u8 stat;
++ uint i;
++
++ for (i=0; i<10000000; i++) {
++ stat = HWIF(drive)->INB(IDE_STATUS_REG);
++ if ((stat == 0x58) && (startend == 0)) // for starting
++ return 0;
++ else if ((stat == 0x50) && (startend == 1))// for ending
++ return 0;
++ }
++ printk("got error in ata_status_check : %08x\n", stat);
++ return -1;
++}
++
++static inline int bus_fifo_status_check (BUS_STATE status)
++{
++ u32 temp;
++ uint i;
++
++ for (i=0; i<10000000; i++) {
++ temp = readl(ata_base + S3C_BUS_FIFO_STATUS);
++ /* wait for IDLE */
++ if ((temp == 0) && (status == IDLE)) {
++ return 0;
++ }
++ /* wait for PAUSEW */
++ else if (((temp >> 16) == 0x5) && (status == PAUSEW)) {
++ return 0;
++ }
++ /* wait for PAUSER2 and read/write pointer 0 */
++ else if ((temp == 0x60000) && (status == PAUSER2)) {
++ return 0;
++ }
++ }
++ return temp;
++}
++
++/*
++ * return 0: OK
++ * return -1: got error
++ */
++static inline int wait_for_host_ready (void)
++{
++ u32 temp;
++ uint i;
++
++ for (i=0; i<10000000; i++) {
++ temp = readl(ata_base + S3C_ATA_FIFO_STATUS);
++ if ((temp >> 28) == 0) {
++ return 0;
++ }
++ DbgAta("S3C_ATA_FIFO_STATUS: %08x\n", temp);
++ }
++ printk("got error in host ready: %08x\n", temp);
++ return -1;
++}
++
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++static u8 read_dev_reg (uint reg)
++{
++ u8 temp;
++
++ wait_for_host_ready();
++ temp = readb(ata_base + reg);
++ wait_for_host_ready();
++ temp = readb(ata_base + S3C_ATA_PIO_RDATA);
++ return temp;
++}
++
++#define STATUS_DEVICE_BUSY 0x80
++static int wait_for_dev_ready (void)
++{
++ u8 temp;
++ uint i;
++
++ for (i=0; i<1000000; i++) {
++ temp = read_dev_reg((uint)S3C_ATA_PIO_CSD);
++// printf("temp2: %08x\n", temp);
++ if ((temp & STATUS_DEVICE_BUSY) == 0) {
++ DbgAta("temp2: %08x\n", temp);
++ DbgAta("wait_for_dev_ready: %d\n", i);
++ return 0;
++ }
++ }
++
++ printk("wait_for_dev_ready: error\n");
++ return -1;
++}
++#endif
++
++#if defined(CONFIG_BLK_DEV_IDE_S3C_UDMA) || defined(CONFIG_BLK_DEV_IDE_S3C_PDMA)
++static void set_config_mode (ATA_MODE mode, int rw)
++{
++ u32 reg = readl(ata_base + S3C_ATA_CFG) & ~(0x39c);
++
++ /* set mode */
++ reg |= mode << 2;
++
++ /* DMA write mode */
++ if (mode && rw)
++ reg |= 0x10;
++
++ /* set ATA DMA auto mode (enable multi block transfer) */
++ if (mode == UDMA)
++ reg |= 0x380;
++
++ writel(reg, ata_base + S3C_ATA_CFG);
++ DbgAta("2:S3C_ATA_CFG = 0x%08x\n", readl(ata_base + S3C_ATA_CFG));
++}
++#endif
++
++#if defined CONFIG_ARCH_S3C2443 || defined (CONFIG_CPU_S3C2450)
++static void init_buf_ctrl (void)
++{
++#if 0
++ /* for EVT0 board */
++ u32 reg = readl(S3C_GPBCON);
++
++ reg &= 0xffffc0fc;
++ reg |= (1<<12 | 1<<10 | 1<<8 | 1<<0);
++ writel(reg, S3C_GPBCON);
++ printk("GPBCON = 0x%08x\n", readl(S3C_GPBCON));
++#else
++ /* for EVT1 board */
++ u32 reg = readl(S3C2410_GPADAT);
++
++ reg &= ~(1<<5);
++ writel(reg, S3C2410_GPADAT);
++
++#endif
++}
++
++static void change_board_buf_mode (ATA_MODE mode, uint rw)
++{
++ u32 reg = readl(S3C2410_GPBDAT) & 0xffffff8e; /* 0,4,5,6 */
++
++ if (mode == UDMA) {
++ /* GPB0->high,GPB4->high => UDMA mode */
++ reg |= (1<<4)|(1);
++ if (rw)
++ reg |= (1<<5);
++ } else {
++ /* GPB0->high,GPB4->low => PIO mode */
++ reg |= (1<<6)|1;
++ }
++ writel(reg, S3C2410_GPBDAT);
++}
++#endif /* CONFIG_ARCH_S3C2443 */
++
++static void set_ata_enable (uint on)
++{
++ u32 temp;
++
++ temp = readl(ata_base + S3C_ATA_CTRL);
++
++ if (on)
++ writel(temp | 0x1, ata_base + S3C_ATA_CTRL);
++ else
++ writel(temp & 0xfffffffe, ata_base + S3C_ATA_CTRL);
++}
++
++static void set_endian_mode (uint little)
++{
++ u32 reg = readl(ata_base + S3C_ATA_CFG);
++
++ /* set Little endian */
++ if (little)
++ reg &= (~0x40);
++ else
++ reg |= 0x40;
++
++ writel(reg, ata_base + S3C_ATA_CFG);
++}
++
++
++static inline void set_trans_command (ATA_TRANSFER_CMD cmd)
++{
++ wait_for_host_ready();
++ writel(cmd, ata_base + S3C_ATA_CMD);
++}
++
++/*
++ * this filter only allows PIO and UDMA.
++ * swdma and mwdma is not supported now. by scsuh
++ */
++static u8 s3c_ide_ratefilter (ide_drive_t *drive, u8 speed)
++{
++ if (drive->media != ide_disk)
++ return min(speed, (u8)XFER_PIO_4);
++
++ switch(speed) {
++ case XFER_UDMA_6:
++ case XFER_UDMA_5:
++ speed = XFER_UDMA_4;// S3C6400 & S3C6410 can support upto UDMA4.
++ break;
++ case XFER_UDMA_4:
++ case XFER_UDMA_3:
++ case XFER_UDMA_2:
++ case XFER_UDMA_1:
++ case XFER_UDMA_0:
++ break;
++ default:
++ speed = min(speed, (u8)XFER_PIO_4);
++ break;
++ }
++ return speed;
++}
++
++static int s3c_ide_tune_chipset (ide_drive_t * drive, u8 xferspeed)
++{
++ ide_hwif_t *hwif = drive->hwif;
++ s3c_ide_hwif_t *s3c_hwif = (s3c_ide_hwif_t *) hwif->hwif_data;
++
++ u8 speed = s3c_ide_ratefilter(drive, xferspeed);
++
++ if (XFER_PIO_0 <= speed && speed <= XFER_PIO_4) {
++ ulong ata_cfg = readl(ata_base + S3C_ATA_CFG);
++
++ switch (speed) {
++ case XFER_PIO_0:
++ case XFER_PIO_1:
++ case XFER_PIO_2:
++ ata_cfg &= (~0x2); //IORDY disable
++ break;
++ case XFER_PIO_3:
++ case XFER_PIO_4:
++ ata_cfg |= 0x2; //IORDY enable
++ break;
++ }
++
++ writel(ata_cfg, ata_base + S3C_ATA_CFG);
++ writel(s3c_hwif->piotime[speed-XFER_PIO_0], ata_base + S3C_ATA_PIO_TIME);
++ } else {
++ writel(s3c_hwif->piotime[0], ata_base + S3C_ATA_PIO_TIME);
++ writel(s3c_hwif->udmatime[speed-XFER_UDMA_0], ata_base + S3C_ATA_UDMA_TIME);
++ }
++ return ide_config_drive_speed(drive, speed);
++}
++
++void read_status (uint index)
++{
++ u32 reg;
++ reg = readl(ata_base + S3C_ATA_IRQ);
++// printk("%d: S3C_ATA_IRQ: %08x\n", index, reg);
++ writel(reg, ata_base + S3C_ATA_IRQ);
++}
++
++int s3c_ide_ack_intr (ide_hwif_t *hwif)
++{
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ s3c_ide_hwif_t *s3c_hwif = (s3c_ide_hwif_t *) hwif->hwif_data;
++#endif
++ u32 reg;
++
++ reg = readl(ata_base + S3C_ATA_IRQ);
++ DbgAta("S3C_ATA_IRQ: %08x\n", reg);
++
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ s3c_hwif->irq_sta = reg;
++#endif
++
++ return 1;
++}
++
++static void s3c_ide_tune_drive (ide_drive_t * drive, u8 pio)
++{
++ pio = ide_get_best_pio_mode(drive, 255, pio);
++ (void) s3c_ide_tune_chipset(drive, (XFER_PIO_0 + pio));
++}
++
++/*
++ * XXX: It is board-specific to support UDMA in smdk24xx.
++ * not supported: SMDK241X, SMDK2443
++ * by scsuh
++ */
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++
++static void s3c_ide_dma_host_on (ide_drive_t * drive)
++{
++ DbgAta("##### %s\n", __FUNCTION__);
++}
++
++static int s3c_ide_dma_on (ide_drive_t * drive)
++{
++ DbgAta("##### %s\n", __FUNCTION__);
++ drive->using_dma = 1;
++ s3c_ide_dma_host_on(drive);
++ return 0;
++}
++
++#if 0
++static int s3c_ide_dma_check (ide_drive_t * drive)
++{
++ u8 speed;
++ DbgAta("##### %s\n", __FUNCTION__);
++ /* Is the drive in our DMA black list? */
++ if (s3c_ide_hwif.black_list) {
++ drive->using_dma = 0;
++
++ /* Borrowed the warning message from ide-dma.c */
++ printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
++ drive->name, drive->id->model);
++ } else
++ drive->using_dma = 1;
++
++ speed = ide_find_best_mode(drive, 0x47);
++ DbgAta("speed: %08x\n", speed);
++
++ if (drive->autodma && (speed & XFER_MODE) == XFER_UDMA) {
++ s3c_ide_tune_chipset(drive, speed);
++ return HWIF(drive)->ide_dma_on(drive);
++ }
++
++ HWIF(drive)->dma_off_quietly(drive);
++
++ return 0;
++}
++
++static ide_startstop_t s3c_ide_dma_intr (ide_drive_t *drive)
++{
++ ide_hwif_t *hwif = HWIF(drive);
++ s3c_ide_hwif_t *s3c_hwif = (s3c_ide_hwif_t *) hwif->hwif_data;
++ ulong reg = s3c_hwif->irq_sta;
++ ide_hwgroup_t *hwgroup = hwif->hwgroup;
++
++ DbgAta("reg = %08lx\n", reg);
++ DbgAta("S3C_ATA_XFR_CNT: %08x\n", readl(S3C_ATA_XFR_CNT));
++ DbgAta("index:%d\n", s3c_hwif->index);
++
++ if (reg & 0x10) {
++ DbgAta("write: %08lx %08lx\n",
++ s3c_hwif->table[s3c_hwif->index].addr,
++ s3c_hwif->table[s3c_hwif->index].len);
++ writel(s3c_hwif->table[s3c_hwif->index].len-0x20, S3C_ATA_SBUF_SIZE);
++ writel(s3c_hwif->table[s3c_hwif->index].addr, S3C_ATA_SBUF_START);
++ } else if (reg & 0x08) {
++ DbgAta("read: %08lx %08lx\n",
++ s3c_hwif->table[s3c_hwif->index].addr,
++ s3c_hwif->table[s3c_hwif->index].len);
++ writel(s3c_hwif->table[s3c_hwif->index].len-0x20, S3C_ATA_TBUF_SIZE);
++ writel(s3c_hwif->table[s3c_hwif->index].addr, S3C_ATA_TBUF_START);
++ }
++ s3c_hwif->index++;
++ set_trans_command(ATA_CMD_CONTINUE);
++ hwgroup->handler = s3c_ide_dma_intr;
++
++ return 1;
++}
++#endif
++
++static int s3c_ide_build_sglist (ide_drive_t * drive, struct request *rq)
++{
++ ide_hwif_t *hwif = drive->hwif;
++ s3c_ide_hwif_t *s3c_hwif = (s3c_ide_hwif_t *) hwif->hwif_data;
++ struct scatterlist *sg = hwif->sg_table;
++
++ DbgAta("##### %s\n", __FUNCTION__);
++ ide_map_sg(drive, rq);
++
++ if (rq_data_dir(rq) == READ)
++ hwif->sg_dma_direction = DMA_FROM_DEVICE;
++ else
++ hwif->sg_dma_direction = DMA_TO_DEVICE;
++
++ return dma_map_sg(&s3c_hwif->dev->dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
++}
++
++static int s3c_ide_build_dmatable (ide_drive_t * drive)
++{
++ int i, size, count = 0;
++ ide_hwif_t *hwif = HWIF(drive);
++ struct request *rq = HWGROUP(drive)->rq;
++
++ s3c_ide_hwif_t *s3c_hwif = (s3c_ide_hwif_t *) hwif->hwif_data;
++ struct scatterlist *sg;
++
++ u32 addr_reg, size_reg;
++
++ DbgAta("##### %s\n", __FUNCTION__);
++
++ if (rq_data_dir(rq) == WRITE) {
++ addr_reg = S3C_ATA_SBUF_START;
++ size_reg = S3C_ATA_SBUF_SIZE;
++ } else {
++ addr_reg = S3C_ATA_TBUF_START;
++ size_reg = S3C_ATA_TBUF_SIZE;
++ }
++
++ /* Save for interrupt context */
++ s3c_hwif->drive = drive;
++
++ /* Build sglist */
++ hwif->sg_nents = size = s3c_ide_build_sglist(drive, rq);
++ DbgAta("##### hwif->sg_nents %d\n", hwif->sg_nents);
++
++ if (size > 1) {
++ s3c_hwif->pseudo_dma = 1;
++ DbgAta("sg_nents is more than 1: %d\n", hwif->sg_nents);
++ }
++ if (!size)
++ return 0;
++
++ /* fill the descriptors */
++ sg = hwif->sg_table;
++ for (i=0, sg = hwif->sg_table; i<size && sg_dma_len(sg); i++, sg++) {
++ s3c_hwif->table[i].addr = sg_dma_address(sg);
++ s3c_hwif->table[i].len = sg_dma_len(sg);
++ count += s3c_hwif->table[i].len;
++ DbgAta("data: %08lx %08lx\n",
++ s3c_hwif->table[i].addr,
++ s3c_hwif->table[i].len);
++ }
++ s3c_hwif->table[i].addr = 0;
++ s3c_hwif->table[i].len = 0;
++ s3c_hwif->queue_size = i;
++ DbgAta("total size: %08x, %d\n", count, s3c_hwif->queue_size);
++
++ DbgAta("rw: %08lx %08lx\n",
++ s3c_hwif->table[0].addr,
++ s3c_hwif->table[0].len);
++ writel(s3c_hwif->table[0].len-0x1, ata_base + size_reg);
++ writel(s3c_hwif->table[0].addr, ata_base + addr_reg);
++
++ s3c_hwif->index = 1;
++
++ writel(count, ata_base + S3C_ATA_XFR_NUM);
++
++ return 1;
++}
++
++static int s3c_ide_dma_setup (ide_drive_t * drive)
++{
++ struct request *rq = HWGROUP(drive)->rq;
++
++ if (!s3c_ide_build_dmatable(drive)) {
++ ide_map_sg(drive, rq);
++ DbgAta("return 1\n");
++ return 1;
++ }
++
++ drive->waiting_for_dma = 1;
++ return 0;
++}
++
++static void s3c_ide_dma_exec_cmd (ide_drive_t * drive, u8 command)
++{
++ wait_for_host_ready();
++
++ /* issue cmd to drive */
++ ide_execute_command(drive, command, &ide_dma_intr, (WAIT_CMD), NULL);
++}
++
++static void s3c_ide_dma_start (ide_drive_t * drive)
++{
++ struct request *rq = HWGROUP(drive)->rq;
++ uint rw = (rq_data_dir(rq) == WRITE);
++
++#if defined CONFIG_ARCH_S3C2443 || defined (CONFIG_CPU_S3C2450)
++ /* apply at specific set using buffer control */
++ change_board_buf_mode(UDMA, rw);
++#endif
++ ata_status_check(drive, 0);
++ writel(0x00000003, ata_base + S3C_ATA_IRQ_MSK);
++
++ wait_for_host_ready();
++ /* must be added to wait for Device ready. by scsuh */
++ wait_for_dev_ready();
++ bus_fifo_status_check(IDLE);
++
++ set_config_mode(UDMA, rw);
++ set_trans_command(ATA_CMD_START);
++ return;
++}
++
++static int s3c_ide_dma_end (ide_drive_t * drive)
++{
++ u32 stat = 0;
++ ide_hwif_t *hwif = HWIF(drive);
++ s3c_ide_hwif_t *s3c_hwif = (s3c_ide_hwif_t *) hwif->hwif_data;
++
++ DbgAta("##### %s\n", __FUNCTION__);
++ DbgAta("left: %08x, %08x\n", readl(ata_base + S3C_ATA_XFR_CNT),
++ readl(ata_base + S3C_ATA_XFR_NUM));
++
++#if defined CONFIG_ARCH_S3C2443 || defined (CONFIG_CPU_S3C2450)
++ /* apply at specific set using buffer control */
++ change_board_buf_mode(PIO_CPU, 0);
++#endif
++ wait_for_host_ready();
++
++ stat = readl(ata_base + S3C_BUS_FIFO_STATUS);
++ if ( (stat >> 16) == 0x5 ) { /* in case of PAUSEW. */
++ writel(ATA_CMD_CONTINUE, ata_base + S3C_ATA_CMD);
++ }
++
++ bus_fifo_status_check(IDLE);
++ writel(0x00000003, ata_base + S3C_ATA_IRQ_MSK);
++ set_config_mode(PIO_CPU, 0);
++ ata_status_check(drive, 1);
++
++ drive->waiting_for_dma = 0;
++
++ if (hwif->sg_nents) {
++ dma_unmap_sg(&s3c_hwif->dev->dev, hwif->sg_table, hwif->sg_nents,
++ hwif->sg_dma_direction);
++ hwif->sg_nents = 0;
++ }
++ return 0;
++}
++
++static int s3c_ide_dma_timeout (ide_drive_t * drive)
++{
++ printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
++
++ if (HWIF(drive)->ide_dma_test_irq(drive))
++ return 0;
++
++ return HWIF(drive)->ide_dma_end(drive);
++}
++
++/* XXX: we must implement correct function. by scsuh. */
++static int s3c_ide_dma_test_irq (ide_drive_t * drive)
++{
++ return 1;
++}
++
++static void s3c_ide_dma_host_off (ide_drive_t * drive)
++{
++ u32 reg;
++
++ DbgAta("##### %s\n", __FUNCTION__);
++
++#if defined CONFIG_ARCH_S3C2443 || defined (CONFIG_CPU_S3C2450)
++ /* apply at specific set using buffer control */
++ change_board_buf_mode(PIO_CPU, 0);
++#endif
++ set_config_mode(PIO_CPU, 0);
++ mdelay(10);
++
++ /* disable ATA DMA auto mode */
++ reg = readl(ata_base + S3C_ATA_CFG);
++ reg &= (~0x200);
++ writel(reg, ata_base + S3C_ATA_CFG);
++}
++
++static void s3c_ide_dma_off_quietly (ide_drive_t * drive)
++{
++ drive->using_dma = 0;
++ s3c_ide_dma_host_off(drive);
++}
++
++static int s3c_ide_dma_lostirq (ide_drive_t * drive)
++{
++ printk("%08x, %08x\n", readl(ata_base + S3C_ATA_IRQ),
++ readl(ata_base + S3C_ATA_IRQ_MSK));
++ printk("left: %08x, %08x\n", readl(ata_base + S3C_ATA_XFR_CNT),
++ readl(ata_base + S3C_ATA_XFR_NUM));
++
++ printk(KERN_ERR "%s: IRQ lost\n", drive->name);
++ return 0;
++}
++
++#endif
++
++static int s3c_ide_irq_hook (void * data)
++{
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ u32 stat = 0;
++ ide_hwif_t *hwif = (ide_hwif_t *)data;
++ s3c_ide_hwif_t *s3c_hwif = (s3c_ide_hwif_t *) hwif->hwif_data;
++#endif
++
++ u32 reg = readl(ata_base + S3C_ATA_IRQ);
++ writel(reg, ata_base + S3C_ATA_IRQ);
++ DbgAta("##### %s, %08x\n", __FUNCTION__, reg);
++
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ if (s3c_hwif->pseudo_dma) {
++ uint i;
++ i = s3c_hwif->index;
++
++ if (reg & 0x10) {
++ DbgAta("write: %08lx %08lx\n",
++ s3c_hwif->table[i].addr,
++ s3c_hwif->table[i].len);
++ bus_fifo_status_check(PAUSER2);
++ writel(s3c_hwif->table[i].len-0x1, ata_base + S3C_ATA_SBUF_SIZE);
++ writel(s3c_hwif->table[i].addr, ata_base + S3C_ATA_SBUF_START);
++ } else if (reg & 0x08) {
++ DbgAta("read: %08lx %08lx\n",
++ s3c_hwif->table[i].addr,
++ s3c_hwif->table[i].len);
++
++ stat = bus_fifo_status_check(PAUSEW);
++ if (stat == 0x60000) {
++ writel(s3c_hwif->table[i].len-0x1, ata_base + S3C_ATA_SBUF_SIZE);
++ writel(s3c_hwif->table[i].addr, ata_base + S3C_ATA_SBUF_START);
++ }
++
++ writel(s3c_hwif->table[i].len-0x1, ata_base + S3C_ATA_TBUF_SIZE);
++ writel(s3c_hwif->table[i].addr, ata_base + S3C_ATA_TBUF_START);
++ } else {
++ DbgAta("unexpected interrupt : 0x%x\n", reg);
++ return 1;
++ }
++
++ s3c_hwif->index++;
++ if (s3c_hwif->queue_size == s3c_hwif->index) {
++ s3c_hwif->pseudo_dma = 0;
++ DbgAta("UDMA close : s3c_hwif->queue_size == s3c_hwif->index\n");
++ }
++
++ writel(ATA_CMD_CONTINUE, ata_base + S3C_ATA_CMD);
++ return 1;
++ }
++
++ stat = readl(ata_base + S3C_BUS_FIFO_STATUS);
++
++ if ( (stat >> 16) == 0x6 ) { /* in case of PAUSER2. */
++ writel(ATA_CMD_CONTINUE, ata_base + S3C_ATA_CMD);
++ return 1;
++ } else if ( (stat >> 16) == 0x5 ) { /* in case of PAUSEW. */
++ writel(ATA_CMD_CONTINUE, ata_base + S3C_ATA_CMD);
++ }
++#endif
++ return 0;
++}
++
++static void s3c_ide_setup_init_value (s3c_ide_hwif_t * s3c_hwif)
++{
++ ulong t1, t2, teoc;
++ ulong uTdvh1, uTdvs, uTrp, uTss, uTackenv;
++ uint pio_t1[5] = {70, 50, 30, 30, 30};
++ uint pio_t2[5] = {290, 290, 290, 80, 70};
++ uint pio_teoc[5] = {20, 20, 10, 10, 10};
++
++#if 0
++ uint uUdmaTdvh[5] = {10, 10, 10, 10, 10};
++ uint uUdmaTdvs[5] = {100, 60, 50, 35, 20};
++ uint uUdmaTrp[5] = {160, 125, 100, 100, 100};
++ uint uUdmaTss[5] = {50, 50, 50, 50, 50};
++ uint uUdmaTackenvMin[5] = {20, 20, 20, 20, 20};
++#else
++ u32 uUdmaTdvh[5] = { 7, 7, 7, 7, 7 };
++ u32 uUdmaTdvs[5] = { 70, 48, 31, 20, 7 };
++ u32 uUdmaTrp[5] = { 160, 125, 100, 100, 100 };
++ u32 uUdmaTss[5] = { 50, 50, 50, 50, 50 };
++ u32 uUdmaTackenvMin[5] = { 20, 20, 20, 20, 20 };
++#endif
++ ulong cycle_time = (uint) (1000000000 / clk_get_rate(s3c_hwif->clk));
++
++ uint i;
++
++ for (i = 0; i < 5; i++) {
++ t1 = (pio_t1[i] / cycle_time) & 0xff;
++ t2 = (pio_t2[i] / cycle_time) & 0xff;
++ teoc = (pio_teoc[i] / cycle_time) & 0x0f;
++ s3c_hwif->piotime[i] = (teoc << 12) | (t2 << 4) | t1;
++ DbgAta("PIO%dTIME = %08lx\n", i, s3c_hwif->piotime[i]);
++ }
++
++ for (i = 0; i < 5; i++) {
++ uTdvh1 = (uUdmaTdvh[i] / cycle_time) & 0x0f;
++ uTdvs = (uUdmaTdvs[i] / cycle_time) & 0xff;
++ uTrp = (uUdmaTrp[i] / cycle_time) & 0xff;
++ uTss = (uUdmaTss[i] / cycle_time) & 0x0f;
++ uTackenv = (uUdmaTackenvMin[i] / cycle_time) & 0x0f;
++ s3c_hwif->udmatime[i] = (uTdvh1 << 24) | (uTdvs << 16) | (uTrp << 8) | (uTss << 4) | uTackenv;
++ DbgAta("UDMA%dTIME = %08lx\n", i, s3c_hwif->udmatime[i]);
++ }
++}
++
++static void s3c_ide_setup_ports (hw_regs_t * hw, s3c_ide_hwif_t * s3c_hwif)
++{
++ int i;
++ unsigned long *ata_regs = hw->io_ports;
++
++ for (i = 0; i < IDE_IRQ_OFFSET; i++) {
++ *ata_regs++ = (u32)ata_base + 0x1954 + (i << 2);
++ }
++}
++
++/*=========================================================================
++ * ata controller register I/O fuctions
++ *=========================================================================
++ */
++
++static void s3c_ide_OUTB (u8 addr, ulong reg)
++{
++ wait_for_host_ready();
++ writeb(addr, reg);
++}
++
++static void s3c_ide_OUTBSYNC (ide_drive_t *drive, u8 addr, ulong port)
++{
++ wait_for_host_ready();
++ writeb(addr, port);
++}
++
++static void s3c_ide_OUTW (u16 addr, ulong reg)
++{
++ wait_for_host_ready();
++ writew(addr, reg);
++}
++
++static u8 s3c_ide_INB (ulong reg)
++{
++ u8 temp;
++
++ wait_for_host_ready();
++ temp = readb(reg);
++ wait_for_host_ready();
++ temp = readb(ata_base + S3C_ATA_PIO_RDATA);
++ return temp;
++}
++
++static u16 s3c_ide_INW (ulong reg)
++{
++ u16 temp;
++
++ wait_for_host_ready();
++ temp = readw(reg);
++ wait_for_host_ready();
++ temp = readw(ata_base + S3C_ATA_PIO_RDATA);
++ return temp;
++}
++
++#ifdef CONFIG_BLK_DEV_IDE_S3C_PDMA
++/*
++ * check transfer status and return result
++ */
++static int check_dma_done (void)
++{
++ u32 reg;
++ uint i;
++
++ for (i=0; i<0x10000000; i++) {
++ reg = readl(ata_base + S3C_ATA_IRQ);
++ if (reg & 0x01)
++ break;
++ }
++ if (i > (0x10000000-5)) {
++ printk("transmission timeout: %08x\n", reg);
++ return -1;
++ }
++
++ reg = readl(ata_base + S3C_ATA_STATUS);
++ if (reg & 3) {
++ printk("\n\ntransmission failed: %08x\n", reg);
++ printk("ata_irq: %08x\n", readl(ata_base + S3C_ATA_IRQ));
++ printk("ata_cfg: %08x\n", readl(ata_base + S3C_ATA_CFG));
++ return -1;
++ }
++
++ return 0;
++}
++
++static void s3c_ide_OUTSW (ulong port, void *addr, u32 count)
++{
++ dma_addr_t dma_addr;
++
++ /* half-word count. we must double it. by scsuh */
++ count = count << 1;
++
++ DbgAta("@@@@@write: %p, %08x\n", addr, count);
++
++ writel(0x000000ff, ata_base + S3C_ATA_IRQ_MSK);
++
++ dma_addr = dma_map_single(NULL, addr, count, DMA_TO_DEVICE);
++ writel(dma_addr, ata_base + S3C_ATA_SBUF_START);
++ writel(count-1, ata_base + S3C_ATA_SBUF_SIZE);
++ writel(count, ata_base + S3C_ATA_XFR_NUM);
++ set_config_mode(PIO_DMA, 1);
++ set_trans_command(ATA_CMD_START);
++ check_dma_done();
++ set_config_mode(PIO_CPU, 0);
++ dma_unmap_single(NULL, dma_addr, count, DMA_TO_DEVICE);
++
++ writel(0x0000001b, ata_base + S3C_ATA_IRQ);
++ writel(0x0000001b, ata_base + S3C_ATA_IRQ_MSK);
++}
++
++static void s3c_ide_INSW (ulong port, void *addr, u32 count)
++{
++ dma_addr_t dma_addr;
++
++ /* half-word count. we must double it. by scsuh */
++ count = count << 1;
++
++ DbgAta("@@@@@read: %p, %08x\n", addr, count);
++
++ writel(0x000000ff, ata_base + S3C_ATA_IRQ_MSK);
++
++ dma_addr = dma_map_single(NULL, addr, count, DMA_FROM_DEVICE);
++ writel(dma_addr, ata_base + S3C_ATA_TBUF_START);
++ writel(count-1, ata_base + S3C_ATA_TBUF_SIZE);
++ writel(count, ata_base + S3C_ATA_XFR_NUM);
++ set_config_mode(PIO_DMA, 0);
++ set_trans_command(ATA_CMD_START);
++ check_dma_done();
++ set_config_mode(PIO_CPU, 0);
++ dma_unmap_single(NULL, dma_addr, count, DMA_FROM_DEVICE);
++
++ writel(0x0000001b, ata_base + S3C_ATA_IRQ);
++ writel(0x0000001b, ata_base + S3C_ATA_IRQ_MSK);
++}
++#else
++static void s3c_ide_OUTSW(ulong port, void *addr, u32 count)
++{
++ uint i;
++ volatile u16 *temp_addr = (u16*)addr;
++
++ for (i=0; i<count; i++, temp_addr++) {
++ wait_for_host_ready();
++ writel(*temp_addr, port);
++ }
++}
++
++static void s3c_ide_INSW (ulong port, void *addr, u32 count)
++{
++ uint i;
++ volatile u16 *temp_addr = (u16*)addr;
++
++ for (i=0; i<count; i++, temp_addr++) {
++ wait_for_host_ready();
++ *temp_addr = readw(port);
++ wait_for_host_ready();
++ *temp_addr = readw(S3C_ATA_PIO_RDATA);
++ }
++}
++#endif
++
++static void change_mode_to_ata (void)
++{
++ /* TDelay 1 unit = 10us */
++ mdelay(1);
++
++ /* CF controller - True IDE mode setting */
++
++ /* Output pad disable, Card power off, ATA mode */
++ writel(0x07, ata_base + S3C_CFATA_MUX);
++ mdelay(10);
++ /* Output pad enable, Card power off, ATA mode */
++ writel(0x03, ata_base + S3C_CFATA_MUX);
++ mdelay(10);
++ /* Output pad enable, Card power on, ATA mode */
++ writel(0x01, ata_base + S3C_CFATA_MUX);
++ mdelay(500); /* wait for 500ms */
++}
++
++static int s3c_ide_probe (struct platform_device *pdev)
++{
++ s3c_ide_hwif_t *s3c_hwif = &s3c_ide_hwif;
++ ide_hwif_t *hwif;
++ hw_regs_t *hw;
++ int ret = 0;
++ ulong reg;
++ u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
++
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ char *mode = "PIO/UDMA";
++#elif defined (CONFIG_BLK_DEV_IDE_S3C_PDMA)
++ char *mode = "PIO_ONLY(DMA)";
++#else
++ char *mode = "PIO_ONLY";
++#endif
++
++ memset(&s3c_ide_hwif, 0, sizeof(s3c_ide_hwif));
++
++ s3c_hwif->dev = pdev;
++ s3c_hwif->irq = platform_get_irq(pdev, 0);
++
++// s3c_hwif->regbase = (u32)S3C24XX_VA_CFATA;
++ ata_base = ioremap(S3C_PA_CFATA, S3C_SZ_CFATA);
++
++ s3c_hwif->clk = clk_get(&pdev->dev, "cfata");
++ if (IS_ERR(s3c_hwif->clk)) {
++ printk("failed to find clock source.\n");
++ ret = PTR_ERR(s3c_hwif->clk);
++ s3c_hwif->clk = NULL;
++ goto out;
++ }
++
++ if ((ret = clk_enable(s3c_hwif->clk))) {
++ printk("failed to enable clock source.\n");
++ goto out;
++ }
++
++ s3c_ide_setup_init_value(s3c_hwif);
++
++ /* XXX: Because this code is 2443 specific
++ * it will be moved to new functions
++ * by scsuh.
++ */
++#if defined CONFIG_ARCH_S3C2443 || defined (CONFIG_CPU_S3C2450)
++ {
++ ulong *temp_adr;
++ mdelay(1); // TDelay 1 unit = 10us
++
++ // GPIO, EBI setting
++ temp_adr = S3C24XX_VA_EBI+8;
++ reg = readl(temp_adr);
++ writel(reg | (1 << 10) | (1 << 9), temp_adr);
++ reg = readl(S3C2410_GPGCON);
++ writel(reg | (3 << 30) | (3 << 28) | (3 << 26) | (3 << 24) | (3 << 22), S3C2410_GPGCON);
++ reg = readl(S3C2410_GPACON);
++ writel(reg | (1 << 27) | (1 << 11) | (1 << 14) | (1 << 13), S3C2410_GPACON);
++ reg = readl(S3C2410_MISCCR);
++ writel(reg & (~(1 << 30)), S3C2410_MISCCR);
++
++ init_buf_ctrl();
++ change_board_buf_mode(PIO_CPU, 0);
++
++ /* CF controller - True IDE mode setting */
++ change_mode_to_ata();
++
++ /* Card configuration */
++ writel(0x1C238, ata_base + S3C_ATA_PIO_TIME);
++ writel(0x20B1362, ata_base + S3C_ATA_UDMA_TIME);
++ set_endian_mode(1);
++ set_ata_enable(1);
++ mdelay(400); // wait for 200ms, be positively necessary
++ }
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ {
++ mdelay(1); // TDelay 1 unit = 10us
++
++ reg = readl(S3C_MEM_SYS_CFG) & (~0x0000003f);
++ writel(reg | 0x00000030, S3C_MEM_SYS_CFG);
++
++#ifdef CONFIG_BLK_DEV_IDE_S3C_DIRECT
++ { /* direct mode */
++ u32 temp;
++
++ printk(" * CF EBI MODE : Direct Mode\n\n");
++ reg = readl(S3C_MEM_SYS_CFG);
++ writel(reg | 0x00004000, S3C_MEM_SYS_CFG);
++
++ temp = readl(S3C_GPACON);
++
++ // D: Set XhiDATA[15:0] pins as CF Data[15:0]
++ writel(0x55555555, S3C_GPK0CON);
++ writel(0x55555555, S3C_GPK1CON);
++ // A: Set XhiADDR[2:0] pins as CF ADDR[2:0]
++ reg = readl(S3C_GPL0CON) & (~0x00000fff);
++ writel(reg | 0x00000666, S3C_GPL0CON);
++ // C: Set Xhi control pins as CF control pins(IORDY, IOWR, IORD, CE[1], CE[0])
++ writel(0x00066666, S3C_GPMCON);
++
++ /* This line must be here because Uart ports(GPIO_A)
++ * are changed after setting GPIO_K.
++ */
++ writel(temp, S3C_GPACON);
++ }
++#else
++ { /* indirect mode */
++ printk(" * CF EBI MODE : InDirect Mode\n\n");
++ reg = readl(S3C_MEM_SYS_CFG) & (~0x00004000);
++ writel(reg, S3C_MEM_SYS_CFG);
++
++ // C: Set Xhi control pins as CF control pins(IORDY, IOWR, IORD, CE[1], CE[0])
++ writel(0x00066666, S3C_GPMCON);
++ }
++#endif
++
++ change_mode_to_ata();
++
++ writel(0x1C238, ata_base + S3C_ATA_PIO_TIME); /* 0x1C238 */
++ writel(0x20B1362, ata_base + S3C_ATA_UDMA_TIME); /* 0x20B1362 */
++ set_endian_mode(1);
++ set_ata_enable(1);
++ mdelay(400); // wait for 200ms, be positively necessary
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ reg = readl(S3C_GPNCON) & ~(0x3<<(2*8));
++ writel(reg | (1<<(2*8)), S3C_GPNCON);
++
++ reg = readl(S3C_GPNDAT);
++ writel(reg | (1<<8), S3C_GPNDAT);
++
++ mdelay(500);
++
++ writel(reg & ~(1<<8), S3C_GPNDAT);
++#endif
++ }
++#endif
++ /* remove IRQ Status */
++ writel(0x1f, ata_base + S3C_ATA_IRQ);
++ writel(0x1f, ata_base + S3C_ATA_IRQ);
++ writel(0x1b, ata_base + S3C_ATA_IRQ_MSK);
++
++ hwif = &ide_hwifs[pdev->id];
++ hw = &hwif->hw;
++ hwif->irq = hw->irq = s3c_hwif->irq;
++ hwif->chipset = ide_s3c;
++ s3c_ide_setup_ports(hw, s3c_hwif);
++ memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
++
++ hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
++ hwif->mwdma_mask = 0x0;
++ hwif->swdma_mask = 0x0;
++
++ hwif->noprobe = 0;
++ hwif->drives[0].unmask = 1;
++ hwif->drives[1].unmask = 1;
++
++ /* hold should be on in all cases */
++ hwif->hold = 1;
++ hwif->mmio = 1;
++
++ hwif->OUTB = &s3c_ide_OUTB;
++ hwif->OUTBSYNC = &s3c_ide_OUTBSYNC;
++ hwif->OUTW = &s3c_ide_OUTW;
++ hwif->OUTSW = &s3c_ide_OUTSW;
++
++ hwif->INB = &s3c_ide_INB;
++ hwif->INW = &s3c_ide_INW;
++ hwif->INSW = &s3c_ide_INSW;
++
++ hwif->pio_mask = XFER_PIO_4;
++ hwif->set_pio_mode = &s3c_ide_tune_drive;
++ hwif->set_dma_mode = &s3c_ide_tune_chipset;
++
++#ifdef CONFIG_IDE_HOOK_IRQ
++ hwif->ide_irq_hook = &s3c_ide_irq_hook;
++#endif
++
++#if defined (CONFIG_BLK_DEV_IDE_S3C_UDMA)
++ hwif->ultra_mask = 0x1f; /* enable Ultra DMA 0 ~ 4 */
++ hwif->dma_off_quietly = &s3c_ide_dma_off_quietly;
++ hwif->dma_timeout = &s3c_ide_dma_timeout;
++
++ hwif->dma_exec_cmd = &s3c_ide_dma_exec_cmd;
++ hwif->dma_start = &s3c_ide_dma_start;
++ hwif->ide_dma_end = &s3c_ide_dma_end;
++ hwif->dma_setup = &s3c_ide_dma_setup;
++ hwif->ide_dma_test_irq = &s3c_ide_dma_test_irq;
++ hwif->dma_host_off = &s3c_ide_dma_host_off;
++ hwif->dma_host_on = &s3c_ide_dma_host_on;
++ hwif->dma_lost_irq = &s3c_ide_dma_lostirq;
++ hwif->ide_dma_on = &s3c_ide_dma_on;
++
++#else
++ hwif->channel = 0;
++ hwif->hold = 1;
++ hwif->select_data = 0; /* no chipset-specific code */
++ hwif->config_data = 0; /* no chipset-specific code */
++#endif
++
++ hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
++ hwif->drives[0].no_io_32bit = 1;
++
++ s3c_ide_hwif.hwif = hwif;
++ hwif->hwif_data = &s3c_ide_hwif;
++
++ idx[0] = hwif->index;
++ ide_device_add(idx);
++
++ dev_set_drvdata(pdev, hwif);
++
++ printk(KERN_INFO "S3C24XX IDE(builtin) configured for %s\n", mode);
++
++out:
++ return ret;
++}
++
++static int s3c_ide_remove(struct platform_device *dev)
++{
++ struct resource *res;
++ ide_hwif_t *hwif = platform_get_drvdata(dev);
++
++ ide_unregister(hwif - ide_hwifs);
++
++ iounmap(ata_base);
++
++ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
++ release_mem_region(res->start, res->end - res->start);
++
++ return 0;
++}
++
++static struct platform_driver s3c_ide_driver = {
++ .probe = s3c_ide_probe,
++ .remove = s3c_ide_remove,
++ .driver = {
++ .name = "s3c-ide",
++ },
++};
++
++
++static int __init s3c_ide_init(void)
++{
++ return platform_driver_register(&s3c_ide_driver);
++}
++
++static void __exit s3c_ide_exit(void)
++{
++ platform_driver_unregister(&s3c_ide_driver);
++}
++
++module_init(s3c_ide_init);
++module_exit(s3c_ide_exit);
++
++static int s3c_ata_proc_read (
++ char *buffer,
++ char **buffer_location,
++ off_t offset,
++ int buffer_length,
++ int *zero,
++ void *ptr
++)
++{
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ char *mode = "PIO/UDMA";
++#elif defined (CONFIG_BLK_DEV_IDE_S3C_PDMA)
++ char *mode = "PIO_ONLY(DMA)";
++#else
++ char *mode = "PIO_ONLY";
++#endif
++
++ printk("current mode is %s\n", mode);
++ return 0;
++}
++
++static int s3c_ata_proc_write (
++ struct file *file,
++ const char *buffer,
++ unsigned long count,
++ void *data
++)
++{
++ return 0;
++}
++
++static struct proc_dir_entry *evb_resource_dump;
++
++int __init s3c_ata_rw_proc (void)
++{
++ evb_resource_dump = create_proc_entry("s3c-ata", 0666, &proc_root);
++ evb_resource_dump->read_proc = s3c_ata_proc_read;
++ evb_resource_dump->write_proc = s3c_ata_proc_write;
++ evb_resource_dump->nlink = 1;
++ return 0;
++}
++module_init(s3c_ata_rw_proc);
++MODULE_DESCRIPTION("S3C ATA in CF/ATA Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/ide/arm/s3c-ide.h b/drivers/ide/arm/s3c-ide.h
+new file mode 100644
+index 0000000..95c45e8
+--- /dev/null
++++ b/drivers/ide/arm/s3c-ide.h
+@@ -0,0 +1,113 @@
++/*
++ * $Id: s3c-ide.h,v 1.2 2008/06/11 00:56:02 scsuh Exp $
++ *
++ * drivers/ide/arm/s3c-ide.h
++ *
++ * This program is free software; you can redistribute it and/or modify it under
++ * the terms of the GNU General Public License as published by the Free Software
++ * Foundation; either version 2 of the License, or (at your option) any later
++ * version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
++ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
++ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++typedef enum {
++ PIO0, PIO1, PIO2, PIO3, PIO4
++} PIOMODE;
++
++typedef enum {
++ UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
++} UDMAMODE;
++
++typedef enum {
++ ATA_CMD_STOP, ATA_CMD_START, ATA_CMD_ABORT, ATA_CMD_CONTINUE
++} ATA_TRANSFER_CMD;
++
++typedef enum {
++ ATA_INT_XFER_DONE, ATA_INT_UDMA_HOLD, ATA_INT_IRQ,
++ ATA_INT_TBUF_FULL, ATA_INT_SBUF_EMPTY
++} ATA_INT_SRC;
++
++typedef enum {
++ PIO_CPU, PIO_DMA, UDMA
++} ATA_MODE;
++
++typedef enum {
++ IDLE, BUSYW, PREP, BUSYR, PAUSER, PAUSEW, PAUSER2
++} BUS_STATE;
++
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ #define DMA_WAIT_TIMEOUT 100
++ #define NUM_DESCRIPTORS PRD_ENTRIES
++#else
++ #define NUM_DESCRIPTORS 2
++#endif
++
++#ifdef CONFIG_PM
++/*
++* This will enable the device to be powered up when write() or read()
++* is called. If this is not defined, the driver will return -EBUSY.
++*/
++#define WAKE_ON_ACCESS 1
++
++typedef struct
++{
++ spinlock_t lock; /* Used to block on state transitions */
++ unsigned stopped; /* USed to signaling device is stopped */
++} pm_state;
++#endif
++
++typedef struct
++{
++ ulong addr; /* Used to block on state transitions */
++ ulong len; /* Power Managers device structure */
++} dma_queue_t;
++
++typedef struct
++{
++ u32 tx_dev_id, rx_dev_id, target_dev_id;
++ ide_hwif_t *hwif;
++#ifdef CONFIG_BLK_DEV_IDE_S3C_UDMA
++ ide_drive_t *drive;
++ u8 white_list, black_list;
++
++ uint index; /* current queue index */
++ uint queue_size; /* total queue size requested */
++ dma_queue_t table[NUM_DESCRIPTORS];
++ uint irq_sta;
++ uint pseudo_dma; /* in DMA session */
++#endif
++ struct platform_device *dev;
++ int irq;
++ void __iomem *regbase;
++ ulong piotime[5];
++ ulong udmatime[5];
++ struct clk *clk;
++
++#ifdef CONFIG_PM
++ pm_state pm;
++#endif
++} s3c_ide_hwif_t;
++
++/* s3c2443 has some faults in bus sharing.
++ * so must use lock and unlock in UDMA. by scsuh.
++ */
++#ifdef CONFIG_ARCH_S3C2443
++void lock_rom_bus(void);
++void unlock_rom_bus(void);
++#endif
++
+diff --git a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
+index 4703837..5f9558d 100644
+--- a/drivers/ide/ide-dma.c
++++ b/drivers/ide/ide-dma.c
+@@ -664,10 +664,15 @@ static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode)
+ /*
+ * avoid false cable warning from eighty_ninty_three()
+ */
++
++// Though 80c ribbon Cable is used on SMDK board, kernel can not detect it.
++// Because CF/ATA Converter Socket is used for ATA interface on SMDK board.
++/*
+ if (req_mode > XFER_UDMA_2) {
+ if ((mask & 0x78) && (eighty_ninty_three(drive) == 0))
+ mask &= 0x07;
+ }
++*/
+ break;
+ case XFER_MW_DMA_0:
+ if ((id->field_valid & 2) == 0)
+diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c
+index bef781f..0693885 100644
+--- a/drivers/ide/ide-io.c
++++ b/drivers/ide/ide-io.c
+@@ -1591,6 +1591,13 @@ irqreturn_t ide_intr (int irq, void *dev_id)
+ return IRQ_NONE;
+ }
+
++#ifdef CONFIG_IDE_HOOK_IRQ
++ if (hwif->ide_irq_hook(hwif)) {
++ spin_unlock_irqrestore(&ide_lock, flags);
++ return IRQ_HANDLED;
++ }
++#endif
++
+ if ((handler = hwgroup->handler) == NULL || hwgroup->polling) {
+ /*
+ * Not expecting an interrupt from this drive.
+diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
+index 63512d9..ee55dcd 100644
+--- a/drivers/input/Kconfig
++++ b/drivers/input/Kconfig
+@@ -114,6 +114,28 @@ config INPUT_JOYDEV
+ To compile this driver as a module, choose M here: the
+ module will be called joydev.
+
++config INPUT_TSDEV
++ tristate "Touchscreen interface"
++ ---help---
++ Say Y here if you have an application that only can understand the
++ Compaq touchscreen protocol for absolute pointer data. This is
++ useful namely for embedded configurations.
++
++ If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ module will be called tsdev.
++
++config INPUT_TSDEV_SCREEN_X
++ int "Horizontal screen resolution"
++ depends on INPUT_TSDEV
++ default "480"
++
++config INPUT_TSDEV_SCREEN_Y
++ int "Vertical screen resolution"
++ depends on INPUT_TSDEV
++ default "640"
++
+ config INPUT_EVDEV
+ tristate "Event interface"
+ help
+diff --git a/drivers/input/Makefile b/drivers/input/Makefile
+index 99af903..8dda9c9 100644
+--- a/drivers/input/Makefile
++++ b/drivers/input/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_INPUT_MOUSEDEV) += mousedev.o
+ obj-$(CONFIG_INPUT_JOYDEV) += joydev.o
+ obj-$(CONFIG_INPUT_EVDEV) += evdev.o
+ obj-$(CONFIG_INPUT_EVBUG) += evbug.o
++obj-$(CONFIG_INPUT_TSDEV) += tsdev.o
+
+ obj-$(CONFIG_INPUT_KEYBOARD) += keyboard/
+ obj-$(CONFIG_INPUT_MOUSE) += mouse/
+diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
+index 086d58c..75331a7 100644
+--- a/drivers/input/keyboard/Kconfig
++++ b/drivers/input/keyboard/Kconfig
+@@ -274,6 +274,16 @@ config KEYBOARD_GPIO
+ To compile this driver as a module, choose M here: the
+ module will be called gpio-keys.
+
++config KEYPAD_S3C
++ tristate "S3C keypad support"
++ depends on (CPU_S3C6400 || CPU_S3C6410)
++ default n
++ help
++ Say Y here if you want to use the S3C SMDK keypad.
++
++ To compile this driver as a module, choose M here: the
++ module will be called s3c-keypad.
++
+ config KEYBOARD_MAPLE
+ tristate "Maple bus keyboard"
+ depends on SH_DREAMCAST && MAPLE
+diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
+index e97455f..212452c 100644
+--- a/drivers/input/keyboard/Makefile
++++ b/drivers/input/keyboard/Makefile
+@@ -25,3 +25,4 @@ obj-$(CONFIG_KEYBOARD_HP6XX) += jornada680_kbd.o
+ obj-$(CONFIG_KEYBOARD_HP7XX) += jornada720_kbd.o
+ obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o
+ obj-$(CONFIG_KEYBOARD_BFIN) += bf54x-keys.o
++obj-$(CONFIG_KEYPAD_S3C) += s3c-keypad.o
+diff --git a/drivers/input/keyboard/s3c-keypad.c b/drivers/input/keyboard/s3c-keypad.c
+new file mode 100644
+index 0000000..7bd73a2
+--- /dev/null
++++ b/drivers/input/keyboard/s3c-keypad.c
+@@ -0,0 +1,337 @@
++/*
++ * drivers/input/keyboard/s3c-keypad.c
++ * KeyPad Interface on S3C
++ *
++ * $Id: s3c-keypad.c,v 1.1 2008/06/09 07:43:16 dark0351 Exp $
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/input.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/delay.h>
++#include <asm/irq.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-keypad.h>
++#include "s3c-keypad.h"
++
++#undef S3C_KEYPAD_DEBUG
++//#define S3C_KEYPAD_DEBUG
++
++#ifdef S3C_KEYPAD_DEBUG
++#define DPRINTK(x...) printk("S3C-Keypad " x)
++#else
++#define DPRINTK(x...) /* !!!! */
++#endif
++
++#define DEVICE_NAME "s3c-keypad"
++
++#define TRUE 1
++#define FALSE 0
++
++static struct timer_list keypad_timer;
++static int is_timer_on = FALSE;
++
++
++static int keypad_scan(u32 *keymask_low, u32 *keymask_high)
++{
++ int i,j = 0;
++ u32 cval,rval;
++
++ for (i=0; i<KEYPAD_COLUMNS; i++) {
++ cval = readl(key_base+S3C_KEYIFCOL) | KEYCOL_DMASK;
++ cval &= ~(1 << i);
++ writel(cval, key_base+S3C_KEYIFCOL);
++
++ udelay(KEYPAD_DELAY);
++
++ rval = ~(readl(key_base+S3C_KEYIFROW)) & KEYROW_DMASK;
++
++ if ((i*KEYPAD_ROWS) < MAX_KEYMASK_NR)
++ *keymask_low |= (rval << (i * KEYPAD_ROWS));
++ else {
++ *keymask_high |= (rval << (j * KEYPAD_ROWS));
++ j = j +1;
++ }
++ }
++
++ writel(KEYIFCOL_CLEAR, key_base+S3C_KEYIFCOL);
++
++ return 0;
++}
++
++static unsigned prevmask_low = 0, prevmask_high = 0;
++
++static void keypad_timer_handler(unsigned long data)
++{
++ u32 keymask_low = 0, keymask_high = 0;
++ u32 press_mask_low, press_mask_high;
++ u32 release_mask_low, release_mask_high;
++ int i;
++ struct s3c_keypad *pdata = (struct s3c_keypad *)data;
++ struct input_dev *dev = pdata->dev;
++
++ keypad_scan(&keymask_low, &keymask_high);
++
++ if (keymask_low != prevmask_low) {
++ press_mask_low =
++ ((keymask_low ^ prevmask_low) & keymask_low);
++ release_mask_low =
++ ((keymask_low ^ prevmask_low) & prevmask_low);
++
++ i = 0;
++ while (press_mask_low) {
++ if (press_mask_low & 1) {
++ input_report_key(dev,pdata->keycodes[i],1);
++ DPRINTK("low Pressed : %d\n",i);
++ }
++ press_mask_low >>= 1;
++ i++;
++ }
++
++ i = 0;
++ while (release_mask_low) {
++ if (release_mask_low & 1) {
++ input_report_key(dev,pdata->keycodes[i],0);
++ DPRINTK("low Released : %d\n",i);
++ }
++ release_mask_low >>= 1;
++ i++;
++ }
++ prevmask_low = keymask_low;
++ }
++
++ if (keymask_high != prevmask_high) {
++ press_mask_high =
++ ((keymask_high ^ prevmask_high) & keymask_high);
++ release_mask_high =
++ ((keymask_high ^ prevmask_high) & prevmask_high);
++
++ i = 0;
++ while (press_mask_high) {
++ if (press_mask_high & 1) {
++ input_report_key(dev,pdata->keycodes[i+MAX_KEYMASK_NR],1);
++ DPRINTK("high Pressed : %d %d\n",pdata->keycodes[i+MAX_KEYMASK_NR],i);
++ }
++ press_mask_high >>= 1;
++ i++;
++ }
++
++ i = 0;
++ while (release_mask_high) {
++ if (release_mask_high & 1) {
++ input_report_key(dev,pdata->keycodes[i+MAX_KEYMASK_NR],0);
++ DPRINTK("high Released : %d\n",pdata->keycodes[i+MAX_KEYMASK_NR]);
++ }
++ release_mask_high >>= 1;
++ i++;
++ }
++ prevmask_high = keymask_high;
++ }
++
++ if (keymask_low | keymask_high) {
++ mod_timer(&keypad_timer,jiffies + HZ/10);
++ } else {
++ writel(KEYIFCON_INIT, key_base+S3C_KEYIFCON);
++ is_timer_on = FALSE;
++ }
++}
++
++static irqreturn_t s3c_keypad_isr(int irq, void *dev_id)
++{
++
++ /* disable keypad interrupt and schedule for keypad timer handler */
++ writel(readl(key_base+S3C_KEYIFCON) & ~(INT_F_EN|INT_R_EN), key_base+S3C_KEYIFCON);
++
++ keypad_timer.expires = jiffies + (HZ/100);
++ if ( is_timer_on == FALSE) {
++ add_timer(&keypad_timer);
++ is_timer_on = TRUE;
++ } else {
++ mod_timer(&keypad_timer,keypad_timer.expires);
++ }
++ /*Clear the keypad interrupt status*/
++ writel(KEYIFSTSCLR_CLEAR, key_base+S3C_KEYIFSTSCLR);
++
++ return IRQ_HANDLED;
++}
++
++
++
++static int __init s3c_keypad_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct input_dev *input_dev;
++ int key, code;
++ struct s3c_keypad *s3c_keypad;
++
++ key_base = ioremap(S3C24XX_PA_KEYPAD, S3C24XX_SZ_KEYPAD);
++
++ if (key_base == NULL) {
++ printk(KERN_ERR "Failed to remap register block\n");
++ return -ENOMEM;
++ }
++
++ s3c_keypad = kzalloc(sizeof(struct s3c_keypad), GFP_KERNEL);
++ input_dev = input_allocate_device();
++
++ if (!s3c_keypad || !input_dev) {
++ kfree(s3c_keypad);
++ input_free_device(input_dev);
++ return -ENOMEM;
++ }
++
++ platform_set_drvdata(pdev, s3c_keypad);
++ s3c_keypad->dev = input_dev;
++
++ writel(KEYIFCON_INIT, key_base+S3C_KEYIFCON);
++ writel(KEYIFFC_DIV, key_base+S3C_KEYIFFC);
++
++ /* Set GPIO Port for keypad mode and pull-up disable*/
++ writel(KEYPAD_ROW_GPIO_SET, KEYPAD_ROW_GPIOCON);
++ writel(KEYPAD_COL_GPIO_SET, KEYPAD_COL_GPIOCON);
++
++ writel(KEYPAD_ROW_GPIOPUD_DIS, KEYPAD_ROW_GPIOPUD);
++ writel(KEYPAD_COL_GPIOPUD_DIS, KEYPAD_COL_GPIOPUD);
++
++ writel(KEYIFCOL_CLEAR, key_base+S3C_KEYIFCOL);
++
++ /* create and register the input driver */
++ set_bit(EV_KEY, input_dev->evbit);
++ set_bit(EV_REP, input_dev->evbit);
++ s3c_keypad->nr_rows = KEYPAD_ROWS;
++ s3c_keypad->no_cols = KEYPAD_COLUMNS;
++ s3c_keypad->total_keys = MAX_KEYPAD_NR;
++
++ for(key = 0; key < s3c_keypad->total_keys; key++){
++ code = s3c_keypad->keycodes[key] = keypad_keycode[key];
++ if(code<=0)
++ continue;
++ set_bit(code & KEY_MAX, input_dev->keybit);
++ }
++
++ input_dev->name = DEVICE_NAME;
++ input_dev->phys = "s3c-keypad/input0";
++ input_dev->cdev.dev = &pdev->dev;
++ input_dev->private = s3c_keypad;
++
++ input_dev->id.bustype = BUS_HOST;
++ input_dev->id.vendor = 0x0001;
++ input_dev->id.product = 0x0001;
++ input_dev->id.version = 0x0001;
++
++ input_dev->keycode = keypad_keycode;
++
++ ret = input_register_device(input_dev);
++ if (ret) {
++ printk("Unable to register s3c-keypad input device!!!\n");
++ goto out;
++ }
++
++
++ /* Scan timer init */
++ init_timer(&keypad_timer);
++ keypad_timer.function = keypad_timer_handler;
++ keypad_timer.data = (unsigned long)s3c_keypad;
++
++ ret = request_irq(IRQ_KEYPAD, s3c_keypad_isr, IRQF_SAMPLE_RANDOM,
++ DEVICE_NAME, (void *) pdev);
++ if (ret) {
++ printk("request_irq failed (IRQ_KEYPAD) !!!\n");
++ goto out;
++ }
++
++ keypad_timer.expires = jiffies + (HZ/10);
++
++ if (is_timer_on == FALSE) {
++ add_timer(&keypad_timer);
++ is_timer_on = TRUE;
++ } else {
++ mod_timer(&keypad_timer,keypad_timer.expires);
++ }
++
++ printk( DEVICE_NAME " Initialized\n");
++ return 0;
++
++out:
++ input_unregister_device(input_dev);
++ kfree(s3c_keypad);
++ return ret;
++}
++
++static int s3c_keypad_remove(struct platform_device *pdev)
++{
++ struct input_dev *input_dev = platform_get_drvdata(pdev);
++ writel(KEYIFCON_CLEAR, key_base+S3C_KEYIFCON);
++
++ input_unregister_device(input_dev);
++ kfree(pdev->dev.platform_data);
++ free_irq(IRQ_KEYPAD, (void *) pdev);
++
++ del_timer(&keypad_timer);
++ printk(DEVICE_NAME " Removed.\n");
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_keypad_suspend(struct platform_device *dev, pm_message_t state)
++{
++ /* TODO */
++ return 0;
++}
++
++static int s3c_keypad_resume(struct platform_device *dev)
++{
++ /* TODO */
++ return 0;
++}
++#else
++#define s3c_keypad_suspend NULL
++#define s3c_keypad_resume NULL
++#endif /* CONFIG_PM */
++
++static struct platform_driver s3c_keypad_driver = {
++ .probe = s3c_keypad_probe,
++ .remove = s3c_keypad_remove,
++ .suspend = s3c_keypad_suspend,
++ .resume = s3c_keypad_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-keypad",
++ },
++};
++
++static int __init s3c_keypad_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&s3c_keypad_driver);
++
++ if(!ret)
++ printk(KERN_INFO "S3C Keypad Driver\n");
++
++ return ret;
++}
++
++static void __exit s3c_keypad_exit(void)
++{
++ platform_driver_unregister(&s3c_keypad_driver);
++}
++
++module_init(s3c_keypad_init);
++module_exit(s3c_keypad_exit);
++
++MODULE_AUTHOR("Samsung");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("KeyPad interface for Samsung S3C");
+diff --git a/drivers/input/keyboard/s3c-keypad.h b/drivers/input/keyboard/s3c-keypad.h
+new file mode 100644
+index 0000000..4207bfa
+--- /dev/null
++++ b/drivers/input/keyboard/s3c-keypad.h
+@@ -0,0 +1,61 @@
++/*
++ *
++ * $Id: s3c-keypad.h,v 1.5 2008/05/23 06:22:53 dark0351 Exp $
++ */
++
++#ifndef _S3C_KEYPAD_H_
++#define _S3C_KEYPAD_H_
++
++static void __iomem *key_base;
++
++#if defined(CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++#define KEYPAD_COLUMNS 8
++#define KEYPAD_ROWS 8
++#define MAX_KEYPAD_NR 64 /* 8*8 */
++#define MAX_KEYMASK_NR 32
++
++int keypad_keycode[] = {
++ 1, 2, KEY_1, KEY_Q, KEY_A, 6, 7, KEY_LEFT,
++ 9, 10, KEY_2, KEY_W, KEY_S, KEY_Z, KEY_RIGHT, 16,
++ 17, 18, KEY_3, KEY_E, KEY_D, KEY_X, 23, KEY_UP,
++ 25, 26, KEY_4, KEY_R, KEY_F, KEY_C, 31, 32,
++ 33, KEY_O, KEY_5, KEY_T, KEY_G, KEY_V, KEY_DOWN, KEY_BACKSPACE,
++ KEY_P, KEY_0, KEY_6, KEY_Y, KEY_H, KEY_SPACE, 47, 48,
++ KEY_M, KEY_L, KEY_7, KEY_U, KEY_J, KEY_N, 55, KEY_ENTER,
++ KEY_LEFTSHIFT, KEY_9, KEY_8, KEY_I, KEY_K, KEY_B, 63, KEY_COMMA
++ };
++
++
++#define KEYPAD_DELAY (50)
++#define KEYPAD_ROW_GPIOCON S3C_GPK1CON
++#define KEYPAD_ROW_GPIOPUD S3C_GPKPU
++#define KEYPAD_COL_GPIOCON S3C_GPL0CON
++#define KEYPAD_COL_GPIOPUD S3C_GPLPU
++
++#define KEYPAD_ROW_GPIO_SET \
++ ((readl(KEYPAD_ROW_GPIOCON) & ~(0xfffffff)) | 0x33333333)
++
++#define KEYPAD_COL_GPIO_SET \
++ ((readl(KEYPAD_COL_GPIOCON) & ~(0xfffffff)) | 0x33333333)
++
++#define KEYPAD_ROW_GPIOPUD_DIS (readl(KEYPAD_ROW_GPIOPUD) & ~(0xffff<<16))
++#define KEYPAD_COL_GPIOPUD_DIS (readl(KEYPAD_COL_GPIOPUD) & ~0xffff)
++
++#define KEYIFCOL_CLEAR (readl(key_base+S3C_KEYIFCOL) & ~0xffff)
++#define KEYIFCON_CLEAR (readl(key_base+S3C_KEYIFCON) & ~0x1f)
++#define KEYIFFC_DIV (readl(key_base+S3C_KEYIFFC) | 0x1)
++
++#else
++#error "Not supported S3C Configuration!!"
++#endif
++
++struct s3c_keypad {
++ struct input_dev *dev;
++ int nr_rows;
++ int no_cols;
++ int total_keys;
++ int keycodes[MAX_KEYPAD_NR];
++};
++
++
++#endif /* _S3C_KEYIF_H_ */
+diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
+index 90e8e92..7d86ea1 100644
+--- a/drivers/input/touchscreen/Kconfig
++++ b/drivers/input/touchscreen/Kconfig
+@@ -54,6 +54,30 @@ config TOUCHSCREEN_CORGI
+ To compile this driver as a module, choose M here: the
+ module will be called corgi_ts.
+
++config TOUCHSCREEN_S3C
++ tristate "S3C touchscreen driver"
++ depends on ARCH_S3C2410
++ default y
++ help
++ Say Y here to enable the driver for the touchscreen on the
++ S3C SMDK board.
++
++ If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ module will be called s3c24xx_ts.
++
++config TOUCHSCREEN_NEW
++ bool "new flip touch"
++ depends on TOUCHSCREEN_S3C
++ default y
++ help
++ Say Y here to enable the driver for the new version touchscreen on the
++ S3C SMDK board.
++
++ Say N here to enable the driver for the old version touchscreen on the
++ S3C SMDK board.
++
+ config TOUCHSCREEN_FUJITSU
+ tristate "Fujitsu serial touchscreen"
+ select SERIO
+diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
+index 35d4097..5fe784a 100644
+--- a/drivers/input/touchscreen/Makefile
++++ b/drivers/input/touchscreen/Makefile
+@@ -19,3 +19,4 @@ obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o
+ obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o
+ obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o
+ obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o
++obj-$(CONFIG_TOUCHSCREEN_S3C) += s3c-ts.o
+diff --git a/drivers/input/touchscreen/s3c-ts.c b/drivers/input/touchscreen/s3c-ts.c
+new file mode 100644
+index 0000000..e04228f
+--- /dev/null
++++ b/drivers/input/touchscreen/s3c-ts.c
+@@ -0,0 +1,468 @@
++/* linux/drivers/input/touchscreen/s3c-ts.c
++ *
++ * $Id: s3c-ts2.c,v 1.2 2008/11/12 05:50:51 ihlee215 Exp $
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
++ * iPAQ H1940 touchscreen support
++ *
++ * ChangeLog
++ *
++ * 2004-09-05: Herbert Potzl <herbert@13thfloor.at>
++ * - added clock (de-)allocation code
++ *
++ * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org>
++ * - h1940_ -> s3c24xx (this driver is now also used on the n30
++ * machines :P)
++ * - Debug messages are now enabled with the config option
++ * TOUCHSCREEN_S3C_DEBUG
++ * - Changed the way the value are read
++ * - Input subsystem should now work
++ * - Use ioremap and readl/writel
++ *
++ * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org>
++ * - Make use of some undocumented features of the touchscreen
++ * controller
++ *
++ * 2006-09-05: Ryu Euiyoul <ryu.real@gmail.com>
++ * - added power management suspend and resume code
++ *
++ */
++
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++
++#include <asm/plat-s3c/regs-adc.h>
++#include <asm/plat-s3c/ts.h>
++#include <asm/arch/irqs.h>
++
++
++#define CONFIG_TOUCHSCREEN_S3C_DEBUG
++#undef CONFIG_TOUCHSCREEN_S3C_DEBUG
++
++/* For ts->dev.id.version */
++#define S3C_TSVERSION 0x0101
++
++#define WAIT4INT(x) (((x)<<8) | \
++ S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \
++ S3C2410_ADCTSC_XY_PST(3))
++
++#define AUTOPST (S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \
++ S3C2410_ADCTSC_AUTO_PST | S3C2410_ADCTSC_XY_PST(0))
++
++
++#define DEBUG_LVL KERN_DEBUG
++
++
++
++/* Touchscreen default configuration */
++struct s3c_ts_mach_info s3c_ts_default_cfg __initdata = {
++ .delay = 10000,
++ .presc = 49,
++ .oversampling_shift = 2,
++ .resol_bit = 10,
++};
++
++/*
++ * Definitions & global arrays.
++ */
++static char *s3c_ts_name = "S3C TouchScreen";
++static void __iomem *ts_base;
++static struct resource *ts_mem;
++static struct resource *ts_irq;
++static struct clk *ts_clock;
++static struct s3c_ts *ts;
++
++static void touch_timer_fire(unsigned long data)
++{
++ unsigned long data0;
++ unsigned long data1;
++ int updown;
++
++ data0 = readl(ts_base+S3C2410_ADCDAT0);
++ data1 = readl(ts_base+S3C2410_ADCDAT1);
++
++ updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT1_UPDOWN));
++
++ if (updown) {
++ if (ts->count) {
++
++#ifdef CONFIG_TOUCHSCREEN_S3C_DEBUG
++ {
++ struct timeval tv;
++ do_gettimeofday(&tv);
++ printk(KERN_INFO "T: %06d, X: %03ld, Y: %03ld\n", (int)tv.tv_usec, ts->xp, ts->yp);
++ }
++#endif
++
++ input_report_abs(ts->dev, ABS_X, ts->xp);
++ input_report_abs(ts->dev, ABS_Y, ts->yp);
++
++ input_report_key(ts->dev, BTN_TOUCH, 1);
++ input_report_abs(ts->dev, ABS_PRESSURE, 1);
++ input_sync(ts->dev);
++ }
++
++ ts->xp = 0;
++ ts->yp = 0;
++ ts->count = 0;
++
++ writel(S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST, ts_base+S3C2410_ADCTSC);
++ writel(readl(ts_base+S3C2410_ADCCON) | S3C2410_ADCCON_ENABLE_START, ts_base+S3C2410_ADCCON);
++ }
++ else {
++
++ ts->count = 0;
++
++ input_report_key(ts->dev, BTN_TOUCH, 0);
++ input_report_abs(ts->dev, ABS_PRESSURE, 0);
++ input_sync(ts->dev);
++
++ writel(WAIT4INT(0), ts_base+S3C2410_ADCTSC);
++ }
++}
++
++static struct timer_list touch_timer =
++ TIMER_INITIALIZER(touch_timer_fire, 0, 0);
++
++static irqreturn_t stylus_updown(int irqno, void *param)
++{
++ unsigned long data0;
++ unsigned long data1;
++ int updown;
++
++ data0 = readl(ts_base+S3C2410_ADCDAT0);
++ data1 = readl(ts_base+S3C2410_ADCDAT1);
++
++ updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT1_UPDOWN));
++
++#ifdef CONFIG_TOUCHSCREEN_S3C_DEBUG
++ printk(KERN_INFO " %c\n", updown ? 'D' : 'U');
++#endif
++
++ /* TODO we should never get an interrupt with updown set while
++ * the timer is running, but maybe we ought to verify that the
++ * timer isn't running anyways. */
++
++ if (updown)
++ touch_timer_fire(0);
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ __raw_writel(0x0, ts_base+S3C6400_ADCCLRWK);
++ __raw_writel(0x0, ts_base+S3C6400_ADCCLRINT);
++#endif
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t stylus_action(int irqno, void *param)
++{
++ unsigned long data0;
++ unsigned long data1;
++
++ data0 = readl(ts_base+S3C2410_ADCDAT0);
++ data1 = readl(ts_base+S3C2410_ADCDAT1);
++
++#if defined(CONFIG_TOUCHSCREEN_NEW)
++ ts->yp += S3C_ADCDAT0_XPDATA_MASK_12BIT - (data0 & S3C_ADCDAT0_XPDATA_MASK_12BIT);
++ ts->xp += S3C_ADCDAT1_YPDATA_MASK_12BIT - (data1 & S3C_ADCDAT1_YPDATA_MASK_12BIT);
++
++#elif defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C6410)
++ ts->xp += data0 & S3C_ADCDAT0_XPDATA_MASK_12BIT;
++ ts->yp += data1 & S3C_ADCDAT1_YPDATA_MASK_12BIT;
++#else
++ ts->xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK;
++ ts->yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK;
++#endif
++
++ ts->count++;
++
++ if (ts->count < (1<<ts->shift)) {
++ writel(S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST, ts_base+S3C2410_ADCTSC);
++ writel(readl(ts_base+S3C2410_ADCCON) | S3C2410_ADCCON_ENABLE_START, ts_base+S3C2410_ADCCON);
++ } else {
++ mod_timer(&touch_timer, jiffies+1);
++ writel(WAIT4INT(1), ts_base+S3C2410_ADCTSC);
++ }
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ __raw_writel(0x0, ts_base+S3C6400_ADCCLRWK);
++ __raw_writel(0x0, ts_base+S3C6400_ADCCLRINT);
++#endif
++
++ return IRQ_HANDLED;
++}
++
++
++static struct s3c_ts_mach_info *s3c_ts_get_platdata (struct device *dev)
++{
++ if (dev->platform_data != NULL)
++ return (struct s3c_ts_mach_info *)dev->platform_data;
++
++ return &s3c_ts_default_cfg;
++}
++
++/*
++ * The functions for inserting/removing us as a module.
++ */
++static int __init s3c_ts_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ struct input_dev *input_dev;
++ struct s3c_ts_mach_info * s3c_ts_cfg;
++ int ret, size;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res == NULL) {
++ printk(KERN_ERR "no memory resource specified\n");
++ return -ENOENT;
++ }
++
++ size = (res->end - res->start) + 1;
++ ts_mem = request_mem_region(res->start, size, pdev->name);
++ if (ts_mem == NULL) {
++ printk(KERN_ERR "failed to get memory region\n");
++ ret = -ENOENT;
++ goto err_req;
++ }
++
++ ts_base = ioremap(res->start, size);
++ if (ts_base == NULL) {
++ printk(KERN_ERR "failed to ioremap() region\n");
++ ret = -EINVAL;
++ goto err_map;
++ }
++
++ ts_clock = clk_get(&pdev->dev, "adc");
++ if (IS_ERR(ts_clock)) {
++ printk(KERN_ERR "failed to find watchdog clock source\n");
++ ret = PTR_ERR(ts_clock);
++ goto err_clk;
++ }
++
++ clk_enable(ts_clock);
++
++ s3c_ts_cfg = s3c_ts_get_platdata(&pdev->dev);
++
++ if ((s3c_ts_cfg->presc&0xff) > 0)
++ writel(S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(s3c_ts_cfg->presc&0xFF),\
++ ts_base+S3C2410_ADCCON);
++ else
++ writel(0, ts_base+S3C2410_ADCCON);
++
++
++ /* Initialise registers */
++ if ((s3c_ts_cfg->delay&0xffff) > 0)
++ writel(s3c_ts_cfg->delay & 0xffff, ts_base+S3C2410_ADCDLY);
++
++ if (s3c_ts_cfg->resol_bit == 12) {
++#if defined(CONFIG_CPU_S3C6410)
++ writel(readl(ts_base+S3C2410_ADCCON)|S3C6410_ADCCON_RESSEL_12BIT, ts_base+S3C2410_ADCCON);
++#elif defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ writel(readl(ts_base+S3C2410_ADCCON)|S3C2450_ADCCON_RESSEL_12BIT, ts_base+S3C2410_ADCCON);
++#endif
++ }
++
++ writel(WAIT4INT(0), ts_base+S3C2410_ADCTSC);
++
++ ts = kzalloc(sizeof(struct s3c_ts), GFP_KERNEL);
++
++ input_dev = input_allocate_device();
++
++ if (!input_dev) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ ts->dev = input_dev;
++
++ ts->dev->evbit[0] = ts->dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
++ ts->dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2416)
++ input_set_abs_params(ts->dev, ABS_X, 0, 0xFFF, 0, 0);
++ input_set_abs_params(ts->dev, ABS_Y, 0, 0xFFF, 0, 0);
++#else
++ input_set_abs_params(ts->dev, ABS_X, 0, 0x3FF, 0, 0);
++ input_set_abs_params(ts->dev, ABS_Y, 0, 0x3FF, 0, 0);
++#endif
++ input_set_abs_params(ts->dev, ABS_PRESSURE, 0, 1, 0, 0);
++
++ sprintf(ts->phys, "input(ts)");
++
++ ts->dev->name = s3c_ts_name;
++ ts->dev->phys = ts->phys;
++ ts->dev->id.bustype = BUS_RS232;
++ ts->dev->id.vendor = 0xDEAD;
++ ts->dev->id.product = 0xBEEF;
++ ts->dev->id.version = S3C_TSVERSION;
++
++ ts->shift = s3c_ts_cfg->oversampling_shift;
++
++ /* Get irqs */
++ ts_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (ts_irq == NULL) {
++ printk(KERN_ERR "no irq resource specified\n");
++ ret = -ENOENT;
++ goto err_clk;
++ }
++
++ ret = request_irq(ts_irq->start, stylus_updown, IRQF_SAMPLE_RANDOM, "s3c_updown", ts);
++ if (ret != 0) {
++ printk(KERN_ERR "s3c_ts.c: Could not allocate ts IRQ_TC !\n");
++ ret = -EIO;
++ goto err_clk;
++ }
++
++ ret = request_irq(ts_irq->end, stylus_action, IRQF_SAMPLE_RANDOM, "s3c_action", ts);
++ if (ret != 0) {
++ printk(KERN_ERR "s3c_ts.c: Could not allocate ts IRQ_ADC !\n");
++ ret = -EIO;
++ goto err_irq;
++ }
++
++ printk(KERN_INFO "%s got loaded successfully : %d bits\n", s3c_ts_name, s3c_ts_cfg->resol_bit);
++
++ /* All went ok, so register to the input system */
++ ret = input_register_device(ts->dev);
++
++ if(ret) {
++ printk(KERN_ERR "s3c_ts.c: Could not register input device(touchscreen)!\n");
++ ret = -EIO;
++ goto fail;
++ }
++
++ return 0;
++
++fail: input_free_device(input_dev);
++ kfree(ts);
++
++err_irq:
++ free_irq(ts_irq->start, ts->dev);
++ free_irq(ts_irq->end, ts->dev);
++
++err_clk:
++ clk_disable(ts_clock);
++ clk_put(ts_clock);
++
++err_map:
++ iounmap(ts_base);
++
++err_req:
++ release_resource(ts_mem);
++ kfree(ts_mem);
++
++ return ret;
++}
++
++static int s3c_ts_remove(struct platform_device *dev)
++{
++ printk(KERN_INFO "s3c_ts_remove() of TS called !\n");
++
++ disable_irq(IRQ_ADC);
++ disable_irq(IRQ_TC);
++ free_irq(IRQ_TC, ts->dev);
++ free_irq(IRQ_ADC, ts->dev);
++
++ if (ts_clock) {
++ clk_disable(ts_clock);
++ clk_put(ts_clock);
++ ts_clock = NULL;
++ }
++
++ input_unregister_device(ts->dev);
++ iounmap(ts_base);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static unsigned int adccon, adctsc, adcdly;
++
++static int s3c_ts_suspend(struct platform_device *dev, pm_message_t state)
++{
++ adccon = readl(ts_base+S3C2410_ADCCON);
++ adctsc = readl(ts_base+S3C2410_ADCTSC);
++ adcdly = readl(ts_base+S3C2410_ADCDLY);
++
++ disable_irq(IRQ_ADC);
++ disable_irq(IRQ_TC);
++
++ clk_disable(ts_clock);
++
++ return 0;
++}
++
++static int s3c_ts_resume(struct platform_device *pdev)
++{
++ clk_enable(ts_clock);
++
++ writel(adccon, ts_base+S3C2410_ADCCON);
++ writel(adctsc, ts_base+S3C2410_ADCTSC);
++ writel(adcdly, ts_base+S3C2410_ADCDLY);
++ writel(WAIT4INT(0), ts_base+S3C2410_ADCTSC);
++
++ enable_irq(IRQ_ADC);
++ enable_irq(IRQ_TC);
++ return 0;
++}
++#else
++#define s3c_ts_suspend NULL
++#define s3c_ts_resume NULL
++#endif
++
++static struct platform_driver s3c_ts_driver = {
++ .probe = s3c_ts_probe,
++ .remove = s3c_ts_remove,
++ .suspend = s3c_ts_suspend,
++ .resume = s3c_ts_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-ts",
++ },
++};
++
++static char banner[] __initdata = KERN_INFO "S3C Touchscreen driver, (c) 2008 Samsung Electronics\n";
++
++static int __init s3c_ts_init(void)
++{
++ printk(banner);
++ return platform_driver_register(&s3c_ts_driver);
++}
++
++static void __exit s3c_ts_exit(void)
++{
++ platform_driver_unregister(&s3c_ts_driver);
++}
++
++module_init(s3c_ts_init);
++module_exit(s3c_ts_exit);
++
++MODULE_AUTHOR("Samsung AP");
++MODULE_DESCRIPTION("S3C touchscreen driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/input/tsdev.c b/drivers/input/tsdev.c
+new file mode 100644
+index 0000000..5622a60
+--- /dev/null
++++ b/drivers/input/tsdev.c
+@@ -0,0 +1,533 @@
++/*
++ * $Id: tsdev.c,v 1.1.1.1 2008/02/04 07:21:25 ihlee215 Exp $
++ *
++ * Copyright (c) 2001 "Crazy" james Simmons
++ *
++ * Compaq touchscreen protocol driver. The protocol emulated by this driver
++ * is obsolete; for new programs use the tslib library which can read directly
++ * from evdev and perform dejittering, variance filtering and calibration -
++ * all in user space, not at kernel level. The meaning of this driver is
++ * to allow usage of newer input drivers with old applications that use the
++ * old /dev/h3600_ts and /dev/h3600_tsraw devices.
++ *
++ * 09-Apr-2004: Andrew Zabolotny <zap@homelink.ru>
++ * Fixed to actually work, not just output random numbers.
++ * Added support for both h3600_ts and h3600_tsraw protocol
++ * emulation.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * Should you need to contact me, the author, you can do so either by
++ * e-mail - mail your message to <jsimmons@infradead.org>.
++ */
++
++#define TSDEV_MINOR_BASE 128
++#define TSDEV_MINORS 32
++/* First 16 devices are h3600_ts compatible; second 16 are h3600_tsraw */
++#define TSDEV_MINOR_MASK 15
++#define TSDEV_BUFFER_SIZE 64
++
++#include <linux/slab.h>
++#include <linux/poll.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/input.h>
++#include <linux/major.h>
++#include <linux/random.h>
++#include <linux/time.h>
++#include <linux/device.h>
++
++#ifndef CONFIG_INPUT_TSDEV_SCREEN_X
++#define CONFIG_INPUT_TSDEV_SCREEN_X 240
++#endif
++#ifndef CONFIG_INPUT_TSDEV_SCREEN_Y
++#define CONFIG_INPUT_TSDEV_SCREEN_Y 320
++#endif
++
++/* This driver emulates both protocols of the old h3600_ts and h3600_tsraw
++ * devices. The first one must output X/Y data in 'cooked' format, e.g.
++ * filtered, dejittered and calibrated. Second device just outputs raw
++ * data received from the hardware.
++ *
++ * This driver doesn't support filtering and dejittering; it supports only
++ * calibration. Filtering and dejittering must be done in the low-level
++ * driver, if needed, because it may gain additional benefits from knowing
++ * the low-level details, the nature of noise and so on.
++ *
++ * The driver precomputes a calibration matrix given the initial xres and
++ * yres values (quite innacurate for most touchscreens) that will result
++ * in a more or less expected range of output values. The driver supports
++ * the TS_SET_CAL ioctl, which will replace the calibration matrix with a
++ * new one, supposedly generated from the values taken from the raw device.
++ */
++
++MODULE_AUTHOR("James Simmons <jsimmons@transvirtual.com>");
++MODULE_DESCRIPTION("Input driver to touchscreen converter");
++MODULE_LICENSE("GPL");
++
++static int xres = CONFIG_INPUT_TSDEV_SCREEN_X;
++module_param(xres, uint, 0);
++MODULE_PARM_DESC(xres, "Horizontal screen resolution (can be negative for X-mirror)");
++
++static int yres = CONFIG_INPUT_TSDEV_SCREEN_Y;
++module_param(yres, uint, 0);
++MODULE_PARM_DESC(yres, "Vertical screen resolution (can be negative for Y-mirror)");
++
++/* From Compaq's Touch Screen Specification version 0.2 (draft) */
++struct ts_event {
++ short pressure;
++ short x;
++ short y;
++ short millisecs;
++};
++
++struct ts_calibration {
++ int xscale;
++ int xtrans;
++ int yscale;
++ int ytrans;
++ int xyswap;
++};
++
++struct tsdev {
++ int exist;
++ int open;
++ int minor;
++ char name[8];
++ struct input_handle handle;
++ wait_queue_head_t wait;
++ struct list_head client_list;
++ struct device dev;
++
++ int x, y, pressure;
++ struct ts_calibration cal;
++};
++
++struct tsdev_client {
++ struct fasync_struct *fasync;
++ struct list_head node;
++ struct tsdev *tsdev;
++ int head, tail;
++ struct ts_event event[TSDEV_BUFFER_SIZE];
++ int raw;
++};
++
++/* The following ioctl codes are defined ONLY for backward compatibility.
++ * Don't use tsdev for new developement; use the tslib library instead.
++ * Touchscreen calibration is a fully userspace task.
++ */
++/* Use 'f' as magic number */
++#define IOC_H3600_TS_MAGIC 'f'
++#define TS_GET_CAL _IOR(IOC_H3600_TS_MAGIC, 10, struct ts_calibration)
++#define TS_SET_CAL _IOW(IOC_H3600_TS_MAGIC, 11, struct ts_calibration)
++
++static struct tsdev *tsdev_table[TSDEV_MINORS/2];
++
++static int tsdev_fasync(int fd, struct file *file, int on)
++{
++ struct tsdev_client *client = file->private_data;
++ int retval;
++
++ retval = fasync_helper(fd, file, on, &client->fasync);
++ return retval < 0 ? retval : 0;
++}
++
++static int tsdev_open(struct inode *inode, struct file *file)
++{
++ int i = iminor(inode) - TSDEV_MINOR_BASE;
++ struct tsdev_client *client;
++ struct tsdev *tsdev;
++ int error;
++
++ printk(KERN_WARNING "tsdev (compaq touchscreen emulation) is scheduled "
++ "for removal.\nSee Documentation/feature-removal-schedule.txt "
++ "for details.\n");
++
++ if (i >= TSDEV_MINORS)
++ return -ENODEV;
++
++ tsdev = tsdev_table[i & TSDEV_MINOR_MASK];
++ if (!tsdev || !tsdev->exist)
++ return -ENODEV;
++
++ get_device(&tsdev->dev);
++
++ client = kzalloc(sizeof(struct tsdev_client), GFP_KERNEL);
++ if (!client) {
++ error = -ENOMEM;
++ goto err_put_tsdev;
++ }
++
++ client->tsdev = tsdev;
++ client->raw = (i >= TSDEV_MINORS / 2) ? 1 : 0;
++ list_add_tail(&client->node, &tsdev->client_list);
++
++ if (!tsdev->open++ && tsdev->exist) {
++ error = input_open_device(&tsdev->handle);
++ if (error)
++ goto err_free_client;
++ }
++
++ file->private_data = client;
++ return 0;
++
++ err_free_client:
++ list_del(&client->node);
++ kfree(client);
++ err_put_tsdev:
++ put_device(&tsdev->dev);
++ return error;
++}
++
++static void tsdev_free(struct device *dev)
++{
++ struct tsdev *tsdev = container_of(dev, struct tsdev, dev);
++
++ tsdev_table[tsdev->minor] = NULL;
++ kfree(tsdev);
++}
++
++static int tsdev_release(struct inode *inode, struct file *file)
++{
++ struct tsdev_client *client = file->private_data;
++ struct tsdev *tsdev = client->tsdev;
++
++ tsdev_fasync(-1, file, 0);
++
++ list_del(&client->node);
++ kfree(client);
++
++ if (!--tsdev->open && tsdev->exist)
++ input_close_device(&tsdev->handle);
++
++ put_device(&tsdev->dev);
++
++ return 0;
++}
++
++static ssize_t tsdev_read(struct file *file, char __user *buffer, size_t count,
++ loff_t *ppos)
++{
++ struct tsdev_client *client = file->private_data;
++ struct tsdev *tsdev = client->tsdev;
++ int retval = 0;
++
++ if (client->head == client->tail && tsdev->exist && (file->f_flags & O_NONBLOCK))
++ return -EAGAIN;
++
++ retval = wait_event_interruptible(tsdev->wait,
++ client->head != client->tail || !tsdev->exist);
++ if (retval)
++ return retval;
++
++ if (!tsdev->exist)
++ return -ENODEV;
++
++ while (client->head != client->tail &&
++ retval + sizeof (struct ts_event) <= count) {
++ if (copy_to_user (buffer + retval, client->event + client->tail,
++ sizeof (struct ts_event)))
++ return -EFAULT;
++ client->tail = (client->tail + 1) & (TSDEV_BUFFER_SIZE - 1);
++ retval += sizeof (struct ts_event);
++ }
++
++ return retval;
++}
++
++/* No kernel lock - fine */
++static unsigned int tsdev_poll(struct file *file, poll_table *wait)
++{
++ struct tsdev_client *client = file->private_data;
++ struct tsdev *tsdev = client->tsdev;
++
++ poll_wait(file, &tsdev->wait, wait);
++ return ((client->head == client->tail) ? 0 : (POLLIN | POLLRDNORM)) |
++ (tsdev->exist ? 0 : (POLLHUP | POLLERR));
++}
++
++static int tsdev_ioctl(struct inode *inode, struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ struct tsdev_client *client = file->private_data;
++ struct tsdev *tsdev = client->tsdev;
++ int retval = 0;
++
++ switch (cmd) {
++ case TS_GET_CAL:
++ if (copy_to_user((void __user *)arg, &tsdev->cal,
++ sizeof (struct ts_calibration)))
++ retval = -EFAULT;
++ break;
++
++ case TS_SET_CAL:
++ if (copy_from_user(&tsdev->cal, (void __user *)arg,
++ sizeof (struct ts_calibration)))
++ retval = -EFAULT;
++ break;
++
++ default:
++ retval = -EINVAL;
++ break;
++ }
++
++ return retval;
++}
++
++static const struct file_operations tsdev_fops = {
++ .owner = THIS_MODULE,
++ .open = tsdev_open,
++ .release = tsdev_release,
++ .read = tsdev_read,
++ .poll = tsdev_poll,
++ .fasync = tsdev_fasync,
++ .ioctl = tsdev_ioctl,
++};
++
++static void tsdev_event(struct input_handle *handle, unsigned int type,
++ unsigned int code, int value)
++{
++ struct tsdev *tsdev = handle->private;
++ struct tsdev_client *client;
++ struct timeval time;
++
++ switch (type) {
++ case EV_ABS:
++ switch (code) {
++ case ABS_X:
++ tsdev->x = value;
++ break;
++
++ case ABS_Y:
++ tsdev->y = value;
++ break;
++
++ case ABS_PRESSURE:
++ if (value > handle->dev->absmax[ABS_PRESSURE])
++ value = handle->dev->absmax[ABS_PRESSURE];
++ value -= handle->dev->absmin[ABS_PRESSURE];
++ if (value < 0)
++ value = 0;
++ tsdev->pressure = value;
++ break;
++ }
++ break;
++
++ case EV_REL:
++ switch (code) {
++ case REL_X:
++ tsdev->x += value;
++ if (tsdev->x < 0)
++ tsdev->x = 0;
++ else if (tsdev->x > xres)
++ tsdev->x = xres;
++ break;
++
++ case REL_Y:
++ tsdev->y += value;
++ if (tsdev->y < 0)
++ tsdev->y = 0;
++ else if (tsdev->y > yres)
++ tsdev->y = yres;
++ break;
++ }
++ break;
++
++ case EV_KEY:
++ if (code == BTN_TOUCH || code == BTN_MOUSE) {
++ switch (value) {
++ case 0:
++ tsdev->pressure = 0;
++ break;
++
++ case 1:
++ if (!tsdev->pressure)
++ tsdev->pressure = 1;
++ break;
++ }
++ }
++ break;
++ }
++
++ if (type != EV_SYN || code != SYN_REPORT)
++ return;
++
++ list_for_each_entry(client, &tsdev->client_list, node) {
++ int x, y, tmp;
++
++ do_gettimeofday(&time);
++ client->event[client->head].millisecs = time.tv_usec / 1000;
++ client->event[client->head].pressure = tsdev->pressure;
++
++ x = tsdev->x;
++ y = tsdev->y;
++
++ /* Calibration */
++ if (!client->raw) {
++ x = ((x * tsdev->cal.xscale) >> 8) + tsdev->cal.xtrans;
++ y = ((y * tsdev->cal.yscale) >> 8) + tsdev->cal.ytrans;
++ if (tsdev->cal.xyswap) {
++ tmp = x; x = y; y = tmp;
++ }
++ }
++
++ client->event[client->head].x = x;
++ client->event[client->head].y = y;
++ client->head = (client->head + 1) & (TSDEV_BUFFER_SIZE - 1);
++ kill_fasync(&client->fasync, SIGIO, POLL_IN);
++ }
++ wake_up_interruptible(&tsdev->wait);
++}
++
++static int tsdev_connect(struct input_handler *handler, struct input_dev *dev,
++ const struct input_device_id *id)
++{
++ struct tsdev *tsdev;
++ int minor, delta;
++ int error;
++
++ for (minor = 0; minor < TSDEV_MINORS / 2 && tsdev_table[minor]; minor++);
++ if (minor >= TSDEV_MINORS / 2) {
++ printk(KERN_ERR
++ "tsdev: You have way too many touchscreens\n");
++ return -ENFILE;
++ }
++
++ tsdev = kzalloc(sizeof(struct tsdev), GFP_KERNEL);
++ if (!tsdev)
++ return -ENOMEM;
++
++ INIT_LIST_HEAD(&tsdev->client_list);
++ init_waitqueue_head(&tsdev->wait);
++
++ tsdev->exist = 1;
++ tsdev->minor = minor;
++ tsdev->handle.dev = dev;
++ tsdev->handle.name = tsdev->name;
++ tsdev->handle.handler = handler;
++ tsdev->handle.private = tsdev;
++ snprintf(tsdev->name, sizeof(tsdev->name), "ts%d", minor);
++
++ /* Precompute the rough calibration matrix */
++ delta = dev->absmax [ABS_X] - dev->absmin [ABS_X] + 1;
++ if (delta == 0)
++ delta = 1;
++ tsdev->cal.xscale = (xres << 8) / delta;
++ tsdev->cal.xtrans = - ((dev->absmin [ABS_X] * tsdev->cal.xscale) >> 8);
++
++ delta = dev->absmax [ABS_Y] - dev->absmin [ABS_Y] + 1;
++ if (delta == 0)
++ delta = 1;
++ tsdev->cal.yscale = (yres << 8) / delta;
++ tsdev->cal.ytrans = - ((dev->absmin [ABS_Y] * tsdev->cal.yscale) >> 8);
++
++ snprintf(tsdev->dev.bus_id, sizeof(tsdev->dev.bus_id),
++ "ts%d", minor);
++ tsdev->dev.class = &input_class;
++ tsdev->dev.parent = &dev->dev;
++ tsdev->dev.devt = MKDEV(INPUT_MAJOR, TSDEV_MINOR_BASE + minor);
++ tsdev->dev.release = tsdev_free;
++ device_initialize(&tsdev->dev);
++
++ tsdev_table[minor] = tsdev;
++
++ error = device_add(&tsdev->dev);
++ if (error)
++ goto err_free_tsdev;
++
++ error = input_register_handle(&tsdev->handle);
++ if (error)
++ goto err_delete_tsdev;
++
++ return 0;
++
++ err_delete_tsdev:
++ device_del(&tsdev->dev);
++ err_free_tsdev:
++ put_device(&tsdev->dev);
++ return error;
++}
++
++static void tsdev_disconnect(struct input_handle *handle)
++{
++ struct tsdev *tsdev = handle->private;
++ struct tsdev_client *client;
++
++ input_unregister_handle(handle);
++ device_del(&tsdev->dev);
++
++ tsdev->exist = 0;
++
++ if (tsdev->open) {
++ input_close_device(handle);
++ list_for_each_entry(client, &tsdev->client_list, node)
++ kill_fasync(&client->fasync, SIGIO, POLL_HUP);
++ wake_up_interruptible(&tsdev->wait);
++ }
++
++ put_device(&tsdev->dev);
++}
++
++static const struct input_device_id tsdev_ids[] = {
++ {
++ .flags = INPUT_DEVICE_ID_MATCH_EVBIT | INPUT_DEVICE_ID_MATCH_KEYBIT | INPUT_DEVICE_ID_MATCH_RELBIT,
++ .evbit = { BIT(EV_KEY) | BIT(EV_REL) },
++ .keybit = { [BIT_WORD(BTN_LEFT)] = BIT(BTN_LEFT) },
++ .relbit = { BIT(REL_X) | BIT(REL_Y) },
++ }, /* A mouse like device, at least one button, two relative axes */
++
++ {
++ .flags = INPUT_DEVICE_ID_MATCH_EVBIT | INPUT_DEVICE_ID_MATCH_KEYBIT | INPUT_DEVICE_ID_MATCH_ABSBIT,
++ .evbit = { BIT(EV_KEY) | BIT(EV_ABS) },
++ .keybit = { [BIT_WORD(BTN_TOUCH)] = BIT(BTN_TOUCH) },
++ .absbit = { BIT(ABS_X) | BIT(ABS_Y) },
++ }, /* A tablet like device, at least touch detection, two absolute axes */
++
++ {
++ .flags = INPUT_DEVICE_ID_MATCH_EVBIT | INPUT_DEVICE_ID_MATCH_ABSBIT,
++ .evbit = { BIT(EV_ABS) },
++ .absbit = { BIT(ABS_X) | BIT(ABS_Y) | BIT(ABS_PRESSURE) },
++ }, /* A tablet like device with several gradations of pressure */
++
++ {} /* Terminating entry */
++};
++
++MODULE_DEVICE_TABLE(input, tsdev_ids);
++
++static struct input_handler tsdev_handler = {
++ .event = tsdev_event,
++ .connect = tsdev_connect,
++ .disconnect = tsdev_disconnect,
++ .fops = &tsdev_fops,
++ .minor = TSDEV_MINOR_BASE,
++ .name = "tsdev",
++ .id_table = tsdev_ids,
++};
++
++static int __init tsdev_init(void)
++{
++ return input_register_handler(&tsdev_handler);
++}
++
++static void __exit tsdev_exit(void)
++{
++ input_unregister_handler(&tsdev_handler);
++}
++
++module_init(tsdev_init);
++module_exit(tsdev_exit);
+diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
+index c9f14bf..6506263 100644
+--- a/drivers/media/video/Kconfig
++++ b/drivers/media/video/Kconfig
+@@ -505,6 +505,47 @@ config TUNER_3036
+ Say Y here to include support for Philips SAB3036 compatible tuners.
+ If in doubt, say N.
+
++
++config VIDEO_SAMSUNG
++ bool "S3C SMDK CAMERA support"
++ depends on I2C && VIDEO_V4L2
++
++ default n
++ ---help---
++ TBA
++choice
++depends on VIDEO_SAMSUNG
++prompt "Select CIS module type"
++default VIDEO_SAMSUNG_S5K3BA
++
++config VIDEO_SAMSUNG_S5K3AA
++ bool "S5K3AA (Samsung 1.3M CIS module, 1280x1024)"
++ ---help---
++ TBA
++
++config VIDEO_SAMSUNG_S5K3BA
++ bool "S5K3BA (Samsung 2.0M CIS module, 1600x1200)"
++ ---help---
++ TBA
++
++config VIDEO_SAMSUNG_S5K4BA
++ bool "S5K4BA (Samsung 2.0M CIS module, 1600x1200)"
++ ---help---
++ TBA
++
++config VIDEO_APTINA_MT9P012
++ bool "MT9P012 (Aptina 5.0M CIS module, 2592x1944)"
++ ---help---
++ TBA
++
++config VIDEO_ADV7180
++ bool "ADV7180 video decoder"
++ ---help---
++ TBA
++
++endchoice
++
++
+ config VIDEO_VINO
+ tristate "SGI Vino Video For Linux (EXPERIMENTAL)"
+ depends on I2C && SGI_IP22 && EXPERIMENTAL && VIDEO_V4L2
+diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
+index b5a0641..cd3d371 100644
+--- a/drivers/media/video/Makefile
++++ b/drivers/media/video/Makefile
+@@ -125,6 +125,7 @@ obj-$(CONFIG_USB_QUICKCAM_MESSENGER) += usbvideo/
+
+ obj-$(CONFIG_VIDEO_IVTV) += ivtv/
+
++obj-$(CONFIG_VIDEO_SAMSUNG) += s3c_camera_driver.o s3c_camif.o samsung/
+ obj-$(CONFIG_VIDEO_VIVI) += vivi.o
+ obj-$(CONFIG_VIDEO_CX23885) += cx23885/
+
+diff --git a/drivers/media/video/s3c_camera_driver.c b/drivers/media/video/s3c_camera_driver.c
+new file mode 100644
+index 0000000..e8a86c0
+--- /dev/null
++++ b/drivers/media/video/s3c_camera_driver.c
+@@ -0,0 +1,2041 @@
++/* drivers/media/video/s3c_camera_driver.c
++ *
++ * Copyright (c) 2008 Samsung Electronics
++ *
++ * Samsung S3C Camera driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/fs.h>
++#include <linux/kernel.h>
++#include <linux/major.h>
++#include <linux/slab.h>
++#include <linux/poll.h>
++#include <linux/signal.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/kmod.h>
++#include <linux/vmalloc.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++#include <linux/mm.h>
++#include <linux/videodev2.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <asm/io.h>
++#include <asm/page.h>
++#include <asm/semaphore.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-camif.h>
++#include <media/v4l2-dev.h>
++#include "s3c_camif.h"
++#include "videodev2_s3c.h"
++
++#if defined(CONFIG_PM)
++#include <asm/plat-s3c24xx/pm.h>
++#endif
++
++static struct clk *cam_clock;
++camif_cfg_t s3c_fimc[CAMIF_DEV_NUM];
++extern camif_cis_t msdma_input;
++extern int s3c_camif_do_postprocess(camif_cfg_t *cfg);
++
++/*************************************************************************
++ * Utility part
++ ************************************************************************/
++camif_cfg_t *s3c_camif_get_fimc_object(int nr)
++{
++ camif_cfg_t *ret = NULL;
++
++ switch (nr) {
++ case CODEC_MINOR:
++ ret = &s3c_fimc[FIMC_CODEC_INDEX];
++ break;
++
++ case PREVIEW_MINOR:
++ ret = &s3c_fimc[FIMC_PREVIEW_INDEX];
++ break;
++
++ default:
++ printk(KERN_ERR "Unknown minor number\n");
++ }
++
++ return ret;
++}
++
++#if defined(FSM_ON_PREVIEW)
++static int s3c_camif_check_global_status(camif_cfg_t *cfg)
++{
++ int ret = 0;
++
++ if (down_interruptible((struct semaphore *) &cfg->cis->lock))
++ return -ERESTARTSYS;
++
++ if (cfg->cis->status & CWANT2START) {
++ cfg->cis->status &= ~CWANT2START;
++ cfg->auto_restart = 1;
++ ret = 1;
++ } else {
++ ret = 0; /* There is no codec */
++ cfg->auto_restart = 0; /* Duplicated ..Dummy */
++ }
++
++ up((struct semaphore *) &cfg->cis->lock);
++
++ return ret;
++}
++#endif
++
++static int s3c_camif_convert_format(int pixfmt, int *fmtptr)
++{
++ int fmt = CAMIF_YCBCR420;
++ int depth = 12;
++
++ switch (pixfmt) {
++ case V4L2_PIX_FMT_RGB565:
++ case V4L2_PIX_FMT_RGB565X:
++ fmt = CAMIF_RGB16;
++ depth = 16;
++ break;
++
++ case V4L2_PIX_FMT_BGR24: /* Not tested */
++ case V4L2_PIX_FMT_RGB24:
++ fmt = CAMIF_RGB24;
++ depth = 24;
++ break;
++
++ case V4L2_PIX_FMT_BGR32:
++ case V4L2_PIX_FMT_RGB32:
++ fmt = CAMIF_RGB24;
++ depth = 32;
++ break;
++
++ case V4L2_PIX_FMT_GREY: /* Not tested */
++ fmt = CAMIF_YCBCR420;
++ depth = 8;
++ break;
++
++ case V4L2_PIX_FMT_YUYV:
++ case V4L2_PIX_FMT_UYVY:
++ fmt = CAMIF_YCBCR422I;
++ depth = 16;
++ break;
++
++ case V4L2_PIX_FMT_YUV422P:
++ fmt = CAMIF_YCBCR422;
++ depth = 16;
++ break;
++
++ case V4L2_PIX_FMT_YUV420:
++ fmt = CAMIF_YCBCR420;
++ depth = 12;
++ break;
++ }
++
++ if (fmtptr) *fmtptr = fmt;
++
++ return depth;
++}
++
++static int s3c_camif_set_fb_info(camif_cfg_t *cfg, int depth, int fourcc)
++{
++ /* To define v4l2_format used currently */
++ cfg->v2.frmbuf.fmt.width = cfg->target_x;
++ cfg->v2.frmbuf.fmt.height = cfg->target_y;
++ cfg->v2.frmbuf.fmt.field = V4L2_FIELD_NONE;
++ cfg->v2.frmbuf.fmt.pixelformat = fourcc;
++ cfg->v2.frmbuf.fmt.bytesperline = cfg->v2.frmbuf.fmt.width * depth >> 3;
++ cfg->v2.frmbuf.fmt.sizeimage = cfg->v2.frmbuf.fmt.height * cfg->v2.frmbuf.fmt.bytesperline;
++
++ return 0;
++}
++
++static int s3c_camif_convert_type(camif_cfg_t *cfg, int f)
++{
++ int pixfmt;
++ cfg->target_x = cfg->v2.frmbuf.fmt.width;
++ cfg->target_y = cfg->v2.frmbuf.fmt.height;
++
++ s3c_camif_convert_format(cfg->v2.frmbuf.fmt.pixelformat, &pixfmt);
++
++ cfg->dst_fmt = pixfmt;
++
++ return 0;
++}
++
++/*************************************************************************
++ * Control part
++ ************************************************************************/
++static int s3c_camif_start_capture(camif_cfg_t * cfg)
++{
++ int ret = 0;
++
++ cfg->capture_enable = CAMIF_DMA_ON;
++
++ s3c_camif_start_dma(cfg);
++
++ cfg->status = CAMIF_STARTED;
++
++ if (!(cfg->fsm == CAMIF_SET_LAST_INT || cfg->fsm == CAMIF_CONTINUOUS_INT)) {
++ cfg->fsm = CAMIF_DUMMY_INT;
++ cfg->perf.frames = 0;
++ }
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ if (cfg->input_channel == MSDMA_FROM_CODEC)
++ s3c_camif_start_codec_msdma(cfg);
++#endif
++ return ret;
++}
++
++ssize_t s3c_camif_start_preview(camif_cfg_t *cfg)
++{
++ cfg->capture_enable = CAMIF_DMA_ON;
++
++ s3c_camif_start_dma(cfg);
++
++ cfg->status = CAMIF_STARTED;
++ cfg->fsm = CAMIF_1st_INT;
++ cfg->perf.frames = 0;
++
++ return 0;
++}
++
++ssize_t s3c_camif_stop_preview(camif_cfg_t *cfg)
++{
++ cfg->capture_enable = CAMIF_DMA_OFF;
++ cfg->status = CAMIF_STOPPED;
++
++ s3c_camif_stop_dma(cfg);
++
++ cfg->perf.frames = 0;
++
++ return 0;
++}
++
++ssize_t s3c_camif_stop_capture(camif_cfg_t *cfg)
++{
++ cfg->capture_enable = CAMIF_DMA_OFF;
++ cfg->status = CAMIF_STOPPED;
++
++ s3c_camif_stop_dma(cfg);
++
++ cfg->perf.frames = 0;
++
++ return 0;
++}
++
++ssize_t s3c_camif_stop_fimc(camif_cfg_t *cfg)
++{
++ cfg->capture_enable = CAMIF_BOTH_DMA_OFF;
++ cfg->fsm = CAMIF_DUMMY_INT;
++ cfg->perf.frames = 0;
++
++ s3c_camif_stop_dma(cfg);
++
++ return 0;
++}
++
++#if defined(FSM_ON_PREVIEW)
++static void s3c_camif_start_preview_with_codec(camif_cfg_t *cfg)
++{
++ camif_cfg_t *other = (camif_cfg_t *)cfg->other;
++
++ /* Preview Stop */
++ cfg->capture_enable = CAMIF_DMA_OFF;
++ s3c_camif_stop_dma(cfg);
++
++ /* Start Preview and CODEC */
++ cfg->capture_enable =CAMIF_BOTH_DMA_ON;
++
++ s3c_camif_start_dma(cfg);
++ cfg->fsm = CAMIF_1st_INT; /* For Preview */
++
++ if (!other)
++ panic("Unexpected error: other is null\n");
++
++ switch (other->pp_num) {
++ case 4:
++ other->fsm = CAMIF_1st_INT; /* For CODEC */
++ break;
++
++ case 1:
++ other->fsm = CAMIF_Yth_INT;
++ break;
++
++ default:
++ panic("Invalid pingpong number");
++ break;
++ }
++}
++
++static void s3c_camif_auto_restart(camif_cfg_t *cfg)
++{
++ if (cfg->auto_restart)
++ s3c_camif_start_preview_with_codec(cfg);
++}
++#endif
++
++static void s3c_camif_change_mode(camif_cfg_t *cfg, int mode)
++{
++ camif_cis_t *cis = cfg->cis;
++ int res;
++
++ if (mode == SENSOR_MAX) {
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K3AA)
++ res = SENSOR_SXGA;
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K3BA)
++ res = SENSOR_UXGA;
++
++/* 4BA max is UXGA, but we don't have UXGA control values */
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++ res = SENSOR_SVGA;
++#elif defined(CONFIG_VIDEO_APTINA_MT9P012)
++ res = SENSOR_QSXGA_MT9P012;
++#endif
++ } else if (mode == SENSOR_DEFAULT) {
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++ res = SENSOR_SVGA;
++#elif defined(CONFIG_VIDEO_APTINA_MT9P012)
++ res = SENSOR_SXGA_MT9P012;
++#else
++ res = SENSOR_VGA;
++#endif
++ } else
++ res = mode;
++
++ s3c_camif_stop_fimc(cfg);
++
++ switch (res) {
++ case SENSOR_SXGA:
++ printk(KERN_INFO "Resolution changed to SXGA (1280x1024) mode -> 1.3M\n");
++ cis->sensor->driver->command(cis->sensor, SENSOR_SXGA, NULL);
++ cis->source_x = 1280;
++ cis->source_y = 1024;
++ break;
++
++ case SENSOR_UXGA:
++ printk(KERN_INFO "Resolution changed to UXGA (1600x1200) mode -> 2.0M\n");
++ cis->sensor->driver->command(cis->sensor, SENSOR_UXGA, NULL);
++ cis->source_x = 1600;
++ cis->source_y = 1200;
++ break;
++
++ case SENSOR_SVGA:
++ printk(KERN_INFO "Resolution changed to SVGA (800x600) mode\n");
++ cis->sensor->driver->command(cis->sensor, SENSOR_SVGA, NULL);
++ cis->source_x = 800;
++ cis->source_y = 600;
++ break;
++
++ case SENSOR_VGA:
++ printk(KERN_INFO "Resolution changed to VGA (640x480) mode\n");
++ cis->sensor->driver->command(cis->sensor, SENSOR_VGA, NULL);
++ cis->source_x = 640;
++ cis->source_y = 480;
++ break;
++
++ case SENSOR_SXGA_MT9P012:
++ printk(KERN_INFO "Resolution changed to SXGA (1296x972) mode -> 1.3M\n");
++ cis->sensor->driver->command(cis->sensor, SENSOR_SXGA_MT9P012, NULL);
++ cis->source_x = 1296;
++ cis->source_y = 972;
++ break;
++
++ case SENSOR_QSXGA_MT9P012:
++ printk(KERN_INFO "Resolution changed to QSXGA (2592x1944) mode -> 5.0M\n");
++ cis->sensor->driver->command(cis->sensor, SENSOR_QSXGA_MT9P012, NULL);
++ cis->source_x = 2592;
++ cis->source_y = 1944;
++ break;
++ }
++
++ cis->win_hor_ofst = cis->win_hor_ofst2 = 0;
++ cis->win_ver_ofst = cis->win_ver_ofst2 = 0;
++
++ s3c_camif_set_source_format(cis);
++}
++
++static int s3c_camif_check_zoom_range(camif_cfg_t *cfg, int type)
++{
++ switch (type) {
++ case V4L2_CID_ZOOMIN:
++ if (((cfg->sc.modified_src_x - (cfg->cis->win_hor_ofst + \
++ ZOOM_AT_A_TIME_IN_PIXELS + cfg->cis->win_hor_ofst2 + \
++ ZOOM_AT_A_TIME_IN_PIXELS)) / cfg->sc.prehratio) > ZOOM_IN_MAX) {
++ printk(KERN_INFO "Invalid Zoom-in: this zoom-in on preview scaler already comes to the maximum\n");
++ return 0;
++ }
++
++ cfg->sc.zoom_in_cnt++;
++ break;
++
++ case V4L2_CID_ZOOMOUT:
++ if (cfg->sc.zoom_in_cnt > 0) {
++ cfg->sc.zoom_in_cnt--;
++ break;
++ } else {
++ printk(KERN_INFO "Invalid Zoom-out: this zoom-out on preview scaler already comes to the minimum\n");
++ return 0;
++ }
++
++ break;
++
++ default:
++ break;
++ }
++
++ return 1;
++}
++
++static int s3c_camif_restart_preview(camif_cfg_t *cfg)
++{
++ int ret = 0;
++
++ s3c_camif_stop_preview(cfg);
++
++ if (s3c_camif_control_fimc(cfg)) {
++ printk(KERN_ERR "S3C fimc control failed\n");
++ ret = -1;
++ }
++
++ s3c_camif_start_preview(cfg);
++
++ return ret;
++}
++
++static int s3c_camif_send_sensor_command(camif_cfg_t *cfg, unsigned int cmd, int arg)
++{
++ cfg->cis->sensor->driver->command(cfg->cis->sensor, cmd, (void *) arg);
++
++ return 0;
++}
++
++/*************************************************************************
++ * V4L2 part
++ ************************************************************************/
++static int s3c_camif_v4l2_querycap(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_capability *cap = arg;
++
++ strcpy(cap->driver, "S3C FIMC Camera driver");
++ strlcpy(cap->card, cfg->v->name, sizeof(cap->card));
++ sprintf(cap->bus_info, "FIMC AHB Bus");
++
++ cap->version = 0;
++ cap->capabilities = cfg->v->type2;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_g_fbuf(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_framebuffer *fb = arg;
++
++ *fb = cfg->v2.frmbuf;
++
++ fb->base = cfg->v2.frmbuf.base;
++ fb->capability = V4L2_FBUF_CAP_LIST_CLIPPING;
++
++ fb->fmt.pixelformat = cfg->v2.frmbuf.fmt.pixelformat;
++ fb->fmt.width = cfg->v2.frmbuf.fmt.width;
++ fb->fmt.height = cfg->v2.frmbuf.fmt.height;
++ fb->fmt.bytesperline = cfg->v2.frmbuf.fmt.bytesperline;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_s_fbuf(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_framebuffer *fb = arg;
++ int i, depth;
++
++ for (i = 0; i < NUMBER_OF_PREVIEW_FORMATS; i++)
++ if (fimc_preview_formats[i].pixelformat == fb->fmt.pixelformat)
++ break;
++
++ if (i == NUMBER_OF_PREVIEW_FORMATS)
++ return -EINVAL;
++
++ cfg->v2.frmbuf.base = fb->base;
++ cfg->v2.frmbuf.flags = fb->flags;
++ cfg->v2.frmbuf.capability = fb->capability;
++
++ cfg->target_x = fb->fmt.width;
++ cfg->target_y = fb->fmt.height;
++
++ depth = s3c_camif_convert_format(fb->fmt.pixelformat, (int *) &(cfg->dst_fmt));
++ s3c_camif_set_fb_info(cfg, depth, fb->fmt.pixelformat);
++
++ return s3c_camif_control_fimc(cfg);
++}
++
++static int s3c_camif_v4l2_g_fmt(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_format *f = (struct v4l2_format *) arg;
++ int size = sizeof(struct v4l2_pix_format);
++ int ret = -1;
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(&f->fmt.pix, 0, size);
++ memcpy(&f->fmt.pix, &cfg->v2.frmbuf.fmt, size);
++ ret = 0;
++ break;
++
++ default:
++ break;
++ }
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_s_fmt(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_format *f = (struct v4l2_format *) arg;
++ int ret = -1;
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ cfg->v2.frmbuf.fmt = f->fmt.pix;
++ cfg->v2.status |= CAMIF_v4L2_DIRTY;
++ cfg->v2.status &= ~CAMIF_v4L2_DIRTY; /* dummy ? */
++
++ s3c_camif_convert_type(cfg, 1);
++ s3c_camif_control_fimc(cfg);
++ ret = 0;
++ break;
++
++ default:
++ break;
++ }
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_enum_fmt(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_fmtdesc *f = arg;
++ int index = f->index;
++
++ if (index >= NUMBER_OF_CODEC_FORMATS)
++ return -EINVAL;
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ break;
++
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ default:
++ return -EINVAL;
++ }
++
++ memset(f, 0, sizeof(*f));
++ memcpy(f, cfg->v2.fmtdesc + index, sizeof(*f));
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_overlay(camif_cfg_t *cfg, void *arg)
++{
++ int on = *((int *) arg);
++ int ret;
++
++ if (on != 0)
++ ret = s3c_camif_start_preview(cfg);
++ else
++ ret = s3c_camif_stop_preview(cfg);
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_g_ctrl(camif_cfg_t *cfg, void *arg)
++{
++ return 0;
++}
++
++static int s3c_camif_v4l2_s_ctrl(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_control *ctrl = (struct v4l2_control *) arg;
++
++ switch (ctrl->id) {
++ case V4L2_CID_ORIGINAL:
++ case V4L2_CID_ARBITRARY:
++ case V4L2_CID_NEGATIVE:
++ case V4L2_CID_EMBOSSING:
++ case V4L2_CID_ART_FREEZE:
++ case V4L2_CID_SILHOUETTE:
++ cfg->effect = ctrl->value;
++ s3c_camif_change_effect(cfg);
++ break;
++
++ case V4L2_CID_HFLIP:
++ cfg->flip = CAMIF_FLIP_X;
++ s3c_camif_change_flip(cfg);
++ break;
++
++ case V4L2_CID_VFLIP:
++ cfg->flip = CAMIF_FLIP_Y;
++ s3c_camif_change_flip(cfg);
++ break;
++
++ case V4L2_CID_ROTATE_180:
++ cfg->flip = CAMIF_FLIP_MIRROR;
++ s3c_camif_change_flip(cfg);
++ break;
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ case V4L2_CID_ROTATE_90:
++ cfg->flip = CAMIF_ROTATE_90;
++ s3c_camif_change_flip(cfg);
++ break;
++
++ case V4L2_CID_ROTATE_270:
++ cfg->flip = CAMIF_FLIP_ROTATE_270;
++ s3c_camif_change_flip(cfg);
++ break;
++#endif
++
++ case V4L2_CID_ROTATE_BYPASS:
++ cfg->flip = CAMIF_FLIP;
++ s3c_camif_change_flip(cfg);
++ break;
++
++ case V4L2_CID_ZOOMIN:
++ if (s3c_camif_check_zoom_range(cfg, ctrl->id)) {
++ cfg->cis->win_hor_ofst += ZOOM_AT_A_TIME_IN_PIXELS;
++ cfg->cis->win_ver_ofst += ZOOM_AT_A_TIME_IN_PIXELS;
++ cfg->cis->win_hor_ofst2 += ZOOM_AT_A_TIME_IN_PIXELS;
++ cfg->cis->win_ver_ofst2 += ZOOM_AT_A_TIME_IN_PIXELS;
++
++ s3c_camif_restart_preview(cfg);
++ }
++
++ break;
++
++ case V4L2_CID_ZOOMOUT:
++ if (s3c_camif_check_zoom_range(cfg, ctrl->id)) {
++ cfg->cis->win_hor_ofst -= ZOOM_AT_A_TIME_IN_PIXELS;
++ cfg->cis->win_ver_ofst -= ZOOM_AT_A_TIME_IN_PIXELS;
++ cfg->cis->win_hor_ofst2 -= ZOOM_AT_A_TIME_IN_PIXELS;
++ cfg->cis->win_ver_ofst2 -= ZOOM_AT_A_TIME_IN_PIXELS;
++
++ s3c_camif_restart_preview(cfg);
++ }
++
++ break;
++
++ case V4L2_CID_CONTRAST:
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ s3c_camif_send_sensor_command(cfg, SENSOR_WB, ctrl->value);
++ break;
++
++ default:
++ printk(KERN_ERR "Invalid control id: %d\n", ctrl->id);
++ return -1;
++ }
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_streamon(camif_cfg_t *cfg, void *arg)
++{
++ int ret = 0;
++
++ ret = s3c_camif_start_capture(cfg);
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_streamoff(camif_cfg_t *cfg, void *arg)
++{
++ int ret = 0;
++
++ cfg->cis->status &= ~C_WORKING;
++
++ s3c_camif_stop_capture(cfg);
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_g_input(camif_cfg_t *cfg, void *arg)
++{
++ unsigned int index = *((int *) arg);
++
++ index = cfg->v2.input->index;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_s_input(camif_cfg_t *cfg, unsigned int index)
++{
++ int ret = -1;
++
++ if (index >= NUMBER_OF_INPUTS)
++ ret = -1;
++ else {
++ cfg->v2.input = &fimc_inputs[index];
++
++ if (cfg->v2.input->type == V4L2_INPUT_TYPE_MSDMA) {
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ cfg->input_channel = MSDMA_FROM_PREVIEW;
++ ret = 0;
++ } else if (cfg->dma_type & CAMIF_CODEC) {
++ cfg->input_channel = MSDMA_FROM_CODEC;
++ ret = 0;
++ }
++ } else {
++ cfg->input_channel = CAMERA_INPUT;
++ ret = 0;
++ }
++ }
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_g_output(camif_cfg_t *cfg, void *arg)
++{
++ unsigned int index = *((int *) arg);
++
++ index = cfg->v2.output->index;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_s_output(camif_cfg_t *cfg, unsigned int index)
++{
++ if (index >= NUMBER_OF_OUTPUTS)
++ return -EINVAL;
++ else {
++ cfg->v2.output = (struct v4l2_output *) &fimc_outputs[index];
++ return 0;
++ }
++}
++
++static int s3c_camif_v4l2_enum_input(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_input *i = arg;
++
++ if (i->index >= NUMBER_OF_INPUTS)
++ return -EINVAL;
++
++ memcpy(i, &fimc_inputs[i->index], sizeof(struct v4l2_input));
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_enum_output(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_output *i = arg;
++
++ if ((i->index) >= NUMBER_OF_OUTPUTS)
++ return -EINVAL;
++
++ memcpy(i, &fimc_outputs[i->index], sizeof(struct v4l2_output));
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_reqbufs(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_requestbuffers *req = arg;
++
++ if (req->memory != V4L2_MEMORY_MMAP) {
++ printk(KERN_ERR "Only V4L2_MEMORY_MMAP capture is supported\n");
++ return -EINVAL;
++ }
++
++ /* control user input */
++ if (req->count > 2)
++ req->count = 4;
++ else if (req->count > 1)
++ req->count = 2;
++ else
++ req->count = 1;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_querybuf(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_buffer *buf = arg;
++
++ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && buf->memory != V4L2_MEMORY_MMAP)
++ return -1;
++
++ buf->length = cfg->buffer_size;
++ buf->m.offset = buf->length * buf->index;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_qbuf(camif_cfg_t *cfg, void *arg)
++{
++ return 0;
++}
++
++static int s3c_camif_v4l2_dqbuf(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_buffer *buf = arg;
++
++ buf->index = cfg->cur_frame_num % cfg->pp_num;
++
++ return 0;
++}
++
++/*
++ * S3C specific
++ */
++static int s3c_camif_v4l2_s_msdma(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_msdma_format *f = arg;
++ int ret = -1;
++
++ switch(f->input_path) {
++ case V4L2_MSDMA_PREVIEW:
++ cfg->cis->user--; /* CIS will be replaced with a CIS for MSDMA */
++
++ cfg->cis = &msdma_input;
++ cfg->cis->user++;
++ cfg->input_channel = MSDMA_FROM_PREVIEW;
++ break;
++
++ case V4L2_MSDMA_CODEC:
++ cfg->cis->user--; /* CIS will be replaced with a CIS for MSDMA */
++
++ cfg->cis = &msdma_input;
++ cfg->cis->user++;
++ cfg->input_channel = MSDMA_FROM_CODEC;
++ break;
++
++ default:
++ cfg->input_channel = CAMERA_INPUT;
++ break;
++ }
++
++ cfg->cis->source_x = f->width;
++ cfg->cis->source_y = f->height;
++
++ s3c_camif_convert_format(f->pixelformat, (int *) &cfg->src_fmt);
++
++ cfg->cis->win_hor_ofst = 0;
++ cfg->cis->win_ver_ofst = 0;
++ cfg->cis->win_hor_ofst2 = 0;
++ cfg->cis->win_ver_ofst2 = 0;
++
++ ret = s3c_camif_control_fimc(cfg);
++
++ switch(f->input_path) {
++ case V4L2_MSDMA_PREVIEW:
++ ret = s3c_camif_start_preview(cfg);
++ break;
++
++ case V4L2_MSDMA_CODEC:
++ ret = s3c_camif_start_capture(cfg);
++ break;
++
++ default:
++ break;
++
++ }
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_msdma_start(camif_cfg_t *cfg, void *arg)
++{
++ if (cfg->input_channel == MSDMA_FROM_PREVIEW) {
++ cfg->msdma_status = 1;
++ s3c_camif_start_preview_msdma(cfg);
++ }
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_msdma_stop(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_msdma_format *f = arg;
++ int ret = -1;
++
++ cfg->cis->status &= ~C_WORKING;
++ cfg->msdma_status = 0;
++
++ switch(f->input_path) {
++ case V4L2_MSDMA_PREVIEW:
++ ret = s3c_camif_stop_preview(cfg);
++ break;
++
++ case V4L2_MSDMA_CODEC:
++ ret = s3c_camif_stop_capture(cfg);
++ break;
++
++ default:
++ break;
++ }
++
++ return ret;
++}
++
++static int s3c_camif_v4l2_camera_start(camif_cfg_t *cfg, void *arg)
++{
++ return 0;
++}
++
++static int s3c_camif_v4l2_camera_stop(camif_cfg_t *cfg, void *arg)
++{
++ return 0;
++}
++
++static int s3c_camif_v4l2_cropcap(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_cropcap *cap = arg;
++
++ if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY)
++ return -EINVAL;
++
++ /* crop limitations */
++ cfg->v2.crop_bounds.left = 0;
++ cfg->v2.crop_bounds.top = 0;
++ cfg->v2.crop_bounds.width = cfg->cis->source_x;
++ cfg->v2.crop_bounds.height = cfg->cis->source_y;
++
++ /* crop default values */
++ cfg->v2.crop_defrect.left = (cfg->cis->source_x - CROP_DEFAULT_WIDTH) / 2;
++ cfg->v2.crop_defrect.top = (cfg->cis->source_y - CROP_DEFAULT_HEIGHT) / 2;
++ cfg->v2.crop_defrect.width = CROP_DEFAULT_WIDTH;
++ cfg->v2.crop_defrect.height = CROP_DEFAULT_HEIGHT;
++
++ cap->bounds = cfg->v2.crop_bounds;
++ cap->defrect = cfg->v2.crop_defrect;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_g_crop(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_crop *crop = arg;
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY)
++ return -EINVAL;
++
++ crop->c = cfg->v2.crop_current;
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_s_crop(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_crop *crop = arg;
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY)
++ return -EINVAL;
++
++ if (crop->c.height < 0)
++ return -EINVAL;
++
++ if (crop->c.width < 0)
++ return -EINVAL;
++
++ if ((crop->c.left + crop->c.width > cfg->cis->source_x) || \
++ (crop->c.top + crop->c.height > cfg->cis->source_y))
++ return -EINVAL;
++
++ cfg->v2.crop_current = crop->c;
++
++ cfg->cis->win_hor_ofst = (cfg->cis->source_x - crop->c.width) / 2;
++ cfg->cis->win_ver_ofst = (cfg->cis->source_y - crop->c.height) / 2;
++
++ cfg->cis->win_hor_ofst2 = cfg->cis->win_hor_ofst;
++ cfg->cis->win_ver_ofst2 = cfg->cis->win_ver_ofst;
++
++ s3c_camif_restart_preview(cfg);
++
++ return 0;
++}
++
++static int s3c_camif_v4l2_s_parm(camif_cfg_t *cfg, void *arg)
++{
++ struct v4l2_streamparm *sp = arg;
++
++ if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++
++#if defined(CONFIG_VIDEO_APTINA_MT9P012)
++ if (cfg->dma_type == CAMIF_CODEC && cfg->target_x == 2592 && cfg->target_y == 1944) {
++ printk("scalerbypass selected\n");
++ cfg->sc.scalerbypass = 1;
++ }
++#endif
++ if (sp->parm.capture.capturemode == V4L2_MODE_HIGHQUALITY) {
++ s3c_camif_change_mode(cfg, SENSOR_MAX);
++ s3c_camif_control_fimc(cfg);
++ } else {
++ s3c_camif_change_mode(cfg, SENSOR_DEFAULT);
++ s3c_camif_control_fimc(cfg);
++ }
++
++ return 0;
++}
++
++/*************************************************************************
++ * Interrupt part
++ ************************************************************************/
++#if defined(FSM_ON_CODEC) && !defined(USE_LAST_IRQ)
++int s3c_camif_do_fsm_codec(camif_cfg_t *cfg)
++{
++ int ret;
++
++ cfg->perf.frames++;
++
++ if ((cfg->fsm == CAMIF_DUMMY_INT) && (cfg->perf.frames > CAMIF_CAPTURE_SKIP_FRAMES))
++ cfg->fsm = CAMIF_NORMAL_INT;
++
++ switch (cfg->fsm) {
++ case CAMIF_DUMMY_INT:
++ DPRINTK(KERN_INFO "CAMIF_DUMMY_INT: %d\n", cfg->perf.frames);
++ cfg->status = CAMIF_STARTED;
++ cfg->fsm = CAMIF_DUMMY_INT;
++ ret = INSTANT_SKIP;
++ break;
++
++ case CAMIF_NORMAL_INT:
++ DPRINTK(KERN_INFO "CAMIF_NORMAL_INT: %d\n", cfg->perf.frames);
++ cfg->status = CAMIF_INT_HAPPEN;
++ cfg->fsm = CAMIF_CONTINUOUS_INT;
++ ret = INSTANT_GO;
++ break;
++
++ case CAMIF_CONTINUOUS_INT:
++ DPRINTK(KERN_INFO "CAMIF_CONTINUOS_INT: %d\n", cfg->perf.frames);
++ cfg->status = CAMIF_INT_HAPPEN;
++ cfg->fsm = CAMIF_CONTINUOUS_INT;
++ ret = INSTANT_GO;
++ break;
++
++ default:
++ printk(KERN_INFO "Unexpected INT: %d\n", cfg->fsm);
++ ret = INSTANT_SKIP;
++ break;
++ }
++
++ return ret;
++}
++#endif
++
++#if defined(FSM_ON_CODEC) && defined(USE_LAST_IRQ)
++int s3c_camif_do_fsm_codec_lastirq(camif_cfg_t *cfg)
++{
++ int ret;
++
++ cfg->perf.frames++;
++
++ if ((cfg->fsm == CAMIF_DUMMY_INT) && (cfg->perf.frames > (CAMIF_CAPTURE_SKIP_FRAMES - 2)))
++ cfg->fsm = CAMIF_SET_LAST_INT;
++
++ switch (cfg->fsm) {
++ case CAMIF_DUMMY_INT:
++ DPRINTK(KERN_INFO "CAMIF_DUMMY_INT: %d\n", cfg->perf.frames);
++ cfg->status = CAMIF_STARTED;
++ cfg->fsm = CAMIF_DUMMY_INT;
++ ret = INSTANT_SKIP;
++ break;
++
++ case CAMIF_SET_LAST_INT:
++ DPRINTK(KERN_INFO "CAMIF_SET_LAST_INT: %d\n", cfg->perf.frames);
++ s3c_camif_enable_lastirq(cfg);
++
++/* in 64xx, lastirq is not auto cleared. */
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ s3c_camif_disable_lastirq(cfg);
++#endif
++ cfg->status = CAMIF_INT_HAPPEN;
++ cfg->fsm = CAMIF_STOP_CAPTURE;
++ ret = INSTANT_SKIP;
++ break;
++
++ case CAMIF_STOP_CAPTURE:
++ DPRINTK(KERN_INFO "CAMIF_STOP_CAPTURE: %d\n", cfg->perf.frames);
++ cfg->capture_enable = CAMIF_DMA_OFF;
++ s3c_camif_stop_dma(cfg);
++ cfg->fsm = CAMIF_LAST_IRQ;
++ ret = INSTANT_SKIP;
++ break;
++
++ case CAMIF_LAST_IRQ:
++ DPRINTK(KERN_INFO "CAMIF_LAST_IRQ: %d\n", cfg->perf.frames);
++ cfg->fsm = CAMIF_SET_LAST_INT;
++ cfg->status = CAMIF_INT_HAPPEN;
++ ret = INSTANT_GO;
++ break;
++
++ default:
++ printk(KERN_INFO "Unexpected INT: %d\n", cfg->fsm);
++ ret = INSTANT_SKIP;
++ break;
++ }
++
++ return ret;
++}
++#endif
++
++#if defined(FSM_ON_PREVIEW)
++static int s3c_camif_do_lastirq_preview(camif_cfg_t *cfg)
++{
++ int ret = 0;
++
++ cfg->perf.frames++;
++
++ if (cfg->fsm == CAMIF_NORMAL_INT) {
++ if (cfg->perf.frames % CHECK_FREQ == 0)
++ ret = s3c_camif_check_global_status(cfg);
++ }
++
++ if (ret > 0)
++ cfg->fsm = CAMIF_Xth_INT;
++
++ switch (cfg->fsm) {
++ case CAMIF_1st_INT:
++ DPRINTK(KERN_INFO "CAMIF_1st_INT INT\n");
++ cfg->fsm = CAMIF_NORMAL_INT;
++ ret = INSTANT_SKIP;
++ break;
++
++ case CAMIF_NORMAL_INT:
++ DPRINTK(KERN_INFO "CAMIF_NORMAL_INT\n");
++ cfg->status = CAMIF_INT_HAPPEN;
++ cfg->fsm = CAMIF_NORMAL_INT;
++ ret = INSTANT_GO;
++ break;
++
++ case CAMIF_Xth_INT:
++ DPRINTK(KERN_INFO "CAMIF_Xth_INT\n");
++ s3c_camif_enable_lastirq(cfg);
++ cfg->status = CAMIF_INT_HAPPEN;
++ cfg->fsm = CAMIF_Yth_INT;
++ ret = INSTANT_GO;
++ break;
++
++ case CAMIF_Yth_INT:
++ DPRINTK(KERN_INFO "CAMIF_Yth_INT\n");
++ s3c_camif_disable_lastirq(cfg);
++ cfg->capture_enable = CAMIF_DMA_OFF;
++ cfg->status = CAMIF_INT_HAPPEN;
++ s3c_camif_stop_dma(cfg);
++ cfg->fsm = CAMIF_Zth_INT;
++ ret = INSTANT_GO;
++ break;
++
++ case CAMIF_Zth_INT:
++ DPRINTK(KERN_INFO "CAMIF_Zth_INT\n");
++ cfg->fsm = CAMIF_DUMMY_INT;
++ cfg->status = CAMIF_INT_HAPPEN;
++ ret = INSTANT_GO;
++ s3c_camif_auto_restart(cfg);
++ break;
++
++ case CAMIF_DUMMY_INT:
++ DPRINTK(KERN_INFO "CAMIF_DUMMY_INT\n");
++ cfg->status = CAMIF_STOPPED;
++ ret = INSTANT_SKIP;
++ break;
++
++ default:
++ printk(KERN_INFO "Unexpected INT %d\n", cfg->fsm);
++ ret = INSTANT_SKIP;
++ break;
++ }
++
++ return ret;
++}
++#endif
++
++static irqreturn_t s3c_camif_do_irq_codec(int irq, void *dev_id)
++{
++ camif_cfg_t *cfg = (camif_cfg_t *) dev_id;
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ gpio_set_value(S3C_GPN15, 1);
++#endif
++ s3c_camif_clear_irq(irq);
++ s3c_camif_get_fifo_status(cfg);
++ s3c_camif_get_frame_num(cfg);
++
++#if defined(FSM_ON_CODEC) && !defined(USE_LAST_IRQ)
++ if (s3c_camif_do_fsm_codec(cfg) == INSTANT_SKIP)
++ return IRQ_HANDLED;
++#endif
++
++#if defined(FSM_ON_CODEC) && defined(USE_LAST_IRQ)
++ if (s3c_camif_do_fsm_codec_lastirq(cfg) == INSTANT_SKIP)
++ return IRQ_HANDLED;
++#endif
++ wake_up_interruptible(&cfg->waitq);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t s3c_camif_do_irq_preview(int irq, void *dev_id)
++{
++ camif_cfg_t *cfg = (camif_cfg_t *) dev_id;
++
++ s3c_camif_clear_irq(irq);
++ s3c_camif_get_fifo_status(cfg);
++ s3c_camif_get_frame_num(cfg);
++ wake_up_interruptible(&cfg->waitq);
++
++#if defined(FSM_ON_PREVIEW)
++ if (s3c_camif_do_lastirq_preview(cfg) == INSTANT_SKIP)
++ return IRQ_HANDLED;
++
++ wake_up_interruptible(&cfg->waitq);
++#endif
++ cfg->status = CAMIF_INT_HAPPEN;
++
++ return IRQ_HANDLED;
++}
++
++static void s3c_camif_release_irq(camif_cfg_t * cfg)
++{
++ disable_irq(cfg->irq);
++ free_irq(cfg->irq, cfg);
++}
++
++static int s3c_camif_request_irq(camif_cfg_t * cfg)
++{
++ int ret = 0;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ if ((ret = request_irq(cfg->irq, s3c_camif_do_irq_codec, IRQF_DISABLED, cfg->shortname, cfg)))
++ printk(KERN_ERR "Request irq (CAM_C) failed\n");
++ else
++ printk(KERN_INFO "Request irq %d for codec\n", cfg->irq);
++ }
++
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ if ((ret = request_irq(cfg->irq, s3c_camif_do_irq_preview, IRQF_DISABLED, cfg->shortname, cfg)))
++ printk("Request_irq (CAM_P) failed\n");
++ else
++ printk(KERN_INFO "Request irq %d for preview\n", cfg->irq);
++ }
++
++ return 0;
++}
++
++/*************************************************************************
++ * Standard file operations part
++ ************************************************************************/
++int s3c_camif_ioctl(struct inode *inode, struct file *file, unsigned int cmd, void *arg)
++{
++ camif_cfg_t *cfg = file->private_data;
++ int ret = -1;
++
++ switch (cmd) {
++ case VIDIOC_QUERYCAP:
++ ret = s3c_camif_v4l2_querycap(cfg, arg);
++ break;
++
++ case VIDIOC_G_FBUF:
++ ret = s3c_camif_v4l2_g_fbuf(cfg, arg);
++ break;
++
++ case VIDIOC_S_FBUF:
++ ret = s3c_camif_v4l2_s_fbuf(cfg, arg);
++ break;
++
++ case VIDIOC_G_FMT:
++ ret = s3c_camif_v4l2_g_fmt(cfg, arg);
++ break;
++
++ case VIDIOC_S_FMT:
++ ret = s3c_camif_v4l2_s_fmt(cfg, arg);
++ break;
++
++ case VIDIOC_ENUM_FMT:
++ ret = s3c_camif_v4l2_enum_fmt(cfg, arg);
++ break;
++
++ case VIDIOC_OVERLAY:
++ ret = s3c_camif_v4l2_overlay(cfg, arg);
++ break;
++
++ case VIDIOC_S_CTRL:
++ ret = s3c_camif_v4l2_s_ctrl(cfg, arg);
++ break;
++
++ case VIDIOC_G_CTRL:
++ ret = s3c_camif_v4l2_g_ctrl(cfg, arg);
++ break;
++
++ case VIDIOC_STREAMON:
++ ret = s3c_camif_v4l2_streamon(cfg, arg);
++ break;
++
++ case VIDIOC_STREAMOFF:
++ ret = s3c_camif_v4l2_streamoff(cfg, arg);
++ break;
++
++ case VIDIOC_G_INPUT:
++ ret = s3c_camif_v4l2_g_input(cfg, arg);
++ break;
++
++ case VIDIOC_S_INPUT:
++ ret = s3c_camif_v4l2_s_input(cfg, *((int *) arg));
++ break;
++
++ case VIDIOC_G_OUTPUT:
++ ret = s3c_camif_v4l2_g_output(cfg, arg);
++ break;
++
++ case VIDIOC_S_OUTPUT:
++ ret = s3c_camif_v4l2_s_output(cfg, *((int *) arg));
++ break;
++
++ case VIDIOC_ENUMINPUT:
++ ret = s3c_camif_v4l2_enum_input(cfg, arg);
++ break;
++
++ case VIDIOC_ENUMOUTPUT:
++ ret = s3c_camif_v4l2_enum_output(cfg, arg);
++ break;
++
++ case VIDIOC_REQBUFS:
++ ret = s3c_camif_v4l2_reqbufs(cfg, arg);
++ break;
++
++ case VIDIOC_QUERYBUF:
++ ret = s3c_camif_v4l2_querybuf(cfg, arg);
++ break;
++
++ case VIDIOC_QBUF:
++ ret = s3c_camif_v4l2_qbuf(cfg, arg);
++ break;
++
++ case VIDIOC_DQBUF:
++ ret = s3c_camif_v4l2_dqbuf(cfg, arg);
++ break;
++
++ case VIDIOC_S_MSDMA:
++ ret = s3c_camif_v4l2_s_msdma(cfg, arg);
++ break;
++
++ case VIDIOC_MSDMA_START:
++ ret = s3c_camif_v4l2_msdma_start(cfg, arg);
++ break;
++
++ case VIDIOC_MSDMA_STOP:
++ ret = s3c_camif_v4l2_msdma_stop(cfg, arg);
++ break;
++
++ case VIDIOC_S_CAMERA_START:
++ ret = s3c_camif_v4l2_camera_start(cfg, arg);
++ break;
++
++ case VIDIOC_S_CAMERA_STOP:
++ ret = s3c_camif_v4l2_camera_stop(cfg, arg);
++ break;
++
++ case VIDIOC_CROPCAP:
++ ret = s3c_camif_v4l2_cropcap(cfg, arg);
++ break;
++
++ case VIDIOC_G_CROP:
++ ret = s3c_camif_v4l2_g_crop(cfg, arg);
++ break;
++
++ case VIDIOC_S_CROP:
++ ret = s3c_camif_v4l2_s_crop(cfg, arg);
++ break;
++
++ case VIDIOC_S_PARM:
++ ret = s3c_camif_v4l2_s_parm(cfg, arg);
++ break;
++
++ default: /* For v4l compatability */
++ v4l_compat_translate_ioctl(inode, file, cmd, arg, s3c_camif_ioctl);
++ break;
++ } /* End of Switch */
++
++ return ret;
++}
++
++int s3c_camif_open(struct inode *inode, struct file *file)
++{
++ int err;
++ camif_cfg_t *cfg = s3c_camif_get_fimc_object(MINOR(inode->i_rdev));
++
++ if (!cfg->cis) {
++ printk(KERN_ERR "An object for a CIS is missing\n");
++ printk(KERN_ERR "Using msdma_input as a default CIS data structure\n");
++ cfg->cis = &msdma_input;
++
++ /* global lock for both Codec and Preview */
++ sema_init((struct semaphore *) &cfg->cis->lock, 1);
++ cfg->cis->status |= P_NOT_WORKING;
++ }
++
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ if (cfg->dma_type & CAMIF_PREVIEW)
++ cfg->cis->status &= ~P_NOT_WORKING;
++
++ up((struct semaphore *) &cfg->cis->lock);
++ }
++
++ err = video_exclusive_open(inode, file);
++ cfg->cis->user++;
++ cfg->status = CAMIF_STOPPED;
++
++ if (err < 0)
++ return err;
++
++ if (file->f_flags & O_NONCAP) {
++ printk(KERN_ERR "Don't support non-capturing open\n");
++ return 0;
++ }
++
++ file->private_data = cfg;
++
++ s3c_camif_init_sensor(cfg);
++
++ return 0;
++}
++
++int s3c_camif_release(struct inode *inode, struct file *file)
++{
++ camif_cfg_t *cfg = s3c_camif_get_fimc_object(MINOR(inode->i_rdev));
++
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ cfg->cis->status &= ~PWANT2START;
++ cfg->cis->status |= P_NOT_WORKING;
++ s3c_camif_stop_preview(cfg);
++ up((struct semaphore *) &cfg->cis->lock);
++ } else {
++ cfg->cis->status &= ~CWANT2START;
++ s3c_camif_stop_capture(cfg);
++ }
++
++ video_exclusive_release(inode, file);
++
++ if (cfg->cis->sensor == NULL)
++ DPRINTK("A CIS sensor for MSDMA has been used\n");
++ else
++ cfg->cis->sensor->driver->command(cfg->cis->sensor, USER_EXIT, NULL);
++
++ cfg->cis->user--;
++ cfg->status = CAMIF_STOPPED;
++
++ return 0;
++}
++
++ssize_t s3c_camif_read(struct file * file, char *buf, size_t count, loff_t * pos)
++{
++ camif_cfg_t *cfg = NULL;
++ size_t end;
++
++ cfg = s3c_camif_get_fimc_object(MINOR(file->f_dentry->d_inode->i_rdev));
++
++#if defined(FSM_ON_PREVIEW)
++ if (cfg->dma_type == CAMIF_PREVIEW) {
++ if (wait_event_interruptible(cfg->waitq, cfg->status == CAMIF_INT_HAPPEN))
++ return -ERESTARTSYS;
++
++ cfg->status = CAMIF_STOPPED;
++ }
++#endif
++
++#if defined(FSM_ON_CODEC)
++ if (cfg->dma_type == CAMIF_CODEC) {
++ if (wait_event_interruptible(cfg->waitq, cfg->status == CAMIF_INT_HAPPEN))
++ return -ERESTARTSYS;
++
++ cfg->status = CAMIF_STOPPED;
++ }
++#endif
++ end = min_t(size_t, cfg->pp_totalsize / cfg->pp_num, count);
++
++ if (copy_to_user(buf, s3c_camif_get_frame(cfg), end))
++ return -EFAULT;
++
++ return end;
++}
++
++ssize_t s3c_camif_write(struct file * f, const char *b, size_t c, loff_t * offset)
++{
++ camif_cfg_t *cfg;
++ int ret = 0;
++
++ cfg = s3c_camif_get_fimc_object(MINOR(f->f_dentry->d_inode->i_rdev));
++
++ switch (*b) {
++ case 'O':
++ if (cfg->dma_type & CAMIF_PREVIEW)
++ s3c_camif_start_preview(cfg);
++ else {
++ ret = s3c_camif_start_capture(cfg);
++
++ if (ret < 0)
++ ret = 1;
++ }
++
++ break;
++
++ case 'X':
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ s3c_camif_stop_preview(cfg);
++ cfg->cis->status |= P_NOT_WORKING;
++ } else {
++ cfg->cis->status &= ~C_WORKING;
++ s3c_camif_stop_capture(cfg);
++ }
++
++ break;
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ case 'P':
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ s3c_camif_start_preview(cfg);
++ s3c_camif_do_postprocess(cfg);
++ return 0;
++ } else
++ return -EFAULT;
++#endif
++ default:
++ panic("s3c_camera_driver.c: s3c_camif_write() - Unexpected Parameter\n");
++ }
++
++ return ret;
++}
++
++int s3c_camif_mmap(struct file* filp, struct vm_area_struct *vma)
++{
++ camif_cfg_t *cfg = filp->private_data;
++
++ unsigned long pageFrameNo;
++ unsigned long size = vma->vm_end - vma->vm_start;
++ unsigned long total_size;
++
++ if (cfg->dma_type == CAMIF_PREVIEW)
++ total_size = RGB_MEM;
++ else
++ total_size = YUV_MEM;
++
++ /* page frame number of the address for a source RGB frame to be stored at. */
++ pageFrameNo = __phys_to_pfn(cfg->pp_phys_buf);
++
++ if (size > total_size) {
++ printk(KERN_ERR "The size of RGB_MEM mapping is too big\n");
++ return -EINVAL;
++ }
++
++ if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) {
++ printk(KERN_ERR "Writable RGB_MEM mapping must be shared\n");
++ return -EINVAL;
++ }
++
++ if (remap_pfn_range(vma, vma->vm_start, pageFrameNo + vma->vm_pgoff, size, vma->vm_page_prot))
++ return -EINVAL;
++
++ return 0;
++}
++
++static unsigned int s3c_camif_poll(struct file *file, poll_table *wait)
++{
++ unsigned int mask = 0;
++ camif_cfg_t *cfg = file->private_data;
++
++ poll_wait(file, &cfg->waitq, wait);
++
++ if (cfg->status == CAMIF_INT_HAPPEN)
++ mask = POLLIN | POLLRDNORM;
++
++ cfg->status = CAMIF_STOPPED;
++
++ return mask;
++}
++
++struct file_operations camif_c_fops = {
++ .owner = THIS_MODULE,
++ .open = s3c_camif_open,
++ .release = s3c_camif_release,
++ .ioctl = s3c_camif_ioctl,
++ .read = s3c_camif_read,
++ .write = s3c_camif_write,
++ .mmap = s3c_camif_mmap,
++ .poll = s3c_camif_poll,
++};
++
++struct file_operations camif_p_fops = {
++ .owner = THIS_MODULE,
++ .open = s3c_camif_open,
++ .release = s3c_camif_release,
++ .ioctl = s3c_camif_ioctl,
++ .read = s3c_camif_read,
++ .write = s3c_camif_write,
++ .mmap = s3c_camif_mmap,
++ .poll = s3c_camif_poll,
++};
++
++/*************************************************************************
++ * Templates for V4L2
++ ************************************************************************/
++void camif_vdev_release (struct video_device *vdev) {
++ kfree(vdev);
++}
++
++struct video_device codec_template = {
++ .name = CODEC_DEV_NAME,
++ .type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES,
++ .type2 = V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
++ .fops = &camif_c_fops,
++ .release = camif_vdev_release,
++ .minor = CODEC_MINOR,
++};
++
++struct video_device preview_template = {
++ .name = PREVIEW_DEV_NAME,
++ .type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES,
++ .type2 = V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING,
++ .fops = &camif_p_fops,
++ .release = camif_vdev_release,
++ .minor = PREVIEW_MINOR,
++};
++
++/*************************************************************************
++ * Initialize part
++ ************************************************************************/
++void s3c_camif_init_sensor(camif_cfg_t *cfg)
++{
++ camif_cis_t *cis = cfg->cis;
++ camif_cis_t *initialized_cis;
++
++ if (!cis->sensor) {
++ initialized_cis = (camif_cis_t *) get_initialized_cis();
++
++ if (initialized_cis == NULL) {
++ printk(KERN_ERR "An I2C client for CIS sensor isn't registered\n");
++ return;
++ }
++
++ cis = cfg->cis = initialized_cis;
++ cfg->input_channel = 0;
++ cfg->cis->user++;
++ }
++
++ if (!cis->init_sensor) {
++ cis->sensor->driver->command(cis->sensor, SENSOR_INIT, NULL);
++ cis->init_sensor = 1;
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K3BA)
++ cis->sensor->driver->command(cis->sensor, SENSOR_VGA, NULL);
++ cis->source_x = 640;
++ cis->source_y = 480;
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++ cis->sensor->driver->command(cis->sensor, SENSOR_SVGA, NULL);
++ cis->source_x = 800;
++ cis->source_y = 600;
++#endif
++ }
++
++ cis->sensor->driver->command(cis->sensor, USER_ADD, NULL);
++}
++
++static int s3c_camif_init_preview(camif_cfg_t * cfg)
++{
++ cfg->target_x = PREVIEW_DEFAULT_WIDTH;
++ cfg->target_y = PREVIEW_DEFAULT_HEIGHT;
++ cfg->pp_num = PREVIEW_DEFAULT_PPNUM;
++ cfg->dma_type = CAMIF_PREVIEW;
++ cfg->input_channel = CAMERA_INPUT;
++ cfg->src_fmt = CAMIF_YCBCR422;
++ cfg->output_channel = CAMIF_OUT_PP;
++ cfg->dst_fmt = CAMIF_RGB16;
++ cfg->flip = CAMIF_FLIP_Y;
++ cfg->v = &preview_template;
++
++ init_MUTEX((struct semaphore *) &cfg->v->lock);
++ init_waitqueue_head(&cfg->waitq);
++
++ cfg->status = CAMIF_STOPPED;
++
++ /* To get the handle of CODEC */
++ cfg->other = s3c_camif_get_fimc_object(CODEC_MINOR);
++
++ return cfg->status;
++}
++
++static int s3c_camif_init_codec(camif_cfg_t * cfg)
++{
++ cfg->target_x = CODEC_DEFAULT_WIDTH;
++ cfg->target_y = CODEC_DEFAULT_HEIGHT;
++ cfg->pp_num = CODEC_DEFAULT_PPNUM;
++ cfg->dma_type = CAMIF_CODEC;
++ cfg->src_fmt = CAMIF_YCBCR422;
++ cfg->input_channel = CAMERA_INPUT;
++ cfg->dst_fmt = CAMIF_YCBCR420;
++ cfg->output_channel = CAMIF_OUT_PP;
++ cfg->flip = CAMIF_FLIP_X;
++ cfg->v = &codec_template;
++
++ init_MUTEX((struct semaphore *) &cfg->v->lock);
++
++ init_waitqueue_head(&cfg->waitq);
++
++ cfg->status = CAMIF_STOPPED;
++
++ /* To get the handle of PREVIEW */
++ cfg->other = s3c_camif_get_fimc_object(PREVIEW_MINOR);
++
++ return cfg->status;
++}
++
++static int s3c_camif_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ camif_cfg_t *codec, *preview;
++ int ret = 0;
++
++ /* Initialize fimc objects */
++ codec = s3c_camif_get_fimc_object(CODEC_MINOR);
++ preview = s3c_camif_get_fimc_object(PREVIEW_MINOR);
++
++ memset(codec, 0, sizeof(camif_cfg_t));
++ memset(preview, 0, sizeof(camif_cfg_t));
++
++ /* Set the fimc name */
++ strcpy(codec->shortname, CODEC_DEV_NAME);
++ strcpy(preview->shortname, PREVIEW_DEV_NAME);
++
++ /* get resource for io memory */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (!res) {
++ printk("Failed to get io memory region resouce.\n");
++ return -1;
++ }
++
++ /* request mem region */
++ res = request_mem_region(res->start, res->end - res->start + 1, pdev->name);
++
++ if (!res) {
++ printk("Failed to request io memory region.\n");
++ return -1;
++ }
++
++ /* ioremap for register block */
++ codec->regs = preview->regs = ioremap(res->start, res->end - res->start + 1);
++
++ if (codec->regs == NULL) {
++ printk(KERN_ERR "Failed to remap register block\n");
++ return -1;
++ }
++
++ /* ioremap for reserved memory */
++ codec->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVED_MEM);
++ codec->pp_virt_buf = ioremap_nocache(codec->pp_phys_buf, YUV_MEM);
++
++ preview->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVED_MEM) + YUV_MEM;
++ preview->pp_virt_buf = ioremap_nocache(preview->pp_phys_buf, RGB_MEM);
++
++ /* Device init */
++ s3c_camif_init();
++ s3c_camif_init_codec(codec);
++ s3c_camif_init_preview(preview);
++
++ /* Set irq */
++ codec->irq = platform_get_irq(pdev, FIMC_CODEC_INDEX);
++ preview->irq = platform_get_irq(pdev, FIMC_PREVIEW_INDEX);
++
++ s3c_camif_request_irq(codec);
++ s3c_camif_request_irq(preview);
++
++ /* Register to video device */
++ if (video_register_device(codec->v, VFL_TYPE_GRABBER, CODEC_MINOR) != 0) {
++ printk(KERN_ERR "Couldn't register this codec driver\n");
++ return -1;
++ }
++
++ if (video_register_device(preview->v, VFL_TYPE_GRABBER, PREVIEW_MINOR) != 0) {
++ printk(KERN_ERR "Couldn't register this preview driver\n");
++ return -1;
++ }
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ cam_clock = clk_get(&pdev->dev, "camera");
++#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2450)
++ cam_clock = clk_get(&pdev->dev, "camif-upll");
++#else
++#error cam_clock should be defined
++#endif
++
++ if (IS_ERR(cam_clock)) {
++ printk("Failed to find camera clock source\n");
++ ret = PTR_ERR(cam_clock);
++ }
++
++ clk_enable(cam_clock);
++
++ /* Print banner */
++ printk(KERN_INFO "S3C FIMC v%s\n", FIMC_VER);
++
++ return 0;
++}
++
++static int s3c_camif_remove(struct platform_device *pdev)
++{
++ camif_cfg_t *codec, *preview;
++
++ codec = s3c_camif_get_fimc_object(CODEC_MINOR);
++ preview = s3c_camif_get_fimc_object(PREVIEW_MINOR);
++
++ s3c_camif_release_irq(codec);
++ s3c_camif_release_irq(preview);
++
++ iounmap(codec->pp_virt_buf);
++ codec->pp_virt_buf = 0;
++
++ iounmap(preview->pp_virt_buf);
++ preview->pp_virt_buf = 0;
++
++ video_unregister_device(codec->v);
++ video_unregister_device(preview->v);
++
++ s3c_camif_set_priority(0);
++ clk_disable(cam_clock);
++
++ memset(codec, 0, sizeof(camif_cfg_t));
++ memset(preview, 0, sizeof(camif_cfg_t));
++
++ return 0;
++}
++
++#if defined(CONFIG_PM)
++
++static struct sleep_save_phy s3c_camif_save[] = {
++ SAVE_ITEM(S3C_CISRCFMT),
++ SAVE_ITEM(S3C_CIWDOFST),
++ SAVE_ITEM(S3C_CIGCTRL),
++ SAVE_ITEM(S3C_CIDOWSFT2),
++ SAVE_ITEM(S3C_CICOYSA1),
++ SAVE_ITEM(S3C_CICOYSA2),
++ SAVE_ITEM(S3C_CICOYSA3),
++ SAVE_ITEM(S3C_CICOYSA4),
++ SAVE_ITEM(S3C_CICOCBSA1),
++ SAVE_ITEM(S3C_CICOCBSA2),
++ SAVE_ITEM(S3C_CICOCBSA3),
++ SAVE_ITEM(S3C_CICOCBSA4),
++ SAVE_ITEM(S3C_CICOTRGFMT),
++ SAVE_ITEM(S3C_CICOCTRL),
++ SAVE_ITEM(S3C_CICOSCPRERATIO),
++ SAVE_ITEM(S3C_CICOSCPREDST),
++ SAVE_ITEM(S3C_CICOSCCTRL),
++ SAVE_ITEM(S3C_CICOTAREA),
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++ SAVE_ITEM(S3C_CIPRCLRSA1),
++ SAVE_ITEM(S3C_CIPRCLRSA2),
++ SAVE_ITEM(S3C_CIPRCLRSA3),
++ SAVE_ITEM(S3C_CIPRCLRSA4),
++ SAVE_ITEM(S3C_CIPRTRGFMT),
++ SAVE_ITEM(S3C_CIPRCTRL),
++ SAVE_ITEM(S3C_CIPRSCPRERATIO),
++ SAVE_ITEM(S3C_CIPRSCPREDST),
++ SAVE_ITEM(S3C_CIPRSCCTRL),
++ SAVE_ITEM(S3C_CIPRTAREA),
++ SAVE_ITEM(S3C_CIIMGCPT),
++ SAVE_ITEM(S3C_CICOCPTSEQ),
++ SAVE_ITEM(S3C_CICOSCOS),
++ SAVE_ITEM(S3C_CIIMGEFF),
++ SAVE_ITEM(S3C_CIMSYSA),
++ SAVE_ITEM(S3C_CIMSCBSA),
++ SAVE_ITEM(S3C_CIMSCRSA),
++ SAVE_ITEM(S3C_CIMSYEND),
++ SAVE_ITEM(S3C_CIMSCBEND),
++ SAVE_ITEM(S3C_CIMSCREND),
++ SAVE_ITEM(S3C_CIMSYOFF),
++ SAVE_ITEM(S3C_CIMSCBOFF),
++ SAVE_ITEM(S3C_CIMSCROFF),
++ SAVE_ITEM(S3C_CIMSWIDTH),
++ SAVE_ITEM(S3C_CIMSCTRL),
++
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ SAVE_ITEM(S3C_CIPRYSA1),
++ SAVE_ITEM(S3C_CIPRYSA2),
++ SAVE_ITEM(S3C_CIPRYSA3),
++ SAVE_ITEM(S3C_CIPRYSA4),
++ SAVE_ITEM(S3C_CIPRCBSA1),
++ SAVE_ITEM(S3C_CIPRCBSA2),
++ SAVE_ITEM(S3C_CIPRCBSA3),
++ SAVE_ITEM(S3C_CIPRCBSA4),
++ SAVE_ITEM(S3C_CIPRCRSA1),
++ SAVE_ITEM(S3C_CIPRCRSA2),
++ SAVE_ITEM(S3C_CIPRCRSA3),
++ SAVE_ITEM(S3C_CIPRCRSA4),
++ SAVE_ITEM(S3C_CIPRTRGFMT),
++ SAVE_ITEM(S3C_CIPRCTRL),
++ SAVE_ITEM(S3C_CIPRSCPRERATIO),
++ SAVE_ITEM(S3C_CIPRSCPREDST),
++ SAVE_ITEM(S3C_CIPRSCCTRL),
++ SAVE_ITEM(S3C_CIPRTAREA),
++ SAVE_ITEM(S3C_CIPRSTATUS),
++ SAVE_ITEM(S3C_CIIMGCPT),
++ SAVE_ITEM(S3C_CICOCPTSEQ),
++ SAVE_ITEM(S3C_CIIMGEFF),
++ SAVE_ITEM(S3C_MSCOY0SA),
++ SAVE_ITEM(S3C_MSCOCB0SA),
++ SAVE_ITEM(S3C_MSCOY0END),
++ SAVE_ITEM(S3C_MSCOCB0END),
++ SAVE_ITEM(S3C_MSCOCR0END),
++ SAVE_ITEM(S3C_MSCOYOFF),
++ SAVE_ITEM(S3C_MSCOCBOFF),
++ SAVE_ITEM(S3C_MSCOCROFF),
++ SAVE_ITEM(S3C_MSCOWIDTH),
++ SAVE_ITEM(S3C_MSCOCTRL),
++ SAVE_ITEM(S3C_MSPRY0SA),
++ SAVE_ITEM(S3C_MSPRCB0SA),
++ SAVE_ITEM(S3C_MSPRY0END),
++ SAVE_ITEM(S3C_MSPRCB0END),
++ SAVE_ITEM(S3C_MSPRCR0END),
++ SAVE_ITEM(S3C_MSPRYOFF),
++ SAVE_ITEM(S3C_MSPRCBOFF),
++ SAVE_ITEM(S3C_MSPRCROFF),
++ SAVE_ITEM(S3C_MSPRWIDTH),
++ SAVE_ITEM(S3C_CIMSCTRL),
++ SAVE_ITEM(S3C_CICOSCOSY),
++ SAVE_ITEM(S3C_CICOSCOSCB),
++ SAVE_ITEM(S3C_CICOSCOSCR),
++ SAVE_ITEM(S3C_CIPRSCOSY),
++ SAVE_ITEM(S3C_CIPRSCOSCB),
++ SAVE_ITEM(S3C_CIPRSCOSCR),
++
++#endif
++};
++
++/*
++ * Suspend
++ */
++int s3c_camif_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ s3c2410_pm_do_save_phy(s3c_camif_save, pdev, ARRAY_SIZE(s3c_camif_save));
++ clk_disable(cam_clock);
++
++ return 0;
++}
++
++/*
++ * Resume
++ */
++int s3c_camif_resume(struct platform_device *pdev)
++{
++ clk_enable(cam_clock);
++
++ s3c_camif_init();
++ s3c_camif_init_sensor(s3c_camif_get_fimc_object(CODEC_MINOR));
++ s3c2410_pm_do_restore_phy(s3c_camif_save, pdev, ARRAY_SIZE(s3c_camif_save));
++
++ return 0;
++}
++
++#else
++
++int s3c_camif_suspend(struct platform_device *dev, pm_message_t state)
++{
++ return 0;
++}
++
++int s3c_camif_resume(struct platform_device *dev)
++{
++ return 0;
++}
++
++#endif
++
++static struct platform_driver s3c_camif_driver =
++{
++ .probe = s3c_camif_probe,
++ .remove = s3c_camif_remove,
++ .suspend = s3c_camif_suspend,
++ .resume = s3c_camif_resume,
++ .driver = {
++ .name = "s3c-camif",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int s3c_camif_register(void)
++{
++ platform_driver_register(&s3c_camif_driver);
++
++ return 0;
++}
++
++static void s3c_camif_unregister(void)
++{
++ platform_driver_unregister(&s3c_camif_driver);
++}
++
++void s3c_camif_open_sensor(camif_cis_t *cis)
++{
++ clk_set_rate(cam_clock, cis->camclk);
++ s3c_camif_reset(cis->reset_type, cis->reset_udelay);
++}
++
++void s3c_camif_register_sensor(struct i2c_client *ptr)
++{
++ camif_cfg_t *codec, *preview;
++ camif_cis_t *cis = (camif_cis_t *) ptr->data;
++
++ codec = s3c_camif_get_fimc_object(CODEC_MINOR);
++ preview = s3c_camif_get_fimc_object(PREVIEW_MINOR);
++
++ codec->cis = preview->cis = cis;
++
++ sema_init((struct semaphore *) &codec->cis->lock, 1);
++ sema_init((struct semaphore *) &preview->cis->lock, 1);
++
++ preview->cis->status |= P_NOT_WORKING; /* Default Value */
++
++ s3c_camif_set_polarity(preview);
++ s3c_camif_set_source_format(cis);
++ s3c_camif_set_priority(1);
++}
++
++void s3c_camif_unregister_sensor(struct i2c_client *ptr)
++{
++ camif_cis_t *cis;
++
++ cis = (camif_cis_t *) (ptr->data);
++ cis->init_sensor = 0;
++}
++
++module_init(s3c_camif_register);
++module_exit(s3c_camif_unregister);
++
++EXPORT_SYMBOL(s3c_camif_register_sensor);
++EXPORT_SYMBOL(s3c_camif_unregister_sensor);
++
++MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
++MODULE_DESCRIPTION("S3C Camera Driver for FIMC Interface");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/media/video/s3c_camif.c b/drivers/media/video/s3c_camif.c
+new file mode 100644
+index 0000000..99df64e
+--- /dev/null
++++ b/drivers/media/video/s3c_camif.c
+@@ -0,0 +1,1871 @@
++/* drivers/media/video/s3c_camif.c
++ *
++ * Copyright (c) 2008 Samsung Electronics
++ *
++ * Samsung S3C Camera driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/completion.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/wait.h>
++#include <linux/videodev.h>
++#include <asm/io.h>
++#include <asm/semaphore.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++#include <asm/arch/map.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-camif.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
++#include <asm/arch/regs-lcd.h>
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#include <asm/arch/regs-irq.h>
++#endif
++
++#include "s3c_camif.h"
++
++static unsigned int irq_old_priority;
++
++/*************************************************************************
++ * Utility part
++ ************************************************************************/
++int s3c_camif_get_frame_num(camif_cfg_t *cfg)
++{
++ int index = 0;
++
++ if (cfg->dma_type & CAMIF_CODEC)
++ index = (readl(cfg->regs + S3C_CICOSTATUS) >> 26) & 0x3;
++ else {
++ assert(cfg->dma_type & CAMIF_PREVIEW);
++ index = (readl(cfg->regs + S3C_CIPRSTATUS) >> 26) & 0x3;
++ }
++
++ cfg->cur_frame_num = (index + 2) % 4; /* When 4 PingPong */
++
++ return 0;
++}
++
++unsigned char* s3c_camif_get_frame(camif_cfg_t *cfg)
++{
++ unsigned char *ret = NULL;
++ int cnt = cfg->cur_frame_num;
++
++ if (cfg->dma_type & CAMIF_PREVIEW)
++ ret = cfg->img_buf[cnt].virt_rgb;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ if ((cfg->dst_fmt & CAMIF_RGB16) || (cfg->dst_fmt & CAMIF_RGB24))
++ ret = cfg->img_buf[cnt].virt_rgb;
++ else
++ ret = cfg->img_buf[cnt].virt_y;
++ }
++
++ return ret;
++}
++
++int s3c_camif_get_fifo_status(camif_cfg_t *cfg)
++{
++ unsigned int reg, val, flag;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ flag = S3C_CICOSTATUS_OVFIY_CO | S3C_CICOSTATUS_OVFICB_CO | S3C_CICOSTATUS_OVFICR_CO;
++ reg = readl(cfg->regs + S3C_CICOSTATUS);
++
++ if (reg & flag) {
++ /* FIFO Error Count ++ */
++ val = readl(cfg->regs + S3C_CIWDOFST);
++ val |= (S3C_CIWDOFST_CLROVCOFIY | S3C_CIWDOFST_CLROVCOFICB | S3C_CIWDOFST_CLROVCOFICR);
++ writel(val, cfg->regs + S3C_CIWDOFST);
++
++ val = readl(cfg->regs + S3C_CIWDOFST);
++ val &= ~(S3C_CIWDOFST_CLROVCOFIY | S3C_CIWDOFST_CLROVCOFICB | S3C_CIWDOFST_CLROVCOFICR);
++ writel(val, cfg->regs + S3C_CIWDOFST);
++
++ return 1; /* Error */
++ }
++ } else if (cfg->dma_type & CAMIF_PREVIEW) {
++ flag = S3C_CIPRSTATUS_OVFICB_PR | S3C_CIPRSTATUS_OVFICR_PR;
++ reg = readl(cfg->regs + S3C_CIPRSTATUS);
++
++ if (reg & flag) {
++ /* FIFO Error Count ++ */
++ val = readl(cfg->regs + S3C_CIWDOFST);
++ val |= (S3C_CIWDOFST_CLROVPRFICB | S3C_CIWDOFST_CLROVPRFICR);
++ writel(val, cfg->regs + S3C_CIWDOFST);
++
++ val = readl(cfg->regs + S3C_CIWDOFST);
++ val &= ~(S3C_CIWDOFST_CLROVPRFIY | S3C_CIWDOFST_CLROVPRFICB | S3C_CIWDOFST_CLROVPRFICR);
++ writel(val, cfg->regs + S3C_CIWDOFST);
++
++ return 1; /* Error */
++ }
++ }
++
++ return 0;
++}
++
++void s3c_camif_set_polarity(camif_cfg_t *cfg)
++{
++ camif_cis_t *cis = cfg->cis;
++ unsigned int val;
++ unsigned int cmd;
++
++ cmd = readl(cfg->regs + S3C_CIGCTRL);
++ cmd &= ~(0x7 << 24);
++
++ if (cis->polarity_pclk)
++ cmd |= S3C_CIGCTRL_INVPOLPCLK;
++
++ if (cis->polarity_vsync)
++ cmd |= S3C_CIGCTRL_INVPOLVSYNC;
++
++ if (cis->polarity_href)
++ cmd |= S3C_CIGCTRL_INVPOLHREF;
++
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val |= cmd;
++ writel(val, cfg->regs + S3C_CIGCTRL);
++}
++
++/*************************************************************************
++ * Memory part
++ ************************************************************************/
++static int s3c_camif_request_memory(camif_cfg_t *cfg)
++{
++ unsigned int t_size = 0, i = 0;
++ unsigned int area = 0;
++
++ area = cfg->target_x * cfg->target_y;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ if (cfg->dst_fmt & CAMIF_YCBCR420)
++ t_size = (area * 3 / 2); /* CAMIF_YCBCR420 */
++ else if (cfg->dst_fmt & CAMIF_YCBCR422 || cfg->dst_fmt & CAMIF_YCBCR422I)
++ t_size = (area * 2); /* CAMIF_YCBCR422 */
++ else if (cfg->dst_fmt & CAMIF_RGB16)
++ t_size = (area * 2); /* 2 bytes per one pixel */
++ else if (cfg->dst_fmt & CAMIF_RGB24)
++ t_size = (area * 4); /* 4 bytes per one pixel */
++ else
++ printk(KERN_INFO "Invalid target format\n");
++
++ if ((t_size % PAGE_SIZE) != 0) {
++ i = t_size / PAGE_SIZE;
++ t_size = (i + 1) * PAGE_SIZE;
++ }
++
++ t_size = t_size * cfg->pp_num;
++ cfg->pp_totalsize = t_size;
++
++ printk(KERN_INFO "Codec memory required: 0x%08X bytes\n", t_size);
++
++ return 0;
++ }else if (cfg->dma_type & CAMIF_PREVIEW) {
++
++ if (cfg->dst_fmt & CAMIF_RGB16)
++ t_size = (area * 2); /* 2 bytes per two pixel*/
++ else if (cfg->dst_fmt & CAMIF_RGB24)
++ t_size = (area * 4); /* 4 bytes per one pixel */
++ else
++ printk(KERN_ERR "Invalid target format\n");
++
++ if ((t_size % PAGE_SIZE) != 0) {
++ i = t_size / PAGE_SIZE;
++ t_size = (i + 1) * PAGE_SIZE;
++ }
++
++ t_size = t_size * cfg->pp_num;
++ cfg->pp_totalsize = t_size;
++
++ printk(KERN_INFO "Preview memory required: 0x%08X bytes\n", t_size);
++
++ return 0;
++ }
++
++ return 0;
++}
++
++static void s3c_camif_calc_burst_length_yuv422i(unsigned int hsize, unsigned int *mburst, unsigned int *rburst)
++{
++ unsigned int tmp, wanted;
++
++ tmp = (hsize / 2) & 0xf;
++
++ switch (tmp) {
++ case 0:
++ wanted = 16;
++ break;
++
++ case 4:
++ wanted = 4;
++ break;
++
++ case 8:
++ wanted = 8;
++ break;
++
++ default:
++ wanted = 4;
++ break;
++ }
++
++ *mburst = wanted / 2;
++ *rburst = wanted / 2;
++}
++
++static void s3c_camif_calc_burst_length(unsigned int hsize, unsigned int *mburst, unsigned int *rburst)
++{
++ unsigned int tmp;
++
++ tmp = (hsize / 4) & 0xf;
++
++ switch (tmp) {
++ case 0:
++ *mburst = 16;
++ *rburst = 16;
++ break;
++
++ case 4:
++ *mburst = 16;
++ *rburst = 4;
++ break;
++
++ case 8:
++ *mburst = 16;
++ *rburst = 8;
++ break;
++
++ default:
++ tmp = (hsize / 4) % 8;
++
++ if (tmp == 0) {
++ *mburst = 8;
++ *rburst = 8;
++ } else if (tmp == 4) {
++ *mburst = 8;
++ *rburst = 4;
++ } else {
++ tmp = (hsize / 4) % 4;
++ *mburst = 4;
++ *rburst = (tmp) ? tmp : 4;
++ }
++
++ break;
++ }
++}
++
++int s3c_camif_setup_dma(camif_cfg_t *cfg)
++{
++ int width = cfg->target_x;
++ unsigned int val, yburst_m, yburst_r, cburst_m, cburst_r;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ if ((cfg->dst_fmt == CAMIF_RGB16) || (cfg->dst_fmt == CAMIF_RGB24)) {
++ if (cfg->dst_fmt == CAMIF_RGB24) {
++ if (width % 2 != 0)
++ return BURST_ERR;
++
++ s3c_camif_calc_burst_length(width * 4, &yburst_m, &yburst_r);
++ } else {
++ if ((width / 2) % 2 != 0)
++ return BURST_ERR;
++
++ s3c_camif_calc_burst_length(width * 2, &yburst_m, &yburst_r);
++ }
++
++ val = readl(cfg->regs + S3C_CICOCTRL);
++ val &= ~(0xfffff << 4);
++
++ if (cfg->dst_fmt == CAMIF_RGB24) {
++ val = S3C_CICOCTRL_YBURST1_CO(yburst_m / 2) | \
++ S3C_CICOCTRL_YBURST2_CO(yburst_r / 4) | (4 << 9) | (2 << 4);
++ } else {
++ val = S3C_CICOCTRL_YBURST1_CO(yburst_m / 2) | \
++ S3C_CICOCTRL_YBURST2_CO(yburst_r / 2) | (4 << 9) | (2 << 4);
++ }
++
++ writel(val, cfg->regs + S3C_CICOCTRL);
++ } else {
++ /* CODEC DMA WIDHT is multiple of 16 */
++ if (width % 16 != 0)
++ return BURST_ERR;
++
++ if (cfg->dst_fmt == CAMIF_YCBCR422I) {
++ s3c_camif_calc_burst_length_yuv422i(width, &yburst_m, &yburst_r);
++ cburst_m = yburst_m / 2;
++ cburst_r = yburst_r / 2;
++ } else {
++ s3c_camif_calc_burst_length(width, &yburst_m, &yburst_r);
++ s3c_camif_calc_burst_length(width / 2, &cburst_m, &cburst_r);
++ }
++
++ val = readl(cfg->regs + S3C_CICOCTRL);
++ val &= ~(0xfffff << 4);
++ val |= (S3C_CICOCTRL_YBURST1_CO(yburst_m) | S3C_CICOCTRL_CBURST1_CO(cburst_m) | \
++ S3C_CICOCTRL_YBURST2_CO(yburst_r) | S3C_CICOCTRL_CBURST2_CO(cburst_r));
++ writel(val, cfg->regs + S3C_CICOCTRL);
++ }
++ } else if (cfg->dma_type & CAMIF_PREVIEW) {
++ if (cfg->dst_fmt == CAMIF_RGB24) {
++ if (width % 2 != 0)
++ return BURST_ERR;
++
++ s3c_camif_calc_burst_length(width * 4, &yburst_m, &yburst_r);
++ } else {
++ if ((width / 2) % 2 != 0)
++ return BURST_ERR;
++
++ s3c_camif_calc_burst_length(width * 2, &yburst_m, &yburst_r);
++ }
++
++ val = readl(cfg->regs + S3C_CIPRCTRL);
++ val &= ~(0x3ff << 14);
++ val |= (S3C_CICOCTRL_YBURST1_CO(yburst_m) | S3C_CICOCTRL_YBURST2_CO(yburst_r));
++ writel(val, cfg->regs + S3C_CIPRCTRL);
++ }
++
++ return 0;
++}
++
++/*************************************************************************
++ * Input path part
++ ************************************************************************/
++/*
++ * 2443 MSDMA (Preview Only)
++ */
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++int s3c_camif_input_msdma_preview(camif_cfg_t * cfg)
++{
++ int ret = 0;
++ unsigned int addr_start_Y = 0, addr_start_CB = 0, addr_start_CR = 0;
++ unsigned int addr_end_Y = 0, addr_end_CB = 0, addr_end_CR = 0;
++ unsigned int val, val_width;
++
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val &= ~(1 << 2);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val |= (1 << 2);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ if (cfg->src_fmt != CAMIF_YCBCR420 && cfg->src_fmt != CAMIF_YCBCR422 && cfg->src_fmt != CAMIF_YCBCR422I)
++ cfg->src_fmt = CAMIF_YCBCR420;
++
++ switch(cfg->src_fmt) {
++ case CAMIF_YCBCR420:
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val = (val & ~(0x1 << 1)) | (0x1 << 1);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ addr_start_Y = readl(cfg->regs + S3C_CIMSYSA);
++ addr_start_CB = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_start_CR = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 4);
++
++ addr_end_Y = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_end_CB = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 4);
++ addr_end_CR = addr_start_CR + (cfg->cis->source_x * cfg->cis->source_y / 4);
++ break;
++
++ case CAMIF_YCBCR422:
++ case CAMIF_YCBCR422I:
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val = (val & ~(0x1 << 5)) | (0x1 << 5); /* Interleave_MS */
++ val &= ~(0x1 << 1);
++ val &= ~(0x3 << 3); /* YCbYCr */
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ addr_start_Y = readl(cfg->regs + S3C_CIMSYSA);
++ addr_start_CB = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_start_CR = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 2);
++
++ addr_end_Y = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_end_CB = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 2);
++ addr_end_CR = addr_start_CR + (cfg->cis->source_x * cfg->cis->source_y / 2);
++ break;
++
++ default:
++ break;
++ }
++
++ /* MSDMA memory */
++ writel(addr_start_Y, cfg->regs + S3C_CIMSYSA);
++ writel(addr_start_CB, cfg->regs + S3C_CIMSCBSA);
++ writel(addr_start_CR, cfg->regs + S3C_CIMSCRSA);
++
++ writel(addr_end_Y, cfg->regs + S3C_CIMSYEND);
++ writel(addr_end_CB, cfg->regs + S3C_CIMSCBEND);
++ writel(addr_end_CR, cfg->regs + S3C_CIMSCREND);
++
++ /* MSDMA memory offset - default : 0 */
++ writel(0, cfg->regs + S3C_CIMSYOFF);
++ writel(0, cfg->regs + S3C_CIMSCBOFF);
++ writel(0, cfg->regs + S3C_CIMSCROFF);
++
++ /* MSDMA for codec source image width */
++ val_width = readl(cfg->regs + S3C_CIMSWIDTH);
++ val_width = (val_width & ~(0x1 << 31)); /* AutoLoadDisable */
++ val_width |= (cfg->cis->source_y << 16); /* MSCOHEIGHT */
++ val_width |= cfg->cis->source_x; /* MSCOWIDTH */
++ val_width = cfg->cis->source_x;
++ writel(val_width, cfg->regs + S3C_CIMSWIDTH);
++
++ return ret;
++}
++
++static int s3c_camif_input_msdma(camif_cfg_t *cfg)
++{
++ if (cfg->input_channel == MSDMA_FROM_PREVIEW)
++ s3c_camif_input_msdma_preview(cfg);
++
++ return 0;
++}
++
++/*
++ * 6400 MSDMA (Preview & Codec)
++ */
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++int s3c_camif_input_msdma_codec(camif_cfg_t * cfg)
++{
++ int ret = 0;
++ u32 addr_start_Y = 0, addr_start_CB = 0, addr_start_CR = 0;
++ u32 addr_end_Y = 0, addr_end_CB = 0, addr_end_CR = 0;
++ u32 val, val_width;
++
++ /* Codec path input data selection */
++ val = readl(cfg->regs + S3C_MSCOCTRL);
++ val &= ~(1 << 3);
++ writel(val, cfg->regs + S3C_MSCOCTRL);
++
++ val = readl(cfg->regs + S3C_MSCOCTRL);
++ val |= (1 << 3);
++ writel(val, cfg->regs + S3C_MSCOCTRL);
++
++ if (cfg->src_fmt != CAMIF_YCBCR420 && cfg->src_fmt != CAMIF_YCBCR422 && cfg->src_fmt != CAMIF_YCBCR422I)
++ cfg->src_fmt = CAMIF_YCBCR420;
++
++ switch(cfg->src_fmt) {
++ case CAMIF_YCBCR420:
++ val = readl(cfg->regs + S3C_MSCOCTRL);
++ val &= ~(0x3 << 1);
++ writel(val, cfg->regs + S3C_MSCOCTRL);
++
++ addr_start_Y = cfg->pp_phys_buf;
++ addr_start_CB = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_start_CR = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 4);
++
++ addr_end_Y = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_end_CB = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 4);
++ addr_end_CR = addr_start_CR + (cfg->cis->source_x * cfg->cis->source_y / 4);
++ break;
++
++ case CAMIF_YCBCR422:
++ case CAMIF_YCBCR422I:
++ val = readl(cfg->regs + S3C_MSCOCTRL);
++ val = (val & ~(0x3 << 1)) |(0x2 << 1);
++ writel(val, cfg->regs + S3C_MSCOCTRL);
++
++ addr_start_Y = cfg->pp_phys_buf;
++ addr_start_CB = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_start_CR = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 2);
++
++ addr_end_Y = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_end_CB = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 2);
++ addr_end_CR = addr_start_CR + (cfg->cis->source_x * cfg->cis->source_y / 2);
++ break;
++
++ default:
++ break;
++ }
++
++ /* MSDMA memory */
++ writel(addr_start_Y, cfg->regs + S3C_MSCOY0SA);
++ writel(addr_start_CB, cfg->regs + S3C_MSCOCB0SA);
++ writel(addr_start_CR, cfg->regs + S3C_MSCOCR0SA);
++
++ writel(addr_end_Y, cfg->regs + S3C_MSCOY0END);
++ writel(addr_end_CB, cfg->regs + S3C_MSCOCB0END);
++ writel(addr_end_CR, cfg->regs + S3C_MSCOCR0END);
++
++ /* MSDMA memory offset */
++ writel(0, cfg->regs + S3C_MSCOYOFF);
++ writel(0, cfg->regs + S3C_MSCOCBOFF);
++ writel(0, cfg->regs + S3C_MSCOCROFF);
++
++ /* MSDMA for codec source image width */
++ val_width = readl(cfg->regs + S3C_MSCOWIDTH);
++ val_width = (val_width & ~(0x1 << 31))|(0x1 << 31); /* AutoLoadEnable */
++ val_width |= (cfg->cis->source_y << 16); /* MSCOHEIGHT */
++ val_width |= cfg->cis->source_x; /* MSCOWIDTH */
++ writel(val_width, cfg->regs + S3C_MSCOWIDTH);
++
++ return ret;
++}
++
++int s3c_camif_input_msdma_preview(camif_cfg_t * cfg)
++{
++ int ret = 0;
++ unsigned int addr_start_Y = 0, addr_start_CB = 0, addr_start_CR = 0;
++ unsigned int addr_end_Y = 0, addr_end_CB = 0, addr_end_CR = 0;
++ unsigned int val, val_width;
++
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val &= ~(0x1 << 3);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val |= (0x1 << 3);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ if (cfg->src_fmt != CAMIF_YCBCR420 && cfg->src_fmt != CAMIF_YCBCR422 && cfg->src_fmt != CAMIF_YCBCR422I)
++ cfg->src_fmt = CAMIF_YCBCR420;
++
++ switch(cfg->src_fmt) {
++ case CAMIF_YCBCR420:
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val &= ~(0x3 << 1);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ addr_start_Y = readl(cfg->regs + S3C_MSPRY0SA);
++ addr_start_CB = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_start_CR = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 4);
++
++ addr_end_Y = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_end_CB = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 4);
++ addr_end_CR = addr_start_CR + (cfg->cis->source_x * cfg->cis->source_y / 4);
++ break;
++
++ case CAMIF_YCBCR422:
++ case CAMIF_YCBCR422I:
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val = (val & ~(0x3 << 1)) | (0x2 << 1); /* YCbCr 422 Interleave */
++ val = (val & ~(0x3 << 4)) | (0x3 << 4); /* YCbYCr */
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ addr_start_Y = readl(cfg->regs + S3C_MSPRY0SA);
++ addr_start_CB = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_start_CR = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 2);
++
++ addr_end_Y = addr_start_Y + (cfg->cis->source_x * cfg->cis->source_y);
++ addr_end_CB = addr_start_CB + (cfg->cis->source_x * cfg->cis->source_y / 2);
++ addr_end_CR = addr_start_CR + (cfg->cis->source_x * cfg->cis->source_y / 2);
++ break;
++
++ default:
++ break;
++ }
++
++ /* MSDMA memory */
++ writel(addr_start_Y, cfg->regs + S3C_MSPRY0SA);
++ writel(addr_start_CB, cfg->regs + S3C_MSPRCB0SA);
++ writel(addr_start_CR, cfg->regs + S3C_MSPRCR0SA);
++
++ writel(addr_end_Y, cfg->regs + S3C_MSPRY0END);
++ writel(addr_end_CB, cfg->regs + S3C_MSPRCB0END);
++ writel(addr_end_CR, cfg->regs + S3C_MSPRCR0END);
++
++ /* MSDMA memory offset */
++ writel(0, cfg->regs + S3C_MSPRYOFF);
++ writel(0, cfg->regs + S3C_MSPRCBOFF);
++ writel(0, cfg->regs + S3C_MSPRCROFF);
++
++ /* MSDMA for codec source image width */
++ val_width = readl(cfg->regs + S3C_MSPRWIDTH);
++ val_width = (val_width & ~(0x1 << 31)); /* AutoLoadEnable */
++ val_width |= (cfg->cis->source_y << 16); /* MSCOHEIGHT */
++ val_width |= cfg->cis->source_x; /* MSCOWIDTH */
++ writel(val_width, cfg->regs + S3C_MSPRWIDTH);
++
++ return ret;
++}
++
++static int s3c_camif_input_msdma(camif_cfg_t *cfg)
++{
++ if (cfg->input_channel == MSDMA_FROM_PREVIEW)
++ s3c_camif_input_msdma_preview(cfg);
++ else if (cfg->input_channel == MSDMA_FROM_CODEC)
++ s3c_camif_input_msdma_codec(cfg);
++
++ return 0;
++}
++#endif
++
++static int s3c_camif_input_camera(camif_cfg_t *cfg)
++{
++ unsigned int val;
++
++ s3c_camif_set_offset(cfg->cis);
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ val = readl(cfg->regs + S3C_MSCOCTRL);
++ val &= ~(1 << 3);
++ writel(val, cfg->regs + S3C_MSCOCTRL);
++#endif
++ } else if (cfg->dma_type & CAMIF_PREVIEW) {
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val &= ~(1 << 2);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++#elif defined(CONFIG_CPU_S3C6400)
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val &= ~(1 << 3);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++#endif
++ } else
++ printk(KERN_ERR "Invalid DMA type\n");
++
++ return 0;
++}
++
++static int s3c_camif_setup_input_path(camif_cfg_t *cfg)
++{
++ if (cfg->input_channel == CAMERA_INPUT)
++ s3c_camif_input_camera(cfg);
++ else
++ s3c_camif_input_msdma(cfg);
++
++ return 0;
++}
++
++/*************************************************************************
++ * Output path part
++ ************************************************************************/
++static int s3c_camif_output_pp_codec_rgb(camif_cfg_t *cfg)
++{
++ int i;
++ unsigned int val;
++ unsigned int area = cfg->target_x * cfg->target_y;
++
++ if (cfg->dst_fmt & CAMIF_RGB24)
++ area = area * 4;
++ else {
++ assert (cfg->dst_fmt & CAMIF_RGB16);
++ area = area * 2;
++ }
++
++ if ((area % PAGE_SIZE) != 0) {
++ i = area / PAGE_SIZE;
++ area = (i + 1) * PAGE_SIZE;
++ }
++
++ cfg->buffer_size = area;
++
++ if (cfg->input_channel == MSDMA_FROM_CODEC) {
++ val = readl(S3C_VIDW00ADD0B0);
++
++ for (i = 0; i < 4; i++)
++ writel(val, cfg->regs + S3C_CICOYSA(i));
++ } else {
++ switch ( cfg->pp_num ) {
++ case 1:
++ for (i = 0; i < 4; i++) {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf;
++ writel(cfg->img_buf[i].phys_rgb, cfg->regs + S3C_CICOYSA(i));
++ }
++
++ break;
++
++ case 2:
++ for (i = 0; i < 4; i++) {
++ if (i == 0 || i == 2) {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf;
++ } else {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + area;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + area;
++ }
++
++ writel(cfg->img_buf[i].phys_rgb, cfg->regs + S3C_CICOYSA(i));
++ }
++
++ break;
++
++ case 4:
++ for (i = 0; i < 4; i++) {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + i * area;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + i * area;
++ writel(cfg->img_buf[i].phys_rgb, cfg->regs + S3C_CICOYSA(i));
++ }
++
++ break;
++
++ default:
++ printk(KERN_ERR "Invalid pingpong number %d\n", cfg->pp_num);
++ panic("s3c camif halt\n");
++ }
++ }
++
++ return 0;
++}
++
++static int s3c_camif_output_pp_codec(camif_cfg_t *cfg)
++{
++ unsigned int i, cbcr_size = 0;
++ unsigned int area = cfg->target_x * cfg->target_y;
++ unsigned int one_p_size;
++
++ area = cfg->target_x * cfg->target_y;
++
++ if (cfg->dst_fmt & CAMIF_YCBCR420)
++ cbcr_size = area / 4;
++ else if (cfg->dst_fmt & CAMIF_YCBCR422 || cfg->dst_fmt & CAMIF_YCBCR422I)
++ cbcr_size = area / 2;
++ else if ((cfg->dst_fmt & CAMIF_RGB16) || (cfg->dst_fmt & CAMIF_RGB24)) {
++ s3c_camif_output_pp_codec_rgb(cfg);
++ return 0;
++ } else
++ printk(KERN_ERR "Invalid target format %d\n", cfg->dst_fmt);
++
++ one_p_size = area + (2 * cbcr_size);
++
++ if ((one_p_size % PAGE_SIZE) != 0) {
++ i = one_p_size / PAGE_SIZE;
++ one_p_size = (i + 1) * PAGE_SIZE;
++ }
++
++ cfg->buffer_size = one_p_size;
++
++ switch (cfg->pp_num) {
++ case 1 :
++ for (i = 0; i < 4; i++) {
++ cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
++ cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
++ cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + area;
++ cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + area;
++ cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + area + cbcr_size;
++ cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + area + cbcr_size;
++ writel(cfg->img_buf[i].phys_y, cfg->regs + S3C_CICOYSA(i));
++ writel(cfg->img_buf[i].phys_cb, cfg->regs + S3C_CICOCBSA(i));
++ writel(cfg->img_buf[i].phys_cr, cfg->regs + S3C_CICOCRSA(i));
++ }
++
++ break;
++
++ case 2:
++ for (i = 0; i < 4; i++) {
++ if (i == 0 || i == 2) {
++ cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
++ cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
++ cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + area;
++ cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + area;
++ cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + area + cbcr_size;
++ cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + area + cbcr_size;
++ } else {
++ cfg->img_buf[i].virt_y = cfg->pp_virt_buf + one_p_size;
++ cfg->img_buf[i].phys_y = cfg->pp_phys_buf + one_p_size;
++ cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + area + one_p_size;
++ cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + area + one_p_size;
++ cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + area + cbcr_size + one_p_size;
++ cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + area + cbcr_size + one_p_size;
++ }
++
++ writel(cfg->img_buf[i].phys_y, cfg->regs + S3C_CICOYSA(i));
++ writel(cfg->img_buf[i].phys_cb, cfg->regs + S3C_CICOCBSA(i));
++ writel(cfg->img_buf[i].phys_cr, cfg->regs + S3C_CICOCRSA(i));
++ }
++
++ break;
++
++ case 4:
++ for (i = 0; i < 4; i++) {
++ cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
++ cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
++ cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + area + i * one_p_size;
++ cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + area + i * one_p_size;
++ cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + area + cbcr_size + i * one_p_size;
++ cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + area + cbcr_size + i * one_p_size;
++ writel(cfg->img_buf[i].phys_y, cfg->regs + S3C_CICOYSA(i));
++ writel(cfg->img_buf[i].phys_cb, cfg->regs + S3C_CICOCBSA(i));
++ writel(cfg->img_buf[i].phys_cr, cfg->regs + S3C_CICOCRSA(i));
++ }
++
++ break;
++
++ default:
++ printk(KERN_ERR "Invalid pingpong number %d\n", cfg->pp_num);
++ }
++
++ return 0;
++}
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++static int s3c_camif_io_duplex_preview(camif_cfg_t *cfg)
++{
++ unsigned int cbcr_size = 0;
++ unsigned int area = cfg->cis->source_x * cfg->cis->source_y;
++ unsigned int val;
++ int i;
++
++ val = readl(S3C_VIDW01ADD0);
++
++ if (!((cfg->dst_fmt & CAMIF_RGB16) || (cfg->dst_fmt & CAMIF_RGB24)))
++ printk(KERN_ERR "Invalid target format\n");
++
++ for (i = 0; i < 4; i++)
++ writel(val, cfg->regs + S3C_CIPRYSA(i));
++
++ if (cfg->src_fmt & CAMIF_YCBCR420) {
++ cbcr_size = area / 4;
++ cfg->img_buf[0].virt_cb = cfg->pp_virt_buf + area;
++ cfg->img_buf[0].phys_cb = cfg->pp_phys_buf + area;
++ cfg->img_buf[0].virt_cr = cfg->pp_virt_buf + area + cbcr_size;
++ cfg->img_buf[0].phys_cr = cfg->pp_phys_buf + area + cbcr_size;
++ } else if (cfg->src_fmt & CAMIF_YCBCR422 || cfg->dst_fmt & CAMIF_YCBCR422I) {
++ area = area * 2;
++ cfg->img_buf[0].virt_cb = 0;
++ cfg->img_buf[0].phys_cb = 0;
++ cfg->img_buf[0].virt_cr = 0;
++ cfg->img_buf[0].phys_cr = 0;
++ }
++
++ cfg->img_buf[0].virt_y = cfg->pp_virt_buf;
++ cfg->img_buf[0].phys_y = cfg->pp_phys_buf;
++
++ writel(cfg->img_buf[0].phys_y, cfg->regs + S3C_CIMSYSA);
++ writel(cfg->img_buf[0].phys_y + area, cfg->regs + S3C_CIMSYEND);
++
++ writel(cfg->img_buf[0].phys_cb, cfg->regs + S3C_CIMSCBSA);
++ writel(cfg->img_buf[0].phys_cb + cbcr_size, cfg->regs + S3C_CIMSCBEND);
++
++ writel(cfg->img_buf[0].phys_cr, cfg->regs + S3C_CIMSCRSA);
++ writel(cfg->img_buf[0].phys_cr + cbcr_size, cfg->regs + S3C_CIMSCREND);
++
++ writel(cfg->cis->source_x, cfg->regs + S3C_CIMSWIDTH);
++
++ return 0;
++}
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++static int s3c_camif_io_duplex_preview(camif_cfg_t *cfg)
++{
++ unsigned int cbcr_size = 0;
++ unsigned int area = cfg->cis->source_x * cfg->cis->source_y;
++ unsigned int val;
++ int i;
++
++ val = readl(S3C_VIDW01ADD0B0);
++
++ if (!((cfg->dst_fmt & CAMIF_RGB16) || (cfg->dst_fmt & CAMIF_RGB24)))
++ printk(KERN_ERR "Invalid target format\n");
++
++ for (i = 0; i < 4; i++)
++ writel(val, cfg->regs + S3C_CIPRYSA(i));
++
++ if (cfg->src_fmt & CAMIF_YCBCR420) {
++ cbcr_size = area / 4;
++ cfg->img_buf[0].virt_cb = cfg->pp_virt_buf + area;
++ cfg->img_buf[0].phys_cb = cfg->pp_phys_buf + area;
++ cfg->img_buf[0].virt_cr = cfg->pp_virt_buf + area + cbcr_size;
++ cfg->img_buf[0].phys_cr = cfg->pp_phys_buf + area + cbcr_size;
++ } else if (cfg->src_fmt & CAMIF_YCBCR422 || cfg->dst_fmt & CAMIF_YCBCR422I){
++ area = area * 2;
++ cfg->img_buf[0].virt_cb = 0;
++ cfg->img_buf[0].phys_cb = 0;
++ cfg->img_buf[0].virt_cr = 0;
++ cfg->img_buf[0].phys_cr = 0;
++ }
++
++ cfg->img_buf[0].virt_y = cfg->pp_virt_buf;
++ cfg->img_buf[0].phys_y = cfg->pp_phys_buf;
++
++ writel(cfg->img_buf[0].phys_y, cfg->regs + S3C_MSPRY0SA);
++ writel(cfg->img_buf[0].phys_y + area, cfg->regs + S3C_MSPRY0END);
++
++ writel(cfg->img_buf[0].phys_cb, cfg->regs + S3C_MSPRCB0SA);
++ writel(cfg->img_buf[0].phys_cb + cbcr_size, cfg->regs + S3C_MSPRCB0END);
++
++ writel(cfg->img_buf[0].phys_cr, cfg->regs + S3C_MSPRCR0SA);
++ writel(cfg->img_buf[0].phys_cr + cbcr_size, cfg->regs + S3C_MSPRCR0END);
++
++ val = readl(cfg->regs + S3C_MSCOWIDTH);
++ val = (val & ~(0x1 << 31)) | (0x1 << 31);
++ val |= (cfg->cis->source_y << 16);
++ val |= cfg->cis->source_x;
++ writel(val, cfg->regs + S3C_MSPRWIDTH);
++
++ return 0;
++}
++#endif
++
++static int s3c_camif_output_pp_preview(camif_cfg_t *cfg)
++{
++ int i;
++ unsigned int cbcr_size = 0;
++ unsigned int area = cfg->target_x * cfg->target_y;
++
++ if (cfg->input_channel) {
++ s3c_camif_io_duplex_preview(cfg);
++ return 0;
++ }
++
++ if (cfg->dst_fmt & CAMIF_YCBCR420)
++ cbcr_size = area / 4;
++ else if (cfg->dst_fmt & CAMIF_YCBCR422 || cfg->dst_fmt & CAMIF_YCBCR422I)
++ cbcr_size = area / 2;
++ else if (cfg->dst_fmt & CAMIF_RGB24)
++ area = area * 4;
++ else if (cfg->dst_fmt & CAMIF_RGB16)
++ area = area * 2;
++ else
++ printk(KERN_ERR "Invalid target format %d\n", cfg->dst_fmt);
++
++ if ((area % PAGE_SIZE) != 0) {
++ i = area / PAGE_SIZE;
++ area = (i + 1) * PAGE_SIZE;
++ }
++
++ cfg->buffer_size = area;
++
++ switch (cfg->pp_num) {
++ case 1:
++ for (i = 0; i < 4; i++) {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf;
++ writel(cfg->img_buf[i].phys_rgb, cfg->regs + S3C_CIPRYSA(i));
++ }
++
++ break;
++
++ case 2:
++ for (i = 0; i < 4; i++) {
++ if (i == 0 || i == 2) {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf;
++ } else {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + area;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + area;
++ }
++
++ writel(cfg->img_buf[i].phys_rgb, cfg->regs + S3C_CIPRYSA(i));
++ }
++
++ break;
++
++ case 4:
++ for (i = 0; i < 4; i++) {
++ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + i * area;
++ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + i * area;
++ writel(cfg->img_buf[i].phys_rgb, cfg->regs + S3C_CIPRYSA(i));
++ }
++
++ break;
++
++ default:
++ printk(KERN_ERR "Invalid pingpong number %d\n", cfg->pp_num);
++ }
++
++ return 0;
++}
++
++static int s3c_camif_output_pp(camif_cfg_t *cfg)
++{
++ if (cfg->dma_type & CAMIF_CODEC)
++ s3c_camif_output_pp_codec(cfg);
++ else if ( cfg->dma_type & CAMIF_PREVIEW)
++ s3c_camif_output_pp_preview(cfg);
++
++ return 0;
++}
++
++static int s3c_camif_output_lcd(camif_cfg_t *cfg)
++{
++ /* To Be Implemented */
++ return 0;
++}
++
++static int s3c_camif_setup_output_path(camif_cfg_t *cfg)
++{
++ if (cfg->output_channel == CAMIF_OUT_FIFO)
++ s3c_camif_output_lcd(cfg);
++ else
++ s3c_camif_output_pp(cfg);
++
++ return 0;
++}
++
++/*************************************************************************
++ * Scaler part
++ ************************************************************************/
++static int s3c_camif_set_target_area(camif_cfg_t *cfg)
++{
++ unsigned int rect = cfg->target_x * cfg->target_y;
++
++ if (cfg->dma_type & CAMIF_CODEC)
++ writel(rect, cfg->regs + S3C_CICOTAREA);
++ else if (cfg->dma_type & CAMIF_PREVIEW)
++ writel(rect, cfg->regs + S3C_CIPRTAREA);
++
++ return 0;
++}
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++static inline int s3c_camif_set_ratio(camif_cfg_t *cfg)
++{
++ unsigned int cmd = (S3C_CICOSCCTRL_CSCR2Y_WIDE | S3C_CICOSCCTRL_CSCY2R_WIDE);
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++
++ writel(S3C_CICOSCPRERATIO_SHFACTOR_CO(cfg->sc.shfactor) | \
++ S3C_CICOSCPRERATIO_PREHORRATIO_CO(cfg->sc.prehratio) | \
++ S3C_CICOSCPRERATIO_PREVERRATIO_CO(cfg->sc.prevratio), cfg->regs + S3C_CICOSCPRERATIO);
++
++ writel(S3C_CICOSCPREDST_PREDSTWIDTH_CO(cfg->sc.predst_x) | \
++ S3C_CICOSCPREDST_PREDSTHEIGHT_CO(cfg->sc.predst_y), cfg->regs + S3C_CICOSCPREDST);
++
++ /* Differ from Preview */
++ if (cfg->sc.scalerbypass)
++ cmd |= S3C_CICOSCCTRL_SCALERBYPASS_CO;
++
++ /* Differ from Codec */
++ if (cfg->dst_fmt & CAMIF_RGB24)
++ cmd |= S3C_CICOSCCTRL_OUTRGB_FMT_RGB888;
++ else
++ cmd |= S3C_CICOSCCTRL_OUTRGB_FMT_RGB565;
++
++ if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
++ cmd |= (S3C_CICOSCCTRL_SCALEUP_H | S3C_CICOSCCTRL_SCALEUP_V);
++
++ writel(cmd | S3C_CICOSCCTRL_MAINHORRATIO_CO(cfg->sc.mainhratio) | \
++ S3C_CICOSCCTRL_MAINVERRATIO_CO(cfg->sc.mainvratio), cfg->regs + S3C_CICOSCCTRL);
++
++ } else if (cfg->dma_type & CAMIF_PREVIEW) {
++
++ writel(S3C_CIPRSCPRERATIO_SHFACTOR_PR(cfg->sc.shfactor) | \
++ S3C_CIPRSCPRERATIO_PREHORRATIO_PR(cfg->sc.prehratio) | \
++ S3C_CIPRSCPRERATIO_PREVERRATIO_PR(cfg->sc.prevratio), cfg->regs + S3C_CIPRSCPRERATIO);
++
++ writel(S3C_CIPRSCPREDST_PREDSTWIDTH_PR(cfg->sc.predst_x) | \
++ S3C_CIPRSCPREDST_PREDSTHEIGHT_PR(cfg->sc.predst_y), cfg->regs + S3C_CIPRSCPREDST);
++
++ if (cfg->dst_fmt & CAMIF_RGB24)
++ cmd |= S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB888;
++ else
++ cmd |= S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB565;
++
++ if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
++ cmd |= ((1 << 30) | (1 << 29));
++
++ writel(cmd | S3C_CIPRSCCTRL_MAINHORRATIO_PR(cfg->sc.mainhratio) | \
++ S3C_CIPRSCCTRL_MAINVERRATIO_PR(cfg->sc.mainvratio), cfg->regs + S3C_CIPRSCCTRL);
++
++ } else
++ printk(KERN_ERR "Invalid DMA type\n");
++
++ return 0;
++}
++#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++static inline int s3c_camif_set_ratio(camif_cfg_t *cfg)
++{
++ u32 cmd = 0;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++
++ writel(S3C_CICOSCPRERATIO_SHFACTOR_CO(cfg->sc.shfactor) | \
++ S3C_CICOSCPRERATIO_PREHORRATIO_CO(cfg->sc.prehratio) | \
++ S3C_CICOSCPRERATIO_PREVERRATIO_CO(cfg->sc.prevratio), cfg->regs + S3C_CICOSCPRERATIO);
++
++ writel(S3C_CICOSCPREDST_PREDSTWIDTH_CO(cfg->sc.predst_x) | \
++ S3C_CICOSCPREDST_PREDSTHEIGHT_CO(cfg->sc.predst_y), cfg->regs + S3C_CICOSCPREDST);
++
++ if (cfg->sc.scalerbypass)
++ cmd |= S3C_CICOSCCTRL_SCALERBYPASS_CO;
++
++ if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
++ cmd |= (S3C_CICOSCCTRL_SCALEUP_H | S3C_CICOSCCTRL_SCALEUP_V);
++
++ writel(cmd | S3C_CICOSCCTRL_MAINHORRATIO_CO(cfg->sc.mainhratio) | \
++ S3C_CICOSCCTRL_MAINVERRATIO_CO(cfg->sc.mainvratio), cfg->regs + S3C_CICOSCCTRL);
++
++ } else if (cfg->dma_type & CAMIF_PREVIEW) {
++
++ cmd |= S3C_CIPRSCCTRL_SAMPLE_PR;
++
++ writel(S3C_CIPRSCPRERATIO_SHFACTOR_PR(cfg->sc.shfactor) | \
++ S3C_CIPRSCPRERATIO_PREHORRATIO_PR(cfg->sc.prehratio) | \
++ S3C_CIPRSCPRERATIO_PREVERRATIO_PR(cfg->sc.prevratio), cfg->regs + S3C_CIPRSCPRERATIO);
++
++ writel(S3C_CIPRSCPREDST_PREDSTWIDTH_PR(cfg->sc.predst_x) | \
++ S3C_CIPRSCPREDST_PREDSTHEIGHT_PR(cfg->sc.predst_y), cfg->regs + S3C_CIPRSCPREDST);
++
++ if (cfg->dst_fmt & CAMIF_RGB24)
++ cmd |= S3C_CIPRSCCTRL_RGBFORMAT_24;
++
++ if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
++ cmd |= ((1 << 29) | (1 << 28));
++
++ writel(cmd | S3C_CIPRSCCTRL_MAINHORRATIO_PR(cfg->sc.mainhratio) | \
++ S3C_CIPRSCCTRL_MAINVERRATIO_PR(cfg->sc.mainvratio), cfg->regs + S3C_CIPRSCCTRL);
++
++ } else
++ printk(KERN_ERR "Invalid DMA type\n");
++
++ return 0;
++}
++#endif
++
++static int s3c_camif_calc_ratio(unsigned int src_width, unsigned int dst_width, unsigned int *ratio, unsigned int *shift)
++{
++ if (src_width >= 64 * dst_width) {
++ printk(KERN_ERR "Out of pre-scaler range: src_width / dst_width = %d (< 64)\n", src_width / dst_width);
++ return 1;
++ } else if (src_width >= 32 * dst_width) {
++ *ratio = 32;
++ *shift = 5;
++ } else if (src_width >= 16 * dst_width) {
++ *ratio = 16;
++ *shift = 4;
++ } else if (src_width >= 8 * dst_width) {
++ *ratio = 8;
++ *shift = 3;
++ } else if (src_width >= 4 * dst_width) {
++ *ratio = 4;
++ *shift = 2;
++ } else if (src_width >= 2 * dst_width) {
++ *ratio = 2;
++ *shift = 1;
++ } else {
++ *ratio = 1;
++ *shift = 0;
++ }
++
++ return 0;
++}
++
++static int s3c_camif_setup_scaler(camif_cfg_t *cfg)
++{
++ int tx = cfg->target_x, ty=cfg->target_y;
++ int sx, sy;
++
++ if (tx <= 0 || ty <= 0) {
++ printk(KERN_ERR "Invalid target size\n");
++ return -1;
++ }
++
++ sx = cfg->cis->source_x - (cfg->cis->win_hor_ofst + cfg->cis->win_hor_ofst2);
++ sy = cfg->cis->source_y - (cfg->cis->win_ver_ofst + cfg->cis->win_hor_ofst2);
++
++ if (sx <= 0 || sy <= 0) {
++ printk(KERN_ERR "Invalid source size\n");
++ return -1;
++ }
++
++ cfg->sc.modified_src_x = sx;
++ cfg->sc.modified_src_y = sy;
++
++ /* Pre-scaler control register 1 */
++ s3c_camif_calc_ratio(sx, tx, &cfg->sc.prehratio, &cfg->sc.hfactor);
++ s3c_camif_calc_ratio(sy, ty, &cfg->sc.prevratio, &cfg->sc.vfactor);
++
++#if defined(CONFIG_CPU_S3C6410)
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ if ((sx / cfg->sc.prehratio) > 720) {
++ printk(KERN_INFO "Internal preview line buffer length is 720 pixels\n");
++ printk(KERN_INFO "Decrease the resolution or adjust window offset values appropriately\n");
++ }
++ }
++#else
++ if (cfg->dma_type & CAMIF_PREVIEW) {
++ if ((sx / cfg->sc.prehratio) > 640) {
++ printk(KERN_INFO "Internal preview line buffer length is 640 pixels\n");
++ printk(KERN_INFO "Decrease the resolution or adjust window offset values appropriately\n");
++ }
++ }
++#endif
++
++ cfg->sc.shfactor = 10 - (cfg->sc.hfactor + cfg->sc.vfactor);
++
++ /* Pre-scaler control register 2 */
++ cfg->sc.predst_x = sx / cfg->sc.prehratio;
++ cfg->sc.predst_y = sy / cfg->sc.prevratio;
++
++ /* Main-scaler control register */
++ cfg->sc.mainhratio = (sx << 8) / (tx << cfg->sc.hfactor);
++ cfg->sc.mainvratio = (sy << 8) / (ty << cfg->sc.vfactor);
++
++ cfg->sc.scaleup_h = (sx <= tx) ? 1 : 0;
++ cfg->sc.scaleup_v = (sy <= ty) ? 1 : 0;
++
++ s3c_camif_set_ratio(cfg);
++ s3c_camif_set_target_area(cfg);
++
++ return 0;
++}
++
++/*************************************************************************
++ * Format part
++ ************************************************************************/
++int s3c_camif_set_source_format(camif_cis_t *cis)
++{
++ camif_cfg_t *cfg = s3c_camif_get_fimc_object(CODEC_MINOR);
++ unsigned int cmd = 0;
++
++ /* Configure CISRCFMT --Source Format */
++ if (cis->itu_fmt & CAMIF_ITU601)
++ cmd = CAMIF_ITU601;
++ else {
++ assert(cis->itu_fmt & CAMIF_ITU656);
++ cmd = CAMIF_ITU656;
++ }
++
++ cmd |= (S3C_CISRCFMT_SOURCEHSIZE(cis->source_x) | S3C_CISRCFMT_SOURCEVSIZE(cis->source_y));
++
++ /* Order422 */
++ cmd |= cis->order422;
++ writel(cmd, cfg->regs + S3C_CISRCFMT);
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ cmd = (cis->order422 >> 14);
++ writel((readl(cfg->regs + S3C_CICOCTRL) & ~(0x3 << 0)) | cmd, cfg->regs + S3C_CICOCTRL);
++#endif
++
++ return 0;
++}
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++static int s3c_camif_set_target_format(camif_cfg_t *cfg)
++{
++ unsigned int cmd = 0;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ cmd |= S3C_CICOTRGFMT_TARGETHSIZE_CO(cfg->target_x) | S3C_CICOTRGFMT_TARGETVSIZE_CO(cfg->target_y);
++
++ if (cfg->dst_fmt & CAMIF_YCBCR420) {
++ cmd |= (S3C_CICOTRGFMT_OUT422_420 | S3C_CICOTRGFMT_IN422_422);
++ writel(cmd, cfg->regs + S3C_CICOTRGFMT);
++ } else if (cfg->dst_fmt & CAMIF_YCBCR422) {
++ cmd |= (S3C_CICOTRGFMT_OUT422_422 | S3C_CICOTRGFMT_IN422_422);
++ writel(cmd, cfg->regs + S3C_CICOTRGFMT);
++ } else if ((cfg->dst_fmt & CAMIF_RGB24) || (cfg->dst_fmt & CAMIF_RGB16)) {
++ cmd |= (S3C_CICOTRGFMT_OUT422_422 | S3C_CICOTRGFMT_IN422_422);
++ writel(cmd | (1 << 29), cfg->regs + S3C_CICOTRGFMT);
++ } else
++ printk(KERN_ERR "Invalid target format\n");
++ } else {
++ assert(cfg->dma_type & CAMIF_PREVIEW);
++
++ cmd = readl(cfg->regs + S3C_CIPRTRGFMT);
++ cmd &= (S3C_CIPRTRGFMT_TARGETHSIZE_PR(0) | S3C_CIPRTRGFMT_TARGETVSIZE_PR(0));
++ cmd |= (S3C_CIPRTRGFMT_TARGETHSIZE_PR(cfg->target_x) | S3C_CIPRTRGFMT_TARGETVSIZE_PR(cfg->target_y));
++
++ writel(cmd | (2 << 30), cfg->regs + S3C_CIPRTRGFMT);
++ }
++
++ return 0;
++}
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++static int s3c_camif_set_target_format(camif_cfg_t *cfg)
++{
++ unsigned int cmd = 0;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ cmd |= (S3C_CICOTRGFMT_TARGETHSIZE_CO(cfg->target_x) | S3C_CICOTRGFMT_TARGETVSIZE_CO(cfg->target_y));
++
++ if (cfg->dst_fmt & CAMIF_YCBCR420) {
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR420OUT;
++ writel(cmd, cfg->regs + S3C_CICOTRGFMT);
++ } else if (cfg->dst_fmt & CAMIF_YCBCR422) {
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUT;
++ writel(cmd, cfg->regs + S3C_CICOTRGFMT);
++ } else if (cfg->dst_fmt & CAMIF_YCBCR422I) {
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUTINTERLEAVE;
++ writel(cmd, cfg->regs + S3C_CICOTRGFMT);
++ } else if ((cfg->dst_fmt & CAMIF_RGB24) || (cfg->dst_fmt & CAMIF_RGB16)) {
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_RGBOUT;
++ writel(cmd, cfg->regs + S3C_CICOTRGFMT);
++ } else
++ printk(KERN_ERR "Invalid target format\n");
++ } else {
++ assert(cfg->dma_type & CAMIF_PREVIEW);
++
++ cmd = readl(cfg->regs + S3C_CIPRTRGFMT);
++ cmd &= (S3C_CIPRTRGFMT_TARGETHSIZE_PR(0) | S3C_CIPRTRGFMT_TARGETVSIZE_PR(0));
++ cmd |= (S3C_CIPRTRGFMT_TARGETHSIZE_PR(cfg->target_x) | S3C_CIPRTRGFMT_TARGETVSIZE_PR(cfg->target_y));
++
++ if (cfg->dst_fmt & CAMIF_YCBCR420)
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR420OUT;
++ else if (cfg->dst_fmt & CAMIF_YCBCR422)
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUT;
++ else if (cfg->dst_fmt & CAMIF_YCBCR422I)
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUTINTERLEAVE;
++ else if ((cfg->dst_fmt & CAMIF_RGB24) || (cfg->dst_fmt & CAMIF_RGB16))
++ cmd |= S3C_CICOTRGFMT_OUTFORMAT_RGBOUT;
++ else
++ printk(KERN_ERR "Invalid target format\n");
++
++ writel(cmd, cfg->regs + S3C_CIPRTRGFMT);
++ }
++
++ return 0;
++}
++#endif
++
++/*************************************************************************
++ * Control part
++ ************************************************************************/
++int s3c_camif_control_fimc(camif_cfg_t *cfg)
++{
++ if (s3c_camif_request_memory(cfg)) {
++ printk(KERN_ERR "Instead of using consistent_alloc(). Let me use dedicated mem for DMA\n");
++ return -1;
++ }
++
++ s3c_camif_setup_input_path(cfg);
++
++ if (s3c_camif_setup_scaler(cfg)) {
++ printk(KERN_ERR "Preview scaler fault: change WinHorOfset or target size\n");
++ return 1;
++ }
++
++ s3c_camif_set_target_format(cfg);
++
++ if (s3c_camif_setup_dma(cfg)) {
++ printk(KERN_ERR "DMA burst length error\n");
++ return 1;
++ }
++
++ s3c_camif_setup_output_path(cfg);
++
++ return 0;
++}
++
++int s3c_camif_start_dma(camif_cfg_t *cfg)
++{
++ unsigned int n_cmd = readl(cfg->regs + S3C_CIIMGCPT);
++ unsigned int val;
++
++ switch(cfg->capture_enable) {
++ case CAMIF_BOTH_DMA_ON:
++ s3c_camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
++
++ /* For Codec */
++ val = readl(cfg->regs + S3C_CICOSCCTRL);
++ val |= S3C_CICOSCCTRL_COSCALERSTART;
++ writel(val, cfg->regs + S3C_CICOSCCTRL);
++
++ /* For Preview */
++ val = readl(cfg->regs + S3C_CIPRSCCTRL);
++ val |= S3C_CIPRSCCTRL_START;
++ writel(val, cfg->regs + S3C_CIPRSCCTRL);
++
++ if (!cfg->sc.scalerbypass)
++ n_cmd |= S3C_CIIMGCPT_IMGCPTEN_COSC | S3C_CIIMGCPT_IMGCPTEN_PRSC;
++
++ break;
++
++ case CAMIF_DMA_ON:
++ s3c_camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ val = readl(cfg->regs + S3C_CICOSCCTRL);
++ val |= S3C_CICOSCCTRL_COSCALERSTART;
++ writel(val, cfg->regs + S3C_CICOSCCTRL);
++
++ if (!cfg->sc.scalerbypass)
++ n_cmd |= S3C_CIIMGCPT_IMGCPTEN_COSC;
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ n_cmd |= (1 << 24);
++#endif
++ } else {
++ val = readl(cfg->regs + S3C_CIPRSCCTRL);
++ val |= S3C_CIPRSCCTRL_START;
++ writel(val, cfg->regs + S3C_CIPRSCCTRL);
++
++ if (!cfg->sc.scalerbypass)
++ n_cmd |= S3C_CIIMGCPT_IMGCPTEN_PRSC;
++ }
++
++ /* wait until Sync Time expires */
++ /* First settting, to wait VSYNC fall */
++ /* By VESA spec,in 640x480 @60Hz
++ MAX Delay Time is around 64us which "while" has.*/
++ while (S3C_CICOSTATUS_VSYNC & readl(cfg->regs + S3C_CICOSTATUS));
++ break;
++
++ default:
++ break;
++ }
++
++#if defined(CONFIG_CPU_S3C2443)
++ if (cfg->dma_type & CAMIF_CODEC) {
++ if (cfg->dst_fmt & CAMIF_RGB24)
++ n_cmd |= (3 << 25);
++ else if (cfg->dst_fmt & CAMIF_RGB16)
++ n_cmd |= (1 << 25);
++ else if (cfg->dst_fmt & CAMIF_YCBCR420)
++ n_cmd |= (2 << 25);
++ }
++#endif
++
++ val = readl(cfg->regs + S3C_CIIMGCPT);
++ val &= ~(0x7 << 29);
++ writel(val | n_cmd | S3C_CIIMGCPT_IMGCPTEN, cfg->regs + S3C_CIIMGCPT);
++
++ return 0;
++}
++
++int s3c_camif_stop_dma(camif_cfg_t *cfg)
++{
++ unsigned int n_cmd = readl(cfg->regs + S3C_CIIMGCPT);
++ unsigned int val;
++
++ switch(cfg->capture_enable) {
++ case CAMIF_BOTH_DMA_OFF:
++ val = readl(cfg->regs + S3C_CICOSCCTRL);
++ val &= ~S3C_CICOSCCTRL_COSCALERSTART;
++ writel(val, cfg->regs + S3C_CICOSCCTRL);
++
++ val = readl(cfg->regs + S3C_CIPRSCCTRL);
++ val &= ~S3C_CIPRSCCTRL_START;
++ writel(val, cfg->regs + S3C_CIPRSCCTRL);
++
++ n_cmd = 0;
++ break;
++
++ case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
++ case CAMIF_DMA_OFF:
++ if (cfg->dma_type & CAMIF_CODEC) {
++ val = readl(cfg->regs + S3C_CICOSCCTRL);
++ val &= ~S3C_CICOSCCTRL_COSCALERSTART;
++ writel(val, cfg->regs + S3C_CICOSCCTRL);
++ n_cmd &= ~S3C_CIIMGCPT_IMGCPTEN_COSC;
++
++ if (!(n_cmd & S3C_CIIMGCPT_IMGCPTEN_PRSC))
++ n_cmd = 0;
++ } else {
++ val = readl(cfg->regs + S3C_CIPRSCCTRL);
++ val &= ~S3C_CIPRSCCTRL_START;
++ writel(val, cfg->regs + S3C_CIPRSCCTRL);
++
++ n_cmd &= ~S3C_CIIMGCPT_IMGCPTEN_PRSC;
++
++ if (!(n_cmd & S3C_CIIMGCPT_IMGCPTEN_COSC))
++ n_cmd = 0;
++ }
++
++ break;
++
++ default:
++ printk(KERN_ERR "Unexpected DMA control\n");
++ }
++
++ writel(n_cmd, cfg->regs + S3C_CIIMGCPT);
++
++ if (cfg->capture_enable == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ */
++ if (cfg->dma_type & CAMIF_CODEC) {
++ val = readl(cfg->regs + S3C_CICOCTRL);
++ val |= S3C_CICOCTRL_LASTIRQEN;
++ writel(val, cfg->regs + S3C_CICOCTRL);
++ } else {
++ val = readl(cfg->regs + S3C_CIPRCTRL);
++ val |= S3C_CIPRCTRL_LASTIRQEN_ENABLE;
++ writel(val, cfg->regs + S3C_CIPRCTRL);
++ }
++ }
++
++ return 0;
++}
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++int s3c_camif_start_codec_msdma(camif_cfg_t *cfg)
++{
++ int ret = 0;
++ u32 val;
++
++ val = readl(cfg->regs + S3C_MSCOCTRL);
++ val &= ~(1 << 0);
++ writel(val, cfg->regs + S3C_MSCOCTRL);
++
++ val = readl(cfg->regs + S3C_MSCOCTRL);
++ val |= (1 << 0);
++ writel(val, cfg->regs + S3C_MSCOCTRL);
++
++ return ret;
++}
++#endif
++
++int s3c_camif_start_preview_msdma(camif_cfg_t * cfg)
++{
++ unsigned int val;
++ int ret = 0;
++
++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410)
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val &= ~(1 << 0);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++#endif
++ val = readl(cfg->regs + S3C_CIMSCTRL);
++ val |= (1 << 0);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ while((readl(cfg->regs + S3C_CIMSCTRL) & (1 << 6)) == 0);
++
++ return ret;
++}
++
++void s3c_camif_change_flip(camif_cfg_t *cfg)
++{
++ unsigned int cmd = 0;
++
++ if (cfg->dma_type & CAMIF_CODEC) {
++ cmd = readl(cfg->regs + S3C_CICOTRGFMT);
++ cmd &= ~((1 << 14) | (1 << 15));
++ cmd |= cfg->flip;
++ writel(cmd, cfg->regs + S3C_CICOTRGFMT);
++ } else {
++ /* if ROT90_Pr == 1, dma burst length must be 4 */
++ if (cfg->flip == CAMIF_ROTATE_90 || cfg->flip == CAMIF_FLIP_ROTATE_270) {
++ cmd = readl(cfg->regs + S3C_CIPRCTRL);
++ cmd &= ~(0x3ff << 14);
++ cmd |= (S3C_CICOCTRL_YBURST1_CO(4) | S3C_CICOCTRL_YBURST2_CO(4));
++ writel(cmd, cfg->regs + S3C_CIPRCTRL);
++ }
++
++ cmd = readl(cfg->regs + S3C_CIPRTRGFMT);
++ cmd &= ~(0x7 << 13);
++ cmd |= cfg->flip;
++ writel(cmd, cfg->regs + S3C_CIPRTRGFMT);
++ }
++}
++
++void s3c_camif_change_effect(camif_cfg_t *cfg)
++{
++ unsigned int val = readl(cfg->regs + S3C_CIIMGEFF);
++ val &= ~((1 << 28) | (1 << 27) | (1 << 26));
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ val |= ((1 << 31) | (1 << 30));
++#endif
++
++ switch(cfg->effect) {
++ case CAMIF_SILHOUETTE:
++ val |= S3C_CIIMGEFF_FIN_SILHOUETTE;
++ break;
++
++ case CAMIF_EMBOSSING:
++ val |= S3C_CIIMGEFF_FIN_EMBOSSING;
++ break;
++
++ case CAMIF_ART_FREEZE:
++ val |= S3C_CIIMGEFF_FIN_ARTFREEZE;
++ break;
++
++ case CAMIF_NEGATIVE:
++ val |= S3C_CIIMGEFF_FIN_NEGATIVE;
++ break;
++
++ case CAMIF_ARBITRARY_CB_CR:
++ val |= S3C_CIIMGEFF_FIN_ARBITRARY;
++ break;
++
++ case CAMIF_BYPASS:
++ default:
++ break;
++ }
++
++ writel(val, cfg->regs + S3C_CIIMGEFF);
++}
++
++int s3c_camif_do_postprocess(camif_cfg_t *cfg)
++{
++ unsigned int val= readl(cfg->regs + S3C_CIMSCTRL);
++
++ if (cfg->dst_fmt & CAMIF_YCBCR420)
++ val |= (1 << 1);
++ else
++ val &= ~(1 << 1);
++
++ val &= ~(1 << 0);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ val |= (1 << 0);
++ writel(val, cfg->regs + S3C_CIMSCTRL);
++
++ printk(KERN_INFO "Postprocessing started\n");
++
++ while((readl(cfg->regs + S3C_CIMSCTRL) & (1 << 6)) == 0);
++
++ printk(KERN_INFO "Postprocessing finished\n");
++
++ return 0;
++}
++
++int s3c_camif_set_offset(camif_cis_t *cis)
++{
++ camif_cfg_t *cfg = s3c_camif_get_fimc_object(CODEC_MINOR);
++ unsigned int h = cis->win_hor_ofst; /* Camera input offset ONLY */
++ unsigned int v = cis->win_ver_ofst; /* Camera input offset ONLY */
++ unsigned int h2 = cis->win_hor_ofst2; /* Camera input offset ONLY */
++ unsigned int v2 = cis->win_ver_ofst2; /* Camera input offset ONLY */
++
++ /*Clear Overflow */
++ writel(S3C_CIWDOFST_CLROVCOFIY | S3C_CIWDOFST_CLROVCOFICB | \
++ S3C_CIWDOFST_CLROVCOFICR | S3C_CIWDOFST_CLROVPRFICB | \
++ S3C_CIWDOFST_CLROVPRFICR, cfg->regs + S3C_CIWDOFST);
++
++ writel(0, cfg->regs + S3C_CIWDOFST);
++
++ if (!h && !v) {
++ writel(0, cfg->regs + S3C_CIWDOFST);
++ writel(0, cfg->regs + S3C_CIDOWSFT2);
++ return 0;
++ }
++
++ writel(S3C_CIWDOFST_WINOFSEN | S3C_CIWDOFST_WINHOROFST(h) | S3C_CIWDOFST_WINVEROFST(v), cfg->regs + S3C_CIWDOFST);
++ writel(S3C_CIDOWSFT2_WINHOROFST2(h) | S3C_CIDOWSFT2_WINVEROFST2(v), cfg->regs + S3C_CIDOWSFT2);
++ writel(S3C_CIDOWSFT2_WINHOROFST2(h2) | S3C_CIDOWSFT2_WINVEROFST2(v2), cfg->regs + S3C_CIDOWSFT2);
++
++ return 0;
++}
++
++void s3c_camif_set_priority(int flag)
++{
++ unsigned int val;
++
++ if (flag) {
++ irq_old_priority = readl(S3C_PRIORITY);
++ val = irq_old_priority;
++ val &= ~(3 << 7);
++ writel(val, S3C_PRIORITY);
++
++ /* Arbiter 1, REQ2 first */
++ val |= (1 << 7);
++ writel(val, S3C_PRIORITY);
++
++ /* Disable Priority Rotate */
++ val &= ~(1 << 1);
++ writel(val, S3C_PRIORITY);
++ } else
++ writel(irq_old_priority, S3C_PRIORITY);
++}
++
++/*************************************************************************
++ * Interrupt part
++ ************************************************************************/
++void s3c_camif_enable_lastirq(camif_cfg_t *cfg)
++{
++ unsigned int val;
++
++ if (cfg->capture_enable == CAMIF_BOTH_DMA_ON) {
++ val = readl(cfg->regs + S3C_CICOCTRL);
++ val |= S3C_CICOCTRL_LASTIRQEN;
++ writel(val, cfg->regs + S3C_CICOCTRL);
++
++ val = readl(cfg->regs + S3C_CIPRCTRL);
++ val |= S3C_CIPRCTRL_LASTIRQEN_ENABLE;
++ writel(val, cfg->regs + S3C_CIPRCTRL);
++ } else {
++ if (cfg->dma_type & CAMIF_CODEC) {
++ val = readl(cfg->regs + S3C_CICOCTRL);
++ val |= S3C_CICOCTRL_LASTIRQEN;
++ writel(val, cfg->regs + S3C_CICOCTRL);
++ } else {
++ val = readl(cfg->regs + S3C_CIPRCTRL);
++ val |= S3C_CIPRCTRL_LASTIRQEN_ENABLE;
++ writel(val, cfg->regs + S3C_CIPRCTRL);
++ }
++ }
++}
++
++void s3c_camif_disable_lastirq(camif_cfg_t *cfg)
++{
++ unsigned int val;
++
++ if (cfg->capture_enable == CAMIF_BOTH_DMA_ON) {
++ val = readl(cfg->regs + S3C_CICOCTRL);
++ val &= ~S3C_CICOCTRL_LASTIRQEN;
++ writel(val, cfg->regs + S3C_CICOCTRL);
++
++ val = readl(cfg->regs + S3C_CIPRCTRL);
++ val &= ~S3C_CIPRCTRL_LASTIRQEN_ENABLE;
++ writel(val, cfg->regs + S3C_CIPRCTRL);
++ } else {
++ if (cfg->dma_type & CAMIF_CODEC) {
++ val = readl(cfg->regs + S3C_CICOCTRL);
++ val &= ~S3C_CICOCTRL_LASTIRQEN;
++ writel(val, cfg->regs + S3C_CICOCTRL);
++ } else {
++ val = readl(cfg->regs + S3C_CIPRCTRL);
++ val &= ~S3C_CIPRCTRL_LASTIRQEN_ENABLE;
++ writel(val, cfg->regs + S3C_CIPRCTRL);
++ }
++ }
++}
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++void s3c_camif_clear_irq(int irq)
++{
++ camif_cfg_t *cfg = s3c_camif_get_fimc_object(CODEC_MINOR);
++ unsigned int val = 0;
++
++ if (irq == IRQ_CAMIF_C) {
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val |= (1 << 19);
++ } else if (irq == IRQ_CAMIF_P) {
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val |= (1 << 18);
++ }
++
++ writel(val, cfg->regs + S3C_CIGCTRL);
++}
++#else
++void s3c_camif_clear_irq(int irq)
++{
++}
++#endif
++
++/*************************************************************************
++ * Initialize part
++ ************************************************************************/
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++static int s3c_camif_set_gpio(void)
++{
++ s3c2410_gpio_cfgpin(S3C2440_GPJ0, S3C2440_GPJ0_CAMDATA0);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ1, S3C2440_GPJ1_CAMDATA1);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ2, S3C2440_GPJ2_CAMDATA2);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ3, S3C2440_GPJ3_CAMDATA3);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ4, S3C2440_GPJ4_CAMDATA4);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ5, S3C2440_GPJ5_CAMDATA5);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ6, S3C2440_GPJ6_CAMDATA6);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ7, S3C2440_GPJ7_CAMDATA7);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ8, S3C2440_GPJ8_CAMPCLK);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ9, S3C2440_GPJ9_CAMVSYNC);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ10, S3C2440_GPJ10_CAMHREF);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ11, S3C2440_GPJ11_CAMCLKOUT);
++ s3c2410_gpio_cfgpin(S3C2440_GPJ12, S3C2440_GPJ12_CAMRESET);
++
++ writel(0x1fff, S3C2443_GPJDN);
++
++ return 0;
++}
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++static int s3c_camif_set_gpio(void)
++{
++ gpio_set_pin(S3C_GPF5, S3C_GPF5_CAMIF_YDATA0);
++ gpio_set_pin(S3C_GPF6, S3C_GPF6_CAMIF_YDATA1);
++ gpio_set_pin(S3C_GPF7, S3C_GPF7_CAMIF_YDATA2);
++ gpio_set_pin(S3C_GPF8, S3C_GPF8_CAMIF_YDATA03);
++ gpio_set_pin(S3C_GPF9, S3C_GPF9_CAMIF_YDATA4);
++ gpio_set_pin(S3C_GPF10, S3C_GPF10_CAMIF_YDATA5);
++ gpio_set_pin(S3C_GPF11, S3C_GPF11_CAMIF_YDATA06);
++ gpio_set_pin(S3C_GPF12, S3C_GPF12_CAMIF_YDATA7);
++ gpio_set_pin(S3C_GPF2, S3C_GPF2_CAMIF_CLK);
++ gpio_set_pin(S3C_GPF4, S3C_GPF4_CAMIF_VSYNC);
++ gpio_set_pin(S3C_GPF1, S3C_GPF1_CAMIF_HREF);
++ gpio_set_pin(S3C_GPF0, S3C_GPF0_CAMIF_CLK);
++ gpio_set_pin(S3C_GPF3, S3C_GPF3_CAMIF_RST);
++
++ writel(0, S3C_GPFPU);
++
++ return 0;
++}
++#endif
++
++void s3c_camif_reset(int is, int delay)
++{
++ camif_cfg_t *cfg = s3c_camif_get_fimc_object(CODEC_MINOR);
++ unsigned int val;
++ unsigned int tmp;
++
++ switch (is) {
++ case CAMIF_RESET:
++ tmp = readl(cfg->regs + S3C_CISRCFMT);
++
++ if (tmp &= (1 << 31)) {
++ /* ITU-R BT 601 */
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val |= S3C_CIGCTRL_SWRST;
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ val |= S3C_CIGCTRL_IRQ_LEVEL;
++#endif
++ writel(val, cfg->regs + S3C_CIGCTRL);
++ mdelay(1);
++
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val &= ~S3C_CIGCTRL_SWRST;
++ writel(val, cfg->regs + S3C_CIGCTRL);
++ } else {
++ /* ITU-R BT 656 */
++ tmp = readl(cfg->regs + S3C_CISRCFMT);
++ tmp |= (1 << 31);
++ writel(tmp, cfg->regs + S3C_CISRCFMT);
++
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val |= S3C_CIGCTRL_SWRST;
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ val |= S3C_CIGCTRL_IRQ_LEVEL;
++#endif
++ writel(val, cfg->regs + S3C_CIGCTRL);
++ mdelay(1);
++
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val &= ~S3C_CIGCTRL_SWRST;
++ writel(val, cfg->regs + S3C_CIGCTRL);
++
++ tmp = readl(cfg->regs + S3C_CISRCFMT);
++ tmp &= ~(1 << 31);
++ writel(tmp, cfg->regs + S3C_CISRCFMT);
++ }
++
++ break;
++
++ case CAMIF_EX_RESET_AH:
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val |= S3C_CIGCTRL_CAMRST;
++ writel(val, cfg->regs + S3C_CIGCTRL);
++ udelay(200);
++
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val &= ~S3C_CIGCTRL_CAMRST;
++ writel(val, cfg->regs + S3C_CIGCTRL);
++ udelay(delay);
++ break;
++
++ case CAMIF_EX_RESET_AL:
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val &= ~S3C_CIGCTRL_CAMRST;
++ writel(val, cfg->regs + S3C_CIGCTRL);
++ udelay(200);
++
++ val = readl(cfg->regs + S3C_CIGCTRL);
++ val |= S3C_CIGCTRL_CAMRST;
++ writel(val, cfg->regs + S3C_CIGCTRL);
++ udelay(delay);
++ break;
++
++ default:
++ break;
++ }
++}
++
++void s3c_camif_init(void)
++{
++ s3c_camif_reset(CAMIF_RESET, 0);
++ s3c_camif_set_gpio();
++}
++
+diff --git a/drivers/media/video/s3c_camif.h b/drivers/media/video/s3c_camif.h
+new file mode 100644
+index 0000000..d4e1040
+--- /dev/null
++++ b/drivers/media/video/s3c_camif.h
+@@ -0,0 +1,404 @@
++/* drivers/media/video/s3c_camif.h
++ *
++ * Copyright (c) 2008 Samsung Electronics
++ *
++ * Samsung S3C Camera driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __S3C_CAMIF_H_
++#define __S3C_CAMIF_H_
++
++#ifdef __KERNEL__
++#include <linux/videodev.h>
++#include <linux/videodev2.h>
++#include <asm/types.h>
++#include <linux/i2c.h>
++#include <linux/video_decoder.h>
++#endif /* __KERNEL__ */
++
++#if !defined(O_NONCAP)
++#define O_NONCAP O_TRUNC
++#endif
++
++#if defined(CAMIF_DEBUG)
++#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
++#else
++#define DPRINTK(fmt, args...)
++#endif
++
++#if defined(CAMIF_DEBUG)
++#define assert(expr) \
++ if(!(expr)) { \
++ printk( "Assertion failed! %s,%s,%s,line=%d\n", \
++ #expr,__FILE__,__FUNCTION__,__LINE__); \
++ }
++#else
++#define assert(expr)
++#endif
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#define MEM_SIZE 0x08000000
++#define FIMC_VER "3.0"
++#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define MEM_SIZE 0x04000000
++#define FIMC_VER "2.3"
++#else
++#define MEM_SIZE 0x04000000
++#define FIMC_VER "2.x"
++#endif
++
++#undef FSM_ON_PREVIEW
++#define FSM_ON_CODEC
++
++#undef USE_LAST_IRQ /* turn on if pp count is 1 */
++
++#define CODEC_DEV_NAME "CAMIF_CODEC"
++#define PREVIEW_DEV_NAME "CAMIF_PREVIEW"
++
++#define CAMIF_DEV_NUM 2
++#define FIMC_CODEC_INDEX 0
++#define FIMC_PREVIEW_INDEX 1
++
++#define BURST_ERR 1
++#define RESERVED_MEM (15 * 1024 * 1024)
++#define YUV_MEM (10 * 1024 * 1024)
++#define RGB_MEM (RESERVED_MEM - YUV_MEM)
++
++#define CODEC_DEFAULT_WIDTH 640
++#define CODEC_DEFAULT_HEIGHT 480
++#define PREVIEW_DEFAULT_WIDTH 640
++#define PREVIEW_DEFAULT_HEIGHT 480
++
++#define CROP_DEFAULT_WIDTH 352
++#define CROP_DEFAULT_HEIGHT 272
++
++#define CODEC_DEFAULT_PPNUM 4
++#define PREVIEW_DEFAULT_PPNUM 4
++
++#define CODEC_MINOR 12
++#define PREVIEW_MINOR 13
++
++#define CHECK_FREQ 5
++#define INSTANT_SKIP 0
++#define INSTANT_GO 1
++
++#define ZOOM_AT_A_TIME_IN_PIXELS 32
++#define ZOOM_IN_MAX 640
++
++/* Codec or Preview Status */
++#define CAMIF_STARTED (1 << 1)
++#define CAMIF_STOPPED (1 << 2)
++#define CAMIF_INT_HAPPEN (1 << 3)
++
++/* Codec or Preview : Interrupt FSM */
++#define CAMIF_1st_INT (1 << 7)
++#define CAMIF_Xth_INT (1 << 8)
++#define CAMIF_Yth_INT (1 << 9)
++#define CAMIF_Zth_INT (1 << 10)
++#define CAMIF_NORMAL_INT (1 << 11)
++#define CAMIF_DUMMY_INT (1 << 12)
++#define CAMIF_CONTINUOUS_INT (1 << 13)
++#define CAMIF_SET_LAST_INT (1 << 14)
++#define CAMIF_STOP_CAPTURE (1 << 15)
++#define CAMIF_LAST_IRQ (1 << 16)
++#define CAMIF_PENDING_INT 0
++
++#define CAMIF_CAPTURE_SKIP_FRAMES 5
++
++/* CAMIF RESET Definition */
++#define CAMIF_RESET (1 << 0)
++#define CAMIF_EX_RESET_AL (1 << 1) /* Active Low */
++#define CAMIF_EX_RESET_AH (1 << 2) /* Active High */
++
++#define USER_EXIT (1 << 2)
++#define USER_ADD (1 << 1)
++#define SENSOR_INIT (1 << 0)
++
++#define SENSOR_MAX 255
++#define SENSOR_QSXGA_MT9P012 (1 << 13)
++#define SENSOR_QSVGA (1 << 12)
++#define SENSOR_UXGA (1 << 11)
++#define SENSOR_SVGA (1 << 10)
++#define SENSOR_SXGA_MT9P012 (1 << 5)
++#define SENSOR_SXGA (1 << 4)
++#define SENSOR_VGA (1 << 3)
++#define SENSOR_DEFAULT 0
++
++#define SENSOR_WB (1 << 9)
++#define SENSOR_AF (1 << 8)
++#define SENSOR_MIRROR (1 << 7)
++#define SENSOR_ZOOMOUT (1 << 6)
++#define SENSOR_ZOOMIN (1 << 5)
++
++/* Global Status Definition */
++#define PWANT2START (1 << 0)
++#define CWANT2START (1 << 1)
++#define BOTH_STARTED (PWANT2START | CWANT2START)
++#define P_NOT_WORKING (1 << 4)
++#define C_WORKING (1 << 5)
++#define P_WORKING (1 << 6)
++#define C_NOT_WORKING (1 << 7)
++
++#define FORMAT_FLAGS_DITHER 0x01
++#define FORMAT_FLAGS_PACKED 0x02
++#define FORMAT_FLAGS_PLANAR 0x04
++#define FORMAT_FLAGS_RAW 0x08
++#define FORMAT_FLAGS_CrCb 0x10
++
++enum camif_itu_fmt {
++ CAMIF_ITU601 = (1 << 31),
++ CAMIF_ITU656 = 0,
++};
++
++/* It is possbie to use two device simultaneously */
++enum camif_dma_type {
++ CAMIF_PREVIEW = (1 << 0),
++ CAMIF_CODEC = (1 << 1),
++};
++
++enum camif_order422 {
++ CAMIF_YCBYCR = 0,
++ CAMIF_YCRYCB = (1 << 14),
++ CAMIF_CBYCRY = (1 << 15),
++ CAMIF_CRYCBY = (1 << 15) | (1 << 14),
++};
++
++enum flip_mode {
++ CAMIF_FLIP = 0,
++ CAMIF_ROTATE_90 = (1 << 13),
++ CAMIF_FLIP_X = (1 << 14),
++ CAMIF_FLIP_Y = (1 << 15),
++ CAMIF_FLIP_MIRROR = (1 << 15) | (1 << 14),
++ CAMIF_FLIP_ROTATE_270 = (1 << 15) | (1 << 14) | (1 << 13),
++};
++
++enum camif_fmt {
++ CAMIF_YCBCR420 = (1 << 0),
++ CAMIF_YCBCR422 = (1 << 1),
++ CAMIF_YCBCR422I = (1 << 2),
++ CAMIF_RGB16 = (1 << 3),
++ CAMIF_RGB24 = (1 << 4),
++ CAMIF_RGB32 = (1 << 5),
++};
++
++enum camif_capturing {
++ CAMIF_BOTH_DMA_ON = (1 << 4),
++ CAMIF_DMA_ON = (1 << 3),
++ CAMIF_BOTH_DMA_OFF = (1 << 1),
++ CAMIF_DMA_OFF = (1 << 0),
++ CAMIF_DMA_OFF_L_IRQ = (1 << 5),
++};
++
++enum image_effect {
++ CAMIF_BYPASS,
++ CAMIF_ARBITRARY_CB_CR,
++ CAMIF_NEGATIVE,
++ CAMIF_ART_FREEZE,
++ CAMIF_EMBOSSING ,
++ CAMIF_SILHOUETTE,
++};
++
++enum input_channel{
++ CAMERA_INPUT,
++ MSDMA_FROM_CODEC,
++ MSDMA_FROM_PREVIEW,
++};
++
++enum output_channel{
++ CAMIF_OUT_PP,
++ CAMIF_OUT_FIFO,
++};
++
++typedef struct camif_performance
++{
++ int frames;
++ int framesdropped;
++ __u64 bytesin;
++ __u64 bytesout;
++ __u32 reserved[4];
++} camif_perf_t;
++
++typedef struct {
++ dma_addr_t phys_y;
++ dma_addr_t phys_cb;
++ dma_addr_t phys_cr;
++ u8 *virt_y;
++ u8 *virt_cb;
++ u8 *virt_cr;
++ dma_addr_t phys_rgb;
++ u8 *virt_rgb;
++} img_buf_t;
++
++/* this structure convers the CIWDOFFST, prescaler, mainscaler */
++typedef struct {
++ u32 modified_src_x; /* After windows applyed to source_x */
++ u32 modified_src_y;
++ u32 hfactor;
++ u32 vfactor;
++ u32 shfactor; /* SHfactor = 10 - ( hfactor + vfactor ) */
++ u32 prehratio;
++ u32 prevratio;
++ u32 predst_x;
++ u32 predst_y;
++ u32 scaleup_h;
++ u32 scaleup_v;
++ u32 mainhratio;
++ u32 mainvratio;
++ u32 scalerbypass; /* only codec */
++ u32 zoom_in_cnt;
++} scaler_t;
++
++enum v4l2_status {
++ CAMIF_V4L2_INIT = (1 << 0),
++ CAMIF_v4L2_DIRTY = (1 << 1),
++};
++
++typedef struct {
++ struct mutex lock;
++ enum camif_itu_fmt itu_fmt;
++ enum camif_order422 order422;
++ struct i2c_client *sensor;
++ u32 win_hor_ofst;
++ u32 win_ver_ofst;
++ u32 win_hor_ofst2;
++ u32 win_ver_ofst2;
++ u32 camclk; /* External Image Sensor Camera Clock */
++ u32 source_x;
++ u32 source_y;
++ u32 polarity_pclk;
++ u32 polarity_vsync;
++ u32 polarity_href;
++ u32 user; /* MAX 2 (codec, preview) */
++ u32 irq_old_priority; /* BUS PRIORITY register */
++ u32 status;
++ u32 init_sensor; /* initializing sensor */
++ u32 reset_type; /* External Sensor Reset Type */
++ u32 reset_udelay;
++ u32 zoom_in_cnt;
++} camif_cis_t;
++
++/* when App want to change v4l2 parameter,
++ * we instantly store it into v4l2_t v2
++ * and then reflect it to hardware
++ */
++typedef struct v4l2 {
++ struct v4l2_fmtdesc *fmtdesc;
++ struct v4l2_framebuffer frmbuf; /* current frame buffer */
++ struct v4l2_input *input;
++ struct v4l2_output *output;
++ enum v4l2_status status;
++
++ /* crop */
++ struct v4l2_rect crop_bounds;
++ struct v4l2_rect crop_defrect;
++ struct v4l2_rect crop_current;
++
++} v4l2_t;
++
++
++typedef struct camif_c_t {
++ struct video_device *v;
++
++ /* V4L2 param only for v4l2 driver */
++ v4l2_t v2;
++ camif_cis_t *cis; /* Common between Codec and Preview */
++
++ /* logical parameter */
++ wait_queue_head_t waitq;
++ u32 status; /* Start/Stop */
++ u32 fsm; /* Start/Stop */
++ u32 open_count; /* duplicated */
++ int irq;
++ char shortname[16];
++ u32 target_x;
++ u32 target_y;
++ scaler_t sc;
++ enum flip_mode flip;
++ enum image_effect effect;
++ enum camif_dma_type dma_type;
++
++ /* 4 pingpong Frame memory */
++ u8 *pp_virt_buf;
++ dma_addr_t pp_phys_buf;
++ u32 pp_totalsize;
++ u32 pp_num; /* used pingpong memory number */
++ img_buf_t img_buf[4];
++ enum camif_fmt src_fmt;
++ enum camif_fmt dst_fmt;
++ enum camif_capturing capture_enable;
++ camif_perf_t perf;
++ u32 cur_frame_num;
++ u32 auto_restart; /* Only For Preview */
++ int input_channel;
++ int output_channel;
++ int buffer_size;
++ void *other; /* other camif_cfg_t */
++ u32 msdma_status; /* 0 : stop, 1 : start */
++ void __iomem *regs;
++} camif_cfg_t;
++
++/* Test Application Usage */
++typedef struct {
++ int src_x;
++ int src_y;
++ int dst_x;
++ int dst_y;
++ int src_fmt;
++ int dst_fmt;
++ int flip;
++ int awb;
++ int effect;
++ int input_channel;
++ int output_channel;
++ unsigned int h_offset;
++ unsigned int v_offset;
++ unsigned int h_offset2;
++ unsigned int v_offset2;
++} camif_param_t;
++
++/* Externs */
++extern camif_cfg_t* s3c_camif_get_fimc_object(int);
++extern int s3c_camif_start_dma(camif_cfg_t *);
++extern int s3c_camif_stop_dma(camif_cfg_t *);
++extern int s3c_camif_get_frame_num(camif_cfg_t *);
++extern unsigned char* s3c_camif_get_frame(camif_cfg_t *);
++extern int s3c_camif_control_fimc(camif_cfg_t *);
++extern void s3c_camif_reset(int, int);
++extern void s3c_camif_init(void);
++extern int s3c_camif_get_fifo_status(camif_cfg_t *);
++extern void s3c_camif_enable_lastirq(camif_cfg_t *);
++extern void s3c_camif_disable_lastirq(camif_cfg_t *);
++extern void s3c_camif_change_flip(camif_cfg_t *);
++extern void s3c_camif_change_effect(camif_cfg_t *);
++extern int s3c_camif_start_codec_msdma(camif_cfg_t *);
++extern int s3c_camif_set_clock(unsigned int camclk);
++extern void s3c_camif_disable_clock(void);
++extern int s3c_camif_start_preview_msdma(camif_cfg_t *);
++extern camif_cis_t* get_initialized_cis(void);
++extern void s3c_camif_clear_irq(int);
++extern int s3c_camif_set_source_format(camif_cis_t *);
++extern void s3c_camif_register_sensor(struct i2c_client *);
++extern void s3c_camif_unregister_sensor(struct i2c_client*);
++extern int s3c_camif_setup_dma(camif_cfg_t *);
++extern void s3c_camif_init_sensor(camif_cfg_t *);
++extern int s3c_camif_set_offset(camif_cis_t *);
++extern void s3c_camif_set_priority(int);
++extern void s3c_camif_open_sensor(camif_cis_t *);
++extern void s3c_camif_set_polarity(camif_cfg_t *cfg);
++
++#endif
++
+diff --git a/drivers/media/video/samsung/3xa_sensor.c b/drivers/media/video/samsung/3xa_sensor.c
+new file mode 100644
+index 0000000..4469317
+--- /dev/null
++++ b/drivers/media/video/samsung/3xa_sensor.c
+@@ -0,0 +1,442 @@
++/*
++ * Copyright (C) 2004 Samsung Electronics
++ * SW.LEE <hitchcar@samsung.com>
++ * - based on Russell King : pcf8583.c
++ * - added smdk24a0, smdk2440
++ * - added poseidon (s3c24a0+wavecom)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Driver for FIMC2.x Camera Decoder
++ *
++ */
++
++//#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/i2c-id.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++
++//#define CAMIF_DEBUG
++
++//#include <asm/arch/registers.h>
++#include "../s3c_camif.h"
++#include "3xa_sensor.h"
++
++static struct i2c_driver sensor_driver;
++
++/* This is an abstract CIS sensor for MSDMA input. */
++
++camif_cis_t msdma_input = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_YCBYCR, /* YCRYCB */
++ camclk: 32000000, /* No effect */
++ source_x: 800,
++ source_y: 480,
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 0,
++ polarity_vsync:1,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
++ reset_udelay: 20000,
++};
++
++camif_cis_t interlace_input = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_YCBYCR, /* YCRYCB */
++ camclk: 32000000, /* No effect */
++ source_x: 720,
++ source_y: 243,
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 1,
++ polarity_vsync:0,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
++ reset_udelay: 20000,
++};
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K3AA)
++/* This is SXGA(1280x1024) camera but start from VGA(640x480) mode */
++static camif_cis_t data = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_CBYCRY, /* YCRYCB */
++ camclk: 48000000, /* No effect */
++ source_x: 640,
++ source_y: 480,
++ win_hor_ofst: 112,
++ win_ver_ofst: 72,
++ win_hor_ofst2: 112,
++ win_ver_ofst2: 72,
++ polarity_pclk: 1,
++ polarity_vsync:0,
++ polarity_href: 0,
++
++#ifdef CONFIG_CPU_S3C24A0A
++ reset_type:CAMIF_EX_RESET_AL, /* Active Low */
++#else
++ reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
++#endif
++ reset_udelay: 1000,
++};
++
++s5k3xa_t s5k3aa_regs_mirror[S5K3AA_REGS];
++
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K3BA)
++/* This is UXGA(1600x1200) camera but start from SVGA(800x600) mode */
++static camif_cis_t data = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_YCBYCR, /* YCRYCB */
++ camclk: 19000000,
++ source_x: 640,
++ source_y: 480,
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 1,
++ polarity_vsync:1,
++ polarity_href: 0,
++ reset_type: CAMIF_EX_RESET_AL, /* Ref board has inverted signal */
++ reset_udelay: 1000,
++};
++
++s5k3xa_t s5k3ba_regs_mirror[S5K3BA_REGS];
++#else
++#error No samsung CIS moudule here !
++#endif
++
++camif_cis_t* get_initialized_cis(void)
++{
++ if(data.init_sensor == 0) return NULL;
++ return &data;
++}
++
++#define CAM_ID 0x5a
++
++static unsigned short ignore[] = { I2C_CLIENT_END };
++static unsigned short normal_addr[] = { (CAM_ID >> 1), I2C_CLIENT_END };
++static unsigned short *forces[] = { NULL };
++
++static struct i2c_client_address_data addr_data = {
++ normal_i2c:normal_addr,
++ //normal_i2c_range:ignore,
++ probe:ignore,
++ //probe_range:ignore,
++ ignore:ignore,
++ //ignore_range:ignore,
++ forces:forces,
++};
++
++
++unsigned char sensor_read(struct i2c_client *client, unsigned char subaddr)
++{
++ int ret;
++ unsigned char buf[1];
++ struct i2c_msg msg = { client->addr, 0, 1, buf };
++ buf[0] = subaddr;
++
++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++ if (ret == -EIO) {
++ printk(" I2C write Error \n");
++ return -EIO;
++ }
++
++ msg.flags = I2C_M_RD;
++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++
++ return buf[0];
++}
++
++
++static int
++sensor_write(struct i2c_client *client,
++ unsigned char subaddr, unsigned char val)
++{
++ unsigned char buf[2];
++ struct i2c_msg msg = { client->addr, 0, 2, buf };
++
++ buf[0] = subaddr;
++ buf[1] = val;
++
++ return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++}
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K3AA)
++void inline sensor_init(struct i2c_client *sam_client)
++{
++ int i;
++ i = (sizeof(s5k3aa_reg)/sizeof(s5k3aa_reg[0]));
++
++ for (i = 0; i < S5K3AA_INIT_REGS; i++) {
++ sensor_write(sam_client,
++ s5k3aa_reg[i].subaddr, s5k3aa_reg[i].value);
++#if 0
++ printk(KERN_ERR "Page:[%03d] Subaddr %02x = 0x%02x\n",i,
++ s5k3aa_reg[i].subaddr,
++ s5k3aa_reg[i].value);
++#endif
++ }
++
++#ifdef YOU_WANT_TO_CHECK_IMG_SENSOR
++ for (i = 0; i < S5K3AA_INIT_REGS; i++) {
++ if (s5k3aa_reg[i].subaddr == PAGE_ADDRESS) {
++ sensor_write(sam_client,
++ s5k3aa_reg[i].subaddr,
++ s5k3aa_reg[i].value);
++
++ printk(KERN_ERR "Page: Subaddr %02x = 0x%02x\n",
++ s5k3aa_reg[i].subaddr,
++ s5k3aa_reg[i].value);
++
++
++ } else {
++ s5k3aa_regs_mirror[i].subaddr =
++ s5k3aa_reg[i].subaddr;
++ s5k3aa_regs_mirror[i].value =
++ s5k3aa_read(sam_client, s5k3aa_reg[i].subaddr);
++ printk(KERN_ERR "Subaddr %02x = 0x%02x\n",
++ s5k3aa_reg[i].subaddr,
++ s5k3aa_regs_mirror[i].value);
++ }
++ }
++#endif
++}
++
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K3BA)
++void inline sensor_init(struct i2c_client *sam_client)
++{
++ int i;
++ i = (sizeof(s5k3ba_reg)/sizeof(s5k3ba_reg[0]));
++
++ for (i = 0; i < S5K3BA_INIT_REGS; i++) {
++ sensor_write(sam_client,
++ s5k3ba_reg[i].subaddr, s5k3ba_reg[i].value);
++ }
++}
++#else
++#error No samsung CIS moudule !
++#endif
++
++static int
++s5k3xa_attach(struct i2c_adapter *adap, int addr, int kind)
++{
++ struct i2c_client *c;
++
++ c = kmalloc(sizeof(*c), GFP_KERNEL);
++ if (!c)
++ return -ENOMEM;
++
++ memset(c, 0, sizeof(struct i2c_client));
++
++ strcpy(c->name, "S5K3XA");
++ c->addr = addr;
++ c->adapter = adap;
++ c->driver = &sensor_driver;
++ c->data = &data;
++ data.sensor = c;
++
++ s3c_camif_register_sensor(c);
++
++ return i2c_attach_client(c);
++}
++
++static int sensor_attach_adapter(struct i2c_adapter *adap)
++{
++ s3c_camif_open_sensor(&data);
++
++ return i2c_probe(adap, &addr_data, s5k3xa_attach);
++}
++
++static int sensor_detach(struct i2c_client *client)
++{
++ i2c_detach_client(client);
++ s3c_camif_unregister_sensor(client);
++ return 0;
++}
++
++/* Purpose:
++ This fucntion only for SXGA Camera : 3AA
++ This fucntion only for UXGA Camera : 3BA
++*/
++static int change_sensor_size(struct i2c_client *client, int size)
++{
++ int i;
++
++ switch (size) {
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K3AA)
++ case SENSOR_VGA:
++ for (i = 0; i < S5K3AA_VGA_REGS; i++) {
++ sensor_write(client, s5k3aa_reg_vga[i].subaddr,
++ s5k3aa_reg_vga[i].value);
++ }
++ break;
++ case SENSOR_SXGA:
++ for (i = 0; i < S5K3AA_SXGA_REGS; i++) {
++ sensor_write(client, s5k3aa_reg_sxga[i].subaddr,
++ s5k3aa_reg_sxga[i].value);
++ }
++ break;
++
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K3BA)
++ case SENSOR_VGA:
++ for (i = 0; i < S5K3BA_VGA_REGS; i++) {
++ sensor_write(client, s5k3ba_reg_vga[i].subaddr,
++ s5k3ba_reg_vga[i].value);
++ }
++ break;
++
++ case SENSOR_SVGA:
++ for (i = 0; i < S5K3BA_INIT_REGS; i++) {
++ sensor_write(client, s5k3ba_reg[i].subaddr,
++ s5k3ba_reg[i].value);
++ }
++ break;
++ case SENSOR_UXGA:
++ for (i = 0; i < S5K3BA_UXGA_REGS; i++) {
++ sensor_write(client, s5k3ba_reg_uxga[i].subaddr,
++ s5k3ba_reg_uxga[i].value);
++ }
++ break;
++#else
++#error No samsung CIS moudule !
++#endif
++ default:
++ panic("3xa_sensor.c: unexpect value \n");
++ }
++
++ return 0;
++}
++
++static int change_sensor_wb(struct i2c_client *client, int type)
++{
++ printk("[ *** Page 0, 3XA Sensor White Balance Mode ***]\n");
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K3AA)
++ sensor_write(client, 0xEC, 0x0);
++ sensor_write(client, 0x30, type);
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K3BA)
++ sensor_write(client, 0xFC, 0x0);
++ sensor_write(client, 0x30, type);
++#endif
++
++ switch(type){
++ case 0:
++ default:
++ printk(" -> AWB auto mode ]\n");
++ break;
++ case 1:
++ printk(" -> Indoor 3100 mode ]\n");
++ break;
++ case 2:
++ printk(" -> Outdoor 5100 mode ]\n");
++ break;
++ case 3:
++ printk(" -> Indoor 2000 mode ]\n");
++ break;
++ case 4:
++ printk(" -> AE/AWB halt ]\n");
++ break;
++ case 5:
++ printk(" -> Cloudy(6000) mode ]\n");
++ break;
++ case 6:
++ printk(" -> Sunny(8000) mode ]\n");
++ break;
++ }
++
++ return 0;
++}
++
++static int
++sensor_command(struct i2c_client *client, unsigned int cmd, void *arg)
++{
++ switch (cmd) {
++ case SENSOR_INIT:
++ sensor_init(client);
++ printk(KERN_INFO "External Camera initialized\n");
++ break;
++
++ case USER_ADD:
++ //MOD_INC_USE_COUNT;
++ break;
++
++ case USER_EXIT:
++ //MOD_DEC_USE_COUNT;
++ break;
++
++ case SENSOR_VGA:
++ change_sensor_size(client, SENSOR_VGA);
++ break;
++
++ case SENSOR_SVGA:
++ change_sensor_size(client, SENSOR_SVGA);
++ break;
++
++ case SENSOR_SXGA:
++ change_sensor_size(client, SENSOR_SXGA);
++ break;
++
++ case SENSOR_UXGA:
++ change_sensor_size(client, SENSOR_UXGA);
++ break;
++/* Todo
++ case SENSOR_BRIGHTNESS:
++ change_sensor_setting();
++ break;
++*/
++ case SENSOR_WB:
++ printk("[ *** 3XA Sensor White Balance , No mode ***]\n");
++ change_sensor_wb(client, (int) arg);
++ break;
++
++ default:
++ panic("3xa_sensor.c : Unexpect Sensor Command \n");
++ break;
++ }
++
++ return 0;
++}
++
++static struct i2c_driver sensor_driver = {
++ .driver = {
++ .name = "s5k3xa",
++ },
++ //name:"S5K3XA",
++ .id = I2C_DRIVERID_S5K3XA,
++ //flags:I2C_DF_NOTIFY,
++ .attach_adapter = sensor_attach_adapter,
++ .detach_client = sensor_detach,
++ .command = sensor_command
++};
++
++static __init int camif_sensor_init(void)
++{
++ return i2c_add_driver(&sensor_driver);
++}
++
++
++static __init void camif_sensor_exit(void)
++{
++ i2c_del_driver(&sensor_driver);
++}
++
++module_init(camif_sensor_init)
++module_exit(camif_sensor_exit)
++
++MODULE_AUTHOR("Yeom, Youngran <yeom@samsung.com>");
++MODULE_DESCRIPTION("I2C Client Driver For Fimc3.x V4L2 Driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/media/video/samsung/3xa_sensor.h b/drivers/media/video/samsung/3xa_sensor.h
+new file mode 100644
+index 0000000..cfe6501
+--- /dev/null
++++ b/drivers/media/video/samsung/3xa_sensor.h
+@@ -0,0 +1,3298 @@
++
++#ifndef _SAMSUNG_SXGA_H_
++#define _SAMSUNG_SXGA_H_
++
++/*******************************************************************************************
++ # Display resolution standards #
++
++ QCIF: 176 x 144
++ CIF: 352 x 288
++ QVGA: 320 x 240
++ VGA: 640 x 480
++ SVGA: 800 x 600
++ XGA: 1024 x 768
++ WXGA: 1280 x 800
++ QVGA: 1280 x 960
++ SXGA: 1280 x 1024
++ SXGA+: 1400 x 1050
++ WSXGA+: 1680 x 1050
++ UXGA: 1600 x 1200
++ WUXGA: 1920 x 1200
++ QXGA: 2048 x 1536
++********************************************************************************************/
++
++//#include "../bits.h"
++
++/* Camera information
++ * FPC Label : Samsung MEGA Pixel Camera : V4220 REV06
++ * Modified by charles -Initial function of '3AA' test routine
++ * Modified and tested by YongHwui.Kim <yonghwui.kim@samsung.com> for S5K3AAEX Camera
++ */
++
++#define CHIP_DELAY 0xFF
++
++typedef struct samsung_t{
++ unsigned char subaddr;
++ unsigned char value;
++ unsigned char page;
++} s5k3xa_t;
++
++#ifdef CONFIG_CPU_S3C24A0A
++#define TRY_HIGH_CLOCK 1
++#endif
++
++ //***************************************************
++ // name: S5K3AAEX EVT2 setfile
++ // ver: v2.61
++ // history:
++ // v0.0 start from 040908 setfile
++ // v1.0 arange register
++ // v1.01 change MCLK(25Mhz) and Frame rate(7fps)
++ // v2.0 adjust register setting for 3AA EVT2
++ // - color correction, RGB shding off, hsync start position, Mirror, fps
++ // - Color Tuning, YGRPDLY
++ // v2.1 change Frame rate(7.5fps) and Total gain to x4
++ // (because of reducing visual noise at low illumination)
++ // - change BPRM AGC Max and FrameAE start
++ // improve AE speed
++ // v2.2 modify AWB G gain and solve 50hz flicker detection fail in 25MHz 7.5fps
++ // v2.3 Adjust gamma, Dark Slice, white point, Hue gain,
++ // White Balance B control, Y gain On, Digital Clamp On
++ // lower AWB G gain
++ // v2.4 Adjust AE window weight, Y Gamma, WhitePoint, Shading and BPR Max Thres.
++ // v2.41 Adjust AE/AWB window and AWB internal window boundary to decrease skin color tracking
++ // v2.411 special version for PSCDS
++ // v2.412 RGB shading off
++ // v2.5 Lens change STW to Sekonix
++ // adjust White point and Y shading Coef (RGB shading off)
++ // v2.6 New Tuning because of Full YC off and YCbCr Coef change
++ // Gamma, Dark Slice, color matrix (not use), Color suppress
++ // R Gain and DBPR agc MIN/MAX
++ // v2.61 VCK inversion(data rising)
++ //***************************************************
++ ///////////////////////////////////////////////////
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K3AA) // page 0
++// VGA : 640 x 480
++s5k3xa_t s5k3aa_reg[] =
++{
++#if 0
++{0xec,0x00},
++{0x02,0x01}, /* 0x0 : SXGA, 0x01 : VGA, 0x02:QVGA */
++{0x72,0xF0}, //MCLK is 48MHz
++{0x74,0x08}, //50Hz Flicker avoidance
++{0x76,0xb0}, //brightness
++{0x77,0xd0}, //color
++{0x79,0x05}, //brightness
++{0x7a,0x03}, //color
++
++{0xec,0x01},
++{0x8b,0x03},
++#else // Mirror
++ {0xec,0x00},
++ {0x23,0x52}, // RV/H Control
++ {0xec,0x06},
++ {0x8c,0x0b}, // in case of wrp wcp control for mirror
++ {0x8d,0x0c},
++ {0x8e,0x0b},
++ {0x8f,0x0c},
++
++ {0xec,0x00},
++ {0x34,0x0e}, // AWB Tracking Boundary Constant R_Limit High
++ /////////////////////////////
++ // Color Tunning
++
++ //White Point
++ {0x40,0x18}, //1c //18
++ {0x41,0x4b}, //4a //41 //4a
++ {0x42,0x1e}, //23 //1e
++ {0x43,0x3c}, //39 //33 //3b
++ {0x44,0x2a}, //29 //2a //2e //2b
++ {0x45,0x2e}, //2b //2c //2b //25 //2d
++
++ //Hue, Gain control
++ {0x48,0xf8}, //f0 //c0 //fe
++ {0x49,0xfe},
++ {0x4a,0x32}, //28 //03 //01
++ {0x4b,0x40},
++ {0x4c,0xfe},
++ {0x4d,0xfe},
++ {0x4e,0x50}, //0e
++ {0x4f,0x08}, //10 //d0 //10 //02
++
++ {0x50,0xf0}, //e0 //a4 //aa //e0
++ {0x51,0xfe}, //fe
++ {0x52,0x42}, //40 //28 //01
++ {0x53,0x40}, //3e
++ {0x54,0xfe},
++ {0x55,0xfe}, //fc //fe
++ {0x56,0x2a}, //6a //2e
++ {0x57,0x20}, //18 //30 //1a //32
++
++ {0x58,0xda}, //ea //ca //a4 //aa //c6
++ {0x59,0xfe}, //ec //fa
++ {0x5a,0x54}, //44 //4a //20 //30 //35 //30
++ {0x5b,0x28}, //38 //20 //1a //32
++ {0x5c,0xfe},
++ {0x5d,0xfe},
++ {0x5e,0x4a}, //7e //7a
++ {0x5f,0x20}, //40 //18 //08 //20 //30 //3a //2a //42
++
++ {0x6c,0x10}, // AE Target
++ {0x77,0xea}, // Color Gain
++ {0x79,0xfe}, // White balance R control
++ {0x7a,0x01}, // White balance B control
++ {0x83,0xc0}, // Color suppress
++ //s8a04 // unstable diff
++
++ ///////////////////////////////////////////////////
++ // page 1
++ {0xec,0x01},
++ {0x8b,0x21}, //V Output Sync inversion, Full_YC off,SCK656_INV_R
++ {0x6a,0x07}, //Y,Cr first ITU R-601 format
++
++ {0xec,0x03},
++ {0x06,0x07},
++
++ {0xec,0x04},
++ {0x06,0x07},
++
++ {0xec,0x01},
++ {0x2d,0x15}, //Adjust YGRPDLY 3clk->0clk
++
++ /// Color Matrix
++ //s107e
++ //s12fe
++ //s187e //a0
++
++ {0x1c,0xd0}, // Highlight Suppress Reference
++ /////////////////////////////
++ // gamma : 1.800000
++ //Y Gamma
++ {0x2e,0x08},
++ {0x2f,0x18},
++ {0x30,0x26},
++ {0x31,0x70}, //60
++ {0x32,0xf0}, //e0
++ {0x33,0x94}, //90
++ {0x34,0x70}, //b0
++ {0x35,0xbc}, //80
++ {0x36,0x00},
++ {0x37,0x1b},
++
++ // Dark Slice
++ //s4018 // Black Balance Red
++ //s4118 //fe // Black Balance Blue
++ //s4211 //fa // Black Balance Green
++
++ {0x41,0xfe}, // Black Balance Blue
++ {0x42,0xfa}, // Black Balance Green
++
++ {0x48,0xee}, // YCrCb Coef
++ {0x49,0xf7},
++
++ //C Gamma
++ {0x55,0x08}, //08
++ {0x56,0x18}, //18
++ {0x57,0x26}, //26
++ {0x58,0x60}, //70 //60
++ {0x59,0xf0}, //e0
++ {0x5a,0xa9}, //94 //90
++ {0x5b,0x60}, //3b //70 //7b //b0
++ {0x5c,0x50}, //96 //bc //5a //80
++ {0x5d,0x00}, //00
++ {0x5e,0x1b}, //1b
++
++ {0x69,0x0f}, // VCK inversion(data rising)
++ {0xec,0x03},
++ {0x05,0x0f},
++ {0xec,0x04},
++ {0x05,0x0f},
++
++ {0xec,0x01},
++ //adjust AE window
++ {0x97,0x18},
++ {0x9a,0xe0},
++ {0x9c,0x20},
++ {0x9e,0xe8},
++
++ {0xec,0x06},
++ {0x00,0x18},
++ {0x02,0xe0},
++ {0x04,0x20},
++ {0x06,0xe8},
++
++ //adjust AWB window
++ {0xec,0x01},
++ {0xa0,0x5a},
++ {0xa2,0xd8},
++ {0xa4,0x33},
++ {0xa6,0xba},
++
++ {0xec,0x06},
++ {0x08,0x5a},
++ {0x0a,0xd8},
++ {0x0c,0x33},
++ {0x0e,0xba},
++
++ {0xec,0x01},
++ {0xaa,0xe0}, // For AWB, High Threshold Value of Y signal
++ {0xab,0x30}, // For AWB, Low Threshold Value of Y signal
++
++ /// Pixel Filter
++ {0xac,0x80}, // AWB B-G Low Threshold
++ {0xad,0x80}, // AWB B-G High Threshold
++ {0xae,0x80}, // AWB R-G Low Threshold
++ {0xaf,0x80}, // AWB R-G Low Threshold
++ {0xb0,0x60}, // AWB R-G,B-G High Threshold
++ {0xb1,0x80}, // AWB R-G,B-G Low Threshold
++
++ ///////////////////////////////////////////////////
++ //// page 2
++ {0xec,0x02},
++ {0x05,0x0b},
++ {0x07,0x0b},
++ //s1f13 //Adjust Global Gain for 20Mhz
++ {0x26,0x86}, //ADLC Set
++ {0x2d,0x00}, //APS Bias Current 6uA ---> 1uA for SHBN & HN reduce
++ {0x2e,0x50}, //Ramp Gain
++ {0x2f,0x30}, //Ramp Bias Current for SHBN reduce
++ {0x30,0x05}, //for reducing noise... switch cap
++
++ ///////////////////////////////////////////////////
++ //// page 5
++ // Shading
++ {0xec,0x05},
++ {0x00,0x0d}, // Shading Old(Y shading) ON & Shading New(RGB Shading) OFF
++ //s000f // Shading Old(Y shading) & Shading New(RGB Shading)
++
++ ///RGB Shading
++ {0x05,0x05}, // R Shading of RGB Shading
++ {0x06,0x05},
++ {0x07,0x05},
++ {0x08,0x05},
++ {0x09,0x00}, // GR Shading of RGB Shading
++ {0x0a,0x00},
++ {0x0b,0x00},
++ {0x0c,0x00},
++ {0x0d,0x00}, // GB Shading of RGB Shading
++ {0x0e,0x00},
++ {0x0f,0x00},
++ {0x10,0x00},
++ {0x11,0x00}, // B Shading of RGB Shading
++ {0x12,0x00},
++ {0x13,0x00},
++ {0x14,0x00},
++
++ /// Y Shading
++ {0x2d,0xd0}, //e0 //d6 //e0
++ {0x2e,0xb0}, //c0 //aa //c0
++ {0x2f,0xa0}, //95 //a0
++ {0x30,0x88}, //86 //88 //80
++ {0x31,0x88}, //86 //88 //80
++ {0x32,0xa0}, //95 //a0
++ {0x33,0xb0}, //c0 //aa //c0
++ {0x34,0xd0}, //e0 //d6 //e0
++
++ {0x35,0xd0}, //e0
++ {0x36,0xb0}, //ba //a6
++ {0x37,0x98}, //94 //90
++ {0x38,0x88}, //80
++ {0x39,0x88}, //80
++ {0x3a,0x98}, //94 //90
++ {0x3b,0xb0}, //ba //a6
++ {0x3c,0xd0}, //e0
++
++ ////////////////////////////////////////////////
++ // page 7
++ {0xec,0x07},
++ {0x11,0xfe}, // GGain_Offset
++ {0x17,0x40}, // lower AWB Ggain because G is stronger than R/B
++ //s1742 // modify AWB Ggain to make <1.46> =0x40(x1)
++
++ {0x3c,0x00}, //adjust AWB internal window boundary to decrease skin color tracking
++
++ // to dectect 50Hz flicker in 25Mhz 7.5fps
++ {0x60,0x10}, // adjust flicker thres
++ {0x62,0x11}, // adjust edge detection boundary
++ {0x63,0x04},
++
++ {0x69,0x10}, // for mirror
++ {0x70,0x80}, // BLC Off
++
++ // AE weight
++ {0x80,0x10}, //40
++ {0x81,0x00}, //10
++ {0x82,0x01}, //10
++ {0x83,0x02}, //10
++ {0x84,0x02}, //30
++
++ ///////////////////////////////
++ // control start position(hsync hblank )
++ // to remove broken pixel width on left side
++ {0xec,0x01},
++ {0x78,0x3d}, // HBLK START
++ {0x82,0x3d}, // HS656 START
++
++ {0xec,0x03},
++ {0x0e,0x3d},
++ {0x18,0x3d},
++
++ {0xec,0x04},
++ {0x0e,0x3d},
++ {0x18,0x3d},
++
++ ////////////////////////////
++ // Control Gain
++ {0xec,0x00},
++ {0x78,0x60}, //Total gain x4 (Only Analog x4)
++ {0x2d,0x5a}, //Frame AE start
++ {0x82,0x5A}, //Color Suppress AGC Min
++
++ ////////////////////////////
++ // Control BPRM
++ // CIS BPR always off
++ {0xec,0x00},
++ {0x7e,0x87}, //Color Suppress On, Y gain On, Digital clamp On, DBPRM On
++ {0x86,0x01}, //DBPR AGC MIN
++ {0x87,0x00}, //DBPRM THRES. MIN
++ //s8710 //DBPRM THRES. MIN.. optimize between BPR and Pseudo color
++ {0xec,0x07},
++ {0x21,0x90}, //50 //DBPRM THRES. MAX
++ {0x22,0x20}, //DBPR AGC MAX
++
++ ////////////////////////////
++ // improve AE speed
++ {0xec,0x00},
++ {0x92,0x80}, //AE ratio high
++ {0xec,0x07},
++ {0x10,0x30}, // AGC predict ON
++
++ //*********************************************************
++ // If you change MCLK or Frame rate, you change below register
++ //*********************************************************
++ /////////////////////////////
++ ///Adjust Global Gain
++ {0xec,0x02},
++ {0x1f,0x0f}, // if MCLK is 25Mhz
++
++ /////////////////////////////
++ ///Flicker setting
++ {0xec,0x00},
++ {0x72,0xF0}, // if MCLK is 25Mhz
++
++ /////////////////////////////
++ // Adjust Vblank depth
++ /// Make 25Mhz 7.5fps
++ {0xec,0x02},
++ {0x17,0x00},
++ {0x18,0x8c},
++
++ {0xec,0x04},
++ {0x01,0x00},
++ {0x02,0x8c},
++ //*********************************************************
++
++ /////////////////////////////
++ ///Flicker setting
++ {0xec,0x00},
++ {0x74,0x18}, // Auto Flicker start 60hz for 7.5fps
++
++ /////////////////////////////
++ // Frame AE
++ {0xec,0x00},
++ //{0x73,0x11}, // frame 1/2 jassi
++ {0x73,0x21}, // frame 1/3
++
++ /////////////////////// 1213 setting
++ {0xec,0x01}, //sdtv
++ {0x19,0x4d},
++ {0x1a,0x96},
++ {0x1b,0x1d},
++ {0x4a,0x41},
++ {0x48,0xea},
++ {0x47,0x41},
++ {0x49,0xf5},
++
++ {0xec,0x00},
++ {0x44,0x2e},
++ {0x45,0x2c},
++
++ {0x5f,0x18},
++
++ {0xec,0x07},
++ {0x21,0x9c},
++ {0x22,0x58},
++
++ {0xec,0x00}, // bpr
++ {0x87,0x00},
++ {0x86,0x48},
++
++ {0xec,0x01},
++ {0x8b,0x23}, // Full YC
++
++ {0x35,0xff}, //Y gamma
++ {0x5c,0xff}, //C gamma
++
++
++ {0xec,0x00}, //Bally adatpion
++ //{0x74,0x04}, // Auto Flicker start 60hz for 7.5fps jassi
++ {0x74,0x08}, // Auto Flicker start 60hz for 7.5fps
++ //{0x73,0x51}, jassi
++ {0x73,0x21},
++// {0x72,0x78}, //MCLK 24Mhz jassi
++// {0x72,0xA0}, //MCLK 32Mhz
++ {0x72,0xF0}, //MCLK 48Mhz
++ {0xec,0x04},
++ {0x01,0x05}, //4fps
++ {0x02,0x8c},
++ {0xec,0x03},
++ {0x57,0x03},
++ {0x58,0x09},
++ {0x5b,0x02},
++ {0x5c,0x84},
++ {0x5f,0x02},
++ {0x60,0x84},
++ {0x69,0x02},
++ {0x6a,0x84},
++ {0x63,0x02},
++ {0x64,0x04},
++ {0x6d,0x02},
++ {0x6e,0x04},
++ {0x65,0x02},
++ {0x66,0x10},
++ {0x6f,0x02},
++ {0x70,0x10},
++ {0xec,0x03},
++ {0x5e,0x38},
++ {0x52,0x48}, //30fps
++ {0xec,0x02},
++ {0x02,0x0d}, //9bit
++ {0x1f,0x07}, //global gain
++ {0xec,0x07},
++ {0x63,0x0a},
++ {0xec,0x03},
++ {0x56,0x04}, // 04->05 05->04
++ {0xec,0x04},
++ {0x06,0x05}, // 04->05
++
++ {0xec,0x07}, //bpr by pyo
++ {0x21,0x9c},
++ {0x22,0x58},
++ {0xec,0x00}, //<============ page 0
++ {0x87,0x00},
++ {0x86,0x48}, //bpr by pyo
++
++ {0x02,0x31}, //<============ page 0 : addr.- 0x2 : value - 1 [VGA(640x480)]
++
++ {0xec,0x01},
++ {0x21,0x40},
++ {0x22,0x40},
++ {0x23,0x00},
++ {0x24,0x00},
++ {0xec,0x00},
++ {0x6d,0x00},
++ {0x6c,0xf0},
++ {0x86,0x10},
++ {0xec,0x07},
++ {0x9d,0x10},
++ {0xec,0x00},
++ {0x75,0x04},
++ {0x96,0x06},
++ {0x78,0x68},
++ {0x66,0x02},
++ {0x94,0x03},
++ {0x97,0x03},
++};
++#endif
++
++#elif defined(CONFIG_VIDEO_SAMSUNG_S5K3BA)
++
++// For SVGA (800 x 600)
++s5k3xa_t s5k3ba_reg[] =
++{
++//[[CAMIF_POWER_UP]]
++{0xfc, 0x02},
++{0x52, 0x86}, // PLL M
++//{0x52, 0x80}, // PLL M
++//{0x52, 0x64}, // PLL M
++{0xfc, 0x01},
++{0x04, 0x03}, // Original ARM Clock Divider
++//{0x04, 0x02},
++{0xfc, 0x02},
++//{0x50, 0x5B}, //Original
++{0x50, 0x59}, // Input Clock 25Mhz
++{0xfc, 0x02},
++{0x30, 0x84}, // Analog offset
++{0x3d, 0x26}, // ADLC enable
++{0x4f, 0x7a}, // I/O driving strength 7mA
++//s45c0 // CDS S1S timing for HN Á¦°Å <- CC
++{0xfc, 0x03},
++//{0x00, 0x02},
++//s2d03 //02
++{0xfc, 0x07},
++{0x58, 0x10},
++{0x59, 0x00},
++{0x5a, 0x00},
++{0x5b, 0x6c},
++{0xfc, 0xf0},
++{0x00, 0x40},
++{0xfc, 0x01},
++//{0x02, 0x02}, // YCbCr Order
++//sfc05
++//s112e // Cb coef.
++{0xfc, 0x05}, // YCbCr Coef
++{0x11, 0x2e},
++//s113d //2e // Blue saturation
++{0x75, 0x05}, // scaler input vsync start
++{0x8c, 0xb1}, // CLIP V size L
++{0x8d, 0x04}, // CLIP V size H
++{0x77, 0xb1}, // scaler input vsync height
++{0xfc, 0x03}, // UXGA Size
++{0x12, 0x05},
++{0x26, 0xb1},
++{0x27, 0x04},
++{0x14, 0xb1},
++///////////////////////////////////////////
++{0xfc, 0x02},
++{0x4a, 0xc1}, // SC type
++{0x37, 0x16}, // SC type
++{0x47, 0xc4}, // r-ramp by chin
++//////////////////////////////////////////
++
++//////////////////////////////////////////
++// Must Mirro Function
++{0xfc, 0x07},
++{0x69, 0x00}, // Mirror XOR
++{0xfc, 0x00},
++{0x23, 0x91}, // Disable wcp/wrd
++// End Mirror
++//////////////////////////////////////////
++
++/////////////////////////////////////////
++// Special Effect Cr Cb setting
++{0xfc, 0x07},
++{0x30, 0x20},
++{0x31, 0xc0},
++{0x32, 0xc0},
++{0x33, 0x40},
++// End
++/////////////////////////////////////////
++
++// AWB Window Area
++//sfc01
++//sc401
++//sc54e
++//sc76e
++
++// color matrix
++{0xfc, 0x01},
++{0x51, 0x06}, //06
++{0x52, 0x68}, //68 //68
++{0x53, 0xFE}, //FE
++{0x54, 0x23}, //23
++{0x55, 0xFF}, //FF
++{0x56, 0x88}, //88
++ //
++{0x57, 0xFE}, //FE
++{0x58, 0x00}, //00
++{0x59, 0x07}, //07
++{0x5A, 0x1F}, ////1F //1F //1F
++{0x5B, 0xFE}, //FE
++{0x5C, 0xF3}, //F3
++ //
++{0x5D, 0xFF}, //FF
++{0x5E, 0x00}, //00
++{0x5F, 0xFC}, //FC
++{0x60, 0x6F}, //df //6F //6F
++{0x61, 0x08}, //08
++{0x62, 0x9F}, //bf //9F //9F
++
++//Edge
++{0xfc, 0x05},
++{0x2c, 0x0f}, //0a //10 //14 // positive gain
++{0x30, 0x0c}, //10 //14 // negative edge gain
++{0x34, 0x12}, /////// // APTCLP
++{0x35, 0x06}, //0c //0a // APTSC
++{0x36, 0x0b}, // ENHANCE
++{0x3f, 0x00}, // NON-LIN
++{0x45, 0x30}, // EGREF
++{0x47, 0x60}, // LLREF
++{0x48, 0x08}, // by chin
++{0x49, 0x39}, // CSSEL EGSEL CS_DLY by
++{0x47, 0x00},
++{0x40, 0x41}, // Y delay
++//Gamma 2
++{0xfc, 0x01},
++{0x6F, 0x08}, // R
++{0x70, 0x10},
++{0x71, 0x40},
++{0x72, 0xd0},
++{0x73, 0x00},
++{0x74, 0xa8},
++{0x75, 0x08},
++{0x76, 0x68},
++{0x77, 0xba},
++{0x78, 0x6a},
++{0x79, 0x08},
++{0x7A, 0x4a},
++{0x7B, 0x6c},
++{0x7C, 0x8a},
++{0x7D, 0xff},
++{0x7E, 0x9e},
++{0x7F, 0xb0},
++{0x80, 0xc0},
++{0x81, 0xd0},
++{0x82, 0xff},
++{0x83, 0xde},
++{0x84, 0xe6},
++{0x85, 0xea},
++{0x86, 0xff},
++{0x87, 0x08}, //G
++{0x88, 0x40},
++{0x89, 0x78},
++{0x8A, 0xf0},
++{0x8B, 0x00},
++{0x8C, 0xb0},
++{0x8D, 0x10},
++{0x8E, 0x68},
++{0x8F, 0xb6},
++{0x90, 0x6a},
++{0x91, 0x04},
++{0x92, 0x30},
++{0x93, 0x53},
++{0x94, 0x74},
++{0x95, 0xff},
++{0x96, 0x8d},
++{0x97, 0xa2},
++{0x98, 0xb6},
++{0x99, 0xc8},
++{0x9A, 0xff},
++{0x9B, 0xd6},
++{0x9C, 0xe0},
++{0x9D, 0xea},
++{0x9E, 0xff},
++{0x9F, 0x08}, //B
++{0xA0, 0x40},
++{0xA1, 0x78},
++{0xA2, 0xf0},
++{0xA3, 0x00},
++{0xA4, 0xb0},
++{0xA5, 0x10},
++{0xA6, 0x68},
++{0xA7, 0xba},
++{0xA8, 0x6a},
++{0xA9, 0x08},
++{0xAA, 0x3a},
++{0xAB, 0x60},
++{0xAC, 0x80},
++{0xAD, 0xff},
++{0xAE, 0x95},
++{0xAF, 0xa8},
++{0xB0, 0xba},
++{0xB1, 0xcc},
++{0xB2, 0xff},
++{0xB3, 0xd8},
++{0xB4, 0xe2},
++{0xB5, 0xea},
++{0xB6, 0xff},
++{0xfc, 0x00}, // Hue Gain
++{0x48, 0x44},
++{0x49, 0x60},
++{0x4a, 0x00},
++{0x4b, 0x18},
++{0x4c, 0x58},
++{0x4d, 0x70}, //60
++{0x4e, 0x00},
++{0x4f, 0x00},
++{0x50, 0x44},
++{0x51, 0x60},
++{0x52, 0x00},
++{0x53, 0x18},
++{0x54, 0x58},
++{0x55, 0x70}, //60
++{0x56, 0x00},
++{0x57, 0x00},
++{0x58, 0x44},
++{0x59, 0x60},
++{0x5a, 0x00},
++{0x5b, 0x18},
++{0x5c, 0x50},
++{0x5d, 0x48},
++{0x5e, 0x08},
++{0x5f, 0x05}, //00
++//ISP_tuning
++{0xfc, 0x00},
++{0x01, 0x00}, // I2C hold mode off
++//s2222 // I2C master ctrl.
++//s2d5a // frame AE start 50
++{0x3e, 0x10}, // Y_min Y min level limit value of AWB ODM
++{0xfc, 0x01},
++{0x00, 0x00}, // ISP BPR Off
++{0x0c, 0x02}, // Full YC
++{0xc8, 0xe0}, //f0 // AWB Y Max
++////////////////////////////////
++// 2005.07.17 cspyo set
++///////////////////////////////
++{0xfc, 0x00},
++{0x24, 0x45}, // zoom skip 5fps
++{0x6c, 0xb8}, //ba //d2 //d8 // AE target
++{0x6d, 0x00}, //
++{0x78, 0x60}, // AGC Max
++{0x79, 0xfb}, //fc // R gain
++{0x7a, 0x03}, // B gain
++{0x81, 0x00}, // AWB G gain suppress disable
++{0x29, 0x04}, // Y level
++{0x2a, 0x10}, //50 // Y level
++{0x2b, 0x04}, // color level H
++{0x2c, 0x00}, //20 // color level L
++{0xfc, 0x07},
++{0x11, 0x00}, // G offset
++{0x37, 0x00}, // Flicker Add
++{0xfc, 0x00},
++{0x72, 0xa0}, // Flicker for 32MHz
++{0x74, 0x08}, // flicker 60Hz
++{0xfc, 0x05},
++{0x64, 0x02}, // Darkslice R
++{0x65, 0xfe}, // Darkslice G
++{0x66, 0xff}, // Darkslice B
++////////////////////////////////////
++{0xfc, 0x00},
++{0x7e, 0xfc},
++//s7e8c //NR GrGb off
++// [7]: BPR [6]:Noise Filter(1D/NR) [4]: GrGb Enable [3]:BPR Data Threshold
++// [2]: color suppress [1]: Y gain suppress [0]: Digital Clamp
++///////////////////////////////////
++////////////////////////////////////
++// GrGb Correction setting
++{0xfc, 0x01},
++{0x44, 0x0c},
++//s4400
++/// [4]: GrGb full [3]: GrGb On
++/// [2]: GrGb Rb On
++{0xfc, 0x0b},
++{0x21, 0x00}, // Start AGC
++{0x22, 0x10}, // AGCMIN
++{0x23, 0x50}, // AGCMAX
++{0x24, 0x18}, //0e //12 //17 // G Th AGCMIN(23d)
++{0x25, 0x32}, // G Th AGCMAX(50d)
++{0x26, 0x18}, //0e //12 //17 // RB Th AGCMIN
++{0x27, 0x32}, // RB Th AGCMAX
++// GrGb Correction setting End
++///////////////////////////////////
++// BPR Setting
++{0xfc, 0x01},
++{0x3f, 0x00}, // setting because S/W bug
++{0xfc, 0x0b},
++{0x0b, 0x00}, // ISP BPR On Start
++{0x0c, 0x00}, // Th13 AGC Min
++{0x0d, 0x40}, //5a // Th13 AGC Max
++{0x0e, 0x01}, //00 // Th1 Max H for AGCMIN
++{0x0f, 0xff}, //c0 // Th1 Max L for AGCMIN
++{0x10, 0x00}, // Th1 Min H for AGCMAX
++{0x11, 0x10}, //00 // Th1 Min L for AGCMAX
++{0x12, 0xff}, // Th3 Max H for AGCMIN
++{0x13, 0xff}, // Th3 Max L for AGCMIN
++{0x14, 0xff}, // Th3 Min H for AGCMAX
++{0x15, 0xff}, // Th3 Min L for AGCMAX
++///////////////////////////////////////////
++// NR Setting
++{0xfc, 0x01},
++{0x4b, 0x01}, // NR Enable
++//s4b00 // NR Enable
++{0xfc, 0x0b},
++{0x28, 0x00}, //NR Start AGC
++{0x29, 0x00}, // SIG Th AGCMIN H
++{0x2a, 0x0a}, //14 // SIG Th AGCMIN L
++{0x2b, 0x00}, // SIG Th AGCMAX H
++{0x2c, 0x0a}, //14 // SIG Th AGCMAX L
++{0x2d, 0x00}, // PRE Th AGCMIN H
++{0x2e, 0x70}, //50 //64 // PRE Th AGCMIN L(100d)
++{0x2f, 0x01}, // PRE Th AGCMAX H(300d)
++{0x30, 0x2c}, // PRE Th AGCMAX L
++{0x31, 0x00}, // POST Th AGCMIN H
++{0x32, 0x70}, //50 //64 // POST Th AGCMIN L(100d)
++{0x33, 0x01}, // POST Th AGCMAX H(300d)
++{0x34, 0x2c}, // POST Th AGCMAX L
++// NR Setting End
++////////////////////////////////
++// Color suppress setting
++{0xfc, 0x0b},
++{0x08, 0x50}, // C suppress AGC MIN
++{0x09, 0x04}, // C suppress MIN H
++{0x0a, 0x00}, // C suppress MIN L
++// C Suppress Setting End
++///////////////////////////////
++// 1D Y LPF Filter
++{0xfc, 0x01},
++//s05e0 // Default s60
++{0x05, 0x60}, // Default s60
++//[7]: Y LPF filter On [6]: Clap On
++{0xfc, 0x0b},
++{0x35, 0x00}, // YLPF Start AGC
++{0x36, 0x50}, // YLPF01 AGCMIN
++{0x37, 0x50}, // YLPF01 AGCMAX
++{0x38, 0x00}, // YLPF SIG01 Th AGCMINH
++{0x39, 0x00}, // YLPF SIG01 Th AGCMINL
++{0x3a, 0x00}, // YLPF SIG01 Th AGCMAXH
++{0x3b, 0xa0}, // YLPF SIG01 Th AGCMAXH
++{0x3c, 0x50}, // YLPF02 AGCMIN
++{0x3d, 0x50}, // YLPF02 AGCMAX
++{0x3e, 0x00}, // YLPF SIG02 Th AGCMINH
++{0x3f, 0x00}, // YLPF SIG02 Th AGCMINL
++{0x40, 0x00}, // YLPF SIG02 Th AGCMAXH
++{0x41, 0xa0}, // YLPF SIG02 Th AGCMAXH
++// Y LPF Filter setting End
++//------------------------------------------------------------------
++/// Set File
++/// - S5K3BAFB_CRF_June02+yihan_050707.xls generates
++/// - date : 2005-07-08
++///------------------------------------------------------------------
++/// Page : ISP Page 9
++{0xfc, 0x09},
++{0x00, 0x02}, // shading on
++{0x01, 0x06}, // size
++{0x02, 0x40},
++{0x03, 0x04},
++{0x04, 0xB0},
++{0x05, 0x03}, // shading center R
++{0x06, 0x19},
++{0x07, 0x02},
++{0x08, 0x75},
++{0x09, 0x03}, // shading center R
++{0x0A, 0x1b},
++{0x0b, 0x02},
++{0x0c, 0x7a},
++{0x0d, 0x03}, // shading center R
++{0x0e, 0x09},
++{0x0f, 0x02},
++{0x10, 0x7d},
++{0x35, 0x00}, // shading R
++{0x36, 0xff},
++{0x37, 0x01},
++{0x38, 0x06},
++{0x39, 0x01},
++{0x3A, 0x1d},
++{0x3B, 0x01},
++{0x3C, 0x44},
++{0x3D, 0x01},
++{0x3E, 0x5d},
++{0x3F, 0x01},
++{0x40, 0x7c},
++{0x41, 0x01},
++{0x42, 0x97},
++{0x43, 0x01},
++{0x44, 0xba},
++{0x45, 0x01}, // shading G
++{0x46, 0x01},
++{0x47, 0x01},
++{0x48, 0x08},
++{0x49, 0x01},
++{0x4A, 0x1d},
++{0x4B, 0x01},
++{0x4C, 0x40},
++{0x4D, 0x01},
++{0x4E, 0x58},
++{0x4F, 0x01},
++{0x50, 0x73},
++{0x51, 0x01},
++{0x52, 0x8a},
++{0x53, 0x01},
++{0x54, 0xa6},
++{0x55, 0x00}, // shading B
++{0x56, 0xff},
++{0x57, 0x01},
++{0x58, 0x05},
++{0x59, 0x01},
++{0x5A, 0x1a},
++{0x5B, 0x01},
++{0x5C, 0x3c},
++{0x5D, 0x01},
++{0x5E, 0x52},
++{0x5F, 0x01},
++{0x60, 0x6e},
++{0x61, 0x01},
++{0x62, 0x8b},
++{0x63, 0x01},
++{0x64, 0xb3},
++// sub-sampling
++{0xfc, 0x03},
++//{0x2d, 0x01}, // UXGA YCrCb Order
++{0x2d, 0x06}, // UXGA YCrCb Order
++{0x12, 0x05},
++{0x26, 0xb1},
++{0x27, 0x04},
++{0x14, 0xb1},
++{0xfc, 0x04},
++{0x14, 0xb1},
++{0x72, 0x05}, // H2 V1
++{0x74, 0xb1},
++{0xa2, 0x05}, // H1 V2
++{0xa3, 0x02},
++{0xa4, 0x59},
++{0xa7, 0x59},
++{0xa8, 0x02},
++{0xae, 0x59},
++{0xaf, 0x02},
++{0xb6, 0x59},
++{0xb7, 0x02},
++{0xd2, 0x05}, // H2 V2
++{0xd3, 0x02},
++{0xd4, 0x59},
++{0xd7, 0x59},
++{0xd8, 0x02},
++{0xde, 0x59},
++{0xdf, 0x02},
++{0xe6, 0x59},
++{0xe7, 0x02},
++{0xfc, 0x14}, // H4 V1
++{0x05, 0x98},
++{0x0e, 0x02},
++{0x12, 0x05},
++{0x13, 0x04},
++{0x14, 0xb1},
++{0x17, 0xb0},
++{0x18, 0x04},
++{0x1e, 0xb0},
++{0x1f, 0x04},
++{0x26, 0xb1},
++{0x27, 0x04},
++{0x35, 0x98}, // H4 V4
++{0x3e, 0x02},
++{0x42, 0x05},
++{0x43, 0x01},
++{0x44, 0x2d},
++{0x47, 0x2d},
++{0x48, 0x01},
++{0x4e, 0x2d},
++{0x4f, 0x01},
++{0x56, 0x2e},
++{0x57, 0x01},
++// AE Window Size control for sub-sampling
++{0xfc, 0x06},
++{0x12, 0x00}, // H=2 V=1(800*1200)
++{0x13, 0x61}, // AE H End
++{0x16, 0x00}, // AE V End
++{0x17, 0x94},
++{0x22, 0x00}, // H=1 V=2(1600*600)
++{0x23, 0xc5}, // AE H End
++{0x26, 0x00}, // AE V End
++{0x27, 0x4b},
++{0x32, 0x00}, // H=2 V=2(800*600)
++{0x33, 0x61}, // AE H End
++{0x36, 0x00}, // AE V End
++{0x37, 0x48},
++{0x38, 0x00}, // AWB Window Size
++{0x39, 0x0a},
++{0x3a, 0x00},
++{0x3b, 0x61},
++{0x3c, 0x00},
++{0x3d, 0x75},
++{0x3e, 0x00},
++{0x3f, 0x3e},
++{0x42, 0x00}, // H=4 V=1(400*1200)
++{0x43, 0x2f}, // AE H End
++{0x46, 0x00}, // AE V End
++{0x47, 0x97},
++{0x52, 0x00}, // H=4 V=4(400*300)
++{0x53, 0x30}, // AE H End
++{0x56, 0x00}, // AE V End
++{0x57, 0x26},
++// white point
++{0xfc, 0x00},
++{0x40, 0x78}, //7d a
++{0x41, 0xe0}, //e2
++{0x42, 0x83}, //95 12
++{0x43, 0xc6}, //ba c
++{0x44, 0xad}, //bc f
++{0x45, 0x9d}, //99 4
++{0x34, 0x18}, //115
++{0x35, 0x14}, //02
++{0x36, 0x04}, //04
++{0x37, 0x12}, //04
++{0x38, 0x06}, //03
++{0x39, 0x1d}, //18 //25
++{0x3a, 0x14}, //12 //22 //1f
++{0x3b, 0x2c}, //16 //18 //1a
++{0xfc, 0x20}, // AE window weight
++{0x60, 0x00},
++{0x61, 0x00},
++{0x62, 0x00},
++{0x63, 0x00},
++{0x64, 0x11},
++{0x65, 0x11},
++{0x66, 0x11},
++{0x67, 0x11},
++{0x68, 0x11},
++{0x69, 0x22},
++{0x6a, 0x22},
++{0x6b, 0x11},
++{0x6c, 0x11},
++{0x6d, 0x22},
++{0x6e, 0x22},
++{0x6f, 0x11},
++{0x70, 0x11},
++{0x71, 0x22},
++{0x72, 0x22},
++{0x73, 0x11},
++{0x74, 0x11},
++{0x75, 0x22},
++{0x76, 0x22},
++{0x77, 0x11},
++{0x78, 0x33},
++{0x79, 0x33},
++{0x7a, 0x33},
++{0x7b, 0x33},
++{0x7c, 0x33},
++{0x7d, 0x33},
++{0x7e, 0x33},
++{0x7f, 0x33},
++{0xfc, 0x01},
++{0x02, 0x02},
++{0xfc, 0x02},
++{0x30, 0x83},
++{0x44, 0x5b}, // clamp enable
++{0x55, 0x03},
++{0xfc, 0x00},
++{0x62, 0x02},
++{0xfc, 0x04},
++{0xee, 0x08},
++{0xfc, 0x03},
++{0x2e, 0x08},
++{0xfc, 0x02},
++{0x11, 0x11},
++{0xfc, 0x01},
++{0x4d, 0x08}, // RV con, Red pixel Ordering
++//{0x01, 0x00}, // PCLK
++{0x01, 0x01}, // Inversion PCLK
++{0xfc, 0x00},
++{0x02, 0x00}, // UXGA Size Out
++
++// for 800x600(SVGA)
++// Page 0
++{0xfc, 0x00},
++{0x02, 0x09}, // 800*600 sub-sampling
++// Page 9
++{0xfc, 0x09}, // 800*600 shading delta value
++{0x1D, 0xFF},
++{0x1E, 0xFF},
++{0x1F, 0xFF},
++{0x20, 0xFF},
++{0x21, 0xFF},
++{0x22, 0xFF},
++{0x23, 0xFF},
++{0x24, 0xFF},
++{0x25, 0xFF},
++{0x26, 0xFF},
++{0x27, 0xFF},
++{0x28, 0xFF},
++{0x29, 0xFF},
++{0x2A, 0xFF},
++{0x2B, 0xFF},
++{0x2C, 0xFF},
++{0x2D, 0xFF},
++{0x2E, 0xFF},
++{0x2F, 0xFF},
++{0x30, 0xFF},
++{0x31, 0xFF},
++{0x32, 0xFF},
++{0x33, 0xFF},
++{0x34, 0xFF},
++// Page 1
++{0xfc, 0x01},
++{0x02, 0x02}, // YCbCr Order
++};
++#else
++#error No samsung CIS moudule !
++#endif
++
++
++// abridged VGA : 640 x 480
++s5k3xa_t s5k3aa_reg_vga[] =
++{
++ /* Only for VGA Mode */
++ {0xec,0x07}, //bpr by pyo
++ {0x21,0x9c},
++ {0x22,0x58},
++ {0xec,0x00},
++ {0x87,0x00},
++ {0x86,0x48}, //bpr by pyo
++
++ {0xec,0x02},
++ {0x02,0x0d}, //9bit
++ {0x1f,0x07}, //global gain
++
++ {0xec,0x01},
++ {0x21,0x40},
++ {0x22,0x40},
++ {0x23,0x00},
++ {0x24,0x00},
++
++ {0xec,0x00},
++ {0x7b,0x00},
++ {0x73,0x51},
++ {0x02,0x31}, //YONGKAL
++};
++
++// abridged SXGA : 1280 x 1023 (1.3M)
++ s5k3xa_t s5k3aa_reg_sxga[] =
++{
++
++ {0xec,0x07},
++ {0x21,0x90},
++ {0x22,0x60},
++ {0xec,0x00},
++ {0x87,0x00},
++ {0x86,0x20},
++
++ {0xec,0x02},
++ {0x02,0x0f},
++ {0x1f,0x0f},
++ {0xec,0x01},
++ {0x21,0x50},
++ {0x22,0x50},
++ {0x23,0x10},
++ {0x24,0x10},
++ {0xec,0x00},
++ {0x7b,0xff},
++ {0x73,0x00},
++ {0x02,0x00},
++};
++
++
++#define PAGE_ADDRESS 0xEC
++
++#define S5K3AA_INIT_REGS (sizeof(s5k3aa_reg)/sizeof(s5k3aa_reg[0]))
++#define S5K3AA_SXGA_REGS (sizeof(s5k3aa_reg_sxga)/sizeof(s5k3aa_reg_sxga[0]))
++#define S5K3AA_VGA_REGS (sizeof(s5k3aa_reg_vga)/sizeof(s5k3aa_reg_vga[0]))
++
++#define S5K3AA_RISC_REGS 0xEB
++#define S5K3AA_ISP_REGS 0xFB /* S5C7323X */
++#define S5K3AA_CIS_REGS 0x2F /* S5K437LA03 */
++
++//#define S5K3AA_REGS (S5K3AA_RISC_REGS+S5K3AA_ISP_REGS+S5K3AA_CIS_REGS)
++#define S5K3AA_REGS (0x1000)
++
++// For VGA ( 640 x 480) on 3BA module
++s5k3xa_t s5k3ba_reg_vga[] =
++{
++ {0xfc, 0x01},
++ {0x04, 0x03}, //ARM Clock divider(1/4)
++
++ //In case of PCLK = 64MHz
++ {0xfc, 0x02},
++ {0x52, 0x80}, //PLL M
++
++ {0xfc, 0x02},
++ {0x50, 0x19}, //PLL S,P
++
++ {0xfc, 0x07},
++ {0x58, 0x10},
++ {0x59, 0x00},
++ {0x5A, 0x00},
++ {0x5B, 0x6c},
++
++ {0xfc, 0xf0},
++ {0x00, 0x40},
++
++ {0xfc, 0x00},
++ {0x62, 0x02},
++ {0xbc, 0xe0}, // AWB_AE_DIFF, 0x03},
++ {0x2d, 0x02},
++ {0xfc, 0x01},
++ {0x02, 0x02}, // YCbCr Order
++
++ {0xfc, 0x02},
++ {0x4a, 0xc1}, // SC type selection
++ {0x37, 0x18}, //16 // SC type global gain
++ {0x47, 0xc4}, // r-ramp by chin
++
++
++ {0xfc, 0x01}, //AWB Window Area (except sky)
++ {0xc4, 0x01},
++ {0xc5, 0x4e},
++ {0xc7, 0x6e},
++
++ {0xfc, 0x02},
++ {0x30, 0x84}, //Analog offset
++
++ {0xfc, 0x00},
++ {0x3d, 0x10}, //AWB Low Y limit
++
++ {0xfc, 0x02},
++ {0x3d, 0x06}, //ADLC OFF
++ {0x44, 0x5b}, //clamp enable
++ {0x55, 0x03},
++
++ {0xfc, 0x06},
++ {0x0c, 0x01},
++ {0x0d, 0x4e},
++ {0x0f, 0x6e},
++
++ {0xfc, 0x00},
++ {0x78, 0x58}, //AGC MAX (30lux_Micron¹à±âY=60code)
++
++ {0xfc, 0x02},
++ {0x45, 0x8c}, //CDS timing_ÀúÁ¶µµ greenish ÇØ°á(15fps)
++ {0x49, 0x80}, // APS Current 2uA
++
++ {0xfc, 0x01},
++ {0x25, 0x14}, //10 //Digital Clamp
++
++ {0xfc, 0x00},
++ {0x6c, 0xac}, //AE target (Macbeth white=240)
++ {0x6d, 0x00},
++
++ // 2. ISP tuning
++ // ISP_tuning
++ {0xfc, 0x00},
++ {0x01, 0x00}, // I2C hold mode off
++
++ {0xfc, 0x01},
++ {0x00, 0x00}, // ISP BPR Off
++ {0x0c, 0x02}, // Full YC
++ {0xc8, 0x19}, // AWB Y Max
++
++ {0xfc, 0x00},
++ {0x81, 0x00}, // AWB G gain suppress disable
++ {0x29, 0x04},
++ {0x2a, 0x00},
++ {0x2b, 0x04}, // color level
++ {0x2c, 0x00},
++
++ {0xfc, 0x07},
++ {0x11, 0x00}, // G offset
++ {0x37, 0x00}, // Flicker Add
++
++ {0xfc, 0x00},
++ {0x72, 0xa0}, // Flicker for 32MHz
++ {0x74, 0x18}, // Flicker
++ {0x73, 0x00}, // Frame AE
++
++ {0xfc, 0x05},
++ {0x64, 0x00}, // Darkslice R
++ {0x65, 0x00}, // Darkslice G
++ {0x66, 0x00}, // Darkslice B
++
++ //Edge
++ {0xfc, 0x05},
++ {0x2c, 0x0a}, //14 // positive gain
++ {0x30, 0x0a}, //10 // negative edge gain
++ {0x34, 0x1a}, // APTCLP
++ {0x35, 0x10}, //0a // APTSC
++ {0x36, 0x0b}, // ENHANCE
++ {0x3f, 0x00}, // NON-LIN
++ {0x45, 0x30}, // EGREF
++ {0x47, 0x00}, // LLREF
++ {0x48, 0x08}, // by chin
++ {0x49, 0x39}, // CSSEL EGSEL CS_DLY by
++ {0x40, 0x41}, // Y delay
++
++ {0xfc, 0x00},
++ {0x7e, 0xfc},
++ // s7e8c //NR GrGb off
++ // [7]: BPR [6]:Noise Filter(1D/NR) [4]: GrGb Enable [3]:BPR Data Threshold
++ // [2]: color suppress [1]: Y gain suppress [0]: Digital Clamp
++
++ // GrGb Correction setting
++ {0xfc, 0x01},
++ {0x44, 0x0c},
++ //s4400
++ /// [4]: GrGb full [3]: GrGb On
++ /// [2]: GrGb Rb On
++ {0xfc, 0x0b},
++ {0x21, 0x00}, // Start AGC
++ {0x22, 0x10}, // AGCMIN
++ {0x23, 0x50}, // AGCMAX
++ {0x24, 0x18}, // G Th AGCMIN(23d)
++ {0x25, 0x52}, // G Th AGCMAX(50d)
++ {0x26, 0x38}, // RB Th AGCMIN
++ {0x27, 0x52}, // RB Th AGCMAX
++ // GrGb Correction setting End
++
++ ///////////////////////////////////
++ // BPR Setting
++ {0xfc, 0x01},
++ {0x3f, 0x00}, // setting because S/W bug
++
++ {0xfc, 0x0b},
++ {0x0b, 0x00}, // ISP BPR On Start
++ {0x0c, 0x00}, // Th13 AGC Min
++ {0x0d, 0x5a}, // Th13 AGC Max
++ {0x0e, 0x01}, //00 // Th1 Max H for AGCMIN
++ {0x0f, 0xff}, //c0 // Th1 Max L for AGCMIN
++ {0x10, 0x00}, // Th1 Min H for AGCMAX
++ {0x11, 0x10}, //00 // Th1 Min L for AGCMAX
++ {0x12, 0xff}, // Th3 Max H for AGCMIN
++ {0x13, 0xff}, // Th3 Max L for AGCMIN
++ {0x14, 0xff}, // Th3 Min H for AGCMAX
++ {0x15, 0xff}, // Th3 Min L for AGCMAX
++
++ // NR Setting
++ {0xfc, 0x01},
++ {0x4b, 0x01}, // NR Enable
++ // s4b00 // NR Enable
++
++ {0xfc, 0x0b},
++ {0x28, 0x00}, //NR Start AGC
++ {0x29, 0x00}, // SIG Th AGCMIN H
++ {0x2a, 0x0a}, //14 // SIG Th AGCMIN L
++ {0x2b, 0x00}, // SIG Th AGCMAX H
++ {0x2c, 0x0a}, //14 // SIG Th AGCMAX L
++ {0x2d, 0x00}, // PRE Th AGCMIN H
++ {0x2e, 0xc0}, //64 // PRE Th AGCMIN L(100d)
++ {0x2f, 0x01}, // PRE Th AGCMAX H(300d)
++ {0x30, 0x2c}, // PRE Th AGCMAX L
++ {0x31, 0x00}, // POST Th AGCMIN H
++ {0x32, 0xe0}, //64 // POST Th AGCMIN L(100d)
++ {0x33, 0x01}, // POST Th AGCMAX H(300d)
++ {0x34, 0x2c}, // POST Th AGCMAX L
++ // NR Setting End
++
++ // Color suppress setting
++ {0xfc, 0x0b},
++ {0x08, 0x50}, // C suppress AGC MIN
++ {0x09, 0x03}, // C suppress MIN H
++ {0x0a, 0x80}, // C suppress MIN L
++ // C Suppress Setting End
++
++ {0xfc, 0x05},
++ {0x4a, 0x00}, //01 // Edge Color Suppress, 9/13
++
++ // 1D Y LPF Filter
++ {0xfc, 0x01},
++ // s05e0 // Default s60
++ {0x05, 0x60}, // Default s60
++ // [7]: Y LPF filter On [6]: Clap On
++
++ {0xfc, 0x0b},
++ {0x35, 0x00}, // YLPF Start AGC
++ {0x36, 0x50}, // YLPF01 AGCMIN
++ {0x37, 0x50}, // YLPF01 AGCMAX
++ {0x38, 0x00}, // YLPF SIG01 Th AGCMINH
++ {0x39, 0x90}, //00 // YLPF SIG01 Th AGCMINL
++ {0x3a, 0x01}, // YLPF SIG01 Th AGCMAXH
++ {0x3b, 0xa0}, // YLPF SIG01 Th AGCMAXL
++ {0x3c, 0x50}, // YLPF02 AGCMIN
++ {0x3d, 0x50}, // YLPF02 AGCMAX
++ {0x3e, 0x00}, // YLPF SIG02 Th AGCMINH
++ {0x3f, 0xa0}, //00 // YLPF SIG02 Th AGCMINL
++ {0x40, 0x01}, // YLPF SIG02 Th AGCMAXH s73
++ {0x41, 0xb0}, // YLPF SIG02 Th AGCMAXL
++ // Y LPF Filter setting End
++
++ // SET EDGE COLOR SUPPRESS AND Y-LPF
++ {0xfc, 0x05},
++ {0x42, 0x1F},
++ {0x43, 0x1F},
++ {0x44, 0x0E},
++ {0x45, 0x8C}, //
++ {0x46, 0x7A},
++ {0x47, 0x60},
++ {0x48, 0x0C},
++ {0x49, 0x39},
++ {0x4A, 0x01},
++ {0x4B, 0xB1},
++ {0x4C, 0x3B},
++ {0x4D, 0x14},
++
++ // NR Setting
++ {0xfc, 0x01},
++ {0x4b, 0x01}, // NR Enable
++
++ // Set multipliers (which are not suppressed)
++ {0xfc, 0x01},
++ {0x48, 0x11},
++
++ // Suppressed parameters
++ {0xfc, 0x0B},
++ {0x21, 0x00},
++ {0x22, 0x10},
++ {0x23, 0x60},
++ {0x24, 0x10},
++ {0x25, 0x28},
++ {0x26, 0x08},
++ {0x27, 0x20},
++
++ {0x28, 0x00}, //NR Start AGC
++ {0x29, 0x00}, // SIG Th AGCMIN H
++ {0x2A, 0x02}, // SIG Th AGCMIN L
++ {0x2B, 0x00}, // SIG Th AGCMAX H
++ {0x2C, 0x14}, // SIG Th AGCMAX L
++ {0x2D, 0x03}, // PRE Th AGCMIN H
++ {0x2E, 0x84}, // PRE Th AGCMIN L
++ {0x2F, 0x03}, // PRE Th AGCMAX H
++ {0x30, 0x84}, // PRE Th AGCMAX L
++ {0x31, 0x00}, // POST Th AGCMIN H
++ {0x32, 0x00}, // POST Th AGCMIN L
++ {0x33, 0x00}, // POST Th AGCMAX H
++ {0x34, 0xC8}, // POST Th AGCMAX L
++
++ {0x35, 0x00}, // 1D Y filter setting
++ {0x36, 0x10},
++ {0x37, 0x50},
++ {0x38, 0x00},
++ {0x39, 0x14},
++ {0x3A, 0x00},
++ {0x3B, 0x50},
++ {0x3C, 0x10},
++ {0x3D, 0x50},
++ {0x3E, 0x00},
++ {0x3F, 0x28},
++ {0x40, 0x00},
++ {0x41, 0xA0},
++
++ // To avoid AWB tracking @ max AGC gain even though AE is unstable state
++ {0xfc, 0x00},
++ {0xba, 0x50}, // AE Target minus AE Average
++ {0xbb, 0x00},
++ {0xbc, 0x00},
++
++ // 3. AE weight & etc linear
++ // AE Window Weight linear(EVT1)0929
++ {0xfc, 0x20}, // upper window weight zero
++
++ {0x60, 0x11},
++ {0x61, 0x11},
++ {0x62, 0x11},
++ {0x63, 0x11},
++ {0x64, 0x11},
++ {0x65, 0x11},
++ {0x66, 0x11},
++ {0x67, 0x11},
++ {0x68, 0x11},
++ {0x69, 0x11},
++ {0x6a, 0x11},
++ {0x6b, 0x11},
++ {0x6c, 0x11},
++ {0x6d, 0x11},
++ {0x6e, 0x11},
++ {0x6f, 0x11},
++ {0x70, 0x11},
++ {0x71, 0x11},
++ {0x72, 0x11},
++ {0x73, 0x11},
++ {0x74, 0x11},
++ {0x75, 0x11},
++ {0x76, 0x11},
++ {0x77, 0x11},
++ {0x78, 0x11},
++ {0x79, 0x11},
++ {0x7a, 0x11},
++ {0x7b, 0x11},
++ {0x7c, 0x11},
++ {0x7d, 0x11},
++ {0x7e, 0x11},
++ {0x7f, 0x11},
++
++
++ // AE window Weight setting End
++ //hue gain linear
++ {0xfc, 0x00},
++
++ {0x48, 0x40},
++ {0x49, 0x40},
++ {0x4a, 0x00},
++ {0x4b, 0x00},
++ {0x4c, 0x40},
++ {0x4d, 0x40},
++ {0x4e, 0x00},
++ {0x4f, 0x00},
++ {0x50, 0x40},
++ {0x51, 0x40},
++ {0x52, 0x00},
++ {0x53, 0x00},
++ {0x54, 0x40},
++ {0x55, 0x40},
++ {0x56, 0x00},
++ {0x57, 0x00},
++ {0x58, 0x40},
++ {0x59, 0x40},
++ {0x5a, 0x00},
++ {0x5b, 0x00},
++ {0x5c, 0x40},
++ {0x5d, 0x40},
++ {0x5e, 0x00},
++ {0x5f, 0x00},
++ {0x62, 0x00}, //hue enable OFF
++
++ // 4. shading (FlexÇâ 3000K manual shading)
++ {0xfc, 0x09},
++ // DSP9_SH_WIDTH_H
++ {0x01, 0x06},
++ {0x02, 0x40},
++ // DSP9_SH_HEIGHT_H
++ {0x03, 0x04},
++ {0x04, 0xB0},
++ {0x05, 0x03},
++ {0x06, 0x13},
++ {0x07, 0x02},
++ {0x08, 0x5A},
++ {0x09, 0x03},
++ {0x0A, 0x15},
++ {0x0B, 0x02},
++ {0x0C, 0x5B},
++ {0x0D, 0x03},
++ {0x0E, 0x0D},
++ {0x0F, 0x02},
++ {0x10, 0x5D},
++ {0x1D, 0x80},
++ {0x1E, 0x00},
++ {0x1F, 0x80},
++ {0x20, 0x00},
++ {0x23, 0x80},
++ {0x24, 0x00},
++ {0x21, 0x80},
++ {0x22, 0x00},
++ {0x25, 0x80},
++ {0x26, 0x00},
++ {0x27, 0x80},
++ {0x28, 0x00},
++ {0x2B, 0x80},
++ {0x2C, 0x00},
++ {0x29, 0x80},
++ {0x2A, 0x00},
++ {0x2D, 0x80},
++ {0x2E, 0x00},
++ {0x2F, 0x80},
++ {0x30, 0x00},
++ {0x33, 0x80},
++ {0x34, 0x00},
++ {0x31, 0x80},
++ {0x32, 0x00},
++ // DSP9_SH_VAL_R0H
++ {0x35, 0x01},
++ {0x36, 0x00},
++ {0x37, 0x01},
++ {0x38, 0x0F},
++ {0x39, 0x01},
++ {0x3A, 0x42},
++ {0x3B, 0x01},
++ {0x3C, 0x9C},
++ {0x3D, 0x01},
++ {0x3E, 0xD0},
++ {0x3F, 0x02},
++ {0x40, 0x0F},
++ {0x41, 0x02},
++ {0x42, 0x3D},
++ {0x43, 0x02},
++ {0x44, 0x5E},
++ {0x45, 0x01},
++ {0x46, 0x00},
++ {0x47, 0x01},
++ {0x48, 0x0A},
++ {0x49, 0x01},
++ {0x4A, 0x2E},
++ {0x4B, 0x01},
++ {0x4C, 0x66},
++ {0x4D, 0x01},
++ {0x4E, 0x89},
++ {0x4F, 0x01},
++ {0x50, 0xB7},
++ {0x51, 0x01},
++ {0x52, 0xD8},
++ {0x53, 0x01},
++ {0x54, 0xFA},
++ // DS9_SH_VAL_B0H
++ {0x55, 0x01},
++ {0x56, 0x00},
++ {0x57, 0x01},
++ {0x58, 0x0A},
++ {0x59, 0x01},
++ {0x5A, 0x28},
++ {0x5B, 0x01},
++ {0x5C, 0x59},
++ {0x5D, 0x01},
++ {0x5E, 0x7A},
++ {0x5F, 0x01},
++ {0x60, 0xA1},
++ {0x61, 0x01},
++ {0x62, 0xC0},
++ {0x63, 0x01},
++ {0x64, 0xDC},
++ // DSP9_SH_M_R2_R1H
++ {0x65, 0x00},
++ {0x66, 0x9F},
++ {0x67, 0xE6},
++ {0x68, 0x02},
++ {0x69, 0x7F},
++ {0x6A, 0x9B},
++ {0x6B, 0x05},
++ {0x6C, 0x9F},
++ {0x6D, 0x1E},
++ {0x6E, 0x07},
++ {0x6F, 0xA6},
++ {0x70, 0xCC},
++ {0x71, 0x09},
++ {0x72, 0xFE},
++ {0x73, 0x6E},
++ {0x74, 0x0C},
++ {0x75, 0xA6},
++ {0x76, 0x04},
++ {0x77, 0x0F},
++ {0x78, 0x9D},
++ {0x79, 0x8C},
++ // DSP9_SH_M_R2_G1H
++ {0x7A, 0x00},
++ {0x7B, 0x9F},
++ {0x7C, 0x95},
++ {0x7D, 0x02},
++ {0x7E, 0x7E},
++ {0x7F, 0x54},
++ {0x80, 0x05},
++ {0x81, 0x9C},
++ {0x82, 0x3E},
++ {0x83, 0x07},
++ {0x84, 0xA2},
++ {0x85, 0xE3},
++ {0x86, 0x09},
++ {0x87, 0xF9},
++ {0x88, 0x53},
++ {0x89, 0x0C},
++ {0x8A, 0x9F},
++ {0x8B, 0x8D},
++ {0x8C, 0x0F},
++ {0x8D, 0x95},
++ {0x8E, 0x91},
++ // DSP9_SH_M_R2_B1H
++ {0x8F, 0x00},
++ {0x90, 0xA1},
++ {0x91, 0xFF},
++ {0x92, 0x02},
++ {0x93, 0x87},
++ {0x94, 0xFD},
++ {0x95, 0x05},
++ {0x96, 0xB1},
++ {0x97, 0xFA},
++ {0x98, 0x07},
++ {0x99, 0xC0},
++ {0x9A, 0x79},
++ {0x9B, 0x0A},
++ {0x9C, 0x1F},
++ {0x9D, 0xF6},
++ {0x9E, 0x0C},
++ {0x9F, 0xD0},
++ {0xA0, 0x74},
++ {0xA1, 0x0F},
++ {0xA2, 0xD1},
++ {0xA3, 0xF1},
++ // DSP9_SH_SUB_RR0H
++ {0xA4, 0x66},
++ {0xA5, 0x76},
++ {0xA6, 0x22},
++ {0xA7, 0x27},
++ {0xA8, 0x14},
++ {0xA9, 0x7E},
++ {0xAA, 0x1F},
++ {0xAB, 0x86},
++ {0xAC, 0x1B},
++ {0xAD, 0x52},
++ {0xAE, 0x18},
++ {0xAF, 0x1B},
++ {0xB0, 0x15},
++ {0xB1, 0x92},
++ // DSP9_SH_SUB_RG0H
++ {0xB2, 0x66},
++ {0xB3, 0xAA},
++ {0xB4, 0x22},
++ {0xB5, 0x38},
++ {0xB6, 0x14},
++ {0xB7, 0x88},
++ {0xB8, 0x1F},
++ {0xB9, 0x97},
++ {0xBA, 0x1B},
++ {0xBB, 0x60},
++ {0xBC, 0x18},
++ {0xBD, 0x28},
++ {0xBE, 0x15},
++ {0xBF, 0x9D},
++ // DSP9_SH_SUB_RB0H
++ {0xC0, 0x65},
++ {0xC1, 0x23},
++ {0xC2, 0x21},
++ {0xC3, 0xB6},
++ {0xC4, 0x14},
++ {0xC5, 0x3A},
++ {0xC6, 0x1F},
++ {0xC7, 0x1E},
++ {0xC8, 0x1A},
++ {0xC9, 0xF8},
++ {0xCA, 0x17},
++ {0xCB, 0xCC},
++ {0xCC, 0x15},
++ {0xCD, 0x4A},
++ {0x00, 0x02}, // shading on
++
++ {0xfc, 0x00},
++ {0x79, 0xf4},
++ {0x7a, 0x09},
++
++ // 5.color correction
++ // 1229 CCM
++ // 2.0251 -1.0203 -0.0048
++ // -0.7080 1.8970 -0.1889
++ // -0.468 -0.444 1.912
++
++ {0xfc, 0x01},
++ {0x51, 0x08}, //R
++ {0x52, 0x18},
++ {0x53, 0xfb},
++ {0x54, 0xec},
++ {0x55, 0xff},
++ {0x56, 0xfc},
++ {0x57, 0xfd}, //G
++ {0x58, 0x2c},
++ {0x59, 0x07},
++ {0x5a, 0x95},
++ {0x5b, 0xff},
++ {0x5c, 0x3f},
++ {0x5d, 0xfe}, //B
++ {0x5e, 0x22},
++ {0x5f, 0xfe},
++ {0x60, 0x3a},
++ {0x61, 0x07},
++ {0x62, 0xa5},
++
++ //6.gamma
++ //Gamma
++ {0xfc, 0x01},
++
++ // R
++ {0x6F, 0x05},
++ {0x70, 0x14},
++ {0x71, 0x3c},
++ {0x72, 0x96},
++ {0x73, 0x00},
++
++ {0x74, 0x2c},
++ {0x75, 0xa2},
++ {0x76, 0xfc},
++ {0x77, 0x44},
++ {0x78, 0x56},
++
++ {0x79, 0x80},
++ {0x7A, 0xb7},
++ {0x7B, 0xed},
++ {0x7C, 0x16},
++ {0x7D, 0xab},
++
++ {0x7E, 0x3c},
++ {0x7F, 0x61},
++ {0x80, 0x83},
++ {0x81, 0xa4},
++ {0x82, 0xff},
++
++ {0x83, 0xc4},
++ {0x84, 0xe2},
++ {0x85, 0xff},
++ {0x86, 0xff},
++
++
++ // G
++ {0x87, 0x05},
++ {0x88, 0x14},
++ {0x89, 0x3c},
++ {0x8A, 0x96},
++ {0x8B, 0x00},
++
++ {0x8C, 0x2c},
++ {0x8D, 0xa2},
++ {0x8E, 0xfc},
++ {0x8F, 0x44},
++ {0x90, 0x56},
++
++ {0x91, 0x80},
++ {0x92, 0xb7},
++ {0x93, 0xed},
++ {0x94, 0x16},
++ {0x95, 0xab},
++
++ {0x96, 0x3c},
++ {0x97, 0x61},
++ {0x98, 0x83},
++ {0x99, 0xa4},
++ {0x9A, 0xff},
++
++ {0x9B, 0xc4},
++ {0x9C, 0xe2},
++ {0x9D, 0xff},
++ {0x9E, 0xff},
++
++ //B
++ {0x9F, 0x05},
++ {0xA0, 0x10},
++ {0xA1, 0x30},
++ {0xA2, 0x70},
++ {0xA3, 0x00},
++
++ {0xA4, 0x2c},
++ {0xA5, 0xa2},
++ {0xA6, 0xfc},
++ {0xA7, 0x44},
++ {0xA8, 0x56},
++
++ {0xA9, 0x80},
++ {0xAA, 0xb7},
++ {0xAB, 0xed},
++ {0xAC, 0x16},
++ {0xAD, 0xab},
++
++ {0xAE, 0x3c},
++ {0xAF, 0x61},
++ {0xB0, 0x83},
++ {0xB1, 0xa4},
++ {0xB2, 0xff},
++
++ {0xB3, 0xc4},
++ {0xB4, 0xe2},
++ {0xB5, 0xff},
++ {0xB6, 0xff},
++
++ // 7.hue
++ {0xFC, 0x00},
++ {0x62, 0x00}, // hue auto control off
++
++ {0xFC, 0x05},
++ {0x4E, 0x60},
++ {0x4F, 0xA0},
++ {0x50, 0x35},
++ {0x51, 0xA0},
++ {0x52, 0x20},
++ {0x53, 0x01},
++ {0x54, 0xE0},
++ {0x55, 0xE0},
++ {0x56, 0x54},
++ {0x57, 0x20},
++ {0x58, 0x20},
++ {0x59, 0xF0},
++
++ // 8.white point
++ // AWB Start Point
++ {0xfc, 0x07},
++ {0x05, 0x00},
++ {0x06, 0x08},
++ {0x07, 0x1b},
++ {0x08, 0xf0},
++ {0x09, 0x00}, // R
++ {0x0a, 0xa8},
++ {0x0b, 0x00}, // B
++ {0x0c, 0xb0},
++ {0x0d, 0x00}, // G
++ {0x0e, 0x40},
++
++ {0xfc, 0x00},
++ {0x70, 0x02},
++
++ {0x40, 0x8a}, //2000K
++ {0x41, 0xe5},
++ {0x42, 0x95}, //3100K
++ {0x43, 0xba},
++ {0x44, 0xbc}, //5100K
++ {0x45, 0x99},
++
++ {0x34, 0x24},
++ {0x35, 0x10},
++ {0x36, 0x13},
++ {0x37, 0x04},
++ {0x38, 0x10},
++ {0x39, 0x28},
++ {0x3a, 0x1e},
++ {0x3b, 0x2a},
++ {0x31, 0x00}, // skin tone[6], CW delete[5]
++#if 0
++ // Added by SOP at 02/09/2006
++ {0xfc, 0x00},
++ {0x02, 0x00} // Image format from UXGA to VGA
++ // 0: UXGA, 1: SXGA, 2: VGA, 3: QVGA, 4: QQVGA, 5: CIF, 6: QCIF
++#else
++ {0xfc, 0x00},
++ {0x72, 0xfa},
++ {0x74, 0x90},
++
++ {0xfc, 0x02},
++ {0x50, 0x12},
++ {0x52, 0x7a}, // AWB_AE_DIFF
++
++ {0xfc, 0x00},
++ {0x74, 0x18},
++
++ {0xfc, 0x04},
++ {0xed, 0x02},
++ {0xc3, 0x76},
++ {0xd7, 0x58},
++
++ {0xdc, 0x80},
++ {0xdd, 0x02}, // SC type selection
++ {0xde, 0xe0}, //16 // SC type global gain
++ {0xdf, 0x01},
++ {0xe4, 0x80},
++ {0xe5, 0x02}, // SC type selection
++ {0xe6, 0xe0}, //16 // SC type global gain
++ {0xe7, 0x01},
++
++ {0xe9, 0x4d},
++ {0xea, 0x08},
++ {0xeb, 0x00},
++
++ {0xda, 0xcd},
++ {0xdb, 0xcd},
++
++ {0xfc, 0x05}, // AWB_AE_DIFF
++ {0x64, 0xfe},
++ {0x65, 0xfe},
++ {0x66, 0xfd},
++
++ {0xfc, 0x0b},
++ {0x24, 0x20},
++ {0x26, 0x20},
++ {0x2e, 0xf0},
++ {0x32, 0xf0},
++ {0x39, 0xa0},
++
++ {0xfc, 0x00},
++ {0x02, 0x09},
++
++ {0xfc, 0x09},
++ {0x1d, 0xff},
++ {0x1e, 0xff},
++ {0x1f, 0xff},
++ {0x20, 0xff},
++ {0x21, 0xff},
++ {0x22, 0xff},
++ {0x23, 0xff},
++ {0x24, 0xff},
++ {0x25, 0xff},
++ {0x26, 0xff},
++ {0x27, 0xff},
++ {0x28, 0xff},
++ {0x29, 0xff},
++ {0x2a, 0xff},
++ {0x2b, 0xff},
++ {0x2c, 0xff},
++ {0x2d, 0xff},
++ {0x2e, 0xff},
++ {0x2f, 0xff},
++ {0x31, 0xff},
++ {0x32, 0xff},
++ {0x33, 0xff},
++ {0x34, 0xff},
++#endif
++};
++
++
++// For SXGA (1280 x 1024 = 1.3M) on 3BA module
++s5k3xa_t s5k3ba_reg_sxga[] =
++{
++// PLL SETTING Input = 25Mhz, Output = 64Mhz, UXGA (2Mpixel)
++ // 1. initial setting
++
++ {0xfc, 0x01},
++ {0x04, 0x03}, //ARM Clock divider(1/4)
++
++ //In case of PCLK = 64MHz
++ {0xfc, 0x02},
++ {0x52, 0x80}, //PLL M
++
++ {0xfc, 0x02},
++ {0x50, 0x19}, //PLL S,P
++
++ {0xfc, 0x07},
++ {0x58, 0x10},
++ {0x59, 0x00},
++ {0x5A, 0x00},
++ {0x5B, 0x6c},
++
++ {0xfc, 0xf0},
++ {0x00, 0x40},
++
++ {0xfc, 0x00},
++ {0x62, 0x02},
++ {0xbc, 0xe0}, // AWB_AE_DIFF
++
++ {0xfc, 0x03},
++ {0x2d, 0x02},
++ {0xfc, 0x01},
++ {0x02, 0x02}, // YCbCr Order
++
++ {0xfc, 0x02},
++ {0x4a, 0xc1}, // SC type selection
++ {0x37, 0x18}, //16 // SC type global gain
++ {0x47, 0xc4}, // r-ramp by chin
++
++
++ {0xfc, 0x01}, //AWB Window Area (except sky)
++ {0xc4, 0x01},
++ {0xc5, 0x4e},
++ {0xc7, 0x6e},
++
++ {0xfc, 0x02},
++ {0x30, 0x84}, //Analog offset
++
++ {0xfc, 0x00},
++ {0x3d, 0x10}, //AWB Low Y limit
++
++ {0xfc, 0x02},
++ {0x3d, 0x06}, //ADLC OFF
++ {0x44, 0x5b}, //clamp enable
++ {0x55, 0x03},
++
++ {0xfc, 0x06},
++ {0x0c, 0x01},
++ {0x0d, 0x4e},
++ {0x0f, 0x6e},
++
++ {0xfc, 0x00},
++ {0x78, 0x58}, //AGC MAX (30lux_Micron¹à±âY=60code)
++
++ {0xfc, 0x02},
++ {0x45, 0x8c}, //CDS timing_ÀúÁ¶µµ greenish ÇØ°á(15fps)
++ {0x49, 0x80}, // APS Current 2uA
++
++ {0xfc, 0x01},
++ {0x25, 0x14}, //10 //Digital Clamp
++
++ {0xfc, 0x00},
++ {0x6c, 0xac}, //AE target (Macbeth white=240)
++ {0x6d, 0x00},
++
++ // 2. ISP tuning
++ // ISP_tuning
++ {0xfc, 0x00},
++ {0x01, 0x00}, // I2C hold mode off
++
++ {0xfc, 0x01},
++ {0x00, 0x00}, // ISP BPR Off
++ {0x0c, 0x02}, // Full YC
++ {0xc8, 0x19}, // AWB Y Max
++
++ {0xfc, 0x00},
++ {0x81, 0x00}, // AWB G gain suppress disable
++ {0x29, 0x04},
++ {0x2a, 0x00},
++ {0x2b, 0x04}, // color level
++ {0x2c, 0x00},
++
++ {0xfc, 0x07},
++ {0x11, 0x00}, // G offset
++ {0x37, 0x00}, // Flicker Add
++
++ {0xfc, 0x00},
++ {0x72, 0xa0}, // Flicker for 32MHz
++ {0x74, 0x18}, // Flicker
++ {0x73, 0x00}, // Frame AE
++
++ {0xfc, 0x05},
++ {0x64, 0x00}, // Darkslice R
++ {0x65, 0x00}, // Darkslice G
++ {0x66, 0x00}, // Darkslice B
++
++ //Edge
++ {0xfc, 0x05},
++ {0x2c, 0x0a}, //14 // positive gain
++ {0x30, 0x0a}, //10 // negative edge gain
++ {0x34, 0x1a}, // APTCLP
++ {0x35, 0x10}, //0a // APTSC
++ {0x36, 0x0b}, // ENHANCE
++ {0x3f, 0x00}, // NON-LIN
++ {0x45, 0x30}, // EGREF
++ {0x47, 0x00}, // LLREF
++ {0x48, 0x08}, // by chin
++ {0x49, 0x39}, // CSSEL EGSEL CS_DLY by
++ {0x40, 0x41}, // Y delay
++
++ {0xfc, 0x00},
++ {0x7e, 0xfc},
++ // s7e8c //NR GrGb off
++ // [7]: BPR [6]:Noise Filter(1D/NR) [4]: GrGb Enable [3]:BPR Data Threshold
++ // [2]: color suppress [1]: Y gain suppress [0]: Digital Clamp
++
++ // GrGb Correction setting
++ {0xfc, 0x01},
++ {0x44, 0x0c},
++ //s4400
++ /// [4]: GrGb full [3]: GrGb On
++ /// [2]: GrGb Rb On
++ {0xfc, 0x0b},
++ {0x21, 0x00}, // Start AGC
++ {0x22, 0x10}, // AGCMIN
++ {0x23, 0x50}, // AGCMAX
++ {0x24, 0x18}, // G Th AGCMIN(23d)
++ {0x25, 0x52}, // G Th AGCMAX(50d)
++ {0x26, 0x38}, // RB Th AGCMIN
++ {0x27, 0x52}, // RB Th AGCMAX
++ // GrGb Correction setting End
++
++ ///////////////////////////////////
++ // BPR Setting
++ {0xfc, 0x01},
++ {0x3f, 0x00}, // setting because S/W bug
++
++ {0xfc, 0x0b},
++ {0x0b, 0x00}, // ISP BPR On Start
++ {0x0c, 0x00}, // Th13 AGC Min
++ {0x0d, 0x5a}, // Th13 AGC Max
++ {0x0e, 0x01}, //00 // Th1 Max H for AGCMIN
++ {0x0f, 0xff}, //c0 // Th1 Max L for AGCMIN
++ {0x10, 0x00}, // Th1 Min H for AGCMAX
++ {0x11, 0x10}, //00 // Th1 Min L for AGCMAX
++ {0x12, 0xff}, // Th3 Max H for AGCMIN
++ {0x13, 0xff}, // Th3 Max L for AGCMIN
++ {0x14, 0xff}, // Th3 Min H for AGCMAX
++ {0x15, 0xff}, // Th3 Min L for AGCMAX
++
++ // NR Setting
++ {0xfc, 0x01},
++ {0x4b, 0x01}, // NR Enable
++ // s4b00 // NR Enable
++
++ {0xfc, 0x0b},
++ {0x28, 0x00}, //NR Start AGC
++ {0x29, 0x00}, // SIG Th AGCMIN H
++ {0x2a, 0x0a}, //14 // SIG Th AGCMIN L
++ {0x2b, 0x00}, // SIG Th AGCMAX H
++ {0x2c, 0x0a}, //14 // SIG Th AGCMAX L
++ {0x2d, 0x00}, // PRE Th AGCMIN H
++ {0x2e, 0xc0}, //64 // PRE Th AGCMIN L(100d)
++ {0x2f, 0x01}, // PRE Th AGCMAX H(300d)
++ {0x30, 0x2c}, // PRE Th AGCMAX L
++ {0x31, 0x00}, // POST Th AGCMIN H
++ {0x32, 0xe0}, //64 // POST Th AGCMIN L(100d)
++ {0x33, 0x01}, // POST Th AGCMAX H(300d)
++ {0x34, 0x2c}, // POST Th AGCMAX L
++ // NR Setting End
++
++ // Color suppress setting
++ {0xfc, 0x0b},
++ {0x08, 0x50}, // C suppress AGC MIN
++ {0x09, 0x03}, // C suppress MIN H
++ {0x0a, 0x80}, // C suppress MIN L
++ // C Suppress Setting End
++
++ {0xfc, 0x05},
++ {0x4a, 0x00}, //01 // Edge Color Suppress, 9/13
++
++ // 1D Y LPF Filter
++ {0xfc, 0x01},
++ // s05e0 // Default s60
++ {0x05, 0x60}, // Default s60
++ // [7]: Y LPF filter On [6]: Clap On
++
++ {0xfc, 0x0b},
++ {0x35, 0x00}, // YLPF Start AGC
++ {0x36, 0x50}, // YLPF01 AGCMIN
++ {0x37, 0x50}, // YLPF01 AGCMAX
++ {0x38, 0x00}, // YLPF SIG01 Th AGCMINH
++ {0x39, 0x90}, //00 // YLPF SIG01 Th AGCMINL
++ {0x3a, 0x01}, // YLPF SIG01 Th AGCMAXH
++ {0x3b, 0xa0}, // YLPF SIG01 Th AGCMAXL
++ {0x3c, 0x50}, // YLPF02 AGCMIN
++ {0x3d, 0x50}, // YLPF02 AGCMAX
++ {0x3e, 0x00}, // YLPF SIG02 Th AGCMINH
++ {0x3f, 0xa0}, //00 // YLPF SIG02 Th AGCMINL
++ {0x40, 0x01}, // YLPF SIG02 Th AGCMAXH s73
++ {0x41, 0xb0}, // YLPF SIG02 Th AGCMAXL
++ // Y LPF Filter setting End
++
++ // SET EDGE COLOR SUPPRESS AND Y-LPF
++ {0xfc, 0x05},
++ {0x42, 0x1F},
++ {0x43, 0x1F},
++ {0x44, 0x0E},
++ {0x45, 0x8C}, //
++ {0x46, 0x7A},
++ {0x47, 0x60},
++ {0x48, 0x0C},
++ {0x49, 0x39},
++ {0x4A, 0x01},
++ {0x4B, 0xB1},
++ {0x4C, 0x3B},
++ {0x4D, 0x14},
++
++ // NR Setting
++ {0xfc, 0x01},
++ {0x4b, 0x01}, // NR Enable
++
++ // Set multipliers (which are not suppressed)
++ {0xfc, 0x01},
++ {0x48, 0x11},
++
++ // Suppressed parameters
++ {0xfc, 0x0B},
++ {0x21, 0x00},
++ {0x22, 0x10},
++ {0x23, 0x60},
++ {0x24, 0x10},
++ {0x25, 0x28},
++ {0x26, 0x08},
++ {0x27, 0x20},
++
++ {0x28, 0x00}, //NR Start AGC
++ {0x29, 0x00}, // SIG Th AGCMIN H
++ {0x2A, 0x02}, // SIG Th AGCMIN L
++ {0x2B, 0x00}, // SIG Th AGCMAX H
++ {0x2C, 0x14}, // SIG Th AGCMAX L
++ {0x2D, 0x03}, // PRE Th AGCMIN H
++ {0x2E, 0x84}, // PRE Th AGCMIN L
++ {0x2F, 0x03}, // PRE Th AGCMAX H
++ {0x30, 0x84}, // PRE Th AGCMAX L
++ {0x31, 0x00}, // POST Th AGCMIN H
++ {0x32, 0x00}, // POST Th AGCMIN L
++ {0x33, 0x00}, // POST Th AGCMAX H
++ {0x34, 0xC8}, // POST Th AGCMAX L
++
++ {0x35, 0x00}, // 1D Y filter setting
++ {0x36, 0x10},
++ {0x37, 0x50},
++ {0x38, 0x00},
++ {0x39, 0x14},
++ {0x3A, 0x00},
++ {0x3B, 0x50},
++ {0x3C, 0x10},
++ {0x3D, 0x50},
++ {0x3E, 0x00},
++ {0x3F, 0x28},
++ {0x40, 0x00},
++ {0x41, 0xA0},
++
++ // To avoid AWB tracking @ max AGC gain even though AE is unstable state
++ {0xfc, 0x00},
++ {0xba, 0x50}, // AE Target minus AE Average
++ {0xbb, 0x00},
++ {0xbc, 0x00},
++
++ // 3. AE weight & etc linear
++ // AE Window Weight linear(EVT1)0929
++ {0xfc, 0x20}, // upper window weight zero
++
++ {0x60, 0x11},
++ {0x61, 0x11},
++ {0x62, 0x11},
++ {0x63, 0x11},
++ {0x64, 0x11},
++ {0x65, 0x11},
++ {0x66, 0x11},
++ {0x67, 0x11},
++ {0x68, 0x11},
++ {0x69, 0x11},
++ {0x6a, 0x11},
++ {0x6b, 0x11},
++ {0x6c, 0x11},
++ {0x6d, 0x11},
++ {0x6e, 0x11},
++ {0x6f, 0x11},
++ {0x70, 0x11},
++ {0x71, 0x11},
++ {0x72, 0x11},
++ {0x73, 0x11},
++ {0x74, 0x11},
++ {0x75, 0x11},
++ {0x76, 0x11},
++ {0x77, 0x11},
++ {0x78, 0x11},
++ {0x79, 0x11},
++ {0x7a, 0x11},
++ {0x7b, 0x11},
++ {0x7c, 0x11},
++ {0x7d, 0x11},
++ {0x7e, 0x11},
++ {0x7f, 0x11},
++
++ // AE window Weight setting End
++ //hue gain linear
++ {0xfc, 0x00},
++
++ {0x48, 0x40},
++ {0x49, 0x40},
++ {0x4a, 0x00},
++ {0x4b, 0x00},
++ {0x4c, 0x40},
++ {0x4d, 0x40},
++ {0x4e, 0x00},
++ {0x4f, 0x00},
++ {0x50, 0x40},
++ {0x51, 0x40},
++ {0x52, 0x00},
++ {0x53, 0x00},
++ {0x54, 0x40},
++ {0x55, 0x40},
++ {0x56, 0x00},
++ {0x57, 0x00},
++ {0x58, 0x40},
++ {0x59, 0x40},
++ {0x5a, 0x00},
++ {0x5b, 0x00},
++ {0x5c, 0x40},
++ {0x5d, 0x40},
++ {0x5e, 0x00},
++ {0x5f, 0x00},
++ {0x62, 0x00}, //hue enable OFF
++
++ // 4. shading (FlexÇâ 3000K manual shading)
++ {0xfc, 0x09},
++ // DSP9_SH_WIDTH_H
++ {0x01, 0x06},
++ {0x02, 0x40},
++ // DSP9_SH_HEIGHT_H
++ {0x03, 0x04},
++ {0x04, 0xB0},
++ {0x05, 0x03},
++ {0x06, 0x13},
++ {0x07, 0x02},
++ {0x08, 0x5A},
++ {0x09, 0x03},
++ {0x0A, 0x15},
++ {0x0B, 0x02},
++ {0x0C, 0x5B},
++ {0x0D, 0x03},
++ {0x0E, 0x0D},
++ {0x0F, 0x02},
++ {0x10, 0x5D},
++ {0x1D, 0x80},
++ {0x1E, 0x00},
++ {0x1F, 0x80},
++ {0x20, 0x00},
++ {0x23, 0x80},
++ {0x24, 0x00},
++ {0x21, 0x80},
++ {0x22, 0x00},
++ {0x25, 0x80},
++ {0x26, 0x00},
++ {0x27, 0x80},
++ {0x28, 0x00},
++ {0x2B, 0x80},
++ {0x2C, 0x00},
++ {0x29, 0x80},
++ {0x2A, 0x00},
++ {0x2D, 0x80},
++ {0x2E, 0x00},
++ {0x2F, 0x80},
++ {0x30, 0x00},
++ {0x33, 0x80},
++ {0x34, 0x00},
++ {0x31, 0x80},
++ {0x32, 0x00},
++ // DSP9_SH_VAL_R0H
++ {0x35, 0x01},
++ {0x36, 0x00},
++ {0x37, 0x01},
++ {0x38, 0x0F},
++ {0x39, 0x01},
++ {0x3A, 0x42},
++ {0x3B, 0x01},
++ {0x3C, 0x9C},
++ {0x3D, 0x01},
++ {0x3E, 0xD0},
++ {0x3F, 0x02},
++ {0x40, 0x0F},
++ {0x41, 0x02},
++ {0x42, 0x3D},
++ {0x43, 0x02},
++ {0x44, 0x5E},
++ {0x45, 0x01},
++ {0x46, 0x00},
++ {0x47, 0x01},
++ {0x48, 0x0A},
++ {0x49, 0x01},
++ {0x4A, 0x2E},
++ {0x4B, 0x01},
++ {0x4C, 0x66},
++ {0x4D, 0x01},
++ {0x4E, 0x89},
++ {0x4F, 0x01},
++ {0x50, 0xB7},
++ {0x51, 0x01},
++ {0x52, 0xD8},
++ {0x53, 0x01},
++ {0x54, 0xFA},
++ // DS9_SH_VAL_B0H
++ {0x55, 0x01},
++ {0x56, 0x00},
++ {0x57, 0x01},
++ {0x58, 0x0A},
++ {0x59, 0x01},
++ {0x5A, 0x28},
++ {0x5B, 0x01},
++ {0x5C, 0x59},
++ {0x5D, 0x01},
++ {0x5E, 0x7A},
++ {0x5F, 0x01},
++ {0x60, 0xA1},
++ {0x61, 0x01},
++ {0x62, 0xC0},
++ {0x63, 0x01},
++ {0x64, 0xDC},
++ // DSP9_SH_M_R2_R1H
++ {0x65, 0x00},
++ {0x66, 0x9F},
++ {0x67, 0xE6},
++ {0x68, 0x02},
++ {0x69, 0x7F},
++ {0x6A, 0x9B},
++ {0x6B, 0x05},
++ {0x6C, 0x9F},
++ {0x6D, 0x1E},
++ {0x6E, 0x07},
++ {0x6F, 0xA6},
++ {0x70, 0xCC},
++ {0x71, 0x09},
++ {0x72, 0xFE},
++ {0x73, 0x6E},
++ {0x74, 0x0C},
++ {0x75, 0xA6},
++ {0x76, 0x04},
++ {0x77, 0x0F},
++ {0x78, 0x9D},
++ {0x79, 0x8C},
++ // DSP9_SH_M_R2_G1H
++ {0x7A, 0x00},
++ {0x7B, 0x9F},
++ {0x7C, 0x95},
++ {0x7D, 0x02},
++ {0x7E, 0x7E},
++ {0x7F, 0x54},
++ {0x80, 0x05},
++ {0x81, 0x9C},
++ {0x82, 0x3E},
++ {0x83, 0x07},
++ {0x84, 0xA2},
++ {0x85, 0xE3},
++ {0x86, 0x09},
++ {0x87, 0xF9},
++ {0x88, 0x53},
++ {0x89, 0x0C},
++ {0x8A, 0x9F},
++ {0x8B, 0x8D},
++ {0x8C, 0x0F},
++ {0x8D, 0x95},
++ {0x8E, 0x91},
++ // DSP9_SH_M_R2_B1H
++ {0x8F, 0x00},
++ {0x90, 0xA1},
++ {0x91, 0xFF},
++ {0x92, 0x02},
++ {0x93, 0x87},
++ {0x94, 0xFD},
++ {0x95, 0x05},
++ {0x96, 0xB1},
++ {0x97, 0xFA},
++ {0x98, 0x07},
++ {0x99, 0xC0},
++ {0x9A, 0x79},
++ {0x9B, 0x0A},
++ {0x9C, 0x1F},
++ {0x9D, 0xF6},
++ {0x9E, 0x0C},
++ {0x9F, 0xD0},
++ {0xA0, 0x74},
++ {0xA1, 0x0F},
++ {0xA2, 0xD1},
++ {0xA3, 0xF1},
++ // DSP9_SH_SUB_RR0H
++ {0xA4, 0x66},
++ {0xA5, 0x76},
++ {0xA6, 0x22},
++ {0xA7, 0x27},
++ {0xA8, 0x14},
++ {0xA9, 0x7E},
++ {0xAA, 0x1F},
++ {0xAB, 0x86},
++ {0xAC, 0x1B},
++ {0xAD, 0x52},
++ {0xAE, 0x18},
++ {0xAF, 0x1B},
++ {0xB0, 0x15},
++ {0xB1, 0x92},
++ // DSP9_SH_SUB_RG0H
++ {0xB2, 0x66},
++ {0xB3, 0xAA},
++ {0xB4, 0x22},
++ {0xB5, 0x38},
++ {0xB6, 0x14},
++ {0xB7, 0x88},
++ {0xB8, 0x1F},
++ {0xB9, 0x97},
++ {0xBA, 0x1B},
++ {0xBB, 0x60},
++ {0xBC, 0x18},
++ {0xBD, 0x28},
++ {0xBE, 0x15},
++ {0xBF, 0x9D},
++ // DSP9_SH_SUB_RB0H
++ {0xC0, 0x65},
++ {0xC1, 0x23},
++ {0xC2, 0x21},
++ {0xC3, 0xB6},
++ {0xC4, 0x14},
++ {0xC5, 0x3A},
++ {0xC6, 0x1F},
++ {0xC7, 0x1E},
++ {0xC8, 0x1A},
++ {0xC9, 0xF8},
++ {0xCA, 0x17},
++ {0xCB, 0xCC},
++ {0xCC, 0x15},
++ {0xCD, 0x4A},
++ {0x00, 0x02}, // shading on
++
++ {0xfc, 0x00},
++ {0x79, 0xf4},
++ {0x7a, 0x09},
++
++ // 5.color correction
++ // 1229 CCM
++ // 2.0251 -1.0203 -0.0048
++ // -0.7080 1.8970 -0.1889
++ // -0.468 -0.444 1.912
++
++ {0xfc, 0x01},
++ {0x51, 0x08}, //R
++ {0x52, 0x18},
++ {0x53, 0xfb},
++ {0x54, 0xec},
++ {0x55, 0xff},
++ {0x56, 0xfc},
++ {0x57, 0xfd}, //G
++ {0x58, 0x2c},
++ {0x59, 0x07},
++ {0x5a, 0x95},
++ {0x5b, 0xff},
++ {0x5c, 0x3f},
++ {0x5d, 0xfe}, //B
++ {0x5e, 0x22},
++ {0x5f, 0xfe},
++ {0x60, 0x3a},
++ {0x61, 0x07},
++ {0x62, 0xa5},
++
++ //6.gamma
++ //Gamma
++ {0xfc, 0x01},
++
++ // R
++ {0x6F, 0x05},
++ {0x70, 0x14},
++ {0x71, 0x3c},
++ {0x72, 0x96},
++ {0x73, 0x00},
++
++ {0x74, 0x2c},
++ {0x75, 0xa2},
++ {0x76, 0xfc},
++ {0x77, 0x44},
++ {0x78, 0x56},
++
++ {0x79, 0x80},
++ {0x7A, 0xb7},
++ {0x7B, 0xed},
++ {0x7C, 0x16},
++ {0x7D, 0xab},
++
++ {0x7E, 0x3c},
++ {0x7F, 0x61},
++ {0x80, 0x83},
++ {0x81, 0xa4},
++ {0x82, 0xff},
++
++ {0x83, 0xc4},
++ {0x84, 0xe2},
++ {0x85, 0xff},
++ {0x86, 0xff},
++
++ // G
++ {0x87, 0x05},
++ {0x88, 0x14},
++ {0x89, 0x3c},
++ {0x8A, 0x96},
++ {0x8B, 0x00},
++
++ {0x8C, 0x2c},
++ {0x8D, 0xa2},
++ {0x8E, 0xfc},
++ {0x8F, 0x44},
++ {0x90, 0x56},
++
++ {0x91, 0x80},
++ {0x92, 0xb7},
++ {0x93, 0xed},
++ {0x94, 0x16},
++ {0x95, 0xab},
++
++ {0x96, 0x3c},
++ {0x97, 0x61},
++ {0x98, 0x83},
++ {0x99, 0xa4},
++ {0x9A, 0xff},
++
++ {0x9B, 0xc4},
++ {0x9C, 0xe2},
++ {0x9D, 0xff},
++ {0x9E, 0xff},
++
++ //B
++ {0x9F, 0x05},
++ {0xA0, 0x10},
++ {0xA1, 0x30},
++ {0xA2, 0x70},
++ {0xA3, 0x00},
++
++ {0xA4, 0x2c},
++ {0xA5, 0xa2},
++ {0xA6, 0xfc},
++ {0xA7, 0x44},
++ {0xA8, 0x56},
++
++ {0xA9, 0x80},
++ {0xAA, 0xb7},
++ {0xAB, 0xed},
++ {0xAC, 0x16},
++ {0xAD, 0xab},
++
++ {0xAE, 0x3c},
++ {0xAF, 0x61},
++ {0xB0, 0x83},
++ {0xB1, 0xa4},
++ {0xB2, 0xff},
++
++ {0xB3, 0xc4},
++ {0xB4, 0xe2},
++ {0xB5, 0xff},
++ {0xB6, 0xff},
++
++ // 7.hue
++ {0xFC, 0x00},
++ {0x62, 0x00}, // hue auto control off
++
++ {0xFC, 0x05},
++ {0x4E, 0x60},
++ {0x4F, 0xA0},
++ {0x50, 0x35},
++ {0x51, 0xA0},
++ {0x52, 0x20},
++ {0x53, 0x01},
++ {0x54, 0xE0},
++ {0x55, 0xE0},
++ {0x56, 0x54},
++ {0x57, 0x20},
++ {0x58, 0x20},
++ {0x59, 0xF0},
++
++ // 8.white point
++ // AWB Start Point
++ {0xfc, 0x07},
++ {0x05, 0x00},
++ {0x06, 0x08},
++ {0x07, 0x1b},
++ {0x08, 0xf0},
++ {0x09, 0x00}, // R
++ {0x0a, 0xa8},
++ {0x0b, 0x00}, // B
++ {0x0c, 0xb0},
++ {0x0d, 0x00}, // G
++ {0x0e, 0x40},
++
++ {0xfc, 0x00},
++ {0x70, 0x02},
++
++ {0x40, 0x8a}, //2000K
++ {0x41, 0xe5},
++ {0x42, 0x95}, //3100K
++ {0x43, 0xba},
++ {0x44, 0xbc}, //5100K
++ {0x45, 0x99},
++
++ {0x34, 0x24},
++ {0x35, 0x10},
++ {0x36, 0x13},
++ {0x37, 0x04},
++ {0x38, 0x10},
++ {0x39, 0x28},
++ {0x3a, 0x1e},
++ {0x3b, 0x2a},
++ {0x31, 0x00}, // skin tone[6], CW delete[5]
++
++ // Added by SOP at 02/09/2006
++ {0xfc, 0x00},
++ {0x02, 0x01} // Image format from UXGA to VGA
++ // 0: UXGA, 1: SXGA, 2: VGA, 3: QVGA, 4: QQVGA, 5: CIF, 6: QCIF
++};
++
++
++// For UXGA (1600 x 1200 = 2M) on 3BA module
++s5k3xa_t s5k3ba_reg_uxga[] =
++{
++
++//[[CAMIF_POWER_UP]]
++{0xfc, 0x02},
++{0x52, 0x86}, // PLL M
++//{0x52, 0x80}, // PLL M
++//{0x52, 0x64}, // PLL M
++{0xfc, 0x01},
++{0x04, 0x03}, // Original ARM Clock Divider
++//{0x04, 0x02},
++{0xfc, 0x02},
++//{0x50, 0x5B}, //Original
++{0x50, 0x59}, // Input Clock 25Mhz
++{0xfc, 0x02},
++{0x30, 0x84}, // Analog offset
++{0x3d, 0x26}, // ADLC enable
++{0x4f, 0x7a}, // I/O driving strength 7mA
++//s45c0 // CDS S1S timing for HN Á¦°Å <- CC
++{0xfc, 0x03},
++//{0x00, 0x02},
++//s2d03 //02
++{0xfc, 0x07},
++{0x58, 0x10},
++{0x59, 0x00},
++{0x5a, 0x00},
++{0x5b, 0x6c},
++{0xfc, 0xf0},
++{0x00, 0x40},
++{0xfc, 0x01},
++//{0x02, 0x02}, // YCbCr Order
++//sfc05
++//s112e // Cb coef.
++{0xfc, 0x05}, // YCbCr Coef
++{0x11, 0x2e},
++//s113d //2e // Blue saturation
++{0x75, 0x05}, // scaler input vsync start
++{0x8c, 0xb1}, // CLIP V size L
++{0x8d, 0x04}, // CLIP V size H
++{0x77, 0xb1}, // scaler input vsync height
++{0xfc, 0x03}, // UXGA Size
++{0x12, 0x05},
++{0x26, 0xb1},
++{0x27, 0x04},
++{0x14, 0xb1},
++///////////////////////////////////////////
++{0xfc, 0x02},
++{0x4a, 0xc1}, // SC type
++{0x37, 0x16}, // SC type
++{0x47, 0xc4}, // r-ramp by chin
++//////////////////////////////////////////
++
++//////////////////////////////////////////
++// Must Mirro Function
++{0xfc, 0x07},
++{0x69, 0x00}, // Mirror XOR
++{0xfc, 0x00},
++{0x23, 0x91}, // Disable wcp/wrd
++// End Mirror
++//////////////////////////////////////////
++
++/////////////////////////////////////////
++// Special Effect Cr Cb setting
++{0xfc, 0x07},
++{0x30, 0x20},
++{0x31, 0xc0},
++{0x32, 0xc0},
++{0x33, 0x40},
++// End
++/////////////////////////////////////////
++
++// AWB Window Area
++//sfc01
++//sc401
++//sc54e
++//sc76e
++
++// color matrix
++{0xfc, 0x01},
++{0x51, 0x06}, //06
++{0x52, 0x68}, //68 //68
++{0x53, 0xFE}, //FE
++{0x54, 0x23}, //23
++{0x55, 0xFF}, //FF
++{0x56, 0x88}, //88
++ //
++{0x57, 0xFE}, //FE
++{0x58, 0x00}, //00
++{0x59, 0x07}, //07
++{0x5A, 0x1F}, ////1F //1F //1F
++{0x5B, 0xFE}, //FE
++{0x5C, 0xF3}, //F3
++ //
++{0x5D, 0xFF}, //FF
++{0x5E, 0x00}, //00
++{0x5F, 0xFC}, //FC
++{0x60, 0x6F}, //df //6F //6F
++{0x61, 0x08}, //08
++{0x62, 0x9F}, //bf //9F //9F
++
++//Edge
++{0xfc, 0x05},
++{0x2c, 0x0f}, //0a //10 //14 // positive gain
++{0x30, 0x0c}, //10 //14 // negative edge gain
++{0x34, 0x12}, /////// // APTCLP
++{0x35, 0x06}, //0c //0a // APTSC
++{0x36, 0x0b}, // ENHANCE
++{0x3f, 0x00}, // NON-LIN
++{0x45, 0x30}, // EGREF
++{0x47, 0x60}, // LLREF
++{0x48, 0x08}, // by chin
++{0x49, 0x39}, // CSSEL EGSEL CS_DLY by
++{0x47, 0x00},
++{0x40, 0x41}, // Y delay
++//Gamma 2
++{0xfc, 0x01},
++{0x6F, 0x08}, // R
++{0x70, 0x10},
++{0x71, 0x40},
++{0x72, 0xd0},
++{0x73, 0x00},
++{0x74, 0xa8},
++{0x75, 0x08},
++{0x76, 0x68},
++{0x77, 0xba},
++{0x78, 0x6a},
++{0x79, 0x08},
++{0x7A, 0x4a},
++{0x7B, 0x6c},
++{0x7C, 0x8a},
++{0x7D, 0xff},
++{0x7E, 0x9e},
++{0x7F, 0xb0},
++{0x80, 0xc0},
++{0x81, 0xd0},
++{0x82, 0xff},
++{0x83, 0xde},
++{0x84, 0xe6},
++{0x85, 0xea},
++{0x86, 0xff},
++{0x87, 0x08}, //G
++{0x88, 0x40},
++{0x89, 0x78},
++{0x8A, 0xf0},
++{0x8B, 0x00},
++{0x8C, 0xb0},
++{0x8D, 0x10},
++{0x8E, 0x68},
++{0x8F, 0xb6},
++{0x90, 0x6a},
++{0x91, 0x04},
++{0x92, 0x30},
++{0x93, 0x53},
++{0x94, 0x74},
++{0x95, 0xff},
++{0x96, 0x8d},
++{0x97, 0xa2},
++{0x98, 0xb6},
++{0x99, 0xc8},
++{0x9A, 0xff},
++{0x9B, 0xd6},
++{0x9C, 0xe0},
++{0x9D, 0xea},
++{0x9E, 0xff},
++{0x9F, 0x08}, //B
++{0xA0, 0x40},
++{0xA1, 0x78},
++{0xA2, 0xf0},
++{0xA3, 0x00},
++{0xA4, 0xb0},
++{0xA5, 0x10},
++{0xA6, 0x68},
++{0xA7, 0xba},
++{0xA8, 0x6a},
++{0xA9, 0x08},
++{0xAA, 0x3a},
++{0xAB, 0x60},
++{0xAC, 0x80},
++{0xAD, 0xff},
++{0xAE, 0x95},
++{0xAF, 0xa8},
++{0xB0, 0xba},
++{0xB1, 0xcc},
++{0xB2, 0xff},
++{0xB3, 0xd8},
++{0xB4, 0xe2},
++{0xB5, 0xea},
++{0xB6, 0xff},
++{0xfc, 0x00}, // Hue Gain
++{0x48, 0x44},
++{0x49, 0x60},
++{0x4a, 0x00},
++{0x4b, 0x18},
++{0x4c, 0x58},
++{0x4d, 0x70}, //60
++{0x4e, 0x00},
++{0x4f, 0x00},
++{0x50, 0x44},
++{0x51, 0x60},
++{0x52, 0x00},
++{0x53, 0x18},
++{0x54, 0x58},
++{0x55, 0x70}, //60
++{0x56, 0x00},
++{0x57, 0x00},
++{0x58, 0x44},
++{0x59, 0x60},
++{0x5a, 0x00},
++{0x5b, 0x18},
++{0x5c, 0x50},
++{0x5d, 0x48},
++{0x5e, 0x08},
++{0x5f, 0x05}, //00
++//ISP_tuning
++{0xfc, 0x00},
++{0x01, 0x00}, // I2C hold mode off
++//s2222 // I2C master ctrl.
++//s2d5a // frame AE start 50
++{0x3e, 0x10}, // Y_min Y min level limit value of AWB ODM
++{0xfc, 0x01},
++{0x00, 0x00}, // ISP BPR Off
++{0x0c, 0x02}, // Full YC
++{0xc8, 0xe0}, //f0 // AWB Y Max
++////////////////////////////////
++// 2005.07.17 cspyo set
++///////////////////////////////
++{0xfc, 0x00},
++{0x24, 0x45}, // zoom skip 5fps
++{0x6c, 0xb8}, //ba //d2 //d8 // AE target
++{0x6d, 0x00}, //
++{0x78, 0x60}, // AGC Max
++{0x79, 0xfb}, //fc // R gain
++{0x7a, 0x03}, // B gain
++{0x81, 0x00}, // AWB G gain suppress disable
++{0x29, 0x04}, // Y level
++{0x2a, 0x10}, //50 // Y level
++{0x2b, 0x04}, // color level H
++{0x2c, 0x00}, //20 // color level L
++{0xfc, 0x07},
++{0x11, 0x00}, // G offset
++{0x37, 0x00}, // Flicker Add
++{0xfc, 0x00},
++{0x72, 0xa0}, // Flicker for 32MHz
++{0x74, 0x08}, // flicker 60Hz
++{0xfc, 0x05},
++{0x64, 0x02}, // Darkslice R
++{0x65, 0xfe}, // Darkslice G
++{0x66, 0xff}, // Darkslice B
++////////////////////////////////////
++{0xfc, 0x00},
++{0x7e, 0xfc},
++//s7e8c //NR GrGb off
++// [7]: BPR [6]:Noise Filter(1D/NR) [4]: GrGb Enable [3]:BPR Data Threshold
++// [2]: color suppress [1]: Y gain suppress [0]: Digital Clamp
++///////////////////////////////////
++////////////////////////////////////
++// GrGb Correction setting
++{0xfc, 0x01},
++{0x44, 0x0c},
++//s4400
++/// [4]: GrGb full [3]: GrGb On
++/// [2]: GrGb Rb On
++{0xfc, 0x0b},
++{0x21, 0x00}, // Start AGC
++{0x22, 0x10}, // AGCMIN
++{0x23, 0x50}, // AGCMAX
++{0x24, 0x18}, //0e //12 //17 // G Th AGCMIN(23d)
++{0x25, 0x32}, // G Th AGCMAX(50d)
++{0x26, 0x18}, //0e //12 //17 // RB Th AGCMIN
++{0x27, 0x32}, // RB Th AGCMAX
++// GrGb Correction setting End
++///////////////////////////////////
++// BPR Setting
++{0xfc, 0x01},
++{0x3f, 0x00}, // setting because S/W bug
++{0xfc, 0x0b},
++{0x0b, 0x00}, // ISP BPR On Start
++{0x0c, 0x00}, // Th13 AGC Min
++{0x0d, 0x40}, //5a // Th13 AGC Max
++{0x0e, 0x01}, //00 // Th1 Max H for AGCMIN
++{0x0f, 0xff}, //c0 // Th1 Max L for AGCMIN
++{0x10, 0x00}, // Th1 Min H for AGCMAX
++{0x11, 0x10}, //00 // Th1 Min L for AGCMAX
++{0x12, 0xff}, // Th3 Max H for AGCMIN
++{0x13, 0xff}, // Th3 Max L for AGCMIN
++{0x14, 0xff}, // Th3 Min H for AGCMAX
++{0x15, 0xff}, // Th3 Min L for AGCMAX
++///////////////////////////////////////////
++// NR Setting
++{0xfc, 0x01},
++{0x4b, 0x01}, // NR Enable
++//s4b00 // NR Enable
++{0xfc, 0x0b},
++{0x28, 0x00}, //NR Start AGC
++{0x29, 0x00}, // SIG Th AGCMIN H
++{0x2a, 0x0a}, //14 // SIG Th AGCMIN L
++{0x2b, 0x00}, // SIG Th AGCMAX H
++{0x2c, 0x0a}, //14 // SIG Th AGCMAX L
++{0x2d, 0x00}, // PRE Th AGCMIN H
++{0x2e, 0x70}, //50 //64 // PRE Th AGCMIN L(100d)
++{0x2f, 0x01}, // PRE Th AGCMAX H(300d)
++{0x30, 0x2c}, // PRE Th AGCMAX L
++{0x31, 0x00}, // POST Th AGCMIN H
++{0x32, 0x70}, //50 //64 // POST Th AGCMIN L(100d)
++{0x33, 0x01}, // POST Th AGCMAX H(300d)
++{0x34, 0x2c}, // POST Th AGCMAX L
++// NR Setting End
++////////////////////////////////
++// Color suppress setting
++{0xfc, 0x0b},
++{0x08, 0x50}, // C suppress AGC MIN
++{0x09, 0x04}, // C suppress MIN H
++{0x0a, 0x00}, // C suppress MIN L
++// C Suppress Setting End
++///////////////////////////////
++// 1D Y LPF Filter
++{0xfc, 0x01},
++//s05e0 // Default s60
++{0x05, 0x60}, // Default s60
++//[7]: Y LPF filter On [6]: Clap On
++{0xfc, 0x0b},
++{0x35, 0x00}, // YLPF Start AGC
++{0x36, 0x50}, // YLPF01 AGCMIN
++{0x37, 0x50}, // YLPF01 AGCMAX
++{0x38, 0x00}, // YLPF SIG01 Th AGCMINH
++{0x39, 0x00}, // YLPF SIG01 Th AGCMINL
++{0x3a, 0x00}, // YLPF SIG01 Th AGCMAXH
++{0x3b, 0xa0}, // YLPF SIG01 Th AGCMAXH
++{0x3c, 0x50}, // YLPF02 AGCMIN
++{0x3d, 0x50}, // YLPF02 AGCMAX
++{0x3e, 0x00}, // YLPF SIG02 Th AGCMINH
++{0x3f, 0x00}, // YLPF SIG02 Th AGCMINL
++{0x40, 0x00}, // YLPF SIG02 Th AGCMAXH
++{0x41, 0xa0}, // YLPF SIG02 Th AGCMAXH
++// Y LPF Filter setting End
++//------------------------------------------------------------------
++/// Set File
++/// - S5K3BAFB_CRF_June02+yihan_050707.xls generates
++/// - date : 2005-07-08
++///------------------------------------------------------------------
++/// Page : ISP Page 9
++{0xfc, 0x09},
++{0x00, 0x02}, // shading on
++{0x01, 0x06}, // size
++{0x02, 0x40},
++{0x03, 0x04},
++{0x04, 0xB0},
++{0x05, 0x03}, // shading center R
++{0x06, 0x19},
++{0x07, 0x02},
++{0x08, 0x75},
++{0x09, 0x03}, // shading center R
++{0x0A, 0x1b},
++{0x0b, 0x02},
++{0x0c, 0x7a},
++{0x0d, 0x03}, // shading center R
++{0x0e, 0x09},
++{0x0f, 0x02},
++{0x10, 0x7d},
++{0x35, 0x00}, // shading R
++{0x36, 0xff},
++{0x37, 0x01},
++{0x38, 0x06},
++{0x39, 0x01},
++{0x3A, 0x1d},
++{0x3B, 0x01},
++{0x3C, 0x44},
++{0x3D, 0x01},
++{0x3E, 0x5d},
++{0x3F, 0x01},
++{0x40, 0x7c},
++{0x41, 0x01},
++{0x42, 0x97},
++{0x43, 0x01},
++{0x44, 0xba},
++{0x45, 0x01}, // shading G
++{0x46, 0x01},
++{0x47, 0x01},
++{0x48, 0x08},
++{0x49, 0x01},
++{0x4A, 0x1d},
++{0x4B, 0x01},
++{0x4C, 0x40},
++{0x4D, 0x01},
++{0x4E, 0x58},
++{0x4F, 0x01},
++{0x50, 0x73},
++{0x51, 0x01},
++{0x52, 0x8a},
++{0x53, 0x01},
++{0x54, 0xa6},
++{0x55, 0x00}, // shading B
++{0x56, 0xff},
++{0x57, 0x01},
++{0x58, 0x05},
++{0x59, 0x01},
++{0x5A, 0x1a},
++{0x5B, 0x01},
++{0x5C, 0x3c},
++{0x5D, 0x01},
++{0x5E, 0x52},
++{0x5F, 0x01},
++{0x60, 0x6e},
++{0x61, 0x01},
++{0x62, 0x8b},
++{0x63, 0x01},
++{0x64, 0xb3},
++// sub-sampling
++{0xfc, 0x03},
++//{0x2d, 0x01}, // UXGA YCrCb Order
++{0x2d, 0x06}, // UXGA YCrCb Order
++{0x12, 0x05},
++{0x26, 0xb1},
++{0x27, 0x04},
++{0x14, 0xb1},
++{0xfc, 0x04},
++{0x14, 0xb1},
++{0x72, 0x05}, // H2 V1
++{0x74, 0xb1},
++{0xa2, 0x05}, // H1 V2
++{0xa3, 0x02},
++{0xa4, 0x59},
++{0xa7, 0x59},
++{0xa8, 0x02},
++{0xae, 0x59},
++{0xaf, 0x02},
++{0xb6, 0x59},
++{0xb7, 0x02},
++{0xd2, 0x05}, // H2 V2
++{0xd3, 0x02},
++{0xd4, 0x59},
++{0xd7, 0x59},
++{0xd8, 0x02},
++{0xde, 0x59},
++{0xdf, 0x02},
++{0xe6, 0x59},
++{0xe7, 0x02},
++{0xfc, 0x14}, // H4 V1
++{0x05, 0x98},
++{0x0e, 0x02},
++{0x12, 0x05},
++{0x13, 0x04},
++{0x14, 0xb1},
++{0x17, 0xb0},
++{0x18, 0x04},
++{0x1e, 0xb0},
++{0x1f, 0x04},
++{0x26, 0xb1},
++{0x27, 0x04},
++{0x35, 0x98}, // H4 V4
++{0x3e, 0x02},
++{0x42, 0x05},
++{0x43, 0x01},
++{0x44, 0x2d},
++{0x47, 0x2d},
++{0x48, 0x01},
++{0x4e, 0x2d},
++{0x4f, 0x01},
++{0x56, 0x2e},
++{0x57, 0x01},
++// AE Window Size control for sub-sampling
++{0xfc, 0x06},
++{0x12, 0x00}, // H=2 V=1(800*1200)
++{0x13, 0x61}, // AE H End
++{0x16, 0x00}, // AE V End
++{0x17, 0x94},
++{0x22, 0x00}, // H=1 V=2(1600*600)
++{0x23, 0xc5}, // AE H End
++{0x26, 0x00}, // AE V End
++{0x27, 0x4b},
++{0x32, 0x00}, // H=2 V=2(800*600)
++{0x33, 0x61}, // AE H End
++{0x36, 0x00}, // AE V End
++{0x37, 0x48},
++{0x38, 0x00}, // AWB Window Size
++{0x39, 0x0a},
++{0x3a, 0x00},
++{0x3b, 0x61},
++{0x3c, 0x00},
++{0x3d, 0x75},
++{0x3e, 0x00},
++{0x3f, 0x3e},
++{0x42, 0x00}, // H=4 V=1(400*1200)
++{0x43, 0x2f}, // AE H End
++{0x46, 0x00}, // AE V End
++{0x47, 0x97},
++{0x52, 0x00}, // H=4 V=4(400*300)
++{0x53, 0x30}, // AE H End
++{0x56, 0x00}, // AE V End
++{0x57, 0x26},
++// white point
++{0xfc, 0x00},
++{0x40, 0x78}, //7d a
++{0x41, 0xe0}, //e2
++{0x42, 0x83}, //95 12
++{0x43, 0xc6}, //ba c
++{0x44, 0xad}, //bc f
++{0x45, 0x9d}, //99 4
++{0x34, 0x18}, //115
++{0x35, 0x14}, //02
++{0x36, 0x04}, //04
++{0x37, 0x12}, //04
++{0x38, 0x06}, //03
++{0x39, 0x1d}, //18 //25
++{0x3a, 0x14}, //12 //22 //1f
++{0x3b, 0x2c}, //16 //18 //1a
++{0xfc, 0x20}, // AE window weight
++{0x60, 0x00},
++{0x61, 0x00},
++{0x62, 0x00},
++{0x63, 0x00},
++{0x64, 0x11},
++{0x65, 0x11},
++{0x66, 0x11},
++{0x67, 0x11},
++{0x68, 0x11},
++{0x69, 0x22},
++{0x6a, 0x22},
++{0x6b, 0x11},
++{0x6c, 0x11},
++{0x6d, 0x22},
++{0x6e, 0x22},
++{0x6f, 0x11},
++{0x70, 0x11},
++{0x71, 0x22},
++{0x72, 0x22},
++{0x73, 0x11},
++{0x74, 0x11},
++{0x75, 0x22},
++{0x76, 0x22},
++{0x77, 0x11},
++{0x78, 0x33},
++{0x79, 0x33},
++{0x7a, 0x33},
++{0x7b, 0x33},
++{0x7c, 0x33},
++{0x7d, 0x33},
++{0x7e, 0x33},
++{0x7f, 0x33},
++{0xfc, 0x01},
++{0x02, 0x02},
++{0xfc, 0x02},
++{0x30, 0x83},
++{0x44, 0x5b}, // clamp enable
++{0x55, 0x03},
++{0xfc, 0x00},
++{0x62, 0x02},
++{0xfc, 0x04},
++{0xee, 0x08},
++{0xfc, 0x03},
++{0x2e, 0x08},
++{0xfc, 0x02},
++{0x11, 0x11},
++{0xfc, 0x01},
++{0x4d, 0x08}, // RV con, Red pixel Ordering
++//{0x01, 0x00}, // PCLK
++{0x01, 0x01}, // Inversion PCLK
++{0xfc, 0x00},
++{0x02, 0x00}, // UXGA Size Out
++};
++
++
++#define S5K3BA_INIT_REGS (sizeof(s5k3ba_reg)/sizeof(s5k3ba_reg[0]))
++#define S5K3BA_UXGA_REGS (sizeof(s5k3ba_reg_uxga)/sizeof(s5k3ba_reg_uxga[0]))
++#define S5K3BA_VGA_REGS (sizeof(s5k3ba_reg_vga)/sizeof(s5k3ba_reg_vga[0]))
++
++
++#define S5K3BA_RISC_REGS 0xEB
++#define S5K3BA_ISP_REGS 0xFB /* S5C7323X */
++#define S5K3BA_CIS_REGS 0x2F /* S5K437LA03 */
++
++
++//#define S5K3AA_REGS (S5K3AA_RISC_REGS+S5K3AA_ISP_REGS+S5K3AA_CIS_REGS)
++#define S5K3BA_REGS (0x1000)
++
++
++#endif
++
+diff --git a/drivers/media/video/samsung/4xa_sensor.c b/drivers/media/video/samsung/4xa_sensor.c
+new file mode 100644
+index 0000000..e68e603
+--- /dev/null
++++ b/drivers/media/video/samsung/4xa_sensor.c
+@@ -0,0 +1,349 @@
++/*
++ * Copyright (C) 2004 Samsung Electronics
++ * SW.LEE <hitchcar@samsung.com>
++ * - based on Russell King : pcf8583.c
++ * - added smdk24a0, smdk2440
++ * - added poseidon (s3c24a0+wavecom)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Driver for FIMC2.x Camera Decoder
++ *
++ */
++
++//#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/i2c-id.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++
++//#define CAMIF_DEBUG
++
++#include "../s3c_camif.h"
++#include "4xa_sensor.h"
++
++static struct i2c_driver sensor_driver;
++
++/* This is an abstract CIS sensor for MSDMA input. */
++
++camif_cis_t msdma_input = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_CBYCRY, /* another case: YCRYCB */
++ camclk: 44000000, /* for 20 fps: 44MHz, for 12 fps(more stable): 26MHz */
++ source_x: 800,
++ source_y: 600,
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 0,
++ polarity_vsync:1,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AL,
++ reset_udelay: 5000,
++};
++
++camif_cis_t interlace_input = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_CBYCRY, /* another case: YCRYCB */
++ camclk: 44000000, /* for 20 fps: 44MHz, for 12 fps(more stable): 26MHz */
++ source_x: 800,
++ source_y: 600,
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 0,
++ polarity_vsync:1,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AL,
++ reset_udelay: 5000,
++};
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++static camif_cis_t data = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_YCBYCR,
++ camclk: 44000000, /* for 20 fps: 44MHz, for 12 fps(more stable): 26MHz */
++ source_x: 800,
++ source_y: 600,
++ win_hor_ofst: 40,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 40,
++ win_ver_ofst2: 0,
++ polarity_pclk: 0,
++ polarity_vsync:1,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AL,
++ reset_udelay: 5000,
++};
++
++s5k4xa_t s5k4ba_regs_mirror[S5K4BA_REGS];
++#else
++#error No samsung CIS moudule here !
++#endif
++
++camif_cis_t* get_initialized_cis(void)
++{
++ if (data.init_sensor == 0)
++ return NULL;
++
++ return &data;
++}
++
++#define CAM_ID 0x5a
++
++static unsigned short ignore[] = { I2C_CLIENT_END };
++static unsigned short normal_addr[] = { (CAM_ID >> 1), I2C_CLIENT_END };
++static unsigned short *forces[] = { NULL };
++
++static struct i2c_client_address_data addr_data = {
++ normal_i2c:normal_addr,
++ /* normal_i2c_range:ignore, */
++ probe:ignore,
++ /* probe_range:ignore, */
++ ignore:ignore,
++ /* ignore_range:ignore, */
++ forces:forces,
++};
++
++
++unsigned char sensor_read(struct i2c_client *client, unsigned char subaddr)
++{
++ int ret;
++ unsigned char buf[1];
++ struct i2c_msg msg = { client->addr, 0, 1, buf };
++ buf[0] = subaddr;
++
++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++ if (ret == -EIO) {
++ printk(" I2C write Error \n");
++ return -EIO;
++ }
++
++ msg.flags = I2C_M_RD;
++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++
++ return buf[0];
++}
++
++static int
++sensor_write(struct i2c_client *client,
++ unsigned char subaddr, unsigned char val)
++{
++ unsigned char buf[2];
++ struct i2c_msg msg = { client->addr, 0, 2, buf };
++
++ buf[0] = subaddr;
++ buf[1] = val;
++
++ return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++}
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++void inline sensor_init(struct i2c_client *sam_client)
++{
++ int i;
++
++ i = (sizeof(s5k4ba_reg)/sizeof(s5k4ba_reg[0]));
++ for (i = 0; i < S5K4BA_INIT_REGS; i++) {
++ sensor_write(sam_client,
++ s5k4ba_reg[i].subaddr, s5k4ba_reg[i].value);
++ }
++}
++#else
++#error No samsung CIS moudule !
++#endif
++
++static int
++s5k4xa_attach(struct i2c_adapter *adap, int addr, int kind)
++{
++ struct i2c_client *c;
++
++ c = kmalloc(sizeof(*c), GFP_KERNEL);
++ if (!c)
++ return -ENOMEM;
++
++ memset(c, 0, sizeof(struct i2c_client));
++
++ strcpy(c->name, "S5K4XA");
++ c->addr = addr;
++ c->adapter = adap;
++ c->driver = &sensor_driver;
++ c->data = &data;
++ data.sensor = c;
++
++ s3c_camif_register_sensor(c);
++
++ return i2c_attach_client(c);
++}
++
++static int sensor_attach_adapter(struct i2c_adapter *adap)
++{
++ s3c_camif_open_sensor(&data);
++ return i2c_probe(adap, &addr_data, s5k4xa_attach);
++}
++
++static int sensor_detach(struct i2c_client *client)
++{
++ i2c_detach_client(client);
++ s3c_camif_unregister_sensor(client);
++ return 0;
++}
++
++/* Purpose:
++ This fucntion only for SVGA Camera : 4BA
++*/
++static int change_sensor_size(struct i2c_client *client, int size)
++{
++ int i;
++
++ switch (size) {
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++ case SENSOR_QSVGA:
++ for (i = 0; i < S5K4BA_QSVGA_REGS; i++) {
++ sensor_write(client, s5k4ba_reg_qsvga[i].subaddr,
++ s5k4ba_reg_qsvga[i].value);
++ }
++ break;
++
++ case SENSOR_SVGA:
++ for (i = 0; i < S5K4BA_SVGA_REGS; i++) {
++ sensor_write(client, s5k4ba_reg_svga[i].subaddr,
++ s5k4ba_reg_svga[i].value);
++ }
++ break;
++#else
++#error No samsung CIS moudule !
++#endif
++ default:
++ panic("4xa_sensor.c: unexpect value\n");
++ }
++
++ return 0;
++}
++
++static int change_sensor_wb(struct i2c_client *client, int type)
++{
++ printk("[ *** Page 0, 4XA Sensor White Balance Mode ***]\n");
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++ sensor_write(client, 0xFC, 0x0);
++ sensor_write(client, 0x30, type);
++#endif
++
++ switch(type){
++ case 0:
++ default:
++ printk(" -> AWB auto mode ]\n");
++ break;
++ case 1:
++ printk(" -> Indoor 3100 mode ]\n");
++ break;
++ case 2:
++ printk(" -> Outdoor 5100 mode ]\n");
++ break;
++ case 3:
++ printk(" -> Indoor 2000 mode ]\n");
++ break;
++ case 4:
++ printk(" -> AE/AWB halt ]\n");
++ break;
++ case 5:
++ printk(" -> Cloudy(6000) mode ]\n");
++ break;
++ case 6:
++ printk(" -> Sunny(8000) mode ]\n");
++ break;
++ }
++
++ return 0;
++}
++
++static int
++sensor_command(struct i2c_client *client, unsigned int cmd, void *arg)
++{
++ switch (cmd) {
++ case SENSOR_INIT:
++ sensor_init(client);
++ printk(KERN_INFO "External Camera initialized\n");
++ break;
++
++ case USER_ADD:
++ break;
++
++ case USER_EXIT:
++ break;
++
++ case SENSOR_QSVGA:
++ change_sensor_size(client, SENSOR_QSVGA);
++ break;
++
++ case SENSOR_VGA:
++ change_sensor_size(client, SENSOR_VGA);
++ break;
++
++ case SENSOR_SVGA:
++ change_sensor_size(client, SENSOR_SVGA);
++ break;
++
++ case SENSOR_SXGA:
++ change_sensor_size(client, SENSOR_SXGA);
++ break;
++
++ case SENSOR_UXGA:
++ change_sensor_size(client, SENSOR_UXGA);
++ break;
++/* Todo
++ case SENSOR_BRIGHTNESS:
++ change_sensor_setting();
++ break;
++*/
++ case SENSOR_WB:
++ printk("[ *** 4XA Sensor White Balance , No mode ***]\n");
++ change_sensor_wb(client, (int) arg);
++ break;
++
++ default:
++ panic("4xa_sensor.c : Unexpect Sensor Command \n");
++ break;
++ }
++
++ return 0;
++}
++
++static struct i2c_driver sensor_driver = {
++ .driver = {
++ .name = "s5k4xa",
++ },
++ .id = I2C_DRIVERID_S5K4XA,
++ .attach_adapter = sensor_attach_adapter,
++ .detach_client = sensor_detach,
++ .command = sensor_command
++};
++
++static __init int camif_sensor_init(void)
++{
++ return i2c_add_driver(&sensor_driver);
++}
++
++
++static __init void camif_sensor_exit(void)
++{
++ i2c_del_driver(&sensor_driver);
++}
++
++module_init(camif_sensor_init)
++module_exit(camif_sensor_exit)
++
++MODULE_AUTHOR("Jinsung, Yang <jsgood.yang@samsung.com>");
++MODULE_DESCRIPTION("I2C Client Driver for FIMC V4L2 Driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/media/video/samsung/4xa_sensor.h b/drivers/media/video/samsung/4xa_sensor.h
+new file mode 100644
+index 0000000..9880f6c
+--- /dev/null
++++ b/drivers/media/video/samsung/4xa_sensor.h
+@@ -0,0 +1,2377 @@
++
++#ifndef _SAMSUNG_SXGA_H_
++#define _SAMSUNG_SXGA_H_
++
++/*******************************************************************************************
++ # Display resolution standards #
++
++ QCIF: 176 x 144
++ CIF: 352 x 288
++ QVGA: 320 x 240
++ VGA: 640 x 480
++ SVGA: 800 x 600
++ XGA: 1024 x 768
++ WXGA: 1280 x 800
++ QVGA: 1280 x 960
++ SXGA: 1280 x 1024
++ SXGA+: 1400 x 1050
++ WSXGA+: 1680 x 1050
++ UXGA: 1600 x 1200
++ WUXGA: 1920 x 1200
++ QXGA: 2048 x 1536
++********************************************************************************************/
++
++//#include "../bits.h"
++
++/* Camera information
++ * FPC Label : Samsung MEGA Pixel Camera : V4220 REV06
++ * Modified by charles -Initial function of '3AA' test routine
++ * Modified and tested by YongHwui.Kim <yonghwui.kim@samsung.com> for S5K3AAEX Camera
++ */
++
++#define CHIP_DELAY 0xFF
++
++typedef struct samsung_t{
++ unsigned char subaddr;
++ unsigned char value;
++ unsigned char page;
++} s5k4xa_t;
++
++#ifdef CONFIG_CPU_S3C24A0A
++#define TRY_HIGH_CLOCK 1
++#endif
++
++ //***************************************************
++ // name: S5K3AAEX EVT2 setfile
++ // ver: v2.61
++ // history:
++ // v0.0 start from 040908 setfile
++ // v1.0 arange register
++ // v1.01 change MCLK(25Mhz) and Frame rate(7fps)
++ // v2.0 adjust register setting for 3AA EVT2
++ // - color correction, RGB shding off, hsync start position, Mirror, fps
++ // - Color Tuning, YGRPDLY
++ // v2.1 change Frame rate(7.5fps) and Total gain to x4
++ // (because of reducing visual noise at low illumination)
++ // - change BPRM AGC Max and FrameAE start
++ // improve AE speed
++ // v2.2 modify AWB G gain and solve 50hz flicker detection fail in 25MHz 7.5fps
++ // v2.3 Adjust gamma, Dark Slice, white point, Hue gain,
++ // White Balance B control, Y gain On, Digital Clamp On
++ // lower AWB G gain
++ // v2.4 Adjust AE window weight, Y Gamma, WhitePoint, Shading and BPR Max Thres.
++ // v2.41 Adjust AE/AWB window and AWB internal window boundary to decrease skin color tracking
++ // v2.411 special version for PSCDS
++ // v2.412 RGB shading off
++ // v2.5 Lens change STW to Sekonix
++ // adjust White point and Y shading Coef (RGB shading off)
++ // v2.6 New Tuning because of Full YC off and YCbCr Coef change
++ // Gamma, Dark Slice, color matrix (not use), Color suppress
++ // R Gain and DBPR agc MIN/MAX
++ // v2.61 VCK inversion(data rising)
++ //***************************************************
++ ///////////////////////////////////////////////////
++
++#if defined(CONFIG_VIDEO_SAMSUNG_S5K4BA)
++
++// For SVGA (800 x 600)
++#if 1 // from han
++s5k4xa_t s5k4ba_reg[] =
++{
++ {0xfc,0x07},
++ {0x66,0x01}, // Watch Dog Time On
++ {0xfc,0x00},
++ {0x00,0xAA}, // For EDS Check
++ {0x21,0x03}, // peter0223 Ãß°¡
++ {0xfc,0x01},
++ {0x04,0x01}, // ARM Clock Divider
++
++ {0xfc,0x02},
++ {0x30,0x90}, // Analog offset
++ {0x37,0x0d}, // Global Gain
++ {0x2d,0x48}, // Double Shutter
++ {0x60,0x00}, // Blank_Adrs
++
++ {0x45,0x1e}, //0e// CDS Timing for Average Sub_Sampling
++ {0x47,0x2f},
++ {0x02,0x0e}, // ADC Resolution
++ {0x3d,0x06}, // Frame ADLC
++ {0x4d,0x08}, // Doubler Volatage
++ {0x54,0x02}, // Double Shutter
++ {0x55,0x1e}, // Line ADLC
++ {0x56,0x30}, //
++ {0x59,0x00}, // LineADLC offset
++ {0x5b,0x08}, // R_Ref_Ctrl
++ {0x44,0x63}, // CLP_EN
++ {0x4A,0x10}, // Clamp Control
++ {0x42,0x02}, //
++ {0x43,0xef}, //
++
++ //==========================================================
++ // Table Set for Sub-Sampling
++ //==========================================================
++ {0xfc,0x03},
++ {0x2c,0x00}, // crcb_sel for Sub-Sampling Table
++ {0x05,0x46}, // Output Image Size Set for Capture
++ {0x07,0xb6},
++ {0x0e,0x04},
++ {0x12,0x03},
++
++ {0xfc,0x04},
++ {0x32,0x04},
++ {0x33,0xbc},
++
++ {0xfc,0x04},
++ {0xc5,0x26}, // Output Image Size Set for Preview
++ {0xc7,0x5e},
++ {0xce,0x04},
++ {0xd2,0x04},
++
++ {0xec,0x06}, //CrCb sel = YCBYCR(0x06) by jsgood
++ {0xc0,0x06},
++ {0xc1,0x70},
++ {0xc2,0x02},
++ {0xc3,0x87},
++
++ {0xfc,0x07},
++ {0x05,0x00},
++ {0x06,0x00},
++ {0x07,0x8b},
++ {0x08,0xf5},
++ {0x09,0x00},
++ {0x0a,0xb4},
++ {0x0b,0x00},
++ {0x0c,0xea},
++ {0x0d,0x00},
++ {0x0e,0x40},
++
++ {0xfc,0x00},
++ {0x70,0x02},
++
++ // Jeongyun added still shot cbcr_sel
++ {0xfc,0x03},
++ {0x2c,0x00},
++ {0x5c,0x00},
++ {0x8c,0x00},
++ {0xbc,0x00},
++ {0xfc,0x04},
++ {0x5c,0x00},
++
++
++ //==========================================================
++ // COMMAND SET
++ //==========================================================
++ {0xfc,0x00},
++ {0x73,0x21}, // Frmae AE Enable peter
++ {0x20,0x02}, // Change AWB Mode
++
++ {0xfc,0x00},
++ {0x6c,0xb0}, // AE target
++ {0x6d,0x00},
++
++ {0xfc,0x20},
++ {0x16,0x5a}, // for Prevating AE Hunting
++
++ {0xfc,0x00},
++ {0x78,0x6a}, // AGC Max
++ {0xfc,0x20},
++ {0x16,0x60}, // Frame AE Start
++
++ {0xfc,0x20},
++ {0x57,0x18}, // Stable_Frame_AE
++ {0x2C,0x30}, // For Forbidden Area
++ {0x2E,0x00}, // For Forbidden Area
++ {0x14,0x70},
++ {0x01,0x00}, // Stepless_Off
++
++ {0xfc,0x07},
++ {0x11,0x02}, // AWB G Gain offset
++
++ {0xfc,0x07},
++ {0x3e,0x0a}, // AWB Cut R max
++
++ {0xfc,0x01},
++ {0xc8,0xd0}, // AWB Y Max e0 Y°ªÀÌ ¾î´À ÀÌ»óÀ϶§ ±× ÀÌ»ó°ªÀ» ©¶ó³»´Â ¼¼Æðª
++ {0xfc,0x00},
++ {0x3e,0x20}, //30 AWB Y_min
++ {0x3d,0x10}, // AWB Y_min Low
++ {0xfc,0x22},
++ {0x8c,0x04}, // AWB Min Y Weight AWB ÇÒ¶§ Y½ÅÈ£¸¦ ±âÁØÀ¸·Î Çϴµ¥ °¡ÁßÄ¡¸¦ ¹Ù²Ù´Â °Í.
++ {0x8d,0x16}, // AWB Max Y Weight
++
++ {0xfc,0x00},
++ {0x32,0x04}, // AWB moving average 8 frame
++ {0x81,0x10}, // AWB G gain suppress Disable
++ {0xbc,0xf0},
++
++ {0x29,0x04}, // Y level H
++ {0x2a,0x00}, // Y level L
++ {0x2b,0x03}, // color level H
++ {0x2c,0xc8}, // color level L
++
++ {0xfc,0x07},
++ {0x37,0x00}, // Flicker Add for 32Mhz
++ {0xfc,0x00},
++ {0x72,0xa0}, // Flicker for 32MHz
++ {0x74,0x08}, // flicker 60Hz Fix
++
++ {0xfc,0x20},
++ {0x02,0x02}, // Flicker Dgain Mode
++
++ {0xfc,0x00},
++ //{0x23,0x40}, // Mirror Option
++ {0x62,0x0a}, // Mirror Option
++
++ {0xfc,0x02},
++ {0x4e,0x00}, // IO current 8mA set
++ {0x4e,0x00}, // IO current 8mA set
++ {0x4e,0x00}, // IO current 8mA set
++ {0x4e,0x00}, // IO current 8mA set
++ {0x4f,0x0a}, // 2a IO current 48mA set
++ {0x4f,0x0a}, // IO current 48mA set
++ {0x4f,0x0a}, // IO current 48mA set
++ {0x4f,0x0a}, // IO current 48mA set
++
++ {0xfc,0x01},
++ {0x0c,0x03}, // Full YC Enable
++ //{0x0c,03}, // Full YC Enable
++ //{0x02,02}, // crcb_sel
++ //{0x02,02}, // crcb_sel peter0222 Ãß°¡
++ //{0x01,01}, // pclk peter0222 Ãß°¡
++ //{0x01,01},
++
++ //==========================================================
++ // COLOR MATRIX
++ //==========================================================
++ {0xfc,0x01}, // color matrix
++ {0x51,0x0A},
++ {0x52,0x42},
++ {0x53,0xF9},
++ {0x54,0x80},
++ {0x55,0x00},
++ {0x56,0x3D},
++
++ {0x57,0xFE},
++ {0x58,0x0B},
++ {0x59,0x06},
++ {0x5A,0x9C},
++ {0x5B,0xFF},
++ {0x5C,0x59},
++
++ {0x5D,0xFF},
++ {0x5E,0xD8},
++ {0x5F,0xFC},
++ {0x60,0x2E},
++ {0x61,0x07},
++ {0x62,0xFA},
++
++ //==========================================================
++ // EDGE ENHANCEMENT
++ //==========================================================
++ {0xfc,0x00},
++ {0x89,0x03}, // Edge Suppress On
++ {0xfc,0x0b},
++ {0x42,0x50}, // Edge AGC MIN
++ {0x43,0x60}, // Edge AGC MAX
++ {0x45,0x18}, // positive gain AGC MIN
++ {0x49,0x0a}, // positive gain AGC MAX
++ {0x4d,0x18}, // negative gain AGC MIN
++ {0x51,0x0a}, // negative gain AGC MAX
++
++ {0xfc,0x05},
++ {0x34,0x20}, // APTCLP
++ {0x35,0x09}, // APTSC
++ {0x36,0x0b}, // ENHANCE
++ {0x3f,0x00}, // NON-LIN
++ {0x42,0x10}, // EGFALL
++ {0x43,0x00}, // HLFALL
++ {0x45,0xa0}, // EGREF
++ {0x46,0x7a}, // HLREF
++ {0x47,0x40}, // LLREF
++ {0x48,0x0c},
++ {0x49,0x31}, // CSSEL EGSEL CS_DLY
++
++ {0x40,0x41}, // Y delay
++
++ //==========================================================
++ // GAMMA
++ //========================================================== -
++ {0xfc,0x01},
++
++ {0x6F,0x0A}, // R
++ {0x70,0x1A},
++ {0x71,0x7A},
++ {0x72,0xF8},
++ {0x73,0x00},
++
++ {0x74,0xA0},
++ {0x75,0x18},
++ {0x76,0x65},
++ {0x77,0xAD},
++ {0x78,0x6A},
++
++ {0x79,0xE2},
++ {0x7A,0x12},
++ {0x7B,0x3D},
++ {0x7C,0x5A},
++ {0x7D,0xBF},
++
++ {0x7E,0x72},
++ {0x7F,0x88},
++ {0x80,0x9D},
++ {0x81,0xB0},
++ {0x82,0xFF},
++
++ {0x83,0xC0},
++ {0x84,0xCF},
++ {0x85,0xDA},
++ {0x86,0xFC},
++
++ {0x87,0x08}, //G
++ {0x88,0x12},
++ {0x89,0x42},
++ {0x8A,0xBA},
++ {0x8B,0x00},
++
++ {0x8C,0x75},
++ {0x8D,0xED},
++ {0x8E,0x42},
++ {0x8F,0x80},
++ {0x90,0x5A},
++
++ {0x91,0xB5},
++ {0x92,0xE5},
++ {0x93,0x10},
++ {0x94,0x35},
++ {0x95,0xAF},
++
++ {0x96,0x55},
++ {0x97,0x70},
++ {0x98,0x88},
++ {0x99,0x9D},
++ {0x9A,0xFF},
++
++ {0x9B,0xB1},
++ {0x9C,0xC4},
++ {0x9D,0xD5},
++ {0x9E,0xFC},
++
++ {0x9F,0x05}, //B
++ {0xA0,0x18},
++ {0xA1,0x42},
++ {0xA2,0xd7},
++ {0xA3,0x00},
++
++ {0xA4,0xB6},
++ {0xA5,0x3b},
++ {0xA6,0x88},
++ {0xA7,0xC8},
++ {0xA8,0x6A},
++
++ {0xA9,0x00},
++ {0xAA,0x30},
++ {0xAB,0x58},
++ {0xAC,0x78},
++ {0xAD,0xFF},
++
++ {0xAE,0x90},
++ {0xAF,0xA5},
++ {0xB0,0xB6},
++ {0xB1,0xC5},
++ {0xB2,0xFF},
++
++ {0xB3,0xD0},
++ {0xB4,0xD6},
++ {0xB5,0xDA},
++ {0xB6,0xFC},
++
++ //==========================================================
++ // HUE CONTROL
++ //==========================================================
++ {0xfc,0x00},
++ {0x48,0x34}, // 2000K
++ {0x49,0x34},
++ {0x4a,0xf4},
++ {0x4b,0x00},
++ {0x4c,0x44},
++ {0x4d,0x3c},
++ {0x4e,0xf0},
++ {0x4f,0x0c},
++
++ {0x50,0x34}, // 3000K
++ {0x51,0x34},
++ {0x52,0xf4},
++ {0x53,0x00},
++ {0x54,0x44},
++ {0x55,0x3c},
++ {0x56,0xf0},
++ {0x57,0x0c},
++
++ {0x58,0x34}, // 5100K
++ {0x59,0x30},
++ {0x5a,0x00},
++ {0x5b,0x04},
++ {0x5c,0x40},
++ {0x5d,0x2c},
++ {0x5e,0xfc},
++ {0x5f,0x04},
++ //==========================================================
++ // UPPRE0x0x FUNCTION
++ //==========================================================
++ {0xfc,0x00},
++ {0x7e,0xf4},
++
++ //==========================================================
++ // BPR
++ //==========================================================
++ {0xfc,0x01},
++ {0x3d,0x10},
++
++ {0xfc,0x0b},
++ {0x0b,0x00}, // ISP BPR On start
++ {0x0c,0x20}, // Th13 AGC Min
++ {0x0d,0x40}, // Th13 AGC Max
++ {0x0e,0x00}, // Th1 Max H for AGCMIN
++ {0x0f,0x20}, // Th1 Max L for AGCMIN
++ {0x10,0x00}, // Th1 Min H for AGCMAX
++ {0x11,0x10}, // Th1 Min L for AGCMAX
++ {0x12,0x00}, // Th3 Max H for AGCMIN
++ {0x13,0x00}, // Th3 Max L for AGCMIN
++ {0x14,0xff}, // Th3 Min H for AGCMAX
++ {0x15,0xff}, // Th3 Min L for AGCMAX
++ {0x16,0x20}, // Th57 AGC Min
++ {0x17,0x40}, // Th57 AGC Max
++ {0x18,0x00}, // Th5 Max H for AGCMIN
++ {0x19,0x00}, // Th5 Max L for AGCMIN
++ {0x1a,0x00}, // Th5 Min H for AGCMAX
++ {0x1b,0x20}, // Th5 Min L for AGCMAX
++ {0x1c,0x00}, // Th7 Max H for AGCMIN
++ {0x1d,0x00}, // Th7 Max L for AGCMIN
++ {0x1e,0x00}, // Th7 Min H for AGCMAX
++ {0x1f,0x20}, // Th7 Min L for AGCMAX
++
++ //==========================================================
++ // GR/GB CORRECTION
++ //==========================================================
++ {0xfc,0x01},
++ {0x45,0x0c},
++
++ {0xfc,0x0b},
++ {0x21,0x00}, // start AGC
++ {0x22,0x18}, // AGCMIN
++ {0x23,0x58}, // AGCMAX
++ {0x24,0x0d}, // G Th AGCMIN
++ {0x25,0x30}, // G Th AGCMAX
++ {0x26,0x0d}, // RB Th AGCMIN
++ {0x27,0x30}, // RB Th AGCMAX
++
++ //==========================================================
++ // NR
++ //==========================================================
++ {0xfc,0x01},
++ {0x4C,0x01}, // NR Enable
++ {0x49,0x15}, // Sig_Th Mult
++ {0x4B,0x0A}, // Pre_Th Mult
++
++ {0xfc,0x0b},
++ {0x28,0x00}, // NR start AGC
++ {0x29,0x00}, // SIG Th AGCMIN H
++ {0x2a,0x14}, // SIG Th AGCMIN L
++ {0x2b,0x00}, // SIG Th AGCMAX H
++ {0x2c,0x14}, // SIG Th AGCMAX L
++ {0x2d,0x00}, // PRE Th AGCMIN H
++ {0x2e,0x90}, // PRE Th AGCMIN L
++ {0x2f,0x01}, // PRE Th AGCMAX H
++ {0x30,0x00}, // PRE Th AGCMAX L
++ {0x31,0x00}, // POST Th AGCMIN H
++ {0x32,0xa0}, // POST Th AGCMIN L
++ {0x33,0x01}, // POST Th AGCMAX H
++ {0x34,0x10}, // POST Th AGCMAX L
++
++ //==========================================================
++ // 1D-Y/C-SIGMA-LPF
++ //==========================================================
++ {0xfc,0x01},
++ {0x05,0xc0},
++
++ {0xfc,0x0b},
++ {0x35,0x00}, // YLPF start AGC
++ {0x36,0x40}, // YLPF01 AGCMIN
++ {0x37,0x60}, // YLPF01 AGCMAX
++ {0x38,0x00}, // YLPF SIG01 Th AGCMINH
++ {0x39,0x18}, // YLPF SIG01 Th AGCMINL
++ {0x3a,0x00}, // YLPF SIG01 Th AGCMAXH
++ {0x3b,0x40}, // YLPF SIG01 Th AGCMAXH
++ {0x3c,0x50}, // YLPF02 AGCMIN
++ {0x3d,0x60}, // YLPF02 AGCMAX
++ {0x3e,0x00}, // YLPF SIG02 Th AGCMINH
++ {0x3f,0x30}, // YLPF SIG02 Th AGCMINL
++ {0x40,0x00}, // YLPF SIG02 Th AGCMAXH
++ {0x41,0x40}, // YLPF SIG02 Th AGCMAXH
++ {0xd4,0x40}, // CLPF AGCMIN
++ {0xd5,0x60}, // CLPF AGCMAX
++ {0xd6,0xb0}, // CLPF SIG01 Th AGCMIN
++ {0xd7,0xf0}, // CLPF SIG01 Th AGCMAX
++ {0xd8,0xb0}, // CLPF SIG02 Th AGCMIN
++ {0xd9,0xf0}, // CLPF SIG02 Th AGCMAX
++
++ //==========================================================
++ // COLOR SUPPRESS
++ //==========================================================
++ {0xfc,0x0b},
++ {0x08,0x58}, // Color suppress AGC MIN
++ {0x09,0x03}, // Color suppress MIN H
++ {0x0a,0x80}, // Color suppress MIN L
++
++ //==========================================================
++ // SHADING
++ //==========================================================
++ {0xfc,0x09},
++ //Shading file for 3BAFX
++ //s90000// shading off
++ // DSP9_SH_WIDTH_H
++ {0x01,0x06},
++ {0x02,0x40},
++ // DSP9_SH_HEIGHT_H
++ {0x03,0x04},
++ {0x04,0xB0},
++ // DSP9_SH_XCH_R
++ {0x05,0x03},
++ {0x06,0x1A},
++ {0x07,0x02},
++ {0x08,0x4E},
++ // DSP9_SH_XCH_G
++ {0x09,0x03},
++ {0x0A,0x27},
++ {0x0B,0x02},
++ {0x0C,0x11},
++ // DSP9_SH_XCH_B
++ {0x0D,0x03},
++ {0x0E,0x15},
++ {0x0F,0x01},
++ {0x10,0xE3},
++ // DSP9_SH_Del_eH_R
++ {0x1D,0x85},
++ {0x1E,0x55},
++ {0x1F,0x77},
++ {0x20,0x9E},
++ {0x23,0x7F},
++ {0x24,0xE6},
++ {0x21,0x7F},
++ {0x22,0xE6},
++ // DSP9_SH_Del_eH_G
++ {0x25,0x82},
++ {0x26,0x9A},
++ {0x27,0x78},
++ {0x28,0xC0},
++ {0x2B,0x76},
++ {0x2C,0x07},
++ {0x29,0x86},
++ {0x2A,0x09},
++ // DSP9_SH_Del_eH_B
++ {0x2D,0x85},
++ {0x2E,0x55},
++ {0x2F,0x75},
++ {0x30,0x6D},
++ {0x33,0x74},
++ {0x34,0xA2},
++ {0x31,0x84},
++ {0x32,0xA2},
++ // DSP9_SH_VAL_R0H
++ {0x35,0x01},
++ {0x36,0x01},
++ {0x37,0x01},
++ {0x38,0x14},
++ {0x39,0x01},
++ {0x3A,0x45},
++ {0x3B,0x01},
++ {0x3C,0x8A},
++ {0x3D,0x01},
++ {0x3E,0xA3},
++ {0x3F,0x01},
++ {0x40,0xB9},
++ {0x41,0x01},
++ {0x42,0xD9},
++ {0x43,0x01},
++ {0x44,0xF6},
++ // DSP9_SH_VAL_G0H
++ {0x45,0x01},
++ {0x46,0x00},
++ {0x47,0x01},
++ {0x48,0x0E},
++ {0x49,0x01},
++ {0x4A,0x34},
++ {0x4B,0x01},
++ {0x4C,0x68},
++ {0x4D,0x01},
++ {0x4E,0x76},
++ {0x4F,0x01},
++ {0x50,0x94},
++ {0x51,0x01},
++ {0x52,0xAB},
++ {0x53,0x01},
++ {0x54,0xC3},
++ // DSP9_SH_VAL_B0H
++ {0x55,0x01},
++ {0x56,0x00},
++ {0x57,0x01},
++ {0x58,0x0C},
++ {0x59,0x01},
++ {0x5A,0x2B},
++ {0x5B,0x01},
++ {0x5C,0x5D},
++ {0x5D,0x01},
++ {0x5E,0x70},
++ {0x5F,0x01},
++ {0x60,0x8A},
++ {0x61,0x01},
++ {0x62,0xA1},
++ {0x63,0x01},
++ {0x64,0xB3},
++ // DSP9_SH_M_R2_R1H
++ {0x65,0x00},
++ {0x66,0x98},
++ {0x67,0x2C},
++ {0x68,0x02},
++ {0x69,0x60},
++ {0x6A,0xB0},
++ {0x6B,0x05},
++ {0x6C,0x59},
++ {0x6D,0x8C},
++ {0x6E,0x07},
++ {0x6F,0x48},
++ {0x70,0x1B},
++ {0x71,0x09},
++ {0x72,0x82},
++ {0x73,0xC0},
++ {0x74,0x0C},
++ {0x75,0x09},
++ {0x76,0x7B},
++ {0x77,0x0E},
++ {0x78,0xDC},
++ {0x79,0x4D},
++ // DSP9_SH_M_R2_G1H
++ {0x7A,0x00},
++ {0x7B,0xAD},
++ {0x7C,0x76},
++ {0x7D,0x02},
++ {0x7E,0xB5},
++ {0x7F,0xD7},
++ {0x80,0x06},
++ {0x81,0x19},
++ {0x82,0x23},
++ {0x83,0x08},
++ {0x84,0x4C},
++ {0x85,0xE2},
++ {0x86,0x0A},
++ {0x87,0xD7},
++ {0x88,0x5C},
++ {0x89,0x0D},
++ {0x8A,0xB8},
++ {0x8B,0x90},
++ {0x8C,0x10},
++ {0x8D,0xF0},
++ {0x8E,0x7F},
++ // DSP9_SH_M_R2_B1H
++ {0x8F,0x00},
++ {0x90,0xC1},
++ {0x91,0xD0},
++ {0x92,0x03},
++ {0x93,0x07},
++ {0x94,0x3F},
++ {0x95,0x06},
++ {0x96,0xD0},
++ {0x97,0x4F},
++ {0x98,0x09},
++ {0x99,0x46},
++ {0x9A,0x32},
++ {0x9B,0x0C},
++ {0x9C,0x1C},
++ {0x9D,0xFE},
++ {0x9E,0x0F},
++ {0x9F,0x54},
++ {0xA0,0xB1},
++ {0xA1,0x12},
++ {0xA2,0xED},
++ {0xA3,0x4C},
++ // DSP9_SH_SUB_RR0H
++ {0xA4,0x6B},
++ {0xA5,0xAA},
++ {0xA6,0x23},
++ {0xA7,0xE3},
++ {0xA8,0x15},
++ {0xA9,0x88},
++ {0xAA,0x21},
++ {0xAB,0x20},
++ {0xAC,0x1C},
++ {0xAD,0xB6},
++ {0xAE,0x19},
++ {0xAF,0x55},
++ {0xB0,0x16},
++ {0xB1,0xAA},
++ // DSP9_SH_SUB_RG0H
++ {0xB2,0x5E},
++ {0xB3,0x74},
++ {0xB4,0x1F},
++ {0xB5,0x7C},
++ {0xB6,0x12},
++ {0xB7,0xE4},
++ {0xB8,0x1D},
++ {0xB9,0x10},
++ {0xBA,0x19},
++ {0xBB,0x30},
++ {0xBC,0x16},
++ {0xBD,0x39},
++ {0xBE,0x13},
++ {0xBF,0xE2},
++ // DSP9_SH_SUB_RB0H
++ {0xC0,0x54},
++ {0xC1,0x89},
++ {0xC2,0x1C},
++ {0xC3,0x2D},
++ {0xC4,0x10},
++ {0xC5,0xE8},
++ {0xC6,0x1A},
++ {0xC7,0x02},
++ {0xC8,0x16},
++ {0xC9,0x8A},
++ {0xCA,0x13},
++ {0xCB,0xE4},
++ {0xCC,0x11},
++ {0xCD,0xCC},
++
++ {0x00,0x02}, // {0xhading on
++
++ //==========================================================
++ // X-SHADING
++ //==========================================================
++ {0xfc,0x1B},
++ {0x80,0x01},
++ {0x81,0x00},
++ {0x82,0x4C},
++ {0x83,0x00},
++ {0x84,0x86},
++ {0x85,0x03},
++ {0x86,0x5E},
++ {0x87,0x00},
++ {0x88,0x07},
++ {0x89,0xA4},
++ {0x90,0x00},
++ {0x91,0x12},
++ {0x92,0x00},
++ {0x93,0x12},
++ {0x94,0x00},
++ {0x95,0x12},
++ {0x96,0x00},
++ {0x97,0x12},
++ {0x98,0x00},
++ {0x99,0x12},
++ {0x9A,0x00},
++ {0x9B,0x12},
++ {0x9C,0x00},
++ {0x9D,0x12},
++ {0x9E,0x00},
++ {0x9F,0x12},
++ {0xA0,0x00},
++ {0xA1,0x12},
++ {0xA2,0x00},
++ {0xA3,0x12},
++ {0xA4,0x00},
++ {0xA5,0x12},
++ {0xA6,0x00},
++ {0xA7,0x12},
++ {0xA8,0x00},
++ {0xA9,0x12},
++ {0xAA,0x00},
++ {0xAB,0x12},
++ {0xAC,0x00},
++ {0xAD,0x12},
++ {0xAE,0x00},
++ {0xAF,0x12},
++ {0xB0,0x00},
++ {0xB1,0x12},
++ {0xB2,0x00},
++ {0xB3,0x12},
++ {0xB4,0x00},
++ {0xB5,0x12},
++ {0xB6,0x00},
++ {0xB7,0x15},
++ {0xB8,0x00},
++ {0xB9,0x12},
++ {0xBA,0x00},
++ {0xBB,0x12},
++ {0xBC,0x00},
++ {0xBD,0x12},
++ {0xBE,0x00},
++ {0xBF,0x12},
++ {0xC0,0x00},
++ {0xC1,0x12},
++ {0xC2,0x00},
++ {0xC3,0x12},
++ {0xC4,0x00},
++ {0xC5,0x12},
++ {0xC6,0x00},
++ {0xC7,0x12},
++ {0xC8,0x00},
++ {0xC9,0x12},
++ {0xCA,0x00},
++ {0xCB,0x12},
++ {0xCC,0x00},
++ {0xCD,0x12},
++ {0xCE,0x00},
++ {0xCF,0x12},
++ {0xD0,0x00},
++ {0xD1,0x12},
++ {0xD2,0x00},
++ {0xD3,0x12},
++ {0xD4,0x00},
++ {0xD5,0x12},
++ // x-shading temp. correlation factor
++ {0xfc,0x0b},
++ {0xda,0x00}, // t0(3100K)
++ {0xdb,0xac},
++ {0xdc,0x01}, // tc(5100K)
++ {0xdd,0x30}, // default eeh
++
++ {0xfc,0x00},
++ {0x81,0x10}, // xshading tem
++
++ {0xfc,0x1b},
++ {0x80,0x01}, // X-Shading On
++
++ //==========================================================
++ // AE WINDOW WEIGHT
++ //==========================================================
++ {0xfc,0x00},
++ {0x03,0x4b}, // AE Suppress On
++
++ {0xfc,0x06},
++ {0x01,0x35}, // UXGA AE Window
++ {0x03,0xc2},
++ {0x05,0x48},
++ {0x07,0xb8},
++ {0x31,0x2a}, // Subsampling AE Window
++ {0x33,0x61},
++ {0x35,0x28},
++ {0x37,0x5c},
++ {0x39,0x28},
++ {0x3B,0x5A},
++ {0x3D,0x10}, // 1c
++ {0x3F,0x44},
++
++ {0xfc,0x20},
++ {0x60,0x11},
++ {0x61,0x11},
++ {0x62,0x11},
++ {0x63,0x11},
++ {0x64,0x11},
++ {0x65,0x22},
++ {0x66,0x22},
++ {0x67,0x11},
++ {0x68,0x11},
++ {0x69,0x33},
++ {0x6a,0x33},
++ {0x6b,0x11},
++ {0x6c,0x12},
++ {0x6d,0x55},
++ {0x6e,0x55},
++ {0x6f,0x21},
++ {0x70,0x13},
++ {0x71,0x55},
++ {0x72,0x55},
++ {0x73,0x31},
++ {0x74,0x33},
++ {0x75,0x33},
++ {0x76,0x33},
++ {0x77,0x33},
++
++ //==========================================================
++ // SAIT AWB
++ //==========================================================
++ //=================================
++ // White Point
++ //=================================
++ {0xfc,0x22}, // White Point (For Hue Control & MWB)
++ {0x01,0xD0}, // D65
++ {0x03,0x9B},
++ {0x05,0xC0}, // 5000K
++ {0x07,0xB8},
++ {0x09,0xA7}, // CWF
++ {0x0b,0xDC},
++ {0x0d,0x98}, // 3000K
++ {0x0f,0xE0},
++ {0x11,0x85}, // A
++ {0x12,0x00},
++ {0x13,0xF6},
++ {0x15,0x80}, // 2000K
++ {0x16,0x01},
++ {0x17,0x00},
++
++ //=================================
++ // Basic Setting
++ //=================================
++ {0xfc,0x22},
++ {0xA0,0x01},
++ {0xA1,0x3F},
++ {0xA2,0x0E},
++ {0xA3,0x65},
++ {0xA4,0x07},
++ {0xA5,0xF4},
++ {0xA6,0x11},
++ {0xA7,0xC8},
++ {0xA9,0x02},
++ {0xAA,0x43},
++ {0xAB,0x26},
++ {0xAC,0x1F},
++ {0xAD,0x02},
++ {0xAE,0x2C},
++ {0xAF,0x19},
++ {0xB0,0x0F},
++
++ {0x94,0x3C},
++ {0x95,0xCC},
++ {0x96,0x5C},
++ {0x97,0x4D},
++ {0xD0,0xA8},
++ {0xD1,0x29},
++ {0xD2,0x39},
++ {0xD3,0x22},
++ {0xD4,0x30},
++ {0xDB,0x29},
++ {0xDC,0x7E},
++ {0xDD,0x22},
++
++ {0xE7,0x00},
++ {0xE8,0xca},
++ {0xE9,0x00},
++ {0xEA,0x62},
++ {0xEB,0x00},
++ {0xEC,0x00},
++ {0xEE,0x97},
++
++ //=================================
++ // Pixel Filter Setting
++ //=================================
++ {0xFC,0x07},
++ {0x95,0x8F},
++
++ {0xfc,0x01},
++ {0xD3,0x4B},
++ {0xD4,0x00},
++ {0xD5,0x38},
++ {0xD6,0x00},
++ {0xD7,0x60},
++ {0xD8,0x00},
++ {0xD9,0x4E},
++ {0xDA,0x00},
++ {0xDB,0x27},
++ {0xDC,0x15},
++ {0xDD,0x23},
++ {0xDE,0xAD},
++ {0xDF,0x24},
++ {0xE0,0x01},
++ {0xE1,0x17},
++ {0xE2,0x4A},
++ {0xE3,0x36},
++ {0xE4,0x40},
++ {0xE5,0x40},
++ {0xE6,0x40},
++ {0xE7,0x40},
++ {0xE8,0x30},
++ {0xE9,0x3D},
++ {0xEA,0x17},
++ {0xEB,0x01},
++
++ //=================================
++ // Polygon AWB Region Tune
++ //=================================
++ {0xfc,0x22},
++ {0x18,0x00}, // 1
++ {0x19,0x5a},
++ {0x1a,0xf8},
++ {0x1b,0x00}, // 2
++ {0x1c,0x59},
++ {0x1d,0xCC},
++ {0x1e,0x00}, // 3
++ {0x1f,0x74},
++ {0x20,0xB3},
++ {0x21,0x00}, // 4
++ {0x22,0x86},
++ {0x23,0xA2},
++ {0x24,0x00}, // 5
++ {0x25,0x94},
++ {0x26,0x89},
++ {0x27,0x00}, // 6
++ {0x28,0xA6},
++ {0x29,0x76},
++ {0x2A,0x00}, // 7
++ {0x2B,0xd0},
++ {0x2C,0x5e},
++ {0x2D,0x00}, // 8
++ {0x2E,0xfa},
++ {0x2F,0x47},
++ {0x30,0x00}, // 9
++ {0x31,0xfD},
++ {0x32,0x5D},
++ {0x33,0x00}, // 10
++ {0x34,0xBB},
++ {0x35,0x7c},
++ {0x36,0x00}, // 11
++ {0x37,0xAD},
++ {0x38,0x88},
++ {0x39,0x00}, // 12
++ {0x3A,0x9A},
++ {0x3B,0xA3},
++ {0x3C,0x00}, // 13
++ {0x3D,0x7C},
++ {0x3E,0xDD},
++ {0x3F,0x00}, // 14
++ {0x40,0x00},
++ {0x41,0x00},
++
++ //=================================
++ // Moving Equation Weight
++ //=================================
++ {0xfc,0x22},
++ {0x98,0x07},
++
++ //=================================
++ // EIT Threshold
++ //=================================
++ {0xfc,0x22},
++ {0xb1,0x00}, // {0xunny
++ {0xb2,0x03},
++ {0xb3,0x00},
++ {0xb4,0xc1},
++
++ {0xb5,0x00}, // Cloudy
++ {0xb6,0x05},
++ {0xb7,0xc9},
++ {0xb9,0x81},
++
++ {0xd7,0x00}, // Shade
++ {0xd8,0x35},
++ {0xd9,0x20},
++ {0xda,0x81},
++
++ //=================================
++ // Gain Offset
++ //=================================
++ {0xfc,0x00},
++ {0x79,0xF9},
++ {0x7A,0x02}, // Global AWB gain off{0xet
++
++ {0xfc,0x22},
++ {0x58,0xf6}, // D65 R Off{0xet
++ {0x59,0xff}, // D65 B Off{0xet
++ {0x5A,0xfa}, // 5000K R Off{0xet
++ {0x5B,0xFe}, // 5000K B Off{0xet
++ {0x5C,0xfb}, // CWF R Off{0xet
++ {0x5D,0xFe}, // CWF B Off{0xet
++ {0x5E,0xfb}, // 3000K R Off{0xet
++ {0x5F,0xFb}, // 3000K B Off{0xet
++ {0x60,0xfb}, // A R Off0xet
++ {0x61,0xfb}, // A B Off0xet
++ {0x62,0xfb}, // 2000K R Off0xet
++ {0x63,0xfb}, // 2000K B Off0xet
++
++ {0xde,0x00}, // LARGE OBJECT BUG FIX
++ {0xf0,0x6a}, // RB Ratio
++ //=================================
++ // Green Stablity Enhance
++ //=================================
++ {0xfc,0x22},
++ {0xb9,0x00},
++ {0xba,0x00},
++ {0xbb,0x00},
++ {0xbc,0x00},
++ {0xe5,0x01},
++ {0xe6,0xff},
++
++ {0xbd,0x90},
++
++ //==========================================================
++ // Special Effect
++ //==========================================================
++ {0xfc,0x07}, // Special Effect
++ {0x30,0xc0},
++ {0x31,0x20},
++ {0x32,0x40},
++ {0x33,0xc0},
++ {0x34,0x00},
++ {0x35,0xb0},
++
++ {0xfc,0x00},
++ {0x73,0x21}, // Frmae AE Enable}, peter0223 À§Ä¡ º¯°æ
++
++ {0xfc,0x04},
++ {0xc0,0x06},
++ {0xc1,0x70},
++ {0xFF,0xFF} // REGISTER END
++};
++#else
++s5k4xa_t s5k4ba_reg[] =
++{
++//==========================================================
++// CAMERA INITIAL (Analog & Clock Setting)
++//==========================================================
++ {0xfc, 0x07},
++ {0x66, 0x01},// WDT
++ {0xfc, 0x00},
++ {0x00, 0xaa},// For EDS Check
++ {0x21, 0x03},// peter0223 added
++
++ {0xfc, 0x01},
++ {0x04, 0x01},// ARM Clock Divider
++
++ {0xfc, 0x02},// Analog setting
++ {0x55, 0x1e},// LineADLC on(s551a), off(s550a)
++ {0x56, 0x10},// BPR 16code
++ {0x30, 0x82},// Analog offset (capture =?h)
++ {0x37, 0x25},// Global Gain (default:31)
++
++ {0x57, 0x80},// // LineADLC Roffset
++ {0x58, 0x80},//89 //90 // LineADLC Goffset
++ {0x59, 0x80},//90 // LineADLC offset don't care
++
++ {0x44, 0x64},//clamp en[6]=1 on
++ {0x4a, 0x30},//clamp level 0011h [7]~[4]
++
++ {0x2d, 0x48},// double shutter (default:00)
++ {0x4d, 0x08},// Voltage doubler (default:04)
++ {0x4e, 0x00},// IO current 8mA set
++ {0x4f, 0x8a},// IO current 48mA set
++
++ {0x66, 0x41},// 1st comp current 2uA
++ {0x43, 0xef},// ec_comp
++ {0x62, 0x60},// LD control , CFPN_EN off
++
++//==========================================================
++// Table Set for Sub-Sampling
++//==========================================================
++ {0xfc, 0x03},
++ {0x01, 0x60},
++ //{0x2e, 0x00},
++ {0x2e, 0x03},//DHL
++ {0x05, 0x46},// Output Image Size Set for Capture
++ {0x07, 0xb6},
++ {0x0e, 0x04},
++ {0x12, 0x03},
++
++ {0xfc, 0x04},
++ {0xc5, 0x26},// Output Image Size Set for Preview
++ {0xc7, 0x5e},
++ {0xce, 0x04},
++ {0xd2, 0x04},
++ //{0xee, 0x00},//DHL
++ {0xee, 0x01},
++ {0xc0, 0x06},
++ {0xc1, 0x60},//frame_H
++ {0xc2, 0x02},
++ {0xc3, 0x8d},//frame_V
++
++ {0xfc, 0x07},
++ {0x05, 0x00},
++ {0x06, 0x00},
++ {0x07, 0x8b},
++ {0x08, 0xf5},
++ {0x09, 0x00},
++ {0x0a, 0xb4},
++ {0x0b, 0x00},
++ {0x0c, 0xea},
++ {0x0d, 0x00},
++ {0x0e, 0x40},
++
++#if 1
++//==========================================================
++// COMMAND SET
++//==========================================================
++ {0xfc, 0x00},
++ {0x70, 0x02},
++
++ {0xfc, 0x00},
++ {0x73, 0x11},//21 Frmae AE Enable, peter0223
++ {0x20, 0x02},// Change AWB Mode
++
++ {0xfc, 0x00},
++ {0x78, 0x6a},// AGC Max
++
++ {0xfc, 0x00},
++ {0x6c, 0xa0},// AE target
++ {0x6d, 0x00},
++
++ {0xfc, 0x20},
++ {0x16, 0x5a},// AGC frame AE start _for Prevating AE Hunting
++ {0x57, 0x18},// Stable_Frame_AE
++
++ {0xfc, 0x00},
++ {0x83, 0x06},//low condition shutter off // Double shutter off
++
++ {0xfc, 0x0b},
++ {0x5c, 0x69},//70 //AGC value to start shutter on/off suppress
++ {0x5d, 0x65},//60 //AGC value to start double shutter on/off suppress
++
++ {0xfc, 0x20},
++ {0x25, 0x00},// CINTR Min
++ {0x2a, 0x01},// forbidden
++ {0x2b, 0x02},// For Forbidden Area
++ {0x2c, 0x0a},
++ {0x2d, 0x00},// For Forbidden Area
++ {0x2e, 0x00},
++ {0x2f, 0x05},// forbidden
++ {0x14, 0x78},//70
++ {0x01, 0x00},// Stepless_Off
++
++ {0xfc, 0x00},
++ {0x29, 0x04},// Y level
++ {0x2a, 0x00},
++ {0x2b, 0x03},// C level
++ {0x2c, 0x80},//60
++
++ {0xfc, 0x07},
++ {0x37, 0x00},// Flicker
++
++ {0xfc, 0x00},
++ {0x72, 0xa0},// Flicker for 32MHz
++ {0x74, 0x08},// flicker 60Hz fix
++ {0xfc, 0x20},
++ {0x02, 0x12},//02 Flicker Dgain Mode
++ {0xfc, 0x00},
++ {0x62, 0x02},// Hue Control Enable
++
++ {0xfc, 0x01},
++ //{0x0c, 0x02},// Full YC Enable
++ {0x0C, 0x03},//Donghoon
++
++
++//==========================================================
++// COLOR MATRIX
++//==========================================================
++ {0xfc, 0x01}, //DL gain 60
++ {0x51, 0x08}, //06 //08 07
++ {0x52, 0xe8}, //df //9B E7
++ {0x53, 0xfc}, //fd //FC FB
++ {0x54, 0x33}, //09 //07 B9
++ {0x55, 0xfe}, //00 //FF 00
++ {0x56, 0xe6}, //17 //5E 5F
++ {0x57, 0xfe}, //fe //FD FD
++ {0x58, 0x3d}, //4f //0E 46
++ {0x59, 0x08}, //06 //07 05
++ {0x5a, 0x21}, //9b //EE E6
++ {0x5b, 0xfd}, //ff //FF 00
++ {0x5c, 0xa3}, //17 //05 D3
++ {0x5d, 0xff}, //ff //FF FF
++ {0x5e, 0xbc}, //81 //7A 53
++ {0x5f, 0xfc}, //fd //FC FB
++ {0x60, 0x96}, //5b //23 B1
++ {0x61, 0x07}, //07 //08 08
++ {0x62, 0xaf}, //24 //64 FD
++
++//==========================================================
++// EDGE ENHANCEMENT
++//==========================================================
++ {0xfc, 0x05},
++ {0x12, 0x3d},
++ {0x13, 0x3b},
++ {0x14, 0x38},
++ {0x15, 0x3b},
++ {0x16, 0x3d},
++
++ {0x17, 0x3b},
++ {0x18, 0x05},
++ {0x19, 0x09},
++ {0x1a, 0x05},
++ {0x1b, 0x3b},
++
++ {0x1c, 0x38},
++ {0x1d, 0x09},
++ {0x1e, 0x1c},
++ {0x1f, 0x09},
++ {0x20, 0x38},
++
++ {0x21, 0x3b},
++ {0x22, 0x05},
++ {0x23, 0x09},
++ {0x24, 0x05},
++ {0x25, 0x3b},
++
++ {0x26, 0x3d},
++ {0x27, 0x3b},
++ {0x28, 0x38},
++ {0x29, 0x3b},
++ {0x2a, 0x3d},
++
++ {0xfc, 0x00},
++ {0x89, 0x00},// Edge Suppress On
++ {0xfc, 0x0b},
++ {0x42, 0x50},// Edge AGC MIN
++ {0x43, 0x60},// Edge AGC MAX
++ {0x45, 0x18},// positive gain AGC MIN
++ {0x49, 0x06},// positive gain AGC MAX
++ {0x4d, 0x18},// negative gain AGC MIN
++ {0x51, 0x06},// negative gain AGC MAX
++
++ {0xfc, 0x05},
++ {0x34, 0x28},// APTCLP
++ {0x35, 0x03},// APTSC
++ {0x36, 0x0b},// ENHANCE
++ {0x3f, 0x00},// NON-LIN
++ {0x42, 0x10},// EGFALL
++ {0x43, 0x00},// HLFALL
++ {0x45, 0xa0},// EGREF
++ {0x46, 0x7a},// HLREF
++ {0x47, 0x40},// LLREF
++ {0x48, 0x0c},
++ {0x49, 0x31},// CSSEL EGSEL CS_DLY
++
++ {0x40, 0x41},// Y delay
++
++ // New Wide Luma Edge
++ {0xfc, 0x1d},
++ {0x86, 0x00},
++ {0x87, 0x60},
++ {0x88, 0x01},
++ {0x89, 0x20},
++ {0x8a, 0x00},
++ {0x8b, 0x00},
++ {0x8c, 0x00},
++ {0x8d, 0x00},
++ {0x8e, 0x00},
++ {0x8f, 0x20},
++ {0x90, 0x00},
++ {0x91, 0x00},
++ {0x92, 0x00},
++ {0x93, 0x0a},
++ {0x94, 0x00},
++ {0x95, 0x00},
++ {0x96, 0x00},
++ {0x97, 0x20},
++ {0x98, 0x00},
++ {0x99, 0x00},
++ {0x9a, 0xff},
++ {0x9b, 0xea},
++ {0x9c, 0xaa},
++ {0x9d, 0xab},
++ {0x9e, 0xff},
++ {0x9f, 0xf1},
++ {0xa0, 0x55},
++ {0xa1, 0x56},
++ {0xa2, 0x07},
++
++ {0x85, 0x01},
++
++//==========================================================
++// GAMMA
++//==========================================================
++ {0xfc, 0x1d},
++ {0x00, 0x0b},
++ {0x01, 0x18},
++ {0x02, 0x3d},
++ {0x03, 0x9c},
++ {0x04, 0x00},
++ {0x05, 0x0c},
++ {0x06, 0x76},
++ {0x07, 0xc2},
++ {0x08, 0x00},
++ {0x09, 0x56},
++ {0x0a, 0x34},
++ {0x0b, 0x60},
++ {0x0c, 0x85},
++ {0x0d, 0xa7},
++ {0x0e, 0xaa},
++ {0x0f, 0xc6},
++ {0x10, 0xe2},
++ {0x11, 0xfc},
++ {0x12, 0x13},
++ {0x13, 0xab},
++ {0x14, 0x29},
++ {0x15, 0x3c},
++ {0x16, 0x4b},
++ {0x17, 0x5a},
++ {0x18, 0xff},
++ {0x19, 0x69},
++ {0x1a, 0x78},
++ {0x1b, 0x84},
++ {0x1c, 0x91},
++ {0x1d, 0xff},
++ {0x1e, 0x9c},
++ {0x1f, 0xa7},
++ {0x20, 0xb2},
++ {0x21, 0xbd},
++ {0x22, 0xff},
++ {0x23, 0xc7},
++ {0x24, 0xd2},
++ {0x25, 0xdb},
++ {0x26, 0xe4},
++ {0x27, 0xff},
++ {0x28, 0xec},
++ {0x29, 0xf5},
++ {0x2a, 0xf0},
++ {0x2b, 0x0b},
++ {0x2c, 0x18},
++ {0x2d, 0x3d},
++ {0x2e, 0x9c},
++ {0x2f, 0x00},
++ {0x30, 0x0c},
++ {0x31, 0x76},
++ {0x32, 0xc2},
++ {0x33, 0x00},
++ {0x34, 0x56},
++ {0x35, 0x34},
++ {0x36, 0x60},
++ {0x37, 0x85},
++ {0x38, 0xa7},
++ {0x39, 0xaa},
++ {0x3a, 0xc6},
++ {0x3b, 0xe2},
++ {0x3c, 0xfc},
++ {0x3d, 0x13},
++ {0x3e, 0xab},
++ {0x3f, 0x29},
++ {0x40, 0x3c},
++ {0x41, 0x4b},
++ {0x42, 0x5a},
++ {0x43, 0xff},
++ {0x44, 0x69},
++ {0x45, 0x78},
++ {0x46, 0x84},
++ {0x47, 0x91},
++ {0x48, 0xff},
++ {0x49, 0x9c},
++ {0x4a, 0xa7},
++ {0x4b, 0xb2},
++ {0x4c, 0xbd},
++ {0x4d, 0xff},
++ {0x4e, 0xc7},
++ {0x4f, 0xd2},
++ {0x50, 0xdb},
++ {0x51, 0xe4},
++ {0x52, 0xff},
++ {0x53, 0xec},
++ {0x54, 0xf5},
++ {0x55, 0xf0},
++ {0x56, 0x0b},
++ {0x57, 0x18},
++ {0x58, 0x3d},
++ {0x59, 0x9c},
++ {0x5a, 0x00},
++ {0x5b, 0x0c},
++ {0x5c, 0x76},
++ {0x5d, 0xc2},
++ {0x5e, 0x00},
++ {0x5f, 0x56},
++ {0x60, 0x34},
++ {0x61, 0x60},
++ {0x62, 0x85},
++ {0x63, 0xa7},
++ {0x64, 0xaa},
++ {0x65, 0xc6},
++ {0x66, 0xe2},
++ {0x67, 0xfc},
++ {0x68, 0x13},
++ {0x69, 0xab},
++ {0x6a, 0x29},
++ {0x6b, 0x3c},
++ {0x6c, 0x4b},
++ {0x6d, 0x5a},
++ {0x6e, 0xff},
++ {0x6f, 0x69},
++ {0x70, 0x78},
++ {0x71, 0x84},
++ {0x72, 0x91},
++ {0x73, 0xff},
++ {0x74, 0x9c},
++ {0x75, 0xa7},
++ {0x76, 0xb2},
++ {0x77, 0xbd},
++ {0x78, 0xff},
++ {0x79, 0xc7},
++ {0x7a, 0xd2},
++ {0x7b, 0xdb},
++ {0x7c, 0xe4},
++ {0x7d, 0xff},
++ {0x7e, 0xec},
++ {0x7f, 0xf5},
++ {0x80, 0xf0},
++
++//==========================================================
++// HUE CONTROL
++//==========================================================
++ {0xfc, 0x00},
++ {0x48, 0x40},// 2000K
++ {0x49, 0x30},
++ {0x4a, 0x00},
++ {0x4b, 0x00},
++ {0x4c, 0x30},
++ {0x4d, 0x38},
++ {0x4e, 0x00},
++ {0x4f, 0x00},
++
++ {0x50, 0x40},// 3000K
++ {0x51, 0x30},
++ {0x52, 0x00},
++ {0x53, 0x00},
++ {0x54, 0x30},
++ {0x55, 0x38},
++ {0x56, 0x00},
++ {0x57, 0x00},
++
++ {0x58, 0x3c},//40 // 5100K
++ {0x59, 0x30},//4a //40
++ {0x5a, 0x00},//0c //00
++ {0x5b, 0x00},//00
++ {0x5c, 0x30},//4a
++ {0x5d, 0x38},//40
++ {0x5e, 0x00},//f6 //15
++ {0x5f, 0xfc},//00
++
++//==========================================================
++// SUPPRESS FUNCTION
++//==========================================================
++ {0xfc, 0x00},
++ {0x7e, 0xf4},
++
++//==========================================================
++// BPR
++//==========================================================
++ {0xfc, 0x0b},
++ {0x3d, 0x10},
++
++ {0xfc, 0x0b},
++ {0x0b, 0x00},
++ {0x0c, 0x40},
++ {0x0d, 0x5a},
++ {0x0e, 0x00},
++ {0x0f, 0x20},
++ {0x10, 0x00},
++ {0x11, 0x10},
++ {0x12, 0x00},
++ {0x13, 0x7f},
++ {0x14, 0x03},
++ {0x15, 0xff},
++ {0x16, 0x48},
++ {0x17, 0x60},
++ {0x18, 0x00},
++ {0x19, 0x00},
++ {0x1a, 0x00},
++ {0x1b, 0x20},
++ {0x1c, 0x00},
++ {0x1d, 0x00},
++ {0x1e, 0x00},
++ {0x1f, 0x20},
++
++//==========================================================
++// GR/GB CORRECTION
++//==========================================================
++ {0xfc, 0x01},
++ {0x45, 0x0c},
++ {0xfc, 0x0b},
++ {0x21, 0x00},
++ {0x22, 0x40},
++ {0x23, 0x60},
++ {0x24, 0x0d},
++ {0x25, 0x20},
++ {0x26, 0x0d},
++ {0x27, 0x20},
++
++//==========================================================
++// NR
++//==========================================================
++ {0xfc, 0x01},
++ {0x4c, 0x01},
++ {0x49, 0x15},
++ {0x4b, 0x0a},
++
++ {0xfc, 0x0b},
++ {0x28, 0x00},
++ {0x29, 0x00},
++ {0x2a, 0x14},
++ {0x2b, 0x00},
++ {0x2c, 0x14},
++ {0x2d, 0x00},
++ {0x2e, 0xD0},
++ {0x2f, 0x02},
++ {0x30, 0x00},
++ {0x31, 0x00},
++ {0x32, 0xa0},
++ {0x33, 0x00},
++ {0x34, 0xe0},
++
++//==========================================================
++// 1D-Y/C-SIGMA-LPF
++//==========================================================
++ {0xfc, 0x01},
++ {0x05, 0xC0},
++
++ {0xfc, 0x0b},
++ {0x35, 0x00},
++ {0x36, 0x40},
++ {0x37, 0x60},
++ {0x38, 0x00},
++ {0x39, 0x18},
++ {0x3a, 0x00},
++ {0x3b, 0x40},
++ {0x3c, 0x50},
++ {0x3d, 0x60},
++ {0x3e, 0x00},
++ {0x3f, 0x30},
++ {0x40, 0x00},
++ {0x41, 0x40},
++ {0xd4, 0x40},
++ {0xd5, 0x60},
++ {0xd6, 0xb0},
++ {0xd7, 0xf0},
++ {0xd8, 0xb0},
++ {0xd9, 0xf0},
++
++//==========================================================
++// COLOR SUPPRESS
++//==========================================================
++ {0xfc, 0x0b},
++ {0x08, 0x58},
++ {0x09, 0x03},
++ {0x0a, 0x00},
++
++//==========================================================
++// SHADING
++//==========================================================
++ {0xfc, 0x09},
++
++ {0x01, 0x06},
++ {0x02, 0x40},
++
++ {0x03, 0x04},
++ {0x04, 0xB0},
++
++ {0x05, 0x03},
++ {0x06, 0x20},
++ {0x07, 0x02},
++ {0x08, 0x91},
++
++ {0x09, 0x03},
++ {0x0A, 0x25},
++ {0x0B, 0x02},
++ {0x0C, 0x64},
++
++ {0x0D, 0x03},
++ {0x0E, 0x0F},
++ {0x0F, 0x02},
++ {0x10, 0x4E},
++
++ {0x1D, 0x80},
++ {0x1E, 0x00},
++ {0x1F, 0x80},
++ {0x20, 0x00},
++ {0x23, 0x85},
++ {0x24, 0x52},
++ {0x21, 0x79},
++ {0x22, 0xE6},
++
++ {0x25, 0x80},
++ {0x26, 0x00},
++ {0x27, 0x80},
++ {0x28, 0x00},
++ {0x2B, 0x81},
++ {0x2C, 0x48},
++ {0x29, 0x81},
++ {0x2A, 0x48},
++
++ {0x2D, 0x80},
++ {0x2E, 0x00},
++ {0x2F, 0x80},
++ {0x30, 0x00},
++ {0x33, 0x7C},
++ {0x34, 0x45},
++ {0x31, 0x7D},
++ {0x32, 0x7D},
++
++ {0x35, 0x01},
++ {0x36, 0x00},
++ {0x37, 0x01},
++ {0x38, 0x11},
++ {0x39, 0x01},
++ {0x3A, 0x4E},
++ {0x3B, 0x01},
++ {0x3C, 0xAB},
++ {0x3D, 0x01},
++ {0x3E, 0xDC},
++ {0x3F, 0x02},
++ {0x40, 0x1A},
++ {0x41, 0x02},
++ {0x42, 0x6A},
++ {0x43, 0x02},
++ {0x44, 0xD3},
++
++ {0x45, 0x01},
++ {0x46, 0x00},
++ {0x47, 0x01},
++ {0x48, 0x0E},
++ {0x49, 0x01},
++ {0x4A, 0x40},
++ {0x4B, 0x01},
++ {0x4C, 0x8A},
++ {0x4D, 0x01},
++ {0x4E, 0xB5},
++ {0x4F, 0x01},
++ {0x50, 0xE8},
++ {0x51, 0x02},
++ {0x52, 0x27},
++ {0x53, 0x02},
++ {0x54, 0x84},
++
++ {0x55, 0x01},
++ {0x56, 0x00},
++ {0x57, 0x01},
++ {0x58, 0x0C},
++ {0x59, 0x01},
++ {0x5A, 0x37},
++ {0x5B, 0x01},
++ {0x5C, 0x74},
++ {0x5D, 0x01},
++ {0x5E, 0x96},
++ {0x5F, 0x01},
++ {0x60, 0xC9},
++ {0x61, 0x02},
++ {0x62, 0x04},
++ {0x63, 0x02},
++ {0x64, 0x4B},
++
++ {0x65, 0x00},
++ {0x66, 0x9A},
++ {0x67, 0x2D},
++ {0x68, 0x02},
++ {0x69, 0x68},
++ {0x6A, 0xB6},
++ {0x6B, 0x05},
++ {0x6C, 0x6B},
++ {0x6D, 0x99},
++ {0x6E, 0x07},
++ {0x6F, 0x60},
++ {0x70, 0xAD},
++ {0x71, 0x09},
++ {0x72, 0xA2},
++ {0x73, 0xD7},
++ {0x74, 0x0C},
++ {0x75, 0x32},
++ {0x76, 0x19},
++ {0x77, 0x0F},
++ {0x78, 0x0E},
++ {0x79, 0x70},
++
++ {0x7A, 0x00},
++ {0x7B, 0x9C},
++ {0x7C, 0x9F},
++ {0x7D, 0x02},
++ {0x7E, 0x72},
++ {0x7F, 0x7A},
++ {0x80, 0x05},
++ {0x81, 0x81},
++ {0x82, 0x94},
++ {0x83, 0x07},
++ {0x84, 0x7E},
++ {0x85, 0x97},
++ {0x86, 0x09},
++ {0x87, 0xC9},
++ {0x88, 0xEA},
++ {0x89, 0x0C},
++ {0x8A, 0x63},
++ {0x8B, 0x8C},
++ {0x8C, 0x0F},
++ {0x8D, 0x4B},
++ {0x8E, 0x7E},
++
++ {0x8F, 0x00},
++ {0x90, 0x9E},
++ {0x91, 0xBD},
++ {0x92, 0x02},
++ {0x93, 0x7A},
++ {0x94, 0xF5},
++ {0x95, 0x05},
++ {0x96, 0x94},
++ {0x97, 0xA8},
++ {0x98, 0x07},
++ {0x99, 0x98},
++ {0x9A, 0x8F},
++ {0x9B, 0x09},
++ {0x9C, 0xEB},
++ {0x9D, 0xD5},
++ {0x9E, 0x0C},
++ {0x9F, 0x8E},
++ {0xA0, 0x7A},
++ {0xA1, 0x0F},
++ {0xA2, 0x80},
++ {0xA3, 0x7D},
++
++ {0xA4, 0x6A},
++ {0xA5, 0x44},
++ {0xA6, 0x23},
++ {0xA7, 0x6C},
++ {0xA8, 0x15},
++ {0xA9, 0x40},
++ {0xAA, 0x20},
++ {0xAB, 0xB2},
++ {0xAC, 0x1C},
++ {0xAD, 0x56},
++ {0xAE, 0x19},
++ {0xAF, 0x01},
++ {0xB0, 0x16},
++ {0xB1, 0x5F},
++
++ {0xB2, 0x68},
++ {0xB3, 0x9C},
++ {0xB4, 0x22},
++ {0xB5, 0xDE},
++ {0xB6, 0x14},
++ {0xB7, 0xEC},
++ {0xB8, 0x20},
++ {0xB9, 0x30},
++ {0xBA, 0x1B},
++ {0xBB, 0xE5},
++ {0xBC, 0x18},
++ {0xBD, 0x9D},
++ {0xBE, 0x16},
++ {0xBF, 0x05},
++
++ {0xC0, 0x67},
++ {0xC1, 0x36},
++ {0xC2, 0x22},
++ {0xC3, 0x67},
++ {0xC4, 0x14},
++ {0xC5, 0xA4},
++ {0xC6, 0x1F},
++ {0xC7, 0xC2},
++ {0xC8, 0x1B},
++ {0xC9, 0x86},
++ {0xCA, 0x18},
++ {0xCB, 0x49},
++ {0xCC, 0x15},
++ {0xCD, 0xBA},
++
++ {0x00, 0x02},// shading on
++
++//==========================================================
++// X-SHADING
++//==========================================================
++ {0xfc, 0x1B},
++ {0x80, 0x01},
++ {0x81, 0x00},
++ {0x82, 0x4C},
++ {0x83, 0x00},
++ {0x84, 0x86},
++ {0x85, 0x03},
++ {0x86, 0x5E},
++ {0x87, 0x00},
++ {0x88, 0x07},
++ {0x89, 0xA4},
++ {0x90, 0x00},
++ {0x91, 0x88},
++ {0x92, 0x00},
++ {0x93, 0xC1},
++ {0x94, 0x00},
++ {0x95, 0xF7},
++ {0x96, 0x01},
++ {0x97, 0x21},
++ {0x98, 0x01},
++ {0x99, 0x37},
++ {0x9A, 0x01},
++ {0x9B, 0x0C},
++ {0x9C, 0x00},
++ {0x9D, 0xCE},
++ {0x9E, 0x00},
++ {0x9F, 0x3B},
++ {0xA0, 0x00},
++ {0xA1, 0x5B},
++ {0xA2, 0x00},
++ {0xA3, 0x7A},
++ {0xA4, 0x00},
++ {0xA5, 0x92},
++ {0xA6, 0x00},
++ {0xA7, 0x91},
++ {0xA8, 0x00},
++ {0xA9, 0x81},
++ {0xAA, 0x00},
++ {0xAB, 0x60},
++ {0xAC, 0x07},
++ {0xAD, 0xCB},
++ {0xAE, 0x07},
++ {0xAF, 0xC5},
++ {0xB0, 0x07},
++ {0xB1, 0xBB},
++ {0xB2, 0x07},
++ {0xB3, 0xAA},
++ {0xB4, 0x07},
++ {0xB5, 0xA9},
++ {0xB6, 0x07},
++ {0xB7, 0xB2},
++ {0xB8, 0x07},
++ {0xB9, 0xBF},
++ {0xBA, 0x07},
++ {0xBB, 0x5E},
++ {0xBC, 0x07},
++ {0xBD, 0x3C},
++ {0xBE, 0x06},
++ {0xBF, 0xF9},
++ {0xC0, 0x06},
++ {0xC1, 0xBD},
++ {0xC2, 0x06},
++ {0xC3, 0xB8},
++ {0xC4, 0x06},
++ {0xC5, 0xE2},
++ {0xC6, 0x07},
++ {0xC7, 0x1A},
++ {0xC8, 0x07},
++ {0xC9, 0x15},
++ {0xCA, 0x06},
++ {0xCB, 0xDE},
++ {0xCC, 0x06},
++ {0xCD, 0x9C},
++ {0xCE, 0x06},
++ {0xCF, 0x6F},
++ {0xD0, 0x06},
++ {0xD1, 0x5E},
++ {0xD2, 0x06},
++ {0xD3, 0x84},
++ {0xD4, 0x06},
++ {0xD5, 0xCA},
++
++ {0xfc, 0x0b},
++ {0xda, 0x00},
++ {0xdb, 0x9c},
++ {0xdc, 0x00},
++ {0xdd, 0xd1},
++
++ {0xfc, 0x1b},
++ {0x80, 0x01},
++
++//==========================================================
++// AE WINDOW WEIGHT
++//==========================================================
++ {0xfc, 0x00},
++ {0x03, 0x4b},
++ {0xfc, 0x06},
++ {0x01, 0x35},
++ {0x03, 0xc2},
++ {0x05, 0x48},
++ {0x07, 0xb8},
++ {0x31, 0x2a},
++ {0x33, 0x61},
++ {0x35, 0x28},
++ {0x37, 0x5c},
++
++ {0xfc, 0x20},
++ {0x60, 0x11},
++ {0x61, 0x11},
++ {0x62, 0x11},
++ {0x63, 0x11},
++ {0x64, 0x11},
++ {0x65, 0x22},
++ {0x66, 0x22},
++ {0x67, 0x11},
++ {0x68, 0x11},
++ {0x69, 0x33},
++ {0x6a, 0x33},
++ {0x6b, 0x11},
++ {0x6c, 0x12},
++ {0x6d, 0x55},
++ {0x6e, 0x55},
++ {0x6f, 0x21},
++ {0x70, 0x13},
++ {0x71, 0x55},
++ {0x72, 0x55},
++ {0x73, 0x31},
++ {0x74, 0x33},
++ {0x75, 0x33},
++ {0x76, 0x33},
++ {0x77, 0x33},
++
++//==========================================================
++// SAIT AWB
++//==========================================================
++ {0xfc, 0x00},
++ {0x7b, 0x00},
++
++ {0xfc, 0x07},
++ {0x3c, 0x10},
++ {0x3d, 0x10},
++ {0x3e, 0x10},
++ {0x3f, 0x10},
++
++ {0xfc, 0x01},
++ {0xc8, 0xe0},
++ {0xfc, 0x00},
++ {0x3e, 0x10},
++
++ {0xfc, 0x00},
++ {0x3e, 0x10},
++ {0x3d, 0x04},
++ {0x32, 0x02},
++ {0x81, 0x10},
++ {0xbc, 0xf0},
++ {0xfc, 0x22},
++ {0x8c, 0x04},
++ {0x8d, 0x06},
++
++ {0xfc, 0x07},
++ {0x97, 0x00},
++
++//=================================
++// White Point
++//=================================
++ {0xfc, 0x22},
++ {0x01, 0xD8},
++ {0x03, 0xA1},
++ {0x05, 0xCA},
++ {0x07, 0xC8},
++ {0x09, 0xB3},
++ {0x0b, 0xE2},
++ {0x0d, 0xA0},
++ {0x0f, 0xF0},
++ {0x11, 0x94},
++ {0x12, 0x00},
++ {0x13, 0xFD},
++ {0x15, 0x88},
++ {0x16, 0x01},
++ {0x17, 0x10},
++
++//=================================
++// Basic Setting
++//=================================
++ {0xfc, 0x22},
++ {0xA8, 0xFF},
++
++ {0xA0, 0x01},
++ {0xA1, 0x38},
++ {0xA2, 0x0E},
++ {0xA3, 0x6D},
++ {0xA4, 0x07},
++ {0xA5, 0xF5},
++ {0xA6, 0x11},
++ {0xA7, 0xBE},
++ {0xA9, 0x02},
++ {0xAA, 0xD2},
++ {0xAB, 0x00},
++ {0xAC, 0x00},
++ {0xAD, 0x02},
++ {0xAE, 0x3F},
++ {0xAF, 0x19},
++ {0xB0, 0x91},
++ {0x94, 0x3D},
++ {0x95, 0x00},
++ {0x96, 0x58},
++ {0x97, 0x80},
++ {0xD0, 0xA2},
++ {0xD1, 0x2E},
++ {0xD2, 0x4D},
++ {0xD3, 0x28},
++ {0xD4, 0x90},
++ {0xDB, 0x2E},
++ {0xDC, 0x7A},
++ {0xDD, 0x28},
++ {0xE7, 0x00},
++ {0xE8, 0xc7},
++ {0xE9, 0x00},
++ {0xEA, 0x62},
++ {0xEB, 0xD2},
++ {0xEC, 0xD9},
++ {0xEE, 0xA6},
++
++ {0xfc, 0x00},
++ {0x8a, 0x02},
++
++//=================================
++// Pixel Filter Setting
++//=================================
++ {0xFC, 0x07},
++ {0x95, 0xCF},
++
++ {0xfc, 0x01},
++ {0xd3, 0x4f},
++ {0xd4, 0x00},
++ {0xd5, 0x3c},
++ {0xd6, 0x80},
++ {0xd7, 0x61},
++ {0xd8, 0x00},
++ {0xd9, 0x49},
++ {0xda, 0x00},
++ {0xdb, 0x24},
++ {0xdc, 0x4b},
++ {0xdd, 0x23},
++ {0xde, 0xf2},
++ {0xdf, 0x20},
++ {0xe0, 0x73},
++ {0xe1, 0x18},
++ {0xe2, 0x69},
++ {0xe3, 0x31},
++ {0xe4, 0x40},
++ {0xe5, 0x34},
++ {0xe6, 0x40},
++ {0xe7, 0x40},
++ {0xe8, 0x32},
++ {0xe9, 0x40},
++ {0xea, 0x1c},
++ {0xeb, 0x00},
++
++//=================================
++// Polygon AWB Region Tune
++//=================================
++
++ // AWB3 - Polygon Region
++ {0xfc, 0x22},
++ {0x18, 0x00},
++ {0x19, 0x4b},
++ {0x1a, 0xfd},
++ {0x1b, 0x00},
++ {0x1c, 0x41},
++ {0x1d, 0xd9},
++ {0x1e, 0x00},
++ {0x1f, 0x66},
++ {0x20, 0xa9},
++ {0x21, 0x00},
++ {0x22, 0x8b},
++ {0x23, 0x82},
++ {0x24, 0x00},
++ {0x25, 0xa4},
++ {0x26, 0x6c},
++ {0x27, 0x00},
++ {0x28, 0xbd},
++ {0x29, 0x5d},
++ {0x2a, 0x00},
++ {0x2b, 0xdc},
++ {0x2c, 0x4d},
++ {0x2d, 0x00},
++ {0x2e, 0xdc},
++ {0x2f, 0x63},
++ {0x30, 0x00},
++ {0x31, 0xc1},
++ {0x32, 0x72},
++ {0x33, 0x00},
++ {0x34, 0xab},
++ {0x35, 0x84},
++ {0x36, 0x00},
++ {0x37, 0x99},
++ {0x38, 0xa0},
++ {0x39, 0x00},
++ {0x3a, 0x81},
++ {0x3b, 0xe9},
++ {0x3c, 0x00},
++ {0x3d, 0x00},
++ {0x3e, 0x00},
++ {0x3f, 0x00},
++ {0x40, 0x00},
++ {0x41, 0x00},
++
++//=================================
++// Moving Equation Weight
++//=================================
++ {0xfc, 0x22},
++ {0x98, 0x07},
++
++//=================================
++// EIT Threshold
++//=================================
++ {0xfc, 0x22},
++ {0xb1, 0x00},
++ {0xb2, 0x02},
++ {0xb3, 0x00},
++ {0xb4, 0xC1},
++
++ {0xb5, 0x00},
++ {0xb6, 0x02},
++ {0xb7, 0x00},
++ {0xb9, 0xc2},
++
++ {0xd7, 0x00},
++ {0xd8, 0x35},
++ {0xd9, 0x20},
++ {0xda, 0x81},
++
++//=================================
++// Gain Offset
++//=================================
++ {0xfc, 0x00},
++ {0x79, 0xf8},
++ {0x7a, 0x08},
++
++ {0xfc, 0x07},
++ {0x11, 0x01},
++
++ {0xfc, 0x22},
++ {0x58, 0xf8},
++ {0x59, 0x00},
++ {0x5A, 0xfc},
++ {0x5B, 0x00},
++ {0x5C, 0x00},
++ {0x5D, 0x00},
++ {0x5E, 0x00},
++ {0x5F, 0x00},
++ {0x60, 0x00},
++ {0x61, 0xf8},
++ {0x62, 0x00},
++ {0x63, 0xf0},
++
++ {0xde, 0x00},
++ {0xf0, 0x6a},
++
++//=================================
++// Green Stablity Enhance
++//=================================
++ {0xfc, 0x22},
++ {0xb9, 0x00},
++ {0xba, 0x00},
++ {0xbb, 0x00},
++ {0xbc, 0x00},
++ {0xe5, 0x01},
++ {0xe6, 0xff},
++ {0xbd, 0x8c},
++
++//==========================================================
++// Special Effect
++//==========================================================
++ {0xfc, 0x07},
++ {0x30, 0xc0},
++ {0x31, 0x20},
++ {0x32, 0x40},
++ {0x33, 0xc0},
++ {0x34, 0x00},
++ {0x35, 0xb0},
++#endif
++//==========================================================
++// ETC
++//==========================================================
++ {0xfc, 0x01},
++ {0x01, 0x01},
++ {0x00, 0x90},
++ {0xfc, 0x02},
++ {0x03, 0x20},
++
++ {0xfc, 0x20},
++ {0x0f, 0x00},
++
++ {0xfc, 0x00},
++ {0x02, 0x09},
++
++ {0xfc, 0x01},
++ //{0x02, 0x00},
++ {0x02, 0x02},//Donghoon
++};
++#endif
++#else
++#error No samsung CIS moudule !
++#endif
++
++
++// For VGA ( 640 x 480) on 4BA module
++s5k4xa_t s5k4ba_reg_vga[] =
++{
++ // To do.
++};
++
++// For SVGA ( 800 x 600) on 4BA module
++s5k4xa_t s5k4ba_reg_svga[] =
++{
++ {0xfc,0x02},
++ {0x2d,0x48},
++ {0x44,0x63},
++
++ {0xfc,0x03},
++ {0x02,0x04},
++ {0xfc,0x20},
++ {0x14,0x70},
++
++ {0xfc,0x00},
++ {0x03,0x4b}, // AE/AWB On
++ {0x7e,0xf4}, // Suppress On
++ {0x89,0x03}, // Edge Suppress On
++
++ {0xfc,0x02},
++ {0x02,0x0e},//sensor BPRoff
++
++ {0xfc,0x20},
++ {0x16,0x60}, // Frame AE Start
++
++ {0xfc,0x02},
++ {0x30,0x90}, // Analog offset
++ {0x37,0x0d}, // Global Gain
++ {0x60,0x00}, // Blank_Adrs
++ {0x45,0x0e}, // CDS Timing for Average Sub_Sampling
++ {0x47,0x2f},
++
++ {0xfc,0x01},
++ {0x9F,0x05}, //B
++ {0xA0,0x18},
++ {0xA1,0x42},
++ {0xA2,0xd7},
++ {0xA3,0x00},
++
++ {0xA4,0xB6},
++ {0xA5,0x3b},
++ {0xA6,0x88},
++ {0xA7,0xC8},
++ {0xA8,0x6A},
++
++ {0xfc,0x05},
++ {0x34,0x20}, // APTCLP
++ {0x35,0x08}, //9 //APTSC
++
++ {0xfc,0x00}, // flash 0821
++ {0x32,0x04}, // AWB moving average 8 frame
++
++ {0xfc,0x01},
++ {0x01,0x01}, // Pclk inversion
++
++ {0xfc,0x00},
++ {0x02,0x09}, // 800 x 600
++
++
++ {0xFF,0xFF} // REGISTER END
++};
++
++// For SXGA (1280 x 1024 = 1.3M) on 4BA module
++s5k4xa_t s5k4ba_reg_sxga[] =
++{
++ // To do.
++};
++
++
++// For UXGA (1600 x 1200 = 2M) on 4BA module
++s5k4xa_t s5k4ba_reg_uxga[] =
++{
++ // To do.
++};
++
++
++// For SQVGA on 4BA module
++s5k4xa_t s5k4ba_reg_qsvga[] =
++{
++ // Pclk inversion
++ {0xfc,0x01},
++ {0x01,0x01},
++
++ // To setting CbCr selection on Table 14h
++ {0xfc, 0x14},
++ {0x5c, 0x00},
++
++ // To load table_11 H4V4
++ {0xfc, 0x00},
++ {0x02, 0x0B}
++};
++
++#define S5K4BA_INIT_REGS (sizeof(s5k4ba_reg)/sizeof(s5k4ba_reg[0]))
++#define S5K4BA_UXGA_REGS (sizeof(s5k4ba_reg_uxga)/sizeof(s5k4ba_reg_uxga[0]))
++#define S5K4BA_SVGA_REGS (sizeof(s5k4ba_reg_svga)/sizeof(s5k4ba_reg_svga[0]))
++#define S5K4BA_VGA_REGS (sizeof(s5k4ba_reg_vga)/sizeof(s5k4ba_reg_vga[0]))
++#define S5K4BA_QSVGA_REGS (sizeof(s5k4ba_reg_qsvga)/sizeof(s5k4ba_reg_qsvga[0]))
++
++
++
++#define S5K4BA_RISC_REGS 0xEB
++#define S5K4BA_ISP_REGS 0xFB /* S5C7323X */
++#define S5K4BA_CIS_REGS 0x2F /* S5K437LA03 */
++
++
++#define S5K4BA_REGS (0x1000)
++
++
++
++#endif
++
+diff --git a/drivers/media/video/samsung/Makefile b/drivers/media/video/samsung/Makefile
+new file mode 100644
+index 0000000..885512c
+--- /dev/null
++++ b/drivers/media/video/samsung/Makefile
+@@ -0,0 +1,9 @@
++#
++# Samsung CIS camera module
++
++obj-$(CONFIG_VIDEO_SAMSUNG_S5K3AA) += 3xa_sensor.o
++obj-$(CONFIG_VIDEO_SAMSUNG_S5K3BA) += 3xa_sensor.o
++obj-$(CONFIG_VIDEO_SAMSUNG_S5K4BA) += 4xa_sensor.o
++obj-$(CONFIG_VIDEO_ADV7180) += adv7180.o
++obj-$(CONFIG_VIDEO_APTINA_MT9P012) += mt9p012.o
++
+diff --git a/drivers/media/video/samsung/adv7180.c b/drivers/media/video/samsung/adv7180.c
+new file mode 100644
+index 0000000..02db70d
+--- /dev/null
++++ b/drivers/media/video/samsung/adv7180.c
+@@ -0,0 +1,421 @@
++/*
++ * ADV7180 Analog decoder driver for S3C2443X
++ *
++ * Jaecheol Lee <jc.lee@samsung.com>
++ * 2007.08.08
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/i2c-id.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/video_decoder.h>
++#include <media/v4l2-dev.h>
++
++//#include <asm/arch/registers.h>
++#include "../s3c_camif.h"
++#include "adv7180.h"
++
++
++
++static const char *sensor_version =
++ "adv7180.c, v 1.00 2007/08/08 jc.lee@samsung.com";
++
++
++static struct i2c_driver i2c_driver_adv7180;
++
++/* This is an abstract CIS sensor for MSDMA input. */
++
++camif_cis_t msdma_input = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_YCBYCR, /* YCRYCB */
++ camclk: 32000000, /* No effect */
++ source_x: 800,
++ source_y: 480,
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 0,
++ polarity_vsync:1,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
++ reset_udelay: 20000,
++};
++
++camif_cis_t interlace_input = {
++ itu_fmt: CAMIF_ITU656,
++ order422: CAMIF_CBYCRY, /* YCRYCB */
++ camclk: 32000000, /* No effect */
++ source_x: 720,
++ source_y: 243,
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 0,
++ polarity_vsync:0,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
++ reset_udelay: 20000,
++};
++
++
++extern camif_cis_t* get_initialized_cis();
++camif_cis_t* get_initialized_cis() {
++ if(interlace_input.init_sensor == 0) return NULL;
++ return &interlace_input;
++
++}
++
++static unsigned short ignore[] = { I2C_CLIENT_END };
++static unsigned short normal_addr[] = { (I2C_ADV7180 >> 1), I2C_CLIENT_END };
++static unsigned short *forces[] = { NULL };
++
++static struct i2c_client_address_data addr_data = {
++ normal_i2c:normal_addr,
++ //normal_i2c_range:ignore,
++ probe:ignore,
++ //probe_range:ignore,
++ ignore:ignore,
++ //ignore_range:ignore,
++ forces:forces,
++};
++
++
++static inline int
++adv7180_write (struct i2c_client *client,
++ u8 reg,
++ u8 value)
++{
++ struct adv7180 *decoder = i2c_get_clientdata(client);
++ decoder->reg[reg] = value;
++ return i2c_smbus_write_byte_data(client, reg, value);
++}
++
++static inline int
++adv7180_read (struct i2c_client *client,
++ u8 reg)
++{
++ return i2c_smbus_read_byte_data(client, reg);
++}
++
++static int
++adv7180_write_block (struct i2c_client *client,
++ const u8 *data,
++ unsigned int len)
++{
++ int ret = -1;
++ u8 reg;
++
++ /* the adv7180 has an autoincrement function, use it if
++ * the adapter understands raw I2C */
++ if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++ /* do raw I2C, not smbus compatible */
++ struct adv7180 *decoder = i2c_get_clientdata(client);
++ struct i2c_msg msg;
++ u8 block_data[32];
++
++ msg.addr = client->addr;
++ msg.flags = 0;
++ while (len >= 2) {
++ msg.buf = (char *) block_data;
++ msg.len = 0;
++ block_data[msg.len++] = reg = data[0];
++ do {
++ block_data[msg.len++] =
++ decoder->reg[reg++] = data[1];
++ len -= 2;
++ data += 2;
++ } while (len >= 2 && data[0] == reg &&
++ msg.len < 32);
++ if ((ret = i2c_transfer(client->adapter,
++ &msg, 1)) < 0)
++ break;
++ }
++ } else {
++ /* do some slow I2C emulation kind of thing */
++ while (len >= 2) {
++ reg = *data++;
++ if ((ret = adv7180_write(client, reg,
++ *data++)) < 0)
++ break;
++ len -= 2;
++ }
++ }
++
++ return ret;
++}
++
++
++static int
++adv7180_detect_client (struct i2c_adapter *adapter,
++ int address,
++ int kind)
++{
++ int i;
++ struct i2c_client *client;
++ struct adv7180 *decoder;
++ char *dname;
++
++ /* Check if the adapter supports the needed features */
++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_EMUL))
++ return 0;
++
++ client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
++ if (client == 0)
++ return -ENOMEM;
++ client->addr = address;
++ client->adapter = adapter;
++ client->driver = &i2c_driver_adv7180;
++ if ((client->addr == I2C_ADV7180 >> 1) ||
++ (client->addr == (I2C_ADV7180 >> 1) + 1)) {
++ dname = adv7180_name;
++ } else {
++ /* We should never get here!!! */
++ kfree(client);
++ return 0;
++ }
++
++ client->data = &interlace_input;
++ interlace_input.sensor = client;
++ camif_register_cis(client);
++
++ strlcpy(I2C_NAME(client), dname, sizeof(I2C_NAME(client)));
++
++ decoder = kzalloc(sizeof(struct adv7180), GFP_KERNEL);
++ if (decoder == NULL) {
++ kfree(client);
++ return -ENOMEM;
++ }
++ decoder->norm = VIDEO_MODE_NTSC;
++ decoder->input = 0;
++ decoder->enable = 1;
++ i2c_set_clientdata(client, decoder);
++
++ i = i2c_attach_client(client);
++ if (i) {
++ kfree(client);
++ kfree(decoder);
++ return i;
++ }
++
++ i = adv7180_write_block(client, init_composite, sizeof(init_composite));
++ if (i >= 0) {
++
++ }
++ if (i < 0) {
++ }
++
++ return 0;
++}
++
++
++
++static int adv7180_attach_adapter(struct i2c_adapter *adap)
++{
++ return i2c_probe(adap, &addr_data, adv7180_detect_client);
++}
++
++static int adv7180_detach_client(struct i2c_client *client)
++{
++ int err;
++ err = i2c_detach_client(client);
++ if(err) {
++ return err;
++ }
++ camif_unregister_cis(client);
++
++ kfree(client);
++ return 0;
++}
++
++static int
++adv7180_command (struct i2c_client *client,
++ unsigned int cmd,
++ void *arg)
++{
++ int tmp;
++ u64 endtime;
++
++ struct adv7180 *decoder = i2c_get_clientdata(client);
++
++ switch (cmd) {
++
++ case 0:
++ /* This is just for testing!!! */
++ adv7180_write_block(client, init_composite,
++ sizeof(init_composite));
++ break;
++
++ case USER_ADD:
++ adv7180_write(client, 0x0f, (1<<7)); // Reset
++ endtime = get_jiffies_64() + RESET_DELAY;
++ while(jiffies < endtime); // Delay for a 5 ms
++ break;
++
++ case USER_EXIT:
++ adv7180_write(client, 0x0f, (1<<5)); // PWRDWN : 1
++ break;
++
++ case DECODER_INIT:
++ break;
++
++ case DECODER_GET_STATUS:
++ {
++ int *iarg = arg;
++
++ tmp = adv7180_read(client, 0x10) & 0x000000ff; // STATUS1
++ tmp = (tmp | (adv7180_read(client, 0x11) & 0x000000ff)<<8); // + IDENTIFICATION
++ tmp = (tmp | (adv7180_read(client, 0x12) & 0x000000ff)<<16); // + STATUS2
++ tmp = (tmp | (adv7180_read(client, 0x13) & 0x000000ff)<<24); // + STATUS3
++
++ *iarg = tmp;
++ }
++ break;
++
++ case DECODER_GET_CAPABILITIES:
++ {
++ struct video_decoder_capability *cap = arg;
++
++ cap->flags = VIDEO_DECODER_NTSC |
++ VIDEO_DECODER_PAL; /* well, hacky */
++ cap->inputs = 2;
++ cap->outputs = 1;
++ }
++ break;
++
++ case DECODER_SET_NORM:
++ {
++ int iarg = *(int *) arg;
++ switch (iarg) {
++
++ case 0: // Composite
++ adv7180_write_block(client, init_composite,
++ sizeof(init_composite));
++ break;
++
++ case 1: //S-VIDEO
++ adv7180_write_block(client, init_svideo,
++ sizeof(init_svideo));
++ break;
++
++ case 2: // Component
++ adv7180_write_block(client, init_component,
++ sizeof(init_component));
++ break;
++ default:
++ return -EINVAL;
++
++ }
++
++ decoder->norm = iarg;
++ }
++ break;
++
++ case DECODER_SET_INPUT:
++ {
++ int iarg = *(int *) arg;
++ decoder->input = iarg;
++
++ switch(decoder->input) {
++
++ case CVBS:
++ adv7180_write_block(client, init_composite,
++ sizeof(init_composite));
++ break;
++
++ case SVIDEO:
++ adv7180_write_block(client, init_svideo,
++ sizeof(init_svideo));
++ break;
++
++ case YPbPr:
++ adv7180_write_block(client, init_component,
++ sizeof(init_component));
++ break;
++
++ default:
++ return -EINVAL;
++
++ }
++ }
++ break;
++
++ case DECODER_SET_OUTPUT:
++ {
++ int *iarg = arg;
++
++ if (*iarg != 0) {
++ return -EINVAL;
++ }
++ }
++ break;
++
++ case DECODER_ENABLE_OUTPUT:
++ {
++ int *iarg = arg;
++
++ decoder->enable = !!*iarg;
++ }
++ break;
++
++ case DECODER_SET_GPIO:
++ {
++ int *iarg = arg;
++ switch(*iarg) {
++ case 0: // Pin 37 output is Field signal
++ adv7180_write(client, 0x58, 0x00);
++ break;
++
++ case 1: // Output is Vsync signal
++ adv7180_write(client, 0x58, (1<<0));
++ break;
++
++ default:
++ return -EINVAL;
++ }
++ }
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static struct i2c_driver i2c_driver_adv7180 = {
++ .driver = {
++ .name = "adv7180",
++ },
++ .id = I2C_DRIVERID_ADV7170, /* Must be fixed!!! */
++
++ .attach_adapter = adv7180_attach_adapter,
++ .detach_client = adv7180_detach_client,
++ .command = adv7180_command
++};
++
++static __init int adv7180_init(void)
++{
++ return i2c_add_driver(&i2c_driver_adv7180);
++}
++
++
++static __init void adv7180_exit(void)
++{
++ i2c_del_driver(&i2c_driver_adv7180);
++}
++
++module_init(adv7180_init)
++module_exit(adv7180_exit)
++
++MODULE_AUTHOR("JaeCheol Lee <jc.lee@samsung.com>");
++MODULE_DESCRIPTION("I2C Client Driver For ADV7180 video decoder");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/media/video/samsung/adv7180.h b/drivers/media/video/samsung/adv7180.h
+new file mode 100644
+index 0000000..afb2c82
+--- /dev/null
++++ b/drivers/media/video/samsung/adv7180.h
+@@ -0,0 +1,71 @@
++
++#ifndef _ADV7180_H_
++#define _ADV7180_H_
++
++//#include "../bits.h"
++
++////#define RESET_DELAY (5*HZ/10) // 5ms
++#define RESET_DELAY (10*HZ/10) // 5ms
++
++#define I2C_ADV7180 0x42
++
++#define I2C_NAME(s) (s)->name
++
++static char adv7180_name[] = "adv7180";
++
++enum input_mode {
++ CVBS, // Composite
++ SVIDEO, // S-video
++ YPbPr, // Component
++};
++
++struct adv7180 {
++ unsigned char reg[128];
++
++ int norm;
++ enum input_mode input;
++ int enable;
++};
++
++static const unsigned char init_composite[] = {
++ 0x00, 0x04,
++ 0x04, 0xD7,
++ 0x17, 0x41,
++ 0x31, 0x02,
++ 0x37, 0x09, ////
++ 0x3D, 0xA2,
++
++ 0x3E, 0x6A,
++ 0x3F, 0xA0,
++ 0x0E, 0x80,
++ 0x55, 0x81,
++ 0x0E, 0x00,
++};
++
++static const unsigned char init_component[] = {
++ 0x00, 0x09,
++ 0x31, 0x02,
++ 0x3D, 0xA2,
++ 0x3E, 0x6A,
++ 0x3F, 0xA0,
++
++ 0x0E, 0x80,
++ 0x55, 0x81,
++ 0x0E, 0x00,
++};
++
++static const unsigned char init_svideo[] = {
++ 0x00, 0x06,
++ 0x04, 0x57,
++ 0x31, 0x02,
++ 0x3D, 0xA2,
++ 0x3E, 0x6A,
++
++ 0x3F, 0xA0,
++ 0x58, 0x04,
++ 0x0E, 0x80,
++ 0x55, 0x81,
++ 0x0E, 0x00,
++};
++#endif
++
+diff --git a/drivers/media/video/samsung/mt9p012.c b/drivers/media/video/samsung/mt9p012.c
+new file mode 100644
+index 0000000..28e3bed
+--- /dev/null
++++ b/drivers/media/video/samsung/mt9p012.c
+@@ -0,0 +1,268 @@
++/*
++ * Copyright (C) 2004 Samsung Electronics
++ * SW.LEE <hitchcar@samsung.com>
++ * - based on Russell King : pcf8583.c
++ * - added smdk24a0, smdk2440
++ * - added poseidon (s3c24a0+wavecom)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Driver for FIMC2.x Camera Decoder
++ *
++ */
++
++//#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/i2c.h>
++#include <linux/i2c-id.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++
++//#define CAMIF_DEBUG
++
++#include "../s3c_camif.h"
++#include "mt9p012.h"
++
++static struct i2c_driver sensor_driver;
++
++camif_cis_t msdma_input;
++
++#define APTINA_MT9P012_INIT_RES_SXGA
++//#define APTINA_MT9P012_INIT_RES_QSXGA
++
++static camif_cis_t data = {
++ itu_fmt: CAMIF_ITU601,
++ order422: CAMIF_CBYCRY,
++ camclk: 16000000,
++
++#if defined(APTINA_MT9P012_INIT_RES_SXGA)
++ source_x: 1296,
++ source_y: 972,
++#elif defined(APTINA_MT9P012_INIT_RES_QSXGA)
++ source_x: 2592,
++ source_y: 1944,
++#endif
++
++ win_hor_ofst: 0,
++ win_ver_ofst: 0,
++ win_hor_ofst2: 0,
++ win_ver_ofst2: 0,
++ polarity_pclk: 0,
++ polarity_vsync:1,
++ polarity_href: 0,
++ reset_type:CAMIF_EX_RESET_AL,
++ reset_udelay: 5000,
++};
++
++camif_cis_t* get_initialized_cis(void)
++{
++ if (data.init_sensor == 0)
++ return NULL;
++
++ return &data;
++}
++
++#define CAM_ID 0x78
++
++static unsigned short ignore[] = { I2C_CLIENT_END };
++static unsigned short normal_addr[] = { (CAM_ID >> 1), I2C_CLIENT_END };
++static unsigned short *forces[] = { NULL };
++
++static struct i2c_client_address_data addr_data = {
++ normal_i2c:normal_addr,
++ /* normal_i2c_range:ignore, */
++ probe:ignore,
++ /* probe_range:ignore, */
++ ignore:ignore,
++ /* ignore_range:ignore, */
++ forces:forces,
++};
++
++
++unsigned char sensor_read(struct i2c_client *client, unsigned char val0)
++{
++ int ret;
++ unsigned char buf[1];
++ struct i2c_msg msg = { client->addr, 0, 1, buf };
++ buf[0] = val0;
++
++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++ if (ret == -EIO) {
++ printk(" I2C write Error \n");
++ return -EIO;
++ }
++
++ msg.flags = I2C_M_RD;
++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++
++ return buf[0];
++}
++
++static int
++sensor_write(struct i2c_client *client,
++ unsigned char val0, unsigned char val1, unsigned char val2, unsigned char val3)
++{
++ unsigned char buf[4];
++ struct i2c_msg msg = { client->addr, 0, 4, buf };
++
++ buf[0] = val0;
++ buf[1] = val1;
++ buf[2] = val2;
++ buf[3] = val3;
++
++ return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
++}
++
++void inline sensor_init(struct i2c_client *sam_client)
++{
++ int i;
++
++ for (i = 0; i < MT9P012_INIT_REGS; i++) {
++ if (mt9p012_init_reg[i].value0 == 0xde && mt9p012_init_reg[i].value1 == 0xde && mt9p012_init_reg[i].value2 == 0xde) {
++ mdelay(mt9p012_init_reg[i].value3);
++ continue;
++ }
++
++ sensor_write(sam_client, mt9p012_init_reg[i].value0, mt9p012_init_reg[i].value1,
++ mt9p012_init_reg[i].value2, mt9p012_init_reg[i].value3);
++ }
++
++#if defined(APTINA_MT9P012_INIT_RES_QSXGA)
++ for (i = 0; i < MT9P012_QSXGA_REGS; i++) {
++ sensor_write(sam_client, mt9p012_qsxga_reg[i].value0, mt9p012_qsxga_reg[i].value1,
++ mt9p012_qsxga_reg[i].value2, mt9p012_qsxga_reg[i].value3);
++ }
++#endif
++}
++
++static int
++mt9p012_attach(struct i2c_adapter *adap, int addr, int kind)
++{
++ struct i2c_client *c;
++
++ c = kmalloc(sizeof(*c), GFP_KERNEL);
++ if (!c)
++ return -ENOMEM;
++
++ memset(c, 0, sizeof(struct i2c_client));
++
++ strcpy(c->name, "mt9p012");
++ c->addr = addr;
++ c->adapter = adap;
++ c->driver = &sensor_driver;
++ c->data = &data;
++ data.sensor = c;
++
++ s3c_camif_register_sensor(c);
++
++ return i2c_attach_client(c);
++}
++
++static int sensor_attach_adapter(struct i2c_adapter *adap)
++{
++ s3c_camif_open_sensor(&data);
++ return i2c_probe(adap, &addr_data, mt9p012_attach);
++}
++
++static int sensor_detach(struct i2c_client *client)
++{
++ i2c_detach_client(client);
++ s3c_camif_unregister_sensor(client);
++ return 0;
++}
++
++/* Purpose:
++ This fucntion only for SVGA Camera : 4BA
++*/
++static int change_sensor_size(struct i2c_client *client, int size)
++{
++ int i;
++
++ switch (size) {
++ case SENSOR_SXGA_MT9P012:
++ for (i = 0; i < MT9P012_SXGA_REGS; i++) {
++ sensor_write(client, mt9p012_sxga_reg[i].value0, mt9p012_sxga_reg[i].value1,
++ mt9p012_sxga_reg[i].value2, mt9p012_sxga_reg[i].value3);
++ }
++ break;
++
++ case SENSOR_QSXGA_MT9P012:
++ for (i = 0; i < MT9P012_QSXGA_REGS; i++) {
++ sensor_write(client, mt9p012_qsxga_reg[i].value0, mt9p012_qsxga_reg[i].value1,
++ mt9p012_qsxga_reg[i].value2, mt9p012_qsxga_reg[i].value3);
++ }
++ break;
++
++ default:
++ printk("mt9p012.c: unexpected value\n");
++ break;
++ }
++
++ return 0;
++}
++
++static int
++sensor_command(struct i2c_client *client, unsigned int cmd, void *arg)
++{
++ switch (cmd) {
++ case SENSOR_INIT:
++ sensor_init(client);
++ printk(KERN_INFO "External Camera initialized\n");
++ break;
++
++ case SENSOR_SXGA_MT9P012:
++ change_sensor_size(client, SENSOR_SXGA_MT9P012);
++ break;
++
++ case SENSOR_QSXGA_MT9P012:
++ change_sensor_size(client, SENSOR_QSXGA_MT9P012);
++ break;
++
++ case USER_ADD:
++ break;
++
++ case USER_EXIT:
++ break;
++
++ default:
++ printk("mt9p012.c: Unexpected sensor command\n");
++ break;
++ }
++
++ return 0;
++}
++
++static struct i2c_driver sensor_driver = {
++ .driver = {
++ .name = "mt9p012",
++ },
++ .id = I2C_DRIVERID_MT9P012,
++ .attach_adapter = sensor_attach_adapter,
++ .detach_client = sensor_detach,
++ .command = sensor_command
++};
++
++static __init int camif_sensor_init(void)
++{
++ return i2c_add_driver(&sensor_driver);
++}
++
++
++static __init void camif_sensor_exit(void)
++{
++ i2c_del_driver(&sensor_driver);
++}
++
++module_init(camif_sensor_init)
++module_exit(camif_sensor_exit)
++
++MODULE_AUTHOR("Jinsung, Yang <jsgood.yang@samsung.com>");
++MODULE_DESCRIPTION("I2C Client Driver For FIMC V4L2 Driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/media/video/samsung/mt9p012.h b/drivers/media/video/samsung/mt9p012.h
+new file mode 100644
+index 0000000..76580d3
+--- /dev/null
++++ b/drivers/media/video/samsung/mt9p012.h
+@@ -0,0 +1,758 @@
++
++#ifndef _MT9P012_H_
++#define _MT9P012_H_
++
++#if defined(CONFIG_VIDEO_APTINA_MT9P012)
++
++typedef struct cam_init_t{
++ unsigned char value0;
++ unsigned char value1;
++ unsigned char value2;
++ unsigned char value3;
++} mt9p012_t;
++
++mt9p012_t mt9p012_init_reg[] =
++{
++ {0x00, 0x1a, 0x00, 0x19},// / / RESET_AND_MISC_CONTROL
++ {0x00, 0x1a, 0x00, 0x18},// / / RESET_AND_MISC_CONTROL
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0x00, 0x14, 0x01, 0x45},// /
++ {0x00, 0x10, 0x00, 0x10},// / / PLL_DIVIDERS (N=0, M=16) VCO = 24M*2*16/(0+1) = 768M
++ {0x00, 0x12, 0x00, 0x70},// /
++ {0x00, 0x2a, 0x78, 0x87},// /
++ {0x00, 0x2c, 0x00, 0x00},// /
++ {0x00, 0x2e, 0x04, 0x00},// /
++ {0x00, 0x14, 0x01, 0x47},// /
++ {0x00, 0x14, 0x00, 0x47},// /
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0x00, 0x14, 0x00, 0x46},// /
++ {0x00, 0x22, 0x01, 0xe0},// / / 24 MHz oscillator
++ {0x00, 0x1a, 0x00, 0x18},// / / RESET_AND_MISC_CONTROL
++ {0x00, 0x18, 0x40, 0x2d},// / / STANDBY_CONTROL_AND_STATUS
++ {0x00, 0x18, 0x40, 0x2c},// / / STANDBY_CONTROL_AND_STATUS
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0x09, 0x8e, 0x60, 0x3c},// / / MCU_ADDRESS [IO_I2C_CLK_DIVIDER]
++ {0x09, 0x90, 0x07, 0x80},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x43},// / / MCU_ADDRESS [PRI_A_CONFIG_AWB_AWB_XSHIFT]
++ {0x09, 0x90, 0x00, 0x47},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x45},// / / MCU_ADDRESS [PRI_A_CONFIG_AWB_AWB_YSHIFT]
++ {0x09, 0x90, 0x00, 0x43},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x43},// / / MCU_ADDRESS [PRI_B_CONFIG_AWB_AWB_XSHIFT]
++ {0x09, 0x90, 0x00, 0x47},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x45},// / / MCU_ADDRESS [PRI_B_CONFIG_AWB_AWB_YSHIFT]
++ {0x09, 0x90, 0x00, 0x43},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc8, 0xf4},// / / MCU_ADDRESS [CAM1_AWB_AWB_XSCALE]
++ {0x09, 0x90, 0x00, 0x03},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc8, 0xf5},// / / MCU_ADDRESS [CAM1_AWB_AWB_YSCALE]
++ {0x09, 0x90, 0x00, 0x02},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xf6},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_0]
++ {0x09, 0x90, 0xde, 0x76},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xf8},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_1]
++ {0x09, 0x90, 0xfe, 0x17},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xfa},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_2]
++ {0x09, 0x90, 0x56, 0x61},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xfc},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_3]
++ {0x09, 0x90, 0xf0, 0x55},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xfe},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_4]
++ {0x09, 0x90, 0x56, 0x05},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x00},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_5]
++ {0x09, 0x90, 0xf7, 0x0d},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x02},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_6]
++ {0x09, 0x90, 0x0f, 0xf0},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x04},// / / MCU_ADDRESS [CAM1_AWB_AWB_WEIGHTS_7]
++ {0x09, 0x90, 0x00, 0xdf},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x06},// / / MCU_ADDRESS [CAM1_AWB_AWB_XSHIFT_PRE_ADJ]
++ {0x09, 0x90, 0x00, 0x47},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x08},// / / MCU_ADDRESS [CAM1_AWB_AWB_YSHIFT_PRE_ADJ]
++ {0x09, 0x90, 0x00, 0x43},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xb0},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_0]
++ {0x09, 0x90, 0x01, 0xfd},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xb2},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_1]
++ {0x09, 0x90, 0xfe, 0xc0},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xb4},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_2]
++ {0x09, 0x90, 0x00, 0x5f},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xb6},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_3]
++ {0x09, 0x90, 0xff, 0xf3},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xb8},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_4]
++ {0x09, 0x90, 0x01, 0x49},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xba},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_5]
++ {0x09, 0x90, 0xff, 0xdf},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xbc},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_6]
++ {0x09, 0x90, 0xff, 0xc9},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xbe},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_7]
++ {0x09, 0x90, 0xfe, 0xd7},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xc0},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_8]
++ {0x09, 0x90, 0x02, 0x7b},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xc2},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_9]
++ {0x09, 0x90, 0x00, 0x1a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xc4},// / / MCU_ADDRESS [CAM1_AWB_CCM_L_10]
++ {0x09, 0x90, 0x00, 0x4a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xc6},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_0]
++ {0x09, 0x90, 0x00, 0x02},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xc8},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_1]
++ {0x09, 0x90, 0x00, 0x39},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xca},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_2]
++ {0x09, 0x90, 0xff, 0xc3},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xcc},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_3]
++ {0x09, 0x90, 0x00, 0x0a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xce},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_4]
++ {0x09, 0x90, 0xff, 0xf2},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xd0},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_5]
++ {0x09, 0x90, 0x00, 0x03},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xd2},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_6]
++ {0x09, 0x90, 0x00, 0x3a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xd4},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_7]
++ {0x09, 0x90, 0x00, 0x30},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xd6},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_8]
++ {0x09, 0x90, 0xff, 0x94},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xd8},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_9]
++ {0x09, 0x90, 0x00, 0x1b},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xda},// / / MCU_ADDRESS [CAM1_AWB_CCM_RL_10]
++ {0x09, 0x90, 0xff, 0xdf},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x39},// / / MCU_ADDRESS [PRI_A_CONFIG_AE_TRACK_AE_MAX_VIRT_AGAIN]
++ {0x09, 0x90, 0x01, 0xfc},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x35},// / / MCU_ADDRESS [PRI_A_CONFIG_AE_TRACK_AE_MAX_VIRT_DGAIN]
++ {0x09, 0x90, 0x01, 0x5e},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x39},// / / MCU_ADDRESS [PRI_B_CONFIG_AE_TRACK_AE_MAX_VIRT_AGAIN]
++ {0x09, 0x90, 0x01, 0xfc},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x35},// / / MCU_ADDRESS [PRI_B_CONFIG_AE_TRACK_AE_MAX_VIRT_DGAIN]
++ {0x09, 0x90, 0x01, 0x5e},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xe8, 0x1f},// / / MCU_ADDRESS [PRI_A_CONFIG_AE_RULE_BASE_TARGET]
++ {0x09, 0x90, 0x00, 0x40},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xec, 0x1f},// / / MCU_ADDRESS [PRI_B_CONFIG_AE_RULE_BASE_TARGET]
++ {0x09, 0x90, 0x00, 0x40},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x67},// / / MCU_ADDRESS [PRI_A_CONFIG_LL_ALGO_RUN]
++ {0x09, 0x90, 0x00, 0x74},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x84, 0x00},// / / MCU_ADDRESS [SEQ_CMD]
++ {0x09, 0x90, 0x00, 0x06},// / / MCU_DATA_0
++ {0x35, 0x40, 0x00, 0x00},// / / ENABLE_TONAL_CURVE
++ {0x09, 0x8e, 0xbc, 0x0b},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_0]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x0c},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_1]
++ {0x09, 0x90, 0x00, 0x1b},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x0d},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_2]
++ {0x09, 0x90, 0x00, 0x2a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x0e},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_3]
++ {0x09, 0x90, 0x00, 0x3e},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x0f},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_4]
++ {0x09, 0x90, 0x00, 0x5a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x10},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_5]
++ {0x09, 0x90, 0x00, 0x70},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x11},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_6]
++ {0x09, 0x90, 0x00, 0x81},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x12},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_7]
++ {0x09, 0x90, 0x00, 0x90},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x13},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_8]
++ {0x09, 0x90, 0x00, 0x9e},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x14},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_9]
++ {0x09, 0x90, 0x00, 0xab},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x15},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_10]
++ {0x09, 0x90, 0x00, 0xb6},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x16},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_11]
++ {0x09, 0x90, 0x00, 0xc1},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x17},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_12]
++ {0x09, 0x90, 0x00, 0xcb},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x18},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_13]
++ {0x09, 0x90, 0x00, 0xd5},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x19},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_14]
++ {0x09, 0x90, 0x00, 0xde},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x1a},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_15]
++ {0x09, 0x90, 0x00, 0xe7},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x1b},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_16]
++ {0x09, 0x90, 0x00, 0xef},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x1c},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_17]
++ {0x09, 0x90, 0x00, 0xf7},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x1d},// / / MCU_ADDRESS [LL_GAMMA_CONTRAST_CURVE_18]
++ {0x09, 0x90, 0x00, 0xff},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x1e},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_0]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x1f},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_1]
++ {0x09, 0x90, 0x00, 0x1b},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x20},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_2]
++ {0x09, 0x90, 0x00, 0x2a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x21},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_3]
++ {0x09, 0x90, 0x00, 0x3e},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x22},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_4]
++ {0x09, 0x90, 0x00, 0x5a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x23},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_5]
++ {0x09, 0x90, 0x00, 0x70},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x24},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_6]
++ {0x09, 0x90, 0x00, 0x81},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x25},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_7]
++ {0x09, 0x90, 0x00, 0x90},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x26},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_8]
++ {0x09, 0x90, 0x00, 0x9e},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x27},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_9]
++ {0x09, 0x90, 0x00, 0xab},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x28},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_10]
++ {0x09, 0x90, 0x00, 0xb6},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x29},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_11]
++ {0x09, 0x90, 0x00, 0xc1},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x2a},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_12]
++ {0x09, 0x90, 0x00, 0xcb},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x2b},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_13]
++ {0x09, 0x90, 0x00, 0xd5},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x2c},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_14]
++ {0x09, 0x90, 0x00, 0xde},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x2d},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_15]
++ {0x09, 0x90, 0x00, 0xe7},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x2e},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_16]
++ {0x09, 0x90, 0x00, 0xef},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x2f},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_17]
++ {0x09, 0x90, 0x00, 0xf7},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x30},// / / MCU_ADDRESS [LL_GAMMA_NEUTRAL_CURVE_18]
++ {0x09, 0x90, 0x00, 0xff},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x31},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_0]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x32},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_1]
++ {0x09, 0x90, 0x00, 0x0d},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x33},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_2]
++ {0x09, 0x90, 0x00, 0x19},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x34},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_3]
++ {0x09, 0x90, 0x00, 0x30},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x35},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_4]
++ {0x09, 0x90, 0x00, 0x56},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x36},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_5]
++ {0x09, 0x90, 0x00, 0x70},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x37},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_6]
++ {0x09, 0x90, 0x00, 0x81},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x38},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_7]
++ {0x09, 0x90, 0x00, 0x90},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x39},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_8]
++ {0x09, 0x90, 0x00, 0x9e},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x3a},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_9]
++ {0x09, 0x90, 0x00, 0xab},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x3b},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_10]
++ {0x09, 0x90, 0x00, 0xb6},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x3c},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_11]
++ {0x09, 0x90, 0x00, 0xc1},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x3d},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_12]
++ {0x09, 0x90, 0x00, 0xcb},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x3e},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_13]
++ {0x09, 0x90, 0x00, 0xd5},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x3f},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_14]
++ {0x09, 0x90, 0x00, 0xde},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x40},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_15]
++ {0x09, 0x90, 0x00, 0xe7},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x41},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_16]
++ {0x09, 0x90, 0x00, 0xef},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x42},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_17]
++ {0x09, 0x90, 0x00, 0xf7},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x43},// / / MCU_ADDRESS [LL_GAMMA_NRCURVE_18]
++ {0x09, 0x90, 0x00, 0xff},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x6d},// / / MCU_ADDRESS [CAM1_LL_START_GAMMA_BM]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x6f},// / / MCU_ADDRESS [CAM1_LL_MID_GAMMA_BM]
++ {0x09, 0x90, 0x00, 0x02},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x71},// / / MCU_ADDRESS [CAM1_LL_STOP_GAMMA_BM]
++ {0x09, 0x90, 0x03, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xdc},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_0]
++ {0x09, 0x90, 0x01, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xde},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_1]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xe0},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_2]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xe2},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_3]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xe4},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_4]
++ {0x09, 0x90, 0x01, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xe6},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_5]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xe8},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_6]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xea},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_7]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xec},// / / MCU_ADDRESS [CAM1_AWB_LL_CCM_8]
++ {0x09, 0x90, 0x01, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xdc, 0x2a},// / / MCU_ADDRESS [SYS_DELTA_GAIN]
++ {0x09, 0x90, 0x00, 0x05},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xdc, 0x2b},// / / MCU_ADDRESS [SYS_DELTA_THRESH]
++ {0x09, 0x90, 0x00, 0x36},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x14},// / / MCU_ADDRESS [CAM1_LL_START_DESATURATION]
++ {0x09, 0x90, 0x00, 0xff},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x15},// / / MCU_ADDRESS [CAM1_LL_END_DESATURATION]
++ {0x09, 0x90, 0x00, 0xff},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x6b},// / / MCU_ADDRESS [PRI_A_CONFIG_LL_START_BRIGHTNESS]
++ {0x09, 0x90, 0x03, 0x84},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x6d},// / / MCU_ADDRESS [PRI_A_CONFIG_LL_STOP_BRIGHTNESS]
++ {0x09, 0x90, 0x0e, 0x74},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xe8, 0x6f},// / / MCU_ADDRESS [PRI_A_CONFIG_LL_START_SATURATION]
++ {0x09, 0x90, 0x00, 0x80},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xe8, 0x70},// / / MCU_ADDRESS [PRI_A_CONFIG_LL_END_SATURATION]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x6b},// / / MCU_ADDRESS [PRI_B_CONFIG_LL_START_BRIGHTNESS]
++ {0x09, 0x90, 0x03, 0x84},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x6d},// / / MCU_ADDRESS [PRI_B_CONFIG_LL_STOP_BRIGHTNESS]
++ {0x09, 0x90, 0x0e, 0x74},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xec, 0x6f},// / / MCU_ADDRESS [PRI_B_CONFIG_LL_START_SATURATION]
++ {0x09, 0x90, 0x00, 0x80},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xec, 0x70},// / / MCU_ADDRESS [PRI_B_CONFIG_LL_END_SATURATION]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x8f},// / / MCU_ADDRESS [CAM1_SYS_UV_COLOR_BOOST]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x90},// / / MCU_ADDRESS [CAM1_SYS_DARK_COLOR_KILL]
++ {0x09, 0x90, 0x00, 0x70},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x91},// / / MCU_ADDRESS [CAM1_SYS_BRIGHT_COLORKILL]
++ {0x09, 0x90, 0x00, 0x70},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x1e},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_0]
++ {0x09, 0x90, 0x00, 0x80},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x20},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_1]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x22},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_2]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x24},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_3]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x26},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_4]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x28},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_5]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x2a},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_6]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x2c},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_7]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x2e},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_8]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x30},// / / MCU_ADDRESS [CAM1_LL_BNR_SETTINGS_9]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x44},// / / MCU_ADDRESS [CAM1_LL_BNR_BLEND_START_0]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x45},// / / MCU_ADDRESS [CAM1_LL_BNR_BLEND_START_1]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x46},// / / MCU_ADDRESS [CAM1_LL_BNR_BLEND_START_2]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x47},// / / MCU_ADDRESS [CAM1_LL_BNR_BLEND_STOP_0]
++ {0x09, 0x90, 0x00, 0x10},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x48},// / / MCU_ADDRESS [CAM1_LL_BNR_BLEND_STOP_1]
++ {0x09, 0x90, 0x00, 0x10},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x49},// / / MCU_ADDRESS [CAM1_LL_BNR_BLEND_STOP_2]
++ {0x09, 0x90, 0x00, 0x10},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x5c},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_0]
++ {0x09, 0x90, 0x00, 0x64},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x5d},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_1]
++ {0x09, 0x90, 0x00, 0x38},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x5e},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_2]
++ {0x09, 0x90, 0x00, 0x64},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x5f},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_3]
++ {0x09, 0x90, 0x00, 0x51},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x60},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_4]
++ {0x09, 0x90, 0x00, 0x10},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x61},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_5]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x62},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_6]
++ {0x09, 0x90, 0x00, 0x10},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x63},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_START_7]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x64},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_0]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x65},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_1]
++ {0x09, 0x90, 0x00, 0x14},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x66},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_2]
++ {0x09, 0x90, 0x00, 0x1d},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x67},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_3]
++ {0x09, 0x90, 0x00, 0x20},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x68},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_4]
++ {0x09, 0x90, 0x00, 0x0c},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x69},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_5]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x6a},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_6]
++ {0x09, 0x90, 0x00, 0x0c},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x6b},// / / MCU_ADDRESS [CAM1_LL_GRB_THRESHOLDS_STOP_7]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x6c},// / / MCU_ADDRESS [CAM1_LL_GRB_WINDOW_PERCENT]
++ {0x09, 0x90, 0x00, 0x64},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x32},// / / MCU_ADDRESS [CAM1_LL_FFNR_SETTINGS_0]
++ {0x09, 0x90, 0x15, 0x2b},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x18},// / / MCU_ADDRESS [CAM1_LL_HF_CONFIG]
++ {0x09, 0x90, 0x00, 0x9f},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x1a},// / / MCU_ADDRESS [CAM1_LL_HF_SLOPE]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x1c},// / / MCU_ADDRESS [CAM1_LL_HF_OFFSET]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x34},// / / MCU_ADDRESS [CAM1_LL_FFNR_SETTINGS_1]
++ {0x09, 0x90, 0x00, 0x0a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x36},// / / MCU_ADDRESS [CAM1_LL_FFNR_SETTINGS_2]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x38},// / / MCU_ADDRESS [CAM1_LL_FFNR_SETTINGS_3]
++ {0x09, 0x90, 0x00, 0x0c},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x4e},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_START_0]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x4f},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_START_1]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x50},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_START_2]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x51},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_START_3]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x52},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_START_4]
++ {0x09, 0x90, 0x00, 0x0f},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x53},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_START_5]
++ {0x09, 0x90, 0x00, 0x0f},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x54},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_STOP_0]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x55},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_STOP_1]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x56},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_STOP_2]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x57},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_STOP_3]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x58},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_STOP_4]
++ {0x09, 0x90, 0x00, 0x08},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x59},// / / MCU_ADDRESS [CAM1_LL_UA_WEIGHTS_STOP_5]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x32, 0x6a, 0x12, 0x08},// / / APERTURE_PARAMETERS_1D
++ {0x09, 0x8e, 0xc9, 0x4b},// / / MCU_ADDRESS [CAM1_LL_LEGACY2DSETTINGS_START_1]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x4a},// / / MCU_ADDRESS [CAM1_LL_LEGACY2DSETTINGS_START_0]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x4c},// / / MCU_ADDRESS [CAM1_LL_LEGACY2DSETTINGS_STOP_0]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc9, 0x4d},// / / MCU_ADDRESS [CAM1_LL_LEGACY2DSETTINGS_STOP_1]
++ {0x09, 0x90, 0x00, 0x09},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x3a},// / / MCU_ADDRESS [CAM1_LL_DCCDC_SETTINGS_0]
++ {0x09, 0x90, 0x00, 0xc8},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xbc, 0x05},// / / MCU_ADDRESS [LL_CLUSTER_DC_TH]
++ {0x09, 0x90, 0x00, 0x38},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x42},// / / MCU_ADDRESS [CAM1_LL_STOP_GAIN_METRIC]
++ {0x09, 0x90, 0x07, 0xd0},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x0a},// / / MCU_ADDRESS [CAM1_AS_INTEG_SCALE_FIRST_PASS]
++ {0x09, 0x90, 0x06, 0x66},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x0c},// / / MCU_ADDRESS [CAM1_AS_MIN_INT_TIME_FIRST_PASS]
++ {0x09, 0x90, 0x01, 0x40},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x57},// / / MCU_ADDRESS [PRI_A_CONFIG_IS_FEATURE_THRESHOLD]
++ {0x09, 0x90, 0x00, 0x14},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x57},// / / MCU_ADDRESS [PRI_B_CONFIG_IS_FEATURE_THRESHOLD]
++ {0x09, 0x90, 0x00, 0x14},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x68, 0x5c},// / / MCU_ADDRESS [PRI_A_CONFIG_IS_BLUR_INPUT_PARAMETER]
++ {0x09, 0x90, 0x00, 0x05},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x5c},// / / MCU_ADDRESS [PRI_B_CONFIG_IS_BLUR_INPUT_PARAMETER]
++ {0x09, 0x90, 0x00, 0x05},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x49, 0x0e},// / / MCU_ADDRESS [CAM1_AS_MAX_DIGITAL_GAIN_ALLOWED]
++ {0x09, 0x90, 0x00, 0xa4},// / / MCU_DATA_0
++ {0x36, 0x4a, 0x01, 0x10},// / / P_R_P0Q0
++ {0x36, 0x4c, 0x1a, 0x2d},// / / P_R_P0Q1
++ {0x36, 0x4e, 0x36, 0x71},// / / P_R_P0Q2
++ {0x36, 0x50, 0xd3, 0x8c},// / / P_R_P0Q3
++ {0x36, 0x52, 0x91, 0xd1},// / / P_R_P0Q4
++ {0x36, 0x8a, 0x82, 0xcc},// / / P_R_P1Q0
++ {0x36, 0x8c, 0x15, 0x8d},// / / P_R_P1Q1
++ {0x36, 0x8e, 0xdf, 0xee},// / / P_R_P1Q2
++ {0x36, 0x90, 0x8b, 0x0e},// / / P_R_P1Q3
++ {0x36, 0x92, 0x63, 0xcf},// / / P_R_P1Q4
++ {0x36, 0xca, 0x35, 0x51},// / / P_R_P2Q0
++ {0x36, 0xcc, 0x07, 0x2b},// / / P_R_P2Q1
++ {0x36, 0xce, 0x92, 0x32},// / / P_R_P2Q2
++ {0x36, 0xd0, 0xae, 0x31},// / / P_R_P2Q3
++ {0x36, 0xd2, 0x7a, 0x50},// / / P_R_P2Q4
++ {0x37, 0x0a, 0x2f, 0xcc},// / / P_R_P3Q0
++ {0x37, 0x0c, 0x94, 0x90},// / / P_R_P3Q1
++ {0x37, 0x0e, 0x32, 0x2e},// / / P_R_P3Q2
++ {0x37, 0x10, 0x12, 0x71},// / / P_R_P3Q3
++ {0x37, 0x12, 0xe9, 0xcd},// / / P_R_P3Q4
++ {0x37, 0x4a, 0xab, 0x90},// / / P_R_P4Q0
++ {0x37, 0x4c, 0x82, 0x30},// / / P_R_P4Q1
++ {0x37, 0x4e, 0xf5, 0x33},// / / P_R_P4Q2
++ {0x37, 0x50, 0x0c, 0x93},// / / P_R_P4Q3
++ {0x37, 0x52, 0x6f, 0x15},// / / P_R_P4Q4
++ {0x36, 0x40, 0x00, 0xd0},// / / P_G1_P0Q0
++ {0x36, 0x42, 0xb1, 0x2c},// / / P_G1_P0Q1
++ {0x36, 0x44, 0x2f, 0x51},// / / P_G1_P0Q2
++ {0x36, 0x46, 0x70, 0x8a},// / / P_G1_P0Q3
++ {0x36, 0x48, 0x82, 0x11},// / / P_G1_P0Q4
++ {0x36, 0x80, 0x97, 0x4b},// / / P_G1_P1Q0
++ {0x36, 0x82, 0x4a, 0xeb},// / / P_G1_P1Q1
++ {0x36, 0x84, 0x82, 0x2f},// / / P_G1_P1Q2
++ {0x36, 0x86, 0xe7, 0x4d},// / / P_G1_P1Q3
++ {0x36, 0x88, 0x2d, 0x4f},// / / P_G1_P1Q4
++ {0x36, 0xc0, 0x22, 0xd1},// / / P_G1_P2Q0
++ {0x36, 0xc2, 0x02, 0x2d},// / / P_G1_P2Q1
++ {0x36, 0xc4, 0x95, 0x12},// / / P_G1_P2Q2
++ {0x36, 0xc6, 0xd0, 0x4d},// / / P_G1_P2Q3
++ {0x36, 0xc8, 0x3a, 0xf0},// / / P_G1_P2Q4
++ {0x37, 0x00, 0x87, 0x4e},// / / P_G1_P3Q0
++ {0x37, 0x02, 0xcb, 0x2e},// / / P_G1_P3Q1
++ {0x37, 0x04, 0x02, 0xb0},// / / P_G1_P3Q2
++ {0x37, 0x06, 0x13, 0xf0},// / / P_G1_P3Q3
++ {0x37, 0x08, 0x25, 0x2f},// / / P_G1_P3Q4
++ {0x37, 0x40, 0x99, 0xf0},// / / P_G1_P4Q0
++ {0x37, 0x42, 0x54, 0xd0},// / / P_G1_P4Q1
++ {0x37, 0x44, 0xa4, 0x33},// / / P_G1_P4Q2
++ {0x37, 0x46, 0xbf, 0x32},// / / P_G1_P4Q3
++ {0x37, 0x48, 0x35, 0x55},// / / P_G1_P4Q4
++ {0x36, 0x54, 0x01, 0x70},// / / P_B_P0Q0
++ {0x36, 0x56, 0xa2, 0x4c},// / / P_B_P0Q1
++ {0x36, 0x58, 0x7e, 0x50},// / / P_B_P0Q2
++ {0x36, 0x5a, 0xe1, 0xcb},// / / P_B_P0Q3
++ {0x36, 0x5c, 0x94, 0x30},// / / P_B_P0Q4
++ {0x36, 0x94, 0x59, 0xab},// / / P_B_P1Q0
++ {0x36, 0x96, 0x28, 0x8d},// / / P_B_P1Q1
++ {0x36, 0x98, 0x92, 0x6d},// / / P_B_P1Q2
++ {0x36, 0x9a, 0x93, 0xee},// / / P_B_P1Q3
++ {0x36, 0x9c, 0x10, 0xae},// / / P_B_P1Q4
++ {0x36, 0xd4, 0x69, 0x70},// / / P_B_P2Q0
++ {0x36, 0xd6, 0x13, 0x0e},// / / P_B_P2Q1
++ {0x36, 0xd8, 0xbd, 0xb0},// / / P_B_P2Q2
++ {0x36, 0xda, 0x8a, 0xb0},// / / P_B_P2Q3
++ {0x36, 0xdc, 0x99, 0xb0},// / / P_B_P2Q4
++ {0x37, 0x14, 0x72, 0x0d},// / / P_B_P3Q0
++ {0x37, 0x16, 0xcb, 0x6f},// / / P_B_P3Q1
++ {0x37, 0x18, 0xcb, 0xac},// / / P_B_P3Q2
++ {0x37, 0x1a, 0x1d, 0x50},// / / P_B_P3Q3
++ {0x37, 0x1c, 0x90, 0x4e},// / / P_B_P3Q4
++ {0x37, 0x54, 0xe4, 0xee},// / / P_B_P4Q0
++ {0x37, 0x56, 0x05, 0xb1},// / / P_B_P4Q1
++ {0x37, 0x58, 0xdc, 0x73},// / / P_B_P4Q2
++ {0x37, 0x5a, 0x99, 0x12},// / / P_B_P4Q3
++ {0x37, 0x5c, 0x35, 0xd5},// / / P_B_P4Q4
++ {0x36, 0x5e, 0x03, 0x50},// / / P_G2_P0Q0
++ {0x36, 0x60, 0x5a, 0x6c},// / / P_G2_P0Q1
++ {0x36, 0x62, 0x34, 0x91},// / / P_G2_P0Q2
++ {0x36, 0x64, 0xa8, 0x2d},// / / P_G2_P0Q3
++ {0x36, 0x66, 0x8b, 0xb1},// / / P_G2_P0Q4
++ {0x36, 0x9e, 0x58, 0x6c},// / / P_G2_P1Q0
++ {0x36, 0xa0, 0x76, 0x6b},// / / P_G2_P1Q1
++ {0x36, 0xa2, 0x1a, 0x6c},// / / P_G2_P1Q2
++ {0x36, 0xa4, 0xe2, 0x2d},// / / P_G2_P1Q3
++ {0x36, 0xa6, 0xbb, 0x0b},// / / P_G2_P1Q4
++ {0x36, 0xde, 0x25, 0x91},// / / P_G2_P2Q0
++ {0x36, 0xe0, 0xaf, 0x2f},// / / P_G2_P2Q1
++ {0x36, 0xe2, 0xa0, 0x12},// / / P_G2_P2Q2
++ {0x36, 0xe4, 0x94, 0x6f},// / / P_G2_P2Q3
++ {0x36, 0xe6, 0x07, 0x91},// / / P_G2_P2Q4
++ {0x37, 0x1e, 0x76, 0xcd},// / / P_G2_P3Q0
++ {0x37, 0x20, 0xf2, 0x8e},// / / P_G2_P3Q1
++ {0x37, 0x22, 0xc7, 0xb0},// / / P_G2_P3Q2
++ {0x37, 0x24, 0x2e, 0xf0},// / / P_G2_P3Q3
++ {0x37, 0x26, 0x25, 0x31},// / / P_G2_P3Q4
++ {0x37, 0x5e, 0xc5, 0xcf},// / / P_G2_P4Q0
++ {0x37, 0x60, 0x59, 0x70},// / / P_G2_P4Q1
++ {0x37, 0x62, 0x9f, 0xd3},// / / P_G2_P4Q2
++ {0x37, 0x64, 0x59, 0x11},// / / P_G2_P4Q3
++ {0x37, 0x66, 0x2b, 0xb5},// / / P_G2_P4Q4
++ {0x37, 0x84, 0x05, 0x0c},// / / CENTER_COLUMN
++ {0x37, 0x82, 0x03, 0xdc},// / / CENTER_ROW
++ {0x32, 0x10, 0x00, 0xb8},// / / COLOR_PIPELINE_CONTROL
++ {0x09, 0x82, 0x00, 0x00},// / / ACCESS_CTL_STAT
++ {0x09, 0x8a, 0x1f, 0x9d},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0x37, 0x3c},// /
++ {0x09, 0x92, 0x3c, 0x30},// /
++ {0x09, 0x94, 0xe6, 0x04},// /
++ {0x09, 0x96, 0xbd, 0x9e},// /
++ {0x09, 0x98, 0xe2, 0xcc},// /
++ {0x09, 0x9a, 0x00, 0x16},// /
++ {0x09, 0x9c, 0x30, 0xed},// /
++ {0x09, 0x9e, 0x02, 0xcc},// /
++ {0x09, 0x8a, 0x1f, 0xad},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0xc7, 0xff},// /
++ {0x09, 0x92, 0xed, 0x00},// /
++ {0x09, 0x94, 0xe6, 0x04},// /
++ {0x09, 0x96, 0x4f, 0x17},// /
++ {0x09, 0x98, 0x5f, 0x84},// /
++ {0x09, 0x9a, 0x38, 0xbd},// /
++ {0x09, 0x9c, 0xa8, 0x50},// /
++ {0x09, 0x9e, 0x38, 0x38},// /
++ {0x09, 0x8a, 0x1f, 0xbd},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0x31, 0x39},// /
++ {0x09, 0x92, 0x0f, 0xbd},// /
++ {0x09, 0x94, 0x1f, 0xde},// /
++ {0x09, 0x96, 0xcc, 0x1f},// /
++ {0x09, 0x98, 0xde, 0xbd},// /
++ {0x09, 0x9a, 0x4c, 0x6c},// /
++ {0x09, 0x9c, 0xc6, 0x01},// /
++ {0x09, 0x9e, 0xf7, 0x1d},// /
++ {0x09, 0x8a, 0x1f, 0xcd},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0x4c, 0xfc},// /
++ {0x09, 0x92, 0x07, 0xe5},// /
++ {0x09, 0x94, 0x83, 0x1f},// /
++ {0x09, 0x96, 0xbf, 0x26},// /
++ {0x09, 0x98, 0x06, 0xce},// /
++ {0x09, 0x9a, 0x07, 0xd5},// /
++ {0x09, 0x9c, 0x1d, 0x04},// /
++ {0x09, 0x9e, 0x04, 0x0e},// /
++ {0x09, 0x8a, 0x1f, 0xdd},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0x39, 0xc6},// /
++ {0x09, 0x92, 0x20, 0xf7},// /
++ {0x09, 0x94, 0x07, 0xdf},// /
++ {0x09, 0x96, 0xc6, 0x01},// /
++ {0x09, 0x98, 0xf7, 0x07},// /
++ {0x09, 0x9a, 0xe0, 0xde},// /
++ {0x09, 0x9c, 0x47, 0x18},// /
++ {0x09, 0x9e, 0xce, 0x00},// /
++ {0x09, 0x8a, 0x1f, 0xed},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0x5b, 0xcc},// /
++ {0x09, 0x92, 0x00, 0x3f},// /
++ {0x09, 0x94, 0xbd, 0x43},// /
++ {0x09, 0x96, 0x14, 0xcc},// /
++ {0x09, 0x98, 0x1f, 0x9d},// /
++ {0x09, 0x9a, 0xfd, 0x00},// /
++ {0x09, 0x9c, 0x7d, 0xcc},// /
++ {0x09, 0x9e, 0x00, 0x5b},// /
++ {0x09, 0x8a, 0x1f, 0xfd},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0xdd, 0x47},// /
++ {0x09, 0x8a, 0x9f, 0xff},// / / PHYSICAL_ADDR_ACCESS
++ {0x09, 0x90, 0x00, 0x39},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x00, 0x10},// / / MCU_ADDRESS [MON_ADDR]
++ {0x09, 0x90, 0x1f, 0xbf},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x00, 0x03},// / / MCU_ADDRESS [MON_ALGO]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xec, 0x8e},// / / MCU_ADDRESS [PRI_B_CONFIG_JPEG_JP_MODE]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0x99},// / / MCU_ADDRESS [CAM1_VT_PIX_CLK_DIV]
++ {0x09, 0x90, 0x00, 0x07},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0x9b},// / / MCU_ADDRESS [CAM1_VT_SYS_CLK_DIV]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0x9d},// / / MCU_ADDRESS [CAM1_PRE_PLL_CLK_DIV]
++ {0x09, 0x90, 0x00, 0x02},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0x9f},// / / MCU_ADDRESS [CAM1_PLL_MULTIPLIER]
++ {0x09, 0x90, 0x00, 0x40},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xa1},// / / MCU_ADDRESS [CAM1_OP_PIX_CLK_DIV]
++ {0x09, 0x90, 0x00, 0x0a},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0xa3},// / / MCU_ADDRESS [CAM1_OP_SYS_CLK_DIV]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc8, 0x98},// / / MCU_ADDRESS [CAM1_B_PLLSETTINGS]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0x0c},// / / MCU_ADDRESS [CAM1_CTX_A_READ_MODE]
++ {0x09, 0x90, 0x04, 0x6c},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0x15},// / / MCU_ADDRESS [CAM1_CTX_A_COARSE_ITMIN]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x48, 0x5d},// / / MCU_ADDRESS [CAM1_CTX_B_COARSE_ITMIN]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x00, 0x1e, 0x07, 0x77},// / / serial
++ {0x3c, 0x86, 0x00, 0xe1},// / / set tx_ss PCLK1 slew rate
++ {0x3c, 0x88, 0x00, 0xe1},// / / set tx_ss PCLK2 slew rate
++ {0x3c, 0x8a, 0x00, 0xe1},// / / set tx_ss PCLK3 slew rate
++ {0x09, 0x8e, 0xc9, 0xab},// / / MCU_ADDRESS [CAM1_SOC_DATAPORT]
++ {0x09, 0x90, 0x00, 0x19},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xc8, 0x94},// / / MCU_ADDRESS [CAM1_DATA_PORT]
++ {0x09, 0x90, 0x00, 0x03},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xcd, 0xab},// / / MCU_ADDRESS [CAM2_SOC_DATAPORT]
++ {0x09, 0x90, 0x00, 0x91},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xcc, 0x94},// / / MCU_ADDRESS [CAM2_DATA_PORT]
++ {0x09, 0x90, 0x00, 0x03},// / / MCU_DATA_0
++ {0x00, 0x2e, 0x05, 0x00},// / / SENSOR_CLOCK_DIVIDER
++ {0x09, 0x8e, 0x80, 0x02},// / / MCU_ADDRESS [MON_MODE]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x3b, 0x86, 0x00, 0x35},// / / TXBUFFER_TOTAL_BYTE_COUNT
++ {0x3b, 0x00, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_0
++ {0x3b, 0x02, 0xb0, 0x30},// / / TXBUFFER_DATA_REGISTER_1
++ {0x3b, 0x04, 0x01, 0x00},// / / TXBUFFER_DATA_REGISTER_2
++ {0x3b, 0x06, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_3
++ {0x3b, 0x08, 0x8e, 0x30},// / / TXBUFFER_DATA_REGISTER_4
++ {0x3b, 0x0a, 0x60, 0xe0},// / / TXBUFFER_DATA_REGISTER_5
++ {0x3b, 0x0c, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_6
++ {0x3b, 0x0e, 0x92, 0x30},// / / TXBUFFER_DATA_REGISTER_7
++ {0x3b, 0x10, 0x52, 0x0a},// / / TXBUFFER_DATA_REGISTER_8
++ {0x3b, 0x12, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_9
++ {0x3b, 0x14, 0x94, 0x30},// / / TXBUFFER_DATA_REGISTER_10
++ {0x3b, 0x16, 0x56, 0x46},// / / TXBUFFER_DATA_REGISTER_11
++ {0x3b, 0x18, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_12
++ {0x3b, 0x1a, 0x96, 0x30},// / / TXBUFFER_DATA_REGISTER_13
++ {0x3b, 0x1c, 0x52, 0x56},// / / TXBUFFER_DATA_REGISTER_14
++ {0x3b, 0x1e, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_15
++ {0x3b, 0x20, 0xca, 0x30},// / / TXBUFFER_DATA_REGISTER_16
++ {0x3b, 0x22, 0x06, 0x80},// / / TXBUFFER_DATA_REGISTER_17
++ {0x3b, 0x24, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_18
++ {0x3b, 0x26, 0x2a, 0x31},// / / TXBUFFER_DATA_REGISTER_19
++ {0x3b, 0x28, 0x02, 0xdd},// / / TXBUFFER_DATA_REGISTER_20
++ {0x3b, 0x2a, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_21
++ {0x3b, 0x2c, 0x2c, 0x31},// / / TXBUFFER_DATA_REGISTER_22
++ {0x3b, 0x2e, 0xe4, 0x00},// / / TXBUFFER_DATA_REGISTER_23
++ {0x3b, 0x30, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_24
++ {0x3b, 0x32, 0x70, 0x31},// / / TXBUFFER_DATA_REGISTER_25
++ {0x3b, 0x34, 0x9a, 0x29},// / / TXBUFFER_DATA_REGISTER_26
++ {0x3b, 0x82, 0x00, 0x01},// / / I2C_MASTER_CONTROL
++ {0x3b, 0x86, 0x00, 0x35},// / / TXBUFFER_TOTAL_BYTE_COUNT
++ {0x3b, 0x00, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_0
++ {0x3b, 0x02, 0x04, 0x02},// / / TXBUFFER_DATA_REGISTER_1
++ {0x3b, 0x04, 0x10, 0x00},// / / TXBUFFER_DATA_REGISTER_2
++ {0x3b, 0x06, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_3
++ {0x3b, 0x08, 0x06, 0x02},// / / TXBUFFER_DATA_REGISTER_4
++ {0x3b, 0x0a, 0x10, 0x00},// / / TXBUFFER_DATA_REGISTER_5
++ {0x3b, 0x0c, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_6
++ {0x3b, 0x0e, 0x08, 0x02},// / / TXBUFFER_DATA_REGISTER_7
++ {0x3b, 0x10, 0x10, 0x00},// / / TXBUFFER_DATA_REGISTER_8
++ {0x3b, 0x12, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_9
++ {0x3b, 0x14, 0x0a, 0x02},// / / TXBUFFER_DATA_REGISTER_10
++ {0x3b, 0x16, 0x10, 0x00},// / / TXBUFFER_DATA_REGISTER_11
++ {0x3b, 0x18, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_12
++ {0x3b, 0x1a, 0x0c, 0x02},// / / TXBUFFER_DATA_REGISTER_13
++ {0x3b, 0x1c, 0x10, 0x00},// / / TXBUFFER_DATA_REGISTER_14
++ {0x3b, 0x1e, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_15
++ {0x3b, 0x20, 0x88, 0x30},// / / TXBUFFER_DATA_REGISTER_16
++ {0x3b, 0x22, 0xf6, 0x6f},// / / TXBUFFER_DATA_REGISTER_17
++ {0x3b, 0x24, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_18
++ {0x3b, 0x26, 0x54, 0x31},// / / TXBUFFER_DATA_REGISTER_19
++ {0x3b, 0x28, 0x82, 0x02},// / / TXBUFFER_DATA_REGISTER_20
++ {0x3b, 0x2a, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_21
++ {0x3b, 0x2c, 0x56, 0x31},// / / TXBUFFER_DATA_REGISTER_22
++ {0x3b, 0x2e, 0x81, 0x03},// / / TXBUFFER_DATA_REGISTER_23
++ {0x3b, 0x30, 0x83, 0x6c},// / / TXBUFFER_DATA_REGISTER_24
++ {0x3b, 0x32, 0x62, 0x31},// / / TXBUFFER_DATA_REGISTER_25
++ {0x3b, 0x34, 0xce, 0x04},// / / TXBUFFER_DATA_REGISTER_26
++ {0x3b, 0x82, 0x00, 0x01},// / / I2C_MASTER_CONTROL
++ {0x09, 0x8e, 0x80, 0x02},// / / MCU_ADDRESS [MON_MODE]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0xde, 0xde, 0xde, 0x20},// Delay(100},
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0x00, 0x2e, 0x04, 0x00},// / / SENSOR_CLOCK_DIVIDER
++ {0x09, 0x8e, 0xe8, 0x2c},// / / MCU_ADDRESS [PRI_A_CONFIG_AE_TRACK_JUMP_DIVISOR]
++ {0x09, 0x90, 0x00, 0x03},// / / MCU_DATA_0
++ {0x00, 0x18, 0x00, 0x28},// / / STANDBY_CONTROL_AND_STATUS
++ {0xde, 0xde, 0xde, 0x40},// Delay(200},
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0x09, 0x8e, 0x6c, 0x07},// / / MCU_ADDRESS [PRI_B_OUTPUT_FORMAT]
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x09},// / / MCU_ADDRESS [PRI_B_OUTPUT_FORMAT_ORDER]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xec, 0x8e},// / / MCU_ADDRESS [PRI_B_CONFIG_JPEG_JP_MODE]
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++
++#if 0 // auto focuing and white balance setting
++ {0x09, 0x8e, 0x6c, 0x19},// / / MCU_ADDRESS [PRI_B_CONFIG_AE_RULE_ALGO_ENTER]
++ {0x09, 0x90, 0x80, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x1b},// / / MCU_ADDRESS [PRI_B_CONFIG_AE_RULE_ALGO_RUN]
++ {0x09, 0x90, 0x00, 0x04},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x27},// / / MCU_ADDRESS [PRI_B_CONFIG_AE_TRACK_ALGO_RUN]
++ {0x09, 0x90, 0x00, 0x07},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x3f},// / / MCU_ADDRESS [PRI_B_CONFIG_AWB_ALGO_RUN]
++ {0x09, 0x90, 0x1f, 0xff},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x5e},// / / MCU_ADDRESS [PRI_B_CONFIG_STAT_ALGO_ENTER]
++ {0x09, 0x90, 0x80, 0x1f},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0x60},// / / MCU_ADDRESS [PRI_B_CONFIG_STAT_ALGO_RUN]
++ {0x09, 0x90, 0x12, 0xe0},// / / MCU_DATA_0
++ {0x09, 0x8e, 0xec, 0x2c},// / / MCU_ADDRESS [PRI_B_CONFIG_AE_TRACK_JUMP_DIVISOR]
++ {0x09, 0x90, 0x00, 0x03},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x6c, 0xad},// / / MCU_ADDRESS [PRI_B_SYNC_FRAME]
++ {0x09, 0x90, 0x01, 0x0c},// / / MCU_DATA_0
++#endif
++
++ {0x09, 0x8e, 0x84, 0x00},// / / MCU_ADDRESS [SEQ_CMD]
++ {0x09, 0x90, 0x00, 0x06},// / / MCU_DATA_0
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++ {0xde, 0xde, 0xde, 0xff},// Delay(2000},
++};
++
++mt9p012_t mt9p012_sxga_reg[] =
++{
++ {0x09, 0x8e, 0xec, 0x05},// / / MCU_DATA_0
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x84, 0x00},// / / MCU_DATA_0
++ {0x09, 0x90, 0x00, 0x01},// / / MCU_DATA_0
++};
++
++mt9p012_t mt9p012_qsxga_reg[] =
++{
++ {0x09, 0x8e, 0xec, 0x05},// / / MCU_DATA_0
++ {0x09, 0x90, 0x00, 0x00},// / / MCU_DATA_0
++ {0x09, 0x8e, 0x84, 0x00},// / / MCU_DATA_0
++ {0x09, 0x90, 0x00, 0x02},// / / MCU_DATA_0
++};
++
++#define MT9P012_INIT_REGS (sizeof(mt9p012_init_reg) / sizeof(mt9p012_init_reg[0]))
++#define MT9P012_SXGA_REGS (sizeof(mt9p012_sxga_reg) / sizeof(mt9p012_sxga_reg[0]))
++#define MT9P012_QSXGA_REGS (sizeof(mt9p012_qsxga_reg) / sizeof(mt9p012_qsxga_reg[0]))
++
++#endif
++
++#endif
++
+diff --git a/drivers/media/video/videodev2_s3c.h b/drivers/media/video/videodev2_s3c.h
+new file mode 100644
+index 0000000..abcf08c
+--- /dev/null
++++ b/drivers/media/video/videodev2_s3c.h
+@@ -0,0 +1,210 @@
++#ifndef __VIDEODEV2_S3C_H_
++#define __VIDEODEV2_S3C_H_
++
++#include <linux/videodev2.h>
++
++#define V4L2_INPUT_TYPE_MSDMA 3
++#define V4L2_INPUT_TYPE_INTERLACE 4
++
++/****************************************************************
++* struct v4l2_control
++* Control IDs defined by S3C
++*****************************************************************/
++/* Image Effect */
++#define V4L2_CID_ORIGINAL (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_ARBITRARY (V4L2_CID_PRIVATE_BASE + 1)
++#define V4L2_CID_NEGATIVE (V4L2_CID_PRIVATE_BASE + 2)
++#define V4L2_CID_ART_FREEZE (V4L2_CID_PRIVATE_BASE + 3)
++#define V4L2_CID_EMBOSSING (V4L2_CID_PRIVATE_BASE + 4)
++#define V4L2_CID_SILHOUETTE (V4L2_CID_PRIVATE_BASE + 5)
++
++/* Image Rotate */
++#define V4L2_CID_ROTATE_90 (V4L2_CID_PRIVATE_BASE + 6)
++#define V4L2_CID_ROTATE_180 (V4L2_CID_PRIVATE_BASE + 7)
++#define V4L2_CID_ROTATE_270 (V4L2_CID_PRIVATE_BASE + 8)
++#define V4L2_CID_ROTATE_BYPASS (V4L2_CID_PRIVATE_BASE + 9)
++
++/* Zoom-in, Zoom-out */
++#define V4L2_CID_ZOOMIN (V4L2_CID_PRIVATE_BASE + 10)
++#define V4L2_CID_ZOOMOUT (V4L2_CID_PRIVATE_BASE + 11)
++
++/****************************************************************
++* I O C T L C O D E S F O R V I D E O D E V I C E S
++* It's only for S3C
++*****************************************************************/
++#define VIDIOC_S_CAMERA_START _IO ('V', BASE_VIDIOC_PRIVATE + 0)
++#define VIDIOC_S_CAMERA_STOP _IO ('V', BASE_VIDIOC_PRIVATE + 1)
++#define VIDIOC_MSDMA_START _IOW ('V', BASE_VIDIOC_PRIVATE + 2, struct v4l2_msdma_format)
++#define VIDIOC_MSDMA_STOP _IOW ('V', BASE_VIDIOC_PRIVATE + 3, struct v4l2_msdma_format)
++#define VIDIOC_S_MSDMA _IOW ('V', BASE_VIDIOC_PRIVATE + 4, struct v4l2_msdma_format)
++#define VIDIOC_S_INTERLACE_MODE _IOW ('V', BASE_VIDIOC_PRIVATE + 5, struct v4l2_interlace_format)
++
++/*
++ * INTERLACE MODE
++ */
++#define S3C_VIDEO_DECODER_PAL 1 /* can decode PAL signal */
++#define S3C_VIDEO_DECODER_NTSC 2 /* can decode NTSC */
++#define S3C_VIDEO_DECODER_SECAM 4 /* can decode SECAM */
++#define S3C_VIDEO_DECODER_AUTO 8 /* can autosense norm */
++#define S3C_VIDEO_DECODER_CCIR 16 /* CCIR-601 pixel rate (720 pixels per line) instead of square pixel rate */
++
++#define S3C_DECODER_INIT _IOW ('V', BASE_VIDIOC_PRIVATE + 14, struct s3c_video_decoder_init) /* init internal registers at once */
++#define S3C_DECODER_GET_CAPABILITIES _IOR ('V', BASE_VIDIOC_PRIVATE + 6, struct s3c_video_decoder_capability)
++#define S3C_DECODER_GET_STATUS _IOR ('V', BASE_VIDIOC_PRIVATE + 7, int)
++#define S3C_DECODER_SET_NORM _IOW ('V', BASE_VIDIOC_PRIVATE + 8, int)
++#define S3C_DECODER_SET_INPUT _IOW ('V', BASE_VIDIOC_PRIVATE + 9, int) /* 0 <= input < #inputs */
++#define S3C_DECODER_SET_OUTPUT _IOW ('V', BASE_VIDIOC_PRIVATE + 10, int) /* 0 <= output < #outputs */
++#define S3C_DECODER_ENABLE_OUTPUT _IOW ('V', BASE_VIDIOC_PRIVATE + 11, int) /* boolean output enable control */
++#define S3C_DECODER_SET_PICTURE _IOW ('V', BASE_VIDIOC_PRIVATE + 12, struct video_picture)
++#define S3C_DECODER_SET_GPIO _IOW ('V', BASE_VIDIOC_PRIVATE + 13, int) /* switch general purpose pin */
++#define S3C_DECODER_SET_VBI_BYPASS _IOW ('V', BASE_VIDIOC_PRIVATE + 15, int) /* switch vbi bypass */
++#define S3C_DECODER_DUMP _IO ('V', BASE_VIDIOC_PRIVATE + 16) /* debug hook */
++
++enum v4l2_msdma_input {
++ V4L2_MSDMA_CODEC = 1,
++ V4L2_MSDMA_PREVIEW = 2,
++};
++
++struct v4l2_msdma_format
++{
++ __u32 width; /* MSDMA INPUT : Source X size */
++ __u32 height; /* MSDMA INPUT : Source Y size */
++ __u32 pixelformat;
++ enum v4l2_msdma_input input_path;
++};
++
++struct v4l2_interlace_format
++{
++ __u32 width; /* INTERLACE INPUT : Source X size */
++ __u32 height; /* INTERLACE INPUT : Source Y size */
++};
++
++struct s3c_video_decoder_init {
++ unsigned char len;
++ const unsigned char *data;
++};
++
++struct s3c_video_decoder_capability { /* this name is too long */
++ __u32 flags;
++ int inputs; /* number of inputs */
++ int outputs; /* number of outputs */
++};
++
++static struct v4l2_input fimc_inputs[] = {
++ {
++ .index = 0,
++ .name = "S3C FIMC External Camera Input",
++ .type = V4L2_INPUT_TYPE_CAMERA,
++ .audioset = 1,
++ .tuner = 0,
++ .std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M,
++ .status = 0,
++ },
++ {
++ .index = 1,
++ .name = "Memory Input (MSDMA)",
++ .type = V4L2_INPUT_TYPE_MSDMA,
++ .audioset = 2,
++ .tuner = 0,
++ .std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M,
++ .status = 0,
++ }
++};
++
++static struct v4l2_output fimc_outputs[] = {
++ {
++ .index = 0,
++ .name = "Pingpong Memory Output",
++ .type = 0,
++ .audioset = 0,
++ .modulator = 0,
++ .std = 0,
++ },
++ {
++ .index = 1,
++ .name = "LCD FIFO Output",
++ .type = 0,
++ .audioset = 0,
++ .modulator = 0,
++ .std = 0,
++ }
++};
++
++const struct v4l2_fmtdesc fimc_codec_formats[] = {
++ {
++ .index = 0,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .description = "16 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ .flags = FORMAT_FLAGS_PACKED,
++ },
++ {
++ .index = 1,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "32 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_BGR32,
++ },
++ {
++ .index = 2,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:2, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++
++ },
++ {
++ .index = 3,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:0, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ }
++};
++
++const struct v4l2_fmtdesc fimc_preview_formats[] = {
++ {
++ .index = 0,
++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "16 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ },
++ {
++ .index = 1,
++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "24 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB24,
++ },
++ {
++ .index = 2,
++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "32 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_BGR32,
++ },
++ {
++ .index = 3,
++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:2, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++
++ },
++ {
++ .index = 4,
++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:0, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ }
++};
++
++#define NUMBER_OF_PREVIEW_FORMATS ARRAY_SIZE(fimc_preview_formats)
++#define NUMBER_OF_CODEC_FORMATS ARRAY_SIZE(fimc_codec_formats)
++#define NUMBER_OF_INPUTS ARRAY_SIZE(fimc_inputs)
++#define NUMBER_OF_OUTPUTS ARRAY_SIZE(fimc_outputs)
++
++#endif
++
+diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
+index b0c22ca..98e0707 100644
+--- a/drivers/mmc/core/bus.c
++++ b/drivers/mmc/core/bus.c
+@@ -231,6 +231,7 @@ int mmc_add_card(struct mmc_card *card)
+ case MMC_TYPE_SDIO:
+ type = "SDIO";
+ break;
++
+ default:
+ type = "?";
+ break;
+diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
+index 68c0e3b..5e773b3 100644
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -397,6 +397,14 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ * Activate wide bus (if supported).
+ */
+ if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) &&
++ (host->caps & MMC_CAP_8_BIT_DATA)) {
++ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
++ EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8);
++ if (err)
++ goto free_card;
++
++ mmc_set_bus_width(card->host, MMC_BUS_WIDTH_8);
++ } else if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) &&
+ (host->caps & MMC_CAP_4_BIT_DATA)) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_4);
+@@ -404,7 +412,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ goto free_card;
+
+ mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4);
+- }
++ }
+
+ if (!oldcard)
+ host->card = card;
+diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
+index 5fef678..e440252 100644
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -14,6 +14,53 @@ config MMC_ARMMMCI
+
+ If unsure, say N.
+
++config MMC_S3C
++ tristate "Samsung S3C Multimedia Card Interface support"
++ select MMC_BLOCK
++ depends on ARCH_S3C2410 && MMC && !(CPU_S3C6400 || CPU_S3C6410)
++ help
++ This selects the Samsung S3C Multimedia Card Interface
++ support.
++
++ If unsure, say N.
++
++config HSMMC_S3C
++ tristate "Samsung S3C High Speed MMC Interface support"
++ select MMC_BLOCK
++ depends on (CPU_S3C2443 || CPU_S3C2450 || CPU_S3C2416 || CPU_S3C6400 || CPU_S3C6410) && MMC
++ help
++ This selects the Samsung S3C Multimedia Card Interface
++ support.
++
++ If unsure, say N.
++
++config USE_MMC_AS_ROOT
++ bool "MMC can be used as a Root Filesystem Device"
++ depends on HSMMC_S3C
++ default y
++ help
++ Say Y here when you want to use MMC as a root file system.
++
++config HSMMC_S3C_IRQ_WORKAROUND
++ bool "Fix IRQ Hanging in HS-MMC"
++ depends on HSMMC_S3C
++ default y
++ help
++ Say Y here when you are using S3C6400 or S3C6410.
++
++config HSMMC_SCATTERGATHER
++ bool "Support Scatter and Gather in HS-MMC"
++ depends on HSMMC_S3C
++ help
++ Say Y here. This option can support scatter and gather
++ using DMA boundary in HS-MMC DMA engine.
++
++config S3CMMC_DEBUG
++ bool "To debug interface, enable all debug messages"
++ depends on (MMC_S3C || HSMMC_S3C)
++ help
++ Say Y here to enable Debug Messages.
++
+ config MMC_PXA
+ tristate "Intel PXA25x/26x/27x Multimedia Card Interface support"
+ depends on ARCH_PXA
+diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
+index 3877c87..a74fea6 100644
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -17,4 +17,5 @@ obj-$(CONFIG_MMC_OMAP) += omap.o
+ obj-$(CONFIG_MMC_AT91) += at91_mci.o
+ obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
+ obj-$(CONFIG_MMC_SPI) += mmc_spi.o
+-
++obj-$(CONFIG_MMC_S3C) += s3cmci.o
++obj-$(CONFIG_HSMMC_S3C) += s3c-hsmmc.o
+diff --git a/drivers/mmc/host/s3c-hsmmc.c b/drivers/mmc/host/s3c-hsmmc.c
+new file mode 100644
+index 0000000..3d8c68e
+--- /dev/null
++++ b/drivers/mmc/host/s3c-hsmmc.c
+@@ -0,0 +1,1398 @@
++/*
++ * linux/drivers/mmc/s3c-hsmmc.c - Samsung S3C24XX HS-MMC driver
++ *
++ * $Id: s3c-hsmmc.c,v 1.53 2008/06/23 07:56:52 jsgood Exp $
++ *
++ * Copyright (C) 2006 Samsung Electronics, All Rights Reserved.
++ * by Suh, Seung-Chull<sc.suh@samsung.com>
++ *
++ * This driver is made for High Speed MMC interface. This interface
++ * is adopted and implemented since s3c2443 was made.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Modified by Ryu,Euiyoul <steven.ryu@samsung.com>
++ * Modified by Suh, Seung-chull to support s3c6400
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/highmem.h>
++#include <linux/dma-mapping.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/sd.h>
++#include <linux/mmc/card.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/proc_fs.h>
++#include <linux/irq.h>
++
++#include <asm/dma.h>
++#include <asm/dma-mapping.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/scatterlist.h>
++#include <asm/sizes.h>
++#include <asm/mach/mmc.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-hsmmc.h>
++#include <asm/plat-s3c24xx/clock.h>
++#include <asm/arch/dma.h>
++
++#include <asm/arch/hsmmc.h>
++
++
++#ifdef CONFIG_S3CMMC_DEBUG
++#define DBG(x...) printk(PFX x)
++#else
++#define DBG(x...) do { } while (0)
++#endif
++
++#include "s3c-hsmmc.h"
++
++#define DRIVER_NAME "s3c-hsmmc"
++#define PFX DRIVER_NAME ": "
++
++#define MULTICARD_ON_SINGLEBUS_SUPPORT
++#undef MULTICARD_ON_SINGLEBUS_SUPPORT
++
++#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
++
++#if defined(CONFIG_PM)
++struct s3c_hsmmc_host *global_host[3];
++#endif
++
++static int card_detect = 0;
++/*****************************************************************************\
++ * *
++ * Low level functions *
++ * *
++\*****************************************************************************/
++
++static struct s3c_hsmmc_cfg s3c_hsmmc_platform = {
++ .hwport = 0,
++ .enabled = 0,
++ .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE),
++ .base = NULL,
++ .highspeed = 0,
++
++ /* ctrl for mmc */
++ .fd_ctrl[0] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
++ .ctrl3[0] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[1] = 0x00000080, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++
++ /* ctrl for sd */
++ .fd_ctrl[1] = {
++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */
++ .ctrl3[0] = 0, /* ctrl3 for low speed */
++ .ctrl3[1] = 0, /* ctrl3 for high speed */
++ .ctrl4 = 0,
++ },
++};
++
++/* s3c_hsmmc_get_platdata
++ *
++ * get the platform data associated with the given device, or return
++ * the default if there is none
++ */
++
++static struct s3c_hsmmc_cfg *s3c_hsmmc_get_platdata (struct device *dev)
++{
++ if (dev->platform_data != NULL)
++ return (struct s3c_hsmmc_cfg *)dev->platform_data;
++
++ return &s3c_hsmmc_platform;
++}
++
++static void s3c_hsmmc_reset (struct s3c_hsmmc_host *host, u8 mask)
++{
++ unsigned long timeout;
++
++ s3c_hsmmc_writeb(mask, S3C_HSMMC_SWRST);
++
++ if (mask & S3C_HSMMC_RESET_ALL)
++ host->clock = (uint)-1;
++
++ /* Wait max 100 ms */
++ timeout = 100;
++
++ /* hw clears the bit when it's done */
++ while (s3c_hsmmc_readb(S3C_HSMMC_SWRST) & mask) {
++ if (timeout == 0) {
++ printk("%s: Reset 0x%x never completed. \n",
++ mmc_hostname(host->mmc), (int)mask);
++ return;
++ }
++ timeout--;
++ mdelay(1);
++ }
++
++}
++
++static void s3c_hsmmc_ios_init (struct s3c_hsmmc_host *host)
++{
++ u32 intmask;
++
++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL);
++
++ intmask = S3C_HSMMC_INT_BUS_POWER | S3C_HSMMC_INT_DATA_END_BIT |
++ S3C_HSMMC_INT_DATA_CRC | S3C_HSMMC_INT_DATA_TIMEOUT | S3C_HSMMC_INT_INDEX |
++ S3C_HSMMC_INT_END_BIT | S3C_HSMMC_INT_CRC | S3C_HSMMC_INT_TIMEOUT |
++ S3C_HSMMC_INT_CARD_REMOVE | S3C_HSMMC_INT_CARD_INSERT |
++ S3C_HSMMC_INT_DATA_AVAIL | S3C_HSMMC_INT_SPACE_AVAIL |
++ S3C_HSMMC_INT_DATA_END | S3C_HSMMC_INT_RESPONSE;
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++ intmask |= S3C_HSMMC_INT_DMA_END;
++#endif
++ s3c_hsmmc_writel(intmask, S3C_HSMMC_NORINTSTSEN);
++ s3c_hsmmc_writel(intmask, S3C_HSMMC_NORINTSIGEN);
++}
++
++/*****************************************************************************\
++ * *
++ * Tasklets *
++ * *
++\*****************************************************************************/
++
++static void s3c_hsmmc_tasklet_card (ulong param)
++{
++ struct s3c_hsmmc_host *host;
++ unsigned long iflags;
++
++ host = (struct s3c_hsmmc_host*)param;
++ spin_lock_irqsave(&host->lock, iflags);
++
++ if (!(s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT)) {
++ if (host->mrq) {
++ printk(KERN_ERR "%s: Card removed during transfer!\n",
++ mmc_hostname(host->mmc));
++ printk(KERN_ERR "%s: Resetting controller.\n",
++ mmc_hostname(host->mmc));
++
++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_CMD);
++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_DATA);
++
++ host->mrq->cmd->error = -ENOMEDIUM;
++ tasklet_schedule(&host->finish_tasklet);
++ }
++ }
++
++ spin_unlock_irqrestore(&host->lock, iflags);
++
++ mmc_detect_change(host->mmc, msecs_to_jiffies(500));
++}
++
++static void s3c_hsmmc_activate_led(struct s3c_hsmmc_host *host)
++{
++#if 0
++ u8 ctrl;
++
++ ctrl = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
++ ctrl |= S3C_HSMMC_CTRL_LED;
++ s3c_hsmmc_writeb(ctrl, S3C_HSMMC_HOSTCTL);
++#endif
++
++#if 0 // for 6400
++ gpio_set_pin(S3C_GPJ13, S3C_GPJ13_SD0LED);
++#endif
++}
++
++static void s3c_hsmmc_deactivate_led(struct s3c_hsmmc_host *host)
++{
++#if 0
++ u8 ctrl;
++
++ ctrl = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
++ ctrl &= ~S3C_HSMMC_CTRL_LED;
++ s3c_hsmmc_writeb(ctrl, S3C_HSMMC_HOSTCTL);
++#endif
++
++#if 0 // for 6400
++ gpio_direction_input(S3C_GPJ13);
++#endif
++}
++
++/*****************************************************************************\
++ * *
++ * Core functions *
++ * *
++\*****************************************************************************/
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++static inline uint s3c_hsmmc_build_dma_table (struct s3c_hsmmc_host *host,
++ struct mmc_data *data)
++{
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
++ uint i, j = 0, sub_num = 0;
++ dma_addr_t addr;
++ uint size, length, end;
++ int boundary, xor_bit;
++ struct scatterlist * sg = data->sg;
++
++ /* build dma table except last one */
++ for (i=0; i<(host->sg_len-1); i++) {
++ addr = sg[i].dma_address;
++ size = sg[i].length;
++ DBG("%d - addr: %08x, size: %08x\n", i, addr, size);
++
++ for (; (j<CONFIG_S3C_HSMMC_MAX_HW_SEGS*4) && size; j++) {
++ end = addr + size;
++ xor_bit = min(7+(2+8+2), fls(addr^end) -1);
++
++ DBG("%08x %08x %08x %d\n", addr, size, end, xor_bit);
++
++ host->dblk[j].dma_address = addr;
++
++ length = (end & ~((1<<xor_bit)-1)) - addr;
++ boundary = xor_bit - (2+8+2);
++ DBG("length: %x, boundary: %d\n", length, boundary);
++
++ if (length < S3C_HSMMC_MALLOC_SIZE) {
++ boundary = 0;
++
++ if ((addr+length) & (S3C_HSMMC_MALLOC_SIZE-1)) {
++ void *dest;
++
++ DBG("#########error fixing: %08x, %x\n", addr, length);
++ dest = host->sub_block[sub_num] + S3C_HSMMC_MALLOC_SIZE - length;
++ if (data->flags & MMC_DATA_WRITE) { /* write */
++ memcpy(dest, phys_to_virt(addr), length);
++ }
++
++ host->dblk[j].original = phys_to_virt(addr);
++ host->dblk[j].dma_address = dma_map_single(NULL, dest, length, host->dma_dir);
++ sub_num++;
++ }
++ }
++
++ host->dblk[j].length = length;
++ host->dblk[j].boundary = boundary;
++ DBG(" %d: %08x, %08x %x\n",
++ j, addr, length, boundary);
++ addr += length;
++ size -= length;
++ }
++ }
++
++ /* the last one */
++ host->dblk[j].dma_address = sg[i].dma_address;
++ host->dblk[j].length = sg[i].length;
++ host->dblk[j].boundary = 0x7;
++
++ return (j+1);
++
++#elif defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450)|| defined(CONFIG_CPU_S3C2416)
++ uint i;
++ struct scatterlist * sg = data->sg;
++
++ /* build dma table except the last one */
++ for (i=0; i<(host->sg_len-1); i++) {
++ host->sdma_descr_tbl[i].dma_address = sg[i].dma_address;
++ host->sdma_descr_tbl[i].length_attr = (sg[i].length << 16) | (S3C_HSMMC_ADMA_ATTR_ACT_TRAN) |
++ (S3C_HSMMC_ADMA_ATTR_VALID);
++
++ DBG(" ADMA2 descr table[%d] - addr: %08x, size+attr: %08x\n", i, host->sdma_descr_tbl[i].dma_address,
++ host->sdma_descr_tbl[i].length_attr);
++ }
++
++ /* the last one */
++ host->sdma_descr_tbl[i].dma_address = sg[i].dma_address;
++ host->sdma_descr_tbl[i].length_attr = (sg[i].length << 16) | (S3C_HSMMC_ADMA_ATTR_ACT_TRAN) |
++ (S3C_HSMMC_ADMA_ATTR_END | S3C_HSMMC_ADMA_ATTR_VALID);
++
++ DBG(" ADMA2 descr table[%d] - addr: %08x, size+attr: %08x\n", i, host->sdma_descr_tbl[i].dma_address,
++ host->sdma_descr_tbl[i].length_attr);
++
++ return (i);
++#endif
++
++}
++#endif
++
++static inline void s3c_hsmmc_prepare_data (struct s3c_hsmmc_host *host,
++ struct mmc_command *cmd)
++{
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ u8 reg8;
++#endif
++ u32 reg;
++ struct mmc_data *data = cmd->data;
++
++ if (data == NULL) {
++ reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN) | S3C_HSMMC_NIS_CMDCMP;
++ s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
++ return;
++ }
++
++ reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN) & ~S3C_HSMMC_NIS_CMDCMP;
++ s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
++
++ host->dma_dir = (data->flags & MMC_DATA_READ)
++ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++ host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
++ host->dma_dir);
++
++ reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN);
++ if (host->sg_len == 1) {
++ reg &= ~S3C_HSMMC_NIS_DMA;
++ } else {
++ reg |= S3C_HSMMC_NIS_DMA;
++ }
++ s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
++
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ reg8 = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
++ reg8 |= S3C_HSMMC_CTRL_ADMA2_32;
++ s3c_hsmmc_writeb(reg8, S3C_HSMMC_HOSTCTL);
++ DBG("HOSTCTL(0x28) = 0x%02x\n", s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL));
++#endif
++ DBG("data->flags(direction) = 0x%x\n", data->flags);
++ DBG("data->blksz: %d\n", data->blksz);
++ DBG("data->blocks: %d\n", data->blocks);
++ DBG("data->sg_len: %d\n", data->sg_len);
++
++ DBG("data->sg->addr: 0x%x\n", data->sg->dma_address);
++ DBG("data->sg->length: 0x%x\n", data->sg->length);
++
++ host->dma_blk = s3c_hsmmc_build_dma_table(host, data);
++ host->next_blk = 0;
++#else
++ DBG("data->flags(direction) = 0x%x\n", data->flags);
++ DBG("data->blksz: %d\n", data->blksz);
++ DBG("data->blocks: %d\n", data->blocks);
++ DBG("data->sg_len: %d\n", data->sg_len);
++ dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
++ host->dma_dir);
++#endif
++}
++
++static inline void s3c_hsmmc_set_transfer_mode (struct s3c_hsmmc_host *host,
++ struct mmc_data *data)
++{
++ u16 mode;
++
++ mode = S3C_HSMMC_TRNS_DMA;
++
++ if (data->stop)
++ mode |= S3C_HSMMC_TRNS_ACMD12;
++
++ if (data->blocks > 1)
++ mode |= S3C_HSMMC_TRNS_MULTI | S3C_HSMMC_TRNS_BLK_CNT_EN;
++ if (data->flags & MMC_DATA_READ)
++ mode |= S3C_HSMMC_TRNS_READ;
++
++ s3c_hsmmc_writew(mode, S3C_HSMMC_TRNMOD);
++}
++
++static inline void s3c_hsmmc_send_register (struct s3c_hsmmc_host *host)
++{
++ struct mmc_command *cmd = host->cmd;
++ struct mmc_data *data = cmd->data;
++
++ u32 cmd_val;
++
++ if (data) {
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
++ struct s3c_hsmmc_dma_blk *dblk;
++
++ dblk = &host->dblk[0];
++ s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(dblk->boundary, data->blksz),
++ S3C_HSMMC_BLKSIZE);
++ s3c_hsmmc_writel(dblk->dma_address, S3C_HSMMC_SYSAD);
++
++#elif defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(0x7, data->blksz), S3C_HSMMC_BLKSIZE);
++ s3c_hsmmc_writel(virt_to_phys(host->sdma_descr_tbl), S3C_HSMMC_ADMASYSADDR);
++ DBG("S3C_HSMMC_ADMASYSADDR(0x58) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_ADMASYSADDR));
++#endif
++
++#else
++ s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(0x7, data->blksz), S3C_HSMMC_BLKSIZE);
++ s3c_hsmmc_writel(sg_dma_address(data->sg), S3C_HSMMC_SYSAD);
++#endif
++ s3c_hsmmc_writew(data->blocks, S3C_HSMMC_BLKCNT);
++ s3c_hsmmc_set_transfer_mode(host, data);
++ }
++
++ s3c_hsmmc_writel(cmd->arg, S3C_HSMMC_ARGUMENT);
++
++ cmd_val = (cmd->opcode << 8);
++ if (cmd_val == (12<<8))
++ cmd_val |= (3 << 6);
++
++ if (cmd->flags & MMC_RSP_136) /* Long RSP */
++ cmd_val |= S3C_HSMMC_CMD_RESP_LONG;
++ else if (cmd->flags & MMC_RSP_BUSY) /* R1B */
++ cmd_val |= S3C_HSMMC_CMD_RESP_SHORT_BUSY;
++ else if (cmd->flags & MMC_RSP_PRESENT) /* Normal RSP */
++ cmd_val |= S3C_HSMMC_CMD_RESP_SHORT;
++
++ if (cmd->flags & MMC_RSP_OPCODE)
++ cmd_val |= S3C_HSMMC_CMD_INDEX;
++
++ if (cmd->flags & MMC_RSP_CRC)
++ cmd_val |= S3C_HSMMC_CMD_CRC;
++
++ if (data)
++ cmd_val |= S3C_HSMMC_CMD_DATA;
++
++ s3c_hsmmc_writew(cmd_val, S3C_HSMMC_CMDREG);
++}
++
++static inline void s3c_hsmmc_send_command (struct s3c_hsmmc_host *host,
++ struct mmc_command *cmd)
++{
++ u32 mask=1;
++ ulong timeout;
++
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ while (s3c_hsmmc_readl(S3C_HSMMC_CONTROL4) & mask);
++#endif
++
++ DBG("Sending cmd=(%d), arg=0x%x\n", cmd->opcode, cmd->arg);
++
++ /* Wait max 10 ms */
++ timeout = 10;
++
++ mask = S3C_HSMMC_CMD_INHIBIT;
++ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
++ mask |= S3C_HSMMC_DATA_INHIBIT;
++
++ while (s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & mask) {
++ printk("########### waiting controller wakeup\n");
++ if (timeout == 0) {
++ printk(KERN_ERR "%s: Controller never released "
++ "inhibit bit(s).\n", mmc_hostname(host->mmc));
++ cmd->error = -EIO;
++ tasklet_schedule(&host->finish_tasklet);
++ return;
++ }
++ timeout--;
++ mdelay(1);
++ }
++
++ mod_timer(&host->timer, jiffies + 10 * HZ);
++
++ host->cmd = cmd;
++
++ s3c_hsmmc_prepare_data(host, cmd);
++ s3c_hsmmc_send_register(host);
++}
++
++static void s3c_hsmmc_finish_data (struct s3c_hsmmc_host *host)
++{
++ struct mmc_data *data;
++ u16 blocks;
++
++ //BUG_ON(!host->data);
++ if(!host->data) return;
++
++ data = host->data;
++ host->data = NULL;
++
++ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
++ (data->flags & MMC_DATA_READ)
++ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
++
++ /*
++ * Controller doesn't count down when in single block mode.
++ */
++ if (data->blocks == 1)
++ blocks = (data->error == 0) ? 0 : 1;
++ else {
++ blocks = s3c_hsmmc_readw(S3C_HSMMC_BLKCNT);
++ }
++ data->bytes_xfered = data->blksz * (data->blocks - blocks);
++
++ if (!data->error && blocks) {
++ printk(KERN_ERR "%s: Controller signalled completion even "
++ "though there were blocks left. : %d\n",
++ mmc_hostname(host->mmc), blocks);
++ data->error = -EIO;
++ }
++ DBG("data->flags(direction) FINISHED = %d\n", data->flags);
++ DBG("data->blksz FINISHED = %d\n", data->blksz);
++ DBG("data->blocks FINISHED = %d\n", data->blocks);
++ DBG("Not FINISHED blocks = %d\n", blocks);
++ DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
++ DBG("\n");
++
++ tasklet_schedule(&host->finish_tasklet);
++}
++
++static void s3c_hsmmc_finish_command (struct s3c_hsmmc_host *host)
++{
++ int i;
++
++ //BUG_ON(host->cmd == NULL);
++ if(!host->cmd) return;
++
++ if (host->cmd->flags & MMC_RSP_PRESENT) {
++ if (host->cmd->flags & MMC_RSP_136) {
++ /* CRC is stripped so we need to do some shifting. */
++ for (i=0; i<4; i++) {
++ host->cmd->resp[i] = s3c_hsmmc_readl(S3C_HSMMC_RSPREG0+ (3-i)*4) << 8;
++ if (i != 3)
++ host->cmd->resp[i] |= s3c_hsmmc_readb(S3C_HSMMC_RSPREG0 + (3-i)*4-1);
++ DBG("cmd (%d) resp[%d] = 0x%x\n", host->cmd->opcode, i, host->cmd->resp[i]);
++ }
++ } else {
++ host->cmd->resp[0] = s3c_hsmmc_readl(S3C_HSMMC_RSPREG0);
++ DBG("cmd (%d) resp[%d] = 0x%x\n", host->cmd->opcode, 0, host->cmd->resp[0]);
++ }
++ }
++
++ host->cmd->error = 0;
++
++ DBG("Ending cmd (%d)\n", host->cmd->opcode);
++ DBG("\n");
++
++ if (host->cmd->data)
++ host->data = host->cmd->data;
++ else
++ tasklet_schedule(&host->finish_tasklet);
++
++ host->cmd = NULL;
++}
++
++static void s3c_hsmmc_tasklet_finish (unsigned long param)
++{
++ struct s3c_hsmmc_host *host;
++ unsigned long iflags;
++ struct mmc_request *mrq;
++
++ host = (struct s3c_hsmmc_host*)param;
++
++ //BUG_ON(!host->mrq);
++ if(!host->mrq) return;
++
++ spin_lock_irqsave(&host->lock, iflags);
++
++ del_timer(&host->timer);
++
++ mrq = host->mrq;
++
++ /*
++ * The controller needs a reset of internal state machines
++ * upon error conditions.
++ */
++ if ((mrq->cmd->error) || (mrq->data && (mrq->data->error)) ) {
++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_CMD);
++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_DATA);
++ }
++
++ host->mrq = NULL;
++ host->cmd = NULL;
++ host->data = NULL;
++
++ s3c_hsmmc_deactivate_led(host);
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, iflags);
++
++ mmc_request_done(host->mmc, mrq);
++}
++
++/*****************************************************************************
++ * *
++ * Interrupt handling *
++ * *
++ *****************************************************************************/
++
++static void s3c_hsmmc_cmd_irq (struct s3c_hsmmc_host *host, u32 intmask)
++{
++ if (!host->cmd) {
++ printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
++ "though no command operation was in progress.\n",
++ mmc_hostname(host->mmc), (unsigned)intmask);
++ return;
++ }
++
++ if (intmask & S3C_HSMMC_INT_TIMEOUT)
++ host->cmd->error = -ETIMEDOUT;
++ else if (intmask & (S3C_HSMMC_INT_CRC | S3C_HSMMC_INT_END_BIT | S3C_HSMMC_INT_INDEX))
++ host->cmd->error = -EILSEQ;
++
++ if (host->cmd->error)
++ tasklet_schedule(&host->finish_tasklet);
++}
++
++static void s3c_hsmmc_data_irq (struct s3c_hsmmc_host *host, u32 intmask)
++{
++ if (!host->data) {
++ /*
++ * A data end interrupt is sent together with the response
++ * for the stop command.
++ */
++ if (intmask & S3C_HSMMC_INT_DATA_END)
++ return;
++
++ printk(KERN_ERR "%s: Got data interrupt even though no "
++ "data operation was in progress.\n",
++ mmc_hostname(host->mmc));
++ return;
++ }
++
++ if (intmask & S3C_HSMMC_INT_DATA_TIMEOUT)
++ host->data->error = -ETIMEDOUT;
++ else if (intmask & (S3C_HSMMC_INT_DATA_CRC|S3C_HSMMC_INT_DATA_END_BIT))
++ host->data->error = -EILSEQ;
++
++ if (host->data->error)
++ s3c_hsmmc_finish_data(host);
++}
++
++
++/*****************************************************************************\
++ * *
++ * Interrupt handling *
++ * *
++\*****************************************************************************/
++
++/*
++ * ISR for SDI Interface IRQ
++ * Communication between driver and ISR works as follows:
++ * host->mrq points to current request
++ * host->complete_what tells the ISR when the request is considered done
++ *
++ * 1) Driver sets up host->mrq and host->complete_what
++ * 2) Driver prepares the transfer
++ * 3) Driver enables interrupts
++ * 4) Driver starts transfer
++ * 5) Driver waits for host->complete_rquest
++ * 6) ISR checks for request status (errors and success)
++ * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
++ * 7) ISR completes host->complete_request
++ * 8) ISR disables interrupts
++ * 9) Driver wakes up and takes care of the request
++ */
++
++static irqreturn_t s3c_hsmmc_irq (int irq, void *dev_id)
++{
++ irqreturn_t result = 0;
++ struct s3c_hsmmc_host *host = dev_id;
++ struct mmc_request *mrq;
++ u32 intsts;
++
++#ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
++ uint i, org_irq_sts;
++#endif
++ spin_lock(&host->lock);
++
++ mrq = host->mrq;
++
++ intsts = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTS);
++
++ /* Sometimes, hsmmc does not update its status bit immediately
++ * when it generates irqs. by scsuh.
++ */
++#ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
++ for (i=0; i<0x1000; i++) {
++ if ((intsts = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTS)))
++ break;
++ }
++#endif
++
++ if (unlikely(!intsts)) {
++ result = IRQ_NONE;
++ goto out;
++ }
++ intsts = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTS);
++#ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
++ org_irq_sts = intsts;
++#endif
++
++ DBG(PFX "Got interrupt = 0x%08x\n", intsts);
++
++ if (unlikely(intsts & S3C_HSMMC_INT_CARD_CHANGE)) {
++ u32 reg16;
++
++ if (intsts & S3C_HSMMC_INT_CARD_INSERT)
++ printk(PFX "card inserted.\n");
++ else if (intsts & S3C_HSMMC_INT_CARD_REMOVE)
++ printk(PFX "card removed.\n");
++
++ reg16 = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTSEN);
++ s3c_hsmmc_writew(reg16 & ~S3C_HSMMC_INT_CARD_CHANGE,
++ S3C_HSMMC_NORINTSTSEN);
++ s3c_hsmmc_writew(S3C_HSMMC_INT_CARD_CHANGE, S3C_HSMMC_NORINTSTS);
++ s3c_hsmmc_writew(reg16, S3C_HSMMC_NORINTSTSEN);
++
++ intsts &= ~S3C_HSMMC_INT_CARD_CHANGE;
++
++ tasklet_schedule(&host->card_tasklet);
++ goto insert;
++ }
++
++ if (likely(!(intsts & S3C_HSMMC_NIS_ERR))) {
++ s3c_hsmmc_writel(intsts, S3C_HSMMC_NORINTSTS);
++
++ if (intsts & S3C_HSMMC_NIS_CMDCMP) {
++ DBG("command done\n");
++ s3c_hsmmc_finish_command(host);
++ }
++
++ if (intsts & S3C_HSMMC_NIS_TRSCMP) {
++ DBG("transfer done\n\n");
++ s3c_hsmmc_finish_command(host);
++ s3c_hsmmc_finish_data(host);
++ intsts &= ~S3C_HSMMC_NIS_DMA;
++ }
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
++ if (intsts & S3C_HSMMC_NIS_DMA) {
++ struct s3c_hsmmc_dma_blk *dblk;
++
++ dblk = &host->dblk[host->next_blk];
++ if (dblk->original) {
++ /* on read */
++ if (host->dma_dir == DMA_FROM_DEVICE) {
++ memcpy(dblk->original, phys_to_virt(dblk->dma_address), dblk->length);
++ }
++ dma_unmap_single(NULL, dblk->dma_address, dblk->length, host->dma_dir);
++ dblk->original = 0;
++ }
++
++ host->next_blk++;
++ dblk = &host->dblk[host->next_blk];
++
++ if (host->next_blk == (host->dma_blk-1)) {
++ u32 reg;
++
++ reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN);
++ reg &= ~S3C_HSMMC_NIS_DMA;
++ s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
++ }
++
++ /* We do not handle DMA boundaries, so set it to max (512 KiB) */
++ s3c_hsmmc_writew((dblk->boundary<<12 | 0x200), S3C_HSMMC_BLKSIZE);
++ s3c_hsmmc_writel(dblk->dma_address, S3C_HSMMC_SYSAD);
++ }
++#endif
++#endif
++ } else {
++ DBG("command FAIL : found bad irq [0x%8x]\n", intsts);
++ DBG("\n");
++ if (intsts & S3C_HSMMC_INT_CMD_MASK) {
++ s3c_hsmmc_writel((intsts & S3C_HSMMC_INT_CMD_MASK)|S3C_HSMMC_INT_RESPONSE, S3C_HSMMC_NORINTSTS);
++ s3c_hsmmc_cmd_irq(host, intsts & S3C_HSMMC_INT_CMD_MASK);
++ }
++
++ if (intsts & S3C_HSMMC_INT_DATA_MASK) {
++ s3c_hsmmc_writel(intsts & S3C_HSMMC_INT_DATA_MASK, S3C_HSMMC_NORINTSTS);
++ s3c_hsmmc_finish_command(host);
++ s3c_hsmmc_data_irq(host, intsts & S3C_HSMMC_INT_DATA_MASK);
++ }
++
++ intsts &= ~(S3C_HSMMC_INT_CMD_MASK | S3C_HSMMC_INT_DATA_MASK);
++ }
++
++ /* XXX: fix later by scsuh */
++#if 0
++ if (intsts & S3C_HSMMC_INT_BUS_POWER) {
++ printk(KERN_ERR "%s: Card is consuming too much power!\n",
++ mmc_hostname(host->mmc));
++ s3c_hsmmc_writel(S3C_HSMMC_INT_BUS_POWER, S3C_HSMMC_NORINTSTS);
++ }
++
++ intsts &= S3C_HSMMC_INT_BUS_POWER;
++
++ if (intsts) {
++ printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
++ mmc_hostname(host->mmc), intsts);
++
++ s3c_hsmmc_writel(intsts, S3C_HSMMC_NORINTSTS);
++ }
++#endif
++
++#ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
++ for (i=0; i<0x1000; i++) {
++ if (org_irq_sts != s3c_hsmmc_readl(S3C_HSMMC_NORINTSTS))
++ break;
++ }
++#endif
++
++insert:
++ result = IRQ_HANDLED;
++ mmiowb();
++
++out:
++ spin_unlock(&host->lock);
++
++ return result;
++}
++
++static irqreturn_t s3c_hsmmc_irq_cd (int irq, void *dev_id)
++{
++ struct s3c_hsmmc_host *host = dev_id;
++ int ext_CD_int = 0;
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ ext_CD_int = readl(S3C2410_GPFDAT);
++ ext_CD_int &= 0x2; /* GPF1 */
++#elif defined(CONFIG_CPU_S3C6410)
++ ext_CD_int = readl(S3C_GPNDAT);
++ ext_CD_int &= 0x2000; /* GPN13 */
++#endif
++
++ if(ext_CD_int && card_detect) {
++ printk("s3c-hsmmc channel-0(EXT): card removed.\n");
++ set_irq_type(host->irq_cd, IRQT_FALLING);
++ card_detect = 0;
++ }
++ else if(!ext_CD_int && !card_detect) {
++ printk("s3c-hsmmc channel-0(EXT): card inserted.\n");
++ set_irq_type(host->irq_cd, IRQT_RISING);
++ card_detect = 1;
++ }
++ else
++ return IRQ_HANDLED;
++
++
++ tasklet_schedule(&host->card_tasklet);
++ mmiowb();
++
++ spin_unlock(&host->lock);
++
++ return IRQ_HANDLED;
++}
++
++static void s3c_hsmmc_check_status (unsigned long data)
++{
++ struct s3c_hsmmc_host *host = (struct s3c_hsmmc_host *)data;
++
++ s3c_hsmmc_irq(0, host);
++}
++
++static void s3c_hsmmc_request (struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct s3c_hsmmc_host *host = mmc_priv(mmc);
++ unsigned long flags;
++
++ DBG("hsmmc request: [CMD] opcode:%d arg:0x%08x flags:0x%02x retries:%u\n",
++ mrq->cmd->opcode, mrq->cmd->arg, mrq->cmd->flags, mrq->cmd->retries);
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ WARN_ON(host->mrq != NULL);
++
++ s3c_hsmmc_activate_led(host);
++
++ host->mrq = mrq;
++
++ if ((s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT) || card_detect) {
++ s3c_hsmmc_send_command(host, mrq->cmd);
++ } else {
++ host->mrq->cmd->error = -ENOMEDIUM;
++ tasklet_schedule(&host->finish_tasklet);
++ }
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
++/* return 0: OK
++ * return -1: error
++ */
++static int s3c_set_bus_width (struct s3c_hsmmc_host *host, uint width)
++{
++ u8 reg;
++
++ reg = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
++
++ switch (width) {
++ case MMC_BUS_WIDTH_1:
++ reg &= ~(S3C_HSMMC_CTRL_4BIT | S3C_HSMMC_CTRL_8BIT);
++ DBG("bus width: 1 bit\n");
++ break;
++
++ case MMC_BUS_WIDTH_4:
++ DBG("bus width: 4 bit\n");
++ reg &= ~(S3C_HSMMC_CTRL_8BIT);
++ reg |= S3C_HSMMC_CTRL_4BIT;
++ break;
++
++ case MMC_BUS_WIDTH_8:
++ reg |= S3C_HSMMC_CTRL_8BIT;
++ DBG("bus width: 8 bit\n");
++ break;
++
++ default:
++ DBG("bus width: Error\n");
++ return -1;
++ }
++
++ s3c_hsmmc_writeb(reg, S3C_HSMMC_HOSTCTL);
++
++ DBG("HOSTCTL(0x28) = 0x%02x\n", s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL));
++
++ return 0;
++}
++
++static void s3c_hsmmc_set_clock (struct s3c_hsmmc_host *host, ulong clock)
++{
++ struct s3c_hsmmc_cfg *cfg = host->plat_data;
++ int cardtype = 0;
++ u32 val = 0, tmp_clk = 0, sel_clk = 0, i, j;
++ u16 div = (u16)-1;
++ ulong timeout;
++ u8 ctrl;
++
++ if(host->mmc->card != NULL)
++ cardtype = host->mmc->card->type;
++
++ /* if we already set, just out. */
++ if (clock == host->clock) {
++ printk("%p:host->clock0 : %d Hz\n", host->base, host->clock);
++ return;
++ }
++
++ /* before setting clock, clkcon must be disabled. */
++ s3c_hsmmc_writew(0, S3C_HSMMC_CLKCON);
++
++ s3c_hsmmc_writeb(S3C_HSMMC_TIMEOUT_MAX, S3C_HSMMC_TIMEOUTCON);
++
++ /* change the edge type according to frequency */
++ ctrl = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
++
++ if (cfg->highspeed)
++ ctrl |= S3C_HSMMC_CTRL_HIGHSPEED;
++ else
++ ctrl &= ~S3C_HSMMC_CTRL_HIGHSPEED;
++
++ s3c_hsmmc_writeb(ctrl, S3C_HSMMC_HOSTCTL);
++
++ if (clock == 0) {
++ DBG(" In case of 0 Hz of clock, I'm afraid DO NOTHING ..\n");
++ return;
++ }
++
++ /* calculate optimal clock. by scsuh */
++ DBG("Requested clock is %ld Hz\n", clock);
++
++ for (i = 0; i < NUM_OF_HSMMC_CLKSOURCES; i++) {
++ if ((tmp_clk = clk_get_rate(host->clk[i])) <= clock) {
++ if (tmp_clk >= val) {
++ val = tmp_clk;
++ div = 0;
++ sel_clk = i;
++ }
++ }
++
++ for (j = 0x1; j <= 0x80; j <<= 1) {
++ tmp_clk = clk_get_rate(host->clk[i]) / (j << 1);
++ if ((val < tmp_clk) && (tmp_clk <= clock)) {
++ val = tmp_clk;
++ div = j;
++ sel_clk = i;
++ break;
++ }
++ }
++ DBG(" tmp_val[%d]: %d\n", sel_clk, val);
++ }
++
++ DBG("Optimal clock : %d Hz, div: 0x%x, SelBaseclk_src: %s(%d)\n", val, div, cfg->clocks[sel_clk].name, cfg->clocks[sel_clk].src);
++
++ /* CONTROL2 */
++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl2 | (cfg->clocks[sel_clk].src << 4), S3C_HSMMC_CONTROL2);
++
++ /* CONTROL3 */
++ if (clock > 25000000)
++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl3[SPEED_HIGH], S3C_HSMMC_CONTROL3);
++ else
++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl3[SPEED_NORMAL], S3C_HSMMC_CONTROL3);
++
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl4 << 16, S3C_HSMMC_CONTROL4);
++#endif
++
++ s3c_hsmmc_writew(((div<<8) | S3C_HSMMC_CLOCK_INT_EN), S3C_HSMMC_CLKCON);
++
++ timeout = 10;
++ while (!((val = s3c_hsmmc_readw(S3C_HSMMC_CLKCON))
++ & S3C_HSMMC_CLOCK_INT_STABLE)) {
++ if (!timeout) {
++ printk("HSMMC: Error in INTERNAL clock stabilization: %08x\n", val);
++ return;
++ }
++ timeout--;
++ mdelay(1);
++ }
++
++ s3c_hsmmc_writew(val | S3C_HSMMC_CLOCK_CARD_EN, S3C_HSMMC_CLKCON);
++
++//out:
++// host->clock = clock;
++// printk("%p: host->clock1 : %d\n", host->base, host->clock);
++}
++
++
++static void s3c_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++ struct s3c_hsmmc_host *host = mmc_priv(mmc);
++
++ unsigned long iflags;
++
++ spin_lock_irqsave(&host->lock, iflags);
++
++ /*
++ * Reset the chip on each power off.
++ * Should clear out any weird states.
++ */
++ if (ios->power_mode == MMC_POWER_OFF) {
++ s3c_hsmmc_writew(0, S3C_HSMMC_NORINTSIGEN);
++ s3c_hsmmc_ios_init(host);
++ }
++
++ if (host->plat_data->enabled)
++ hsmmc_set_gpio(host->plat_data->hwport, host->plat_data->bus_width);
++
++ DBG("\nios->clock: %d Hz\n", ios->clock);
++ s3c_hsmmc_set_clock(host, ios->clock);
++
++ DBG("\nios->bus_width: %d\n", ios->bus_width);
++ s3c_set_bus_width(host, ios->bus_width);
++
++ DBG("S3C_HSMMC_CONTROL2(0x80) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_CONTROL2));
++ DBG("S3C_HSMMC_CONTROL3(0x84) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_CONTROL3));
++ DBG("S3C_HSMMC_CLKCON (0x2c) = 0x%04x\n", s3c_hsmmc_readw(S3C_HSMMC_CLKCON));
++
++ if (ios->power_mode == MMC_POWER_OFF)
++ s3c_hsmmc_writeb(S3C_HSMMC_POWER_OFF, S3C_HSMMC_PWRCON);
++ else
++ s3c_hsmmc_writeb(S3C_HSMMC_POWER_ON_ALL, S3C_HSMMC_PWRCON);
++
++ udelay(1000);
++ spin_unlock_irqrestore(&host->lock, iflags);
++}
++
++static struct mmc_host_ops s3c_hsmmc_ops = {
++ .request = s3c_hsmmc_request,
++ .set_ios = s3c_hsmmc_set_ios,
++};
++
++static int s3c_hsmmc_probe (struct platform_device *pdev)
++{
++ struct mmc_host *mmc;
++ struct s3c_hsmmc_host *host;
++ struct s3c_hsmmc_cfg *plat_data;
++ uint i;
++ int ret;
++
++ mmc = mmc_alloc_host(sizeof(struct s3c_hsmmc_host), &pdev->dev);
++
++ if (mmc==NULL) {
++ ret = -ENOMEM;
++ printk("Failed to get mmc_alloc_host.\n");
++ return ret;
++ }
++
++ plat_data = s3c_hsmmc_get_platdata(&pdev->dev);
++
++ host = mmc_priv(mmc);
++
++ host->mmc = mmc;
++
++ host->plat_data = plat_data;
++
++ host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!host->mem) {
++ printk("Failed to get io memory region resouce.\n");
++ ret = -ENOENT;
++ goto probe_free_host;
++ }
++
++ host->mem = request_mem_region(host->mem->start,
++ RESSIZE(host->mem), pdev->name);
++ if (!host->mem) {
++ printk("Failed to request io memory region.\n");
++ ret = -ENOENT;
++ goto probe_free_host;
++ }
++
++ host->base = ioremap(host->mem->start, (host->mem->end - host->mem->start)+1);
++ if (host->base == NULL) {
++ printk(KERN_ERR "Failed to remap register block\n");
++ return -ENOMEM;
++ }
++
++ host->irq = platform_get_irq(pdev, 0);
++ if (host->irq == 0) {
++ printk("Failed to get interrupt resouce.\n");
++ ret = -EINVAL;
++ goto untasklet;
++ }
++
++ /* To detect a card inserted on channel 0, an external interrupt is used. */
++ if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) {
++ host->irq_cd = platform_get_irq(pdev, 1);
++ if (host->irq_cd == 0) {
++ printk("Failed to get interrupt resouce.\n");
++ ret = -EINVAL;
++ goto untasklet;
++ }
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ set_irq_type(host->irq_cd, IRQT_BOTHEDGE);
++#elif defined(CONFIG_CPU_S3C6410)
++ set_irq_type(host->irq_cd, IRQT_LOW);
++#endif
++ }
++
++ host->flags |= S3C_HSMMC_USE_DMA;
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
++ for (i=0; i<S3C_HSMMC_MAX_SUB_BUF; i++)
++ host->sub_block[i] = kmalloc(S3C_HSMMC_MALLOC_SIZE, GFP_KERNEL);
++#endif
++#endif
++
++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL);
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ clk_enable(clk_get(&pdev->dev, "sclk_48m"));
++#endif
++
++ /* register some clock sources if exist */
++ for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
++ host->clk[i] = clk_get(&pdev->dev, plat_data->clocks[i].name);
++ if (IS_ERR(host->clk[i])) {
++ ret = PTR_ERR(host->clk[i]);
++ host->clk[i] = ERR_PTR(-ENOENT);
++ }
++
++ if (clk_enable(host->clk[i])) {
++ host->clk[i] = ERR_PTR(-ENOENT);
++ }
++
++ if (!IS_ERR(host->clk[i])) {
++ DBG("MMC clock source[%d], %s is %ld Hz\n",i, plat_data->clocks[i].name, clk_get_rate(host->clk[i]));
++ }
++ }
++
++ mmc->ops = &s3c_hsmmc_ops;
++ mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
++ mmc->f_min = 400 * 1000; /* at least 400kHz */
++
++ /* you must make sure that our hsmmc block can support
++ * up to 52MHz. by scsuh
++ */
++ mmc->f_max = 100 * MHZ;
++ mmc->caps = plat_data->host_caps;
++ DBG("mmc->caps: %08x\n", mmc->caps);
++
++ spin_lock_init(&host->lock);
++
++ /*
++ * Maximum number of segments. Hardware cannot do scatter lists.
++ * XXX: must modify later. by scsuh
++ */
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++ mmc->max_hw_segs = CONFIG_S3C_HSMMC_MAX_HW_SEGS;
++ mmc->max_phys_segs = CONFIG_S3C_HSMMC_MAX_HW_SEGS;
++#else
++ mmc->max_hw_segs = 1;
++#endif
++
++ /*
++ * Maximum number of sectors in one transfer. Limited by DMA boundary
++ * size (512KiB), which means (512 KiB/512=) 1024 entries.
++ */
++ //mmc->max_sectors = 128; /* 65535/512=128 */
++
++ /*
++ * Maximum segment size. Could be one segment with the maximum number
++ * of sectors.
++ */
++ mmc->max_blk_size = 512;
++ //mmc->max_seg_size = mmc->max_sectors * mmc->max_blk_size;
++ mmc->max_seg_size = 128 * mmc->max_blk_size;
++
++ //mmc->max_blk_count = mmc->max_sectors;
++ mmc->max_blk_count = 128;
++ mmc->max_req_size = mmc->max_seg_size;
++
++
++ init_timer(&host->timer);
++ host->timer.data = (unsigned long)host;
++ host->timer.function = s3c_hsmmc_check_status;
++ host->timer.expires = jiffies + HZ;
++
++ /*
++ * Init tasklets.
++ */
++ tasklet_init(&host->card_tasklet,
++ s3c_hsmmc_tasklet_card, (unsigned long)host);
++ tasklet_init(&host->finish_tasklet,
++ s3c_hsmmc_tasklet_finish, (unsigned long)host);
++
++ ret = request_irq(host->irq, s3c_hsmmc_irq, 0, DRIVER_NAME, host);
++ if (ret)
++ goto untasklet;
++
++ if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) {
++ ret = request_irq(host->irq_cd, s3c_hsmmc_irq_cd, 0, DRIVER_NAME, host);
++ if (ret)
++ goto untasklet;
++ }
++
++ s3c_hsmmc_ios_init(host);
++
++ mmc_add_host(mmc);
++
++#if defined(CONFIG_PM)
++ global_host[plat_data->hwport] = host;
++#endif
++
++ printk(KERN_INFO "[s3c_hsmmc_probe]: %s.%d: at 0x%p with irq %d. clk src:",
++ pdev->name, pdev->id, host->base, host->irq);
++
++ for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
++ if (!IS_ERR(host->clk[i]))
++ printk(" %s", host->clk[i]->name);
++ }
++ printk("\n");
++
++ return 0;
++
++untasklet:
++ tasklet_kill(&host->card_tasklet);
++ tasklet_kill(&host->finish_tasklet);
++
++ for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
++ if (host->clk[i] != ERR_PTR(-ENOENT)) {
++ clk_disable(host->clk[i]);
++ clk_put(host->clk[i]);
++ }
++ }
++
++probe_free_host:
++ mmc_free_host(mmc);
++
++ return ret;
++}
++
++static int s3c_hsmmc_remove(struct platform_device *dev)
++{
++ struct mmc_host *mmc = platform_get_drvdata(dev);
++ struct s3c_hsmmc_host *host = mmc_priv(mmc);
++ int i;
++
++ mmc = host->mmc;
++
++ mmc_remove_host(mmc);
++
++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL);
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ clk_disable(clk_get(&dev->dev, "sclk_48m"));
++#endif
++
++ for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
++ clk_disable(host->clk[i]);
++ clk_put(host->clk[i]);
++ }
++
++ free_irq(host->irq, host);
++
++ del_timer_sync(&host->timer);
++
++ tasklet_kill(&host->card_tasklet);
++ tasklet_kill(&host->finish_tasklet);
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
++ kfree(host->sub_block);
++#endif
++#endif
++ mmc_free_host(mmc);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
++{
++// struct mmc_card *card;
++ struct s3c_hsmmc_host *s3c_host = global_host[pdev->id];
++ struct mmc_host *host = s3c_host->mmc;
++
++#if 0
++ /*
++ * Fix me later by jsgood
++ */
++ list_for_each_entry(card, &host->cards, node) {
++ if (card->state & MMC_STATE_PRESENT)
++ card->state &= ~MMC_STATE_PRESENT;
++ }
++#endif
++ mmc_suspend_host(host, state);
++
++ return 0;
++}
++
++static int s3c_hsmmc_resume(struct platform_device *pdev)
++{
++ struct s3c_hsmmc_host *s3c_host = global_host[pdev->id];
++ struct mmc_host *host = s3c_host->mmc;
++
++ s3c_hsmmc_ios_init(s3c_host);
++ mmc_resume_host(host);
++
++ return 0;
++}
++#else
++#define s3c_hsmmc_suspend NULL
++#define s3c_hsmmc_resume NULL
++#endif
++
++
++static struct platform_driver s3c_hsmmc_driver =
++{
++ .probe = s3c_hsmmc_probe,
++ .remove = s3c_hsmmc_remove,
++ .suspend = s3c_hsmmc_suspend,
++ .resume = s3c_hsmmc_resume,
++ .driver = {
++ .name = "s3c-hsmmc",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init s3c_hsmmc_drv_init(void)
++{
++ return platform_driver_register(&s3c_hsmmc_driver);
++}
++
++static void __exit s3c_hsmmc_drv_exit(void)
++{
++ platform_driver_unregister(&s3c_hsmmc_driver);
++}
++
++
++module_init(s3c_hsmmc_drv_init);
++module_exit(s3c_hsmmc_drv_exit);
++
++
++MODULE_DESCRIPTION("S3C SD HOST I/F 1.0 and 2.0 Driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/mmc/host/s3c-hsmmc.h b/drivers/mmc/host/s3c-hsmmc.h
+new file mode 100644
+index 0000000..3b3d3e4
+--- /dev/null
++++ b/drivers/mmc/host/s3c-hsmmc.h
+@@ -0,0 +1,101 @@
++/*
++ * linux/drivers/mmc/s3c-hsmmc.h - Samsung S3C HS-MMC Interface driver
++ *
++ * $Id: s3c-hsmmc.h,v 1.1 2008/03/03 00:40:28 ihlee215 Exp $
++ *
++ * Copyright (C) 2004 Thomas Kleffel, All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef MHZ
++#define MHZ (1000*1000)
++#endif
++
++#define s3c_hsmmc_readl(x) readl((host->base)+(x))
++#define s3c_hsmmc_readw(x) readw((host->base)+(x))
++#define s3c_hsmmc_readb(x) readb((host->base)+(x))
++
++#define s3c_hsmmc_writel(v,x) writel((v),(host->base)+(x))
++#define s3c_hsmmc_writew(v,x) writew((v),(host->base)+(x))
++#define s3c_hsmmc_writeb(v,x) writeb((v),(host->base)+(x))
++
++#define S3C_HSMMC_CLOCK_ON 1
++#define S3C_HSMMC_CLOCK_OFF 0
++
++#define SPEED_NORMAL 0
++#define SPEED_HIGH 1
++
++
++#ifndef CONFIG_S3C_HSMMC_MAX_HW_SEGS
++#define CONFIG_S3C_HSMMC_MAX_HW_SEGS 32
++#endif
++
++
++/* For SDMA */
++struct s3c_hsmmc_dma_blk {
++ dma_addr_t dma_address; /* dma address */
++ uint length; /* length */
++ uint boundary; /* Host DMA Buffer Boundary */
++ void *original;
++};
++
++/* For ADMA2 */
++struct s3c_hsmmc_adma_descr {
++ volatile u32 length_attr; /* length + attribute */
++ volatile u32 dma_address; /* dma address */
++} __packed;
++
++
++struct s3c_hsmmc_host {
++ void __iomem *base;
++ struct mmc_request *mrq;
++ struct mmc_command *cmd;
++ struct mmc_data *data;
++ struct mmc_host *mmc;
++ struct clk *clk[3];
++ struct resource *mem;
++
++ struct timer_list timer;
++
++ struct s3c_hsmmc_cfg *plat_data;
++
++ int irq;
++ int irq_cd;
++
++ spinlock_t lock;
++
++ struct tasklet_struct card_tasklet; /* Tasklet structures */
++ struct tasklet_struct finish_tasklet;
++
++ unsigned int clock; /* Current clock (MHz) */
++ unsigned int ctrl2;
++ unsigned int ctrl3[3]; /* 0: normal, 1: high */
++ unsigned int ctrl4;
++
++#define S3C_HSMMC_USE_DMA (1<<0)
++ int flags; /* Host attributes */
++
++ uint dma_dir;
++
++#ifdef CONFIG_HSMMC_SCATTERGATHER
++ uint sg_len; /* size of scatter list */
++
++ /* For SDMA */
++ uint dma_blk; /* total dmablk number */
++ uint next_blk; /* next block to send */
++ struct s3c_hsmmc_dma_blk dblk[CONFIG_S3C_HSMMC_MAX_HW_SEGS*4];
++
++ /* when pseudo algo cannot deal with sglist */
++#define S3C_HSMMC_MALLOC_SIZE PAGE_SIZE
++#define S3C_HSMMC_MAX_SUB_BUF CONFIG_S3C_HSMMC_MAX_HW_SEGS
++ void *sub_block[S3C_HSMMC_MAX_SUB_BUF];
++
++ /* For ADMA2 */
++ struct s3c_hsmmc_adma_descr sdma_descr_tbl[CONFIG_S3C_HSMMC_MAX_HW_SEGS];
++#endif
++
++};
++
+diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
+new file mode 100644
+index 0000000..45e603d
+--- /dev/null
++++ b/drivers/mmc/host/s3cmci.c
+@@ -0,0 +1,893 @@
++/*
++ * linux/drivers/mmc/s3cmci.c - Samsung S3C SDI Interface driver
++ *
++ * $Id: s3cmci.c,v 1.1 2008/03/03 00:40:28 ihlee215 Exp $
++ *
++ * Copyright (C) 2004 Thomas Kleffel, All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/mmc.h>
++#include <linux/err.h>
++
++#include <asm/dma.h>
++#include <asm/dma-mapping.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/scatterlist.h>
++#include <asm/sizes.h>
++#include <asm/mach/mmc.h>
++
++#include <asm/arch/registers.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/dma.h>
++
++#ifdef CONFIG_S3CMCI_DEBUG
++#define DBG(x...) printk(x)
++#else
++#define DBG(x...) do { } while (0)
++#endif
++
++#include "s3cmci.h"
++
++#ifndef MHZ
++#define MHZ (1000*1000)
++#endif
++
++#define DRIVER_NAME "s3c-sdi"
++#define PFX DRIVER_NAME ": "
++
++#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
++
++typedef enum {
++ DMAP_READ,
++ DMAP_WRITE,
++} eDMAPurpose_t;
++
++#ifdef CONFIG_S3CMCI_DEBUG
++uint cmd_rec[40];
++uint cmd_idx = 0;
++#endif
++
++static struct s3c_dma_client s3c_sdi_dma_client = {
++ .name = "s3c-sdi-dma",
++};
++
++/*
++ * ISR for SDI Interface IRQ
++ * Communication between driver and ISR works as follows:
++ * host->mrq points to current request
++ * host->complete_what tells the ISR when the request is considered done
++ * COMPLETION_CMDSENT when the command was sent
++ * COMPLETION_RSPFIN when a response was received
++ * COMPLETION_XFERFINISH when the data transfer is finished
++ * COMPLETION_XFERFINISH_RSPFIN both of the above.
++ * host->complete_request is the completion-object the driver waits for
++ *
++ * 1) Driver sets up host->mrq and host->complete_what
++ * 2) Driver prepares the transfer
++ * 3) Driver enables interrupts
++ * 4) Driver starts transfer
++ * 5) Driver waits for host->complete_rquest
++ * 6) ISR checks for request status (errors and success)
++ * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
++ * 7) ISR completes host->complete_request
++ * 8) ISR disables interrupts
++ * 9) Driver wakes up and takes care of the request
++ */
++
++static irqreturn_t s3c_sdi_irq(int irq, void *dev_id, struct pt_regs *regs)
++{
++ struct s3c_sdi_host *host;
++ struct mmc_request *mrq;
++ u32 sdi_csta, sdi_dsta, sdi_fsta;
++ u32 sdi_cclear, sdi_dclear;
++ unsigned long iflags;
++
++ host = (struct s3c_sdi_host *)dev_id;
++
++ /* Check for things not supposed to happen */
++ if (!host)
++ return IRQ_HANDLED;
++
++ spin_lock_irqsave( &host->complete_lock, iflags);
++
++ if ( host->complete_what==COMPLETION_NONE ) {
++ goto clear_imask;
++ }
++
++ if (!host->mrq) {
++ goto clear_imask;
++ }
++
++ mrq = host->mrq;
++
++ sdi_csta = readl(host->base + S3C_SDICSTA);
++ sdi_dsta = readl(host->base + S3C_SDIDSTA);
++ sdi_fsta = readl(host->base + S3C_SDIFSTA);
++ sdi_cclear = 0;
++ sdi_dclear = 0;
++
++ if (sdi_csta & S3C_SDICSTA_CMDTOUT) {
++ mrq->cmd->error = MMC_ERR_TIMEOUT;
++ DBG("cmd timeout\n");
++ goto transfer_closed;
++ }
++
++ if (sdi_csta & S3C_SDICSTA_CMDSENT) {
++ if (host->complete_what == COMPLETION_CMDSENT) {
++ mrq->cmd->error = MMC_ERR_NONE;
++ goto transfer_closed;
++ }
++
++ sdi_cclear |= S3C_SDICSTA_CMDSENT;
++ }
++
++ if (sdi_csta & S3C_SDICSTA_CRCFAIL) {
++ if (mrq->cmd->flags & MMC_RSP_CRC) {
++ DBG("cmd badcrc\n");
++ mrq->cmd->error = MMC_ERR_BADCRC;
++ goto transfer_closed;
++ }
++
++ sdi_cclear |= S3C_SDICSTA_CRCFAIL;
++ }
++
++ if (sdi_csta & S3C_SDICSTA_RSPFIN) {
++ if (host->complete_what == COMPLETION_RSPFIN) {
++ mrq->cmd->error = MMC_ERR_NONE;
++ goto transfer_closed;
++ }
++
++ if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) {
++ mrq->cmd->error = MMC_ERR_NONE;
++ host->complete_what = COMPLETION_XFERFINISH;
++ }
++
++ sdi_cclear |= S3C_SDICSTA_RSPFIN;
++ }
++
++ if (sdi_fsta & S3C_SDIFSTA_FIFOFAIL) {
++ printk(PFX "Unchartererd Waters ....\n");
++ mrq->cmd->error = MMC_ERR_NONE;
++ mrq->data->error = MMC_ERR_FIFO;
++ goto transfer_closed;
++ }
++
++ if (sdi_dsta & S3C_SDIDSTA_RXCRCFAIL) {
++ mrq->cmd->error = MMC_ERR_NONE;
++ mrq->data->error = MMC_ERR_BADCRC;
++ printk(PFX "crc error - RXCRCFAIL\n");
++ goto transfer_closed;
++ }
++
++ if (sdi_dsta & S3C_SDIDSTA_CRCFAIL) {
++ mrq->cmd->error = MMC_ERR_NONE;
++ mrq->data->error = MMC_ERR_BADCRC;
++ printk(PFX "crc error - TXCRCFAIL\n");
++ goto transfer_closed;
++ }
++
++ if (sdi_dsta & S3C_SDIDSTA_DATATIMEOUT) {
++ mrq->cmd->error = MMC_ERR_NONE;
++ mrq->data->error = MMC_ERR_TIMEOUT;
++#ifdef CONFIG_S3CMCI_DEBUG
++ printk(PFX "timeout(%d) - DSTA: %08x\n", mrq->cmd->opcode, readl(host->base + S3C_SDIDSTA));
++ {
++ int i;
++ printk("cmd_idx: %d\n", cmd_idx);
++ for (i=0; i<40; i++) {
++ printk("%02d: %d\n", i, cmd_rec[i]);
++ }
++ }
++#endif
++ goto transfer_closed;
++ }
++
++ if (sdi_dsta & S3C_SDIDSTA_XFERFINISH) {
++ if (host->complete_what == COMPLETION_XFERFINISH) {
++ mrq->cmd->error = MMC_ERR_NONE;
++ mrq->data->error = MMC_ERR_NONE;
++ goto transfer_closed;
++ }
++
++ if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) {
++ mrq->data->error = MMC_ERR_NONE;
++ host->complete_what = COMPLETION_RSPFIN;
++ }
++
++ sdi_dclear |= S3C_SDIDSTA_XFERFINISH;
++ }
++
++ writel(sdi_cclear, host->base + S3C_SDICSTA);
++ writel(sdi_dclear, host->base + S3C_SDIDSTA);
++
++ spin_unlock_irqrestore( &host->complete_lock, iflags);
++ DBG(PFX "IRQ still waiting.\n");
++ return IRQ_HANDLED;
++
++
++transfer_closed:
++ host->complete_what = COMPLETION_NONE;
++ complete(&host->complete_request);
++ writel(0, host->base + S3C_SDIIMSK);
++ spin_unlock_irqrestore( &host->complete_lock, iflags);
++ DBG(PFX "IRQ transfer closed.\n");
++ return IRQ_HANDLED;
++
++clear_imask:
++ writel(0, host->base + S3C_SDIIMSK);
++ spin_unlock_irqrestore( &host->complete_lock, iflags);
++ DBG(PFX "IRQ clear imask.\n");
++ return IRQ_HANDLED;
++}
++
++static void s3c_sdi_check_status(unsigned long data)
++{
++ struct s3c_sdi_host *host = (struct s3c_sdi_host *)data;
++
++ s3c_sdi_irq(0, host, NULL);
++}
++
++/*
++ * ISR for the CardDetect Pin
++ */
++static irqreturn_t s3c_sdi_irq_cd(int irq, void *dev_id, struct pt_regs *regs)
++{
++ struct s3c_sdi_host *host = (struct s3c_sdi_host *)dev_id;
++ mmc_detect_change(host->mmc, 0);
++
++ DBG(PFX "mmc device mode is changed.\n");
++ return IRQ_HANDLED;
++}
++
++#ifdef CONFIG_ARCH_MDIRAC3
++void s3c_sdi_dma_done_callback (
++ s3c_dma_subchan_t *dma_ch,
++ void *buf_id,
++ int size,
++ s3c_dma_buffresult_t result
++#else
++void s3c_sdi_dma_done_callback (
++ s3c_dma_chan_t *dma_ch,
++ void *buf_id,
++ int size,
++ s3c_dma_buffresult_t result
++)
++#endif
++{ unsigned long iflags;
++ uint sdi_dcnt;
++ struct s3c_sdi_host *host = (struct s3c_sdi_host *)buf_id;
++
++ spin_lock_irqsave( &host->complete_lock, iflags);
++
++ if (!host->mrq)
++ goto out;
++ if (!host->mrq->data)
++ goto out;
++
++ sdi_dcnt = readl(host->base + S3C_SDIDCNT);
++
++ if (result!=S3C_RES_OK)
++ goto fail_request;
++
++
++ if (host->mrq->data->flags & MMC_DATA_READ) {
++ if (sdi_dcnt > 0)
++ goto fail_request;
++ }
++
++out:
++ complete(&host->complete_dma);
++ spin_unlock_irqrestore( &host->complete_lock, iflags);
++ return;
++
++
++fail_request:
++ host->mrq->data->error = MMC_ERR_FAILED;
++ host->complete_what = COMPLETION_NONE;
++ complete(&host->complete_dma);
++ complete(&host->complete_request);
++ writel(0, host->base + S3C_SDIIMSK);
++ DBG(PFX "dma fail\n");
++ goto out;
++
++}
++
++#ifdef CONFIG_ARCH_MDIRAC3
++void s3c_sdi_dma_setup(struct s3c_sdi_host *host, eDMAPurpose_t purpose)
++{
++ int flowctrl,dest_per,src_per;
++
++ switch(purpose) {
++ case DMAP_READ:
++ dest_per = 0;
++ src_per = S3C_DMA3_SDMMC;
++ flowctrl=S3C_DMA_PER2MEM;
++ break;
++
++ case DMAP_WRITE:
++ dest_per= S3C_DMA3_SDMMC;
++ src_per = 0;
++ flowctrl=S3C_DMA_MEM2PER;
++ break;
++
++ default:
++ //add something for other type of transfers
++ // printk("coming to default statement dma transfer\n");
++ break;
++ }
++
++ s3c_dma_devconfig(host->dma,host->subchannel,flowctrl,src_per,dest_per, host->mem->start + S3C_SDIDAT);
++ s3c_dma_config(host->dma,host->subchannel, 4,4);
++ s3c_dma_set_buffdone_fn(host->dma,host->subchannel, s3c_sdi_dma_done_callback);
++ s3c_dma_setflags(host->dma,host->subchannel, S3C_DMAF_AUTOSTART);
++}
++#else
++void s3c_sdi_dma_setup(struct s3c_sdi_host *host, eDMAPurpose_t purpose)
++{
++ s3c_dmasrc_t source = 0;
++
++ switch(purpose) {
++ case DMAP_READ:
++ source = S3C_DMASRC_HW;
++ break;
++
++ case DMAP_WRITE:
++ source=S3C_DMASRC_MEM;
++ break;
++ }
++
++ s3c_dma_devconfig(host->dma, source, 3, host->mem->start + S3C_SDIDAT);
++ s3c_dma_config(host->dma, 4, 0, S3C_REQSEL_SDMMC | (1<<0));
++ s3c_dma_set_buffdone_fn(host->dma, s3c_sdi_dma_done_callback);
++ s3c_dma_setflags(host->dma, S3C_DMAF_AUTOSTART);
++}
++#endif
++
++#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
++
++static void s3c_sdi_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct s3c_sdi_host *host = mmc_priv(mmc);
++ u32 sdi_carg, sdi_ccon, sdi_timer, sdi_fsta;
++ u32 sdi_bsize, sdi_dcon = 0, sdi_imsk;
++ u32 dma_dir = 0;
++
++ WARN_ON(host->mrq != NULL);
++
++ DBG("#############request: [CMD] opcode:0x%02x arg:0x%08x flags:%x retries:%u\n",
++ mrq->cmd->opcode, mrq->cmd->arg, mrq->cmd->flags, mrq->cmd->retries);
++
++ host->mrq = mrq;
++
++ sdi_ccon = mrq->cmd->opcode & S3C_SDICCON_INDEX;
++ sdi_ccon|= (S3C_SDICCON_SENDERHOST | S3C_SDICCON_CMDSTART);
++
++#ifdef CONFIG_S3CMCI_DEBUG
++ {
++ cmd_rec[cmd_idx] = mrq->cmd->opcode;
++ cmd_idx++;
++ cmd_idx %= 40;
++ }
++#endif
++ sdi_carg = mrq->cmd->arg;
++
++ /* XXX: Timer value ?! */
++ sdi_timer= 0x7fffff;
++
++ sdi_bsize= 0;
++
++ /* enable interrupts for transmission errors */
++ sdi_imsk = (S3C_SDIIMSK_RESPONSEND | S3C_SDIIMSK_CRCSTATUS);
++
++ host->complete_what = COMPLETION_CMDSENT;
++
++ if (RSP_TYPE(mmc_resp_type(mrq->cmd))) {
++ host->complete_what = COMPLETION_RSPFIN;
++
++ sdi_ccon |= S3C_SDICCON_WAITRSP;
++ sdi_imsk |= S3C_SDIIMSK_CMDTIMEOUT;
++ } else {
++ /* We need the CMDSENT-Interrupt only if we want are not waiting
++ * for a response
++ */
++ sdi_imsk |= S3C_SDIIMSK_CMDSENT;
++ }
++
++ if (mrq->cmd->flags & MMC_RSP_136) {
++ sdi_ccon|= S3C_SDICCON_LONGRSP;
++ }
++
++ if (mrq->cmd->flags & MMC_RSP_CRC) {
++ sdi_imsk |= S3C_SDIIMSK_RESPONSECRC;
++ }
++
++ if (mrq->data) {
++ host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
++
++ sdi_ccon|= S3C_SDICCON_WITHDATA;
++
++ sdi_bsize = mrq->data->blksz;
++
++ sdi_dcon = (mrq->data->blocks & S3C_SDIDCON_BLKNUM_MASK);
++ sdi_dcon |= S3C_SDIDCON_DMAEN;
++ sdi_dcon |= S3C_SDIDCON_WORDTX;
++
++ if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
++ sdi_dcon |= S3C_SDIDCON_WIDEBUS;
++ }
++
++ sdi_imsk |= 0xFFFFFFE0;
++
++ DBG(PFX "request: [DAT] bsize:%u blocks:%u bytes:%u\n",
++ sdi_bsize, mrq->data->blocks, mrq->data->blocks * sdi_bsize);
++
++ if (!(mrq->data->flags & MMC_DATA_STREAM)) {
++ sdi_dcon |= S3C_SDIDCON_BLOCKMODE;
++ }
++
++ if (mrq->data->flags & MMC_DATA_WRITE) {
++ sdi_dcon |= S3C_SDIDCON_TXAFTERRESP;
++ sdi_dcon |= S3C_SDIDCON_XFER_TX;
++ sdi_dcon |= S3C_SDIDCON_DSTART;
++ s3c_sdi_dma_setup(host, DMAP_WRITE);
++ dma_dir = DMA_TO_DEVICE;
++ } else {
++ sdi_dcon |= S3C_SDIDCON_RXAFTERCMD;
++ sdi_dcon |= S3C_SDIDCON_XFER_RX;
++ sdi_dcon |= S3C_SDIDCON_DSTART;
++ s3c_sdi_dma_setup(host, DMAP_READ);
++ dma_dir = DMA_FROM_DEVICE;
++ }
++
++ sdi_fsta = S3C_SDIFSTA_FRST;
++ __raw_writel(sdi_fsta,host->base + S3C_SDIFSTA);
++
++ /* start DMA */
++ dma_map_sg(mmc_dev(mmc), mrq->data->sg, mrq->data->sg_len, dma_dir);
++ s3c_dma_enqueue(host->dma, (void *) host,
++ sg_dma_address(mrq->data->sg),
++ (mrq->data->blocks * mrq->data->blksz) );
++ }
++
++ host->mrq = mrq;
++ init_completion(&host->complete_request);
++ init_completion(&host->complete_dma);
++
++ /* Clear command and data status registers */
++ writel(0xFFFFFFFF, host->base + S3C_SDICSTA);
++ writel(0xFFFFFFFF, host->base + S3C_SDIDSTA);
++
++ /* Setup SDI controller */
++ writel(sdi_bsize,host->base + S3C_SDIBSIZE);
++ writel(sdi_timer,host->base + S3C_SDITIMER);
++ writel(sdi_imsk,host->base + S3C_SDIIMSK);
++
++ /* Setup SDI command argument and data control */
++ writel(sdi_carg, host->base + S3C_SDICARG);
++ writel(sdi_dcon, host->base + S3C_SDIDCON);
++ /* This initiates transfer */
++ writel(sdi_ccon, host->base + S3C_SDICCON);
++
++ /* this wait is very important to sd/mmc run correctly.
++ * Without this blocking code, operation sequence may be crashed.
++ * by scsuh.
++ */
++ /* Wait for transfer to complete */
++ wait_for_completion(&host->complete_request);
++ if (mrq->data && (host->mrq->data->error == MMC_ERR_NONE)) {
++ wait_for_completion(&host->complete_dma);
++ DBG("[DAT] DMA complete.\n");
++ sdi_fsta = readl(host->base + S3C_SDIFSTA);
++ writel(sdi_fsta,host->base + S3C_SDIFSTA);
++ }
++
++ /* Cleanup controller */
++ writel(0, host->base + S3C_SDICARG);
++ writel(0, host->base + S3C_SDIDCON);
++ writel(0, host->base + S3C_SDICCON);
++ writel(0, host->base + S3C_SDIIMSK);
++
++ /* Read response */
++ mrq->cmd->resp[0] = readl(host->base + S3C_SDIRSP0);
++ mrq->cmd->resp[1] = readl(host->base + S3C_SDIRSP1);
++ mrq->cmd->resp[2] = readl(host->base + S3C_SDIRSP2);
++ mrq->cmd->resp[3] = readl(host->base + S3C_SDIRSP3);
++
++ host->mrq = NULL;
++
++ DBG(PFX "request done.\n");
++
++ if (mrq->data) {
++ dma_unmap_sg(mmc_dev(mmc), mrq->data->sg, mrq->data->sg_len, dma_dir);
++
++ /* Calulate the amout of bytes transfer, but only if there was
++ * no error
++ */
++ if (mrq->data->error == MMC_ERR_NONE)
++ mrq->data->bytes_xfered = (mrq->data->blocks * mrq->data->blksz);
++ else
++ mrq->data->bytes_xfered = 0;
++
++ /* If we had an error while transfering data we flush the
++ * DMA channel to clear out any garbage
++ */
++ if (mrq->data->error != MMC_ERR_NONE) {
++#ifdef CONFIG_ARCH_MDIRAC3
++ s3c_dma_ctrl(host->dma,host->subchannel, S3C_DMAOP_FLUSH);
++#else
++ s3c_dma_ctrl(host->dma, S3C_DMAOP_FLUSH);
++#endif
++ DBG(PFX "flushing DMA.\n");
++ }
++ /* Issue stop command */
++ if (mrq->data->stop)
++ mmc_wait_for_cmd(mmc, mrq->data->stop, 3);
++ }
++
++ mrq->done(mrq);
++}
++
++static void s3c_sdi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++ struct s3c_sdi_host *host = mmc_priv(mmc);
++ u32 sdi_psc, sdi_con = 0, sdi_fsta;
++
++ writel(0, host->base + S3C_SDICON);
++ udelay(1000);
++
++ DBG("%d, %d\n", ios->clock, ios->bus_width);
++ /* Set power */
++ switch(ios->power_mode) {
++ case MMC_POWER_ON:
++ case MMC_POWER_UP:
++#ifdef CONFIG_ARCH_S3C2460
++ gpio_set_pin(S3C_GPA8, S3C_GPA8_SDIO_CMD);
++ gpio_set_pin(S3C_GPA9, S3C_GPA9_SDIO_DAT0);
++ gpio_set_pin(S3C_GPA10, S3C_GPA10_SDIO_DAT1);
++ gpio_set_pin(S3C_GPA11, S3C_GPA11_SDIO_DAT2);
++ gpio_set_pin(S3C_GPA12, S3C_GPA12_SDIO_DAT3);
++ gpio_set_pin(S3C_GPA13, S3C_GPA13_SDIO_CLK);
++ sdi_con = S3C_SDICON_CLKTYPE_MMC | (1 << 6);
++#else
++ gpio_set_pin(S3C_GPE5, S3C_GPE5_SDCLK);
++ gpio_set_pin(S3C_GPE6, S3C_GPE6_SDCMD);
++ gpio_set_pin(S3C_GPE7, S3C_GPE7_SDDAT0);
++ gpio_set_pin(S3C_GPE8, S3C_GPE8_SDDAT1);
++ gpio_set_pin(S3C_GPE9, S3C_GPE9_SDDAT2);
++ gpio_set_pin(S3C_GPE10, S3C_GPE10_SDDAT3);
++#endif
++
++ if (mmc->mode == MMC_MODE_MMC) {
++ sdi_con = S3C_SDICON_CLKTYPE_MMC;
++ }
++ break;
++
++ case MMC_POWER_OFF:
++ default:
++ sdi_con = S3C_SDICON_RESET;
++ writel(sdi_con, host->base + S3C_SDICON);
++ while(readl(host->base + S3C_SDICON) & S3C_SDICON_RESET);
++#ifdef CONFIG_ARCH_S3C2460
++ gpio_direction_output(S3C_GPA13);
++#else
++ gpio_direction_output(S3C_GPE5);
++#endif
++ break;
++ }
++
++ sdi_fsta = S3C_SDIFSTA_FRST;
++ writel(sdi_fsta,host->base + S3C_SDIFSTA);
++
++ /* Set clock */
++ for(sdi_psc=0;sdi_psc<254;sdi_psc++) {
++ if ( (clk_get_rate(host->clk) / (sdi_psc+1)) <= ios->clock)
++ break;
++ }
++
++ if (sdi_psc > 255)
++ sdi_psc = 255;
++ writel(sdi_psc, host->base + S3C_SDIPRE);
++
++#ifdef CONFIG_S3CMCI_DEBUG
++ if (sdi_psc < 10)
++ printk(" clock is: %lu.%luMHz of %uMHz\n",
++ clk_get_rate(host->clk)/(sdi_psc+1)/1000000,
++ (clk_get_rate(host->clk)/(sdi_psc+1)/1000)%1000,
++ (ios->clock)/1000000);
++#endif
++
++ /* Only SD clock can support more than 20MHz clock.
++ * by scsuh
++ */
++ if (clk_get_rate(host->clk) / (sdi_psc+1) > 20 * MHZ)
++ sdi_con &= ~S3C_SDICON_CLKTYPE_MMC;
++
++ /* Set CLOCK_ENABLE */
++ if (ios->clock)
++ sdi_con |= S3C_SDICON_CLKENABLE;
++ else
++ sdi_con &=~S3C_SDICON_CLKENABLE;
++
++ writel(sdi_con, host->base + S3C_SDICON);
++ udelay(1000);
++}
++
++static struct mmc_host_ops s3c_sdi_ops = {
++ .request = s3c_sdi_request,
++ .set_ios = s3c_sdi_set_ios,
++};
++
++static int s3c_sdi_probe(struct platform_device *pdev)
++{
++ struct mmc_host *mmc;
++ struct s3c_sdi_host *host;
++
++ int ret;
++#ifdef CONFIG_S3C2443_EVT1
++ /* EXTINT0 S3C2443 EVT1 workaround */
++ u32 tmp;
++#endif
++
++ mmc = mmc_alloc_host(sizeof(struct s3c_sdi_host), &pdev->dev);
++ if (!mmc) {
++ ret = -ENOMEM;
++ goto probe_out;
++ }
++
++ host = mmc_priv(mmc);
++ spin_lock_init(&host->complete_lock);
++ host->complete_what = COMPLETION_NONE;
++ host->mmc = mmc;
++#ifdef CONFIG_ARCH_S3C2460
++ host->irq_cd = IRQ_EINT3;
++#elif defined(CONFIG_MACH_SMDK2443)
++ host->irq_cd = IRQ_EINT1;
++#elif defined CONFIG_MACH_SMDK2412
++ host->irq_cd = IRQ_EINT18;
++#endif
++ host->dma = S3C_SDI_DMA;
++
++ host->mem = platform_get_resource(pdev, IORESOURCE_MEM ,0);
++ if (!host->mem) {
++ printk("failed to get io memory region resource.\n");
++ ret = -ENOENT;
++ goto probe_free_host;
++ }
++
++ host->mem = request_mem_region(host->mem->start,
++ RESSIZE(host->mem), pdev->name);
++
++ if (!host->mem) {
++ printk("failed to request io memory region.\n");
++ ret = -ENOENT;
++ goto probe_free_host;
++ }
++
++ /* if there is an error here, check your SoC dependent code.
++ * You must have iotable that contains SDI in it.
++ * by scsuh.
++ */
++ host->base = S3C_VA_SDI;
++ host->irq = platform_get_irq(pdev, 0);
++
++ if (host->irq == 0) {
++ printk("failed to get interrupt resouce.\n");
++ ret = -EINVAL;
++ goto release_memory;
++ }
++
++ if (request_irq(host->irq, s3c_sdi_irq, 0, DRIVER_NAME, host)) {
++ printk("failed to request sdi interrupt.\n");
++ ret = -ENOENT;
++ goto release_memory;
++ }
++
++#if defined(CONFIG_MACH_SMDK2443)
++#ifdef CONFIG_S3C2443_EVT1
++ /* EXTINT0 S3C2443 EVT1 workaround */
++ tmp = __raw_readl(S3C_EXTINT0);
++ s3c_swap_4bit(tmp);
++ __raw_writel(tmp | (1<<7), S3C_EXTINT0);
++#endif
++ gpio_set_pin(S3C_GPF1, S3C_GPF1_EINT1);
++#elif defined(CONFIG_ARCH_S3C2460)
++ gpio_set_pin(S3C_GPJ3, S3C_GPJ3_EXT_INT3);
++#elif defined (CONFIG_MACH_SMDK2412)
++ gpio_set_pin(S3C_GPG10, S3C_GPG10_EINT18);
++#endif
++
++ set_irq_type(host->irq_cd, IRQT_BOTHEDGE);
++
++ if (request_irq(host->irq_cd, s3c_sdi_irq_cd, SA_INTERRUPT, DRIVER_NAME, host)) {
++ printk("failed to request card detect interrupt.\n" );
++ ret = -ENOENT;
++ goto probe_free_irq;
++ }
++
++ if (s3c_dma_request(S3C_SDI_DMA, &s3c_sdi_dma_client, NULL)) {
++ printk("unable to get DMA channel.\n" );
++ ret = -EBUSY;
++ goto probe_free_irq_cd;
++ }
++
++ host->clk = clk_get(&pdev->dev, "sdi");
++ if (IS_ERR(host->clk)) {
++ printk("failed to find clock source.\n");
++ ret = PTR_ERR(host->clk);
++ host->clk = NULL;
++ goto probe_free_host;
++ }
++
++ if ((ret = clk_enable(host->clk))) {
++ printk("failed to enable clock source.\n");
++ goto clk_free;
++ }
++
++ mmc->ops = &s3c_sdi_ops;
++ mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
++ mmc->f_min = clk_get_rate(host->clk) / 512;
++ /* you must make sure that our sdmmc block can support
++ * up to 25MHz. by scsuh
++ */
++ mmc->f_max = 25 * MHZ;
++ mmc->caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE);
++
++ /*
++ * Since we only have a 16-bit data length register, we must
++ * ensure that we don't exceed 2^16-1 bytes in a single request.
++ * Choose 64 (512-byte) sectors as the limit.
++ */
++ mmc->max_sectors = 64;
++
++ /*
++ * Set the maximum segment size. Since we aren't doing DMA
++ * (yet) we are only limited by the data length register.
++ */
++
++ mmc->max_seg_size = mmc->max_sectors << 9;
++ printk(KERN_INFO PFX "probe: mapped sdi_base=%p irq=%u irq_cd=%u dma=%u.\n",
++ host->base, host->irq, host->irq_cd, host->dma);
++ platform_set_drvdata(pdev, mmc);
++
++ init_timer(&host->timer);
++ host->timer.data = (unsigned long)host;
++ host->timer.function = s3c_sdi_check_status;
++ host->timer.expires = jiffies + HZ;
++
++ if ((ret = mmc_add_host(mmc))) {
++ printk(KERN_INFO PFX "failed to add mmc host.\n");
++ goto free_dmabuf;
++ }
++
++ printk(KERN_INFO PFX "initialization done.\n");
++ return 0;
++
++free_dmabuf:
++ clk_disable(host->clk);
++
++clk_free:
++ clk_put(host->clk);
++
++probe_free_irq_cd:
++ free_irq(host->irq_cd, host);
++
++probe_free_irq:
++ free_irq(host->irq, host);
++
++release_memory:
++ release_mem_region(host->mem->start, RESSIZE(host->mem));
++
++probe_free_host:
++ mmc_free_host(mmc);
++
++probe_out:
++ return ret;
++}
++
++static int s3c_sdi_remove(struct platform_device *dev)
++{
++ struct mmc_host *mmc = platform_get_drvdata(dev);
++ struct s3c_sdi_host *host = mmc_priv(mmc);
++
++ del_timer_sync(&host->timer);
++ mmc_remove_host(mmc);
++
++ clk_disable(host->clk);
++ clk_put(host->clk);
++ free_irq(host->irq_cd, host);
++ free_irq(host->irq, host);
++ mmc_free_host(mmc);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_sdi_suspend(struct platform_device *dev, pm_message_t state)
++{
++ struct mmc_host *mmc = platform_get_drvdata(dev);
++ struct s3c_sdi_host *host = mmc_priv(mmc);
++ int ret = 0;
++
++ if (mmc)
++#if 0
++ mmc_remove_host(host);
++#else
++ ret = mmc_suspend_host(mmc, state);
++ s3c_dma_free(host->dma, &s3c_sdi_dma_client);
++#endif
++
++ //clk_disable(host->clk);
++ return ret;
++}
++
++static int s3c_sdi_resume(struct platform_device *dev)
++{
++ struct mmc_host *mmc = platform_get_drvdata(dev);
++ struct s3c_sdi_host *host = mmc_priv(mmc);
++ int ret = 0;
++
++#if 0
++ clk_enable(host->clk);
++ init_timer(&host->timer);
++ host->timer.data = (unsigned long)host;
++ host->timer.function = s3c_sdi_check_status;
++ host->timer.expires = jiffies + HZ;
++
++ if ((ret = mmc_add_host(mmc))) {
++ printk(KERN_INFO PFX "failed to add mmc host.\n");
++ }
++
++ printk(KERN_INFO PFX "initialization done.\n");
++#else
++ s3c_dma_request(host->dma, &s3c_sdi_dma_client, NULL);
++ if (mmc)
++ ret = mmc_resume_host(mmc);
++#endif
++
++ return ret;
++}
++#else
++#define s3c_sdi_suspend NULL
++#define s3c_sdi_resume NULL
++#endif
++
++static struct platform_driver s3c_sdi_driver =
++{
++ .probe = s3c_sdi_probe,
++ .remove = s3c_sdi_remove,
++ .suspend = s3c_sdi_suspend,
++ .resume = s3c_sdi_resume,
++ .driver = {
++ .name = "s3c-sdi",
++ },
++};
++
++static int __init s3c_sdi_init(void)
++{
++ return platform_driver_register(&s3c_sdi_driver);
++}
++
++static void __exit s3c_sdi_exit(void)
++{
++ platform_driver_unregister(&s3c_sdi_driver);
++}
++module_init(s3c_sdi_init);
++module_exit(s3c_sdi_exit);
++
++MODULE_DESCRIPTION("S3C Multimedia Card I/F Driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/mmc/host/s3cmci.h b/drivers/mmc/host/s3cmci.h
+new file mode 100644
+index 0000000..d51ab02
+--- /dev/null
++++ b/drivers/mmc/host/s3cmci.h
+@@ -0,0 +1,52 @@
++/*
++ * linux/drivers/mmc/s3c2413mci.h - Samsung S3C2413 SDI Interface driver
++ *
++ * $Id: s3cmci.h,v 1.2 2007/07/17 01:37:30 ihlee215 Exp $
++ *
++ * Copyright (C) 2004 Thomas Kleffel, All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#define S3C_SDI_DMA 0
++
++enum s3c_sdi_waitfor {
++ COMPLETION_NONE,
++ COMPLETION_CMDSENT,
++ COMPLETION_RSPFIN,
++ COMPLETION_XFERFINISH,
++ COMPLETION_XFERFINISH_RSPFIN,
++};
++
++struct s3c_sdi_host {
++ void __iomem *base;
++ struct mmc_request *mrq;
++ struct mmc_command *cmd;
++ struct mmc_data *data;
++ struct mmc_host *mmc;
++ struct clk *clk;
++ struct resource *mem;
++
++ unsigned int data_xfered;
++
++ struct timer_list timer;
++
++ int irq;
++ int irq_cd;
++ int dma;
++ int subchannel;
++ int dma_dir;
++
++ spinlock_t complete_lock;
++ struct completion complete_request;
++ struct completion complete_dma;
++ enum s3c_sdi_waitfor complete_what;
++
++ struct scatterlist *sg_ptr;
++ unsigned int sg_len;
++ unsigned int sg_off;
++ unsigned int size;
++};
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index 246d451..4022302 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -1,5 +1,5 @@
+ # drivers/mtd/nand/Kconfig
+-# $Id: Kconfig,v 1.35 2005/11/07 11:14:30 gleixner Exp $
++# $Id: Kconfig,v 1.1.1.1 2008/02/18 02:22:57 ihlee215 Exp $
+
+ menuconfig MTD_NAND
+ tristate "NAND Device Support"
+@@ -151,6 +151,52 @@ config MTD_NAND_S3C2410_HWECC
+ incorrect ECC generation, and if using these, the default of
+ software ECC is preferable.
+
++ If you lay down a device with the hardware ECC, then you will
++ currently not be able to switch to software, as there is no
++ implementation for ECC method used by the S3C2410
++
++config MTD_NAND_S3C
++ tristate "NAND Flash support for S3C SoC"
++ depends on ARCH_S3C2410 && MTD_NAND
++ help
++ This enables the NAND flash controller on the S3C.
++
++ No board specfic support is done by this driver, each board
++ must advertise a platform_device for the driver to attach.
++
++config MTD_NAND_S3C_DEBUG
++ bool "S3C NAND driver debug"
++ depends on MTD_NAND_S3C
++ help
++ Enable debugging of the S3C NAND driver
++
++config MTD_NO_ECC_WARNING
++ bool "S3C MTD NO ECC warning"
++ depends on MTD_NAND_S3C
++ default y
++ help
++ Disable warnings when reading or writing on NO ECC Mode.
++
++config MTD_NAND_S3C_HWECC
++ bool "S3C NAND Hardware ECC"
++ depends on MTD_NAND_S3C
++ help
++ Enable the use of the S3C's internal ECC generator when
++ using NAND. Early versions of the chip have had problems with
++ incorrect ECC generation, and if using these, the default of
++ software ECC is preferable.
++
++ If you lay down a device with the hardware ECC, then you will
++ currently not be able to switch to software, as there is no
++ implementation for ECC method used by the S3C
++
++config S3C_LARGEPAGE_NAND
++ bool "Large (2K) page nand Support Enable"
++ depends on MTD_NAND_S3C
++ default n
++ help
++ S3C Large Page nand support.
++
+ config MTD_NAND_NDFC
+ tristate "NDFC NanD Flash Controller"
+ depends on 4xx && !PPC_MERGE
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index 3ad6c01..2d293c1 100644
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # linux/drivers/nand/Makefile
+ #
+-# $Id: Makefile.common,v 1.15 2004/11/26 12:28:22 dedekind Exp $
++# $Id: Makefile,v 1.1.1.1 2008/02/18 02:22:57 ihlee215 Exp $
+
+ obj-$(CONFIG_MTD_NAND) += nand.o nand_ecc.o
+ obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o
+@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
+ obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
+ obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
++obj-$(CONFIG_MTD_NAND_S3C) += s3c_nand.o
+ obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
+ obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
+ obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
+diff --git a/drivers/mtd/nand/s3c_nand.c b/drivers/mtd/nand/s3c_nand.c
+new file mode 100644
+index 0000000..e55e90a
+--- /dev/null
++++ b/drivers/mtd/nand/s3c_nand.c
+@@ -0,0 +1,930 @@
++/* linux/drivers/mtd/nand/s3c_nand.c
++ *
++ * Copyright (c) 2007 Samsung Electronics
++ *
++ * Samsung S3C NAND driver
++ *
++ * $Id: s3c_nand.c,v 1.14 2008/09/16 07:29:25 jsgood Exp $
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * Based on nand driver from Ben Dooks <ben@simtec.co.uk>
++ * modified by scsuh. based on au1550nd.c
++ *
++ * Many functions for hardware ecc are implemented by jsgood.
++ */
++
++/* Simple H/W Table for Implementation of S3C nand driver
++ * by scsuh
++ * ------------------------------------------------------------------
++ * | En/Dis CE | required | |
++ * | En/Dis ALE | X | * nand controller does |
++ * | En/Dis CLE | X | * nand controller does |
++ * | Wait/Ready | required | |
++ * | Write Command | required | |
++ * | Write Address | required | |
++ * | Write Data | required | |
++ * | Read Data | required | |
++ * | WP on/off | required | * board specific |
++ * | AP Specific Init | required | |
++ * ------------------------------------------------------------------
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/ioport.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/jiffies.h>
++#include <linux/sched.h>
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/nand_ecc.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/io.h>
++#include <asm/mach-types.h>
++
++#include <asm/plat-s3c/regs-nand.h>
++#include <asm/plat-s3c/nand.h>
++
++struct s3c_nand_info {
++ /* mtd info */
++ struct nand_hw_control controller;
++ struct s3c_nand_mtd_info *mtds;
++ struct s3c2410_platform_nand *platform;
++
++ /* device info */
++ struct device *device;
++ struct resource *area;
++ struct clk *clk;
++ void __iomem *regs;
++ void __iomem *sel_reg;
++ int sel_bit;
++ int mtd_count;
++
++ //enum s3c_cpu_type cpu_type;
++};
++static struct s3c_nand_info s3c_nand;
++
++static struct mtd_info *s3c_mtd = NULL;
++
++/* Nand flash definition values by jsgood */
++#define S3C_NAND_TYPE_UNKNOWN 0x0
++#define S3C_NAND_TYPE_SLC 0x1
++#define S3C_NAND_TYPE_MLC 0x2
++
++/*
++ * Cached progamming disabled for now, Not sure if its worth the
++ * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
++ *
++ * if want to use cached program, define next
++ * by jsgood (modified to keep prevent rule)
++ */
++#undef CONFIG_MTD_NAND_S3C_CACHEDPROG
++
++/* Nand flash global values by jsgood */
++int cur_ecc_mode = 0;
++int nand_type = S3C_NAND_TYPE_UNKNOWN;
++
++#if defined(CONFIG_MTD_NAND_S3C_HWECC)
++/* Nand flash oob definition for SLC 512b page size by jsgood */
++static struct nand_ecclayout s3c_nand_oob_16 = {
++ .eccbytes = 4,
++ .eccpos = {1, 2, 3, 4},
++ .oobfree = {
++ {.offset = 6,
++ .length = 10}}
++};
++
++/* Nand flash oob definition for SLC 2k page size by jsgood */
++static struct nand_ecclayout s3c_nand_oob_64 = {
++ .eccbytes = 16,
++ .eccpos = {40, 41, 42, 43, 44, 45, 46, 47,
++ 48, 49, 50, 51, 52, 53, 54, 55},
++ .oobfree = {
++ {.offset = 2,
++ .length = 38}}
++};
++
++/* Nand flash oob definition for MLC 2k page size by jsgood */
++static struct nand_ecclayout s3c_nand_oob_mlc_64 = {
++ .eccbytes = 32,
++ .eccpos = {
++ 32, 33, 34, 35, 36, 37, 38, 39,
++ 40, 41, 42, 43, 44, 45, 46, 47,
++ 48, 49, 50, 51, 52, 53, 54, 55,
++ 56, 57, 58, 59, 60, 61, 62, 63},
++ .oobfree = {
++ {.offset = 2,
++ .length = 28}}
++};
++#endif
++
++#if defined(CONFIG_MTD_NAND_S3C_DEBUG)
++/*
++ * Function to print out oob buffer for debugging
++ * Written by jsgood
++ */
++void print_oob(const char *header, struct mtd_info *mtd)
++{
++ int i;
++ struct nand_chip *chip = mtd->priv;
++
++ printk("%s:\t", header);
++
++ for(i = 0; i < 64; i++)
++ printk("%02x ", chip->oob_poi[i]);
++
++ printk("\n");
++}
++EXPORT_SYMBOL(print_oob);
++#endif
++
++
++/*
++ * Hardware specific access to control-lines function
++ * Written by jsgood
++ */
++static void s3c_nand_hwcontrol(struct mtd_info *mtd, int dat, unsigned int ctrl)
++{
++ unsigned int cur;
++ void __iomem *regs = s3c_nand.regs;
++
++ if (ctrl & NAND_CTRL_CHANGE) {
++ if (ctrl & NAND_NCE) {
++ if (dat != NAND_CMD_NONE) {
++ cur = readl(regs + S3C2440_NFCONT);
++ cur &= ~S3C2412_NFCONT_nFCE0;
++ writel(cur, regs + S3C2440_NFCONT);
++ }
++ } else {
++ cur = readl(regs + S3C2440_NFCONT);
++ cur |= S3C2412_NFCONT_nFCE0;
++ writel(cur, regs + S3C2440_NFCONT);
++ }
++ }
++
++ if (dat != NAND_CMD_NONE) {
++ if (ctrl & NAND_CLE)
++ writeb(dat, regs + S3C2440_NFCMD);
++ else if (ctrl & NAND_ALE)
++ writeb(dat, regs + S3C2440_NFADDR);
++ }
++}
++
++/*
++ * Function for checking device ready pin
++ * Written by jsgood
++ */
++static int s3c_nand_device_ready(struct mtd_info *mtd)
++{
++ void __iomem *regs = s3c_nand.regs;
++/* it's to check the RnB nand signal bit and return to device ready condition in nand_base.c */
++ return ((readl(regs + S3C2412_NFSTAT) & S3C2410_NFSTAT_BUSY));
++}
++
++/*
++ * We don't use a bad block table
++ */
++static int s3c_nand_scan_bbt(struct mtd_info *mtdinfo)
++{
++ return 0;
++}
++
++#if defined(CONFIG_MTD_NAND_S3C_HWECC)
++#if 0
++/*
++ * S3C Nand flash chip enable function
++ * Written by jsgood
++ */
++static void s3c_nand_ce_on(struct mtd_info *mtd)
++{
++ struct nand_chip *chip = mtd->priv;
++
++ chip->cmd_ctrl(mtd, 0x0, NAND_NCE | NAND_CTRL_CHANGE);
++ nand_wait_ready(mtd);
++}
++
++/*
++ * S3C Nand flash chip disable function
++ * Written by jsgood
++ */
++static void s3c_nand_ce_off(struct mtd_info *mtd)
++{
++ struct nand_chip *chip = mtd->priv;
++
++ chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_CTRL_CHANGE);
++ nand_wait_ready(mtd);
++}
++#endif
++
++/*
++ * Function for checking ECCEncDone in NFSTAT
++ * Written by jsgood
++ */
++static void s3c_nand_wait_enc(void)
++{
++ /* S3C2412 can not check S3C2412_NFSTAT_ECC_ENCDONE */
++#if defined(CONFIG_S3C2443) || defined(CONFIG_S3C6400) || defined(CONFIG_S3C2450) || defined(CONFIG_CPU_S3C2416)
++
++ void __iomem *regs = s3c_nand.regs;
++ unsigned long timeo = jiffies;
++
++ timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */
++
++ /* Apply this short delay always to ensure that we do wait tWB in
++ * any case on any machine. */
++
++ while (time_before(jiffies, timeo)) {
++ if (readl(regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_ECC_ENCDONE)
++ break;
++ cond_resched();
++ }
++#else
++ return;
++#endif
++
++}
++
++/*
++ * Function for checking ECCDecDone in NFSTAT
++ * Written by jsgood
++ */
++static void s3c_nand_wait_dec(void)
++{
++ void __iomem *regs = s3c_nand.regs;
++ unsigned long timeo = jiffies;
++
++ timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */
++
++ /* Apply this short delay always to ensure that we do wait tWB in
++ * any case on any machine. */
++
++ while (time_before(jiffies, timeo)) {
++ if (readl(regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_ECC_DECDONE)
++ break;
++ cond_resched();
++ }
++}
++
++/*
++ * Function for checking ECC Busy
++ * Written by jsgood
++ */
++static void s3c_nand_wait_ecc_busy(void)
++{
++ void __iomem *regs = s3c_nand.regs;
++ unsigned long timeo = jiffies;
++
++ timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */
++
++ /* Apply this short delay always to ensure that we do wait tWB in
++ * any case on any machine. */
++
++ while (time_before(jiffies, timeo)) {
++ if (!(readl(regs + S3C2412_NFMECC_ERR0) & S3C_NFSTAT0_ECCBUSY))
++ break;
++ cond_resched();
++ }
++}
++
++/*
++ * This function is called before encoding ecc codes to ready ecc engine.
++ * Written by jsgood
++ */
++static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ u_long nfcont;
++ u_long nfconf;
++ void __iomem *regs = s3c_nand.regs;
++
++ cur_ecc_mode = mode;
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ nfconf = readl(regs + S3C2410_NFCONF);
++
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450)
++ nfconf &= ~(0x3 << 23);
++
++ if (nand_type == S3C_NAND_TYPE_SLC)
++ nfconf |= S3C_NFCONF_ECC_1BIT;
++ else
++ nfconf |= S3C_NFCONF_ECC_4BIT;
++#else
++
++ if (nand_type == S3C_NAND_TYPE_SLC)
++ nfconf &= ~S3C2412_NFCONF_ECC_MLC; /* SLC */
++ else
++ nfconf |= S3C2412_NFCONF_ECC_MLC; /* MLC */
++#endif
++
++ writel(nfconf, regs + S3C2410_NFCONF);
++#endif
++ /* Init main ECC & unlock */
++ nfcont = readl(regs + S3C2440_NFCONT);
++ nfcont |= S3C_NFCONT_INITMECC;
++ nfcont &= ~S3C2412_NFCONT_MAIN_ECC_LOCK;
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ if (nand_type == S3C_NAND_TYPE_MLC) {
++ if (mode == NAND_ECC_WRITE)
++ nfcont |= S3C2412_NFCONT_ECC4_DIRWR;
++ else if (mode == NAND_ECC_READ)
++ nfcont &= ~S3C2412_NFCONT_ECC4_DIRWR;
++ }
++#endif
++ writel(nfcont, regs + S3C2440_NFCONT);
++}
++
++/*
++ * This function is called immediately after encoding ecc codes.
++ * This function returns encoded ecc codes.
++ * Written by jsgood
++ */
++static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
++{
++ u_long nfcont, nfmecc0, nfmecc1;
++ void __iomem *regs = s3c_nand.regs;
++
++ /* Lock */
++ nfcont = readl(regs + S3C2440_NFCONT);
++ nfcont |= S3C2412_NFCONT_MAIN_ECC_LOCK;
++ writel(nfcont, regs + S3C2440_NFCONT);
++
++ if (nand_type == S3C_NAND_TYPE_SLC) {
++ nfmecc0 = readl(regs + S3C2412_NFMECC0);
++
++ ecc_code[0] = nfmecc0 & 0xff;
++ ecc_code[1] = (nfmecc0 >> 8) & 0xff;
++ ecc_code[2] = (nfmecc0 >> 16) & 0xff;
++ ecc_code[3] = (nfmecc0 >> 24) & 0xff;
++ } else {
++ if (cur_ecc_mode == NAND_ECC_READ)
++ s3c_nand_wait_dec();
++ else {
++ s3c_nand_wait_enc();
++
++ nfmecc0 = readl(regs + S3C2412_NFMECC0);
++ nfmecc1 = readl(regs + S3C2412_NFMECC1);
++
++ ecc_code[0] = nfmecc0 & 0xff;
++ ecc_code[1] = (nfmecc0 >> 8) & 0xff;
++ ecc_code[2] = (nfmecc0 >> 16) & 0xff;
++ ecc_code[3] = (nfmecc0 >> 24) & 0xff;
++ ecc_code[4] = nfmecc1 & 0xff;
++ ecc_code[5] = (nfmecc1 >> 8) & 0xff;
++ ecc_code[6] = (nfmecc1 >> 16) & 0xff;
++ ecc_code[7] = (nfmecc1 >> 24) & 0xff;
++ }
++ }
++
++ return 0;
++}
++
++/*
++ * This function determines whether read data is good or not.
++ * If SLC, must write ecc codes to controller before reading status bit.
++ * If MLC, status bit is already set, so only reading is needed.
++ * If status bit is good, return 0.
++ * If correctable errors occured, do that.
++ * If uncorrectable errors occured, return -1.
++ * Written by jsgood
++ */
++static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
++{
++ int ret = -1;
++ u_long nfestat0, nfestat1, nfmeccdata0, nfmeccdata1, nfmlcbitpt;
++ u_char err_type;
++ void __iomem *regs = s3c_nand.regs;
++
++ if (!dat) {
++ printk("No page data\n");
++ return ret;
++ }
++
++ if (nand_type == S3C_NAND_TYPE_SLC) {
++ /* SLC: Write ECC data to compare */
++ nfmeccdata0 = (read_ecc[1] << 16) | read_ecc[0];
++ nfmeccdata1 = (read_ecc[3] << 16) | read_ecc[2];
++ writel(nfmeccdata0, regs + S3C2440_NFECCD0);
++ writel(nfmeccdata1, regs + S3C2440_NFECCD1);
++
++ /* Read ECC status */
++ nfestat0 = readl(regs + S3C2412_NFMECC_ERR0);
++ err_type = nfestat0 & 0x3;
++
++ switch (err_type) {
++ case 0: /* No error */
++ ret = 0;
++ break;
++
++ case 1: /* 1 bit error (Correctable)
++ (nfestat0 >> 7) & 0x7ff :error byte number
++ (nfestat0 >> 4) & 0x7 :error bit number */
++ printk("s3c-nand: 1 bit error detected at byte %ld, correcting from "
++ "0x%02x ", (nfestat0 >> 7) & 0x7ff, dat[(nfestat0 >> 7) & 0x7ff]);
++ dat[(nfestat0 >> 7) & 0x7ff] ^= (1 << ((nfestat0 >> 4) & 0x7));
++ printk("to 0x%02x...OK\n", dat[(nfestat0 >> 7) & 0x7ff]);
++ ret = 1;
++ break;
++
++ case 2: /* Multiple error */
++ case 3: /* ECC area error */
++ printk("s3c-nand: ECC uncorrectable error detected\n");
++ ret = -1;
++ break;
++ }
++ } else {
++ /* MLC: */
++ s3c_nand_wait_ecc_busy();
++
++ nfestat0 = readl(regs + S3C2412_NFMECC_ERR0);
++ nfestat1 = readl(regs + S3C2412_NFMECC_ERR1);
++ nfmlcbitpt = readl(regs + S3C_NFMLCBITPT);
++
++ err_type = (nfestat0 >> 26) & 0x7;
++
++ /* No error, If free page (all 0xff) */
++ if ((nfestat0 >> 29) & 0x1) {
++ err_type = 0;
++ } else {
++ /* No error, If all 0xff from 17th byte in oob (in case of JFFS2 format) */
++ if (dat) {
++ if (dat[17] == 0xff && dat[26] == 0xff && dat[35] == 0xff && dat[44] == 0xff && dat[54] == 0xff)
++ err_type = 0;
++ }
++ }
++
++ switch (err_type) {
++ case 5: /* Uncorrectable */
++ printk("s3c-nand: ECC uncorrectable error detected\n");
++ ret = -1;
++ break;
++
++ case 4: /* 4 bit error (Correctable) */
++ dat[(nfestat1 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 24) & 0xff);
++
++ case 3: /* 3 bit error (Correctable) */
++ dat[nfestat1 & 0x3ff] ^= ((nfmlcbitpt >> 16) & 0xff);
++
++ case 2: /* 2 bit error (Correctable) */
++ dat[(nfestat0 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 8) & 0xff);
++
++ case 1: /* 1 bit error (Correctable) */
++ printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);
++ dat[nfestat0 & 0x3ff] ^= (nfmlcbitpt & 0xff);
++ ret = err_type;
++ break;
++
++ case 0: /* No error */
++ ret = 0;
++ break;
++ }
++ }
++
++ return ret;
++}
++
++static int s3c_nand_write_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip,
++ int page)
++{
++ uint8_t *ecc_calc = chip->buffers->ecccalc;
++ int status = 0;
++ int eccbytes = chip->ecc.bytes;
++ int secc_start = mtd->oobsize - eccbytes;
++ int i;
++
++ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
++
++ /* spare area */
++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
++ chip->write_buf(mtd, chip->oob_poi, secc_start);
++ chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]);
++
++ for (i = 0; i < eccbytes; i++)
++ chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i];
++
++ chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes);
++
++ /* Send command to program the OOB data */
++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++
++ status = chip->waitfunc(mtd, chip);
++
++ return status & NAND_STATUS_FAIL ? -EIO : 0;
++}
++
++static int s3c_nand_read_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip,
++ int page, int sndcmd)
++{
++ uint8_t *ecc_calc = chip->buffers->ecccalc;
++ int eccbytes = chip->ecc.bytes;
++ int secc_start = mtd->oobsize - eccbytes;
++
++ if (sndcmd) {
++ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
++ sndcmd = 0;
++ }
++
++ chip->ecc.hwctl(mtd, NAND_ECC_READ);
++ chip->read_buf(mtd, chip->oob_poi, secc_start);
++ chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]);
++ chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes);
++
++ /* jffs2 special case */
++ if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19))
++ chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0);
++
++ return sndcmd;
++}
++
++static void s3c_nand_write_page_1bit(struct mtd_info *mtd, struct nand_chip *chip,
++ const uint8_t *buf)
++{
++ int i, eccsize = chip->ecc.size;
++ int eccbytes = chip->ecc.bytes;
++ int eccsteps = chip->ecc.steps;
++ int secc_start = mtd->oobsize - eccbytes;
++ uint8_t *ecc_calc = chip->buffers->ecccalc;
++ const uint8_t *p = buf;
++
++ uint32_t *eccpos = chip->ecc.layout->eccpos;
++
++ /* main area */
++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
++ chip->write_buf(mtd, p, eccsize);
++ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
++ }
++
++ for (i = 0; i < chip->ecc.total; i++)
++ chip->oob_poi[eccpos[i]] = ecc_calc[i];
++
++ /* spare area */
++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
++ chip->write_buf(mtd, chip->oob_poi, secc_start);
++ chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]);
++
++ for (i = 0; i < eccbytes; i++)
++ chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i];
++
++ chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes);
++}
++
++static int s3c_nand_read_page_1bit(struct mtd_info *mtd, struct nand_chip *chip,
++ uint8_t *buf)
++{
++ int i, stat, eccsize = chip->ecc.size;
++ int eccbytes = chip->ecc.bytes;
++ int eccsteps = chip->ecc.steps;
++ int secc_start = mtd->oobsize - eccbytes;
++ int col = 0;
++ uint8_t *p = buf;
++ uint32_t *mecc_pos = chip->ecc.layout->eccpos;
++ uint8_t *ecc_calc = chip->buffers->ecccalc;
++
++ col = mtd->writesize;
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
++
++ /* spare area */
++ chip->ecc.hwctl(mtd, NAND_ECC_READ);
++ chip->read_buf(mtd, chip->oob_poi, secc_start);
++ chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]);
++ chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes);
++
++ /* jffs2 special case */
++ if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19))
++ chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0);
++
++ col = 0;
++
++ /* main area */
++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
++ chip->ecc.hwctl(mtd, NAND_ECC_READ);
++ chip->read_buf(mtd, p, eccsize);
++ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
++
++ stat = chip->ecc.correct(mtd, p, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), 0);
++ if (stat == -1)
++ mtd->ecc_stats.failed++;
++
++ col = eccsize * (chip->ecc.steps + 1 - eccsteps);
++ }
++
++ return 0;
++}
++
++/*
++ * Hardware specific page read function for MLC.
++ * Written by jsgood
++ */
++static int s3c_nand_read_page_4bit(struct mtd_info *mtd, struct nand_chip *chip,
++ uint8_t *buf)
++{
++ int i, stat, eccsize = chip->ecc.size;
++ int eccbytes = chip->ecc.bytes;
++ int eccsteps = chip->ecc.steps;
++ int col = 0;
++ uint8_t *p = buf;
++ uint32_t *mecc_pos = chip->ecc.layout->eccpos;
++
++ /* Step1: read whole oob */
++ col = mtd->writesize;
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
++
++ col = 0;
++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
++ chip->ecc.hwctl(mtd, NAND_ECC_READ);
++ chip->read_buf(mtd, p, eccsize);
++ chip->write_buf(mtd, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), eccbytes);
++ chip->ecc.calculate(mtd, 0, 0);
++ stat = chip->ecc.correct(mtd, p, 0, 0);
++
++ if (stat == -1)
++ mtd->ecc_stats.failed++;
++
++ col = eccsize * (chip->ecc.steps + 1 - eccsteps);
++ }
++
++ return 0;
++}
++
++/*
++ * Hardware specific page write function for MLC.
++ * Written by jsgood
++ */
++static void s3c_nand_write_page_4bit(struct mtd_info *mtd, struct nand_chip *chip,
++ const uint8_t *buf)
++{
++ int i, eccsize = chip->ecc.size;
++ int eccbytes = chip->ecc.bytes;
++ int eccsteps = chip->ecc.steps;
++ const uint8_t *p = buf;
++ uint8_t *ecc_calc = chip->buffers->ecccalc;
++ uint32_t *mecc_pos = chip->ecc.layout->eccpos;
++
++ /* Step1: write main data and encode mecc */
++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
++ chip->write_buf(mtd, p, eccsize);
++ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
++ }
++
++ /* Step2: save encoded mecc */
++ for (i = 0; i < chip->ecc.total; i++)
++ chip->oob_poi[mecc_pos[i]] = ecc_calc[i];
++
++ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
++}
++#endif
++
++/* s3c_nand_probe
++ *
++ * called by device layer when it finds a device matching
++ * one our driver can handled. This code checks to see if
++ * it can allocate all necessary resources then calls the
++ * nand layer to look for devices
++ */
++static int s3c_nand_probe(struct platform_device *pdev)
++{
++ struct s3c_nand_mtd_info *plat_info = pdev->dev.platform_data;
++ struct mtd_partition *partition_info = (struct mtd_partition *)plat_info->partition;
++ struct nand_chip *nand;
++ struct resource *res;
++ int err = 0;
++ int ret = 0;
++ int i, j, size;
++
++#if defined(CONFIG_MTD_NAND_S3C_HWECC)
++ struct nand_flash_dev *type = NULL;
++ u_char tmp;
++#endif
++
++ /* get the clock source and enable it */
++
++ s3c_nand.clk = clk_get(&pdev->dev, "nand");
++ if (IS_ERR(s3c_nand.clk)) {
++ dev_err(&pdev->dev, "failed to get clock");
++ err = -ENOENT;
++ goto exit_error;
++ }
++
++ clk_enable(s3c_nand.clk);
++
++ /* allocate and map the resource */
++
++ /* currently we assume we have the one resource */
++ res = pdev->resource;
++ size = res->end - res->start + 1;
++
++ s3c_nand.area = request_mem_region(res->start, size, pdev->name);
++
++ if (s3c_nand.area == NULL) {
++ dev_err(&pdev->dev, "cannot reserve register region\n");
++ err = -ENOENT;
++ goto exit_error;
++ }
++
++ s3c_nand.device = &pdev->dev;
++ s3c_nand.regs = ioremap(res->start, size);
++
++ if (s3c_nand.regs == NULL) {
++ dev_err(&pdev->dev, "cannot reserve register region\n");
++ err = -EIO;
++ goto exit_error;
++ }
++
++ /* allocate memory for MTD device structure and private data */
++ s3c_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
++
++ if (!s3c_mtd) {
++ printk("Unable to allocate NAND MTD dev structure.\n");
++ return -ENOMEM;
++ }
++
++ /* Get pointer to private data */
++ nand = (struct nand_chip *) (&s3c_mtd[1]);
++
++ /* Initialize structures */
++ memset((char *) s3c_mtd, 0, sizeof(struct mtd_info));
++ memset((char *) nand, 0, sizeof(struct nand_chip));
++
++ /* Link the private data with the MTD structure */
++ s3c_mtd->priv = nand;
++
++ for (i = 0; i < plat_info->chip_nr; i++) {
++ nand->IO_ADDR_R = (char *)(s3c_nand.regs+S3C2440_NFDATA);
++ nand->IO_ADDR_W = (char *)(s3c_nand.regs+S3C2440_NFDATA);
++ nand->cmd_ctrl = s3c_nand_hwcontrol;
++ nand->dev_ready = s3c_nand_device_ready;
++ nand->scan_bbt = s3c_nand_scan_bbt;
++ nand->options = 0;
++
++#if defined(CONFIG_MTD_NAND_S3C_CACHEDPROG)
++ nand->options |= NAND_CACHEPRG;
++#endif
++
++#if defined(CONFIG_MTD_NAND_S3C_HWECC)
++ nand->ecc.mode = NAND_ECC_HW;
++ nand->ecc.hwctl = s3c_nand_enable_hwecc;
++ nand->ecc.calculate = s3c_nand_calculate_ecc;
++ nand->ecc.correct = s3c_nand_correct_data;
++
++ s3c_nand_hwcontrol(0, NAND_CMD_READID, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
++ s3c_nand_hwcontrol(0, 0x00, NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
++ s3c_nand_hwcontrol(0, 0x00, NAND_NCE | NAND_ALE);
++ s3c_nand_hwcontrol(0, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
++ s3c_nand_device_ready(0);
++
++ tmp = readb(nand->IO_ADDR_R); /* Maf. ID */
++ tmp = readb(nand->IO_ADDR_R); /* Device ID */
++
++ for (j = 0; nand_flash_ids[j].name != NULL; j++) {
++ if (tmp == nand_flash_ids[j].id) {
++ type = &nand_flash_ids[j];
++ break;
++ }
++ }
++
++ if (!type) {
++ printk("Unknown NAND Device.\n");
++ goto exit_error;
++ }
++
++ nand->cellinfo = readb(nand->IO_ADDR_R); /* 3rd byte */
++ tmp = readb(nand->IO_ADDR_R); /* 4th byte */
++
++ if (!type->pagesize) {
++ if (((nand->cellinfo >> 2) & 0x3) == 0) {
++ nand_type = S3C_NAND_TYPE_SLC;
++ nand->ecc.size = 512;
++ nand->ecc.bytes = 4;
++
++ if ((1024 << (tmp & 0x3)) > 512) {
++ nand->ecc.read_page = s3c_nand_read_page_1bit;
++ nand->ecc.write_page = s3c_nand_write_page_1bit;
++ nand->ecc.read_oob = s3c_nand_read_oob_1bit;
++ nand->ecc.write_oob = s3c_nand_write_oob_1bit;
++ nand->ecc.layout = &s3c_nand_oob_64;
++ } else {
++ nand->ecc.layout = &s3c_nand_oob_16;
++ }
++ } else {
++ nand_type = S3C_NAND_TYPE_MLC;
++ nand->options |= NAND_NO_SUBPAGE_WRITE; /* NOP = 1 if MLC */
++ nand->ecc.read_page = s3c_nand_read_page_4bit;
++ nand->ecc.write_page = s3c_nand_write_page_4bit;
++ nand->ecc.size = 512;
++ nand->ecc.bytes = 8; /* really 7 bytes */
++ nand->ecc.layout = &s3c_nand_oob_mlc_64;
++ }
++ } else {
++ nand_type = S3C_NAND_TYPE_SLC;
++ nand->ecc.size = 512;
++ nand->cellinfo = 0;
++ nand->ecc.bytes = 4;
++ nand->ecc.layout = &s3c_nand_oob_16;
++ }
++
++ printk("S3C NAND Driver is using hardware ECC.\n");
++#else
++ nand->ecc.mode = NAND_ECC_SOFT;
++ printk("S3C NAND Driver is using software ECC.\n");
++#endif
++ if (nand_scan(s3c_mtd, 1)) {
++ ret = -ENXIO;
++ goto exit_error;
++ }
++
++ /* Register the partitions */
++ add_mtd_partitions(s3c_mtd, partition_info, plat_info->mtd_part_nr);
++ }
++
++ pr_debug("initialized ok\n");
++ return 0;
++
++exit_error:
++ kfree(s3c_mtd);
++
++ return ret;
++}
++
++
++/* PM Support */
++#if defined(CONFIG_PM)
++static int s3c_nand_suspend(struct platform_device *dev, pm_message_t pm)
++{
++
++ return 0;
++}
++
++static int s3c_nand_resume(struct platform_device *dev)
++{
++
++ return 0;
++}
++
++#else
++#define s3c_nand_suspend NULL
++#define s3c_nand_resume NULL
++#endif
++
++/* device management functions */
++static int s3c_nand_remove(struct platform_device *dev)
++{
++ platform_set_drvdata(dev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver s3c_nand_driver = {
++ .probe = s3c_nand_probe,
++ .remove = s3c_nand_remove,
++ .suspend = s3c_nand_suspend,
++ .resume = s3c_nand_resume,
++ .driver = {
++ .name = "s3c-nand",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init s3c_nand_init(void)
++{
++ printk("S3C NAND Driver, (c) 2007 Samsung Electronics\n");
++ return platform_driver_register(&s3c_nand_driver);
++}
++
++static void __exit s3c_nand_exit(void)
++{
++ platform_driver_unregister(&s3c_nand_driver);
++}
++
++module_init(s3c_nand_init);
++module_exit(s3c_nand_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
++MODULE_DESCRIPTION("S3C MTD NAND driver");
+diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
+index 4d2eacf..f77301f 100644
+--- a/drivers/mtd/onenand/Makefile
++++ b/drivers/mtd/onenand/Makefile
+@@ -3,7 +3,7 @@
+ #
+
+ # Core functionality.
+-obj-$(CONFIG_MTD_ONENAND) += onenand.o
++obj-$(CONFIG_MTD_ONENAND) += onenand.o onenand_bbt.o
+
+ # Board specific.
+ obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o
+@@ -11,4 +11,10 @@ obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o
+ # Simulator
+ obj-$(CONFIG_MTD_ONENAND_SIM) += onenand_sim.o
+
+-onenand-objs = onenand_base.o onenand_bbt.o
++ifeq ($(CONFIG_CPU_S3C6400),y)
++onenand-objs = s3c_onenand.o
++else ifeq ($(CONFIG_CPU_S3C6410),y)
++onenand-objs = s3c_onenand.o
++else
++onenand-objs = onenand_base.o
++endif
+diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c
+index aecdd50..58993c3 100644
+--- a/drivers/mtd/onenand/onenand_bbt.c
++++ b/drivers/mtd/onenand/onenand_bbt.c
+@@ -13,9 +13,15 @@
+ */
+
+ #include <linux/slab.h>
+-#include <linux/mtd/mtd.h>
++#include <linux/mtd/mtd.h>
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#include "s3c_onenand.h"
++#else
+ #include <linux/mtd/onenand.h>
+-#include <linux/mtd/compatmac.h>
++#endif
++
++#include <linux/mtd/compatmac.h>
+
+ extern int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
+ struct mtd_oob_ops *ops);
+diff --git a/drivers/mtd/onenand/s3c_onenand.c b/drivers/mtd/onenand/s3c_onenand.c
+new file mode 100644
+index 0000000..3de2f14
+--- /dev/null
++++ b/drivers/mtd/onenand/s3c_onenand.c
+@@ -0,0 +1,2636 @@
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/interrupt.h>
++#include <linux/jiffies.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/io.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#include <linux/dma-mapping.h>
++#include "s3c_onenand.h"
++
++#undef CONFIG_MTD_ONENAND_CHECK_SPEED
++#undef DEBUG_ONENAND
++
++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED
++#include <asm/arch/regs-gpio.h>
++#endif
++
++#ifdef DEBUG_ONENAND
++#define dbg(x...) printk(x)
++#else
++#define dbg(x...) do { } while (0)
++#endif
++
++#if defined(CONFIG_CPU_S3C6400)
++#define onenand_phys_to_virt(x) (void __iomem *)(chip->dev_base + (x & 0xffffff))
++#define onenand_virt_to_phys(x) (void __iomem *)(ONENAND_AHB_ADDR + (x & 0xffffff))
++#else
++#define onenand_phys_to_virt(x) (void __iomem *)(chip->dev_base + (x & 0x3ffffff))
++#define onenand_virt_to_phys(x) (void __iomem *)(ONENAND_AHB_ADDR + (x & 0x3ffffff))
++#endif
++
++/**
++ * onenand_oob_64 - oob info for large (2KB) page
++ */
++static struct nand_ecclayout onenand_oob_64 = {
++ .eccbytes = 20,
++ .eccpos = {
++ 8, 9, 10, 11, 12,
++ 24, 25, 26, 27, 28,
++ 40, 41, 42, 43, 44,
++ 56, 57, 58, 59, 60,
++ },
++
++ /* For YAFFS2 tag information */
++ .oobfree = {
++ {2, 6}, {13, 3}, {18, 6}, {29, 3},
++ {34, 6}, {45, 3}, {50, 6}, {61, 3}}
++#if 0
++ .oobfree = {
++ {2, 6}, {14, 2}, {18, 6}, {30, 2},
++ {34, 6}, {46, 2}, {50, 6}}
++
++ .oobfree = {
++ {2, 3}, {14, 2}, {18, 3}, {30, 2},
++ {34, 3}, {46, 2}, {50, 3}, {62, 2}
++ }
++#endif
++};
++
++/**
++ * onenand_oob_32 - oob info for middle (1KB) page
++ */
++static struct nand_ecclayout onenand_oob_32 = {
++ .eccbytes = 10,
++ .eccpos = {
++ 8, 9, 10, 11, 12,
++ 24, 25, 26, 27, 28,
++ },
++ .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
++};
++
++static const unsigned char ffchars[] = {
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
++};
++
++static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops);
++
++
++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
++static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to, size_t len);
++static int onenand_verify_ops(struct mtd_info *mtd, struct mtd_oob_ops *ops, loff_t to, size_t len);
++#endif
++
++/**
++ * dma client
++ */
++static struct s3c2410_dma_client s3c6400onenand_dma_client = {
++ .name = "s3c6400-onenand-dma",
++};
++
++static unsigned int onenand_readl(void __iomem *addr)
++{
++ return readl(addr);
++}
++
++static void onenand_writel(unsigned int value, void __iomem *addr)
++{
++ writel(value, addr);
++}
++
++static void onenand_irq_wait(struct onenand_chip *chip, int stat)
++{
++ while (!chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & stat);
++}
++
++static void onenand_irq_ack(struct onenand_chip *chip, int stat)
++{
++ chip->write(stat, chip->base + ONENAND_REG_INT_ERR_ACK);
++}
++
++static int onenand_irq_pend(struct onenand_chip *chip, int stat)
++{
++ return (chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & stat);
++}
++
++static void onenand_irq_wait_ack(struct onenand_chip *chip, int stat)
++{
++ onenand_irq_wait(chip, stat);
++ onenand_irq_ack(chip, stat);
++}
++
++static int onenand_blkrw_complete(struct onenand_chip *chip, int cmd)
++{
++ int cmp_bit = 0, fail_bit = 0, ret = 0;
++
++ if (cmd == ONENAND_CMD_READ) {
++ cmp_bit = ONENAND_INT_ERR_LOAD_CMP;
++ fail_bit = ONENAND_INT_ERR_LD_FAIL_ECC_ERR;
++ } else if (cmd == ONENAND_CMD_PROG) {
++ cmp_bit = ONENAND_INT_ERR_PGM_CMP;
++ fail_bit = ONENAND_INT_ERR_PGM_FAIL;
++ } else {
++ ret = 1;
++ }
++
++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_INT_ACT);
++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_BLK_RW_CMP);
++ onenand_irq_wait_ack(chip, cmp_bit);
++
++ if (onenand_irq_pend(chip, fail_bit)) {
++ onenand_irq_ack(chip, fail_bit);
++ ret = 1;
++ }
++
++ return ret;
++}
++
++/**
++ * onenand_read_burst
++ *
++ * 16 Burst read: performance is improved up to 40%.
++ */
++static void onenand_read_burst(void *dest, const void *src, size_t len)
++{
++ int count;
++
++ if (len % 16 != 0)
++ return;
++
++ count = len / 16;
++
++ __asm__ __volatile__(
++ " stmdb r13!, {r0-r3,r9-r12}\n"
++ " mov r2, %0\n"
++ "read_page:\n"
++ " ldmia r1, {r9-r12}\n"
++ " stmia r0!, {r9-r12}\n"
++ " subs r2, r2, #0x1\n"
++ " bne read_page\n"
++ " ldmia r13!, {r0-r3,r9-r12}\n"
++ ::"r" (count));
++}
++
++/**
++ *
++ * onenand_dma_finish
++ *
++ */
++void onenand_dma_finish(struct s3c2410_dma_chan *dma_ch, void *buf_id,
++ int size, enum s3c2410_dma_buffresult result)
++{
++ struct onenand_chip *chip = (struct onenand_chip *) buf_id;
++ complete(chip->done);
++}
++
++/**
++ *
++ * onenand_read_dma
++ *
++ */
++#if 1
++static void onenand_read_dma(struct onenand_chip *chip, unsigned int *dst, void __iomem *src, size_t len)
++{
++ void __iomem *phys_addr = onenand_virt_to_phys((u_int) src);
++
++ DECLARE_COMPLETION_ONSTACK(complete);
++ chip->done = &complete;
++
++#if 0
++ if (s3c_dma_request(chip->dma, chip->dma_ch, &s3c6400onenand_dma_client, NULL)) {
++ printk(KERN_WARNING "Unable to get DMA channel.\n");
++ return;
++ }
++
++ s3c_dma_set_buffdone_fn(chip->dma, chip->dma_ch, onenand_dma_finish);
++ s3c_dma_devconfig(chip->dma, chip->dma_ch, S3C_DMA_MEM2MEM, 1, 0, (u_long) phys_addr);
++ s3c_dma_config(chip->dma, chip->dma_ch, ONENAND_DMA_TRANSFER_WORD, ONENAND_DMA_TRANSFER_WORD);
++ s3c_dma_setflags(chip->dma, chip->dma_ch, S3C2410_DMAF_AUTOSTART);
++ consistent_sync((void *) dst, len, DMA_FROM_DEVICE);
++ s3c_dma_enqueue(chip->dma, chip->dma_ch, (void *) chip, (dma_addr_t) virt_to_dma(NULL, dst), len);
++
++ wait_for_completion(&complete);
++
++ s3c_dma_free(chip->dma, chip->dma_ch, &s3c6400onenand_dma_client);
++#else
++ if (s3c2410_dma_request(DMACH_ONENAND_IN, &s3c6400onenand_dma_client, NULL)) {
++ printk(KERN_WARNING "Unable to get DMA channel.\n");
++ return;
++ }
++
++ s3c2410_dma_set_buffdone_fn(DMACH_ONENAND_IN, onenand_dma_finish);
++ s3c2410_dma_devconfig(DMACH_ONENAND_IN, S3C_DMA_MEM2MEM_P, 1, (u_long) phys_addr);
++ s3c2410_dma_config(DMACH_ONENAND_IN, ONENAND_DMA_TRANSFER_WORD, ONENAND_DMA_TRANSFER_WORD);
++ s3c2410_dma_setflags(DMACH_ONENAND_IN, S3C2410_DMAF_AUTOSTART);
++ dma_cache_maint((void *) dst, len, DMA_FROM_DEVICE);
++ s3c2410_dma_enqueue(DMACH_ONENAND_IN, (void *) chip, (dma_addr_t) virt_to_dma(NULL, dst), len);
++
++ wait_for_completion(&complete);
++
++ s3c2410_dma_free(DMACH_ONENAND_IN, &s3c6400onenand_dma_client);
++#endif
++}
++#else
++extern s3c_dma_mainchan_t s3c_mainchans[S3C_DMA_CONTROLLERS];
++extern void s3c_enable_dmac(unsigned int channel);
++extern void s3c_disable_dmac(unsigned int channel);
++static void onenand_read_dma(struct onenand_chip *chip, unsigned int *dst, void __iomem *src, size_t len)
++{
++ s3c_dma_mainchan_t *mainchan = &s3c_mainchans[chip->dma];
++ void __iomem *phys_addr = onenand_virt_to_phys((u_int) src);
++
++ s3c_enable_dmac(chip->dma);
++ s3c_dma_set_buffdone_fn(chip->dma, chip->dma_ch, onenand_dma_finish);
++ s3c_dma_devconfig(chip->dma, chip->dma_ch, S3C_DMA_MEM2MEM_P, 1, 0, (u_long) phys_addr);
++ s3c_dma_config(chip->dma, chip->dma_ch, ONENAND_DMA_TRANSFER_WORD, ONENAND_DMA_TRANSFER_WORD);
++ s3c_dma_setflags(chip->dma, chip->dma_ch, S3C_DMAF_AUTOSTART);
++ consistent_sync((void *) dst, len, DMA_FROM_DEVICE);
++ s3c_dma_enqueue(chip->dma, chip->dma_ch, (void *) chip, (dma_addr_t) virt_to_dma(NULL, dst), len);
++
++ while (readl(mainchan->regs + S3C_DMAC_ENBLD_CHANNELS) & (1 << chip->dma_ch));
++
++ s3c_dma_ctrl(chip->dma, chip->dma_ch, S3C_DMAOP_STOP);
++ s3c_disable_dmac(chip->dma);
++}
++#endif
++
++/**
++ * onenand_command_map - [DEFAULT] Get command type
++ * @param cmd command
++ * @return command type (00, 01, 10, 11)
++ *
++ */
++static int onenand_command_map(int cmd)
++{
++ int type = ONENAND_CMD_MAP_FF;
++
++ switch (cmd) {
++ case ONENAND_CMD_READ:
++ case ONENAND_CMD_READOOB:
++ case ONENAND_CMD_PROG:
++ case ONENAND_CMD_PROGOOB:
++ type = ONENAND_CMD_MAP_01;
++ break;
++
++ case ONENAND_CMD_UNLOCK:
++ case ONENAND_CMD_LOCK:
++ case ONENAND_CMD_LOCK_TIGHT:
++ case ONENAND_CMD_UNLOCK_ALL:
++ case ONENAND_CMD_ERASE:
++ case ONENAND_CMD_OTP_ACCESS:
++ case ONENAND_CMD_PIPELINE_READ:
++ case ONENAND_CMD_PIPELINE_WRITE:
++ type = ONENAND_CMD_MAP_10;
++ break;
++
++ case ONENAND_CMD_RESET:
++ case ONENAND_CMD_READID:
++ type = ONENAND_CMD_MAP_11;
++ break;
++ default:
++ type = ONENAND_CMD_MAP_FF;
++ break;
++ }
++
++ return type;
++}
++
++/**
++ * onenand_addr_field - [DEFAULT] Generate address field
++ * @param dev_id device id
++ * @param fba block number
++ * @param fpa page number
++ * @param fsa sector number
++ * @return address field
++ *
++ * Refer to Table 7-1 MEM_ADDR Fields in S3C6400/10 User's Manual
++ */
++#if defined(CONFIG_CPU_S3C6400)
++static u_int onenand_addr_field(int dev_id, int fba, int fpa, int fsa)
++{
++ u_int mem_addr = 0;
++ int ddp, density;
++
++ ddp = dev_id & ONENAND_DEVICE_IS_DDP;
++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
++
++ switch (density & 0xf) {
++ case ONENAND_DEVICE_DENSITY_128Mb:
++ mem_addr = (((fba & ONENAND_FBA_MASK_128Mb) << ONENAND_FBA_SHIFT_128Mb) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_128Mb) | \
++ (fsa << ONENAND_FSA_SHIFT));
++ break;
++
++ case ONENAND_DEVICE_DENSITY_256Mb:
++ mem_addr = (((fba & ONENAND_FBA_MASK_256Mb) << ONENAND_FBA_SHIFT_256Mb) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_256Mb) | \
++ (fsa << ONENAND_FSA_SHIFT));
++ break;
++
++ case ONENAND_DEVICE_DENSITY_512Mb:
++ mem_addr = (((fba & ONENAND_FBA_MASK_512Mb) << ONENAND_FBA_SHIFT_512Mb) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_512Mb) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ break;
++
++ case ONENAND_DEVICE_DENSITY_1Gb:
++ if (ddp) {
++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_1Gb) | \
++ ((fba & ONENAND_FBA_MASK_1Gb_DDP) << ONENAND_FBA_SHIFT_1Gb_DDP) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_1Gb_DDP) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ } else {
++ mem_addr = (((fba & ONENAND_FBA_MASK_1Gb) << ONENAND_FBA_SHIFT_1Gb) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_1Gb) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ }
++
++ break;
++
++ case ONENAND_DEVICE_DENSITY_2Gb:
++ if (ddp) {
++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_2Gb) | \
++ ((fba & ONENAND_FBA_MASK_2Gb_DDP) << ONENAND_FBA_SHIFT_2Gb_DDP) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_2Gb_DDP) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ } else {
++ mem_addr = (((fba & ONENAND_FBA_MASK_2Gb) << ONENAND_FBA_SHIFT_2Gb) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_2Gb) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ }
++
++ break;
++
++ case ONENAND_DEVICE_DENSITY_4Gb:
++ if (ddp) {
++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_4Gb) | \
++ ((fba & ONENAND_FBA_MASK_4Gb_DDP) << ONENAND_FBA_SHIFT_4Gb_DDP) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_4Gb_DDP) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ } else {
++ mem_addr = (((fba & ONENAND_FBA_MASK_4Gb) << ONENAND_FBA_SHIFT_4Gb) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_4Gb) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ }
++
++ break;
++ }
++
++ return mem_addr;
++}
++#else
++static u_int onenand_addr_field(int dev_id, int fba, int fpa, int fsa)
++{
++ u_int mem_addr = 0;
++ int ddp, density;
++
++ ddp = dev_id & ONENAND_DEVICE_IS_DDP;
++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
++
++ switch (density & 0xf) {
++ case ONENAND_DEVICE_DENSITY_128Mb:
++ mem_addr = (((fba & ONENAND_FBA_MASK_128Mb) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ (fsa << ONENAND_FSA_SHIFT));
++ break;
++
++ case ONENAND_DEVICE_DENSITY_256Mb:
++ mem_addr = (((fba & ONENAND_FBA_MASK_256Mb) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ (fsa << ONENAND_FSA_SHIFT));
++ break;
++
++ case ONENAND_DEVICE_DENSITY_512Mb:
++ mem_addr = (((fba & ONENAND_FBA_MASK_512Mb) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ break;
++
++ case ONENAND_DEVICE_DENSITY_1Gb:
++ if (ddp) {
++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_1Gb) | \
++ ((fba & ONENAND_FBA_MASK_1Gb_DDP) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ } else {
++ mem_addr = (((fba & ONENAND_FBA_MASK_1Gb) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ }
++
++ break;
++
++ case ONENAND_DEVICE_DENSITY_2Gb:
++ if (ddp) {
++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_2Gb) | \
++ ((fba & ONENAND_FBA_MASK_2Gb_DDP) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ } else {
++ mem_addr = (((fba & ONENAND_FBA_MASK_2Gb) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ }
++
++ break;
++
++ case ONENAND_DEVICE_DENSITY_4Gb:
++ if (ddp) {
++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_1Gb) | \
++ ((fba & ONENAND_FBA_MASK_4Gb_DDP) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ } else {
++ mem_addr = (((fba & ONENAND_FBA_MASK_4Gb) << ONENAND_FBA_SHIFT) | \
++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \
++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT));
++ }
++
++ break;
++ }
++
++ return mem_addr;
++}
++#endif
++
++/**
++ * onenand_command_address - [DEFAULT] Generate command address
++ * @param mtd MTD device structure
++ * @param cmd_type command type
++ * @param fba block number
++ * @param fpa page number
++ * @param fsa sector number
++ * @param onenand_addr onenand device address to access directly (command 00/11)
++ * @return command address
++ *
++ * Refer to 'Command Mapping' in S3C6400/10 User's Manual
++ */
++static u_int onenand_command_address(struct mtd_info *mtd, int cmd_type, int fba, int fpa, int fsa, int onenand_addr)
++{
++ struct onenand_chip *chip = mtd->priv;
++ u_int cmd_addr = (ONENAND_AHB_ADDR | (cmd_type << ONENAND_CMD_SHIFT));
++ int dev_id;
++
++ dev_id = chip->read(chip->base + ONENAND_REG_DEVICE_ID);
++
++ switch (cmd_type) {
++ case ONENAND_CMD_MAP_00:
++ cmd_addr |= ((onenand_addr & 0xffff) << 1);
++ break;
++
++ case ONENAND_CMD_MAP_01:
++ case ONENAND_CMD_MAP_10:
++ cmd_addr |= (onenand_addr_field(dev_id, fba, fpa, fsa) & ONENAND_MEM_ADDR_MASK);
++ break;
++
++ case ONENAND_CMD_MAP_11:
++ cmd_addr |= ((onenand_addr & 0xffff) << 2);
++ break;
++
++ default:
++ cmd_addr = 0;
++ break;
++ }
++
++ return cmd_addr;
++}
++
++/**
++ * onenand_command - [DEFAULT] Generate command address
++ * @param mtd MTD device structure
++ * @param cmd command
++ * @param addr onenand device address
++ * @return command address
++ *
++ */
++static u_int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int sectors = 4, onenand_addr = -1;
++ int cmd_type, fba = 0, fpa = 0, fsa = 0, page;
++ u_int cmd_addr;
++
++ cmd_type = onenand_command_map(cmd);
++
++ switch (cmd) {
++ case ONENAND_CMD_UNLOCK:
++ case ONENAND_CMD_UNLOCK_ALL:
++ case ONENAND_CMD_LOCK:
++ case ONENAND_CMD_LOCK_TIGHT:
++ case ONENAND_CMD_ERASE:
++ fba = (int) (addr >> chip->erase_shift);
++ page = -1;
++ break;
++
++ default:
++ fba = (int) (addr >> chip->erase_shift);
++ page = (int) (addr >> chip->page_shift);
++ page &= chip->page_mask;
++ fpa = page & ONENAND_FPA_MASK;
++ fsa = sectors & ONENAND_FSA_MASK;
++ break;
++ }
++
++ cmd_addr = onenand_command_address(mtd, cmd_type, fba, fpa, fsa, onenand_addr);
++
++ if (!cmd_addr) {
++ printk("Command address mapping failed\n");
++ return -1;
++ }
++
++ return cmd_addr;
++}
++
++static int onenand_get_device(struct mtd_info *mtd, int new_state)
++{
++/* disable now: future work */
++#if 0
++ struct onenand_chip *chip = mtd->priv;
++ DECLARE_WAITQUEUE(wait, current);
++
++ /*
++ * Grab the lock and see if the device is available
++ */
++ while (1) {
++ spin_lock(&chip->chip_lock);
++ if (chip->state == FL_READY) {
++ chip->state = new_state;
++ spin_unlock(&chip->chip_lock);
++ break;
++ }
++ if (new_state == FL_PM_SUSPENDED) {
++ spin_unlock(&chip->chip_lock);
++ return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
++ }
++ set_current_state(TASK_UNINTERRUPTIBLE);
++ add_wait_queue(&chip->wq, &wait);
++ spin_unlock(&chip->chip_lock);
++ schedule();
++ remove_wait_queue(&chip->wq, &wait);
++ }
++#endif
++ return 0;
++}
++
++/**
++ * onenand_release_device - [GENERIC] release chip
++ * @param mtd MTD device structure
++ *
++ * Deselect, release chip lock and wake up anyone waiting on the device
++ */
++static void onenand_release_device(struct mtd_info *mtd)
++{
++/* disable now: future work */
++#if 0
++ struct onenand_chip *chip = mtd->priv;
++
++ /* Release the chip */
++ spin_lock(&chip->chip_lock);
++ chip->state = FL_READY;
++ wake_up(&chip->wq);
++ spin_unlock(&chip->chip_lock);
++#endif
++}
++
++/**
++ * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan
++ * @param mtd MTD device structure
++ * @param from offset to read from
++ * @param ops oob operation description structure
++ *
++ * OneNAND read out-of-band data from the spare area for bbt scan
++ */
++int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
++ struct mtd_oob_ops *ops)
++{
++ struct onenand_chip *chip = mtd->priv;
++ void __iomem *cmd_addr;
++ int i;
++ size_t len = ops->ooblen;
++ u_char *buf = ops->oobbuf;
++ u_int bbinfo;
++ u_char *bb_poi = (u_char *)&bbinfo;
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len);
++
++ /* Initialize return value */
++ ops->oobretlen = 0;
++
++ /* Do not allow reads past end of device */
++ if (unlikely((from + len) > mtd->size)) {
++ printk(KERN_ERR "onenand_bbt_read_oob: Attempt read beyond end of device\n");
++ return ONENAND_BBT_READ_FATAL_ERROR;
++ }
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_READING);
++
++ /* on the TRANSFER SPARE bit */
++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* get start address to read data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from));
++
++ switch (chip->options & ONENAND_READ_MASK) {
++ case ONENAND_READ_BURST:
++ onenand_read_burst((u_int *)chip->page_buf, cmd_addr, mtd->writesize);
++ onenand_read_burst((u_int *)chip->oob_buf, cmd_addr, mtd->oobsize);
++ buf[0] = chip->oob_buf[0];
++ buf[1] = chip->oob_buf[1];
++ break;
++
++ case ONENAND_READ_DMA:
++ onenand_read_dma(chip, (u_int *)chip->page_buf, cmd_addr, mtd->writesize);
++ onenand_read_dma(chip, (u_int *)chip->oob_buf, cmd_addr, mtd->oobsize);
++ buf[0] = chip->oob_buf[0];
++ buf[1] = chip->oob_buf[1];
++ break;
++
++ case ONENAND_READ_POLLING:
++ /* read main data and throw into garbage box */
++ for (i = 0; i < (mtd->writesize / 4); i++)
++ chip->read(cmd_addr);
++
++ /* read first 4 bytes of spare data */
++ bbinfo = chip->read(cmd_addr);
++ buf[0] = bb_poi[0];
++ buf[1] = bb_poi[1];
++
++ for (i = 0; i < (mtd->oobsize / 4) - 1; i++)
++ chip->read(cmd_addr);
++ break;
++ }
++
++ onenand_blkrw_complete(chip, ONENAND_CMD_READ);
++
++ /* off the TRANSFER SPARE bit */
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ ops->oobretlen = len;
++ return 0;
++}
++
++/**
++ * onenand_block_isbad_nolock - [GENERIC] Check if a block is marked bad
++ * @param mtd MTD device structure
++ * @param ofs offset from device start
++ * @param allowbbt 1, if its allowed to access the bbt area
++ *
++ * Check, if the block is bad. Either by reading the bad block table or
++ * calling of the scan function.
++ */
++static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allowbbt)
++{
++ struct onenand_chip *chip = mtd->priv;
++
++ if (chip->options & ONENAND_CHECK_BAD) {
++ struct bbm_info *bbm = chip->bbm;
++
++ /* Return info from the table */
++ return bbm->isbad_bbt(mtd, ofs, allowbbt);
++ } else
++ return 0;
++}
++
++/**
++ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
++ * @param mtd MTD device structure
++ * @param ofs offset relative to mtd start
++ *
++ * Check whether the block is bad
++ */
++static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
++{
++ /* Check for invalid offset */
++ if (ofs > mtd->size)
++ return -EINVAL;
++
++ return onenand_block_isbad_nolock(mtd, ofs, 0);
++}
++
++/**
++ * onenand_default_block_markbad - [DEFAULT] mark a block bad
++ * @param mtd MTD device structure
++ * @param ofs offset from device start
++ *
++ * This is the default implementation, which can be overridden by
++ * a hardware specific driver.
++ */
++static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++ struct onenand_chip *this = mtd->priv;
++ struct bbm_info *bbm = this->bbm;
++ u_char buf[2] = {0, 0};
++ int block;
++ struct mtd_oob_ops ops = {
++ .mode = MTD_OOB_PLACE,
++ .ooblen = 2,
++ .oobbuf = buf,
++ .ooboffs = 0,
++ };
++
++ /* Get block number */
++ block = ((int) ofs) >> bbm->bbt_erase_shift;
++ if (bbm->bbt)
++ bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
++
++ /* We write two bytes, so we dont have to mess with 16 bit access */
++ ofs += mtd->oobsize + (bbm->badblockpos & ~0x01);
++ return onenand_write_oob_nolock(mtd, ofs, &ops);
++}
++
++
++/**
++ * onenand_set_pipeline - [MTD Interface] Set pipeline ahead
++ * @param mtd MTD device structure
++ * @param from offset to read from
++ * @param len number of bytes to read
++ *
++ */
++static int onenand_set_pipeline(struct mtd_info *mtd, loff_t from, size_t len)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int page_cnt = (int) (len >> chip->page_shift);
++ void __iomem *cmd_addr;
++
++ if (len % mtd->writesize > 0)
++ page_cnt++;
++
++ if (page_cnt > 1) {
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PIPELINE_READ, from));
++ chip->write(ONENAND_DATAIN_PIPELINE_READ | page_cnt, cmd_addr);
++ }
++
++ return 0;
++}
++
++/**
++ * onenand_read - [MTD Interface] Read data from flash
++ * @param mtd MTD device structure
++ * @param from offset to read from
++ * @param len number of bytes to read
++ * @param retlen pointer to variable to store the number of read bytes
++ * @param buf the databuffer to put data
++ *
++ */
++static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
++ size_t *retlen, u_char *buf)
++{
++ struct onenand_chip *chip = mtd->priv;
++ struct mtd_ecc_stats stats;
++ int i, ret = 0, read = 0, col, thislen;
++ u_int *buf_poi = (u_int *) chip->page_buf;
++ void __iomem *cmd_addr;
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i, col = %i\n", (unsigned int) from, (int) len, (int) col);
++
++ /* Do not allow reads past end of device */
++ if ((from + len) > mtd->size) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: Attempt read beyond end of device\n");
++ *retlen = 0;
++ return -EINVAL;
++ }
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_READING);
++
++ /* TODO handling oob */
++ stats = mtd->ecc_stats;
++
++ /* column (start offset to read) */
++ col = (int)(from & (mtd->writesize - 1));
++
++ if (chip->options & ONENAND_PIPELINE_AHEAD)
++ onenand_set_pipeline(mtd, from, len);
++
++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED
++ if (len > 100000) {
++ writel((readl(S3C_GPNCON) & ~(0x3 << 30)) | (0x1 << 30), S3C_GPNCON);
++ writel(1 << 15, S3C_GPNDAT);
++ }
++#endif
++
++ //while (!ret) {
++ while (1) {
++ if (chip->options & ONENAND_CHECK_BAD) {
++ if (onenand_block_isbad(mtd, from)) {
++ printk (KERN_WARNING "\nonenand_read: skipped to read from a bad block at addr 0x%08x.\n", (unsigned int) from);
++ from += (1 << chip->erase_shift);
++
++ if (col != 0)
++ col = (int)(from & (mtd->writesize - 1));
++
++ continue;
++ }
++ }
++
++ /* get start address to read data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from));
++
++ switch (chip->options & ONENAND_READ_MASK) {
++ case ONENAND_READ_BURST:
++ onenand_read_burst(buf_poi, cmd_addr, mtd->writesize);
++ break;
++
++ case ONENAND_READ_DMA:
++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->writesize);
++ break;
++
++ case ONENAND_READ_POLLING:
++ for (i = 0; i < (mtd->writesize / 4); i++)
++ *buf_poi++ = chip->read(cmd_addr);
++
++ buf_poi -= (mtd->writesize / 4);
++ break;
++
++ default:
++ printk("onenand_read: read mode undefined.\n");
++ return -1;
++ }
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) {
++ printk(KERN_WARNING "onenand_read: Read operation failed:0x%08x.\n", (unsigned int)from);
++#if 0
++ return -1;
++#endif
++ }
++
++ thislen = min_t(int, mtd->writesize - col, len - read);
++ memcpy(buf, chip->page_buf + col, thislen);
++
++ read += thislen;
++
++ if (read == len)
++ break;
++
++ buf += thislen;
++ from += mtd->writesize;
++ col = 0;
++ }
++
++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED
++ if (len > 100000) {
++ printk("len: %d\n", len);
++ writel(0 << 15, S3C_GPNDAT);
++ }
++#endif
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ /*
++ * Return success, if no ECC failures, else -EBADMSG
++ * fs driver will take care of that, because
++ * retlen == desired len and result == -EBADMSG
++ */
++ *retlen = read;
++
++ if (mtd->ecc_stats.failed - stats.failed)
++ return -EBADMSG;
++
++ if (ret)
++ return ret;
++
++ return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
++}
++
++/**
++ * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer
++ * @param mtd MTD device structure
++ * @param buf destination address
++ * @param column oob offset to read from
++ * @param thislen oob length to read
++ */
++static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column,
++ int thislen)
++{
++ struct onenand_chip *chip = mtd->priv;
++ struct nand_oobfree *free;
++ int readcol = column;
++ int readend = column + thislen;
++ int lastgap = 0;
++ uint8_t *oob_buf = chip->oob_buf;
++
++ for (free = chip->ecclayout->oobfree; free->length; ++free) {
++ if (readcol >= lastgap)
++ readcol += free->offset - lastgap;
++ if (readend >= lastgap)
++ readend += free->offset - lastgap;
++ lastgap = free->offset + free->length;
++ }
++
++ for (free = chip->ecclayout->oobfree; free->length; ++free) {
++ int free_end = free->offset + free->length;
++ if (free->offset < readend && free_end > readcol) {
++ int st = max_t(int,free->offset,readcol);
++ int ed = min_t(int,free_end,readend);
++ int n = ed - st;
++ memcpy(buf, oob_buf + st, n);
++ buf += n;
++ } else
++ break;
++ }
++ return 0;
++}
++
++
++/**
++ * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band
++ * @param mtd MTD device structure
++ * @param from offset to read from
++ * @param ops: oob operation description structure
++ *
++ * OneNAND read main and/or out-of-band data
++ */
++static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int read = 0, thislen, column, oobsize;
++ int i, ret = 0;
++ void __iomem *cmd_addr;
++ u_int *buf_poi, *dbuf_poi;
++
++ int len = ops->ooblen;
++ u_char *buf = ops->datbuf;
++ u_char *sparebuf = ops->oobbuf;
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
++
++ /* Initialize return length value */
++ ops->retlen = 0;
++ ops->oobretlen = 0;
++
++ if (ops->mode == MTD_OOB_AUTO)
++ oobsize = chip->ecclayout->oobavail;
++ else
++ oobsize = mtd->oobsize;
++
++ column = from & (mtd->oobsize - 1);
++
++ if (unlikely(column >= oobsize)) {
++ printk(KERN_ERR "onenand_read_ops_nolock: Attempted to start read outside oob\n");
++ return -EINVAL;
++ }
++
++ /* Do not allow reads past end of device */
++ if (unlikely(from >= mtd->size ||
++ column + len > ((mtd->size >> chip->page_shift) -
++ (from >> chip->page_shift)) * oobsize)) {
++ printk(KERN_ERR "onenand_read_ops_nolock: Attempted to read beyond end of device\n");
++ return -EINVAL;
++ }
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_READING);
++
++ dbuf_poi = (u_int *)buf;
++
++ if (chip->options & ONENAND_PIPELINE_AHEAD)
++ onenand_set_pipeline(mtd, from, len);
++
++ /* on the TRANSFER SPARE bit */
++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ while (read < len) {
++ if (chip->options & ONENAND_CHECK_BAD) {
++ if (onenand_block_isbad(mtd, from)) {
++ printk (KERN_WARNING "onenand_read_ops_nolock: skipped to read oob from a bad block at addr 0x%08x.\n", (unsigned int) from);
++ from += (1 << chip->erase_shift);
++
++ if (column != 0)
++ column = from & (mtd->oobsize - 1);
++
++ continue;
++ }
++ }
++
++ /* get start address to read data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from));
++
++ thislen = oobsize - column;
++ thislen = min_t(int, thislen, len);
++
++ //if (ops->mode == MTD_OOB_AUTO)
++ buf_poi = (u_int *)chip->oob_buf;
++ //else
++ //buf_poi = (u_int *)buf;
++
++ switch (chip->options & ONENAND_READ_MASK) {
++ case ONENAND_READ_BURST:
++ onenand_read_burst(dbuf_poi, cmd_addr, mtd->writesize);
++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize);
++ break;
++
++ case ONENAND_READ_DMA:
++ onenand_read_dma(chip, dbuf_poi, cmd_addr, mtd->writesize);
++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->oobsize);
++ break;
++
++ case ONENAND_READ_POLLING:
++ /* read main data and throw into garbage box */
++ for (i = 0; i < (mtd->writesize / 4); i++)
++ *dbuf_poi = chip->read(cmd_addr);
++
++ /* read spare data */
++ for (i = 0; i < (mtd->oobsize / 4); i++)
++ *buf_poi++ = chip->read(cmd_addr);
++
++ break;
++ }
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) {
++ printk(KERN_WARNING "onenand_read_ops_nolock: Read operation failed:0x%x\n", (unsigned int)from);
++#if 0
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++ return -1;
++#endif
++ }
++
++ if (ops->mode == MTD_OOB_AUTO)
++ onenand_transfer_auto_oob(mtd, sparebuf, column, thislen);
++
++ read += thislen;
++
++ if (read == len)
++ break;
++
++ buf += thislen;
++
++ /* Read more? */
++ if (read < len) {
++ /* Page size */
++ from += mtd->writesize;
++ column = 0;
++ }
++ }
++
++ /* off the TRANSFER SPARE bit */
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ ops->retlen = mtd->writesize;
++ ops->oobretlen = read;
++
++ return ret;
++}
++
++
++/**
++ * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band
++ * @param mtd MTD device structure
++ * @param from offset to read from
++ * @param ops: oob operation description structure
++ *
++ * OneNAND read out-of-band data from the spare area
++ */
++static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int read = 0, thislen, column, oobsize;
++ int i, ret = 0;
++ void __iomem *cmd_addr;
++ u_int *buf_poi;
++
++ size_t len = ops->ooblen;
++ mtd_oob_mode_t mode = ops->mode;
++ u_char *buf = ops->oobbuf;
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
++
++ /* Initialize return length value */
++ ops->oobretlen = 0;
++
++ if (mode == MTD_OOB_AUTO)
++ oobsize = chip->ecclayout->oobavail;
++ else
++ oobsize = mtd->oobsize;
++
++ column = from & (mtd->oobsize - 1);
++
++ if (unlikely(column >= oobsize)) {
++ printk(KERN_ERR "onenand_read_oob_nolock: Attempted to start read outside oob\n");
++ return -EINVAL;
++ }
++
++ /* Do not allow reads past end of device */
++ if (unlikely(from >= mtd->size ||
++ column + len > ((mtd->size >> chip->page_shift) -
++ (from >> chip->page_shift)) * oobsize)) {
++ printk(KERN_ERR "onenand_read_oob_nolock: Attempted to read beyond end of device\n");
++ return -EINVAL;
++ }
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_READING);
++
++ if (chip->options & ONENAND_PIPELINE_AHEAD)
++ onenand_set_pipeline(mtd, from, len);
++
++ /* on the TRANSFER SPARE bit */
++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ while (read < len) {
++ if (chip->options & ONENAND_CHECK_BAD) {
++ if (onenand_block_isbad(mtd, from)) {
++ printk (KERN_WARNING "\nonenand_do_read_oob: skipped to read oob from a bad block at addr 0x%08x.\n", (unsigned int) from);
++ from += (1 << chip->erase_shift);
++
++ if (column != 0)
++ column = from & (mtd->oobsize - 1);
++
++ continue;
++ }
++ }
++
++ /* get start address to read data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from));
++
++ thislen = oobsize - column;
++ thislen = min_t(int, thislen, len);
++
++ if (mode == MTD_OOB_AUTO)
++ buf_poi = (u_int *)chip->oob_buf;
++ else
++ buf_poi = (u_int *)buf;
++
++ switch (chip->options & ONENAND_READ_MASK) {
++ case ONENAND_READ_BURST:
++ onenand_read_burst(buf_poi, cmd_addr, mtd->writesize);
++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize);
++ break;
++
++ case ONENAND_READ_DMA:
++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->writesize);
++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->oobsize);
++ break;
++
++ case ONENAND_READ_POLLING:
++ /* read main data and throw into garbage box */
++ for (i = 0; i < (mtd->writesize / 4); i++)
++ *buf_poi = chip->read(cmd_addr);
++
++ /* read spare data */
++ for (i = 0; i < (mtd->oobsize / 4); i++)
++ *buf_poi++ = chip->read(cmd_addr);
++
++ break;
++ }
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) {
++ printk(KERN_WARNING "onenand_read_oob_nolock: Read operation failed:0x%x\n", (unsigned int)from);
++#if 0
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++ return -1;
++#endif
++ }
++
++ if (mode == MTD_OOB_AUTO)
++ onenand_transfer_auto_oob(mtd, buf, column, thislen);
++
++ read += thislen;
++
++ if (read == len)
++ break;
++
++ buf += thislen;
++
++ /* Read more? */
++ if (read < len) {
++ /* Page size */
++ from += mtd->writesize;
++ column = 0;
++ }
++ }
++
++ /* off the TRANSFER SPARE bit */
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ ops->oobretlen = read;
++ return ret;
++}
++
++/**
++ * onenand_read_oob - [MTD Interface] NAND write data and/or out-of-band
++ * @mtd: MTD device structure
++ * @from: offset to read from
++ * @ops: oob operation description structure
++ */
++static int onenand_read_oob(struct mtd_info *mtd, loff_t from,
++ struct mtd_oob_ops *ops)
++{
++ int ret = 0;
++
++ switch (ops->mode) {
++ case MTD_OOB_PLACE:
++ case MTD_OOB_AUTO:
++ break;
++ case MTD_OOB_RAW:
++ /* Not implemented yet */
++ default:
++ return -EINVAL;
++ }
++
++ if (ops->datbuf != NULL)
++ ret = onenand_read_ops_nolock(mtd, from, ops);
++ else
++ ret = onenand_read_oob_nolock(mtd, from, ops);
++
++ return ret;
++}
++
++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
++/**
++ * onenand_verify_page - [GENERIC] verify the chip contents after a write
++ * @param mtd MTD device structure
++ * @param buf the databuffer to verify
++ * @param addr address to read
++ * @return 0, if ok
++ */
++static int onenand_verify_page(struct mtd_info *mtd, const u_int *buf, loff_t addr)
++{
++ struct onenand_chip *chip = mtd->priv;
++ void __iomem *cmd_addr;
++ int i, ret = 0;
++ u_int *written = (u_int *)kmalloc(mtd->writesize, GFP_KERNEL);
++
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, addr));
++
++ /* write all data of 1 page by 4 bytes at a time */
++ for (i = 0; i < (mtd->writesize / 4); i++) {
++ *written = chip->read(cmd_addr);
++ written++;
++ }
++
++ written -= (mtd->writesize / 4);
++
++ /* Check, if data is same */
++ if (memcmp(written, buf, mtd->writesize))
++ ret = -EBADMSG;
++
++ kfree(written);
++
++ return ret;
++}
++
++/**
++ * onenand_verify_oob - [GENERIC] verify the oob contents after a write
++ * @param mtd MTD device structure
++ * @param buf the databuffer to verify
++ * @param to offset to read from
++ *
++ */
++static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to, size_t len)
++{
++ struct onenand_chip *chip = mtd->priv;
++ char oobbuf[64];
++ u_int *buf_poi, *dbuf_poi;
++ int read = 0, thislen, column, oobsize, i;
++ void __iomem *cmd_addr;
++ mtd_oob_mode_t mode = MTD_OOB_AUTO;
++
++ if (mode == MTD_OOB_AUTO)
++ oobsize = chip->ecclayout->oobavail;
++ else
++ oobsize = mtd->oobsize;
++
++ column = to & (mtd->oobsize - 1);
++ dbuf_poi = (u_int *)chip->page_buf;
++
++ while (read < len) {
++ /* get start address to read data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, to));
++
++ thislen = oobsize - column;
++ thislen = min_t(int, thislen, len);
++
++ if (mode == MTD_OOB_AUTO)
++ buf_poi = (u_int *)chip->oob_buf;
++ else
++ buf_poi = (u_int *)buf;
++
++ onenand_read_burst(dbuf_poi, cmd_addr, mtd->writesize);
++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize);
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) {
++ printk(KERN_WARNING "onenand_verify_oob: Read operation failed:0x%x\n", (unsigned int)to);
++#if 0
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++ return -1;
++#endif
++ }
++
++ if (mode == MTD_OOB_AUTO)
++ onenand_transfer_auto_oob(mtd, oobbuf, column, thislen);
++
++ read += thislen;
++
++ if (read == len)
++ break;
++
++ }
++
++
++ for (i = 0; i < len; i++)
++ if (buf[i] != oobbuf[i])
++ return -EBADMSG;
++
++ return 0;
++}
++
++
++/**
++ * onenand_verify_ops - [GENERIC] verify the oob contents after a write
++ * @param mtd MTD device structure
++ * @param ops oob operation description structure
++ * @param to offset to read from
++ * @param len number of bytes to read
++ *
++ */
++static int onenand_verify_ops(struct mtd_info *mtd, struct mtd_oob_ops *ops, loff_t to, size_t len)
++{
++ struct onenand_chip *chip = mtd->priv;
++ char oobbuf[64];
++ u_int *buf_poi, *dbuf_poi;
++ int read = 0, thislen, column, oobsize, i;
++ void __iomem *cmd_addr;
++ int ret = 0;
++
++ if (ops->mode == MTD_OOB_AUTO)
++ oobsize = chip->ecclayout->oobavail;
++ else
++ oobsize = mtd->oobsize;
++
++ column = to & (mtd->oobsize - 1);
++
++ while (read < len) {
++ /* get start address to read data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, to));
++
++ thislen = oobsize - column;
++ thislen = min_t(int, thislen, len);
++
++ dbuf_poi = (u_int *)chip->page_buf;
++
++ if (ops->mode == MTD_OOB_AUTO)
++ buf_poi = (u_int *)chip->oob_buf;
++ else
++ buf_poi = (u_int *)oobbuf;
++
++ onenand_read_burst(dbuf_poi, cmd_addr, mtd->writesize);
++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize);
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) {
++ printk(KERN_WARNING "onenand_verify_oob: Read operation failed:0x%x\n", (unsigned int)to);
++ return -EBADMSG;
++ }
++
++ if (ops->mode == MTD_OOB_AUTO)
++ onenand_transfer_auto_oob(mtd, oobbuf, column, thislen);
++
++ read += thislen;
++
++ if (read == len)
++ break;
++
++ }
++
++ /* Check, if data is same */
++ if (memcmp(chip->page_buf, ops->datbuf, mtd->writesize)) {
++ printk("Invalid data buffer : 0x%x\n", (unsigned int)to);
++ ret = -EBADMSG;
++ }
++
++ for (i = 0; i < len; i++)
++ if (ops->oobbuf[i] != oobbuf[i]) {
++ printk("Invalid OOB buffer :0x%x\n", (unsigned int)to);
++ ret = -EBADMSG;
++ }
++
++ return ret;
++}
++
++#endif
++
++#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
++
++/**
++ * onenand_write - [MTD Interface] write buffer to FLASH
++ * @param mtd MTD device structure
++ * @param to offset to write to
++ * @param len number of bytes to write
++ * @param retlen pointer to variable to store the number of written bytes
++ * @param buf the data to write
++ *
++ */
++int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
++ size_t *retlen, const u_char *buf)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int written = 0;
++ int i, ret = 0;
++ void __iomem *cmd_addr;
++ u_int *buf_poi = (u_int *)buf;
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
++
++ /* Initialize retlen, in case of early exit */
++ *retlen = 0;
++
++ /* Do not allow writes past end of device */
++ if (unlikely((to + len) > mtd->size)) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: Attempt write to past end of device\n");
++ return -EINVAL;
++ }
++
++ /* Reject writes, which are not page aligned */
++ if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: Attempt to write not page aligned data\n");
++ return -EINVAL;
++ }
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_WRITING);
++
++ /* Loop until all data write */
++ while (written < len) {
++ if (chip->options & ONENAND_CHECK_BAD) {
++ if (onenand_block_isbad(mtd, to)) {
++ printk (KERN_WARNING "onenand_write: skipped to write to a bad block at addr 0x%08x.\n", (unsigned int) to);
++ to += (1 << chip->erase_shift);
++ continue;
++ }
++ }
++
++ /* get start address to write data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PROG, to));
++
++ /* write all data of 1 page by 4 bytes at a time */
++ for (i = 0; i < (mtd->writesize / 4); i++) {
++ chip->write(*buf_poi, cmd_addr);
++ buf_poi++;
++ }
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_PROG)) {
++ printk(KERN_WARNING "onenand_write: Program operation failed.\n");
++ return -1;
++ }
++
++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
++ /* Only check verify write turn on */
++ ret = onenand_verify_page(mtd, buf_poi - (mtd->writesize / 4), to);
++
++ if (ret) {
++ printk("onenand_write: verify failed:0x%x.\n", (unsigned int)to);
++ break;
++ }
++#endif
++ written += mtd->writesize;
++
++ if (written == len)
++ break;
++
++ to += mtd->writesize;
++ }
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ *retlen = written;
++
++ return ret;
++}
++
++/**
++ * onenand_fill_auto_oob - [Internal] oob auto-placement transfer
++ * @param mtd MTD device structure
++ * @param oob_buf oob buffer
++ * @param buf source address
++ * @param column oob offset to write to
++ * @param thislen oob length to write
++ */
++static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
++ const u_char *buf, int column, int thislen)
++{
++ struct onenand_chip *chip = mtd->priv;
++ struct nand_oobfree *free;
++ int writecol = column;
++ int writeend = column + thislen;
++ int lastgap = 0;
++
++ for (free = chip->ecclayout->oobfree; free->length; ++free) {
++ if (writecol >= lastgap)
++ writecol += free->offset - lastgap;
++ if (writeend >= lastgap)
++ writeend += free->offset - lastgap;
++ lastgap = free->offset + free->length;
++ }
++ for (free = chip->ecclayout->oobfree; free->length; ++free) {
++ int free_end = free->offset + free->length;
++ if (free->offset < writeend && free_end > writecol) {
++ int st = max_t(int,free->offset,writecol);
++ int ed = min_t(int,free_end,writeend);
++ int n = ed - st;
++ memcpy(oob_buf + st, buf, n);
++ buf += n;
++ } else
++ break;
++ }
++ return 0;
++}
++
++
++/**
++ * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band
++ * @param mtd MTD device structure
++ * @param to offset to write to
++ * @param ops oob operation description structure
++ *
++ * Write main and/or oob with ECC
++ */
++static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int i, column, ret = 0, oobsize;
++ int written = 0;
++
++ int len = ops->ooblen;
++ u_char *buf = ops->datbuf;
++ u_char *sparebuf = ops->oobbuf;
++ u_char *oobbuf;
++
++ void __iomem *cmd_addr;
++ u_int *buf_poi;
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ops_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
++
++ /* Initialize retlen, in case of early exit */
++ ops->retlen = 0;
++ ops->oobretlen = 0;
++
++ if (ops->mode == MTD_OOB_AUTO)
++ oobsize = chip->ecclayout->oobavail;
++ else
++ oobsize = mtd->oobsize;
++
++ column = to & (mtd->oobsize - 1);
++
++ if (unlikely(column >= oobsize)) {
++ printk(KERN_ERR "onenand_write_ops_nolock: Attempted to start write outside oob\n");
++ return -EINVAL;
++ }
++
++ /* For compatibility with NAND: Do not allow write past end of page */
++ if (unlikely(column + len > oobsize)) {
++ printk(KERN_ERR "onenand_write_ops_nolock: "
++ "Attempt to write past end of page\n");
++ return -EINVAL;
++ }
++
++ /* Do not allow reads past end of device */
++ if (unlikely(to >= mtd->size ||
++ column + len > ((mtd->size >> chip->page_shift) -
++ (to >> chip->page_shift)) * oobsize)) {
++ printk(KERN_ERR "onenand_write_ops_nolock: Attempted to write past end of device\n");
++ return -EINVAL;
++ }
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_WRITING);
++
++ oobbuf = chip->oob_buf;
++ buf_poi = (u_int *)buf;
++
++ /* on the TRANSFER SPARE bit */
++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* Loop until all data write */
++ while (written < len) {
++ int thislen = min_t(int, oobsize, len - written);
++
++ if (chip->options & ONENAND_CHECK_BAD) {
++ if (onenand_block_isbad(mtd, to)) {
++ printk (KERN_WARNING "onenand_write_ops_nolock: skipped to write oob to a bad block at addr 0x%08x.\n", (unsigned int) to);
++ to += (1 << chip->erase_shift);
++
++ if (column != 0)
++ column = to & (mtd->oobsize - 1);
++
++ continue;
++ }
++ }
++
++ /* get start address to write data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PROG, to));
++
++ /* write all data of 1 page by 4 bytes at a time */
++ for (i = 0; i < (mtd->writesize / 4); i++) {
++ chip->write(*buf_poi, cmd_addr);
++ buf_poi++;
++ }
++
++ /* We send data to spare ram with oobsize
++ * to prevent byte access */
++ memset(oobbuf, 0xff, mtd->oobsize);
++
++ if (ops->mode == MTD_OOB_AUTO)
++ onenand_fill_auto_oob(mtd, oobbuf, sparebuf, column, thislen);
++ else
++ memcpy(oobbuf + column, buf, thislen);
++
++ buf_poi = (u_int *)chip->oob_buf;
++ for (i = 0; i < (mtd->oobsize / 4); i++) {
++ chip->write(*buf_poi, cmd_addr);
++ buf_poi++;
++ }
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_PROG)) {
++ printk(KERN_WARNING "onenand_write_ops_nolock: Program operation failed.\n");
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++ return -1;
++ }
++
++
++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
++ ret = onenand_verify_ops(mtd, ops, to, len);
++
++ if (ret) {
++ printk(KERN_ERR "onenand_write_ops_nolock: verify failed :0x%x\n", (unsigned int)to);
++ break;
++ }
++#endif
++ written += thislen;
++
++ if (written == len)
++ break;
++
++ to += mtd->writesize;
++ buf += thislen;
++ column = 0;
++ }
++
++ /* off the TRANSFER SPARE bit */
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ ops->retlen = mtd->writesize;
++ ops->oobretlen = written;
++
++ return ret;
++}
++
++
++/**
++ * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band
++ * @param mtd MTD device structure
++ * @param to offset to write to
++ * @param len number of bytes to write
++ * @param retlen pointer to variable to store the number of written bytes
++ * @param buf the data to write
++ * @param mode operation mode
++ *
++ * OneNAND write out-of-band
++ */
++static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int i, column, ret = 0, oobsize;
++ int written = 0;
++ u_char *oobbuf, *orgbuf;
++ void __iomem *cmd_addr;
++ u_int *buf_poi;
++
++ size_t len = ops->ooblen;
++ const u_char *buf = ops->oobbuf;
++ mtd_oob_mode_t mode = ops->mode;
++
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
++
++ /* Initialize retlen, in case of early exit */
++ ops->oobretlen = 0;
++
++ if (mode == MTD_OOB_AUTO)
++ oobsize = chip->ecclayout->oobavail;
++ else
++ oobsize = mtd->oobsize;
++
++ column = to & (mtd->oobsize - 1);
++
++ if (unlikely(column >= oobsize)) {
++ printk(KERN_ERR "onenand_write_oob_nolock: Attempted to start write outside oob\n");
++ return -EINVAL;
++ }
++
++ /* For compatibility with NAND: Do not allow write past end of page */
++ if (unlikely(column + len > oobsize)) {
++ printk(KERN_ERR "onenand_write_oob_nolock: "
++ "Attempt to write past end of page\n");
++ return -EINVAL;
++ }
++
++ /* Do not allow reads past end of device */
++ if (unlikely(to >= mtd->size ||
++ column + len > ((mtd->size >> chip->page_shift) -
++ (to >> chip->page_shift)) * oobsize)) {
++ printk(KERN_ERR "onenand_write_oob_nolock: Attempted to write past end of device\n");
++ return -EINVAL;
++ }
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_WRITING);
++
++ orgbuf = buf;
++ oobbuf = chip->oob_buf;
++ buf_poi = (u_int *)chip->oob_buf;
++
++ /* on the TRANSFER SPARE bit */
++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* Loop until all data write */
++ while (written < len) {
++ int thislen = min_t(int, oobsize, len - written);
++
++ if (chip->options & ONENAND_CHECK_BAD) {
++ if (onenand_block_isbad(mtd, to)) {
++ printk (KERN_WARNING "\nonenand_do_write_oob: skipped to write oob to a bad block at addr 0x%08x.\n", (unsigned int) to);
++ to += (1 << chip->erase_shift);
++
++ if (column != 0)
++ column = to & (mtd->oobsize - 1);
++
++ continue;
++ }
++ }
++
++ /* get start address to write data */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PROG, to));
++
++ /* We send data to spare ram with oobsize
++ * to prevent byte access */
++ memset(oobbuf, 0xff, mtd->oobsize);
++
++ if (mode == MTD_OOB_AUTO)
++ onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen);
++ else
++ memcpy(oobbuf + column, buf, thislen);
++
++ for (i = 0; i < (mtd->writesize / 4); i++)
++ chip->write(0xffffffff, cmd_addr);
++
++ for (i = 0; i < (mtd->oobsize / 4); i++) {
++ chip->write(*buf_poi, cmd_addr);
++ buf_poi++;
++ }
++
++ if (onenand_blkrw_complete(chip, ONENAND_CMD_PROG)) {
++ printk(KERN_WARNING "\onenand_write_oob_nolock: Program operation failed.\n");
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++ return -1;
++ }
++
++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
++ ret = onenand_verify_oob(mtd, orgbuf, to, len);
++
++ if (ret) {
++ printk(KERN_ERR "onenand_write_oob_nolock: verify failed :0x%x\n", (unsigned int)to);
++ break;
++ }
++#endif
++ written += thislen;
++
++ if (written == len)
++ break;
++
++ to += mtd->writesize;
++ buf += thislen;
++ column = 0;
++ }
++
++ /* off the TRANSFER SPARE bit */
++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE);
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ ops->oobretlen = written;
++
++ return ret;
++}
++
++/**
++ * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band
++ * @param mtd: MTD device structure
++ * @param to: offset to write
++ * @param ops: oob operation description structure
++ */
++static int onenand_write_oob(struct mtd_info *mtd, loff_t to,
++ struct mtd_oob_ops *ops)
++{
++ int ret;
++
++ switch (ops->mode) {
++ case MTD_OOB_PLACE:
++ case MTD_OOB_AUTO:
++ break;
++ case MTD_OOB_RAW:
++ /* Not implemented yet */
++ default:
++ return -EINVAL;
++ }
++
++ if (ops->datbuf != NULL)
++ ret = onenand_write_ops_nolock(mtd, to, ops);
++ else
++ ret = onenand_write_oob_nolock(mtd, to, ops);
++ return ret;
++
++}
++
++/**
++ * onenand_erase - [MTD Interface] erase block(s)
++ * @param mtd MTD device structure
++ * @param instr erase instruction
++ *
++ * Erase one ore more blocks
++ */
++static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
++{
++ struct onenand_chip *chip = mtd->priv;
++ unsigned int block_size;
++ loff_t addr;
++ int len, ret = 0;
++ void __iomem *cmd_addr;
++
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
++
++ block_size = (1 << chip->erase_shift);
++
++ /* Start address must align on block boundary */
++ if (unlikely(instr->addr & (block_size - 1))) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: Unaligned address\n");
++ return -EINVAL;
++ }
++
++ /* Length must align on block boundary */
++ if (unlikely(instr->len & (block_size - 1))) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: Length not block aligned\n");
++ return -EINVAL;
++ }
++
++ /* Do not allow erase past end of device */
++ if (unlikely((instr->len + instr->addr) > mtd->size)) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: Erase past end of device\n");
++ return -EINVAL;
++ }
++
++ instr->fail_addr = 0xffffffff;
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_ERASING);
++
++ /* Loop throught the pages */
++ len = instr->len;
++ addr = instr->addr;
++
++ instr->state = MTD_ERASING;
++
++ while (len) {
++ if (chip->options & ONENAND_CHECK_BAD) {
++
++ /* Check if we have a bad block, we do not erase bad blocks */
++ if (onenand_block_isbad_nolock(mtd, addr, 0)) {
++ printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr);
++ instr->state = MTD_ERASE_FAILED;
++ goto erase_exit;
++ }
++ }
++
++ /* get address to erase */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_ERASE, addr));
++
++ chip->write(ONENAND_DATAIN_ERASE_SINGLE, cmd_addr); /* single block erase */
++
++ /* wait irq */
++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_INT_ACT);
++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_ERS_CMP);
++
++ chip->write(ONENAND_DATAIN_ERASE_VERIFY, cmd_addr);
++
++ /* wait irq */
++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_INT_ACT);
++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_ERS_CMP);
++
++ /* check fail */
++ if (onenand_irq_pend(chip, ONENAND_INT_ERR_ERS_FAIL)) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: block %d erase verify failed.\n", addr >> chip->erase_shift);
++ onenand_irq_ack(chip, ONENAND_INT_ERR_ERS_FAIL);
++
++ /* check lock */
++ if (onenand_irq_pend(chip, ONENAND_INT_ERR_LOCKED_BLK)) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: block %d is locked.\n", addr >> chip->erase_shift);
++ onenand_irq_ack(chip, ONENAND_INT_ERR_LOCKED_BLK);
++ }
++ }
++
++ len -= block_size;
++ addr += block_size;
++ }
++
++ instr->state = MTD_ERASE_DONE;
++
++erase_exit:
++ ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
++ /* Do call back function */
++ if (!ret)
++ mtd_erase_callback(instr);
++
++ /* Deselect and wake up anyone waiting on the device */
++ onenand_release_device(mtd);
++
++ return ret;
++}
++
++/**
++ * onenand_sync - [MTD Interface] sync
++ * @param mtd MTD device structure
++ *
++ * Sync is actually a wait for chip ready function
++ */
++static void onenand_sync(struct mtd_info *mtd)
++{
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
++
++ /* Grab the lock and see if the device is available */
++ onenand_get_device(mtd, FL_SYNCING);
++
++ /* Release it and go back */
++ onenand_release_device(mtd);
++}
++
++/**
++ * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s)
++ * @param mtd MTD device structure
++ * @param ofs offset relative to mtd start
++ * @param len number of bytes to lock or unlock
++ *
++ * Lock or unlock one or more blocks
++ */
++static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int start, end, ofs_end, block_size;
++ int datain1, datain2;
++ void __iomem *cmd_addr;
++
++ start = ofs >> chip->erase_shift;
++ end = len >> chip->erase_shift;
++ block_size = 1 << chip->erase_shift;
++ ofs_end = ofs + len - block_size;
++
++ if (cmd == ONENAND_CMD_LOCK) {
++ datain1 = ONENAND_DATAIN_LOCK_START;
++ datain2 = ONENAND_DATAIN_LOCK_END;
++ } else {
++ datain1 = ONENAND_DATAIN_UNLOCK_START;
++ datain2 = ONENAND_DATAIN_UNLOCK_END;
++ }
++
++ if (ofs < ofs_end) {
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, cmd, ofs));
++ chip->write(datain1, cmd_addr);
++ }
++
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, cmd, ofs));
++ chip->write(datain2, cmd_addr);
++
++ if (cmd == ONENAND_CMD_LOCK) {
++ if (!chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & ONENAND_INT_ERR_LOCKED_BLK) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_do_lock_cmd: lock failed.\n");
++ return -1;
++ }
++ } else {
++ if (chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & ONENAND_INT_ERR_LOCKED_BLK) {
++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_do_lock_cmd: unlock failed.\n");
++ return -1;
++ }
++ }
++
++ return 0;
++}
++
++/**
++ * onenand_lock - [MTD Interface] Lock block(s)
++ * @param mtd MTD device structure
++ * @param ofs offset relative to mtd start
++ * @param len number of bytes to lock
++ *
++ * Lock one or more blocks
++ */
++static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
++{
++ return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK);
++}
++
++/**
++ * onenand_unlock - [MTD Interface] Unlock block(s)
++ * @param mtd MTD device structure
++ * @param ofs offset relative to mtd start
++ * @param len number of bytes to unlock
++ *
++ * Unlock one or more blocks
++ */
++int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
++{
++ return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
++}
++
++/**
++ * onenand_check_lock_status - [OneNAND Interface] Check lock status
++ * @param this onenand chip data structure
++ *
++ * Check lock status
++ */
++static void onenand_check_lock_status(struct mtd_info *mtd)
++{
++ struct onenand_chip *chip = mtd->priv;
++ unsigned int block, end;
++ void __iomem *cmd_addr;
++ int tmp;
++
++ end = chip->chipsize >> chip->erase_shift;
++
++ for (block = 0; block < end; block++) {
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, block << chip->erase_shift));
++ tmp = chip->read(cmd_addr);
++
++ if (chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & ONENAND_INT_ERR_LOCKED_BLK) {
++ printk(KERN_ERR "block %d is write-protected!\n", block);
++ chip->write(ONENAND_INT_ERR_LOCKED_BLK, chip->base + ONENAND_REG_INT_ERR_ACK);
++ }
++ }
++}
++
++/**
++ * onenand_unlock_all - [OneNAND Interface] unlock all blocks
++ * @param mtd MTD device structure
++ *
++ * Unlock all blocks
++ */
++static int onenand_unlock_all(struct mtd_info *mtd)
++{
++ struct onenand_chip *chip = mtd->priv;
++ void __iomem *cmd_addr;
++
++ if (chip->options & ONENAND_HAS_UNLOCK_ALL) {
++ /* write unlock command */
++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0));
++ chip->write(ONENAND_DATAIN_UNLOCK_ALL, cmd_addr);
++
++ /* Workaround for all block unlock in DDP */
++ if (chip->device_id & ONENAND_DEVICE_IS_DDP) {
++ loff_t ofs;
++ size_t len;
++
++ /* 1st block on another chip */
++ ofs = chip->chipsize >> 1;
++ len = 1 << chip->erase_shift;
++
++ onenand_unlock(mtd, ofs, len);
++ }
++
++ onenand_check_lock_status(mtd);
++
++ return 0;
++ }
++
++ onenand_unlock(mtd, 0x0, chip->chipsize);
++
++ return 0;
++}
++
++/**
++ * onenand_lock_scheme - Check and set OneNAND lock scheme
++ * @param mtd MTD data structure
++ *
++ * Check and set OneNAND lock scheme
++ */
++static void onenand_lock_scheme(struct mtd_info *mtd)
++{
++ struct onenand_chip *chip = mtd->priv;
++ unsigned int density, process;
++
++ /* Lock scheme depends on density and process */
++ density = chip->device_id >> ONENAND_DEVICE_DENSITY_SHIFT;
++ process = chip->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
++
++ /* Lock scheme */
++ if (density >= ONENAND_DEVICE_DENSITY_1Gb) {
++ /* A-Die has all block unlock */
++ if (process) {
++ printk(KERN_DEBUG "Chip support all block unlock\n");
++ chip->options |= ONENAND_HAS_UNLOCK_ALL;
++ }
++ } else {
++ /* Some OneNAND has continues lock scheme */
++ if (!process) {
++ printk(KERN_DEBUG "Lock scheme is Continues Lock\n");
++ chip->options |= ONENAND_HAS_CONT_LOCK;
++ }
++ }
++}
++
++/**
++ * onenand_print_device_info - Print device ID
++ * @param device device ID
++ *
++ * Print device ID
++ */
++void onenand_print_device_info(int device, int version)
++{
++ int vcc, demuxed, ddp, density;
++
++ vcc = device & ONENAND_DEVICE_VCC_MASK;
++ demuxed = device & ONENAND_DEVICE_IS_DEMUX;
++ ddp = device & ONENAND_DEVICE_IS_DDP;
++ density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
++ printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
++ demuxed ? "" : "Muxed ",
++ ddp ? "(DDP)" : "",
++ (16 << density),
++ vcc ? "2.65/3.3" : "1.8",
++ device);
++ printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version);
++}
++
++static const struct onenand_manufacturers onenand_manuf_ids[] = {
++ {ONENAND_MFR_SAMSUNG, "Samsung"},
++};
++
++/**
++ * onenand_check_maf - Check manufacturer ID
++ * @param manuf manufacturer ID
++ *
++ * Check manufacturer ID
++ */
++static int onenand_check_maf(int manuf)
++{
++ int size = ARRAY_SIZE(onenand_manuf_ids);
++ char *name;
++ int i;
++
++ for (i = 0; i < size; i++)
++ if (manuf == onenand_manuf_ids[i].id)
++ break;
++
++ if (i < size)
++ name = onenand_manuf_ids[i].name;
++ else
++ name = "Unknown";
++
++ printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf);
++
++ return (i == size);
++}
++
++/**
++ * onenand_suspend - [MTD Interface] Suspend the OneNAND flash
++ * @param mtd MTD device structure
++ */
++static int onenand_suspend(struct mtd_info *mtd)
++{
++ return onenand_get_device(mtd, FL_PM_SUSPENDED);
++}
++
++/**
++ * onenand_resume - [MTD Interface] Resume the OneNAND flash
++ * @param mtd MTD device structure
++ */
++static void onenand_resume(struct mtd_info *mtd)
++{
++ struct onenand_chip *chip = mtd->priv;
++
++ if (chip->state == FL_PM_SUSPENDED)
++ onenand_release_device(mtd);
++ else
++ printk(KERN_ERR "resume() called for the chip which is not"
++ "in suspended state\n");
++}
++
++/*
++ * Setting address width registers
++ * (FBA_WIDTH, FPA_WIDTH, FSA_WIDTH, DFS_DBS_WIDTH)
++ */
++static void s3c_onenand_width_regs(struct onenand_chip *chip)
++{
++ int dev_id, ddp, density;
++ int w_dfs_dbs = 0, w_fba = 10, w_fpa = 6, w_fsa = 2;
++
++ dev_id = readl(chip->base + ONENAND_REG_DEVICE_ID);
++
++ ddp = dev_id & ONENAND_DEVICE_IS_DDP;
++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
++
++ switch (density & 0xf) {
++ case ONENAND_DEVICE_DENSITY_128Mb:
++ w_dfs_dbs = 0;
++ w_fba = 8;
++ w_fpa = 6;
++ w_fsa = 1;
++ break;
++
++ case ONENAND_DEVICE_DENSITY_256Mb:
++ w_dfs_dbs = 0;
++ w_fba = 9;
++ w_fpa = 6;
++ w_fsa = 1;
++ break;
++
++ case ONENAND_DEVICE_DENSITY_512Mb:
++ w_dfs_dbs = 0;
++ w_fba = 9;
++ w_fpa = 6;
++ w_fsa = 2;
++ break;
++
++ case ONENAND_DEVICE_DENSITY_1Gb:
++ if (ddp) {
++ w_dfs_dbs = 1;
++ w_fba = 9;
++ } else {
++ w_dfs_dbs = 0;
++ w_fba = 10;
++ }
++
++ w_fpa = 6;
++ w_fsa = 2;
++ break;
++
++ case ONENAND_DEVICE_DENSITY_2Gb:
++ if (ddp) {
++ w_dfs_dbs = 1;
++ w_fba = 10;
++ } else {
++ w_dfs_dbs = 0;
++ w_fba = 11;
++ }
++
++ w_fpa = 6;
++ w_fsa = 2;
++ break;
++
++ case ONENAND_DEVICE_DENSITY_4Gb:
++ if (ddp) {
++ w_dfs_dbs = 1;
++ w_fba = 11;
++ } else {
++ w_dfs_dbs = 0;
++ w_fba = 12;
++ }
++
++ w_fpa = 6;
++ w_fsa = 2;
++ break;
++ }
++
++ writel(w_fba, chip->base + ONENAND_REG_FBA_WIDTH);
++ writel(w_fpa, chip->base + ONENAND_REG_FPA_WIDTH);
++ writel(w_fsa, chip->base + ONENAND_REG_FSA_WIDTH);
++ writel(w_dfs_dbs, chip->base + ONENAND_REG_DBS_DFS_WIDTH);
++}
++
++/*
++ * Board-specific NAND initialization. The following members of the
++ * argument are board-specific (per include/linux/mtd/nand.h):
++ * - base : address that OneNAND is located at.
++ * - scan_bbt: board specific bad block scan function.
++ * Members with a "?" were not set in the merged testing-NAND branch,
++ * so they are not set here either.
++ */
++static int s3c_onenand_init (struct onenand_chip *chip)
++{
++ int value;
++
++ chip->options |= (ONENAND_READ_BURST | ONENAND_CHECK_BAD | ONENAND_PIPELINE_AHEAD);
++
++ /*** Initialize Controller ***/
++
++ /* SYSCON */
++ value = readl(S3C_CLK_DIV0);
++ value = (value & ~(3 << 16)) | (1 << 16);
++ writel(value, S3C_CLK_DIV0);
++
++#if defined(CONFIG_CPU_S3C6410)
++ writel(ONENAND_FLASH_AUX_WD_DISABLE, chip->base + ONENAND_REG_FLASH_AUX_CNTRL);
++#endif
++
++ /* Cold Reset */
++ writel(ONENAND_MEM_RESET_COLD, chip->base + ONENAND_REG_MEM_RESET);
++
++ /* Access Clock Register */
++ writel(ONENAND_ACC_CLOCK_134_67, chip->base + ONENAND_REG_ACC_CLOCK);
++
++ /* FBA, FPA, FSA, DBS_DFS Width Register */
++ s3c_onenand_width_regs(chip);
++
++ /* Enable Interrupts */
++ writel(0x3ff, chip->base + ONENAND_REG_INT_ERR_MASK);
++ writel(ONENAND_INT_PIN_ENABLE, chip->base + ONENAND_REG_INT_PIN_ENABLE);
++ writel(readl(chip->base + ONENAND_REG_INT_ERR_MASK) & ~(ONENAND_INT_ERR_RDY_ACT),
++ chip->base + ONENAND_REG_INT_ERR_MASK);
++
++ /* Memory Device Configuration Register */
++ value = (ONENAND_MEM_CFG_SYNC_READ | ONENAND_MEM_CFG_BRL_4 | \
++ ONENAND_MEM_CFG_BL_16| ONENAND_MEM_CFG_IOBE | \
++ ONENAND_MEM_CFG_INT_HIGH | ONENAND_MEM_CFG_RDY_HIGH);
++ writel(value, chip->base + ONENAND_REG_MEM_CFG);
++
++ /* Burst Length Register */
++ writel(ONENAND_BURST_LEN_16, chip->base + ONENAND_REG_BURST_LEN);
++
++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED
++ writel((readl(S3C_GPNCON) & ~(0x3 << 30)) | (0x1 << 30), S3C_GPNCON);
++ writel(0 << 15, S3C_GPNDAT);
++#endif
++
++ return 0;
++}
++
++/**
++ * onenand_probe - [OneNAND Interface] Probe the OneNAND device
++ * @param mtd MTD device structure
++ *
++ * OneNAND detection method:
++ * Compare the the values from command with ones from register
++ */
++static int onenand_probe(struct mtd_info *mtd)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int maf_id, dev_id, ver_id, density;
++
++ s3c_onenand_init(chip);
++
++ chip->dev_base = (void __iomem *)ioremap_nocache(ONENAND_AHB_ADDR, SZ_256M);
++
++ if (!chip->dev_base) {
++ printk("ioremap failed.\n");
++ return -1;
++ }
++
++ printk("onenand_probe: OneNAND memory device is remapped at 0x%08x.\n", (u_int) chip->dev_base);
++
++ chip->dma = ONENAND_DMA_CON;
++ chip->dma_ch = DMACH_ONENAND_IN;
++
++ /* Read manufacturer and device IDs from Register */
++ maf_id = chip->read(chip->base + ONENAND_REG_MANUFACT_ID);
++ dev_id = chip->read(chip->base + ONENAND_REG_DEVICE_ID);
++ ver_id = chip->read(chip->base + ONENAND_REG_FLASH_VER_ID);
++
++ /* Check manufacturer ID */
++ if (onenand_check_maf(maf_id))
++ return -ENXIO;
++
++ /* Flash device information */
++ onenand_print_device_info(dev_id, ver_id);
++ chip->device_id = dev_id;
++ chip->version_id = ver_id;
++
++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
++ chip->chipsize = (16 << density) << 20;
++ /* Set density mask. it is used for DDP */
++ chip->density_mask = (1 << (density + 6));
++
++ /* OneNAND page size & block size */
++ /* The data buffer size is equal to page size */
++ mtd->writesize = chip->read(chip->base + ONENAND_REG_DATA_BUF_SIZE);
++ mtd->oobsize = mtd->writesize >> 5;
++ /* Pagers per block is always 64 in OneNAND */
++ mtd->erasesize = mtd->writesize << 6;
++
++ chip->erase_shift = ffs(mtd->erasesize) - 1;
++ chip->page_shift = ffs(mtd->writesize) - 1;
++ chip->page_mask = (mtd->erasesize / mtd->writesize) - 1;
++
++ /* REVIST: Multichip handling */
++
++ mtd->size = chip->chipsize;
++
++ /* Check OneNAND lock scheme */
++ onenand_lock_scheme(mtd);
++
++ return 0;
++}
++
++/**
++ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
++ * @param mtd MTD device structure
++ * @param ofs offset relative to mtd start
++ *
++ * Mark the block as bad
++ */
++static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++ struct onenand_chip *chip = mtd->priv;
++ int ret;
++
++ if (chip->options & ONENAND_CHECK_BAD) {
++ ret = onenand_block_isbad(mtd, ofs);
++ if (ret) {
++ /* If it was bad already, return success and do nothing */
++ if (ret > 0)
++ return 0;
++ return ret;
++ }
++
++ return chip->block_markbad(mtd, ofs);
++ } else
++ return 0;
++}
++
++int s3c_onenand_scan_bbt(struct mtd_info *mtd)
++{
++ struct onenand_chip *chip = mtd->priv;
++
++ if (chip->options & ONENAND_CHECK_BAD)
++ return onenand_default_bbt(mtd);
++ else
++ return 0;
++}
++
++/**
++ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
++ * @param mtd MTD device structure
++ * @param maxchips Number of chips to scan for
++ *
++ * This fills out all the not initialized function pointers
++ * with the defaults.
++ * The flash ID is read and the mtd/chip structures are
++ * filled with the appropriate values.
++ */
++int onenand_scan(struct mtd_info *mtd, int maxchips)
++{
++ int i;
++ struct onenand_chip *chip = mtd->priv;
++
++ if (!chip->read)
++ chip->read = onenand_readl;
++
++ if (!chip->write)
++ chip->write = onenand_writel;
++
++ if (!chip->command)
++ chip->command = onenand_command;
++
++ if (!chip->block_markbad)
++ chip->block_markbad = onenand_default_block_markbad;
++
++ if (!chip->scan_bbt)
++ chip->scan_bbt = s3c_onenand_scan_bbt;
++
++ if (onenand_probe(mtd))
++ return -ENXIO;
++
++ /* Allocate buffers, if necessary */
++ if (!chip->page_buf) {
++ size_t len;
++ len = mtd->writesize + mtd->oobsize;
++ chip->page_buf = kmalloc(len, GFP_KERNEL);
++ if (!chip->page_buf) {
++ printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n");
++ return -ENOMEM;
++ }
++ chip->options |= ONENAND_PAGEBUF_ALLOC;
++ }
++
++ if (!chip->oob_buf) {
++ chip->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL);
++ if (!chip->oob_buf) {
++ printk(KERN_ERR "onenand_scan(): Can't allocate oob_buf\n");
++ if (chip->options & ONENAND_PAGEBUF_ALLOC) {
++ chip->options &= ~ONENAND_PAGEBUF_ALLOC;
++ kfree(chip->page_buf);
++ }
++ return -ENOMEM;
++ }
++ chip->options |= ONENAND_OOBBUF_ALLOC;
++ }
++
++ /*
++ * Allow subpage writes up to oobsize.
++ */
++ switch (mtd->oobsize) {
++ case 64:
++ chip->ecclayout = &onenand_oob_64;
++ mtd->subpage_sft = 2;
++ break;
++
++ case 32:
++ chip->ecclayout = &onenand_oob_32;
++ mtd->subpage_sft = 1;
++ break;
++
++ default:
++ printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n",
++ mtd->oobsize);
++ mtd->subpage_sft = 0;
++ /* To prevent kernel oops */
++ chip->ecclayout = &onenand_oob_32;
++ break;
++ }
++
++ chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
++
++ /*
++ * The number of bytes available for a client to place data into
++ * the out of band area
++ */
++ chip->ecclayout->oobavail = 0;
++ for (i = 0; chip->ecclayout->oobfree[i].length; i++)
++ chip->ecclayout->oobavail +=
++ chip->ecclayout->oobfree[i].length;
++ mtd->oobavail = chip->ecclayout->oobavail;
++
++ mtd->ecclayout = chip->ecclayout;
++
++ /* Fill in remaining MTD driver data */
++ mtd->type = MTD_NANDFLASH;
++ mtd->flags = MTD_CAP_NANDFLASH;
++ mtd->erase = onenand_erase;
++ mtd->point = NULL;
++ mtd->unpoint = NULL;
++ mtd->read = onenand_read;
++ mtd->write = onenand_write;
++ mtd->read_oob = onenand_read_oob;
++ mtd->write_oob = onenand_write_oob;
++ mtd->sync = onenand_sync;
++ mtd->lock = onenand_lock;
++ mtd->unlock = onenand_unlock;
++ mtd->block_isbad = onenand_block_isbad;
++ mtd->block_markbad = onenand_block_markbad;
++ mtd->suspend = onenand_suspend;
++ mtd->resume = onenand_resume;
++ mtd->owner = THIS_MODULE;
++
++ /* Unlock whole block */
++ onenand_unlock_all(mtd);
++
++ return chip->scan_bbt(mtd);
++}
++
++/**
++ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
++ * @param mtd MTD device structure
++ */
++void onenand_release(struct mtd_info *mtd)
++{
++ struct onenand_chip *chip = mtd->priv;
++
++#ifdef CONFIG_MTD_PARTITIONS
++ /* Deregister partitions */
++ del_mtd_partitions (mtd);
++#endif
++ /* Deregister the device */
++ del_mtd_device (mtd);
++
++ /* Free bad block table memory, if allocated */
++ if (chip->bbm) {
++ struct bbm_info *bbm = chip->bbm;
++ kfree(bbm->bbt);
++ kfree(chip->bbm);
++ }
++
++ /* Buffer allocated by onenand_scan */
++ if (chip->options & ONENAND_PAGEBUF_ALLOC)
++ kfree(chip->page_buf);
++ if (chip->options & ONENAND_OOBBUF_ALLOC)
++ kfree(chip->oob_buf);
++}
++
++EXPORT_SYMBOL_GPL(onenand_scan);
++EXPORT_SYMBOL_GPL(onenand_release);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Jinsung Yang <jsgood.yang@samsung.com>");
++MODULE_DESCRIPTION("S3C OneNAND Controller Driver");
+diff --git a/drivers/mtd/onenand/s3c_onenand.h b/drivers/mtd/onenand/s3c_onenand.h
+new file mode 100644
+index 0000000..b37792f
+--- /dev/null
++++ b/drivers/mtd/onenand/s3c_onenand.h
+@@ -0,0 +1,158 @@
++#ifndef __LINUX_MTD_S3C_ONENAND_H
++#define __LINUX_MTD_S3C_ONENAND_H
++
++#include <linux/spinlock.h>
++#include <linux/completion.h>
++#include <asm/arch/regs-onenand.h>
++#include <linux/mtd/bbm.h>
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++
++#define MAX_BUFFERRAM 2
++
++/* Scan and identify a OneNAND device */
++extern int onenand_scan(struct mtd_info *mtd, int max_chips);
++/* Free resources held by the OneNAND device */
++extern void onenand_release(struct mtd_info *mtd);
++
++/*
++ * onenand_state_t - chip states
++ * Enumeration for OneNAND flash chip state
++ */
++typedef enum {
++ FL_READY,
++ FL_READING,
++ FL_WRITING,
++ FL_ERASING,
++ FL_SYNCING,
++ FL_LOCKING,
++ FL_RESETING,
++ FL_OTPING,
++ FL_PM_SUSPENDED,
++} onenand_state_t;
++
++/**
++ * struct onenand_bufferram - OneNAND BufferRAM Data
++ * @block: block address in BufferRAM
++ * @page: page address in BufferRAM
++ * @valid: valid flag
++ */
++struct onenand_bufferram {
++ int block;
++ int page;
++ int valid;
++};
++
++/**
++ * struct onenand_chip - OneNAND Private Flash Chip Data
++ * @base: [BOARDSPECIFIC] address to access OneNAND
++ * @chipsize: [INTERN] the size of one chip for multichip arrays
++ * @device_id: [INTERN] device ID
++ * @density_mask: chip density, used for DDP devices
++ * @verstion_id: [INTERN] version ID
++ * @options: [BOARDSPECIFIC] various chip options. They can
++ * partly be set to inform onenand_scan about
++ * @erase_shift: [INTERN] number of address bits in a block
++ * @page_shift: [INTERN] number of address bits in a page
++ * @page_mask: [INTERN] a page per block mask
++ * @bufferram_index: [INTERN] BufferRAM index
++ * @bufferram: [INTERN] BufferRAM info
++ * @readw: [REPLACEABLE] hardware specific function for read short
++ * @writew: [REPLACEABLE] hardware specific function for write short
++ * @command: [REPLACEABLE] hardware specific function for writing
++ * commands to the chip
++ * @wait: [REPLACEABLE] hardware specific function for wait on ready
++ * @read_bufferram: [REPLACEABLE] hardware specific function for BufferRAM Area
++ * @write_bufferram: [REPLACEABLE] hardware specific function for BufferRAM Area
++ * @read_word: [REPLACEABLE] hardware specific function for read
++ * register of OneNAND
++ * @write_word: [REPLACEABLE] hardware specific function for write
++ * register of OneNAND
++ * @mmcontrol: sync burst read function
++ * @block_markbad: function to mark a block as bad
++ * @scan_bbt: [REPLACEALBE] hardware specific function for scanning
++ * Bad block Table
++ * @chip_lock: [INTERN] spinlock used to protect access to this
++ * structure and the chip
++ * @wq: [INTERN] wait queue to sleep on if a OneNAND
++ * operation is in progress
++ * @state: [INTERN] the current state of the OneNAND device
++ * @page_buf: data buffer
++ * @subpagesize: [INTERN] holds the subpagesize
++ * @ecclayout: [REPLACEABLE] the default ecc placement scheme
++ * @bbm: [REPLACEABLE] pointer to Bad Block Management
++ * @priv: [OPTIONAL] pointer to private chip date
++ */
++struct onenand_chip {
++ void __iomem *base; /* SFR base address (0x7010_0000 ~) */
++ void __iomem *dev_base; /* virtual address base for AHB Port Address (0x2000_0000 ~ 0x20FF_FFFF) */
++ unsigned int chipsize;
++ unsigned int device_id;
++ unsigned int version_id;
++ unsigned int density_mask;
++ unsigned int options;
++
++ unsigned int erase_shift;
++ unsigned int page_shift;
++ unsigned int page_mask;
++
++ unsigned int bufferram_index;
++ struct onenand_bufferram bufferram[MAX_BUFFERRAM];
++
++ uint (*command)(struct mtd_info *mtd, int cmd, loff_t address);
++ unsigned int (*read)(void __iomem *addr);
++ void (*write)(unsigned int value, void __iomem *addr);
++ int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
++ int (*scan_bbt)(struct mtd_info *mtd);
++
++ int irq;
++
++ spinlock_t chip_lock;
++ wait_queue_head_t wq;
++ onenand_state_t state;
++
++ unsigned char *page_buf;
++ unsigned char *oob_buf;
++
++ int subpagesize;
++ struct nand_ecclayout *ecclayout;
++
++ void *bbm;
++ void *priv;
++
++ int dma;
++ unsigned int dma_ch;
++ void *done; /* completion */
++};
++
++/*
++ * Options bits
++ */
++#define ONENAND_HAS_CONT_LOCK (0x0001)
++#define ONENAND_HAS_UNLOCK_ALL (0x0002)
++#define ONENAND_CHECK_BAD (0x0004)
++#define ONENAND_READ_POLLING (0x0010)
++#define ONENAND_READ_BURST (0x0020)
++#define ONENAND_READ_DMA (0x0040)
++#define ONENAND_PIPELINE_AHEAD (0x0100)
++#define ONENAND_READ_MASK (0x00F0)
++#define ONENAND_PAGEBUF_ALLOC (0x1000)
++#define ONENAND_OOBBUF_ALLOC (0x2000)
++
++/*
++ * OneNAND Flash Manufacturer ID Codes
++ */
++#define ONENAND_MFR_SAMSUNG 0xec
++
++/**
++ * struct onenand_manufacturers - NAND Flash Manufacturer ID Structure
++ * @name: Manufacturer name
++ * @id: manufacturer ID code of device.
++*/
++struct onenand_manufacturers {
++ int id;
++ char *name;
++};
++
++#endif /* __LINUX_MTD_ONENAND_H */
++
+diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
+index 28d284a..8d649ab 100644
+--- a/drivers/net/Kconfig
++++ b/drivers/net/Kconfig
+@@ -916,7 +916,7 @@ config SMC911X
+ tristate "SMSC LAN911[5678] support"
+ select CRC32
+ select MII
+- depends on ARCH_PXA || SH_MAGIC_PANEL_R2
++ depends on ARCH_PXA || SH_MAGIC_PANEL_R2 || MACH_SMDK6410 || MACH_SMDK2450 || MACH_SMDK2416 || MACH_SMDK6430
+ help
+ This is a driver for SMSC's LAN911x series of Ethernet chipsets
+ including the new LAN9115, LAN9116, LAN9117, and LAN9118.
+diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
+index 5717509..7515c2b 100644
+--- a/drivers/net/cs89x0.c
++++ b/drivers/net/cs89x0.c
+@@ -194,6 +194,24 @@ static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0};
+ #define CIRRUS_DEFAULT_IRQ VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */
+ static unsigned int netcard_portlist[] __initdata = {CIRRUS_DEFAULT_BASE, 0};
+ static unsigned int cs8900_irq_map[] = {CIRRUS_DEFAULT_IRQ, 0, 0, 0};
++#elif defined(CONFIG_MACH_SMDK2443)
++#include <asm/irq.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++static unsigned int netcard_portlist[] __initdata = {(uint)S3C24XX_VA_CS8900 + 0x300, 0};
++static unsigned int cs8900_irq_map[] = {IRQ_EINT13,0,0,0};
++#elif defined(CONFIG_MACH_SMDK2450) || defined(CONFIG_MACH_SMDK2416)
++#include <asm/irq.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++static unsigned int netcard_portlist[] __initdata = {(uint)S3C24XX_VA_CS8900 + 0x300, 0};
++static unsigned int cs8900_irq_map[] = {IRQ_EINT4,0,0,0};
++#elif defined(CONFIG_MACH_SMDK6400) || defined(CONFIG_MACH_SMDK6410)
++#include <asm/irq.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++static unsigned int netcard_portlist[] __initdata = {(uint)S3C24XX_VA_CS8900 + 0x300, 0};
++static unsigned int cs8900_irq_map[] = {IRQ_EINT10,0,0,0};
+ #else
+ static unsigned int netcard_portlist[] __initdata =
+ { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0};
+@@ -316,6 +334,13 @@ struct net_device * __init cs89x0_probe(int unit)
+ int irq;
+ int io;
+
++#if defined(CONFIG_MACH_SMDK2443) || defined(CONFIG_MACH_SMDK2450) ||defined(CONFIG_MACH_SMDK2416) || defined(CONFIG_MACH_SMDK6400) || defined(CONFIG_MACH_SMDK6410)
++ if (unit > 0) {
++ err = -ENODEV;
++ return ERR_PTR(err);
++ }
++#endif
++
+ if (!dev)
+ return ERR_PTR(-ENODEV);
+
+@@ -518,6 +543,10 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
+ int retval;
+ DECLARE_MAC_BUF(mac);
+
++#if defined(CONFIG_MACH_SMDK2443) || defined(CONFIG_MACH_SMDK2450) || defined(CONFIG_MACH_SMDK2416)|| defined(CONFIG_MACH_SMDK6400) || defined(CONFIG_MACH_SMDK6410)
++ set_irq_type(cs8900_irq_map[0], IRQT_HIGH);
++#endif
++
+ /* Initialize the device structure. */
+ if (!modular) {
+ memset(lp, 0, sizeof(*lp));
+@@ -532,6 +561,10 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
+ #endif
+ lp->force = g_cs89x0_media__force;
+ #endif
++
++#if defined(CONFIG_MACH_SMDK2443) || defined(CONFIG_MACH_SMDK2450) ||defined(CONFIG_MACH_SMDK2416) || defined(CONFIG_MACH_SMDK6400) || defined(CONFIG_MACH_SMDK6410)
++ lp->force = FORCE_RJ45 | FORCE_HALF;
++#endif
+ }
+
+ #ifdef CONFIG_ARCH_PNX010X
+@@ -840,6 +873,15 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
+ printk(", programmed I/O");
+ }
+
++#if defined(CONFIG_MACH_SMDK2443) || defined(CONFIG_MACH_SMDK2450) || defined(CONFIG_MACH_SMDK2416) || defined(CONFIG_MACH_SMDK6400) || defined(CONFIG_MACH_SMDK6410)
++ dev->dev_addr[0] = 0x00;
++ dev->dev_addr[1] = 0x09;
++ dev->dev_addr[2] = 0xc0;
++ dev->dev_addr[3] = 0xff;
++ dev->dev_addr[4] = 0xec;
++ dev->dev_addr[5] = 0x48;
++#endif
++
+ /* print the ethernet address. */
+ printk(", MAC %s", print_mac(mac, dev->dev_addr));
+
+@@ -1128,6 +1170,9 @@ detect_tp(struct net_device *dev)
+ case FORCE_FULL:
+ writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900);
+ break;
++ default:
++ /* only for evaluation in order to get full duplex mode */
++ writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900);
+ }
+ fdx = readreg(dev, PP_TestCTL) & FDX_8900;
+ } else {
+@@ -1304,7 +1349,8 @@ net_open(struct net_device *dev)
+ else
+ #endif
+ {
+-#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_ARCH_PNX010X)
++#if !defined(CONFIG_MACH_IXDP2351) && !defined(CONFIG_ARCH_IXDP2X01) && !defined(CONFIG_ARCH_PNX010X) && \
++ !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2450) && !defined(CONFIG_MACH_SMDK2416) && !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410)
+ if (((1 << dev->irq) & lp->irq_map) == 0) {
+ printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n",
+ dev->name, dev->irq, lp->irq_map);
+diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig
+index 6580695..b427100 100644
+--- a/drivers/net/irda/Kconfig
++++ b/drivers/net/irda/Kconfig
+@@ -3,6 +3,12 @@ menu "Infrared-port device drivers"
+
+ comment "SIR device drivers"
+
++config S3C_SIR
++ tristate "S3C Irda SIR device"
++ depends on IRDA
++ help
++ Say Y here if you want to have S3C IRDA support.
++
+ config IRTTY_SIR
+ tristate "IrTTY (uses Linux serial driver)"
+ depends on IRDA
+diff --git a/drivers/net/irda/Makefile b/drivers/net/irda/Makefile
+index fefbb59..f9af62d 100644
+--- a/drivers/net/irda/Makefile
++++ b/drivers/net/irda/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_EP7211_IR) += ep7211_ir.o
+ obj-$(CONFIG_AU1000_FIR) += au1k_ir.o
+ # New SIR drivers
+ obj-$(CONFIG_IRTTY_SIR) += irtty-sir.o sir-dev.o
++obj-$(CONFIG_S3C_SIR) += s3c-sir.o
+ # New dongles drivers for new SIR drivers
+ obj-$(CONFIG_ESI_DONGLE) += esi-sir.o
+ obj-$(CONFIG_TEKRAM_DONGLE) += tekram-sir.o
+diff --git a/drivers/net/irda/s3c-sir.c b/drivers/net/irda/s3c-sir.c
+new file mode 100644
+index 0000000..e65bfe2
+--- /dev/null
++++ b/drivers/net/irda/s3c-sir.c
+@@ -0,0 +1,1166 @@
++/*
++ * linux/drivers/net/irda/s3c-sir.c
++ *
++ * Copyright (C) 2000-2001 Russell King
++ * Copyright (C) 2006 Naushad K
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Infra-red driver for the S3C embedded microprocessor
++ * Derived from sa1100 irda file.
++ *
++ */
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/netdevice.h>
++#include <linux/slab.h>
++#include <linux/rtnetlink.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++
++#include <net/irda/irda.h>
++#include <net/irda/wrapper.h>
++#include <net/irda/irda_device.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/mach/irda.h>
++
++#include <asm/arch/map.h>
++#include <asm/arch/hardware.h>
++//#include <asm/arch/regs-sir.h>
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++
++#include <asm/dma.h>
++#include <asm/dma-mapping.h>
++#include <asm/arch/dma.h>
++#include <asm/arch/irqs.h>
++
++//#define S3C_IRDA_DEBUG
++#undef S3C_IRDA_DEBUG
++
++#ifdef S3C_IRDA_DEBUG
++#define DBG(x...) printk(PFX x)
++#else
++#define DBG(x...) do { } while (0)
++#endif
++
++#define DRIVER_NAME "s3c-irda"
++#define PFX DRIVER_NAME ": "
++
++#if 0
++static int power_level = 3;
++static int tx_lpm;
++#endif
++static int max_rate = 115200;
++
++struct s3c_irda {
++ unsigned char hscr0;
++ unsigned char utcr4;
++ unsigned char power;
++ unsigned char open;
++
++ int speed;
++ int newspeed;
++
++ struct sk_buff *txskb;
++ struct sk_buff *rxskb;
++
++ struct net_device_stats stats;
++ struct device *dev;
++ struct irda_platform_data *pdata;
++ struct irlap_cb *irlap;
++ struct qos_info qos;
++
++ iobuff_t tx_buff;
++ iobuff_t rx_buff;
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ unsigned int sir_irq;
++#else
++ unsigned int sir_rx_irq;
++ unsigned int sir_tx_irq;
++ unsigned int sir_err_irq;
++#endif
++
++ struct resource *sir_mem;
++ struct clk *sir_clk;
++ void __iomem *sir_base;
++ int dma;
++};
++
++
++#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
++#define S3C_SIR_MAX_RXLEN 2047
++
++static const unsigned int nSlotTable[16] = {0x0000,0x0080,0x0808,0x8888,0x2222,0x4924,0x4a52,0x54aa,
++ 0x5555,0xd555,0xd5d5,0xddd5,0xdddd,0xdfdd,0xdfdf,0xffdf};
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++// UART3 port has been reserved for Irda.
++#define sir_writereg(val,reg) writel(val, (S3C24XX_VA_UART3 + reg))
++#define sir_readreg(reg) readl(S3C24XX_VA_UART3 + reg)
++#else
++#define sir_writereg(val,reg) writel(val, (S3C24XX_VA_UART2 + reg))
++#define sir_readreg(reg) readl(S3C24XX_VA_UART2 + reg)
++#endif
++
++
++extern int clk_enable(struct clk *clk);
++extern unsigned long clk_get_rate(struct clk *clk);
++extern struct clk *clk_get(struct device *dev, const char *id);
++extern void clk_put(struct clk *clk);
++extern void clk_disable(struct clk *clk);
++
++
++static void s3c_irda_gpio_conf(void)
++{
++#if defined(CONFIG_CPU_S3C2412)
++ gpio_set_pin(S3C_GPH6, S3C_GPH6_TXD2);
++ gpio_set_pin(S3C_GPH7, S3C_GPH7_RXD2);
++ gpio_set_pin(S3C_GPG12, S3C_GPG12_OUTP);
++ gpio_set_pin(S3C_GPH8, S3C_GPH8_UCLK);
++ gpio_set_value(S3C_GPG12, 1);
++#endif
++
++
++#if defined(CONFIG_CPU_S3C2443)
++ gpio_set_pin(S3C_GPH4, S3C_GPH4_TXD2);
++ gpio_set_pin(S3C_GPH5, S3C_GPH5_RXD2);
++ gpio_set_pin(S3C_GPH12, S3C_GPH12_UCLK);
++#endif
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_TXD1);
++ s3c2410_gpio_cfgpin(S3C2410_GPH5, S3C2410_GPH5_RXD1);
++ s3c2410_gpio_cfgpin(S3C2410_GPH12, S3C2410_GPH12_EXTUART);
++#endif
++
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ gpio_set_pin(S3C_GPB3, S3C_GPB3_UART_TXD3);
++ gpio_set_pin(S3C_GPB2, S3C_GPB2_UART_RXD3);
++ //gpio_set_pin(S3C_GPH12, S3C_GPH12_UCLK);
++#endif
++
++}
++
++
++static int s3c_irda_sir_init(struct s3c_irda *si)
++{
++ u32 ucon,ulcon,ufcon;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ // Enable uart clock
++ clk_enable(si->sir_clk);
++
++ s3c_irda_gpio_conf();
++
++ ulcon = S3C_LCON_IRM | S3C_LCON_PNONE | S3C_LCON_CS8;
++ ucon = S3C_UCON_PCLK | S3C_UCON_TXILEVEL | S3C_UCON_RXILEVEL |S3C_UCON_RXFIFO_TOI| S3C_UCON_RX_ESIE | S3C_UCON_LOOP_OPERATION | S3C_UCON_NO_SBS | S3C_UCON_RXIRQMODE;
++ ufcon = S3C_UFCON_TXTRIG16 | S3C_UFCON_RXTRIG32 | S3C_UFCON_RESETBOTH| S3C_UFCON_FIFO_ENABLE;
++
++
++ sir_writereg(ulcon, S3C_ULCON);
++ sir_writereg(ufcon, S3C_UFCON);
++ sir_writereg(ucon, S3C_UCON);
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ enable_irq(si->sir_err_irq);
++ enable_irq(si->sir_tx_irq);
++ enable_irq(si->sir_rx_irq);
++#endif
++
++ return 0;
++}
++
++
++static int s3c_irda_sir_stop(struct s3c_irda *si)
++{
++ DBG("%s\r\n",__FUNCTION__);
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ disable_irq(si->sir_irq);
++#else
++ disable_irq(si->sir_rx_irq);
++ disable_irq(si->sir_tx_irq);
++ disable_irq(si->sir_err_irq);
++#endif
++
++ sir_writereg(0, S3C_ULCON);
++ sir_writereg(0, S3C_UFCON);
++ sir_writereg(0, S3C_UCON);
++
++ // disable uart clock
++ clk_disable(si->sir_clk);
++
++ return 0;
++}
++
++
++//extern unsigned int s3c24xx_pclk;
++static int s3c_irda_sir_setspeed(struct s3c_irda *si, u32 speed)
++{
++ u32 ubrdiv, pclk;
++ int slot = -1;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ pclk = clk_get_rate(si->sir_clk);
++ ubrdiv = (int) (pclk/16/speed ) - 1;
++
++ DBG("sir : pclk %d speed %d ubrdiv %d \r\n",pclk,speed,ubrdiv);
++
++ sir_writereg(ubrdiv,S3C_UBRDIV);
++
++ if(slot >= 0){
++ sir_writereg(nSlotTable[slot], S3C_UDIVSLOT);
++ }
++ return 0;
++}
++
++
++/*
++ * Set the IrDA communications speed.
++ */
++static int s3c_irda_set_speed(struct s3c_irda *si, int speed)
++{
++ unsigned long flags;
++ int ret = -EINVAL;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ switch (speed) {
++ case 9600: case 19200: case 38400:
++ case 57600: case 115200:
++
++ local_irq_save(flags);
++ s3c_irda_sir_setspeed(si,speed);
++ si->speed = speed;
++ local_irq_restore(flags);
++ ret = 0;
++ break;
++
++ default:
++ break;
++ }
++
++ return ret;
++
++}
++
++
++/*
++ * Control the power state of the IrDA transmitter.
++ * State:
++ * 0 - off
++ * 1 - short range, lowest power
++ * 2 - medium range, medium power
++ * 3 - maximum range, high power
++ *
++ * Currently, only assabet is known to support this.
++ */
++static int
++__s3c_irda_set_power(struct s3c_irda *si, unsigned int state)
++{
++ int ret = 0;
++ DBG("%s\r\n",__FUNCTION__);
++
++ if (si->pdata->set_power)
++ ret = si->pdata->set_power(si->dev, state);
++ return ret;
++}
++
++
++static inline int s3c_set_power(struct s3c_irda *si, unsigned int state)
++{
++ int ret;
++ DBG("%s\r\n",__FUNCTION__);
++
++ ret = __s3c_irda_set_power(si, state);
++ if (ret == 0)
++ si->power = state;
++
++ return ret;
++}
++
++static int s3c_irda_startup(struct s3c_irda *si)
++{
++ int ret;
++
++ /*
++ * Ensure that the ports for this device are setup correctly.
++ */
++
++ DBG("%s\r\n",__FUNCTION__);
++
++#if defined(CONFIG_CPU_S3C2412)
++ gpio_pullup(S3C_GPH6, 1);
++ gpio_pullup(S3C_GPH7, 1);
++ gpio_pullup(S3C_GPH8, 1);
++ gpio_pullup(S3C_GPG12, 1);
++#endif
++
++#if defined(CONFIG_CPU_S3C2443)
++ gpio_pullup(S3C_GPH4, 1);
++ gpio_pullup(S3C_GPH5, 1);
++ gpio_pullup(S3C_GPH12, 1);
++#endif
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ s3c2410_gpio_pullup(S3C2410_GPH4, 1);
++ s3c2410_gpio_pullup(S3C2410_GPH5, 1);
++ s3c2410_gpio_pullup(S3C2410_GPH12, 1);
++#endif
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ gpio_pullup(S3C_GPB3, 1);
++ gpio_pullup(S3C_GPB2, 1);
++// gpio_pullup(S3C_GPH12, 1);
++#endif
++
++ ret = s3c_irda_sir_init(si);
++ if(ret) {
++ printk("Irda Startup failed\r\n");
++ return ret;
++ }
++
++ ret = s3c_irda_set_speed(si, si->speed = 9600);
++ if (ret) {
++ s3c_irda_sir_stop(si);
++ }
++
++ return ret;
++}
++
++static void s3c_irda_shutdown(struct s3c_irda *si)
++{
++ DBG("%s\r\n",__FUNCTION__);
++ s3c_irda_sir_stop(si);
++}
++
++
++#ifdef CONFIG_PM
++/*
++ * Suspend the IrDA interface.
++ */
++static int s3c_irda_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct net_device *dev = platform_get_drvdata(pdev);
++ struct s3c_irda *si;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ if (!dev)
++ return 0;
++
++ si = dev->priv;
++ if (si->open) {
++ /*
++ * Stop the transmit queue
++ */
++ netif_device_detach(dev);
++ //disable_irq(dev->irq);
++ s3c_irda_shutdown(si);
++ __s3c_irda_set_power(si, 0);
++ }
++
++ return 0;
++}
++
++
++/*
++ * Resume the IrDA interface.
++ */
++static int s3c_irda_resume(struct platform_device *pdev)
++{
++ struct net_device *dev = platform_get_drvdata(pdev);
++ struct s3c_irda *si;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ if (!dev)
++ return 0;
++
++ si = dev->priv;
++ if (si->open) {
++ /*
++ * If we missed a speed change, initialise at the new speed
++ * directly. It is debatable whether this is actually
++ * required, but in the interests of continuing from where
++ * we left off it is desireable. The converse argument is
++ * that we should re-negotiate at 9600 baud again.
++ */
++ if (si->newspeed) {
++ si->speed = si->newspeed;
++ si->newspeed = 0;
++ }
++
++ s3c_irda_startup(si);
++ __s3c_irda_set_power(si, si->power);
++
++ /*
++ * This automatically wakes up the queue
++ */
++ netif_device_attach(dev);
++ }
++
++ return 0;
++}
++#else
++#define s3c_irda_suspend NULL
++#define s3c_irda_resume NULL
++#endif
++
++
++/*
++ * SIR format interrupt service routines.
++ */
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++static irqreturn_t s3c_irda_sir_irq(int irq, void *dev_id)
++{
++
++ struct net_device *dev = dev_id;
++ struct s3c_irda *si = dev->priv;
++ int err_status;
++
++ u8 data;
++ u32 ucon, ufcon, ufstat, intpnd;
++
++ intpnd = sir_readreg(S3C_UINTPND);
++ DBG("%s == 0x%1x\r\n",__FUNCTION__, sir_readreg(S3C_UINTPND));
++
++ err_status = sir_readreg(S3C_UERSTAT);
++
++ if(err_status) {
++ printk("Error : 0x%x\n", sir_readreg(S3C_UERSTAT));
++ data = sir_readreg(S3C_URXH);
++ si->stats.rx_errors++;
++ si->stats.rx_frame_errors++;
++ }
++ if(intpnd & UART_ERR_INT){
++ printk(KERN_DEBUG "Uart Error = 0x%1x", intpnd);
++ sir_writereg(UART_ERR_INT , S3C_UINTPND);
++ sir_readreg(S3C_UINTPND);
++ }
++ if(intpnd & UART_RX_INT) {
++ DBG("Rx intr : 0x%1x\n", intpnd);
++ sir_writereg(UART_RX_INT , S3C_UINTPND);
++ sir_readreg(S3C_UINTPND);
++ DBG("Rx intr : 0x%1x\n", intpnd);
++
++ while ((sir_readreg(S3C_UFSTAT) & 0X3F) > 0) {
++ data = sir_readreg(S3C_URXH);
++ async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
++ }
++ dev->last_rx = jiffies;
++
++ // Clear fifo
++ ufcon = sir_readreg(S3C_UFCON);
++ ufcon |= 3;
++ sir_writereg(ufcon,S3C_UFCON);
++ }
++
++ if(intpnd & UART_TX_INT) {
++
++ DBG("Tx intr : 0x%1x\n", intpnd);
++ sir_writereg(UART_TX_INT , S3C_UINTPND);
++ sir_readreg(S3C_UINTPND);
++ DBG("Tx intr : 0x%1x\n", intpnd);
++
++ if(si->tx_buff.len > 0) {
++
++ ufstat = sir_readreg(S3C_UFSTAT);
++ /*
++ * Transmitter FIFO is not full
++ */
++ while (!(ufstat & (1 << 14)) ) {
++ while(!(sir_readreg(S3C_UTRSTAT)&0x02));
++ sir_writereg(*si->tx_buff.data++,S3C_UTXH);
++ if(si->tx_buff.len == 0)
++ break;
++ si->tx_buff.len -= 1;
++ rmb();
++ ufstat = sir_readreg(S3C_UFSTAT);
++ }
++
++ if (si->tx_buff.len == 0) {
++ si->stats.tx_packets++;
++ si->stats.tx_bytes += si->tx_buff.data -
++ si->tx_buff.head;
++
++ /*
++ * We need to ensure that the transmitter has
++ * finished.
++ */
++ do {
++ rmb();
++ ufstat = sir_readreg(S3C_UFSTAT);
++ } while (((ufstat >> 8 )& 0x3f ) > 0);
++
++ /*
++ * Ok, we've finished transmitting. Now enable
++ * the receiver. Sometimes we get a receive IRQ
++ * immediately after a transmit...
++ */
++ ufcon = sir_readreg(S3C_UFCON);
++ ufcon |= 7;
++ sir_writereg(ufcon, S3C_UFCON);
++
++ ucon = sir_readreg(S3C_UCON);
++ ucon &= ~( 3 << 2);
++ sir_writereg(ucon, S3C_UCON);
++
++ if (si->newspeed) {
++ s3c_irda_set_speed(si, si->newspeed);
++ si->newspeed = 0;
++ }
++
++ if (1) {
++ ucon |= 1;
++ sir_writereg(ucon, S3C_UCON);
++ }
++
++ netif_wake_queue(dev);
++ }
++ }
++ }
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ if(intpnd & UART_MODEM_INT) {
++ printk("MODEM interrupt ...\n");
++ }
++#endif
++
++ return IRQ_HANDLED;
++
++}
++
++#else
++
++static irqreturn_t s3c_irda_sir_irq(int irq, void *dev_id, struct pt_regs *regs)
++{
++ struct net_device *dev = dev_id;
++ struct s3c_irda *si = dev->priv;
++ int err_status;
++ u8 data;
++
++#ifdef S3C_IRDA_DEBUG
++ printk("%s\r\n",__FUNCTION__);
++#endif
++
++ err_status = sir_readreg(S3C_UERSTAT);
++
++ if(err_status) {
++#ifdef S3C_IRDA_DEBUG
++ printk("Rx Error");
++#endif
++ data = sir_readreg(S3C_URXH);
++ si->stats.rx_errors++;
++ si->stats.rx_frame_errors++;
++ }
++
++ if(irq == si->sir_rx_irq) {
++#ifdef S3C_IRDA_DEBUG
++ printk("Rx intr");
++#endif
++
++ while ((sir_readreg(S3C_UFSTAT) & 0X3F) > 0) {
++ data = sir_readreg(S3C_URXH);
++ async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
++ }
++ dev->last_rx = jiffies;
++ }
++
++ if((irq == si->sir_tx_irq) && (si->tx_buff.len > 0) ) {
++ u32 ufstat;
++#ifdef S3C_IRDA_DEBUG
++ printk("Tx intr");
++#endif
++
++ ufstat = sir_readreg(S3C_UFSTAT);
++ /*
++ * Transmitter FIFO is not full
++ */
++ while (!(ufstat & (1 << 14)) ){
++ while(!(sir_readreg(S3C_UTRSTAT)&0x02));
++ sir_writereg(*si->tx_buff.data++,S3C_UTXH);
++ if(si->tx_buff.len == 0)
++ break;
++ si->tx_buff.len -= 1;
++ rmb();
++ ufstat = sir_readreg(S3C_UFSTAT);
++ };
++
++ if (si->tx_buff.len == 0) {
++ u32 ucon,ufcon;
++
++ si->stats.tx_packets++;
++ si->stats.tx_bytes += si->tx_buff.data -
++ si->tx_buff.head;
++
++ /*
++ * We need to ensure that the transmitter has
++ * finished.
++ */
++ do {
++ rmb();
++ ufstat = sir_readreg(S3C_UFSTAT);
++ }while (((ufstat >> 8 )& 0x3f ) > 0);
++
++ /*
++ * Ok, we've finished transmitting. Now enable
++ * the receiver. Sometimes we get a receive IRQ
++ * immediately after a transmit...
++ */
++ ucon = sir_readreg(S3C_UCON);
++ ucon &= ~( 3 << 2);
++ sir_writereg(ucon,S3C_UCON);
++
++ ufcon = sir_readreg(S3C_UFCON);
++ ufcon |= 7;
++
++ sir_writereg(ufcon,S3C_UFCON);
++
++ if (si->newspeed) {
++ s3c_irda_set_speed(si, si->newspeed);
++ si->newspeed = 0;
++ }
++ if (1) {
++ ucon |= 1;
++ sir_writereg(ucon,S3C_UCON);
++ }
++
++ /* I'm hungry! */
++ netif_wake_queue(dev);
++ }
++ }
++ return IRQ_HANDLED;
++
++}
++#endif
++
++
++static int s3c_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct s3c_irda *si = dev->priv;
++ int speed = irda_get_next_speed(skb);
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ /*
++ * Does this packet contain a request to change the interface
++ * speed? If so, remember it until we complete the transmission
++ * of this frame.
++ */
++ if (speed != si->speed && speed != -1) {
++ DBG("Irda New Speed %d bps\r\n",speed);
++
++ si->newspeed = speed;
++ }
++ /*
++ * If this is an empty frame, we can bypass a lot.
++ */
++ if (skb->len == 0) {
++ if (si->newspeed) {
++ si->newspeed = 0;
++ s3c_irda_set_speed(si, speed);
++ }
++ dev_kfree_skb(skb);
++ return 0;
++ }
++
++ {
++ u32 ucon, ufcon, len, bytes;
++ u8 *cp;
++
++ netif_stop_queue(dev);
++
++ cp = si->tx_buff.data = si->tx_buff.head;
++ len = si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data,
++ si->tx_buff.truesize);
++
++ /*
++ * Set the transmit interrupt enable. This will fire
++ * off an interrupt immediately. Note that we disable
++ * the receiver so we won't get spurious characteres
++ * received.
++ */
++
++ // Stop Rx
++ // UCON : Receive Mode Disable
++ ucon = sir_readreg(S3C_UCON);
++ ucon &= ~( 3); // UCON : Receive Mode Disable
++ sir_writereg(ucon,S3C_UCON);
++
++ // Clear fifo
++ ufcon = sir_readreg(S3C_UFCON);
++ ufcon |= 7;
++ sir_writereg(ufcon,S3C_UFCON);
++
++ // Enable Tx and Tx Int
++#if defined(CONFIG_CPU_S3C2412)
++ gpio_set_value(S3C_GPG12, 0);
++#endif
++
++ // UCON : Transmit Mode - 01 - Interrupt request or polling mode
++ ucon |= (1 << 2 );
++ sir_writereg(ucon,S3C_UCON);
++
++ dev_kfree_skb(skb);
++ }
++
++ dev->trans_start = jiffies;
++ return 0;
++}
++
++
++static int s3c_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
++{
++ struct if_irda_req *rq = (struct if_irda_req *)ifreq;
++ struct s3c_irda *si = dev->priv;
++ int ret = -EOPNOTSUPP;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ switch (cmd) {
++ case SIOCSBANDWIDTH:
++
++ if (capable(CAP_NET_ADMIN)) {
++ /*
++ * We are unable to set the speed if the
++ * device is not running.
++ */
++ if (si->open) {
++ ret = s3c_irda_set_speed(si,
++ rq->ifr_baudrate);
++ } else {
++ DBG("s3c_irda_ioctl: SIOCSBANDWIDTH: !netif_running\n");
++ ret = 0;
++ }
++ }
++ break;
++
++ case SIOCSMEDIABUSY:
++ ret = -EPERM;
++ if (capable(CAP_NET_ADMIN)) {
++ irda_device_set_media_busy(dev, TRUE);
++ ret = 0;
++ }
++ break;
++
++ case SIOCGRECEIVING:
++ rq->ifr_receiving = si->rx_buff.state != OUTSIDE_FRAME;
++ ret = 0;
++ break;
++
++ default:
++ break;
++ }
++
++ return ret;
++}
++
++
++static struct net_device_stats *s3c_irda_stats(struct net_device *dev)
++{
++ struct s3c_irda *si = dev->priv;
++
++ DBG("%s\r\n",__FUNCTION__);
++ return &si->stats;
++}
++
++static int s3c_irda_start(struct net_device *dev)
++{
++ struct s3c_irda *si = dev->priv;
++ int err;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ si->speed = 9600;
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ err = request_irq(si->sir_irq, s3c_irda_sir_irq, 0, dev->name, dev);
++ if (err)
++ goto err_irq1;
++#else
++ err = request_irq(si->sir_rx_irq, s3c_irda_sir_irq, 0, dev->name, dev);
++ if (err)
++ goto err_irq1;
++ err = request_irq(si->sir_tx_irq, s3c_irda_sir_irq, 0, dev->name, dev);
++ if (err)
++ goto err_irq2;
++ err = request_irq(si->sir_err_irq, s3c_irda_sir_irq, 0, dev->name, dev);
++ if (err)
++ goto err_irlap;
++#endif
++
++ /*
++ * The interrupt must remain disabled for now.
++ */
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ disable_irq(si->sir_irq);
++#else
++ disable_irq(si->sir_rx_irq);
++ disable_irq(si->sir_tx_irq);
++ disable_irq(si->sir_err_irq);
++#endif
++
++ /*
++ * Setup the serial port for the specified speed.
++ */
++ err = s3c_irda_startup(si);
++ if (err)
++ goto err_irq2;
++
++ /*
++ * Open a new IrLAP layer instance.
++ */
++ si->irlap = irlap_open(dev, &si->qos, "s3c");
++
++ err = -ENOMEM;
++ if (!si->irlap)
++ goto err_irlap;
++
++ /*
++ * Now enable the interrupt and start the queue
++ */
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ enable_irq(si->sir_irq);
++#endif
++ si->open = 1;
++ netif_start_queue(dev);
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ sir_writereg(0,S3C_UINTMSK); // clean mask
++#endif
++ return 0;
++
++err_irlap:
++ si->open = 0;
++ s3c_irda_shutdown(si);
++err_irq2:
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ free_irq(si->sir_irq, dev);
++#else
++ free_irq(si->sir_err_irq, dev);
++ free_irq(si->sir_rx_irq, dev);
++ free_irq(si->sir_tx_irq, dev);
++#endif
++err_irq1:
++ return err;
++}
++
++static int s3c_irda_stop(struct net_device *dev)
++{
++ struct s3c_irda *si = dev->priv;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ disable_irq(si->sir_irq);
++#else
++ disable_irq(si->sir_rx_irq);
++ disable_irq(si->sir_tx_irq);
++ disable_irq(si->sir_err_irq);
++#endif
++
++ s3c_irda_shutdown(si);
++
++ /*
++ * If we have been doing DMA receive, make sure we
++ * tidy that up cleanly.
++ */
++ if (si->rxskb) {
++ dev_kfree_skb(si->rxskb);
++ si->rxskb = NULL;
++ }
++
++ /* Stop IrLAP */
++ if (si->irlap) {
++ irlap_close(si->irlap);
++ si->irlap = NULL;
++ }
++
++ netif_stop_queue(dev);
++ si->open = 0;
++
++ /*
++ * Free resources
++ */
++ //free_irq(dev->irq, dev);
++
++// s3c_set_power(si, 0);
++ return 0;
++}
++
++static int s3c_irda_init_iobuf(iobuff_t *io, int size)
++{
++ DBG("%s\r\n",__FUNCTION__);
++
++ io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
++
++ if (io->head != NULL) {
++ io->truesize = size;
++ io->in_frame = FALSE;
++ io->state = OUTSIDE_FRAME;
++ io->data = io->head;
++ }
++
++ return io->head ? 0 : -ENOMEM;
++}
++
++
++static int s3c_irda_init_mem( struct s3c_irda *si,
++ struct platform_device *pdev)
++{
++ int ret = 0;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ si->sir_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (!si->sir_mem) {
++ printk("failed to get io sir_memory region resouce.\n");
++ return -ENOENT;
++ }
++
++ if(NULL == request_mem_region(si->sir_mem->start,
++ RESSIZE(si->sir_mem), pdev->name)) {
++ printk("failed to request io sir memory region.\n");
++ ret = -ENOENT;
++ }
++
++ return ret;
++}
++
++
++static int s3c_irda_free_mem( struct s3c_irda *si)
++{
++ DBG("%s\r\n",__FUNCTION__);
++
++// iounmap(si->sir_base);
++ release_mem_region(si->sir_mem->start, RESSIZE(si->sir_mem));
++ return 0;
++}
++
++static int s3c_irda_init_clk(struct device *dev,
++ struct s3c_irda *si)
++{
++ int ret;
++ DBG("%s \r\n",__FUNCTION__);
++
++#if defined(CONFIG_CPU_S3C2443)
++ si->sir_clk = clk_get(dev, "uart2");
++#endif
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ si->sir_clk = clk_get(dev, "uart");
++#endif
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ si->sir_clk = clk_get(dev, "UART2");
++#endif
++
++ if (IS_ERR(si->sir_clk)) {
++ DBG(KERN_INFO PFX "failed to find sir clock source.\n");
++ ret = PTR_ERR(si->sir_clk);
++ si->sir_clk = NULL;
++ goto sir_free_si;
++ }
++
++ /*Please edit for s3cx*/
++ if((ret = clk_enable(si->sir_clk))) {
++ printk("failed to use sir clock source.\n");
++ ret =-ENODEV;
++ goto sir_clk_free;
++ }
++
++ return 0;
++
++sir_clk_free:
++ clk_put(si->sir_clk);
++sir_free_si:
++ return ret;
++}
++
++
++static int s3c_irda_stop_clk( struct s3c_irda *si)
++{
++ DBG("%s\r\n",__FUNCTION__);
++
++ clk_disable(si->sir_clk);
++ clk_put(si->sir_clk);
++ return 0;
++}
++
++
++static int s3c_irda_probe(struct platform_device *pdev)
++{
++ struct net_device *dev;
++ struct s3c_irda *si;
++ unsigned int baudrate_mask;
++ int err;
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ dev = alloc_irdadev(sizeof(struct s3c_irda));
++ if (!dev){
++ printk("alloc_irdadev Error! \r\n");
++ return -ENOMEM;
++ }
++
++ si = dev->priv;
++ si->dev = &pdev->dev;
++ si->pdata = pdev->dev.platform_data;
++
++ if( (err = s3c_irda_init_mem(si,pdev)) != 0)
++ goto err_mem;
++
++
++ err = s3c_irda_init_iobuf(&si->rx_buff, 14384);
++ if (err)
++ goto err_iobuf_rx;
++#if 0
++ err = s3c_irda_init_iobuf(&si->tx_buff, 4000);
++#else
++ err = s3c_irda_init_iobuf(&si->tx_buff, 14384);
++#endif
++
++ if (err)
++ goto err_iobuf_tx;
++
++ dev->hard_start_xmit = s3c_irda_hard_xmit;
++ dev->open = s3c_irda_start;
++ dev->stop = s3c_irda_stop;
++ dev->do_ioctl = s3c_irda_ioctl;
++ dev->get_stats = s3c_irda_stats;
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ si->sir_irq = platform_get_irq(pdev, 0);
++
++ if (si->sir_irq == 0) {
++ printk("failed to get interrupt resouce.\n");
++ goto err_irq;
++ }
++#else
++ si->sir_rx_irq = platform_get_irq(pdev, 0);
++ if (si->sir_rx_irq == 0) {
++#ifdef S3C_IRDA_DEBUG
++ printk("failed to get interrupt resouce.\n");
++#endif
++
++ goto err_irq;
++ }
++
++ si->sir_tx_irq = si->sir_rx_irq + 1;
++ si->sir_err_irq = si->sir_rx_irq + 2;
++#endif
++
++ if(s3c_irda_init_clk(&pdev->dev,si)!= 0)
++ goto err_irq;
++
++ irda_init_max_qos_capabilies(&si->qos);
++
++ baudrate_mask = IR_9600|IR_19200|IR_38400|IR_57600|IR_115200;
++
++ switch (max_rate) {
++ case 115200: baudrate_mask |= IR_115200;
++ case 57600: baudrate_mask |= IR_57600;
++ case 38400: baudrate_mask |= IR_38400;
++ case 19200: baudrate_mask |= IR_19200;
++ }
++
++ si->qos.baud_rate.bits &= baudrate_mask;
++ si->qos.min_turn_time.bits = 7;
++
++ irda_qos_bits_to_value(&si->qos);
++
++ sir_writereg(0, S3C_UCON);
++ sir_writereg(0, S3C_ULCON);
++
++// __raw_writel(7 << 3, S3C_SUBSRCPND);
++// __raw_writel(1 << 23, S3C_SRCPND);
++
++ err = register_netdev(dev);
++ if (err == 0){
++ platform_set_drvdata(pdev, dev);
++ DBG("%s success \r\n",__FUNCTION__);
++ }
++
++ if (err) {
++ s3c_irda_stop_clk(si);
++ err_irq:
++ kfree(si->tx_buff.head);
++ err_iobuf_tx:
++ kfree(si->rx_buff.head);
++ err_iobuf_rx:
++ s3c_irda_free_mem(si);
++ err_mem:
++ free_netdev(dev);
++ }
++ return err;
++}
++
++
++static int s3c_irda_remove(struct platform_device *pdev)
++{
++ struct net_device *dev = platform_get_drvdata(pdev);
++
++ DBG("%s\r\n",__FUNCTION__);
++
++ if (dev) {
++ struct s3c_irda *si = dev->priv;
++ unregister_netdev(dev);
++ kfree(si->tx_buff.head);
++ kfree(si->rx_buff.head);
++ s3c_irda_free_mem(si);
++ s3c_irda_stop_clk(si);
++ free_netdev(dev);
++ }
++
++ return 0;
++}
++
++
++static struct platform_driver s3c_irda_driver = {
++ .probe = s3c_irda_probe,
++ .remove = s3c_irda_remove,
++ .suspend = s3c_irda_suspend,
++ .resume = s3c_irda_resume,
++ .driver = {
++ .name = "s3c-irda",
++ },
++};
++
++static char banner[] = KERN_INFO "S3C IrDA driver, (c) 2006 Samsung Electronics\n";
++
++static int __init s3c_irda_init(void)
++{
++ printk(banner);
++ return platform_driver_register(&s3c_irda_driver);
++
++}
++
++
++static void __exit s3c_irda_exit(void)
++{
++ DBG("%s\r\n",__FUNCTION__);
++ platform_driver_unregister(&s3c_irda_driver);
++}
++
++
++module_init(s3c_irda_init);
++module_exit(s3c_irda_exit);
++
++MODULE_AUTHOR("alinuxguy <alinuxguy@samsung.com>");
++MODULE_DESCRIPTION("S3C IrDA driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
+index 76cc1d3..264bd05 100644
+--- a/drivers/net/smc911x.c
++++ b/drivers/net/smc911x.c
+@@ -1986,6 +1986,17 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
+
+ spin_lock_init(&lp->lock);
+
++#if defined(CONFIG_MACH_SMDK6410) || defined(CONFIG_MACH_SMDK2450) || defined(CONFIG_MACH_SMDK2416)
++ dev->dev_addr[0] = 0x00;
++ dev->dev_addr[1] = 0x09;
++ dev->dev_addr[2] = 0xc0;
++ dev->dev_addr[3] = 0xff;
++ dev->dev_addr[4] = 0xec;
++ dev->dev_addr[5] = 0x48;
++
++ SMC_SET_MAC_ADDR(dev->dev_addr);
++#endif
++
+ /* Get the MAC address */
+ SMC_GET_MAC_ADDR(dev->dev_addr);
+
+diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
+index 7defa63..9ae3c87 100644
+--- a/drivers/net/smc911x.h
++++ b/drivers/net/smc911x.h
+@@ -37,7 +37,7 @@
+ #define SMC_USE_16BIT 0
+ #define SMC_USE_32BIT 1
+ #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
+-#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
++#elif defined(CONFIG_SH_MAGIC_PANEL_R2) || defined(CONFIG_MACH_SMDK6410) || defined(CONFIG_MACH_SMDK2450) || defined(CONFIG_MACH_SMDK2416)
+ #define SMC_USE_SH_DMA 0
+ #define SMC_USE_16BIT 0
+ #define SMC_USE_32BIT 1
+diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
+index e2041b4..de5dbcd 100644
+--- a/drivers/rtc/rtc-s3c.c
++++ b/drivers/rtc/rtc-s3c.c
+@@ -44,6 +44,14 @@ static int s3c_rtc_freq = 1;
+ static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
+ static unsigned int tick_count;
+
++/* common function function */
++
++extern void s3c_rtc_set_pie(void __iomem *base, uint to);
++extern void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, unchar *s3c_freq);
++extern void s3c_rtc_enable_set(struct platform_device *dev,void __iomem *base, int en);
++extern unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val);
++extern unsigned int s3c_rtc_read_alarm_status(void __iomem *base);
++
+ /* IRQ Handlers */
+
+ static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
+@@ -51,6 +59,9 @@ static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
+ struct rtc_device *rdev = id;
+
+ rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
++
++ s3c_rtc_set_bit_byte(s3c_rtc_base,S3C_INTP,S3C_INTP_ALM);
++
+ return IRQ_HANDLED;
+ }
+
+@@ -59,6 +70,9 @@ static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
+ struct rtc_device *rdev = id;
+
+ rtc_update_irq(rdev, tick_count++, RTC_PF | RTC_IRQF);
++
++ s3c_rtc_set_bit_byte(s3c_rtc_base,S3C_INTP,S3C_INTP_TIC);
++
+ return IRQ_HANDLED;
+ }
+
+@@ -75,36 +89,32 @@ static void s3c_rtc_setaie(int to)
+ tmp |= S3C2410_RTCALM_ALMEN;
+
+ writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
++
++ if (s3c_rtc_read_alarm_status(s3c_rtc_base))
++
++ enable_irq_wake(s3c_rtc_alarmno);
++ else
++ disable_irq_wake(s3c_rtc_alarmno);
++
+ }
+
+ static void s3c_rtc_setpie(int to)
+ {
+- unsigned int tmp;
+-
+ pr_debug("%s: pie=%d\n", __FUNCTION__, to);
+
+ spin_lock_irq(&s3c_rtc_pie_lock);
+- tmp = readb(s3c_rtc_base + S3C2410_TICNT) & ~S3C2410_TICNT_ENABLE;
+
+- if (to)
+- tmp |= S3C2410_TICNT_ENABLE;
++ s3c_rtc_set_pie(s3c_rtc_base,to);
+
+- writeb(tmp, s3c_rtc_base + S3C2410_TICNT);
+ spin_unlock_irq(&s3c_rtc_pie_lock);
+ }
+
+ static void s3c_rtc_setfreq(int freq)
+ {
+- unsigned int tmp;
+-
+ spin_lock_irq(&s3c_rtc_pie_lock);
+- tmp = readb(s3c_rtc_base + S3C2410_TICNT) & S3C2410_TICNT_ENABLE;
+-
+- s3c_rtc_freq = freq;
+
+- tmp |= (128 / freq)-1;
++ s3c_rtc_set_freq_regs(s3c_rtc_base,freq,&s3c_rtc_freq);
+
+- writeb(tmp, s3c_rtc_base + S3C2410_TICNT);
+ spin_unlock_irq(&s3c_rtc_pie_lock);
+ }
+
+@@ -153,6 +163,7 @@ static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
+ static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
+ {
+ void __iomem *base = s3c_rtc_base;
++
+ int year = tm->tm_year - 100;
+
+ pr_debug("set time %02d.%02d.%02d %02d/%02d/%02d\n",
+@@ -277,11 +288,6 @@ static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+ disable_irq_wake(s3c_rtc_alarmno);
+ }
+
+- if (alrm->enabled)
+- enable_irq_wake(s3c_rtc_alarmno);
+- else
+- disable_irq_wake(s3c_rtc_alarmno);
+-
+ return 0;
+ }
+
+@@ -403,36 +409,7 @@ static void s3c_rtc_enable(struct platform_device *pdev, int en)
+ if (s3c_rtc_base == NULL)
+ return;
+
+- if (!en) {
+- tmp = readb(base + S3C2410_RTCCON);
+- writeb(tmp & ~S3C2410_RTCCON_RTCEN, base + S3C2410_RTCCON);
+-
+- tmp = readb(base + S3C2410_TICNT);
+- writeb(tmp & ~S3C2410_TICNT_ENABLE, base + S3C2410_TICNT);
+- } else {
+- /* re-enable the device, and check it is ok */
+-
+- if ((readb(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){
+- dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
+-
+- tmp = readb(base + S3C2410_RTCCON);
+- writeb(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON);
+- }
+-
+- if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){
+- dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
+-
+- tmp = readb(base + S3C2410_RTCCON);
+- writeb(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON);
+- }
+-
+- if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){
+- dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
+-
+- tmp = readb(base + S3C2410_RTCCON);
+- writeb(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON);
+- }
+- }
++ s3c_rtc_enable_set(pdev,base,en);
+ }
+
+ static int s3c_rtc_remove(struct platform_device *dev)
+@@ -457,6 +434,7 @@ static int s3c_rtc_probe(struct platform_device *pdev)
+ struct rtc_device *rtc;
+ struct resource *res;
+ int ret;
++ unsigned char bcd_tmp,bcd_loop;
+
+ pr_debug("%s: probe=%p\n", __FUNCTION__, pdev);
+
+@@ -522,7 +500,15 @@ static int s3c_rtc_probe(struct platform_device *pdev)
+ goto err_nortc;
+ }
+
+- rtc->max_user_freq = 128;
++ rtc->max_user_freq = S3C_MAX_CNT;
++
++ /* check rtc time */
++ for (bcd_loop = S3C2410_RTCSEC ; bcd_loop <= S3C2410_RTCYEAR ; bcd_loop +=0x4)
++ {
++ bcd_tmp = readb(s3c_rtc_base + bcd_loop);
++ if(((bcd_tmp & 0xf) > 0x9) || ((bcd_tmp & 0xf0) > 0x90))
++ writeb(0, s3c_rtc_base + bcd_loop);
++ }
+
+ platform_set_drvdata(pdev, rtc);
+ return 0;
+@@ -542,19 +528,38 @@ static int s3c_rtc_probe(struct platform_device *pdev)
+
+ /* RTC Power management control */
+
++static struct timespec s3c_rtc_delta;
+ static int ticnt_save;
+
+ static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+ {
++ struct rtc_time tm;
++ struct timespec time;
++
++ time.tv_nsec = 0;
+ /* save TICNT for anyone using periodic interrupts */
+ ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
++ /* calculate time delta for suspend */
++
++ s3c_rtc_gettime(&pdev->dev, &tm);
++ rtc_tm_to_time(&tm, &time.tv_sec);
++ save_time_delta(&s3c_rtc_delta, &time);
+ s3c_rtc_enable(pdev, 0);
++
+ return 0;
+ }
+
+ static int s3c_rtc_resume(struct platform_device *pdev)
+ {
++ struct rtc_time tm;
++ struct timespec time;
++
++ time.tv_nsec = 0;
++
+ s3c_rtc_enable(pdev, 1);
++ s3c_rtc_gettime(&pdev->dev, &tm);
++ rtc_tm_to_time(&tm, &time.tv_sec);
++ restore_time_delta(&s3c_rtc_delta, &time);
+ writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
+ return 0;
+ }
+diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c
+index facb678..101016e 100644
+--- a/drivers/serial/21285.c
++++ b/drivers/serial/21285.c
+@@ -5,7 +5,7 @@
+ *
+ * Based on drivers/char/serial.c
+ *
+- * $Id: 21285.c,v 1.37 2002/07/28 10:03:27 rmk Exp $
++ * $Id: 21285.c,v 1.2 2008/10/28 10:50:02 ihlee215 Exp $
+ */
+ #include <linux/module.h>
+ #include <linux/tty.h>
+@@ -488,7 +488,7 @@ static int __init serial21285_init(void)
+ {
+ int ret;
+
+- printk(KERN_INFO "Serial: 21285 driver $Revision: 1.37 $\n");
++ printk(KERN_INFO "Serial: 21285 driver $Revision: 1.2 $\n");
+
+ serial21285_setup_ports();
+
+@@ -509,5 +509,5 @@ module_init(serial21285_init);
+ module_exit(serial21285_exit);
+
+ MODULE_LICENSE("GPL");
+-MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver $Revision: 1.37 $");
++MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver $Revision: 1.2 $");
+ MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);
+diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
+index d7e1996..f3f17d5 100644
+--- a/drivers/serial/Kconfig
++++ b/drivers/serial/Kconfig
+@@ -1,7 +1,7 @@
+ #
+ # Serial device configuration
+ #
+-# $Id: Kconfig,v 1.11 2004/03/11 18:08:04 lethal Exp $
++# $Id: Kconfig,v 1.2 2008/07/30 06:46:07 eyryu Exp $
+ #
+
+ menu "Serial drivers"
+@@ -461,6 +461,67 @@ config SERIAL_S3C2410_CONSOLE
+ your boot loader about how to pass options to the kernel at
+ boot time.)
+
++config SERIAL_S3C6400
++ tristate "Samsung S3C6400 Serial port support"
++ depends on CPU_S3C6400 || CPU_S3C6410
++ select SERIAL_CORE
++ help
++ Support for the on-chip UARTs on the Samsung S3C64XX series CPUs,
++ providing /dev/ttySAC0, 1 and 2 (note, some machines may not
++ provide all of these ports, depending on how the serial port
++ pins are configured.
++
++ Currently this driver supports the UARTS on the S3C6400 CPU.
++
++config SERIAL_S3C64XX_CONSOLE
++ bool "Support for console on S3C64XX serial port"
++ depends on SERIAL_S3C6400=y
++ select SERIAL_CORE_CONSOLE
++ help
++ Allow selection of the S3C64XX on-board serial ports for use as
++ an virtual console.
++
++ Even if you say Y here, the currently visible virtual console
++ (/dev/tty0) will still be used as the system console by default, but
++ you can alter that using a kernel command line option such as
++ "console=ttySACx". (Try "man bootparam" or see the documentation of
++ your boot loader about how to pass options to the kernel at
++ boot time.)
++
++config SERIAL_S3C64XX_HS_UART
++ bool "Support for High speed UART(Max.4000000bps) on S3C64XX serial port"
++ depends on SERIAL_S3C6400=y
++ select SERIAL_CORE
++ help
++ Allow High speed UART on the S3C64XX on-board serial ports
++
++config SERIAL_S5PC100
++ tristate "Samsung S5PC100 Serial port support"
++ depends on CPU_S5PC100
++ select SERIAL_CORE
++ help
++ Support for the on-chip UARTs on the Samsung S3C64XX series CPUs,
++ providing /dev/ttySAC0, 1 and 2 (note, some machines may not
++ provide all of these ports, depending on how the serial port
++ pins are configured.
++
++ Currently this driver supports the UARTS on the S5PC100 CPU.
++
++config SERIAL_S5PC1XX_CONSOLE
++ bool "Support for console on S5PC1XX serial port"
++ depends on SERIAL_S5PC100=y
++ select SERIAL_CORE_CONSOLE
++ help
++ Allow selection of the S5PC1XX on-board serial ports for use as
++ an virtual console.
++
++ Even if you say Y here, the currently visible virtual console
++ (/dev/tty0) will still be used as the system console by default, but
++ you can alter that using a kernel command line option such as
++ "console=ttySACx". (Try "man bootparam" or see the documentation of
++ your boot loader about how to pass options to the kernel at
++ boot time.)
++
+ config SERIAL_DZ
+ bool "DECstation DZ serial driver"
+ depends on MACH_DECSTATION && 32BIT
+diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
+index af6377d..8d45997 100644
+--- a/drivers/serial/Makefile
++++ b/drivers/serial/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for the kernel serial device drivers.
+ #
+-# $Id: Makefile,v 1.8 2002/07/21 21:32:30 rmk Exp $
++# $Id: Makefile,v 1.2 2008/07/30 06:46:07 eyryu Exp $
+ #
+
+ obj-$(CONFIG_SERIAL_CORE) += serial_core.o
+@@ -29,6 +29,8 @@ obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
+ obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
+ obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o
+ obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
++obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
++obj-$(CONFIG_SERIAL_S5PC100) += s5pc100.o
+ obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
+ obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
+ obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
+diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
+index e773c8e..2ca26fa 100644
+--- a/drivers/serial/s3c2410.c
++++ b/drivers/serial/s3c2410.c
+@@ -643,7 +643,14 @@ static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
+ rate /= clksrc->divisor;
+
+ calc->clksrc = clksrc;
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ /* Error correction */
++ calc->quot = (rate) / (16 * baud);
++#else
++ /* Error to calculation of UART BAUD RATE DIVISOR */
+ calc->quot = (rate + (8 * baud)) / (16 * baud);
++#endif
+ calc->calc = (rate / (calc->quot * 16));
+
+ calc->quot--;
+@@ -1364,8 +1371,7 @@ static inline void s3c2410_serial_exit(void)
+
+ #endif /* CONFIG_CPU_S3C2410 */
+
+-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+-
++#if defined(CONFIG_CPU_S3C2440)||defined(CONFIG_CPU_S3C2442)||defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
+ static int s3c2440_serial_setsource(struct uart_port *port,
+ struct s3c24xx_uart_clksrc *clk)
+ {
+@@ -1379,7 +1385,11 @@ static int s3c2440_serial_setsource(struct uart_port *port,
+ ucon |= S3C2440_UCON_UCLK;
+ else if (strcmp(clk->name, "pclk") == 0)
+ ucon |= S3C2440_UCON_PCLK;
++#if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ else if (strcmp(clk->name, "esysclk") == 0)
++#else
+ else if (strcmp(clk->name, "fclk") == 0)
++#endif
+ ucon |= S3C2440_UCON_FCLK;
+ else {
+ printk(KERN_ERR "unknown clock source %s\n", clk->name);
+@@ -1436,8 +1446,11 @@ static int s3c2440_serial_getsource(struct uart_port *port,
+ /* manual calims 44, seems to be 9 */
+ clk->divisor = 9;
+ }
+-
++#if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ clk->name = "esysclk";
++#else
+ clk->name = "fclk";
++#endif
+ break;
+ }
+
+diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c
+new file mode 100644
+index 0000000..89e15c7
+--- /dev/null
++++ b/drivers/serial/s3c6400.c
+@@ -0,0 +1,1676 @@
++/*
++ * based on linux/drivers/serial/s3c6400.c
++ * modified by ihlee215. ts=8
++ *
++ * Driver for onboard UARTs on the Samsung S3C
++ *
++ * Based on drivers/char/serial.c and drivers/char/21285.c
++ *
++ * Ben Dooks, (c) 2003 Simtec Electronics
++ *
++ * Changelog:
++ *
++ * 22-Jul-2004 BJD Finished off device rewrite
++ *
++ * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
++ * problems with baud rate and loss of IR settings. Update
++ * to add configuration via platform_device structure
++ *
++ * 28-Sep-2004 BJD Re-write for the following items
++ * - S3C serial support
++ * - Power Management support
++ * - Fix console via IrDA devices
++ * - SysReq (Herbert Ptzl)
++ * - Break character handling (Herbert Ptzl)
++ * - spin-lock initialisation (Dimitry Andric)
++ * - added clock control
++ * - updated init code to use platform_device info
++*/
++
++/* Note on 24XX error handling
++ *
++ * The s3c2410 manual has a love/hate affair with the contents of the
++ * UERSTAT register in the UART blocks, and keeps marking some of the
++ * error bits as reserved. Having checked with the s3c2410x01,
++ * it copes with BREAKs properly, so I am happy to ignore the RESERVED
++ * feature from the latter versions of the manual.
++ *
++ * If it becomes aparrent that latter versions of the 2410 remove these
++ * bits, then action will have to be taken to differentiate the versions
++ * and change the policy on BREAK
++ *
++ * BJD, 04-Nov-2004
++*/
++
++#if defined(CONFIG_SERIAL_S3C64XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
++
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <linux/platform_device.h>
++#include <linux/init.h>
++#include <linux/sysrq.h>
++#include <linux/console.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/serial_core.h>
++#include <linux/serial.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <asm/hardware.h>
++
++#include <asm/arch/gpio.h>
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++/* structures */
++
++struct s3c_uart_info {
++ char *name;
++ unsigned int type;
++ unsigned int fifosize;
++ unsigned long rx_fifomask;
++ unsigned long rx_fifoshift;
++ unsigned long rx_fifofull;
++ unsigned long tx_fifomask;
++ unsigned long tx_fifoshift;
++ unsigned long tx_fifofull;
++
++ /* clock source control */
++
++ int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
++ int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
++
++ /* uart controls */
++ int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
++};
++
++struct s3c_uart_port {
++ unsigned char rx_claimed;
++ unsigned char tx_claimed;
++
++ struct s3c_uart_info *info;
++ struct s3c24xx_uart_clksrc *clksrc;
++ struct clk *clk;
++ struct clk *baudclk;
++ struct uart_port port;
++};
++
++
++/* configuration defines */
++
++#if 0
++#if 1
++/* send debug to the low-level output routines */
++
++extern void printascii(const char *);
++
++static void
++s3c_serial_dbg(const char *fmt, ...)
++{
++ va_list va;
++ char buff[256];
++
++ va_start(va, fmt);
++ vsprintf(buff, fmt, va);
++ va_end(va);
++
++ printascii(buff);
++}
++
++#define dbg(x...) s3c_serial_dbg(x)
++
++#else
++#define dbg(x...) printk(KERN_DEBUG "s3c: ");
++#endif
++#else /* no debug */
++#define dbg(x...) do {} while(0)
++#endif
++
++/* UART name and device definitions */
++#define S3C_SERIAL_NAME "ttySAC"
++//#define S3C_SERIAL_MAJOR TTY_MAJOR
++#define S3C_SERIAL_MAJOR 204
++#define S3C_SERIAL_MINOR 64
++
++/* conversion functions */
++#define s3c_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
++#define s3c_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
++
++/* port irq numbers */
++#define TX_IRQ(port) ((port)->irq + 1)
++#define RX_IRQ(port) ((port)->irq)
++#define UART_IRQ(port) ((port)->irq)
++
++/* register access controls */
++#define portaddr(port, reg) ((port)->membase + (reg))
++
++#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
++#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
++
++#define wr_regb(port, reg, val) \
++ do { __raw_writeb(val, portaddr(port, reg)); } while(0)
++
++#define wr_regl(port, reg, val) \
++ do { __raw_writel(val, portaddr(port, reg)); } while(0)
++
++/* macros to change one thing to another */
++#define tx_enabled(port) ((port)->unused[0])
++#define rx_enabled(port) ((port)->unused[1])
++
++const unsigned int nSlotTable[16] = {0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4a52, 0x54aa,
++ 0x5555, 0xd555, 0xd5d5, 0xddd5, 0xdddd, 0xdfdd, 0xdfdf, 0xffdf};
++
++#ifdef UART_HAS_INTMSK
++static inline void uart_enable_irq (struct uart_port *port, uint val)
++{
++ uint mask;
++
++ mask = rd_regl(port, S3C_UINTMSK);
++ mask &= ~val;
++ wr_regl(port, S3C_UINTMSK, mask);
++}
++
++static inline void uart_disable_irq (struct uart_port *port, uint val)
++{
++ uint mask;
++
++ mask = rd_regl(port, S3C_UINTMSK);
++ mask |= val;
++ wr_regl(port, S3C_UINTMSK, mask);
++
++}
++#endif
++
++/* flag to ignore all characters comming in */
++#define RXSTAT_DUMMY_READ (0x10000000)
++
++/* now comes the code to initialise either the s3c serial
++ * port information
++ */
++static int s3c_serial_getsource_hw(struct uart_port *port,
++ struct s3c24xx_uart_clksrc *clk)
++{
++ unsigned long ucon = rd_regl(port, S3C_UCON);
++
++ switch (ucon & S3C_UCON_CLKMASK) {
++ case S3C_UCON_UCLK:
++ clk->divisor = 1;
++ clk->name = "uclk";
++ break;
++
++ case S3C_UCON_PCLK:
++ case S3C_UCON_PCLK2:
++ clk->divisor = 1;
++ clk->name = "pclk";
++ break;
++
++ case S3C_UCON_FCLK:
++
++#if defined (CONFIG_SERIAL_S3C64XX_HS_UART)
++
++ clk->divisor = 2; /* For 4000000bps, epll_clk_192Mhz is needed. */
++ clk->name = "epll_clk_uart_192m";
++
++#else
++
++ clk->divisor = 2;
++ clk->name = "mpll_clk_uart";
++
++#endif
++ break;
++ }
++
++ return 0;
++}
++
++
++static int s3c_serial_setsource_hw(struct uart_port *port,
++ struct s3c24xx_uart_clksrc *clk)
++{
++ unsigned long ucon = rd_regl(port, S3C_UCON);
++
++ ucon &= ~S3C_UCON_CLKMASK;
++
++ if (strcmp(clk->name, "uclk") == 0)
++ ucon |= S3C_UCON_UCLK;
++ else if (strcmp(clk->name, "pclk") == 0)
++ ucon |= S3C_UCON_PCLK;
++ else if (strcmp(clk->name, "epll_clk_uart_192m") == 0)
++ ucon |= S3C_UCON_FCLK;
++ else if (strcmp(clk->name, "mpll_clk_uart") == 0)
++ ucon |= S3C_UCON_FCLK;
++ else {
++ printk(KERN_ERR "unknown clock source %s\n", clk->name);
++ return -EINVAL;
++ }
++
++ wr_regl(port, S3C_UCON, ucon);
++ return 0;
++}
++
++static inline struct s3c_uart_port *to_ourport(struct uart_port *port)
++{
++ return container_of(port, struct s3c_uart_port, port);
++}
++
++/* translate a port to the device name */
++
++static inline const char *s3c_serial_portname(struct uart_port *port)
++{
++ return to_platform_device(port->dev)->name;
++}
++
++static int s3c_serial_txempty_nofifo(struct uart_port *port)
++{
++ return (rd_regl(port, S3C_UTRSTAT) & S3C_UTRSTAT_TXE);
++}
++
++static void s3c_serial_rx_enable(struct uart_port *port)
++{
++ unsigned long flags;
++ unsigned int ucon, ufcon;
++ int count = 10000;
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ while (--count && !s3c_serial_txempty_nofifo(port))
++ udelay(100);
++
++ ufcon = rd_regl(port, S3C_UFCON);
++ ufcon |= S3C_UFCON_RESETRX;
++ wr_regl(port, S3C_UFCON, ufcon);
++
++ ucon = rd_regl(port, S3C_UCON);
++ ucon |= S3C_UCON_RXIRQMODE;
++ wr_regl(port, S3C_UCON, ucon);
++
++ rx_enabled(port) = 1;
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void s3c_serial_rx_disable(struct uart_port *port)
++{
++ unsigned long flags;
++ unsigned int ucon;
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ ucon = rd_regl(port, S3C_UCON);
++ ucon &= ~S3C_UCON_RXIRQMODE;
++ wr_regl(port, S3C_UCON, ucon);
++
++ rx_enabled(port) = 0;
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void s3c_serial_stop_tx(struct uart_port *port)
++{
++ if (tx_enabled(port)) {
++#ifdef UART_HAS_INTMSK
++ uart_disable_irq(port, UART_TX_INT);
++#else
++ disable_irq(TX_IRQ(port));
++#endif
++ tx_enabled(port) = 0;
++ if (port->flags & UPF_CONS_FLOW)
++ s3c_serial_rx_enable(port);
++ }
++}
++
++static void s3c_serial_start_tx(struct uart_port *port)
++{
++ if (!tx_enabled(port)) {
++ if (port->flags & UPF_CONS_FLOW)
++ s3c_serial_rx_disable(port);
++
++#ifdef UART_HAS_INTMSK
++ uart_enable_irq(port, UART_TX_INT);
++#else
++ enable_irq(TX_IRQ(port));
++#endif
++ tx_enabled(port) = 1;
++ }
++}
++
++
++static void s3c_serial_stop_rx(struct uart_port *port)
++{
++ if (rx_enabled(port)) {
++#ifdef UART_HAS_INTMSK
++ uart_disable_irq(port, UART_RX_INT);
++#else
++ disable_irq(RX_IRQ(port));
++#endif
++ rx_enabled(port) = 0;
++ }
++}
++
++static void s3c_serial_enable_ms(struct uart_port *port)
++{
++}
++
++static inline struct s3c_uart_info *s3c_port_to_info(struct uart_port *port)
++{
++ return to_ourport(port)->info;
++}
++
++static inline struct s3c2410_uartcfg *s3c_port_to_cfg(struct uart_port *port)
++{
++ if (port->dev == NULL)
++ return NULL;
++
++ return (struct s3c2410_uartcfg *)port->dev->platform_data;
++}
++
++static int s3c_serial_rx_fifocnt(struct s3c_uart_port *ourport,
++ unsigned long ufstat)
++{
++ struct s3c_uart_info *info = ourport->info;
++
++ if (ufstat & info->rx_fifofull)
++ return info->fifosize;
++
++ return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
++}
++
++
++/* ? - where has parity gone?? */
++#define S3C_UERSTAT_PARITY (0x1000)
++
++static irqreturn_t
++s3c_serial_rx_chars(int irq, void *dev_id)
++{
++ struct s3c_uart_port *ourport = dev_id;
++ struct uart_port *port = &ourport->port;
++ struct tty_struct *tty = port->info->tty;
++ unsigned int ufcon, ch, flag, ufstat, uerstat;
++ int max_count = 64;
++
++ while (max_count-- > 0) {
++ ufcon = rd_regl(port, S3C_UFCON);
++ ufstat = rd_regl(port, S3C_UFSTAT);
++
++ if (s3c_serial_rx_fifocnt(ourport, ufstat) == 0)
++ break;
++
++ uerstat = rd_regl(port, S3C_UERSTAT);
++ ch = rd_regb(port, S3C_URXH);
++
++ if (port->flags & UPF_CONS_FLOW) {
++ int txe = s3c_serial_txempty_nofifo(port);
++
++ if (rx_enabled(port)) {
++ if (!txe) {
++ rx_enabled(port) = 0;
++ continue;
++ }
++ } else {
++ if (txe) {
++ ufcon |= S3C_UFCON_RESETRX;
++ wr_regl(port, S3C_UFCON, ufcon);
++ rx_enabled(port) = 1;
++ goto out;
++ }
++ continue;
++ }
++ }
++
++ /* insert the character into the buffer */
++
++ flag = TTY_NORMAL;
++ port->icount.rx++;
++
++ if (uerstat & S3C_UERSTAT_ANY) {
++ dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", ch, uerstat);
++
++ /* check for break */
++ if (uerstat & S3C_UERSTAT_BREAK) {
++ dbg("break!\n");
++ port->icount.brk++;
++ flag = TTY_BREAK;
++ if (uart_handle_break(port))
++ goto recv_char;
++ }
++
++ if (uerstat & S3C_UERSTAT_FRAME)
++ port->icount.frame++;
++ if (uerstat & S3C_UERSTAT_OVERRUN)
++ port->icount.overrun++;
++
++ uerstat &= port->read_status_mask;
++
++ if (uerstat & S3C_UERSTAT_BREAK)
++ flag = TTY_BREAK;
++ else if (uerstat & S3C_UERSTAT_PARITY)
++ flag = TTY_PARITY;
++ else if (uerstat & ( S3C_UERSTAT_FRAME | S3C_UERSTAT_OVERRUN))
++ flag = TTY_FRAME;
++
++ uart_insert_char(port, uerstat, S3C_UERSTAT_OVERRUN, ch, flag);
++ }
++
++ uart_handle_sysrq_char(port, ch);
++ recv_char:
++ uart_insert_char(port, uerstat, S3C_UERSTAT_OVERRUN, ch, flag);
++
++ ignore_char:
++ continue;
++ }
++ tty_flip_buffer_push(tty);
++
++ out:
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t s3c_serial_tx_chars(int irq, void *id)
++{
++ struct s3c_uart_port *ourport = id;
++ struct uart_port *port = &ourport->port;
++ struct circ_buf *xmit = &port->info->xmit;
++ int count = 256;
++
++ if (port->x_char) {
++ wr_regb(port, S3C_UTXH, port->x_char);
++ port->icount.tx++;
++ port->x_char = 0;
++ goto out;
++ }
++
++ /* if there isnt anything more to transmit, or the uart is now
++ * stopped, disable the uart and exit
++ */
++
++ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
++ s3c_serial_stop_tx(port);
++ goto out;
++ }
++
++ /* try and drain the buffer... */
++
++ while (!uart_circ_empty(xmit) && count-- > 0) {
++ if (rd_regl(port, S3C_UFSTAT) & ourport->info->tx_fifofull)
++ break;
++
++ wr_regb(port, S3C_UTXH, xmit->buf[xmit->tail]);
++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++ port->icount.tx++;
++ }
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(port);
++
++ if (uart_circ_empty(xmit))
++ s3c_serial_stop_tx(port);
++
++ out:
++ return IRQ_HANDLED;
++}
++
++static unsigned int s3c_serial_tx_empty(struct uart_port *port)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++ unsigned long ufstat = rd_regl(port, S3C_UFSTAT);
++ unsigned long ufcon = rd_regl(port, S3C_UFCON);
++
++ if (ufcon & S3C_UFCON_FIFOMODE) {
++ if ((ufstat & info->tx_fifomask) != 0 ||
++ (ufstat & info->tx_fifofull))
++ return 0;
++
++ return 1;
++ }
++
++ return s3c_serial_txempty_nofifo(port);
++}
++
++/* no modem control lines */
++static unsigned int s3c_serial_get_mctrl(struct uart_port *port)
++{
++ unsigned int umstat = rd_regb(port,S3C_UMSTAT);
++
++ if (umstat & S3C_UMSTAT_CTS)
++ return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
++ else
++ return TIOCM_CAR | TIOCM_DSR;
++}
++
++static void s3c_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++ /* todo - possibly remove AFC and do manual CTS */
++}
++
++static void s3c_serial_break_ctl(struct uart_port *port, int break_state)
++{
++ unsigned long flags;
++ unsigned int ucon;
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ ucon = rd_regl(port, S3C_UCON);
++
++ if (break_state)
++ ucon |= S3C_UCON_SBREAK;
++ else
++ ucon &= ~S3C_UCON_SBREAK;
++
++ wr_regl(port, S3C_UCON, ucon);
++
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void s3c_serial_shutdown(struct uart_port *port)
++{
++ struct s3c_uart_port *ourport = to_ourport(port);
++
++#ifdef UART_HAS_INTMSK
++ if (ourport->tx_claimed || ourport->rx_claimed) {
++ free_irq(UART_IRQ(port), ourport);
++
++ ourport->tx_claimed = 0;
++ ourport->rx_claimed = 0;
++ tx_enabled(port) = 0;
++ rx_enabled(port) = 0;
++ }
++#else
++ if (ourport->tx_claimed) {
++ free_irq(TX_IRQ(port), ourport);
++ tx_enabled(port) = 0;
++ ourport->tx_claimed = 0;
++ }
++
++ if (ourport->rx_claimed) {
++ free_irq(RX_IRQ(port), ourport);
++ ourport->rx_claimed = 0;
++ rx_enabled(port) = 0;
++ }
++#endif
++}
++
++#ifdef UART_HAS_INTMSK
++static irqreturn_t
++s3c_serial_interrupt(int irq, void *dev_id)
++{
++ struct s3c_uart_port *ourport = dev_id;
++ struct uart_port *port = &ourport->port;
++ uint intpnd;
++
++ intpnd = rd_regl(port, S3C_UINTPND);
++
++ if (intpnd & UART_RX_INT) {
++ wr_regl(port, S3C_UINTPND, UART_RX_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++
++ return s3c_serial_rx_chars( irq, dev_id);
++ }
++ else if (intpnd & UART_TX_INT) {
++ wr_regl(port, S3C_UINTPND, UART_TX_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++ return s3c_serial_tx_chars(irq, dev_id);
++ }
++ else if (intpnd & UART_ERR_INT) {
++ printk("UART err int.\n");
++ wr_regl(port, S3C_UINTPND, UART_ERR_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++ return IRQ_HANDLED;
++ }
++ else if (intpnd & UART_MODEM_INT) {
++ printk("In Modem ... other case\n");
++ wr_regl(port, S3C_UINTPND, UART_MODEM_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++ return IRQ_HANDLED;
++ }
++ // work around h/w problem : interrupt status bit update delay
++ //return IRQ_NONE;
++ return IRQ_HANDLED;
++
++}
++#endif
++
++static int s3c_serial_startup(struct uart_port *port)
++{
++ struct s3c_uart_port *ourport = to_ourport(port);
++ unsigned long flags;
++ int ret;
++
++ dbg("s3c_serial_startup: port=%p (%08lx,%p)\n",
++ port->mapbase, port->membase);
++
++ local_irq_save(flags);
++
++ rx_enabled(port) = 1;
++ tx_enabled(port) = 1;
++
++#ifdef UART_HAS_INTMSK
++ uart_enable_irq(port, UART_TX_INT | UART_RX_INT);
++ ret = request_irq(UART_IRQ(port), s3c_serial_interrupt, 0,
++ s3c_serial_portname(port), ourport);
++ if (ret != 0) {
++ printk(KERN_ERR "cannot get irq %d\n", UART_IRQ(port));
++ return ret;
++ }
++#else
++ ret = request_irq(RX_IRQ(port),
++ s3c_serial_rx_chars, 0,
++ s3c_serial_portname(port), ourport);
++ if (ret != 0) {
++ printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
++ return ret;
++ }
++
++ ret = request_irq(TX_IRQ(port),
++ s3c_serial_tx_chars, 0,
++ s3c_serial_portname(port), ourport);
++ if (ret) {
++ printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
++ s3c_serial_shutdown(port);
++ local_irq_restore(flags);
++ return ret;
++ }
++#endif
++
++ ourport->rx_claimed = 1;
++ ourport->tx_claimed = 1;
++
++ dbg("s3c_serial_startup ok\n");
++
++ /* the port reset code should have done the correct
++ * register setup for the port controls */
++ local_irq_restore(flags);
++ return ret;
++}
++
++/* power power management control */
++static void s3c_serial_pm(struct uart_port *port, unsigned int level,
++ unsigned int old)
++{
++ struct s3c_uart_port *ourport = to_ourport(port);
++
++ switch (level) {
++ case 3:
++ if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
++ clk_disable(ourport->baudclk);
++
++ clk_disable(ourport->clk);
++ break;
++
++ case 0:
++ clk_enable(ourport->clk);
++
++ if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
++ clk_enable(ourport->baudclk);
++
++ break;
++ default:
++ printk(KERN_ERR "s3c_serial: unknown pm %d\n", level);
++ }
++}
++
++/* baud rate calculation
++ *
++ * The UARTs on the S3C can take their clocks from a number
++ * of different sources, including the peripheral clock ("pclk") and an
++ * external clock ("uclk"). The S3C2413 also adds the core clock ("fclk")
++ * with a programmable extra divisor.
++ *
++ * The following code goes through the clock sources, and calculates the
++ * baud clocks (and the resultant actual baud rates) and then tries to
++ * pick the closest one and select that.
++ *
++ * NOTES:
++ * 1) there is no current code to properly select/deselect FCLK on
++ * the s3c2413, so only specify FCLK or non-FCLK in the clock
++ * sources for the UART
++ *
++*/
++
++
++#define MAX_CLKS (8)
++
++static struct s3c24xx_uart_clksrc tmp_clksrc = {
++ .name = "pclk",
++ .min_baud = 0,
++ .max_baud = 0,
++ .divisor = 1,
++};
++
++static inline int
++s3c_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ return (info->get_clksrc)(port, c);
++}
++
++static inline int
++s3c_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ return (info->set_clksrc)(port, c);
++}
++
++
++struct baud_calc {
++ struct s3c24xx_uart_clksrc *clksrc;
++ unsigned int calc;
++ unsigned int quot;
++ unsigned int slot;
++ struct clk *src;
++};
++
++static int s3c_serial_calcbaud(struct baud_calc *calc,
++ struct uart_port *port,
++ struct s3c24xx_uart_clksrc *clksrc,
++ unsigned int baud)
++{
++ unsigned long rate,nslot;
++ unsigned long tempdiv;
++ unsigned int serial_result_1,serial_result_2;
++
++ calc->src = clk_get(port->dev, clksrc->name);
++ if (calc->src == NULL || IS_ERR(calc->src))
++ return 0;
++
++ baud/=100;
++
++ rate = clk_get_rate(calc->src);
++ rate /= clksrc->divisor;
++
++ calc->clksrc = clksrc;
++
++ tempdiv = (rate*10/(baud*16))-1000;
++ serial_result_1 = ((tempdiv%1000)*16)/1000;
++ serial_result_2 = (((tempdiv%1000)*16) - (serial_result_1*1000));
++
++ if (serial_result_2 >=500)
++ nslot = serial_result_1+1;
++ else
++ nslot = serial_result_1;
++
++ calc->quot = tempdiv/1000;
++ calc->calc = (rate / (calc->quot * 16));
++ calc->slot = nSlotTable[nslot];
++ printk(KERN_DEBUG "FOUND quot %d, calc %d, slot 0x%x, nslot %ld\n",
++ calc->quot, calc->calc ,
++ calc->slot, nslot);
++ return 1;
++}
++
++static unsigned int s3c_serial_getclk(struct uart_port *port,
++ struct s3c24xx_uart_clksrc **clksrc,
++ struct clk **clk,
++ unsigned int baud, unsigned int *slot)
++{
++ struct s3c2410_uartcfg *cfg = s3c_port_to_cfg(port);
++ struct s3c24xx_uart_clksrc *clkp;
++ struct baud_calc res[MAX_CLKS];
++ struct baud_calc *resptr, *best, *sptr;
++ int i;
++
++ clkp = cfg->clocks;
++ best = NULL;
++
++ if (cfg->clocks_size < 2) {
++ if (cfg->clocks_size == 0)
++ clkp = &tmp_clksrc;
++
++ /* check to see if we're sourcing fclk, and if so we're
++ * going to have to update the clock source
++ */
++
++ if (strcmp(clkp->name, "fclk") == 0) {
++ struct s3c24xx_uart_clksrc src;
++
++ s3c_serial_getsource(port, &src);
++
++ /* check that the port already using fclk, and if
++ * not, then re-select fclk
++ */
++
++ if (strcmp(src.name, clkp->name) == 0) {
++ s3c_serial_setsource(port, clkp);
++ s3c_serial_getsource(port, &src);
++ }
++
++ clkp->divisor = src.divisor;
++ }
++
++ s3c_serial_calcbaud(res, port, clkp, baud);
++ best = res;
++ resptr = best + 1;
++ } else {
++ resptr = res;
++
++ for (i = 0; i < cfg->clocks_size; i++, clkp++) {
++ if (s3c_serial_calcbaud(resptr, port, clkp, baud))
++ resptr++;
++ }
++ }
++
++ /* ok, we now need to select the best clock we found */
++
++ if (best==NULL) {
++ unsigned int deviation = (1<<30)|((1<<30)-1);
++ int calc_deviation;
++
++ best = sptr = res;
++
++ for (sptr = res; sptr < resptr; sptr++) {
++ printk(KERN_DEBUG
++ "found clk %p (%s) quot %d, calc %d\n",
++ sptr->clksrc, sptr->clksrc->name,
++ sptr->quot, sptr->calc);
++
++ calc_deviation = baud - sptr->calc;
++
++ if (calc_deviation < 0)
++ calc_deviation = -calc_deviation;
++
++ if (calc_deviation < deviation) {
++ best = sptr;
++ deviation = calc_deviation;
++ }
++ }
++
++ printk(KERN_DEBUG "The best clksrc among candidate clksrc: %p(%s) (deviation: %d bps)\n", best, best->clksrc->name, deviation);
++ }
++
++ printk(KERN_DEBUG "Selected clock is %p (%s) quot %d, calc %d\n",
++ best->clksrc, best->clksrc->name, best->quot, best->calc);
++
++ /* store results to pass back */
++ *clksrc = best->clksrc;
++ *clk = best->src;
++ *slot = best->slot;
++
++ return best->quot;
++}
++
++static void s3c_serial_set_termios(struct uart_port *port,
++ struct ktermios *termios,
++ struct ktermios *old)
++{
++ struct s3c2410_uartcfg *cfg = s3c_port_to_cfg(port);
++ struct s3c_uart_port *ourport = to_ourport(port);
++ struct s3c24xx_uart_clksrc *clksrc = NULL;
++ struct clk *clk = NULL;
++ unsigned long flags;
++ unsigned int baud, quot, slot = 0;
++ unsigned int ulcon;
++ unsigned int umcon;
++
++ /*
++ * We don't support modem control lines.
++ */
++ termios->c_cflag &= ~(HUPCL | CMSPAR);
++ termios->c_cflag |= CLOCAL;
++
++ /*
++ * Ask the core to calculate the divisor for us.
++ */
++
++ baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
++
++ if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
++ quot = port->custom_divisor;
++ else
++ quot = s3c_serial_getclk(port, &clksrc, &clk, baud, &slot);
++
++ /* check to see if we need to change clock source */
++
++ if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
++ s3c_serial_setsource(port, clksrc);
++
++ if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
++ clk_disable(ourport->baudclk);
++ ourport->baudclk = NULL;
++ }
++
++ clk_enable(clk);
++
++ ourport->clksrc = clksrc;
++ ourport->baudclk = clk;
++ }
++
++ switch (termios->c_cflag & CSIZE) {
++ case CS5:
++ dbg("config: 5bits/char\n");
++ ulcon = S3C_LCON_CS5;
++ break;
++ case CS6:
++ dbg("config: 6bits/char\n");
++ ulcon = S3C_LCON_CS6;
++ break;
++ case CS7:
++ dbg("config: 7bits/char\n");
++ ulcon = S3C_LCON_CS7;
++ break;
++ case CS8:
++ default:
++ dbg("config: 8bits/char\n");
++ ulcon = S3C_LCON_CS8;
++ break;
++ }
++
++ /* preserve original lcon IR settings */
++ ulcon |= (cfg->ulcon & S3C_LCON_IRM);
++
++ if (termios->c_cflag & CSTOPB)
++ ulcon |= S3C_LCON_STOPB;
++
++ umcon = (termios->c_cflag & CRTSCTS) ? S3C_UMCOM_AFC : 0;
++
++ if (termios->c_cflag & PARENB) {
++ if (termios->c_cflag & PARODD)
++ ulcon |= S3C_LCON_PODD;
++ else
++ ulcon |= S3C_LCON_PEVEN;
++ } else {
++ ulcon |= S3C_LCON_PNONE;
++ }
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
++
++ wr_regl(port, S3C_ULCON, ulcon);
++ wr_regl(port, S3C_UBRDIV, quot);
++ wr_regl(port, S3C_UDIVSLOT, slot);
++ wr_regl(port, S3C_UMCON, umcon);
++
++ dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
++ rd_regl(port, S3C_ULCON),
++ rd_regl(port, S3C_UCON),
++ rd_regl(port, S3C_UFCON));
++
++ /*
++ * Update the per-port timeout.
++ */
++ uart_update_timeout(port, termios->c_cflag, baud);
++
++ /*
++ * Which character status flags are we interested in?
++ */
++ port->read_status_mask = S3C_UERSTAT_OVERRUN;
++ if (termios->c_iflag & INPCK)
++ port->read_status_mask |= S3C_UERSTAT_FRAME | S3C_UERSTAT_PARITY;
++
++ /*
++ * Which character status flags should we ignore?
++ */
++ port->ignore_status_mask = 0;
++ if (termios->c_iflag & IGNPAR)
++ port->ignore_status_mask |= S3C_UERSTAT_OVERRUN;
++ if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
++ port->ignore_status_mask |= S3C_UERSTAT_FRAME;
++
++ /*
++ * Ignore all characters if CREAD is not set.
++ */
++ if ((termios->c_cflag & CREAD) == 0)
++ port->ignore_status_mask |= RXSTAT_DUMMY_READ;
++
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static const char *s3c_serial_type(struct uart_port *port)
++{
++ switch (port->type) {
++ case PORT_S3C2410:
++ return "S3C";
++ default:
++ return NULL;
++ }
++}
++
++#define MAP_SIZE (0x100)
++
++static void s3c_serial_release_port(struct uart_port *port)
++{
++ release_mem_region(port->mapbase, MAP_SIZE);
++}
++
++static int s3c_serial_request_port(struct uart_port *port)
++{
++ const char *name = s3c_serial_portname(port);
++ return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
++}
++
++static void s3c_serial_config_port(struct uart_port *port, int flags)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ if (flags & UART_CONFIG_TYPE && s3c_serial_request_port(port) == 0)
++ port->type = info->type;
++}
++
++/*
++ * verify the new serial_struct (for TIOCSSERIAL).
++ */
++static int
++s3c_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ if (ser->type != PORT_UNKNOWN && ser->type != info->type)
++ return -EINVAL;
++
++ return 0;
++}
++
++
++#ifdef CONFIG_SERIAL_S3C64XX_CONSOLE
++
++static struct console s3c_serial_console;
++
++#define S3C64XX_SERIAL_CONSOLE &s3c_serial_console
++#else
++#define S3C64XX_SERIAL_CONSOLE NULL
++#endif
++
++static struct uart_ops s3c_serial_ops = {
++ .pm = s3c_serial_pm,
++ .tx_empty = s3c_serial_tx_empty,
++ .get_mctrl = s3c_serial_get_mctrl,
++ .set_mctrl = s3c_serial_set_mctrl,
++ .stop_tx = s3c_serial_stop_tx,
++ .start_tx = s3c_serial_start_tx,
++ .stop_rx = s3c_serial_stop_rx,
++ .enable_ms = s3c_serial_enable_ms,
++ .break_ctl = s3c_serial_break_ctl,
++ .startup = s3c_serial_startup,
++ .shutdown = s3c_serial_shutdown,
++ .set_termios = s3c_serial_set_termios,
++ .type = s3c_serial_type,
++ .release_port = s3c_serial_release_port,
++ .request_port = s3c_serial_request_port,
++ .config_port = s3c_serial_config_port,
++ .verify_port = s3c_serial_verify_port,
++};
++
++
++static struct uart_driver s3c_uart_drv = {
++ .owner = THIS_MODULE,
++ .dev_name = "s3c_serial",
++ .nr = NR_PORTS,
++ .cons = S3C64XX_SERIAL_CONSOLE,
++ .driver_name = S3C_SERIAL_NAME,
++ .major = S3C_SERIAL_MAJOR,
++ .minor = S3C_SERIAL_MINOR,
++};
++
++static struct s3c_uart_port s3c_serial_ports[NR_PORTS] = {
++ [0] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART0,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 0,
++ }
++ },
++ [1] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART1,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 1,
++ }
++ },
++#if NR_PORTS > 2
++ [2] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART2,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 2,
++ }
++ },
++ [3] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART3,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 3,
++ }
++ }
++#endif
++};
++
++/* s3c_serial_resetport
++ *
++ * wrapper to call the specific reset for this port (reset the fifos
++ * and the settings)
++*/
++
++static int s3c_serial_resetport(struct uart_port *port,
++ struct s3c2410_uartcfg *cfg)
++{
++#if 0
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ return (info->reset_port)(port, cfg);
++#else
++ /* ensure registers are setup */
++ dbg("s3c_serial_resetport: port=%p (%08lx), cfg=%p\n",
++ port, port->mapbase, cfg);
++
++ wr_regl(port, S3C_UCON, cfg->ucon);
++ wr_regl(port, S3C_ULCON, cfg->ulcon);
++
++ /* reset both fifos */
++ wr_regl(port, S3C_UFCON, cfg->ufcon | S3C_UFCON_RESETBOTH);
++ wr_regl(port, S3C_UFCON, cfg->ufcon);
++
++ return 0;
++
++#endif
++}
++
++/* s3c_serial_init_port
++ *
++ * initialise a single serial port from the platform device given
++ */
++
++static int s3c_serial_init_port(struct s3c_uart_port *ourport,
++ struct s3c_uart_info *info,
++ struct platform_device *plat_dev)
++{
++ struct uart_port *port = &ourport->port;
++ struct s3c2410_uartcfg *cfg;
++ struct resource *res;
++
++ dbg("s3c_serial_init_port: port=%p, plat_dev=%p\n", port, plat_dev);
++
++ if (plat_dev == NULL)
++ return -ENODEV;
++
++ cfg = s3c_dev_to_cfg(&plat_dev->dev);
++
++ if (port->mapbase != 0)
++ return 0;
++
++ if (cfg->hwport > NR_PORTS)
++ return -EINVAL;
++
++ /*GPIO setup for each port*/
++ switch(port->line) {
++ case 0:
++ gpio_set_pin(S3C_GPA0, S3C_GPA0_UART_RXD0);
++ gpio_set_pin(S3C_GPA1, S3C_GPA1_UART_TXD0);
++ gpio_set_pin(S3C_GPA2, S3C_GPA2_UART_CTS0);
++ gpio_set_pin(S3C_GPA3, S3C_GPA3_UART_RTS0);
++ break;
++ case 1:
++ gpio_set_pin(S3C_GPA4, S3C_GPA4_UART_RXD1);
++ gpio_set_pin(S3C_GPA5, S3C_GPA5_UART_TXD1);
++ gpio_set_pin(S3C_GPA5, S3C_GPA6_UART_CTS1);
++ gpio_set_pin(S3C_GPA7, S3C_GPA7_UART_RTS1);
++ break;
++ case 2:
++ gpio_set_pin(S3C_GPB0, S3C_GPB0_UART_RXD2);
++ gpio_set_pin(S3C_GPB1, S3C_GPB1_UART_TXD2);
++ break;
++ case 3:
++ gpio_set_pin(S3C_GPB2, S3C_GPB2_UART_RXD3);
++ gpio_set_pin(S3C_GPB3, S3C_GPB3_UART_TXD3);
++ break;
++ default:
++ break;
++ }
++
++ /* setup info for port */
++ port->dev = &plat_dev->dev;
++ ourport->info = info;
++
++ /* copy the info in from provided structure */
++ ourport->port.fifosize = info->fifosize;
++
++ dbg("s3c_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
++
++ port->uartclk = UART_CLK;
++
++ if (cfg->uart_flags & UPF_CONS_FLOW) {
++ dbg("s3c_serial_init_port: enabling flow control\n");
++ port->flags |= UPF_CONS_FLOW;
++ }
++
++ /* sort our the physical and virtual addresses for each UART */
++
++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
++ if (res == NULL) {
++ printk(KERN_ERR "failed to find memory resource for uart\n");
++ return -EINVAL;
++ }
++
++ dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
++
++ port->mapbase = res->start;
++ port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
++ port->irq = platform_get_irq(plat_dev, 0);
++
++ ourport->clk = clk_get(&plat_dev->dev, "UART0");
++
++ dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
++ port->mapbase, port->membase, port->irq, port->uartclk);
++
++ /* reset the fifos (and setup the uart) */
++ s3c_serial_resetport(port, cfg);
++ return 0;
++}
++
++/* Device driver serial port probe */
++static int probe_index = 0;
++
++static int s3c6400_serial_probe(struct platform_device *dev,
++ struct s3c_uart_info *info)
++{
++ struct s3c_uart_port *ourport;
++ int ret;
++
++ dbg("s3c_serial_probe(%p) %d\n", dev, probe_index);
++
++ ourport = &s3c_serial_ports[probe_index];
++ probe_index++;
++
++ dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
++
++ //ret = s3c_serial_init_port(ourport, &s3c_uart_inf, dev);
++ ret = s3c_serial_init_port(ourport, info, dev);
++ if (ret < 0)
++ goto probe_err;
++
++ dbg("%s: adding port\n", __FUNCTION__);
++ uart_add_one_port(&s3c_uart_drv, &ourport->port);
++ platform_set_drvdata(dev, &ourport->port);
++
++ return 0;
++
++ probe_err:
++ return ret;
++}
++
++static int s3c_serial_remove(struct platform_device *dev)
++{
++ struct uart_port *port = s3c_dev_to_port(&dev->dev);
++
++ if (port)
++ uart_remove_one_port(&s3c_uart_drv, port);
++
++ return 0;
++}
++
++/* UART power management code */
++
++#ifdef CONFIG_PM
++
++#include <asm/plat-s3c24xx/pm.h>
++
++#define SAVE_UART(va) \
++ SAVE_ITEM((va) + S3C_ULCON), \
++ SAVE_ITEM((va) + S3C_UCON), \
++ SAVE_ITEM((va) + S3C_UFCON), \
++ SAVE_ITEM((va) + S3C_UMCON), \
++ SAVE_ITEM((va) + S3C_UBRDIV), \
++ SAVE_ITEM((va) + S3C_UDIVSLOT), \
++ SAVE_ITEM((va) + S3C_UINTMSK)
++
++
++static struct sleep_save uart_save[] = {
++ SAVE_UART(S3C24XX_VA_UART0),
++ SAVE_UART(S3C24XX_VA_UART1),
++ SAVE_UART(S3C24XX_VA_UART2),
++ SAVE_UART(S3C24XX_VA_UART3),
++};
++static int s3c_serial_suspend(struct platform_device *dev, pm_message_t state)
++{
++ struct uart_port *port = s3c_dev_to_port(&dev->dev);
++
++ s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
++
++ if (port)
++ uart_suspend_port(&s3c_uart_drv, port);
++
++ return 0;
++}
++
++static int s3c_serial_resume(struct platform_device *dev)
++{
++ struct uart_port *port = s3c_dev_to_port(&dev->dev);
++ struct s3c_uart_port *ourport = to_ourport(port);
++
++ if (port) {
++ clk_enable(ourport->clk);
++ s3c_serial_resetport(port, s3c_port_to_cfg(port));
++ clk_disable(ourport->clk);
++
++ s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
++
++ uart_resume_port(&s3c_uart_drv, port);
++ }
++
++ return 0;
++}
++
++#else
++#define s3c_serial_suspend NULL
++#define s3c_serial_resume NULL
++#endif
++
++static int s3c_serial_init(struct platform_driver *drv,
++ struct s3c_uart_info *info)
++{
++ dbg("s3c64xx_serial_init(%p,%p)\n", drv, info);
++ return platform_driver_register(drv);
++}
++
++static struct s3c_uart_info s3c_uart_inf = {
++ .name = "Samsung S3C UART",
++ .type = PORT_S3C2410,
++ .fifosize = UART_FIFO_SIZE,
++ .rx_fifomask = S3C_UFSTAT_RXMASK,
++ .rx_fifoshift = S3C_UFSTAT_RXSHIFT,
++ .rx_fifofull = S3C_UFSTAT_RXFULL,
++ .tx_fifofull = S3C_UFSTAT_TXFULL,
++ .tx_fifomask = S3C_UFSTAT_TXMASK,
++ .tx_fifoshift = S3C_UFSTAT_TXSHIFT,
++ .get_clksrc = s3c_serial_getsource_hw,
++ .set_clksrc = s3c_serial_setsource_hw,
++// .reset_port = s3c_serial_resetport,
++};
++
++/* device management */
++
++static int s3c_serial_probe(struct platform_device *dev)
++{
++ return s3c6400_serial_probe(dev, &s3c_uart_inf);
++}
++
++static struct platform_driver s3c_serial_drv = {
++ .probe = s3c_serial_probe,
++ .remove = s3c_serial_remove,
++ .suspend = s3c_serial_suspend,
++ .resume = s3c_serial_resume,
++ .driver = {
++ .name = "s3c-uart",
++ .owner = THIS_MODULE,
++ },
++};
++
++static inline int s3c6400_serial_init(void)
++{
++ return s3c_serial_init(&s3c_serial_drv, &s3c_uart_inf);
++}
++
++static inline void s3c6400_serial_exit(void)
++{
++ platform_driver_unregister(&s3c_serial_drv);
++}
++
++
++/* module initialisation code */
++static int __init s3c_serial_modinit(void)
++{
++ int ret;
++
++ ret = uart_register_driver(&s3c_uart_drv);
++ if (ret < 0) {
++ printk(KERN_ERR "failed to register UART driver\n");
++ return -1;
++ }
++
++ s3c6400_serial_init();
++
++ return 0;
++}
++
++static void __exit s3c_serial_modexit(void)
++{
++ s3c6400_serial_exit();
++
++ uart_unregister_driver(&s3c_uart_drv);
++}
++
++module_init(s3c_serial_modinit);
++module_exit(s3c_serial_modexit);
++
++/* ----------------------------------------------------------------------------------*/
++/* Console code for UART */
++/*-----------------------------------------------------------------------------------*/
++
++#ifdef CONFIG_SERIAL_S3C64XX_CONSOLE
++
++static struct uart_port *cons_uart;
++
++static int
++s3c_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++ unsigned long ufstat, utrstat;
++
++ if (ufcon & S3C_UFCON_FIFOMODE) {
++ /* fifo mode - check ammount of data in fifo registers... */
++ ufstat = rd_regl(port, S3C_UFSTAT);
++ return (ufstat & info->tx_fifofull) ? 0 : 1;
++ }
++
++ /* in non-fifo mode, we go and use the tx buffer empty */
++ utrstat = rd_regl(port, S3C_UTRSTAT);
++ return (utrstat & S3C_UTRSTAT_TXE) ? 1 : 0;
++}
++
++static void
++s3c_serial_console_write(struct console *co, const char *s,
++ unsigned int count)
++{
++ int i;
++ unsigned int ufcon = rd_regl(cons_uart, S3C_UFCON);
++
++ for (i = 0; i < count; i++) {
++ while (!s3c_serial_console_txrdy(cons_uart, ufcon))
++ barrier();
++
++ wr_regb(cons_uart, S3C_UTXH, s[i]);
++
++ if (s[i] == '\n') {
++ while (!s3c_serial_console_txrdy(cons_uart, ufcon))
++ barrier();
++
++ wr_regb(cons_uart, S3C_UTXH, '\r');
++ }
++ }
++}
++
++static void __init
++s3c_serial_get_options(struct uart_port *port, int *baud,
++ int *parity, int *bits)
++{
++ struct s3c24xx_uart_clksrc clksrc;
++ struct clk *clk;
++ unsigned int ulcon;
++ unsigned int ucon;
++ unsigned int ubrdiv;
++ unsigned long rate;
++
++ ulcon = rd_regl(port, S3C_ULCON);
++ ucon = rd_regl(port, S3C_UCON);
++ ubrdiv = rd_regl(port, S3C_UBRDIV);
++
++ dbg("s3c_serial_get_options: port=%p\n"
++ "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
++ port, ulcon, ucon, ubrdiv);
++
++ if ((ucon & 0xf) != 0) {
++ /* consider the serial port configured if the tx/rx mode set */
++ switch (ulcon & S3C_LCON_CSMASK) {
++ case S3C_LCON_CS5:
++ *bits = 5;
++ break;
++
++ case S3C_LCON_CS6:
++ *bits = 6;
++ break;
++
++ case S3C_LCON_CS7:
++ *bits = 7;
++ break;
++
++ case S3C_LCON_CS8:
++ default:
++ *bits = 8;
++ break;
++ }
++
++ switch (ulcon & S3C_LCON_PMASK) {
++ case S3C_LCON_PEVEN:
++ *parity = 'e';
++ break;
++
++ case S3C_LCON_PODD:
++ *parity = 'o';
++ break;
++
++ case S3C_LCON_PNONE:
++ default:
++ *parity = 'n';
++ }
++
++ /* now calculate the baud rate */
++ s3c_serial_getsource(port, &clksrc);
++
++ clk = clk_get(port->dev, clksrc.name);
++ if (!IS_ERR(clk) && clk != NULL)
++ rate = clk_get_rate(clk) / clksrc.divisor;
++ else
++ rate = 1;
++
++
++ *baud = rate / ( 16 * (ubrdiv + 1));
++ dbg("calculated baud %d\n", *baud);
++ }
++
++}
++
++/* s3c_serial_init_ports
++ *
++ * initialise the serial ports from the machine provided initialisation
++ * data.
++*/
++
++static int s3c_serial_init_ports(struct s3c_uart_info *info)
++{
++ struct s3c_uart_port *ptr = s3c_serial_ports;
++ struct platform_device **platdev_ptr;
++ int i;
++
++ dbg("s3c_serial_init_ports: initialising ports...\n");
++
++ platdev_ptr = s3c24xx_uart_devs;
++
++ for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
++ s3c_serial_init_port(ptr, info, *platdev_ptr);
++ }
++
++ return 0;
++}
++
++static int __init
++s3c_serial_console_setup(struct console *co, char *options)
++{
++ struct uart_port *port;
++ int baud = 9600;
++ int bits = 8;
++ int parity = 'n';
++ int flow = 'n';
++
++ dbg("s3c_serial_console_setup: co=%p (%d), %s\n",
++ co, co->index, options);
++
++ /* is this a valid port */
++
++ if (co->index == -1 || co->index >= NR_PORTS)
++ co->index = 0;
++
++ port = &s3c_serial_ports[co->index].port;
++
++ /* is the port configured? */
++
++ if (port->mapbase == 0x0) {
++ co->index = 0;
++ port = &s3c_serial_ports[co->index].port;
++ }
++
++ cons_uart = port;
++
++ dbg("s3c_serial_console_setup: port=%p (%d)\n", port, co->index);
++
++ /*
++ * Check whether an invalid uart number has been specified, and
++ * if so, search for the first available port that does have
++ * console support.
++ */
++ if (options)
++ uart_parse_options(options, &baud, &parity, &bits, &flow);
++ else
++ s3c_serial_get_options(port, &baud, &parity, &bits);
++
++ dbg("s3c_serial_console_setup: baud %d\n", baud);
++
++ return uart_set_options(port, co, baud, parity, bits, flow);
++}
++
++/* s3c_serial_initconsole
++ *
++ * initialise the console from one of the uart drivers
++ */
++
++static struct console s3c_serial_console =
++{
++ .name = S3C_SERIAL_NAME,
++ .device = uart_console_device,
++ .flags = CON_PRINTBUFFER,
++ .index = -1,
++ .write = s3c_serial_console_write,
++ .setup = s3c_serial_console_setup
++};
++
++static int s3c_serial_initconsole(void)
++{
++ dbg("s3c_serial_initconsole\n");
++
++ s3c_serial_console.data = &s3c_uart_drv;
++ s3c_serial_init_ports(&s3c_uart_inf);
++
++ register_console(&s3c_serial_console);
++ return 0;
++}
++
++console_initcall(s3c_serial_initconsole);
++
++#endif /* CONFIG_SERIAL_S3C_CONSOLE */
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
++MODULE_DESCRIPTION("Samsung S3C Serial port driver");
+diff --git a/drivers/serial/s5pc100.c b/drivers/serial/s5pc100.c
+new file mode 100644
+index 0000000..9d311a6
+--- /dev/null
++++ b/drivers/serial/s5pc100.c
+@@ -0,0 +1,1643 @@
++/*
++ * based on linux/drivers/serial/s5pc100.c
++ *
++ * Driver for onboard UARTs on the Samsung S3C
++ *
++ * Based on drivers/char/serial.c and drivers/char/21285.c
++ *
++ * Ben Dooks, (c) 2003 Simtec Electronics
++ *
++ * Changelog:
++ *
++ * 22-Jul-2004 BJD Finished off device rewrite
++ *
++ * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
++ * problems with baud rate and loss of IR settings. Update
++ * to add configuration via platform_device structure
++ *
++ * 28-Sep-2004 BJD Re-write for the following items
++ * - S3C serial support
++ * - Power Management support
++ * - Fix console via IrDA devices
++ * - SysReq (Herbert Ptzl)
++ * - Break character handling (Herbert Ptzl)
++ * - spin-lock initialisation (Dimitry Andric)
++ * - added clock control
++ * - updated init code to use platform_device info
++*/
++
++/* Note on 24XX error handling
++ *
++ * The s3c2410 manual has a love/hate affair with the contents of the
++ * UERSTAT register in the UART blocks, and keeps marking some of the
++ * error bits as reserved. Having checked with the s3c2410x01,
++ * it copes with BREAKs properly, so I am happy to ignore the RESERVED
++ * feature from the latter versions of the manual.
++ *
++ * If it becomes aparrent that latter versions of the 2410 remove these
++ * bits, then action will have to be taken to differentiate the versions
++ * and change the policy on BREAK
++ *
++ * BJD, 04-Nov-2004
++*/
++
++#if defined(CONFIG_SERIAL_S5PC1XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
++
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <linux/platform_device.h>
++#include <linux/init.h>
++#include <linux/sysrq.h>
++#include <linux/console.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/serial_core.h>
++#include <linux/serial.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <asm/hardware.h>
++
++#include <asm/plat-s3c/regs-serial.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++/* structures */
++
++struct s3c_uart_info {
++ char *name;
++ unsigned int type;
++ unsigned int fifosize;
++ unsigned long rx_fifomask;
++ unsigned long rx_fifoshift;
++ unsigned long rx_fifofull;
++ unsigned long tx_fifomask;
++ unsigned long tx_fifoshift;
++ unsigned long tx_fifofull;
++
++ /* clock source control */
++
++ int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
++ int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
++
++ /* uart controls */
++ int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
++};
++
++struct s3c_uart_port {
++ unsigned char rx_claimed;
++ unsigned char tx_claimed;
++
++ struct s3c_uart_info *info;
++ struct s3c24xx_uart_clksrc *clksrc;
++ struct clk *clk;
++ struct clk *baudclk;
++ struct uart_port port;
++};
++
++
++/* configuration defines */
++
++#if 1
++#if 0
++/* send debug to the low-level output routines */
++
++extern void printascii(const char *);
++
++static void
++s3c_serial_dbg(const char *fmt, ...)
++{
++ va_list va;
++ char buff[256];
++
++ va_start(va, fmt);
++ vsprintf(buff, fmt, va);
++ va_end(va);
++
++ printascii(buff);
++}
++
++#define dbg(x...) s3c_serial_dbg(x)
++
++#else
++#define dbg(x...) printk(KERN_DEBUG "s3c: ");
++#endif
++#else /* no debug */
++#define dbg(x...) do {} while(0)
++#endif
++
++/* UART name and device definitions */
++#define S3C_SERIAL_NAME "ttySAC"
++//#define S3C_SERIAL_MAJOR TTY_MAJOR
++#define S3C_SERIAL_MAJOR 204
++#define S3C_SERIAL_MINOR 64
++
++/* conversion functions */
++#define s3c_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
++#define s3c_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
++
++/* port irq numbers */
++#define TX_IRQ(port) ((port)->irq + 1)
++#define RX_IRQ(port) ((port)->irq)
++#define UART_IRQ(port) ((port)->irq)
++
++/* register access controls */
++#define portaddr(port, reg) ((port)->membase + (reg))
++
++#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
++#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
++
++#define wr_regb(port, reg, val) \
++ do { __raw_writeb(val, portaddr(port, reg)); } while(0)
++
++#define wr_regl(port, reg, val) \
++ do { __raw_writel(val, portaddr(port, reg)); } while(0)
++
++/* macros to change one thing to another */
++#define tx_enabled(port) ((port)->unused[0])
++#define rx_enabled(port) ((port)->unused[1])
++
++const unsigned int nSlotTable[16] = {0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4a52, 0x54aa,
++ 0x5555, 0xd555, 0xd5d5, 0xddd5, 0xdddd, 0xdfdd, 0xdfdf, 0xffdf};
++
++#ifdef UART_HAS_INTMSK
++static inline void uart_enable_irq (struct uart_port *port, uint val)
++{
++ uint mask;
++
++ mask = rd_regl(port, S3C_UINTMSK);
++ mask &= ~val;
++ wr_regl(port, S3C_UINTMSK, mask);
++}
++
++static inline void uart_disable_irq (struct uart_port *port, uint val)
++{
++ uint mask;
++
++ mask = rd_regl(port, S3C_UINTMSK);
++ mask |= val;
++ wr_regl(port, S3C_UINTMSK, mask);
++
++}
++#endif
++
++/* flag to ignore all characters comming in */
++#define RXSTAT_DUMMY_READ (0x10000000)
++
++/* now comes the code to initialise either the s3c serial
++ * port information
++ */
++static int s3c_serial_getsource_hw(struct uart_port *port,
++ struct s3c24xx_uart_clksrc *clk)
++{
++ unsigned long ucon = rd_regl(port, S3C_UCON);
++
++ switch (ucon & S3C_UCON_CLKMASK) {
++ case S3C_UCON_UCLK:
++ clk->divisor = 1;
++ clk->name = "uclk";
++ break;
++
++ case S3C_UCON_PCLK:
++ case S3C_UCON_PCLK2:
++ clk->divisor = 1;
++ clk->name = "pclkd1";
++ break;
++
++ case S3C_UCON_FCLK:
++
++#if defined (CONFIG_SERIAL_S3C64XX_HS_UART)
++
++ clk->divisor = 2; /* For 4000000bps, epll_clk_192Mhz is needed. */
++ clk->name = "epll_clk_uart_192m";
++
++#else
++
++ clk->divisor = 2;
++ clk->name = "mpll_clk_uart";
++
++#endif
++ break;
++ }
++
++ return 0;
++}
++
++
++static int s3c_serial_setsource_hw(struct uart_port *port,
++ struct s3c24xx_uart_clksrc *clk)
++{
++ unsigned long ucon = rd_regl(port, S3C_UCON);
++
++ ucon &= ~S3C_UCON_CLKMASK;
++
++ if (strcmp(clk->name, "uclk") == 0)
++ ucon |= S3C_UCON_UCLK;
++ else if (strcmp(clk->name, "pclkd1") == 0)
++ ucon |= S3C_UCON_PCLK;
++ else if (strcmp(clk->name, "epll_clk_uart_192m") == 0)
++ ucon |= S3C_UCON_FCLK;
++ else if (strcmp(clk->name, "mpll_clk_uart") == 0)
++ ucon |= S3C_UCON_FCLK;
++ else {
++ printk(KERN_ERR "unknown clock source %s\n", clk->name);
++ return -EINVAL;
++ }
++
++ wr_regl(port, S3C_UCON, ucon);
++ return 0;
++}
++
++static inline struct s3c_uart_port *to_ourport(struct uart_port *port)
++{
++ return container_of(port, struct s3c_uart_port, port);
++}
++
++/* translate a port to the device name */
++
++static inline const char *s3c_serial_portname(struct uart_port *port)
++{
++ return to_platform_device(port->dev)->name;
++}
++
++static int s3c_serial_txempty_nofifo(struct uart_port *port)
++{
++ return (rd_regl(port, S3C_UTRSTAT) & S3C_UTRSTAT_TXE);
++}
++
++static void s3c_serial_rx_enable(struct uart_port *port)
++{
++ unsigned long flags;
++ unsigned int ucon, ufcon;
++ int count = 10000;
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ while (--count && !s3c_serial_txempty_nofifo(port))
++ udelay(100);
++
++ ufcon = rd_regl(port, S3C_UFCON);
++ ufcon |= S3C_UFCON_RESETRX;
++ wr_regl(port, S3C_UFCON, ufcon);
++
++ ucon = rd_regl(port, S3C_UCON);
++ ucon |= S3C_UCON_RXIRQMODE;
++ wr_regl(port, S3C_UCON, ucon);
++
++ rx_enabled(port) = 1;
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void s3c_serial_rx_disable(struct uart_port *port)
++{
++ unsigned long flags;
++ unsigned int ucon;
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ ucon = rd_regl(port, S3C_UCON);
++ ucon &= ~S3C_UCON_RXIRQMODE;
++ wr_regl(port, S3C_UCON, ucon);
++
++ rx_enabled(port) = 0;
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void s3c_serial_stop_tx(struct uart_port *port)
++{
++ if (tx_enabled(port)) {
++#ifdef UART_HAS_INTMSK
++ uart_disable_irq(port, UART_TX_INT);
++#else
++ disable_irq(TX_IRQ(port));
++#endif
++ tx_enabled(port) = 0;
++ if (port->flags & UPF_CONS_FLOW)
++ s3c_serial_rx_enable(port);
++ }
++}
++
++static void s3c_serial_start_tx(struct uart_port *port)
++{
++ if (!tx_enabled(port)) {
++ if (port->flags & UPF_CONS_FLOW)
++ s3c_serial_rx_disable(port);
++
++#ifdef UART_HAS_INTMSK
++ uart_enable_irq(port, UART_TX_INT);
++#else
++ enable_irq(TX_IRQ(port));
++#endif
++ tx_enabled(port) = 1;
++ }
++}
++
++
++static void s3c_serial_stop_rx(struct uart_port *port)
++{
++ if (rx_enabled(port)) {
++#ifdef UART_HAS_INTMSK
++ uart_disable_irq(port, UART_RX_INT);
++#else
++ disable_irq(RX_IRQ(port));
++#endif
++ rx_enabled(port) = 0;
++ }
++}
++
++static void s3c_serial_enable_ms(struct uart_port *port)
++{
++}
++
++static inline struct s3c_uart_info *s3c_port_to_info(struct uart_port *port)
++{
++ return to_ourport(port)->info;
++}
++
++static inline struct s3c2410_uartcfg *s3c_port_to_cfg(struct uart_port *port)
++{
++ if (port->dev == NULL)
++ return NULL;
++
++ return (struct s3c2410_uartcfg *)port->dev->platform_data;
++}
++
++static int s3c_serial_rx_fifocnt(struct s3c_uart_port *ourport,
++ unsigned long ufstat)
++{
++ struct s3c_uart_info *info = ourport->info;
++
++ if (ufstat & info->rx_fifofull)
++ return info->fifosize;
++
++ return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
++}
++
++
++/* ? - where has parity gone?? */
++#define S3C_UERSTAT_PARITY (0x1000)
++
++static irqreturn_t
++s3c_serial_rx_chars(int irq, void *dev_id)
++{
++ struct s3c_uart_port *ourport = dev_id;
++ struct uart_port *port = &ourport->port;
++ struct tty_struct *tty = port->info->tty;
++ unsigned int ufcon, ch, flag, ufstat, uerstat;
++ int max_count = 64;
++
++ while (max_count-- > 0) {
++ ufcon = rd_regl(port, S3C_UFCON);
++ ufstat = rd_regl(port, S3C_UFSTAT);
++
++ if (s3c_serial_rx_fifocnt(ourport, ufstat) == 0)
++ break;
++
++ uerstat = rd_regl(port, S3C_UERSTAT);
++ ch = rd_regb(port, S3C_URXH);
++
++ if (port->flags & UPF_CONS_FLOW) {
++ int txe = s3c_serial_txempty_nofifo(port);
++
++ if (rx_enabled(port)) {
++ if (!txe) {
++ rx_enabled(port) = 0;
++ continue;
++ }
++ } else {
++ if (txe) {
++ ufcon |= S3C_UFCON_RESETRX;
++ wr_regl(port, S3C_UFCON, ufcon);
++ rx_enabled(port) = 1;
++ goto out;
++ }
++ continue;
++ }
++ }
++
++ /* insert the character into the buffer */
++
++ flag = TTY_NORMAL;
++ port->icount.rx++;
++
++ if (uerstat & S3C_UERSTAT_ANY) {
++ dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", ch, uerstat);
++
++ /* check for break */
++ if (uerstat & S3C_UERSTAT_BREAK) {
++ dbg("break!\n");
++ port->icount.brk++;
++ if (uart_handle_break(port))
++ goto ignore_char;
++ }
++
++ if (uerstat & S3C_UERSTAT_FRAME)
++ port->icount.frame++;
++ if (uerstat & S3C_UERSTAT_OVERRUN)
++ port->icount.overrun++;
++
++ uerstat &= port->read_status_mask;
++
++ if (uerstat & S3C_UERSTAT_BREAK)
++ flag = TTY_BREAK;
++ else if (uerstat & S3C_UERSTAT_PARITY)
++ flag = TTY_PARITY;
++ else if (uerstat & ( S3C_UERSTAT_FRAME | S3C_UERSTAT_OVERRUN))
++ flag = TTY_FRAME;
++ }
++
++ if (uart_handle_sysrq_char(port, ch))
++ goto ignore_char;
++
++ uart_insert_char(port, uerstat, S3C_UERSTAT_OVERRUN, ch, flag);
++
++ ignore_char:
++ continue;
++ }
++ tty_flip_buffer_push(tty);
++
++ out:
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t s3c_serial_tx_chars(int irq, void *id)
++{
++ struct s3c_uart_port *ourport = id;
++ struct uart_port *port = &ourport->port;
++ struct circ_buf *xmit = &port->info->xmit;
++ int count = 256;
++
++ if (port->x_char) {
++ wr_regb(port, S3C_UTXH, port->x_char);
++ port->icount.tx++;
++ port->x_char = 0;
++ goto out;
++ }
++
++ /* if there isnt anything more to transmit, or the uart is now
++ * stopped, disable the uart and exit
++ */
++
++ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
++ s3c_serial_stop_tx(port);
++ goto out;
++ }
++
++ /* try and drain the buffer... */
++
++ while (!uart_circ_empty(xmit) && count-- > 0) {
++ if (rd_regl(port, S3C_UFSTAT) & ourport->info->tx_fifofull)
++ break;
++
++ wr_regb(port, S3C_UTXH, xmit->buf[xmit->tail]);
++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++ port->icount.tx++;
++ }
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(port);
++
++ if (uart_circ_empty(xmit))
++ s3c_serial_stop_tx(port);
++
++ out:
++ return IRQ_HANDLED;
++}
++
++static unsigned int s3c_serial_tx_empty(struct uart_port *port)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++ unsigned long ufstat = rd_regl(port, S3C_UFSTAT);
++ unsigned long ufcon = rd_regl(port, S3C_UFCON);
++
++ if (ufcon & S3C_UFCON_FIFOMODE) {
++ if ((ufstat & info->tx_fifomask) != 0 ||
++ (ufstat & info->tx_fifofull))
++ return 0;
++
++ return 1;
++ }
++
++ return s3c_serial_txempty_nofifo(port);
++}
++
++/* no modem control lines */
++static unsigned int s3c_serial_get_mctrl(struct uart_port *port)
++{
++ unsigned int umstat = rd_regb(port,S3C_UMSTAT);
++
++ if (umstat & S3C_UMSTAT_CTS)
++ return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
++ else
++ return TIOCM_CAR | TIOCM_DSR;
++}
++
++static void s3c_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++ /* todo - possibly remove AFC and do manual CTS */
++}
++
++static void s3c_serial_break_ctl(struct uart_port *port, int break_state)
++{
++ unsigned long flags;
++ unsigned int ucon;
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ ucon = rd_regl(port, S3C_UCON);
++
++ if (break_state)
++ ucon |= S3C_UCON_SBREAK;
++ else
++ ucon &= ~S3C_UCON_SBREAK;
++
++ wr_regl(port, S3C_UCON, ucon);
++
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static void s3c_serial_shutdown(struct uart_port *port)
++{
++ struct s3c_uart_port *ourport = to_ourport(port);
++
++#ifdef UART_HAS_INTMSK
++ if (ourport->tx_claimed || ourport->rx_claimed) {
++ free_irq(UART_IRQ(port), ourport);
++
++ ourport->tx_claimed = 0;
++ ourport->rx_claimed = 0;
++ tx_enabled(port) = 0;
++ rx_enabled(port) = 0;
++ }
++#else
++ if (ourport->tx_claimed) {
++ free_irq(TX_IRQ(port), ourport);
++ tx_enabled(port) = 0;
++ ourport->tx_claimed = 0;
++ }
++
++ if (ourport->rx_claimed) {
++ free_irq(RX_IRQ(port), ourport);
++ ourport->rx_claimed = 0;
++ rx_enabled(port) = 0;
++ }
++#endif
++}
++
++#ifdef UART_HAS_INTMSK
++static irqreturn_t
++s3c_serial_interrupt(int irq, void *dev_id)
++{
++ struct s3c_uart_port *ourport = dev_id;
++ struct uart_port *port = &ourport->port;
++ uint intpnd;
++
++ intpnd = rd_regl(port, S3C_UINTPND);
++
++ if (intpnd & UART_RX_INT) {
++ wr_regl(port, S3C_UINTPND, UART_RX_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++
++ return s3c_serial_rx_chars( irq, dev_id);
++ }
++ else if (intpnd & UART_TX_INT) {
++ wr_regl(port, S3C_UINTPND, UART_TX_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++ return s3c_serial_tx_chars(irq, dev_id);
++ }
++ else if (intpnd & UART_ERR_INT) {
++ printk("UART err int.\n");
++ wr_regl(port, S3C_UINTPND, UART_ERR_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++ return IRQ_HANDLED;
++ }
++ else if (intpnd & UART_MODEM_INT) {
++ printk("In Modem ... other case\n");
++ wr_regl(port, S3C_UINTPND, UART_MODEM_INT);
++ rd_regl(port, S3C_UINTPND); /*clearing the interrupt*/
++ return IRQ_HANDLED;
++ }
++ // work around h/w problem : interrupt status bit update delay
++ //return IRQ_NONE;
++ return IRQ_HANDLED;
++
++}
++#endif
++
++static int s3c_serial_startup(struct uart_port *port)
++{
++ struct s3c_uart_port *ourport = to_ourport(port);
++ unsigned long flags;
++ int ret;
++
++ dbg("s3c_serial_startup: port=%p (%08lx,%p)\n",
++ port->mapbase, port->membase);
++
++ local_irq_save(flags);
++
++ rx_enabled(port) = 1;
++ tx_enabled(port) = 1;
++
++#ifdef UART_HAS_INTMSK
++ uart_enable_irq(port, UART_TX_INT | UART_RX_INT);
++ ret = request_irq(UART_IRQ(port), s3c_serial_interrupt, 0,
++ s3c_serial_portname(port), ourport);
++ if (ret != 0) {
++ printk(KERN_ERR "cannot get irq %d\n", UART_IRQ(port));
++ return ret;
++ }
++#else
++ ret = request_irq(RX_IRQ(port),
++ s3c_serial_rx_chars, 0,
++ s3c_serial_portname(port), ourport);
++ if (ret != 0) {
++ printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
++ return ret;
++ }
++
++ ret = request_irq(TX_IRQ(port),
++ s3c_serial_tx_chars, 0,
++ s3c_serial_portname(port), ourport);
++ if (ret) {
++ printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
++ s3c_serial_shutdown(port);
++ local_irq_restore(flags);
++ return ret;
++ }
++#endif
++
++ ourport->rx_claimed = 1;
++ ourport->tx_claimed = 1;
++
++ dbg("s3c_serial_startup ok\n");
++
++ /* the port reset code should have done the correct
++ * register setup for the port controls */
++ local_irq_restore(flags);
++ return ret;
++}
++
++/* power power management control */
++static void s3c_serial_pm(struct uart_port *port, unsigned int level,
++ unsigned int old)
++{
++ struct s3c_uart_port *ourport = to_ourport(port);
++
++ switch (level) {
++ case 3:
++ if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
++ clk_disable(ourport->baudclk);
++
++ clk_disable(ourport->clk);
++ break;
++
++ case 0:
++ clk_enable(ourport->clk);
++
++ if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
++ clk_enable(ourport->baudclk);
++
++ break;
++ default:
++ printk(KERN_ERR "s3c_serial: unknown pm %d\n", level);
++ }
++}
++
++/* baud rate calculation
++ *
++ * The UARTs on the S3C can take their clocks from a number
++ * of different sources, including the peripheral clock ("pclk") and an
++ * external clock ("uclk"). The S3C2413 also adds the core clock ("fclk")
++ * with a programmable extra divisor.
++ *
++ * The following code goes through the clock sources, and calculates the
++ * baud clocks (and the resultant actual baud rates) and then tries to
++ * pick the closest one and select that.
++ *
++ * NOTES:
++ * 1) there is no current code to properly select/deselect FCLK on
++ * the s3c2413, so only specify FCLK or non-FCLK in the clock
++ * sources for the UART
++ *
++*/
++
++
++#define MAX_CLKS (8)
++
++static struct s3c24xx_uart_clksrc tmp_clksrc = {
++ .name = "pclkd1",
++ .min_baud = 0,
++ .max_baud = 0,
++ .divisor = 1,
++};
++
++static inline int
++s3c_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ return (info->get_clksrc)(port, c);
++}
++
++static inline int
++s3c_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ return (info->set_clksrc)(port, c);
++}
++
++
++struct baud_calc {
++ struct s3c24xx_uart_clksrc *clksrc;
++ unsigned int calc;
++ unsigned int quot;
++ unsigned int slot;
++ struct clk *src;
++};
++
++static int s3c_serial_calcbaud(struct baud_calc *calc,
++ struct uart_port *port,
++ struct s3c24xx_uart_clksrc *clksrc,
++ unsigned int baud)
++{
++ unsigned long rate,nslot;
++ unsigned long tempdiv;
++
++ calc->src = clk_get(port->dev, clksrc->name);
++ if (calc->src == NULL || IS_ERR(calc->src))
++ return 0;
++
++ baud/=10;
++
++ rate = clk_get_rate(calc->src);
++ rate /= clksrc->divisor;
++
++ calc->clksrc = clksrc;
++
++ tempdiv = (rate*10/(baud*16))-100;
++ nslot = (((tempdiv%100)*16)+50)/100; /* 50 means round operation by ryu */
++ calc->quot = tempdiv/100;
++ calc->calc = (rate / (calc->quot * 16));
++ calc->slot = nSlotTable[nslot];
++ printk(KERN_DEBUG "FOUND quot %d, calc %d, slot 0x%x, nslot %ld\n",
++ calc->quot, calc->calc ,
++ calc->slot, nslot);
++ return 1;
++}
++
++static unsigned int s3c_serial_getclk(struct uart_port *port,
++ struct s3c24xx_uart_clksrc **clksrc,
++ struct clk **clk,
++ unsigned int baud, unsigned int *slot)
++{
++ struct s3c2410_uartcfg *cfg = s3c_port_to_cfg(port);
++ struct s3c24xx_uart_clksrc *clkp;
++ struct baud_calc res[MAX_CLKS];
++ struct baud_calc *resptr, *best, *sptr;
++ int i;
++
++ clkp = cfg->clocks;
++ best = NULL;
++
++ if (cfg->clocks_size < 2) {
++ if (cfg->clocks_size == 0)
++ clkp = &tmp_clksrc;
++
++ /* check to see if we're sourcing fclk, and if so we're
++ * going to have to update the clock source
++ */
++
++ if (strcmp(clkp->name, "fclk") == 0) {
++ struct s3c24xx_uart_clksrc src;
++
++ s3c_serial_getsource(port, &src);
++
++ /* check that the port already using fclk, and if
++ * not, then re-select fclk
++ */
++
++ if (strcmp(src.name, clkp->name) == 0) {
++ s3c_serial_setsource(port, clkp);
++ s3c_serial_getsource(port, &src);
++ }
++
++ clkp->divisor = src.divisor;
++ }
++
++ s3c_serial_calcbaud(res, port, clkp, baud);
++ best = res;
++ resptr = best + 1;
++ } else {
++ resptr = res;
++
++ for (i = 0; i < cfg->clocks_size; i++, clkp++) {
++ if (s3c_serial_calcbaud(resptr, port, clkp, baud))
++ resptr++;
++ }
++ }
++
++ /* ok, we now need to select the best clock we found */
++
++ if (best==NULL) {
++ unsigned int deviation = (1<<30)|((1<<30)-1);
++ int calc_deviation;
++
++ best = sptr = res;
++
++ for (sptr = res; sptr < resptr; sptr++) {
++ printk(KERN_DEBUG
++ "found clk %p (%s) quot %d, calc %d\n",
++ sptr->clksrc, sptr->clksrc->name,
++ sptr->quot, sptr->calc);
++
++ calc_deviation = baud - sptr->calc;
++
++ if (calc_deviation < 0)
++ calc_deviation = -calc_deviation;
++
++ if (calc_deviation < deviation) {
++ best = sptr;
++ deviation = calc_deviation;
++ }
++ }
++
++ printk(KERN_DEBUG "The best clksrc among candidate clksrc: %p(%s) (deviation: %d bps)\n", best, best->clksrc->name, deviation);
++ }
++
++ printk(KERN_DEBUG "Selected clock is %p (%s) quot %d, calc %d\n",
++ best->clksrc, best->clksrc->name, best->quot, best->calc);
++
++ /* store results to pass back */
++ *clksrc = best->clksrc;
++ *clk = best->src;
++ *slot = best->slot;
++
++ return best->quot;
++}
++
++static void s3c_serial_set_termios(struct uart_port *port,
++ struct ktermios *termios,
++ struct ktermios *old)
++{
++ struct s3c2410_uartcfg *cfg = s3c_port_to_cfg(port);
++ struct s3c_uart_port *ourport = to_ourport(port);
++ struct s3c24xx_uart_clksrc *clksrc = NULL;
++ struct clk *clk = NULL;
++ unsigned long flags;
++ unsigned int baud, quot, slot = 0;
++ unsigned int ulcon;
++ unsigned int umcon;
++
++ /*
++ * We don't support modem control lines.
++ */
++ termios->c_cflag &= ~(HUPCL | CMSPAR);
++ termios->c_cflag |= CLOCAL;
++
++ /*
++ * Ask the core to calculate the divisor for us.
++ */
++
++ baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
++
++ if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
++ quot = port->custom_divisor;
++ else
++ quot = s3c_serial_getclk(port, &clksrc, &clk, baud, &slot);
++
++ /* check to see if we need to change clock source */
++
++ if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
++ s3c_serial_setsource(port, clksrc);
++
++ if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
++ clk_disable(ourport->baudclk);
++ ourport->baudclk = NULL;
++ }
++
++ clk_enable(clk);
++
++ ourport->clksrc = clksrc;
++ ourport->baudclk = clk;
++ }
++
++ switch (termios->c_cflag & CSIZE) {
++ case CS5:
++ dbg("config: 5bits/char\n");
++ ulcon = S3C_LCON_CS5;
++ break;
++ case CS6:
++ dbg("config: 6bits/char\n");
++ ulcon = S3C_LCON_CS6;
++ break;
++ case CS7:
++ dbg("config: 7bits/char\n");
++ ulcon = S3C_LCON_CS7;
++ break;
++ case CS8:
++ default:
++ dbg("config: 8bits/char\n");
++ ulcon = S3C_LCON_CS8;
++ break;
++ }
++
++ /* preserve original lcon IR settings */
++ ulcon |= (cfg->ulcon & S3C_LCON_IRM);
++
++ if (termios->c_cflag & CSTOPB)
++ ulcon |= S3C_LCON_STOPB;
++
++ umcon = (termios->c_cflag & CRTSCTS) ? S3C_UMCOM_AFC : 0;
++
++ if (termios->c_cflag & PARENB) {
++ if (termios->c_cflag & PARODD)
++ ulcon |= S3C_LCON_PODD;
++ else
++ ulcon |= S3C_LCON_PEVEN;
++ } else {
++ ulcon |= S3C_LCON_PNONE;
++ }
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
++
++ wr_regl(port, S3C_ULCON, ulcon);
++ wr_regl(port, S3C_UBRDIV, quot);
++ wr_regl(port, S3C_UDIVSLOT, slot);
++ wr_regl(port, S3C_UMCON, umcon);
++
++ dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
++ rd_regl(port, S3C_ULCON),
++ rd_regl(port, S3C_UCON),
++ rd_regl(port, S3C_UFCON));
++
++ /*
++ * Update the per-port timeout.
++ */
++ uart_update_timeout(port, termios->c_cflag, baud);
++
++ /*
++ * Which character status flags are we interested in?
++ */
++ port->read_status_mask = S3C_UERSTAT_OVERRUN;
++ if (termios->c_iflag & INPCK)
++ port->read_status_mask |= S3C_UERSTAT_FRAME | S3C_UERSTAT_PARITY;
++
++ /*
++ * Which character status flags should we ignore?
++ */
++ port->ignore_status_mask = 0;
++ if (termios->c_iflag & IGNPAR)
++ port->ignore_status_mask |= S3C_UERSTAT_OVERRUN;
++ if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
++ port->ignore_status_mask |= S3C_UERSTAT_FRAME;
++
++ /*
++ * Ignore all characters if CREAD is not set.
++ */
++ if ((termios->c_cflag & CREAD) == 0)
++ port->ignore_status_mask |= RXSTAT_DUMMY_READ;
++
++ spin_unlock_irqrestore(&port->lock, flags);
++}
++
++static const char *s3c_serial_type(struct uart_port *port)
++{
++ switch (port->type) {
++ case PORT_S3C2410:
++ return "S3C";
++ default:
++ return NULL;
++ }
++}
++
++#define MAP_SIZE (0x100)
++
++static void s3c_serial_release_port(struct uart_port *port)
++{
++ release_mem_region(port->mapbase, MAP_SIZE);
++}
++
++static int s3c_serial_request_port(struct uart_port *port)
++{
++ const char *name = s3c_serial_portname(port);
++ return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
++}
++
++static void s3c_serial_config_port(struct uart_port *port, int flags)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ if (flags & UART_CONFIG_TYPE && s3c_serial_request_port(port) == 0)
++ port->type = info->type;
++}
++
++/*
++ * verify the new serial_struct (for TIOCSSERIAL).
++ */
++static int
++s3c_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ if (ser->type != PORT_UNKNOWN && ser->type != info->type)
++ return -EINVAL;
++
++ return 0;
++}
++
++
++#ifdef CONFIG_SERIAL_S5PC1XX_CONSOLE
++
++static struct console s3c_serial_console;
++
++#define S3C64XX_SERIAL_CONSOLE &s3c_serial_console
++#else
++#define S3C64XX_SERIAL_CONSOLE NULL
++#endif
++
++static struct uart_ops s3c_serial_ops = {
++ .pm = s3c_serial_pm,
++ .tx_empty = s3c_serial_tx_empty,
++ .get_mctrl = s3c_serial_get_mctrl,
++ .set_mctrl = s3c_serial_set_mctrl,
++ .stop_tx = s3c_serial_stop_tx,
++ .start_tx = s3c_serial_start_tx,
++ .stop_rx = s3c_serial_stop_rx,
++ .enable_ms = s3c_serial_enable_ms,
++ .break_ctl = s3c_serial_break_ctl,
++ .startup = s3c_serial_startup,
++ .shutdown = s3c_serial_shutdown,
++ .set_termios = s3c_serial_set_termios,
++ .type = s3c_serial_type,
++ .release_port = s3c_serial_release_port,
++ .request_port = s3c_serial_request_port,
++ .config_port = s3c_serial_config_port,
++ .verify_port = s3c_serial_verify_port,
++};
++
++
++static struct uart_driver s3c_uart_drv = {
++ .owner = THIS_MODULE,
++ .dev_name = "s3c_serial",
++ .nr = NR_PORTS,
++ .cons = S3C64XX_SERIAL_CONSOLE,
++ .driver_name = S3C_SERIAL_NAME,
++ .major = S3C_SERIAL_MAJOR,
++ .minor = S3C_SERIAL_MINOR,
++};
++
++static struct s3c_uart_port s3c_serial_ports[NR_PORTS] = {
++ [0] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART0,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 0,
++ }
++ },
++ [1] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART1,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 1,
++ }
++ },
++#if NR_PORTS > 2
++ [2] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART2,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 2,
++ }
++ },
++ [3] = {
++ .port = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .iotype = UPIO_MEM,
++ .irq = S3C_IRQ_UART3,
++ .uartclk = 0,
++ .fifosize = UART_FIFO_SIZE,
++ .ops = &s3c_serial_ops,
++ .flags = UPF_BOOT_AUTOCONF,
++ .line = 3,
++ }
++ }
++#endif
++};
++
++/* s3c_serial_resetport
++ *
++ * wrapper to call the specific reset for this port (reset the fifos
++ * and the settings)
++*/
++
++static int s3c_serial_resetport(struct uart_port *port,
++ struct s3c2410_uartcfg *cfg)
++{
++#if 0
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++
++ return (info->reset_port)(port, cfg);
++#else
++ /* ensure registers are setup */
++ dbg("s3c_serial_resetport: port=%p (%08lx), cfg=%p\n",
++ port, port->mapbase, cfg);
++
++ wr_regl(port, S3C_UCON, cfg->ucon);
++ wr_regl(port, S3C_ULCON, cfg->ulcon);
++
++ /* reset both fifos */
++ wr_regl(port, S3C_UFCON, cfg->ufcon | S3C_UFCON_RESETBOTH);
++ wr_regl(port, S3C_UFCON, cfg->ufcon);
++
++ return 0;
++
++#endif
++}
++
++/* s3c_serial_init_port
++ *
++ * initialise a single serial port from the platform device given
++ */
++
++static int s3c_serial_init_port(struct s3c_uart_port *ourport,
++ struct s3c_uart_info *info,
++ struct platform_device *plat_dev)
++{
++ struct uart_port *port = &ourport->port;
++ struct s3c2410_uartcfg *cfg;
++ struct resource *res;
++
++ dbg("s3c_serial_init_port: port=%p, plat_dev=%p\n", port, plat_dev);
++
++ if (plat_dev == NULL)
++ return -ENODEV;
++
++ cfg = s3c_dev_to_cfg(&plat_dev->dev);
++
++ if (port->mapbase != 0)
++ return 0;
++
++ if (cfg->hwport > NR_PORTS)
++ return -EINVAL;
++
++ /*GPIO setup for each port*/
++ switch(port->line) {
++ case 0:
++ gpio_set_pin(S3C_GPA0, S3C_GPA0_UART_RXD0);
++ gpio_set_pin(S3C_GPA1, S3C_GPA1_UART_TXD0);
++ gpio_set_pin(S3C_GPA2, S3C_GPA2_UART_CTS0);
++ gpio_set_pin(S3C_GPA3, S3C_GPA3_UART_RTS0);
++ break;
++ case 1:
++ gpio_set_pin(S3C_GPA4, S3C_GPA4_UART_RXD1);
++ gpio_set_pin(S3C_GPA5, S3C_GPA5_UART_TXD1);
++ gpio_set_pin(S3C_GPA5, S3C_GPA6_UART_CTS1);
++ gpio_set_pin(S3C_GPA7, S3C_GPA7_UART_RTS1);
++ break;
++ case 2:
++ gpio_set_pin(S3C_GPB0, S3C_GPB0_UART_RXD2);
++ gpio_set_pin(S3C_GPB1, S3C_GPB1_UART_TXD2);
++ break;
++ case 3:
++ gpio_set_pin(S3C_GPB2, S3C_GPB2_UART_RXD3);
++ gpio_set_pin(S3C_GPB3, S3C_GPB3_UART_TXD3);
++ break;
++ default:
++ break;
++ }
++
++ /* setup info for port */
++ port->dev = &plat_dev->dev;
++ ourport->info = info;
++
++ /* copy the info in from provided structure */
++ ourport->port.fifosize = info->fifosize;
++
++ dbg("s3c_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
++
++ port->uartclk = UART_CLK;
++
++ if (cfg->uart_flags & UPF_CONS_FLOW) {
++ dbg("s3c_serial_init_port: enabling flow control\n");
++ port->flags |= UPF_CONS_FLOW;
++ }
++
++ /* sort our the physical and virtual addresses for each UART */
++
++ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
++ if (res == NULL) {
++ printk(KERN_ERR "failed to find memory resource for uart\n");
++ return -EINVAL;
++ }
++
++ dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
++
++ port->mapbase = res->start;
++ port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
++ port->irq = platform_get_irq(plat_dev, 0);
++
++ ourport->clk = clk_get(&plat_dev->dev, "UART0");
++
++ dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
++ port->mapbase, port->membase, port->irq, port->uartclk);
++
++ /* reset the fifos (and setup the uart) */
++ s3c_serial_resetport(port, cfg);
++ return 0;
++}
++
++/* Device driver serial port probe */
++static int probe_index = 0;
++
++static int s3c6400_serial_probe(struct platform_device *dev,
++ struct s3c_uart_info *info)
++{
++ struct s3c_uart_port *ourport;
++ int ret;
++
++ dbg("s3c_serial_probe(%p) %d\n", dev, probe_index);
++
++ ourport = &s3c_serial_ports[probe_index];
++ probe_index++;
++
++ dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
++
++ //ret = s3c_serial_init_port(ourport, &s3c_uart_inf, dev);
++ ret = s3c_serial_init_port(ourport, info, dev);
++ if (ret < 0)
++ goto probe_err;
++
++ dbg("%s: adding port\n", __FUNCTION__);
++ uart_add_one_port(&s3c_uart_drv, &ourport->port);
++ platform_set_drvdata(dev, &ourport->port);
++
++ return 0;
++
++ probe_err:
++ return ret;
++}
++
++static int s3c_serial_remove(struct platform_device *dev)
++{
++ struct uart_port *port = s3c_dev_to_port(&dev->dev);
++
++ if (port)
++ uart_remove_one_port(&s3c_uart_drv, port);
++
++ return 0;
++}
++
++/* UART power management code */
++
++#ifdef CONFIG_PM
++
++static int s3c_serial_suspend(struct platform_device *dev, pm_message_t state)
++{
++ struct uart_port *port = s3c_dev_to_port(&dev->dev);
++
++ if (port)
++ uart_suspend_port(&s3c_uart_drv, port);
++
++ return 0;
++}
++
++static int s3c_serial_resume(struct platform_device *dev)
++{
++ struct uart_port *port = s3c_dev_to_port(&dev->dev);
++ struct s3c_uart_port *ourport = to_ourport(port);
++
++ if (port) {
++ clk_enable(ourport->clk);
++ s3c_serial_resetport(port, s3c_port_to_cfg(port));
++ clk_disable(ourport->clk);
++
++ uart_resume_port(&s3c_uart_drv, port);
++ }
++
++ return 0;
++}
++
++#else
++#define s3c_serial_suspend NULL
++#define s3c_serial_resume NULL
++#endif
++
++static int s3c_serial_init(struct platform_driver *drv,
++ struct s3c_uart_info *info)
++{
++ dbg("s3c64xx_serial_init(%p,%p)\n", drv, info);
++ return platform_driver_register(drv);
++}
++
++static struct s3c_uart_info s3c_uart_inf = {
++ .name = "Samsung S3C UART",
++ .type = PORT_S3C2410,
++ .fifosize = UART_FIFO_SIZE,
++ .rx_fifomask = S3C_UFSTAT_RXMASK,
++ .rx_fifoshift = S3C_UFSTAT_RXSHIFT,
++ .rx_fifofull = S3C_UFSTAT_RXFULL,
++ .tx_fifofull = S3C_UFSTAT_TXFULL,
++ .tx_fifomask = S3C_UFSTAT_TXMASK,
++ .tx_fifoshift = S3C_UFSTAT_TXSHIFT,
++ .get_clksrc = s3c_serial_getsource_hw,
++ .set_clksrc = s3c_serial_setsource_hw,
++// .reset_port = s3c_serial_resetport,
++};
++
++/* device management */
++
++static int s3c_serial_probe(struct platform_device *dev)
++{
++ return s3c6400_serial_probe(dev, &s3c_uart_inf);
++}
++
++static struct platform_driver s3c_serial_drv = {
++ .probe = s3c_serial_probe,
++ .remove = s3c_serial_remove,
++ .suspend = s3c_serial_suspend,
++ .resume = s3c_serial_resume,
++ .driver = {
++ .name = "s3c-uart",
++ .owner = THIS_MODULE,
++ },
++};
++
++static inline int s3c6400_serial_init(void)
++{
++ return s3c_serial_init(&s3c_serial_drv, &s3c_uart_inf);
++}
++
++static inline void s3c6400_serial_exit(void)
++{
++ platform_driver_unregister(&s3c_serial_drv);
++}
++
++
++/* module initialisation code */
++static int __init s3c_serial_modinit(void)
++{
++ int ret;
++
++ ret = uart_register_driver(&s3c_uart_drv);
++ if (ret < 0) {
++ printk(KERN_ERR "failed to register UART driver\n");
++ return -1;
++ }
++
++ s3c6400_serial_init();
++
++ return 0;
++}
++
++static void __exit s3c_serial_modexit(void)
++{
++ s3c6400_serial_exit();
++
++ uart_unregister_driver(&s3c_uart_drv);
++}
++
++module_init(s3c_serial_modinit);
++module_exit(s3c_serial_modexit);
++
++/* ----------------------------------------------------------------------------------*/
++/* Console code for UART */
++/*-----------------------------------------------------------------------------------*/
++
++#ifdef CONFIG_SERIAL_S5PC1XX_CONSOLE
++
++static struct uart_port *cons_uart;
++
++static int
++s3c_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
++{
++ struct s3c_uart_info *info = s3c_port_to_info(port);
++ unsigned long ufstat, utrstat;
++
++ if (ufcon & S3C_UFCON_FIFOMODE) {
++ /* fifo mode - check ammount of data in fifo registers... */
++ ufstat = rd_regl(port, S3C_UFSTAT);
++ return (ufstat & info->tx_fifofull) ? 0 : 1;
++ }
++
++ /* in non-fifo mode, we go and use the tx buffer empty */
++ utrstat = rd_regl(port, S3C_UTRSTAT);
++ return (utrstat & S3C_UTRSTAT_TXE) ? 1 : 0;
++}
++
++static void
++s3c_serial_console_write(struct console *co, const char *s,
++ unsigned int count)
++{
++ int i;
++ unsigned int ufcon = rd_regl(cons_uart, S3C_UFCON);
++
++ for (i = 0; i < count; i++) {
++ while (!s3c_serial_console_txrdy(cons_uart, ufcon))
++ barrier();
++
++ wr_regb(cons_uart, S3C_UTXH, s[i]);
++
++ if (s[i] == '\n') {
++ while (!s3c_serial_console_txrdy(cons_uart, ufcon))
++ barrier();
++
++ wr_regb(cons_uart, S3C_UTXH, '\r');
++ }
++ }
++}
++
++static void __init
++s3c_serial_get_options(struct uart_port *port, int *baud,
++ int *parity, int *bits)
++{
++ struct s3c24xx_uart_clksrc clksrc;
++ struct clk *clk;
++ unsigned int ulcon;
++ unsigned int ucon;
++ unsigned int ubrdiv;
++ unsigned long rate;
++
++ ulcon = rd_regl(port, S3C_ULCON);
++ ucon = rd_regl(port, S3C_UCON);
++ ubrdiv = rd_regl(port, S3C_UBRDIV);
++
++ dbg("s3c_serial_get_options: port=%p\n"
++ "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
++ port, ulcon, ucon, ubrdiv);
++
++ if ((ucon & 0xf) != 0) {
++ /* consider the serial port configured if the tx/rx mode set */
++ switch (ulcon & S3C_LCON_CSMASK) {
++ case S3C_LCON_CS5:
++ *bits = 5;
++ break;
++
++ case S3C_LCON_CS6:
++ *bits = 6;
++ break;
++
++ case S3C_LCON_CS7:
++ *bits = 7;
++ break;
++
++ case S3C_LCON_CS8:
++ default:
++ *bits = 8;
++ break;
++ }
++
++ switch (ulcon & S3C_LCON_PMASK) {
++ case S3C_LCON_PEVEN:
++ *parity = 'e';
++ break;
++
++ case S3C_LCON_PODD:
++ *parity = 'o';
++ break;
++
++ case S3C_LCON_PNONE:
++ default:
++ *parity = 'n';
++ }
++
++ /* now calculate the baud rate */
++ s3c_serial_getsource(port, &clksrc);
++
++ clk = clk_get(port->dev, clksrc.name);
++ if (!IS_ERR(clk) && clk != NULL)
++ rate = clk_get_rate(clk) / clksrc.divisor;
++ else
++ rate = 1;
++
++
++ *baud = rate / ( 16 * (ubrdiv + 1));
++ dbg("calculated baud %d\n", *baud);
++ }
++
++}
++
++/* s3c_serial_init_ports
++ *
++ * initialise the serial ports from the machine provided initialisation
++ * data.
++*/
++
++static int s3c_serial_init_ports(struct s3c_uart_info *info)
++{
++ struct s3c_uart_port *ptr = s3c_serial_ports;
++ struct platform_device **platdev_ptr;
++ int i;
++
++ dbg("s3c_serial_init_ports: initialising ports...\n");
++
++ platdev_ptr = s3c24xx_uart_devs;
++
++ for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
++ s3c_serial_init_port(ptr, info, *platdev_ptr);
++ }
++
++ return 0;
++}
++
++static int __init
++s3c_serial_console_setup(struct console *co, char *options)
++{
++ struct uart_port *port;
++ int baud = 9600;
++ int bits = 8;
++ int parity = 'n';
++ int flow = 'n';
++
++ dbg("s3c_serial_console_setup: co=%p (%d), %s\n",
++ co, co->index, options);
++
++ /* is this a valid port */
++
++ if (co->index == -1 || co->index >= NR_PORTS)
++ co->index = 0;
++
++ port = &s3c_serial_ports[co->index].port;
++
++ /* is the port configured? */
++
++ if (port->mapbase == 0x0) {
++ co->index = 0;
++ port = &s3c_serial_ports[co->index].port;
++ }
++
++ cons_uart = port;
++
++ dbg("s3c_serial_console_setup: port=%p (%d)\n", port, co->index);
++
++ /*
++ * Check whether an invalid uart number has been specified, and
++ * if so, search for the first available port that does have
++ * console support.
++ */
++ if (options)
++ uart_parse_options(options, &baud, &parity, &bits, &flow);
++ else
++ s3c_serial_get_options(port, &baud, &parity, &bits);
++
++ dbg("s3c_serial_console_setup: baud %d\n", baud);
++
++ return uart_set_options(port, co, baud, parity, bits, flow);
++}
++
++/* s3c_serial_initconsole
++ *
++ * initialise the console from one of the uart drivers
++ */
++
++static struct console s3c_serial_console =
++{
++ .name = S3C_SERIAL_NAME,
++ .device = uart_console_device,
++ .flags = CON_PRINTBUFFER,
++ .index = -1,
++ .write = s3c_serial_console_write,
++ .setup = s3c_serial_console_setup
++};
++
++static int s3c_serial_initconsole(void)
++{
++ dbg("s3c_serial_initconsole\n");
++
++ s3c_serial_console.data = &s3c_uart_drv;
++ s3c_serial_init_ports(&s3c_uart_inf);
++
++ register_console(&s3c_serial_console);
++ return 0;
++}
++
++console_initcall(s3c_serial_initconsole);
++
++#endif /* CONFIG_SERIAL_S3C_CONSOLE */
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
++MODULE_DESCRIPTION("Samsung S3C Serial port driver");
+diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
+index abf0504..12380e8 100644
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -174,6 +174,57 @@ config SPI_S3C24XX_GPIO
+ GPIO lines to provide the SPI bus. This can be used where
+ the inbuilt hardware cannot provide the transfer mode, or
+ where the board is using non hardware connected pins.
++
++config HS_SPI_S3C2450
++ tristate "S3C2450 High Speed SPI Driver"
++ depends on SPI && MACH_SMDK2450
++ help
++ Say Y here to include support for SPI controller in the
++ Samsung S3C2450 based System-on-Chip devices.
++
++config HS_SPI_S3C2416
++ tristate "S3C2416 High Speed SPI Driver"
++ depends on SPI && MACH_SMDK2416
++ help
++ Say Y here to include support for SPI controller in the
++ Samsung S3C2416 based System-on-Chip devices.
++
++config HS_SPI_S3C6410
++ tristate "S3C6410 High Speed SPI Driver"
++ depends on SPI && (MACH_SMDK6410 || MACH_SMDK6430)
++ help
++ Say Y here to include support for SPI controller in the
++ Samsung S3C6410 based System-on-Chip devices.
++
++choice
++ prompt "High Speed SPI Clock Implementations"
++ depends on HS_SPI_S3C2450 || HS_SPI_S3C6410 || HS_SPI_S3C2416
++
++config SPICLK_PCLK
++ bool "PCLK"
++ depends on HS_SPI_S3C2450 || HS_SPI_S3C6410 || HS_SPI_S3C2416
++ help
++ Say Y here to include support for pclk source.
++
++config SPICLK_EPLL
++ bool "EPLL"
++ depends on HS_SPI_S3C2450 || HS_SPI_S3C6410 || HS_SPI_S3C2416
++ help
++ Say Y here to include support for EPLL source.
++
++config SPICLK_USBCLK
++ bool "USBCLK"
++ depends on HS_SPI_S3C6400 || HS_SPI_S3C6410
++ help
++ Say Y here to include support for USB clock source.
++
++endchoice
++
++config WORD_TRANSIZE
++ bool "Tansfer size as Word"
++ depends on HS_SPI_S3C6400 || HS_SPI_S3C6410
++ help
++ Say Y here to include support for word transfer size.
+
+ config SPI_TXX9
+ tristate "Toshiba TXx9 SPI controller"
+diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
+index 41fbac4..35c6f87 100644
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -35,6 +35,18 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
+ obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o
+ # ... add above this line ...
+
++ifeq ($(CONFIG_MACH_SMDK2450),y)
++obj-$(CONFIG_SPI) += spi-dev.o hspi-s3c24xx.o
++endif
++
++ifeq ($(CONFIG_MACH_SMDK2416),y)
++obj-$(CONFIG_SPI) += spi-dev.o hspi-s3c24xx.o
++endif
++
++ifeq ($(CONFIG_MACH_SMDK6410),y)
++obj-$(CONFIG_SPI) += spi-dev.o hspi-s3c64xx.o
++endif
++
+ # SPI slave controller drivers (upstream link)
+ # ... add above this line ...
+
+diff --git a/drivers/spi/hspi-s3c24xx.c b/drivers/spi/hspi-s3c24xx.c
+new file mode 100644
+index 0000000..853e240
+--- /dev/null
++++ b/drivers/spi/hspi-s3c24xx.c
+@@ -0,0 +1,773 @@
++/* spi-s3c2443.c
++ *
++ * Copyright (C) 2006 Samsung Electronics Co. Ltd.
++ *
++ * S3C2443 SPI Controller
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/time.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++
++#include <asm/arch-s3c2410/regs-s3c-clock.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-clock.h>
++#include <asm/arch/regs-spi.h>
++#include <asm/dma.h>
++
++#include "spi-dev.h"
++#include "hspi-s3c24xx.h"
++
++#undef debug
++//#define debug
++
++#ifdef debug
++#define DBG(x...) printk(x)
++#define DEBUG printk("%s :: %d\n",__FUNCTION__,__LINE__)
++void print_reg(struct s3c_spi *spi)
++{
++ printk("CH_CFG = 0x%08x\n",readl(spi->regs + S3C_CH_CFG));
++ printk("CLK_CFG = 0x%08x\n",readl(spi->regs + S3C_CLK_CFG));
++ printk("MODE_CFG = 0x%08x\n",readl(spi->regs + S3C_MODE_CFG));
++ printk("SLAVE_CFG = 0x%08x\n",readl(spi->regs + S3C_SLAVE_SEL));
++ printk("INT_EN = 0x%08x\n",readl(spi->regs + S3C_SPI_INT_EN));
++ printk("SPI_STATUS = 0x%08x\n",readl(spi->regs + S3C_SPI_STATUS));
++ printk("PACKET_CNT = 0x%08x\n",readl(spi->regs + S3C_PACKET_CNT));
++ printk("PEND_CLR = 0x%08x\n",readl(spi->regs + S3C_PENDING_CLR));
++}
++#else
++#define DEBUG
++#define DBG(x...) do { } while (0)
++void print_reg(struct s3c_spi *spi)
++{
++}
++#endif
++
++static void s3c_spi_free(struct s3c_spi *spi)
++{
++ DEBUG;
++
++ if (spi->clk != NULL && !IS_ERR(spi->clk)) {
++ clk_disable(spi->clk);
++ clk_put(spi->clk);
++ spi->clk = NULL;
++ }
++
++ if (spi->regs != NULL) {
++ iounmap(spi->regs);
++ spi->regs = NULL;
++ }
++
++ if (spi->ioarea != NULL) {
++ release_resource(spi->ioarea);
++ kfree(spi->ioarea);
++ spi->ioarea = NULL;
++ }
++}
++
++static int s3c_spi_hw_init(struct s3c_spi *spi)
++{
++
++ /* program defaults into the registers */
++ writel(readl(S3C2443_SCLKCON)|(1<<14), S3C2443_SCLKCON);
++ writel(readl(S3C2443_PCLKCON)|(1<<6), S3C2443_PCLKCON);
++
++ writel(readl(S3C24XX_MISCCR)|S3C24XX_MISCCR_SPISEL, S3C24XX_MISCCR);
++
++ /* initialize the gpio */
++ s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
++ s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
++ s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
++
++ s3c2410_gpio_cfgpin(S3C2410_GPL13, S3C2410_GPL13_SS0);
++ s3c2410_gpio_cfgpin(S3C2410_GPL14, S3C2410_GPL14_SS1);
++
++ s3c2410_gpio_cfgpin(S3C2410_GPL11, S3C2410_GPL11_SPIMOSI1);
++ s3c2410_gpio_cfgpin(S3C2410_GPL12, S3C2410_GPL12_SPIMISO1);
++ s3c2410_gpio_cfgpin(S3C2410_GPL10, S3C2410_GPL10_SPICLK1);
++
++#ifdef CONFIG_SPICLK_PCLK
++ /*Enable PCLK into the HS SPI*/
++ writel(readl(S3C2443_PCLKCON)|(1<<6), S3C2443_PCLKCON);
++
++ clk_enable(spi->clk);
++
++#elif defined CONFIG_SPICLK_EPLL
++ /* implemetation when use EPLL clock */
++ writel(0x800, S3C2443_LOCKCON1);
++ writel( (readl( S3C2443_CLKSRC ) | (1 << 6) ), S3C2443_CLKSRC); // EPLL Output
++
++#if defined(CONFIG_CPU_S3C2443)
++ writel((40<<16)|(1<<8)|(1<<0) ,S3C2443_EPLLCON);//96MHz
++#elif defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ writel((48<<16)|(3<<8)|(1<<0) ,S3C2443_EPLLCON);//96MHz
++#else
++# error Any CPU Type is not selected
++#endif
++
++ writel( readl(S3C2443_EPLLCON)& (~(1<<24)) , S3C2443_EPLLCON ); //EPLL On
++ writel(( readl(S3C2443_CLKDIV1) & (~(0x3<<24))) | (0x0 << 24) , S3C2443_CLKDIV1 ); // Epll Ratio is 1
++ writel(( readl(S3C24XX_MISCCR) & (~(0x7<<8))) | (0x1 << 8) , S3C24XX_MISCCR );
++
++ /* Epll, prescaler = 1 */
++ /* clock = ( clock source / (2 * ( prescaler + 1))) */
++ writel(0x501, spi->regs + S3C_CLK_CFG); //Use EPLL Clock and Clock On Prescaler 1
++#else
++#error you must define correct confige file.
++#endif
++ /* hspi software restet */
++
++ writeb(readb(spi->regs + S3C_CH_CFG) | (1<<5), spi->regs + S3C_CH_CFG);
++ writeb(readb(spi->regs + S3C_CH_CFG) & (~(1<<5)), spi->regs + S3C_CH_CFG);
++
++ DEBUG;
++
++ return 0;
++}
++
++static int s3c_spi_dma_init(struct s3c_spi *spi, int mode)
++{
++ DEBUG;
++
++ // TX
++ if (mode == 0) {
++ s3c2410_dma_devconfig(spi->dma, S3C2410_DMASRC_MEM, S3C_SPI_DMA_HWCFG, S3C_SPI_TX_DATA_REG);
++ s3c2410_dma_config(spi->dma, S3C_DMA_XFER_BYTE, S3C_DCON_SPI1);
++
++ }
++
++ // RX
++ if (mode == 1) {
++ s3c2410_dma_devconfig(spi->dma, S3C2410_DMASRC_HW, S3C_SPI_DMA_HWCFG, S3C_SPI_RX_DATA_REG);
++ s3c2410_dma_config(spi->dma, S3C_DMA_XFER_BYTE, S3C_DCON_SPI1);
++
++ }
++
++ s3c2410_dma_setflags(spi->dma, S3C2410_DMAF_AUTOSTART);
++
++ return 0;
++}
++
++static inline void s3c_spi_write_fifo(struct s3c_spi *spi)
++{
++ u32 wdata = 0;
++
++ if (spi->msg->wbuf) {
++ wdata = spi->msg->wbuf[spi->msg_ptr++];
++ } else {
++ spi->msg_ptr++;
++ wdata = 0xff;
++ }
++
++ DBG("wdata = %x\n",wdata);
++ writel(wdata, spi->regs + S3C_SPI_TX_DATA);
++}
++
++/* s3c_spi_master_complete
++ *
++ * complete the message and wake up the caller, using the given return code,
++ * or zero to mean ok.
++*/
++static inline void s3c_spi_master_complete(struct s3c_spi *spi, int ret)
++{
++ DEBUG;
++
++ spi->msg_ptr = 0;
++ spi->msg_rd_ptr = 0;
++ spi->msg->flags = 0;
++ spi->msg = NULL;
++ spi->msg_idx ++;
++ spi->msg_num = 0;
++
++ writel(0xff, spi->regs + S3C_PENDING_CLR);
++
++
++ if (ret)
++ spi->msg_idx = ret;
++}
++
++static int s3c_spi_done(struct s3c_spi *spi)
++{
++ u32 spi_clkcfg;
++ DEBUG;
++
++ spi_clkcfg = readl( spi->regs + S3C_CLK_CFG);
++ spi_clkcfg &= SPI_ENCLK_DISABLE;
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ return 0;
++
++}
++
++static inline void s3c_spi_stop(struct s3c_spi *spi, int ret)
++{
++ DEBUG;
++
++ writel(0x0, spi->regs + S3C_SPI_INT_EN);
++ writel(0x1f, spi->regs + S3C_PENDING_CLR);
++ writel(0x0, spi->regs + S3C_CH_CFG);
++
++ s3c_spi_done(spi);
++ spi->state = STATE_IDLE;
++ s3c_spi_master_complete(spi, ret);
++ print_reg(spi);
++ up(&spi->sem);
++}
++
++void s3c_spi_dma_cb(struct s3c2410_dma_chan *dma_ch, void *buf_id,
++ int size, enum s3c2410_dma_buffresult result)
++{
++ struct s3c_spi *spi = (struct s3c_spi *)buf_id;
++ unsigned long status = 0;
++ DEBUG;
++
++ status = readl(spi->regs + S3C_SPI_STATUS);
++
++ pr_debug("DMA call back\n");
++
++ if (spi->msg->wbuf)
++ while (!(readl(spi->regs +S3C_SPI_STATUS) & SPI_STUS_TX_DONE)) {}
++
++ s3c_spi_stop(spi, status);
++}
++
++/* s3c_spi_message_start
++ *
++ * configure the spi controler and transmit start of a message onto the bus
++*/
++static void s3c_spi_message_start(struct s3c_spi *spi)
++{
++ struct spi_msg *msg = spi->msg;
++
++ u32 spi_chcfg = 0, spi_slavecfg, spi_inten= 0, spi_packet=0;
++
++ u8 prescaler = 1;
++ u32 spi_clkcfg = 0, spi_modecfg = 0 ;
++
++ DEBUG;
++
++ /* initialise the spi controller */
++ s3c_spi_hw_init(spi);
++
++ /* 1. Set transfer type (CPOL & CPHA set) */
++ spi_chcfg = SPI_CH_RISING | SPI_CH_FORMAT_A;
++
++ if (spi->msg->flags & SPI_M_MODE_MASTER) {
++ spi_chcfg |= SPI_CH_MASTER;
++ } else if(spi->msg->flags & SPI_M_MODE_SLAVE){
++ spi_chcfg |= SPI_CH_SLAVE;
++ }
++
++ writel( spi_chcfg , spi->regs + S3C_CH_CFG);
++
++ /* 2. Set clock configuration register */
++ spi_clkcfg = SPI_ENCLK_ENABLE;
++
++#if defined CONFIG_SPICLK_PCLK
++ spi_clkcfg |= SPI_CLKSEL_PCLK;
++#elif defined CONFIG_SPICLK_EPLL
++ spi_clkcfg |= SPI_CLKSEL_ECLK;
++#else
++#error you must define correct confige file.
++#endif
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ spi_clkcfg = readl( spi->regs + S3C_CLK_CFG);
++
++ /* SPI clockout = clock source / (2 * (prescaler +1)) */
++ spi_clkcfg |= prescaler;
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ /* 3. Set SPI MODE configuration register */
++#ifdef CONFIG_WORD_TRANSIZE
++ spi_modecfg = SPI_MODE_CH_TSZ_WORD;
++#else
++ spi_modecfg = SPI_MODE_CH_TSZ_BYTE;
++#endif
++ spi_modecfg |= SPI_MODE_TXDMA_OFF| SPI_MODE_SINGLE| SPI_MODE_RXDMA_OFF;
++
++ if (msg->flags & SPI_M_DMA_MODE) {
++ spi_modecfg |= SPI_MODE_TXDMA_ON| SPI_MODE_RXDMA_ON;
++ }
++
++ if (msg->wbuf)
++ spi_modecfg |= ( 0x3f << 5); /* Tx FIFO trigger level in INT mode */
++ if (msg->rbuf)
++ spi_modecfg |= ( 0x3f << 11); /* Rx FIFO trigger level in INT mode */
++
++ spi_modecfg |= ( 0x3ff << 19);
++ writel(spi_modecfg, spi->regs + S3C_MODE_CFG);
++
++ /* 4. Set SPI INT_EN register */
++
++ if (msg->wbuf)
++ spi_inten = SPI_INT_TX_FIFORDY_EN|SPI_INT_TX_UNDERRUN_EN|SPI_INT_TX_OVERRUN_EN;
++ if (msg->rbuf){
++ spi_inten = SPI_INT_RX_FIFORDY_EN|SPI_INT_RX_UNDERRUN_EN|SPI_INT_RX_OVERRUN_EN|SPI_INT_TRAILING_EN;
++ }
++ writel(spi_inten, spi->regs + S3C_SPI_INT_EN);
++
++ writel(0x1f, spi->regs + S3C_PENDING_CLR);
++
++ /* 5. Set Packet Count configuration register */
++ spi_packet = SPI_PACKET_CNT_EN;
++ spi_packet |= 0xffff;
++ writel(spi_packet, spi->regs + S3C_PACKET_CNT);
++
++ /* 6. Set Tx or Rx Channel on */
++ spi_chcfg = readl(spi->regs + S3C_CH_CFG);
++
++ spi_chcfg |= SPI_CH_TXCH_OFF | SPI_CH_RXCH_OFF;
++
++ if (msg->wbuf)
++ spi_chcfg |= SPI_CH_TXCH_ON;
++ if (msg->rbuf)
++ spi_chcfg |= SPI_CH_RXCH_ON;
++
++ writel(spi_chcfg, spi->regs + S3C_CH_CFG);
++
++ if (msg->flags & SPI_M_DMA_MODE) {
++
++ if (msg->wbuf)
++ spi->dma = DMACH_SPI_TX;
++ if (msg->rbuf)
++ spi->dma = DMACH_SPI_RX;
++
++ if (s3c2410_dma_request(spi->dma, &s3c2443spi_dma_client, NULL)) {
++ printk(KERN_WARNING "unable to get DMA channel.\n" );
++ }
++
++ s3c2410_dma_set_buffdone_fn(spi->dma, s3c_spi_dma_cb);
++ s3c2410_dma_set_opfn(spi->dma, NULL);
++
++
++ if (msg->wbuf)
++ s3c_spi_dma_init(spi, 0);
++ if (msg->rbuf)
++ s3c_spi_dma_init(spi, 1);
++
++ s3c2410_dma_enqueue(spi->dma, (void *) spi, spi->dmabuf_addr, spi->msg->len);
++ }
++ /* 7. Set nSS low to start Tx or Rx operation */
++ spi_slavecfg = readl(spi->regs + S3C_SLAVE_SEL);
++ spi_slavecfg &= SPI_SLAVE_SIG_ACT;
++ writel(spi_slavecfg, spi->regs + S3C_SLAVE_SEL);
++
++ print_reg(spi);
++}
++
++/* is_msgend
++ *
++ * returns TRUE if we reached the end of the current message
++*/
++
++static inline int tx_msgend(struct s3c_spi *spi)
++{
++ return spi->msg_ptr >= spi->msg->len;
++}
++
++static inline int rx_msgend(struct s3c_spi *spi)
++{
++ return spi->msg_rd_ptr >= spi->msg->len;
++}
++
++/* spi_s3c_irq_nextbyte
++ *
++ * process an interrupt and work out what to do
++ */
++static void spi_s3c_irq_nextbyte(struct s3c_spi *spi, unsigned long spsta)
++{
++ DEBUG;
++ DBG("spi->state = %d \n",spi->state);
++ switch (spi->state) {
++ case STATE_IDLE:
++ DBG("%s: called in STATE_IDLE\n", __FUNCTION__);
++ break;
++
++ case STATE_STOP:
++ udelay(200);
++ s3c_spi_stop(spi, 0);
++ DBG("%s: called in STATE_STOP\n", __FUNCTION__);
++ break;
++
++ case STATE_XFER_TX:
++ DEBUG;
++ print_reg(spi);
++ DBG("msg_ptr = 0x%x, len = 0x%x \n", spi->msg_ptr ,spi->msg->len);
++ while(!(tx_msgend(spi)))
++ s3c_spi_write_fifo(spi);
++ DEBUG;
++ print_reg(spi);
++ spi->state = STATE_STOP;
++ break;
++ case STATE_XFER_RX:
++ DEBUG;
++ print_reg(spi);
++ DBG("msg_rd_ptr = 0x%x, len = 0x%x \n", spi->msg_rd_ptr ,spi->msg->len);
++ while(!(rx_msgend(spi))){
++ spi->msg->rbuf[spi->msg_rd_ptr++] = readl(spi->regs + S3C_SPI_RX_DATA);
++ DBG("msg_rd_ptr = 0x%x, len = 0x%x \n", spi->msg_rd_ptr ,spi->msg->len);
++ DBG("msg_rbuf = 0x%x\n", spi->msg->rbuf[spi->msg_rd_ptr - 1]);
++ }
++ DBG("msg_rd_ptr = 0x%x, len = 0x%x \n", spi->msg_rd_ptr ,spi->msg->len);
++ DEBUG;
++ print_reg(spi);
++ s3c_spi_stop(spi, 0);
++ break;
++ default:
++ dev_err(spi->dev, "%s: called with Invalid option\n", __FUNCTION__);
++ }
++
++ return;
++}
++
++/* s3c_spi_irq
++ *
++ * top level IRQ servicing routine
++*/
++static irqreturn_t s3c_spi_irq(int irqno, void *dev_id)
++{
++ struct s3c_spi *spi = dev_id;
++ unsigned long spi_sts;
++
++ spi_sts = readl(spi->regs + S3C_SPI_STATUS);
++
++ if (spi_sts & SPI_STUS_RX_OVERRUN_ERR) {
++ printk("hspi : Rx overrun error detected\n");
++ }
++
++ if (spi_sts & SPI_STUS_RX_UNDERRUN_ERR) {
++ printk("hspi : Rx underrun error detected\n");
++ }
++
++ if (spi_sts & SPI_STUS_TX_OVERRUN_ERR) {
++ printk("hspi : Tx overrun error detected\n");
++ }
++
++ if (spi_sts & SPI_STUS_TX_UNDERRUN_ERR) {
++ printk("hspi : Tx underrun error detected\n");
++ }
++
++ /* pretty much this leaves us with the fact that we've
++ * transmitted or received whatever byte we last sent */
++ spi_s3c_irq_nextbyte(spi, spi_sts);
++
++ return IRQ_HANDLED;
++}
++
++static int s3c_spi_doxfer(struct s3c_spi *spi, struct spi_msg msgs[], int num)
++{
++ int ret;
++
++ spin_lock_irq(&spi->lock);
++
++ spi->msg = msgs;
++ spi->msg_num = num;
++ spi->msg_ptr = 0;
++ spi->msg_rd_ptr = 0;
++ spi->msg_idx = 0;
++
++ if (spi->msg->flags & SPI_M_DMA_MODE) {
++ spi->dmabuf_addr = spi->spidev.dmabuf;
++ pr_debug("spi->dmabuf_addr = 0x%x\n",spi->dmabuf_addr);
++ }
++
++ if (spi->msg->wbuf) {
++ DEBUG;
++ spi->state = STATE_XFER_TX;
++ } else if (spi->msg->rbuf) {
++ DEBUG;
++ spi->state = STATE_XFER_RX;
++ } else {
++ dev_err(spi->dev,"Unknown functionality \n");
++ return -ESRCH;
++ }
++ s3c_spi_message_start(spi);
++ DEBUG;
++
++ if (down_interruptible(&spi->sem))
++ return -EINTR;
++
++ DEBUG;
++ spin_unlock_irq(&spi->lock);
++
++ DEBUG;
++ ret = spi->msg_idx;
++
++ return ret;
++}
++
++
++/* s3c_spi_xfer
++ *
++ * first port of call from the spi bus code when an message needs
++ * transfering across the spi bus.
++*/
++static int s3c_spi_xfer(struct spi_dev *spi_dev,
++ struct spi_msg msgs[], int num)
++{
++ struct s3c_spi *spi = (struct s3c_spi *)spi_dev->algo_data;
++ int retry;
++ int ret;
++
++ for (retry = 0; retry < spi_dev->retries; retry++) {
++
++ ret = s3c_spi_doxfer(spi, msgs, num);
++
++ print_reg(spi);
++ if (ret != -EAGAIN)
++ return ret;
++ printk("Retrying transmission (%d)\n", retry);
++
++ udelay(100);
++ }
++
++ DEBUG;
++ return -EREMOTEIO;
++}
++
++static int s3c_spi_close(struct spi_dev *spi_dev)
++{
++ struct s3c_spi *spi = (struct s3c_spi *)spi_dev->algo_data;
++ u32 spi_clkcfg;
++ DEBUG;
++
++ spi_clkcfg = readl( spi->regs + S3C_CLK_CFG);
++ spi_clkcfg &= SPI_ENCLK_DISABLE;
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ /* Buffer Clear after finish xfer */
++ writel( 0x20, spi->regs + S3C_CH_CFG);
++ writel( 0x0, spi->regs + S3C_CH_CFG);
++
++ return 0;
++
++}
++
++
++/* spi bus registration info */
++
++static struct spi_algorithm s3c_spi_algorithm = {
++ .name = "S3C2443-spi-algorithm",
++ .master_xfer = s3c_spi_xfer,
++ .close = s3c_spi_close,
++};
++
++static struct s3c_spi s3c_spi[2] = {
++ [0] = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .spidev = {
++ .algo = &s3c_spi_algorithm,
++ .retries = 2,
++ .timeout = 5,
++ }
++ },
++ [1] = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .spidev = {
++ .algo = &s3c_spi_algorithm,
++ .retries = 2,
++ .timeout = 5,
++ }
++ },
++};
++
++
++/* s3c_spi_probe
++ *
++ * called by the bus driver when a suitable device is found
++*/
++
++static int s3c_spi_probe(struct platform_device *pdev)
++{
++ struct s3c_spi *spi = &s3c_spi[pdev->id];
++ struct resource *res;
++ int ret;
++
++ /* find the clock and enable it */
++ sema_init(&spi->sem, 0);
++ spi->nr = pdev->id;
++ spi->dev = &pdev->dev;
++
++ spi->clk = clk_get(&pdev->dev, "spi");
++
++ if (IS_ERR(spi->clk)) {
++ dev_err(&pdev->dev, "cannot get clock\n");
++ ret = -ENOENT;
++ goto out;
++ }
++
++ /* map the registers */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (res == NULL) {
++ dev_err(&pdev->dev, "cannot find IO resource\n");
++ ret = -ENOENT;
++ goto out;
++ }
++
++ spi->ioarea = request_mem_region(res->start, (res->end - res->start) + 1, pdev->name);
++
++ if (spi->ioarea == NULL) {
++ dev_err(&pdev->dev, "cannot request IO\n");
++ ret = -ENXIO;
++ goto out;
++ }
++
++ printk(KERN_ALERT "resource start : %x\n",res->start);
++
++ spi->regs = ioremap(res->start, (res->end - res->start) + 1);
++
++ if (spi->regs == NULL) {
++ dev_err(&pdev->dev, "cannot map IO\n");
++ ret = -ENXIO;
++ goto out;
++ }
++
++ printk(KERN_ALERT "hspi registers %p (%p, %p)\n", spi->regs, spi->ioarea, res);
++
++ /* setup info block for the spi core */
++
++ spi->spidev.algo_data = spi;
++ spi->spidev.dev.parent = &pdev->dev;
++ spi->spidev.minor = spi->nr;
++ init_MUTEX(&spi->spidev.bus_lock);
++
++ /* find the IRQ for this unit (note, this relies on the init call to
++ * ensure no current IRQs pending
++ */
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++
++ if (res == NULL) {
++ printk("hspi cannot find IRQ\n");
++ ret = -ENOENT;
++ goto out;
++ }
++
++ ret = request_irq(res->start, s3c_spi_irq, SA_INTERRUPT,
++ pdev->name, spi);
++
++ if (ret != 0) {
++ printk("hspi cannot claim IRQ\n");
++ goto out;
++ }
++
++ ret = spi_attach_spidev(&spi->spidev);
++
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to add adapter to spi core\n");
++ goto out;
++ }
++
++ dev_set_drvdata(&pdev->dev, spi);
++
++ dev_info(&pdev->dev, "%s: S3C SPI adapter\n", spi->dev->bus_id);
++
++ printk("%s: S3C SPI adapter\n", spi->dev->bus_id);
++
++out:
++ if (ret < 0)
++ s3c_spi_free(spi);
++
++ return ret;
++}
++
++/* s3c_spi_remove
++ *
++ * called when device is removed from the bus
++*/
++static int s3c_spi_remove(struct platform_device *pdev)
++{
++ struct s3c_spi *spi = dev_get_drvdata(&pdev->dev);
++
++ DEBUG;
++
++ if (spi != NULL) {
++ spi_detach_spidev(&spi->spidev);
++ s3c_spi_free(spi);
++ dev_set_drvdata(&pdev->dev, NULL);
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_spi_suspend(struct platform_device *pdev, pm_message_t msg)
++{
++ struct s3c_spi *hw = platform_get_drvdata(pdev);
++ clk_disable(hw->clk);
++ return 0;
++}
++
++static int s3c_spi_resume(struct platform_device *pdev)
++{
++ struct s3c_spi *hw = platform_get_drvdata(pdev);
++ clk_enable(hw->clk);
++ return 0;
++}
++#else
++#define s3c_spi_suspend NULL
++#define s3c_spi_resume NULL
++#endif
++
++/* device driver for platform bus bits */
++static struct platform_driver s3c_spi_driver = {
++ .probe = s3c_spi_probe,
++ .remove = s3c_spi_remove,
++#ifdef CONFIG_PM
++ .suspend = s3c_spi_suspend,
++ .resume = s3c_spi_resume,
++#endif
++ .driver = {
++ .name = "s3c2410-spi",
++ .owner = THIS_MODULE,
++ .bus = &platform_bus_type,
++ },
++};
++
++static int __init s3c_spi_driver_init(void)
++{
++ printk(KERN_INFO "S3C2443 HSPI Driver \n");
++
++ return platform_driver_register(&s3c_spi_driver);
++}
++
++static void __exit s3c_spi_driver_exit(void)
++{
++ platform_driver_unregister(&s3c_spi_driver);
++}
++
++module_init(s3c_spi_driver_init);
++module_exit(s3c_spi_driver_exit);
++
++MODULE_DESCRIPTION("S3C2443 SPI Bus driver");
++MODULE_AUTHOR("Ryu Euiyoul<steven.ryu@samsung.com>");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/spi/hspi-s3c24xx.h b/drivers/spi/hspi-s3c24xx.h
+new file mode 100644
+index 0000000..66c7094
+--- /dev/null
++++ b/drivers/spi/hspi-s3c24xx.h
+@@ -0,0 +1,95 @@
++/* ------------------------------------------------------------------------- */
++/* */
++/* spi-s3c6400.h - definitions of s3c6400 specific spi interface */
++/* */
++/* ------------------------------------------------------------------------- */
++/* Copyright (C) 2006 Samsung Electronics Co. ltd.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
++/* ------------------------------------------------------------------------- */
++
++#ifndef _S3C2443_SPI_H
++#define _S3C2443_SPI_H
++
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++
++#define S3C_DCON_HANDSHAKE (1<<31)
++#define S3C_DCON_SYNC_PCLK (0<<30)
++
++//#define SPI_CHANNEL 1
++
++#if(SPI_CHANNEL==0)
++/* SPI CHANNEL 0 */
++#define S3C_SPI_TX_DATA_REG 0x52000018 //SPI TX data
++#define S3C_SPI_RX_DATA_REG 0x5200001C //SPI RX data
++#else
++/* SPI CHANNEL 1 */
++#define S3C_SPI_TX_DATA_REG 0x59000018 //SPI TX data
++#define S3C_SPI_RX_DATA_REG 0x5900001C //SPI RX data
++#endif
++
++/* DMA transfer unit (byte). */
++#define S3C_DMA_XFER_BYTE 1
++#define S3C_DMA_XFER_WORD 4
++
++/* DMA configuration setup byte. */
++#define S3C_DCON_SPI1 (S3C_DCON_HANDSHAKE | S3C_DCON_SYNC_PCLK)
++
++/* DMA hardware configuration mode (DISRCC register). */
++#define S3C_SPI1_DMA_HWCFG 3
++#define S3C_SPI_DMA_HWCFG 3
++
++#define DMA_BUFFER_SIZE 1500
++
++/* spi controller state */
++int req_dma_flag = 1;
++enum s3c_spi_state {
++ STATE_IDLE,
++ STATE_XFER_TX,
++ STATE_XFER_RX,
++ STATE_STOP
++};
++
++static struct s3c2410_dma_client s3c2443spi_dma_client = {
++ .name = "s3c2443-spi-dma",
++};
++
++struct s3c_spi {
++ spinlock_t lock;
++ struct semaphore sem;
++ int nr;
++ int dma;
++ u_int subchannel;/* user fragment index */
++ dma_addr_t dmabuf_addr;
++
++ struct spi_msg *msg;
++ unsigned int msg_num;
++ unsigned int msg_idx;
++ unsigned int msg_ptr;
++ unsigned int msg_rd_ptr;
++
++ enum s3c_spi_state state;
++
++ void __iomem *regs;
++ struct clk *clk;
++ struct device *dev;
++ struct resource *irq;
++ struct resource *ioarea;
++ struct spi_dev spidev;
++};
++
++
++#endif /* _S3C6400_SPI_H */
+diff --git a/drivers/spi/hspi-s3c64xx.c b/drivers/spi/hspi-s3c64xx.c
+new file mode 100644
+index 0000000..6407a8b
+--- /dev/null
++++ b/drivers/spi/hspi-s3c64xx.c
+@@ -0,0 +1,789 @@
++/* spi-s3c6400.c
++ *
++ * Copyright (C) 2006 Samsung Electronics Co. Ltd.
++ *
++ * S3C6400 SPI Controller
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/time.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/err.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include <asm/arch-s3c2410/regs-s3c-clock.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/plat-s3c24xx/regs-spi.h>
++#include <asm/dma.h>
++
++#include "spi-dev.h"
++#include "hspi-s3c64xx.h"
++
++//#define S3C_SPI_DEBUG
++
++#ifdef S3C_SPI_DEBUG
++#define DBG(x...) printk(x)
++#define DEBUG printk("%s :: %d\n",__FUNCTION__,__LINE__)
++void print_reg(struct s3c_spi *spi)
++{
++ printk("CH_CFG = 0x%08x\n",readl(spi->regs + S3C_CH_CFG));
++ printk("CLK_CFG = 0x%08x\n",readl(spi->regs + S3C_CLK_CFG));
++ printk("MODE_CFG = 0x%08x\n",readl(spi->regs + S3C_MODE_CFG));
++ printk("SLAVE_CFG = 0x%08x\n",readl(spi->regs + S3C_SLAVE_SEL));
++ printk("INT_EN = 0x%08x\n",readl(spi->regs + S3C_SPI_INT_EN));
++ printk("SPI_STATUS = 0x%08x\n",readl(spi->regs + S3C_SPI_STATUS));
++ printk("PACKET_CNT = 0x%08x\n",readl(spi->regs + S3C_PACKET_CNT));
++ printk("PEND_CLR = 0x%08x\n",readl(spi->regs + S3C_PENDING_CLR));
++ printk("SWAP_CFG = 0x%08x\n",readl(spi->regs + S3C_SWAP_CFG));
++ printk("FB_CLK = 0x%08x\n",readl(spi->regs + S3C_FB_CLK));
++}
++#else
++#define DEBUG
++#define DBG(x...) do { } while (0)
++void print_reg(struct s3c_spi *spi)
++{
++}
++#endif
++
++static void s3c_spi_free(struct s3c_spi *spi)
++{
++ if (spi->clk != NULL && !IS_ERR(spi->clk)) {
++ clk_disable(spi->clk);
++ clk_put(spi->clk);
++ spi->clk = NULL;
++ }
++
++ if (spi->regs != NULL) {
++ iounmap(spi->regs);
++ spi->regs = NULL;
++ }
++
++ if (spi->ioarea != NULL) {
++ release_resource(spi->ioarea);
++ kfree(spi->ioarea);
++ spi->ioarea = NULL;
++ }
++}
++
++static int s3c_spi_hw_init(struct s3c_spi *spi)
++{
++
++ unsigned int s3c_spcon;
++
++#ifdef CONFIG_SPICLK_PCLK
++ clk_enable(spi->clk);
++#elif defined (CONFIG_SPICLK_EPLL)
++ writel((readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_SPI0|S3C_CLKCON_PCLK_SPI1),S3C_PCLK_GATE);
++ writel((readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_SPI0|S3C_CLKCON_SCLK_SPI1),S3C_SCLK_GATE);
++
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_MPLL_CLKSEL, S3C_CLK_SRC);
++
++ /* Set SPi Clock to MOUT(266Mhz)*/
++ if(SPI_CHANNEL == 0)
++ writel((readl(S3C_CLK_SRC)&~(0x3<<14))|(1<<14), S3C_CLK_SRC);
++ else /* SPI_CHANNEL = 1 */
++ writel((readl(S3C_CLK_SRC)&~(0x3<<16))|(1<<16), S3C_CLK_SRC);
++
++ /* CLK_DIV2 setting */
++ /* SPI Input Clock(88.87Mhz) = 266.66Mhz / (2 + 1)*/
++ writel(((readl(S3C_CLK_DIV2) & ~(0xff << 0)) | 2) , S3C_CLK_DIV2);
++
++#elif defined (CONFIG_SPICLK_USBCLK)
++ writel((readl(S3C_PCLK_GATE)| S3C_CLKCON_PCLK_SPI0|S3C_CLKCON_PCLK_SPI1),S3C_PCLK_GATE);
++ writel((readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_SPI0_48|S3C_CLKCON_SCLK_SPI1_48),S3C_SCLK_GATE);
++#endif
++
++ /* initialize the gpio */
++ if (SPI_CHANNEL == 0) {
++
++ gpio_set_pin(S3C_GPC0, S3C_GPC0_SPI_MISO0);
++ gpio_set_pin(S3C_GPC1, S3C_GPC1_SPI_CLK0);
++ gpio_set_pin(S3C_GPC2, S3C_GPC2_SPI_MOSI0);
++ gpio_set_pin(S3C_GPC3, S3C_GPC3_SPI_CS0);
++
++ gpio_pullup(S3C_GPC0, 1);
++ gpio_pullup(S3C_GPC1, 1);
++ gpio_pullup(S3C_GPC2, 1);
++ gpio_pullup(S3C_GPC3, 1);
++
++ } else {
++
++ gpio_set_pin(S3C_GPC4, S3C_GPC4_SPI_MISO1);
++ gpio_set_pin(S3C_GPC5, S3C_GPC5_SPI_CLK1);
++ gpio_set_pin(S3C_GPC6, S3C_GPC6_SPI_MOSI1);
++ gpio_set_pin(S3C_GPC7, S3C_GPC7_SPI_CS1);
++
++ gpio_pullup(S3C_GPC4, 1);
++ gpio_pullup(S3C_GPC5, 1);
++ gpio_pullup(S3C_GPC6, 1);
++ gpio_pullup(S3C_GPC7, 1);
++ }
++
++ /* SPI drive strength */
++ s3c_spcon = readl(S3C_SPCON);
++ writel((s3c_spcon & ~(3<<28)) | (1<<28), S3C_SPCON);
++
++ return 0;
++}
++
++static int s3c_spi_dma_init(struct s3c_spi *spi, int mode)
++{
++ // TX
++ if (mode == 0) {
++ if(SPI_CHANNEL == 0)
++ s3c2410_dma_devconfig(spi->subchannel, S3C2410_DMASRC_MEM, 0, S3C_SPI_TX_DATA_REG);
++ else // SPI_CHANNEL = 1
++ s3c2410_dma_devconfig(spi->subchannel, S3C2410_DMASRC_MEM, 0, S3C_SPI_TX_DATA_REG);
++
++ }
++
++ // RX
++ if (mode == 1) {
++ if(SPI_CHANNEL == 0)
++ s3c2410_dma_devconfig(spi->subchannel, S3C2410_DMASRC_HW, 0, S3C_SPI_RX_DATA_REG);
++ else // SPI_CHANNEL = 1
++ s3c2410_dma_devconfig(spi->subchannel, S3C2410_DMASRC_HW, 0, S3C_SPI_RX_DATA_REG);
++
++ }
++
++#ifdef CONFIG_WORD_TRANSIZE
++ s3c2410_dma_config(spi->subchannel, S3C_DMA_XFER_WORD, S3C_DMA_XFER_WORD);
++#else
++ s3c2410_dma_config(spi->subchannel, S3C_DMA_XFER_BYTE, S3C_DMA_XFER_BYTE);
++#endif
++ s3c2410_dma_setflags(spi->subchannel, S3C2410_DMAF_AUTOSTART);
++
++ return 0;
++}
++
++static inline void s3c_spi_write_fifo(struct s3c_spi *spi)
++{
++ u32 wdata = 0;
++
++ if (spi->msg->wbuf){
++ wdata = spi->msg->wbuf[spi->msg_ptr++];
++ } else {
++ spi->msg_ptr++;
++ wdata = 0xff;
++ }
++
++ DBG("wdata = %x\n",wdata);
++ writel(wdata, spi->regs + S3C_SPI_TX_DATA);
++}
++
++/* s3c_spi_master_complete
++ *
++ * complete the message and wake up the caller, using the given return code,
++ * or zero to mean ok.
++*/
++static inline void s3c_spi_master_complete(struct s3c_spi *spi, int ret)
++{
++ spi->msg_ptr = 0;
++ spi->msg_rd_ptr = 0;
++ spi->msg->flags = 0;
++ spi->msg = NULL;
++ spi->msg_idx ++;
++ spi->msg_num = 0;
++
++ writel(0xff, spi->regs + S3C_PENDING_CLR);
++
++ if (ret)
++ spi->msg_idx = ret;
++}
++
++static int s3c_spi_done(struct s3c_spi *spi)
++{
++ u32 spi_clkcfg;
++
++ /* initialize the gpio */
++ if(SPI_CHANNEL == 0) {
++ gpio_direction_input(S3C_GPC0);
++ gpio_direction_input(S3C_GPC1);
++ gpio_direction_input(S3C_GPC2);
++ gpio_direction_input(S3C_GPC3);
++
++ } else {
++ gpio_direction_input(S3C_GPC4);
++ gpio_direction_input(S3C_GPC5);
++ gpio_direction_input(S3C_GPC6);
++ gpio_direction_input(S3C_GPC7);
++ }
++ spi_clkcfg = readl( spi->regs + S3C_CLK_CFG);
++ spi_clkcfg &= SPI_ENCLK_DISABLE;
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ return 0;
++
++}
++
++static inline void s3c_spi_stop(struct s3c_spi *spi, int ret)
++{
++ writel(0x0, spi->regs + S3C_SPI_INT_EN);
++ writel(0x1f, spi->regs + S3C_PENDING_CLR);
++ writel(0x0, spi->regs + S3C_CH_CFG);
++
++ s3c_spi_done(spi);
++ spi->state = STATE_IDLE;
++ s3c_spi_master_complete(spi, ret);
++ print_reg(spi);
++ up(&spi->sem);
++}
++
++void s3c_spi_dma_cb(struct s3c2410_dma_chan *dma_ch, void *buf_id,
++ int size, enum s3c2410_dma_buffresult result)
++{
++ struct s3c_spi *spi = (struct s3c_spi *)buf_id;
++ unsigned long status = 0;
++
++ status = readl(spi->regs + S3C_SPI_STATUS);
++
++ pr_debug("DMA call back\n");
++
++ if (spi->msg->wbuf)
++ while (!(readl(spi->regs +S3C_SPI_STATUS) & SPI_STUS_TX_DONE)) {}
++
++ //s3c_spi_stop(spi, status);
++ s3c_spi_stop(spi, 0);
++}
++
++/* s3c_spi_message_start
++ *
++ * configure the spi controler and transmit start of a message onto the bus
++*/
++static void s3c_spi_message_start(struct s3c_spi *spi)
++{
++ struct spi_msg *msg = spi->msg;
++
++ u32 spi_chcfg = 0, spi_slavecfg, spi_inten= 0, spi_packet=0;
++
++// u8 prescaler = 0; // 44.435 Mhz
++ u8 prescaler = 1; // 22.2175 Mhz
++// u8 prescaler = 2; // 14.81 Mhz
++// u8 prescaler = 3; // 11.10875 Mhz
++// u8 prescaler = 4; // 8.887Mhz
++
++ u32 spi_clkcfg = 0, spi_modecfg = 0 ;
++
++ /* initialise the spi controller */
++ s3c_spi_hw_init(spi);
++
++ /* 1. Set transfer type (CPOL & CPHA set) */
++ spi_chcfg = SPI_CH_RISING | SPI_CH_FORMAT_A;
++
++ if (spi->msg->flags & SPI_M_MODE_MASTER) {
++ spi_chcfg |= SPI_CH_MASTER;
++ } else if(spi->msg->flags & SPI_M_MODE_SLAVE){
++ spi_chcfg |= SPI_CH_SLAVE;
++ }
++
++ writel( spi_chcfg , spi->regs + S3C_CH_CFG);
++
++ /* 2. Set clock configuration register */
++ spi_clkcfg = SPI_ENCLK_ENABLE;
++
++#if defined CONFIG_SPICLK_PCLK
++ spi_clkcfg |= SPI_CLKSEL_PCLK;
++#elif defined CONFIG_SPICLK_EPLL
++ spi_clkcfg |= SPI_CLKSEL_ECLK;
++#elif defined CONFIG_SPICLK_USBCLK
++ spi_clkcfg |= SPI_CLKSEL_USBCLK;
++#endif
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ spi_clkcfg = readl( spi->regs + S3C_CLK_CFG);
++
++ /* SPI clockout = clock source / (2 * (prescaler +1)) */
++ spi_clkcfg |= prescaler;
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ /* 3. Set SPI MODE configuration register */
++#ifdef CONFIG_WORD_TRANSIZE
++ spi_modecfg = SPI_MODE_CH_TSZ_WORD| SPI_MODE_BUS_TSZ_WORD;
++#else
++ spi_modecfg = SPI_MODE_CH_TSZ_BYTE| SPI_MODE_BUS_TSZ_BYTE;
++#endif
++ spi_modecfg |= SPI_MODE_TXDMA_OFF| SPI_MODE_SINGLE| SPI_MODE_RXDMA_OFF;
++
++ if (msg->flags & SPI_M_DMA_MODE) {
++ spi_modecfg |= SPI_MODE_TXDMA_ON| SPI_MODE_RXDMA_ON;
++ }
++
++ if (msg->wbuf)
++ spi_modecfg |= ( 0x3f << 5); /* Tx FIFO trigger level in INT mode */
++ if (msg->rbuf)
++ spi_modecfg |= ( 0x3f << 11); /* Rx FIFO trigger level in INT mode */
++
++ spi_modecfg |= ( 0x3ff << 19);
++ writel(spi_modecfg, spi->regs + S3C_MODE_CFG);
++
++ /* 4. Set SPI INT_EN register */
++
++ if (msg->wbuf)
++ spi_inten = SPI_INT_TX_FIFORDY_EN|SPI_INT_TX_UNDERRUN_EN|SPI_INT_TX_OVERRUN_EN;
++ if (msg->rbuf){
++ spi_inten = SPI_INT_RX_FIFORDY_EN|SPI_INT_RX_UNDERRUN_EN|SPI_INT_RX_OVERRUN_EN|SPI_INT_TRAILING_EN ;
++ }
++ writel(spi_inten, spi->regs + S3C_SPI_INT_EN);
++
++ writel(0x1f, spi->regs + S3C_PENDING_CLR);
++
++ /* 5. Set Packet Count configuration register */
++ spi_packet = SPI_PACKET_CNT_EN;
++ spi_packet |= 0xffff;
++ writel(spi_packet, spi->regs + S3C_PACKET_CNT);
++
++ if (msg->flags & SPI_M_DMA_MODE) {
++ spi->dma = S3C_SPI_DMA;
++
++ if (msg->wbuf)
++ spi->subchannel = DMACH_SPI0_OUT;
++ if (msg->rbuf)
++ spi->subchannel = DMACH_SPI0_IN;
++
++ if (s3c2410_dma_request(spi->subchannel, &s3c6400spi_dma_client, NULL)) {
++ printk(KERN_WARNING "unable to get DMA channel.\n" );
++ }
++
++ s3c2410_dma_set_buffdone_fn(spi->subchannel, s3c_spi_dma_cb);
++ s3c2410_dma_set_opfn(spi->subchannel, NULL);
++
++
++ if (msg->wbuf)
++ s3c_spi_dma_init(spi, 0);
++ if (msg->rbuf)
++ s3c_spi_dma_init(spi, 1);
++
++ s3c2410_dma_enqueue(spi->subchannel, (void *) spi, spi->dmabuf_addr, spi->msg->len);
++ }
++
++ /* 6. Set Tx or Rx Channel on */
++ spi_chcfg = readl(spi->regs + S3C_CH_CFG);
++ spi_chcfg |= SPI_CH_TXCH_OFF | SPI_CH_RXCH_OFF;
++
++ if (msg->wbuf)
++ spi_chcfg |= SPI_CH_TXCH_ON;
++ if (msg->rbuf)
++ spi_chcfg |= SPI_CH_RXCH_ON;
++
++ writel(spi_chcfg, spi->regs + S3C_CH_CFG);
++
++ /* 7. Set nSS low to start Tx or Rx operation */
++ spi_slavecfg = readl(spi->regs + S3C_SLAVE_SEL);
++ spi_slavecfg &= SPI_SLAVE_SIG_ACT;
++ spi_slavecfg |= (0x3f << 4);
++ writel(spi_slavecfg, spi->regs + S3C_SLAVE_SEL);
++
++ print_reg(spi);
++}
++
++/* is_msgend
++ *
++ * returns TRUE if we reached the end of the current message
++*/
++
++static inline int tx_msgend(struct s3c_spi *spi)
++{
++ return spi->msg_ptr >= spi->msg->len;
++}
++
++static inline int rx_msgend(struct s3c_spi *spi)
++{
++ return spi->msg_rd_ptr >= spi->msg->len;
++}
++
++/* spi_s3c_irq_nextbyte
++ *
++ * process an interrupt and work out what to do
++ */
++static void spi_s3c_irq_nextbyte(struct s3c_spi *spi, unsigned long spsta)
++{
++ DBG("spi->state = %d \n",spi->state);
++ switch (spi->state) {
++ case STATE_IDLE:
++ DBG("%s: called in STATE_IDLE\n", __FUNCTION__);
++ break;
++
++ case STATE_STOP:
++ udelay(200);
++ s3c_spi_stop(spi, 0);
++ DBG("%s: called in STATE_STOP\n", __FUNCTION__);
++ break;
++
++ case STATE_XFER_TX:
++ print_reg(spi);
++ DBG("msg_ptr = 0x%x, len = 0x%x \n", spi->msg_ptr ,spi->msg->len);
++ while(!(tx_msgend(spi)))
++ s3c_spi_write_fifo(spi);
++ print_reg(spi);
++ spi->state = STATE_STOP;
++ break;
++ case STATE_XFER_RX:
++ print_reg(spi);
++ DBG("msg_rd_ptr = 0x%x, len = 0x%x \n", spi->msg_rd_ptr ,spi->msg->len);
++ while(!(rx_msgend(spi))){
++ spi->msg->rbuf[spi->msg_rd_ptr++] = readl(spi->regs + S3C_SPI_RX_DATA);
++ DBG("msg_rd_ptr = 0x%x, len = 0x%x \n", spi->msg_rd_ptr ,spi->msg->len);
++ DBG("msg_rbuf = 0x%x\n", spi->msg->rbuf[spi->msg_rd_ptr - 1]);
++ }
++ DBG("msg_rd_ptr = 0x%x, len = 0x%x \n", spi->msg_rd_ptr ,spi->msg->len);
++ print_reg(spi);
++ s3c_spi_stop(spi, 0);
++ break;
++ default:
++ dev_err(spi->dev, "%s: called with Invalid option\n", __FUNCTION__);
++ }
++
++ return;
++}
++
++/* s3c_spi_irq
++ *
++ * top level IRQ servicing routine
++*/
++static irqreturn_t s3c_spi_irq(int irqno, void *dev_id)
++{
++ struct s3c_spi *spi = dev_id;
++ unsigned long spi_sts;
++
++ spi_sts = readl(spi->regs + S3C_SPI_STATUS);
++ if (spi_sts & SPI_STUS_RX_OVERRUN_ERR) {
++ printk("hspi : Rx overrun error detected\n");
++ }
++
++ if (spi_sts & SPI_STUS_RX_UNDERRUN_ERR) {
++ printk("hspi : Rx underrun error detected\n");
++ }
++
++ if (spi_sts & SPI_STUS_TX_OVERRUN_ERR) {
++ printk("hspi : Tx overrun error detected\n");
++ }
++
++ if (spi_sts & SPI_STUS_TX_UNDERRUN_ERR) {
++ printk("hspi : Tx underrun error detected\n");
++ }
++
++ /* pretty much this leaves us with the fact that we've
++ * transmitted or received whatever byte we last sent */
++ spi_s3c_irq_nextbyte(spi, spi_sts);
++
++ return IRQ_HANDLED;
++}
++
++static int s3c_spi_doxfer(struct s3c_spi *spi, struct spi_msg msgs[], int num)
++{
++ int ret;
++
++ spin_lock_irq(&spi->lock);
++
++ spi->msg = msgs;
++ spi->msg_num = num;
++ spi->msg_ptr = 0;
++ spi->msg_rd_ptr = 0;
++ spi->msg_idx = 0;
++
++ if (spi->msg->flags & SPI_M_DMA_MODE) {
++ spi->dmabuf_addr = spi->spidev.dmabuf;
++ pr_debug("spi->dmabuf_addr = 0x%x\n",spi->dmabuf_addr);
++ }
++
++ if (spi->msg->wbuf) {
++ spi->state = STATE_XFER_TX;
++ } else if (spi->msg->rbuf) {
++ spi->state = STATE_XFER_RX;
++ } else {
++ dev_err(spi->dev,"Unknown functionality \n");
++ return -ESRCH;
++ }
++
++ s3c_spi_message_start(spi);
++
++ if (down_interruptible(&spi->sem))
++ return -EINTR;
++
++ spin_unlock_irq(&spi->lock);
++
++ ret = spi->msg_idx;
++
++ return ret;
++}
++
++
++/* s3c_spi_xfer
++ *
++ * first port of call from the spi bus code when an message needs
++ * transfering across the spi bus.
++*/
++static int s3c_spi_xfer(struct spi_dev *spi_dev,
++ struct spi_msg msgs[], int num)
++{
++ struct s3c_spi *spi = (struct s3c_spi *)spi_dev->algo_data;
++ int retry;
++ int ret;
++
++ for (retry = 0; retry < spi_dev->retries; retry++) {
++ ret = s3c_spi_doxfer(spi, msgs, num);
++
++ print_reg(spi);
++ if (ret != -EAGAIN)
++ return ret;
++ printk("Retrying transmission (%d)\n", retry);
++
++ udelay(100);
++ }
++
++ return -EREMOTEIO;
++}
++
++static int s3c_spi_close(struct spi_dev *spi_dev)
++{
++ struct s3c_spi *spi = (struct s3c_spi *)spi_dev->algo_data;
++ u32 spi_clkcfg;
++
++ s3c2410_dma_free(spi->subchannel, &s3c6400spi_dma_client);
++
++ if(SPI_CHANNEL == 0) {
++
++ gpio_direction_input(S3C_GPC0);
++ gpio_direction_input(S3C_GPC1);
++ gpio_direction_input(S3C_GPC2);
++ gpio_direction_input(S3C_GPC3);
++
++ } else {
++
++ gpio_direction_input(S3C_GPC4);
++ gpio_direction_input(S3C_GPC5);
++ gpio_direction_input(S3C_GPC6);
++ gpio_direction_input(S3C_GPC7);
++ }
++ spi_clkcfg = readl( spi->regs + S3C_CLK_CFG);
++ spi_clkcfg &= SPI_ENCLK_DISABLE;
++ writel( spi_clkcfg , spi->regs + S3C_CLK_CFG);
++
++ /* Buffer Clear after finish xfer */
++ writel( 0x20, spi->regs + S3C_CH_CFG);
++ writel( 0x0, spi->regs + S3C_CH_CFG);
++
++ return 0;
++
++}
++
++
++/* spi bus registration info */
++static struct spi_algorithm s3c_spi_algorithm = {
++ .name = "S3C6400-spi-algorithm",
++ .master_xfer = s3c_spi_xfer,
++ .close = s3c_spi_close,
++};
++
++static struct s3c_spi s3c_spi[2] = {
++ [0] = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .spidev = {
++ .algo = &s3c_spi_algorithm,
++ .retries = 2,
++ .timeout = 5,
++ }
++ },
++ [1] = {
++ .lock = SPIN_LOCK_UNLOCKED,
++ .spidev = {
++ .algo = &s3c_spi_algorithm,
++ .retries = 2,
++ .timeout = 5,
++ }
++ },
++};
++
++
++/* s3c_spi_probe
++ *
++ * called by the bus driver when a suitable device is found
++*/
++
++static int s3c_spi_probe(struct platform_device *pdev)
++{
++ struct s3c_spi *spi = &s3c_spi[pdev->id];
++ struct resource *res;
++ int ret;
++
++ /* find the clock and enable it */
++ sema_init(&spi->sem, 0);
++ spi->nr = pdev->id;
++ spi->dev = &pdev->dev;
++
++ spi->clk = clk_get(&pdev->dev, "spi");
++
++ if (IS_ERR(spi->clk)) {
++ dev_err(&pdev->dev, "cannot get clock\n");
++ ret = -ENOENT;
++ goto out;
++ }
++
++ /* map the registers */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (res == NULL) {
++ dev_err(&pdev->dev, "cannot find IO resource\n");
++ ret = -ENOENT;
++ goto out;
++ }
++
++ spi->ioarea = request_mem_region(res->start, (res->end - res->start) + 1, pdev->name);
++
++ if (spi->ioarea == NULL) {
++ dev_err(&pdev->dev, "cannot request IO\n");
++ ret = -ENXIO;
++ goto out;
++ }
++
++ spi->regs = ioremap(res->start, (res->end - res->start) + 1);
++
++ if (spi->regs == NULL) {
++ dev_err(&pdev->dev, "cannot map IO\n");
++ ret = -ENXIO;
++ goto out;
++ }
++
++ printk("hspi registers %p (%p, %p)\n", spi->regs, spi->ioarea, res);
++
++ /* setup info block for the spi core */
++ spi->spidev.algo_data = spi;
++ spi->spidev.dev.parent = &pdev->dev;
++ spi->spidev.minor = spi->nr;
++ init_MUTEX(&spi->spidev.bus_lock);
++
++ /* find the IRQ for this unit (note, this relies on the init call to
++ * ensure no current IRQs pending
++ */
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++
++ if (res == NULL) {
++ printk("hspi cannot find IRQ\n");
++ ret = -ENOENT;
++ goto out;
++ }
++
++ ret = request_irq(res->start, s3c_spi_irq, SA_INTERRUPT,
++ pdev->name, spi);
++
++ if (ret != 0) {
++ printk("hspi cannot claim IRQ\n");
++ goto out;
++ }
++
++ printk("hspi irq resource %p (%d)\n", res, res->start);
++
++ ret = spi_attach_spidev(&spi->spidev);
++
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to add adapter to spi core\n");
++ goto out;
++ }
++
++ dev_set_drvdata(&pdev->dev, spi);
++
++ dev_info(&pdev->dev, "%s: S3C SPI adapter\n", spi->dev->bus_id);
++
++ printk("%s: S3C SPI adapter\n", spi->dev->bus_id);
++
++out:
++ if (ret < 0)
++ s3c_spi_free(spi);
++
++ return ret;
++}
++
++/* s3c_spi_remove
++ *
++ * called when device is removed from the bus
++*/
++static int s3c_spi_remove(struct platform_device *pdev)
++{
++ struct s3c_spi *spi = dev_get_drvdata(&pdev->dev);
++
++ if (spi != NULL) {
++ spi_detach_spidev(&spi->spidev);
++ s3c_spi_free(spi);
++ dev_set_drvdata(&pdev->dev, NULL);
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_spi_suspend(struct platform_device *pdev, pm_message_t msg)
++{
++ struct s3c_spi *hw = platform_get_drvdata(pdev);
++ clk_disable(hw->clk);
++ return 0;
++}
++
++static int s3c_spi_resume(struct platform_device *pdev)
++{
++ struct s3c_spi *hw = platform_get_drvdata(pdev);
++ clk_enable(hw->clk);
++ return 0;
++}
++#else
++#define s3c_spi_suspend NULL
++#define s3c_spi_resume NULL
++#endif
++
++/* device driver for platform bus bits */
++static struct platform_driver s3c_spi_driver = {
++ .probe = s3c_spi_probe,
++ .remove = s3c_spi_remove,
++#ifdef CONFIG_PM
++ .suspend = s3c_spi_suspend,
++ .resume = s3c_spi_resume,
++#endif
++ .driver = {
++ .name = "s3c2410-spi",
++ .owner = THIS_MODULE,
++ .bus = &platform_bus_type,
++ },
++};
++
++static int __init s3c_spi_driver_init(void)
++{
++ printk(KERN_INFO "S3C64XX SPI Driver \n");
++
++ return platform_driver_register(&s3c_spi_driver);
++}
++
++static void __exit s3c_spi_driver_exit(void)
++{
++ platform_driver_unregister(&s3c_spi_driver);
++}
++
++module_init(s3c_spi_driver_init);
++module_exit(s3c_spi_driver_exit);
++
++MODULE_DESCRIPTION("S3C64XX SPI Bus driver");
++MODULE_AUTHOR("Jongpill Lee<boyko.lee@samsung.com>");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/spi/hspi-s3c64xx.h b/drivers/spi/hspi-s3c64xx.h
+new file mode 100644
+index 0000000..8ecda6d
+--- /dev/null
++++ b/drivers/spi/hspi-s3c64xx.h
+@@ -0,0 +1,95 @@
++/* ------------------------------------------------------------------------- */
++/* */
++/* spi-s3c6400.h - definitions of s3c6400 specific spi interface */
++/* */
++/* ------------------------------------------------------------------------- */
++/* Copyright (C) 2006 Samsung Electronics Co. ltd.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
++/* ------------------------------------------------------------------------- */
++
++#ifndef _S3C6400_SPI_H
++#define _S3C6400_SPI_H
++
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++
++//#define SPI_CHANNEL 1
++
++#if(SPI_CHANNEL==0)
++/* SPI CHANNEL 0 */
++#define S3C_SPI_TX_DATA_REG 0x7F00B018 //SPI TX data
++#define S3C_SPI_RX_DATA_REG 0x7F00B01C //SPI RX data
++#else
++/* SPI CHANNEL 1 */
++#define S3C_SPI_TX_DATA_REG 0x7F00C018 //SPI TX data
++#define S3C_SPI_RX_DATA_REG 0x7F00C01C //SPI RX data
++#endif
++
++/* DMA channel to be used for the SPI interface. */
++#define S3C_SPI_DMA 0
++
++/* DMA transfer unit (byte). */
++#define S3C_DMA_XFER_BYTE 1
++#define S3C_DMA_XFER_WORD 4
++
++/* DMA configuration setup byte. */
++#define S3C_DCON_SPI1 (S3C_DCON_HANDSHAKE | S3C_DCON_SYNC_PCLK)
++
++/* DMA hardware configuration mode (DISRCC register). */
++#define S3C_SPI1_DMA_HWCFG 3
++#define S3C_SPI_DMA_HWCFG 3
++
++#define DMA_BUFFER_SIZE 1500
++
++/* spi controller state */
++int req_dma_flag = 1;
++enum s3c_spi_state {
++ STATE_IDLE,
++ STATE_XFER_TX,
++ STATE_XFER_RX,
++ STATE_STOP
++};
++
++static struct s3c2410_dma_client s3c6400spi_dma_client = {
++ .name = "s3c6400-spi-dma",
++};
++
++struct s3c_spi {
++ spinlock_t lock;
++ struct semaphore sem;
++ int nr;
++ int dma;
++ u_int subchannel;/* user fragment index */
++ dma_addr_t dmabuf_addr;
++
++ struct spi_msg *msg;
++ unsigned int msg_num;
++ unsigned int msg_idx;
++ unsigned int msg_ptr;
++ unsigned int msg_rd_ptr;
++
++ enum s3c_spi_state state;
++
++ void __iomem *regs;
++ struct clk *clk;
++ struct device *dev;
++ struct resource *irq;
++ struct resource *ioarea;
++ struct spi_dev spidev;
++};
++
++
++#endif /* _S3C6400_SPI_H */
+diff --git a/drivers/spi/spi-dev.c b/drivers/spi/spi-dev.c
+new file mode 100644
+index 0000000..a74a944
+--- /dev/null
++++ b/drivers/spi/spi-dev.c
+@@ -0,0 +1,379 @@
++/*
++* spi-dev.c - spi-bus driver, char device interface
++*
++* Copyright (C) 2006 Samsung Electronics Co. Ltd.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the License, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not, write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*/
++
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++//#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/smp_lock.h>
++//#include <linux/devfs_fs_kernel.h>
++#include <linux/init.h>
++#include <linux/dma-mapping.h>
++#include "spi-dev.h"
++#include <asm/uaccess.h>
++
++#undef debug
++//#define debug
++#ifdef debug
++#define CRDEBUG printk("%s :: %d\n",__FUNCTION__,__LINE__)
++#else
++#define CRDEBUG
++#endif
++
++//#define pr_debuf printk
++#define BUFFER_SIZE 65536 //8192 for perf measurement
++#define SPI_MINORS 2
++static struct spi_dev *spi_dev_array[SPI_MINORS];
++static spinlock_t (spi_dev_array_lock);
++
++static struct spi_dev *attach_to_spi_dev_array(struct spi_dev *spi_dev)
++{
++ CRDEBUG;
++ spin_lock(&spi_dev_array_lock);
++
++ if (spi_dev_array[spi_dev->minor]) {
++ spin_unlock(&spi_dev_array_lock);
++ dev_err(&spi_dev->dev, "spi-dev already has a device assigned to this adapter\n");
++ goto error;
++ }
++ spi_dev_array[spi_dev->minor] = spi_dev;
++ spin_unlock(&spi_dev_array_lock);
++ return spi_dev;
++error:
++ return ERR_PTR(-ENODEV);
++}
++
++static void return_spi_dev(struct spi_dev *spi_dev)
++{
++ CRDEBUG;
++ spin_lock(&spi_dev_array_lock);
++ spi_dev_array[spi_dev->minor] = NULL;
++ spin_unlock(&spi_dev_array_lock);
++}
++
++int spi_attach_spidev(struct spi_dev *spidev)
++{
++ struct spi_dev *spi_dev;
++
++ CRDEBUG;
++ spi_dev = attach_to_spi_dev_array(spidev);
++ if (IS_ERR(spi_dev))
++ return PTR_ERR(spi_dev);
++
++// devfs_mk_cdev(MKDEV(SPI_MAJOR, spi_dev->minor),
++// S_IFCHR|S_IRUSR|S_IWUSR, "spi/%d", spi_dev->minor);
++ dev_dbg(&spi_dev->dev, "Registered as minor %d\n", spi_dev->minor);
++
++ return 0;
++}
++
++int spi_detach_spidev(struct spi_dev *spi_dev)
++{
++ CRDEBUG;
++// devfs_remove("spi/%d", spi_dev->minor);
++ return_spi_dev(spi_dev);
++
++ dev_dbg(&spi_dev->dev, "Adapter unregistered\n");
++ return 0;
++}
++
++struct spi_dev *spi_dev_get_by_minor(unsigned index)
++{
++ struct spi_dev *spi_dev;
++
++ CRDEBUG;
++ spin_lock(&spi_dev_array_lock);
++ spi_dev = spi_dev_array[index];
++ spin_unlock(&spi_dev_array_lock);
++ return spi_dev;
++}
++
++int spi_master_recv(struct spi_dev *spi_dev, char *rbuf ,int count)
++{
++ struct spi_msg msg;
++ int ret;
++
++ CRDEBUG;
++ if (spi_dev->algo->master_xfer) {
++ msg.flags = spi_dev->flags;
++ msg.len = count;
++ msg.wbuf = NULL;
++ msg.rbuf = rbuf;
++
++ dev_dbg(&spi_dev->dev, "master_recv: reading %d bytes.\n",
++ count);
++
++ down(&spi_dev->bus_lock);
++ ret = spi_dev->algo->master_xfer(spi_dev, &msg, 1);
++ up(&spi_dev->bus_lock);
++
++ dev_dbg(&spi_dev->dev, "master_recv: return:%d (count:%d)\n",
++ ret, count);
++
++ /* if everything went ok (i.e. 1 msg transmitted), return #bytes
++ * transmitted, else error code.
++ */
++ return (ret == 1 )? count : ret;
++ } else {
++ dev_err(&spi_dev->dev, "SPI level transfers not supported\n");
++ return -ENOSYS;
++ }
++}
++
++int spi_master_send(struct spi_dev *spi_dev, char *wbuf, int count)
++{
++ int ret;
++ struct spi_msg msg;
++
++ CRDEBUG;
++ if (spi_dev->algo->master_xfer) {
++ msg.flags = spi_dev->flags;
++ msg.len = count;
++ msg.wbuf = wbuf;
++ msg.rbuf = NULL;
++
++ dev_dbg(&spi_dev->dev, "master_send: writing %d bytes.\n",
++ count);
++ down(&spi_dev->bus_lock);
++ ret = spi_dev->algo->master_xfer(spi_dev, &msg, 1);
++ up(&spi_dev->bus_lock);
++
++ /* if everything went ok (i.e. 1 msg transmitted), return #bytes
++ * transmitted, else error code.
++ */
++ return (ret == 1 )? count : ret;
++ } else {
++ dev_err(&spi_dev->dev, "SPI level transfers not supported\n");
++ return -ENOSYS;
++ }
++}
++
++static ssize_t spidev_read (struct file *file, char __user *buf, size_t count,
++ loff_t *offset)
++{
++ char *tmp;
++ int ret;
++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data;
++#ifdef CONFIG_WORD_TRANSIZE
++ count = count * 4;
++#endif
++ CRDEBUG;
++ if (count > BUFFER_SIZE)
++ count = BUFFER_SIZE;
++
++ if(spi_dev->flags & SPI_M_DMA_MODE){
++ tmp = dma_alloc_coherent(NULL, BUFFER_SIZE,
++ &spi_dev->dmabuf, GFP_KERNEL | GFP_DMA);
++ }else{
++ tmp = kmalloc(count,GFP_KERNEL);
++ }
++ if (tmp==NULL)
++ return -ENOMEM;
++
++ pr_debug("%s: tmp=0x%x dmabuf=0x%x\n",
++ __FUNCTION__,*tmp,spi_dev->dmabuf);
++ pr_debug("spi-dev: spi-%d reading %zd bytes.\n",
++ iminor(file->f_dentry->d_inode), count);
++
++ ret = spi_master_recv(spi_dev,tmp,count);
++ if (ret >= 0)
++ ret = copy_to_user(buf,tmp,count)?-EFAULT:ret;
++ if(spi_dev->flags & SPI_M_DMA_MODE){
++ dma_free_coherent(NULL,BUFFER_SIZE,tmp,spi_dev->dmabuf);
++ }else{
++ kfree(tmp);
++ }
++ return ret;
++}
++
++static ssize_t spidev_write (struct file *file, const char __user *buf, size_t count,
++ loff_t *offset)
++{
++ int ret;
++ char *tmp;
++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data;
++#ifdef CONFIG_WORD_TRANSIZE
++ count = count * 4;
++#endif
++ if (count > BUFFER_SIZE)
++ count = BUFFER_SIZE;
++ if(spi_dev->flags & SPI_M_DMA_MODE){
++ tmp = dma_alloc_coherent(NULL, BUFFER_SIZE,
++ &spi_dev->dmabuf, GFP_KERNEL | GFP_DMA);
++ }else{
++ tmp = kmalloc(count,GFP_KERNEL);
++ }
++
++ if (tmp==NULL)
++ return -ENOMEM;
++ pr_debug("%s: tmp=0x%x dmabuf=0x%x\n",
++ __FUNCTION__,*tmp,spi_dev->dmabuf);
++
++ if (copy_from_user(tmp, buf, count)) {
++ if(spi_dev->flags & SPI_M_DMA_MODE){
++ dma_free_coherent(NULL,BUFFER_SIZE,tmp,spi_dev->dmabuf);
++ }else{
++ kfree(tmp);
++ }
++ return -EFAULT;
++ }
++
++ pr_debug("spi-dev: spi-%d writing %zd bytes.\n",
++ iminor(file->f_dentry->d_inode), count);
++
++ ret = spi_master_send(spi_dev, tmp, count);
++ if(spi_dev->flags & SPI_M_DMA_MODE){
++ dma_free_coherent(NULL,BUFFER_SIZE,tmp,spi_dev->dmabuf);
++ }else{
++ kfree(tmp);
++ }
++ return ret;
++}
++
++int spidev_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
++ unsigned long arg)
++{
++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data;
++
++ CRDEBUG;
++ dev_dbg(&spi_dev->dev, "spi-%d ioctl, cmd: 0x%x, arg: %lx.\n",
++ iminor(inode),cmd, arg);
++
++ switch ( cmd ) {
++ case SET_SPI_FLAGS:
++ spi_dev->flags = (unsigned int) arg;
++ break;
++ case SET_SPI_RETRIES:
++ spi_dev->retries = arg;
++ break;
++ case SET_SPI_TIMEOUT:
++ spi_dev->timeout = arg;
++ break;
++ default:
++ printk("Invalid ioctl option\n");
++ }
++ return 0;
++}
++
++static int spidev_open(struct inode *inode, struct file *file)
++{
++ unsigned int minor = iminor(inode);
++ struct spi_dev *spi_dev;
++
++ CRDEBUG;
++
++ spi_dev = spi_dev_get_by_minor(minor);
++ if (!spi_dev)
++ return -ENODEV;
++
++ /* registered with adapter, passed as client to user */
++ file->private_data = spi_dev;
++
++ return 0;
++}
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++int spi_master_close(struct spi_dev *spi_dev)
++{
++ int ret;
++ CRDEBUG;
++ ret = spi_dev->algo->close(spi_dev);
++ return 0;
++}
++static int spidev_release(struct inode *inode, struct file *file)
++{
++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data;
++ int ret;
++ CRDEBUG;
++
++ ret = spi_master_close(spi_dev);
++ file->private_data = NULL;
++
++ return 0;
++}
++#else
++
++static int spidev_release(struct inode *inode, struct file *file)
++{
++ CRDEBUG;
++ file->private_data = NULL;
++
++ return 0;
++}
++#endif
++static struct file_operations spidev_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .read = spidev_read,
++ .write = spidev_write,
++ .ioctl = spidev_ioctl,
++ .open = spidev_open,
++ .release = spidev_release,
++};
++
++//static int __init spi_dev_init(void)
++static int spi_dev_init(void)
++{
++ int res;
++
++ printk(KERN_INFO "spi /dev entries driver\n");
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#if(SPI_CHANNEL==0)
++ res = register_chrdev(SPI_MAJOR, "spi0", &spidev_fops);
++#else
++ res = register_chrdev(SPI_MAJOR, "spi1", &spidev_fops);
++#endif
++#elif defined CONFIG_HS_SPI_S3C2443
++ res = register_chrdev(SPI_MAJOR, "spi0", &spidev_fops);
++#else
++ res = register_chrdev(SPI_MAJOR, "spi", &spidev_fops);
++#endif
++ if (res)
++ goto out;
++
++// devfs_mk_dir("spi");
++ return 0;
++
++out:
++ printk(KERN_ERR "%s: Driver Initialisation failed\n", __FILE__);
++ return res;
++}
++
++//static void __exit spi_dev_exit(void)
++static void spi_dev_exit(void)
++{
++ CRDEBUG;
++// devfs_remove("spi");
++ unregister_chrdev(SPI_MAJOR,"spi");
++}
++
++MODULE_AUTHOR("Samsung Electronics");
++MODULE_DESCRIPTION("spi /dev entries driver");
++MODULE_LICENSE("GPL");
++
++module_init(spi_dev_init);
++module_exit(spi_dev_exit);
++
++EXPORT_SYMBOL(spi_attach_spidev);
++EXPORT_SYMBOL(spi_detach_spidev);
+diff --git a/drivers/spi/spi-dev.h b/drivers/spi/spi-dev.h
+new file mode 100644
+index 0000000..5e06654
+--- /dev/null
++++ b/drivers/spi/spi-dev.h
+@@ -0,0 +1,138 @@
++/* ------------------------------------------------------------------------- */
++/* */
++/* spi.h - definitions for the spi-bus interface */
++/* */
++/* ------------------------------------------------------------------------- */
++/* Copyright (C) 2006 Samsung Electronics Co. ltd.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
++/* ------------------------------------------------------------------------- */
++
++#ifndef _LINUX_SPI_H
++#define _LINUX_SPI_H
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/device.h> /* for struct device */
++#include <asm/semaphore.h>
++
++/* --- General options ------------------------------------------------ */
++
++struct spi_msg;
++struct spi_dev;
++struct spi_algorithm;
++
++/*
++ * The master routines are the ones normally used to transmit data to devices
++ * on a bus (or/and read from them). Apart from these basic transfer functions
++ * to transmit one message at a time, a more complex version can be used to
++ * transmit an arbitrary number of messages without interruption.
++ */
++extern int spi_master_send(struct spi_dev *,char* ,int);
++extern int spi_master_recv(struct spi_dev *,char* ,int);
++
++#define SPI_CHANNEL 0
++
++/*
++ * A driver is capable of handling one or more physical devices present on
++ * SPI adapters. This information is used to inform the driver of adapter
++ * events.
++ */
++
++struct spi_dev {
++ int minor;
++
++ dma_addr_t dmabuf; /* handle for DMA transfer */
++ unsigned int flags; /* flags for the SPI operation */
++ struct semaphore bus_lock; /* semaphore for bus access */
++
++ struct spi_algorithm *algo; /* the algorithm to access the bus */
++ void *algo_data; /* the bus control struct */
++
++ int timeout;
++ int retries;
++ struct device dev; /* the adapter device */
++};
++
++/*
++ * The following structs are for those who like to implement new bus drivers:
++ * spi_algorithm is the interface to a class of hardware solutions which can
++ * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
++ * to name two of the most common.
++ */
++struct spi_algorithm {
++ char name[32]; /* textual description */
++ unsigned int id;
++
++ /* If an adapter algorithm can't to SPI-level access, set master_xfer
++ to NULL. If an adapter algorithm can do SMBus access, set
++ smbus_xfer. If set to NULL, the SMBus protocol is simulated
++ using common SPI messages */
++ int (*master_xfer)(struct spi_dev *spi_dev,struct spi_msg *msgs,
++ int num);
++
++ /* --- ioctl like call to set div. parameters. */
++ int (*algo_control)(struct spi_dev *, unsigned int, unsigned long);
++
++ /* To determine what the adapter supports */
++ u32 (*functionality) (struct spi_dev *);
++ int (*close)(struct spi_dev *spi_dev);
++};
++
++/* ----- functions exported by spi.o */
++
++/* administration...
++ */
++extern int spi_attach_spidev(struct spi_dev *);
++extern int spi_detach_spidev(struct spi_dev *);
++
++/*
++ * SPI Message - used for pure spi transaction, also from /dev interface
++ */
++
++#define SPI_M_MODE_MASTER 0x001
++#define SPI_M_MODE_SLAVE 0x002
++#define SPI_M_USE_FIFO 0x004
++#define SPI_M_CPOL_ACTHIGH 0x010
++#define SPI_M_CPOL_ACTLOW 0x020
++#define SPI_M_CPHA_FORMATA 0x040
++#define SPI_M_CPHA_FORMATB 0x080
++#define SPI_M_DMA_MODE 0x100
++#define SPI_M_INT_MODE 0x200
++#define SPI_M_POLL_MODE 0x400
++#define SPI_M_DEBUG 0x800
++#define SPI_M_FIFO_POLL 0x1000
++
++
++struct spi_msg {
++ __u16 flags;
++ __u16 len; /* msg length */
++ __u8 *wbuf; /* pointer to msg data to write */
++ __u8 *rbuf; /* pointer to msg data for read */
++};
++
++/* ----- commands for the ioctl call: */
++ /* -> spi-adapter specific ioctls */
++#define SET_SPI_RETRIES 0x0701 /* number of times a device address */
++ /* should be polled when not */
++ /* acknowledging */
++#define SET_SPI_TIMEOUT 0x0702 /* set timeout - call with int */
++#define SET_SPI_FLAGS 0x0704 /* set flags for h/w settings */
++
++#define SPI_MAJOR 153 /* Device major number */
++ /* minor 0-15 spi0 - spi15 */
++
++#endif /* _LINUX_SPI_H */
++
+diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c
+index 89d6685..fb692db 100644
+--- a/drivers/spi/spi_s3c24xx.c
++++ b/drivers/spi/spi_s3c24xx.c
+@@ -127,7 +127,7 @@ static int s3c24xx_spi_setupxfer(struct spi_device *spi,
+
+ div = (div / 2) - 1;
+
+- if (div < 0)
++ if (div == 0)
+ div = 1;
+
+ if (div > 255)
+diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
+index 516a640..ee04968 100644
+--- a/drivers/usb/Makefile
++++ b/drivers/usb/Makefile
+@@ -16,6 +16,7 @@ obj-$(CONFIG_USB_UHCI_HCD) += host/
+ obj-$(CONFIG_USB_SL811_HCD) += host/
+ obj-$(CONFIG_USB_U132_HCD) += host/
+ obj-$(CONFIG_USB_R8A66597_HCD) += host/
++obj-$(CONFIG_USB_S3C_OTG_HOST) += host/
+
+ obj-$(CONFIG_USB_ACM) += class/
+ obj-$(CONFIG_USB_PRINTER) += class/
+diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
+index f81d08d..10e2993 100644
+--- a/drivers/usb/gadget/Kconfig
++++ b/drivers/usb/gadget/Kconfig
+@@ -87,6 +87,8 @@ config USB_GADGET_SELECTED
+ choice
+ prompt "USB Peripheral Controller"
+ depends on USB_GADGET
++ default USB_GADGET_S3C_OTGD_HS if PLAT_S3C64XX
++ default USB_GADGET_S3C_HS if PLAT_S3C24XX
+ help
+ A USB device uses a controller to talk to its host.
+ Systems should have only one such upstream link.
+@@ -274,6 +276,41 @@ config USB_OMAP
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
++config USB_GADGET_S3C_FS
++ boolean "S3C full speed(1.1) USB device"
++ depends on CPU_S3C2412
++ select USB_GADGET_SELECTED
++ help
++ Say "y" to link the driver statically, or "m" to build a
++ dynamically linked module called "s3c_udc_fs" and force all
++ gadget drivers to also be dynamically linked.
++
++config USB_GADGET_S3C_HS
++ boolean "S3C high speed(2.0, dual-speed) USB device"
++ depends on (CPU_S3C2443 || CPU_S3C2450)
++ select USB_GADGET_SELECTED
++ select USB_GADGET_DUALSPEED
++ help
++ Say "y" to link the driver statically, or "m" to build a
++ dynamically linked module called "s3c_udc_hs" and force all
++ gadget drivers to also be dynamically linked.
++
++config USB_GADGET_S3C_OTGD_HS
++ boolean "S3C USB OTG controller"
++ depends on PLAT_S3C64XX && !(USB_S3C_OTG_HOST)
++ select USB_GADGET_SELECTED
++ select USB_GADGET_DUALSPEED
++ help
++ Samsung's S3C64XX processors have high speed USB OTG controller.
++ To link the driver eables
++ the 'S3C high speed(2.0, dual-speed) USB OTG device' below.
++
++config USB_S3C
++ tristate
++ depends on USB_GADGET_S3C_FS && USB_GADGET_S3C_HS && USB_GADGET_S3C_OTGD_HS
++ default USB_GADGET
++ select USB_GADGET_SELECTED
++
+ config USB_OTG
+ boolean "OTG Support"
+ depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD
+@@ -358,6 +395,42 @@ config USB_DUMMY_HCD
+
+ endchoice
+
++comment "NOTE: S3C OTG device role enables the controller driver below"
++ depends on USB_GADGET_S3C_OTGD_HS
++
++
++config USB_S3C_OTGD_HS
++ tristate "S3C high speed(2.0, dual-speed) USB OTG device"
++ depends on USB_GADGET && USB_GADGET_S3C_OTGD_HS && !(USB_S3C_OTG_HOST)
++ default y
++ help
++ Say "y" to link the driver statically, or "m" to build a
++ dynamically linked module called "s3c-udc-otg-hs" and force all
++ gadget drivers to also be dynamically linked.
++
++choice
++ prompt "S3C OTGD transfer mode"
++ depends on USB_S3C_OTGD_HS
++ default USB_GADGET_S3C_OTGD_HS_DMA_MODE
++ help
++ S3C USB OTG conteroller supports DMA mode and Slave mode
++ for the dat transfer. You must slect one for the core
++ operation mode.
++
++config USB_GADGET_S3C_OTGD_HS_DMA_MODE
++ bool "enabled DMA MODE"
++ depends on USB_GADGET_S3C_OTGD_HS
++ default y
++ help
++ S3C USB OTG core operates in DMA mode.
++
++config USB_GADGET_S3C_OTGD_HS_SLAVE_MODE
++ bool "enabled Slave MODE"
++ depends on USB_GADGET_S3C_OTGD_HS
++ help
++ S3C USB OTG core operates in Slave mode.
++endchoice
++
+ config USB_GADGET_DUALSPEED
+ bool
+ depends on USB_GADGET
+diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
+index 904e57b..057795c 100644
+--- a/drivers/usb/gadget/Makefile
++++ b/drivers/usb/gadget/Makefile
+@@ -17,6 +17,9 @@ obj-$(CONFIG_USB_AT91) += at91_udc.o
+ obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
+ obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
+ obj-$(CONFIG_USB_M66592) += m66592-udc.o
++obj-$(CONFIG_USB_GADGET_S3C_HS) += s3c-udc-hs.o
++obj-$(CONFIG_USB_GADGET_S3C_FS) += s3c-udc-fs.o
++obj-$(CONFIG_USB_S3C_OTGD_HS) += s3c-udc-otg-hs.o
+
+ #
+ # USB gadget drivers
+diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
+index f9d0710..b98059b 100644
+--- a/drivers/usb/gadget/epautoconf.c
++++ b/drivers/usb/gadget/epautoconf.c
+@@ -264,6 +264,24 @@ struct usb_ep * __devinit usb_ep_autoconfig (
+ return ep;
+ }
+
++ } else if (gadget_is_s3c(gadget)) {
++ if (USB_ENDPOINT_XFER_INT == type) {
++ /* single buffering is enough */
++ ep = find_ep (gadget, "ep3-int");
++ if (ep && ep_matches (gadget, ep, desc))
++ return ep;
++ } else if (USB_ENDPOINT_XFER_BULK == type
++ && (USB_DIR_IN & desc->bEndpointAddress)) {
++ ep = find_ep (gadget, "ep2-bulk");
++ if (ep && ep_matches (gadget, ep, desc))
++ return ep;
++ }
++ else if (USB_ENDPOINT_XFER_BULK == type
++ && !(USB_DIR_IN & desc->bEndpointAddress)) {
++ ep = find_ep (gadget, "ep1-bulk");
++ if (ep && ep_matches (gadget, ep, desc))
++ return ep;
++ }
+ } else if (gadget_is_sh (gadget) && USB_ENDPOINT_XFER_INT == type) {
+ /* single buffering is enough; maybe 8 byte fifo is too */
+ ep = find_ep (gadget, "ep3in-bulk");
+diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
+index ba7935d..889efed 100644
+--- a/drivers/usb/gadget/ether.c
++++ b/drivers/usb/gadget/ether.c
+@@ -32,6 +32,7 @@
+ #include <linux/usb/cdc.h>
+ #include <linux/usb/gadget.h>
+
++#include <asm/cacheflush.h>
+ #include "gadget_chips.h"
+
+ /*-------------------------------------------------------------------------*/
+@@ -90,6 +91,21 @@ static const char driver_desc [] = DRIVER_DESC;
+ |USB_CDC_PACKET_TYPE_DIRECTED)
+
+
++/* for memory copying socket buffers, it enhances performance of data communication */
++#define SKB_MEMCOPY 1
++
++#if SKB_MEMCOPY
++
++#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS_DMA_MODE) /* DMA Mode */
++ #define MEMCOPY_FOR_DMA
++ #undef MEMCOPY_FOR_SLAVE
++#else /* Slave Mode */
++ #define MEMCOPY_FOR_SLAVE
++ #undef MEMCOPY_FOR_DMA
++#endif
++
++#endif //SKB_MEMCOPY
++
+ /*-------------------------------------------------------------------------*/
+
+ struct eth_dev {
+@@ -243,6 +259,10 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address");
+ #define DEV_CONFIG_CDC
+ #endif
+
++#if defined(CONFIG_USB_GADGET_S3C_FS) || defined(CONFIG_USB_GADGET_S3C_HS) || defined(CONFIG_USB_GADGET_S3C_OTGD_HS)
++#define DEV_CONFIG_CDC
++#endif
++
+ #ifdef CONFIG_USB_GADGET_AT91
+ #define DEV_CONFIG_CDC
+ #endif
+@@ -1704,7 +1724,23 @@ rx_submit (struct eth_dev *dev, struct usb_request *req, gfp_t gfp_flags)
+ */
+ skb_reserve(skb, NET_IP_ALIGN);
+
++#if SKB_MEMCOPY
++
++#ifdef MEMCOPY_FOR_DMA
++ req->buf = kmalloc(size, GFP_ATOMIC| GFP_DMA);
++#endif
++#ifdef MEMCOPY_FOR_SLAVE
++ req->buf = kmalloc(size, GFP_ATOMIC);
++#endif
++
++ if (!req->buf) {
++ req->buf = skb->data;
++ printk("%s: fail to kmalloc [req->buf = skb->data]\n", __FUNCTION__);
++ }
++
++#else
+ req->buf = skb->data;
++#endif
+ req->length = size;
+ req->complete = rx_complete;
+ req->context = skb;
+@@ -1715,8 +1751,13 @@ enomem:
+ defer_kevent (dev, WORK_RX_MEMORY);
+ if (retval) {
+ DEBUG (dev, "rx submit --> %d\n", retval);
+- if (skb)
++ if (skb) {
+ dev_kfree_skb_any(skb);
++#ifdef SKB_MEMCOPY
++ if(req->buf != skb->data)
++ kfree(req->buf);
++#endif
++ }
+ spin_lock(&dev->req_lock);
+ list_add (&req->list, &dev->rx_reqs);
+ spin_unlock(&dev->req_lock);
+@@ -1734,6 +1775,10 @@ static void rx_complete (struct usb_ep *ep, struct usb_request *req)
+
+ /* normal completion */
+ case 0:
++#ifdef SKB_MEMCOPY
++ if(req->buf != skb->data)
++ memcpy(skb->data, req->buf, req->actual);
++#endif
+ skb_put (skb, req->actual);
+ /* we know MaxPacketsPerTransfer == 1 here */
+ if (rndis_active(dev))
+@@ -1755,6 +1800,11 @@ static void rx_complete (struct usb_ep *ep, struct usb_request *req)
+ * use skb buffers.
+ */
+ status = netif_rx (skb);
++
++#ifdef SKB_MEMCOPY
++ if(req->buf != skb->data)
++ kfree(req->buf);
++#endif
+ skb = NULL;
+ break;
+
+@@ -1770,6 +1820,10 @@ static void rx_complete (struct usb_ep *ep, struct usb_request *req)
+ defer_kevent (dev, WORK_RX_MEMORY);
+ quiesce:
+ dev_kfree_skb_any (skb);
++#ifdef SKB_MEMCOPY
++ if(req->buf != skb->data)
++ kfree(req->buf);
++#endif
+ goto clean;
+
+ /* data overrun */
+@@ -1783,8 +1837,13 @@ quiesce:
+ break;
+ }
+
+- if (skb)
++ if (skb) {
+ dev_kfree_skb_any (skb);
++#ifdef SKB_MEMCOPY
++ if(req->buf != skb->data)
++ kfree(req->buf);
++#endif
++ }
+ if (!netif_running (dev->net)) {
+ clean:
+ spin_lock(&dev->req_lock);
+@@ -1913,7 +1972,10 @@ static void tx_complete (struct usb_ep *ep, struct usb_request *req)
+ list_add (&req->list, &dev->tx_reqs);
+ spin_unlock(&dev->req_lock);
+ dev_kfree_skb_any (skb);
+-
++#ifdef SKB_MEMCOPY
++ if(req->buf != skb->data)
++ kfree(req->buf);
++#endif
+ atomic_dec (&dev->tx_qlen);
+ if (netif_carrier_ok (dev->net))
+ netif_wake_queue (dev->net);
+@@ -1993,7 +2055,25 @@ static int eth_start_xmit (struct sk_buff *skb, struct net_device *net)
+ rndis_add_hdr (skb);
+ length = skb->len;
+ }
++#if SKB_MEMCOPY
++
++#ifdef MEMCOPY_FOR_DMA
++ req->buf = kmalloc(skb->len +2, GFP_ATOMIC | GFP_DMA);
++#endif
++#ifdef MEMCOPY_FOR_SLAVE
++ req->buf = kmalloc(skb->len +2, GFP_ATOMIC);
++#endif
++
++ if (!req->buf) {
++ req->buf = skb->data;
++ printk("%s: fail to kmalloc [req->buf = skb->data]\n", __FUNCTION__);
++ }
++ else
++ memcpy((void *)req->buf, (void *)skb->data, skb->len);
++
++#else
+ req->buf = skb->data;
++#endif
+ req->context = skb;
+ req->complete = tx_complete;
+
+@@ -2027,6 +2107,10 @@ static int eth_start_xmit (struct sk_buff *skb, struct net_device *net)
+ drop:
+ dev->stats.tx_dropped++;
+ dev_kfree_skb_any (skb);
++#ifdef SKB_MEMCOPY
++ if(req->buf != skb->data)
++ kfree(req->buf);
++#endif
+ spin_lock_irqsave(&dev->req_lock, flags);
+ if (list_empty (&dev->tx_reqs))
+ netif_start_queue (net);
+diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
+index f7f159c..3b8da62 100644
+--- a/drivers/usb/gadget/gadget_chips.h
++++ b/drivers/usb/gadget/gadget_chips.h
+@@ -100,6 +100,12 @@
+ #define gadget_is_s3c2410(g) 0
+ #endif
+
++#if defined(CONFIG_USB_GADGET_S3C_FS) || defined(CONFIG_USB_GADGET_S3C_HS) || defined(CONFIG_USB_GADGET_S3C_OTGD_HS)
++#define gadget_is_s3c(g) !strcmp("s3c-udc", (g)->name)
++#else
++#define gadget_is_s3c(g) 0
++#endif
++
+ #ifdef CONFIG_USB_GADGET_AT91
+ #define gadget_is_at91(g) !strcmp("at91_udc", (g)->name)
+ #else
+@@ -212,5 +218,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
+ return 0x20;
+ else if (gadget_is_m66592(gadget))
+ return 0x21;
++ else if (gadget_is_s3c(gadget))
++ return 0x22;
+ return -ENOENT;
+ }
+diff --git a/drivers/usb/gadget/s3c-udc-fs.c b/drivers/usb/gadget/s3c-udc-fs.c
+new file mode 100644
+index 0000000..67aa9f6
+--- /dev/null
++++ b/drivers/usb/gadget/s3c-udc-fs.c
+@@ -0,0 +1,1875 @@
++/*
++ * linux/drivers/usb/gadget/s3c24x0_udc.c
++ * Samsung S3C24X0 on-chip full speed USB device controllers
++ *
++ * Copyright (C) 2005 for Samsung Electronics
++ * - by Jaswinder Singh Brar <jassi@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#include "s3c-udc.h"
++#include <linux/platform_device.h>
++
++#define GPIO_INIT do{ \
++ u32 val; \
++ val = __raw_readl(S3C_GPFCON); \
++ val &= ~(3<<4); \
++ val |= (1<<4); \
++ __raw_writel(val, S3C_GPFCON); \
++ val = __raw_readl(S3C_GPFDN); \
++ val |= (1<<2); \
++ __raw_writel(val, S3C_GPFDN); \
++ val = __raw_readl(S3C_GPFDAT); \
++ val &= ~(1<<2); \
++ __raw_writel(val, S3C_GPFDAT); \
++ }while(0)
++
++#define GPIO_DEINIT do{ \
++ u32 val; \
++ val = __raw_readl(S3C_GPFCON); \
++ val &= ~(3<<4); \
++ __raw_writel(val, S3C_GPFCON); \
++ val = __raw_readl(S3C_GPFDN); \
++ val &= ~(1<<2); \
++ __raw_writel(val, S3C_GPFDN); \
++ val = __raw_readl(S3C_GPFDAT); \
++ val &= ~(1<<2); \
++ __raw_writel(val, S3C_GPFDAT); \
++ }while(0)
++
++#define GPIO_ENABLE do{ \
++ u32 val; \
++ val = __raw_readl(S3C_GPFDAT); \
++ val |= (1<<2); \
++ __raw_writel(val, S3C_GPFDAT); \
++ }while(0)
++
++#define GPIO_DISABLE do{ \
++ u32 val; \
++ val = __raw_readl(S3C_GPFDAT); \
++ val &= ~(1<<2); \
++ __raw_writel(val, S3C_GPFDAT); \
++ }while(0)
++
++#ifndef DEBUG_EP0
++# define DEBUG_EP0(fmt,args...)
++#endif
++#ifndef DEBUG_SETUP
++# define DEBUG_SETUP(fmt,args...)
++#endif
++#ifndef DEBUG
++# define NO_STATES
++# define DEBUG(fmt,args...)
++#endif
++
++//#define DEBUG_EP0 printk
++//#define DEBUG_SETUP printk
++
++#define DRIVER_DESC "Samsung USB Full/High speed Device Controller"
++#define DRIVER_VERSION __DATE__
++
++#ifndef _BIT /* FIXME - what happended to _BIT in 2.6.7bk18? */
++#define _BIT(x) (1<<(x))
++#endif
++
++struct s3c_udc *the_controller;
++static struct clk *udc_clock;
++
++static const char driver_name[] = "s3c-udc";
++static const char driver_desc[] = DRIVER_DESC;
++static const char ep0name[] = "ep0-control";
++
++/*
++ Local definintions.
++*/
++
++static char *state_names[] = {
++ "WAIT_FOR_SETUP",
++ "DATA_STATE_XMIT",
++ "DATA_STATE_NEED_ZLP",
++ "WAIT_FOR_OUT_STATUS",
++ "DATA_STATE_RECV"
++};
++
++/*
++ Local declarations.
++*/
++static int s3c_ep_enable(struct usb_ep *ep,
++ const struct usb_endpoint_descriptor *);
++static int s3c_ep_disable(struct usb_ep *ep);
++static struct usb_request *s3c_alloc_request(struct usb_ep *ep, int);
++static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
++static int s3c_queue(struct usb_ep *ep, struct usb_request *, int);
++static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
++static int s3c_set_halt(struct usb_ep *ep, int);
++static int s3c_fifo_status(struct usb_ep *ep);
++static void s3c_fifo_flush(struct usb_ep *ep);
++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
++static void s3c_handle_ep0(struct s3c_udc *dev);
++
++static void done(struct s3c_ep *ep, struct s3c_request *req,
++ int status);
++static void stop_activity(struct s3c_udc *dev,
++ struct usb_gadget_driver *driver);
++static int udc_enable(struct s3c_udc *dev);
++static void udc_set_address(struct s3c_udc *dev, unsigned char address);
++static void reconfig_usbd(void);
++
++static __inline__ u32 usb_read(u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ return __raw_readl(port);
++}
++
++static __inline__ void usb_write(u32 val, u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ __raw_writel(val, port);
++}
++
++static __inline__ void usb_set(u32 val, u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ __raw_writel(__raw_readl(port) | val, port);
++}
++
++static __inline__ void usb_clear(u32 val, u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ __raw_writel(__raw_readl(port) & ~val, port);
++}
++
++static struct usb_ep_ops s3c_ep_ops = {
++ .enable = s3c_ep_enable,
++ .disable = s3c_ep_disable,
++
++ .alloc_request = s3c_alloc_request,
++ .free_request = s3c_free_request,
++
++ .queue = s3c_queue,
++ .dequeue = s3c_dequeue,
++
++ .set_halt = s3c_set_halt,
++ .fifo_status = s3c_fifo_status,
++ .fifo_flush = s3c_fifo_flush,
++};
++
++/* Inline code */
++
++static __inline__ int write_packet(struct s3c_ep *ep,
++ struct s3c_request *req, int max)
++{
++ u8 *buf;
++ int length, count;
++ u32 fifo = ep->fifo;
++
++ buf = req->req.buf + req->req.actual;
++ prefetch(buf);
++
++ length = req->req.length - req->req.actual;
++ length = min(length, max);
++ req->req.actual += length;
++
++ DEBUG("Write %d (max %d), fifo %p\n", length, max, fifo);
++
++ count = length;
++
++ while (count--)
++ __raw_writel(*buf++, fifo);
++
++ return length;
++}
++
++#ifdef CONFIG_USB_GADGET_DEBUG_FILES
++
++static const char proc_node_name[] = "driver/udc";
++
++static int
++udc_proc_read(char *page, char **start, off_t off, int count,
++ int *eof, void *_dev)
++{
++ char *buf = page;
++ struct s3c_udc *dev = _dev;
++ char *next = buf;
++ unsigned size = count;
++ unsigned long flags;
++ int t;
++
++ if (off != 0)
++ return 0;
++
++ local_irq_save(flags);
++
++ /* basic device status */
++ t = scnprintf(next, size,
++ DRIVER_DESC "\n"
++ "%s version: %s\n"
++ "Gadget driver: %s\n"
++ "\n",
++ driver_name, DRIVER_VERSION,
++ dev->driver ? dev->driver->driver.name : "(none)");
++ size -= t;
++ next += t;
++
++ local_irq_restore(flags);
++ *eof = 1;
++ return count - size;
++}
++
++#define create_proc_files() create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
++#define remove_proc_files() remove_proc_entry(proc_node_name, NULL)
++
++#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
++
++#define create_proc_files() do {} while (0)
++#define remove_proc_files() do {} while (0)
++
++#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
++
++/*
++ * udc_disable - disable USB device controller
++ */
++static void udc_disable(struct s3c_udc *dev)
++{
++ DEBUG("%s, %p\n", __FUNCTION__, dev);
++
++ udc_set_address(dev, 0);
++
++ if (udc_clock) {
++ clk_disable(udc_clock);
++ //clk_unuse(udc_clock);
++ clk_put(udc_clock);
++ udc_clock = NULL;
++ }
++
++ dev->ep0state = WAIT_FOR_SETUP;
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++ dev->usb_address = 0;
++}
++
++/*
++ * udc_reinit - initialize software state
++ */
++static void udc_reinit(struct s3c_udc *dev)
++{
++ u32 i;
++
++ DEBUG("%s, %p\n", __FUNCTION__, dev);
++
++ /* device/ep0 records init */
++ INIT_LIST_HEAD(&dev->gadget.ep_list);
++ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
++ dev->ep0state = WAIT_FOR_SETUP;
++
++ /* basic endpoint records init */
++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
++ struct s3c_ep *ep = &dev->ep[i];
++
++ if (i != 0)
++ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
++
++ ep->desc = 0;
++ ep->stopped = 0;
++ INIT_LIST_HEAD(&ep->queue);
++ ep->pio_irqs = 0;
++ }
++
++ /* the rest was statically initialized, and is read-only */
++}
++
++#define BYTES2MAXP(x) (x / 8)
++#define MAXP2BYTES(x) (x * 8)
++
++/* until it's enabled, this UDC should be completely invisible
++ * to any USB host.
++ */
++static int udc_enable(struct s3c_udc *dev)
++{
++ u32 val;
++
++ DEBUG("%s, %p\n", __FUNCTION__, dev);
++
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++
++ val = usb_read(S3C_MISCCR, 0);
++ val &= ~((1<<3)|(1<<13)); // USB Device in Normal mode
++ usb_write(val, S3C_MISCCR, 0);
++
++ /* Enable Clock */
++ udc_clock = clk_get(NULL, "usb-device");
++ if (!udc_clock) {
++ printk("failed to get udc clock source\n");
++ return -ENOENT;
++ }
++ //clk_use(udc_clock);
++ clk_enable(udc_clock);
++
++ val = (1<<0);
++ usb_write(val, S3C_UDC_EP_INT_REG, 0); //clear
++ val = (1<<2); //UD_USBINTE_RESET
++ usb_write(val, S3C_UDC_USB_INT_REG, 0); //clear
++
++ /* Set MAXP values for each */
++ usb_write(dev->ep[0].ep.maxpacket>>3, S3C_UDC_MAXP_REG, 0);
++
++ usb_write(dev->ep[1].ep.maxpacket>>3, S3C_UDC_MAXP_REG, 1);
++
++ usb_write(dev->ep[2].ep.maxpacket>>3, S3C_UDC_MAXP_REG, 2);
++
++ usb_write(dev->ep[3].ep.maxpacket>>3, S3C_UDC_MAXP_REG, 3);
++
++ usb_write(dev->ep[4].ep.maxpacket>>3, S3C_UDC_MAXP_REG, 4);
++
++ return 0;
++}
++
++/*
++ Register entry point for the peripheral controller driver.
++*/
++int usb_gadget_register_driver(struct usb_gadget_driver *driver)
++{
++ struct s3c_udc *dev = the_controller;
++ int retval;
++
++ DEBUG("%s: %s\n", __FUNCTION__, driver->driver.name);
++
++ if (!driver
++ || driver->speed != USB_SPEED_FULL
++ || !driver->bind
++ || !driver->unbind || !driver->disconnect || !driver->setup)
++ return -EINVAL;
++ if (!dev)
++ return -ENODEV;
++ if (dev->driver)
++ return -EBUSY;
++
++ /* first hook up the driver ... */
++ dev->driver = driver;
++ dev->gadget.dev.driver = &driver->driver;
++
++ device_add(&dev->gadget.dev);
++ retval = driver->bind(&dev->gadget);
++ if (retval) {
++ printk("%s: bind to driver %s --> error %d\n", dev->gadget.name,
++ driver->driver.name, retval);
++ device_del(&dev->gadget.dev);
++
++ dev->driver = 0;
++ dev->gadget.dev.driver = 0;
++ return retval;
++ }
++
++ reconfig_usbd();
++ enable_irq(IRQ_USBD);
++
++ printk("Registered gadget driver '%s'\n", driver->driver.name);
++
++ GPIO_ENABLE;
++
++ return 0;
++}
++
++EXPORT_SYMBOL(usb_gadget_register_driver);
++
++/*
++ Unregister entry point for the peripheral controller driver.
++*/
++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++{
++ struct s3c_udc *dev = the_controller;
++ unsigned long flags;
++
++ GPIO_DISABLE;
++
++ if (!dev)
++ return -ENODEV;
++ if (!driver || driver != dev->driver)
++ return -EINVAL;
++
++ spin_lock_irqsave(&dev->lock, flags);
++ dev->driver = 0;
++ stop_activity(dev, driver);
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ driver->unbind(&dev->gadget);
++ device_del(&dev->gadget.dev);
++
++ disable_irq(IRQ_USBD);
++
++ printk("Unregistered gadget driver '%s'\n", driver->driver.name);
++ return 0;
++}
++
++EXPORT_SYMBOL(usb_gadget_unregister_driver);
++
++/*-------------------------------------------------------------------------*/
++
++/** Write request to FIFO (max write == maxp size)
++ * Return: 0 = still running, 1 = completed, negative = errno
++ */
++static int write_fifo(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 max;
++ unsigned count;
++ int is_last, is_short;
++
++ max = le16_to_cpu(ep->desc->wMaxPacketSize);
++
++ count = write_packet(ep, req, max);
++
++ /* last packet is usually short (or a zlp) */
++ if (unlikely(count != max))
++ is_last = is_short = 1;
++ else {
++ if (likely(req->req.length != req->req.actual)
++ || req->req.zero)
++ is_last = 0;
++ else
++ is_last = 1;
++ /* interrupt/iso maxpacket may not fill the fifo */
++ is_short = unlikely(max < ep_maxpacket(ep));
++ }
++
++ /* requests complete when all IN data is in the FIFO */
++ if (is_last) {
++ if(!ep_index(ep)){ // EP0 must not come here
++ BUG();
++ //usb_set(S3C_UDC_EP0_CSR_IPKRDY | S3C_UDC_EP0_CSR_DE,
++ // S3C_UDC_EP0_CSR_REG, 0);
++ }else{
++ usb_set(S3C_UDC_ICSR1_PKTRDY, ep->csr1, ep_index(ep));
++ }
++ done(ep, req, 0);
++ return 1;
++ } else{
++ usb_set(S3C_UDC_ICSR1_PKTRDY, ep->csr1, ep_index(ep));
++ }
++
++ DEBUG_EP0("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
++ ep->ep.name, count,
++ is_last ? "/L" : "", is_short ? "/S" : "",
++ req->req.length - req->req.actual, req);
++
++ return 0;
++}
++
++/** Read to request from FIFO (max read == bytes in fifo)
++ * Return: 0 = still running, 1 = completed, negative = errno
++ */
++static int read_fifo(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 csr;
++ u8 *buf;
++ unsigned bufferspace, count, is_short;
++ u32 fifo = ep->fifo;
++
++ /* make sure there's a packet in the FIFO. */
++ csr = usb_read(ep->csr1, ep_index(ep));
++ if (!(csr & S3C_UDC_OCSR1_PKTRDY)) {
++ DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ buf = req->req.buf + req->req.actual;
++ prefetchw(buf);
++ bufferspace = req->req.length - req->req.actual;
++
++ /* read all bytes from this packet */
++ count = (( (usb_read(S3C_UDC_OUT_FIFO_CNT2_REG, ep_index(ep)) & 0xff ) << 8) | (usb_read(S3C_UDC_OUT_FIFO_CNT1_REG, ep_index(ep)) & 0xff));
++ req->req.actual += min(count, bufferspace);
++
++ is_short = (count < ep->ep.maxpacket);
++ DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
++ ep->ep.name, csr, count,
++ is_short ? "/S" : "", req, req->req.actual, req->req.length);
++
++ while (likely(count-- != 0)) {
++ u8 byte = (u8) __raw_readl(fifo);
++
++ if (unlikely(bufferspace == 0)) {
++ /* this happens when the driver's buffer
++ * is smaller than what the host sent.
++ * discard the extra data.
++ */
++ if (req->req.status != -EOVERFLOW)
++ printk("%s overflow %d\n", ep->ep.name, count);
++ req->req.status = -EOVERFLOW;
++ } else {
++ *buf++ = byte;
++ bufferspace--;
++ }
++ }
++
++ usb_clear(S3C_UDC_OCSR1_PKTRDY, ep->csr1, ep_index(ep));
++
++ /* completion */
++ if (is_short || req->req.actual == req->req.length) {
++ done(ep, req, 0);
++ return 1;
++ }
++
++ /* finished that packet. the next one may be waiting... */
++ return 0;
++}
++
++/*
++ * done - retire a request; caller blocked irqs
++ */
++static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
++{
++ unsigned int stopped = ep->stopped;
++
++ DEBUG("%s, %p\n", __FUNCTION__, ep);
++ list_del_init(&req->queue);
++
++ if (likely(req->req.status == -EINPROGRESS))
++ req->req.status = status;
++ else
++ status = req->req.status;
++
++ if (status && status != -ESHUTDOWN)
++ DEBUG("complete %s req %p stat %d len %u/%u\n",
++ ep->ep.name, &req->req, status,
++ req->req.actual, req->req.length);
++
++ /* don't modify queue heads during completion callback */
++ ep->stopped = 1;
++
++ spin_unlock(&ep->dev->lock);
++ req->req.complete(&ep->ep, &req->req);
++ spin_lock(&ep->dev->lock);
++
++ ep->stopped = stopped;
++}
++
++/*
++ * nuke - dequeue ALL requests
++ */
++void nuke(struct s3c_ep *ep, int status)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s, %p\n", __FUNCTION__, ep);
++
++ /* called with irqs blocked */
++ while (!list_empty(&ep->queue)) {
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ done(ep, req, status);
++ }
++}
++
++/**
++ * s3c_in_epn - handle IN interrupt
++ */
++static void s3c_in_epn(struct s3c_udc *dev, u32 ep_idx)
++{
++ u32 csr;
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req;
++
++ csr = usb_read(ep->csr1, ep_index(ep));
++ DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
++
++ if (csr & S3C_UDC_ICSR1_SENTSTL) {
++ printk("S3C_UDC_ICSR1_SENTSTL\n");
++ usb_set(S3C_UDC_ICSR1_SENTSTL /*| S3C_UDC_ICSR1_SENDSTL */ ,
++ ep->csr1, ep_index(ep));
++ return;
++ }
++
++ if (!ep->desc) {
++ DEBUG("%s: NO EP DESC\n", __FUNCTION__);
++ return;
++ }
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ DEBUG("req: %p\n", req);
++
++ if (!req)
++ return;
++
++ write_fifo(ep, req);
++}
++
++/* ********************************************************************************************* */
++/* Bulk OUT (recv)
++ */
++
++static void s3c_out_epn(struct s3c_udc *dev, u32 ep_idx)
++{
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req;
++
++ DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
++
++ if (ep->desc) {
++ u32 csr;
++ csr = usb_read(ep->csr1, ep_index(ep));
++
++ while ((csr = usb_read(ep->csr1, ep_index(ep)))
++ & (S3C_UDC_OCSR1_PKTRDY | S3C_UDC_OCSR1_SENTSTL)) {
++
++ DEBUG("%s: %x\n", __FUNCTION__, csr);
++
++ if (csr & S3C_UDC_OCSR1_SENTSTL) {
++ DEBUG("%s: stall sent, flush fifo\n",
++ __FUNCTION__);
++ /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1, ep_index(ep)); */
++ } else if (csr & S3C_UDC_OCSR1_PKTRDY) {
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next,
++ struct s3c_request, queue);
++
++ if (!req) {
++ //printk("%s: NULL REQ %d\n",
++ // __FUNCTION__, ep_idx);
++ break;
++ } else {
++ read_fifo(ep, req);
++ }
++ }
++ }
++ } else {
++ /* Throw packet away.. */
++ printk("%s: No descriptor?!?\n", __FUNCTION__);
++ }
++}
++
++static void stop_activity(struct s3c_udc *dev,
++ struct usb_gadget_driver *driver)
++{
++ int i;
++
++ /* don't disconnect drivers more than once */
++ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
++ driver = 0;
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++
++ /* prevent new request submissions, kill any outstanding requests */
++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
++ struct s3c_ep *ep = &dev->ep[i];
++ ep->stopped = 1;
++ nuke(ep, -ESHUTDOWN);
++ }
++
++ /* report disconnect; the driver is already quiesced */
++ if (driver) {
++ spin_unlock(&dev->lock);
++ driver->disconnect(&dev->gadget);
++ spin_lock(&dev->lock);
++ }
++
++ /* re-init driver-visible data structures */
++ udc_reinit(dev);
++}
++
++static void reconfig_usbd(void)
++{
++ u32 val;
++
++ usb_write(0, S3C_UDC_PWR_REG, 0);
++
++ /* EP0 */
++ val = EP0_FIFO_SIZE>>3;
++ usb_write(val, S3C_UDC_MAXP_REG, 0);
++
++ val = (1<<6)|(1<<7); //EP0_CSR_SOPKTRDY | EP0_CSR_SSE;
++ usb_write(val, S3C_UDC_EP0_CSR_REG, 0);
++
++ /* EP3 -- INT */
++ val = EP_FIFO_SIZE>>3;
++ usb_write(val, S3C_UDC_MAXP_REG, 3);
++
++ val = (1<<6)|(1<<3); //UD_ICSR1_FFLUSH | UD_ICSR1_CLRDT;
++ usb_write(val, S3C_UDC_IN_CSR1_REG, 3);
++
++ val = (1<<5)|(1<<4); //UD_ICSR2_MODEIN | UD_ICSR2_DMAIEN;
++ usb_write(val, S3C_UDC_IN_CSR2_REG, 3);
++
++ /* EP2 -- IN */
++ val = EP_FIFO_SIZE>>3;
++ usb_write(val, S3C_UDC_MAXP_REG, 2);
++
++ val = (1<<6)|(1<<3); //UD_ICSR1_FFLUSH | UD_ICSR1_CLRDT;
++ usb_write(val, S3C_UDC_IN_CSR1_REG, 2);
++
++ val = (1<<5)|(1<<4); //UD_ICSR2_MODEIN | UD_ICSR2_DMAIEN;
++ usb_write(val, S3C_UDC_IN_CSR2_REG, 2);
++
++ /* EP1 -- OUT */
++ val = EP_FIFO_SIZE>>3;
++ usb_write(val, S3C_UDC_MAXP_REG, 1);
++
++ val = (1<<6)|(1<<3); //UD_ICSR1_FFLUSH | UD_ICSR1_CLRDT;
++ usb_write(val, S3C_UDC_IN_CSR1_REG, 1);
++
++ usb_write(0, S3C_UDC_IN_CSR2_REG, 1); // output mode
++
++ val = (1<<4)|(1<<7); //UD_OCSR1_FFLUSH | UD_OCSR1_CLRDT;
++ usb_write(val, S3C_UDC_OUT_CSR1_REG, 1);
++
++ val = (1<<5); //UD_OCSR2_DMAIEN;
++ usb_write(val, S3C_UDC_OUT_CSR2_REG, 1);
++
++ val = EP_FIFO_SIZE>>3;
++ usb_write(val, S3C_UDC_MAXP_REG, 3);
++
++ val = EP_FIFO_SIZE>>3;
++ usb_write(val, S3C_UDC_MAXP_REG, 2);
++
++ val = EP_FIFO_SIZE>>3;
++ usb_write(val, S3C_UDC_MAXP_REG, 1);
++
++ //val = (1<<0)|(1<<1)|(1<<2); //UD_INTE_EP0 | UD_INTE_EP2 | UD_INTE_EP1;
++ val = (1<<0)|(1<<1)|(1<<2)|(1<<3); //UD_INTE_EP0 | UD_INTE_EP2 | UD_INTE_EP1;
++ usb_write(val, S3C_UDC_EP_INT_EN_REG, 0);
++ usb_write(val & ~(1<<0), S3C_UDC_EP_INT_REG, 0); //clear
++
++ val = (1<<0)|(1<<2); //UD_USBINTE_RESET | UD_USBINTE_SUSPND;
++ usb_write(val, S3C_UDC_USB_INT_EN_REG, 0);
++ usb_write(val, S3C_UDC_USB_INT_REG, 0); //clear
++}
++
++/*
++ * elfin usb client interrupt handler.
++ */
++static irqreturn_t s3c_udc_irq(int irq, void *_dev, struct pt_regs *r)
++{
++ struct s3c_udc *dev = _dev;
++
++ spin_lock(&dev->lock);
++
++ u32 intr_out, intr_in;
++ u32 intr_int, val;
++
++ intr_out = intr_in = usb_read(S3C_UDC_EP_INT_REG, 0);
++ intr_int = usb_read(S3C_UDC_USB_INT_REG, 0);
++
++ /* We have only 3 usable eps now -jassi */
++ intr_in &= (S3C_UDC_INT_EP3 | S3C_UDC_INT_EP2 | S3C_UDC_INT_EP0);
++ intr_out &= S3C_UDC_INT_EP1;
++
++ if (!intr_out && !intr_in && !intr_int){
++ spin_unlock(&dev->lock);
++ return IRQ_HANDLED;
++ }
++
++ DEBUG("%s (on state %s)\n", __FUNCTION__,
++ state_names[dev->ep0state]);
++ DEBUG("intr_out = %x\n", intr_out);
++ DEBUG("intr_in = %x\n", intr_in);
++ DEBUG("intr_int = %x\n", intr_int);
++
++ if (intr_in) {
++ if (intr_in & S3C_UDC_INT_EP0){
++ //printk("EP0 ");
++ usb_write(S3C_UDC_INT_EP0, S3C_UDC_EP_INT_REG, 0);
++ s3c_handle_ep0(dev);
++ }else if (intr_in & S3C_UDC_INT_EP2){
++ //printk("EP2 ");
++ usb_write(S3C_UDC_INT_EP2, S3C_UDC_EP_INT_REG, 2);
++ s3c_in_epn(dev, 2); // hard coded !!! -jassi
++ }else{
++ //printk("EP3 ");
++ usb_write(S3C_UDC_INT_EP3, S3C_UDC_EP_INT_REG, 3);
++ s3c_in_epn(dev, 3); // hard coded !!! -jassi
++ }
++ }
++
++ if (intr_out) {
++ //printk("EP1 ");
++ usb_write(S3C_UDC_INT_EP1, S3C_UDC_EP_INT_REG, 1);
++ s3c_out_epn(dev, 1); // hard coded !!! -jassi
++ }
++
++ if (intr_int) {
++ if (intr_int & S3C_UDC_USBINT_RESET) {
++ reconfig_usbd();
++ dev->gadget.speed = USB_SPEED_FULL;
++ dev->ep0state = WAIT_FOR_SETUP;
++ usb_write(S3C_UDC_USBINT_RESET, S3C_UDC_USB_INT_REG, 0);
++ DEBUG_SETUP("RESET");
++ }
++
++ usb_write(intr_int, S3C_UDC_USB_INT_REG, 0);
++
++ if (intr_int & S3C_UDC_USBINT_RESUME) {
++ DEBUG_SETUP("USB resume\n");
++
++ if (dev->gadget.speed != USB_SPEED_UNKNOWN
++ && dev->driver
++ && dev->driver->resume) {
++ dev->driver->resume(&dev->gadget);
++ }
++ }
++
++ if (intr_int & S3C_UDC_USBINT_SUSPEND) {
++ if (dev->gadget.speed !=
++ USB_SPEED_UNKNOWN && dev->driver
++ && dev->driver->suspend) {
++ dev->driver->suspend(&dev->gadget);
++ }
++ }
++
++ }
++
++
++ __raw_writel(IRQ_USBD, S3C_INTPND);
++ __raw_writel(IRQ_USBD, S3C_SRCPND);
++
++ spin_unlock(&dev->lock);
++
++ return IRQ_HANDLED;
++}
++
++static int s3c_ep_enable(struct usb_ep *_ep,
++ const struct usb_endpoint_descriptor *desc)
++{
++ struct s3c_ep *ep;
++ struct s3c_udc *dev;
++ unsigned long flags;
++
++ DEBUG("%s, %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || !desc || ep->desc || _ep->name == ep0name
++ || desc->bDescriptorType != USB_DT_ENDPOINT
++ || ep->bEndpointAddress != desc->bEndpointAddress
++ || ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) {
++ DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ /* xfer types must match, except that interrupt ~= bulk */
++ if (ep->bmAttributes != desc->bmAttributes
++ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
++ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
++ DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
++ return -EINVAL;
++ }
++
++ /* hardware _could_ do smaller, but driver doesn't */
++ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
++ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep))
++ || !desc->wMaxPacketSize) {
++ DEBUG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
++ return -ERANGE;
++ }
++
++ dev = ep->dev;
++ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
++ DEBUG("%s, bogus device state\n", __FUNCTION__);
++ return -ESHUTDOWN;
++ }
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ ep->stopped = 0;
++ ep->desc = desc;
++ ep->pio_irqs = 0;
++ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
++
++ /* Reset halt state */
++ s3c_set_halt(_ep, 0);
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++
++ DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
++ return 0;
++}
++
++/** Disable EP
++ */
++static int s3c_ep_disable(struct usb_ep *_ep)
++{
++ struct s3c_ep *ep;
++ unsigned long flags;
++
++ DEBUG("%s, %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || !ep->desc) {
++ DEBUG("%s, %s not enabled\n", __FUNCTION__,
++ _ep ? ep->ep.name : NULL);
++ return -EINVAL;
++ }
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ /* Nuke all pending requests */
++ nuke(ep, -ESHUTDOWN);
++
++ ep->desc = 0;
++ ep->stopped = 1;
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++
++ DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
++ return 0;
++}
++
++static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
++ int gfp_flags)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s, %p\n", __FUNCTION__, ep);
++
++ req = kmalloc(sizeof *req, gfp_flags);
++ if (!req)
++ return 0;
++
++ memset(req, 0, sizeof *req);
++ INIT_LIST_HEAD(&req->queue);
++
++ return &req->req;
++}
++
++static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s, %p\n", __FUNCTION__, ep);
++
++ req = container_of(_req, struct s3c_request, req);
++ WARN_ON(!list_empty(&req->queue));
++ kfree(req);
++}
++
++
++/** Queue one request
++ * Kickstart transfer if needed
++ */
++static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
++ int gfp_flags)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep;
++ struct s3c_udc *dev;
++ unsigned long flags;
++
++ DEBUG("\n\n\n%s, %p\n", __FUNCTION__, _ep);
++
++ req = container_of(_req, struct s3c_request, req);
++ if (unlikely
++ (!_req || !_req->complete || !_req->buf
++ || !list_empty(&req->queue))) {
++ DEBUG("%s, bad params\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
++ DEBUG("%s, bad ep\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ dev = ep->dev;
++ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
++ DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
++ return -ESHUTDOWN;
++ }
++
++ DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
++ _req->buf);
++
++ spin_lock_irqsave(&dev->lock, flags);
++
++ _req->status = -EINPROGRESS;
++ _req->actual = 0;
++
++ /* kickstart this i/o queue? */
++ DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
++ ep->stopped);
++ if (list_empty(&ep->queue) && likely(!ep->stopped)) {
++ u32 csr;
++
++ if (unlikely(ep_index(ep) == 0)) {
++ /* EP0 */
++ list_add_tail(&req->queue, &ep->queue);
++ s3c_ep0_kick(dev, ep);
++ req = 0;
++ } else if (ep_is_in(ep)) {
++ csr = usb_read(ep->csr1, ep_index(ep));
++ if(!(csr & S3C_UDC_ICSR1_PKTRDY)&&(write_fifo(ep, req) == 1))
++ req = 0;
++ } else {
++ csr = usb_read(ep->csr1, ep_index(ep));
++ if (read_fifo(ep, req) == 1)
++ req = 0;
++ }
++ }
++
++ /* pio or dma irq handler advances the queue. */
++ if (likely(req != 0))
++ list_add_tail(&req->queue, &ep->queue);
++
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ return 0;
++}
++
++/* dequeue JUST ONE request */
++static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
++{
++ struct s3c_ep *ep;
++ struct s3c_request *req;
++ unsigned long flags;
++
++ DEBUG("%s, %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || ep->ep.name == ep0name)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ /* make sure it's actually queued on this endpoint */
++ list_for_each_entry(req, &ep->queue, queue) {
++ if (&req->req == _req)
++ break;
++ }
++ if (&req->req != _req) {
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++ return -EINVAL;
++ }
++
++ done(ep, req, -ECONNRESET);
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++ return 0;
++}
++
++/** Halt specific EP
++ * Return 0 if success
++ */
++static int s3c_set_halt(struct usb_ep *_ep, int value)
++{
++ return 0;
++}
++
++/** Return bytes in EP FIFO
++ */
++static int s3c_fifo_status(struct usb_ep *_ep)
++{
++ u32 csr;
++ int count = 0;
++ struct s3c_ep *ep;
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep) {
++ DEBUG("%s, bad ep\n", __FUNCTION__);
++ return -ENODEV;
++ }
++
++ DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
++
++ /* LPD can't report unclaimed bytes from IN fifos */
++ if (ep_is_in(ep))
++ return -EOPNOTSUPP;
++
++ csr = usb_read(ep->csr1, ep_index(ep));
++ if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
++ csr & S3C_UDC_OCSR1_PKTRDY) {
++ count = ( ((usb_read(S3C_UDC_OUT_FIFO_CNT2_REG, ep_index(ep)) & 0xff) << 8)
++ | (usb_read(S3C_UDC_OUT_FIFO_CNT1_REG, ep_index(ep)) & 0xff));
++ }
++
++ return count;
++}
++
++/** Flush EP FIFO
++ */
++static void s3c_fifo_flush(struct usb_ep *_ep)
++{
++ struct s3c_ep *ep;
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
++ DEBUG("%s, bad ep\n", __FUNCTION__);
++ return;
++ }
++}
++
++/****************************************************************/
++/* End Point 0 related functions */
++/****************************************************************/
++
++/* return: 0 = still running, 1 = completed, negative = errno */
++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 max;
++ unsigned count;
++ int is_last;
++
++ max = ep_maxpacket(ep);
++
++ DEBUG_EP0("%s\n", __FUNCTION__);
++
++ count = write_packet(ep, req, max);
++
++ /* last packet is usually short (or a zlp) */
++ if (unlikely(count != max))
++ is_last = 1;
++ else {
++ if (likely(req->req.length != req->req.actual) || req->req.zero)
++ is_last = 0;
++ else
++ is_last = 1;
++ }
++
++ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
++ ep->ep.name, count,
++ is_last ? "/L" : "", req->req.length - req->req.actual, req);
++
++ /* requests complete when all IN data is in the FIFO */
++ if (is_last) {
++ return 1;
++ }
++
++ return 0;
++}
++
++static __inline__ int s3c_fifo_read(struct s3c_ep *ep,
++ unsigned char *cp, int max)
++{
++ int bytes;
++ int count;
++ u32 fifo = ep->fifo;
++
++ count = ( ((usb_read(S3C_UDC_OUT_FIFO_CNT2_REG, ep_index(ep)) & 0xff ) << 8)
++ | (usb_read(S3C_UDC_OUT_FIFO_CNT1_REG, ep_index(ep)) & 0xff) );
++
++ if (count != max){
++ printk("count=%d max=%d\n", count, max);
++ count = max;
++ }
++ bytes = count;
++ while (count--)
++ *cp++ = (u8) __raw_readl(fifo);
++
++ return bytes;
++}
++
++static __inline__ void s3c_fifo_write(struct s3c_ep *ep,
++ unsigned char *cp, int count)
++{
++ u32 fifo = ep->fifo;
++ DEBUG_EP0("fifo_write: %d %d\n", ep_index(ep), count);
++ while (count--)
++ __raw_writel(*cp++, fifo);
++}
++
++static int read_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 csr;
++ u8 *buf;
++ unsigned bufferspace, count, is_short;
++ u32 fifo = ep->fifo;
++
++ DEBUG_EP0("%s\n", __FUNCTION__);
++
++ csr = usb_read(S3C_UDC_EP0_CSR_REG, ep_index(ep));
++ if (!(csr & S3C_UDC_OCSR1_PKTRDY))
++ return 0;
++
++ buf = req->req.buf + req->req.actual;
++ prefetchw(buf);
++ bufferspace = req->req.length - req->req.actual;
++
++ /* read all bytes from this packet */
++ if (likely(csr & S3C_UDC_EP0_CSR_OPKRDY)) {
++ count = 8; // I do !!!
++ req->req.actual += min(count, bufferspace);
++ } else { // zlp
++ count = 0;
++ }
++
++ is_short = (count < ep->ep.maxpacket);
++ DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
++ ep->ep.name, csr, count,
++ is_short ? "/S" : "", req, req->req.actual, req->req.length);
++
++ while (likely(count-- != 0)) {
++ u8 byte = (u8) __raw_readl(fifo);
++
++ if (unlikely(bufferspace == 0)) {
++ /* this happens when the driver's buffer
++ * is smaller than what the host sent.
++ * discard the extra data.
++ */
++ if (req->req.status != -EOVERFLOW)
++ DEBUG_EP0("%s overflow %d\n", ep->ep.name,
++ count);
++ req->req.status = -EOVERFLOW;
++ } else {
++ *buf++ = byte;
++ bufferspace--;
++ }
++ }
++
++ /* completion */
++ if (is_short || req->req.actual == req->req.length) {
++ return 1;
++ }
++
++ return 0;
++}
++
++/**
++ * udc_set_address - set the USB address for this device
++ * @address:
++ *
++ * Called from control endpoint function after it decodes a set address setup packet.
++ */
++static void udc_set_address(struct s3c_udc *dev, unsigned char address)
++{
++ DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
++ dev->usb_address = address;
++ usb_set((1<<7) | (address & 0x7f), S3C_UDC_FUNC_ADDR_REG, 0);
++}
++
++/*
++ * DATA_STATE_RECV (OUT_PKT_RDY)
++ * - if error
++ * set S3C_UDC_EP0_CSR_SOPKTRDY | S3C_UDC_EP0_CSR_DE | S3C_UDC_EP0_CSR_SENDSTL bits
++ * - else
++ * set S3C_UDC_EP0_CSR_SOPKTRDY bit
++ if last set S3C_UDC_EP0_CSR_DE bit
++ */
++static int first_time = 1;
++
++static void s3c_ep0_read(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret;
++
++ if (!list_empty(&ep->queue))
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ else
++ BUG(); //logic ensures -jassi
++
++ if(req->req.length == 0) {
++ usb_set((S3C_UDC_EP0_CSR_SOPKTRDY | S3C_UDC_EP0_CSR_DE),
++ S3C_UDC_EP0_CSR_REG, 0);
++ dev->ep0state = WAIT_FOR_SETUP;
++ first_time = 1;
++ done(ep, req, 0);
++ return;
++ }
++
++ if(!req->req.actual && first_time){ //for SetUp packet
++ usb_set(S3C_UDC_EP0_CSR_SOPKTRDY, S3C_UDC_EP0_CSR_REG, 0);
++ first_time = 0;
++ return;
++ }
++
++ ret = read_fifo_ep0(ep, req);
++ if (ret) {
++ usb_set((S3C_UDC_EP0_CSR_SOPKTRDY | S3C_UDC_EP0_CSR_DE),
++ S3C_UDC_EP0_CSR_REG, 0);
++ dev->ep0state = WAIT_FOR_SETUP;
++ first_time = 1;
++ done(ep, req, 0);
++ return;
++ }
++ usb_set(S3C_UDC_EP0_CSR_SOPKTRDY, S3C_UDC_EP0_CSR_REG, 0);
++}
++
++/*
++ * DATA_STATE_XMIT
++ */
++static int s3c_ep0_write(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret, need_zlp = 0;
++
++ DEBUG_EP0("%s: %x\n", __FUNCTION__);
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ if (!req) {
++ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
++ return 0;
++ }
++
++ if (req->req.length == 0) {
++ usb_set((S3C_UDC_EP0_CSR_IPKRDY | S3C_UDC_EP0_CSR_DE),
++ S3C_UDC_EP0_CSR_REG, 0);
++ dev->ep0state = WAIT_FOR_SETUP;
++ done(ep, req, 0);
++ return 1;
++ }
++
++ if (req->req.length - req->req.actual == EP0_FIFO_SIZE) {
++ /* Next write will end with the packet size, */
++ /* so we need Zero-length-packet */
++ need_zlp = 1;
++ }
++
++ ret = write_fifo_ep0(ep, req);
++
++ if ((ret == 1) && !need_zlp) {
++ /* Last packet */
++ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
++
++ usb_set((S3C_UDC_EP0_CSR_IPKRDY | S3C_UDC_EP0_CSR_DE),
++ S3C_UDC_EP0_CSR_REG, 0);
++ dev->ep0state = WAIT_FOR_SETUP;
++ } else {
++ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
++ usb_set(S3C_UDC_EP0_CSR_IPKRDY, S3C_UDC_EP0_CSR_REG, 0);
++ }
++
++ if (need_zlp) {
++ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
++ dev->ep0state = DATA_STATE_NEED_ZLP;
++ }
++
++ if(ret)
++ done(ep, req, 0);
++
++ return 1;
++}
++
++#if 0
++static int s3c_handle_get_status(struct s3c_udc *dev,
++ struct usb_ctrlrequest *ctrl)
++{
++ struct s3c_ep *ep0 = &dev->ep[0];
++ struct s3c_ep *qep;
++ int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
++ u16 val = 0;
++
++ if (reqtype == USB_RECIP_INTERFACE) {
++ /* This is not supported.
++ * And according to the USB spec, this one does nothing..
++ * Just return 0
++ */
++ DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
++ } else if (reqtype == USB_RECIP_DEVICE) {
++ DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
++ val |= (1 << 0); /* Self powered */
++ /*val |= (1<<1); *//* Remote wakeup */
++ } else if (reqtype == USB_RECIP_ENDPOINT) {
++ int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
++
++ DEBUG_SETUP
++ ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
++ ep_num, ctrl->wLength);
++
++ if (ctrl->wLength > 2 || ep_num > 3)
++ return -EOPNOTSUPP;
++
++ qep = &dev->ep[ep_num];
++ if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
++ && ep_index(qep) != 0) {
++ return -EOPNOTSUPP;
++ }
++
++ /* Return status on next IN token */
++ switch (qep->ep_type) {
++ case ep_control:
++ val =
++ (usb_read(qep->csr1, ep_index(qep)) & S3C_UDC_EP0_CSR_SENDSTL) ==
++ S3C_UDC_EP0_CSR_SENDSTL;
++ break;
++ case ep_bulk_in:
++ case ep_interrupt:
++ val = (usb_read(qep->csr1, ep_index(qep))
++ & S3C_UDC_ICSR1_SENDSTL) == S3C_UDC_ICSR1_SENDSTL;
++ break;
++ case ep_bulk_out:
++ val = (usb_read(qep->csr1, ep_index(qep))
++ & S3C_UDC_OCSR1_SENDSTL) == S3C_UDC_OCSR1_SENDSTL;
++ break;
++ }
++
++ /* Back to EP0 index */
++
++ DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
++ ctrl->wIndex, val);
++ } else {
++ DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
++ return -EOPNOTSUPP;
++ }
++
++ /* Clear "out packet ready" */
++ usb_set((S3C_UDC_EP0_CSR_SOPKTRDY), S3C_UDC_EP0_CSR_REG, 0);
++ /* Put status to FIFO */
++ s3c_fifo_write(ep0, (u8 *) & val, sizeof(val));
++ /* Issue "In packet ready" */
++ usb_set((S3C_UDC_EP0_CSR_IPKRDY | S3C_UDC_EP0_CSR_DE),
++ S3C_UDC_EP0_CSR_REG, 0);
++
++ return 0;
++}
++#endif
++
++/*
++ * WAIT_FOR_SETUP (OUT_PKT_RDY)
++ * - read data packet from EP0 FIFO
++ * - decode command
++ * - if error
++ * set S3C_UDC_EP0_CSR_SOPKTRDY | S3C_UDC_EP0_CSR_DE | S3C_UDC_EP0_CSR_SENDSTL bits
++ * - else
++ * set S3C_UDC_EP0_CSR_SOPKTRDY | S3C_UDC_EP0_CSR_DE bits
++ */
++static void s3c_ep0_setup(struct s3c_udc *dev, u32 csr)
++{
++ struct s3c_ep *ep = &dev->ep[0];
++ struct usb_ctrlrequest ctrl;
++ int i, bytes, is_in;
++
++ DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
++
++ /* Nuke all previous transfers */
++ nuke(ep, -EPROTO);
++
++ /* read control req from fifo (8 bytes) */
++ bytes = s3c_fifo_read(ep, (unsigned char *)&ctrl, 8);
++ DEBUG_SETUP("Read CTRL REQ %d bytes\n", bytes);
++ DEBUG_SETUP("CTRL.bRequestType = 0x%x (is_in %d)\n", ctrl.bRequestType,
++ ctrl.bRequestType & USB_DIR_IN);
++ DEBUG_SETUP("CTRL.bRequest = 0x%x\n", ctrl.bRequest);
++ DEBUG_SETUP("CTRL.wLength = 0x%x\n", ctrl.wLength);
++ DEBUG_SETUP("CTRL.wValue = 0x%x (%d)\n", ctrl.wValue, ctrl.wValue >> 8);
++ DEBUG_SETUP("CTRL.wIndex = 0x%x\n", ctrl.wIndex);
++
++ /* Set direction of EP0 */
++ if (likely(ctrl.bRequestType & USB_DIR_IN)) {
++ ep->bEndpointAddress |= USB_DIR_IN;
++ is_in = 1;
++ } else {
++ ep->bEndpointAddress &= ~USB_DIR_IN;
++ is_in = 0;
++ }
++
++ dev->req_pending = 1;
++
++ /* Handle some SETUP packets ourselves */
++ switch (ctrl.bRequest) {
++ case USB_REQ_SET_ADDRESS:
++ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
++ break;
++
++ DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
++ udc_set_address(dev, ctrl.wValue);
++ usb_set((S3C_UDC_EP0_CSR_SOPKTRDY | S3C_UDC_EP0_CSR_DE), S3C_UDC_EP0_CSR_REG, 0);
++ return;
++#if 0
++ case USB_REQ_GET_STATUS:
++ DEBUG_SETUP("USB_REQ_GET_STATUS \n");
++ if (s3c_handle_get_status(dev, &ctrl) == 0)
++ return;
++#endif
++ default:
++ DEBUG_SETUP(" DFAULT\n");
++ break;
++ }
++
++ if (likely(dev->driver)) {
++ /* device-2-host (IN) or no data setup command, process immediately */
++ spin_unlock(&dev->lock);
++ i = dev->driver->setup(&dev->gadget, &ctrl);
++ spin_lock(&dev->lock);
++
++ if (i < 0) {
++ /* setup processing failed, force stall */
++ printk(" --> ERROR: gadget setup FAILED (stalling), \
++ setup returned %d\n", i);
++ usb_set((S3C_UDC_EP0_CSR_SOPKTRDY | S3C_UDC_EP0_CSR_DE
++ |S3C_UDC_EP0_CSR_SENDSTL), S3C_UDC_EP0_CSR_REG, 0);
++ /* ep->stopped = 1; */
++ dev->ep0state = WAIT_FOR_SETUP;
++ }
++ }
++}
++
++/*
++ * DATA_STATE_NEED_ZLP
++ */
++static void s3c_ep0_in_zlp(struct s3c_udc *dev, u32 csr)
++{
++ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
++
++ usb_set((S3C_UDC_EP0_CSR_IPKRDY | S3C_UDC_EP0_CSR_DE),
++ S3C_UDC_EP0_CSR_REG, 0);
++ dev->ep0state = WAIT_FOR_SETUP;
++}
++
++/*
++ * handle ep0 interrupt
++ */
++static void s3c_handle_ep0(struct s3c_udc *dev)
++{
++ struct s3c_ep *ep = &dev->ep[0];
++ u32 csr;
++
++ csr = usb_read(S3C_UDC_EP0_CSR_REG, ep_index(ep));
++
++ DEBUG_EP0("%s: csr = %x\n", __FUNCTION__, csr);
++
++ /*
++ * if SENT_STALL is set
++ * - clear the SENT_STALL bit
++ */
++ if (csr & S3C_UDC_EP0_CSR_SENTSTL) {
++ printk("%s: S3C_UDC_EP0_CSR_SENTSTL is set: %x\n", __FUNCTION__, csr);
++ usb_write(0, S3C_UDC_EP0_CSR_REG, 0);
++ nuke(ep, -ECONNABORTED);
++ dev->ep0state = WAIT_FOR_SETUP;
++ return;
++ }
++
++ /*
++ * if SETUP_END is set
++ * - abort the last transfer
++ * - set SERVICED_SETUP_END_BIT
++ */
++ if (csr & S3C_UDC_EP0_CSR_SE) {
++ DEBUG_EP0("%s: S3C_UDC_EP0_CSR_SE is set: %x\n", __FUNCTION__, csr);
++
++ usb_clear(0xc0, S3C_UDC_EP0_CSR_REG, 0);
++ usb_set(S3C_UDC_EP0_CSR_SSE, S3C_UDC_EP0_CSR_REG, 0);
++
++ nuke(ep, 0);
++ dev->ep0state = WAIT_FOR_SETUP;
++ }
++
++ /*
++ * if a transfer is in progress && IN_PKT_RDY and OUT_PKT_RDY are clear
++ * - fill EP0 FIFO
++ * - if last packet
++ * - set IN_PKT_RDY | DATA_END
++ * - else
++ * set IN_PKT_RDY
++ */
++ if (!(csr & (S3C_UDC_EP0_CSR_IPKRDY | S3C_UDC_EP0_CSR_OPKRDY))) {
++ switch (dev->ep0state) {
++ case DATA_STATE_XMIT:
++ DEBUG_EP0("continue with DATA_STATE_XMIT\n");
++ s3c_ep0_write(dev);
++ return;
++ case DATA_STATE_NEED_ZLP:
++ DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
++ s3c_ep0_in_zlp(dev, csr);
++ return;
++ default:
++ /* Stall? */
++ DEBUG_EP0("Odd state!! state = %s\n",
++ state_names[dev->ep0state]);
++ dev->ep0state = WAIT_FOR_SETUP;
++ /* nuke(ep, 0); */
++ /* usb_set(S3C_UDC_EP0_CSR_SENDSTL, ep->csr1, ep_index(ep)); */
++ break;
++ }
++ }
++
++ /*
++ * if S3C_UDC_EP0_CSR_OPKRDY is set
++ * - read data packet from EP0 FIFO
++ * - decode command
++ * - if error
++ * set SERVICED_OUT_PKT_RDY | DATA_END bits | SEND_STALL
++ * - else
++ * set SERVICED_OUT_PKT_RDY | DATA_END bits
++ */
++ if (csr & S3C_UDC_EP0_CSR_OPKRDY) {
++ switch (dev->ep0state) {
++ case WAIT_FOR_SETUP:
++ DEBUG_EP0("WAIT_FOR_SETUP\n");
++ s3c_ep0_setup(dev, csr);
++ break;
++
++ case DATA_STATE_RECV:
++ DEBUG_EP0("DATA_STATE_RECV\n");
++ s3c_ep0_read(dev);
++ break;
++
++ default:
++ /* send stall? */
++ DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
++ dev->ep0state);
++ break;
++ }
++ }
++}
++
++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
++{
++ if (ep_is_in(ep)) {
++ /* Clear "out packet ready" */
++ usb_set(S3C_UDC_EP0_CSR_SOPKTRDY, S3C_UDC_EP0_CSR_REG, 0);
++ udelay(5); // time to settle things down
++
++ dev->ep0state = DATA_STATE_XMIT;
++ s3c_ep0_write(dev);
++ } else {
++ dev->ep0state = DATA_STATE_RECV;
++ s3c_ep0_read(dev);
++ }
++}
++
++/* ---------------------------------------------------------------------------
++ * device-scoped parts of the api to the usb controller hardware
++ * ---------------------------------------------------------------------------
++ */
++
++static int s3c_udc_get_frame(struct usb_gadget *_gadget)
++{
++ u32 frame1 = usb_read(S3C_UDC_FRAME_NUM1_REG, 0);/* Least significant 8 bits */
++ u32 frame2 = usb_read(S3C_UDC_FRAME_NUM1_REG, 0);/* Most significant 3 bits */
++ DEBUG("%s, %p\n", __FUNCTION__, _gadget);
++ return ((frame2 & 0x07) << 8) | (frame1 & 0xff);
++}
++
++static int s3c_udc_wakeup(struct usb_gadget *_gadget)
++{
++ return -ENOTSUPP;
++}
++
++static const struct usb_gadget_ops s3c_udc_ops = {
++ .get_frame = s3c_udc_get_frame,
++ .wakeup = s3c_udc_wakeup,
++ /* current versions must always be self-powered */
++};
++
++static void nop_release(struct device *dev)
++{
++ DEBUG("%s %s\n", __FUNCTION__, dev->bus_id);
++}
++
++static struct s3c_udc memory = {
++ .usb_address = 0,
++
++ .gadget = {
++ .ops = &s3c_udc_ops,
++ .ep0 = &memory.ep[0].ep,
++ .name = driver_name,
++ .dev = {
++ .bus_id = "gadget",
++ .release = nop_release,
++ },
++ },
++
++ /* control endpoint */
++ .ep[0] = {
++ .ep = {
++ .name = ep0name,
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP0_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = 0,
++ .bmAttributes = 0,
++
++ .ep_type = ep_control,
++ .fifo = S3C_UDC_EP0_FIFO_REG,
++ .csr1 = S3C_UDC_EP0_CSR_REG,
++ .csr2 = S3C_UDC_EP0_CSR_REG,
++ },
++
++ /* first group of endpoints */
++ .ep[1] = {
++ .ep = {
++ .name = "ep1-bulk",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = 1,
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++
++ .ep_type = ep_bulk_out,
++ .fifo = S3C_UDC_EP1_FIFO_REG,
++ .csr1 = S3C_UDC_OUT_CSR1_REG,
++ .csr2 = S3C_UDC_OUT_CSR2_REG,
++ },
++
++ .ep[2] = {
++ .ep = {
++ .name = "ep2-bulk",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 2,
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++
++ .ep_type = ep_bulk_in,
++ .fifo = S3C_UDC_EP2_FIFO_REG,
++ .csr1 = S3C_UDC_IN_CSR1_REG,
++ .csr2 = S3C_UDC_IN_CSR2_REG,
++ },
++
++ .ep[3] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep3-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 3,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = S3C_UDC_EP3_FIFO_REG,
++ .csr1 = S3C_UDC_IN_CSR1_REG,
++ .csr2 = S3C_UDC_IN_CSR2_REG,
++ },
++ .ep[4] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep4-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 4,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = S3C_UDC_EP4_FIFO_REG,
++ .csr1 = S3C_UDC_IN_CSR1_REG,
++ .csr2 = S3C_UDC_IN_CSR2_REG,
++ },
++};
++
++/*
++ * probe - binds to the platform device
++ */
++static int s3c_udc_probe(struct platform_device *pdev)
++{
++ struct s3c_udc *dev = &memory;
++ int retval;
++
++ DEBUG("%s: %p\n", __FUNCTION__, pdev);
++
++ GPIO_INIT;
++
++ spin_lock_init(&dev->lock);
++ dev->dev = &pdev;
++
++ device_initialize(&dev->gadget.dev);
++ dev->gadget.dev.parent = &pdev->dev;
++
++ //dev->gadget.is_dualspeed = 1; // Hack only
++ dev->gadget.is_otg = 0;
++ dev->gadget.is_a_peripheral = 0;
++ dev->gadget.b_hnp_enable = 0;
++ dev->gadget.a_hnp_support = 0;
++ dev->gadget.a_alt_hnp_support = 0;
++
++ the_controller = dev;
++ platform_set_drvdata(pdev, dev);
++
++ udc_reinit(dev);
++
++ local_irq_disable();
++
++ /* irq setup after old hardware state is cleaned up */
++ retval =
++ request_irq(IRQ_USBD, s3c_udc_irq, SA_INTERRUPT, driver_name,
++ dev);
++ if (retval != 0) {
++ DEBUG(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name,
++ IRQ_USBD, retval);
++ return -EBUSY;
++ }
++
++ disable_irq(IRQ_USBD);
++
++ udc_enable(dev);
++ reconfig_usbd();
++
++ local_irq_enable();
++ create_proc_files();
++
++ return retval;
++}
++
++static int s3c_udc_remove(struct platform_device *pdev)
++{
++ struct s3c_udc *dev = platform_get_drvdata(pdev);
++
++ DEBUG("%s: %p\n", __FUNCTION__, pdev);
++
++ udc_disable(dev);
++ remove_proc_files();
++ usb_gadget_unregister_driver(dev->driver);
++
++ free_irq(IRQ_USBD, dev);
++
++ platform_set_drvdata(pdev, 0);
++
++ the_controller = 0;
++
++ return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static struct platform_driver s3c_udc_driver = {
++ .probe = s3c_udc_probe,
++ .remove = s3c_udc_remove,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-udc",
++ },
++};
++
++
++static int __init s3c_udc_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&s3c_udc_driver);
++ if(!ret)
++ printk("Loaded %s version %s\n", driver_name, DRIVER_VERSION);
++
++ return ret;
++}
++
++static void __exit s3c_udc_exit(void)
++{
++ platform_driver_unregister(&s3c_udc_driver);
++ printk("Unloaded %s version %s\n", driver_name, DRIVER_VERSION);
++}
++
++module_init(s3c_udc_init);
++module_exit(s3c_udc_exit);
++
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_AUTHOR("Samsung");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/usb/gadget/s3c-udc-hs.c b/drivers/usb/gadget/s3c-udc-hs.c
+new file mode 100644
+index 0000000..839b392
+--- /dev/null
++++ b/drivers/usb/gadget/s3c-udc-hs.c
+@@ -0,0 +1,1959 @@
++/*
++ * drivers/usb/gadget/s3c-udc-hs.c
++ * Samsung S3C on-chip full/high speed USB device controllers
++ *
++ * $Id: s3c-udc-hs.c,v 1.2 2008/03/05 02:14:45 ihlee215 Exp $*
++ *
++ * Copyright (C) 2006 for Samsung Electronics
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <asm/irq.h>
++#include <asm/arch/regs-irq.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c2443-clock.h>
++#include <asm/arch/regs-udc-hs.h>
++#include "s3c-udc.h"
++
++#undef DEBUG_S3C_UDC_SETUP
++#undef DEBUG_S3C_UDC_EP0
++#undef DEBUG_S3C_UDC
++
++// USB Device DMA support
++#define RX_DMA_MODE 0
++#define TX_DMA_MODE 0
++static int tx_dmaStart = 0;
++static int rx_dmaStart = 0;
++
++
++#ifdef DEBUG_S3C_UDC_SETUP
++static char *state_names[] = {
++ "WAIT_FOR_SETUP",
++ "DATA_STATE_XMIT",
++ "DATA_STATE_NEED_ZLP",
++ "WAIT_FOR_OUT_STATUS",
++ "DATA_STATE_RECV"
++ };
++#define DEBUG_SETUP(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG_SETUP(fmt,args...) do {} while(0)
++#endif
++
++#ifdef DEBUG_S3C_UDC_EP0
++#define DEBUG_EP0(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG_EP0(fmt,args...) do {} while(0)
++#endif
++
++#ifdef DEBUG_S3C_UDC
++#define DEBUG(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG(fmt,args...) do {} while(0)
++#endif
++
++#define DRIVER_DESC "Samsung Dual-speed USB Device Controller"
++#define DRIVER_VERSION __DATE__
++
++struct s3c_udc *the_controller;
++
++static const char driver_name[] = "s3c-udc";
++static const char driver_desc[] = DRIVER_DESC;
++static const char ep0name[] = "ep0-control";
++
++// Max packet size
++static u32 ep0_fifo_size = 64;
++static u32 ep_fifo_size = 512;
++static u32 ep_fifo_size2 = 1024;
++
++/*
++ Local declarations.
++*/
++static int s3c_ep_enable(struct usb_ep *ep,
++ const struct usb_endpoint_descriptor *);
++static int s3c_ep_disable(struct usb_ep *ep);
++static struct usb_request *s3c_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
++static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
++
++static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
++static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
++static int s3c_set_halt(struct usb_ep *ep, int);
++static int s3c_fifo_status(struct usb_ep *ep);
++static void s3c_fifo_flush(struct usb_ep *ep);
++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
++static void s3c_handle_ep0(struct s3c_udc *dev);
++
++static void done(struct s3c_ep *ep, struct s3c_request *req,
++ int status);
++static void stop_activity(struct s3c_udc *dev,
++ struct usb_gadget_driver *driver);
++static int udc_enable(struct s3c_udc *dev);
++static void udc_set_address(struct s3c_udc *dev, unsigned char address);
++static void reconfig_usbd(void);
++
++static __inline__ u32 usb_read(u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ return __raw_readl(port);
++}
++
++static __inline__ void usb_write(u32 val, u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ __raw_writel(val, port);
++}
++
++static __inline__ void usb_set(u32 val, u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ __raw_writel(__raw_readl(port) | val, port);
++}
++
++static __inline__ void usb_clear(u32 val, u32 port, u8 ind)
++{
++ __raw_writel(ind, S3C_UDC_INDEX_REG);
++ __raw_writel(__raw_readl(port) & ~val, port);
++}
++
++static struct usb_ep_ops s3c_ep_ops = {
++ .enable = s3c_ep_enable,
++ .disable = s3c_ep_disable,
++
++ .alloc_request = s3c_alloc_request,
++ .free_request = s3c_free_request,
++
++ .queue = s3c_queue,
++ .dequeue = s3c_dequeue,
++
++ .set_halt = s3c_set_halt,
++ .fifo_status = s3c_fifo_status,
++ .fifo_flush = s3c_fifo_flush,
++};
++
++
++/* Inline code */
++static __inline__ int write_packet(struct s3c_ep *ep,
++ struct s3c_request *req, int max)
++{
++ u16 *buf;
++ int length, count;
++ u32 fifo = ep->fifo;
++
++ buf = req->req.buf + req->req.actual;
++ prefetch(buf);
++
++ length = req->req.length - req->req.actual;
++ length = min(length, max);
++ req->req.actual += length;
++
++ DEBUG("%s: Write %d (max %d), fifo=0x%x\n",
++ __FUNCTION__, length, max, fifo);
++
++ usb_write(length, (u32) S3C_UDC_BYTE_WRITE_CNT_REG, ep_index(ep));
++
++
++ for (count=0;count<length;count+=2) {
++ __raw_writel(*buf++, fifo);
++ }
++
++ return length;
++}
++
++#ifdef CONFIG_USB_GADGET_DEBUG_FILES
++
++static const char proc_node_name[] = "driver/udc";
++
++static int
++udc_proc_read(char *page, char **start, off_t off, int count,
++ int *eof, void *_dev)
++{
++ char *buf = page;
++ struct s3c_udc *dev = _dev;
++ char *next = buf;
++ unsigned size = count;
++ unsigned long flags;
++ int t;
++
++ if (off != 0)
++ return 0;
++
++ local_irq_save(flags);
++
++ /* basic device status */
++ t = scnprintf(next, size,
++ DRIVER_DESC "\n"
++ "%s version: %s\n"
++ "Gadget driver: %s\n"
++ "\n",
++ driver_name, DRIVER_VERSION,
++ dev->driver ? dev->driver->driver.name : "(none)");
++ size -= t;
++ next += t;
++
++ local_irq_restore(flags);
++ *eof = 1;
++ return count - size;
++}
++
++#define create_proc_files() \
++ create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
++#define remove_proc_files() \
++ remove_proc_entry(proc_node_name, NULL)
++
++#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
++
++#define create_proc_files() do {} while (0)
++#define remove_proc_files() do {} while (0)
++
++#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
++
++/*
++ * udc_disable - disable USB device controller
++ */
++static void udc_disable(struct s3c_udc *dev)
++{
++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev);
++
++ udc_set_address(dev, 0);
++
++ dev->ep0state = WAIT_FOR_SETUP;
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++ dev->usb_address = 0;
++ __raw_writel(__raw_readl(S3C_PWRCFG)&~(1<<4), S3C_PWRCFG);
++}
++
++/*
++ * udc_reinit - initialize software state
++ */
++static void udc_reinit(struct s3c_udc *dev)
++{
++ u32 i;
++
++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev);
++
++ /* device/ep0 records init */
++ INIT_LIST_HEAD(&dev->gadget.ep_list);
++ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
++ dev->ep0state = WAIT_FOR_SETUP;
++
++ /* basic endpoint records init */
++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
++ struct s3c_ep *ep = &dev->ep[i];
++
++ if (i != 0)
++ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
++
++ ep->desc = 0;
++ ep->stopped = 0;
++ INIT_LIST_HEAD(&ep->queue);
++ ep->pio_irqs = 0;
++ }
++
++ /* the rest was statically initialized, and is read-only */
++}
++
++#define BYTES2MAXP(x) (x / 8)
++#define MAXP2BYTES(x) (x * 8)
++
++/* until it's enabled, this UDC should be completely invisible
++ * to any USB host.
++ */
++static int udc_enable(struct s3c_udc *dev)
++{
++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev);
++
++ /* if reset by sleep wakeup, control the retention I/O cell */
++ if (__raw_readl(S3C_RSTSTAT) & 0x8)
++ __raw_writel(__raw_readl(S3C_RSTCON)|(1<<16), S3C_RSTCON);
++
++
++ /* USB Port is Normal mode */
++ __raw_writel(__raw_readl(S3C2410_MISCCR)&~(1<<12), S3C2410_MISCCR);
++
++ /* PHY power enable */
++ __raw_writel(__raw_readl(S3C_PWRCFG)|(1<<4), S3C_PWRCFG);
++
++ /* USB device 2.0 must reset like bellow,
++ * 1st phy reset and after at least 10us, func_reset & host reset
++ * phy reset can reset bellow registers.
++ */
++ /* PHY 2.0 S/W reset */
++ __raw_writel((0<<2)|(0<<1)|(1<<0), S3C_URSTCON);
++ udelay(20); /* phy reset must be asserted for at 10us */
++
++ /*Function 2.0, Host 1.1 S/W reset*/
++ __raw_writel((1<<2)|(1<<1)|(0<<0), S3C_URSTCON);
++ __raw_writel((0<<2)|(0<<1)|(0<<0), S3C_URSTCON);
++
++ /* 48Mhz,Crystal,External X-tal,device */
++ __raw_writel((0<<3)|(0<<2)|(1<<1)|(0<<0), S3C_PHYCTRL);
++
++ /* 48Mhz clock on ,PHY2.0 analog block power on
++ * XO block power on,XO block power in suspend mode,
++ * PHY 2.0 Pll power on ,suspend signal for save mode disable
++ */
++ __raw_writel((1<<31)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0), S3C_PHYPWR);
++
++ /* D+ pull up disable(VBUS detect), USB2.0 Function clock Enable,
++ * USB1.1 HOST disable, USB2.0 PHY test enable
++ */
++ __raw_writel((0<<31)|(1<<2)|(0<<1)|(1<<0), S3C_UCLKCON);
++
++ __raw_writel(IRQ_USBD, S3C2410_INTPND);
++ __raw_writel(IRQ_USBD, S3C2410_SRCPND);
++
++ reconfig_usbd();
++
++ __raw_writel(__raw_readl(S3C2410_INTMSK)&~(IRQ_USBD), S3C2410_INTMSK);
++
++ /* D+ pull up , USB2.0 Function clock Enable,
++ * USB1.1 HOST disable,USB2.0 PHY test enable
++ */
++ __raw_writel((1<<31)|(1<<2)|(0<<1)|(1<<0), S3C_UCLKCON);
++
++ DEBUG_SETUP("S3C2443 USB Controller Core Initialized\n");
++
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++
++ return 0;
++}
++
++/*
++ Register entry point for the peripheral controller driver.
++*/
++int usb_gadget_register_driver(struct usb_gadget_driver *driver)
++{
++ struct s3c_udc *dev = the_controller;
++ int retval;
++
++ DEBUG_SETUP("%s: %s\n", __FUNCTION__, driver->driver.name);
++
++ if (!driver
++ || (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
++ || !driver->bind
++ || !driver->unbind || !driver->disconnect || !driver->setup)
++ return -EINVAL;
++ if (!dev)
++ return -ENODEV;
++ if (dev->driver)
++ return -EBUSY;
++
++ /* first hook up the driver ... */
++ dev->driver = driver;
++ dev->gadget.dev.driver = &driver->driver;
++ retval = device_add(&dev->gadget.dev);
++
++ if(retval) { /* TODO */
++ printk("target device_add failed, error %d\n", retval);
++ return retval;
++ }
++
++ retval = driver->bind(&dev->gadget);
++ if (retval) {
++ printk("%s: bind to driver %s --> error %d\n", dev->gadget.name,
++ driver->driver.name, retval);
++ device_del(&dev->gadget.dev);
++
++ dev->driver = 0;
++ dev->gadget.dev.driver = 0;
++ return retval;
++ }
++
++ enable_irq(IRQ_USBD);
++
++ printk("Registered gadget driver '%s'\n", driver->driver.name);
++ udc_enable(dev);
++
++ return 0;
++}
++
++EXPORT_SYMBOL(usb_gadget_register_driver);
++
++/*
++ Unregister entry point for the peripheral controller driver.
++*/
++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++{
++ struct s3c_udc *dev = the_controller;
++ unsigned long flags;
++
++ if (!dev)
++ return -ENODEV;
++ if (!driver || driver != dev->driver)
++ return -EINVAL;
++
++ spin_lock_irqsave(&dev->lock, flags);
++ dev->driver = 0;
++ stop_activity(dev, driver);
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ driver->unbind(&dev->gadget);
++ device_del(&dev->gadget.dev);
++
++ disable_irq(IRQ_USBD);
++
++ printk("Unregistered gadget driver '%s'\n", driver->driver.name);
++ return 0;
++}
++
++EXPORT_SYMBOL(usb_gadget_unregister_driver);
++
++/*-------------------------------------------------------------------------*/
++
++/** Write request to FIFO (max write == maxp size)
++ * Return: 0 = still running, 1 = completed, negative = errno
++ */
++static int write_fifo(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 max;
++ unsigned count;
++ int is_last = 0, is_short = 0;
++
++#if TX_DMA_MODE
++ if(tx_dmaStart) return 0;
++ if ((req->req.actual == 0) && (req->req.length > ep->ep.maxpacket) && (!tx_dmaStart)) {
++
++ DEBUG("TX_DMA_Start:: %s: read %s, bytes req %p %d/%d\n",
++ __FUNCTION__, ep->ep.name, req, req->req.actual, req->req.length);
++
++ usb_set(S3C_DMA_ENABLE,
++ (u32) S3C_UDC_FCON_REG, ep_index(ep));
++
++ usb_write(ep->ep.maxpacket, (u32) S3C_UDC_MAXP_REG, ep_index(ep));
++ usb_write(ep->ep.maxpacket, (u32) S3C_UDC_BYTE_WRITE_CNT_REG, ep_index(ep));
++
++ usb_set((u16)req->req.length,
++ (u32) S3C_UDC_DMA_TOTAL_CNT1_REG, ep_index(ep));
++
++ usb_set((u16)((req->req.length)>>16),
++ (u32) S3C_UDC_DMA_TOTAL_CNT2_REG, ep_index(ep));
++
++ usb_set(virt_to_phys(req->req.buf),
++ (u32) S3C_UDC_DMA_MEM_BASE_ADDR_REG, ep_index(ep));
++
++ usb_set(ep->ep.maxpacket,
++ (u32) S3C_UDC_DMA_CNT_REG, ep_index(ep));
++
++ usb_set(ep->ep.maxpacket,
++ (u32) S3C_UDC_DMA_FIFO_CNT_REG, ep_index(ep));
++
++ usb_set(S3C_MAX_BURST_INCR16,
++ (u32) S3C_UDC_DMA_IF_CON_REG, ep_index(ep));
++
++ usb_set(S3C_DMA_FLY_ENABLE|S3C_DMA_TX_START|S3C_USB_DMA_MODE,
++ (u32) S3C_UDC_DMA_CON_REG, ep_index(ep));
++ tx_dmaStart = 1;
++
++ udelay(600);
++
++ }
++ else {
++#endif
++ max = le16_to_cpu(ep->desc->wMaxPacketSize);
++ count = write_packet(ep, req, max);
++
++ /* last packet is usually short (or a zlp) */
++ if (unlikely(count != max))
++ is_last = is_short = 1;
++ else {
++ if (likely(req->req.length != req->req.actual)
++ || req->req.zero)
++ is_last = 0;
++ else
++ is_last = 1;
++ /* interrupt/iso maxpacket may not fill the fifo */
++ is_short = unlikely(max < ep_maxpacket(ep));
++ }
++
++ DEBUG("%s: wrote %s %d bytes%s%s req %p %d/%d\n", __FUNCTION__,
++ ep->ep.name, count,
++ is_last ? "/L" : "", is_short ? "/S" : "",
++ req, req->req.actual, req->req.length);
++
++#if TX_DMA_MODE
++ }
++#endif
++
++ /* requests complete when all IN data is in the FIFO */
++ if (is_last) {
++ if(!ep_index(ep)){
++ DEBUG("%s: --> Error EP0 must not come here!\n",
++ __FUNCTION__);
++ BUG();
++ }
++ done(ep, req, 0);
++ return 1;
++ }
++
++ return 0;
++}
++
++
++
++/** Read to request from FIFO (max read == bytes in fifo)
++ * Return: 0 = still running, 1 = completed, negative = errno
++ */
++static int read_fifo(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 csr;
++ u16 *buf;
++ unsigned bufferspace, count, count_bytes, is_short = 0;
++ u32 fifo = ep->fifo;
++
++ csr = usb_read( (u32) S3C_UDC_EP_STATUS_REG, ep_index(ep));
++
++ /* make sure there's a packet in the FIFO. */
++ if (!(csr & S3C_UDC_EP_RX_SUCCESS)) {
++ DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ buf = req->req.buf + req->req.actual;
++ prefetchw(buf);
++ bufferspace = req->req.length - req->req.actual;
++
++ /* read all bytes from this packet */
++ count = usb_read((u32) S3C_UDC_BYTE_READ_CNT_REG, ep_index(ep));
++ if (csr & S3C_UDC_EP_LWO)
++ count_bytes = count * 2 -1;
++ else
++ count_bytes = count * 2;
++
++
++#if RX_DMA_MODE
++ if(rx_dmaStart) return 0;
++
++ if ((req->req.actual == 0) && (req->req.length > ep->ep.maxpacket) && (!rx_dmaStart)) {
++
++ DEBUG("RX_DMA_Start :: %s: read %s, %d bytes req %p %d/%d CSR::0x%x\n",
++ __FUNCTION__, ep->ep.name, count_bytes, req, req->req.actual, req->req.length, csr);
++
++
++ usb_set(S3C_DMA_ENABLE,
++ (u32) S3C_UDC_FCON_REG, ep_index(ep));
++
++ usb_set((u16)req->req.length,
++ (u32) S3C_UDC_DMA_TOTAL_CNT1_REG, ep_index(ep));
++
++ usb_set((u16)((req->req.length)>>16),
++ (u32) S3C_UDC_DMA_TOTAL_CNT2_REG, ep_index(ep));
++
++ usb_set(ep->ep.maxpacket,
++ (u32) S3C_UDC_DMA_CNT_REG, ep_index(ep));
++ //usb_set(512,
++ //(u32) S3C_UDC_DMA_FIFO_CNT_REG, ep_index(ep));
++
++ usb_set(S3C_MAX_BURST_INCR16,
++ (u32) S3C_UDC_DMA_IF_CON_REG, ep_index(ep));
++
++ usb_set(virt_to_phys(buf),
++ (u32) S3C_UDC_DMA_MEM_BASE_ADDR_REG, ep_index(ep));
++
++ usb_set(S3C_DMA_FLY_ENABLE|S3C_DMA_RX_START|S3C_USB_DMA_MODE,
++ (u32) S3C_UDC_DMA_CON_REG, ep_index(ep));
++ rx_dmaStart = 1;
++
++
++ }
++ else {
++#endif
++ req->req.actual += min(count_bytes, bufferspace);
++
++ is_short = (count_bytes < ep->ep.maxpacket);
++ DEBUG("%s: read %s, %d bytes%s req %p %d/%d\n",
++ __FUNCTION__,
++ ep->ep.name, count_bytes,
++ is_short ? "/S" : "", req, req->req.actual, req->req.length);
++
++ while (likely(count-- != 0)) {
++ u16 byte = (u16) __raw_readl(fifo);
++
++ if (unlikely(bufferspace == 0)) {
++ /* this happens when the driver's buffer
++ * is smaller than what the host sent.
++ * discard the extra data.
++ */
++ if (req->req.status != -EOVERFLOW)
++ printk("%s overflow %d\n", ep->ep.name, count);
++ req->req.status = -EOVERFLOW;
++ } else {
++ *buf++ = byte;
++ bufferspace--;
++ }
++ }
++
++#if RX_DMA_MODE
++ }
++#endif
++
++ /* completion */
++ if (is_short || req->req.actual == req->req.length) {
++ done(ep, req, 0);
++ return 1;
++ }
++
++ /* finished that packet. the next one may be waiting... */
++ return 0;
++}
++
++/*
++ * done - retire a request; caller blocked irqs
++ */
++static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
++{
++ unsigned int stopped = ep->stopped;
++
++ DEBUG("%s: %p\n", __FUNCTION__, ep);
++ list_del_init(&req->queue);
++
++ if (likely(req->req.status == -EINPROGRESS))
++ req->req.status = status;
++ else
++ status = req->req.status;
++
++ if (status && status != -ESHUTDOWN)
++ DEBUG("complete %s req %p stat %d len %u/%u\n",
++ ep->ep.name, &req->req, status,
++ req->req.actual, req->req.length);
++
++ /* don't modify queue heads during completion callback */
++ ep->stopped = 1;
++
++ spin_unlock(&ep->dev->lock);
++ req->req.complete(&ep->ep, &req->req);
++ spin_lock(&ep->dev->lock);
++
++ ep->stopped = stopped;
++}
++
++/*
++ * nuke - dequeue ALL requests
++ */
++void nuke(struct s3c_ep *ep, int status)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s: %p\n", __FUNCTION__, ep);
++
++ /* called with irqs blocked */
++ while (!list_empty(&ep->queue)) {
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ done(ep, req, status);
++ }
++}
++
++/**
++ * s3c_in_epn - handle IN interrupt
++ */
++static void s3c_in_epn(struct s3c_udc *dev, u32 ep_idx)
++{
++ u32 csr;
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req;
++
++ csr = usb_read((u32) S3C_UDC_EP_STATUS_REG, ep_idx);
++ DEBUG("%s: S3C_UDC_EP%d_STATUS_REG=0x%x\n", __FUNCTION__, ep_idx, csr);
++
++ if (csr & S3C_UDC_EP_STALL) {
++ DEBUG("%s: S3C_UDC_EP_STALL\n", __FUNCTION__);
++ usb_set(S3C_UDC_EP_STALL, (u32) S3C_UDC_EP_STATUS_REG, ep_idx);
++ return;
++ }
++
++ if (!ep->desc) {
++ DEBUG("%s: NO EP DESC\n", __FUNCTION__);
++ return;
++ }
++
++
++ if (csr & S3C_UDC_EP_DTCZ) {
++ DEBUG("%s: TX_DMA :: DMA Total Count Zero:: S3C_UDC_EP%d_STATUS_REG=0x%x\n",
++ __FUNCTION__, ep_index(ep), csr);
++
++ tx_dmaStart = 0;
++ usb_set(S3C_DMA_DISABLE,
++ (u32) S3C_UDC_FCON_REG, ep_idx);
++
++ usb_set(S3C_DMA_TX_STOP|S3C_USB_INT_MODE,
++ (u32) S3C_UDC_DMA_CON_REG, ep_idx);
++
++ usb_set(S3C_UDC_EP_DTCZ, (u32) S3C_UDC_EP_STATUS_REG, ep_idx);
++
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next,
++ struct s3c_request, queue);
++ if (unlikely(!req)) {
++ DEBUG("%s: TX_DMA :: NULL REQ\n", __FUNCTION__, ep_idx, req);
++ //return;
++ } else {
++ DEBUG("%s: TX_DMA_DONE - REQ is %p (%d/%d) CSR:0x%x\n", __FUNCTION__, req, req->req.actual, req->req.length, csr);
++ req->req.actual = req->req.length;
++ done(ep, req, 0);
++ }
++
++ }
++
++
++ if (csr & S3C_UDC_EP_TX_SUCCESS) {
++ usb_set(S3C_UDC_EP_TX_SUCCESS,
++ (u32) S3C_UDC_EP_STATUS_REG, ep_idx);
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ if (unlikely(!req)) {
++ DEBUG("%s:NULL REQ :: EP_TX_SUCCESS, req = %p CSR:0x%x\n", __FUNCTION__, req, csr);
++ return;
++ }
++ else {
++ DEBUG("%s: EP_TX_SUCCESS, req = %p CSR:0x%x\n", __FUNCTION__, req, csr);
++ if ((write_fifo(ep, req)==0) && (csr & S3C_UDC_EP_PSIF_TWO))
++ write_fifo(ep, req);
++
++ }
++ }
++
++}
++
++/* ********************************************************************************************* */
++/* Bulk OUT (recv)
++ */
++
++static void s3c_out_epn(struct s3c_udc *dev, u32 ep_idx)
++{
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req;
++ u32 csr;
++
++ csr=usb_read((u32) S3C_UDC_EP_STATUS_REG, ep_index(ep));
++ DEBUG("%s: S3C_UDC_EP%d_STATUS_REG=0x%x\n",
++ __FUNCTION__, ep_index(ep), csr);
++
++ if (unlikely(!(ep->desc))) {
++ /* Throw packet away.. */
++ printk("%s: No descriptor?!?\n", __FUNCTION__);
++ return;
++ }
++
++ if (csr & S3C_UDC_EP_STALL) {
++ DEBUG("%s: stall sent\n", __FUNCTION__);
++ usb_set(S3C_UDC_EP_STALL, (u32) S3C_UDC_EP_STATUS_REG, ep_idx);
++ return;
++ }
++
++ if (csr & S3C_UDC_EP_FIFO_FLUSH) {
++ DEBUG("%s: fifo flush \n", __FUNCTION__);
++ usb_set(S3C_UDC_EP_FIFO_FLUSH, (u32) S3C_UDC_EP_CON_REG, ep_idx);
++ return;
++ }
++
++
++ if (csr & S3C_UDC_EP_DTCZ) {
++ DEBUG("%s: DMA Total Count Zero:: S3C_UDC_EP%d_STATUS_REG=0x%x\n",
++ __FUNCTION__, ep_index(ep), csr);
++
++ rx_dmaStart = 0;
++ usb_set(S3C_DMA_DISABLE,
++ (u32) S3C_UDC_FCON_REG, ep_idx);
++
++ usb_set(S3C_DMA_RX_STOP|S3C_USB_INT_MODE,
++ (u32) S3C_UDC_DMA_CON_REG, ep_idx);
++
++ usb_set(S3C_UDC_EP_DTCZ, (u32) S3C_UDC_EP_STATUS_REG, ep_idx);
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next,
++ struct s3c_request, queue);
++ if (unlikely(!req)) {
++ DEBUG("RX_DMA :: %s: NULL REQ\n", __FUNCTION__, ep_idx, req);
++ } else {
++ DEBUG("%s : RX_DMA_DONE - REQ : %p\n", __FUNCTION__, req);
++ req->req.actual = req->req.length;
++ done(ep, req, 0);
++ }
++ }
++
++
++ if (csr & S3C_UDC_EP_RX_SUCCESS) {
++ if(!rx_dmaStart) {
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next,
++ struct s3c_request, queue);
++
++ if (unlikely(!req)) {
++ DEBUG("%s: NULL REQ on ISR %d\n", __FUNCTION__, ep_idx);
++ return;
++ } else {
++ if(((read_fifo(ep, req))==0) && (csr & S3C_UDC_EP_PSIF_TWO))
++ read_fifo(ep, req);
++ }
++ }
++ }
++
++}
++
++static void stop_activity(struct s3c_udc *dev,
++ struct usb_gadget_driver *driver)
++{
++ int i;
++
++ /* don't disconnect drivers more than once */
++ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
++ driver = 0;
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++
++ /* prevent new request submissions, kill any outstanding requests */
++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
++ struct s3c_ep *ep = &dev->ep[i];
++ ep->stopped = 1;
++ nuke(ep, -ESHUTDOWN);
++ }
++
++ /* report disconnect; the driver is already quiesced */
++ if (driver) {
++ spin_unlock(&dev->lock);
++ driver->disconnect(&dev->gadget);
++ spin_lock(&dev->lock);
++ }
++
++ /* re-init driver-visible data structures */
++ udc_reinit(dev);
++}
++
++static void reconfig_usbd(void)
++{
++ __raw_writel(0x04, S3C_UDC_EP_DIR_REG); /* EP1:OUT, EP2:IN */
++
++ /* EP0~2 Interrupt enable */
++ __raw_writel(0x7, S3C_UDC_EP_INT_EN_REG);
++
++ __raw_writel(0x0000, S3C_UDC_TEST_REG);
++
++ /* error interrupt enable, 16bit bus, Little format,
++ * suspend&reset enable
++ */
++ __raw_writel(S3C_UDC_DTZIEN_EN|S3C_UDC_RRD_EN
++ |S3C_UDC_SUS_EN|S3C_UDC_RST_EN,
++ S3C_UDC_SYS_CON_REG);
++
++ __raw_writel(0x0000, S3C_UDC_EP0_CON_REG);
++
++ /* EP1, EP2 dual FIFO mode enable */
++ usb_write(0x0080, (u32) S3C_UDC_EP_CON_REG, 1);
++ usb_write(0x0080, (u32) S3C_UDC_EP_CON_REG, 2);
++
++ __raw_writel(0, S3C_UDC_INDEX_REG);
++
++}
++
++void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
++{
++ if (speed == USB_SPEED_HIGH)
++ {
++ ep0_fifo_size = 64;
++ ep_fifo_size = 512;
++ ep_fifo_size2 = 1024;
++ dev->gadget.speed = USB_SPEED_HIGH;
++ }
++ else
++ {
++ ep0_fifo_size = 64;
++ ep_fifo_size = 64;
++ ep_fifo_size2 = 64;
++ dev->gadget.speed = USB_SPEED_FULL;
++ }
++
++ dev->ep[0].ep.maxpacket = ep0_fifo_size;
++ dev->ep[1].ep.maxpacket = ep_fifo_size;
++ dev->ep[2].ep.maxpacket = ep_fifo_size;
++ dev->ep[3].ep.maxpacket = ep_fifo_size;
++ dev->ep[4].ep.maxpacket = ep_fifo_size;
++ dev->ep[5].ep.maxpacket = ep_fifo_size2;
++ dev->ep[6].ep.maxpacket = ep_fifo_size2;
++ dev->ep[7].ep.maxpacket = ep_fifo_size2;
++ dev->ep[8].ep.maxpacket = ep_fifo_size2;
++
++ usb_write(ep0_fifo_size, (u32) S3C_UDC_MAXP_REG, 0);
++ usb_write(ep_fifo_size, (u32) S3C_UDC_MAXP_REG, 1);
++ usb_write(ep_fifo_size, (u32) S3C_UDC_MAXP_REG, 2);
++ usb_write(ep_fifo_size, (u32) S3C_UDC_MAXP_REG, 3);
++ usb_write(ep_fifo_size, (u32) S3C_UDC_MAXP_REG, 4);
++ usb_write(ep_fifo_size2, (u32) S3C_UDC_MAXP_REG, 5);
++ usb_write(ep_fifo_size2, (u32) S3C_UDC_MAXP_REG, 6);
++ usb_write(ep_fifo_size2, (u32) S3C_UDC_MAXP_REG, 7);
++ usb_write(ep_fifo_size2, (u32) S3C_UDC_MAXP_REG, 8);
++
++}
++
++/*
++ * elfin usb client interrupt handler.
++ */
++static irqreturn_t s3c_udc_irq(int irq, void *_dev)
++{
++ struct s3c_udc *dev = _dev;
++ u32 intr_out;
++ u32 intr_in;
++ u32 intr_status, intr_status_chk;
++
++ spin_lock(&dev->lock);
++
++
++ intr_status = __raw_readl(S3C_UDC_SYS_STATUS_REG);
++ intr_out = intr_in = __raw_readl(S3C_UDC_EP_INT_REG);
++
++ DEBUG_SETUP("\n\n%s: S3C_UDC_EP_INT_REG=0x%x, S3C_UDC_SYS_STATUS_REG=0x%x(on state %s)\n",
++ __FUNCTION__, intr_out, intr_status, state_names[dev->ep0state]);
++
++ /* We have only 3 usable eps now */
++ intr_status_chk = intr_status & S3C_UDC_INT_CHECK;
++ intr_in &= (S3C_UDC_INT_EP2 | S3C_UDC_INT_EP0);
++ intr_out &= S3C_UDC_INT_EP1;
++
++
++ if (!intr_out && !intr_in && !intr_status_chk){
++ spin_unlock(&dev->lock);
++ return IRQ_HANDLED;
++ }
++
++ if (intr_status) {
++ if (intr_status & S3C_UDC_INT_VBUSON) {
++ DEBUG_SETUP("%s: VBUSON interrupt\n", __FUNCTION__);
++ __raw_writel(S3C_UDC_INT_VBUSON, S3C_UDC_SYS_STATUS_REG);
++ }
++
++ if (intr_status & S3C_UDC_INT_ERR) {
++ DEBUG_SETUP("%s: Error interrupt\n", __FUNCTION__);
++ __raw_writel(S3C_UDC_INT_ERR, S3C_UDC_SYS_STATUS_REG);
++ }
++
++ if (intr_status & S3C_UDC_INT_SDE) {
++ DEBUG_SETUP("%s: Speed Detection interrupt\n",
++ __FUNCTION__);
++ __raw_writel(S3C_UDC_INT_SDE, S3C_UDC_SYS_STATUS_REG);
++
++ if (intr_status & S3C_UDC_INT_HSP) {
++ DEBUG_SETUP("%s: High Speed Detection\n",
++ __FUNCTION__);
++ set_max_pktsize(dev, USB_SPEED_HIGH);
++ }
++ else {
++ DEBUG_SETUP("%s: Full Speed Detection\n",
++ __FUNCTION__);
++ set_max_pktsize(dev, USB_SPEED_FULL);
++ }
++ }
++
++ if (intr_status & S3C_UDC_INT_SUSPEND) {
++ DEBUG_SETUP("%s: SUSPEND interrupt\n", __FUNCTION__);
++ __raw_writel(S3C_UDC_INT_SUSPEND, S3C_UDC_SYS_STATUS_REG);
++ if (dev->gadget.speed != USB_SPEED_UNKNOWN
++ && dev->driver
++ && dev->driver->suspend) {
++ dev->driver->suspend(&dev->gadget);
++ }
++ }
++
++ if (intr_status & S3C_UDC_INT_RESUME) {
++ DEBUG_SETUP("%s: RESUME interrupt\n", __FUNCTION__);
++ __raw_writel(S3C_UDC_INT_RESUME, S3C_UDC_SYS_STATUS_REG);
++ if (dev->gadget.speed != USB_SPEED_UNKNOWN
++ && dev->driver
++ && dev->driver->resume) {
++ dev->driver->resume(&dev->gadget);
++ }
++ }
++
++ if (intr_status & S3C_UDC_INT_RESET) {
++ DEBUG_SETUP("%s: RESET interrupt\n", __FUNCTION__);
++ __raw_writel(S3C_UDC_INT_RESET, S3C_UDC_SYS_STATUS_REG);
++ reconfig_usbd();
++ dev->ep0state = WAIT_FOR_SETUP;
++ }
++ }
++
++ if (intr_in) {
++ if (intr_in & S3C_UDC_INT_EP0){
++ __raw_writel(S3C_UDC_INT_EP0, S3C_UDC_EP_INT_REG);
++ s3c_handle_ep0(dev);
++ }else if (intr_in & S3C_UDC_INT_EP2){
++ __raw_writel(S3C_UDC_INT_EP2, S3C_UDC_EP_INT_REG);
++ s3c_in_epn(dev, 2); // hard coded !!!
++ }else{
++ __raw_writel(S3C_UDC_INT_EP3, S3C_UDC_EP_INT_REG);
++ s3c_in_epn(dev, 3); // hard coded !!!
++ }
++ }
++
++ if (intr_out) {
++ usb_write(S3C_UDC_INT_EP1, (u32) S3C_UDC_EP_INT_REG, 1);
++ s3c_out_epn(dev, 1); // hard coded !!!
++ }
++
++ __raw_writel(IRQ_USBD, S3C2410_INTPND);
++ __raw_writel(IRQ_USBD, S3C2410_SRCPND);
++
++ spin_unlock(&dev->lock);
++
++ return IRQ_HANDLED;
++}
++
++static int s3c_ep_enable(struct usb_ep *_ep,
++ const struct usb_endpoint_descriptor *desc)
++{
++ struct s3c_ep *ep;
++ struct s3c_udc *dev;
++ unsigned long flags;
++
++ DEBUG("%s: %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || !desc || ep->desc || _ep->name == ep0name
++ || desc->bDescriptorType != USB_DT_ENDPOINT
++ || ep->bEndpointAddress != desc->bEndpointAddress
++ || ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) {
++ DEBUG("%s: bad ep or descriptor\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ /* xfer types must match, except that interrupt ~= bulk */
++ if (ep->bmAttributes != desc->bmAttributes
++ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
++ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
++ DEBUG("%s: %s type mismatch\n", __FUNCTION__, _ep->name);
++ return -EINVAL;
++ }
++
++ /* hardware _could_ do smaller, but driver doesn't */
++ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
++ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep))
++ || !desc->wMaxPacketSize) {
++ DEBUG("%s: bad %s maxpacket\n", __FUNCTION__, _ep->name);
++ return -ERANGE;
++ }
++
++ dev = ep->dev;
++ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
++ DEBUG("%s: bogus device state\n", __FUNCTION__);
++ return -ESHUTDOWN;
++ }
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ ep->stopped = 0;
++ ep->desc = desc;
++ ep->pio_irqs = 0;
++ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
++
++ /* Reset halt state */
++ s3c_set_halt(_ep, 0);
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++
++ DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
++ return 0;
++}
++
++/** Disable EP
++ */
++static int s3c_ep_disable(struct usb_ep *_ep)
++{
++ struct s3c_ep *ep;
++ unsigned long flags;
++
++ DEBUG("%s: %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || !ep->desc) {
++ DEBUG("%s: %s not enabled\n", __FUNCTION__,
++ _ep ? ep->ep.name : NULL);
++ return -EINVAL;
++ }
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ /* Nuke all pending requests */
++ nuke(ep, -ESHUTDOWN);
++
++ ep->desc = 0;
++ ep->stopped = 1;
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++
++ DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
++ return 0;
++}
++
++static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
++ gfp_t gfp_flags)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s: %p\n", __FUNCTION__, ep);
++
++ req = kmalloc(sizeof *req, gfp_flags);
++ if (!req)
++ return 0;
++
++ memset(req, 0, sizeof *req);
++ INIT_LIST_HEAD(&req->queue);
++
++ return &req->req;
++}
++
++static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s: %p\n", __FUNCTION__, ep);
++
++ req = container_of(_req, struct s3c_request, req);
++ WARN_ON(!list_empty(&req->queue));
++ kfree(req);
++}
++
++
++/** Queue one request
++ * Kickstart transfer if needed
++ */
++static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
++ gfp_t gfp_flags)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep;
++ struct s3c_udc *dev;
++ unsigned long flags;
++
++ DEBUG("%s: %p\n", __FUNCTION__, _ep);
++
++ req = container_of(_req, struct s3c_request, req);
++ if (unlikely
++ (!_req || !_req->complete || !_req->buf
++ || !list_empty(&req->queue))) {
++ DEBUG("%s: bad params\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
++ DEBUG("%s: bad ep\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ dev = ep->dev;
++ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
++ DEBUG("%s: bogus device state %p\n", __FUNCTION__, dev->driver);
++ return -ESHUTDOWN;
++ }
++
++ DEBUG("%s: %s queue req %p, len %d buf %p\n",
++ __FUNCTION__, _ep->name, _req, _req->length, _req->buf);
++
++ spin_lock_irqsave(&dev->lock, flags);
++
++ _req->status = -EINPROGRESS;
++ _req->actual = 0;
++
++ /* kickstart this i/o queue? */
++ DEBUG("%s: Add to ep=%d, Q empty=%d, stopped=%d\n",
++ __FUNCTION__, ep_index(ep), list_empty(&ep->queue), ep->stopped);
++ if (list_empty(&ep->queue) && likely(!ep->stopped)) {
++ u32 csr;
++
++ if (unlikely(ep_index(ep) == 0)) {
++ /* EP0 */
++ list_add_tail(&req->queue, &ep->queue);
++ s3c_ep0_kick(dev, ep);
++ req = 0;
++
++ } else if (ep_is_in(ep)) {
++ csr = usb_read((u32) S3C_UDC_EP_STATUS_REG, ep_index(ep));
++ DEBUG("%s: ep_is_in, S3C_UDC_EP%d_STATUS_REG=0x%x\n",
++ __FUNCTION__, ep_index(ep), csr);
++
++ if(!(csr & S3C_UDC_EP_TX_SUCCESS)
++ && (write_fifo(ep, req) == 1))
++ req = 0;
++ else
++ DEBUG("IN-list_add_taill :: req =%p\n", req);
++
++ } else {
++ csr = usb_read((u32) S3C_UDC_EP_STATUS_REG, ep_index(ep));
++ DEBUG("%s: ep_is_out, S3C_UDC_EP%d_STATUS_REG=0x%x\n",
++ __FUNCTION__, ep_index(ep),csr);
++
++ if((csr & S3C_UDC_EP_RX_SUCCESS)
++ && (read_fifo(ep, req) == 1))
++ req = 0;
++ else
++ DEBUG("OUT-list_add_taill :: req =%p\n", req);
++ }
++ }
++
++ /* pio or dma irq handler advances the queue. */
++ if (likely(req != 0))
++ list_add_tail(&req->queue, &ep->queue);
++
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ return 0;
++}
++
++/* dequeue JUST ONE request */
++static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
++{
++ struct s3c_ep *ep;
++ struct s3c_request *req;
++ unsigned long flags;
++
++ DEBUG("%s: %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || ep->ep.name == ep0name)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ /* make sure it's actually queued on this endpoint */
++ list_for_each_entry(req, &ep->queue, queue) {
++ if (&req->req == _req)
++ break;
++ }
++ if (&req->req != _req) {
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++ return -EINVAL;
++ }
++
++ done(ep, req, -ECONNRESET);
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++ return 0;
++}
++
++/** Halt specific EP
++ * Return 0 if success
++ */
++static int s3c_set_halt(struct usb_ep *_ep, int value)
++{
++ return 0;
++}
++
++/** Return bytes in EP FIFO
++ */
++static int s3c_fifo_status(struct usb_ep *_ep)
++{
++ u32 csr;
++ int count = 0;
++ struct s3c_ep *ep;
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep) {
++ DEBUG("%s: bad ep\n", __FUNCTION__);
++ return -ENODEV;
++ }
++
++ DEBUG("%s: %d\n", __FUNCTION__, ep_index(ep));
++
++ /* LPD can't report unclaimed bytes from IN fifos */
++ if (ep_is_in(ep))
++ return -EOPNOTSUPP;
++
++ csr = usb_read((u32) S3C_UDC_EP_STATUS_REG, ep_index(ep));
++ if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
++ csr & S3C_UDC_EP_RX_SUCCESS) {
++
++ count = usb_read((u32) S3C_UDC_BYTE_READ_CNT_REG, ep_index(ep));
++
++ if (usb_read((u32) S3C_UDC_EP_STATUS_REG, ep_index(ep))
++ & S3C_UDC_EP_LWO)
++ count = count * 2 -1;
++ else
++ count = count * 2;
++ }
++
++ return count;
++}
++
++/** Flush EP FIFO
++ */
++static void s3c_fifo_flush(struct usb_ep *_ep)
++{
++ struct s3c_ep *ep;
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
++ DEBUG("%s: bad ep\n", __FUNCTION__);
++ return;
++ }
++
++ DEBUG("%s: %d\n", __FUNCTION__, ep_index(ep));
++}
++
++/****************************************************************/
++/* End Point 0 related functions */
++/****************************************************************/
++
++/* return: 0 = still running, 1 = completed, negative = errno */
++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 max;
++ unsigned count;
++ int is_last;
++
++ max = ep_maxpacket(ep);
++
++ DEBUG_EP0("%s: max = %d\n", __FUNCTION__, max);
++
++ count = write_packet(ep, req, max);
++
++ /* last packet is usually short (or a zlp) */
++ if (unlikely(count != max))
++ is_last = 1;
++ else {
++ if (likely(req->req.length != req->req.actual) || req->req.zero)
++ is_last = 0;
++ else
++ is_last = 1;
++ }
++
++ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
++ ep->ep.name, count,
++ is_last ? "/L" : "", req->req.length - req->req.actual, req);
++
++ /* requests complete when all IN data is in the FIFO */
++ if (is_last) {
++ return 1;
++ }
++
++ return 0;
++}
++
++static __inline__ int s3c_fifo_read(struct s3c_ep *ep, u16 *cp, int max)
++{
++ int bytes;
++ int count;
++
++ count = usb_read((u32) S3C_UDC_BYTE_READ_CNT_REG, ep_index(ep));
++ DEBUG_EP0("%s: count=%d, ep_index=%d, fifo=0x%x\n",
++ __FUNCTION__, count, ep_index(ep), ep->fifo);
++ bytes = count * 2;
++
++ while (count--) {
++ *cp++ = (u16) __raw_readl(S3C_UDC_EP0_FIFO_REG);
++ }
++
++ __raw_writel(S3C_UDC_EP0_RX_SUCCESS, S3C_UDC_EP0_STATUS_REG);/* clear */
++
++ return bytes;
++}
++
++static int read_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 csr;
++ u16 *buf;
++ unsigned bufferspace, count, is_short, bytes;
++ u32 fifo = ep->fifo;
++
++ DEBUG_EP0("%s\n", __FUNCTION__);
++
++ csr = __raw_readl(S3C_UDC_EP0_STATUS_REG);
++ if (!(csr & S3C_UDC_EP0_RX_SUCCESS))
++ return 0;
++
++ buf = req->req.buf + req->req.actual;
++ prefetchw(buf);
++ bufferspace = req->req.length - req->req.actual;
++
++ /* read all bytes from this packet */
++ if (likely(csr & S3C_UDC_EP0_RX_SUCCESS)) {
++ count = usb_read((u32) S3C_UDC_BYTE_READ_CNT_REG, ep_index(ep));
++ if (csr & S3C_UDC_EP0_LWO)
++ bytes = count * 2 -1;
++ else
++ bytes = count * 2;
++
++ req->req.actual += min(bytes, bufferspace);
++ } else { // zlp
++ count = 0;
++ bytes = 0;
++ }
++
++ is_short = (bytes < ep->ep.maxpacket);
++ DEBUG_EP0("%s: read %s %02x, %d bytes%s req %p %d/%d\n",
++ __FUNCTION__,
++ ep->ep.name, csr, bytes,
++ is_short ? "/S" : "", req, req->req.actual, req->req.length);
++
++ while (likely(count-- != 0)) {
++ u16 byte = (u16) __raw_readl(fifo);
++
++ if (unlikely(bufferspace == 0)) {
++ /* this happens when the driver's buffer
++ * is smaller than what the host sent.
++ * discard the extra data.
++ */
++ if (req->req.status != -EOVERFLOW)
++ DEBUG_EP0("%s overflow %d\n", ep->ep.name,
++ count);
++ req->req.status = -EOVERFLOW;
++ } else {
++ *buf++ = byte;
++ bufferspace = bufferspace - 2;
++ }
++ }
++
++ __raw_writel(S3C_UDC_EP0_RX_SUCCESS, S3C_UDC_EP0_STATUS_REG);/* clear */
++
++ /* completion */
++ if (is_short || req->req.actual == req->req.length) {
++ return 1;
++ }
++
++ return 0;
++}
++
++/**
++ * udc_set_address - set the USB address for this device
++ * @address:
++ *
++ * Called from control endpoint function
++ * after it decodes a set address setup packet.
++ */
++static void udc_set_address(struct s3c_udc *dev, unsigned char address)
++{
++ DEBUG_EP0("%s: address=%d, S3C_UDC_FUNC_ADDR_REG=0x%x\n",
++ __FUNCTION__, address, __raw_readl(S3C_UDC_FUNC_ADDR_REG));
++ dev->usb_address = address;
++}
++
++/*
++ * DATA_STATE_RECV (OUT_PKT_RDY)
++ */
++static int first_time = 1;
++
++static void s3c_ep0_read(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret;
++
++ if (!list_empty(&ep->queue))
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ else {
++ DEBUG_EP0("%s: ---> BUG\n", __FUNCTION__);
++ BUG(); //logic ensures -jassi
++ return;
++ }
++
++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n",
++ __FUNCTION__, req->req.length, req->req.actual);
++
++ if(req->req.length == 0) {
++ __raw_writel(S3C_UDC_EP0_RX_SUCCESS, S3C_UDC_EP0_STATUS_REG);
++ dev->ep0state = WAIT_FOR_SETUP;
++ first_time = 1;
++ done(ep, req, 0);
++ return;
++ }
++
++ if(!req->req.actual && first_time){ //for SetUp packet
++ __raw_writel(S3C_UDC_EP0_RX_SUCCESS, S3C_UDC_EP0_STATUS_REG);
++ first_time = 0;
++ return;
++ }
++
++ ret = read_fifo_ep0(ep, req);
++ if (ret) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ first_time = 1;
++ done(ep, req, 0);
++ return;
++ }
++
++}
++
++/*
++ * DATA_STATE_XMIT
++ */
++static int s3c_ep0_write(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret, need_zlp = 0;
++
++ DEBUG_EP0("%s: ep0 write\n", __FUNCTION__);
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ if (!req) {
++ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
++ return 0;
++ }
++
++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n",
++ __FUNCTION__, req->req.length, req->req.actual);
++
++ if (req->req.length == 0) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ done(ep, req, 0);
++ return 1;
++ }
++
++ if (req->req.length - req->req.actual == ep0_fifo_size) {
++ /* Next write will end with the packet size, */
++ /* so we need Zero-length-packet */
++ need_zlp = 1;
++ }
++
++ ret = write_fifo_ep0(ep, req);
++
++ if ((ret == 1) && !need_zlp) {
++ /* Last packet */
++ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
++ dev->ep0state = WAIT_FOR_SETUP;
++ } else {
++ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
++ }
++
++ if (need_zlp) {
++ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
++ dev->ep0state = DATA_STATE_NEED_ZLP;
++ }
++
++ if(ret)
++ done(ep, req, 0);
++
++ return 1;
++}
++
++/*
++ * WAIT_FOR_SETUP (OUT_PKT_RDY)
++ */
++static void s3c_ep0_setup(struct s3c_udc *dev, u32 csr)
++{
++ struct s3c_ep *ep = &dev->ep[0];
++ struct usb_ctrlrequest ctrl;
++ int i, bytes, is_in;
++
++ DEBUG_SETUP("%s: csr = 0x%x\n", __FUNCTION__, csr);
++
++ /* Nuke all previous transfers */
++ nuke(ep, -EPROTO);
++
++ /* read control req from fifo (8 bytes) */
++ bytes = s3c_fifo_read(ep, (u16 *)&ctrl, 8);
++
++ DEBUG_SETUP("Read CTRL REQ %d bytes\n", bytes);
++ DEBUG_SETUP("CTRL.bRequestType = 0x%x (is_in %d)\n", ctrl.bRequestType,
++ ctrl.bRequestType & USB_DIR_IN);
++ DEBUG_SETUP("CTRL.bRequest = 0x%x\n", ctrl.bRequest);
++ DEBUG_SETUP("CTRL.wLength = 0x%x\n", ctrl.wLength);
++ DEBUG_SETUP("CTRL.wValue = 0x%x (%d)\n", ctrl.wValue, ctrl.wValue >> 8);
++ DEBUG_SETUP("CTRL.wIndex = 0x%x\n", ctrl.wIndex);
++
++ /* Set direction of EP0 */
++ if (likely(ctrl.bRequestType & USB_DIR_IN)) {
++ ep->bEndpointAddress |= USB_DIR_IN;
++ is_in = 1;
++ } else {
++ ep->bEndpointAddress &= ~USB_DIR_IN;
++ is_in = 0;
++ }
++
++ dev->req_pending = 1;
++
++ /* Handle some SETUP packets ourselves */
++ switch (ctrl.bRequest) {
++ case USB_REQ_SET_ADDRESS:
++ if (ctrl.bRequestType
++ != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
++ break;
++
++ DEBUG_SETUP("%s: USB_REQ_SET_ADDRESS (%d)\n",
++ __FUNCTION__, ctrl.wValue);
++ udc_set_address(dev, ctrl.wValue);
++ return;
++ default:
++ DEBUG_SETUP("%s: DFAULT\n", __FUNCTION__);
++ break;
++ }
++
++ if (likely(dev->driver)) {
++ /* device-2-host (IN) or no data setup command,
++ * process immediately */
++ spin_unlock(&dev->lock);
++ i = dev->driver->setup(&dev->gadget, &ctrl);
++ spin_lock(&dev->lock);
++
++ if (i < 0) {
++ /* setup processing failed, force stall */
++ printk("%s: --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
++ __FUNCTION__, i);
++ /* ep->stopped = 1; */
++ dev->ep0state = WAIT_FOR_SETUP;
++ }
++ }
++}
++
++/*
++ * handle ep0 interrupt
++ */
++static void s3c_handle_ep0(struct s3c_udc *dev)
++{
++ struct s3c_ep *ep = &dev->ep[0];
++ u32 csr;
++
++ csr = __raw_readl(S3C_UDC_EP0_STATUS_REG);
++
++ DEBUG_EP0("%s: S3C_UDC_EP0_STATUS_REG = 0x%x\n", __FUNCTION__, csr);
++
++ /*
++ * if SENT_STALL is set
++ * - clear the SENT_STALL bit
++ */
++ if (csr & S3C_UDC_EP0_STALL) {
++ printk("%s: S3C_UDC_EP0_STALL\n", __FUNCTION__);
++ __raw_writel(S3C_UDC_EP0_STALL, S3C_UDC_EP0_STATUS_REG); /* clear */
++ nuke(ep, -ECONNABORTED);
++ dev->ep0state = WAIT_FOR_SETUP;
++ return;
++ }
++
++ if (csr & S3C_UDC_EP0_TX_SUCCESS) {
++ DEBUG_EP0("%s: EP0_TX_SUCCESS \n", __FUNCTION__);
++ __raw_writel(S3C_UDC_EP0_TX_SUCCESS, S3C_UDC_EP0_STATUS_REG); /* clear */
++ }
++
++ if (csr & S3C_UDC_EP0_RX_SUCCESS) {
++ if (dev->ep0state == WAIT_FOR_SETUP) {
++ DEBUG_EP0("%s: WAIT_FOR_SETUP\n", __FUNCTION__);
++ s3c_ep0_setup(dev, csr);
++ } else {
++ DEBUG_EP0("%s: strange state!!(state = %s)\n",
++ __FUNCTION__, state_names[dev->ep0state]);
++ }
++ }
++}
++
++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
++{
++ DEBUG_EP0("%s: ep_is_in = %d\n", __FUNCTION__, ep_is_in(ep));
++ if (ep_is_in(ep)) {
++ dev->ep0state = DATA_STATE_XMIT;
++ s3c_ep0_write(dev);
++ } else {
++ dev->ep0state = DATA_STATE_RECV;
++ s3c_ep0_read(dev);
++ }
++}
++
++/* ---------------------------------------------------------------------------
++ * device-scoped parts of the api to the usb controller hardware
++ * ---------------------------------------------------------------------------
++ */
++
++static int s3c_udc_get_frame(struct usb_gadget *_gadget)
++{
++ /*fram count number [10:0]*/
++ u32 frame = __raw_readl(S3C_UDC_FRAME_NUM_REG);
++ DEBUG("%s: %p\n", __FUNCTION__, _gadget);
++ return (frame & 0x7ff);
++}
++
++static int s3c_udc_wakeup(struct usb_gadget *_gadget)
++{
++ return -ENOTSUPP;
++}
++
++static const struct usb_gadget_ops s3c_udc_ops = {
++ .get_frame = s3c_udc_get_frame,
++ .wakeup = s3c_udc_wakeup,
++ /* current versions must always be self-powered */
++};
++
++static void nop_release(struct device *dev)
++{
++ DEBUG("%s %s\n", __FUNCTION__, dev->bus_id);
++}
++
++static struct s3c_udc memory = {
++ .usb_address = 0,
++
++ .gadget = {
++ .ops = &s3c_udc_ops,
++ .ep0 = &memory.ep[0].ep,
++ .name = driver_name,
++ .dev = {
++ .bus_id = "gadget",
++ .release = nop_release,
++ },
++ },
++
++ /* control endpoint */
++ .ep[0] = {
++ .ep = {
++ .name = ep0name,
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP0_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = 0,
++ .bmAttributes = 0,
++
++ .ep_type = ep_control,
++ .fifo = (u32) S3C_UDC_EP0_FIFO_REG,
++ },
++
++ /* first group of endpoints */
++ .ep[1] = {
++ .ep = {
++ .name = "ep1-bulk",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = 1,
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++
++ .ep_type = ep_bulk_out,
++ .fifo = (u32) S3C_UDC_EP1_FIFO_REG,
++ },
++
++ .ep[2] = {
++ .ep = {
++ .name = "ep2-bulk",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 2,
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++
++ .ep_type = ep_bulk_in,
++ .fifo = (u32) S3C_UDC_EP2_FIFO_REG,
++ },
++
++ .ep[3] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep3-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 3,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_EP3_FIFO_REG,
++ },
++ .ep[4] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep4-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 4,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_EP4_FIFO_REG,
++ },
++ .ep[5] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep5-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 5,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_EP5_FIFO_REG,
++ },
++ .ep[6] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep6-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 6,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_EP6_FIFO_REG,
++ },
++ .ep[7] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep7-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 7,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_EP7_FIFO_REG,
++ },
++ .ep[8] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep8-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 8,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_EP8_FIFO_REG,
++ },
++};
++
++/*
++ * probe - binds to the platform device
++ */
++static struct clk *udc_clock = NULL;
++
++static int s3c_udc_probe(struct platform_device *pdev)
++{
++ struct s3c_udc *dev = &memory;
++ int retval;
++
++ DEBUG("%s: %p\n", __FUNCTION__, pdev);
++
++ spin_lock_init(&dev->lock);
++ dev->dev = pdev;
++
++ device_initialize(&dev->gadget.dev);
++ dev->gadget.dev.parent = &pdev->dev;
++
++ dev->gadget.is_dualspeed = 1; // Hack only
++ dev->gadget.is_otg = 0;
++ dev->gadget.is_a_peripheral = 0;
++ dev->gadget.b_hnp_enable = 0;
++ dev->gadget.a_hnp_support = 0;
++ dev->gadget.a_alt_hnp_support = 0;
++
++ the_controller = dev;
++ platform_set_drvdata(pdev, dev);
++
++ udc_reinit(dev);
++
++ udc_clock = clk_get(&pdev->dev, "usb-device");
++ if (udc_clock == NULL) {
++ printk(KERN_INFO "failed to find usb-device clock source\n");
++ return -ENOENT;
++ }
++ clk_enable(udc_clock);
++
++ local_irq_disable();
++
++ /* irq setup after old hardware state is cleaned up */
++ retval =
++ request_irq(IRQ_USBD, s3c_udc_irq, IRQF_DISABLED, driver_name,
++ dev);
++ if (retval != 0) {
++ DEBUG(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name,
++ IRQ_USBD, retval);
++ return -EBUSY;
++ }
++
++ disable_irq(IRQ_USBD);
++ local_irq_enable();
++ create_proc_files();
++
++ return retval;
++}
++
++static int s3c_udc_remove(struct platform_device *pdev)
++{
++ struct s3c_udc *dev = platform_get_drvdata(pdev);
++
++ DEBUG("%s: %p\n", __FUNCTION__, pdev);
++
++ udc_disable(dev);
++ remove_proc_files();
++ usb_gadget_unregister_driver(dev->driver);
++
++ free_irq(IRQ_USBD, dev);
++
++ platform_set_drvdata(pdev, 0);
++
++ the_controller = 0;
++
++ return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++static struct platform_driver s3c_udc_driver = {
++ .probe = s3c_udc_probe,
++ .remove = s3c_udc_remove,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c2410-usbgadget",
++ },
++};
++
++static int __init udc_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&s3c_udc_driver);
++ if(!ret)
++ printk("Loaded %s version %s\n", driver_name, DRIVER_VERSION);
++
++ return ret;
++}
++
++static void __exit udc_exit(void)
++{
++ platform_driver_unregister(&s3c_udc_driver);
++ printk("Unloaded %s version %s\n", driver_name, DRIVER_VERSION);
++}
++
++module_init(udc_init);
++module_exit(udc_exit);
++
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_AUTHOR("Samsung");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/usb/gadget/s3c-udc-otg-hs.c b/drivers/usb/gadget/s3c-udc-otg-hs.c
+new file mode 100644
+index 0000000..7b95e2c
+--- /dev/null
++++ b/drivers/usb/gadget/s3c-udc-otg-hs.c
+@@ -0,0 +1,1091 @@
++/*
++ * drivers/usb/gadget/s3c-udc-otg-hs.c
++ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
++ *
++ * $Id: s3c-udc-otg-hs.c,v 1.12 2008/09/28 01:33:52 dasan Exp $*
++ *
++ * Copyright (C) 2006 for Samsung Electronics
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#include "s3c-udc.h"
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/arch/regs-usb-otg-hs.h>
++
++/*
++ * DMA Mode : support File-backed Storage and Ethernet(CDC, RNDIS) Gadget
++ * Slave Mode : support File-backed Storage and Ethernet(CDC) Gadget
++ */
++
++#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS_DMA_MODE) /* DMA mode */
++#define OTG_DMA_MODE 1
++
++#elif defined(CONFIG_USB_GADGET_S3C_OTGD_HS_SLAVE_MODE) /* Slave mode */
++#define OTG_DMA_MODE 0
++
++#else
++#error " Unknown S3C OTG operation mode, Slect a correct operation mode"
++#endif
++
++#undef DEBUG_S3C_UDC_SETUP
++#undef DEBUG_S3C_UDC_EP0
++#undef DEBUG_S3C_UDC_ISR
++#undef DEBUG_S3C_UDC_OUT_EP
++#undef DEBUG_S3C_UDC_IN_EP
++#undef DEBUG_S3C_UDC
++
++//#define DEBUG_S3C_UDC_SETUP
++//#define DEBUG_S3C_UDC_EP0
++//#define DEBUG_S3C_UDC_ISR
++//#define DEBUG_S3C_UDC_OUT_EP
++//#define DEBUG_S3C_UDC_IN_EP
++//#define DEBUG_S3C_UDC
++
++#define EP0_CON 0
++#define EP1_OUT 1
++#define EP2_IN 2
++#define EP3_IN 3
++#define EP_MASK 0xF
++
++#if defined(DEBUG_S3C_UDC_ISR) || defined(DEBUG_S3C_UDC_EP0)
++static char *state_names[] = {
++ "WAIT_FOR_SETUP",
++ "DATA_STATE_XMIT",
++ "DATA_STATE_NEED_ZLP",
++ "WAIT_FOR_OUT_STATUS",
++ "DATA_STATE_RECV",
++ "RegReadErr"
++ };
++#endif
++
++#ifdef DEBUG_S3C_UDC_SETUP
++#define DEBUG_SETUP(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG_SETUP(fmt,args...) do {} while(0)
++#endif
++
++#ifdef DEBUG_S3C_UDC_EP0
++#define DEBUG_EP0(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG_EP0(fmt,args...) do {} while(0)
++#endif
++
++#ifdef DEBUG_S3C_UDC
++#define DEBUG(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG(fmt,args...) do {} while(0)
++#endif
++
++#ifdef DEBUG_S3C_UDC_ISR
++#define DEBUG_ISR(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG_ISR(fmt,args...) do {} while(0)
++#endif
++
++#ifdef DEBUG_S3C_UDC_OUT_EP
++#define DEBUG_OUT_EP(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG_OUT_EP(fmt,args...) do {} while(0)
++#endif
++
++#ifdef DEBUG_S3C_UDC_IN_EP
++#define DEBUG_IN_EP(fmt,args...) printk(fmt, ##args)
++#else
++#define DEBUG_IN_EP(fmt,args...) do {} while(0)
++#endif
++
++
++#define DRIVER_DESC "Samsung Dual-speed USB 2.0 OTG Device Controller"
++#define DRIVER_VERSION __DATE__
++
++struct s3c_udc *the_controller;
++
++static const char driver_name[] = "s3c-udc";
++static const char driver_desc[] = DRIVER_DESC;
++static const char ep0name[] = "ep0-control";
++
++// Max packet size
++static u32 ep0_fifo_size = 64;
++static u32 ep_fifo_size = 512;
++static u32 ep_fifo_size2 = 1024;
++static int reset_available = 1;
++
++/* extern declarations in arch/arm/mach-s3c64xx*/
++#define OTGD_PHY_CLK_VALUE (0x20) /* UTMI Interface, Oscillator */
++extern void otg_phy_init(u32 otg_phy_clk);
++extern void otg_phy_off(void);
++extern struct usb_ctrlrequest usb_ctrl;
++
++/*
++ Local declarations.
++*/
++static int s3c_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *);
++static int s3c_ep_disable(struct usb_ep *ep);
++static struct usb_request *s3c_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
++static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
++
++static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
++static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
++static int s3c_set_halt(struct usb_ep *ep, int);
++static int s3c_fifo_status(struct usb_ep *ep);
++static void s3c_fifo_flush(struct usb_ep *ep);
++static void s3c_ep0_read(struct s3c_udc *dev);
++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
++static void s3c_handle_ep0(struct s3c_udc *dev);
++static int s3c_ep0_write(struct s3c_udc *dev);
++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
++static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
++static void stop_activity(struct s3c_udc *dev, struct usb_gadget_driver *driver);
++static int udc_enable(struct s3c_udc *dev);
++static void udc_set_address(struct s3c_udc *dev, unsigned char address);
++static void reconfig_usbd(void);
++static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
++static void nuke(struct s3c_ep *ep, int status);
++
++static struct usb_ep_ops s3c_ep_ops = {
++ .enable = s3c_ep_enable,
++ .disable = s3c_ep_disable,
++
++ .alloc_request = s3c_alloc_request,
++ .free_request = s3c_free_request,
++
++ .queue = s3c_queue,
++ .dequeue = s3c_dequeue,
++
++ .set_halt = s3c_set_halt,
++ .fifo_status = s3c_fifo_status,
++ .fifo_flush = s3c_fifo_flush,
++};
++
++#ifdef CONFIG_USB_GADGET_DEBUG_FILES
++
++static const char proc_node_name[] = "driver/udc";
++
++static int
++udc_proc_read(char *page, char **start, off_t off, int count,
++ int *eof, void *_dev)
++{
++ char *buf = page;
++ struct s3c_udc *dev = _dev;
++ char *next = buf;
++ unsigned size = count;
++ unsigned long flags;
++ int t;
++
++ if (off != 0)
++ return 0;
++
++ local_irq_save(flags);
++
++ /* basic device status */
++ t = scnprintf(next, size,
++ DRIVER_DESC "\n"
++ "%s version: %s\n"
++ "Gadget driver: %s\n"
++ "\n",
++ driver_name, DRIVER_VERSION,
++ dev->driver ? dev->driver->driver.name : "(none)");
++ size -= t;
++ next += t;
++
++ local_irq_restore(flags);
++ *eof = 1;
++ return count - size;
++}
++
++#define create_proc_files() \
++ create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
++#define remove_proc_files() \
++ remove_proc_entry(proc_node_name, NULL)
++
++#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
++
++#define create_proc_files() do {} while (0)
++#define remove_proc_files() do {} while (0)
++
++#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
++
++#if OTG_DMA_MODE /* DMA Mode */
++#include "s3c-udc-otg-xfer-dma.c"
++
++#else /* Slave Mode */
++#include "s3c-udc-otg-xfer-slave.c"
++#endif
++
++/*
++ * udc_disable - disable USB device controller
++ */
++static void udc_disable(struct s3c_udc *dev)
++{
++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev);
++
++ udc_set_address(dev, 0);
++
++ dev->ep0state = WAIT_FOR_SETUP;
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++ dev->usb_address = 0;
++
++ otg_phy_off();
++}
++
++/*
++ * udc_reinit - initialize software state
++ */
++static void udc_reinit(struct s3c_udc *dev)
++{
++ u32 i;
++
++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev);
++
++ /* device/ep0 records init */
++ INIT_LIST_HEAD(&dev->gadget.ep_list);
++ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
++ dev->ep0state = WAIT_FOR_SETUP;
++
++ /* basic endpoint records init */
++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
++ struct s3c_ep *ep = &dev->ep[i];
++
++ if (i != 0)
++ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
++
++ ep->desc = 0;
++ ep->stopped = 0;
++ INIT_LIST_HEAD(&ep->queue);
++ ep->pio_irqs = 0;
++ }
++
++ /* the rest was statically initialized, and is read-only */
++}
++
++#define BYTES2MAXP(x) (x / 8)
++#define MAXP2BYTES(x) (x * 8)
++
++/* until it's enabled, this UDC should be completely invisible
++ * to any USB host.
++ */
++static int udc_enable(struct s3c_udc *dev)
++{
++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev);
++
++ otg_phy_init(OTGD_PHY_CLK_VALUE);
++ reconfig_usbd();
++
++ DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
++ readl(S3C_UDC_OTG_GINTMSK));
++
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++
++ return 0;
++}
++
++/*
++ Register entry point for the peripheral controller driver.
++*/
++int usb_gadget_register_driver(struct usb_gadget_driver *driver)
++{
++ struct s3c_udc *dev = the_controller;
++ int retval;
++
++ DEBUG_SETUP("%s: %s\n", __FUNCTION__, driver->driver.name);
++
++ if (!driver
++ || (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
++ || !driver->bind
++ || !driver->unbind || !driver->disconnect || !driver->setup)
++ return -EINVAL;
++ if (!dev)
++ return -ENODEV;
++ if (dev->driver)
++ return -EBUSY;
++
++ /* first hook up the driver ... */
++ dev->driver = driver;
++ dev->gadget.dev.driver = &driver->driver;
++ retval = device_add(&dev->gadget.dev);
++
++ if(retval) { /* TODO */
++ printk("target device_add failed, error %d\n", retval);
++ return retval;
++ }
++
++ retval = driver->bind(&dev->gadget);
++ if (retval) {
++ printk("%s: bind to driver %s --> error %d\n", dev->gadget.name,
++ driver->driver.name, retval);
++ device_del(&dev->gadget.dev);
++
++ dev->driver = 0;
++ dev->gadget.dev.driver = 0;
++ return retval;
++ }
++
++ enable_irq(IRQ_OTG);
++
++ printk("Registered gadget driver '%s'\n", driver->driver.name);
++ udc_enable(dev);
++
++ return 0;
++}
++
++EXPORT_SYMBOL(usb_gadget_register_driver);
++
++/*
++ Unregister entry point for the peripheral controller driver.
++*/
++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++{
++ struct s3c_udc *dev = the_controller;
++ unsigned long flags;
++
++ if (!dev)
++ return -ENODEV;
++ if (!driver || driver != dev->driver)
++ return -EINVAL;
++
++ spin_lock_irqsave(&dev->lock, flags);
++ dev->driver = 0;
++ stop_activity(dev, driver);
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ driver->unbind(&dev->gadget);
++ device_del(&dev->gadget.dev);
++
++ disable_irq(IRQ_OTG);
++
++ printk("Unregistered gadget driver '%s'\n", driver->driver.name);
++
++ udc_disable(dev);
++
++ return 0;
++}
++
++EXPORT_SYMBOL(usb_gadget_unregister_driver);
++
++/*
++ * done - retire a request; caller blocked irqs
++ */
++static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
++{
++ u32 stopped = ep->stopped;
++
++ DEBUG("%s: %s %p, req = %p, stopped = %d\n",__FUNCTION__, ep->ep.name, ep, &req->req, stopped);
++ list_del_init(&req->queue);
++
++ if (likely(req->req.status == -EINPROGRESS)) {
++ req->req.status = status;
++ } else {
++ status = req->req.status;
++ }
++
++ if (status && status != -ESHUTDOWN) {
++ DEBUG("complete %s req %p stat %d len %u/%u\n",
++ ep->ep.name, &req->req, status,
++ req->req.actual, req->req.length);
++ }
++
++ /* don't modify queue heads during completion callback */
++ ep->stopped = 1;
++
++ spin_unlock(&ep->dev->lock);
++ req->req.complete(&ep->ep, &req->req);
++ spin_lock(&ep->dev->lock);
++
++ ep->stopped = stopped;
++}
++
++/*
++ * nuke - dequeue ALL requests
++ */
++static void nuke(struct s3c_ep *ep, int status)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s: %s %p\n", __FUNCTION__, ep->ep.name, ep);
++
++ /* called with irqs blocked */
++ while (!list_empty(&ep->queue)) {
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ done(ep, req, status);
++ }
++}
++
++static void stop_activity(struct s3c_udc *dev,
++ struct usb_gadget_driver *driver)
++{
++ int i;
++
++ /* don't disconnect drivers more than once */
++ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
++ driver = 0;
++ dev->gadget.speed = USB_SPEED_UNKNOWN;
++
++ /* prevent new request submissions, kill any outstanding requests */
++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
++ struct s3c_ep *ep = &dev->ep[i];
++ ep->stopped = 1;
++ nuke(ep, -ESHUTDOWN);
++ }
++
++ /* report disconnect; the driver is already quiesced */
++ if (driver) {
++ spin_unlock(&dev->lock);
++ driver->disconnect(&dev->gadget);
++ spin_lock(&dev->lock);
++ }
++
++ /* re-init driver-visible data structures */
++ udc_reinit(dev);
++}
++
++static void reconfig_usbd(void)
++{
++ // 2. Soft-reset OTG Core and then unreset again.
++ u32 uTemp = writel(CORE_SOFT_RESET, S3C_UDC_OTG_GRSTCTL);
++
++ writel( 0<<15 // PHY Low Power Clock sel
++ |1<<14 // Non-Periodic TxFIFO Rewind Enable
++ |0x5<<10 // Turnaround time
++ |0<<9|0<<8 // [0:HNP disable, 1:HNP enable][ 0:SRP disable, 1:SRP enable] H1= 1,1
++ |0<<7 // Ulpi DDR sel
++ |0<<6 // 0: high speed utmi+, 1: full speed serial
++ |0<<4 // 0: utmi+, 1:ulpi
++ |1<<3 // phy i/f 0:8bit, 1:16bit
++ |0x7<<0, // HS/FS Timeout*
++ S3C_UDC_OTG_GUSBCFG);
++
++ // 3. Put the OTG device core in the disconnected state.
++ uTemp = readl(S3C_UDC_OTG_DCTL);
++ uTemp |= SOFT_DISCONNECT;
++ writel(uTemp, S3C_UDC_OTG_DCTL);
++
++ udelay(20);
++
++ // 4. Make the OTG device core exit from the disconnected state.
++ uTemp = readl(S3C_UDC_OTG_DCTL);
++ uTemp = uTemp & ~SOFT_DISCONNECT;
++ writel(uTemp, S3C_UDC_OTG_DCTL);
++
++ // 5. Configure OTG Core to initial settings of device mode.
++ writel(1<<18|0x0<<0, S3C_UDC_OTG_DCFG); // [][1: full speed(30Mhz) 0:high speed]
++
++ mdelay(1);
++
++ // 6. Unmask the core interrupts
++ writel(GINTMSK_INIT, S3C_UDC_OTG_GINTMSK);
++
++ // 7. Set NAK bit of EP0, EP1, EP2
++ writel(DEPCTL_EPDIS|DEPCTL_SNAK|(0<<0), S3C_UDC_OTG_DOEPCTL0); /* EP0: Control OUT */
++ writel(DEPCTL_EPDIS|DEPCTL_SNAK|(0<<0), S3C_UDC_OTG_DIEPCTL0); /* EP0: Control IN */
++
++ writel(DEPCTL_EPDIS|DEPCTL_SNAK|DEPCTL_BULK_TYPE|(0<<0), S3C_UDC_OTG_DOEPCTL1); /* EP1:Data OUT */
++ writel(DEPCTL_EPDIS|DEPCTL_SNAK|DEPCTL_BULK_TYPE|(0<<0), S3C_UDC_OTG_DIEPCTL2); /* EP2:Data IN */
++ writel(DEPCTL_EPDIS|DEPCTL_SNAK|DEPCTL_BULK_TYPE|(0<<0), S3C_UDC_OTG_DIEPCTL3); /* EP3:IN Interrupt*/
++
++ // 8. Unmask EP interrupts on IN EPs : 0, 2, 3
++ // OUT EPs : 0, 1
++ writel( (((1<<EP1_OUT)|(1<<EP0_CON))<<16) |
++ (1<<EP3_IN)|(1<<EP2_IN)|(1<<EP0_CON),
++ S3C_UDC_OTG_DAINTMSK);
++
++ // 9. Unmask device OUT EP common interrupts
++ writel(DOEPMSK_INIT, S3C_UDC_OTG_DOEPMSK);
++
++ // 10. Unmask device IN EP common interrupts
++ writel(DIEPMSK_INIT, S3C_UDC_OTG_DIEPMSK);
++
++ // 11. Set Rx FIFO Size
++ writel(RX_FIFO_SIZE, S3C_UDC_OTG_GRXFSIZ);
++
++ // 12. Set Non Periodic Tx FIFO Size
++ writel(NPTX_FIFO_SIZE<<16| NPTX_FIFO_START_ADDR<<0, S3C_UDC_OTG_GNPTXFSIZ);
++
++ // 13. Clear NAK bit of EP0, EP1, EP2
++ // For Slave mode
++ writel(DEPCTL_EPDIS|DEPCTL_CNAK|(0<<0), S3C_UDC_OTG_DOEPCTL0); /* EP0: Control OUT */
++
++ // 14. Initialize OTG Link Core.
++ writel(GAHBCFG_INIT, S3C_UDC_OTG_GAHBCFG);
++
++}
++
++static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
++{
++ u32 ep_ctrl;
++
++ if (speed == USB_SPEED_HIGH) {
++ ep0_fifo_size = 64;
++ ep_fifo_size = 512;
++ ep_fifo_size2 = 1024;
++ dev->gadget.speed = USB_SPEED_HIGH;
++ } else {
++ ep0_fifo_size = 64;
++ ep_fifo_size = 64;
++ ep_fifo_size2 = 64;
++ dev->gadget.speed = USB_SPEED_FULL;
++ }
++
++ dev->ep[0].ep.maxpacket = ep0_fifo_size;
++ dev->ep[1].ep.maxpacket = ep_fifo_size;
++ dev->ep[2].ep.maxpacket = ep_fifo_size;
++ dev->ep[3].ep.maxpacket = ep_fifo_size;
++ dev->ep[4].ep.maxpacket = ep_fifo_size;
++ dev->ep[5].ep.maxpacket = ep_fifo_size2;
++ dev->ep[6].ep.maxpacket = ep_fifo_size2;
++ dev->ep[7].ep.maxpacket = ep_fifo_size2;
++ dev->ep[8].ep.maxpacket = ep_fifo_size2;
++
++
++ if (speed == USB_SPEED_HIGH) {
++ // EP0 - Control IN (64 bytes)
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ writel(ep_ctrl|(0<<0), (u32) S3C_UDC_OTG_DIEPCTL0);
++
++ // EP0 - Control OUT (64 bytes)
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++ writel(ep_ctrl|(0<<0), (u32) S3C_UDC_OTG_DOEPCTL0);
++ } else {
++ // EP0 - Control IN (8 bytes)
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ writel(ep_ctrl|(3<<0), (u32) S3C_UDC_OTG_DIEPCTL0);
++
++ // EP0 - Control OUT (8 bytes)
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++ writel(ep_ctrl|(3<<0), (u32) S3C_UDC_OTG_DOEPCTL0);
++ }
++
++
++ // EP1 - Bulk Data OUT (512 bytes)
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1);
++ writel(ep_ctrl|(ep_fifo_size<<0), (u32) S3C_UDC_OTG_DOEPCTL1);
++
++ // EP2 - Bulk Data IN (512 bytes)
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL2);
++ writel(ep_ctrl|(ep_fifo_size<<0), (u32) S3C_UDC_OTG_DIEPCTL2);
++
++ // EP3 - INTR Data IN (512 bytes)
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL3);
++ writel(ep_ctrl|(ep_fifo_size<<0), (u32) S3C_UDC_OTG_DIEPCTL3);
++
++}
++
++static int s3c_ep_enable(struct usb_ep *_ep,
++ const struct usb_endpoint_descriptor *desc)
++{
++ struct s3c_ep *ep;
++ struct s3c_udc *dev;
++ unsigned long flags;
++
++ DEBUG("%s: %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || !desc || ep->desc || _ep->name == ep0name
++ || desc->bDescriptorType != USB_DT_ENDPOINT
++ || ep->bEndpointAddress != desc->bEndpointAddress
++ || ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) {
++
++ DEBUG("%s: bad ep or descriptor\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ /* xfer types must match, except that interrupt ~= bulk */
++ if (ep->bmAttributes != desc->bmAttributes
++ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
++ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
++
++ DEBUG("%s: %s type mismatch\n", __FUNCTION__, _ep->name);
++ return -EINVAL;
++ }
++
++ /* hardware _could_ do smaller, but driver doesn't */
++ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
++ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep))
++ || !desc->wMaxPacketSize) {
++
++ DEBUG("%s: bad %s maxpacket\n", __FUNCTION__, _ep->name);
++ return -ERANGE;
++ }
++
++ dev = ep->dev;
++ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
++
++ DEBUG("%s: bogus device state\n", __FUNCTION__);
++ return -ESHUTDOWN;
++ }
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ ep->stopped = 0;
++ ep->desc = desc;
++ ep->pio_irqs = 0;
++ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
++
++ /* Reset halt state */
++ s3c_set_halt(_ep, 0);
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++
++ DEBUG("%s: enabled %s, stopped = %d, maxpacket = %d\n",
++ __FUNCTION__, _ep->name, ep->stopped, ep->ep.maxpacket);
++ return 0;
++}
++
++/** Disable EP
++ */
++static int s3c_ep_disable(struct usb_ep *_ep)
++{
++ struct s3c_ep *ep;
++ unsigned long flags;
++
++ DEBUG("%s: %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || !ep->desc) {
++ DEBUG("%s: %s not enabled\n", __FUNCTION__,
++ _ep ? ep->ep.name : NULL);
++ return -EINVAL;
++ }
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ /* Nuke all pending requests */
++ nuke(ep, -ESHUTDOWN);
++
++ ep->desc = 0;
++ ep->stopped = 1;
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++
++ DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
++ return 0;
++}
++
++static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
++ gfp_t gfp_flags)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s: %s %p\n", __FUNCTION__, ep->name, ep);
++
++ req = kmalloc(sizeof *req, gfp_flags);
++ if (!req)
++ return 0;
++
++ memset(req, 0, sizeof *req);
++ INIT_LIST_HEAD(&req->queue);
++
++ return &req->req;
++}
++
++static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
++{
++ struct s3c_request *req;
++
++ DEBUG("%s: %p\n", __FUNCTION__, ep);
++
++ req = container_of(_req, struct s3c_request, req);
++ WARN_ON(!list_empty(&req->queue));
++ kfree(req);
++}
++
++/* dequeue JUST ONE request */
++static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
++{
++ struct s3c_ep *ep;
++ struct s3c_request *req;
++ unsigned long flags;
++
++ DEBUG("%s: %p\n", __FUNCTION__, _ep);
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep || ep->ep.name == ep0name)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ep->dev->lock, flags);
++
++ /* make sure it's actually queued on this endpoint */
++ list_for_each_entry(req, &ep->queue, queue) {
++ if (&req->req == _req)
++ break;
++ }
++ if (&req->req != _req) {
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++ return -EINVAL;
++ }
++
++ done(ep, req, -ECONNRESET);
++
++ spin_unlock_irqrestore(&ep->dev->lock, flags);
++ return 0;
++}
++
++/** Halt specific EP
++ * Return 0 if success
++ */
++static int s3c_set_halt(struct usb_ep *_ep, int value)
++{
++ return 0;
++}
++
++/** Return bytes in EP FIFO
++ */
++static int s3c_fifo_status(struct usb_ep *_ep)
++{
++ int count = 0;
++ struct s3c_ep *ep;
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (!_ep) {
++ DEBUG("%s: bad ep\n", __FUNCTION__);
++ return -ENODEV;
++ }
++
++ DEBUG("%s: %d\n", __FUNCTION__, ep_index(ep));
++
++ /* LPD can't report unclaimed bytes from IN fifos */
++ if (ep_is_in(ep))
++ return -EOPNOTSUPP;
++
++ return count;
++}
++
++/** Flush EP FIFO
++ */
++static void s3c_fifo_flush(struct usb_ep *_ep)
++{
++ struct s3c_ep *ep;
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
++ DEBUG("%s: bad ep\n", __FUNCTION__);
++ return;
++ }
++
++ DEBUG("%s: %d\n", __FUNCTION__, ep_index(ep));
++}
++
++/* ---------------------------------------------------------------------------
++ * device-scoped parts of the api to the usb controller hardware
++ * ---------------------------------------------------------------------------
++ */
++
++static int s3c_udc_get_frame(struct usb_gadget *_gadget)
++{
++ /*fram count number [21:8]*/
++ u32 frame = readl(S3C_UDC_OTG_DSTS);
++
++ DEBUG("%s: %p\n", __FUNCTION__, _gadget);
++ return (frame & 0x3ff00);
++}
++
++static int s3c_udc_wakeup(struct usb_gadget *_gadget)
++{
++ return -ENOTSUPP;
++}
++
++static const struct usb_gadget_ops s3c_udc_ops = {
++ .get_frame = s3c_udc_get_frame,
++ .wakeup = s3c_udc_wakeup,
++ /* current versions must always be self-powered */
++};
++
++static void nop_release(struct device *dev)
++{
++ DEBUG("%s %s\n", __FUNCTION__, dev->bus_id);
++}
++
++static struct s3c_udc memory = {
++ .usb_address = 0,
++
++ .gadget = {
++ .ops = &s3c_udc_ops,
++ .ep0 = &memory.ep[0].ep,
++ .name = driver_name,
++ .dev = {
++ .bus_id = "gadget",
++ .release = nop_release,
++ },
++ },
++
++ /* control endpoint */
++ .ep[0] = {
++ .ep = {
++ .name = ep0name,
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP0_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = 0,
++ .bmAttributes = 0,
++
++ .ep_type = ep_control,
++ .fifo = (u32) S3C_UDC_OTG_EP0_FIFO,
++ },
++
++ /* first group of endpoints */
++ .ep[1] = {
++ .ep = {
++ .name = "ep1-bulk",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = 1,
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++
++ .ep_type = ep_bulk_out,
++ .fifo = (u32) S3C_UDC_OTG_EP1_FIFO,
++ },
++
++ .ep[2] = {
++ .ep = {
++ .name = "ep2-bulk",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 2,
++ .bmAttributes = USB_ENDPOINT_XFER_BULK,
++
++ .ep_type = ep_bulk_in,
++ .fifo = (u32) S3C_UDC_OTG_EP2_FIFO,
++ },
++
++ .ep[3] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep3-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 3,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_OTG_EP3_FIFO,
++ },
++ .ep[4] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep4-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 4,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_OTG_EP4_FIFO,
++ },
++ .ep[5] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep5-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 5,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_OTG_EP5_FIFO,
++ },
++ .ep[6] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep6-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 6,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_OTG_EP6_FIFO,
++ },
++ .ep[7] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep7-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 7,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_OTG_EP7_FIFO,
++ },
++ .ep[8] = { // Though NOT USED XXX
++ .ep = {
++ .name = "ep8-int",
++ .ops = &s3c_ep_ops,
++ .maxpacket = EP_FIFO_SIZE2,
++ },
++ .dev = &memory,
++
++ .bEndpointAddress = USB_DIR_IN | 8,
++ .bmAttributes = USB_ENDPOINT_XFER_INT,
++
++ .ep_type = ep_interrupt,
++ .fifo = (u32) S3C_UDC_OTG_EP8_FIFO,
++ },
++};
++
++/*
++ * probe - binds to the platform device
++ */
++static struct clk *otg_clock = NULL;
++
++static int s3c_udc_probe(struct platform_device *pdev)
++{
++ struct s3c_udc *dev = &memory;
++ int retval;
++
++ DEBUG("%s: %p\n", __FUNCTION__, pdev);
++
++ spin_lock_init(&dev->lock);
++ dev->dev = pdev;
++
++ device_initialize(&dev->gadget.dev);
++ dev->gadget.dev.parent = &pdev->dev;
++
++ dev->gadget.is_dualspeed = 1; // Hack only
++ dev->gadget.is_otg = 0;
++ dev->gadget.is_a_peripheral = 0;
++ dev->gadget.b_hnp_enable = 0;
++ dev->gadget.a_hnp_support = 0;
++ dev->gadget.a_alt_hnp_support = 0;
++
++ the_controller = dev;
++ platform_set_drvdata(pdev, dev);
++
++ otg_clock = clk_get(&pdev->dev, "otg");
++ if (otg_clock == NULL) {
++ printk(KERN_INFO "failed to find otg clock source\n");
++ return -ENOENT;
++ }
++ clk_enable(otg_clock);
++
++ udc_reinit(dev);
++
++ local_irq_disable();
++
++ /* irq setup after old hardware state is cleaned up */
++ retval =
++ request_irq(IRQ_OTG, s3c_udc_irq, SA_INTERRUPT, driver_name,
++ dev);
++
++ if (retval != 0) {
++ DEBUG(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name,
++ IRQ_OTG, retval);
++ return -EBUSY;
++ }
++
++ disable_irq(IRQ_OTG);
++ local_irq_enable();
++ create_proc_files();
++
++ return retval;
++}
++
++static int s3c_udc_remove(struct platform_device *pdev)
++{
++ struct s3c_udc *dev = platform_get_drvdata(pdev);
++
++ DEBUG("%s: %p\n", __FUNCTION__, pdev);
++
++ if (otg_clock != NULL) {
++ clk_disable(otg_clock);
++ clk_put(otg_clock);
++ otg_clock = NULL;
++ }
++
++ remove_proc_files();
++ usb_gadget_unregister_driver(dev->driver);
++
++ free_irq(IRQ_OTG, dev);
++
++ platform_set_drvdata(pdev, 0);
++
++ the_controller = 0;
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_udc_suspend(struct platform_device *dev, pm_message_t state)
++{
++ return 0;
++}
++
++static int s3c_udc_resume(struct platform_device *dev)
++{
++ return 0;
++}
++#else
++#define s3c_udc_suspend NULL
++#define s3c_udc_resume NULL
++#endif /* CONFIG_PM */
++
++/*-------------------------------------------------------------------------*/
++static struct platform_driver s3c_udc_driver = {
++ .probe = s3c_udc_probe,
++ .remove = s3c_udc_remove,
++ .suspend = s3c_udc_suspend,
++ .resume = s3c_udc_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c2410-usbgadget",
++ },
++};
++
++static int __init udc_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&s3c_udc_driver);
++ if(!ret)
++ printk("Loaded %s version %s %s\n", driver_name, DRIVER_VERSION,
++ OTG_DMA_MODE? "(DMA Mode)" : "(Slave Mode)");
++
++ return ret;
++}
++
++static void __exit udc_exit(void)
++{
++ platform_driver_unregister(&s3c_udc_driver);
++ printk("Unloaded %s version %s\n", driver_name, DRIVER_VERSION);
++}
++
++module_init(udc_init);
++module_exit(udc_exit);
++
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_AUTHOR("Samsung");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/usb/gadget/s3c-udc-otg-xfer-dma.c b/drivers/usb/gadget/s3c-udc-otg-xfer-dma.c
+new file mode 100644
+index 0000000..f635acb
+--- /dev/null
++++ b/drivers/usb/gadget/s3c-udc-otg-xfer-dma.c
+@@ -0,0 +1,947 @@
++/*
++ * drivers/usb/gadget/s3c-udc-otg-hs-dma.c
++ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
++ *
++ * $Id: s3c-udc-otg-xfer-dma.c,v 1.2 2009/01/19 01:03:13 dasan Exp $*
++ *
++ * Copyright (C) 2009 for Samsung Electronics
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#define GINTMSK_INIT (INT_OUT_EP|INT_IN_EP|INT_RESUME|INT_ENUMDONE|INT_RESET|INT_SUSPEND)
++#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE|AHB_ERROR|TRANSFER_DONE)
++#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
++#define GAHBCFG_INIT (PTXFE_HALF|NPTXFE_HALF|MODE_DMA|BURST_INCR4|GBL_INT_UNMASK)
++
++/* Send Zero Length Packet for status stage of control transfer */
++static inline void s3c_send_zlp(void)
++{
++ u32 diepsiz0, diepctl0;
++
++ diepsiz0 = readl(S3C_UDC_OTG_DIEPTSIZ0);
++ diepctl0 = readl(S3C_UDC_OTG_DIEPCTL0);
++
++ writel(diepsiz0|1<<19| 0<<0, S3C_UDC_OTG_DIEPTSIZ0);
++ writel(diepctl0|DEPCTL_EPENA|DEPCTL_CNAK|EP3_IN<<11, S3C_UDC_OTG_DIEPCTL0);
++}
++
++static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 *buf, ctrl;
++ u32 length, pktcnt;
++ u32 ep_num = ep_index(ep);
++
++ buf = req->req.buf + req->req.actual;
++ prefetchw(buf);
++
++ length = req->req.length - req->req.actual;
++ dma_cache_maint(buf, length, DMA_FROM_DEVICE);
++
++ if(length == 0)
++ pktcnt = 1;
++ else
++ pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
++
++ if(ep_num == EP0_CON) {
++ ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++
++ writel(virt_to_phys(buf), S3C_UDC_OTG_DOEPDMA0);
++ writel((pktcnt<<19)|(length<<0), S3C_UDC_OTG_DOEPTSIZ0);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, S3C_UDC_OTG_DOEPCTL0);
++
++ DEBUG_OUT_EP("%s: RX DMA start : DOEPDMA0 = 0x%x, DOEPTSIZ0 = 0x%x, DOEPCTL0 = 0x%x,pktcnt = %d, xfersize = %d\n",
++ __FUNCTION__,
++ readl(S3C_UDC_OTG_DOEPDMA0),
++ readl(S3C_UDC_OTG_DOEPTSIZ0),
++ readl(S3C_UDC_OTG_DOEPCTL0),
++ pktcnt, length);
++
++ } else if (ep_num == EP1_OUT) {
++ ctrl = readl(S3C_UDC_OTG_DOEPCTL1);
++
++ writel(virt_to_phys(buf), S3C_UDC_OTG_DOEPDMA1);
++ writel((pktcnt<<19)|(length<<0), S3C_UDC_OTG_DOEPTSIZ1);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, S3C_UDC_OTG_DOEPCTL1);
++
++ DEBUG_OUT_EP("%s: RX DMA start : DOEPDMA1 = 0x%x, DOEPTSIZ1 = 0x%x, DOEPCTL1 = 0x%x, "
++ "pktcnt = %d, xfersize = %d\n",
++ __FUNCTION__,
++ readl(S3C_UDC_OTG_DOEPDMA1),
++ readl(S3C_UDC_OTG_DOEPTSIZ1),
++ readl(S3C_UDC_OTG_DOEPCTL1),
++ pktcnt, length);
++
++ } else {
++ DEBUG_OUT_EP("Not Support EP\n");
++ }
++
++ return 0;
++
++}
++
++static int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 *buf, ctrl;
++ u32 length, pktcnt;
++ u32 ep_num = ep_index(ep);
++
++ buf = req->req.buf + req->req.actual;
++ prefetch(buf);
++ length = req->req.length - req->req.actual;
++
++ if(ep_num == EP0_CON) {
++ length = min(length, (u32)ep_maxpacket(ep));
++ }
++
++ req->req.actual += length;
++ dma_cache_maint(buf, length, DMA_TO_DEVICE);
++
++ if(length == 0) {
++ pktcnt = 1;
++ } else {
++ pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
++ }
++
++ if(ep_num == EP0_CON) {
++ ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++
++ writel(virt_to_phys(buf), S3C_UDC_OTG_DIEPDMA0);
++ writel((pktcnt<<19)|(length<<0), (u32) S3C_UDC_OTG_DIEPTSIZ0);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP2_IN<<11), (u32) S3C_UDC_OTG_DIEPCTL0);
++
++ DEBUG_IN_EP("%s:TX DMA start : DIEPDMA0 = 0x%x, DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x,"
++ "pktcnt = %d, xfersize = %d\n",
++ __FUNCTION__,
++ readl(S3C_UDC_OTG_DIEPDMA0),
++ readl(S3C_UDC_OTG_DIEPTSIZ0),
++ readl(S3C_UDC_OTG_DIEPCTL0),
++ pktcnt, length);
++
++ } else if (ep_num == EP2_IN) {
++ ctrl = readl(S3C_UDC_OTG_DIEPCTL2);
++
++ writel(virt_to_phys(buf), S3C_UDC_OTG_DIEPDMA2);
++ writel((pktcnt<<19)|(length<<0), S3C_UDC_OTG_DIEPTSIZ2);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP0_CON<<11)|ctrl, (u32) S3C_UDC_OTG_DIEPCTL2);
++
++ DEBUG_IN_EP("%s:TX DMA start : DIEPDMA2 = 0x%x, DIEPTSIZ2 = 0x%x, DIEPCTL2 = 0x%x,"
++ "pktcnt = %d, xfersize = %d\n",
++ __FUNCTION__,
++ readl(S3C_UDC_OTG_DIEPDMA2),
++ readl(S3C_UDC_OTG_DIEPTSIZ2),
++ readl(S3C_UDC_OTG_DIEPCTL2),
++ pktcnt, length);
++
++ } else if (ep_num == EP3_IN) {
++ ctrl = readl(S3C_UDC_OTG_DIEPCTL3);
++
++ writel(virt_to_phys(buf), S3C_UDC_OTG_DIEPDMA3);
++ writel((pktcnt<<19)|(length<<0), S3C_UDC_OTG_DIEPTSIZ3);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP0_CON<<11)| ctrl, (u32) S3C_UDC_OTG_DIEPCTL3);
++
++ DEBUG_IN_EP("%s:TX DMA start : DIEPDMA3 = 0x%x, DIEPTSIZ3 = 0x%x, DIEPCTL3 = 0x%x,"
++ "pktcnt = %d, xfersize = %d\n",
++ __FUNCTION__,
++ readl(S3C_UDC_OTG_DIEPDMA3),
++ readl(S3C_UDC_OTG_DIEPTSIZ3),
++ readl(S3C_UDC_OTG_DIEPCTL3),
++ pktcnt, length);
++
++ } else {
++ DEBUG_IN_EP("%s: --> Error Unused Endpoint!!\n",
++ __FUNCTION__);
++ BUG();
++ }
++
++ return length;
++}
++
++static void complete_rx(struct s3c_udc *dev, u32 ep_idx)
++{
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req = NULL;
++ u32 csr, count_bytes=0, xfer_length, is_short = 0;
++ DEBUG_OUT_EP("%s\n",__FUNCTION__);
++
++ if (list_empty(&ep->queue)) {
++ DEBUG_OUT_EP("%s: NULL REQ on OUT EP-%d\n", __FUNCTION__, ep_idx);
++ return;
++
++ }
++
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ if(ep_idx == EP0_CON) {
++ csr = readl(S3C_UDC_OTG_DOEPTSIZ0);
++ count_bytes = (csr & 0x7f);
++
++ } else if (ep_idx == EP1_OUT) {
++ csr = readl(S3C_UDC_OTG_DOEPTSIZ1);
++ count_bytes = (csr & 0x7fff);
++
++ } else {
++ DEBUG_OUT_EP("%s : Not support EP\n");
++ }
++
++ dma_cache_maint(req->req.buf, req->req.length, DMA_FROM_DEVICE);
++ xfer_length = req->req.length-count_bytes;
++ req->req.actual += min(xfer_length, req->req.length-req->req.actual);
++ is_short = (xfer_length < ep->ep.maxpacket);
++
++ DEBUG_OUT_EP("%s: RX DMA done : %d/%d bytes received%s, DOEPTSIZ1 = 0x%x, %d bytes remained\n",
++ __FUNCTION__, req->req.actual, req->req.length,
++ is_short ? "/S" : "", csr, count_bytes);
++ DEBUG_OUT_EP("%s : req->length = %d / req->actual = %d / xfer_length = %d / ep.maxpacket = %d / is_short = %d \n",
++ __FUNCTION__, req->req.length,req->req.actual,
++ xfer_length,ep->ep.maxpacket, is_short);
++
++ if (is_short || req->req.actual == xfer_length) {
++ if(ep_idx == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
++ DEBUG_OUT_EP(" => Send ZLP\n");
++ dev->ep0state = WAIT_FOR_SETUP;
++ s3c_send_zlp();
++
++ } else {
++ done(ep, req, 0);
++
++ if(!list_empty(&ep->queue)) {
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ DEBUG_OUT_EP("%s: Next Rx request start...\n", __FUNCTION__);
++ setdma_rx(ep, req);
++ }
++ }
++ }
++}
++
++static void complete_tx(struct s3c_udc *dev, u32 ep_idx)
++{
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req;
++ u32 count_bytes = 0;
++
++ if (list_empty(&ep->queue)) {
++ DEBUG_IN_EP("%s: NULL REQ on IN EP-%d\n", __FUNCTION__, ep_idx);
++ return;
++
++ }
++
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ if(dev->ep0state == DATA_STATE_XMIT) {
++ u32 last = write_fifo_ep0(ep, req);
++
++ if(last) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ }
++
++ return;
++ }
++
++ if(ep_idx == EP0_CON) {
++ count_bytes = (readl(S3C_UDC_OTG_DIEPTSIZ0)) & 0x7f;
++ req->req.actual = req->req.length-count_bytes;
++
++ DEBUG_IN_EP("%s: TX DMA done : %d/%d bytes sent, DIEPTSIZ0 = 0x%x\n",
++ __FUNCTION__, req->req.actual,
++ req->req.length,
++ readl(S3C_UDC_OTG_DIEPTSIZ0));
++
++ } else if (ep_idx == EP2_IN) {
++ count_bytes = (readl(S3C_UDC_OTG_DIEPTSIZ2)) & 0x7fff;
++ req->req.actual = req->req.length-count_bytes;
++
++ DEBUG_IN_EP("%s: TX DMA done : %d/%d bytes sent, DIEPTSIZ2 = 0x%x\n",
++ __FUNCTION__, req->req.actual,
++ req->req.length,
++ readl(S3C_UDC_OTG_DIEPTSIZ2));
++
++ }
++ else if (ep_idx == EP3_IN)
++ {
++ count_bytes = (readl(S3C_UDC_OTG_DIEPTSIZ3)) & 0x7fff;
++ req->req.actual = req->req.length-count_bytes;
++
++ DEBUG_IN_EP("%s: TX DMA done : %d/%d bytes sent, DIEPTSIZ3 = 0x%x\n",
++ __FUNCTION__, req->req.actual,
++ req->req.length,
++ readl(S3C_UDC_OTG_DIEPTSIZ3));
++ } else {
++ DEBUG_IN_EP("%s: --> Error Unused Endpoint-%d!!\n", __FUNCTION__, ep_idx);
++ }
++
++ if (req->req.actual == req->req.length) {
++ done(ep, req, 0);
++
++ if(!list_empty(&ep->queue)) {
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ DEBUG_IN_EP("%s: Next Tx request start...\n", __FUNCTION__);
++ setdma_tx(ep, req);
++ }
++ }
++}
++
++static void process_ep_in_intr(struct s3c_udc *dev)
++{
++ u32 ep_int, ep_int_status, ep_ctrl;
++
++ ep_int = readl(S3C_UDC_OTG_DAINT);
++ DEBUG_IN_EP("\tDAINT : 0x%x \n", ep_int);
++
++
++ /* CONTROL IN endpont */
++ if (ep_int & (1<<EP0_CON)) {
++ ep_int_status = readl(S3C_UDC_OTG_DIEPINT0);
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ DEBUG_EP0("\tEP0-IN : DIEPINT0 = 0x%x, DIEPCTL0 = 0x%x \n", ep_int_status, ep_ctrl);
++ writel(ep_int_status, S3C_UDC_OTG_DIEPINT0); // Interrupt Clear
++
++ if (ep_int_status & TRANSFER_DONE) {
++ DEBUG_EP0("\tEP0-IN transaction completed - (TX DMA done)\n");
++
++ complete_tx(dev, EP0_CON);
++
++ if(dev->ep0state == WAIT_FOR_SETUP) {
++ writel((1 << 19)|sizeof(struct usb_ctrlrequest), S3C_UDC_OTG_DOEPTSIZ0);
++ writel(virt_to_phys(&usb_ctrl), S3C_UDC_OTG_DOEPDMA0);
++ writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL0);
++ }
++
++ }
++
++ }
++
++ /* EP2 - BULK IN endpont */
++ else if(ep_int & (1<<EP2_IN)) { /* BULK IN endpont */
++ ep_int_status = readl(S3C_UDC_OTG_DIEPINT2);
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL2);
++
++ DEBUG_IN_EP("\tEP2-IN : DIEPINT2 = 0x%x, DIEPCTL2 = 0x%x\n", ep_int_status, ep_ctrl);
++
++ if (ep_int_status & TRANSFER_DONE) {
++ DEBUG_IN_EP("\tBULK IN transaction completed - (TX DMA done)\n");
++ complete_tx(dev, EP2_IN);
++ }
++ writel(ep_int_status, S3C_UDC_OTG_DIEPINT2); // ep2 Interrupt Clear
++
++ }
++
++ /* EP3 - INTR IN endpont */
++ else if(ep_int & (1<<EP3_IN)) { /* BULK IN endpont */
++ ep_int_status = readl(S3C_UDC_OTG_DIEPINT3);
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL3);
++
++ DEBUG_IN_EP("\tEP3-IN : DIEPINT3 = 0x%x, DIEPCTL3 = 0x%x\n", ep_int_status, ep_ctrl);
++
++ if (ep_int_status & TRANSFER_DONE) {
++ DEBUG_IN_EP("\tBULK IN transaction completed - (TX DMA done)\n");
++ complete_tx(dev, EP3_IN);
++ }
++ writel(ep_int_status, S3C_UDC_OTG_DIEPINT3); // ep2 Interrupt Clear
++ }
++
++}
++
++static void process_ep_out_intr(struct s3c_udc * dev)
++{
++ u32 ep_int, ep_int_status, ep_ctrl;
++
++ ep_int = readl(S3C_UDC_OTG_DAINT);
++ DEBUG_OUT_EP("\tDAINT : 0x%x \n", ep_int);
++
++ /* CONTROL OUT endpont */
++ if (ep_int & ((1<<EP0_CON)<<16)) {
++ ep_int_status = readl(S3C_UDC_OTG_DOEPINT0);
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++ DEBUG_EP0("\tEP0-OUT : DOEPINT0 = 0x%x, DOEPCTL0 = 0x%x\n", ep_int_status, ep_ctrl);
++
++ if (ep_int_status & CTRL_OUT_EP_SETUP_PHASE_DONE) {
++
++ DEBUG_EP0("\tSETUP packet(transaction) arrived\n");
++ s3c_handle_ep0(dev);
++ writel(ep_int_status & CTRL_OUT_EP_SETUP_PHASE_DONE, S3C_UDC_OTG_DOEPINT0); // Interrupt Clear
++
++ } else if (ep_int_status & TRANSFER_DONE) {
++
++ DEBUG_EP0("\tEP0-OUT transaction completed - (RX DMA done)\n");
++ complete_rx(dev, EP0_CON);
++ writel((1 << 19)|sizeof(struct usb_ctrlrequest), S3C_UDC_OTG_DOEPTSIZ0);
++ writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL0); // ep0 OUT enable, clear nak
++ writel(ep_int_status & TRANSFER_DONE, S3C_UDC_OTG_DOEPINT0); // Interrupt Clear
++
++ } else {
++ writel(ep_int_status, S3C_UDC_OTG_DOEPINT0); // Interrupt Clear
++ }
++
++ } else if (ep_int & ((1<<EP1_OUT)<<16)) {/* EP1 - BULK OUT endpont */
++ ep_int_status = readl(S3C_UDC_OTG_DOEPINT1);
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1);
++
++ DEBUG_OUT_EP("\tEP1-OUT : DOEPINT1 = 0x%x, DOEPCTL1 = 0x%x\n", ep_int_status, ep_ctrl);
++
++ if (ep_int_status & TRANSFER_DONE) {
++ DEBUG_OUT_EP("\tBULK OUT packet(transaction) arrived - (RX DMA done)\n");
++ complete_rx(dev, EP1_OUT);
++ }
++ writel(ep_int_status, S3C_UDC_OTG_DOEPINT1); // ep1 Interrupt Clear
++
++ }
++
++
++}
++
++/*
++ * elfin usb client interrupt handler.
++ */
++static irqreturn_t s3c_udc_irq(int irq, void *_dev)
++{
++ struct s3c_udc *dev = _dev;
++ u32 intr_status;
++ u32 usb_status, gintmsk;
++
++ spin_lock(&dev->lock);
++
++ intr_status = readl(S3C_UDC_OTG_GINTSTS);
++ gintmsk = readl(S3C_UDC_OTG_GINTMSK);
++
++ DEBUG_ISR("\n**** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x, DAINT : 0x%x, DAINTMSK : 0x%x\n",
++ __FUNCTION__, intr_status, state_names[dev->ep0state], gintmsk,
++ readl(S3C_UDC_OTG_DAINT), readl(S3C_UDC_OTG_DAINTMSK));
++
++ if (!intr_status) {
++ spin_unlock(&dev->lock);
++ return IRQ_HANDLED;
++ }
++
++ if (intr_status & INT_ENUMDONE) {
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s: Speed Detection interrupt\n",
++ __FUNCTION__);
++
++ writel(INT_ENUMDONE, S3C_UDC_OTG_GINTSTS);
++ usb_status = (readl(S3C_UDC_OTG_DSTS) & 0x6);
++
++ if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
++ DEBUG_SETUP(" %s: Full Speed Detection\n",__FUNCTION__);
++ set_max_pktsize(dev, USB_SPEED_FULL);
++
++ } else {
++ DEBUG_SETUP(" %s: High Speed Detection : 0x%x\n", __FUNCTION__, usb_status);
++ set_max_pktsize(dev, USB_SPEED_HIGH);
++ }
++ }
++
++ if (intr_status & INT_EARLY_SUSPEND) {
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s:Early suspend interrupt\n", __FUNCTION__);
++ writel(INT_EARLY_SUSPEND, S3C_UDC_OTG_GINTSTS);
++ }
++
++ if (intr_status & INT_SUSPEND) {
++ usb_status = readl(S3C_UDC_OTG_DSTS);
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s:Suspend interrupt :(DSTS):0x%x\n", __FUNCTION__, usb_status);
++ writel(INT_SUSPEND, S3C_UDC_OTG_GINTSTS);
++
++ if (dev->gadget.speed != USB_SPEED_UNKNOWN
++ && dev->driver
++ && dev->driver->suspend) {
++
++ dev->driver->suspend(&dev->gadget);
++ }
++ }
++
++ if (intr_status & INT_RESUME) {
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s: Resume interrupt\n", __FUNCTION__);
++ writel(INT_RESUME, S3C_UDC_OTG_GINTSTS);
++
++ if (dev->gadget.speed != USB_SPEED_UNKNOWN
++ && dev->driver
++ && dev->driver->resume) {
++
++ dev->driver->resume(&dev->gadget);
++ }
++ }
++
++ if (intr_status & INT_RESET) {
++ usb_status = readl(S3C_UDC_OTG_GOTGCTL);
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s: Reset interrupt - (GOTGCTL):0x%x\n", __FUNCTION__, usb_status);
++ writel(INT_RESET, S3C_UDC_OTG_GINTSTS);
++
++ if((usb_status & 0xc0000) == (0x3 << 18)) {
++ if(reset_available) {
++ DEBUG_SETUP(" ===> OTG core got reset (%d)!! \n", reset_available);
++ reconfig_usbd();
++ dev->ep0state = WAIT_FOR_SETUP;
++ reset_available = 0;
++
++ writel((1 << 19)|sizeof(struct usb_ctrlrequest), S3C_UDC_OTG_DOEPTSIZ0);
++ writel(virt_to_phys(&usb_ctrl), S3C_UDC_OTG_DOEPDMA0);
++ writel(DEPCTL_EPENA |DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL0);
++ }
++ } else {
++ reset_available = 1;
++ DEBUG_SETUP(" RESET handling skipped : reset_available : %d\n", reset_available);
++ }
++ }
++
++ if (intr_status & INT_IN_EP) {
++ DEBUG_IN_EP("####################################\n");
++ DEBUG_IN_EP(" %s: EP In interrupt \n", __FUNCTION__);
++
++ process_ep_in_intr(dev);
++ }
++
++ if(intr_status & INT_OUT_EP) {
++ DEBUG_OUT_EP("####################################\n");
++ DEBUG_OUT_EP(" %s: EP In interrupt \n", __FUNCTION__);
++
++ process_ep_out_intr(dev);
++ }
++
++ spin_unlock(&dev->lock);
++
++ return IRQ_HANDLED;
++}
++
++/** Queue one request
++ * Kickstart transfer if needed
++ */
++static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
++ gfp_t gfp_flags)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep;
++ struct s3c_udc *dev;
++ unsigned long flags;
++ u32 ep_num;
++
++ req = container_of(_req, struct s3c_request, req);
++ if (unlikely(!_req || !_req->complete || !_req->buf || !list_empty(&req->queue))) {
++
++ DEBUG("%s: bad params\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++
++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
++
++ DEBUG("%s: bad ep\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ ep_num = (u32)ep_index(ep);
++ dev = ep->dev;
++ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
++
++ DEBUG("%s: bogus device state %p\n", __FUNCTION__, dev->driver);
++ return -ESHUTDOWN;
++ }
++
++ DEBUG("\n%s: %s queue req %p, len %d buf %p\n",
++ __FUNCTION__,_ep->name, _req, _req->length, _req->buf);
++
++ spin_lock_irqsave(&dev->lock, flags);
++
++ _req->status = -EINPROGRESS;
++ _req->actual = 0;
++
++ /* kickstart this i/o queue? */
++ DEBUG("%s: Add to ep=%d, Q empty=%d, stopped=%d\n",
++ __FUNCTION__, ep_num, list_empty(&ep->queue), ep->stopped);
++
++ if (list_empty(&ep->queue) && !ep->stopped) {
++ u32 csr;
++
++ if (ep_num == 0) {
++ /* EP0 */
++ list_add_tail(&req->queue, &ep->queue);
++ s3c_ep0_kick(dev, ep);
++ req = 0;
++
++ } else if (ep_num == EP2_IN || ep_num == EP3_IN) {
++ csr = readl((u32) S3C_UDC_OTG_GINTSTS);
++ DEBUG_IN_EP("%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
++ __FUNCTION__, csr);
++
++ setdma_tx(ep, req);
++
++ } else {
++ csr = readl((u32) S3C_UDC_OTG_GINTSTS);
++ DEBUG_OUT_EP("%s: ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
++ __FUNCTION__, csr);
++
++ setdma_rx(ep, req);
++ }
++ }
++
++ /* pio or dma irq handler advances the queue. */
++ if (likely(req != 0)) {
++ list_add_tail(&req->queue, &ep->queue);
++ }
++
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ return 0;
++}
++
++/****************************************************************/
++/* End Point 0 related functions */
++/****************************************************************/
++
++/* return: 0 = still running, 1 = completed, negative = errno */
++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 max;
++ unsigned count;
++ int is_last;
++
++ max = ep_maxpacket(ep);
++
++ DEBUG_EP0("%s: max = %d\n", __FUNCTION__, max);
++
++ count = setdma_tx(ep, req);
++
++ /* last packet is usually short (or a zlp) */
++ if (likely(count != max))
++ is_last = 1;
++ else {
++ if (likely(req->req.length != req->req.actual) || req->req.zero)
++ is_last = 0;
++ else
++ is_last = 1;
++ }
++
++ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
++ ep->ep.name, count,
++ is_last ? "/L" : "", req->req.length - req->req.actual, req);
++
++ /* requests complete when all IN data is in the FIFO */
++ if (is_last) {
++ ep->dev->ep0state = WAIT_FOR_SETUP;
++ return 1;
++ }
++
++ return 0;
++}
++
++static __inline__ int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
++{
++ u32 bytes;
++
++ bytes = sizeof(struct usb_ctrlrequest);
++ dma_cache_maint(&usb_ctrl, bytes, DMA_FROM_DEVICE);
++ DEBUG_EP0("%s: bytes=%d, ep_index=%d \n", __FUNCTION__, bytes, ep_index(ep));
++
++ return bytes;
++}
++
++/**
++ * udc_set_address - set the USB address for this device
++ * @address:
++ *
++ * Called from control endpoint function
++ * after it decodes a set address setup packet.
++ */
++static void udc_set_address(struct s3c_udc *dev, unsigned char address)
++{
++ u32 ctrl = readl(S3C_UDC_OTG_DCFG);
++ writel(address << 4 | ctrl, S3C_UDC_OTG_DCFG);
++ writel((1 << 19)|(0<<0), S3C_UDC_OTG_DIEPTSIZ0);
++
++ ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, S3C_UDC_OTG_DIEPCTL0); /* EP0: Control IN */
++
++ DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
++ __FUNCTION__, address, readl(S3C_UDC_OTG_DCFG));
++
++ dev->usb_address = address;
++}
++
++static void s3c_ep0_read(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret;
++
++ if (!list_empty(&ep->queue)) {
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ } else {
++ DEBUG("%s: ---> BUG\n", __FUNCTION__);
++ BUG(); //logic ensures -jassi
++ return;
++ }
++
++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n",
++ __FUNCTION__, req->req.length, req->req.actual);
++
++ if(req->req.length == 0) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ done(ep, req, 0);
++ return;
++ }
++
++ ret = setdma_rx(ep, req);
++
++ if (ret) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ done(ep, req, 0);
++ return;
++ }
++
++}
++
++/*
++ * DATA_STATE_XMIT
++ */
++static int s3c_ep0_write(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret, need_zlp = 0;
++
++ DEBUG_EP0("%s: ep0 write\n", __FUNCTION__);
++
++ if (list_empty(&ep->queue)) {
++ req = 0;
++
++ } else {
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ }
++
++ if (!req) {
++ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
++ return 0;
++ }
++
++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n",
++ __FUNCTION__, req->req.length, req->req.actual);
++
++ if (req->req.length == 0) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ s3c_send_zlp();
++ done(ep, req, 0);
++ return 1;
++ }
++
++ if (req->req.length - req->req.actual == ep0_fifo_size) {
++ /* Next write will end with the packet size, */
++ /* so we need Zero-length-packet */
++ need_zlp = 1;
++ }
++
++ ret = write_fifo_ep0(ep, req);
++
++ if ((ret == 1) && !need_zlp) {
++ /* Last packet */
++ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
++ dev->ep0state = WAIT_FOR_SETUP;
++
++ } else {
++ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
++ dev->ep0state = DATA_STATE_XMIT;
++ }
++
++ if (need_zlp) {
++ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
++ dev->ep0state = DATA_STATE_NEED_ZLP;
++ }
++
++ if(ret) {
++ done(ep, req, 0);
++ }
++
++ return 1;
++}
++
++u16 g_status;
++
++/*
++ * WAIT_FOR_SETUP (OUT_PKT_RDY)
++ */
++static void s3c_ep0_setup(struct s3c_udc *dev)
++{
++ struct s3c_ep *ep = &dev->ep[0];
++ int i, bytes, is_in;
++ u32 ep_ctrl, pktcnt;
++
++ /* Nuke all previous transfers */
++ nuke(ep, -EPROTO);
++
++ /* read control req from fifo (8 bytes) */
++ bytes = s3c_fifo_read(ep, (u32 *)&usb_ctrl, 8);
++
++ DEBUG_SETUP("Read CTRL REQ %d bytes\n", bytes);
++ DEBUG_SETUP(" CTRL.bRequestType = 0x%x (is_in %d)\n", usb_ctrl.bRequestType,
++ usb_ctrl.bRequestType & USB_DIR_IN);
++ DEBUG_SETUP(" CTRL.bRequest = 0x%x\n", usb_ctrl.bRequest);
++ DEBUG_SETUP(" CTRL.wLength = 0x%x\n", usb_ctrl.wLength);
++ DEBUG_SETUP(" CTRL.wValue = 0x%x (%d)\n", usb_ctrl.wValue, usb_ctrl.wValue >> 8);
++ DEBUG_SETUP(" CTRL.wIndex = 0x%x\n", usb_ctrl.wIndex);
++
++ /* Set direction of EP0 */
++ if (likely(usb_ctrl.bRequestType & USB_DIR_IN)) {
++ ep->bEndpointAddress |= USB_DIR_IN;
++ is_in = 1;
++
++ } else {
++ ep->bEndpointAddress &= ~USB_DIR_IN;
++ is_in = 0;
++ }
++
++ dev->req_pending = 1;
++
++ /* Handle some SETUP packets ourselves */
++ switch (usb_ctrl.bRequest) {
++ case USB_REQ_SET_ADDRESS:
++ if (usb_ctrl.bRequestType
++ != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
++ break;
++
++ DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n",
++ __FUNCTION__, usb_ctrl.wValue);
++ udc_set_address(dev, usb_ctrl.wValue);
++ return;
++
++ case USB_REQ_SET_CONFIGURATION :
++ DEBUG_SETUP("============================================\n");
++ DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n",
++ __FUNCTION__, usb_ctrl.wValue);
++config_change:
++ writel((1 << 19)|(0<<0), S3C_UDC_OTG_DIEPTSIZ0);
++
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ep_ctrl, S3C_UDC_OTG_DIEPCTL0); /* EP0: Control IN */
++
++ // For Startng EP1 on this new configuration
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1);
++ writel(DEPCTL_CNAK|DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DOEPCTL1); /* EP1: Bulk OUT */
++
++ // For starting EP2 on this new configuration
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL2);
++ writel(DEPCTL_CNAK|DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DIEPCTL2); /* EP2: Bulk IN */
++
++ // For starting EP3 on this new configuration
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL3);
++ writel(DEPCTL_CNAK|DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DIEPCTL3); /* EP3: INTR IN */
++
++ DEBUG_SETUP("%s:(DOEPCTL1):0x%x, (DIEPCTL2):0x%x, (DIEPCTL3):0x%x\n",
++ __FUNCTION__,
++ readl(S3C_UDC_OTG_DOEPCTL1),
++ readl(S3C_UDC_OTG_DIEPCTL2),
++ readl(S3C_UDC_OTG_DIEPCTL3));
++
++ DEBUG_SETUP("============================================\n");
++
++ reset_available = 1;
++ dev->req_config = 1;
++ break;
++
++ case USB_REQ_GET_DESCRIPTOR:
++ DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR \n",__FUNCTION__);
++ break;
++
++ case USB_REQ_SET_INTERFACE:
++ DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n",
++ __FUNCTION__, usb_ctrl.wValue);
++ goto config_change;
++ break;
++
++ case USB_REQ_GET_CONFIGURATION:
++ DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION \n",__FUNCTION__);
++ break;
++
++ case USB_REQ_GET_STATUS:
++ DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS \n",__FUNCTION__);
++
++ if ((usb_ctrl.bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
++ != (USB_DIR_IN | USB_TYPE_STANDARD)) {
++
++ DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS : delegated !!! \n",__FUNCTION__);
++ break;
++ }
++
++ g_status = __constant_cpu_to_le16(0);
++
++ dma_cache_maint(&g_status, 2, DMA_TO_DEVICE);
++ pktcnt = 1;
++
++ writel(virt_to_phys(&g_status), S3C_UDC_OTG_DIEPDMA0);
++ writel((pktcnt<<19)|(2<<0), (u32) S3C_UDC_OTG_DIEPTSIZ0);
++
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP0_CON<<11), (u32) S3C_UDC_OTG_DIEPCTL0);
++
++ dev->ep0state = WAIT_FOR_SETUP;
++ return;
++
++ default:
++ DEBUG_SETUP("%s: *** Default of usb_ctrl.bRequest=0x%x happened.\n",
++ __FUNCTION__, usb_ctrl.bRequest);
++ break;
++ }
++
++ if (likely(dev->driver)) {
++ /* device-2-host (IN) or no data setup command,
++ * process immediately */
++ spin_unlock(&dev->lock);
++ DEBUG_SETUP("%s: usb_ctrlrequest will be passed to fsg_setup()\n", __FUNCTION__);
++ i = dev->driver->setup(&dev->gadget, &usb_ctrl);
++ spin_lock(&dev->lock);
++
++ if (i < 0) {
++ /* setup processing failed, force stall */
++ DEBUG_SETUP("%s: gadget setup FAILED (stalling), setup returned %d\n",
++ __FUNCTION__, i);
++ /* ep->stopped = 1; */
++ dev->ep0state = WAIT_FOR_SETUP;
++ }
++ }
++}
++
++/*
++ * handle ep0 interrupt
++ */
++static void s3c_handle_ep0(struct s3c_udc *dev)
++{
++ if (dev->ep0state == WAIT_FOR_SETUP) {
++ DEBUG_EP0("%s: WAIT_FOR_SETUP\n", __FUNCTION__);
++ s3c_ep0_setup(dev);
++
++ } else {
++ DEBUG_EP0("%s: strange state!!(state = %s)\n",
++ __FUNCTION__, state_names[dev->ep0state]);
++ }
++}
++
++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
++{
++ DEBUG_EP0("%s: ep_is_in = %d\n", __FUNCTION__, ep_is_in(ep));
++ if (ep_is_in(ep)) {
++ dev->ep0state = DATA_STATE_XMIT;
++ s3c_ep0_write(dev);
++
++ } else {
++ dev->ep0state = DATA_STATE_RECV;
++ s3c_ep0_read(dev);
++ }
++}
+diff --git a/drivers/usb/gadget/s3c-udc-otg-xfer-slave.c b/drivers/usb/gadget/s3c-udc-otg-xfer-slave.c
+new file mode 100644
+index 0000000..9f9d52d
+--- /dev/null
++++ b/drivers/usb/gadget/s3c-udc-otg-xfer-slave.c
+@@ -0,0 +1,957 @@
++/*
++ * drivers/usb/gadget/s3c-udc-otg-hs-slave.c
++ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
++ *
++ * $Id: s3c-udc-otg-xfer-slave.c,v 1.2 2009/01/19 01:03:13 dasan Exp $*
++ *
++ * Copyright (C) 2009 for Samsung Electronics
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#define GINTMSK_INIT (INT_RESUME|INT_ENUMDONE|INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY)
++#define DOEPMSK_INIT (AHB_ERROR)
++#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR)
++#define GAHBCFG_INIT (PTXFE_HALF|NPTXFE_HALF|MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK)
++
++u32 tx_ep_num = 2;
++
++static int set_interface_first = 0;
++
++/*-------------------------------------------------------------------------*/
++
++/** Read to request from FIFO (max read == bytes in fifo)
++ * Return: 0 = still running, 1 = completed, negative = errno
++ */
++static int read_fifo(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 csr, gintmsk;
++ u32 *buf;
++ u32 bufferspace, count, count_bytes, is_short = 0;
++ u32 fifo = ep->fifo;
++
++ csr = readl(S3C_UDC_OTG_GRXSTSP);
++ count_bytes = (csr & 0x7ff0)>>4;
++
++ gintmsk = readl(S3C_UDC_OTG_GINTMSK);
++
++ if(!count_bytes) {
++ DEBUG_OUT_EP("%s: count_bytes %d bytes\n", __FUNCTION__, count_bytes);
++
++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY
++ writel(gintmsk | INT_RX_FIFO_NOT_EMPTY, S3C_UDC_OTG_GINTMSK);
++ return 0;
++ }
++
++ buf = req->req.buf + req->req.actual;
++ prefetchw(buf);
++ bufferspace = req->req.length - req->req.actual;
++
++ count = count_bytes / 4;
++ if(count_bytes%4) count = count + 1;
++
++ req->req.actual += min(count_bytes, bufferspace);
++
++ is_short = (count_bytes < ep->ep.maxpacket);
++ DEBUG_OUT_EP("%s: read %s, %d bytes%s req %p %d/%d GRXSTSP:0x%x\n",
++ __FUNCTION__,
++ ep->ep.name, count_bytes,
++ is_short ? "/S" : "", req, req->req.actual, req->req.length, csr);
++
++ while (likely(count-- != 0)) {
++ u32 byte = (u32) readl(fifo);
++
++ if (unlikely(bufferspace == 0)) {
++ /* this happens when the driver's buffer
++ * is smaller than what the host sent.
++ * discard the extra data.
++ */
++ if (req->req.status != -EOVERFLOW)
++ printk("%s overflow %d\n", ep->ep.name, count);
++ req->req.status = -EOVERFLOW;
++ } else {
++ *buf++ = byte;
++ bufferspace-=4;
++ }
++ }
++
++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY
++ writel(gintmsk | INT_RX_FIFO_NOT_EMPTY, S3C_UDC_OTG_GINTMSK);
++
++ /* completion */
++ if (is_short || req->req.actual == req->req.length) {
++ done(ep, req, 0);
++ return 1;
++ }
++
++ /* finished that packet. the next one may be waiting... */
++ return 0;
++}
++
++/* Inline code */
++static __inline__ int write_packet(struct s3c_ep *ep,
++ struct s3c_request *req, int max)
++{
++ u32 *buf;
++ int length, count;
++ u32 fifo = ep->fifo, in_ctrl;
++
++ buf = req->req.buf + req->req.actual;
++ prefetch(buf);
++
++ length = req->req.length - req->req.actual;
++ length = min(length, max);
++ req->req.actual += length;
++
++ DEBUG("%s: Write %d (max %d), fifo=0x%x\n",
++ __FUNCTION__, length, max, fifo);
++
++ if(ep_index(ep) == EP0_CON) {
++ writel((1<<19)|(length<<0), (u32) S3C_UDC_OTG_DIEPTSIZ0);
++
++ in_ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP2_IN<<11)| in_ctrl, (u32) S3C_UDC_OTG_DIEPCTL0);
++
++ DEBUG_EP0("%s:(DIEPTSIZ0):0x%x, (DIEPCTL0):0x%x, (GNPTXSTS):0x%x\n", __FUNCTION__,
++ readl(S3C_UDC_OTG_DIEPTSIZ0),readl(S3C_UDC_OTG_DIEPCTL0),
++ readl(S3C_UDC_OTG_GNPTXSTS));
++
++ udelay(30);
++
++ } else if ((ep_index(ep) == EP2_IN)) {
++ writel((1<<19)|(length<<0), S3C_UDC_OTG_DIEPTSIZ2);
++
++ in_ctrl = readl(S3C_UDC_OTG_DIEPCTL2);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP2_IN<<11)| in_ctrl, (u32) S3C_UDC_OTG_DIEPCTL2);
++
++ DEBUG_IN_EP("%s:(DIEPTSIZ2):0x%x, (DIEPCTL2):0x%x, (GNPTXSTS):0x%x\n", __FUNCTION__,
++ readl(S3C_UDC_OTG_DIEPTSIZ2),readl(S3C_UDC_OTG_DIEPCTL2),
++ readl(S3C_UDC_OTG_GNPTXSTS));
++
++ udelay(30);
++
++ } else if ((ep_index(ep) == EP3_IN)) {
++
++ if (set_interface_first == 1) {
++ DEBUG_IN_EP("%s: first packet write skipped after set_interface\n", __FUNCTION__);
++ set_interface_first = 0;
++ return length;
++ }
++
++ writel((1<<19)|(length<<0), S3C_UDC_OTG_DIEPTSIZ3);
++
++ in_ctrl = readl(S3C_UDC_OTG_DIEPCTL3);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP2_IN<<11)| in_ctrl, (u32) S3C_UDC_OTG_DIEPCTL3);
++
++ DEBUG_IN_EP("%s:(DIEPTSIZ3):0x%x, (DIEPCTL3):0x%x, (GNPTXSTS):0x%x\n", __FUNCTION__,
++ readl(S3C_UDC_OTG_DIEPTSIZ3),readl(S3C_UDC_OTG_DIEPCTL3),
++ readl(S3C_UDC_OTG_GNPTXSTS));
++
++ udelay(30);
++
++ } else {
++ printk("%s: --> Error Unused Endpoint!!\n",
++ __FUNCTION__);
++ BUG();
++ }
++
++ for (count=0;count<length;count+=4) {
++ writel(*buf++, fifo);
++ }
++ return length;
++}
++
++/** Write request to FIFO (max write == maxp size)
++ * Return: 0 = still running, 1 = completed, negative = errno
++ */
++static int write_fifo(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 max, gintmsk;
++ unsigned count;
++ int is_last = 0, is_short = 0;
++
++ gintmsk = readl(S3C_UDC_OTG_GINTMSK);
++
++ max = le16_to_cpu(ep->desc->wMaxPacketSize);
++ count = write_packet(ep, req, max);
++
++ /* last packet is usually short (or a zlp) */
++ if (unlikely(count != max))
++ is_last = is_short = 1;
++ else {
++ if (likely(req->req.length != req->req.actual)
++ || req->req.zero)
++ is_last = 0;
++ else
++ is_last = 1;
++ /* interrupt/iso maxpacket may not fill the fifo */
++ is_short = unlikely(max < ep_maxpacket(ep));
++ }
++
++ DEBUG_IN_EP("%s: wrote %s %d bytes%s%s req %p %d/%d\n",
++ __FUNCTION__,
++ ep->ep.name, count,
++ is_last ? "/L" : "", is_short ? "/S" : "",
++ req, req->req.actual, req->req.length);
++
++ /* requests complete when all IN data is in the FIFO */
++ if (is_last) {
++ if(!ep_index(ep)){
++ printk("%s: --> Error EP0 must not come here!\n",
++ __FUNCTION__);
++ BUG();
++ }
++ writel(gintmsk&(~INT_NP_TX_FIFO_EMPTY), S3C_UDC_OTG_GINTMSK);
++ done(ep, req, 0);
++ return 1;
++ }
++
++ // Unmask USB OTG 2.0 interrupt source : INT_NP_TX_FIFO_EMPTY
++ writel(gintmsk | INT_NP_TX_FIFO_EMPTY, S3C_UDC_OTG_GINTMSK);
++ return 0;
++}
++
++/* ********************************************************************************************* */
++/* Bulk OUT (recv)
++ */
++
++static void s3c_out_epn(struct s3c_udc *dev, u32 ep_idx)
++{
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req;
++
++ if (unlikely(!(ep->desc))) {
++ /* Throw packet away.. */
++ printk("%s: No descriptor?!?\n", __FUNCTION__);
++ return;
++ }
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next,
++ struct s3c_request, queue);
++
++ if (unlikely(!req)) {
++ DEBUG_OUT_EP("%s: NULL REQ on OUT EP-%d\n", __FUNCTION__, ep_idx);
++ return;
++
++ } else {
++ read_fifo(ep, req);
++ }
++
++}
++
++/**
++ * s3c_in_epn - handle IN interrupt
++ */
++static void s3c_in_epn(struct s3c_udc *dev, u32 ep_idx)
++{
++ struct s3c_ep *ep = &dev->ep[ep_idx];
++ struct s3c_request *req;
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ if (unlikely(!req)) {
++ DEBUG_IN_EP("%s: NULL REQ on IN EP-%d\n", __FUNCTION__, ep_idx);
++ return;
++ }
++ else {
++ write_fifo(ep, req);
++ }
++
++}
++
++/*
++ * elfin usb client interrupt handler.
++ */
++static irqreturn_t s3c_udc_irq(int irq, void *_dev)
++{
++ struct s3c_udc *dev = _dev;
++ u32 intr_status;
++ u32 usb_status, ep_ctrl, gintmsk;
++
++ spin_lock(&dev->lock);
++
++ intr_status = readl(S3C_UDC_OTG_GINTSTS);
++ gintmsk = readl(S3C_UDC_OTG_GINTMSK);
++
++ DEBUG_ISR("\n**** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x\n",
++ __FUNCTION__, intr_status, state_names[dev->ep0state], gintmsk);
++
++ if (!intr_status) {
++ spin_unlock(&dev->lock);
++ return IRQ_HANDLED;
++ }
++
++ if (intr_status & INT_ENUMDONE) {
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s: Speed Detection interrupt\n",
++ __FUNCTION__);
++ writel(INT_ENUMDONE, S3C_UDC_OTG_GINTSTS);
++
++ usb_status = (readl(S3C_UDC_OTG_DSTS) & 0x6);
++
++ if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
++ DEBUG_SETUP(" %s: Full Speed Detection\n",__FUNCTION__);
++ set_max_pktsize(dev, USB_SPEED_FULL);
++
++ } else {
++ DEBUG_SETUP(" %s: High Speed Detection : 0x%x\n", __FUNCTION__, usb_status);
++ set_max_pktsize(dev, USB_SPEED_HIGH);
++ }
++ }
++
++ if (intr_status & INT_EARLY_SUSPEND) {
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s:Early suspend interrupt\n", __FUNCTION__);
++ writel(INT_EARLY_SUSPEND, S3C_UDC_OTG_GINTSTS);
++ }
++
++ if (intr_status & INT_SUSPEND) {
++ usb_status = readl(S3C_UDC_OTG_DSTS);
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s:Suspend interrupt :(DSTS):0x%x\n", __FUNCTION__, usb_status);
++ writel(INT_SUSPEND, S3C_UDC_OTG_GINTSTS);
++
++ if (dev->gadget.speed != USB_SPEED_UNKNOWN
++ && dev->driver
++ && dev->driver->suspend) {
++
++ dev->driver->suspend(&dev->gadget);
++ }
++ }
++
++ if (intr_status & INT_RESUME) {
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s: Resume interrupt\n", __FUNCTION__);
++ writel(INT_RESUME, S3C_UDC_OTG_GINTSTS);
++
++ if (dev->gadget.speed != USB_SPEED_UNKNOWN
++ && dev->driver
++ && dev->driver->resume) {
++
++ dev->driver->resume(&dev->gadget);
++ }
++ }
++
++ if (intr_status & INT_RESET) {
++ usb_status = readl(S3C_UDC_OTG_GOTGCTL);
++ DEBUG_SETUP("####################################\n");
++ DEBUG_SETUP(" %s: Reset interrupt - (GOTGCTL):0x%x\n", __FUNCTION__, usb_status);
++ writel(INT_RESET, S3C_UDC_OTG_GINTSTS);
++
++ if((usb_status & 0xc0000) == (0x3 << 18)) {
++ if(reset_available) {
++ DEBUG_SETUP(" ===> OTG core got reset (%d)!! \n", reset_available);
++ reconfig_usbd();
++ dev->ep0state = WAIT_FOR_SETUP;
++ reset_available = 0;
++ }
++ } else {
++ reset_available = 1;
++ DEBUG_SETUP(" RESET handling skipped : reset_available : %d\n", reset_available);
++ }
++ }
++
++ if (intr_status & INT_RX_FIFO_NOT_EMPTY) {
++ u32 grx_status, packet_status, ep_num, fifoCntByte = 0;
++
++ // Mask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY
++ gintmsk &= ~INT_RX_FIFO_NOT_EMPTY;
++ writel(gintmsk, S3C_UDC_OTG_GINTMSK);
++
++ grx_status = readl(S3C_UDC_OTG_GRXSTSR);
++ DEBUG_ISR(" INT_RX_FIFO_NOT_EMPTY(GRXSTSR):0x%x, GINTMSK:0x%x\n", grx_status, gintmsk);
++
++ packet_status = grx_status & 0x1E0000;
++ fifoCntByte = (grx_status & 0x7ff0)>>4;
++ ep_num = grx_status & EP_MASK;
++
++ if (fifoCntByte) {
++
++ if (packet_status == SETUP_PKT_RECEIVED) {
++ DEBUG_EP0(" => A SETUP data packet received : %d bytes\n", fifoCntByte);
++ s3c_handle_ep0(dev);
++
++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY
++ gintmsk |= INT_RX_FIFO_NOT_EMPTY;
++
++ } else if (packet_status == OUT_PKT_RECEIVED) {
++
++ if(ep_num == EP1_OUT) {
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1);
++ DEBUG_ISR(" => A Bulk OUT data packet received : %d bytes, (DOEPCTL1):0x%x\n",
++ fifoCntByte, ep_ctrl);
++ s3c_out_epn(dev, 1);
++ gintmsk = readl(S3C_UDC_OTG_GINTMSK);
++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL1);
++ } else if (ep_num == EP0_CON) {
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++ DEBUG_EP0(" => A CONTROL OUT data packet received : %d bytes, (DOEPCTL0):0x%x\n",
++ fifoCntByte, ep_ctrl);
++ dev->ep0state = DATA_STATE_RECV;
++ s3c_ep0_read(dev);
++ gintmsk |= INT_RX_FIFO_NOT_EMPTY;
++ } else {
++ DEBUG_ISR(" => Unused EP: %d bytes, (GRXSTSR):0x%x\n", fifoCntByte, grx_status);
++ }
++ } else {
++ grx_status = readl(S3C_UDC_OTG_GRXSTSP);
++
++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY
++ gintmsk |= INT_RX_FIFO_NOT_EMPTY;
++
++ DEBUG_ISR(" => A reserved packet received : %d bytes\n", fifoCntByte);
++ }
++ } else {
++ if (dev->ep0state == DATA_STATE_XMIT) {
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++ DEBUG_EP0(" => Write ep0 continue... (DOEPCTL0):0x%x\n", ep_ctrl);
++ s3c_ep0_write(dev);
++ }
++
++ if (packet_status == SETUP_TRANSACTION_COMPLETED) {
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++ DEBUG_EP0(" => A SETUP transaction completed (DOEPCTL0):0x%x\n", ep_ctrl);
++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL0);
++
++ } else if (packet_status == OUT_TRANSFER_COMPLELTED) {
++ if (ep_num == EP1_OUT) {
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1);
++ DEBUG_ISR(" => An OUT transaction completed (DOEPCTL1):0x%x\n", ep_ctrl);
++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL1);
++ } else if (ep_num == EP0_CON) {
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0);
++ DEBUG_ISR(" => An OUT transaction completed (DOEPCTL0):0x%x\n", ep_ctrl);
++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL0);
++ } else {
++ DEBUG_ISR(" => Unused EP: %d bytes, (GRXSTSR):0x%x\n", fifoCntByte, grx_status);
++ }
++ } else if (packet_status == OUT_PKT_RECEIVED) {
++ DEBUG_ISR(" => A OUT PACKET RECEIVED (NO FIFO CNT BYTE)...(GRXSTSR):0x%x\n", grx_status);
++ } else {
++ DEBUG_ISR(" => A RESERVED PACKET RECEIVED (NO FIFO CNT BYTE)...(GRXSTSR):0x%x\n", grx_status);
++ }
++
++ grx_status = readl(S3C_UDC_OTG_GRXSTSP);
++
++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY
++ gintmsk |= INT_RX_FIFO_NOT_EMPTY;
++
++ }
++
++ // Un/Mask USB OTG 2.0 interrupt sources
++ writel(gintmsk, S3C_UDC_OTG_GINTMSK);
++
++ spin_unlock(&dev->lock);
++ return IRQ_HANDLED;
++ }
++
++
++ if (intr_status & INT_NP_TX_FIFO_EMPTY) {
++ DEBUG_ISR(" INT_NP_TX_FIFO_EMPTY (GNPTXSTS):0x%x, (GINTMSK):0x%x, ep_num=%d\n",
++ readl(S3C_UDC_OTG_GNPTXSTS),
++ readl(S3C_UDC_OTG_GINTMSK),
++ tx_ep_num);
++
++ s3c_in_epn(dev, tx_ep_num);
++ }
++
++ spin_unlock(&dev->lock);
++
++ return IRQ_HANDLED;
++}
++
++/** Queue one request
++ * Kickstart transfer if needed
++ */
++static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
++ gfp_t gfp_flags)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep;
++ struct s3c_udc *dev;
++ unsigned long flags;
++
++ req = container_of(_req, struct s3c_request, req);
++ if (unlikely(!_req || !_req->complete || !_req->buf
++ || !list_empty(&req->queue)))
++ {
++ DEBUG("%s: bad params\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ ep = container_of(_ep, struct s3c_ep, ep);
++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
++ DEBUG("%s: bad ep\n", __FUNCTION__);
++ return -EINVAL;
++ }
++
++ dev = ep->dev;
++ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
++ DEBUG("%s: bogus device state %p\n", __FUNCTION__, dev->driver);
++ return -ESHUTDOWN;
++ }
++
++ DEBUG("\n%s: %s queue req %p, len %d buf %p\n",
++ __FUNCTION__, _ep->name, _req, _req->length, _req->buf);
++
++ spin_lock_irqsave(&dev->lock, flags);
++
++ _req->status = -EINPROGRESS;
++ _req->actual = 0;
++
++ /* kickstart this i/o queue? */
++ DEBUG("%s: Add to ep=%d, Q empty=%d, stopped=%d\n",
++ __FUNCTION__, ep_index(ep), list_empty(&ep->queue), ep->stopped);
++
++ if (list_empty(&ep->queue) && likely(!ep->stopped)) {
++ u32 csr;
++
++ if (unlikely(ep_index(ep) == 0)) {
++ /* EP0 */
++ list_add_tail(&req->queue, &ep->queue);
++ s3c_ep0_kick(dev, ep);
++ req = 0;
++
++ } else if (ep_is_in(ep)) {
++ csr = readl((u32) S3C_UDC_OTG_GINTSTS);
++ DEBUG_IN_EP("%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
++ __FUNCTION__, csr);
++
++ if((csr & INT_NP_TX_FIFO_EMPTY) &&
++ (write_fifo(ep, req) == 1)) {
++ req = 0;
++ } else {
++ DEBUG("++++ IN-list_add_taill::req=%p, ep=%d\n",
++ req, ep_index(ep));
++ tx_ep_num = ep_index(ep);
++ }
++ } else {
++ csr = readl((u32) S3C_UDC_OTG_GINTSTS);
++ DEBUG_OUT_EP("%s: ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
++ __FUNCTION__, csr);
++
++ if((csr & INT_RX_FIFO_NOT_EMPTY) &&
++ (read_fifo(ep, req) == 1))
++ req = 0;
++ else
++ DEBUG("++++ OUT-list_add_taill::req=%p, DOEPCTL1:0x%x\n",
++ req, readl(S3C_UDC_OTG_DOEPCTL1));
++ }
++ }
++
++ /* pio or dma irq handler advances the queue. */
++ if (likely(req != 0))
++ list_add_tail(&req->queue, &ep->queue);
++
++ spin_unlock_irqrestore(&dev->lock, flags);
++
++ return 0;
++}
++
++/****************************************************************/
++/* End Point 0 related functions */
++/****************************************************************/
++
++/* return: 0 = still running, 1 = completed, negative = errno */
++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 max;
++ unsigned count;
++ int is_last;
++
++ max = ep_maxpacket(ep);
++
++ DEBUG_EP0("%s: max = %d\n", __FUNCTION__, max);
++
++ count = write_packet(ep, req, max);
++
++ /* last packet is usually short (or a zlp) */
++ if (likely(count != max))
++ is_last = 1;
++ else {
++ if (likely(req->req.length != req->req.actual) || req->req.zero)
++ is_last = 0;
++ else
++ is_last = 1;
++ }
++
++ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
++ ep->ep.name, count,
++ is_last ? "/L" : "", req->req.length - req->req.actual, req);
++
++ /* requests complete when all IN data is in the FIFO */
++ if (is_last) {
++ return 1;
++ }
++
++ return 0;
++}
++
++static __inline__ int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
++{
++ int bytes;
++ int count;
++ u32 grx_status = readl(S3C_UDC_OTG_GRXSTSP);
++ bytes = (grx_status & 0x7ff0)>>4;
++
++ DEBUG_EP0("%s: GRXSTSP=0x%x, bytes=%d, ep_index=%d, fifo=0x%x\n",
++ __FUNCTION__, grx_status, bytes, ep_index(ep), ep->fifo);
++
++ // 32 bits interface
++ count = bytes / 4;
++
++ while (count--) {
++ *cp++ = (u32) readl(S3C_UDC_OTG_EP0_FIFO);
++ }
++
++ return bytes;
++}
++
++static int read_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
++{
++ u32 csr;
++ u32 *buf;
++ unsigned bufferspace, count, is_short, bytes;
++ u32 fifo = ep->fifo;
++
++ DEBUG_EP0("%s\n", __FUNCTION__);
++
++ csr = readl(S3C_UDC_OTG_GRXSTSP);
++ bytes = (csr & 0x7ff0)>>4;
++
++ buf = req->req.buf + req->req.actual;
++ prefetchw(buf);
++ bufferspace = req->req.length - req->req.actual;
++
++ /* read all bytes from this packet */
++ if (likely((csr & EP_MASK) == EP0_CON)) {
++ count = bytes / 4;
++ req->req.actual += min(bytes, bufferspace);
++
++ } else { // zlp
++ count = 0;
++ bytes = 0;
++ }
++
++ is_short = (bytes < ep->ep.maxpacket);
++ DEBUG_EP0("%s: read %s %02x, %d bytes%s req %p %d/%d\n",
++ __FUNCTION__,
++ ep->ep.name, csr, bytes,
++ is_short ? "/S" : "", req, req->req.actual, req->req.length);
++
++ while (likely(count-- != 0)) {
++ u32 byte = (u32) readl(fifo);
++
++ if (unlikely(bufferspace == 0)) {
++ /* this happens when the driver's buffer
++ * is smaller than what the host sent.
++ * discard the extra data.
++ */
++ if (req->req.status != -EOVERFLOW)
++ DEBUG_EP0("%s overflow %d\n", ep->ep.name,
++ count);
++ req->req.status = -EOVERFLOW;
++ } else {
++ *buf++ = byte;
++ bufferspace = bufferspace - 4;
++ }
++ }
++
++ /* completion */
++ if (is_short || req->req.actual == req->req.length) {
++ return 1;
++ }
++
++ return 0;
++}
++
++/**
++ * udc_set_address - set the USB address for this device
++ * @address:
++ *
++ * Called from control endpoint function
++ * after it decodes a set address setup packet.
++ */
++static void udc_set_address(struct s3c_udc *dev, unsigned char address)
++{
++ u32 ctrl = readl(S3C_UDC_OTG_DCFG);
++ writel(address << 4 | ctrl, S3C_UDC_OTG_DCFG);
++
++ ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, S3C_UDC_OTG_DIEPCTL0); /* EP0: Control IN */
++
++ DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
++ __FUNCTION__, address, readl(S3C_UDC_OTG_DCFG));
++
++ dev->usb_address = address;
++}
++
++
++
++static int first_time = 1;
++
++static void s3c_ep0_read(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret;
++
++ if (!list_empty(&ep->queue))
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++ else {
++ printk("%s: ---> BUG\n", __FUNCTION__);
++ BUG(); //logic ensures -jassi
++ return;
++ }
++
++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n",
++ __FUNCTION__, req->req.length, req->req.actual);
++
++ if(req->req.length == 0) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ first_time = 1;
++ done(ep, req, 0);
++ return;
++ }
++
++ if(!req->req.actual && first_time){ //for SetUp packet
++ first_time = 0;
++ return;
++ }
++
++ ret = read_fifo_ep0(ep, req);
++ if (ret) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ first_time = 1;
++ done(ep, req, 0);
++ return;
++ }
++
++}
++
++/*
++ * DATA_STATE_XMIT
++ */
++static int s3c_ep0_write(struct s3c_udc *dev)
++{
++ struct s3c_request *req;
++ struct s3c_ep *ep = &dev->ep[0];
++ int ret, need_zlp = 0;
++
++ DEBUG_EP0("%s: ep0 write\n", __FUNCTION__);
++
++ if (list_empty(&ep->queue))
++ req = 0;
++ else
++ req = list_entry(ep->queue.next, struct s3c_request, queue);
++
++ if (!req) {
++ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
++ return 0;
++ }
++
++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n",
++ __FUNCTION__, req->req.length, req->req.actual);
++
++ if (req->req.length == 0) {
++ dev->ep0state = WAIT_FOR_SETUP;
++ done(ep, req, 0);
++ return 1;
++ }
++
++ if (req->req.length - req->req.actual == ep0_fifo_size) {
++ /* Next write will end with the packet size, */
++ /* so we need Zero-length-packet */
++ need_zlp = 1;
++ }
++
++ ret = write_fifo_ep0(ep, req);
++
++ if ((ret == 1) && !need_zlp) {
++ /* Last packet */
++ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
++ dev->ep0state = WAIT_FOR_SETUP;
++ } else {
++ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
++ }
++
++ if (need_zlp) {
++ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
++ dev->ep0state = DATA_STATE_NEED_ZLP;
++ }
++
++ if(ret)
++ done(ep, req, 0);
++
++ return 1;
++}
++
++/*
++ * WAIT_FOR_SETUP (OUT_PKT_RDY)
++ */
++static void s3c_ep0_setup(struct s3c_udc *dev)
++{
++ struct s3c_ep *ep = &dev->ep[0];
++ int i, bytes, is_in;
++ u32 ep_ctrl;
++
++ /* Nuke all previous transfers */
++ nuke(ep, -EPROTO);
++
++ /* read control req from fifo (8 bytes) */
++ bytes = s3c_fifo_read(ep, (u32 *)&usb_ctrl, 8);
++
++ DEBUG_SETUP("Read CTRL REQ %d bytes\n", bytes);
++ DEBUG_SETUP(" CTRL.bRequestType = 0x%x (is_in %d)\n", usb_ctrl.bRequestType,
++ usb_ctrl.bRequestType & USB_DIR_IN);
++ DEBUG_SETUP(" CTRL.bRequest = 0x%x\n", usb_ctrl.bRequest);
++ DEBUG_SETUP(" CTRL.wLength = 0x%x\n", usb_ctrl.wLength);
++ DEBUG_SETUP(" CTRL.wValue = 0x%x (%d)\n", usb_ctrl.wValue, usb_ctrl.wValue >> 8);
++ DEBUG_SETUP(" CTRL.wIndex = 0x%x\n", usb_ctrl.wIndex);
++
++ /* Set direction of EP0 */
++ if (likely(usb_ctrl.bRequestType & USB_DIR_IN)) {
++ ep->bEndpointAddress |= USB_DIR_IN;
++ is_in = 1;
++ } else {
++ ep->bEndpointAddress &= ~USB_DIR_IN;
++ is_in = 0;
++ }
++
++ dev->req_pending = 1;
++
++ /* Handle some SETUP packets ourselves */
++ switch (usb_ctrl.bRequest) {
++ case USB_REQ_SET_ADDRESS:
++ if (usb_ctrl.bRequestType
++ != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
++ break;
++
++ DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n",
++ __FUNCTION__, usb_ctrl.wValue);
++ udc_set_address(dev, usb_ctrl.wValue);
++ return;
++
++ case USB_REQ_SET_CONFIGURATION :
++ DEBUG_SETUP("============================================\n");
++ DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n",
++ __FUNCTION__, usb_ctrl.wValue);
++config_change:
++ // Just to send ZLP(Zero length Packet) to HOST in response to SET CONFIGURATION
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL0);
++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ep_ctrl, S3C_UDC_OTG_DIEPCTL0); /* EP0: Control IN */
++
++ // For Startng EP1 on this new configuration
++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1);
++ writel(DEPCTL_EPDIS|DEPCTL_CNAK|DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DOEPCTL1); /* EP1: Bulk OUT */
++
++ // For starting EP2 on this new configuration
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL2);
++ writel(DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DIEPCTL2); /* EP2: Bulk IN */
++
++ // For starting EP3 on this new configuration
++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL3);
++ writel(DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DIEPCTL3); /* EP3: INTR IN */
++
++ DEBUG_SETUP("%s:(DOEPCTL1):0x%x, (DIEPCTL2):0x%x, (DIEPCTL3):0x%x\n",
++ __FUNCTION__,
++ readl(S3C_UDC_OTG_DOEPCTL1),
++ readl(S3C_UDC_OTG_DIEPCTL2),
++ readl(S3C_UDC_OTG_DIEPCTL3));
++
++ DEBUG_SETUP("============================================\n");
++
++ reset_available = 1;
++ dev->req_config = 1;
++ break;
++
++ case USB_REQ_GET_DESCRIPTOR:
++ DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR \n",__FUNCTION__);
++ break;
++
++ case USB_REQ_SET_INTERFACE:
++ DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n",
++ __FUNCTION__, usb_ctrl.wValue);
++
++ set_interface_first = 1;
++ goto config_change;
++ break;
++
++ case USB_REQ_GET_CONFIGURATION:
++ DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION \n",__FUNCTION__);
++ break;
++
++ case USB_REQ_GET_STATUS:
++ DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS \n",__FUNCTION__);
++ break;
++
++ default:
++ DEBUG_SETUP("%s: *** Default of usb_ctrl.bRequest=0x%x happened.\n",
++ __FUNCTION__, usb_ctrl.bRequest);
++ break;
++ }
++
++ if (likely(dev->driver)) {
++ /* device-2-host (IN) or no data setup command,
++ * process immediately */
++ spin_unlock(&dev->lock);
++ DEBUG_SETUP("%s: usb_ctrlrequest will be passed to fsg_setup()\n", __FUNCTION__);
++ i = dev->driver->setup(&dev->gadget, &usb_ctrl);
++ spin_lock(&dev->lock);
++
++ if (i < 0) {
++ /* setup processing failed, force stall */
++ DEBUG_SETUP("%s: gadget setup FAILED (stalling), setup returned %d\n",
++ __FUNCTION__, i);
++ /* ep->stopped = 1; */
++ dev->ep0state = WAIT_FOR_SETUP;
++ }
++ }
++}
++
++/*
++ * handle ep0 interrupt
++ */
++static void s3c_handle_ep0(struct s3c_udc *dev)
++{
++ if (dev->ep0state == WAIT_FOR_SETUP) {
++ DEBUG_EP0("%s: WAIT_FOR_SETUP\n", __FUNCTION__);
++ s3c_ep0_setup(dev);
++
++ } else {
++ DEBUG_EP0("%s: strange state!!(state = %s)\n",
++ __FUNCTION__, state_names[dev->ep0state]);
++ }
++}
++
++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
++{
++ DEBUG_EP0("%s: ep_is_in = %d\n", __FUNCTION__, ep_is_in(ep));
++ if (ep_is_in(ep)) {
++ dev->ep0state = DATA_STATE_XMIT;
++ s3c_ep0_write(dev);
++ } else {
++ dev->ep0state = DATA_STATE_RECV;
++ s3c_ep0_read(dev);
++ }
++}
+diff --git a/drivers/usb/gadget/s3c-udc.h b/drivers/usb/gadget/s3c-udc.h
+new file mode 100644
+index 0000000..d64f5e6
+--- /dev/null
++++ b/drivers/usb/gadget/s3c-udc.h
+@@ -0,0 +1,136 @@
++/*
++ * drivers/usb/gadget/s3c-udc.h
++ * Samsung S3C on-chip full/high speed USB device controllers
++ * $Id: s3c-udc.h,v 1.4 2008/06/15 00:25:28 ihlee215 Exp $*
++ * Copyright (C) 2005 for Samsung Electronics
++ * - by Jaswinder Singh Brar <jassi@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#ifndef __S3C_USB_GADGET
++#define __S3C_USB_GADGET
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/ioport.h>
++#include <linux/types.h>
++#include <linux/version.h>
++#include <linux/errno.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/timer.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/proc_fs.h>
++#include <linux/mm.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++
++#include <asm/byteorder.h>
++#include <asm/dma.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/system.h>
++#include <asm/unaligned.h>
++#include <asm/hardware.h>
++//#include <asm/hardware/clock.h>
++
++#include <linux/usb/ch9.h>
++#include <linux/usb/gadget.h>
++
++// Max packet size
++#if defined(CONFIG_USB_GADGET_S3C_FS)
++#define EP0_FIFO_SIZE 8
++#define EP_FIFO_SIZE 64
++#define S3C_MAX_ENDPOINTS 5
++#elif defined(CONFIG_USB_GADGET_S3C_HS)
++#define EP0_FIFO_SIZE 64
++#define EP_FIFO_SIZE 512
++#define EP_FIFO_SIZE2 1024
++#define S3C_MAX_ENDPOINTS 9
++#else
++#define EP0_FIFO_SIZE 64
++#define EP_FIFO_SIZE 512
++#define EP_FIFO_SIZE2 1024
++#define S3C_MAX_ENDPOINTS 16
++#endif
++
++#define WAIT_FOR_SETUP 0
++#define DATA_STATE_XMIT 1
++#define DATA_STATE_NEED_ZLP 2
++#define WAIT_FOR_OUT_STATUS 3
++#define DATA_STATE_RECV 4
++#define RegReadErr 5
++#define FAIL_TO_SETUP 6
++
++/* ********************************************************************************************* */
++/* IO
++ */
++
++typedef enum ep_type {
++ ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
++} ep_type_t;
++
++struct s3c_ep {
++ struct usb_ep ep;
++ struct s3c_udc *dev;
++
++ const struct usb_endpoint_descriptor *desc;
++ struct list_head queue;
++ unsigned long pio_irqs;
++
++ u8 stopped;
++ u8 bEndpointAddress;
++ u8 bmAttributes;
++
++ ep_type_t ep_type;
++ u32 fifo;
++#ifdef CONFIG_USB_GADGET_S3C_FS
++ u32 csr1;
++ u32 csr2;
++#endif
++};
++
++struct s3c_request {
++ struct usb_request req;
++ struct list_head queue;
++};
++
++struct s3c_udc {
++ struct usb_gadget gadget;
++ struct usb_gadget_driver *driver;
++ //struct device *dev;
++ struct platform_device *dev;
++ spinlock_t lock;
++
++ int ep0state;
++ struct s3c_ep ep[S3C_MAX_ENDPOINTS];
++
++ unsigned char usb_address;
++
++ unsigned req_pending:1, req_std:1, req_config:1;
++};
++
++extern struct s3c_udc *the_controller;
++
++#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
++#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
++#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
++
++#endif
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 49a91c5..cdd0ed1 100644
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -261,3 +261,8 @@ config USB_R8A66597_HCD
+ To compile this driver as a module, choose M here: the
+ module will be called r8a66597-hcd.
+
++config USB_S3C_OTG_HOST
++ tristate "S3C USB OTG Host support"
++ depends on (USB && PLAT_S3C64XX)
++ help
++ S3C6400 & S3C6410 OTG Host.
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index bb8e9d4..8a01634 100644
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -16,4 +16,4 @@ obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o
+ obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
+ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
+ obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
+-
++obj-$(CONFIG_USB_S3C_OTG_HOST) += s3c-otg/
+diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
+index 44b79e8..c214ef5 100644
+--- a/drivers/usb/host/ohci-s3c2410.c
++++ b/drivers/usb/host/ohci-s3c2410.c
+@@ -24,6 +24,9 @@
+
+ #include <asm/hardware.h>
+ #include <asm/arch/usb-control.h>
++#include <asm/arch/regs-gpio.h>
++
++#include <asm/arch/regs-s3c-clock.h>
+
+ #define valid_port(idx) ((idx) == 1 || (idx) == 2)
+
+@@ -32,6 +35,22 @@
+ static struct clk *clk;
+ static struct clk *usb_clk;
+
++#undef USB_HOST_PORT2_EN
++//#define USB_HOST_PORT2_EN
++
++#if defined(CONFIG_PLAT_S3C64XX)
++#define S3C_USB_CLKSRC_EPLL 0
++#define S3C_USB_CLKSRC_48M 1
++extern void usb_host_clk_en(int usb_host_clksrc, u32 otg_phy_clk);
++
++#ifdef USB_HOST_PORT2_EN
++static struct clk *otg_clk;
++#define OTGH_PHY_CLK_VALUE (0x60) /* Serial Interface, Oscillator */
++#else
++#define OTGH_PHY_CLK_VALUE (0x20) /* UTMI Interface, Oscillator */
++#endif
++#endif
++
+ /* forward definitions */
+
+ static void s3c2410_hcd_oc(struct s3c2410_hcd_info *info, int port_oc);
+@@ -54,6 +73,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)
+
+ clk_enable(clk);
+
++#if defined(USB_HOST_PORT2_EN) && defined(CONFIG_PLAT_S3C64XX)
++ clk_enable(otg_clk);
++#endif
++
+ if (info != NULL) {
+ info->hcd = hcd;
+ info->report_oc = s3c2410_hcd_oc;
+@@ -332,6 +355,48 @@ usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev)
+ usb_put_hcd(hcd);
+ }
+
++#if defined(CONFIG_PLAT_S3C24XX) && defined(USB_HOST_PORT2_EN)
++#include <asm/arch/regs-udc-hs.h>
++static int usb20_phy_init(void)
++{
++ s3c2410_gpio_pullup(S3C2443_GPH14, 2); /* usb power pull-up enable */
++ s3c2410_gpio_pullup(S3C2410_GPF2, 0); /* vbus detect pull-up/down disable */
++ s3c2410_gpio_cfgpin(S3C2443_GPH14, S3C2443_GPH14_OUTP);
++ s3c2410_gpio_setpin(S3C2443_GPH14, 1); /* usb power enbale */
++
++ mdelay(1);
++
++ /* if reset by sleep wakeup, control the retention I/O cell */
++ if (readl(S3C_RSTSTAT) & 0x8)
++ writel(readl(S3C_RSTCON)|(1<<16), S3C_RSTCON);
++
++
++ /* USB Port is Normal mode */
++ writel(readl(S3C2410_MISCCR)&~(1<<12), S3C2410_MISCCR);
++
++ /* PHY power enable */
++ writel(readl(S3C_PWRCFG)|(1<<4), S3C_PWRCFG);
++
++ /* USB device 2.0 must reset like bellow,
++ * 1st phy reset and after at least 10us, func_reset & host reset
++ * phy reset can reset bellow registers.
++ */
++ /* PHY 2.0 S/W reset */
++ writel((0<<2)|(0<<1)|(1<<0), S3C_URSTCON);
++ udelay(20); /* phy reset must be asserted for at 10us */
++
++ /*Function 2.0, Host 1.1 S/W reset*/
++ writel((1<<2)|(1<<1)|(0<<0), S3C_URSTCON);
++ writel((0<<2)|(0<<1)|(0<<0), S3C_URSTCON);
++
++ writel(0x00000030, S3C2443_CLKREG(0x84));
++ writel(0x80000005, S3C2443_CLKREG(0x8c));
++ writel(5, S3C2443_CLKREG(0x80));
++
++ return 0;
++}
++#endif
++
+ /**
+ * usb_hcd_s3c2410_probe - initialize S3C2410-based HCDs
+ * Context: !in_interrupt()
+@@ -346,6 +411,20 @@ static int usb_hcd_s3c2410_probe (const struct hc_driver *driver,
+ {
+ struct usb_hcd *hcd = NULL;
+ int retval;
++#if defined(CONFIG_PLAT_S3C24XX)
++ /* USB host Power enable */
++ s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP);
++ s3c2410_gpio_pullup(S3C2410_GPB4, 0);
++ s3c2410_gpio_setpin(S3C2410_GPB4, 1);
++
++#if defined(USB_HOST_PORT2_EN) && defined(CONFIG_PLAT_S3C24XX)
++ usb20_phy_init();
++#endif
++#endif
++
++#if defined(CONFIG_PLAT_S3C64XX)
++ usb_host_clk_en(S3C_USB_CLKSRC_48M, OTGH_PHY_CLK_VALUE);
++#endif
+
+ s3c2410_usb_set_power(dev->dev.platform_data, 1, 1);
+ s3c2410_usb_set_power(dev->dev.platform_data, 2, 1);
+@@ -370,13 +449,23 @@ static int usb_hcd_s3c2410_probe (const struct hc_driver *driver,
+ goto err_mem;
+ }
+
++#if defined(USB_HOST_PORT2_EN) && defined(CONFIG_PLAT_S3C64XX)
++ otg_clk = clk_get(&dev->dev, "otg");
++ if (IS_ERR(clk)) {
++ dev_err(&dev->dev, "cannot get otg clock\n");
++ retval = -ENOENT;
++ goto err_clk;
++ }
++#endif
++
++#if defined(CONFIG_PLAT_S3C24XX)
+ usb_clk = clk_get(&dev->dev, "usb-bus-host");
+ if (IS_ERR(usb_clk)) {
+ dev_err(&dev->dev, "cannot get usb-host clock\n");
+ retval = -ENOENT;
+ goto err_clk;
+ }
+-
++#endif
+ s3c2410_start_hc(dev, hcd);
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+@@ -399,8 +488,10 @@ static int usb_hcd_s3c2410_probe (const struct hc_driver *driver,
+ iounmap(hcd->regs);
+ clk_put(usb_clk);
+
++#if defined(CONFIG_PLAT_S3C24XX) || defined(CONFIG_PLAT_S3C64XX)
+ err_clk:
+ clk_put(clk);
++#endif
+
+ err_mem:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+@@ -433,7 +524,7 @@ ohci_s3c2410_start (struct usb_hcd *hcd)
+
+ static const struct hc_driver ohci_s3c2410_hc_driver = {
+ .description = hcd_name,
+- .product_desc = "S3C24XX OHCI",
++ .product_desc = "S3C OHCI",
+ .hcd_priv_size = sizeof(struct ohci_hcd),
+
+ /*
+diff --git a/drivers/usb/host/s3c-otg/Makefile b/drivers/usb/host/s3c-otg/Makefile
+new file mode 100644
+index 0000000..12cfd34
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/Makefile
+@@ -0,0 +1,18 @@
++#
++# Makefile for USB OTG Host Controller Drivers
++#
++
++obj-$(CONFIG_USB_S3C_OTG_HOST) += s3c_otg_hcd.o
++
++s3c_otg_hcd-objs += s3c-otg-hcdi-driver.o s3c-otg-hcdi-hcd.o
++s3c_otg_hcd-objs += s3c-otg-transfer-common.o s3c-otg-transfer-nonperiodic.o \
++ s3c-otg-transfer-periodic.o
++s3c_otg_hcd-objs += s3c-otg-scheduler-ischeduler.o s3c-otg-scheduler-scheduler.o \
++ s3c-otg-scheduler-readyq.o
++s3c_otg_hcd-objs += s3c-otg-oci.o
++s3c_otg_hcd-objs += s3c-otg-transferchecker-common.o \
++ s3c-otg-transferchecker-control.o \
++ s3c-otg-transferchecker-bulk.o \
++ s3c-otg-transferchecker-interrupt.o
++s3c_otg_hcd-objs += s3c-otg-isr.o
++s3c_otg_hcd-objs += s3c-otg-roothub.o
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-common-common.h b/drivers/usb/host/s3c-otg/s3c-otg-common-common.h
+new file mode 100644
+index 0000000..ee3011d
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-common-common.h
+@@ -0,0 +1,50 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-common-common.h
++ * @brief it includes common header files for all modules \n
++ * @version
++ * ex)-# Jun 11,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _S3C_OTG_COMMON_COMMON_H_
++#define _S3C_OTG_COMMON_COMMON_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-common-errorcode.h"
++#include <linux/errno.h>
++#include <linux/usb.h>
++
++//Define OS
++#define LINUX 1
++
++//Kernel Version
++#define KERNEL_2_6_21
++
++
++#ifdef __cplusplus
++}
++#endif
++#endif /* _S3C_OTG_COMMON_COMMON_H_ */
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-common-const.h b/drivers/usb/host/s3c-otg/s3c-otg-common-const.h
+new file mode 100644
+index 0000000..bdad246
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-common-const.h
+@@ -0,0 +1,167 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : s3c-otg-common-const.h
++ * [Description] : The Header file defines constants to be used at sub-modules of S3C6400HCD.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/03
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created s3c-otg-common-const.h file and defines some constants.
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _CONST_TYPE_DEF_H_
++#define _CONST_TYPE_DEF_H_
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++
++#include "s3c-otg-common-common.h"
++
++//#include "s3c-otg-common-regdef.h"
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++/**
++ * @def OTG_PORT_NUMBER
++ *
++ * @brief write~ description
++ *
++ * describe in detail
++ */
++#define OTG_PORT_NUMBER 0
++
++
++
++//Defines Stages of Control Transfer
++#define SETUP_STAGE 1
++#define DATA_STAGE 2
++#define STATUS_STAGE 3
++#define COMPLETE_STAGE 4
++
++
++//Defines Direction of Endpoint
++#define EP_IN 1
++#define EP_OUT 0
++
++//Define speed of USB Device
++#define LOW_SPEED_OTG 2
++#define FULL_SPEED_OTG 1
++#define HIGH_SPEED_OTG 0
++#define SUPER_SPEED_OTG 3
++
++//Define multiple count of packet in periodic transfer.
++#define MULTI_COUNT_ZERO 0
++#define MULTI_COUNT_ONE 1
++#define MULTI_COUNT_TWO 2
++
++//Define USB Transfer Types.
++#define CONTROL_TRANSFER 0
++#define ISOCH_TRANSFER 1
++#define BULK_TRANSFER 2
++#define INT_TRANSFER 3
++
++#define BULK_TIMEOUT 300
++
++//Defines PID
++#define DATA0 0
++#define DATA1 2
++#define DATA2 1
++#define MDATA 3
++#define SETUP 3
++
++//Defines USB Transfer Request Size on USB2.0
++#define USB_20_STAND_DEV_REQUEST_SIZE 8
++//Define Max Channel Number
++#define MAX_CH_NUMBER 16
++//Define Channel Number
++#define CH_0 0
++#define CH_1 1
++#define CH_2 2
++#define CH_3 3
++#define CH_4 4
++#define CH_5 5
++#define CH_6 6
++#define CH_7 7
++#define CH_8 8
++#define CH_9 9
++#define CH_10 10
++#define CH_11 11
++#define CH_12 12
++#define CH_13 13
++#define CH_14 14
++#define CH_15 15
++#define CH_NONE 20
++
++
++// define the Constant for result of processing the USB Transfer.
++#define RE_TRANSMIT 1
++#define RE_SCHEDULE 2
++#define DE_ALLOCATE 3
++#define NO_ACTION 4
++
++//define the threshold value to retransmit USB Transfer
++#define RETRANSMIT_THRESHOLD 2
++
++//define the maximum size of data to be tranferred through channel.
++#define MAX_CH_TRANSFER_SIZE 65536//65535
++
++//define Max Frame Number which Synopsys OTG suppports.
++#define MAX_FRAME_NUMBER 0x3FFF
++// Channel Interrupt Status
++#define CH_STATUS_DataTglErr (0x1<<10)
++#define CH_STATUS_FrmOvrun (0x1<<9)
++#define CH_STATUS_BblErr (0x1<<8)
++#define CH_STATUS_XactErr (0x1<<7)
++#define CH_STATUS_NYET (0x1<<6)
++#define CH_STATUS_ACK (0x1<<5)
++#define CH_STATUS_NAK (0x1<<4)
++#define CH_STATUS_STALL (0x1<<3)
++#define CH_STATUS_AHBErr (0x1<<2)
++#define CH_STATUS_ChHltd (0x1<<1)
++#define CH_STATUS_XferCompl (0x1<<0)
++#define CH_STATUS_ALL 0x7FF
++
++
++//Define USB Transfer Flag..
++//typedef URB_SHORT_NOT_OK USB_TRANS_FLAG_NOT_SHORT;
++//typedef URB_ISO_ASAP USB_TRANS_FLAG_ISO_ASYNCH;
++
++#define USB_TRANS_FLAG_NOT_SHORT URB_SHORT_NOT_OK
++#define USB_TRANS_FLAG_ISO_ASYNCH URB_ISO_ASAP
++
++
++#define HFNUM_MAX_FRNUM 0x3FFF
++#define SCHEDULE_SLOT 10
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h b/drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h
+new file mode 100644
+index 0000000..f5f5d52
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h
+@@ -0,0 +1,870 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : s3c-otg-common-datastruct.h
++ * [Description] : The Header file defines Data Structures to be used at sub-modules of S3C6400HCD.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/03
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines Data Structure to be managed by Transfer.
++ * (2) 2008/08/18 by SeungSoo Yang ( ss1.yang@samsung.com )
++ * - modifying ED structure
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _DATA_STRUCT_DEF_H
++#define _DATA_STRUCT_DEF_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-hcdi-list.h"
++
++//#include "s3c-otg-common-regdef.h"
++//#include "s3c-otg-common-errorcode.h"
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++typedef struct
++{
++ u32 apll_lock; // 0x00
++ u32 MPLL_LOCK; // 0x04
++ u32 EPLL_LOCK; // 0x08
++ u32 APLL_CON; // 0x0c
++
++ u32 MPLL_CON; // 0x10
++ u32 EPLL_CON0; // 0x14
++ u32 EPLL_CON1; // 0x18
++ u32 CLK_SRC; // 0x1c
++
++ u32 CLK_DIV0; // 0x20
++ u32 CLK_DIV1; // 0x24
++ u32 CLK_DIV2; // 0x28
++ u32 CLK_OUT; // 0x2c
++
++ u32 HCLK_GATE; // 0x30
++ u32 PCLK_GATE; // 0x34
++ u32 SCLK_GATE; // 0x38
++ u32 PAD0; // 0x3c
++
++ u32 PAD1[48]; // 0x40~0xff
++
++ u32 AHB_CON0; // 0x100
++ u32 AHB_CON1; // 0x104
++ u32 AHB_CON2; // 0x108
++ u32 PAD2; // 0x10c
++
++ u32 SDMA_SEL; // 0x110
++ u32 SW_RST; // 0x114
++ u32 SYS_ID; // 0x118
++ u32 PAD3; // 0x11c
++
++ u32 MEM_SYS_CFG; // 0x120
++ u32 QOS_OVERRIDE0; // 0x124
++ u32 QOS_OVERRIDE1; // 0x128
++ u32 MEM_CFG_STAT; // 0x12c
++
++ u32 PAD4[436]; // 0x130~0x7ff
++
++ u32 PAD5; // 0x800
++ u32 PWR_CFG; // 0x804
++ u32 EINT_MASK; // 0x808
++ u32 PAD6; // 0x80c
++
++ u32 NORMAL_CFG; // 0x810
++ u32 STOP_CFG; // 0x814
++ u32 SLEEP_CFG; // 0x818
++ u32 PAD7; // 0x81c
++
++ u32 OSC_FREQ; // 0x820
++ u32 OSC_STABLE; // 0x824
++ u32 PWR_STABLE; // 0x828
++ u32 FPC_STABLE; // 0x82c
++
++ u32 MTC_STABLE; // 0x830
++ u32 PAD8[3]; // 0x834~0x83f
++
++ u32 PAD9[48]; // 0x840~0x8ff
++
++ u32 OTHERS; // 0x900
++ u32 RST_STAT; // 0x904
++ u32 WAKEUP_STAT; // 0x908
++ u32 BLK_PWR_STAT; // 0x90c
++
++ u32 PAD10[60]; // 0x910~0x9ff
++
++ u32 INFORM0; // 0xa00
++ u32 INFORM1; // 0xa04
++ u32 INFORM2; // 0xa08
++ u32 INFORM3; // 0xa0c
++
++ u32 INFORM4; // 0xa10
++ u32 INFORM5; // 0xa14
++ u32 INFORM6; // 0xa18
++ u32 INFORM7; // 0xa1c
++} S3C6400_SYSCON_REG, *PS3C6400_SYSCON_REG;
++
++typedef union _hcintmsk_t
++{
++ // raw register data
++ u32 d32;
++
++ // register bits
++ struct
++ {
++ unsigned xfercompl : 1;
++ unsigned chhltd : 1;
++ unsigned ahberr : 1;
++ unsigned stall : 1;
++ unsigned nak : 1;
++ unsigned ack : 1;
++ unsigned nyet : 1;
++ unsigned xacterr : 1;
++ unsigned bblerr : 1;
++ unsigned frmovrun : 1;
++ unsigned datatglerr : 1;
++ unsigned reserved : 21;
++ } b;
++} hcintmsk_t;
++
++typedef union _hcintn_t
++{
++ u32 d32;
++ struct
++ {
++ u32 xfercompl :1;
++ u32 chhltd :1;
++ u32 abherr :1;
++ u32 stall :1;
++ u32 nak :1;
++ u32 ack :1;
++ u32 nyet :1;
++ u32 xacterr :1;
++ u32 bblerr :1;
++ u32 frmovrun :1;
++ u32 datatglerr :1;
++ u32 reserved :21;
++ }b;
++}hcintn_t;
++
++
++typedef union _pcgcctl_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned stoppclk :1;
++ unsigned gatehclk :1;
++ unsigned pwrclmp :1;
++ unsigned rstpdwnmodule :1;
++ unsigned physuspended :1;
++ unsigned Reserved5_31 :27;
++ }b;
++}pcgcctl_t;
++
++
++typedef struct isoch_packet_desc
++{
++ u32 isoch_packiet_start_addr;// start address of buffer is buffer address + uiOffsert.
++ u32 buf_size;
++ u32 transferred_szie;
++ u32 isoch_status;
++}isoch_packet_desc_t;//, *isoch_packet_desc_t *,**isoch_packet_desc_t **;
++
++
++typedef struct standard_dev_req_info
++{
++ bool is_data_stage;
++ u8 conrol_transfer_stage;
++ u32 vir_standard_dev_req_addr;
++ u32 phy_standard_dev_req_addr;
++}standard_dev_req_info_t;
++
++
++typedef struct control_data_tgl_t
++{
++ u8 setup_tgl;
++ u8 data_tgl;
++ u8 status_tgl;
++}control_data_tgl_t;
++
++
++
++typedef struct ed_status
++{
++ u8 data_tgl;
++ control_data_tgl_t control_data_tgl;
++ bool is_ping_enable;
++ bool is_in_transfer_ready_q;
++ bool is_in_transferring;
++ u32 in_transferring_td;
++ bool is_alloc_resource_for_ed;
++}ed_status_t;//, *ed_status_t *,**ed_status_t **;
++
++
++typedef struct ed_desc
++{
++ u8 device_addr;
++ u8 endpoint_num;
++ bool is_ep_in;
++ u8 dev_speed;
++ u8 endpoint_type;
++ u16 max_packet_size;
++ u8 mc;
++ u8 interval;
++ u32 sched_frame;
++ u32 used_bus_time;
++ u8 hub_addr;
++ u8 hub_port;
++ bool is_do_split;
++}ed_dest_t;//, *ed_dest_t *,**ed_dest_t **;
++
++
++//Defines the Data Structures of Transfer.
++typedef struct hc_reg
++{
++
++ hcintmsk_t hc_int_msk;
++ hcintn_t hc_int;
++ u32 dma_addr;
++
++}hc_reg_t;//, *hc_reg_t *, **hc_reg_t **;
++
++
++typedef struct stransfer
++{
++ u32 stransfer_id;
++ u32 parent_td;
++ ed_dest_t *ed_desc_p;
++ ed_status_t *ed_status_p;
++ u32 start_vir_buf_addr;
++ u32 start_phy_buf_addr;
++ u32 buf_size;
++ u32 packet_cnt;
++ u8 alloc_chnum;
++ hc_reg_t hc_reg;
++}stransfer_t;//, *stransfer_t *,**stransfer_t **;
++
++
++typedef struct ed
++{
++ u32 ed_id;
++ bool is_halted;
++ bool is_need_to_insert_scheduler;
++ ed_dest_t ed_desc;
++ ed_status_t ed_status;
++ otg_list_head ed_list_entry;
++ otg_list_head td_list_entry;
++ otg_list_head trans_ready_q_list_entry;
++ u32 num_td;
++ void *ed_private;
++}ed_t;//, *ed_t *, **ed_t **;
++
++
++
++typedef struct td
++{
++ u32 td_id;
++ ed_t *parent_ed_p;
++ void *call_back_func_p;
++ void *call_back_func_param_p;
++ bool is_transferring;
++ bool is_transfer_done;
++ u32 transferred_szie;
++ bool is_standard_dev_req;
++ standard_dev_req_info_t standard_dev_req_info;
++ u32 vir_buf_addr;
++ u32 phy_buf_addr;
++ u32 buf_size;
++ u32 transfer_flag;
++ stransfer_t cur_stransfer;
++ USB_ERROR_CODE error_code;
++ u32 err_cnt;
++ otg_list_head td_list_entry;
++
++ //Isochronous Transfer Specific
++ u32 isoch_packet_num;
++ isoch_packet_desc_t *isoch_packet_desc_p;
++ u32 isoch_packet_index;
++ u32 isoch_packet_position;
++ u32 sched_frame;
++ u32 interval;
++ u32 used_total_bus_time;
++
++ // the private data can be used by S3C6400Interface.
++ void *td_private;
++}td_t;//, *td_t *,**td_t **;
++
++
++//Define Data Structures of Scheduler.
++typedef struct trans_ready_q
++{
++bool is_periodic_transfer;
++otg_list_head trans_ready_q_list_head;
++u32 trans_ready_entry_num;
++
++//In case of Periodic Transfer
++u32 total_perio_bus_bandwidth;
++u8 total_alloc_chnum;
++}trans_ready_q_t;//, *trans_ready_q_t *,**trans_ready_q_t **;
++
++
++//Define USB OTG Reg Data Structure by Kyuhyeok.
++
++#define MAX_COUNT 10000
++#define INT_ALL 0xffffffff
++
++typedef union _haint_t
++{
++ u32 d32;
++ struct
++ {
++ u32 reserved1 :16;
++ u32 channel_intr_15 :1;
++ u32 channel_intr_14 :1;
++ u32 channel_intr_13 :1;
++ u32 channel_intr_12 :1;
++ u32 channel_intr_11 :1;
++ u32 channel_intr_10 :1;
++ u32 channel_intr_9 :1;
++ u32 channel_intr_8 :1;
++ u32 channel_intr_7 :1;
++ u32 channel_intr_6 :1;
++ u32 channel_intr_5 :1;
++ u32 channel_intr_4 :1;
++ u32 channel_intr_3 :1;
++ u32 channel_intr_2 :1;
++ u32 channel_intr_1 :1;
++ u32 channel_intr_0 :1;
++ }b;
++}haint_t;
++
++typedef union _gresetctl_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned csftrst : 1;
++ unsigned hsftrst : 1;
++ unsigned hstfrm : 1;
++ unsigned intknqflsh : 1;
++ unsigned rxfflsh : 1;
++ unsigned txfflsh : 1;
++ unsigned txfnum : 5;
++ unsigned reserved11_29 : 19;
++ unsigned dmareq : 1;
++ unsigned ahbidle : 1;
++ } b;
++} gresetctl_t;
++
++
++typedef union _gahbcfg_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned glblintrmsk : 1;
++#define GAHBCFG_GLBINT_ENABLE 1
++ unsigned hburstlen : 4;
++#define INT_DMA_MODE_SINGLE 00
++#define INT_DMA_MODE_INCR 01
++#define INT_DMA_MODE_INCR4 03
++#define INT_DMA_MODE_INCR8 05
++#define INT_DMA_MODE_INCR16 07
++ unsigned dmaenable : 1;
++#define GAHBCFG_DMAENABLE 1
++ unsigned reserved : 1;
++ unsigned nptxfemplvl : 1;
++ unsigned ptxfemplvl : 1;
++#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
++#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
++ unsigned reserved9_31 : 22;
++ } b;
++} gahbcfg_t;
++
++typedef union _gusbcfg_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned toutcal : 3;
++ unsigned phyif : 1;
++ unsigned ulpi_utmi_sel : 1;
++ unsigned fsintf : 1;
++ unsigned physel : 1;
++ unsigned ddrsel : 1;
++ unsigned srpcap : 1;
++ unsigned hnpcap : 1;
++ unsigned usbtrdtim : 4;
++ unsigned nptxfrwnden : 1;
++ unsigned phylpwrclksel : 1;
++ unsigned reserved : 13;
++ unsigned forcehstmode : 1;
++ unsigned reserved2 : 2;
++ } b;
++} gusbcfg_t;
++
++
++typedef union _ghwcfg2_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct {
++ /* GHWCFG2 */
++ unsigned op_mode : 3;
++#define MODE_HNP_SRP_CAPABLE 0
++#define MODE_SRP_ONLY_CAPABLE 1
++#define MODE_NO_HNP_SRP_CAPABLE 2
++#define MODE_SRP_CAPABLE_DEVICE 3
++#define MODE_NO_SRP_CAPABLE_DEVICE 4
++#define MODE_SRP_CAPABLE_HOST 5
++#define MODE_NO_SRP_CAPABLE_HOST 6
++
++ unsigned architecture : 2;
++#define HWCFG2_ARCH_SLAVE_ONLY 0x00
++#define HWCFG2_ARCH_EXT_DMA 0x01
++#define HWCFG2_ARCH_INT_DMA 0x02
++
++ unsigned point2point : 1;
++ unsigned hs_phy_type : 2;
++ unsigned fs_phy_type : 2;
++ unsigned num_dev_ep : 4;
++ unsigned num_host_chan : 4;
++ unsigned perio_ep_supported : 1;
++ unsigned dynamic_fifo : 1;
++ unsigned rx_status_q_depth : 2;
++ unsigned nonperio_tx_q_depth : 2;
++ unsigned host_perio_tx_q_depth : 2;
++ unsigned dev_token_q_depth : 5;
++ unsigned reserved31 : 1;
++ } b;
++} ghwcfg2_t;
++
++typedef union _gintsts_t
++{
++ /** raw register data */
++ u32 d32;
++#define SOF_INTR_MASK 0x0008
++ /** register bits */
++ struct
++ {
++#define HOST_MODE 1
++#define DEVICE_MODE 0
++ unsigned curmode : 1;
++#define OTG_HOST_MODE 1
++#define OTG_DEVICE_MODE 0
++
++ unsigned modemismatch : 1;
++ unsigned otgintr : 1;
++ unsigned sofintr : 1;
++ unsigned rxstsqlvl : 1;
++ unsigned nptxfempty : 1;
++ unsigned ginnakeff : 1;
++ unsigned goutnakeff : 1;
++ unsigned reserved8 : 1;
++ unsigned i2cintr : 1;
++ unsigned erlysuspend : 1;
++ unsigned usbsuspend : 1;
++ unsigned usbreset : 1;
++ unsigned enumdone : 1;
++ unsigned isooutdrop : 1;
++ unsigned eopframe : 1;
++ unsigned intokenrx : 1;
++ unsigned epmismatch : 1;
++ unsigned inepint : 1;
++ unsigned outepintr : 1;
++ unsigned incompisoin : 1;
++ unsigned incompisoout : 1;
++ unsigned reserved22_23 : 2;
++ unsigned portintr : 1;
++ unsigned hcintr : 1;
++ unsigned ptxfempty : 1;
++ unsigned reserved27 : 1;
++ unsigned conidstschng : 1;
++ unsigned disconnect : 1;
++ unsigned sessreqintr : 1;
++ unsigned wkupintr : 1;
++ } b;
++} gintsts_t;
++
++
++typedef union _hcfg_t
++{
++ /** raw register data */
++ u32 d32;
++
++ /** register bits */
++ struct
++ {
++ /** FS/LS Phy Clock Select */
++ unsigned fslspclksel : 2;
++#define HCFG_30_60_MHZ 0
++#define HCFG_48_MHZ 1
++#define HCFG_6_MHZ 2
++
++ /** FS/LS Only Support */
++ unsigned fslssupp : 1;
++ } b;
++} hcfg_t;
++
++typedef union _hprt_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned prtconnsts : 1;
++ unsigned prtconndet : 1;
++ unsigned prtena : 1;
++ unsigned prtenchng : 1;
++ unsigned prtovrcurract : 1;
++ unsigned prtovrcurrchng : 1;
++ unsigned prtres : 1;
++ unsigned prtsusp : 1;
++ unsigned prtrst : 1;
++ unsigned reserved9 : 1;
++ unsigned prtlnsts : 2;
++ unsigned prtpwr : 1;
++ unsigned prttstctl : 4;
++ unsigned prtspd : 2;
++#define HPRT0_PRTSPD_HIGH_SPEED 0
++#define HPRT0_PRTSPD_FULL_SPEED 1
++#define HPRT0_PRTSPD_LOW_SPEED 2
++ unsigned reserved19_31 : 13;
++ } b;
++} hprt_t;
++
++
++typedef union _gintmsk_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned reserved0 : 1;
++ unsigned modemismatch : 1;
++ unsigned otgintr : 1;
++ unsigned sofintr : 1;
++ unsigned rxstsqlvl : 1;
++ unsigned nptxfempty : 1;
++ unsigned ginnakeff : 1;
++ unsigned goutnakeff : 1;
++ unsigned reserved8 : 1;
++ unsigned i2cintr : 1;
++ unsigned erlysuspend : 1;
++ unsigned usbsuspend : 1;
++ unsigned usbreset : 1;
++ unsigned enumdone : 1;
++ unsigned isooutdrop : 1;
++ unsigned eopframe : 1;
++ unsigned reserved16 : 1;
++ unsigned epmismatch : 1;
++ unsigned inepintr : 1;
++ unsigned outepintr : 1;
++ unsigned incompisoin : 1;
++ unsigned incompisoout : 1;
++ unsigned reserved22_23 : 2;
++ unsigned portintr : 1;
++ unsigned hcintr : 1;
++ unsigned ptxfempty : 1;
++ unsigned reserved27 : 1;
++ unsigned conidstschng : 1;
++ unsigned disconnect : 1;
++ unsigned sessreqintr : 1;
++ unsigned wkupintr : 1;
++ } b;
++} gintmsk_t;
++
++
++typedef struct _hc_t
++{
++
++ u8 hc_num; // Host channel number used for register address lookup
++
++ unsigned dev_addr : 7; // Device to access
++ unsigned ep_is_in : 1; // EP direction; 0: OUT, 1: IN
++
++ unsigned ep_num : 4; // EP to access
++ unsigned low_speed : 1; // 1: Low speed, 0: Not low speed
++ unsigned ep_type : 2; // Endpoint type.
++ // One of the following values:
++ // - OTG_EP_TYPE_CONTROL: 0
++ // - OTG_EP_TYPE_ISOC: 1
++ // - OTG_EP_TYPE_BULK: 2
++ // - OTG_EP_TYPE_INTR: 3
++
++ unsigned rsvdb1 : 1; // 8 bit padding
++
++ u8 rsvd2; // 4 byte boundary
++
++ unsigned max_packet : 12; // Max packet size in bytes
++
++ unsigned data_pid_start : 2;
++#define OTG_HC_PID_DATA0 0
++#define OTG_HC_PID_DATA2 1
++#define OTG_HC_PID_DATA1 2
++#define OTG_HC_PID_MDATA 3
++#define OTG_HC_PID_SETUP 3
++
++ unsigned multi_count : 2; // Number of periodic transactions per (micro)frame
++
++
++ // Flag to indicate whether the transfer has been started. Set to 1 if
++ // it has been started, 0 otherwise.
++ u8 xfer_started;
++
++
++ // Set to 1 to indicate that a PING request should be issued on this
++ // channel. If 0, process normally.
++ u8 do_ping;
++
++ // Set to 1 to indicate that the error count for this transaction is
++ // non-zero. Set to 0 if the error count is 0.
++ u8 error_state;
++ u32 *xfer_buff; // Pointer to the current transfer buffer position.
++ u16 start_pkt_count; // Packet count at start of transfer.
++
++ u32 xfer_len; // Total number of bytes to transfer.
++ u32 xfer_count; // Number of bytes transferred so far.
++
++
++ // Set to 1 if the host channel has been halted, but the core is not
++ // finished flushing queued requests. Otherwise 0.
++ u8 halt_pending;
++ u8 halt_status; // Reason for halting the host channel
++ u8 short_read; // Set when the host channel does a short read.
++ u8 rsvd3; // 4 byte boundary
++
++} hc_t;
++
++
++// Port status for the HC
++#define HCD_DRIVE_RESET 0x0001
++#define HCD_SEND_SETUP 0x0002
++
++#define HC_MAX_PKT_COUNT 511
++#define HC_MAX_TRANSFER_SIZE 65535
++#define MAXP_SIZE_64BYTE 64
++#define MAXP_SIZE_512BYTE 512
++#define MAXP_SIZE_1024BYTE 1024
++
++typedef union _hcchar_t
++{
++ // raw register data
++ u32 d32;
++
++ // register bits
++ struct
++ {
++ // Maximum packet size in bytes
++ unsigned mps : 11;
++
++ // Endpoint number
++ unsigned epnum : 4;
++
++ // 0: OUT, 1: IN
++ unsigned epdir : 1;
++#define HCDIR_OUT 0
++#define HCDIR_IN 1
++
++ unsigned reserved : 1;
++
++ // 0: Full/high speed device, 1: Low speed device
++ unsigned lspddev : 1;
++
++ // 0: Control, 1: Isoc, 2: Bulk, 3: Intr
++ unsigned eptype : 2;
++#define OTG_EP_TYPE_CONTROL 0
++#define OTG_EP_TYPE_ISOC 1
++#define OTG_EP_TYPE_BULK 2
++#define OTG_EP_TYPE_INTR 3
++
++ // Packets per frame for periodic transfers. 0 is reserved.
++ unsigned multicnt : 2;
++
++ // Device address
++ unsigned devaddr : 7;
++
++ // Frame to transmit periodic transaction.
++ // 0: even, 1: odd
++ unsigned oddfrm : 1;
++
++ // Channel disable
++ unsigned chdis : 1;
++
++ // Channel enable
++ unsigned chen : 1;
++ } b;
++} hcchar_t;
++
++typedef union _hctsiz_t
++{
++ // raw register data
++ u32 d32;
++
++ // register bits
++ struct
++ {
++ // Total transfer size in bytes
++ unsigned xfersize : 19;
++
++ // Data packets to transfer
++ unsigned pktcnt : 10;
++
++ // Packet ID for next data packet
++ // 0: DATA0
++ // 1: DATA2
++ // 2: DATA1
++ // 3: MDATA (non-Control), SETUP (Control)
++ unsigned pid : 2;
++#define HCTSIZ_DATA0 0
++#define HCTSIZ_DATA1 2
++#define HCTSIZ_DATA2 1
++#define HCTSIZ_MDATA 3
++#define HCTSIZ_SETUP 3
++
++ // Do PING protocol when 1
++ unsigned dopng : 1;
++ } b;
++} hctsiz_t;
++
++
++
++typedef union _grxstsr_t
++{
++ // raw register data
++ u32 d32;
++
++ // register bits
++ struct
++ {
++ unsigned Reserved : 11;
++ unsigned pktsts : 4;
++ unsigned dpid : 2;
++ unsigned bcnt : 11;
++ unsigned chnum : 4;
++ } b;
++} grxstsr_t;
++
++typedef union _hfir_t
++{
++ // raw register data
++ u32 d32;
++
++ // register bits
++ struct
++ {
++ unsigned Reserved : 16;
++ unsigned frint : 16;
++ } b;
++} hfir_t;
++
++typedef union _hfnum_t
++{
++ // raw register data
++ u32 d32;
++
++ // register bits
++ struct
++ {
++ unsigned frnum : 16;
++#define HFNUM_MAX_FRNUM 0x3FFF
++ unsigned frrem : 16;
++ } b;
++} hfnum_t;
++
++typedef union grstctl_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned csftrst : 1;
++ unsigned hsftrst : 1;
++ unsigned hstfrm : 1;
++ unsigned intknqflsh : 1;
++ unsigned rxfflsh : 1;
++ unsigned txfflsh : 1;
++ unsigned txfnum : 5;
++ unsigned reserved11_29 : 19;
++ unsigned dmareq : 1;
++ unsigned ahbidle : 1;
++ } b;
++} grstctl_t;
++
++
++
++
++typedef struct hc_info
++{
++ hcintmsk_t hc_int_msk;
++ hcintn_t hc_int;
++ u32 dma_addr;
++ hcchar_t hc_char;
++ hctsiz_t hc_size;
++}hc_info_t;//, *hc_info_t *, **hc_info_t **;
++
++#ifndef USB_MAXCHILDREN
++ #define USB_MAXCHILDREN (31)
++#endif
++
++typedef struct _usb_hub_descriptor_t
++{
++ u8 desc_length;
++ u8 desc_type;
++ u8 port_number;
++ u16 hub_characteristics;
++ u8 power_on_to_power_good;
++ u8 hub_control_current;
++ /* add 1 bit for hub status change; round to bytes */
++ u8 DeviceRemovable[(USB_MAXCHILDREN + 1 + 7) / 8];
++ u8 port_pwr_ctrl_mask[(USB_MAXCHILDREN + 1 + 7) / 8];
++}usb_hub_descriptor_t;
++
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
++
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h b/drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h
+new file mode 100644
+index 0000000..d471357
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h
+@@ -0,0 +1,114 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : s3c-otg-common-errorcode.h
++ * [Description] : The Header file defines Error Codes to be used at sub-modules of S3C6400HCD.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/03
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file.
++ * (2) 2008/08/18 by SeungSoo Yang ( ss1.yang@samsung.com )
++ * - add HCD error code
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _ERROR_CODE_DEF_H
++#define _ERROR_CODE_DEF_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-common-common.h"
++
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++
++typedef int USB_ERROR_CODE;
++
++//General USB Error Code.
++#define USB_ERR_SUCCESS 0
++#define USB_ERR_FAIL -1
++
++#define USB_ERR_NO 1
++
++#define USB_ERR_NO_ENTITY -2
++
++//S3CTransfer Error Code
++#define USB_ERR_NODEV -ENODEV
++#define USB_ERR_NOMEM -ENOMEM
++#define USB_ERR_NOSPACE -ENOSPC
++
++//OTG-HCD error code
++#define USB_ERR_NOELEMENT -ENOENT
++#define USB_ERR_ESHUTDOWN -ESHUTDOWN /* unplug */
++#define USB_ERR_DEQUEUED -ECONNRESET /* unlink */
++
++
++//S3CScheduler Error Code
++#define USB_ERR_ALREADY_EXIST -1
++#define USB_ERR_NO_RESOURCE -2
++#define USB_ERR_NO_CHANNEL -3
++#define USB_ERR_NO_BANDWIDTH -4
++#define USB_ERR_ALL_RESROUCE -5
++
++
++
++
++/************************************************
++ *Defines the USB Error Status Code of USB Transfer.
++ ************************************************/
++
++//#ifdef LINUX
++
++#define USB_ERR_STATUS_COMPLETE 0
++#define USB_ERR_STATUS_INPROGRESS -EINPROGRESS
++#define USB_ERR_STATUS_CRC -EILSEQ
++#define USB_ERR_STATUS_XACTERR -EPROTO
++#define USB_ERR_STATUS_STALL -EPIPE
++#define USB_ERR_STATUS_BBLERR -EOVERFLOW
++#define USB_ERR_STATUS_AHBERR -EIO
++#define USB_ERR_STATUS_FRMOVRUN_OUT -ENOSR
++#define USB_ERR_STATUS_FRMOVRUN_IN -ECOMM
++#define USB_ERR_STATUS_SHORTREAD -EREMOTEIO
++
++//#else
++
++//#endif
++
++
++
++
++
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h b/drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h
+new file mode 100644
+index 0000000..cfccc4a
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h
+@@ -0,0 +1,317 @@
++/****************************************************************************
++* (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++*
++* [File Name] : S3C6400_OtgDevice.h
++* [Description] :
++*
++* [Author] : Kyu Hyeok Jang { kyuhyeok.jang@samsung.com }
++* [Department] : System LSI Division/Embedded Software Center
++* [Created Date]: 2007/12/15
++* [Revision History]
++* (1) 2007/12/15 by Kyu Hyeok Jang { kyuhyeok.jang@samsung.com }
++* - Created
++*
++****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _OTG_REG_DEF_H
++#define _OTG_REG_DEF_H
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++//#include "s3c-otg-common-typedef.h"
++
++#define RegOpenKey(hkey, lpsz, phk) \
++ RegOpenKeyEx((hkey), (lpsz), 0, 0, (phk))
++
++#define OTG_LINK_REG_SIZE 0x11000
++
++// "IoBase"=dword:B1800000
++// "IoLen"=dword:11000 ; chandolp 1000 --> 10000
++
++////////////////////////////////////////////////////////////
++#define S3C6400_BASE_REG_PA_USBOTG_PHY 0x7C100000
++#define S3C6400_BASE_REG_PA_SYSCON 0x7E00F000
++////////////////////////////////////////////////////////////
++
++typedef struct {
++ u32 OPHYPWR;
++ u32 OPHYCLK;
++ u32 ORSTCON;
++}OTG_PHY_REG, *PS_OTG_PHY_REG;
++
++#define GOTGCTL 0x000 // OTG Control & Status
++#define GOTGINT 0x004 // OTG Interrupt
++#define GAHBCFG 0x008 // Core AHB Configuration
++#define GUSBCFG 0x00C // Core USB Configuration
++#define GRSTCTL 0x010 // Core Reset
++#define GINTSTS 0x014 // Core Interrupt
++#define GINTMSK 0x018 // Core Interrupt Mask
++#define GRXSTSR 0x01C // Receive Status Debug Read/Status Read
++#define GRXSTSP 0x020 // Receive Status Debug Pop/Status Pop
++#define GRXFSIZ 0x024 // Receive FIFO Size
++#define GNPTXFSIZ 0x028 // Non-Periodic Transmit FIFO Size
++#define GNPTXSTS 0x02C // Non-Periodic Transmit FIFO/Queue Status
++#define GPVNDCTL 0x034 // PHY Vendor Control
++#define GGPIO 0x038 // General Purpose I/O
++#define GUID 0x03C // User ID
++#define GSNPSID 0x040 // Synopsys ID
++#define GHWCFG1 0x044 // User HW Config1
++#define GHWCFG2 0x048 // User HW Config2
++#define GHWCFG3 0x04C // User HW Config3
++#define GHWCFG4 0x050 // User HW Config4
++
++#define HPTXFSIZ 0x100 // Host Periodic Transmit FIFO Size
++#define DPTXFSIZ1 0x104 // Device Periodic Transmit FIFO-1 Size
++#define DPTXFSIZ2 0x108 // Device Periodic Transmit FIFO-2 Size
++#define DPTXFSIZ3 0x10C // Device Periodic Transmit FIFO-3 Size
++#define DPTXFSIZ4 0x110 // Device Periodic Transmit FIFO-4 Size
++#define DPTXFSIZ5 0x114 // Device Periodic Transmit FIFO-5 Size
++#define DPTXFSIZ6 0x118 // Device Periodic Transmit FIFO-6 Size
++#define DPTXFSIZ7 0x11C // Device Periodic Transmit FIFO-7 Size
++#define DPTXFSIZ8 0x120 // Device Periodic Transmit FIFO-8 Size
++#define DPTXFSIZ9 0x124 // Device Periodic Transmit FIFO-9 Size
++#define DPTXFSIZ10 0x128 // Device Periodic Transmit FIFO-10 Size
++#define DPTXFSIZ11 0x12C // Device Periodic Transmit FIFO-11 Size
++#define DPTXFSIZ12 0x130 // Device Periodic Transmit FIFO-12 Size
++#define DPTXFSIZ13 0x134 // Device Periodic Transmit FIFO-13 Size
++#define DPTXFSIZ14 0x138 // Device Periodic Transmit FIFO-14 Size
++#define DPTXFSIZ15 0x13C // Device Periodic Transmit FIFO-15 Size
++
++//*********************************************************************
++// Host Mode Registers
++//*********************************************************************
++// Host Global Registers
++
++// Channel specific registers
++#define HCCHAR_ADDR 0x500
++#define HCCHAR(n) 0x500 + ((n)*0x20)
++#define HCSPLT(n) 0x504 + ((n)*0x20)
++#define HCINT(n) 0x508 + ((n)*0x20)
++#define HCINTMSK(n) 0x50C + ((n)*0x20)
++#define HCTSIZ(n) 0x510 + ((n)*0x20)
++#define HCDMA(n) 0x514 + ((n)*0x20)
++
++#define HCFG 0x400 // Host Configuration
++#define HFIR 0x404 // Host Frame Interval
++#define HFNUM 0x408 // Host Frame Number/Frame Time Remaining
++#define HPTXSTS 0x410 // Host Periodic Transmit FIFO/Queue Status
++#define HAINT 0x414 // Host All Channels Interrupt
++#define HAINTMSK 0x418 // Host All Channels Interrupt Mask
++
++// Host Port Control & Status Registers
++
++#define HPRT 0x440 // Host Port Control & Status
++
++// Device Logical Endpoints-Specific Registers
++
++#define DIEPCTL 0x900 // Device IN Endpoint 0 Control
++#define DOEPCTL(n) 0xB00 + ((n)*0x20)) // Device OUT Endpoint 0 Control
++#define DIEPINT(n) 0x908 + ((n)*0x20)) // Device IN Endpoint 0 Interrupt
++#define DOEPINT(n) 0xB08 + ((n)*0x20)) // Device OUT Endpoint 0 Interrupt
++#define DIEPTSIZ(n) 0x910 + ((n)*0x20)) // Device IN Endpoint 0 Transfer Size
++#define DOEPTSIZ(n) 0xB10 + ((n)*0x20)) // Device OUT Endpoint 0 Transfer Size
++#define DIEPDMA(n) 0x914 + ((n)*0x20)) // Device IN Endpoint 0 DMA Address
++#define DOEPDMA(n) 0xB14 + ((n)*0x20)) // Device OUT Endpoint 0 DMA Address
++
++#define EP_FIFO(n) 0x1000 + ((n)*0x1000))
++
++#define PCGCCTL 0x0E00
++
++//
++#define BASE_REGISTER_OFFSET 0x0
++#define REGISTER_SET_SIZE 0x200
++
++// Power Reg Bits
++#define USB_RESET 0x8
++#define MCU_RESUME 0x4
++#define SUSPEND_MODE 0x2
++#define SUSPEND_MODE_ENABLE_CTRL 0x1
++
++// EP0 CSR
++#define EP0_OUT_PACKET_RDY 0x1
++#define EP0_IN_PACKET_RDY 0x2
++#define EP0_SENT_STALL 0x4
++#define DATA_END 0x8
++#define SETUP_END 0x10
++#define EP0_SEND_STALL 0x20
++#define SERVICED_OUT_PKY_RDY 0x40
++#define SERVICED_SETUP_END 0x80
++
++// IN_CSR1_REG Bit definitions
++#define IN_PACKET_READY 0x1
++#define UNDER_RUN 0x4 // Iso Mode Only
++#define FLUSH_IN_FIFO 0x8
++#define IN_SEND_STALL 0x10
++#define IN_SENT_STALL 0x20
++#define IN_CLR_DATA_TOGGLE 0x40
++
++// OUT_CSR1_REG Bit definitions
++#define OUT_PACKET_READY 0x1
++#define FLUSH_OUT_FIFO 0x10
++#define OUT_SEND_STALL 0x20
++#define OUT_SENT_STALL 0x40
++#define OUT_CLR_DATA_TOGGLE 0x80
++
++// IN_CSR2_REG Bit definitions
++#define IN_DMA_INT_DISABLE 0x10
++#define SET_MODE_IN 0x20
++
++#define EPTYPE (0x3<<18)
++#define SET_TYPE_CONTROL (0x0<<18)
++#define SET_TYPE_ISO (0x1<<18)
++#define SET_TYPE_BULK (0x2<<18)
++#define SET_TYPE_INTERRUPT (0x3<<18)
++
++#define AUTO_MODE 0x80
++
++// OUT_CSR2_REG Bit definitions
++#define AUTO_CLR 0x40
++#define OUT_DMA_INT_DISABLE 0x20
++
++// Can be used for Interrupt and Interrupt Enable Reg - common bit def
++#define EP0_IN_INT (0x1<<0)
++#define EP1_IN_INT (0x1<<1)
++#define EP2_IN_INT (0x1<<2)
++#define EP3_IN_INT (0x1<<3)
++#define EP4_IN_INT (0x1<<4)
++#define EP5_IN_INT (0x1<<5)
++#define EP6_IN_INT (0x1<<6)
++#define EP7_IN_INT (0x1<<7)
++#define EP8_IN_INT (0x1<<8)
++#define EP9_IN_INT (0x1<<9)
++#define EP10_IN_INT (0x1<<10)
++#define EP11_IN_INT (0x1<<11)
++#define EP12_IN_INT (0x1<<12)
++#define EP13_IN_INT (0x1<<13)
++#define EP14_IN_INT (0x1<<14)
++#define EP15_IN_INT (0x1<<15)
++#define EP0_OUT_INT (0x1<<16)
++#define EP1_OUT_INT (0x1<<17)
++#define EP2_OUT_INT (0x1<<18)
++#define EP3_OUT_INT (0x1<<19)
++#define EP4_OUT_INT (0x1<<20)
++#define EP5_OUT_INT (0x1<<21)
++#define EP6_OUT_INT (0x1<<22)
++#define EP7_OUT_INT (0x1<<23)
++#define EP8_OUT_INT (0x1<<24)
++#define EP9_OUT_INT (0x1<<25)
++#define EP10_OUT_INT (0x1<<26)
++#define EP11_OUT_INT (0x1<<27)
++#define EP12_OUT_INT (0x1<<28)
++#define EP13_OUT_INT (0x1<<29)
++#define EP14_OUT_INT (0x1<<30)
++#define EP15_OUT_INT (0x1<<31)
++
++// GOTGINT
++#define SesEndDet (0x1<<2)
++
++// GRSTCTL
++#define TxFFlsh (0x1<<5)
++#define RxFFlsh (0x1<<4)
++#define INTknQFlsh (0x1<<3)
++#define FrmCntrRst (0x1<<2)
++#define HSftRst (0x1<<1)
++#define CSftRst (0x1<<0)
++
++#define CLEAR_ALL_EP_INTRS 0xffffffff
++
++#define EP_INTERRUPT_DISABLE_ALL 0x0 // Bits to write to EP_INT_EN_REG - Use CLEAR
++
++// DMA control register bit definitions
++#define RUN_OB 0x80
++#define STATE 0x70
++#define DEMAND_MODE 0x8
++#define OUT_DMA_RUN 0x4
++#define IN_DMA_RUN 0x2
++#define DMA_MODE_EN 0x1
++
++
++#define REAL_PHYSICAL_ADDR_EP0_FIFO (0x520001c0) //Endpoint 0 FIFO
++#define REAL_PHYSICAL_ADDR_EP1_FIFO (0x520001c4) //Endpoint 1 FIFO
++#define REAL_PHYSICAL_ADDR_EP2_FIFO (0x520001c8) //Endpoint 2 FIFO
++#define REAL_PHYSICAL_ADDR_EP3_FIFO (0x520001cc) //Endpoint 3 FIFO
++#define REAL_PHYSICAL_ADDR_EP4_FIFO (0x520001d0) //Endpoint 4 FIFO
++
++// GAHBCFG
++#define MODE_DMA (1<<5)
++#define MODE_SLAVE (0<<5)
++#define BURST_SINGLE (0<<1)
++#define BURST_INCR (1<<1)
++#define BURST_INCR4 (3<<1)
++#define BURST_INCR8 (5<<1)
++#define BURST_INCR16 (7<<1)
++#define GBL_INT_MASK (0<<0)
++#define GBL_INT_UNMASK (1<<0)
++
++// For USB DMA
++//BOOL InitUsbdDriverGlobals(void); //:-)
++//void UsbdDeallocateVm(void); //:-)
++//BOOL UsbdAllocateVm(void); //:-)
++//void UsbdInitDma(int epnum, int bufIndex,int bufOffset); //:-)
++
++
++//by Kevin
++
++//////////////////////////////////////////////////////////////////////////
++
++/*
++inline u32 ReadReg(
++ u32 uiOffset
++ )
++{
++ volatile u32 *pbReg = ctrlr_base_reg_addr(uiOffset);
++ u32 uiValue = (u32) *pbReg;
++ return uiValue;
++}
++
++inline void WriteReg(
++ u32 uiOffset,
++ u32 bValue
++ )
++{
++ volatile ULONG *pbReg = ctrlr_base_reg_addr(uiOffset);
++ *pbReg = (ULONG) bValue;
++}
++
++inline void UpdateReg(
++ u32 uiOffset,
++ u32 bValue
++ )
++{
++ WriteReg(uiOffset, (ReadReg(uiOffset) | bValue));
++};
++
++inline void ClearReg(
++ u32 uiOffeset,
++ u32 bValue
++ )
++{
++ WriteReg(uiOffeset, (ReadReg(uiOffeset) & ~bValue));
++};
++*/
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif //_S3C6400OTGDEVICE_H_
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h
+new file mode 100644
+index 0000000..cbbf452
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h
+@@ -0,0 +1,96 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-debug.c
++ * @brief It provides debug functions for display message \n
++ * @version
++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _S3C_OTG_HCDI_DEBUG_H_
++#define _S3C_OTG_HCDI_DEBUG_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++
++#ifdef OTG_DEBUG
++
++#define OTG_DBG_ACTIVE true
++#define OTG_DBG_INACTIVE false
++
++#define OTG_DBG_OTGHCDI true
++#define OTG_DBG_OTGHCDI_DRIVER true
++#define OTG_DBG_OTGHCDI_HCD true
++#define OTG_DBG_OTGHCDI_KAL true
++#define OTG_DBG_OTGHCDI_LIST false
++#define OTG_DBG_OTGHCDI_MEM false
++
++#define OTG_DBG_TRANSFER false
++#define OTG_DBG_SCHEDULE false
++#define OTG_DBG_OCI false
++#define OTG_DBG_DONETRASF false
++#define OTG_DBG_ISR false
++#define OTG_DBG_ROOTHUB false
++
++
++#if defined(__linux__)
++
++#include <linux/kernel.h> //for printk
++
++# define otg_err(is_active, msg...) \
++ do{ if ((is_active) == true)\
++ {\
++ printk(KERN_ERR "otg_err: in %s()::%05d ", __func__ , __LINE__); \
++ printk("=> " msg); \
++ }\
++ }while(0)
++
++# define otg_dbg(is_active, msg...) \
++ do{ if ((is_active) == true)\
++ {\
++ printk(KERN_DEBUG "otg_dbg: in %s()::%05d ", __func__, __LINE__); \
++ printk("=> " msg); \
++ }\
++ }while(0)
++
++#else
++
++#error Not supported OS
++
++#endif
++
++#else //OTG_DEBUG
++
++# define otg_err(is_active, msg...) do{}while(0)
++# define otg_dbg(is_active, msg...) do{}while(0)
++
++#endif
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _S3C_OTG_HCDI_DEBUG_H_ */
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c
+new file mode 100644
+index 0000000..9ab4cf2
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c
+@@ -0,0 +1,256 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-driver.c
++ * @brief It provides functions related with module for OTGHCD driver. \n
++ * @version
++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Modifying for successful rmmod & disconnecting \n
++ * @see None
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-hcdi-driver.h"
++
++/**
++ * static int s3c6410_otg_drv_probe (struct platform_device *pdev)
++ *
++ * @brief probe function of OTG hcd platform_driver
++ *
++ * @param [in] pdev : pointer of platform_device of otg hcd platform_driver
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If fail \n
++ * @remark
++ * it allocates resources of it and call other modules' init function.
++ * then call usb_create_hcd, usb_add_hcd, s3c6410_otghcd_start functions
++ */
++
++static int s3c6410_otg_drv_probe (struct platform_device *pdev)
++{
++
++ int ret_val = 0;
++ u32 reg_val = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c6410_otg_drv_probe \n");
++
++/**
++ 2.6.20+ requires pdev.dma_mask to be set prior to calling usb_create_hcd()
++ Set device flags indicating whether the HCD supports DMA.
++*/
++ pdev->dev.dma_mask = (void *) ~0;
++ pdev->dev.coherent_dma_mask = ~0;
++
++
++///init for host mode
++/**
++ Allocate memory for the base HCD & Initialize the base HCD.
++*/
++ g_pUsbHcd = usb_create_hcd(&s3c6410_otg_hc_driver, &pdev->dev, pdev->dev.bus_id);
++ if (g_pUsbHcd == NULL)
++ {
++ ret_val = -ENOMEM;
++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "failed to usb_create_hcd\n");
++ goto err_out_clk;
++ }
++
++
++// mapping hcd resource & device resource
++
++ g_pUsbHcd->rsrc_start = pdev->resource[0].start;
++ g_pUsbHcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
++
++ if (!request_mem_region(g_pUsbHcd->rsrc_start, g_pUsbHcd->rsrc_len, gHcdName))
++ {
++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "failed to request_mem_region\n");
++ reg_val = -EBUSY;
++ goto err_out_create_hcd;
++ }
++
++
++//Physical address => Virtual address
++ g_pUsbHcd->regs = S3C24XX_VA_OTG;
++ g_pUsbHcd->self.otg_port = 1;
++
++ g_pUDCBase = (u8 *)g_pUsbHcd->regs;
++
++ /// call others' init()
++ reg_val = otg_hcd_init_modules();
++ if( reg_val != USB_ERR_SUCCESS)
++ {
++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "failed to otg_hcd_init_modules\n");
++ reg_val = USB_ERR_FAIL;
++ goto err_out_create_hcd;
++ }
++
++ /**
++ * Attempt to ensure this device is really a s3c6410 USB-OTG Controller.
++ * Read and verify the SNPSID register contents. The value should be
++ * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
++ */
++ //reg_val = read_reg_32((unsigned int *)((u8 *)g_pUsbHcd->regs + 0x40));
++
++ reg_val = read_reg_32(0x40);
++ if ((reg_val & 0xFFFFF000) != 0x4F542000)
++ {
++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "Bad value for SNPSID: 0x%08x\n", (u16)reg_val);
++ ret_val = -EINVAL;
++ goto err_out_create_hcd_init;
++ }
++
++ /*
++ * Finish generic HCD initialization and start the HCD. This function
++ * allocates the DMA buffer pool, registers the USB bus, requests the
++ * IRQ line, and calls s3c6410_otghcd_start method.
++ */
++ ret_val = usb_add_hcd(g_pUsbHcd, pdev->resource[1].start, IRQF_DISABLED);
++ if (ret_val < 0)
++ {
++ goto err_out_create_hcd_init;
++ }
++
++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER,"OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
++ "EMSP OTG Controller", g_pUsbHcd->self.busnum);
++ return USB_ERR_SUCCESS;
++
++err_out_create_hcd_init:
++ otg_hcd_deinit_modules();
++ release_mem_region(g_pUsbHcd->rsrc_start, g_pUsbHcd->rsrc_len);
++
++err_out_create_hcd:
++ usb_put_hcd(g_pUsbHcd);
++
++err_out_clk:
++
++ return ret_val;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * static int s3c6410_otg_drv_remove (struct platform_device *dev)
++ *
++ * @brief remove function of OTG hcd platform_driver
++ *
++ * @param [in] pdev : pointer of platform_device of otg hcd platform_driver
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If fail \n
++ * @remark
++ * This function is called when the otg device unregistered with the
++ * s3c6410_otg_driver. This happens, for example, when the rmmod command is
++ * executed. The device may or may not be electrically present. If it is
++ * present, the driver stops device processing. Any resources used on behalf
++ * of this device are freed.
++ */
++static int s3c6410_otg_drv_remove (struct platform_device *dev)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c6410_otg_drv_remove \n");
++
++ otg_hcd_deinit_modules();
++
++ usb_remove_hcd(g_pUsbHcd);
++
++ release_mem_region(g_pUsbHcd->rsrc_start, g_pUsbHcd->rsrc_len);
++
++ usb_put_hcd(g_pUsbHcd);
++
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * @struct s3c6410_otg_driver
++ *
++ * @brief
++ * This structure defines the methods to be called by a bus driver
++ * during the lifecycle of a device on that bus. Both drivers and
++ * devices are registered with a bus driver. The bus driver matches
++ * devices to drivers based on information in the device and driver
++ * structures.
++ *
++ * The probe function is called when the bus driver matches a device
++ * to this driver. The remove function is called when a device is
++ * unregistered with the bus driver.
++ */
++static struct platform_driver s3c6410_otg_driver = {
++ .probe = s3c6410_otg_drv_probe,
++ .remove = s3c6410_otg_drv_remove,
++ .shutdown = usb_hcd_platform_shutdown,
++ .driver = {
++ .name = "s3c6410_OTGHCD",
++ .owner = THIS_MODULE,
++ },
++};
++//-------------------------------------------------------------------------------
++
++/**
++ * static int __init s3c6410_otg_module_init(void)
++ *
++ * @brief module_init function
++ *
++ * @return it returns result of platform_driver_register
++ * @remark
++ * This function is called when the s3c6410_otg_driver is installed with the
++ * insmod command. It registers the s3c6410_otg_driver structure with the
++ * appropriate bus driver. This will cause the s3c6410_otg_driver_probe function
++ * to be called. In addition, the bus driver will automatically expose
++ * attributes defined for the device and driver in the special sysfs file
++ * system.
++ */
++static int __init s3c6410_otg_module_init(void)
++{
++ int ret_val = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c6410_otg_module_init \n");
++
++ ret_val = platform_driver_register(&s3c6410_otg_driver);
++ if (ret_val < 0)
++ {
++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "platform_driver_register \n");
++ }
++ return ret_val;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * static void __exit s3c6410_otg_module_exit(void)
++ *
++ * @brief module_exit function
++ *
++ * @remark
++ * This function is called when the driver is removed from the kernel
++ * with the rmmod command. The driver unregisters itself with its bus
++ * driver.
++ */
++static void __exit s3c6410_otg_module_exit(void)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c6410_otg_module_exit \n");
++ platform_driver_unregister(&s3c6410_otg_driver);
++}
++//-------------------------------------------------------------------------------
++
++module_init(s3c6410_otg_module_init);
++module_exit(s3c6410_otg_module_exit);
++
++MODULE_DESCRIPTION("OTG USB HOST controller driver");
++MODULE_AUTHOR("SAMSUNG / System LSI / EMSP");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h
+new file mode 100644
+index 0000000..e00f57d
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h
+@@ -0,0 +1,73 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-driver.h
++ * @brief header of s3c-otg-hcdi-driver \n
++ * @version
++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Modifying for successful rmmod & disconnecting \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _S3C_OTG_HCDI_DRIVER_H_
++#define _S3C_OTG_HCDI_DRIVER_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++#include <linux/module.h>
++#include <linux/init.h>
++//#include <linux/clk.h> //for clk_get, clk_enable etc.
++
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h> //for SA_SHIRQ
++#include <asm/arch/map.h> //address for smdk
++#include <linux/dma-mapping.h> //dma_alloc_coherent
++#include <linux/ioport.h> //request_mem_request ...
++#include <asm/arch/irqs.h> //for IRQ_OTG
++
++//#include <asm/io.h> //for ioremap
++
++#include "s3c-otg-common-common.h"
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-hcdi-hcd.h"
++#include "s3c-otg-hcdi-kal.h"
++
++//struct clk* g_pOTG_clock = NULL;
++struct usb_hcd* g_pUsbHcd = NULL;
++
++volatile u8 * g_pUDCBase;
++
++static const char gHcdName[] = "EMSP_OTG_HCD";
++
++extern int otg_hcd_init_modules(void);
++extern void otg_hcd_deinit_modules(void);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _S3C_OTG_HCDI_DRIVER_H_ */
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c
+new file mode 100644
+index 0000000..cfb8590
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c
+@@ -0,0 +1,651 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-hcd.c
++ * @brief implementation of structure hc_drive \n
++ * @version
++ * -# Jun 11,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Modifying for successful rmmod & disconnecting \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-hcdi-hcd.h"
++
++static SPINLOCK_t otg_hcd_spin_lock = SPIN_LOCK_INIT;
++
++/**
++ * otg_hcd_init_modules()
++ *
++ * @brief call other modules' init functions
++ *
++ * @return PASS : If success \n
++ * FAIL : If fail \n
++ */
++int otg_hcd_init_modules(void)
++{
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "OTGHCD_InitModuless \n");
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ init_transfer();
++ init_scheduler();
++ oci_init();
++
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ return USB_ERR_SUCCESS;
++};
++
++/**
++ * void otg_hcd_deinit_modules(void)
++ *
++ * @brief call other modules' de-init functions
++ *
++ * @return PASS : If success \n
++ * FAIL : If fail \n
++ */
++void otg_hcd_deinit_modules(void)
++{
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "otg_hcd_deinit_modules \n");
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ deinit_transfer();
++
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++}
++
++/**
++ * irqreturn_t (*s3c6410_otghcd_irq) (struct usb_hcd *hcd)
++ *
++ * @brief interrupt handler of otg irq
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ *
++ * @return IRQ_HANDLED \n
++ */
++irqreturn_t s3c6410_otghcd_irq(struct usb_hcd *hcd)
++{
++
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(false, "s3c6410_otghcd_irq \n");
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ otg_handle_interrupt();
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++
++ return IRQ_HANDLED;
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * int s3c6410_otghcd_start(struct usb_hcd *hcd)
++ *
++ * @brief initialize and start otg hcd
++ *
++ * @param [in] usb_hcd_p : pointer of usb_hcd
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++int s3c6410_otghcd_start(struct usb_hcd *usb_hcd_p)
++{
++ struct usb_bus *usb_bus_p;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_start \n");
++
++ usb_bus_p = hcd_to_bus(usb_hcd_p);
++
++ //* Initialize and connect root hub if one is not already attached */
++ if (usb_bus_p->root_hub) {
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "OTG HCD Has Root Hub\n");
++
++ //* Inform the HUB driver to resume. */
++ otg_usbcore_resume_roothub();
++ } else {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "OTG HCD Does Not Have Root Hub\n");
++ return USB_ERR_FAIL;
++ }
++
++ usb_hcd_p->poll_rh = 1;
++ usb_hcd_p->uses_new_polling = 1;
++
++ ///init bus state before enable irq
++ usb_hcd_p->state = HC_STATE_RUNNING;
++
++ oci_start();//enable irq
++
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void s3c6410_otghcd_stop(struct usb_hcd *hcd)
++ *
++ * @brief deinitialize and stop otg hcd
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ *
++ */
++void s3c6410_otghcd_stop(struct usb_hcd *hcd)
++{
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_stop \n");
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ otg_hcd_deinit_modules();
++ oci_stop();
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void s3c6410_otghcd_shutdown(struct usb_hcd *hcd)
++ *
++ * @brief shutdown otg hcd
++ *
++ * @param [in] usb_hcd_p : pointer of usb_hcd
++ *
++ */
++void s3c6410_otghcd_shutdown(struct usb_hcd *usb_hcd_p)
++{
++
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_shutdown \n");
++ otg_hcd_deinit_modules();
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ oci_stop();
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ free_irq(IRQ_OTG, usb_hcd_p);
++ usb_hcd_p->state = HC_STATE_HALT;
++ otg_usbcore_hc_died();
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * int s3c6410_otghcd_get_frame_number(struct usb_hcd *hcd)
++ *
++ * @brief get currnet frame number
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ *
++ * @return ret : frame number \n
++ */
++int s3c6410_otghcd_get_frame_number(struct usb_hcd *hcd)
++{
++ int ret = 0;
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_get_frame_number \n");
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ ret = oci_get_frame_num();
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return ret;
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * int s3c6410_otghcd_urb_enqueue()
++ *
++ * @brief enqueue a urb to otg hcd
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ * [in] ep : pointer of usb_host_endpoint
++ * [in] urb : pointer of urb
++ * [in] mem_flags : type of gfp_t
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++int
++s3c6410_otghcd_urb_enqueue
++(
++ struct usb_hcd *hcd,
++ struct urb *urb,
++ gfp_t mem_flags
++)
++{
++
++ int ret_val = 0;
++ u32 trans_flag = 0;
++ u32 return_td_addr = 0;
++ u8 dev_speed, ed_type = 0, additional_multi_count;
++ u16 max_packet_size;
++
++ u8 dev_addr = 0;
++ u8 ep_num = 0;
++ bool f_is_ep_in = true;
++ u8 interval = 0;
++ u32 sched_frame = 0;
++ u8 hub_addr = 0;
++ u8 hub_port = 0;
++ bool f_is_do_split = false;
++
++ u32 spin_lock_flag = 0;
++
++ ed_t * target_ed = NULL;
++ isoch_packet_desc_t * new_isoch_packet_desc = NULL;
++
++ otg_dbg(false, "s3c6410_otghcd_urb_enqueue \n");
++
++ /// check ep has ed_t or not
++ if(!(urb->ep->hcpriv))
++ {
++ ///for getting dev_speed
++ switch (urb->dev->speed)
++ {
++ case USB_SPEED_HIGH :
++ dev_speed = HIGH_SPEED_OTG; break;
++
++ case USB_SPEED_FULL :
++ dev_speed = FULL_SPEED_OTG; break;
++
++ case USB_SPEED_LOW :
++ dev_speed = LOW_SPEED_OTG; break;
++
++ default:
++ otg_err(OTG_DBG_OTGHCDI_HCD, "unKnown Device Speed \n");
++ return USB_ERR_FAIL;
++ }
++
++ ///for getting ed_type
++ switch (usb_pipetype(urb->pipe))
++ {
++ case PIPE_BULK :
++ ed_type = BULK_TRANSFER; break;
++
++ case PIPE_INTERRUPT :
++ ed_type = INT_TRANSFER; break;
++
++ case PIPE_CONTROL :
++ ed_type = CONTROL_TRANSFER; break;
++
++ case PIPE_ISOCHRONOUS :
++ ed_type = ISOCH_TRANSFER; break;
++ default:
++ otg_err(OTG_DBG_OTGHCDI_HCD, "unKnown ep type \n");
++ return USB_ERR_FAIL;
++ }
++
++ max_packet_size = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
++
++ additional_multi_count = ((max_packet_size) >> 11) & 0x03;
++
++ if ( ((dev_speed == FULL_SPEED_OTG) || (dev_speed == LOW_SPEED_OTG)) &&
++ (urb->dev->tt) && (urb->dev->tt->hub->devnum != 1) )
++ {
++ f_is_do_split = true;
++ }
++
++ dev_addr = usb_pipedevice(urb->pipe);
++ ep_num = usb_pipeendpoint(urb->pipe);
++ f_is_ep_in = usb_pipein(urb->pipe) ? true : false;
++ interval = (u8)(urb->interval);
++ sched_frame = (u8)(urb->start_frame);
++
++ //check
++ if(urb->dev->tt == NULL)
++ {
++ hub_port = 0; //u8 hub_port
++ hub_addr = 0; //u8 hub_addr,
++ }
++ else
++ {
++ hub_port = (u8)(urb->dev->ttport); //u8 hub_port,
++ hub_addr = (u8)(urb->dev->tt->hub->devnum);//u8 hub_addr,
++ }
++
++ ret_val = create_ed(&target_ed);
++ if(ret_val != USB_ERR_SUCCESS)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to create_ed() \n");
++ return ret_val;
++ }
++
++ ret_val = init_ed( target_ed,
++ dev_addr,
++ ep_num,
++ f_is_ep_in,
++ dev_speed,
++ ed_type,
++ max_packet_size,
++ additional_multi_count,
++ interval,
++ sched_frame,
++ hub_addr,
++ hub_port,
++ f_is_do_split,
++ (void *)urb->ep);
++
++ if(ret_val != USB_ERR_SUCCESS)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to init_ed() :err = %d \n",(int)ret_val);
++ otg_mem_free(target_ed);
++ return USB_ERR_FAIL;
++ }
++
++ urb->ep->hcpriv = (void *)(target_ed);
++ } // if(!(ep->hcpriv))
++ else
++ {
++ dev_addr = usb_pipedevice(urb->pipe);
++ if(((ed_t *)(urb->ep->hcpriv))->ed_desc.device_addr != dev_addr)
++ {
++ ((ed_t *)urb->ep->hcpriv)->ed_desc.device_addr = dev_addr;
++ }
++ }
++
++ target_ed = (ed_t *)urb->ep->hcpriv;
++
++ if(urb->transfer_flags & URB_SHORT_NOT_OK)
++ trans_flag += USB_TRANS_FLAG_NOT_SHORT;
++ if (urb->transfer_flags & URB_ISO_ASAP)
++ trans_flag += USB_TRANS_FLAG_ISO_ASYNCH;
++
++ if(ed_type == ISOCH_TRANSFER)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "ISO not yet supported \n");
++ return USB_ERR_FAIL;
++ }
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ if (!HC_IS_RUNNING(hcd->state)) {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "!HC_IS_RUNNING(hcd->state) \n");
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return -USB_ERR_NODEV;
++ }
++
++ /* in case of unlink-during-submit */
++ if (urb->status != -EINPROGRESS) {
++ urb->hcpriv = NULL;
++ usb_hcd_giveback_urb(hcd, urb, urb->status);
++ goto fail;
++ }
++
++ ret_val = issue_transfer( target_ed, (void *)NULL, (void *)NULL,
++ trans_flag,
++ (usb_pipetype(urb->pipe) == PIPE_CONTROL)?true:false,
++ (u32)urb->setup_packet, (u32)urb->setup_dma,
++ (u32)urb->transfer_buffer, (u32)urb->transfer_dma,
++ (u32)urb->transfer_buffer_length,
++ (u32)urb->start_frame,(u32)urb->number_of_packets,
++ new_isoch_packet_desc, (void *)urb, &return_td_addr);
++
++ if(ret_val != USB_ERR_SUCCESS)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to issue_transfer() \n");
++ return USB_ERR_FAIL;
++ }
++ urb->hcpriv = (void *)return_td_addr;
++
++fail:
++
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int s3c6410_otghcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb )
++ *
++ * @brief dequeue a urb to otg
++ *
++ * @param [in] _hcd : pointer of usb_hcd
++ * [in] _urb : pointer of urb
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++int s3c6410_otghcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int status)
++{
++ int ret_val = 0;
++
++ u32 spin_lock_flag = 0;
++ td_t * cancel_td = (td_t *)_urb->hcpriv;
++
++ if (cancel_td == NULL)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "cancel_td == NULL \n");
++ return USB_ERR_FAIL;
++ }
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_urb_dequeue \n");
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ if (!HC_IS_RUNNING(_hcd->state)) {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "!HC_IS_RUNNING(hcd->state) \n");
++ otg_usbcore_giveback(cancel_td);
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return 0;
++ }
++
++ ret_val = cancel_transfer(cancel_td->parent_ed_p, cancel_td);
++ if(ret_val != USB_ERR_DEQUEUED && ret_val != USB_ERR_NOELEMENT)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to cancel_transfer() \n");
++ otg_usbcore_giveback(cancel_td);
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return USB_ERR_FAIL;
++ }
++
++ otg_usbcore_giveback(cancel_td);
++
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * void s3c6410_otghcd_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
++ *
++ * @brief disable a endpoint
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ * [in] ep : pointer of usb_host_endpoint
++ */
++void s3c6410_otghcd_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
++{
++ int ret_val = 0;
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_endpoint_disable \n");
++
++ if(!((ed_t *)ep->hcpriv))
++ return;
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ ret_val = delete_ed((ed_t *)ep->hcpriv);
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ if(ret_val != USB_ERR_SUCCESS)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to delete_ed() \n");
++ return ;
++ }
++ //ep->hcpriv = NULL; delete_ed coveres it
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * int s3c6410_otghcd_hub_status_data(struct usb_hcd *_hcd, char *_buf)
++ *
++ * @brief get status of root hub
++ *
++ * @param [in] _hcd : pointer of usb_hcd
++ * [inout] _buf : pointer of buffer for write a status data
++ *
++ * @return ret_val : return port status \n
++ */
++int s3c6410_otghcd_hub_status_data(struct usb_hcd *_hcd, char *_buf)
++{
++ int ret_val = 0;
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(false, "s3c6410_otghcd_hub_status_data \n");
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ ret_val = get_otg_port_status(OTG_PORT_NUMBER, _buf);
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ return (int)ret_val;
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * int s3c6410_otghcd_hub_control()
++ *
++ * @brief control root hub
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ * [in] typeReq : type of control request
++ * [in] value : value
++ * [in] index : index
++ * [in] buf_p : pointer of urb
++ * [in] length : type of gfp_t
++ *
++ * @return ret_val : return root_hub_feature \n
++ */
++int
++s3c6410_otghcd_hub_control
++(
++ struct usb_hcd *hcd,
++ u16 typeReq,
++ u16 value,
++ u16 index,
++ char* buf_p,
++ u16 length
++)
++{
++ int ret_val = 0;
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(false, "s3c6410_otghcd_hub_control \n");
++
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ ret_val = root_hub_feature(OTG_PORT_NUMBER, typeReq, value, (void *)buf_p);
++
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ if(ret_val != USB_ERR_SUCCESS)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to root_hub_feature() \n");
++ return ret_val;
++ }
++ return (int)ret_val;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd)
++ *
++ * @brief suspend otg hcd
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ *
++ * @return USB_ERR_SUCCESS \n
++ */
++int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd)
++{
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_bus_suspend \n");
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ bus_suspend();
++
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int s3c6410_otghcd_bus_resume(struct usb_hcd *hcd)
++ *
++ * @brief resume otg hcd
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ *
++ * @return USB_ERR_SUCCESS \n
++ */
++int s3c6410_otghcd_bus_resume(struct usb_hcd *hcd)
++{
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_bus_resume \n");
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ if(bus_resume() != USB_ERR_SUCCESS)
++ {
++ return USB_ERR_FAIL;
++ }
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int s3c6410_otghcd_start_port_reset(struct usb_hcd *hcd, unsigned port)
++ *
++ * @brief reset otg port
++ *
++ * @param [in] hcd : pointer of usb_hcd
++ * [in] port : number of port
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * ret_val : If call fail \n
++ */
++int s3c6410_otghcd_start_port_reset(struct usb_hcd *hcd, unsigned port)
++{
++ int ret_val = 0;
++
++ u32 spin_lock_flag = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_start_port_reset \n");
++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++
++ ret_val = reset_and_enable_port(OTG_PORT_NUMBER);
++
++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
++ if(ret_val != USB_ERR_SUCCESS)
++ {
++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to reset_and_enable_port() \n");
++ return ret_val;
++ }
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h
+new file mode 100644
+index 0000000..031ebf6
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h
+@@ -0,0 +1,144 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-hcd.h
++ * @brief header of s3c-otg-hcdi-hcd \n
++ * @version
++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Modifying for successful rmmod & disconnecting \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _S3C_OTG_HCDI_HCD_H_
++#define _S3C_OTG_HCDI_HCD_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++//for IRQ_NONE (0) IRQ_HANDLED (1) IRQ_RETVAL(x) ((x) != 0)
++#include <linux/interrupt.h>
++
++#include <linux/usb.h>
++//#include <../drivers/usb/core/hcd.h>
++
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-hcdi-kal.h"
++
++#include "s3c-otg-common-common.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-common-const.h"
++
++#include "s3c-otg-transfer-transfer.h"
++#include "s3c-otg-oci.h"
++#include "s3c-otg-roothub.h"
++
++//placed in ISR
++extern void otg_handle_interrupt(void);
++
++int otg_hcd_init_modules(void);
++void otg_hcd_deinit_modules(void);
++
++
++irqreturn_t s3c6410_otghcd_irq(struct usb_hcd *hcd);
++
++int s3c6410_otghcd_start(struct usb_hcd *hcd);
++void s3c6410_otghcd_stop(struct usb_hcd *hcd);
++void s3c6410_otghcd_shutdown(struct usb_hcd *hcd);
++
++int s3c6410_otghcd_get_frame_number(struct usb_hcd *hcd);
++
++int s3c6410_otghcd_urb_enqueue(
++ struct usb_hcd *hcd,
++ struct urb *urb,
++ gfp_t mem_flags);
++
++int s3c6410_otghcd_urb_dequeue(
++ struct usb_hcd *_hcd,
++ struct urb *_urb,
++ int status);
++
++void s3c6410_otghcd_endpoint_disable(
++ struct usb_hcd *hcd,
++ struct usb_host_endpoint *ep);
++
++int s3c6410_otghcd_hub_status_data(
++ struct usb_hcd *_hcd,
++ char *_buf);
++
++int s3c6410_otghcd_hub_control(
++ struct usb_hcd *hcd,
++ u16 type_req,
++ u16 value,
++ u16 index,
++ char * buf,
++ u16 length);
++
++int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd);
++int s3c6410_otghcd_bus_resume(struct usb_hcd *hcd);
++int s3c6410_otghcd_start_port_reset(struct usb_hcd *hcd, unsigned port);
++
++/**
++ * @struct hc_driver s3c6410_otg_hc_driver
++ *
++ * @brief implementation of hc_driver for OTG HCD
++ *
++ * describe in detail
++ */
++static const struct hc_driver s3c6410_otg_hc_driver = {
++ .description = "EMSP_OTGHCD",
++ .product_desc = "S3C6410 OTGHCD",
++
++ .irq = s3c6410_otghcd_irq,
++ .flags = HCD_MEMORY | HCD_USB2,
++
++ /** basic lifecycle operations */
++ //.reset =
++ .start = s3c6410_otghcd_start,
++ //.suspend = ,
++ //.resume = ,
++ .stop = s3c6410_otghcd_stop,
++ .shutdown = s3c6410_otghcd_shutdown,
++
++ /** managing i/o requests and associated device resources */
++ .urb_enqueue = s3c6410_otghcd_urb_enqueue,
++ .urb_dequeue = s3c6410_otghcd_urb_dequeue,
++ .endpoint_disable = s3c6410_otghcd_endpoint_disable,
++
++ /** scheduling support */
++ .get_frame_number = s3c6410_otghcd_get_frame_number,
++
++ /** root hub support */
++ .hub_status_data = s3c6410_otghcd_hub_status_data,
++ .hub_control = s3c6410_otghcd_hub_control,
++ //.hub_irq_enable =
++ .bus_suspend = s3c6410_otghcd_bus_suspend,
++ .bus_resume = s3c6410_otghcd_bus_resume,
++ .start_port_reset = s3c6410_otghcd_start_port_reset,
++};
++
++#ifdef __cplusplus
++}
++#endif
++#endif /* _S3C_OTG_HCDI_HCD_H_ */
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h
+new file mode 100644
+index 0000000..5d1203d
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h
+@@ -0,0 +1,420 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-kal.h
++ * @brief header of s3c-otg-hcdi-kal \n
++ * @version
++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Modifying for successful rmmod & disconnecting \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _S3C_OTG_HCDI_KAL_H_
++#define _S3C_OTG_HCDI_KAL_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-common-common.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-common-const.h"
++
++#include <asm/io.h> //for readl, writel
++#include <linux/usb/ch9.h> //for usb_device_driver, enum usb_device_speed
++#include <linux/usb.h>
++#include <../drivers/usb/core/hcd.h>
++
++extern volatile u8 * g_pUDCBase;
++extern struct usb_hcd* g_pUsbHcd;
++
++
++#if defined(__linux__)
++
++#include <linux/spinlock.h>
++#define SPINLOCK_t spinlock_t
++#define SPIN_LOCK_INIT SPIN_LOCK_UNLOCKED
++
++#else
++
++#error Not supported OS
++
++#endif
++
++#define spin_lock_otg(lock) spin_lock(lock)
++#define spin_lock_irg_otg(lock) spin_lock_irq(lock)
++#define spin_lock_irg_save_otg(lock, flags) spin_lock_irqsave(lock, flags)
++
++#define spin_unlock_otg(lock) spin_unlock(lock)
++#define spin_unlock_irq_otg(lock) spin_unlock_irq(lock)
++#define spin_unlock_irq_save_otg(lock, flags) spin_unlock_irqrestore(lock, flags)
++
++#define ctrlr_base_reg_addr(offset) \
++ ((volatile unsigned int *)((g_pUDCBase) + (offset)))
++/**
++ * otg_kal_make_ep_null
++ *
++ * @brief make ep->hcpriv NULL
++ *
++ * @param [in] pdelete_ed : pointer of ed
++ *
++ * @return void \n
++ */
++static inline void
++otg_kal_make_ep_null
++(
++ ed_t *pdelete_ed
++)
++{
++ ((struct usb_host_endpoint *)(pdelete_ed->ed_private))->hcpriv = NULL;
++}
++//---------------------------------------------------------------------------------------
++
++/**
++ * otg_kal_is_ep_null
++ *
++ * @brief check ep->hcpriv is NULL or not
++ *
++ * @param [in] pdelete_ed : pointer of ed
++ *
++ * @return bool \n
++ */
++static inline bool
++otg_kal_is_ep_null
++(
++ ed_t *pdelete_ed
++)
++{
++ if (((struct usb_host_endpoint *)(pdelete_ed->ed_private))->hcpriv == NULL)
++ return true;
++ else
++ return false;
++}
++//---------------------------------------------------------------------------------------
++
++
++/**
++ * int otg_usbcore_get_calc_bustime()
++ *
++ * @brief get bus time of usbcore
++ *
++ * @param [in] speed : usb speed
++ * [in] is_input : input or not
++ * [in] is_isoch : isochronous or not
++ * [in] byte_count : bytes
++ *
++ * @return bus time of usbcore \n
++ */
++static inline int
++otg_usbcore_get_calc_bustime
++(
++ u8 speed,
++ bool is_input,
++ bool is_isoch,
++ unsigned int byte_count
++)
++{
++ unsigned int convert_speed = 0;
++
++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_get_calc_bustime \n");
++/* enum usb_device_speed {
++ USB_SPEED_UNKNOWN = 0,
++ USB_SPEED_LOW, USB_SPEED_FULL,
++ USB_SPEED_HIGH,
++ USB_SPEED_VARIABLE, };*/
++ switch(speed)
++ {
++ case HIGH_SPEED_OTG : convert_speed = USB_SPEED_HIGH; break;
++ case FULL_SPEED_OTG : convert_speed = USB_SPEED_FULL; break;
++ case LOW_SPEED_OTG : convert_speed = USB_SPEED_LOW; break;
++ default: convert_speed = USB_SPEED_UNKNOWN; break;
++ }
++ return usb_calc_bus_time(convert_speed, is_input, (unsigned int)is_isoch, byte_count);
++}
++
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_usbcore_giveback(td_t td_p)
++ *
++ * @brief give-back a td as urb
++ *
++ * @param [in] td_p : pointer of td_t to give back
++ *
++ * @return void \n
++ */
++static inline void
++otg_usbcore_giveback(td_t * td_p)
++{
++ struct urb *urb_p = NULL;
++
++// otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_giveback \n");
++ if (td_p->td_private == NULL)
++ {
++ otg_err(OTG_DBG_OTGHCDI_KAL, "td_p->td_private == NULL \n");
++ return;
++ }
++
++ urb_p = (struct urb *)td_p->td_private;
++
++ urb_p->actual_length = (int)(td_p->transferred_szie);
++ urb_p->status = (int)(td_p->error_code);
++ urb_p->error_count = (int)(td_p->err_cnt);
++ urb_p->hcpriv = NULL;
++
++#ifdef OTG_DEBUG
++ if(urb_p->transfer_buffer_length != td_p->transferred_szie)
++ {
++ if(!td_p->parent_ed_p->ed_desc.is_ep_in)
++ {
++ otg_dbg(false, "###OUT ==> %d: %d : %d\n",(int)urb_p->transfer_buffer_length,(int)td_p->transferred_szie, (int)td_p->buf_size);
++ }
++ else
++ {
++ otg_dbg(false, "###IN ==> %d: %d : %d\n",(int)urb_p->transfer_buffer_length,(int)td_p->transferred_szie, (int)td_p->buf_size);
++ }
++ }
++#endif
++ usb_hcd_giveback_urb(g_pUsbHcd, urb_p, urb_p->status);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_usbcore_hc_died(void)
++ *
++ * @brief inform usbcore of hc die
++ *
++ * @return void \n
++ */
++static inline void
++otg_usbcore_hc_died(void)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_hc_died \n");
++ usb_hc_died(g_pUsbHcd);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_usbcore_poll_rh_status(void)
++ *
++ * @brief invoke usbcore's usb_hcd_poll_rh_status
++ *
++ * @param void
++ *
++ * @return void \n
++ */
++static inline void
++otg_usbcore_poll_rh_status(void)
++{
++ usb_hcd_poll_rh_status(g_pUsbHcd);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_usbcore_resume_roothub(void)
++ *
++ * @brief invoke usbcore's usb_hcd_resume_root_hub
++ *
++ * @param void
++ *
++ * @return void \n
++ */
++static inline void
++otg_usbcore_resume_roothub(void)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_resume_roothub \n");
++ usb_hcd_resume_root_hub(g_pUsbHcd);
++};
++//-------------------------------------------------------------------------------
++
++/**
++ * int otg_usbcore_inc_usb_bandwidth(u32 band_width)
++ *
++ * @brief increase bandwidth of usb bus
++ *
++ * @param [in] band_width : bandwidth to be increased
++ *
++ * @return USB_ERR_SUCCESS \n
++ */
++static inline int
++otg_usbcore_inc_usb_bandwidth(u32 band_width)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_inc_usb_bandwidth \n");
++ hcd_to_bus(g_pUsbHcd)->bandwidth_allocated += band_width;
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int otg_usbcore_des_usb_bandwidth(u32 uiBandwidth)
++ *
++ * @brief decrease bandwidth of usb bus
++ *
++ * @param [in] band_width : bandwidth to be decreased
++ *
++ * @return USB_ERR_SUCCESS \n
++ */
++static inline int
++otg_usbcore_des_usb_bandwidth(u32 band_width)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_des_usb_bandwidth \n");
++ hcd_to_bus(g_pUsbHcd)->bandwidth_allocated -= band_width;
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int otg_usbcore_inc_periodic_transfer_cnt(u8 transfer_type)
++ *
++ * @brief increase count of periodic transfer
++ *
++ * @param [in] transfer_type : type of transfer
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++static inline int
++otg_usbcore_inc_periodic_transfer_cnt(u8 transfer_type)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_inc_periodic_transfer_cnt \n");
++
++ switch(transfer_type)
++ {
++ case INT_TRANSFER :
++ hcd_to_bus(g_pUsbHcd)->bandwidth_int_reqs++;
++ break;
++ case ISOCH_TRANSFER :
++ hcd_to_bus(g_pUsbHcd)->bandwidth_isoc_reqs++;
++ break;
++ default:
++ otg_err(OTG_DBG_OTGHCDI_KAL, "not proper TransferType for otg_usbcore_inc_periodic_transfer_cnt()\n");
++ return USB_ERR_FAIL;
++ }
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int otg_usbcore_des_periodic_transfer_cnt(u8 transfer_type)
++ *
++ * @brief decrease count of periodic transfer
++ *
++ * @param [in] transfer_type : type of transfer
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++static inline int
++otg_usbcore_des_periodic_transfer_cnt(u8 transfer_type)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_des_periodic_transfer_cnt \n");
++
++ switch(transfer_type)
++ {
++ case INT_TRANSFER :
++ hcd_to_bus(g_pUsbHcd)->bandwidth_int_reqs--;
++ break;
++ case ISOCH_TRANSFER :
++ hcd_to_bus(g_pUsbHcd)->bandwidth_isoc_reqs--;
++ break;
++ default:
++ otg_err(OTG_DBG_OTGHCDI_KAL, "not proper TransferType for otg_usbcore_des_periodic_transfer_cnt()\n");
++ return USB_ERR_FAIL;
++ }
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * u32 read_reg_32(u32 offset)
++ *
++ * @brief Reads the content of a register.
++ *
++ * @param [in] offset : offset of address of register to read.
++ *
++ * @return contents of the register. \n
++ * @remark call readl()
++ */
++static inline u32 read_reg_32(u32 offset)
++{
++ volatile unsigned int * reg_addr_p = ctrlr_base_reg_addr(offset);
++ return *reg_addr_p;
++ //return readl(reg_addr_p);
++};
++//-------------------------------------------------------------------------------
++
++/**
++ * void write_reg_32( u32 offset, const u32 value)
++ *
++ * @brief Writes a register with a 32 bit value.
++ *
++ * @param [in] offset : offset of address of register to write.
++ * @param [in] value : value to write
++ *
++ * @remark call writel()
++ */
++static inline void write_reg_32( u32 offset, const u32 value)
++{
++ volatile unsigned int * reg_addr_p = ctrlr_base_reg_addr(offset);
++ *reg_addr_p = value;
++ //writel( value, reg_addr_p );
++};
++//-------------------------------------------------------------------------------
++
++/**
++ * void update_reg_32(u32 offset, u32 value)
++ *
++ * @brief logic or operation
++ *
++ * @param [in] offset : offset of address of register to write.
++ * @param [in] value : value to or
++ *
++ */
++static inline void update_reg_32(u32 offset, u32 value)
++{
++ write_reg_32(offset, (read_reg_32(offset) | value));
++}
++//---------------------------------------------------------------------------------------
++
++/**
++ * void clear_reg_32(u32 offset, u32 value)
++ *
++ * @brief logic not operation
++ *
++ * @param [in] offset : offset of address of register to write.
++ * @param [in] value : value to not
++ *
++ */
++static inline void clear_reg_32(u32 offset, u32 value)
++{
++ write_reg_32(offset, (read_reg_32(offset) & ~value));
++}
++//---------------------------------------------------------------------------------------
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _S3C_OTG_HCDI_KAL_H_ */
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h
+new file mode 100644
+index 0000000..d3731cd
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h
+@@ -0,0 +1,225 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-list.h
++ * @brief list functions for otg \n
++ * @version
++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _S3C_OTG_HCDI_LIST_H_
++#define _S3C_OTG_HCDI_LIST_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++#include "s3c-otg-common-common.h"
++#include "s3c-otg-hcdi-debug.h"
++
++#if defined(__linux__)
++
++#include <linux/list.h>
++
++typedef struct list_head otg_list_head;
++
++#else
++
++#error Not supported OS
++
++#endif
++
++#define otg_list_get_node(ptr, type, member) container_of(ptr, type, member)
++
++
++#define otg_list_for_each_safe(pos, n, head) \
++ for (pos = (head)->next, n = pos->next; pos != (head); \
++ pos = n, n = pos->next)
++
++
++/**
++ * void otg_list_push_next(otg_list_head *new_node_p, otg_list_head *list_head_p)
++ *
++ * @brief push a list node into the next of head
++ *
++ * @param [in] new_node_p : node to be pushed
++ * @param [in] otg_list_head : target list head
++ *
++ * @return void \n
++ */
++
++static inline
++void otg_list_push_next(otg_list_head *new_node_p, otg_list_head *list_head_p)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_push_next \n");
++ list_add(new_node_p, list_head_p);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_list_push_prev(otg_list_head *new_node_p, otg_list_head *list_head_p)
++ *
++ * @brief push a list node into the previous of head
++ *
++ * @param [in] new_node_p : node to be pushed
++ * @param [in] otg_list_head : target list head
++ *
++ * @return void \n
++ */
++static inline
++void otg_list_push_prev(otg_list_head *new_node_p, otg_list_head *list_head_p)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_push_prev \n");
++ list_add_tail(new_node_p, list_head_p);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_list_pop(otg_list_head *list_entity_p)
++ *
++ * @brief pop a list node
++ *
++ * @param [in] new_node_p : node to be poped
++ * @param [in] otg_list_head : target list head
++ *
++ * @return void \n
++ */
++static inline
++void otg_list_pop(otg_list_head *list_entity_p)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_pop \n");
++ list_del(list_entity_p);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_list_move_next(otg_list_head *node_p, otg_list_head *list_head_p)
++ *
++ * @brief move a list to next of head
++ *
++ * @param [in] new_node_p : node to be moved
++ * @param [in] otg_list_head : target list head
++ *
++ * @return void \n
++ */
++static inline
++void otg_list_move_next(otg_list_head *node_p, otg_list_head *list_head_p)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_move_next \n");
++ list_move(node_p, list_head_p);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_list_move_prev(otg_list_head *node_p, otg_list_head *list_head_p)
++ *
++ * @brief move a list to previous of head
++ *
++ * @param [in] new_node_p : node to be moved
++ * @param [in] otg_list_head : target list head
++ *
++ * @return void \n
++ */
++static inline
++void otg_list_move_prev(otg_list_head *node_p, otg_list_head *list_head_p)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_move_prev \n");
++ list_move_tail(node_p, list_head_p);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * bool otg_list_empty(otg_list_head *list_head_p)
++ *
++ * @brief check a list empty or not
++ *
++ * @param [in] list_head_p : node to check
++ *
++ * @return true : empty list \n
++ * false : not empty list
++ */
++static inline
++bool otg_list_empty(otg_list_head *list_head_p)
++{
++
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_empty \n");
++ if(list_empty(list_head_p))
++ return true;
++ return false;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_list_merge(otg_list_head *list_p, otg_list_head *head_p)
++ *
++ * @brief merge two list
++ *
++ * @param [in] list_p : a head
++ * @param [in] head_p : target list head
++ *
++ * @return void \n
++ */
++static inline
++void otg_list_merge(otg_list_head *list_p, otg_list_head *head_p)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_merge \n");
++ list_splice(list_p, head_p);
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * void otg_list_init(otg_list_head *list_p)
++ *
++ * @brief initialize a list
++ *
++ * @param [in] list_p : node to be initialized
++ *
++ * @return void \n
++ */
++static inline
++void otg_list_init(otg_list_head *list_p)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_init \n");
++ list_p->next = list_p;
++ list_p->prev = list_p;
++}
++//-------------------------------------------------------------------------------
++
++/*
++void otg_list_push_next(otg_list_head *new_node_p, otg_list_head *list_head_p );
++void otg_list_push_prev(otg_list_head *new_node_p, otg_list_head *list_head_p);
++void otg_list_pop(otg_list_head *list_entity_p);
++
++void otg_list_move_next(otg_list_head *node_p, otg_list_head *list_head_p);
++void otg_list_move_prev(otg_list_head *node_p, otg_list_head *list_head_p);
++
++bool otg_list_empty(otg_list_head *list_head_p);
++void otg_list_merge(otg_list_head *list_p, otg_list_head *head_p);
++void otg_list_init(otg_list_head *list_p);
++*/
++
++#ifdef __cplusplus
++}
++#endif
++#endif /* _S3C_OTG_HCDI_LIST_H_ */
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h
+new file mode 100644
+index 0000000..a0a4af8
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h
+@@ -0,0 +1,180 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * @file s3c-otg-hcdi-memory.h
++ * @brief header of s3c-otg-hcdi-memory \n
++ * @version
++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Creating the initial version of this code \n
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ * @see None
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _S3C_OTG_HCDI_MEMORY_H_
++#define _S3C_OTG_HCDI_MEMORY_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++#include "s3c-otg-common-common.h"
++#include "s3c-otg-hcdi-debug.h"
++
++/**
++ * @enum otg_mem_alloc_flag
++ *
++ * @brief enumeration for flag of memory allocation
++ */
++typedef
++enum otg_mem_alloc_flag
++{
++ USB_MEM_SYNC, USB_MEM_ASYNC, USB_MEM_DMA
++}otg_mem_alloc_flag_t;
++//---------------------------------------------------------------------------------------
++
++/*
++inline int otg_mem_alloc(void ** addr_pp, u16 byte_size, otg_mem_alloc_flag_t type);
++inline int otg_mem_copy(void * to_addr_p, void * from_addr_p, u16 byte_size);
++//inline int otg_mem_free(void * addr_p);
++inline int otg_mem_set(void * addr_p, char value, u16 byte_size);
++*/
++
++/**
++ * int otg_mem_alloc(void ** addr_pp, u16 byte_size, u8 ubType);
++ *
++ * @brief allocating momory specified
++ *
++ * @param [inout] addr_pp : address to be assigned
++ * [in] byte_size : size of memory
++ * [in] type : otg_mem_alloc_flag_t type
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++static inline int
++otg_mem_alloc
++(
++ void ** addr_pp,
++ u16 byte_size,
++ otg_mem_alloc_flag_t type
++)
++{
++ gfp_t flags;
++ otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_alloc \n");
++
++ switch(type)
++ {
++ case USB_MEM_SYNC: flags = GFP_KERNEL; break;
++ case USB_MEM_ASYNC: flags = GFP_ATOMIC; break;
++ case USB_MEM_DMA: flags = GFP_DMA; break;
++ default:
++ otg_err(OTG_DBG_OTGHCDI_MEM, "not proper otg_mem_alloc_flag_t in otg_mem_alloc \n");
++ return USB_ERR_FAIL;
++ }
++
++ *addr_pp = kmalloc((size_t)byte_size, flags);
++ if(*addr_pp == 0)
++ {
++ otg_err(OTG_DBG_OTGHCDI_MEM, "kmalloc failed\n");
++ return USB_ERR_FAIL;
++ }
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int otg_mem_copy(void * to_addr_p, void * from_addr_p, u16 byte_size);
++ *
++ * @brief memory copy
++ *
++ * @param [in] to_addr_p : target address
++ * [in] from_addr_p : source address
++ * [in] byte_size : size
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++static inline int
++otg_mem_copy
++(
++ void * to_addr_p,
++ void * from_addr_p,
++ u16 byte_size
++)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_copy \n");
++
++ memcpy(to_addr_p, from_addr_p, (size_t)byte_size);
++
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int otg_mem_free(void * addr_p);
++ *
++ * @brief de-allocating memory
++ *
++ * @param [in] addr_p : target address to be de-allocated
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++static inline int
++otg_mem_free(void * addr_p)
++{
++ //otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_free \n");
++ kfree(addr_p);
++ return USB_ERR_SUCCESS;
++}
++
++//-------------------------------------------------------------------------------
++
++/**
++ * int otg_mem_set(void * addr_p, char value, u16 byte_size)
++ *
++ * @brief writing a value to memory
++ *
++ * @param [in] addr_p : target address
++ * [in] value : value to be written
++ * [in] byte_size : size
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ */
++static inline int
++otg_mem_set
++(
++ void * addr_p,
++ char value,
++ u16 byte_size
++)
++{
++ otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_set \n");
++ memset(addr_p, value, (size_t)byte_size);
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++
++#ifdef __cplusplus
++}
++#endif
++#endif /* _S3C_OTG_HCDI_MEMORY_H_ */
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-isr.c b/drivers/usb/host/s3c-otg/s3c-otg-isr.c
+new file mode 100644
+index 0000000..b2946a5
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-isr.c
+@@ -0,0 +1,283 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : Isr.c
++ * [Description] : The file implement the external and internal functions of ISR
++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * [Department] : System LSI Division/Embedded S/W Platform
++ * [Created Date]: 2008/06/13
++ * [Revision History]
++ * (1) 2008/06/13 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * - Created this file and implements functions of ISR
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-isr.h"
++
++/**
++ * void otg_handle_interrupt(void)
++ *
++ * @brief Main interrupt processing routine
++ *
++ * @param None
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++
++extern port_flags_t port_flag;
++extern bool ch_halt;
++
++__inline__ void otg_handle_interrupt(void)
++{
++ gintsts_t clearIntr = {.d32 = 0};
++ gintsts_t gintsts = {.d32 = 0};
++
++ gintsts.d32 = read_reg_32(GINTSTS) & read_reg_32(GINTMSK);
++
++ if (gintsts.b.wkupintr)
++ {
++ //otg_dbg(OTG_DBG_ISR, "Wakeup Interrupt\n");
++ clearIntr.b.wkupintr = 1;
++ }
++
++ if (gintsts.b.disconnect)
++ {
++ //otg_dbg(OTG_DBG_ISR, "Disconnect Interrupt\n");
++ port_flag.b.port_connect_status_change = 1;
++ port_flag.b.port_connect_status = 0;
++ clearIntr.b.disconnect = 1;
++ }
++
++ if (gintsts.b.conidstschng)
++ {
++ //otg_dbg(OTG_DBG_ISR, "Connect ID Status Change Interrupt\n");
++ clearIntr.b.conidstschng = 1;
++ oci_init_mode();
++ }
++
++ if (gintsts.b.hcintr)
++ {
++ //Mask Channel Interrupt to prevent generating interrupt
++ //otg_dbg(OTG_DBG_ISR, "Channel Interrupt\n");
++ if(!ch_halt)
++ {
++ do_transfer_checker();
++ }
++
++ }
++
++ if (gintsts.b.portintr)
++ {
++ // Read Only
++ //otg_dbg(OTG_DBG_ISR, "Port Interrupt\n");
++ process_port_intr();
++ }
++
++
++ if (gintsts.b.otgintr)
++ {
++ // Read Only
++ //otg_dbg(OTG_DBG_ISR, "OTG Interrupt\n");
++ }
++
++ if (gintsts.b.sofintr)
++ {
++ otg_dbg(OTG_DBG_ISR, "SOF Interrupt\n");
++ do_schedule();
++ clearIntr.b.sofintr = 1;
++ }
++
++ if (gintsts.b.modemismatch)
++ {
++ //otg_dbg(OTG_DBG_ISR, "Mode Mismatch Interrupt\n");
++ clearIntr.b.modemismatch = 1;
++ }
++ update_reg_32(GINTSTS, clearIntr.d32);
++
++}
++
++/**
++ * void mask_channel_interrupt(u32 ch_num, u32 mask_info)
++ *
++ * @brief Mask specific channel interrupt
++ *
++ * @param [IN] chnum : channel number for masking
++ * [IN] mask_info : mask information to write register
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++void mask_channel_interrupt(u32 ch_num, u32 mask_info)
++{
++ clear_reg_32(HCINTMSK(ch_num),mask_info);
++}
++
++/**
++ * void unmask_channel_interrupt(u32 ch_num, u32 mask_info)
++ *
++ * @brief Unmask specific channel interrupt
++ *
++ * @param [IN] chnum : channel number for unmasking
++ * [IN] mask_info : mask information to write register
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++void unmask_channel_interrupt(u32 ch_num, u32 mask_info)
++{
++ update_reg_32(HCINTMSK(ch_num),mask_info);
++}
++
++/**
++ * int get_ch_info(hc_info_t * hc_reg, u8 ch_num)
++ *
++ * @brief Get current channel information about specific channel
++ *
++ * @param [OUT] hc_reg : structure to write channel inforamtion value
++ * [IN] ch_num : channel number for unmasking
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++int get_ch_info(hc_info_t *hc_reg, u8 ch_num)
++{
++ if(hc_reg !=NULL)
++ {
++ hc_reg->hc_int_msk.d32 = read_reg_32(HCINTMSK(ch_num));
++ hc_reg->hc_int.d32 = read_reg_32(HCINT(ch_num));
++ hc_reg->dma_addr = read_reg_32(HCDMA(ch_num));
++ hc_reg->hc_char.d32 = read_reg_32(HCCHAR(ch_num));
++ hc_reg->hc_size.d32 = read_reg_32(HCTSIZ(ch_num));
++
++ return USB_ERR_SUCCESS;
++ }
++ return USB_ERR_FAIL;
++}
++
++/**
++ * void get_intr_ch(u32* haint, u32* haintmsk)
++ *
++ * @brief Get Channel Interrupt Information in HAINT, HAINTMSK register
++ *
++ * @param [OUT] haint : HAINT register value
++ * [OUT] haintmsk : HAINTMSK register value
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++void get_intr_ch(u32 *haint, u32 *haintmsk)
++{
++ *haint = read_reg_32(HAINT);
++ *haintmsk = read_reg_32(HAINTMSK);
++}
++
++
++/**
++ * void clear_ch_intr(u8 ch_num, u32 clear_bit)
++ *
++ * @brief Get Channel Interrupt Information in HAINT, HAINTMSK register
++ *
++ * @param [IN] haint : HAINT register value
++ * [IN] haintmsk : HAINTMSK register value
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++void clear_ch_intr(u8 ch_num, u32 clear_bit)
++{
++ update_reg_32(HCINT(ch_num),clear_bit);
++}
++
++/**
++ * void enable_sof(void)
++ *
++ * @brief Generate SOF Interrupt.
++ *
++ * @param None
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++void enable_sof(void)
++{
++ gintmsk_t gintmsk = {.d32 = 0};
++ gintmsk.b.sofintr = 1;
++ update_reg_32(GINTMSK, gintmsk.d32);
++}
++
++/**
++ * void disable_sof(void)
++ *
++ * @brief Stop to generage SOF interrupt
++ *
++ * @param None
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++ void disable_sof(void)
++{
++ gintmsk_t gintmsk = {.d32 = 0};
++ gintmsk.b.sofintr = 1;
++ clear_reg_32(GINTMSK, gintmsk.d32);
++}
++
++/*Internal function of isr */
++void process_port_intr(void)
++{
++ hprt_t hprt;//by ss1, clear_hprt;
++ hprt.d32 = read_reg_32(HPRT);
++
++ //otg_dbg(OTG_DBG_ISR,"\nPort Interrupt() : HPRT = 0x%x\n",hprt.d32);
++
++ if(hprt.b.prtconndet)
++ {
++ port_flag.b.port_connect_status_change = 1;
++ port_flag.b.port_connect_status = 1;
++ }
++
++
++ if(hprt.b.prtenchng)
++ {
++ port_flag.b.port_enable_change = 1;
++ }
++
++ hprt.b.prtena = 0; //prtena¸¦ writeclear½ÃÅ°¸é ¾ÈµÊ.
++ //hprt.b.prtpwr = 0;
++ hprt.b.prtrst = 0;
++ hprt.b.prtconnsts = 0;
++ write_reg_32(HPRT, hprt.d32);
++
++}
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-isr.h b/drivers/usb/host/s3c-otg/s3c-otg-isr.h
+new file mode 100644
+index 0000000..2d30c44
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-isr.h
+@@ -0,0 +1,72 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] :s3c-otg-isr.h
++ * [Description] : The Header file defines the external and internal functions of ISR.
++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * [Department] : System LSI Division/Embedded S/W Platform
++ * [Created Date]: 2008/06/18
++ * [Revision History]
++ * (1) 2008/06/18 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * - Created this file and defines functions of Scheduler
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _ISR_H_
++#define _ISR_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-common-regdef.h"
++#include "s3c-otg-hcdi-kal.h"
++#include "s3c-otg-scheduler-scheduler.h"
++#include "s3c-otg-transferchecker-common.h"
++#include "s3c-otg-roothub.h"
++#include "s3c-otg-oci.h"
++
++__inline__ void otg_handle_interrupt(void);
++
++void process_port_intr(void);
++
++void mask_channel_interrupt(u32 ch_num, u32 mask_info);
++
++void unmask_channel_interrupt(u32 ch_num, u32 mask_info);
++
++extern int get_ch_info(hc_info_t *hc_reg, u8 ch_num);
++
++extern void get_intr_ch(u32 *haint, u32 *haintmsk);
++
++extern void clear_ch_intr(u8 ch_num, u32 clear_bit);
++
++extern void enable_sof(void);
++
++extern void disable_sof(void);
++
++#ifdef __cplusplus
++}
++#endif
++#endif /* _ISR_H_ */
++
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-oci.c b/drivers/usb/host/s3c-otg/s3c-otg-oci.c
+new file mode 100644
+index 0000000..5e927c0
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-oci.c
+@@ -0,0 +1,792 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : OCI.c
++ * [Description] : The file implement the external and internal functions of OCI
++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * [Department] : System LSI Division/Embedded S/W Platform
++ * [Created Date]: 2008/06/12
++ * [Revision History]
++ * (1) 2008/06/12 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * - Created this file and Implement functions of OCI
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-oci.h"
++
++static bool ch_enable[16];
++bool ch_halt;
++
++/**
++ * int oci_init(void)
++ *
++ * @brief Initialize oci module.
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++int oci_init(void)
++{
++ otg_mem_set((void*)ch_enable, true, sizeof(bool)*16);
++ ch_halt = false;
++
++ if(oci_sys_init() == USB_ERR_SUCCESS)
++ {
++ if(oci_core_reset() == USB_ERR_SUCCESS)
++ {
++ oci_set_global_interrupt(false);
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ //otg_dbg(OTG_DBG_OCI, "oci_core_reset() Fail\n");
++ return USB_ERR_FAIL;
++ }
++ }
++
++ return USB_ERR_FAIL;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int oci_core_init(void)
++ *
++ * @brief process core initialize as s3c6410 otg spec
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++int oci_core_init(void)
++{
++ gahbcfg_t ahbcfg = {.d32 = 0};
++ gusbcfg_t usbcfg = {.d32 = 0};
++ ghwcfg2_t hwcfg2 = {.d32 = 0};
++ gintmsk_t gintmsk = {.d32 = 0};
++
++ //otg_dbg(OTG_DBG_OCI, "oci_core_init \n");
++
++ /* PHY parameters */
++ usbcfg.b.physel = 0;
++ usbcfg.b.phyif = 1; // 16 bit
++ usbcfg.b.ulpi_utmi_sel = 0; // UTMI
++ //usbcfg.b.ddrsel = 1; // DDR
++ usbcfg.b.usbtrdtim = 5; // 16 bit UTMI
++ usbcfg.b.toutcal = 7;
++ write_reg_32 (GUSBCFG, usbcfg.d32);
++
++ // Reset after setting the PHY parameters
++ if(oci_core_reset() == USB_ERR_SUCCESS)
++ {
++ /* Program the GAHBCFG Register.*/
++ hwcfg2.d32 = read_reg_32 (GHWCFG2);
++
++ switch (hwcfg2.b.architecture)
++ {
++ case HWCFG2_ARCH_SLAVE_ONLY:
++ //otg_dbg(OTG_DBG_OCI, "Slave Only Mode\n");
++ ahbcfg.b.nptxfemplvl = 0;
++ ahbcfg.b.ptxfemplvl = 0;
++ break;
++
++ case HWCFG2_ARCH_EXT_DMA:
++ //otg_dbg(OTG_DBG_OCI, "External DMA Mode - TBD!\n");
++ break;
++
++ case HWCFG2_ARCH_INT_DMA:
++ //otg_dbg(OTG_DBG_OCI, "Internal DMA Setting \n");
++ ahbcfg.b.dmaenable = true;
++ ahbcfg.b.hburstlen = INT_DMA_MODE_INCR;
++ break;
++
++ default:
++ //otg_dbg(OTG_DBG_OCI, "ERR> hwcfg2\n ");
++ break;
++ }
++ write_reg_32 (GAHBCFG, ahbcfg.d32);
++
++ /* Program the GUSBCFG register.*/
++ switch (hwcfg2.b.op_mode)
++ {
++ case MODE_HNP_SRP_CAPABLE:
++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_HNP_SRP_CAPABLE \n");
++ usbcfg.b.hnpcap = 1;
++ usbcfg.b.srpcap = 1;
++ break;
++
++ case MODE_SRP_ONLY_CAPABLE:
++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_SRP_ONLY_CAPABLE \n");
++ usbcfg.b.srpcap = 1;
++ break;
++
++ case MODE_NO_HNP_SRP_CAPABLE:
++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_NO_HNP_SRP_CAPABLE \n");
++ usbcfg.b.hnpcap = 0;
++ break;
++
++ case MODE_SRP_CAPABLE_DEVICE:
++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_SRP_CAPABLE_DEVICE \n");
++ usbcfg.b.srpcap = 1;
++ break;
++
++ case MODE_NO_SRP_CAPABLE_DEVICE:
++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_NO_SRP_CAPABLE_DEVICE \n");
++ usbcfg.b.srpcap = 0;
++ break;
++
++ case MODE_SRP_CAPABLE_HOST:
++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_SRP_CAPABLE_HOST \n");
++ usbcfg.b.srpcap = 1;
++ break;
++
++ case MODE_NO_SRP_CAPABLE_HOST:
++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_NO_SRP_CAPABLE_HOST \n");
++ usbcfg.b.srpcap = 0;
++ break;
++ default :
++ //otg_dbg(OTG_DBG_OCI, "ERR> hwcfg2\n ");
++ break;
++ }
++ write_reg_32 (GUSBCFG, usbcfg.d32);
++
++ /* Program the GINTMSK register.*/
++ gintmsk.b.modemismatch = 1;
++ gintmsk.b.sofintr = 1;
++ //gintmsk.b.otgintr = 1;
++ gintmsk.b.conidstschng = 1;
++ //gintmsk.b.wkupintr = 1;
++ gintmsk.b.disconnect = 1;
++ //gintmsk.b.usbsuspend = 1;
++ //gintmsk.b.sessreqintr = 1;
++ //gintmsk.b.portintr = 1;
++ //gintmsk.b.hcintr = 1;
++ write_reg_32(GINTMSK, gintmsk.d32);
++
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ //otg_dbg(OTG_DBG_OCI, "Core Reset FAIL\n");
++ return USB_ERR_FAIL;
++ }
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int oci_host_init(void)
++ *
++ * @brief Process host initialize as s3c6410 spec
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++int oci_host_init(void)
++{
++ gintmsk_t gintmsk = {.d32 = 0};
++ hcfg_t hcfg = {.d32 = 0};
++ hprt_t hprt;
++ hprt.d32 = read_reg_32(HPRT);
++
++ //otg_dbg(OTG_DBG_OCI, "oci_host_init \n");
++
++ gintmsk.b.portintr = 1;
++ update_reg_32(GINTMSK,gintmsk.d32);
++
++ hcfg.b.fslspclksel = HCFG_30_60_MHZ;
++ update_reg_32(HCFG, hcfg.d32);
++
++ /* turn on vbus */
++ if(!hprt.b.prtpwr)
++ {
++ hprt.b.prtpwr = 1;
++ write_reg_32(HPRT, hprt.d32);
++ }
++
++ oci_config_flush_fifo(OTG_HOST_MODE);
++
++ return USB_ERR_SUCCESS;
++
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * int oci_start(void)
++ *
++ * @brief start to operate oci module by calling oci_core_init function
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++int oci_start(void)
++{
++ //otg_dbg(OTG_DBG_OCI, "oci_start \n");
++
++ if(oci_core_init() == USB_ERR_SUCCESS)
++ {
++ mdelay(50);
++
++ if(oci_init_mode() == USB_ERR_SUCCESS)
++ {
++ oci_set_global_interrupt(true);
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ //otg_dbg(OTG_DBG_OCI, "oci_init_mode() Fail\n");
++ return USB_ERR_FAIL;
++ }
++ }
++ else
++ {
++ //otg_dbg(OTG_DBG_OCI, "oci_core_init() Fail\n");
++ return USB_ERR_FAIL;
++ }
++
++
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int oci_stop(void)
++ *
++ * @brief stop to opearte otg core
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++int oci_stop(void)
++{
++ //otg_dbg(OTG_DBG_OCI, "oci_stop \n");
++
++ oci_set_global_interrupt(false);
++
++ root_hub_feature(0,
++ ClearPortFeature,
++ USB_PORT_FEAT_POWER,
++ NULL
++ );
++
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++
++/**
++ * oci_start_transfer( stransfer_t *st_t)
++ *
++ * @brief start transfer by using transfer information to receive from scheduler
++ *
++ * @param [IN] *st_t - information about transfer to write register by calling oci_channel_init function
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++
++u8 oci_start_transfer( stransfer_t *st_t)
++{
++ hcchar_t hcchar = {.d32 = 0};
++ //otg_dbg(OTG_DBG_OCI, "oci_start_transfer \n");
++
++ if(st_t->alloc_chnum ==CH_NONE)
++ {
++ if( oci_channel_alloc(&(st_t->alloc_chnum)) == USB_ERR_SUCCESS)
++ {
++ oci_channel_init(st_t->alloc_chnum, st_t);
++
++ hcchar.b.chen = 1;
++ update_reg_32(HCCHAR(st_t->alloc_chnum), hcchar.d32);
++
++ return st_t->alloc_chnum;
++ }
++ else
++ {
++ //otg_dbg(OTG_DBG_OCI, "oci_start_transfer Fail - Channel Allocation Error\n");
++ return CH_NONE;
++ }
++ }
++ else
++ {
++ oci_channel_init(st_t->alloc_chnum, st_t);
++
++ hcchar.b.chen = 1;
++ update_reg_32(HCCHAR(st_t->alloc_chnum), hcchar.d32);
++
++ return st_t->alloc_chnum;
++ }
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int oci_stop_transfer(u8 ch_num)
++ *
++ * @brief stop to transfer even if transfering
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++int oci_stop_transfer(u8 ch_num)
++{
++ hcchar_t hcchar = {.d32 = 0};
++ hcintmsk_t hcintmsk = {.d32 = 0};
++
++ //otg_dbg(OTG_DBG_OCI, "++oci_stop_transfer \n");
++
++ if(ch_num>16)
++ {
++ return USB_ERR_FAIL;
++ }
++
++ ch_halt = true;
++
++ hcintmsk.b.chhltd = 1;
++ update_reg_32(HCINTMSK(ch_num),hcintmsk.d32);
++
++ hcchar.b.chdis = 1;
++ hcchar.b.chen = 1;
++ update_reg_32(HCCHAR(ch_num),hcchar.d32);
++
++ oci_channel_dealloc(ch_num);
++
++ clear_reg_32(HAINTMSK,ch_num);
++ write_reg_32(HCINT(ch_num),INT_ALL);
++ clear_reg_32(HCINTMSK(ch_num), INT_ALL);
++
++ ch_halt =false;
++ //otg_dbg(OTG_DBG_OCI, "--oci_stop_transfer \n");
++
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * int oci_channel_init( u8 ch_num, stransfer_t *st_t)
++ *
++ * @brief Process channel initialize to prepare starting transfer
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++int oci_channel_init( u8 ch_num, stransfer_t *st_t)
++{
++ u32 intr_enable = 0;
++ gintmsk_t gintmsk = {.d32 = 0};
++ hcchar_t hcchar = {.d32 = 0};
++ hctsiz_t hctsiz = {.d32 = 0};
++
++ //otg_dbg(OTG_DBG_OCI, "oci_channel_init \n");
++
++ //Clear channel information
++ write_reg_32(HCTSIZ(ch_num), 0);
++ write_reg_32(HCCHAR(ch_num), 0);
++ write_reg_32(HCINTMSK(ch_num), 0);
++ write_reg_32(HCINT(ch_num), INT_ALL);
++ write_reg_32(HCDMA(ch_num), 0);
++
++ //enable host channel interrupt in GINTSTS
++ gintmsk.b.hcintr =1;
++ update_reg_32(GINTMSK, gintmsk.d32);
++ // Enable the top level host channel interrupt in HAINT
++ intr_enable = (1 << ch_num);
++ update_reg_32(HAINTMSK, intr_enable);
++ // unmask the down level host channel interrupt in HCINT
++ write_reg_32(HCINTMSK(ch_num),st_t->hc_reg.hc_int_msk.d32);
++
++ // Program the HCSIZn register with the endpoint characteristics for
++ hctsiz.b.xfersize = st_t->buf_size;
++ hctsiz.b.pktcnt = st_t->packet_cnt;
++
++ // Program the HCCHARn register with the endpoint characteristics for
++ hcchar.b.mps = st_t->ed_desc_p->max_packet_size;
++ hcchar.b.epnum = st_t->ed_desc_p->endpoint_num;
++ hcchar.b.epdir = st_t->ed_desc_p->is_ep_in;
++ hcchar.b.lspddev = (st_t->ed_desc_p->dev_speed == LOW_SPEED_OTG);
++ hcchar.b.eptype = st_t->ed_desc_p->endpoint_type;
++ hcchar.b.multicnt = st_t->ed_desc_p->mc;
++ hcchar.b.devaddr = st_t->ed_desc_p->device_addr;
++
++ if(st_t->ed_desc_p->endpoint_type == INT_TRANSFER ||
++ st_t->ed_desc_p->endpoint_type == ISOCH_TRANSFER)
++ {
++ u32 uiFrameNum = 0;
++ uiFrameNum = oci_get_frame_num();
++
++ hcchar.b.oddfrm = uiFrameNum%2?1:0;
++
++ //if transfer type is periodic transfer, must support sof interrupt
++ /*
++ gintmsk.b.sofintr = 1;
++ update_reg_32(GINTMSK, gintmsk.d32);
++ */
++ }
++
++
++ if(st_t->ed_desc_p->endpoint_type == CONTROL_TRANSFER)
++ {
++ td_t *td_p;
++ td_p = (td_t *)st_t->parent_td;
++
++ switch(td_p->standard_dev_req_info.conrol_transfer_stage)
++ {
++ case SETUP_STAGE:
++ hctsiz.b.pid = st_t->ed_status_p->control_data_tgl.setup_tgl;
++ hcchar.b.epdir = EP_OUT;
++ break;
++ case DATA_STAGE:
++ hctsiz.b.pid = st_t->ed_status_p->control_data_tgl.data_tgl;
++ hcchar.b.epdir = st_t->ed_desc_p->is_ep_in;
++ break;
++ case STATUS_STAGE:
++ hctsiz.b.pid = st_t->ed_status_p->control_data_tgl.status_tgl;
++
++ if(td_p->standard_dev_req_info.is_data_stage)
++ {
++ hcchar.b.epdir = ~(st_t->ed_desc_p->is_ep_in);
++ }
++ else
++ {
++ hcchar.b.epdir = EP_IN;
++ }
++ break;
++ default:break;
++ }
++ }
++ else
++ {
++ hctsiz.b.pid = st_t->ed_status_p->data_tgl;
++ }
++
++ hctsiz.b.dopng = st_t->ed_status_p->is_ping_enable;
++ write_reg_32(HCTSIZ(ch_num),hctsiz.d32);
++ st_t->ed_status_p->is_ping_enable = false;
++
++ // Write DMA Address
++ write_reg_32(HCDMA(ch_num),st_t->start_phy_buf_addr);
++
++ //Wrote HCCHAR Register
++ write_reg_32(HCCHAR(ch_num),hcchar.d32);
++
++ return USB_ERR_SUCCESS;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * u32 oci_get_frame_num(void)
++ *
++ * @brief Get current frame number by reading register.
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++u32 oci_get_frame_num(void)
++{
++ hfnum_t hfnum;
++ hfnum.d32 = read_reg_32(HFNUM);
++ return hfnum.b.frnum;
++}
++//-------------------------------------------------------------------------------
++
++/**
++ * u16 oci_get_frame_interval(void)
++ *
++ * @brief Get current frame interval by reading register.
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ * @remark
++ *
++ */
++u16 oci_get_frame_interval(void)
++{
++ hfir_t hfir;
++ hfir.d32 = read_reg_32(HFIR);
++ return hfir.b.frint;
++}
++//-------------------------------------------------------------------------------
++
++void oci_set_frame_interval(u16 interval)
++{
++ hfir_t hfir = {.d32 = 0};
++ hfir.b.frint = interval;
++ write_reg_32(HFIR, hfir.d32);
++
++}
++
++///OCI Internal Functions
++
++int oci_channel_alloc(u8 *ch_num)
++{
++ u8 ch;
++ for(ch = 0 ; ch<16 ; ch++)
++ {
++ if(ch_enable[ch] == true)
++ {
++ *ch_num = ch;
++
++ ch_enable[ch] = false;
++ return USB_ERR_SUCCESS;
++ }
++ }
++ return USB_ERR_FAIL;
++}
++
++int oci_channel_dealloc(u8 ch_num)
++{
++ if(ch_num < 16 && ch_enable[ch_num] == false)
++ {
++ ch_enable[ch_num] = true;
++
++ write_reg_32(HCTSIZ(ch_num), 0);
++ write_reg_32(HCCHAR(ch_num), 0);
++ write_reg_32(HCINTMSK(ch_num), 0);
++ write_reg_32(HCINT(ch_num), INT_ALL);
++ write_reg_32(HCDMA(ch_num), 0);
++ return USB_ERR_SUCCESS;
++ }
++ return USB_ERR_FAIL;
++}
++
++int oci_sys_init(void)
++{
++ volatile S3C6400_SYSCON_REG *syscon_reg;
++ volatile OTG_PHY_REG *otgphy_reg;
++
++ //otg_dbg(OTG_DBG_OCI, "oci_sys_init \n");
++
++ otgphy_reg = S3C24XX_VA_OTGSFR;
++ syscon_reg = S3C24XX_VA_SYSCON;
++
++ syscon_reg->HCLK_GATE |= (0x1<<20);
++ syscon_reg->OTHERS |= (0x1<<16);
++ otgphy_reg->OPHYPWR = 0x0;
++ otgphy_reg->OPHYCLK = 0x20;
++
++ otgphy_reg->ORSTCON = 0x1;
++ mdelay(80);
++
++ otgphy_reg->ORSTCON = 0x0;
++ mdelay(80);
++
++ return USB_ERR_SUCCESS;
++}
++
++void oci_set_global_interrupt(bool set)
++{
++ gahbcfg_t ahbcfg;
++
++ ahbcfg.d32 = 0;
++ ahbcfg.b.glblintrmsk = 1;
++
++ if(set)
++ {
++ update_reg_32(GAHBCFG,ahbcfg.d32);
++ }
++ else
++ {
++ clear_reg_32(GAHBCFG,ahbcfg.d32);
++ }
++}
++
++int oci_init_mode(void)
++{
++ gintsts_t gintsts;
++ gintsts.d32 = read_reg_32(GINTSTS);
++ //otg_dbg(OTG_DBG_OCI,"GINSTS = 0x%x\n",(unsigned int)gintsts.d32);
++ //otg_dbg(OTG_DBG_OCI,"GINMSK = 0x%x\n",(unsigned int)read_reg_32(GINTMSK));
++
++ if(gintsts.b.curmode == OTG_HOST_MODE)
++ {
++ //otg_dbg(OTG_DBG_OCI,"HOST Mode\n");
++ if(oci_host_init() == USB_ERR_SUCCESS)
++ {
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ //otg_dbg(OTG_DBG_OCI,"oci_host_init() Fail\n");
++ return USB_ERR_FAIL;
++ }
++ }
++
++ else // Device Mode
++ {
++ //otg_dbg(OTG_DBG_OCI,"DEVICE Mode\n");
++ if(oci_dev_init() == USB_ERR_SUCCESS)
++ {
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ //otg_dbg(OTG_DBG_OCI,"oci_dev_init() Fail\n");
++ return USB_ERR_FAIL;
++ }
++ }
++
++ return USB_ERR_SUCCESS;
++}
++
++void oci_config_flush_fifo(u32 mode)
++{
++ ghwcfg2_t hwcfg2 = {.d32 = 0};
++ //otg_dbg(OTG_DBG_OCI,"oci_config_flush_fifo\n");
++
++ hwcfg2.d32 = read_reg_32(GHWCFG2);
++
++ // Configure data FIFO sizes
++ if (hwcfg2.b.dynamic_fifo)
++ {
++ // Rx FIFO
++ write_reg_32(GRXFSIZ, 0x0000010D);
++
++ // Non-periodic Tx FIFO
++ write_reg_32(GNPTXFSIZ, 0x0080010D);
++
++ if (mode == OTG_HOST_MODE)
++ {
++ // For Periodic transactions,
++ // program HPTXFSIZ
++ }
++ }
++
++ // Flush the FIFOs
++ oci_flush_tx_fifo(0);
++
++ oci_flush_rx_fifo();
++}
++
++void oci_flush_tx_fifo(u32 num)
++{
++ grstctl_t greset = {.d32 = 0};
++ u32 count = 0;
++
++ //otg_dbg(OTG_DBG_OCI,"oci_flush_tx_fifo\n");
++
++ greset.b.txfflsh = 1;
++ greset.b.txfnum = num;
++ write_reg_32(GRSTCTL, greset.d32);
++
++ // wait for flush to end
++ while (greset.b.txfflsh == 1)
++ {
++ greset.d32 = read_reg_32(GRSTCTL);
++ if (++count > MAX_COUNT)
++ {
++ break;
++ }
++ };
++
++ /* Wait for 3 PHY Clocks*/
++ udelay(30);
++}
++
++void oci_flush_rx_fifo(void)
++{
++ grstctl_t greset = {.d32 = 0};
++ u32 count = 0;
++
++ //otg_dbg(OTG_DBG_OCI,"oci_flush_rx_fifo\n");
++
++ greset.b.rxfflsh = 1;
++ write_reg_32(GRSTCTL, greset.d32 );
++
++ do
++ {
++ greset.d32 = read_reg_32(GRSTCTL);
++
++ if (++count > MAX_COUNT)
++ {
++ break;
++ }
++
++ } while (greset.b.rxfflsh == 1);
++
++ /* Wait for 3 PHY Clocks*/
++ udelay(30);
++}
++
++int oci_core_reset(void)
++{
++ u32 count = 0;
++ grstctl_t greset = {.d32 = 0};
++
++ //otg_dbg(OTG_DBG_OCI,"oci_core_reset\n");
++
++ /* Wait for AHB master IDLE state. */
++ do
++ {
++ greset.d32 = read_reg_32 (GRSTCTL);
++ mdelay (50);
++
++ if(++count>100)
++ {
++ //otg_dbg(OTG_DBG_OCI,"AHB status is not IDLE\n");
++ return USB_ERR_FAIL;
++ }
++ } while (greset.b.ahbidle != 1);
++
++ /* Core Soft Reset */
++ greset.b.csftrst = 1;
++ write_reg_32 (GRSTCTL, greset.d32);
++
++ /* Wait for 3 PHY Clocks*/
++ mdelay (50);
++ return USB_ERR_SUCCESS;
++}
++
++int oci_dev_init(void)
++{
++ //otg_dbg(OTG_DBG_OCI,"Current Not Support Device Mode! \n");
++ //return USB_ERR_FAIL;
++ return USB_ERR_SUCCESS;
++}
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-oci.h b/drivers/usb/host/s3c-otg/s3c-otg-oci.h
+new file mode 100644
+index 0000000..b6b2c47
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-oci.h
+@@ -0,0 +1,83 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] :s3c-otg-oci.h
++ * [Description] : The Header file defines the external and internal functions of OCI.
++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * [Department] : System LSI Division/Embedded S/W Platform
++ * [Created Date]: 2008/06/18
++ * [Revision History]
++ * (1) 2008/06/25 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * - Added some functions and data structure of OCI
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _OCI_H_
++#define _OCI_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++//#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-regdef.h"
++#include "s3c-otg-hcdi-kal.h"
++#include "s3c-otg-hcdi-memory.h"
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-roothub.h"
++
++#include <asm/arch/map.h> //virtual address for smdk
++
++
++///OCI interace
++int oci_init(void);
++
++int oci_start(void);
++int oci_stop(void);
++
++u8 oci_start_transfer(stransfer_t *st_t);
++int oci_stop_transfer(u8 ch_num);
++
++int oci_channel_init(u8 ch_num, stransfer_t *st_t);
++u32 oci_get_frame_num(void);
++u16 oci_get_frame_interval(void);
++void oci_set_frame_interval(u16 intervl);
++
++///OCI Internal Functions
++int oci_sys_init(void);
++int oci_core_init(void);
++int oci_init_mode(void);
++int oci_host_init(void);
++int oci_dev_init(void);
++
++int oci_channel_alloc(u8 *ch_num);
++int oci_channel_dealloc(u8 ch_num);
++
++void oci_config_flush_fifo(u32 mode);
++void oci_flush_tx_fifo(u32 num);
++void oci_flush_rx_fifo(void);
++
++int oci_core_reset(void);
++void oci_set_global_interrupt(bool set);
++
++#ifdef __cplusplus
++}
++#endif
++#endif /* _OCI_H_ */
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-roothub.c b/drivers/usb/host/s3c-otg/s3c-otg-roothub.c
+new file mode 100644
+index 0000000..c38d115
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-roothub.c
+@@ -0,0 +1,467 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : RootHub.c
++ * [Description] : The file implement the external and internal functions of RootHub
++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * [Department] : System LSI Division/Embedded S/W Platform
++ * [Created Date]: 2008/06/13
++ * [Revision History]
++ * (1) 2008/06/13 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * - Created this file and implements functions of RootHub
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-roothub.h"
++
++port_flags_t port_flag;
++
++/**
++ * int get_otg_port_status(const u8 port, char* status)
++ *
++ * @brief Get port change bitmap information
++ *
++ * @param [IN] port : port number
++ * [OUT] status : buffer to store bitmap information
++ *
++ * @returnUSB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ *
++ * @remark
++ *
++ */
++__inline__ int get_otg_port_status(const u8 port, char *status)
++{
++ //return root_hub_feature(port, GetPortStatus, NULL, status);
++
++ status[port] = 0;
++ status[port] |= (port_flag.b.port_connect_status_change ||
++ port_flag.b.port_reset_change ||
++ port_flag.b.port_enable_change ||
++ port_flag.b.port_suspend_change ||
++ port_flag.b.port_over_current_change) << 1;
++
++ if (status[port]) {
++ otg_dbg(OTG_DBG_ROOTHUB, " Root port status changed\n");
++ otg_dbg(OTG_DBG_ROOTHUB, " port_connect_status_change: %d\n",
++ port_flag.b.port_connect_status_change);
++ otg_dbg(OTG_DBG_ROOTHUB, " port_reset_change: %d\n",
++ port_flag.b.port_reset_change);
++ otg_dbg(OTG_DBG_ROOTHUB, " port_enable_change: %d\n",
++ port_flag.b.port_enable_change);
++ otg_dbg(OTG_DBG_ROOTHUB, " port_suspend_change: %d\n",
++ port_flag.b.port_suspend_change);
++ otg_dbg(OTG_DBG_ROOTHUB, " port_over_current_change: %d\n",
++ port_flag.b.port_over_current_change);
++ }
++
++ return (status[port] !=0);
++}
++
++/**
++ * int reset_and_enable_port(const u8 port)
++ *
++ * @brief Reset port and make enable status the specific port
++ *
++ * @param [IN] port : port number
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ *
++ * @remark
++ *
++ */
++int reset_and_enable_port(const u8 port)
++{
++ hprt_t hprt;
++ u32 count = 0;
++ u32 max_error_count = 1000;
++
++ mdelay(50);
++ hprt.d32 = read_reg_32(HPRT);
++
++ if(!hprt.b.prtena)
++ {
++ hprt.b.prtrst = 1; // drive reset
++ write_reg_32(HPRT, hprt.d32);
++ mdelay(80);
++
++ hprt.b.prtrst = 0;
++ write_reg_32(HPRT, hprt.d32);
++ mdelay(60);
++
++ do
++ {
++ hprt.d32 = read_reg_32(HPRT);
++ udelay(10);
++
++ if(count > max_error_count)
++ {
++ otg_dbg(OTG_DBG_ROOTHUB,"Port Reset Fail : HPRT : 0x%x\n",(u16)read_reg_32(HPRT));
++ return USB_ERR_FAIL;
++ }
++ count++;
++ }while(!hprt.b.prtena);
++ }
++
++ return USB_ERR_SUCCESS;
++}
++
++/**
++ * int root_hub_feature(const u8 port,
++ * const u16 type_req,
++ * const u16 feature,
++ * void* buf)
++ *
++ * @brief Get port change bitmap information
++ *
++ * @param [IN] port : port number
++ * [IN] type_req : request type of hub feature as usb 2.0 spec
++ * [IN] feature : hub feature as usb 2.0 spec
++ * [OUT] status : buffer to store results
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ *
++ * @remark
++ *
++ */
++__inline__ int root_hub_feature(const u8 port,
++ const u16 type_req,
++ const u16 feature,
++ void *buf)
++{
++ int retval = USB_ERR_SUCCESS;
++ usb_hub_descriptor_t *desc = NULL;
++ u32 port_status = 0;
++ hprt_t hprt = {.d32 = 0};
++
++ switch (type_req)
++ {
++ case ClearHubFeature:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearHubFeature\n");
++ switch (feature)
++ {
++ case C_HUB_LOCAL_POWER:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearHubFeature -C_HUB_LOCAL_POWER \n");
++ break;
++ case C_HUB_OVER_CURRENT:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearHubFeature -C_HUB_OVER_CURRENT \n");
++ /* Nothing required here */
++ break;
++ default:
++ retval = USB_ERR_FAIL;
++ }
++ break;
++
++ case ClearPortFeature:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature\n");
++ switch (feature)
++ {
++ case USB_PORT_FEAT_ENABLE:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_ENABLE \n");
++ hprt.b.prtena = 1;
++ update_reg_32(HPRT, hprt.d32);
++ break;
++
++ case USB_PORT_FEAT_SUSPEND:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_SUSPEND \n");
++ bus_resume();
++ break;
++
++ case USB_PORT_FEAT_POWER:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_POWER \n");
++ hprt.b.prtpwr = 1;
++ clear_reg_32(HPRT, hprt.d32);
++ break;
++
++ case USB_PORT_FEAT_INDICATOR:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_INDICATOR \n");
++ /* Port inidicator not supported */
++ break;
++
++ case USB_PORT_FEAT_C_CONNECTION:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_CONNECTION \n");
++ /* Clears drivers internal connect status change
++ * flag */
++ port_flag.b.port_connect_status_change = 0;
++ break;
++
++ case USB_PORT_FEAT_C_RESET:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_RESET \n");
++ /* Clears the driver's internal Port Reset Change
++ * flag */
++ port_flag.b.port_reset_change = 0;
++ break;
++
++ case USB_PORT_FEAT_C_ENABLE:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_ENABLE \n");
++ /* Clears the driver's internal Port
++ * Enable/Disable Change flag */
++ port_flag.b.port_enable_change = 0;
++ break;
++
++ case USB_PORT_FEAT_C_SUSPEND:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_SUSPEND \n");
++ /* Clears the driver's internal Port Suspend
++ * Change flag, which is set when resume signaling on
++ * the host port is complete */
++ port_flag.b.port_suspend_change = 0;
++ break;
++
++ case USB_PORT_FEAT_C_OVER_CURRENT:
++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_OVER_CURRENT \n");
++ port_flag.b.port_over_current_change = 0;
++ break;
++
++ default:
++ retval = USB_ERR_FAIL;
++ }
++ break;
++
++ case GetHubDescriptor:
++ otg_dbg(OTG_DBG_ROOTHUB,"case GetHubDescriptor\n");
++ desc = (usb_hub_descriptor_t *)buf;
++ desc->desc_length = 9;
++ desc->desc_type = 0x29;
++ desc->port_number = 1;
++ desc->hub_characteristics = 0x08;
++ desc->power_on_to_power_good = 1;
++ desc->hub_control_current = 0;
++ desc->bitmap[0] = 0;
++ desc->bitmap[1] = 0xff;
++ break;
++
++ case GetHubStatus:
++ otg_dbg(OTG_DBG_ROOTHUB,"case GetHubStatus\n");
++ otg_mem_set(buf, 0, 4);
++ break;
++
++ case GetPortStatus:
++ //otg_dbg(OTG_DBG_ROOTHUB_KH,"case GetPortStatus\n");
++
++
++ if (port_flag.b.port_connect_status_change)
++ port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
++
++ if (port_flag.b.port_enable_change)
++ port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
++
++ if (port_flag.b.port_suspend_change)
++ port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
++
++ if (port_flag.b.port_reset_change)
++ port_status|= (1 << USB_PORT_FEAT_C_RESET);
++
++ if (port_flag.b.port_over_current_change)
++ port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
++
++
++ if (!port_flag.b.port_connect_status)
++ {
++ //
++ // The port is disconnected, which means the core is
++ // either in device mode or it soon will be. Just
++ // return 0's for the remainder of the port status
++ // since the port register can't be read if the core
++ // is in device mode.
++
++ *((__le32*)buf) = cpu_to_le32(port_status);
++ break;
++ }
++
++
++ hprt.d32 = read_reg_32(HPRT);
++
++ if (hprt.b.prtconnsts)
++ port_status|= (1 << USB_PORT_FEAT_CONNECTION);
++
++ if (hprt.b.prtena)
++ port_status |= (1 << USB_PORT_FEAT_ENABLE);
++
++ if (hprt.b.prtsusp)
++ port_status |= (1 << USB_PORT_FEAT_SUSPEND);
++
++ if (hprt.b.prtovrcurract)
++ port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
++
++ if (hprt.b.prtrst)
++ port_status |= (1 << USB_PORT_FEAT_RESET);
++
++ if (hprt.b.prtpwr)
++ port_status |= (1 << USB_PORT_FEAT_POWER);
++
++ if (hprt.b.prtspd == 0)
++ port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
++
++ else if (hprt.b.prtspd == 2)
++ port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
++
++ if (hprt.b.prttstctl)
++ port_status |= (1 << USB_PORT_FEAT_TEST);
++
++ *((__le32*)buf) = cpu_to_le32(port_status);
++ break;
++
++ case SetHubFeature:
++ otg_dbg(OTG_DBG_ROOTHUB,"case SetHubFeature\n");
++ /* No HUB features supported */
++ break;
++
++ case SetPortFeature:
++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature\n");
++ if (!port_flag.b.port_connect_status) {
++ /*
++ * The port is disconnected, which means the core is
++ * either in device mode or it soon will be. Just
++ * return without doing anything since the port
++ * register can't be written if the core is in device
++ * mode.
++ */
++ break;
++ }
++
++ switch (feature)
++ {
++ case USB_PORT_FEAT_SUSPEND:
++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature -USB_PORT_FEAT_SUSPEND \n");
++ bus_suspend();
++ break;
++
++ case USB_PORT_FEAT_POWER:
++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature -USB_PORT_FEAT_POWER \n");
++ hprt.d32 = read_reg_32(HPRT);
++ if(!hprt.b.prtpwr)
++ {
++ //hprt.d32 = 0;
++ hprt.b.prtpwr = 1;
++ write_reg_32(HPRT, hprt.d32);
++ }
++ break;
++
++ case USB_PORT_FEAT_RESET:
++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature -USB_PORT_FEAT_RESET \n");
++ retval = reset_and_enable_port(port);
++ break;
++
++ case USB_PORT_FEAT_INDICATOR:
++ otg_dbg(OTG_DBG_ROOTHUB,"case USB_PORT_FEAT_INDICATOR\n");
++ break;
++
++ default :
++ retval = USB_ERR_FAIL;
++ break;
++ }
++ break;
++
++ default:
++ retval = USB_ERR_FAIL;
++ otg_dbg(OTG_DBG_ROOTHUB,"root_hub_feature() Function Error\n");
++ break;
++ }
++ if(retval != USB_ERR_SUCCESS)
++ retval = USB_ERR_FAIL;
++ return retval;
++}
++
++/**
++ * void bus_suspend(void)
++ *
++ * @brief Make suspend status when this platform support PM Mode
++ *
++ * @param None
++ *
++ * @return None
++ *
++ * @remark
++ *
++ */
++void bus_suspend(void)
++{
++ hprt_t hprt;
++ pcgcctl_t pcgcctl;
++
++ hprt.d32 = 0;
++ pcgcctl.d32 = 0;
++
++ hprt.b.prtsusp = 1;
++ update_reg_32(HPRT, hprt.d32);
++
++ pcgcctl.b.pwrclmp = 1;
++ update_reg_32(PCGCCTL,pcgcctl.d32);
++ udelay(1);
++
++ pcgcctl.b.rstpdwnmodule = 1;
++ update_reg_32(PCGCCTL,pcgcctl.d32);
++ udelay(1);
++
++ pcgcctl.b.stoppclk = 1;
++ update_reg_32(PCGCCTL,pcgcctl.d32);
++ udelay(1);
++}
++
++/**
++ * int bus_resume(void)
++ *
++ * @brief Make resume status when this platform support PM Mode
++ *
++ * @param None
++ *
++ * @return USB_ERR_SUCCESS : If success \n
++ * USB_ERR_FAIL : If call fail \n
++ *
++ * @remark
++ *
++ */
++int bus_resume(void)
++{
++ /*
++ hprt_t hprt;
++ pcgcctl_t pcgcctl;
++ hprt.d32 = 0;
++ pcgcctl.d32 = 0;
++
++ pcgcctl.b.stoppclk = 1;
++ clear_reg_32(PCGCCTL,pcgcctl.d32);
++ udelay(1);
++
++ pcgcctl.b.pwrclmp = 1;
++ clear_reg_32(PCGCCTL,pcgcctl.d32);
++ udelay(1);
++
++ pcgcctl.b.rstpdwnmodule = 1;
++ clear_reg_32(PCGCCTL,pcgcctl.d32);
++ udelay(1);
++
++ hprt.b.prtres = 1;
++ update_reg_32(HPRT, hprt.d32);
++ mdelay(20);
++
++ clear_reg_32(HPRT, hprt.d32);
++ */
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "bus_resume()...... \n");
++ if(oci_init() == USB_ERR_SUCCESS)
++ {
++ if(oci_start() == USB_ERR_SUCCESS)
++ {
++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "OTG Init Success...... \n");
++ return USB_ERR_SUCCESS;
++ }
++ }
++ return USB_ERR_FAIL;
++}
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-roothub.h b/drivers/usb/host/s3c-otg/s3c-otg-roothub.h
+new file mode 100644
+index 0000000..036d4be
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-roothub.h
+@@ -0,0 +1,84 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] :s3c-otg-roothub.h
++ * [Description] : The Header file defines the external and internal functions of RootHub.
++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * [Department] : System LSI Division/Embedded S/W Platform
++ * [Created Date]: 2008/06/13
++ * [Revision History]
++ * (1) 2008/06/13 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com }
++ * - Created this file and defines functions of RootHub
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _ROOTHUB_H_
++#define _ROOTHUB_H_
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-regdef.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-hcdi-kal.h"
++#include "s3c-otg-hcdi-memory.h"
++#include "s3c-otg-oci.h"
++
++typedef union _port_flags_t
++{
++ /** raw register data */
++ u32 d32;
++ /** register bits */
++ struct
++ {
++ unsigned port_connect_status_change : 1;
++ unsigned port_connect_status : 1;
++ unsigned port_reset_change : 1;
++ unsigned port_enable_change : 1;
++ unsigned port_suspend_change : 1;
++ unsigned port_over_current_change : 1;
++ unsigned reserved : 27;
++ } b;
++}port_flags_t;
++
++
++
++__inline__ int root_hub_feature(const u8 port,
++ const u16 typeReq,
++ const u16 feature,
++ void *buf
++ );
++
++__inline__ int get_otg_port_status(const u8 port,
++ char *status);
++
++int reset_and_enable_port(const u8 port);
++
++void bus_suspend(void);
++
++int bus_resume(void);
++
++#ifdef __cplusplus
++}
++#endif
++#endif /* _ROOTHUB_H_ */
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c
+new file mode 100644
+index 0000000..3a694ff
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c
+@@ -0,0 +1,427 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : Scheduler.c
++ * [Description] : The source file implements the internal functions of Scheduler.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/04
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements functions of Scheduler
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-scheduler-scheduler.h"
++
++void init_scheduler(void)
++{
++ //init_scheduling();
++ init_transfer_ready_q();
++}
++
++#if 0 //by ss1 inlined
++/******************************************************************************/
++/*!
++ * @name int insert_ed_to_scheduler(ed_t *pInsertED)
++ *
++ * @brief this function transfers the pInsertED to S3C6400Scheduler, and
++ * after that, the pInsertED is inserted to TransferReadyQ and scheduled by Scheduler.
++ *
++ *
++ * @param [IN] pInsertED = indicates pointer of ed_t to be inserted to TransferReadyQ.
++ *
++ * @return USB_ERR_ALREADY_EXIST - if the pInsertED is already existed.
++ * USB_ERR_SUCCESS - if success to insert pInsertED to S3CScheduler.
++ */
++/******************************************************************************/
++int insert_ed_to_scheduler(ed_t *pInsertED)
++{
++ if(!pInsertED->is_need_to_insert_scheduler)
++ {
++ return USB_ERR_ALREADY_EXIST;
++ }
++
++ insert_ed_to_ready_q(pInsertED, false);
++ pInsertED->is_need_to_insert_scheduler = false;
++ pInsertED->ed_status.is_in_transfer_ready_q = true;
++
++ do_periodic_schedule();
++ do_nonperiodic_schedule();
++
++ return USB_ERR_SUCCESS;
++}
++#endif
++
++/******************************************************************************/
++/*!
++ * @name int reserve_used_resource_for_periodic(u32 usb_time)
++ *
++ * @brief this function reserves the necessary resource of USB Transfer for Periodic Transfer.
++ * So, this function firstly checks there ares some available USB Time
++ * and Channel resource for USB Transfer.
++ * if there exists necessary resources for Periodic Transfer, then reserves the resource.
++ *
++ * @param [IN] usb_time = indicates the USB Time for the USB Transfer.
++ *
++ * @return USB_ERR_SUCCESS - if success to insert pInsertED to S3CScheduler.
++ * USB_ERR_NO_BANDWIDTH - if fail to reserve the USB Bandwidth.
++ * USB_ERR_NO_CHANNEL - if fail to reserve the Channel.
++ */
++/******************************************************************************/
++
++int reserve_used_resource_for_periodic(u32 usb_time,
++ u8 dev_speed,
++ u8 trans_type)
++{
++ if(inc_perio_bus_time(usb_time,dev_speed)==USB_ERR_SUCCESS)
++ {
++ if(inc_perio_chnum()==USB_ERR_SUCCESS)
++ {
++ otg_usbcore_inc_usb_bandwidth(usb_time);
++ otg_usbcore_inc_periodic_transfer_cnt(trans_type);
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ dec_perio_bus_time(usb_time);
++ return USB_ERR_NO_CHANNEL;
++ }
++ }
++ else
++ {
++ return USB_ERR_NO_BANDWIDTH;
++ }
++
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int free_usb_resource_for_periodic(ed_t * pFreeED)
++ *
++ * @brief this function frees the resources to be allocated to pFreeED at S3CScheduler.
++ * that is, this functions only releases the resources to be allocated by S3C6400Scheduler.
++ *
++ * @param [IN] pFreeED = indicates ed_t to have the information of the resource to be released.
++ *
++ * @return USB_ERR_SUCCESS - if success to free the USB Resource.
++ * USB_ERR_FAIL - if fail to free the USB Resrouce.
++ */
++/******************************************************************************/
++int free_usb_resource_for_periodic( u32 free_usb_time,
++ u8 free_chnum,
++ u8 trans_type)
++{
++ if(dec_perio_bus_time(free_usb_time)==USB_ERR_SUCCESS)
++ {
++ if(dec_perio_chnum()==USB_ERR_SUCCESS)
++ {
++ if(free_chnum!=CH_NONE)
++ {
++ oci_channel_dealloc(free_chnum);
++ set_transferring_td_array(free_chnum, 0);
++ }
++ otg_usbcore_des_usb_bandwidth(free_usb_time);
++ otg_usbcore_des_periodic_transfer_cnt(trans_type);
++ return USB_ERR_SUCCESS;
++ }
++ }
++ return USB_ERR_FAIL;
++}
++
++/******************************************************************************/
++/*!
++ * @name int remove_ed_from_scheduler(ed_t * remove_ed)
++ *
++ * @brief this function just remove the remove_ed from TransferReadyQ. So if you want to
++ * stop the USB Tranfer of remove_ed or release the releated resources.
++ * you should call another functions of S3CScheduler.
++ *
++ * @param [IN] remove_ed = indicates ed_t to be removed from TransferReadyQ.
++ *
++ * @return USB_ERR_SUCCESS - if success to remove the remove_ed from TransferReadyQ.
++ * USB_ERR_FAIL - if fail to remove the remove_ed from TransferReadyQ.
++ */
++ /******************************************************************************/
++int remove_ed_from_scheduler(ed_t *remove_ed)
++{
++ if(remove_ed->ed_status.is_in_transfer_ready_q)
++ {
++ remove_ed_from_ready_q(remove_ed);
++ remove_ed->ed_status.is_in_transfer_ready_q = false;
++
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++}
++
++/******************************************************************************/
++/*!
++ * @name int cancel_to_transfer_td(td_t * cancel_td)
++ *
++ * @brief this function stop to execute the USB Transfer of cancel_td and
++ * release the Channel Resources to be allocated the cancel_td ,if the Transfer Type of
++ * cancel_td is NonPeriodic Transfer.
++ * this function don't release any usb resources(Channel, USB Bandwidth) for Periodic Transfer.
++ * if you want to release some usb resources for a periodic Transfer, you should call
++ * the free_usb_resource_for_periodic()
++ *
++ * @param [IN] cancel_td = indicates the td_t to be canceled.
++ *
++ * @return USB_ERR_SUCCESS - if success to cancel the USB Transfer of cancel_td.
++ * USB_ERR_FAIL - if fail to cancel the USB Transfer of cancel_td.
++ */
++ /******************************************************************************/
++int cancel_to_transfer_td(td_t *cancel_td)
++{
++ if(cancel_td->is_transfer_done)
++ {
++ return USB_ERR_FAIL;
++ }
++
++ if(cancel_td->is_transferring)
++ {
++ int err;
++
++ err = oci_stop_transfer(cancel_td->cur_stransfer.alloc_chnum);
++
++ if(err == USB_ERR_SUCCESS)
++ {
++ set_transferring_td_array(cancel_td->cur_stransfer.alloc_chnum,0);
++
++ cancel_td->cur_stransfer.alloc_chnum = CH_NONE;
++ cancel_td->is_transferring = false;
++ cancel_td->parent_ed_p->ed_status.is_in_transferring = false;
++ cancel_td->parent_ed_p->ed_status.in_transferring_td = 0;
++
++ if(cancel_td->cur_stransfer.ed_desc_p->endpoint_type == BULK_TRANSFER||
++ cancel_td->cur_stransfer.ed_desc_p->endpoint_type == CONTROL_TRANSFER )
++ {
++ dec_nonperio_chnum();
++ }
++ return err;
++ }
++ else
++ {
++ return err;
++ }
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++}
++
++
++
++
++/******************************************************************************/
++/*!
++ * @name int retransmit(td_t *retrasmit_td)
++ *
++ * @brief this function retransmits the retrasmit_td immediately.
++ * So, the Channel of pRetransmitted is reused for retransmittion.
++ *
++ * @param [IN] retrasmit_td = indicates the pointer ot the td_t to be retransmitted.
++ *
++ * @return USB_ERR_SUCCESS - if success to retransmit the retrasmit_td.
++ * USB_ERR_FAIL - if fail to retransmit the retrasmit_td.
++ */
++ /******************************************************************************/
++int retransmit(td_t *retrasmit_td)
++{
++ u32 td_addr=0;
++
++ if(get_transferring_td_array(retrasmit_td->cur_stransfer.alloc_chnum,&td_addr)==USB_ERR_SUCCESS)
++ {
++ if(td_addr == (u32)retrasmit_td)
++ {
++ if(oci_start_transfer(&retrasmit_td->cur_stransfer)== retrasmit_td->cur_stransfer.alloc_chnum)
++ {
++ retrasmit_td->is_transferring = true;
++ retrasmit_td->parent_ed_p->ed_status.in_transferring_td = (u32)retrasmit_td;
++ retrasmit_td->parent_ed_p->ed_status.is_in_transfer_ready_q = false;
++ retrasmit_td->parent_ed_p->ed_status.is_in_transferring = true;
++ }
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++
++ return USB_ERR_SUCCESS;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name int reschedule(td_t *reschedule_td)
++ *
++ * @brief this function re-schedules the reschedule_td.
++ * So, the Channel of pRescheuleTD is released and reschedule_td is inserted to TransferReadyQ.
++ *
++ * @param [IN] reschedule_td = indicates the pointer ot the td_t to be rescheduled.
++ *
++ * @return USB_ERR_SUCCESS - if success to re-schedule the reschedule_td.
++ * USB_ERR_FAIL - if fail to re-schedule the reschedule_td.
++ */
++ /******************************************************************************/
++int reschedule(td_t *reschedule_td)
++{
++ u32 td_addr;
++
++ if(get_transferring_td_array(reschedule_td->cur_stransfer.alloc_chnum, &td_addr)==USB_ERR_SUCCESS)
++ {
++ if((u32)reschedule_td == td_addr)
++ {
++ set_transferring_td_array(reschedule_td->cur_stransfer.alloc_chnum, 0);
++ oci_channel_dealloc(reschedule_td->cur_stransfer.alloc_chnum);
++
++ reschedule_td->cur_stransfer.alloc_chnum = CH_NONE;
++ reschedule_td->parent_ed_p->is_need_to_insert_scheduler = true;
++ reschedule_td->parent_ed_p->ed_status.in_transferring_td = 0;
++
++ if(reschedule_td->parent_ed_p->ed_desc.endpoint_type == BULK_TRANSFER||
++ reschedule_td->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER )
++ {
++ //Increase the available Channel
++ dec_nonperio_chnum();
++
++ }
++
++ insert_ed_to_ready_q(reschedule_td->parent_ed_p, false);
++ reschedule_td->parent_ed_p->ed_status.is_in_transfer_ready_q =true;
++
++ }
++ else
++ {
++ //this case is not support....
++ }
++ }
++ return USB_ERR_SUCCESS;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name int deallocate(td_t *deallocate_td)
++ *
++ * @brief this function frees resources to be allocated deallocate_td by S3CScheduler.
++ * this function just free the resource by S3CScheduler. that is, Channel Resource.
++ * if there are another td_t at ed_t, deallocate() insert the ed_t to TransferReadyQ.
++ *
++ * @param [IN] deallocate_td = indicates the pointer ot the td_t to be deallocated.
++ *
++ * @return USB_ERR_SUCCESS - if success to dealloate the resources for the deallocate_td.
++ * USB_ERR_FAIL - if fail to dealloate the resources for the deallocate_td.
++ */
++ /******************************************************************************/
++int deallocate(td_t *deallocate_td)
++{
++ u32 td_addr;
++
++ if(get_transferring_td_array(deallocate_td->cur_stransfer.alloc_chnum , &td_addr)==USB_ERR_SUCCESS)
++ {
++ if((u32)deallocate_td == td_addr)
++ {
++ set_transferring_td_array(deallocate_td->cur_stransfer.alloc_chnum, 0);
++ oci_channel_dealloc(deallocate_td->cur_stransfer.alloc_chnum);
++
++ deallocate_td->cur_stransfer.alloc_chnum = CH_NONE;
++
++ if(deallocate_td->parent_ed_p->ed_desc.endpoint_type == BULK_TRANSFER||
++ deallocate_td->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER )
++ {
++ //Increase the available Channel
++ dec_nonperio_chnum();
++ }
++
++ deallocate_td->parent_ed_p->is_need_to_insert_scheduler = true;
++
++ if(deallocate_td->parent_ed_p->num_td)
++ {
++ //insert ed_t to TransferReadyQ.
++ insert_ed_to_ready_q(deallocate_td->parent_ed_p , false);
++ deallocate_td->parent_ed_p->ed_status.is_in_transfer_ready_q = true;
++ deallocate_td->parent_ed_p->is_need_to_insert_scheduler = false;
++ }
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++
++}
++
++//TBD....
++void do_schedule(void)
++{
++ if(get_avail_chnum())
++ {
++ do_periodic_schedule();
++ do_nonperiodic_schedule();
++ }
++}
++
++/******************************************************************************/
++/*!
++ * @name int get_td_info(u8 chnum,
++ * unsigned int *td_addr_p)
++ *
++ * @brief this function returns the pointer of td_t at TransferringTDArray[chnum]
++ *
++ * @param [IN] chnum = indicates the index of TransferringTDArray
++ * to include the address of td_t which we gets
++ * [OUT] td_addr_p= indicate pointer to store the address of td_t.
++ *
++ * @return USB_ERR_SUCCESS -if success to get the address of td_t.
++ * USB_ERR_FAIL -if fail to get the address of td_t.
++ */
++ /******************************************************************************/
++int get_td_info( u8 chnum,
++ unsigned int *td_addr_p)
++{
++ u32 td_addr;
++
++ if(get_transferring_td_array(chnum, &td_addr)==USB_ERR_SUCCESS)
++ {
++ *td_addr_p = td_addr;
++ return USB_ERR_SUCCESS;
++ }
++
++ return USB_ERR_FAIL;
++}
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c
+new file mode 100644
+index 0000000..e6e9749
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c
+@@ -0,0 +1,253 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : TransferReadyQ.c
++ * [Description] : The source file implements the internal functions of TransferReadyQ.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/04
++ * [Revision History]
++ * (1) 2008/06/04 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements functions of TransferReadyQ.
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ *
++ ****************************************************************************/
++
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-scheduler-scheduler.h"
++
++static trans_ready_q_t periodic_trans_ready_q;
++static trans_ready_q_t nonperiodic_trans_ready_q;
++
++/******************************************************************************/
++/*!
++ * @name void init_transfer_ready_q(void)
++ *
++ * @brief this function initiates PeriodicTransferReadyQ and NonPeriodicTransferReadyQ.
++ *
++ *
++ * @param void
++ *
++ * @return void.
++ */
++/******************************************************************************/
++void init_transfer_ready_q(void)
++{
++
++ otg_dbg(OTG_DBG_SCHEDULE,"start init_transfer_ready_q\n");
++
++ otg_list_init(&periodic_trans_ready_q.trans_ready_q_list_head);
++ periodic_trans_ready_q.is_periodic_transfer = true;
++ periodic_trans_ready_q.trans_ready_entry_num = 0;
++ periodic_trans_ready_q.total_alloc_chnum = 0;
++ periodic_trans_ready_q.total_perio_bus_bandwidth = 0;
++
++ otg_list_init(&nonperiodic_trans_ready_q.trans_ready_q_list_head);
++ nonperiodic_trans_ready_q.is_periodic_transfer = false;
++ nonperiodic_trans_ready_q.trans_ready_entry_num = 0;
++ nonperiodic_trans_ready_q.total_alloc_chnum = 0;
++ nonperiodic_trans_ready_q.total_perio_bus_bandwidth = 0;
++
++
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int insert_ed_to_ready_q(ed_t *insert_ed,
++ * bool f_isfirst)
++ *
++ * @brief this function inserts ed_t * to TransferReadyQ.
++ *
++ *
++ * @param [IN] insert_ed = indicates the ed_t to be inserted to TransferReadyQ.
++ * [IN] f_isfirst = indicates whether the insert_ed is inserted as first entry of TransferReadyQ.
++ *
++ * @return USB_ERR_SUCCESS -if successes to insert the insert_ed to TransferReadyQ.
++ * USB_ERR_FAILl -if fails to insert the insert_ed to TransferReadyQ.
++ */
++/******************************************************************************/
++int insert_ed_to_ready_q(ed_t *insert_ed,
++ bool f_isfirst)
++{
++
++ if(insert_ed->ed_desc.endpoint_type == BULK_TRANSFER||
++ insert_ed->ed_desc.endpoint_type == CONTROL_TRANSFER)
++ {
++ if(f_isfirst)
++ {
++ otg_list_push_next(&insert_ed->trans_ready_q_list_entry,&nonperiodic_trans_ready_q.trans_ready_q_list_head);
++ }
++ else
++ {
++ otg_list_push_prev(&insert_ed->trans_ready_q_list_entry,&nonperiodic_trans_ready_q.trans_ready_q_list_head);
++ }
++ nonperiodic_trans_ready_q.trans_ready_entry_num++;
++ }
++ else
++ {
++ if(f_isfirst)
++ {
++ otg_list_push_next(&insert_ed->trans_ready_q_list_entry,&periodic_trans_ready_q.trans_ready_q_list_head);
++ }
++ else
++ {
++ otg_list_push_prev(&insert_ed->trans_ready_q_list_entry,&periodic_trans_ready_q.trans_ready_q_list_head);
++ }
++ periodic_trans_ready_q.trans_ready_entry_num++;
++ }
++
++ return USB_ERR_SUCCESS;
++
++}
++
++
++u32 get_periodic_ready_q_entity_num(void)
++{
++ return periodic_trans_ready_q.trans_ready_entry_num;
++}
++/******************************************************************************/
++/*!
++ * @name int remove_ed_from_ready_q(ed_t *remove_ed)
++ *
++ * @brief this function removes ed_t * from TransferReadyQ.
++ *
++ *
++ * @param [IN] remove_ed = indicate the ed_t to be removed from TransferReadyQ.
++ *
++ * @return USB_ERR_SUCCESS -if successes to remove the remove_ed from TransferReadyQ.
++ * USB_ERR_FAILl -if fails to remove the remove_ed from TransferReadyQ.
++ */
++/******************************************************************************/
++int remove_ed_from_ready_q(ed_t *remove_ed)
++{
++// SPINLOCK_t SLForRemoveED_t = SPIN_LOCK_INIT;
++// u32 uiSLFlag=0;
++
++ otg_list_pop(&remove_ed->trans_ready_q_list_entry);
++
++ if(remove_ed->ed_desc.endpoint_type == BULK_TRANSFER||
++ remove_ed->ed_desc.endpoint_type == CONTROL_TRANSFER)
++ {
++// spin_lock_irg_save_otg(&SLForRemoveED_t, uiSLFlag);
++// otg_list_pop(&remove_ed->trans_ready_q_list_entry);
++ nonperiodic_trans_ready_q.trans_ready_entry_num--;
++// spin_unlock_irq_save_otg(&SLForRemoveED_t, uiSLFlag);
++ }
++ else
++ {
++// spin_lock_irg_save_otg(&SLForRemoveED_t, uiSLFlag);
++// otg_list_pop(&remove_ed->trans_ready_q_list_entry);
++ periodic_trans_ready_q.trans_ready_entry_num--;
++// spin_unlock_irq_save_otg(&SLForRemoveED_t, uiSLFlag);
++ }
++
++ return USB_ERR_SUCCESS;
++
++}
++
++//by ss1 unused func
++/*
++bool check_ed_on_ready_q(ed_t *check_ed_p)
++{
++
++ if(check_ed_p->ed_status.is_in_transfer_ready_q)
++ return true;
++ else
++ return false;
++}*/
++
++/******************************************************************************/
++/*!
++ * @name int get_ed_from_ready_q(bool f_isperiodic,
++ * td_t **get_ed)
++ *
++ * @brief this function returns the first entity of TransferReadyQ.
++ * if there are some ed_t on TransferReadyQ, this function pops first ed_t from TransferReadyQ.
++ * So, the TransferReadyQ don's has the poped ed_t.
++ *
++ *
++ * @param [IN] f_isperiodic = indicate whether Periodic or not
++ * [OUT] get_ed = indicate the double pointer to store the address of first entity
++ * on TransferReadyQ.
++ *
++ * @return USB_ERR_SUCCESS -if successes to get frist ed_t from TransferReadyQ.
++ * USB_ERR_NO_ENTITY -if fails to get frist ed_t from TransferReadyQ
++ * because there is no entity on TransferReadyQ.
++ */
++/******************************************************************************/
++
++int get_ed_from_ready_q(bool f_isperiodic,
++ ed_t **get_ed)
++{
++ if(f_isperiodic)
++ {
++ otg_list_head *transreadyq_list_entity=NULL;
++
++ if(periodic_trans_ready_q.trans_ready_entry_num==0)
++ {
++ return USB_ERR_NO_ENTITY;
++ }
++
++ transreadyq_list_entity = periodic_trans_ready_q.trans_ready_q_list_head.next;
++
++ //if(transreadyq_list_entity!= &periodic_trans_ready_q.trans_ready_q_list_head)
++ if(!otg_list_empty(&periodic_trans_ready_q.trans_ready_q_list_head))
++ {
++ *get_ed = otg_list_get_node(transreadyq_list_entity,ed_t,trans_ready_q_list_entry);
++ otg_list_pop(transreadyq_list_entity);
++ periodic_trans_ready_q.trans_ready_entry_num--;
++
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_NO_ENTITY;
++ }
++ }
++ else
++ {
++ otg_list_head *transreadyq_list_entity=NULL;
++
++ if(nonperiodic_trans_ready_q.trans_ready_entry_num==0)
++ {
++ return USB_ERR_NO_ENTITY;
++ }
++
++ transreadyq_list_entity = nonperiodic_trans_ready_q.trans_ready_q_list_head.next;
++
++ //if(transreadyq_list_entity!= &nonperiodic_trans_ready_q.trans_ready_q_list_head)
++ if(!otg_list_empty(&nonperiodic_trans_ready_q.trans_ready_q_list_head))
++ {
++ *get_ed = otg_list_get_node(transreadyq_list_entity,ed_t, trans_ready_q_list_entry);
++
++ otg_list_pop(transreadyq_list_entity);
++
++ nonperiodic_trans_ready_q.trans_ready_entry_num--;
++
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_NO_ENTITY;
++ }
++ }
++}
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c
+new file mode 100644
+index 0000000..26bd50e
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c
+@@ -0,0 +1,449 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : Scheduler.c
++ * [Description] : The source file implements the internal functions of Scheduler.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/04
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements functions of Scheduler
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-scheduler-scheduler.h"
++
++//Define constant variables
++
++//the max periodic bus time is 80%*125us on High Speed Mode
++static const u32 perio_highbustime_threshold = 100;
++
++//the max periodic bus time is 90%*1000us(1ms) on Full/Low Speed Mode .
++static const u32 perio_fullbustime_threshold = 900;
++
++static const u8 perio_chnum_threshold = 14;
++//static const u8 total_chnum_threshold = 16;
++static u8 total_chnum_threshold = 16;
++
++ //Define global variables
++
++static u32 perio_used_bustime = 0;
++static u8 perio_used_chnum = 0;
++static u8 nonperio_used_chnum = 0;
++static u8 total_used_chnum = 0;
++static u32 transferring_td_array[16]={0};
++
++
++int inc_perio_bus_time(u32 bus_time, u8 dev_speed)
++{
++ switch(dev_speed)
++ {
++ case HIGH_SPEED_OTG:
++ if((bus_time+perio_used_bustime)<=perio_highbustime_threshold)
++ {
++ perio_used_bustime=+bus_time;
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++
++ case LOW_SPEED_OTG:
++ case FULL_SPEED_OTG:
++ if((bus_time+perio_used_bustime)<=perio_fullbustime_threshold)
++ {
++ perio_used_bustime=+bus_time;
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++ case SUPER_SPEED_OTG:
++ break;
++ default:
++ break;
++ }
++ return USB_ERR_FAIL;
++}
++
++int dec_perio_bus_time(u32 bus_time)
++{
++ if(perio_used_bustime >= bus_time )
++ {
++ perio_used_bustime =- bus_time;
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++}
++
++int inc_perio_chnum(void)
++{
++ if(perio_used_chnum<perio_chnum_threshold)
++ {
++ if(total_used_chnum<total_chnum_threshold)
++ {
++ perio_used_chnum++;
++ total_used_chnum++;
++ return USB_ERR_SUCCESS;
++ }
++ }
++ return USB_ERR_FAIL;
++}
++
++u8 get_avail_chnum(void)
++{
++ return total_chnum_threshold - total_used_chnum;
++}
++
++int dec_perio_chnum(void)
++{
++ if(perio_used_chnum>0)
++ {
++ if(total_used_chnum>0)
++ {
++ perio_used_chnum--;
++ total_used_chnum--;
++ return USB_ERR_SUCCESS;
++ }
++ }
++ return USB_ERR_FAIL;
++}
++
++int inc_non_perio_chnum(void)
++{
++ if(nonperio_used_chnum<total_chnum_threshold)
++ {
++ if(total_used_chnum<total_chnum_threshold)
++ {
++ nonperio_used_chnum++;
++ total_used_chnum++;
++ return USB_ERR_SUCCESS;
++ }
++ }
++ return USB_ERR_FAIL;
++}
++
++int dec_nonperio_chnum(void)
++{
++ if(nonperio_used_chnum>0)
++ {
++ if(total_used_chnum>0)
++ {
++ nonperio_used_chnum--;
++ total_used_chnum--;
++ return USB_ERR_SUCCESS;
++ }
++ }
++ return USB_ERR_FAIL;
++}
++
++int get_transferring_td_array(u8 chnum, unsigned int *td_addr)
++{
++ if(transferring_td_array[chnum]!=0)
++ {
++ *td_addr = transferring_td_array[chnum];
++ return USB_ERR_SUCCESS;
++ }
++
++ return USB_ERR_FAIL;
++}
++
++int set_transferring_td_array(u8 chnum, u32 td_addr)
++{
++ if(td_addr ==0)
++ {
++ transferring_td_array[chnum] = td_addr;
++ return USB_ERR_SUCCESS;
++ }
++
++ if(transferring_td_array[chnum] == 0)
++ {
++ transferring_td_array[chnum] = td_addr;
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_FAIL;
++ }
++}
++
++/******************************************************************************/
++/*!
++ * @name int insert_ed_to_scheduler(ed_t *insert_ed)
++ *
++ * @brief this function transfers the insert_ed to S3C6400Scheduler, and
++ * after that, the insert_ed is inserted to TransferReadyQ and scheduled by Scheduler.
++ *
++ *
++ * @param [IN] insert_ed = indicates pointer of ed_t to be inserted to TransferReadyQ.
++ *
++ * @return USB_ERR_ALREADY_EXIST - if the insert_ed is already existed.
++ * USB_ERR_SUCCESS - if success to insert insert_ed to S3CScheduler.
++ */
++/******************************************************************************/
++int insert_ed_to_scheduler(ed_t *insert_ed)
++{
++ if(!insert_ed->is_need_to_insert_scheduler)
++ {
++ return USB_ERR_ALREADY_EXIST;
++ }
++
++ insert_ed_to_ready_q(insert_ed, false);
++ insert_ed->is_need_to_insert_scheduler = false;
++ insert_ed->ed_status.is_in_transfer_ready_q = true;
++
++ do_periodic_schedule();
++ do_nonperiodic_schedule();
++
++ return USB_ERR_SUCCESS;
++}
++
++/******************************************************************************/
++/*!
++ * @name int do_periodic_schedule(void)
++ *
++ * @brief this function schedules PeriodicTransferReadyQ.
++ * this function checks whether PeriodicTransferReadyQ has some ed_t.
++ * if there are some ed_t on PeriodicTransferReadyQ
++ * , this function request to start USB Trasnfer to S3C6400OCI.
++ *
++ *
++ * @param void
++ *
++ * @return void
++ */
++/******************************************************************************/
++void do_periodic_schedule(void)
++{
++ ed_t *scheduling_ed= NULL;
++ int err_sched = USB_ERR_SUCCESS;
++ u32 sched_cnt = 0;
++
++ otg_dbg(OTG_DBG_SCHEDULE,"*******Start to DoPeriodicSchedul*********\n");
++
++ sched_cnt = get_periodic_ready_q_entity_num();
++
++ while(sched_cnt)
++ {
++
++ //in periodic transfser, the channel resource was already reserved.
++ //So, we don't need this routine...
++
++start_sched_perio_transfer:
++ if(!sched_cnt)
++ goto end_sched_perio_transfer;
++
++ err_sched = get_ed_from_ready_q(true, &scheduling_ed);
++
++ if(err_sched==USB_ERR_SUCCESS)
++ {
++ otg_list_head *td_list_entry;
++ td_t *td;
++ u32 cur_frame_num = 0;
++
++ otg_dbg(OTG_DBG_SCHEDULE,"the ed_t to be scheduled :%d",(int)scheduling_ed);
++ sched_cnt--;
++ td_list_entry = scheduling_ed->td_list_entry.next;
++
++ if(td_list_entry == &scheduling_ed->td_list_entry)
++ {
++ //scheduling_ed has no td_t. so we schedules another ed_t on PeriodicTransferReadyQ.
++ goto start_sched_perio_transfer;
++ }
++
++ if(scheduling_ed->ed_status.is_in_transferring)
++ {
++ //scheduling_ed is already Scheduled. so we schedules another ed_t on PeriodicTransferReadyQ.
++ goto start_sched_perio_transfer;
++ }
++
++ cur_frame_num = oci_get_frame_num();
++
++ if(((cur_frame_num-scheduling_ed->ed_desc.sched_frame)&HFNUM_MAX_FRNUM)>(HFNUM_MAX_FRNUM>>1))
++ {
++ insert_ed_to_ready_q(scheduling_ed, false);
++ goto start_sched_perio_transfer;
++ }
++
++ td = otg_list_get_node(td_list_entry, td_t, td_list_entry);
++
++ if((!td->is_transferring) && (!td->is_transfer_done))
++ {
++ u8 alloc_ch;
++ otg_dbg(OTG_DBG_SCHEDULE,"the td_t to be scheduled :%d",(int)td);
++ alloc_ch = oci_start_transfer(&td->cur_stransfer);
++ if(alloc_ch<total_chnum_threshold)
++ {
++ td->cur_stransfer.alloc_chnum = alloc_ch;
++ transferring_td_array[alloc_ch] = (u32)td;
++
++ scheduling_ed->ed_status.is_in_transferring = true;
++ scheduling_ed->ed_status.is_in_transfer_ready_q = false;
++ scheduling_ed->ed_status.in_transferring_td = (u32)td;
++
++ td->is_transferring = true;
++ }
++ else
++ {
++ //we should insert the ed_t to TransferReadyQ, because the USB Transfer of the ed_t is failed.
++ scheduling_ed->ed_status.is_in_transferring = false;
++ scheduling_ed->ed_status.is_in_transfer_ready_q = true;
++ scheduling_ed->ed_status.in_transferring_td = 0;
++
++ insert_ed_to_ready_q(scheduling_ed,true);
++
++ scheduling_ed->is_need_to_insert_scheduler = false;
++ goto end_sched_perio_transfer;
++ }
++
++ }
++ else
++ { // the selected td_t was already transferring or completed to transfer.
++ //we should decide how to control this case.
++ goto end_sched_perio_transfer;
++ }
++
++
++ }
++ else
++ {
++ // there is no ED on PeriodicTransferQ. So we finish scheduling.
++ goto end_sched_perio_transfer;
++ }
++ }
++
++end_sched_perio_transfer:
++
++ return;
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int do_nonperiodic_schedule(void)
++ *
++ * @brief this function start to schedule thie NonPeriodicTransferReadyQ.
++ * this function checks whether NonPeriodicTransferReadyQ has some ed_t.
++ * if there are some ed_t on NonPeriodicTransferReadyQ
++ * , this function request to start USB Trasnfer to S3C6400OCI.
++ *
++ *
++ * @param void
++ *
++ * @return void
++ */
++/******************************************************************************/
++void do_nonperiodic_schedule(void)
++{
++ if(total_used_chnum<total_chnum_threshold)
++ {
++ ed_t *scheduling_ed;
++ int err_sched;
++
++ while(1)
++ {
++
++start_sched_nonperio_transfer:
++
++ //check there is available channel resource for Non-Periodic Transfer.
++ if(total_used_chnum==total_chnum_threshold)
++ {
++ goto end_sched_nonperio_transfer;
++ }
++
++ err_sched = get_ed_from_ready_q(false, &scheduling_ed);
++
++ if(err_sched ==USB_ERR_SUCCESS )
++ {
++ otg_list_head *td_list_entry;
++ td_t *td;
++
++ td_list_entry = scheduling_ed->td_list_entry.next;
++
++ //if(td_list_entry == &scheduling_ed->td_list_entry)
++ if(otg_list_empty(&scheduling_ed->td_list_entry))
++ {
++ //scheduling_ed has no td_t. so we schedules another ed_t on PeriodicTransferReadyQ.
++ goto start_sched_nonperio_transfer;
++ }
++
++ if(scheduling_ed->ed_status.is_in_transferring)
++ {
++ //scheduling_ed is already Scheduled. so we schedules another ed_t on PeriodicTransferReadyQ.
++ goto start_sched_nonperio_transfer;
++ }
++
++ td = otg_list_get_node(td_list_entry, td_t, td_list_entry);
++
++ if((!td->is_transferring) && (!td->is_transfer_done))
++ {
++ u8 alloc_ch;
++
++ alloc_ch =oci_start_transfer(&td->cur_stransfer);
++
++ if(alloc_ch<total_chnum_threshold)
++ {
++ td->cur_stransfer.alloc_chnum = alloc_ch;
++ transferring_td_array[alloc_ch] = (u32)td;
++
++ inc_non_perio_chnum();
++
++ scheduling_ed->ed_status.is_in_transferring = true;
++ scheduling_ed->ed_status.is_in_transfer_ready_q = false;
++ scheduling_ed->ed_status.in_transferring_td =(u32)td;
++ td->is_transferring = true;
++ }
++ else
++ {
++ //we should insert the ed_t to TransferReadyQ, because the USB Transfer of the ed_t is failed.
++ scheduling_ed->ed_status.is_in_transferring = false;
++ scheduling_ed->ed_status.in_transferring_td =0;
++ insert_ed_to_ready_q(scheduling_ed,true);
++ scheduling_ed->ed_status.is_in_transfer_ready_q = true;
++
++ goto end_sched_nonperio_transfer;
++ }
++ }
++ else
++ {
++ goto end_sched_nonperio_transfer;
++ }
++ }
++ else
++ { //there is no ed_t on NonPeriodicTransferReadyQ.
++ //So, we finish do_nonperiodic_schedule().
++ goto end_sched_nonperio_transfer;
++ }
++ }
++ }
++
++end_sched_nonperio_transfer:
++
++ return;
++}
++
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h
+new file mode 100644
+index 0000000..5b7e553
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h
+@@ -0,0 +1,103 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : Scheduler.h
++ * [Description] : The Header file defines the external and internal functions of Scheduler.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/03
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines functions of Scheduler
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _SCHEDULER_H
++#define _SCHEDULER_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-hcdi-memory.h"
++#include "s3c-otg-hcdi-kal.h"
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-oci.h"
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++
++//Defines external functions of IScheduler.c
++extern void init_scheduler(void);
++//extern int insert_ed_to_scheduler(ed_t *insert_ed);
++extern int reserve_used_resource_for_periodic(u32 usb_time,u8 dev_speed, u8 trans_type);
++extern int free_usb_resource_for_periodic(u32 free_usb_time, u8 free_chnum, u8 trans_type);
++extern int remove_ed_from_scheduler(ed_t *remove_ed);
++extern int cancel_to_transfer_td(td_t *cancel_td);
++extern int retransmit(td_t *retransmit_td);
++extern int reschedule(td_t *resched_td);
++extern int deallocate(td_t *dealloc_td);
++extern void do_schedule(void);
++
++extern int get_td_info(u8 chnum,unsigned int *td_addr);
++
++
++// Defines functiions of TranferReadyQ.
++void init_transfer_ready_q(void);
++int insert_ed_to_ready_q(ed_t *insert_ed, bool f_isfirst);
++int remove_ed_from_ready_q(ed_t *remove_ed);
++int get_ed_from_ready_q(bool f_isperiodic, ed_t **get_ed);
++
++//Define functions of Scheduler
++void do_periodic_schedule(void);
++void do_nonperiodic_schedule(void);
++int set_transferring_td_array(u8 chnum, u32 td_addr);
++int get_transferring_td_array(u8 chnum, unsigned int *td_addr);
++
++
++//Define fuctions to manage some static global variable.
++int inc_perio_bus_time(u32 uiBusTime, u8 dev_speed);
++int dec_perio_bus_time(u32 uiBusTime);
++
++u8 get_avail_chnum(void);
++int inc_perio_chnum(void);
++int dec_perio_chnum(void);
++int inc_non_perio_chnum(void);
++int dec_nonperio_chnum(void);
++u32 get_periodic_ready_q_entity_num(void);
++
++int insert_ed_to_scheduler(ed_t * insert_ed);
++
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c b/drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c
+new file mode 100644
+index 0000000..6cce851
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c
+@@ -0,0 +1,838 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : Commons3c-otg-transfer-transfer.h
++ * [Description] : This source file implements the functions to be defined at CommonTransfer Module.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/03
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements some functions of CommonTransfer.
++ * (2) 2008/07/15 by SeungSoo Yang ( ss1.yang@samsung.com )n
++ * - Optimizing for performance \n
++ * (3) 2008/08/18 by SeungSoo Yang ( ss1.yang@samsung.com )
++ * - Modifying for successful rmmod & disconnecting \n
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-transfer-transfer.h"
++
++// the header pointer to indicate the ED_list to manage the ed_t to be created and initiated.
++otg_list_head ed_list_head;
++u32 ref_periodic_transfer;
++
++/******************************************************************************/
++/*!
++ * @name void init_transfer(void)
++ *
++ * @brief this function initiates the S3CTranfer module. that is, this functions initiates
++ * the ED_list_head OTG List which manages the all ed_t to be existed.
++ *
++ * @param void
++ *
++ * @return void
++ */
++/******************************************************************************/
++
++void init_transfer(void)
++{
++ otg_dbg(OTG_DBG_TRANSFER,"start to init_transfer\n");
++ otg_list_init(&ed_list_head);
++ ref_periodic_transfer = 0;
++
++}
++
++
++/******************************************************************************/
++/*!
++ * @name void DeInitTransfer(void)
++ *
++ * @brief this function Deinitiates the S3CTranfer module. this functions check which there are
++ * some ed_t on ED_list_head. if some ed_t exists, deinit_transfer() deletes the ed_t.
++ *
++ *
++ * @param void
++ *
++ * @return void
++ */
++/******************************************************************************/
++void deinit_transfer(void)
++{
++ otg_list_head *ed_list_member;
++ ed_t *delete_ed_p;
++
++ while(otg_list_empty(&ed_list_head) != true)
++ {
++ ed_list_member = ed_list_head.next;
++
++ // otg_list_pop(ed_list_member);
++
++ delete_ed_p= otg_list_get_node(ed_list_member,ed_t,ed_list_entry);
++
++ delete_ed(delete_ed_p);
++ }
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int delete_ed(ed_t *delete_ed)
++ *
++ * @brief this function delete the delete_ed.
++ * if there is some available TD_ts on delete_ed, then this function also deletes these td_t
++ *
++ *
++ * @param [IN] delete_ed = indicates the address of ed_t to be deleted.
++ *
++ * @return USB_ERR_SUCCESS -if successes to delete the ed_t.
++ * USB_ERR_FAILl -if fails to delete the ed_t.
++ */
++/******************************************************************************/
++int delete_ed(ed_t *delete_ed)
++{
++ otg_kal_make_ep_null(delete_ed);
++
++ if(delete_ed->num_td)
++ {
++ cancel_all_td(delete_ed);
++/**
++ need to giveback of td's urb with considering life-cycle of
++ TD, ED, urb->hcpriv, td->private, ep->hcpriv, td->parentED
++ (commented by ss1.yang)
++*/
++ }
++
++ otg_list_pop(&delete_ed->ed_list_entry);
++
++ if(delete_ed->ed_desc.endpoint_type == INT_TRANSFER ||
++ delete_ed->ed_desc.endpoint_type == ISOCH_TRANSFER)
++ {
++ ref_periodic_transfer--;
++ }
++
++ if(ref_periodic_transfer==0)
++ {
++ disable_sof();
++ }
++ otg_mem_free(delete_ed);
++
++ return USB_ERR_SUCCESS;
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int delete_td(td_t *delete_td)
++ *
++ * @brief this function frees memory resource for the delete_td.
++ * and if delete_td is transferring USB Transfer, then this function request to cancel
++ * the USB Transfer to S3CScheduler.
++ *
++ *
++ * @param [OUT] new_td_p = returns the address of the new td_t .
++ *
++ * @return USB_ERR_SUCCESS -if successes to create the new td_t.
++ * USB_ERR_FAILl -if fails to create to new td_t.
++ */
++/******************************************************************************/
++int delete_td(td_t *delete_td)
++{
++
++ if(delete_td->is_transferring)
++ {
++ //at this case, we should cancel the USB Transfer.
++ cancel_to_transfer_td(delete_td);
++ }
++
++ otg_mem_free(delete_td);
++ return USB_ERR_SUCCESS;
++}
++
++
++int create_isoch_packet_desc( isoch_packet_desc_t **new_isoch_packet_desc,
++ u32 isoch_packet_num)
++{
++ return otg_mem_alloc((void **)new_isoch_packet_desc, (u16)sizeof(isoch_packet_desc_t)*isoch_packet_num,USB_MEM_SYNC);
++}
++
++int delete_isoch_packet_desc( isoch_packet_desc_t *del_isoch_packet_desc,
++ u32 isoch_packet_num)
++{
++ return otg_mem_free(del_isoch_packet_desc);
++}
++
++
++/******************************************************************************/
++/*!
++ * @name void init_isoch_packet_desc( isoch_packet_desc_t *init_isoch_packet_desc,
++ * u32 isoch_packet_start_addr,
++ * u32 isoch_packet_size,
++ * u32 index)
++ *
++ * @brief this function initiates the isoch_packet_desc_t[index].
++ *
++ *
++ * @param [OUT] init_isoch_packet_desc = indicates the pointer of IsochPackDesc_t to be initiated.
++ * [IN] isoch_packet_start_addr = indicates the start address of the buffer to be used
++ * at USB Isochronous Transfer.
++ * [IN] isoch_packet_size = indicates the size of Isochronous packet.
++ * [IN] index = indicates the index to be mapped with this init_isoch_packet_desc.
++ *
++ * @return void
++ */
++/******************************************************************************/
++void init_isoch_packet_desc( isoch_packet_desc_t *init_isoch_packet_desc,
++ u32 isoch_packet_start_addr,
++ u32 isoch_packet_size,
++ u32 index)
++{
++
++ init_isoch_packet_desc[index].buf_size = isoch_packet_size;
++ init_isoch_packet_desc[index].isoch_packiet_start_addr = isoch_packet_start_addr;
++ init_isoch_packet_desc[index].isoch_status = 0;
++ init_isoch_packet_desc[index].transferred_szie = 0;
++
++
++}
++
++/******************************************************************************/
++/*!
++ * @name int create_ed(ed_t **new_ed)
++ *
++ * @brief this function creates a new ed_t and returns the ed_t to Caller
++ *
++ *
++ * @param [OUT] new_ed = returns the address of the new ed_t .
++ *
++ * @return USB_ERR_SUCCESS -if successes to create the new ed_t.
++ * USB_ERR_FAILl -if fails to create to new ed_t.
++ */
++/******************************************************************************/
++int create_ed(ed_t **new_ed)
++{
++ int err_code = USB_ERR_SUCCESS;
++
++ err_code = otg_mem_alloc((void **)new_ed,(u16)sizeof(ed_t), USB_MEM_SYNC);
++ otg_mem_set(*new_ed, 0, sizeof(ed_t));
++ return err_code;
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int init_ed( ed_t *init_ed,
++ * u8 dev_addr,
++ * u8 ep_num,
++ * bool f_is_ep_in,
++ * u8 dev_speed,
++ * u8 ep_type,
++ * u32 max_packet_size,
++ * u8 multi_count,
++ * u8 interval,
++ * u32 sched_frame,
++ * u8 hub_addr,
++ * u8 hub_port,
++ * bool f_is_do_split)
++ *
++ * @brief this function initiates the init_ed by using the another parameters.
++ *
++ *
++ * @param [OUT] init_ed = returns the ed_t to be initiated.
++ * [IN] dev_addr = inidcates the address of USB Device.
++ * [IN] ep_num = inidcates the number of the specific endpoint on USB Device.
++ * [IN] f_is_ep_in = inidcates whether the endpoint is IN or not
++ * [IN] dev_speed = inidcates the speed of USB Device.
++ * [IN] max_packet_size = inidcates the maximum packet size of a specific endpoint on USB Device.
++ * [IN] multi_count = if the endpoint supports periodic transfer
++ * , this indicates the multiple packet to be transferred on a uframe
++ * [IN] interval= if the endpoint support periodic transfer, this indicates the polling rate.
++ * [IN] sched_frame= if the endpoint supports periodic transfer, this indicates the start frame number.
++ * [IN] hub_addr= indicate the address of hub which the USB device attachs to.
++ * [IN] hub_port= inidcates the port number of the hub which the USB device attachs to.
++ * [IN] f_is_do_split= inidcates whether this tranfer is split transaction or not.
++ *
++ * @return USB_ERR_SUCCESS -if successes to initiate the ed_t.
++ * USB_ERR_FAILl -if fails to initiate the ed_t.
++ * USB_ERR_NOSPACE -if fails to initiate the ed_t
++ * because there is no USB Resource for this init_ed.
++ */
++/******************************************************************************/
++int init_ed(ed_t *init_ed,
++ u8 dev_addr,
++ u8 ep_num,
++ bool f_is_ep_in,
++ u8 dev_speed,
++ u8 ep_type,
++ u16 max_packet_size,
++ u8 multi_count,
++ u8 interval,
++ u32 sched_frame,
++ u8 hub_addr,
++ u8 hub_port,
++ bool f_is_do_split,
++ void *ep)
++{
++ init_ed->is_halted = false;
++ init_ed->is_need_to_insert_scheduler= true;
++ init_ed->ed_id = (u32)init_ed;
++ init_ed->num_td = 0;
++ init_ed->ed_private = ep;
++
++ otg_list_init(&init_ed->td_list_entry);
++
++ //start to initiate struct ed_desc....
++ init_ed->ed_desc.is_do_split = f_is_do_split;
++ init_ed->ed_desc.is_ep_in = f_is_ep_in;
++ init_ed->ed_desc.dev_speed = dev_speed;
++ init_ed->ed_desc.hub_addr = hub_addr;
++ init_ed->ed_desc.hub_port = hub_port;
++ init_ed->ed_desc.mc = multi_count;
++ init_ed->ed_desc.device_addr = dev_addr;
++ init_ed->ed_desc.endpoint_num = ep_num;
++ init_ed->ed_desc.endpoint_type = ep_type;
++ init_ed->ed_desc.max_packet_size = max_packet_size;
++ init_ed->ed_desc.sched_frame = sched_frame;
++
++ if(init_ed->ed_desc.endpoint_type == INT_TRANSFER)
++ {
++ if(init_ed->ed_desc.dev_speed == LOW_SPEED_OTG ||init_ed->ed_desc.dev_speed == FULL_SPEED_OTG)
++ {
++ init_ed->ed_desc.interval =interval;
++ }
++ else if(init_ed->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ u8 count = 0;
++ u8 cal_interval = 1;
++
++ for(count = 0;count<(init_ed->ed_desc.interval-1);count++)
++ {
++ cal_interval *=2;
++ }
++
++ init_ed->ed_desc.interval =cal_interval;
++ }
++ else
++ {
++ otg_dbg(OTG_DBG_TRANSFER,"Super-Speed is not supported\n");
++ }
++ init_ed->ed_desc.sched_frame = (SCHEDULE_SLOT+oci_get_frame_num())&HFNUM_MAX_FRNUM;
++ ref_periodic_transfer++;
++ }
++ if(init_ed->ed_desc.endpoint_type==ISOCH_TRANSFER)
++ {
++ u8 count = 0;
++ u8 cal_interval = 1;
++
++ for(count = 0;count<(init_ed->ed_desc.interval-1);count++)
++ {
++ cal_interval *=2;
++ }
++
++ init_ed->ed_desc.interval = cal_interval;
++ init_ed->ed_desc.sched_frame = (SCHEDULE_SLOT+oci_get_frame_num())&HFNUM_MAX_FRNUM;
++ ref_periodic_transfer++;
++ }
++
++ //start to initiate struct ed_status....
++
++ //initiates PID
++ switch(ep_type)
++ {
++ case BULK_TRANSFER:
++ case INT_TRANSFER:
++ init_ed->ed_status.data_tgl = DATA0;
++ break;
++
++ case CONTROL_TRANSFER:
++ init_ed->ed_status.control_data_tgl.setup_tgl = SETUP;
++ init_ed->ed_status.control_data_tgl.data_tgl = DATA1;
++ init_ed->ed_status.control_data_tgl.status_tgl = DATA1;
++ break;
++
++ case ISOCH_TRANSFER:
++ if(f_is_ep_in)
++ {
++ switch(multi_count)
++ {
++ case MULTI_COUNT_ZERO :
++ init_ed->ed_status.data_tgl = DATA0;
++ break;
++ case MULTI_COUNT_ONE :
++ init_ed->ed_status.data_tgl = DATA1;
++ break;
++ case MULTI_COUNT_TWO :
++ init_ed->ed_status.data_tgl = DATA2;
++ break;
++ default:break;
++ }
++ }
++ else
++ {
++ switch(multi_count)
++ {
++ case MULTI_COUNT_ZERO :
++ init_ed->ed_status.data_tgl = DATA0;
++ break;
++ case MULTI_COUNT_ONE :
++ init_ed->ed_status.data_tgl = MDATA;
++ break;
++ case MULTI_COUNT_TWO :
++ init_ed->ed_status.data_tgl = MDATA;
++ break;
++ default:break;
++ }
++ }
++ break;
++ default:
++ break;
++
++ }
++
++ if(init_ed->ed_desc.endpoint_type == INT_TRANSFER ||
++ init_ed->ed_desc.endpoint_type == ISOCH_TRANSFER)
++ {
++ u32 usb_time = 0, byte_count = 0;
++
++ //calculates the bytes to be transferred at one (uframe)frame.
++ byte_count = (init_ed->ed_desc.mc+1)*init_ed->ed_desc.max_packet_size;
++
++ usb_time = (u32)otg_usbcore_get_calc_bustime(init_ed->ed_desc.dev_speed,
++ init_ed->ed_desc.is_ep_in,
++ (init_ed->ed_desc.endpoint_type==ISOCH_TRANSFER?true:false),
++ byte_count);
++ usb_time /= 1000; //convert nanosec unit to usec unit
++
++ if(reserve_used_resource_for_periodic(usb_time, init_ed->ed_desc.dev_speed, init_ed->ed_desc.endpoint_type)!=USB_ERR_SUCCESS)
++ {
++ return USB_ERR_NOSPACE;
++ }
++
++ init_ed->ed_status.is_alloc_resource_for_ed =true;
++ init_ed->ed_desc.used_bus_time =usb_time;
++ init_ed->ed_desc.mc =multi_count+1;
++ }
++
++ init_ed->ed_status.is_in_transfer_ready_q =false;
++ init_ed->ed_status.is_in_transferring =false;
++ init_ed->ed_status.is_ping_enable =false;
++ init_ed->ed_status.in_transferring_td =0;
++
++ //push the ed_t to ED_list.
++ otg_list_push_prev(&init_ed->ed_list_entry,&ed_list_head);
++
++ if(ref_periodic_transfer)
++ {
++ enable_sof();
++ }
++ return USB_ERR_SUCCESS;
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int create_td(td_t **new_td)
++ *
++ * @brief this function creates a new td_t and returns the td_t to Caller
++ *
++ *
++ * @param [OUT] new_td = returns the address of the new td_t .
++ *
++ * @return USB_ERR_SUCCESS -if successes to create the new td_t.
++ * USB_ERR_FAILl -if fails to create to new td_t.
++ */
++/******************************************************************************/
++int create_td(td_t **new_td)
++{
++ int err_code = USB_ERR_SUCCESS;
++
++ err_code = otg_mem_alloc((void **)new_td,(u16)sizeof(td_t), USB_MEM_SYNC);
++ otg_mem_set(*new_td, 0, sizeof(td_t));
++ return err_code;
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int init_td( td_t *init_td,
++ * ed_t *parent_ed,
++ * void *call_back_fun,
++ * void *call_back_param,
++ * u32 transfer_flag,
++ * bool f_is_standard_dev_req,
++ * u32 phy_setup,
++ * u32 vir_setup,
++ * u32 vir_buf_addr,
++ * u32 phy_buf_addr,
++ * u32 buf_size,
++ * u32 isoch_start_frame,
++ * isoch_packet_desc_t *isoch_packet_desc,
++ * u32 isoch_packet_num,
++ * void *td_priv)
++ *
++ * @brief this function initiates the init_td by using another parameter.
++ *
++ *
++ * @param [IN] init_td - indicate the td_t to be initiated.
++ * [IN] parent_ed - indicate the ed_t to manage this init_td
++ * [IN] call_back_func - indicate the call-back function of application.
++ * [IN] call_back_param - indicate the parameter of the call-back function.
++ * [IN] transfer_flag - indicate the transfer flag.
++ * [IN] f_is_standard_dev_req - indicates the issue transfer request is USB Standard Request
++ * [IN] phy_setup - the physical address of buffer to store the USB Standard Request.
++ * [IN] vir_setup - the virtual address of buffer to store the USB Standard Request.
++ * [IN] vir_buf_addr - the virtual address of buffer to store the data to be transferred or received.
++ * [IN] phy_buf_addr - the physical address of buffer to store the data to be transferred or received.
++ * [IN] buf_size - indicates the buffer size.
++ * [IN] isoch_start_frame - if this usb transfer is isochronous transfer
++ * , this indicates the start frame to start the usb transfer.
++ * [IN] isoch_packet_desc - if the usb transfer is isochronous transfer
++ * , this indicates the structure to describe the isochronous transfer.
++ * [IN] isoch_packet_num - if the usb transfer is isochronous transfer
++ * , this indicates the number of packet to consist of the usb transfer.
++ * [IN] td_priv - indicate the private data to be delivered from usb core of linux.
++ * td_priv stores the urb of linux.
++ *
++ * @return USB_ERR_SUCCESS -if successes to initiate the new td_t.
++ * USB_ERR_FAILl -if fails to create to new td_t.
++ */
++/******************************************************************************/
++int init_td( td_t *init_td,
++ ed_t *parent_ed,
++ void *call_back_fun,
++ void *call_back_param,
++ u32 transfer_flag,
++ bool f_is_standard_dev_req,
++ u32 phy_setup,
++ u32 vir_setup,
++ u32 vir_buf_addr,
++ u32 phy_buf_addr,
++ u32 buf_size,
++ u32 isoch_start_frame,
++ isoch_packet_desc_t *isoch_packet_desc,
++ u32 isoch_packet_num,
++ void *td_priv)
++{
++ if(f_is_standard_dev_req)
++ {
++ if((phy_buf_addr>0) && (buf_size>0))
++ {
++ init_td->standard_dev_req_info.is_data_stage = true;
++ }
++ else
++ {
++ init_td->standard_dev_req_info.is_data_stage = false;
++ }
++ init_td->standard_dev_req_info.conrol_transfer_stage = SETUP_STAGE;
++ init_td->standard_dev_req_info.phy_standard_dev_req_addr = phy_setup;
++ init_td->standard_dev_req_info.vir_standard_dev_req_addr = vir_setup;
++ }
++
++ init_td->call_back_func_p = call_back_fun;
++ init_td->call_back_func_param_p = call_back_param;
++ init_td->error_code = USB_ERR_SUCCESS;
++ init_td->is_standard_dev_req = f_is_standard_dev_req;
++ init_td->is_transfer_done = false;
++ init_td->is_transferring = false;
++ init_td->td_private = td_priv;
++ init_td->err_cnt = 0;
++ init_td->parent_ed_p = parent_ed;
++ init_td->phy_buf_addr = phy_buf_addr;
++ init_td->vir_buf_addr = vir_buf_addr;
++ init_td->buf_size = buf_size;
++ init_td->isoch_packet_desc_p = isoch_packet_desc;
++ init_td->isoch_packet_num = isoch_packet_num;
++ init_td->isoch_packet_index = 0;
++ init_td->isoch_packet_position = 0;
++ init_td->sched_frame = isoch_start_frame;
++ init_td->used_total_bus_time = parent_ed->ed_desc.used_bus_time;
++ init_td->td_id = (u32)init_td;
++ init_td->transfer_flag = transfer_flag;
++ init_td->transferred_szie = 0;
++
++ switch(parent_ed->ed_desc.endpoint_type)
++ {
++ case CONTROL_TRANSFER:
++ init_nonperio_stransfer(true, init_td);
++ break;
++
++ case BULK_TRANSFER:
++ init_nonperio_stransfer(false, init_td);
++ break;
++
++ case INT_TRANSFER:
++ init_perio_stransfer(false, init_td);
++ break;
++
++ case ISOCH_TRANSFER:
++ init_perio_stransfer(true, init_td);
++ break;
++
++ default:
++ return USB_ERR_FAIL;
++ }
++
++ //insert the td_t to parent_ed->td_list_entry.
++ otg_list_push_prev(&init_td->td_list_entry,&parent_ed->td_list_entry);
++ parent_ed->num_td++;
++
++ return USB_ERR_SUCCESS;
++}
++
++/******************************************************************************/
++/*!
++ * @name int issue_transfer(ed_t *parent_ed,
++ * void *call_back_func,
++ * void *call_back_param,
++ * u32 transfer_flag,
++ * bool f_is_standard_dev_req,
++ * u32 setup_vir_addr,
++ * u32 setup_phy_addr,
++ * u32 vir_buf_addr,
++ * u32 phy_buf_addr,
++ * u32 buf_size,
++ * u32 start_frame,
++ * u32 isoch_packet_num,
++ * isoch_packet_desc_t *isoch_packet_desc,
++ * void *td_priv,
++ * unsigned int *return_td_addr)
++ *
++ * @brief this function start USB Transfer
++ *
++ *
++ * @param [IN] parent_ed - indicate the ed_t to manage this issue transfer.
++ * [IN] call_back_func - indicate the call-back function of application.
++ * [IN] call_back_param - indicate the parameter of the call-back function.
++ * [IN] transfer_flag - indicate the transfer flag.
++ * [IN] f_is_standard_dev_req - indicates the issue transfer request is USB Standard Request
++ * [IN] setup_vir_addr - the virtual address of buffer to store the USB Standard Request.
++ * [IN] setup_phy_addr - the physical address of buffer to store the USB Standard Request.
++ * [IN] vir_buf_addr - the virtual address of buffer to store the data to be transferred or received.
++ * [IN] phy_buf_addr - the physical address of buffer to store the data to be transferred or received.
++ * [IN] buf_size - indicates the buffer size.
++ * [IN] start_frame - if this usb transfer is isochronous transfer
++ * , this indicates the start frame to start the usb transfer.
++ * [IN] isoch_packet_num - if the usb transfer is isochronous transfer
++ * , this indicates the number of packet to consist of the usb transfer.
++ * [IN] isoch_packet_desc - if the usb transfer is isochronous transfer
++ * , this indicates the structure to describe the isochronous transfer.
++ * [IN] td_priv - indicate the private data to be delivered from usb core of linux.
++ * td_priv stores the urb of linux.
++ * [OUT] return_td_addr - indicates the variable address to store the new td_t for this transfer
++ *
++ * @return USB_ERR_SUCCESS -if successes to initiate the new td_t.
++ * USB_ERR_FAILl -if fails to create to new td_t.
++ */
++/******************************************************************************/
++int issue_transfer(ed_t *parent_ed,
++ void *call_back_func,
++ void *call_back_param,
++ u32 transfer_flag,
++ bool f_is_standard_dev_req,
++ u32 setup_vir_addr,
++ u32 setup_phy_addr,
++ u32 vir_buf_addr,
++ u32 phy_buf_addr,
++ u32 buf_size,
++ u32 start_frame,
++ u32 isoch_packet_num,
++ isoch_packet_desc_t *isoch_packet_desc,
++ void *td_priv,
++ unsigned int *return_td_addr)
++{
++ td_t *new_td_p = NULL;
++
++ int err = USB_ERR_SUCCESS;
++ if(create_td(&new_td_p)==USB_ERR_SUCCESS)
++ {
++ err = init_td( new_td_p,
++ parent_ed,
++ call_back_func,
++ call_back_param,
++ transfer_flag,
++ f_is_standard_dev_req,
++ setup_phy_addr,
++ setup_vir_addr,
++ vir_buf_addr,
++ phy_buf_addr,
++ buf_size,
++ start_frame,
++ isoch_packet_desc,
++ isoch_packet_num,
++ td_priv);
++
++ if(err !=USB_ERR_SUCCESS)
++ {
++ return USB_ERR_NOMEM;
++ }
++
++ if(parent_ed->is_need_to_insert_scheduler)
++ {
++ insert_ed_to_scheduler(parent_ed);
++ }
++
++ *return_td_addr = (u32)new_td_p;
++
++ return USB_ERR_SUCCESS;
++ }
++ else
++ {
++ return USB_ERR_NOMEM;
++ }
++}
++
++/******************************************************************************/
++/*!
++ * @name int cancel_transfer( ed_t *parent_ed,
++ * td_t *cancel_td)
++ *
++ * @brief this function cancels to transfer USB Transfer of cancel_td.
++ * this function firstly check whether this cancel_td is transferring or not
++ * if the cancel_td is transferring, the this function requests to cancel the USB Transfer
++ * to S3CScheduler. if the parent_ed is for Periodic Transfer, and
++ * there is not any td_t at parent_ed, then this function requests to release
++ * some usb resources for the ed_t to S3CScheduler. finally this function deletes the cancel_td.
++ *
++ * @param [IN] pUpdateTD = indicates the pointer ot the td_t to have STransfer to be updated.
++ *
++ * @return USB_ERR_SUCCESS - if success to update the STranfer of pUpdateTD.
++ * USB_ERR_FAIL - if fail to update the STranfer of pUpdateTD.
++ */
++ /******************************************************************************/
++int cancel_transfer(ed_t *parent_ed,
++ td_t *cancel_td)
++{
++ int err = USB_ERR_DEQUEUED;
++ otg_list_head *tmp_list_p, *tmp_list2_p;
++ bool cond_found = false;
++
++ if(parent_ed == NULL || cancel_td == NULL)
++ {
++ otg_dbg(OTG_DBG_TRANSFER, "parent_ed == NULL || cancel_td == NULL");
++ cancel_td->error_code = USB_ERR_NOELEMENT;
++ // otg_usbcore_giveback(cancel_td);
++ return cancel_td->error_code;
++ }
++
++ otg_list_for_each_safe(tmp_list_p, tmp_list2_p, &parent_ed->td_list_entry) {
++ if(&cancel_td->td_list_entry == tmp_list_p)
++ {
++ cond_found = true;
++ break;
++ }
++ }
++ if (cond_found != true)
++ {
++ otg_dbg(OTG_DBG_TRANSFER, "cond_found != true \n");
++ cancel_td->error_code = USB_ERR_NOELEMENT;
++ // otg_usbcore_giveback(cancel_td);
++ return cancel_td->error_code;
++ }
++
++
++ if(cancel_td->is_transferring)
++ {
++ if(!parent_ed->ed_status.is_in_transfer_ready_q)
++ {
++ err = cancel_to_transfer_td(cancel_td);
++
++ parent_ed->ed_status.in_transferring_td = 0;
++
++ if(err != USB_ERR_SUCCESS)
++ {
++ otg_dbg(OTG_DBG_TRANSFER, "cancel_to_transfer_td \n");
++ cancel_td->error_code = err;
++ // otg_usbcore_giveback(cancel_td);
++ goto ErrorStatus;
++ }
++
++ otg_list_pop(&cancel_td->td_list_entry);
++ parent_ed->num_td--;
++ }
++ }
++ else
++ {
++ otg_list_pop(&cancel_td->td_list_entry);
++ parent_ed->num_td--;
++
++ if(parent_ed->num_td==0)
++ {
++ remove_ed_from_scheduler(parent_ed);
++ }
++ }
++
++ if(parent_ed->num_td)
++ {
++ parent_ed->is_need_to_insert_scheduler = true;
++ insert_ed_to_scheduler(parent_ed);
++ }
++ else
++ {
++ if(parent_ed->ed_desc.endpoint_type == INT_TRANSFER ||
++ parent_ed->ed_desc.endpoint_type == ISOCH_TRANSFER)
++ {
++ //Release channel and usb bus resource for this ed_t.
++ //but, not release memory for this ed_t.
++ free_usb_resource_for_periodic(parent_ed->ed_desc.used_bus_time,
++ cancel_td->cur_stransfer.alloc_chnum,
++ cancel_td->parent_ed_p->ed_desc.endpoint_type);
++
++ parent_ed->ed_status.is_alloc_resource_for_ed =false;
++ }
++ }
++ // the caller of this functions should call otg_usbcore_giveback(cancel_td);
++ cancel_td->error_code = USB_ERR_DEQUEUED;
++ //otg_usbcore_giveback(cancel_td);
++ delete_td(cancel_td);
++
++ErrorStatus:
++
++ return err;
++
++
++}
++
++
++/******************************************************************************/
++/*!
++ * @name int cancel_all_td(ed_t *parent_ed)
++ *
++ * @brief this function cancels all Transfer which parent_ed manages.
++ *
++ * @param [IN] parent_ed = indicates the pointer ot the ed_t to manage TD_ts to be canceled.
++ *
++ * @return USB_ERR_SUCCESS - if success to cancel all TD_ts of pParentsED.
++ * USB_ERR_FAIL - if fail to cancel all TD_ts of pParentsED.
++ */
++ /******************************************************************************/
++int cancel_all_td(ed_t *parent_ed)
++{
++ otg_list_head *cancel_td_list_entry;
++ td_t *cancel_td;
++
++ do
++ {
++ cancel_td_list_entry = parent_ed->td_list_entry.next;
++
++ cancel_td = otg_list_get_node(cancel_td_list_entry,td_t, td_list_entry);
++
++ cancel_transfer(parent_ed, cancel_td);
++ } while(parent_ed->num_td);
++
++ return USB_ERR_SUCCESS;
++}
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c b/drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c
+new file mode 100644
+index 0000000..9e17dad
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c
+@@ -0,0 +1,147 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : NonPeriodicTransfer.c
++ * [Description] : This source file implements the functions to be defined at NonPeriodicTransfer Module.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/07
++ * [Revision History]
++ * (1) 2008/06/07 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements some functions of NonPeriodicTransfer.
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++
++#include "s3c-otg-transfer-transfer.h"
++
++/******************************************************************************/
++/*!
++ * @name int init_nonperio_stransfer( bool f_is_standard_dev_req,
++ * td_t *parent_td)
++ *
++ * @brief this function initiates the parent_td->cur_stransfer for NonPeriodic Transfer and
++ * inserts this init_td_p to init_td_p->parent_ed_p.
++ *
++ * @param [IN] f_is_standard_dev_req = indicates whether this transfer is Control or not.
++ * [IN] parent_td = indicates the address of td_t to be initiated.
++ *
++ * @return USB_ERR_SUCCESS - if success to update the STranfer of pUpdateTD.
++ * USB_ERR_FAIL - if fail to update the STranfer of pUpdateTD.
++ */
++ /******************************************************************************/
++int init_nonperio_stransfer(bool f_is_standard_dev_req,
++ td_t *parent_td)
++{
++
++
++ parent_td->cur_stransfer.ed_desc_p = &parent_td->parent_ed_p->ed_desc;
++ parent_td->cur_stransfer.ed_status_p = &parent_td->parent_ed_p->ed_status;
++ parent_td->cur_stransfer.alloc_chnum = CH_NONE;
++ parent_td->cur_stransfer.parent_td = (u32)parent_td;
++ parent_td->cur_stransfer.stransfer_id = (u32)&parent_td->cur_stransfer;
++
++ otg_mem_set(&(parent_td->cur_stransfer.hc_reg), 0, sizeof(hc_reg_t));
++
++ parent_td->cur_stransfer.hc_reg.hc_int_msk.b.chhltd = 1;
++
++ if(f_is_standard_dev_req)
++ {
++ parent_td->cur_stransfer.buf_size = USB_20_STAND_DEV_REQUEST_SIZE;
++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->standard_dev_req_info.phy_standard_dev_req_addr;
++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->standard_dev_req_info.vir_standard_dev_req_addr;
++ }
++ else
++ {
++ parent_td->cur_stransfer.buf_size = (parent_td->buf_size>MAX_CH_TRANSFER_SIZE)
++ ?MAX_CH_TRANSFER_SIZE
++ :parent_td->buf_size;
++
++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr;
++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr;
++ }
++
++ parent_td->cur_stransfer.packet_cnt = calc_packet_cnt(parent_td->cur_stransfer.buf_size
++ , parent_td->parent_ed_p->ed_desc.max_packet_size);
++
++ return USB_ERR_SUCCESS;
++}
++
++
++/******************************************************************************/
++/*!
++ * @name void update_nonperio_stransfer(td_t *parent_td)
++ *
++ * @brief this function updates the parent_td->cur_stransfer to be used by S3COCI.
++ *
++ * @param [IN/OUT]parent_td = indicates the pointer of td_t to store the STranser to be updated.
++ *
++ * @return USB_ERR_SUCCESS -if success to update the parent_td->cur_stransfer.
++ * USB_ERR_FAIL -if fail to update the parent_td->cur_stransfer.
++ */
++ /******************************************************************************/
++void update_nonperio_stransfer(td_t *parent_td)
++{
++ switch(parent_td->parent_ed_p->ed_desc.endpoint_type)
++ {
++ case BULK_TRANSFER:
++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr+parent_td->transferred_szie;
++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr+parent_td->transferred_szie;
++ parent_td->cur_stransfer.buf_size = ((parent_td->buf_size - parent_td->transferred_szie)>MAX_CH_TRANSFER_SIZE)
++ ?MAX_CH_TRANSFER_SIZE
++ :parent_td->buf_size - parent_td->transferred_szie;
++ break;
++
++ case CONTROL_TRANSFER:
++ if(parent_td->standard_dev_req_info.conrol_transfer_stage == SETUP_STAGE)
++ {
++ // but, this case will not be occured......
++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->standard_dev_req_info.phy_standard_dev_req_addr;
++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->standard_dev_req_info.vir_standard_dev_req_addr;
++ parent_td->cur_stransfer.buf_size = 8;
++ }
++ else if(parent_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr+parent_td->transferred_szie;
++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr+parent_td->transferred_szie;
++ parent_td->cur_stransfer.buf_size = ((parent_td->buf_size - parent_td->transferred_szie)>MAX_CH_TRANSFER_SIZE)
++ ?MAX_CH_TRANSFER_SIZE
++ :parent_td->buf_size - parent_td->transferred_szie;
++ }
++ else
++ {
++ parent_td->cur_stransfer.start_phy_buf_addr = 0;
++ parent_td->cur_stransfer.start_vir_buf_addr = 0;
++ parent_td->cur_stransfer.buf_size = 0;
++ }
++ break;
++
++
++ default:
++ break;
++ }
++
++ parent_td->cur_stransfer.packet_cnt = calc_packet_cnt(parent_td->cur_stransfer.buf_size, parent_td->parent_ed_p->ed_desc.max_packet_size);
++
++}
++
++
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c b/drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c
+new file mode 100644
+index 0000000..7bc6ed3
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c
+@@ -0,0 +1,131 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : NonPeriodicTransfer.c
++ * [Description] : This source file implements the functions to be defined at NonPeriodicTransfer Module.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/09
++ * [Revision History]
++ * (1) 2008/06/09 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements some functions of PeriodicTransfer.
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-transfer-transfer.h"
++
++
++/******************************************************************************/
++/*!
++ * @name int init_perio_stransfer( bool f_is_isoch_transfer,
++ * td_t *parent_td)
++ *
++ * @brief this function initiates the parent_td->cur_stransfer for Periodic Transfer and
++ * inserts this init_td_p to init_td_p->parent_ed_p.
++ *
++ * @param [IN] f_is_isoch_transfer = indicates whether this transfer is Isochronous or not.
++ * [IN] parent_td = indicates the address of td_t to be initiated.
++ *
++ * @return USB_ERR_SUCCESS -if success to update the STranfer of pUpdateTD.
++ * USB_ERR_FAIL -if fail to update the STranfer of pUpdateTD.
++ */
++ /******************************************************************************/
++int init_perio_stransfer( bool f_is_isoch_transfer,
++ td_t *parent_td)
++{
++ parent_td->cur_stransfer.ed_desc_p = &parent_td->parent_ed_p->ed_desc;
++ parent_td->cur_stransfer.ed_status_p = &parent_td->parent_ed_p->ed_status;
++ parent_td->cur_stransfer.alloc_chnum = CH_NONE;
++ parent_td->cur_stransfer.parent_td = (u32)parent_td;
++ parent_td->cur_stransfer.stransfer_id = (u32)&parent_td->cur_stransfer;
++
++ otg_mem_set(&parent_td->cur_stransfer.hc_reg, 0, sizeof(hc_reg_t));
++
++ parent_td->cur_stransfer.hc_reg.hc_int_msk.b.chhltd = 1;
++
++ if(f_is_isoch_transfer)
++ {
++ // initiates the STransfer usinb the IsochPacketDesc[0].
++ parent_td->cur_stransfer.buf_size =parent_td->isoch_packet_desc_p[0].buf_size;
++ parent_td->cur_stransfer.start_phy_buf_addr =parent_td->phy_buf_addr + parent_td->isoch_packet_desc_p[0].isoch_packiet_start_addr;
++ parent_td->cur_stransfer.start_vir_buf_addr =parent_td->vir_buf_addr + parent_td->isoch_packet_desc_p[0].isoch_packiet_start_addr;
++ }
++ else
++ {
++ parent_td->cur_stransfer.buf_size =(parent_td->buf_size>MAX_CH_TRANSFER_SIZE)
++ ?MAX_CH_TRANSFER_SIZE
++ :parent_td->buf_size;
++
++ parent_td->cur_stransfer.start_phy_buf_addr =parent_td->phy_buf_addr;
++ parent_td->cur_stransfer.start_vir_buf_addr =parent_td->vir_buf_addr;
++ }
++
++ parent_td->cur_stransfer.packet_cnt = calc_packet_cnt(parent_td->cur_stransfer.buf_size, parent_td->parent_ed_p->ed_desc.max_packet_size);
++
++ return USB_ERR_SUCCESS;
++}
++
++
++/******************************************************************************/
++/*!
++ * @name void update_perio_stransfer(td_t *parent_td)
++ *
++ * @brief this function updates the parent_td->cur_stransfer to be used by S3COCI.
++ * the STransfer of parent_td is for Periodic Transfer.
++ *
++ * @param [IN/OUT]parent_td = indicates the pointer of td_t to store the STranser to be updated.
++ *
++ * @return USB_ERR_SUCCESS -if success to update the parent_td->cur_stransfer.
++ * USB_ERR_FAIL -if fail to update the parent_td->cur_stransfer.
++ */
++ /******************************************************************************/
++void update_perio_stransfer(td_t *parent_td)
++{
++
++ switch(parent_td->parent_ed_p->ed_desc.endpoint_type)
++ {
++ case INT_TRANSFER:
++ parent_td->cur_stransfer.start_phy_buf_addr =parent_td->phy_buf_addr+parent_td->transferred_szie;
++ parent_td->cur_stransfer.start_vir_buf_addr =parent_td->vir_buf_addr+parent_td->transferred_szie;
++ parent_td->cur_stransfer.buf_size =(parent_td->buf_size>MAX_CH_TRANSFER_SIZE)
++ ?MAX_CH_TRANSFER_SIZE
++ :parent_td->buf_size;
++ break;
++
++ case ISOCH_TRANSFER:
++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr
++ +parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].isoch_packiet_start_addr
++ +parent_td->isoch_packet_position;
++
++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr
++ +parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].isoch_packiet_start_addr
++ +parent_td->isoch_packet_position;
++
++ parent_td->cur_stransfer.buf_size = (parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].buf_size - parent_td->isoch_packet_position)>MAX_CH_TRANSFER_SIZE
++ ?MAX_CH_TRANSFER_SIZE
++ :parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].buf_size - parent_td->isoch_packet_position;
++
++ break;
++
++ default:
++ break;
++ }
++}
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h b/drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h
+new file mode 100644
+index 0000000..07f4d0b
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h
+@@ -0,0 +1,147 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : s3c-otg-transfer-transfer.h
++ * [Description] : The Header file defines the external and internal functions of Transfer.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/03
++ * [Revision History]
++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines functions of Transfer
++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n
++ * : Optimizing for performance \n
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _TRANSFER_H
++#define _TRANSFER_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++//#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-hcdi-memory.h"
++#include "s3c-otg-hcdi-kal.h"
++#include "s3c-otg-hcdi-debug.h"
++
++#include "s3c-otg-scheduler-scheduler.h"
++#include "s3c-otg-isr.h"
++
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++// the header pointer to indicate the ED_list to manage the ed_t to be created and initiated.
++extern otg_list_head ed_list_head;
++extern u32 ref_periodic_transfer;
++
++
++void init_transfer(void);
++void deinit_transfer(void);
++
++int issue_transfer(ed_t *parent_ed,
++ void *call_back_func,
++ void *call_back_param,
++ u32 transfer_flag,
++ bool f_is_standard_dev_req,
++ u32 setup_vir_addr,
++ u32 setup_phy_addr,
++ u32 vir_buf_addr,
++ u32 phy_buf_addr,
++ u32 buf_size,
++ u32 start_frame,
++ u32 isoch_packet_num,
++ isoch_packet_desc_t *isoch_packet_desc,
++ void *td_priv,
++ unsigned int *return_td_addr);
++
++int cancel_transfer(ed_t *parent_ed,
++ td_t *cancel_td);
++
++int cancel_all_td(ed_t *parent_ed);
++
++int create_ed(ed_t ** new_ed);
++
++int init_ed(ed_t * init_ed,
++ u8 dev_addr,
++ u8 ep_num,
++ bool f_is_ep_in,
++ u8 dev_speed,
++ u8 ep_type,
++ u16 max_packet_size,
++ u8 multi_count,
++ u8 interval,
++ u32 sched_frame,
++ u8 hub_addr,
++ u8 hub_port,
++ bool f_is_do_split,
++ void *ep);
++
++int delete_ed(ed_t *delete_ed);
++
++int delete_td(td_t * delete_td);
++
++int create_isoch_packet_desc( isoch_packet_desc_t **new_isoch_packet_desc,
++ u32 isoch_packet_num);
++
++int delete_isoch_packet_desc( isoch_packet_desc_t *del_isoch_packet_desc,
++ u32 isoch_packet_num);
++
++
++void init_isoch_packet_desc( isoch_packet_desc_t *init_isoch_packet_desc,
++ u32 offset,
++ u32 isoch_packet_size,
++ u32 index);
++
++// NonPeriodicTransfer.c implements.
++
++int init_nonperio_stransfer(bool f_is_standard_dev_req,
++ td_t *parent_td);
++
++void update_nonperio_stransfer(td_t *parent_td);
++
++//PeriodicTransfer.c implements
++
++int init_perio_stransfer( bool f_is_isoch_transfer,
++ td_t *parent_td);
++
++void update_perio_stransfer(td_t *parent_td);
++
++static inline u32 calc_packet_cnt(u32 data_size, u16 max_packet_size)
++{
++ if(data_size != 0)
++ {
++ return (data_size%max_packet_size==0)?data_size/max_packet_size:data_size/max_packet_size+1;
++ }
++ return 1;
++}
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c
+new file mode 100644
+index 0000000..5f0a993
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c
+@@ -0,0 +1,673 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : BulkTransferChecker.c
++ * [Description] : The Source file implements the external and internal functions of BulkTransferChecker.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/13
++ * [Revision History]
++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements functions of BulkTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-transferchecker-bulk.h"
++#include "s3c-otg-isr.h"
++
++/******************************************************************************/
++/*!
++ * @name u8 process_bulk_transfer(td_t *result_td,
++ hc_info_t *hc_reg_data)
++
++ *
++ * @brief this function processes the result of the Bulk Transfer.
++ * firstly, this function checks the result of the Bulk Transfer.
++ * and according to the result, calls the sub-functions to process the result.
++ *
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t whose channel is interruped.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if need to retransmit the result_td.
++ * RE_SCHEDULE -if need to reschedule the result_td.
++ * DE_ALLOCATE -if USB Transfer is completed.
++ * NO_ACTION -if we don't need any action,
++ */
++/******************************************************************************/
++u8 process_bulk_transfer(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ hcintn_t hc_intr_info;
++ u8 return_val=0;
++
++ //we just deal with the interrupts to be unmasked.
++ hc_intr_info.d32 = hc_reg_data->hc_int.d32 & result_td->cur_stransfer.hc_reg.hc_int_msk.d32;
++
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ if(hc_intr_info.b.chhltd)
++ {
++ return_val = process_chhltd_on_bulk(result_td, hc_reg_data);
++ }
++
++ else if (hc_intr_info.b.ack)
++ {
++ return_val =process_ack_on_bulk(result_td, hc_reg_data);
++ }
++
++ else if (hc_intr_info.b.nak)
++ {
++ return_val =process_nak_on_bulk(result_td, hc_reg_data);
++ }
++
++ else if (hc_intr_info.b.datatglerr)
++ {
++ return_val = process_datatgl_on_bulk(result_td,hc_reg_data);
++ }
++ }
++ else
++ {
++ if(hc_intr_info.b.chhltd)
++ {
++ return_val = process_chhltd_on_bulk(result_td, hc_reg_data);
++
++ }
++
++ else if(hc_intr_info.b.ack)
++ {
++ return_val =process_ack_on_bulk( result_td, hc_reg_data);
++ }
++ }
++
++ return return_val;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_chhltd_on_bulk(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function processes Channel Halt event according to Synopsys OTG Spec.
++ * firstly, this function checks the reason of the Channel Halt, and according to the reason,
++ * calls the sub-functions to process the result.
++ *
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if need to retransmit the result_td.
++ * RE_SCHEDULE -if need to reschedule the result_td.
++ * DE_ALLOCATE -if USB Transfer is completed.
++ */
++/******************************************************************************/
++u8 process_chhltd_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ if(hc_reg_data->hc_int.b.xfercompl)
++ {
++ return process_xfercompl_on_bulk( result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.stall)
++ {
++ return process_stall_on_bulk(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.bblerr)
++ {
++ return process_bblerr_on_bulk(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.xacterr)
++ {
++ return process_xacterr_on_bulk(result_td, hc_reg_data);
++ }
++ else
++ {
++ //Occure Error State.....
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->err_cnt++;
++ if(result_td->err_cnt == 3)
++ {
++ result_td->error_code = USB_ERR_STATUS_XACTERR;
++ result_td->err_cnt = 0;
++ return DE_ALLOCATE;
++ }
++
++ return RE_TRANSMIT;
++ }
++ }
++ else
++ {
++ if(hc_reg_data->hc_int.b.xfercompl)
++ {
++ return process_xfercompl_on_bulk(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.stall)
++ {
++ return process_stall_on_bulk(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.xacterr)
++ {
++ return process_xacterr_on_bulk(result_td, hc_reg_data);
++ }
++
++ else if(hc_reg_data->hc_int.b.nak)
++ {
++ return process_nak_on_bulk(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.nyet)
++ {
++ return process_nyet_on_bulk(result_td, hc_reg_data);
++ }
++ else
++ {
++ //occur error state...
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->err_cnt++;
++ if(result_td->err_cnt == 3)
++ {
++ result_td->error_code = USB_ERR_STATUS_XACTERR;
++ result_td->err_cnt = 0;
++ return DE_ALLOCATE;
++ }
++
++ return RE_TRANSMIT;
++ }
++
++
++
++ }
++ return USB_ERR_SUCCESS;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_xfercompl_on_bulk( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the xfercompl event according to Synopsys OTG Spec.
++ * the procedure of this function is as following
++ * 1. clears all bits of the channel' HCINT by using clear_ch_intr() of S3CIsr.
++ * 2. masks some bit of HCINTMSK
++ * 3. updates the result_td fields
++ * err_cnt/u8/standard_dev_req_info.
++ * 4. updates the result_td->parent_ed_p->ed_status.
++ * BulkDataTgl.
++ * 5. calculates the tranferred size by calling calc_transferred_size() on DATA_STAGE.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return USB_ERR_SUCCESS
++ */
++/******************************************************************************/
++u8 process_xfercompl_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ u8 ret_val=0;
++
++ result_td->err_cnt = 0;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable =false;
++
++ result_td->transferred_szie += calc_transferred_size(true,result_td, hc_reg_data);
++
++ if(result_td->transferred_szie==result_td->buf_size)
++ {//at IN Transfer, short transfer is accepted.
++ result_td->error_code = USB_ERR_STATUS_COMPLETE;
++ ret_val = DE_ALLOCATE;
++ }
++ else
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in&& hc_reg_data->hc_size.b.xfersize)
++ {
++ if(result_td->transfer_flag&USB_TRANS_FLAG_NOT_SHORT)
++ {
++ result_td->error_code =USB_ERR_STATUS_SHORTREAD;
++ }
++ else
++ {
++ result_td->error_code =USB_ERR_STATUS_COMPLETE;
++ }
++ ret_val = DE_ALLOCATE;
++ }
++ else
++ {
++ ret_val = RE_SCHEDULE;
++ }
++ }
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ if(hc_reg_data->hc_int.b.nyet)
++ {
++ //at OUT Transfer, we must re-transmit.
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++ }
++ }
++
++ return ret_val;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_ahb_on_bulk(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with theAHB Errorl event according to Synopsys OTG Spec.
++ * this function stop the channel to be executed
++ * TBD....
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return USB_ERR_SUCCESS
++ */
++/******************************************************************************/
++u8 process_ahb_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt =0;
++ result_td->error_code =USB_ERR_STATUS_AHBERR;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_AHBErr);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ // we just calculate the size of the transferred data on Data Stage of Bulk Transfer.
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++
++ return DE_ALLOCATE;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_stall_on_bulk(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with theStall event according to Synopsys OTG Spec.
++ * when Stall is occured at Bulk Transfer, we should reset the PID as DATA0
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ */
++/******************************************************************************/
++u8 process_stall_on_bulk( td_t * result_td,
++ hc_info_t * hc_reg_data)
++{
++ result_td->err_cnt =0;
++ result_td->error_code =USB_ERR_STATUS_STALL;
++
++ //this channel is stalled, So we don't process another interrupts.
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ update_datatgl(DATA0, result_td);
++
++
++ return DE_ALLOCATE;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_nak_on_bulk(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the nak event according to Synopsys OTG Spec.
++ * nak is occured at OUT/IN Transaction of Data/Status Stage, and is not occured at Setup Stage.
++ * If nak is occured at IN Transaction, this function processes this interrupt as following.
++ * 1. resets the result_td->err_cnt.
++ * 2. masks ack/nak/DaaTglErr bit of HCINTMSK.
++ * 3. clears the nak bit of HCINT
++ * 4. be careful, nak of IN Transaction don't require re-transmit.
++ * If nak is occured at OUT Transaction, this function processes this interrupt as following.
++ * 1. all procedures of IN Transaction are executed.
++ * 2. calculates the size of the transferred data.
++ * 3. if the speed of USB Device is High-Speed, sets the ping protocol.
++ * 4. update the Toggle
++ * at OUT Transaction, this function check whether the speed of USB Device is High-Speed or not.
++ * if USB Device is High-Speed, then
++ * this function sets the ping protocol.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_SCHEDULE -if the direction of the Transfer is OUT
++ * NO_ACTION -if the direction of the Transfer is IN
++ */
++/******************************************************************************/
++u8 process_nak_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++
++ //at OUT Transfer, we must re-transmit.
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ return RE_TRANSMIT;
++ }
++ return NO_ACTION;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_ack_on_bulk(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the ack event according to Synopsys OTG Spec.
++ * ack of IN/OUT Transaction don't need any retransmit.
++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK.
++ * finally, this function clears ack bit of HCINT and ed_status.is_ping_enable.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return USB_ERR_SUCCESS
++ */
++/******************************************************************************/
++u8 process_ack_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++
++ return NO_ACTION;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_nyet_on_bulk(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the nyet event according to Synopsys OTG Spec.
++ * nyet is only occured at OUT Transaction.
++ * If nyet is occured at OUT Transaction, this function processes this interrupt as following.
++ * 1. resets the result_td->err_cnt.
++ * 2. masks ack/nak/datatglerr bit of HCINTMSK.
++ * 3. clears the nyet bit of HCINT
++ * 4. calculates the size of the transferred data.
++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol.
++ * 6. update the Data Toggle.
++ * 7. return RE_SCHEDULE to retransmit.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_SCHEDULE
++ */
++/******************************************************************************/
++u8 process_nyet_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ // Error State....
++ return NO_ACTION;
++ }
++
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NYET);
++
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ return RE_TRANSMIT;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_xacterr_on_bulk( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the xacterr event according to Synopsys OTG Spec.
++ * xacterr is occured at OUT/IN Transaction and we should retransmit the USB Transfer
++ * if the Error Counter is less than the RETRANSMIT_THRESHOLD.
++ * the reasons of xacterr is Timeout/CRC error/false EOP.
++ * the procedure to process xacterr is as following.
++ * 1. increses the result_td->err_cnt
++ * 2. check whether the result_td->err_cnt is equal to 3.
++ * 2. unmasks ack/nak/datatglerr bit of HCINTMSK.
++ * 3. clears the xacterr bit of HCINT
++ * 4. calculates the size of the transferred data.
++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol.
++ * 6. update the Data Toggle.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if the error count is less than 3
++ * DE_ALLOCATE -if the error count is equal to 3
++ */
++/******************************************************************************/
++u8 process_xacterr_on_bulk( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ u8 ret_val = 0;
++
++ if(result_td->err_cnt<RETRANSMIT_THRESHOLD)
++ {
++ result_td->cur_stransfer.hc_reg.hc_int_msk.d32 |= (CH_STATUS_ACK+CH_STATUS_NAK+CH_STATUS_DataTglErr);
++ ret_val = RE_TRANSMIT;
++ result_td->err_cnt++ ;
++ }
++ else
++ {
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ ret_val = DE_ALLOCATE;
++ result_td->err_cnt = 0 ;
++ result_td->error_code = USB_ERR_STATUS_XACTERR;
++ }
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++ }
++
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ return ret_val;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name void process_bblerr_on_bulk(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the Babble event according to Synopsys OTG Spec.
++ * babble error is occured when the buffer to receive data to be transmit is overflow.
++ * So, babble error can be just occured at IN Transaction.
++ * when Babble Error is occured, we should stop the USB Transfer, and return the fact
++ * to Application.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ */
++/******************************************************************************/
++u8 process_bblerr_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++
++ if(!result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ return NO_ACTION;
++ }
++
++ result_td->err_cnt =0;
++ result_td->error_code =USB_ERR_STATUS_BBLERR;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable =false;
++ result_td->transferred_szie += calc_transferred_size(false, result_td, hc_reg_data);
++
++ return DE_ALLOCATE;
++
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_datatgl_on_bulk( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the datatglerr event according to Synopsys OTG Spec.
++ * the datatglerr event is occured at IN Transfer, and the channel is not halted.
++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK.
++ * finally, this function clears datatglerr bit of HCINT.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return NO_ACTION
++ */
++/******************************************************************************/
++u8 process_datatgl_on_bulk(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ return NO_ACTION;
++
++}
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h
+new file mode 100644
+index 0000000..f1f8593
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h
+@@ -0,0 +1,88 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : BulkTransferChecker.h
++ * [Description] : The Header file defines the external and internal functions of BulkTransferChecker
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/18
++ * [Revision History]
++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines functions of BulkTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _BULK_TRANSFER_CHECKER_H
++#define _BULK_TRANSFER_CHECKER_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-datastruct.h"
++
++
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++u8 process_bulk_transfer(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_xfercompl_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_chhltd_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_ahb_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_stall_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_nak_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_ack_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_nyet_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_xacterr_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_bblerr_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_datatgl_on_bulk(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h
+new file mode 100644
+index 0000000..8026fc6
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h
+@@ -0,0 +1,66 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : DoneTransferChecker.h
++ * [Description] : The Header file defines the external and internal functions of S3CDoneTransferChecker.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/12
++ * [Revision History]
++ * (1) 2008/06/12 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines functions of S3CDoneTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _DONE_TRANSFER_CHECKER_H
++#define _DONE_TRANSFER_CHECKER_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-datastruct.h"
++
++#include "s3c-otg-hcdi-debug.h"
++
++
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
++
++
++
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c
+new file mode 100644
+index 0000000..86d96de
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c
+@@ -0,0 +1,256 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : CommonTransferChecker.c
++ * [Description] : The Source file implements the external and internal functions of CommonTransferChecker.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2009/01/12
++ * [Revision History]
++ * (1) 2008/06/12 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements functions of CommonTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-transferchecker-common.h"
++
++
++/******************************************************************************/
++/*!
++ * @name int init_done_transfer_checker(void)
++ *
++ * @brief this function initiates S3CDoneTransferChecker Module.
++ *
++ *
++ * @param void
++ *
++ * @return void
++ */
++/******************************************************************************/
++//ss1
++/*void init_done_transfer_checker(void)
++{
++ return USB_ERR_SUCCESS;
++}*/
++
++/******************************************************************************/
++/*!
++ * @name void do_transfer_checker(void)
++ *
++ * @brief this function processes the result of USB Transfer. So, do_transfer_checker fistly
++ * check which channel occurs OTG Interrupt and gets the status information of the channel.
++ * do_transfer_checker requests the information of td_t to S3CScheduler.
++ * To process the interrupt of the channel, do_transfer_checker calls the sub-modules of
++ * S3CDoneTransferChecker, for example, ControlTransferChecker, BulkTransferChecker.
++ * according to the process result of the channel interrupt, do_transfer_checker decides
++ * the USB Transfer will be done or retransmitted.
++ *
++ *
++ * @param void
++ *
++ * @return void
++ */
++/*******************************************************************************/
++void do_transfer_checker (void)
++{
++ u32 hc_intr = 0;
++ u32 hc_intr_msk = 0;
++ u8 do_try_cnt = 0;
++
++ hc_info_t ch_info;
++ u32 td_addr = 0;
++ td_t *done_td = {0};
++ u8 proc_result = 0;
++
++ //by ss1
++ otg_mem_set((void *)&ch_info, 0, sizeof(hc_info_t));
++
++ // Get value of HAINT...
++ get_intr_ch(&hc_intr,&hc_intr_msk);
++
++start_do_transfer_checker:
++
++ while(do_try_cnt<MAX_CH_NUMBER)
++ {
++ //checks the channel number to be masked or not.
++ if(!(hc_intr & hc_intr_msk & (1<<do_try_cnt)))
++ {
++ do_try_cnt++;
++ goto start_do_transfer_checker;
++ }
++
++ //Gets the address of the td_t to have the channel to be interrupted.
++ get_td_info(do_try_cnt, &td_addr);
++
++ done_td = (td_t *)td_addr;
++
++ if(do_try_cnt != done_td->cur_stransfer.alloc_chnum)
++ {
++ do_try_cnt++;
++ goto start_do_transfer_checker;
++ }
++
++ //Gets the informationof channel to be interrupted.
++ get_ch_info(&ch_info,do_try_cnt);
++
++ switch(done_td->parent_ed_p->ed_desc.endpoint_type)
++ {
++ case CONTROL_TRANSFER:
++ proc_result = process_control_transfer(done_td, &ch_info);
++ break;
++ case BULK_TRANSFER:
++ proc_result = process_bulk_transfer(done_td, &ch_info);
++ break;
++ case INT_TRANSFER:
++ proc_result = process_intr_transfer(done_td, &ch_info);
++ break;
++ case ISOCH_TRANSFER:
++ // proc_result = ProcessIsochTransfer(done_td, &ch_info);
++ break;
++ default:break;
++ }
++
++ if((proc_result == RE_TRANSMIT) || (proc_result == RE_SCHEDULE))
++ {
++ done_td->parent_ed_p->ed_status.is_in_transferring = false;
++ done_td->is_transfer_done = false;
++ done_td->is_transferring = false;
++
++ if(done_td->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER ||
++ done_td->parent_ed_p->ed_desc.endpoint_type==BULK_TRANSFER)
++ {
++ update_nonperio_stransfer(done_td);
++ }
++ else
++ {
++ update_perio_stransfer(done_td);
++ }
++
++ if(proc_result == RE_TRANSMIT)
++ {
++ retransmit(done_td);
++ }
++ else
++ {
++ reschedule(done_td);
++ }
++ }
++
++ else if(proc_result==DE_ALLOCATE)
++ {
++ done_td->parent_ed_p->ed_status.is_in_transferring = false;
++ done_td->parent_ed_p->ed_status.in_transferring_td = 0;
++ done_td->is_transfer_done = true;
++ done_td->is_transferring = false;
++
++ otg_usbcore_giveback( done_td);
++ release_trans_resource(done_td);
++ }
++
++ else
++ { //NO_ACTION....
++ done_td->parent_ed_p->ed_status.is_in_transferring = true;
++ done_td->parent_ed_p->ed_status.in_transferring_td = (u32)done_td;
++ done_td->is_transfer_done = false;
++ done_td->is_transferring = true;
++ }
++ do_try_cnt++;
++ }
++ // Complete to process the Channel Interrupt.
++ // So. we now start to scheduler of S3CScheduler.
++ do_schedule();
++
++}
++
++
++int release_trans_resource(td_t * done_td)
++{
++ //remove the pDeallocateTD from parent_ed_p.
++ otg_list_pop(&done_td->td_list_entry);
++ done_td->parent_ed_p->num_td--;
++
++ //Call deallocate to release the channel and bandwidth resource of S3CScheduler.
++ deallocate(done_td);
++ delete_td(done_td);
++ return USB_ERR_SUCCESS;
++}
++
++u32 calc_transferred_size(bool f_is_complete,
++ td_t *td,
++ hc_info_t *hc_info)
++{
++ if(f_is_complete)
++ {
++ if(td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ return td->cur_stransfer.buf_size - hc_info->hc_size.b.xfersize;
++ }
++ else
++ {
++ return td->cur_stransfer.buf_size;
++ }
++ }
++ else
++ {
++ return (td->cur_stransfer.packet_cnt - hc_info->hc_size.b.pktcnt)*td->parent_ed_p->ed_desc.max_packet_size;
++ }
++
++}
++
++void update_frame_number(td_t *pResultTD)
++{
++ u32 cur_frame_num=0;
++
++ if(pResultTD->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER ||
++ pResultTD->parent_ed_p->ed_desc.endpoint_type == BULK_TRANSFER)
++ {
++ return;
++ }
++
++ pResultTD->parent_ed_p->ed_desc.sched_frame+= pResultTD->parent_ed_p->ed_desc.interval;
++ pResultTD->parent_ed_p->ed_desc.sched_frame &= HFNUM_MAX_FRNUM;
++
++ cur_frame_num = oci_get_frame_num();
++ if(((cur_frame_num - pResultTD->parent_ed_p->ed_desc.sched_frame)&HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM>>1))
++ {
++ pResultTD->parent_ed_p->ed_desc.sched_frame = cur_frame_num;
++ }
++}
++
++void update_datatgl(u8 ubCurDataTgl,
++ td_t *td)
++{
++ switch(td->parent_ed_p->ed_desc.endpoint_type)
++ {
++ case CONTROL_TRANSFER:
++ if(td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ td->parent_ed_p->ed_status.control_data_tgl.data_tgl = ubCurDataTgl;
++ }
++ break;
++ case BULK_TRANSFER:
++ case INT_TRANSFER:
++ td->parent_ed_p->ed_status.data_tgl =ubCurDataTgl;
++ break;
++
++ case ISOCH_TRANSFER:
++ break;
++ default:break;
++ }
++}
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h
+new file mode 100644
+index 0000000..3b9822e
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h
+@@ -0,0 +1,79 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : CommonTransferChecker.h
++ * [Description] : The Header file defines the external and internal functions of CommonTransferChecker.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/12
++ * [Revision History]
++ * (1) 2008/06/12 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines functions of CommonTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _COMMON_TRANSFER_CHECKER_H
++#define _COMMON_TRANSFER_CHECKER_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++
++#include "s3c-otg-common-common.h"
++//#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-common-regdef.h"
++#include "s3c-otg-transfer-transfer.h"
++
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-hcdi-memory.h"
++#include "s3c-otg-scheduler-scheduler.h"
++#include "s3c-otg-isr.h"
++#include "s3c-otg-transferchecker-control.h"
++#include "s3c-otg-transferchecker-bulk.h"
++#include "s3c-otg-transferchecker-interrupt.h"
++//#include "s3c-otg-transferchecker-iso.h"
++
++
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++//void init_done_transfer_checker (void);
++void do_transfer_checker (void);
++int release_trans_resource(td_t *done_td);
++u32 calc_transferred_size(bool f_is_complete,
++ td_t *td,
++ hc_info_t *hc_info);
++void update_frame_number(td_t *result_td);
++void update_datatgl(u8 cur_data_tgl,
++ td_t *td);
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c
+new file mode 100644
+index 0000000..bd7f54f
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c
+@@ -0,0 +1,791 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : ControlTransferChecker.c
++ * [Description] : The Source file implements the external and internal functions of ControlTransferChecker.
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2009/01/12
++ * [Revision History]
++ * (1) 2008/06/13 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements functions of ControlTransferChecker
++ * (2) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Completed to implement ControlTransferChecker.c v1.0
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#include "s3c-otg-transferchecker-control.h"
++#include "s3c-otg-isr.h"
++
++
++
++/******************************************************************************/
++/*!
++ * @name u8 process_control_transfer(td_t *result_td,
++ hc_info_t *hc_reg_data)
++
++ *
++ * @brief this function processes the result of the Control Transfer.
++ * firstly, this function checks the result the Control Transfer.
++ * and according to the result, calls the sub-functions to process the result.
++ *
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] ubChNum -indicates the number of the channel to be interrupted.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if need to retransmit the result_td.
++ * RE_SCHEDULE -if need to reschedule the result_td.
++ * DE_ALLOCATE -if USB Transfer is completed.
++ */
++/******************************************************************************/
++u8 process_control_transfer(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ hcintn_t hcintr_info;
++ u8 ret_val=0;
++
++ //we just deal with the interrupts to be unmasked.
++ hcintr_info.d32 = hc_reg_data->hc_int.d32&result_td->cur_stransfer.hc_reg.hc_int_msk.d32;
++
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ if(hcintr_info.b.chhltd)
++ {
++ ret_val = process_chhltd_on_control(result_td, hc_reg_data);
++ }
++
++ else if (hcintr_info.b.ack)
++ {
++ ret_val =process_ack_on_control(result_td, hc_reg_data);
++ }
++
++ else if (hcintr_info.b.nak)
++ {
++ ret_val =process_nak_on_control(result_td, hc_reg_data);
++ }
++
++ else if (hcintr_info.b.datatglerr)
++ {
++ ret_val = process_datatgl_on_control(result_td,hc_reg_data);
++ }
++ }
++ else
++ {
++ if(hcintr_info.b.chhltd)
++ {
++ ret_val = process_chhltd_on_control(result_td, hc_reg_data);
++ }
++
++ else if(hcintr_info.b.ack)
++ {
++ ret_val =process_ack_on_control( result_td, hc_reg_data);
++
++ }
++ }
++
++ return ret_val;
++}
++
++
++u8 process_indirection_on_control( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ if(hc_reg_data->hc_int.b.xfercompl)
++ {
++ return process_xfercompl_on_control( result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.stall)
++ {
++ return process_stall_on_control(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.bblerr)
++ {
++ return process_bblerr_on_control(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.xacterr)
++ {
++ return process_xacterr_on_control(result_td, hc_reg_data);
++ }
++ else
++ {
++
++ //Occure Error State.....
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ result_td->err_cnt++;
++ if(result_td->err_cnt == 3)
++ {
++ result_td->error_code = USB_ERR_STATUS_XACTERR;
++ result_td->err_cnt = 0;
++ return DE_ALLOCATE;
++ }
++ return RE_TRANSMIT;
++ }
++}
++u8 process_outdirection_on_control(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ if(hc_reg_data->hc_int.b.xfercompl)
++ {
++ return process_xfercompl_on_control(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.stall)
++ {
++ return process_stall_on_control(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.nak)
++ {
++ return process_nak_on_control(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.xacterr)
++ {
++ return process_xacterr_on_control(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.nyet)
++ {
++ return process_nyet_on_control(result_td, hc_reg_data);
++ }
++ else
++ {
++ //occur error state...
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->err_cnt++;
++ if(result_td->err_cnt == 3)
++ {
++ result_td->error_code = USB_ERR_STATUS_XACTERR;
++ result_td->err_cnt = 0;
++ return DE_ALLOCATE;
++ }
++
++ return RE_TRANSMIT;
++ }
++}
++
++/********************************************************************************
++ * @name u8 process_chhltd_on_control( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function processes Channel Halt event according to Synopsys OTG Spec.
++ * firstly, this function checks the reason of the Channel Halt, and according to the reason,
++ * calls the sub-functions to process the result.
++ *
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if need to retransmit the result_td.
++ * RE_SCHEDULE -if need to reschedule the result_td.
++ * DE_ALLOCATE -if USB Transfer is completed.
++ */
++/******************************************************************************/
++u8 process_chhltd_on_control( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == SETUP_STAGE)
++ {
++ return process_outdirection_on_control(result_td, hc_reg_data);
++ }
++ else if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ return process_indirection_on_control(result_td, hc_reg_data);
++ }
++ else
++ {
++ return process_outdirection_on_control(result_td, hc_reg_data);
++ }
++ }
++ else
++ {
++ if(result_td->standard_dev_req_info.is_data_stage == true)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ return process_outdirection_on_control(result_td, hc_reg_data);
++ }
++ else
++ {
++ return process_indirection_on_control(result_td, hc_reg_data);
++ }
++ }
++ else
++ {
++ return process_indirection_on_control(result_td, hc_reg_data);
++ }
++ }
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_xfercompl_on_control(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the xfercompl event according to Synopsys OTG Spec.
++ * the procedure of this function is as following
++ * 1. clears all bits of the channel' HCINT by using clear_ch_intr() of S3CIsr.
++ * 2. masks some bit of HCINTMSK
++ * 3. updates the result_td fields
++ * err_cnt/u8/standard_dev_req_info.
++ * 4. updates the result_td->parent_ed_p->ed_status.
++ * control_data_tgl.
++ * 5. calculates the tranferred size by calling calc_transferred_size() on DATA_STAGE.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return USB_ERR_SUCCESS
++ */
++/******************************************************************************/
++u8 process_xfercompl_on_control(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ u8 ret_val = 0;
++
++ result_td->err_cnt = 0;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum,CH_STATUS_ALL);
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable =false;
++
++ switch(result_td->standard_dev_req_info.conrol_transfer_stage)
++ {
++ case SETUP_STAGE:
++ if(result_td->standard_dev_req_info.is_data_stage)
++ {
++ result_td->standard_dev_req_info.conrol_transfer_stage = DATA_STAGE;
++ }
++ else
++ {
++ result_td->standard_dev_req_info.conrol_transfer_stage = STATUS_STAGE;
++ }
++ ret_val = RE_TRANSMIT;
++
++ break;
++
++ case DATA_STAGE:
++
++ result_td->transferred_szie += calc_transferred_size(true,result_td, hc_reg_data);
++
++ if(result_td->transferred_szie==result_td->buf_size)
++ {//at IN Transfer, short transfer is accepted.
++ result_td->standard_dev_req_info.conrol_transfer_stage =STATUS_STAGE;
++ result_td->error_code = USB_ERR_STATUS_COMPLETE;
++ }
++ else
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in&& hc_reg_data->hc_size.b.xfersize)
++ {
++ if(result_td->transfer_flag&USB_TRANS_FLAG_NOT_SHORT)
++ {
++ result_td->error_code =USB_ERR_STATUS_SHORTREAD;
++ result_td->standard_dev_req_info.conrol_transfer_stage=STATUS_STAGE;
++ }
++ else
++ {
++ result_td->error_code =USB_ERR_STATUS_COMPLETE;
++ result_td->standard_dev_req_info.conrol_transfer_stage =STATUS_STAGE;
++ }
++ }
++ else
++ { // the Data Stage is not completed. So we need to continue Data Stage.
++ result_td->standard_dev_req_info.conrol_transfer_stage = DATA_STAGE;
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++ }
++ }
++
++ if(hc_reg_data->hc_int.b.nyet)
++ {
++ //at OUT Transfer, we must re-transmit.
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++ }
++ }
++ ret_val = RE_TRANSMIT;
++ break;
++
++ case STATUS_STAGE:
++ result_td->standard_dev_req_info.conrol_transfer_stage = COMPLETE_STAGE;
++
++ if(hc_reg_data->hc_int.b.nyet)
++ {
++ //at OUT Transfer, we must re-transmit.
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++ }
++ }
++
++ ret_val = DE_ALLOCATE;
++ break;
++
++ default:
++ break;
++ }
++
++ return ret_val;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_ahb_on_control( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with theAHB Errorl event according to Synopsys OTG Spec.
++ * this function stop the channel to be executed
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ */
++/******************************************************************************/
++u8 process_ahb_on_control( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt =0;
++ result_td->error_code =USB_ERR_STATUS_AHBERR;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_AHBErr);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ // we just calculate the size of the transferred data on Data Stage of Control Transfer.
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++ }
++
++ return DE_ALLOCATE;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_stall_on_control( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with theStall event according to Synopsys OTG Spec.
++ * but USB2.0 Spec don't permit the Stall on Setup Stage of Control Transfer.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ */
++/******************************************************************************/
++u8 process_stall_on_control( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt =0;
++ result_td->error_code =USB_ERR_STATUS_STALL;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++
++ // we just calculate the size of the transferred data on Data Stage of Control Transfer.
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++ }
++
++ return DE_ALLOCATE;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_nak_on_control( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the nak event according to Synopsys OTG Spec.
++ * nak is occured at OUT/IN Transaction of Data/Status Stage, and is not occured at Setup Stage.
++ * If nak is occured at IN Transaction, this function processes this interrupt as following.
++ * 1. resets the result_td->err_cnt.
++ * 2. masks ack/nak/DaaTglErr bit of HCINTMSK.
++ * 3. clears the nak bit of HCINT
++ * 4. be careful, nak of IN Transaction don't require re-transmit.
++ * If nak is occured at OUT Transaction, this function processes this interrupt as following.
++ * 1. all procedures of IN Transaction are executed.
++ * 2. calculates the size of the transferred data.
++ * 3. if the speed of USB Device is High-Speed, sets the ping protocol.
++ * 4. update the Toggle
++ * at OUT Transaction, this function check whether the speed of USB Device is High-Speed or not.
++ * if USB Device is High-Speed, then
++ * this function sets the ping protocol.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_SCHEDULE
++ */
++/******************************************************************************/
++u8 process_nak_on_control( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++
++ //at OUT Transfer, we must re-transmit.
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++ }
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ }
++ else if(result_td->standard_dev_req_info.conrol_transfer_stage == STATUS_STAGE)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==true)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++
++ }
++
++ return RE_SCHEDULE;
++
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_ack_on_control( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the ack event according to Synopsys OTG Spec.
++ * ack of IN/OUT Transaction don't need any retransmit.
++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK.
++ * finally, this function clears ack bit of HCINT.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return NO_ACTION
++ */
++/******************************************************************************/
++u8 process_ack_on_control(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable =false;
++
++ return NO_ACTION;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_nyet_on_control(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the nyet event according to Synopsys OTG Spec.
++ * nyet is occured at OUT Transaction of Data/Status Stage, and is not occured at Setup Stage.
++ * If nyet is occured at OUT Transaction, this function processes this interrupt as following.
++ * 1. resets the result_td->err_cnt.
++ * 2. masks ack/nak/datatglerr bit of HCINTMSK.
++ * 3. clears the nyet bit of HCINT
++ * 4. calculates the size of the transferred data.
++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol.
++ * 6. update the Data Toggle.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_SCHEDULE
++ */
++/******************************************************************************/
++u8 process_nyet_on_control(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NYET);
++
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ }
++ else if(result_td->standard_dev_req_info.conrol_transfer_stage == STATUS_STAGE)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==true)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++
++ }
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ return RE_SCHEDULE;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_xacterr_on_control( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the xacterr event according to Synopsys OTG Spec.
++ * xacterr is occured at OUT/IN Transaction of Data/Status Stage, and is not occured at Setup Stage.
++ * if Timeout/CRC error/false EOP is occured, then xacterr is occured.
++ * the procedure to process xacterr is as following.
++ * 1. increses the result_td->err_cnt
++ * 2. check whether the result_td->err_cnt is equal to 3.
++ * 2. unmasks ack/nak/datatglerr bit of HCINTMSK.
++ * 3. clears the xacterr bit of HCINT
++ * 4. calculates the size of the transferred data.
++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol.
++ * 6. update the Data Toggle.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if the Error Counter is less than RETRANSMIT_THRESHOLD
++ * DE_ALLOCATE -if the Error Counter is equal to RETRANSMIT_THRESHOLD
++ */
++/******************************************************************************/
++u8 process_xacterr_on_control(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ u8 ret_val=0;
++
++ if(result_td->err_cnt<RETRANSMIT_THRESHOLD)
++ {
++ result_td->cur_stransfer.hc_reg.hc_int_msk.d32 |= (CH_STATUS_ACK+CH_STATUS_NAK+CH_STATUS_DataTglErr);
++ ret_val = RE_TRANSMIT;
++ unmask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ unmask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ unmask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ result_td->err_cnt++ ;
++ }
++ else
++ {
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ ret_val = DE_ALLOCATE;
++ result_td->err_cnt = 0 ;
++ result_td->error_code = USB_ERR_STATUS_XACTERR;
++ }
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ }
++
++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG)
++ {
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ }
++ else if(result_td->standard_dev_req_info.conrol_transfer_stage == STATUS_STAGE)
++ {
++ if(result_td->parent_ed_p->ed_desc.is_ep_in==true)
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = true;
++ }
++ }
++ else
++ {
++ result_td->parent_ed_p->ed_status.is_ping_enable = false;
++ }
++
++
++ }
++
++
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ return ret_val;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name void process_bblerr_on_control( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the Babble event according to Synopsys OTG Spec.
++ * babble error can be just occured at IN Transaction. So if the direction of transfer is
++ * OUT, this function return Error Code.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ * NO_ACTION -if the direction is OUT
++ */
++/******************************************************************************/
++u8 process_bblerr_on_control( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++
++ if(!result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ return NO_ACTION;
++ }
++
++ result_td->err_cnt = 0;
++ result_td->error_code =USB_ERR_STATUS_BBLERR;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->parent_ed_p->ed_status.is_ping_enable =false;
++
++ // we just calculate the size of the transferred data on Data Stage of Control Transfer.
++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE)
++ {
++ result_td->transferred_szie += calc_transferred_size(false, result_td, hc_reg_data);
++ }
++
++ return DE_ALLOCATE;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_datatgl_on_control(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the datatglerr event according to Synopsys OTG Spec.
++ * the datatglerr event is occured at IN Transfer.
++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK.
++ * finally, this function clears datatglerr bit of HCINT.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return NO_ACTION
++ */
++/******************************************************************************/
++u8 process_datatgl_on_control( td_t * result_td,
++ hc_info_t * hc_reg_data)
++{
++ result_td->err_cnt = 0;
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ return NO_ACTION;
++
++}
++
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h
+new file mode 100644
+index 0000000..120a0c5
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h
+@@ -0,0 +1,100 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : ControlTransferChecker.h
++ * [Description] : The Header file defines the external and internal functions of ControlTransferChecker
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2009/01/12
++ * [Revision History]
++ * (1) 2008/06/13 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines functions of ControlTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _CONTROL_TRANSFER_CHECKER_H
++#define _CONTROL_TRANSFER_CHECKER_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++
++#include "s3c-otg-common-common.h"
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-common-regdef.h"
++
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-scheduler-scheduler.h"
++
++#include "s3c-otg-transferchecker-checker.h"
++
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++u8 process_control_transfer( td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_xfercompl_on_control(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_chhltd_on_control( td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_ahb_on_control( td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_stall_on_control( td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_nak_on_control (td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_ack_on_control (td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_nyet_on_control( td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_xacterr_on_control(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_bblerr_on_control( td_t *raw_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_datatgl_on_control(td_t *raw_td,
++ hc_info_t *hc_reg_data);
++u8 process_indirection_on_control( td_t *result_td,
++ hc_info_t *hc_reg_data);
++
++u8 process_outdirection_on_control(td_t *result_td,
++ hc_info_t *hc_reg_data);
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c
+new file mode 100644
+index 0000000..b9ac765
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c
+@@ -0,0 +1,582 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : IntTransferChecker.c
++ * [Description] : The Source file implements the external and internal functions of IntTransferChecker
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/19
++ * [Revision History]
++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and implements functions of IntTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++
++#include "s3c-otg-transferchecker-interrupt.h"
++
++/******************************************************************************/
++/*!
++ * @name u8 process_intr_transfer(td_t *result_td,
++ * hc_info_t *HCRegData)
++ *
++ *
++ * @brief this function processes the result of the Interrupt Transfer.
++ * firstly, this function checks the result of the Interrupt Transfer.
++ * and according to the result, calls the sub-functions to process the result.
++ *
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t whose channel is interruped.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if need to retransmit the result_td.
++ * RE_SCHEDULE -if need to reschedule the result_td.
++ * DE_ALLOCATE -if USB Transfer is completed.
++ * NO_ACTION -if we don't need any action,
++ */
++/******************************************************************************/
++u8 process_intr_transfer(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ hcintn_t hc_intr_info;
++ u8 ret_val=0;
++
++ //we just deal with the interrupts to be unmasked.
++ hc_intr_info.d32 = hc_reg_data->hc_int.d32&result_td->cur_stransfer.hc_reg.hc_int_msk.d32;
++
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ if(hc_intr_info.b.chhltd)
++ {
++ ret_val = process_chhltd_on_intr(result_td, hc_reg_data);
++ }
++
++ else if (hc_intr_info.b.ack)
++ {
++ ret_val =process_ack_on_intr(result_td, hc_reg_data);
++ }
++ }
++ else
++ {
++ if(hc_intr_info.b.chhltd)
++ {
++ ret_val = process_chhltd_on_intr(result_td, hc_reg_data);
++
++ }
++
++ else if(hc_intr_info.b.ack)
++ {
++ ret_val =process_ack_on_intr( result_td, hc_reg_data);
++ }
++ }
++
++ return ret_val;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_chhltd_on_intr(td_t *result_td,
++ * hc_info_t *HCRegData)
++ *
++ *
++ * @brief this function processes Channel Halt event according to Synopsys OTG Spec.
++ * firstly, this function checks the reason of the Channel Halt, and according to the reason,
++ * calls the sub-functions to process the result.
++ *
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_TRANSMIT -if need to retransmit the result_td.
++ * RE_SCHEDULE -if need to reschedule the result_td.
++ * DE_ALLOCATE -if USB Transfer is completed.
++ */
++/******************************************************************************/
++u8 process_chhltd_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ if(result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ if(hc_reg_data->hc_int.b.xfercompl)
++ {
++ return process_xfercompl_on_intr( result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.stall)
++ {
++ return process_stall_on_intr(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.bblerr)
++ {
++ return process_bblerr_on_intr(result_td, hc_reg_data);
++ }
++ else if (hc_reg_data->hc_int.b.nak)
++ {
++ return process_nak_on_intr(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.datatglerr)
++ {
++ return process_datatgl_on_intr(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.frmovrun)
++ {
++ return process_frmovrrun_on_intr(result_td,hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.xacterr)
++ {
++ return process_xacterr_on_intr(result_td, hc_reg_data);
++ }
++ else
++ {
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ return RE_TRANSMIT;
++ }
++ }
++ else
++ {
++ if(hc_reg_data->hc_int.b.xfercompl)
++ {
++ return process_xfercompl_on_intr( result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.stall)
++ {
++ return process_stall_on_intr(result_td, hc_reg_data);
++ }
++ else if (hc_reg_data->hc_int.b.nak)
++ {
++ return process_nak_on_intr(result_td, hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.frmovrun)
++ {
++ return process_frmovrrun_on_intr(result_td,hc_reg_data);
++ }
++ else if(hc_reg_data->hc_int.b.xacterr)
++ {
++ return process_xacterr_on_intr(result_td, hc_reg_data);
++ }
++ else
++ {
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->err_cnt++;
++ if(result_td->err_cnt == 3)
++ {
++ result_td->error_code = USB_ERR_STATUS_XACTERR;
++ result_td->err_cnt = 0;
++ return DE_ALLOCATE;
++ }
++
++ return RE_TRANSMIT;
++ }
++
++ }
++
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_xfercompl_on_intr( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the xfercompl event according to Synopsys OTG Spec.
++ * the procedure of this function is as following
++ * 1. clears all bits of the channel' HCINT by using clear_ch_intr() of S3CIsr.
++ * 2. masks ack/nak(?)/datatglerr(?) bit of HCINTMSK
++ * 3. Resets the err_cnt of result_td.
++ * 4. updates the result_td->parent_ed_p->ed_status.
++ * IntDataTgl.
++ * 5. calculates the tranferred size by calling calc_transferred_size() on DATA_STAGE.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE -if USB Transfer is completed.
++ * RE_TRANSMIT -if need to retransmit the result_td.
++ */
++/******************************************************************************/
++u8 process_xfercompl_on_intr( td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ u8 ret_val=0;
++
++ result_td->err_cnt =0;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->transferred_szie += calc_transferred_size(true,result_td, hc_reg_data);
++
++ if(result_td->transferred_szie==result_td->buf_size)
++ {//at IN Transfer, short transfer is accepted.
++ result_td->error_code = USB_ERR_STATUS_COMPLETE;
++ ret_val = DE_ALLOCATE;
++ }
++ else
++ {
++ // this routine will not be executed on Interrupt Transfer.
++ // So, we should decide to remove this routine or not.
++ if(result_td->parent_ed_p->ed_desc.is_ep_in&& hc_reg_data->hc_size.b.xfersize)
++ {
++ if(result_td->transfer_flag&USB_TRANS_FLAG_NOT_SHORT)
++ {
++ result_td->error_code = USB_ERR_STATUS_SHORTREAD;
++ }
++ else
++ {
++ result_td->error_code = USB_ERR_STATUS_COMPLETE;
++ }
++ ret_val = DE_ALLOCATE;
++ }
++ else
++ { // the Data Stage is not completed. So we need to continue Data Stage.
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++ ret_val = RE_TRANSMIT;
++ }
++ }
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ return ret_val;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_ahb_on_intr(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with theAHB Errorl event according to Synopsys OTG Spec.
++ * this function stop the channel to be executed
++ *
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ */
++/******************************************************************************/
++u8 process_ahb_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++ result_td->error_code = USB_ERR_STATUS_AHBERR;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_AHBErr);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ // we just calculate the size of the transferred data on Data Stage of Int Transfer.
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++ result_td->parent_ed_p->ed_status.is_ping_enable =false;
++
++ return DE_ALLOCATE;
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_stall_on_intr(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the Stall event according to Synopsys OTG Spec.
++ * when Stall is occured at Int Transfer, we should reset the PID as DATA0
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ */
++/******************************************************************************/
++u8 process_stall_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++ result_td->error_code = USB_ERR_STATUS_STALL;
++
++ //this channel is stalled, So we don't process another interrupts.
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ update_datatgl(DATA0, result_td);
++
++ return DE_ALLOCATE;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_nak_on_intr(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the nak event according to Synopsys OTG Spec.
++ * nak is occured at OUT/IN Transaction of Interrupt Transfer.
++ * we can't use ping protocol on Interrupt Transfer. and Syonopsys OTG IP occures
++ * chhltd interrupt on nak of IN/OUT Transaction. So we should retransmit the transfer
++ * on IN Transfer.
++ * If nak is occured at IN Transaction, this function processes this interrupt as following.
++ * 1. resets the result_td->err_cnt.
++ * 2. masks ack/nak/DaaTglErr bit of HCINTMSK.
++ * 3. clears the nak bit of HCINT
++ * 4. calculates frame number to retransmit this Interrupt Transfer.
++ *
++ * If nak is occured at OUT Transaction, this function processes this interrupt as following.
++ * 1. all procedures of IN Transaction are executed.
++ * 2. calculates the size of the transferred data.
++ * 3. if the speed of USB Device is High-Speed, sets the ping protocol.
++ * 4. update the Toggle
++ * at OUT Transaction, this function check whether the speed of USB Device is High-Speed or not.
++ * if USB Device is High-Speed, then
++ * this function sets the ping protocol.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_SCHEDULE -if the direction of the Transfer is OUT
++ * NO_ACTION -if the direction of the Transfer is IN
++ */
++/******************************************************************************/
++u8 process_nak_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++
++
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ update_frame_number(result_td);
++
++ return RE_SCHEDULE;
++// return RE_TRANSMIT;
++
++
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_ack_on_intr(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the ack event according to Synopsys OTG Spec.
++ * ack of IN/OUT Transaction don't need any retransmit.
++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK.
++ * finally, this function clears ack bit of HCINT and ed_status.is_ping_enable.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return NO_ACTION
++ */
++/******************************************************************************/
++u8 process_ack_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++
++ return NO_ACTION;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_xacterr_on_intr(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ * @brief this function deals with the xacterr event according to Synopsys OTG Spec.
++ * xacterr is occured at OUT/IN Transaction and we should retransmit the USB Transfer
++ * if the Error Counter is less than the RETRANSMIT_THRESHOLD.
++ * the reasons of xacterr is Timeout/CRC error/false EOP.
++ * the procedure to process xacterr is as following.
++ * 1. increses the result_td->err_cnt
++ * 2. check whether the result_td->err_cnt is equal to 3.
++ * 2. unmasks ack/nak/datatglerr bit of HCINTMSK.
++ * 3. clears the xacterr bit of HCINT
++ * 4. calculates the size of the transferred data.
++ * 5. update the Data Toggle.
++ * 6. update the frame number to start retransmitting the Interrupt Transfer.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_SCHEDULE -if the error count is less than 3
++ * DE_ALLOCATE -if the error count is equal to 3
++ */
++/******************************************************************************/
++u8 process_xacterr_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ u8 ret_val = 0;
++
++ if(result_td->err_cnt<RETRANSMIT_THRESHOLD)
++ {
++ result_td->cur_stransfer.hc_reg.hc_int_msk.d32 |=(CH_STATUS_ACK+CH_STATUS_NAK+CH_STATUS_DataTglErr);
++ ret_val = RE_SCHEDULE;
++ result_td->err_cnt++ ;
++ }
++ else
++ {
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++ ret_val = DE_ALLOCATE;
++ result_td->err_cnt = 0 ;
++ }
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ if(ret_val == RE_SCHEDULE)
++ { //Calculates the frame number
++ update_frame_number(result_td);
++ }
++
++ return ret_val;
++}
++
++/******************************************************************************/
++/*!
++ * @name void process_bblerr_on_intr(td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ *
++ * @brief this function deals with the Babble event according to Synopsys OTG Spec.
++ * babble error is occured when the USB device continues to send packets
++ * althrough EOP is occured. So Babble error is only occured at IN Transfer.
++ * when Babble Error is occured, we should stop the USB Transfer, and return the fact
++ * to Application.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return DE_ALLOCATE
++ */
++/******************************************************************************/
++u8 process_bblerr_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++
++ if(!result_td->parent_ed_p->ed_desc.is_ep_in)
++ {
++ return NO_ACTION;
++ }
++
++ result_td->err_cnt = 0;
++ result_td->error_code =USB_ERR_STATUS_BBLERR;
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL);
++
++ //Mask ack Interrupt..
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ result_td->transferred_szie += calc_transferred_size(false, result_td, hc_reg_data);
++ return DE_ALLOCATE;
++}
++
++/******************************************************************************/
++/*!
++ * @name u8 process_datatgl_on_intr( td_t *result_td,
++ * hc_info_t *hc_reg_data)
++ *
++ * @brief this function deals with the datatglerr event according to Synopsys OTG Spec.
++ * the datatglerr event is occured at IN Transfer, and the channel is not halted.
++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK.
++ * finally, this function clears datatglerr bit of HCINT.
++ *
++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum.
++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted
++ *
++ * @return RE_SCHEDULE
++ */
++/******************************************************************************/
++u8 process_datatgl_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++ result_td->err_cnt = 0;
++
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr);
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++
++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data);
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ update_frame_number(result_td);
++
++ return RE_SCHEDULE;
++}
++
++u8 process_frmovrrun_on_intr(td_t *result_td,
++ hc_info_t *hc_reg_data)
++{
++
++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK);
++
++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td);
++
++ update_frame_number(result_td);
++
++ return RE_TRANSMIT;
++}
++
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h
+new file mode 100644
+index 0000000..0436117
+--- /dev/null
++++ b/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h
+@@ -0,0 +1,97 @@
++/****************************************************************************
++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved
++ *
++ * [File Name] : IntTransferChecker.h
++ * [Description] : The Header file defines the external and internal functions of IntTransferChecker
++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com }
++ * [Department] : System LSI Division/System SW Lab
++ * [Created Date]: 2008/06/19
++ * [Revision History]
++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com }
++ * - Created this file and defines functions of IntTransferChecker
++ *
++ ****************************************************************************/
++/****************************************************************************
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ ****************************************************************************/
++
++#ifndef _INT_TRANSFER_CHECKER_H
++#define _INT_TRANSFER_CHECKER_H
++
++/*
++// ----------------------------------------------------------------------------
++// Include files : None.
++// ----------------------------------------------------------------------------
++*/
++
++#include "s3c-otg-common-common.h"
++//#include "s3c-otg-common-typedef.h"
++#include "s3c-otg-common-const.h"
++#include "s3c-otg-common-errorcode.h"
++#include "s3c-otg-common-datastruct.h"
++#include "s3c-otg-common-regdef.h"
++
++#include "s3c-otg-hcdi-debug.h"
++#include "s3c-otg-scheduler-scheduler.h"
++#include "s3c-otg-isr.h"
++#include "s3c-otg-transferchecker-checker.h"
++
++
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++u8 process_intr_transfer(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_xfercompl_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_chhltd_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_ahb_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_stall_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_nak_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_frmovrrun_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_ack_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_xacterr_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_bblerr_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++u8 process_datatgl_on_intr(td_t *pRawTD,
++ hc_info_t *pHCRegData);
++
++#ifdef __cplusplus
++}
++#endif
++
++
++#endif
++
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index 5b3dbcf..4212cd0 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -201,6 +201,93 @@ config FB_TILEBLITTING
+ comment "Frame buffer hardware drivers"
+ depends on FB
+
++config FB_S3C
++ tristate "S3C Framebuffer Support"
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ depends on FB && ARCH_S3C2410
++
++ default n
++ ---help---
++ TBA
++
++choice
++depends on FB_S3C
++prompt "Select LCD Type"
++default FB_S3C_LTE480WV
++config FB_S3C_LTE480WV
++ bool "LTE480WV/LTP700WV"
++ ---help---
++ TBA
++
++config FB_S3C_LTV350QV
++ bool "LTV350QV"
++ ---help---
++ TBA
++
++config FB_S3C_LTS222QV
++ bool "LTS222QV"
++ ---help---
++ TBA
++
++endchoice
++
++config FB_S3C_BPP
++ tristate "Advanced options for S3C Framebuffer"
++ depends on FB_S3C
++ default n
++ ---help---
++ TBA
++
++choice
++depends on FB_S3C_BPP
++prompt "Select BPP(Bits Per Pixel)"
++default FB_S3C_BPP_16
++config FB_S3C_BPP_8
++ bool "8 BPP"
++ ---help---
++ TBA
++
++config FB_S3C_BPP_16
++ bool "16 BPP"
++ ---help---
++ TBA
++
++config FB_S3C_BPP_24
++ bool "24 BPP"
++ ---help---
++ TBA
++
++config FB_S3C_BPP_32
++ bool "32 BPP"
++ ---help---
++ TBA
++endchoice
++
++config FB_S3C_NUM
++ int "Number of Framebuffers"
++ depends on ARCH_S3C2410 && FB_S3C_BPP
++ default "1"
++ ---help---
++ TBA
++
++config FB_S3C_VIRTUAL_SCREEN
++ bool "Enable Virtual Screen"
++ depends on FB_S3C_BPP
++
++ default n
++ ---help---
++ TBA
++
++config FB_S3C_DOUBLE_BUFFERING
++ bool "Enable Double Buffering"
++ depends on FB_S3C_BPP
++
++ default n
++ ---help---
++ TBA
++
+ config FB_CIRRUS
+ tristate "Cirrus Logic support"
+ depends on FB && (ZORRO || PCI)
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index 83e02b3..87d6c8f 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -106,6 +106,7 @@ obj-$(CONFIG_FB_MAXINE) += maxinefb.o
+ obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
+ obj-$(CONFIG_FB_IMX) += imxfb.o
+ obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
++obj-$(CONFIG_FB_S3C) += s3c/
+ obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/
+ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
+ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
+@@ -128,3 +129,4 @@ obj-$(CONFIG_FB_VIRTUAL) += vfb.o
+
+ #video output switch sysfs driver
+ obj-$(CONFIG_VIDEO_OUTPUT_CONTROL) += output.o
++
+diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
+index 9609a6c..710dcc4 100644
+--- a/drivers/video/backlight/Kconfig
++++ b/drivers/video/backlight/Kconfig
+@@ -75,6 +75,14 @@ config BACKLIGHT_HP680
+ If you have a HP Jornada 680, say y to enable the
+ backlight driver.
+
++config BACKLIGHT_SMDK
++ tristate "SMDK Backlight Driver"
++ depends on BACKLIGHT_CLASS_DEVICE && MACH_SMDK
++ default y
++ help
++ If you have SMDK board, say y to enable the
++ backlight driver.
++
+ config BACKLIGHT_PROGEAR
+ tristate "Frontpath ProGear Backlight Driver"
+ depends on BACKLIGHT_CLASS_DEVICE && PCI && X86
+diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
+index 965a78b..3096708 100644
+--- a/drivers/video/backlight/Makefile
++++ b/drivers/video/backlight/Makefile
+@@ -9,3 +9,4 @@ obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
+ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
+ obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
+ obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
++obj-$(CONFIG_BACKLIGHT_SMDK) += smdk_bl.o
+diff --git a/drivers/video/backlight/smdk_bl.c b/drivers/video/backlight/smdk_bl.c
+new file mode 100644
+index 0000000..91a2b75
+--- /dev/null
++++ b/drivers/video/backlight/smdk_bl.c
+@@ -0,0 +1,166 @@
++/*
++ * Backlight Driver for SMDK(Samsung Mobile Develop Kit) board
++ *
++ * Copyright (c) 2008 Jongpill Lee
++ *
++ * Based on hp680 Backlight Driver
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++#include <linux/fb.h>
++#include <linux/backlight.h>
++
++#define SMDK_MAX_INTENSITY 100
++#define SMDK_DEFAULT_INTENSITY 0
++
++unsigned int smdk_bl_suspend_ck;
++static int current_intensity = 0;
++
++extern void s3cfb_set_brightness(int val);
++
++static DEFINE_SPINLOCK(bl_lock);
++
++static void smdk_bl_send_intensity(struct backlight_device *bd)
++{
++ unsigned long flags;
++ int intensity = bd->props.brightness;
++
++ if (bd->props.power != FB_BLANK_UNBLANK)
++ intensity = 0;
++ if (bd->props.fb_blank != FB_BLANK_UNBLANK)
++ intensity = 0;
++ if (smdk_bl_suspend_ck)
++ intensity = 0;
++
++ s3cfb_set_brightness(SMDK_MAX_INTENSITY - intensity);
++
++ current_intensity = intensity;
++}
++
++
++#ifdef CONFIG_PM
++static int smdk_bl_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct backlight_device *bd = platform_get_drvdata(pdev);
++
++ smdk_bl_suspend_ck = 1;
++ smdk_bl_send_intensity(bd);
++
++ return 0;
++}
++
++static int smdk_bl_resume(struct platform_device *pdev)
++{
++ struct backlight_device *bd = platform_get_drvdata(pdev);
++
++ smdk_bl_suspend_ck = 0;
++ smdk_bl_send_intensity(bd);
++
++ return 0;
++}
++#else
++#define smdk_bl_suspend NULL
++#define smdk_bl_resume NULL
++#endif
++
++static int smdk_bl_set_intensity(struct backlight_device *bd)
++{
++ smdk_bl_send_intensity(bd);
++ return 0;
++}
++
++static int smdk_bl_get_intensity(struct backlight_device *bd)
++{
++ return current_intensity;
++}
++
++static struct backlight_ops smdk_bl_ops = {
++ .get_brightness = smdk_bl_get_intensity,
++ .update_status = smdk_bl_set_intensity,
++};
++
++static int __init smdk_bl_probe(struct platform_device *pdev)
++{
++ struct backlight_device *bd;
++
++ bd = backlight_device_register ("smdk-backlight", &pdev->dev, NULL,
++ &smdk_bl_ops);
++ if (IS_ERR(bd))
++ return PTR_ERR(bd);
++
++ platform_set_drvdata(pdev, bd);
++
++ bd->props.max_brightness = SMDK_MAX_INTENSITY;
++ bd->props.brightness = SMDK_DEFAULT_INTENSITY;
++ smdk_bl_send_intensity(bd);
++
++ return 0;
++}
++
++static int smdk_bl_remove(struct platform_device *pdev)
++{
++ struct backlight_device *bd = platform_get_drvdata(pdev);
++
++ bd->props.brightness = 0;
++ bd->props.power = 0;
++ smdk_bl_send_intensity(bd);
++
++ backlight_device_unregister(bd);
++
++ return 0;
++}
++
++static struct platform_driver smdk_bl_driver = {
++ .probe = smdk_bl_probe,
++ .remove = smdk_bl_remove,
++ .suspend = smdk_bl_suspend,
++ .resume = smdk_bl_resume,
++ .driver = {
++ .name = "smdk-backlight",
++ },
++};
++
++static struct platform_device *smdk_bl_device;
++
++static int __init smdk_bl_init(void)
++{
++ int ret;
++
++ printk("SMDK board LCD Backlight Device Driver (c) 2008 Samsung Electronics \n");
++
++ ret = platform_driver_register(&smdk_bl_driver);
++ if (!ret) {
++ smdk_bl_device = platform_device_alloc("smdk-backlight", -1);
++ if (!smdk_bl_device)
++ return -ENOMEM;
++
++ ret = platform_device_add(smdk_bl_device);
++
++ if (ret) {
++ platform_device_put(smdk_bl_device);
++ platform_driver_unregister(&smdk_bl_driver);
++ }
++ }
++ return ret;
++}
++
++static void __exit smdk_bl_exit(void)
++{
++ platform_device_unregister(smdk_bl_device);
++ platform_driver_unregister(&smdk_bl_driver);
++}
++
++module_init(smdk_bl_init);
++module_exit(smdk_bl_exit);
++
++MODULE_AUTHOR("Jongpill Lee <boyko.lee@samsung.com>");
++MODULE_DESCRIPTION("SMDK board Backlight Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/cfbimgblt.c b/drivers/video/cfbimgblt.c
+index f598907..bc85262 100644
+--- a/drivers/video/cfbimgblt.c
++++ b/drivers/video/cfbimgblt.c
+@@ -84,7 +84,13 @@ static inline void color_imageblit(const struct fb_image *image,
+ /* Draw the penguin */
+ u32 __iomem *dst, *dst2;
+ u32 color = 0, val, shift;
++
++#if defined(CONFIG_FB_S3C)
++ int i, n, bpp = p->fix.line_length / p->var.width * 8;
++#else
+ int i, n, bpp = p->var.bits_per_pixel;
++#endif
++
+ u32 null_bits = 32 - bpp;
+ u32 *palette = (u32 *) p->pseudo_palette;
+ const u8 *src = image->data;
+diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig
+index 9de1c11..0e55269 100644
+--- a/drivers/video/logo/Kconfig
++++ b/drivers/video/logo/Kconfig
+@@ -27,6 +27,11 @@ config LOGO_LINUX_CLUT224
+ bool "Standard 224-color Linux logo"
+ default y
+
++config LOGO_LINUX_LANDSCAPED_CLUT224
++ bool "Standard landscape 224-color Linux logo"
++ depends on LOGO
++ default y
++
+ config LOGO_DEC_CLUT224
+ bool "224-color Digital Equipment Corporation Linux logo"
+ depends on MACH_DECSTATION || ALPHA
+diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile
+index a5fc4ed..a5ad676 100644
+--- a/drivers/video/logo/Makefile
++++ b/drivers/video/logo/Makefile
+@@ -4,6 +4,7 @@ obj-$(CONFIG_LOGO) += logo.o
+ obj-$(CONFIG_LOGO_LINUX_MONO) += logo_linux_mono.o
+ obj-$(CONFIG_LOGO_LINUX_VGA16) += logo_linux_vga16.o
+ obj-$(CONFIG_LOGO_LINUX_CLUT224) += logo_linux_clut224.o
++obj-$(CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224) += logo_linux_landscaped_clut224.o
+ obj-$(CONFIG_LOGO_DEC_CLUT224) += logo_dec_clut224.o
+ obj-$(CONFIG_LOGO_MAC_CLUT224) += logo_mac_clut224.o
+ obj-$(CONFIG_LOGO_PARISC_CLUT224) += logo_parisc_clut224.o
+diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c
+index fc72684..d1ec7fd 100644
+--- a/drivers/video/logo/logo.c
++++ b/drivers/video/logo/logo.c
+@@ -24,6 +24,7 @@
+ extern const struct linux_logo logo_linux_mono;
+ extern const struct linux_logo logo_linux_vga16;
+ extern const struct linux_logo logo_linux_clut224;
++extern const struct linux_logo logo_linux_landscaped_clut224;
+ extern const struct linux_logo logo_dec_clut224;
+ extern const struct linux_logo logo_mac_clut224;
+ extern const struct linux_logo logo_parisc_clut224;
+@@ -76,6 +77,10 @@ const struct linux_logo * __init_refok fb_find_logo(int depth)
+ /* Generic Linux logo */
+ logo = &logo_linux_clut224;
+ #endif
++#ifdef CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224
++ /* Generic Linux logo */
++ logo = &logo_linux_landscaped_clut224;
++#endif
+ #ifdef CONFIG_LOGO_DEC_CLUT224
+ /* DEC Linux logo on MIPS/MIPS64 or ALPHA */
+ logo = &logo_dec_clut224;
+diff --git a/drivers/video/logo/logo_linux_clut224.ppm b/drivers/video/logo/logo_linux_clut224.ppm
+index 3c14e43..98b9f74 100644
+--- a/drivers/video/logo/logo_linux_clut224.ppm
++++ b/drivers/video/logo/logo_linux_clut224.ppm
+@@ -1,1604 +1,9843 @@
+ P3
+-# Standard 224-color Linux logo
+-80 80
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+ 255
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++
+diff --git a/drivers/video/logo/logo_linux_landscaped_clut224.ppm b/drivers/video/logo/logo_linux_landscaped_clut224.ppm
+new file mode 100644
+index 0000000..025b85d
+--- /dev/null
++++ b/drivers/video/logo/logo_linux_landscaped_clut224.ppm
+@@ -0,0 +1,48483 @@
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
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++
+diff --git a/drivers/video/s3c/Makefile b/drivers/video/s3c/Makefile
+new file mode 100644
+index 0000000..3f52d72
+--- /dev/null
++++ b/drivers/video/s3c/Makefile
+@@ -0,0 +1,12 @@
++#
++# Makefile for the s3c framebuffer driver
++#
++
++obj-$(CONFIG_FB_S3C) += s3cfb.o s3cfb_spi.o
++obj-$(CONFIG_PLAT_S3C24XX) += s3cfb_fimd3x.o
++obj-$(CONFIG_PLAT_S3C64XX) += s3cfb_fimd4x.o
++obj-$(CONFIG_PLAT_S5PC1XX) += s5pfb_fimd5x.o
++obj-$(CONFIG_FB_S3C_LTS222QV) += s3cfb_lts222qv.o
++obj-$(CONFIG_FB_S3C_LTV350QV) += s3cfb_ltv350qv.o
++obj-$(CONFIG_FB_S3C_LTE480WV) += s3cfb_lte480wv.o
++
+diff --git a/drivers/video/s3c/s3cfb.c b/drivers/video/s3c/s3cfb.c
+new file mode 100644
+index 0000000..d9b8196
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb.c
+@@ -0,0 +1,991 @@
++/*
++ * drivers/video/s3c/s3cfb.c
++ *
++ * $Id: s3cfb.c,v 1.34 2008/09/25 06:44:39 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/workqueue.h>
++#include <linux/wait.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/div64.h>
++
++#include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/idle.h>
++
++#include "s3cfb.h"
++
++/*
++ * Globals
++ */
++s3c_fb_info_t s3c_fb_info[S3C_FB_NUM];
++s3c_vsync_info_t s3c_vsync_info;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++s3c_vs_info_t s3c_vs_info;
++#endif
++
++static int backlight_level = S3C_FB_DEFAULT_BACKLIGHT_LEVEL;
++static int backlight_power = 1;
++static int lcd_power = 1;
++static int s3c_palette_win;
++
++static void s3cfb_set_lcd_power(int to)
++{
++ lcd_power = to;
++
++ if (s3c_fimd.set_lcd_power)
++ (s3c_fimd.set_lcd_power)(to);
++}
++
++static void s3cfb_set_backlight_power(int to)
++{
++ backlight_power = to;
++
++ if (s3c_fimd.set_backlight_power)
++ (s3c_fimd.set_backlight_power)(to);
++}
++
++static void s3cfb_set_backlight_level(int to)
++{
++ backlight_level = to;
++
++ if (s3c_fimd.set_brightness)
++ (s3c_fimd.set_brightness)(to);
++}
++
++static int __init s3cfb_map_video_memory(s3c_fb_info_t *fbi)
++{
++ DPRINTK("map_video_memory(fbi=%p)\n", fbi);
++
++ fbi->map_size_f1 = PAGE_ALIGN(fbi->fb.fix.smem_len);
++ fbi->map_cpu_f1 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f1, &fbi->map_dma_f1, GFP_KERNEL);
++ fbi->map_size_f1 = fbi->fb.fix.smem_len;
++
++ if (fbi->map_cpu_f1) {
++ /* prevent initial garbage on screen */
++ printk("Window[%d] - FB1: map_video_memory: clear %p:%08x\n",
++ fbi->win_id, fbi->map_cpu_f1, fbi->map_size_f1);
++ memset(fbi->map_cpu_f1, 0xf0, fbi->map_size_f1);
++
++ fbi->screen_dma_f1 = fbi->map_dma_f1;
++ fbi->fb.screen_base = fbi->map_cpu_f1;
++ fbi->fb.fix.smem_start = fbi->screen_dma_f1;
++
++ printk(" FB1: map_video_memory: dma=%08x cpu=%p size=%08x\n",
++ fbi->map_dma_f1, fbi->map_cpu_f1, fbi->fb.fix.smem_len);
++ }
++
++ if (!fbi->map_cpu_f1)
++ return -ENOMEM;
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ if (fbi->win_id < 2 && fbi->map_cpu_f1) {
++ fbi->map_size_f2 = (fbi->fb.fix.smem_len / 2);
++ fbi->map_cpu_f2 = fbi->map_cpu_f1 + fbi->map_size_f2;
++ fbi->map_dma_f2 = fbi->map_dma_f1 + fbi->map_size_f2;
++
++ /* prevent initial garbage on screen */
++ printk("Window[%d] - FB2: map_video_memory: clear %p:%08x\n",
++ fbi->win_id, fbi->map_cpu_f2, fbi->map_size_f2);
++
++ fbi->screen_dma_f2 = fbi->map_dma_f2;
++
++ printk(" FB2: map_video_memory: dma=%08x cpu=%p size=%08x\n",
++ fbi->map_dma_f2, fbi->map_cpu_f2, fbi->map_size_f2);
++ }
++#endif
++
++ if (s3c_fimd.map_video_memory)
++ (s3c_fimd.map_video_memory)(fbi);
++
++ return 0;
++}
++
++void s3cfb_unmap_video_memory(s3c_fb_info_t *fbi)
++{
++ dma_free_writecombine(fbi->dev, fbi->map_size_f1, fbi->map_cpu_f1, fbi->map_dma_f1);
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ dma_free_writecombine(fbi->dev, fbi->map_size_f2, fbi->map_cpu_f2, fbi->map_dma_f2);
++#endif
++
++ if (s3c_fimd.unmap_video_memory)
++ (s3c_fimd.unmap_video_memory)(fbi);
++}
++
++EXPORT_SYMBOL(s3cfb_unmap_video_memory);
++
++/*
++ * s3cfb_check_var():
++ * Get the video params out of 'var'. If a value doesn't fit, round it up,
++ * if it's too big, return -EINVAL.
++ *
++ */
++static int s3cfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ DPRINTK("check_var(var=%p, info=%p)\n", var, info);
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ var->red = s3c_fb_rgb_8.red;
++ var->green = s3c_fb_rgb_8.green;
++ var->blue = s3c_fb_rgb_8.blue;
++ var->transp = s3c_fb_rgb_8.transp;
++ s3c_fimd.bytes_per_pixel = 1;
++ break;
++
++ case 16:
++ var->red = s3c_fb_rgb_16.red;
++ var->green = s3c_fb_rgb_16.green;
++ var->blue = s3c_fb_rgb_16.blue;
++ var->transp = s3c_fb_rgb_16.transp;
++ s3c_fimd.bytes_per_pixel = 2;
++ break;
++
++ case 24:
++ var->red = s3c_fb_rgb_24.red;
++ var->green = s3c_fb_rgb_24.green;
++ var->blue = s3c_fb_rgb_24.blue;
++ var->transp = s3c_fb_rgb_24.transp;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++
++ case 32:
++ var->red = s3c_fb_rgb_32.red;
++ var->green = s3c_fb_rgb_32.green;
++ var->blue = s3c_fb_rgb_32.blue;
++ var->transp = s3c_fb_rgb_32.transp;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++ }
++
++ return 0;
++}
++
++/*
++ * s3cfb_set_par - Optional function. Alters the hardware state.
++ * @info: frame buffer structure that represents a single frame buffer
++ *
++ */
++static int s3cfb_set_par(struct fb_info *info)
++{
++ struct fb_var_screeninfo *var = &info->var;
++ s3c_fb_info_t *fbi = (s3c_fb_info_t *) info;
++
++ if (var->bits_per_pixel == 16 || var->bits_per_pixel == 24)
++ fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
++ else
++ fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
++
++ fbi->fb.fix.line_length = var->width * s3c_fimd.bytes_per_pixel;
++
++ /* activate this new configuration */
++ s3cfb_activate_var(fbi, var);
++
++ return 0;
++}
++
++/**
++ * s3cfb_pan_display
++ * @var: frame buffer variable screen structure
++ * @info: frame buffer structure that represents a single frame buffer
++ *
++ * Pan (or wrap, depending on the `vmode' field) the display using the
++ * `xoffset' and `yoffset' fields of the `var' structure.
++ * If the values don't fit, return -EINVAL.
++ *
++ * Returns negative errno on error, or zero on success.
++ */
++static int s3cfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ s3c_fb_info_t *fbi = (s3c_fb_info_t *)info;
++
++ DPRINTK("s3c_fb_pan_display(var=%p, info=%p)\n", var, info);
++
++ if (var->xoffset != 0)
++ return -EINVAL;
++
++ if (var->yoffset + info->var.yres > info->var.yres_virtual)
++ return -EINVAL;
++
++ fbi->fb.var.xoffset = var->xoffset;
++ fbi->fb.var.yoffset = var->yoffset;
++
++ s3cfb_set_fb_addr(fbi);
++
++ return 0;
++}
++
++/**
++ * s3cfb_blank
++ * @blank_mode: the blank mode we want.
++ * @info: frame buffer structure that represents a single frame buffer
++ *
++ * Blank the screen if blank_mode != 0, else unblank. Return 0 if
++ * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
++ * video mode which doesn't support it. Implements VESA suspend
++ * and powerdown modes on hardware that supports disabling hsync/vsync:
++ * blank_mode == 2: suspend vsync
++ * blank_mode == 3: suspend hsync
++ * blank_mode == 4: powerdown
++ *
++ * Returns negative errno on error, or zero on success.
++ *
++ */
++static int s3cfb_blank(int blank_mode, struct fb_info *info)
++{
++ DPRINTK("blank(mode=%d, info=%p)\n", blank_mode, info);
++
++ switch (blank_mode) {
++ case VESA_NO_BLANKING: /* lcd on, backlight on */
++ s3cfb_set_lcd_power(1);
++ s3cfb_set_backlight_power(1);
++ break;
++
++ case VESA_VSYNC_SUSPEND: /* lcd on, backlight off */
++ case VESA_HSYNC_SUSPEND:
++ s3cfb_set_lcd_power(1);
++ s3cfb_set_backlight_power(0);
++ break;
++
++ case VESA_POWERDOWN: /* lcd and backlight off */
++ s3cfb_set_lcd_power(0);
++ s3cfb_set_backlight_power(0);
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++int s3cfb_set_vs_info(s3c_vs_info_t vs_info)
++{
++ /* check invalid value */
++ if (vs_info.width != s3c_fimd.width || vs_info.height != s3c_fimd.height)
++ return 1;
++
++ if (!(vs_info.bpp == 8 || vs_info.bpp == 16 || vs_info.bpp == 24 || vs_info.bpp == 32))
++ return 1;
++
++ if (vs_info.offset < 0)
++ return 1;
++
++ if (vs_info.v_width != s3c_fimd.xres_virtual || vs_info.v_height != s3c_fimd.yres_virtual)
++ return 1;
++
++ /* save virtual screen information */
++ s3c_vs_info = vs_info;
++
++ if (s3c_vs_info.offset < 1)
++ s3c_vs_info.offset = 1;
++
++ if (s3c_vs_info.offset > S3C_FB_MAX_DISPLAY_OFFSET)
++ s3c_vs_info.offset = S3C_FB_MAX_DISPLAY_OFFSET;
++
++ s3c_vs_offset = s3c_vs_info.offset;
++
++ return 0;
++}
++#endif
++
++int s3cfb_onoff_win(s3c_fb_info_t *fbi, int onoff)
++{
++ int win_num = fbi->win_id;
++
++ if (onoff)
++ writel(readl(S3C_WINCON0 + (0x04 * win_num)) | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0 + (0x04 * win_num));
++ else
++ writel(readl(S3C_WINCON0 + (0x04 * win_num)) &~ (S3C_WINCONx_ENWIN_F_ENABLE), S3C_WINCON0 + (0x04 * win_num));
++
++ return 0;
++}
++
++int s3cfb_onoff_color_key_alpha(s3c_fb_info_t *fbi, int onoff)
++{
++ int win_num = fbi->win_id - 1;
++
++ if (onoff)
++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) | S3C_WxKEYCON0_KEYBLEN_ENABLE, S3C_W1KEYCON0 + (0x08 * win_num));
++ else
++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) &~ (S3C_WxKEYCON0_KEYBLEN_ENABLE), S3C_W1KEYCON0 + (0x08 * win_num));
++
++ return 0;
++}
++
++int s3cfb_onoff_color_key(s3c_fb_info_t *fbi, int onoff)
++{
++ int win_num = fbi->win_id - 1;
++
++ if (onoff)
++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) | S3C_WxKEYCON0_KEYEN_F_ENABLE, S3C_W1KEYCON0 + (0x08 * win_num));
++ else
++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) &~ (S3C_WxKEYCON0_KEYEN_F_ENABLE), S3C_W1KEYCON0 + (0x08 * win_num));
++
++ return 0;
++}
++
++int s3cfb_set_color_key_registers(s3c_fb_info_t *fbi, s3c_color_key_info_t colkey_info)
++{
++ unsigned int compkey = 0;
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support color key\n");
++ return -1;
++ }
++
++ win_num--;
++
++ if (fbi->fb.var.bits_per_pixel == S3C_FB_PIXEL_BPP_16) {
++ /* RGB 5-6-5 mode */
++ compkey = (((colkey_info.compkey_red & 0x1f) << 19) | 0x70000);
++ compkey |= (((colkey_info.compkey_green & 0x3f) << 10) | 0x300);
++ compkey |= (((colkey_info.compkey_blue & 0x1f) << 3 )| 0x7);
++ } else if (fbi->fb.var.bits_per_pixel == S3C_FB_PIXEL_BPP_24) {
++ /* currently RGB 8-8-8 mode */
++ compkey = ((colkey_info.compkey_red & 0xff) << 16);
++ compkey |= ((colkey_info.compkey_green & 0xff) << 8);
++ compkey |= ((colkey_info.compkey_blue & 0xff) << 0);
++ } else
++ printk("Invalid BPP has been given!\n");
++
++ if (colkey_info.direction == S3C_FB_COLOR_KEY_DIR_BG)
++ writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE, S3C_W1KEYCON0 + (0x08 * win_num));
++
++ else if (colkey_info.direction == S3C_FB_COLOR_KEY_DIR_FG)
++ writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE, S3C_W1KEYCON0 + (0x08 * win_num));
++
++ else
++ printk("Color key direction is not correct :: %d!\n", colkey_info.direction);
++
++ return 0;
++}
++
++int s3cfb_set_color_value(s3c_fb_info_t *fbi, s3c_color_val_info_t colval_info)
++{
++ unsigned int colval = 0;
++
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support color key value\n");
++ return -1;
++ }
++
++ win_num--;
++
++ if (fbi->fb.var.bits_per_pixel == S3C_FB_PIXEL_BPP_16) {
++ /* RGB 5-6-5 mode */
++ colval = (((colval_info.colval_red & 0x1f) << 19) | 0x70000);
++ colval |= (((colval_info.colval_green & 0x3f) << 10) | 0x300);
++ colval |= (((colval_info.colval_blue & 0x1f) << 3 )| 0x7);
++ } else if (fbi->fb.var.bits_per_pixel == S3C_FB_PIXEL_BPP_24) {
++ /* currently RGB 8-8-8 mode */
++ colval = ((colval_info.colval_red & 0xff) << 16);
++ colval |= ((colval_info.colval_green & 0xff) << 8);
++ colval |= ((colval_info.colval_blue & 0xff) << 0);
++ } else
++ printk("Invalid BPP has been given!\n");
++
++ writel(S3C_WxKEYCON1_COLVAL(colval), S3C_W1KEYCON1 + (0x08 * win_num));
++
++ return 0;
++}
++
++static int s3cfb_set_bpp(s3c_fb_info_t *fbi, int bpp)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++ unsigned int val;
++
++ val = readl(S3C_WINCON0 + (0x04 * win_num));
++ val &= ~(S3C_WINCONx_BPPMODE_F_MASK | S3C_WINCONx_BLD_PIX_MASK);
++ val |= S3C_WINCONx_ALPHA_SEL_1;
++
++ switch (bpp) {
++ case 1:
++ case 2:
++ case 4:
++ case 8:
++ s3c_fimd.bytes_per_pixel = 1;
++ break;
++
++ case 16:
++ writel(val | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE, S3C_WINCON0 + (0x04 * win_num));
++ var->bits_per_pixel = bpp;
++ s3c_fimd.bytes_per_pixel = 2;
++ break;
++
++ case 24:
++ writel(val | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE, S3C_WINCON0 + (0x04 * win_num));
++ var->bits_per_pixel = bpp;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++
++ case 25:
++ writel(val | S3C_WINCONx_BPPMODE_F_25BPP_A888 | S3C_WINCONx_BLD_PIX_PLANE, S3C_WINCON0 + (0x04 * win_num));
++ var->bits_per_pixel = bpp;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++
++ case 28:
++ writel(val | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL, S3C_WINCON0 + (0x04 * win_num));
++ var->bits_per_pixel = bpp;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++
++ case 32:
++ var->bits_per_pixel = bpp;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++ }
++
++ return 0;
++}
++
++void s3cfb_stop_lcd(void)
++{
++ unsigned long flags;
++ unsigned long tmp;
++
++ local_irq_save(flags);
++
++ tmp = readl(S3C_VIDCON0);
++ writel(tmp & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE), S3C_VIDCON0);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s3cfb_stop_lcd);
++
++void s3cfb_start_lcd(void)
++{
++ unsigned long flags;
++ unsigned long tmp;
++
++ local_irq_save(flags);
++
++ tmp = readl(S3C_VIDCON0);
++ writel(tmp | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
++
++ local_irq_restore(flags);
++}
++
++EXPORT_SYMBOL(s3cfb_start_lcd);
++
++void s3cfb_set_clock(unsigned int clkval)
++{
++ unsigned int tmp;
++
++ tmp = readl(S3C_VIDCON0);
++
++ tmp &= ~(0x1 << 4);
++ tmp &= ~(0xff << 6);
++
++ writel(tmp | (clkval << 6) | (1 << 4), S3C_VIDCON0);
++}
++
++EXPORT_SYMBOL(s3cfb_set_clock);
++
++int s3cfb_init_win(s3c_fb_info_t *fbi, int bpp, int left_x, int top_y, int width, int height, int onoff)
++{
++ s3cfb_onoff_win(fbi, OFF);
++ s3cfb_set_bpp(fbi, bpp);
++ s3cfb_set_win_position(fbi, left_x, top_y, width, height);
++ s3cfb_set_win_size(fbi, width, height);
++ s3cfb_set_fb_size(fbi);
++ s3cfb_onoff_win(fbi, onoff);
++
++ return 0;
++}
++
++int s3cfb_wait_for_vsync(void)
++{
++ int cnt;
++
++ cnt = s3c_vsync_info.count;
++ wait_event_interruptible_timeout(s3c_vsync_info.wait_queue, cnt != s3c_vsync_info.count, HZ / 10);
++
++ return cnt;
++}
++
++static void s3cfb_update_palette(s3c_fb_info_t *fbi, unsigned int regno, unsigned int val)
++{
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ fbi->palette_buffer[regno] = val;
++
++ if (!fbi->palette_ready) {
++ fbi->palette_ready = 1;
++ s3c_palette_win = fbi->win_id;
++ }
++
++ local_irq_restore(flags);
++}
++
++static inline unsigned int s3cfb_chan_to_field(unsigned int chan, struct fb_bitfield bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf.length;
++
++ return chan << bf.offset;
++}
++
++static int s3cfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue, unsigned int transp, struct fb_info *info)
++{
++ s3c_fb_info_t *fbi = (s3c_fb_info_t *)info;
++ unsigned int val = 0;
++
++ switch (fbi->fb.fix.visual) {
++ case FB_VISUAL_TRUECOLOR:
++ if (regno < 16) {
++ unsigned int *pal = fbi->fb.pseudo_palette;
++
++ val = s3cfb_chan_to_field(red, fbi->fb.var.red);
++ val |= s3cfb_chan_to_field(green, fbi->fb.var.green);
++ val |= s3cfb_chan_to_field(blue, fbi->fb.var.blue);
++
++ pal[regno] = val;
++ }
++
++ break;
++
++ case FB_VISUAL_PSEUDOCOLOR:
++ if (regno < 256) {
++// if (info->var.bits_per_pixel == 16) {
++ val = ((red >> 0) & 0xf800);
++ val |= ((green >> 5) & 0x07e0);
++ val |= ((blue >> 11) & 0x001f);
++// } else if (info->var.bits_per_pixel == 24) {
++// val = ((red << 8) & 0xff0000);
++// val |= ((green >> 0) & 0xff00);
++// val |= ((blue >> 8) & 0xff);
++// }
++
++ DPRINTK("index = %d, val = 0x%08x\n", regno, val);
++ s3cfb_update_palette(fbi, regno, val);
++ }
++
++ break;
++
++ default:
++ return 1; /* unknown type */
++ }
++
++ return 0;
++}
++
++/* sysfs export of baclight control */
++static int s3cfb_sysfs_show_lcd_power(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", lcd_power);
++}
++
++static int s3cfb_sysfs_store_lcd_power(struct device *dev, struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ s3cfb_set_lcd_power(1);
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ s3cfb_set_lcd_power(0);
++ else
++ return -EINVAL;
++
++ return len;
++}
++
++static int s3cfb_sysfs_show_backlight_power(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", backlight_power);
++}
++
++static int s3cfb_sysfs_store_backlight_power(struct device *dev, struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ s3cfb_set_backlight_power(1);
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ s3cfb_set_backlight_power(0);
++ else
++ return -EINVAL;
++
++ return len;
++}
++
++static int s3cfb_sysfs_show_backlight_level(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", backlight_level);
++}
++
++static int s3cfb_sysfs_store_backlight_level(struct device *dev, struct device_attribute *attr, const char *buf, size_t len)
++{
++ unsigned long value = simple_strtoul(buf, NULL, 10);
++
++ if (value < s3c_fimd.backlight_min || value > s3c_fimd.backlight_max)
++ return -ERANGE;
++
++ s3cfb_set_backlight_level(value);
++
++ return len;
++}
++
++static DEVICE_ATTR(lcd_power, 0644,
++ s3cfb_sysfs_show_lcd_power,
++ s3cfb_sysfs_store_lcd_power);
++
++static DEVICE_ATTR(backlight_power, 0644,
++ s3cfb_sysfs_show_backlight_power,
++ s3cfb_sysfs_store_backlight_power);
++
++static DEVICE_ATTR(backlight_level, 0644,
++ s3cfb_sysfs_show_backlight_level,
++ s3cfb_sysfs_store_backlight_level);
++
++struct fb_ops s3cfb_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = s3cfb_check_var,
++ .fb_set_par = s3cfb_set_par,
++ .fb_blank = s3cfb_blank,
++ .fb_pan_display = s3cfb_pan_display,
++ .fb_setcolreg = s3cfb_setcolreg,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++ .fb_cursor = soft_cursor,
++ .fb_ioctl = s3cfb_ioctl,
++};
++
++static void s3cfb_init_fbinfo(s3c_fb_info_t *finfo, char *drv_name, int index)
++{
++ int i = 0;
++
++ if (index == 0)
++ s3cfb_init_hw();
++
++ strcpy(finfo->fb.fix.id, drv_name);
++
++ finfo->win_id = index;
++ finfo->fb.fix.type = FB_TYPE_PACKED_PIXELS;
++ finfo->fb.fix.type_aux = 0;
++ finfo->fb.fix.xpanstep = 0;
++ finfo->fb.fix.ypanstep = 1;
++ finfo->fb.fix.ywrapstep = 0;
++ finfo->fb.fix.accel = FB_ACCEL_NONE;
++
++ finfo->fb.fbops = &s3cfb_ops;
++ finfo->fb.flags = FBINFO_FLAG_DEFAULT;
++
++ finfo->fb.pseudo_palette = &finfo->pseudo_pal;
++
++ finfo->fb.var.nonstd = 0;
++ finfo->fb.var.activate = FB_ACTIVATE_NOW;
++ finfo->fb.var.accel_flags = 0;
++ finfo->fb.var.vmode = FB_VMODE_NONINTERLACED;
++
++ finfo->fb.var.xoffset = s3c_fimd.xoffset;
++ finfo->fb.var.yoffset = s3c_fimd.yoffset;
++
++ if (index == 0) {
++ finfo->fb.var.height = s3c_fimd.height;
++ finfo->fb.var.width = s3c_fimd.width;
++
++ finfo->fb.var.xres = s3c_fimd.xres;
++ finfo->fb.var.yres = s3c_fimd.yres;
++
++ finfo->fb.var.xres_virtual = s3c_fimd.xres_virtual;
++ finfo->fb.var.yres_virtual = s3c_fimd.yres_virtual;
++ } else {
++ finfo->fb.var.height = s3c_fimd.osd_height;
++ finfo->fb.var.width = s3c_fimd.osd_width;
++
++ finfo->fb.var.xres = s3c_fimd.osd_xres;
++ finfo->fb.var.yres = s3c_fimd.osd_yres;
++
++ finfo->fb.var.xres_virtual = s3c_fimd.osd_xres_virtual;
++ finfo->fb.var.yres_virtual = s3c_fimd.osd_yres_virtual;
++ }
++
++ finfo->fb.var.bits_per_pixel = s3c_fimd.bpp;
++ finfo->fb.var.pixclock = s3c_fimd.pixclock;
++ finfo->fb.var.hsync_len = s3c_fimd.hsync_len;
++ finfo->fb.var.left_margin = s3c_fimd.left_margin;
++ finfo->fb.var.right_margin = s3c_fimd.right_margin;
++ finfo->fb.var.vsync_len = s3c_fimd.vsync_len;
++ finfo->fb.var.upper_margin = s3c_fimd.upper_margin;
++ finfo->fb.var.lower_margin = s3c_fimd.lower_margin;
++ finfo->fb.var.sync = s3c_fimd.sync;
++ finfo->fb.var.grayscale = s3c_fimd.cmap_grayscale;
++
++ finfo->fb.fix.smem_len = finfo->fb.var.xres_virtual * finfo->fb.var.yres_virtual * s3c_fimd.bytes_per_pixel;
++
++ finfo->fb.fix.line_length = finfo->fb.var.width * s3c_fimd.bytes_per_pixel;
++
++#if !defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) && defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ if (index < 2)
++ finfo->fb.fix.smem_len *= 2;
++#endif
++
++ for (i = 0; i < 256; i++)
++ finfo->palette_buffer[i] = S3C_FB_PALETTE_BUFF_CLEAR;
++}
++
++/*
++ * Probe
++ */
++static int __init s3cfb_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ struct fb_info *fbinfo;
++ s3c_fb_info_t *info;
++
++ char driver_name[] = "s3cfb";
++ int index = 0, ret, size;
++
++ fbinfo = framebuffer_alloc(sizeof(s3c_fb_info_t), &pdev->dev);
++
++ if (!fbinfo)
++ return -ENOMEM;
++
++ platform_set_drvdata(pdev, fbinfo);
++
++ info = fbinfo->par;
++ info->dev = &pdev->dev;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (res == NULL) {
++ dev_err(&pdev->dev, "failed to get memory registers\n");
++ ret = -ENXIO;
++ goto dealloc_fb;
++ }
++
++ size = (res->end - res->start) + 1;
++ info->mem = request_mem_region(res->start, size, pdev->name);
++
++ if (info->mem == NULL) {
++ dev_err(&pdev->dev, "failed to get memory region\n");
++ ret = -ENOENT;
++ goto dealloc_fb;
++ }
++
++ info->io = ioremap(res->start, size);
++
++ if (info->io == NULL) {
++ dev_err(&pdev->dev, "ioremap() of registers failed\n");
++ ret = -ENXIO;
++ goto release_mem;
++ }
++
++ s3cfb_pre_init();
++ s3cfb_set_backlight_power(1);
++ s3cfb_set_lcd_power(1);
++ s3cfb_set_backlight_level(S3C_FB_DEFAULT_BACKLIGHT_LEVEL);
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++ info->clk = clk_get(NULL, "hclkd1");
++#else
++ info->clk = clk_get(NULL, "lcd");
++#endif
++
++ if (!info->clk || IS_ERR(info->clk)) {
++ printk(KERN_INFO "failed to get lcd clock source\n");
++ ret = -ENOENT;
++ goto release_irq;
++ }
++
++ clk_enable(info->clk);
++ printk("S3C_LCD clock got enabled :: %ld.%03ld Mhz\n", PRINT_MHZ(clk_get_rate(info->clk)));
++
++ s3c_vsync_info.count = 0;
++ init_waitqueue_head(&s3c_vsync_info.wait_queue);
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ ret = request_irq(IRQ_S3C2443_LCD3, s3cfb_irq, 0, "s3c-lcd", pdev);
++
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++ ret = request_irq(IRQ_LCD_VSYNC, s3cfb_irq, 0, "s3c-lcd", pdev);
++
++#elif defined(CONFIG_PLAT_S5PC1XX)
++ ret = request_irq(IRQ_LCD0, s3cfb_irq, 0, "s3c-lcd", pdev);
++
++#endif
++
++ if (ret != 0) {
++ printk("Failed to install irq (%d)\n", ret);
++ goto release_irq;
++ }
++
++ msleep(5);
++
++ for (index = 0; index < S3C_FB_NUM; index++) {
++ s3c_fb_info[index].mem = info->mem;
++ s3c_fb_info[index].io = info->io;
++ s3c_fb_info[index].clk = info->clk;
++
++ s3cfb_init_fbinfo(&s3c_fb_info[index], driver_name, index);
++
++ /* Initialize video memory */
++ ret = s3cfb_map_video_memory(&s3c_fb_info[index]);
++
++ if (ret) {
++ printk("Failed to allocate video RAM: %d\n", ret);
++ ret = -ENOMEM;
++ goto release_clock;
++ }
++
++ ret = s3cfb_init_registers(&s3c_fb_info[index]);
++ ret = s3cfb_check_var(&s3c_fb_info[index].fb.var, &s3c_fb_info[index].fb);
++
++ if (index < 2){
++ if (fb_alloc_cmap(&s3c_fb_info[index].fb.cmap, 256, 0) < 0)
++ goto dealloc_fb;
++ } else {
++ if (fb_alloc_cmap(&s3c_fb_info[index].fb.cmap, 16, 0) < 0)
++ goto dealloc_fb;
++ }
++
++ ret = register_framebuffer(&s3c_fb_info[index].fb);
++
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to register framebuffer device: %d\n", ret);
++ goto free_video_memory;
++ }
++
++ printk(KERN_INFO "fb%d: %s frame buffer device\n", s3c_fb_info[index].fb.node, s3c_fb_info[index].fb.fix.id);
++
++ }
++
++ /* create device files */
++ ret = device_create_file(&(pdev->dev), &dev_attr_backlight_power);
++
++ if (ret < 0)
++ printk(KERN_WARNING "s3cfb: failed to add entries\n");
++
++ ret = device_create_file(&(pdev->dev), &dev_attr_backlight_level);
++
++ if (ret < 0)
++ printk(KERN_WARNING "s3cfb: failed to add entries\n");
++
++ ret = device_create_file(&(pdev->dev), &dev_attr_lcd_power);
++
++ if (ret < 0)
++ printk(KERN_WARNING "s3cfb: failed to add entries\n");
++
++ return 0;
++
++free_video_memory:
++ s3cfb_unmap_video_memory(&s3c_fb_info[index]);
++
++release_clock:
++ clk_disable(info->clk);
++ clk_put(info->clk);
++
++release_mem:
++ release_resource(info->mem);
++ kfree(info->mem);
++
++release_irq:
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ free_irq(IRQ_S3C2443_LCD3, &info);
++
++#elif defined(CONFIG_CPU_S3C6400)|| defined(CONFIG_CPU_S3C6410)
++ free_irq(IRQ_LCD_VSYNC, &info);
++#endif
++
++dealloc_fb:
++ framebuffer_release(&s3c_fb_info[index].fb);
++ return ret;
++}
++
++/*
++ * Remove
++ */
++static int s3cfb_remove(struct platform_device *pdev)
++{
++ struct fb_info *fbinfo = platform_get_drvdata(pdev);
++ s3c_fb_info_t *info = fbinfo->par;
++ int index = 0, irq;
++
++ s3cfb_stop_lcd();
++ msleep(1);
++
++ if (info->clk) {
++ clk_disable(info->clk);
++ clk_put(info->clk);
++ info->clk = NULL;
++ }
++
++ irq = platform_get_irq(pdev, 0);
++ release_resource(info->mem);
++
++ for (index = 0; index < S3C_FB_NUM; index++) {
++ s3cfb_unmap_video_memory((s3c_fb_info_t *) &s3c_fb_info[index]);
++ free_irq(irq, &s3c_fb_info[index]);
++ unregister_framebuffer(&info[index].fb);
++ }
++
++ return 0;
++}
++
++static struct platform_driver s3cfb_driver = {
++ .probe = s3cfb_probe,
++ .remove = s3cfb_remove,
++ .suspend = s3cfb_suspend,
++ .resume = s3cfb_resume,
++ .driver = {
++ .name = "s3c-lcd",
++ .owner = THIS_MODULE,
++ },
++};
++
++int __devinit s3cfb_init(void)
++{
++ return platform_driver_register(&s3cfb_driver);
++}
++static void __exit s3cfb_cleanup(void)
++{
++ platform_driver_unregister(&s3cfb_driver);
++}
++
++module_init(s3cfb_init);
++module_exit(s3cfb_cleanup);
++
++MODULE_AUTHOR("Jinsung Yang");
++MODULE_DESCRIPTION("S3C Framebuffer Driver");
++MODULE_LICENSE("GPL");
++
+diff --git a/drivers/video/s3c/s3cfb.h b/drivers/video/s3c/s3cfb.h
+new file mode 100644
+index 0000000..cf66ec4
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb.h
+@@ -0,0 +1,505 @@
++/*
++ * drivers/video/s3c/s3cfb.h
++ *
++ * $Id: s3cfb.h,v 1.26 2008/09/18 07:27:06 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#ifndef _S3CFB_H_
++#define _S3CFB_H_
++
++#include <linux/interrupt.h>
++#if defined(CONFIG_S3C6410_PWM)
++extern int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned long g_tcmp);
++#endif
++
++/*
++ * Debug macros
++ */
++#define DEBUG 0
++
++#if DEBUG
++#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
++#else
++#define DPRINTK(fmt, args...)
++#endif
++
++/*
++ * Definitions
++ */
++#ifndef MHZ
++#define MHZ (1000 * 1000)
++#endif
++
++#define ON 1
++#define OFF 0
++
++#define S3C_FB_PIXEL_BPP_8 8
++#define S3C_FB_PIXEL_BPP_16 16 /* RGB 5-6-5 format for SMDK EVAL BOARD */
++#define S3C_FB_PIXEL_BPP_24 24 /* RGB 8-8-8 format for SMDK EVAL BOARD */
++
++#define S3C_FB_OUTPUT_RGB 0
++#define S3C_FB_OUTPUT_TV 1
++#define S3C_FB_OUTPUT_I80_LDI0 2
++#define S3C_FB_OUTPUT_I80_LDI1 3
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C_FB_MAX_NUM 2
++
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#define S3C_FB_MAX_NUM 5
++
++#else
++#define S3C_FB_MAX_NUM 1
++
++#endif
++
++#define S3C_FB_PALETTE_BUFF_CLEAR (0x80000000) /* entry is clear/invalid */
++#define S3C_FB_COLOR_KEY_DIR_BG 0
++#define S3C_FB_COLOR_KEY_DIR_FG 1
++#define S3C_FB_DEFAULT_BACKLIGHT_LEVEL 2
++#define S3C_FB_MAX_DISPLAY_OFFSET 200
++#define S3C_FB_DEFAULT_DISPLAY_OFFSET 100
++#define S3C_FB_MAX_ALPHA_LEVEL 0xf
++#define S3C_FB_MAX_BRIGHTNESS 90
++#define S3C_FB_DEFAULT_BRIGHTNESS 4
++#define S3C_FB_VS_SET 12
++#define S3C_FB_VS_MOVE_LEFT 15
++#define S3C_FB_VS_MOVE_RIGHT 16
++#define S3C_FB_VS_MOVE_UP 17
++#define S3C_FB_VS_MOVE_DOWN 18
++
++/*
++ * macros
++ */
++#define PRINT_MHZ(m) ((m) / MHZ), ((m / 1000) % 1000)
++#define FB_MAX_NUM(x, y) ((x) > (y) ? (y) : (x))
++#define S3C_FB_NUM FB_MAX_NUM(S3C_FB_MAX_NUM, CONFIG_FB_S3C_NUM)
++
++/*
++ * ioctls
++ */
++#define S3C_FB_GET_BRIGHTNESS _IOR ('F', 1, unsigned int)
++#define S3C_FB_SET_BRIGHTNESS _IOW ('F', 2, unsigned int)
++#define S3C_FB_WIN_ON _IOW ('F', 10, unsigned int)
++#define S3C_FB_WIN_OFF _IOW ('F', 11, unsigned int)
++#define FBIO_WAITFORVSYNC _IOW ('F', 32, unsigned int)
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++#define S3C_FB_VS_START _IO ('F', 103)
++#define S3C_FB_VS_STOP _IO ('F', 104)
++#define S3C_FB_VS_SET_INFO _IOW ('F', 105, s3c_vs_info_t)
++#define S3C_FB_VS_MOVE _IOW ('F', 106, unsigned int)
++#endif
++
++#define S3C_FB_OSD_START _IO ('F', 201)
++#define S3C_FB_OSD_STOP _IO ('F', 202)
++#define S3C_FB_OSD_ALPHA_UP _IO ('F', 203)
++#define S3C_FB_OSD_ALPHA_DOWN _IO ('F', 204)
++#define S3C_FB_OSD_MOVE_LEFT _IO ('F', 205)
++#define S3C_FB_OSD_MOVE_RIGHT _IO ('F', 206)
++#define S3C_FB_OSD_MOVE_UP _IO ('F', 207)
++#define S3C_FB_OSD_MOVE_DOWN _IO ('F', 208)
++#define S3C_FB_OSD_SET_INFO _IOW ('F', 209, s3c_win_info_t)
++#define S3C_FB_OSD_ALPHA_SET _IOW ('F', 210, unsigned int)
++#define S3C_FB_OSD_ALPHA0_SET _IOW ('F', 211, unsigned int)
++#define S3C_FB_OSD_ALPHA_MODE _IOW ('F', 212, unsigned int)
++
++#define S3C_FB_COLOR_KEY_START _IO ('F', 300)
++#define S3C_FB_COLOR_KEY_STOP _IO ('F', 301)
++#define S3C_FB_COLOR_KEY_ALPHA_START _IO ('F', 302)
++#define S3C_FB_COLOR_KEY_ALPHA_STOP _IO ('F', 303)
++#define S3C_FB_COLOR_KEY_SET_INFO _IOW ('F', 304, s3c_color_key_info_t)
++#define S3C_FB_COLOR_KEY_VALUE _IOW ('F', 305, s3c_color_val_info_t)
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++#define S3C_FB_GET_NUM _IOWR('F', 306, unsigned int)
++#endif
++
++#define S3C_FB_GET_INFO _IOR ('F', 307, s3c_fb_dma_info_t)
++#define S3C_FB_CHANGE_REQ _IOW ('F', 308, int)
++#define S3C_FB_SET_VSYNC_INT _IOW ('F', 309, int)
++#define S3C_FB_SET_NEXT_FB_INFO _IOW ('F', 320, s3c_fb_next_info_t)
++#define S3C_FB_GET_CURR_FB_INFO _IOR ('F', 321, s3c_fb_next_info_t)
++
++#define S3C_FB_RELEASE_DEFAULT_FB _IO ('F', 322)
++
++
++/*
++ * structures
++ */
++typedef struct {
++ int bpp;
++ int left_x;
++ int top_y;
++ int width;
++ int height;
++} s3c_win_info_t;
++
++typedef struct {
++ int width;
++ int height;
++ int bpp;
++ int offset;
++ int v_width;
++ int v_height;
++} s3c_vs_info_t;
++
++typedef struct {
++ int direction;
++ unsigned int compkey_red;
++ unsigned int compkey_green;
++ unsigned int compkey_blue;
++} s3c_color_key_info_t;
++
++typedef struct {
++ unsigned int colval_red;
++ unsigned int colval_green;
++ unsigned int colval_blue;
++} s3c_color_val_info_t;
++
++typedef struct {
++ wait_queue_head_t wait_queue;
++ int count;
++} s3c_vsync_info_t;
++
++typedef struct
++{
++ dma_addr_t map_dma_f1;
++ dma_addr_t map_dma_f2;
++} s3c_fb_dma_info_t;
++
++typedef struct {
++ __u32 phy_start_addr;
++ __u32 xres; /* visible resolution*/
++ __u32 yres;
++ __u32 xres_virtual; /* virtual resolution*/
++ __u32 yres_virtual;
++ __u32 xoffset; /* offset from virtual to visible */
++ __u32 yoffset; /* resolution */
++ __u32 lcd_offset_x;
++ __u32 lcd_offset_y;
++} s3c_fb_next_info_t;
++
++typedef struct {
++ struct fb_bitfield red;
++ struct fb_bitfield green;
++ struct fb_bitfield blue;
++ struct fb_bitfield transp;
++} s3c_fb_rgb_t;
++
++const static s3c_fb_rgb_t s3c_fb_rgb_8 = {
++ .red = {.offset = 0, .length = 8,},
++ .green = {.offset = 0, .length = 8,},
++ .blue = {.offset = 0, .length = 8,},
++ .transp = {.offset = 0, .length = 0,},
++};
++
++const static s3c_fb_rgb_t s3c_fb_rgb_16 = {
++ .red = {.offset = 11, .length = 5,},
++ .green = {.offset = 5, .length = 6,},
++ .blue = {.offset = 0, .length = 5,},
++ .transp = {.offset = 0, .length = 0,},
++};
++
++const static s3c_fb_rgb_t s3c_fb_rgb_24 = {
++ .red = {.offset = 16, .length = 8,},
++ .green = {.offset = 8, .length = 8,},
++ .blue = {.offset = 0, .length = 8,},
++ .transp = {.offset = 0, .length = 0,},
++};
++
++const static s3c_fb_rgb_t s3c_fb_rgb_32 = {
++ .red = {.offset = 16, .length = 8,},
++ .green = {.offset = 8, .length = 8,},
++ .blue = {.offset = 0, .length = 8,},
++ .transp = {.offset = 24, .length = 8,},
++};
++
++typedef struct {
++ struct fb_info fb;
++ struct device *dev;
++
++ struct clk *clk;
++
++ struct resource *mem;
++ void __iomem *io;
++
++ unsigned int win_id;
++
++ unsigned int max_bpp;
++ unsigned int max_xres;
++ unsigned int max_yres;
++
++ /* raw memory addresses */
++ dma_addr_t map_dma_f1; /* physical */
++ u_char * map_cpu_f1; /* virtual */
++ unsigned int map_size_f1;
++
++ /* addresses of pieces placed in raw buffer */
++ u_char * screen_cpu_f1; /* virtual address of frame buffer */
++ dma_addr_t screen_dma_f1; /* physical address of frame buffer */
++
++ /* raw memory addresses */
++ dma_addr_t map_dma_f2; /* physical */
++ u_char * map_cpu_f2; /* virtual */
++ unsigned int map_size_f2;
++
++ /* addresses of pieces placed in raw buffer */
++ u_char * screen_cpu_f2; /* virtual address of frame buffer */
++ dma_addr_t screen_dma_f2; /* physical address of frame buffer */
++
++ unsigned int palette_ready;
++ unsigned int fb_change_ready;
++
++ /* keep these registers in case we need to re-write palette */
++ unsigned int palette_buffer[256];
++ unsigned int pseudo_pal[16];
++
++ unsigned int lcd_offset_x;
++ unsigned int lcd_offset_y;
++ unsigned int next_fb_info_change_req;
++ s3c_fb_next_info_t next_fb_info;
++} s3c_fb_info_t;
++
++typedef struct {
++
++ /* Screen size */
++ int width;
++ int height;
++
++ /* Screen info */
++ int xres;
++ int yres;
++
++ /* Virtual Screen info */
++ int xres_virtual;
++ int yres_virtual;
++ int xoffset;
++ int yoffset;
++
++ /* OSD Screen size */
++ int osd_width;
++ int osd_height;
++
++ /* OSD Screen info */
++ int osd_xres;
++ int osd_yres;
++
++ /* OSD Screen info */
++ int osd_xres_virtual;
++ int osd_yres_virtual;
++
++ int bpp;
++ int bytes_per_pixel;
++ unsigned long pixclock;
++
++ int hsync_len;
++ int left_margin;
++ int right_margin;
++ int vsync_len;
++ int upper_margin;
++ int lower_margin;
++ int sync;
++
++ int cmap_grayscale:1;
++ int cmap_inverse:1;
++ int cmap_static:1;
++ int unused:29;
++
++ /* lcd configuration registers */
++ unsigned long lcdcon1;
++ unsigned long lcdcon2;
++
++ unsigned long lcdcon3;
++ unsigned long lcdcon4;
++ unsigned long lcdcon5;
++
++ /* GPIOs */
++ unsigned long gpcup;
++ unsigned long gpcup_mask;
++ unsigned long gpccon;
++ unsigned long gpccon_mask;
++ unsigned long gpdup;
++ unsigned long gpdup_mask;
++ unsigned long gpdcon;
++ unsigned long gpdcon_mask;
++
++ /* lpc3600 control register */
++ unsigned long lpcsel;
++ unsigned long lcdtcon1;
++ unsigned long lcdtcon2;
++ unsigned long lcdtcon3;
++ unsigned long lcdosd1;
++ unsigned long lcdosd2;
++ unsigned long lcdosd3;
++ unsigned long lcdsaddrb1;
++ unsigned long lcdsaddrb2;
++ unsigned long lcdsaddrf1;
++ unsigned long lcdsaddrf2;
++ unsigned long lcdeaddrb1;
++ unsigned long lcdeaddrb2;
++ unsigned long lcdeaddrf1;
++ unsigned long lcdeaddrf2;
++ unsigned long lcdvscrb1;
++ unsigned long lcdvscrb2;
++ unsigned long lcdvscrf1;
++ unsigned long lcdvscrf2;
++ unsigned long lcdintcon;
++ unsigned long lcdkeycon;
++ unsigned long lcdkeyval;
++ unsigned long lcdbgcon;
++ unsigned long lcdfgcon;
++ unsigned long lcddithcon;
++
++ unsigned long vidcon0;
++ unsigned long vidcon1;
++ unsigned long vidtcon0;
++ unsigned long vidtcon1;
++ unsigned long vidtcon2;
++ unsigned long vidtcon3;
++ unsigned long wincon0;
++ unsigned long wincon2;
++ unsigned long wincon1;
++ unsigned long wincon3;
++ unsigned long wincon4;
++
++ unsigned long vidosd0a;
++ unsigned long vidosd0b;
++ unsigned long vidosd0c;
++ unsigned long vidosd1a;
++ unsigned long vidosd1b;
++ unsigned long vidosd1c;
++ unsigned long vidosd1d;
++ unsigned long vidosd2a;
++ unsigned long vidosd2b;
++ unsigned long vidosd2c;
++ unsigned long vidosd2d;
++ unsigned long vidosd3a;
++ unsigned long vidosd3b;
++ unsigned long vidosd3c;
++ unsigned long vidosd4a;
++ unsigned long vidosd4b;
++ unsigned long vidosd4c;
++
++ unsigned long vidw00add0b0;
++ unsigned long vidw00add0b1;
++ unsigned long vidw01add0;
++ unsigned long vidw01add0b0;
++ unsigned long vidw01add0b1;
++
++ unsigned long vidw00add1b0;
++ unsigned long vidw00add1b1;
++ unsigned long vidw01add1;
++ unsigned long vidw01add1b0;
++ unsigned long vidw01add1b1;
++
++ unsigned long vidw00add2b0;
++ unsigned long vidw00add2b1;
++
++ unsigned long vidw02add0;
++ unsigned long vidw03add0;
++ unsigned long vidw04add0;
++
++ unsigned long vidw02add1;
++ unsigned long vidw03add1;
++ unsigned long vidw04add1;
++ unsigned long vidw00add2;
++ unsigned long vidw01add2;
++ unsigned long vidw02add2;
++ unsigned long vidw03add2;
++ unsigned long vidw04add2;
++
++ unsigned long vidintcon;
++ unsigned long vidintcon0;
++ unsigned long vidintcon1;
++ unsigned long w1keycon0;
++ unsigned long w1keycon1;
++ unsigned long w2keycon0;
++ unsigned long w2keycon1;
++ unsigned long w3keycon0;
++ unsigned long w3keycon1;
++ unsigned long w4keycon0;
++ unsigned long w4keycon1;
++
++ unsigned long win0map;
++ unsigned long win1map;
++ unsigned long win2map;
++ unsigned long win3map;
++ unsigned long win4map;
++
++ unsigned long wpalcon;
++ unsigned long dithmode;
++ unsigned long intclr0;
++ unsigned long intclr1;
++ unsigned long intclr2;
++
++ unsigned long win0pal;
++ unsigned long win1pal;
++
++ /* backlight info */
++ int backlight_min;
++ int backlight_max;
++ int backlight_default;
++
++ /* utility functions */
++ void (*set_backlight_power)(int);
++ void (*set_lcd_power)(int);
++ void (*set_brightness)(int);
++ int (*map_video_memory)(s3c_fb_info_t *);
++ int (*unmap_video_memory)(s3c_fb_info_t *);
++}s3c_fimd_info_t;
++
++/*
++ * Externs
++ */
++extern s3c_fb_info_t s3c_fb_info[];
++extern s3c_fimd_info_t s3c_fimd;
++
++extern s3c_vsync_info_t s3c_vsync_info;
++extern int s3c_vs_offset;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++extern s3c_vs_info_t s3c_vs_info;
++#endif
++
++extern int soft_cursor(struct fb_info *info, struct fb_cursor *cursor);
++extern int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg);
++extern void s3cfb_activate_var(s3c_fb_info_t *fbi, struct fb_var_screeninfo *var);
++extern void s3cfb_set_fb_addr(s3c_fb_info_t *fbi);
++extern void s3cfb_init_hw(void);
++extern irqreturn_t s3cfb_irq(int irqno, void *param);
++extern int s3cfb_init_registers(s3c_fb_info_t *fbi);
++extern int s3cfb_set_win_position(s3c_fb_info_t *fbi, int left_x, int top_y, int width, int height);
++extern int s3cfb_set_win_size(s3c_fb_info_t *fbi, int width, int height);
++extern int s3cfb_set_fb_size(s3c_fb_info_t *fbi);
++extern int s3cfb_set_vs_info(s3c_vs_info_t vs_info);
++extern int s3cfb_wait_for_vsync(void);
++extern int s3cfb_onoff_color_key(s3c_fb_info_t *fbi, int onoff);
++extern int s3cfb_onoff_color_key_alpha(s3c_fb_info_t *fbi, int onoff);
++extern int s3cfb_set_color_key_registers(s3c_fb_info_t *fbi, s3c_color_key_info_t colkey_info);
++extern int s3cfb_set_color_value(s3c_fb_info_t *fbi, s3c_color_val_info_t colval_info);
++extern int s3cfb_init_win(s3c_fb_info_t *fbi, int bpp, int left_x, int top_y, int width, int height, int onoff);
++extern int s3cfb_onoff_win(s3c_fb_info_t *fbi, int onoff);
++extern void s3cfb_set_gpio(void);
++extern void s3cfb_start_lcd(void);
++extern void s3cfb_stop_lcd(void);
++extern int s3cfb_suspend(struct platform_device *dev, pm_message_t state);
++extern int s3cfb_resume(struct platform_device *dev);
++extern void s3cfb_spi_lcd_den(int ch, int value);
++extern void s3cfb_spi_lcd_dseri(int ch, int value);
++extern void s3cfb_spi_lcd_dclk(int ch, int value);
++extern void s3cfb_spi_set_lcd_data(int ch);
++extern void s3cfb_pre_init(void);
++extern void s3cfb_unmap_video_memory(s3c_fb_info_t *fbi);
++
++#endif
++
+diff --git a/drivers/video/s3c/s3cfb_fimd3x.c b/drivers/video/s3c/s3cfb_fimd3x.c
+new file mode 100644
+index 0000000..3555e52
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_fimd3x.c
+@@ -0,0 +1,840 @@
++/*
++ * drivers/video/s3c/s3c24xxfb.c
++ *
++ * $Id: s3cfb_fimd3x.c,v 1.11 2008/09/18 07:27:06 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/dma-mapping.h>
++#include <linux/string.h>
++#include <linux/ioctl.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#include <asm/mach/map.h>
++#include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#if defined(CONFIG_PM)
++#include <asm/plat-s3c24xx/pm.h>
++#endif
++
++#include "s3cfb.h"
++
++int s3c_vs_offset = S3C_FB_DEFAULT_DISPLAY_OFFSET;
++int s3c_osd_alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++int s3c_display_brightness = S3C_FB_DEFAULT_BRIGHTNESS;
++static int s3c_palette_win;
++
++s3c_fimd_info_t s3c_fimd = {
++ .vidcon0 = S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_VCLKEN_ENABLE | S3C_VIDCON0_CLKSEL_F_HCLK,
++
++#if defined (CONFIG_FB_S3C_BPP_8)
++ .wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL,
++ .wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .bpp = S3C_FB_PIXEL_BPP_8,
++ .bytes_per_pixel = 1,
++ .wpalcon = S3C_WPALCON_W0PAL_16BIT,
++
++#elif defined (CONFIG_FB_S3C_BPP_16)
++ .wincon0 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565,
++ .wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .bpp = S3C_FB_PIXEL_BPP_16,
++ .bytes_per_pixel = 2,
++ .wpalcon = S3C_WPALCON_W0PAL_16BIT,
++
++#elif defined (CONFIG_FB_S3C_BPP_24)
++ .wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888,
++ .wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .bpp = S3C_FB_PIXEL_BPP_24,
++ .bytes_per_pixel = 4,
++ .wpalcon = S3C_WPALCON_W0PAL_24BIT,
++#endif
++
++ .vidosd1c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++ .vidintcon = S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_ENABLE | S3C_VIDINTCON0_INTEN_ENABLE,
++
++ .xoffset = 0,
++ .yoffset = 0,
++
++ .w1keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w1keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w2keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w2keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w3keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w3keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w4keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w4keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++
++ .sync = 0,
++ .cmap_static = 1,
++};
++
++#if defined(CONFIG_S3C2450_PWM) || defined(CONFIG_S3C2416_PWM)
++void s3cfb_set_brightness(int val)
++{
++ int channel = 3; /* must use channel-3 */
++ int usec = 0; /* don't care value */
++ unsigned long tcnt = 1000;
++ unsigned long tcmp = 0;
++
++ if (val < 0)
++ val = 0;
++
++ if (val > S3C_FB_MAX_BRIGHTNESS)
++ val = S3C_FB_MAX_BRIGHTNESS;
++
++ s3c_display_brightness = val;
++ tcmp = val * 50;
++
++ s3c2450_timer_setup (channel, usec, tcnt, tcmp);
++}
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++
++static void s3cfb_change_buff(int req_win, int req_fb)
++{
++ /* Software-based trigger */
++ writel((1 << 0), S3C_CPUTRIGCON2);
++}
++
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++static int s3cfb_set_vs_registers(int vs_cmd)
++{
++ int page_width, offset;
++ int shift_value;
++
++ page_width = s3c_fimd.xres * s3c_fimd.bytes_per_pixel;
++ offset = (s3c_fimd.xres_virtual - s3c_fimd.xres) * s3c_fimd.bytes_per_pixel;
++
++ switch (vs_cmd){
++ case S3C_FB_VS_SET:
++ /* size of buffer */
++ s3c_fimd.vidw00add2b0 = S3C_VIDWxxADD2_OFFSIZE_F(offset) | S3C_VIDWxxADD2_PAGEWIDTH_F(page_width);
++ s3c_fimd.vidw00add2b1 = S3C_VIDWxxADD2_OFFSIZE_F(offset) | S3C_VIDWxxADD2_PAGEWIDTH_F(page_width);
++
++ writel(s3c_fimd.vidw00add2b0, S3C_VIDW00ADD2B0);
++ writel(s3c_fimd.vidw00add2b1, S3C_VIDW00ADD2B1);
++ break;
++
++ case S3C_FB_VS_MOVE_LEFT:
++ if (s3c_fimd.xoffset < s3c_vs_offset)
++ shift_value = s3c_fimd.xoffset;
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.xoffset -= shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 - (s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 - (s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_RIGHT:
++ if ((s3c_vs_info.v_width - (s3c_fimd.xoffset + s3c_vs_info.width)) < (s3c_vs_offset))
++ shift_value = s3c_vs_info.v_width - (s3c_fimd.xoffset + s3c_vs_info.width);
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.xoffset += shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 + (s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 + (s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_UP:
++ if (s3c_fimd.yoffset < s3c_vs_offset)
++ shift_value = s3c_fimd.yoffset;
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.yoffset -= shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 - (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 - (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_DOWN:
++ if ((s3c_vs_info.v_height - (s3c_fimd.yoffset + s3c_vs_info.height)) < (s3c_vs_offset))
++ shift_value = s3c_vs_info.v_height - (s3c_fimd.yoffset + s3c_vs_info.height);
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.yoffset += shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 + (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 + (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ /* End address */
++ s3c_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(s3c_fimd.vidw00add0b0 + (page_width + offset) * (s3c_fimd.yres));
++ s3c_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(s3c_fimd.vidw00add0b1 + (page_width + offset) * (s3c_fimd.yres));
++
++ writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ writel(s3c_fimd.vidw00add0b1, S3C_VIDW00ADD0B1);
++ writel(s3c_fimd.vidw00add1b0, S3C_VIDW00ADD1B0);
++ writel(s3c_fimd.vidw00add1b1, S3C_VIDW00ADD1B1);
++
++ return 0;
++}
++#endif
++
++void s3cfb_write_palette(s3c_fb_info_t *fbi)
++{
++ unsigned int i;
++ unsigned long ent;
++
++ fbi->palette_ready = 0;
++
++ writel((s3c_fimd.wpalcon | S3C_WPALCON_PALUPDATEEN), S3C_WPALCON);
++
++ for (i = 0; i < 256; i++) {
++ if ((ent = fbi->palette_buffer[i]) == S3C_FB_PALETTE_BUFF_CLEAR)
++ continue;
++
++ writel(ent, S3C_TFTPAL0(i));
++
++ /* it seems the only way to know exactly
++ * if the palette wrote ok, is to check
++ * to see if the value verifies ok
++ */
++ if (readl(S3C_TFTPAL0(i)) == ent) {
++ fbi->palette_buffer[i] = S3C_FB_PALETTE_BUFF_CLEAR;
++ } else {
++ fbi->palette_ready = 1; /* retry */
++ printk("Retry writing into the palette\n");
++ }
++ }
++
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++}
++
++irqreturn_t s3cfb_irq(int irqno, void *param)
++{
++ if (s3c_fb_info[s3c_palette_win].palette_ready)
++ s3cfb_write_palette(&s3c_fb_info[s3c_palette_win]);
++
++ s3c_vsync_info.count++;
++ wake_up_interruptible(&s3c_vsync_info.wait_queue);
++
++ return IRQ_HANDLED;
++}
++
++int s3cfb_init_registers(s3c_fb_info_t *fbi)
++{
++ struct clk *lcd_clock;
++ struct fb_var_screeninfo *var = &fbi->fb.var;
++ unsigned long flags = 0, page_width = 0, offset = 0;
++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1;
++ unsigned long video_phy_temp_f2 = fbi->screen_dma_f2;
++ int win_num = fbi->win_id;
++
++ /* Initialise LCD with values from hare */
++ local_irq_save(flags);
++
++ page_width = var->xres * s3c_fimd.bytes_per_pixel;
++ offset = (var->xres_virtual - var->xres) * s3c_fimd.bytes_per_pixel;
++
++ if (win_num == 0) {
++ s3c_fimd.vidcon0 = s3c_fimd.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE);
++ writel(s3c_fimd.vidcon0, S3C_VIDCON0);
++
++ lcd_clock = clk_get(NULL, "lcd");
++ s3c_fimd.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int) ((clk_get_rate(lcd_clock) / s3c_fimd.pixclock) - 1));
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ offset = 0;
++ s3c_fimd.vidw00add0b0 = video_phy_temp_f1;
++ s3c_fimd.vidw00add0b1 = video_phy_temp_f2;
++ s3c_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres));
++ s3c_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres));
++#endif
++
++ writel(video_phy_temp_f2, S3C_VIDW00ADD0B1);
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1);
++ writel(S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)), S3C_VIDW00ADD2B1);
++ }
++
++ writel(video_phy_temp_f1, S3C_VIDW00ADD0B0 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)), S3C_VIDW00ADD2B0 + (0x08 * win_num));
++
++ switch (win_num) {
++ case 0:
++ writel(s3c_fimd.wincon0, S3C_WINCON0);
++ writel(s3c_fimd.vidcon0, S3C_VIDCON0);
++ writel(s3c_fimd.vidcon1, S3C_VIDCON1);
++ writel(s3c_fimd.vidtcon0, S3C_VIDTCON0);
++ writel(s3c_fimd.vidtcon1, S3C_VIDTCON1);
++ writel(s3c_fimd.vidtcon2, S3C_VIDTCON2);
++ writel(s3c_fimd.vidintcon, S3C_VIDINTCON);
++ writel(s3c_fimd.vidosd0a, S3C_VIDOSD0A);
++ writel(s3c_fimd.vidosd0b, S3C_VIDOSD0B);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, ON);
++ break;
++
++ case 1:
++ writel(s3c_fimd.wincon1, S3C_WINCON1);
++ writel(s3c_fimd.vidosd1a, S3C_VIDOSD1A);
++ writel(s3c_fimd.vidosd1b, S3C_VIDOSD1B);
++ writel(s3c_fimd.vidosd1c, S3C_VIDOSD1C);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++ }
++
++ local_irq_restore(flags);
++
++ return 0;
++ }
++
++void s3cfb_activate_var(s3c_fb_info_t *fbi, struct fb_var_screeninfo *var)
++{
++ DPRINTK("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ s3c_fimd.wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_8;
++ s3c_fimd.bytes_per_pixel = 1;
++ s3c_fimd.wpalcon = S3C_WPALCON_W0PAL_24BIT;
++ break;
++
++ case 16:
++ s3c_fimd.wincon0 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_16;
++ s3c_fimd.bytes_per_pixel = 2;
++ break;
++
++ case 24:
++ s3c_fimd.wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_24;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++
++ case 32:
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++ }
++
++ /* write new registers */
++ writel(s3c_fimd.wincon0, S3C_WINCON0);
++ writel(s3c_fimd.wincon1, S3C_WINCON1);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++ writel(s3c_fimd.vidcon0 | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
++}
++
++/* JJNAHM comment.
++ * We had some problems related to frame buffer address.
++ * We used 2 frame buffers (FB0 and FB1) and GTK used FB1.
++ * When GTK launched, GTK set FB0's address to FB1's address.
++ * (GTK calls s3c_fb_pan_display() and then it calls this s3c_fb_set_lcdaddr())
++ * Even though fbi->win_id is not 0, above original codes set ONLY FB0's address.
++ * So, I modified the codes like below.
++ * It works by fbi->win_id value.
++ * Below codes are not verified yet
++ * and there are nothing about Double buffering features
++ */
++void s3cfb_set_fb_addr(s3c_fb_info_t *fbi)
++{
++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1;
++ unsigned long start_address, end_address;
++ unsigned int start;
++
++ start = fbi->fb.fix.line_length * fbi->fb.var.yoffset;
++
++ /* for buffer start address and end address */
++ start_address = video_phy_temp_f1 + start;
++ end_address = start_address + (fbi->fb.fix.line_length * fbi->fb.var.yres);
++
++ switch (fbi->win_id)
++ {
++ case 0:
++ s3c_fimd.vidw00add0b0 = start_address;
++ s3c_fimd.vidw00add1b0 = end_address;
++ __raw_writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ __raw_writel(s3c_fimd.vidw00add1b0, S3C_VIDW00ADD1B0);
++ break;
++
++ case 1:
++ s3c_fimd.vidw01add0 = start_address;
++ s3c_fimd.vidw01add1 = end_address;
++ __raw_writel(s3c_fimd.vidw01add0, S3C_VIDW01ADD0);
++ __raw_writel(s3c_fimd.vidw01add1, S3C_VIDW01ADD1);
++ break;
++
++ }
++}
++
++static int s3cfb_set_alpha_level(s3c_fb_info_t *fbi, unsigned int level)
++{
++ unsigned long alpha_val;
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support alpha blending.\n");
++ return -1;
++ }
++
++ alpha_val = S3C_VIDOSDxC_ALPHA1_B(level) | S3C_VIDOSDxC_ALPHA1_G(level) | S3C_VIDOSDxC_ALPHA1_R(level);
++ writel(alpha_val, S3C_VIDOSD1C);
++
++ return 0;
++}
++
++#if 0
++static int s3cfb_set_alpha_mode(s3c_fb_info_t *fbi, int mode, int level)
++{
++ unsigned long alpha_val;
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support alpha blending.\n");
++ return -1;
++ }
++
++ switch (mode) {
++ case 0: /* Plane Blending */
++ writel(readl(S3C_WINCON0 + (0x04 * win_num)) | S3C_WINCONx_BLD_PIX_PLANE, S3C_WINCON0 + (0x04 * win_num));
++ break;
++
++ case 1: /* Pixel Blending & chroma(color) key */
++ writel(readl(S3C_WINCON0 + (0x04 * win_num)) | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_0, S3C_WINCON0 + (0x04 * win_num));
++ break;
++ }
++
++ s3c_osd_alpha_level = level;
++ alpha_val = S3C_VIDOSDxC_ALPHA1_B(s3c_osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(s3c_osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_R(s3c_osd_alpha_level);
++ writel(alpha_val, S3C_VIDOSD1C);
++
++ return 0;
++}
++#endif
++
++int s3cfb_set_win_position(s3c_fb_info_t *fbi, int left_x, int top_y, int width, int height)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++
++ writel(S3C_VIDOSDxA_OSD_LTX_F(left_x) | S3C_VIDOSDxA_OSD_LTY_F(top_y), S3C_VIDOSD0A + (0x0c * win_num));
++ writel(S3C_VIDOSDxB_OSD_RBX_F(width - 1 + left_x) | S3C_VIDOSDxB_OSD_RBY_F(height - 1 + top_y), S3C_VIDOSD0B + (0x0c * win_num));
++
++ var->xoffset = left_x;
++ var->yoffset = top_y;
++
++ return 0;
++}
++
++int s3cfb_set_win_size(s3c_fb_info_t *fbi, int width, int height)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++
++ var->xres = width;
++ var->yres = height;
++ var->xres_virtual = width;
++ var->yres_virtual = height;
++
++ return 0;
++}
++
++int s3cfb_set_fb_size(s3c_fb_info_t *fbi)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++ unsigned long offset = 0;
++ unsigned long page_width = 0;
++ unsigned long fb_size = 0;
++
++ page_width = var->xres * s3c_fimd.bytes_per_pixel;
++ offset = (var->xres_virtual - var->xres) * s3c_fimd.bytes_per_pixel;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ if (win_num == 0)
++ offset=0;
++#endif
++
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B0 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num));
++
++ if (win_num == 1)
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B1 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num));
++
++ /* size of frame buffer */
++ fb_size = S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width));
++ writel(fb_size, S3C_VIDW00ADD2B0 + (0x08 * win_num));
++
++ if (win_num == 0)
++ writel(fb_size, S3C_VIDW00ADD2B1);
++
++ return 0;
++}
++
++int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
++{
++ s3c_fb_info_t *fbi = container_of(info, s3c_fb_info_t, fb);
++ s3c_win_info_t win_info;
++ s3c_color_key_info_t colkey_info;
++ s3c_color_val_info_t colval_info;
++ s3c_fb_dma_info_t dma_info;
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ unsigned int crt, alpha_level;
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ unsigned int f_num_val;
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_vs_info_t vs_info;
++#endif
++
++ switch(cmd){
++ case S3C_FB_GET_INFO:
++ dma_info.map_dma_f1 = fbi->map_dma_f1;
++ dma_info.map_dma_f2 = fbi->map_dma_f2;
++
++ if(copy_to_user((void *) arg, (const void *) &dma_info, sizeof(s3c_fb_dma_info_t)))
++ return -EFAULT;
++ break;
++
++ case S3C_FB_OSD_SET_INFO:
++ if (copy_from_user(&win_info, (s3c_win_info_t *) arg, sizeof(s3c_win_info_t)))
++ return -EFAULT;
++
++ s3cfb_init_win(fbi, win_info.bpp, win_info.left_x, win_info.top_y, win_info.width, win_info.height, OFF);
++ break;
++
++ case S3C_FB_OSD_START:
++ s3cfb_onoff_win(fbi, ON);
++ break;
++
++ case S3C_FB_OSD_STOP:
++ s3cfb_set_alpha_level(fbi, S3C_FB_MAX_ALPHA_LEVEL);
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case S3C_FB_OSD_ALPHA_UP:
++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf;
++
++ if (alpha_level < S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level++;
++
++ s3cfb_set_alpha_level(fbi, alpha_level);
++ break;
++
++ case S3C_FB_OSD_ALPHA_DOWN:
++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf;
++
++ if (alpha_level > 0)
++ alpha_level--;
++
++ s3cfb_set_alpha_level(fbi, alpha_level);
++ break;
++
++ case S3C_FB_OSD_ALPHA_SET:
++ if (copy_from_user(&alpha_level, (int *) arg, sizeof(int)))
++ return -EFAULT;
++
++ if (alpha_level > S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++ else if (alpha_level < 0)
++ alpha_level = 0;
++
++ s3cfb_set_alpha_level(fbi, alpha_level);
++ break;
++
++ case S3C_FB_OSD_MOVE_LEFT:
++ if (var->xoffset > 0)
++ var->xoffset--;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_RIGHT:
++ if (var->xoffset < (s3c_fimd.width - var->xres))
++ var->xoffset++;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_UP:
++ if (var->yoffset > 0)
++ var->yoffset--;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_DOWN:
++ if (var->yoffset < (s3c_fimd.height - var->yres))
++ var->yoffset++;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case FBIO_WAITFORVSYNC:
++ if (get_user(crt, (unsigned int __user *)arg))
++ return -EFAULT;
++
++ return s3cfb_wait_for_vsync();
++
++ case S3C_FB_COLOR_KEY_START:
++ s3cfb_onoff_color_key(fbi, ON);
++ break;
++
++ case S3C_FB_COLOR_KEY_STOP:
++ s3cfb_onoff_color_key(fbi, OFF);
++ break;
++
++ case S3C_FB_COLOR_KEY_ALPHA_START:
++ s3cfb_onoff_color_key_alpha(fbi, ON);
++ break;
++
++ case S3C_FB_COLOR_KEY_ALPHA_STOP:
++ s3cfb_onoff_color_key_alpha(fbi, OFF);
++ break;
++
++ case S3C_FB_COLOR_KEY_SET_INFO:
++ if (copy_from_user(&colkey_info, (s3c_color_key_info_t *) arg, sizeof(s3c_color_key_info_t)))
++ return -EFAULT;
++
++ s3cfb_set_color_key_registers(fbi, colkey_info);
++ break;
++
++ case S3C_FB_COLOR_KEY_VALUE:
++ if (copy_from_user(&colval_info, (s3c_color_val_info_t *) arg, sizeof(s3c_color_val_info_t)))
++ return -EFAULT;
++
++ s3cfb_set_color_value(fbi, colval_info);
++ break;
++
++ case S3C_FB_SET_VSYNC_INT:
++ s3c_fimd.vidintcon &= ~S3C_VIDINTCON0_FRAMESEL0_MASK;
++ s3c_fimd.vidintcon |= S3C_VIDINTCON0_FRAMESEL0_VSYNC;
++
++ if (arg)
++ s3c_fimd.vidintcon |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
++ else
++ s3c_fimd.vidintcon &= ~S3C_VIDINTCON0_INTFRMEN_ENABLE;
++
++ writel(s3c_fimd.vidintcon, S3C_VIDINTCON);
++ break;
++
++ case S3C_FB_GET_BRIGHTNESS:
++ if (copy_to_user((void *)arg, (const void *) &s3c_display_brightness, sizeof(int)))
++ return -EFAULT;
++ break;
++
++#if defined(CONFIG_S3C2450_PWM) || defined(CONFIG_S3C2416_PWM)
++ case S3C_FB_SET_BRIGHTNESS:
++ if (copy_from_user(&brightness, (int *) arg, sizeof(int)))
++ return -EFAULT;
++
++ s3cfb_set_brightness(brightness);
++ break;
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ case S3C_FB_VS_START:
++ s3c_fimd.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE);
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++
++ case S3C_FB_VS_STOP:
++ break;
++
++ case S3C_FB_VS_SET_INFO:
++ if (copy_from_user(&vs_info, (s3c_vs_info_t *) arg, sizeof(s3c_vs_info_t)))
++ return -EFAULT;
++
++ if (s3cfb_set_vs_info(vs_info)) {
++ printk("Error S3C_FB_VS_SET_INFO\n");
++ return -EINVAL;
++ }
++
++ s3cfb_set_vs_registers(S3C_FB_VS_SET);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++
++ case S3C_FB_VS_MOVE:
++ s3cfb_set_vs_registers(arg);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ case S3C_FB_GET_NUM:
++ if (copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int)))
++ return -EFAULT;
++
++ if (copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int)))
++ return -EFAULT;
++
++ break;
++
++ case S3C_FB_CHANGE_REQ:
++ s3cfb_change_buff(0, (int) arg);
++ break;
++#endif
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++void s3cfb_pre_init(void)
++{
++ /* initialize the fimd specific */
++ s3c_fimd.vidintcon &= ~S3C_VIDINTCON0_FRAMESEL0_MASK;
++ s3c_fimd.vidintcon |= S3C_VIDINTCON0_FRAMESEL0_VSYNC;
++ s3c_fimd.vidintcon |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
++
++ writel(s3c_fimd.vidintcon, S3C_VIDINTCON);
++}
++
++void s3cfb_set_gpio(void)
++{
++ unsigned long val;
++
++ /* enable clock to LCD */
++ val = readl(S3C2443_HCLKCON);
++ val |= S3C2443_HCLKCON_LCDC;
++ writel(val, S3C2443_HCLKCON);
++
++ /* select TFT LCD type */
++ val = readl(S3C2410_MISCCR);
++ val |= (1 << 28);
++ writel(val, S3C2410_MISCCR);
++
++ /* VD */
++ writel(0xaaaa02aa, S3C2410_GPCCON);
++ writel(0xaaaaaaaa, S3C2410_GPDCON);
++ writel(0x0, S3C2410_GPCUP);
++ writel(0x0, S3C2410_GPDUP);
++
++ /* backlight ON */
++ s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPB0_OUTP);
++ s3c2410_gpio_setpin(S3C2410_GPB0, 1);
++
++ /* backlight dimming ON */
++ s3c2410_gpio_cfgpin(S3C2410_GPB3, S3C2410_GPB3_OUTP);
++ s3c2410_gpio_setpin(S3C2410_GPB3, 1);
++
++ /* backlight dimming control pull-down disable*/
++ s3c2410_gpio_pullup(S3C2410_GPB3, 0);
++
++ /* module reset */
++ s3c2410_gpio_cfgpin(S3C2410_GPB1, S3C2410_GPB1_OUTP);
++ s3c2410_gpio_setpin(S3C2410_GPB1, 1);
++ mdelay(100);
++
++ s3c2410_gpio_setpin(S3C2410_GPB1, 0);
++ mdelay(10);
++
++ s3c2410_gpio_setpin(S3C2410_GPB1, 1);
++ mdelay(10);
++}
++
++#if defined(CONFIG_PM)
++
++static struct sleep_save s3c_lcd_save[] = {
++};
++
++/*
++ * Suspend
++ */
++int s3cfb_suspend(struct platform_device *dev, pm_message_t state)
++{
++ struct fb_info *fbinfo = platform_get_drvdata(dev);
++ s3c_fb_info_t *info = fbinfo->par;
++
++ s3cfb_stop_lcd();
++ s3c2410_pm_do_save(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
++
++ /* sleep before disabling the clock, we need to ensure
++ * the LCD DMA engine is not going to get back on the bus
++ * before the clock goes off again (bjd) */
++
++ msleep(1);
++ clk_disable(info->clk);
++
++ return 0;
++}
++
++/*
++ * Resume
++ */
++int s3cfb_resume(struct platform_device *dev)
++{
++ struct fb_info *fbinfo = platform_get_drvdata(dev);
++ s3c_fb_info_t *info = fbinfo->par;
++
++ clk_enable(info->clk);
++ msleep(1);
++ s3c2410_pm_do_restore(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
++
++ s3cfb_init_hw();
++ s3cfb_start_lcd();
++
++ return 0;
++}
++
++#else
++
++int s3cfb_suspend(struct platform_device *dev, pm_message_t state)
++{
++ return 0;
++}
++
++int s3cfb_resume(struct platform_device *dev)
++{
++ return 0;
++}
++
++#endif
++
+diff --git a/drivers/video/s3c/s3cfb_fimd4x.c b/drivers/video/s3c/s3cfb_fimd4x.c
+new file mode 100644
+index 0000000..c2ff1e8
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_fimd4x.c
+@@ -0,0 +1,1295 @@
++/*
++ * drivers/video/s3c/s3c64xxfb.c
++ *
++ * $Id: s3cfb_fimd4x.c,v 1.21 2008/09/29 03:50:47 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/dma-mapping.h>
++#include <linux/string.h>
++#include <linux/ioctl.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#include <asm/mach/map.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#if defined(CONFIG_PM)
++#include <asm/plat-s3c24xx/pm.h>
++#endif
++
++#include "s3cfb.h"
++
++int s3c_vs_offset = S3C_FB_DEFAULT_DISPLAY_OFFSET;
++int s3c_osd_alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++int s3c_display_brightness = S3C_FB_DEFAULT_BRIGHTNESS;
++static int s3c_palette_win;
++
++s3c_fimd_info_t s3c_fimd = {
++ .vidcon0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_L1_DATA16_SUB_16_MODE | \
++ S3C_VIDCON0_L0_DATA16_MAIN_16_MODE | S3C_VIDCON0_PNRMODE_RGB_P | \
++ S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK | \
++ S3C_VIDCON0_ENVID_DISABLE | S3C_VIDCON0_ENVID_F_DISABLE,
++
++ .dithmode = (S3C_DITHMODE_RDITHPOS_5BIT | S3C_DITHMODE_GDITHPOS_6BIT | S3C_DITHMODE_BDITHPOS_5BIT ) & S3C_DITHMODE_DITHERING_DISABLE,
++
++#if defined (CONFIG_FB_S3C_BPP_8)
++ .wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL,
++ .wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .bpp = S3C_FB_PIXEL_BPP_8,
++ .bytes_per_pixel = 1,
++ .wpalcon = S3C_WPALCON_W0PAL_16BIT,
++
++#elif defined (CONFIG_FB_S3C_BPP_16)
++ .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_1 | S3C_WINCONx_BUFAUTOEN_DISABLE | \
++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon1 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | \
++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | \
++ S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon2 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | \
++ S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | \
++ S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon3 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | \
++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon4 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE |
++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .bpp = S3C_FB_PIXEL_BPP_16,
++ .bytes_per_pixel = 2,
++ .wpalcon = S3C_WPALCON_W0PAL_16BIT,
++
++#elif defined (CONFIG_FB_S3C_BPP_24)
++ .wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888,
++ .wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .bpp = S3C_FB_PIXEL_BPP_24,
++ .bytes_per_pixel = 4,
++ .wpalcon = S3C_WPALCON_W0PAL_24BIT,
++#endif
++
++ .vidosd1c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++ .vidosd2c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++ .vidosd3c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++ .vidosd4c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++
++ .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | \
++ S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_ENABLE,
++ .vidintcon1 = 0,
++
++ .xoffset = 0,
++ .yoffset = 0,
++
++ .w1keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w1keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w2keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w2keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w3keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w3keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w4keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w4keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++
++ .sync = 0,
++ .cmap_static = 1,
++};
++
++#if defined(CONFIG_S3C6410_PWM)
++void s3cfb_set_brightness(int val)
++{
++ int channel = 1; /* must use channel-1 */
++ int usec = 0; /* don't care value */
++ unsigned long tcnt = 1000;
++ unsigned long tcmp = 0;
++
++ if (val < 0)
++ val = 0;
++
++ if (val > S3C_FB_MAX_BRIGHTNESS)
++ val = S3C_FB_MAX_BRIGHTNESS;
++
++ s3c_display_brightness = val;
++ tcmp = val * 5;
++
++ s3c6410_timer_setup (channel, usec, tcnt, tcmp);
++}
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++
++static void s3cfb_change_buff(int req_win, int req_fb)
++{
++ switch (req_win) {
++ case 0:
++ if (req_fb == 0)
++ s3c_fimd.wincon0 &= ~(1 << 20);
++ else
++ s3c_fimd.wincon0 |= (1 << 20);
++
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++ break;
++
++ case 1:
++ if (req_fb == 0)
++ s3c_fimd.wincon1 &= ~(1 << 20);
++ else
++ s3c_fimd.wincon1 |= (1 << 20);
++
++ writel(s3c_fimd.wincon1 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON1);
++ break;
++
++ default:
++ break;
++ }
++}
++
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++static int s3cfb_set_vs_registers(int vs_cmd)
++{
++ int page_width, offset;
++ int shift_value;
++
++ page_width = s3c_fimd.xres * s3c_fimd.bytes_per_pixel;
++ offset = (s3c_fimd.xres_virtual - s3c_fimd.xres) * s3c_fimd.bytes_per_pixel;
++
++ switch (vs_cmd){
++ case S3C_FB_VS_SET:
++ /* size of buffer */
++ s3c_fimd.vidw00add2 = S3C_VIDWxxADD2_OFFSIZE_F(offset) | S3C_VIDWxxADD2_PAGEWIDTH_F(page_width);
++ writel(s3c_fimd.vidw00add2, S3C_VIDW00ADD2);
++ break;
++
++ case S3C_FB_VS_MOVE_LEFT:
++ if (s3c_fimd.xoffset < s3c_vs_offset)
++ shift_value = s3c_fimd.xoffset;
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.xoffset -= shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 - (s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 - (s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_RIGHT:
++ if ((s3c_vs_info.v_width - (s3c_fimd.xoffset + s3c_vs_info.width)) < (s3c_vs_offset))
++ shift_value = s3c_vs_info.v_width - (s3c_fimd.xoffset + s3c_vs_info.width);
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.xoffset += shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 + (s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 + (s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_UP:
++ if (s3c_fimd.yoffset < s3c_vs_offset)
++ shift_value = s3c_fimd.yoffset;
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.yoffset -= shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 - (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 - (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_DOWN:
++ if ((s3c_vs_info.v_height - (s3c_fimd.yoffset + s3c_vs_info.height)) < (s3c_vs_offset))
++ shift_value = s3c_vs_info.v_height - (s3c_fimd.yoffset + s3c_vs_info.height);
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.yoffset += shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 + (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 + (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ /* End address */
++ s3c_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(s3c_fimd.vidw00add0b0 + (page_width + offset) * (s3c_fimd.yres));
++ s3c_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(s3c_fimd.vidw00add0b1 + (page_width + offset) * (s3c_fimd.yres));
++
++ writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ writel(s3c_fimd.vidw00add0b1, S3C_VIDW00ADD0B1);
++ writel(s3c_fimd.vidw00add1b0, S3C_VIDW00ADD1B0);
++ writel(s3c_fimd.vidw00add1b1, S3C_VIDW00ADD1B1);
++
++ return 0;
++}
++#endif
++
++void s3cfb_write_palette(s3c_fb_info_t *fbi)
++{
++ unsigned int i;
++ unsigned long ent;
++ unsigned int win_num = fbi->win_id;
++
++ fbi->palette_ready = 0;
++
++ writel((s3c_fimd.wpalcon | S3C_WPALCON_PALUPDATEEN), S3C_WPALCON);
++
++ for (i = 0; i < 256; i++) {
++ if ((ent = fbi->palette_buffer[i]) == S3C_FB_PALETTE_BUFF_CLEAR)
++ continue;
++
++ writel(ent, S3C_TFTPAL0(i) + 0x400 * win_num);
++
++ /* it seems the only way to know exactly
++ * if the palette wrote ok, is to check
++ * to see if the value verifies ok
++ */
++ if (readl(S3C_TFTPAL0(i) + 0x400 * win_num) == ent) {
++ fbi->palette_buffer[i] = S3C_FB_PALETTE_BUFF_CLEAR;
++ } else {
++ fbi->palette_ready = 1; /* retry */
++ printk("Retry writing into the palette\n");
++ }
++ }
++
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++}
++
++irqreturn_t s3cfb_irq(int irqno, void *param)
++{
++ unsigned long buffer_size = 0;
++ unsigned int i;
++ unsigned int buffer_page_offset, buffer_page_width;
++ unsigned int fb_start_address, fb_end_address;
++
++ if (s3c_fb_info[s3c_palette_win].palette_ready)
++ s3cfb_write_palette(&s3c_fb_info[s3c_palette_win]);
++
++ for (i = 0; i < CONFIG_FB_S3C_NUM; i++) {
++ if (s3c_fb_info[i].next_fb_info_change_req) {
++ /* fb variable setting */
++ s3c_fb_info[i].fb.fix.smem_start = s3c_fb_info[i].next_fb_info.phy_start_addr;
++
++ s3c_fb_info[i].fb.fix.line_length = s3c_fb_info[i].next_fb_info.xres_virtual *
++ s3c_fimd.bytes_per_pixel;
++
++ s3c_fb_info[i].fb.fix.smem_len = s3c_fb_info[i].next_fb_info.xres_virtual *
++ s3c_fb_info[i].next_fb_info.yres_virtual *
++ s3c_fimd.bytes_per_pixel;
++
++ s3c_fb_info[i].fb.var.xres = s3c_fb_info[i].next_fb_info.xres;
++ s3c_fb_info[i].fb.var.yres = s3c_fb_info[i].next_fb_info.yres;
++ s3c_fb_info[i].fb.var.xres_virtual = s3c_fb_info[i].next_fb_info.xres_virtual;
++ s3c_fb_info[i].fb.var.yres_virtual= s3c_fb_info[i].next_fb_info.yres_virtual;
++ s3c_fb_info[i].fb.var.xoffset = s3c_fb_info[i].next_fb_info.xoffset;
++ s3c_fb_info[i].fb.var.yoffset = s3c_fb_info[i].next_fb_info.yoffset;
++
++ s3c_fb_info[i].lcd_offset_x= s3c_fb_info[i].next_fb_info.lcd_offset_x;
++ s3c_fb_info[i].lcd_offset_y= s3c_fb_info[i].next_fb_info.lcd_offset_y;
++
++
++ /* fb start / end address setting */
++ fb_start_address = s3c_fb_info[i].next_fb_info.phy_start_addr +
++ s3c_fb_info[i].fb.fix.line_length * s3c_fb_info[i].next_fb_info.yoffset +
++ s3c_fb_info[i].next_fb_info.xoffset * s3c_fimd.bytes_per_pixel;
++
++ fb_end_address = fb_start_address + s3c_fb_info[i].fb.fix.line_length *
++ s3c_fb_info[i].next_fb_info.yres;
++
++ writel(fb_start_address, S3C_VIDW00ADD0B0 + 0x8 * i);
++ writel(S3C_VIDWxxADD1_VBASEL_F(fb_end_address), S3C_VIDW00ADD1B0 + 0x8 * i);
++
++
++ /* fb virtual / visible size setting */
++ buffer_page_width = s3c_fb_info[i].next_fb_info.xres * s3c_fimd.bytes_per_pixel;
++
++ buffer_page_offset = (s3c_fb_info[i].next_fb_info.xres_virtual -
++ s3c_fb_info[i].next_fb_info.xres) * s3c_fimd.bytes_per_pixel;
++
++ buffer_size = S3C_VIDWxxADD2_OFFSIZE_F(buffer_page_offset) |
++ (S3C_VIDWxxADD2_PAGEWIDTH_F(buffer_page_width));
++
++ writel(buffer_size, S3C_VIDW00ADD2 + 0x04 * i);
++
++ /* LCD position setting */
++ writel(S3C_VIDOSDxA_OSD_LTX_F(s3c_fb_info[i].next_fb_info.lcd_offset_x) |
++ S3C_VIDOSDxA_OSD_LTY_F(s3c_fb_info[i].next_fb_info.lcd_offset_y), S3C_VIDOSD0A+(0x10 * i));
++
++ writel(S3C_VIDOSDxB_OSD_RBX_F(s3c_fb_info[i].next_fb_info.lcd_offset_x - 1 + s3c_fb_info[i].next_fb_info.xres) |
++ S3C_VIDOSDxB_OSD_RBY_F(s3c_fb_info[i].next_fb_info.lcd_offset_y - 1 + s3c_fb_info[i].next_fb_info.yres),
++ S3C_VIDOSD0B + (0x10 * i));
++
++
++ /* fb size setting */
++ if (i == 0)
++ writel(S3C_VIDOSD0C_OSDSIZE(s3c_fb_info[i].next_fb_info.xres * s3c_fb_info[i].next_fb_info.yres), S3C_VIDOSD0C);
++ else if (i == 1)
++ writel(S3C_VIDOSD0C_OSDSIZE(s3c_fb_info[i].next_fb_info.xres * s3c_fb_info[i].next_fb_info.yres), S3C_VIDOSD1D);
++ else if (i == 2)
++ writel(S3C_VIDOSD0C_OSDSIZE(s3c_fb_info[i].next_fb_info.xres * s3c_fb_info[i].next_fb_info.yres), S3C_VIDOSD2D);
++
++ s3c_fb_info[i].next_fb_info_change_req = 0;
++ }
++ }
++
++ /* for clearing the interrupt source */
++ writel(readl(S3C_VIDINTCON1), S3C_VIDINTCON1);
++
++ s3c_vsync_info.count++;
++ wake_up_interruptible(&s3c_vsync_info.wait_queue);
++
++ return IRQ_HANDLED;
++}
++
++void s3cfb_enable_local_post(int in_yuv)
++{
++ unsigned int value;
++
++ s3c_fimd.wincon0 &= ~(1 << 22 | 1 << 13);
++ value = S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_ENWIN_F_ENABLE;
++
++ if (in_yuv)
++ value |= S3C_WINCONx_INRGB_YUV;
++
++ writel(s3c_fimd.wincon0 | value, S3C_WINCON0);
++}
++
++EXPORT_SYMBOL(s3cfb_enable_local_post);
++
++void s3cfb_enable_dma(void)
++{
++ u32 value;
++
++ s3c_fimd.wincon0 &= ~((1<<22)| (1<<13));
++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_ENWIN_F_ENABLE;
++
++ __raw_writel(s3c_fimd.wincon0 | value, S3C_WINCON0);
++}
++
++EXPORT_SYMBOL(s3cfb_enable_dma);
++
++int s3cfb_init_registers(s3c_fb_info_t *fbi)
++{
++ struct clk *lcd_clock;
++ struct fb_var_screeninfo *var = &fbi->fb.var;
++ unsigned long flags = 0, page_width = 0, offset = 0;
++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1;
++ unsigned long video_phy_temp_f2 = fbi->screen_dma_f2;
++ int win_num = fbi->win_id;
++
++ /* Initialise LCD with values from hare */
++ local_irq_save(flags);
++
++ page_width = var->xres * s3c_fimd.bytes_per_pixel;
++ offset = (var->xres_virtual - var->xres) * s3c_fimd.bytes_per_pixel;
++
++ if (win_num == 0) {
++ s3c_fimd.vidcon0 = s3c_fimd.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE);
++ writel(s3c_fimd.vidcon0, S3C_VIDCON0);
++
++ lcd_clock = clk_get(NULL, "lcd");
++ s3c_fimd.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int) ((clk_get_rate(lcd_clock) / s3c_fimd.pixclock) - 1));
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ offset = 0;
++ s3c_fimd.vidw00add0b0 = video_phy_temp_f1;
++ s3c_fimd.vidw00add0b1 = video_phy_temp_f2;
++ s3c_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres));
++ s3c_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres));
++#endif
++ }
++
++ writel(video_phy_temp_f1, S3C_VIDW00ADD0B0 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)), S3C_VIDW00ADD2 + (0x04 * win_num));
++
++ if (win_num < 2) {
++ writel(video_phy_temp_f2, S3C_VIDW00ADD0B1 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num));
++ }
++
++ switch (win_num) {
++ case 0:
++ writel(s3c_fimd.wincon0, S3C_WINCON0);
++ writel(s3c_fimd.vidcon0, S3C_VIDCON0);
++ writel(s3c_fimd.vidcon1, S3C_VIDCON1);
++ writel(s3c_fimd.vidtcon0, S3C_VIDTCON0);
++ writel(s3c_fimd.vidtcon1, S3C_VIDTCON1);
++ writel(s3c_fimd.vidtcon2, S3C_VIDTCON2);
++ writel(s3c_fimd.dithmode, S3C_DITHMODE);
++ writel(s3c_fimd.vidintcon0, S3C_VIDINTCON0);
++ writel(s3c_fimd.vidintcon1, S3C_VIDINTCON1);
++ writel(s3c_fimd.vidosd0a, S3C_VIDOSD0A);
++ writel(s3c_fimd.vidosd0b, S3C_VIDOSD0B);
++ writel(s3c_fimd.vidosd0c, S3C_VIDOSD0C);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, ON);
++ break;
++
++ case 1:
++ writel(s3c_fimd.wincon1, S3C_WINCON1);
++ writel(s3c_fimd.vidosd1a, S3C_VIDOSD1A);
++ writel(s3c_fimd.vidosd1b, S3C_VIDOSD1B);
++ writel(s3c_fimd.vidosd1c, S3C_VIDOSD1C);
++ writel(s3c_fimd.vidosd1d, S3C_VIDOSD1D);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case 2:
++ writel(s3c_fimd.wincon2, S3C_WINCON2);
++ writel(s3c_fimd.vidosd2a, S3C_VIDOSD2A);
++ writel(s3c_fimd.vidosd2b, S3C_VIDOSD2B);
++ writel(s3c_fimd.vidosd2c, S3C_VIDOSD2C);
++ writel(s3c_fimd.vidosd2d, S3C_VIDOSD2D);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case 3:
++ writel(s3c_fimd.wincon3, S3C_WINCON3);
++ writel(s3c_fimd.vidosd3a, S3C_VIDOSD3A);
++ writel(s3c_fimd.vidosd3b, S3C_VIDOSD3B);
++ writel(s3c_fimd.vidosd3c, S3C_VIDOSD3C);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case 4:
++ writel(s3c_fimd.wincon4, S3C_WINCON4);
++ writel(s3c_fimd.vidosd4a, S3C_VIDOSD4A);
++ writel(s3c_fimd.vidosd4b, S3C_VIDOSD4B);
++ writel(s3c_fimd.vidosd4c, S3C_VIDOSD4C);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++ }
++
++ local_irq_restore(flags);
++
++ return 0;
++ }
++
++void s3cfb_activate_var(s3c_fb_info_t *fbi, struct fb_var_screeninfo *var)
++{
++ DPRINTK("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ s3c_fimd.wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_8;
++ s3c_fimd.bytes_per_pixel = 1;
++ s3c_fimd.wpalcon = S3C_WPALCON_W0PAL_16BIT;
++ break;
++
++ case 16:
++ s3c_fimd.wincon0 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_16;
++ s3c_fimd.bytes_per_pixel = 2;
++ break;
++
++ case 24:
++ s3c_fimd.wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_24;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++
++ case 32:
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++ }
++
++ /* write new registers */
++ writel(s3c_fimd.wincon0, S3C_WINCON0);
++ writel(s3c_fimd.wincon1, S3C_WINCON1);
++ writel(s3c_fimd.wincon2, S3C_WINCON2);
++ writel(s3c_fimd.wincon3, S3C_WINCON3);
++ writel(s3c_fimd.wincon4, S3C_WINCON4);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++ writel(s3c_fimd.vidcon0 | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
++}
++
++/* JJNAHM comment.
++ * We had some problems related to frame buffer address.
++ * We used 2 frame buffers (FB0 and FB1) and GTK used FB1.
++ * When GTK launched, GTK set FB0's address to FB1's address.
++ * (GTK calls s3c_fb_pan_display() and then it calls this s3c_fb_set_lcdaddr())
++ * Even though fbi->win_id is not 0, above original codes set ONLY FB0's address.
++ * So, I modified the codes like below.
++ * It works by fbi->win_id value.
++ * Below codes are not verified yet
++ * and there are nothing about Double buffering features
++ */
++void s3cfb_set_fb_addr(s3c_fb_info_t *fbi)
++{
++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1;
++ unsigned long start_address, end_address;
++ unsigned int start;
++
++ start = fbi->fb.fix.line_length * fbi->fb.var.yoffset;
++
++ /* for buffer start address and end address */
++ start_address = video_phy_temp_f1 + start;
++ end_address = start_address + (fbi->fb.fix.line_length * fbi->fb.var.yres);
++
++ switch (fbi->win_id)
++ {
++ case 0:
++ s3c_fimd.vidw00add0b0 = start_address;
++ s3c_fimd.vidw00add1b0 = end_address;
++ __raw_writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ __raw_writel(s3c_fimd.vidw00add1b0, S3C_VIDW00ADD1B0);
++ break;
++
++ case 1:
++ s3c_fimd.vidw01add0b0 = start_address;
++ s3c_fimd.vidw01add1b0 = end_address;
++ __raw_writel(s3c_fimd.vidw01add0b0, S3C_VIDW01ADD0B0);
++ __raw_writel(s3c_fimd.vidw01add1b0, S3C_VIDW01ADD1B0);
++ break;
++
++ case 2:
++ s3c_fimd.vidw02add0 = start_address;
++ s3c_fimd.vidw02add1 = end_address;
++ __raw_writel(s3c_fimd.vidw02add0, S3C_VIDW02ADD0);
++ __raw_writel(s3c_fimd.vidw02add1, S3C_VIDW02ADD1);
++ break;
++
++ case 3:
++ s3c_fimd.vidw03add0 = start_address;
++ s3c_fimd.vidw03add1 = end_address;
++ __raw_writel(s3c_fimd.vidw03add0, S3C_VIDW03ADD0);
++ __raw_writel(s3c_fimd.vidw03add1, S3C_VIDW03ADD1);
++ break;
++
++ case 4:
++ s3c_fimd.vidw04add0 = start_address;
++ s3c_fimd.vidw04add1 = end_address;
++ __raw_writel(s3c_fimd.vidw04add0, S3C_VIDW04ADD0);
++ __raw_writel(s3c_fimd.vidw04add1, S3C_VIDW04ADD1);
++ break;
++ }
++}
++
++static int s3cfb_set_alpha_level(s3c_fb_info_t *fbi, unsigned int level, unsigned int alpha_index)
++{
++ unsigned long alpha_val;
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support alpha blending.\n");
++ return -1;
++ }
++
++ alpha_val = readl(S3C_VIDOSD0C+(0x10 * win_num));
++
++ if (alpha_index == 0) {
++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA0_B(0xf) | S3C_VIDOSDxC_ALPHA0_G(0xf) | S3C_VIDOSDxC_ALPHA0_R(0xf));
++ alpha_val |= S3C_VIDOSDxC_ALPHA0_B(level) | S3C_VIDOSDxC_ALPHA0_G(level) | S3C_VIDOSDxC_ALPHA0_R(level);
++ } else {
++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA1_B(0xf) | S3C_VIDOSDxC_ALPHA1_G(0xf) | S3C_VIDOSDxC_ALPHA1_R(0xf));
++ alpha_val = S3C_VIDOSDxC_ALPHA1_B(level) | S3C_VIDOSDxC_ALPHA1_G(level) | S3C_VIDOSDxC_ALPHA1_R(level);
++ }
++
++ writel(alpha_val, S3C_VIDOSD0C + (0x10 * win_num));
++
++ return 0;
++}
++
++int s3cfb_set_alpha_mode(s3c_fb_info_t *fbi, int mode)
++{
++ unsigned long alpha_mode;
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support alpha blending.\n");
++ return -1;
++ }
++
++ alpha_mode = readl(S3C_WINCON0 + (0x04 * win_num));
++ alpha_mode &= ~(S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1);
++
++ switch (mode) {
++ case 0: /* Plane Blending */
++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, S3C_WINCON0 + (0x04 * win_num));
++ break;
++
++ case 1: /* Pixel Blending & chroma(color) key */
++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_0, S3C_WINCON0 + (0x04 * win_num));
++ break;
++ }
++
++ return 0;
++}
++
++int s3cfb_set_win_position(s3c_fb_info_t *fbi, int left_x, int top_y, int width, int height)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++
++ writel(S3C_VIDOSDxA_OSD_LTX_F(left_x) | S3C_VIDOSDxA_OSD_LTY_F(top_y), S3C_VIDOSD0A + (0x10 * win_num));
++ writel(S3C_VIDOSDxB_OSD_RBX_F(width - 1 + left_x) | S3C_VIDOSDxB_OSD_RBY_F(height - 1 + top_y), S3C_VIDOSD0B + (0x10 * win_num));
++
++ var->xoffset = left_x;
++ var->yoffset = top_y;
++
++ return 0;
++}
++
++int s3cfb_set_win_size(s3c_fb_info_t *fbi, int width, int height)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++
++ if (win_num == 1)
++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD1D);
++
++ else if (win_num == 2)
++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD2D);
++
++ var->xres = width;
++ var->yres = height;
++ var->xres_virtual = width;
++ var->yres_virtual = height;
++
++ return 0;
++}
++
++int s3cfb_set_fb_size(s3c_fb_info_t *fbi)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++ unsigned long offset = 0;
++ unsigned long page_width = 0;
++ unsigned long fb_size = 0;
++
++ page_width = var->xres * s3c_fimd.bytes_per_pixel;
++ offset = (var->xres_virtual - var->xres) * s3c_fimd.bytes_per_pixel;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ if (win_num == 0)
++ offset=0;
++#endif
++
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B0 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num));
++
++ if (win_num == 1)
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B1 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num));
++
++ /* size of frame buffer */
++ fb_size = S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width));
++
++ writel(fb_size, S3C_VIDW00ADD2 + (0x04 * win_num));
++
++ return 0;
++}
++
++void s3cfb_set_output_path(int out)
++{
++ unsigned int tmp;
++
++ tmp = readl(S3C_VIDCON0);
++
++ /* if output mode is LCD mode, Scan mode always should be progressive mode */
++ if (out == S3C_FB_OUTPUT_TV)
++ tmp &= ~(1 << 29);
++
++ tmp &= ~(0x7 << 26);
++ tmp |= (out << 26);
++
++ writel(tmp, S3C_VIDCON0);
++}
++
++EXPORT_SYMBOL(s3cfb_set_output_path);
++
++void s3cfb_enable_rgbport(int on)
++{
++ if (on)
++ writel(0x380, S3C_VIDCON2);
++ else
++ writel(0x0, S3C_VIDCON2);
++}
++
++EXPORT_SYMBOL(s3cfb_enable_rgbport);
++
++int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
++{
++ s3c_fb_info_t *fbi = container_of(info, s3c_fb_info_t, fb);
++ s3c_win_info_t win_info;
++ s3c_color_key_info_t colkey_info;
++ s3c_color_val_info_t colval_info;
++ s3c_fb_dma_info_t dma_info;
++ s3c_fb_next_info_t next_fb_info;
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ unsigned int crt, alpha_level, alpha_mode;
++
++#if defined(CONFIG_S3C6410_PWM)
++ int brightness;
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ unsigned int f_num_val;
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_vs_info_t vs_info;
++#endif
++
++ switch(cmd){
++ case S3C_FB_GET_INFO:
++ dma_info.map_dma_f1 = fbi->map_dma_f1;
++ dma_info.map_dma_f2 = fbi->map_dma_f2;
++
++ if(copy_to_user((void *) arg, (const void *) &dma_info, sizeof(s3c_fb_dma_info_t)))
++ return -EFAULT;
++ break;
++
++ case S3C_FB_OSD_SET_INFO:
++ if (copy_from_user(&win_info, (s3c_win_info_t *) arg, sizeof(s3c_win_info_t)))
++ return -EFAULT;
++
++ s3cfb_init_win(fbi, win_info.bpp, win_info.left_x, win_info.top_y, win_info.width, win_info.height, OFF);
++ break;
++
++ case S3C_FB_OSD_START:
++ s3cfb_onoff_win(fbi, ON);
++ break;
++
++ case S3C_FB_OSD_STOP:
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case S3C_FB_OSD_ALPHA_UP:
++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf;
++
++ if (alpha_level < S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level++;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 1);
++ break;
++
++ case S3C_FB_OSD_ALPHA_DOWN:
++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf;
++
++ if (alpha_level > 0)
++ alpha_level--;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 1);
++ break;
++
++ case S3C_FB_OSD_ALPHA0_SET:
++ alpha_level = arg;
++
++ if (alpha_level > S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++ else if(alpha_level < 0)
++ alpha_level = 0;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 0);
++ break;
++
++ case S3C_FB_OSD_ALPHA_SET:
++ alpha_level = (unsigned int) arg;
++
++ if (alpha_level > S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++ else if (alpha_level < 0)
++ alpha_level = 0;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 1);
++ break;
++
++ case S3C_FB_OSD_ALPHA_MODE:
++ alpha_mode = arg;
++ s3cfb_set_alpha_mode(fbi, alpha_mode);
++ break;
++
++ case S3C_FB_OSD_MOVE_LEFT:
++ if (var->xoffset > 0)
++ var->xoffset--;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_RIGHT:
++ if (var->xoffset < (s3c_fimd.width - var->xres))
++ var->xoffset++;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_UP:
++ if (var->yoffset > 0)
++ var->yoffset--;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_DOWN:
++ if (var->yoffset < (s3c_fimd.height - var->yres))
++ var->yoffset++;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case FBIO_WAITFORVSYNC:
++ if (get_user(crt, (unsigned int __user *)arg))
++ return -EFAULT;
++
++ return s3cfb_wait_for_vsync();
++
++ case S3C_FB_COLOR_KEY_START:
++ s3cfb_onoff_color_key(fbi, ON);
++ break;
++
++ case S3C_FB_COLOR_KEY_STOP:
++ s3cfb_onoff_color_key(fbi, OFF);
++ break;
++
++ case S3C_FB_COLOR_KEY_ALPHA_START:
++ s3cfb_onoff_color_key_alpha(fbi, ON);
++ break;
++
++ case S3C_FB_COLOR_KEY_ALPHA_STOP:
++ s3cfb_onoff_color_key_alpha(fbi, OFF);
++ break;
++
++ case S3C_FB_COLOR_KEY_SET_INFO:
++ if (copy_from_user(&colkey_info, (s3c_color_key_info_t *) arg, sizeof(s3c_color_key_info_t)))
++ return -EFAULT;
++
++ s3cfb_set_color_key_registers(fbi, colkey_info);
++ break;
++
++ case S3C_FB_COLOR_KEY_VALUE:
++ if (copy_from_user(&colval_info, (s3c_color_val_info_t *) arg, sizeof(s3c_color_val_info_t)))
++ return -EFAULT;
++
++ s3cfb_set_color_value(fbi, colval_info);
++ break;
++
++ case S3C_FB_SET_VSYNC_INT:
++ s3c_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK;
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC;
++
++ if (arg)
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
++ else
++ s3c_fimd.vidintcon0 &= ~S3C_VIDINTCON0_INTFRMEN_ENABLE;
++
++ writel(s3c_fimd.vidintcon0, S3C_VIDINTCON0);
++ break;
++
++ case S3C_FB_SET_NEXT_FB_INFO:
++ if (copy_from_user(&next_fb_info, (s3c_fb_next_info_t *) arg, sizeof(s3c_fb_next_info_t)))
++ return -EFAULT;
++
++ /* check arguments */
++ if ((next_fb_info.xres + next_fb_info.xoffset) > next_fb_info.xres_virtual ||
++ (next_fb_info.yres + next_fb_info.yoffset) > next_fb_info.yres_virtual ||
++ (next_fb_info.xres + next_fb_info.lcd_offset_x ) > s3c_fimd.width ||
++ (next_fb_info.yres + next_fb_info.lcd_offset_y ) > s3c_fimd.height)
++ return -EINVAL;
++
++ fbi->next_fb_info = next_fb_info;
++ fbi->next_fb_info_change_req = 1;
++ break;
++
++ case S3C_FB_GET_CURR_FB_INFO:
++ next_fb_info.phy_start_addr = fbi->fb.fix.smem_start;
++ next_fb_info.xres = fbi->fb.var.xres;
++ next_fb_info.yres = fbi->fb.var.yres;
++ next_fb_info.xres_virtual = fbi->fb.var.xres_virtual;
++ next_fb_info.yres_virtual = fbi->fb.var.yres_virtual;
++ next_fb_info.xoffset = fbi->fb.var.xoffset;
++ next_fb_info.yoffset = fbi->fb.var.yoffset;
++ next_fb_info.lcd_offset_x = fbi->lcd_offset_x;
++ next_fb_info.lcd_offset_y = fbi->lcd_offset_y;
++
++ if (copy_to_user((void *)arg, (s3c_fb_next_info_t *) &next_fb_info, sizeof(s3c_fb_next_info_t)))
++ return -EFAULT;
++ break;
++
++ case S3C_FB_GET_BRIGHTNESS:
++ if (copy_to_user((void *)arg, (const void *) &s3c_display_brightness, sizeof(int)))
++ return -EFAULT;
++ break;
++
++#if defined(CONFIG_S3C6410_PWM)
++ case S3C_FB_SET_BRIGHTNESS:
++ if (copy_from_user(&brightness, (int *) arg, sizeof(int)))
++ return -EFAULT;
++
++ s3cfb_set_brightness(brightness);
++ break;
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ case S3C_FB_VS_START:
++ s3c_fimd.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE);
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++
++ case S3C_FB_VS_STOP:
++ s3c_fimd.vidw00add0b0 = fbi->screen_dma_f1;
++ s3c_fimd.vidw00add0b1 = fbi->screen_dma_f2;
++ fbi->fb.var.xoffset = 0;
++ fbi->fb.var.yoffset = 0;
++
++ writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ writel(s3c_fimd.vidw00add0b1, S3C_VIDW00ADD0B1);
++
++ break;
++
++ case S3C_FB_VS_SET_INFO:
++ if (copy_from_user(&vs_info, (s3c_vs_info_t *) arg, sizeof(s3c_vs_info_t)))
++ return -EFAULT;
++
++ if (s3cfb_set_vs_info(vs_info)) {
++ printk("Error S3C_FB_VS_SET_INFO\n");
++ return -EINVAL;
++ }
++
++ s3cfb_set_vs_registers(S3C_FB_VS_SET);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++
++ case S3C_FB_VS_MOVE:
++ s3cfb_set_vs_registers(arg);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ case S3C_FB_GET_NUM:
++ if (copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int)))
++ return -EFAULT;
++
++ if (copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int)))
++ return -EFAULT;
++
++ break;
++#endif
++
++ case S3C_FB_RELEASE_DEFAULT_FB:
++ s3cfb_unmap_video_memory(fbi);
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++void s3cfb_pre_init(void)
++{
++ /* initialize the fimd specific */
++ s3c_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK;
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC;
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
++
++ writel(s3c_fimd.vidintcon0, S3C_VIDINTCON0);
++}
++
++void s3cfb_set_gpio(void)
++{
++ unsigned long val;
++
++ /* Must be '0' for Normal-path instead of By-pass */
++ writel(0x0, S3C_HOSTIFB_MIFPCON);
++
++ /* enable clock to LCD */
++ val = readl(S3C_HCLK_GATE);
++ val |= S3C_CLKCON_HCLK_LCD;
++ writel(val, S3C_HCLK_GATE);
++
++ /* select TFT LCD type (RGB I/F) */
++ val = readl(S3C_SPCON);
++ val &= ~0x3;
++ val |= (1 << 0);
++ writel(val, S3C_SPCON);
++
++ /* VD */
++ gpio_set_pin(S3C_GPI0, S3C_GPI0_LCD_VD0);
++ gpio_set_pin(S3C_GPI1, S3C_GPI1_LCD_VD1);
++ gpio_set_pin(S3C_GPI2, S3C_GPI2_LCD_VD2);
++ gpio_set_pin(S3C_GPI3, S3C_GPI3_LCD_VD3);
++ gpio_set_pin(S3C_GPI4, S3C_GPI4_LCD_VD4);
++ gpio_set_pin(S3C_GPI5, S3C_GPI5_LCD_VD5);
++ gpio_set_pin(S3C_GPI6, S3C_GPI6_LCD_VD6);
++ gpio_set_pin(S3C_GPI7, S3C_GPI7_LCD_VD7);
++ gpio_set_pin(S3C_GPI8, S3C_GPI8_LCD_VD8);
++ gpio_set_pin(S3C_GPI9, S3C_GPI9_LCD_VD9);
++ gpio_set_pin(S3C_GPI10, S3C_GPI10_LCD_VD10);
++ gpio_set_pin(S3C_GPI11, S3C_GPI11_LCD_VD11);
++ gpio_set_pin(S3C_GPI12, S3C_GPI12_LCD_VD12);
++ gpio_set_pin(S3C_GPI13, S3C_GPI13_LCD_VD13);
++ gpio_set_pin(S3C_GPI14, S3C_GPI14_LCD_VD14);
++ gpio_set_pin(S3C_GPI15, S3C_GPI15_LCD_VD15);
++ gpio_set_pin(S3C_GPJ0, S3C_GPJ0_LCD_VD16);
++ gpio_set_pin(S3C_GPJ1, S3C_GPJ1_LCD_VD17);
++ gpio_set_pin(S3C_GPJ2, S3C_GPJ2_LCD_VD18);
++ gpio_set_pin(S3C_GPJ3, S3C_GPJ3_LCD_VD19);
++ gpio_set_pin(S3C_GPJ4, S3C_GPJ4_LCD_VD20);
++ gpio_set_pin(S3C_GPJ5, S3C_GPJ5_LCD_VD21);
++ gpio_set_pin(S3C_GPJ6, S3C_GPJ6_LCD_VD22);
++ gpio_set_pin(S3C_GPJ7, S3C_GPJ7_LCD_VD23);
++ gpio_set_pin(S3C_GPJ8, S3C_GPJ8_LCD_HSYNC);
++ gpio_set_pin(S3C_GPJ9, S3C_GPJ9_LCD_VSYNC);
++ gpio_set_pin(S3C_GPJ10, S3C_GPJ10_LCD_VDEN);
++ gpio_set_pin(S3C_GPJ11, S3C_GPJ11_LCD_VCLK);
++
++ /* backlight ON */
++ gpio_direction_output(S3C_GPF15, 1);
++
++ /* module reset */
++ gpio_direction_output(S3C_GPN5, 1);
++ mdelay(100);
++
++ gpio_set_value(S3C_GPN5, 0);
++ mdelay(10);
++
++ gpio_set_value(S3C_GPN5, 1);
++ mdelay(10);
++}
++
++#if defined(CONFIG_PM)
++
++static struct sleep_save s3c_lcd_save[] = {
++ SAVE_ITEM(S3C_VIDCON0),
++ SAVE_ITEM(S3C_VIDCON1),
++
++ SAVE_ITEM(S3C_VIDTCON0),
++ SAVE_ITEM(S3C_VIDTCON1),
++ SAVE_ITEM(S3C_VIDTCON2),
++ SAVE_ITEM(S3C_VIDTCON3),
++
++ SAVE_ITEM(S3C_WINCON0),
++ SAVE_ITEM(S3C_WINCON1),
++ SAVE_ITEM(S3C_WINCON2),
++ SAVE_ITEM(S3C_WINCON3),
++ SAVE_ITEM(S3C_WINCON4),
++
++ SAVE_ITEM(S3C_VIDOSD0A),
++ SAVE_ITEM(S3C_VIDOSD0B),
++ SAVE_ITEM(S3C_VIDOSD0C),
++
++ SAVE_ITEM(S3C_VIDOSD1A),
++ SAVE_ITEM(S3C_VIDOSD1B),
++ SAVE_ITEM(S3C_VIDOSD1C),
++ SAVE_ITEM(S3C_VIDOSD1D),
++
++ SAVE_ITEM(S3C_VIDOSD2A),
++ SAVE_ITEM(S3C_VIDOSD2B),
++ SAVE_ITEM(S3C_VIDOSD2C),
++ SAVE_ITEM(S3C_VIDOSD2D),
++
++ SAVE_ITEM(S3C_VIDOSD3A),
++ SAVE_ITEM(S3C_VIDOSD3B),
++ SAVE_ITEM(S3C_VIDOSD3C),
++
++ SAVE_ITEM(S3C_VIDOSD4A),
++ SAVE_ITEM(S3C_VIDOSD4B),
++ SAVE_ITEM(S3C_VIDOSD4C),
++
++ SAVE_ITEM(S3C_VIDW00ADD0B0),
++ SAVE_ITEM(S3C_VIDW00ADD0B1),
++ SAVE_ITEM(S3C_VIDW01ADD0B0),
++ SAVE_ITEM(S3C_VIDW01ADD0B1),
++ SAVE_ITEM(S3C_VIDW02ADD0),
++ SAVE_ITEM(S3C_VIDW03ADD0),
++ SAVE_ITEM(S3C_VIDW04ADD0),
++ SAVE_ITEM(S3C_VIDW00ADD1B0),
++ SAVE_ITEM(S3C_VIDW00ADD1B1),
++ SAVE_ITEM(S3C_VIDW01ADD1B0),
++ SAVE_ITEM(S3C_VIDW01ADD1B1),
++ SAVE_ITEM(S3C_VIDW02ADD1),
++ SAVE_ITEM(S3C_VIDW03ADD1),
++ SAVE_ITEM(S3C_VIDW04ADD1),
++ SAVE_ITEM(S3C_VIDW00ADD2),
++ SAVE_ITEM(S3C_VIDW01ADD2),
++ SAVE_ITEM(S3C_VIDW02ADD2),
++ SAVE_ITEM(S3C_VIDW03ADD2),
++ SAVE_ITEM(S3C_VIDW04ADD2),
++
++ SAVE_ITEM(S3C_VIDINTCON0),
++ SAVE_ITEM(S3C_VIDINTCON1),
++ SAVE_ITEM(S3C_W1KEYCON0),
++ SAVE_ITEM(S3C_W1KEYCON1),
++ SAVE_ITEM(S3C_W2KEYCON0),
++ SAVE_ITEM(S3C_W2KEYCON1),
++
++ SAVE_ITEM(S3C_W3KEYCON0),
++ SAVE_ITEM(S3C_W3KEYCON1),
++ SAVE_ITEM(S3C_W4KEYCON0),
++ SAVE_ITEM(S3C_W4KEYCON1),
++ SAVE_ITEM(S3C_DITHMODE),
++
++ SAVE_ITEM(S3C_WIN0MAP),
++ SAVE_ITEM(S3C_WIN1MAP),
++ SAVE_ITEM(S3C_WIN2MAP),
++ SAVE_ITEM(S3C_WIN3MAP),
++ SAVE_ITEM(S3C_WIN4MAP),
++ SAVE_ITEM(S3C_WPALCON),
++
++ SAVE_ITEM(S3C_TRIGCON),
++ SAVE_ITEM(S3C_I80IFCONA0),
++ SAVE_ITEM(S3C_I80IFCONA1),
++ SAVE_ITEM(S3C_I80IFCONB0),
++ SAVE_ITEM(S3C_I80IFCONB1),
++ SAVE_ITEM(S3C_LDI_CMDCON0),
++ SAVE_ITEM(S3C_LDI_CMDCON1),
++ SAVE_ITEM(S3C_SIFCCON0),
++ SAVE_ITEM(S3C_SIFCCON1),
++ SAVE_ITEM(S3C_SIFCCON2),
++
++ SAVE_ITEM(S3C_LDI_CMD0),
++ SAVE_ITEM(S3C_LDI_CMD1),
++ SAVE_ITEM(S3C_LDI_CMD2),
++ SAVE_ITEM(S3C_LDI_CMD3),
++ SAVE_ITEM(S3C_LDI_CMD4),
++ SAVE_ITEM(S3C_LDI_CMD5),
++ SAVE_ITEM(S3C_LDI_CMD6),
++ SAVE_ITEM(S3C_LDI_CMD7),
++ SAVE_ITEM(S3C_LDI_CMD8),
++ SAVE_ITEM(S3C_LDI_CMD9),
++ SAVE_ITEM(S3C_LDI_CMD10),
++ SAVE_ITEM(S3C_LDI_CMD11),
++
++ SAVE_ITEM(S3C_W2PDATA01),
++ SAVE_ITEM(S3C_W2PDATA23),
++ SAVE_ITEM(S3C_W2PDATA45),
++ SAVE_ITEM(S3C_W2PDATA67),
++ SAVE_ITEM(S3C_W2PDATA89),
++ SAVE_ITEM(S3C_W2PDATAAB),
++ SAVE_ITEM(S3C_W2PDATACD),
++ SAVE_ITEM(S3C_W2PDATAEF),
++ SAVE_ITEM(S3C_W3PDATA01),
++ SAVE_ITEM(S3C_W3PDATA23),
++ SAVE_ITEM(S3C_W3PDATA45),
++ SAVE_ITEM(S3C_W3PDATA67),
++ SAVE_ITEM(S3C_W3PDATA89),
++ SAVE_ITEM(S3C_W3PDATAAB),
++ SAVE_ITEM(S3C_W3PDATACD),
++ SAVE_ITEM(S3C_W3PDATAEF),
++ SAVE_ITEM(S3C_W4PDATA01),
++ SAVE_ITEM(S3C_W4PDATA23),
++};
++
++/*
++ * Suspend
++ */
++int s3cfb_suspend(struct platform_device *dev, pm_message_t state)
++{
++ struct fb_info *fbinfo = platform_get_drvdata(dev);
++ s3c_fb_info_t *info = fbinfo->par;
++
++ s3cfb_stop_lcd();
++ s3c2410_pm_do_save(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
++
++ /* sleep before disabling the clock, we need to ensure
++ * the LCD DMA engine is not going to get back on the bus
++ * before the clock goes off again (bjd) */
++
++ msleep(1);
++ clk_disable(info->clk);
++
++ return 0;
++}
++
++/*
++ * Resume
++ */
++int s3cfb_resume(struct platform_device *dev)
++{
++ struct fb_info *fbinfo = platform_get_drvdata(dev);
++ s3c_fb_info_t *info = fbinfo->par;
++
++ clk_enable(info->clk);
++ msleep(1);
++ s3c2410_pm_do_restore(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
++
++ s3cfb_init_hw();
++ s3cfb_start_lcd();
++
++ return 0;
++}
++
++#else
++
++int s3cfb_suspend(struct platform_device *dev, pm_message_t state)
++{
++ return 0;
++}
++
++int s3cfb_resume(struct platform_device *dev)
++{
++ return 0;
++}
++
++#endif
++
+diff --git a/drivers/video/s3c/s3cfb_lte480wv.c b/drivers/video/s3c/s3cfb_lte480wv.c
+new file mode 100644
+index 0000000..6ca0a4b
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_lte480wv.c
+@@ -0,0 +1,98 @@
++/*
++ * drivers/video/s3c/s3cfb_lte480wv.c
++ *
++ * $Id: s3cfb_lte480wv.c,v 1.12 2008/06/05 02:13:24 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/wait.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-lcd.h>
++
++#include "s3cfb.h"
++
++#define S3C_FB_HFP 8 /* front porch */
++#define S3C_FB_HSW 3 /* hsync width */
++#define S3C_FB_HBP 13 /* back porch */
++
++#define S3C_FB_VFP 5 /* front porch */
++#define S3C_FB_VSW 1 /* vsync width */
++#define S3C_FB_VBP 7 /* back porch */
++
++#define S3C_FB_HRES 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES 480 /* line cnt y resolution */
++
++#define S3C_FB_HRES_VIRTUAL 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES_VIRTUAL 960 /* line cnt y resolution */
++
++#define S3C_FB_HRES_OSD 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES_OSD 480 /* line cnt y resolution */
++
++#define S3C_FB_VFRAME_FREQ 75 /* frame rate freq */
++
++#define S3C_FB_PIXEL_CLOCK (S3C_FB_VFRAME_FREQ * (S3C_FB_HFP + S3C_FB_HSW + S3C_FB_HBP + S3C_FB_HRES) * (S3C_FB_VFP + S3C_FB_VSW + S3C_FB_VBP + S3C_FB_VRES))
++
++static void s3cfb_set_fimd_info(void)
++{
++ s3c_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL;
++ s3c_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3C_FB_VBP - 1) | S3C_VIDTCON0_VFPD(S3C_FB_VFP - 1) | S3C_VIDTCON0_VSPW(S3C_FB_VSW - 1);
++ s3c_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3C_FB_HBP - 1) | S3C_VIDTCON1_HFPD(S3C_FB_HFP - 1) | S3C_VIDTCON1_HSPW(S3C_FB_HSW - 1);
++ s3c_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3C_FB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3C_FB_HRES - 1);
++
++ s3c_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES - 1);
++
++ s3c_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES_OSD - 1);
++
++ s3c_fimd.width = S3C_FB_HRES;
++ s3c_fimd.height = S3C_FB_VRES;
++ s3c_fimd.xres = S3C_FB_HRES;
++ s3c_fimd.yres = S3C_FB_VRES;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_fimd.xres_virtual = S3C_FB_HRES_VIRTUAL;
++ s3c_fimd.yres_virtual = S3C_FB_VRES_VIRTUAL;
++#else
++ s3c_fimd.xres_virtual = S3C_FB_HRES;
++ s3c_fimd.yres_virtual = S3C_FB_VRES;
++#endif
++
++ s3c_fimd.osd_width = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_height = S3C_FB_VRES_OSD;
++ s3c_fimd.osd_xres = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres = S3C_FB_VRES_OSD;
++
++ s3c_fimd.osd_xres_virtual = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres_virtual = S3C_FB_VRES_OSD;
++
++ s3c_fimd.pixclock = S3C_FB_PIXEL_CLOCK;
++
++ s3c_fimd.hsync_len = S3C_FB_HSW;
++ s3c_fimd.vsync_len = S3C_FB_VSW;
++ s3c_fimd.left_margin = S3C_FB_HFP;
++ s3c_fimd.upper_margin = S3C_FB_VFP;
++ s3c_fimd.right_margin = S3C_FB_HBP;
++ s3c_fimd.lower_margin = S3C_FB_VBP;
++}
++
++void s3cfb_init_hw(void)
++{
++ printk(KERN_INFO "LCD TYPE :: LTE480WV will be initialized\n");
++
++ s3cfb_set_fimd_info();
++ s3cfb_set_gpio();
++}
++
+diff --git a/drivers/video/s3c/s3cfb_lts222qv.c b/drivers/video/s3c/s3cfb_lts222qv.c
+new file mode 100644
+index 0000000..a43413b
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_lts222qv.c
+@@ -0,0 +1,311 @@
++/*
++ * drivers/video/s3c/s3cfb_lte480wv.c
++ *
++ * $Id: s3cfb_lts222qv.c,v 1.9 2008/06/19 11:11:34 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/wait.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-lcd.h>
++
++#include "s3cfb.h"
++
++#define S3C_FB_SPI_CH 0 /* spi channel for module init */
++
++#define S3C_FB_HFP 7 /* front porch */
++#define S3C_FB_HSW 4 /* hsync width */
++#define S3C_FB_HBP 2 /* back porch */
++
++#define S3C_FB_VFP 11 /* front porch */
++#define S3C_FB_VSW 4 /* vsync width */
++#define S3C_FB_VBP 10 /* back porch */
++
++#define S3C_FB_HRES 240 /* horizon pixel x resolition */
++#define S3C_FB_VRES 320 /* line cnt y resolution */
++
++#define S3C_FB_HRES_VIRTUAL 240 /* horizon pixel x resolition */
++#define S3C_FB_VRES_VIRTUAL 640 /* line cnt y resolution */
++
++#define S3C_FB_HRES_OSD 240 /* horizon pixel x resolition */
++#define S3C_FB_VRES_OSD 320 /* line cnt y resolution */
++
++#if defined(CONFIG_PLAT_S3C24XX)
++#define S3C_FB_VFRAME_FREQ 75 /* frame rate freq */
++#else
++#define S3C_FB_VFRAME_FREQ 60 /* frame rate freq */
++#endif
++
++#define S3C_FB_PIXEL_CLOCK (S3C_FB_VFRAME_FREQ * (S3C_FB_HFP + S3C_FB_HSW + S3C_FB_HBP + S3C_FB_HRES) * (S3C_FB_VFP + S3C_FB_VSW + S3C_FB_VBP + S3C_FB_VRES))
++
++static void s3cfb_set_fimd_info(void)
++{
++ s3c_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL;
++ s3c_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3C_FB_VBP - 1) | S3C_VIDTCON0_VFPD(S3C_FB_VFP - 1) | S3C_VIDTCON0_VSPW(S3C_FB_VSW - 1);
++ s3c_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3C_FB_HBP - 1) | S3C_VIDTCON1_HFPD(S3C_FB_HFP - 1) | S3C_VIDTCON1_HSPW(S3C_FB_HSW - 1);
++ s3c_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3C_FB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3C_FB_HRES - 1);
++
++ s3c_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES - 1);
++
++ s3c_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES_OSD - 1);
++
++ s3c_fimd.width = S3C_FB_HRES;
++ s3c_fimd.height = S3C_FB_VRES;
++ s3c_fimd.xres = S3C_FB_HRES;
++ s3c_fimd.yres = S3C_FB_VRES;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_fimd.xres_virtual = S3C_FB_HRES_VIRTUAL;
++ s3c_fimd.yres_virtual = S3C_FB_VRES_VIRTUAL;
++#else
++ s3c_fimd.xres_virtual = S3C_FB_HRES;
++ s3c_fimd.yres_virtual = S3C_FB_VRES;
++#endif
++
++ s3c_fimd.osd_width = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_height = S3C_FB_VRES_OSD;
++ s3c_fimd.osd_xres = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres = S3C_FB_VRES_OSD;
++
++ s3c_fimd.osd_xres_virtual = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres_virtual = S3C_FB_VRES_OSD;
++
++ s3c_fimd.pixclock = S3C_FB_PIXEL_CLOCK;
++
++ s3c_fimd.hsync_len = S3C_FB_HSW;
++ s3c_fimd.vsync_len = S3C_FB_VSW;
++ s3c_fimd.left_margin = S3C_FB_HFP;
++ s3c_fimd.upper_margin = S3C_FB_VFP;
++ s3c_fimd.right_margin = S3C_FB_HBP;
++ s3c_fimd.lower_margin = S3C_FB_VBP;
++}
++
++static void s3cfb_spi_write_byte(int data)
++{
++ unsigned int delay = 50;
++ int i;
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 1);
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 0);
++ udelay(delay);
++
++ for (i = 7; i >= 0; i--) {
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++
++ if ((data >> i) & 0x1)
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ else
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++ }
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++}
++
++static void s3cfb_spi_write(int address, int data)
++{
++ unsigned int mode = 0x8;
++
++ writel(mode | 0x01, S3C_SIFCCON0);
++ writel(mode | 0x03, S3C_SIFCCON0);
++
++ s3cfb_spi_write_byte(address);
++
++ writel(mode | 0x01, S3C_SIFCCON0);
++ writel(mode | 0x00, S3C_SIFCCON0);
++
++ udelay(100);
++
++ writel(mode | 0x01, S3C_SIFCCON0);
++ writel(mode | 0x03, S3C_SIFCCON0);
++
++ s3cfb_spi_write_byte(data);
++
++ writel(mode | 0x01, S3C_SIFCCON0);
++ writel(mode | 0x00, S3C_SIFCCON0);
++}
++
++static void s3cfb_init_ldi(void)
++{
++ unsigned long long endtime;
++
++ s3cfb_spi_write(0x22, 0x01);
++ s3cfb_spi_write(0x03, 0x01);
++
++ s3cfb_spi_write(0x00, 0xa0); udelay(5);
++ s3cfb_spi_write(0x01, 0x10); udelay(5);
++ s3cfb_spi_write(0x02, 0x00); udelay(5);
++ s3cfb_spi_write(0x05, 0x00); udelay(5);
++
++ s3cfb_spi_write(0x0d, 0x00);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x0e, 0x00); udelay(5);
++ s3cfb_spi_write(0x0f, 0x00); udelay(5);
++ s3cfb_spi_write(0x10, 0x00); udelay(5);
++ s3cfb_spi_write(0x11, 0x00); udelay(5);
++ s3cfb_spi_write(0x12, 0x00); udelay(5);
++ s3cfb_spi_write(0x13, 0x00); udelay(5);
++ s3cfb_spi_write(0x14, 0x00); udelay(5);
++ s3cfb_spi_write(0x15, 0x00); udelay(5);
++ s3cfb_spi_write(0x16, 0x00); udelay(5);
++ s3cfb_spi_write(0x17, 0x00); udelay(5);
++ s3cfb_spi_write(0x34, 0x01); udelay(5);
++
++ s3cfb_spi_write(0x35, 0x00);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x8d, 0x01); udelay(5);
++ s3cfb_spi_write(0x8b, 0x28); udelay(5);
++ s3cfb_spi_write(0x4b, 0x00); udelay(5);
++ s3cfb_spi_write(0x4e, 0x00); udelay(5);
++ s3cfb_spi_write(0x4d, 0x00); udelay(5);
++ s3cfb_spi_write(0x4e, 0x00); udelay(5);
++ s3cfb_spi_write(0x4f, 0x00); udelay(5);
++
++ s3cfb_spi_write(0x50, 0x00);
++ endtime = get_jiffies_64() + 5; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x86, 0x00); udelay(5);
++ s3cfb_spi_write(0x87, 0x26); udelay(5);
++ s3cfb_spi_write(0x88, 0x02); udelay(5);
++ s3cfb_spi_write(0x89, 0x05); udelay(5);
++ s3cfb_spi_write(0x33, 0x01); udelay(5);
++
++ s3cfb_spi_write(0x37, 0x06);
++ endtime = get_jiffies_64() + 5; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x76, 0x00);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x42, 0x00); udelay(5);
++ s3cfb_spi_write(0x43, 0x00); udelay(5);
++ s3cfb_spi_write(0x44, 0x00); udelay(5);
++ s3cfb_spi_write(0x45, 0x00); udelay(5);
++ s3cfb_spi_write(0x46, 0xef); udelay(5);
++ s3cfb_spi_write(0x47, 0x00); udelay(5);
++ s3cfb_spi_write(0x48, 0x00); udelay(5);
++
++ s3cfb_spi_write(0x49, 0x01);
++ endtime = get_jiffies_64() + 5; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x4a, 0x3f); udelay(5);
++ s3cfb_spi_write(0x3c, 0x00); udelay(5);
++ s3cfb_spi_write(0x3d, 0x00); udelay(5);
++ s3cfb_spi_write(0x3e, 0x01); udelay(5);
++ s3cfb_spi_write(0x3f, 0x3f); udelay(5);
++ s3cfb_spi_write(0x40, 0x01); udelay(5);
++ s3cfb_spi_write(0x41, 0x0a); udelay(5);
++
++ s3cfb_spi_write(0x8f, 0x3f);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x90, 0x3f); udelay(5);
++ s3cfb_spi_write(0x91, 0x33); udelay(5);
++ s3cfb_spi_write(0x92, 0x77); udelay(5);
++ s3cfb_spi_write(0x93, 0x77); udelay(5);
++ s3cfb_spi_write(0x94, 0x17); udelay(5);
++ s3cfb_spi_write(0x95, 0x3f); udelay(5);
++ s3cfb_spi_write(0x96, 0x00); udelay(5);
++ s3cfb_spi_write(0x97, 0x33); udelay(5);
++ s3cfb_spi_write(0x98, 0x77); udelay(5);
++ s3cfb_spi_write(0x99, 0x77); udelay(5);
++ s3cfb_spi_write(0x9a, 0x17); udelay(5);
++ s3cfb_spi_write(0x9b, 0x07); udelay(5);
++ s3cfb_spi_write(0x9c, 0x07); udelay(5);
++
++ s3cfb_spi_write(0x9d, 0x80);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x1d, 0x08);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x23, 0x00);
++ endtime = get_jiffies_64() + 5; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x24, 0x94);
++ endtime = get_jiffies_64() + 5; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x25, 0x6f);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x28, 0x1e);
++ s3cfb_spi_write(0x1a, 0x00);
++ s3cfb_spi_write(0x21, 0x10);
++ s3cfb_spi_write(0x18, 0x25);
++
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x19, 0x48);
++ s3cfb_spi_write(0x18, 0xe5);
++
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x18, 0xF7);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x1b, 0x07);
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x1f, 0x68);
++ s3cfb_spi_write(0x20, 0x45);
++ s3cfb_spi_write(0x1e, 0xc1);
++
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x21, 0x00);
++ s3cfb_spi_write(0x3b, 0x01);
++
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++
++ s3cfb_spi_write(0x00, 0x20);
++ s3cfb_spi_write(0x02, 0x01);
++
++ endtime = get_jiffies_64() + 4; while(jiffies < endtime);
++}
++
++static void s3cfb_set_gpio_lts222qv(void)
++{
++ gpio_direction_output(S3C_GPC1, 1);
++ gpio_direction_output(S3C_GPC2, 1);
++ gpio_direction_output(S3C_GPC3, 1);
++
++ gpio_pullup(S3C_GPC1, 0);
++ gpio_pullup(S3C_GPC2, 0);
++ gpio_pullup(S3C_GPC3, 0);
++}
++
++void s3cfb_init_hw(void)
++{
++ printk(KERN_INFO "LCD TYPE :: LTV222QV will be initialized\n");
++
++ s3cfb_set_fimd_info();
++ s3cfb_set_gpio();
++ s3cfb_set_gpio_lts222qv();
++ s3cfb_init_ldi();
++}
++
+diff --git a/drivers/video/s3c/s3cfb_ltv350qv.c b/drivers/video/s3c/s3cfb_ltv350qv.c
+new file mode 100644
+index 0000000..2b2ffd7
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_ltv350qv.c
+@@ -0,0 +1,288 @@
++/*
++ * drivers/video/s3c/s3cfb_lte480wv.c
++ *
++ * $Id: s3cfb_ltv350qv.c,v 1.8 2008/09/09 01:39:49 eyryu Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/wait.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-lcd.h>
++
++#include "s3cfb.h"
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C_FB_SPI_CH 0 /* spi channel for module init */
++#else
++#define S3C_FB_SPI_CH 1 /* spi channel for module init */
++#endif
++
++#define S3C_FB_HFP 3 /* front porch */
++#define S3C_FB_HSW 10 /* hsync width */
++#define S3C_FB_HBP 5 /* back porch */
++
++#define S3C_FB_VFP 3 /* front porch */
++#define S3C_FB_VSW 4 /* vsync width */
++#define S3C_FB_VBP 5 /* back porch */
++
++#define S3C_FB_HRES 320 /* horizon pixel x resolition */
++#define S3C_FB_VRES 240 /* line cnt y resolution */
++
++#define S3C_FB_HRES_VIRTUAL 320 /* horizon pixel x resolition */
++#define S3C_FB_VRES_VIRTUAL 480 /* line cnt y resolution */
++
++#define S3C_FB_HRES_OSD 320 /* horizon pixel x resolition */
++#define S3C_FB_VRES_OSD 240 /* line cnt y resolution */
++
++#if defined(CONFIG_PLAT_S3C24XX)
++#define S3C_FB_VFRAME_FREQ 75 /* frame rate freq */
++#else
++#define S3C_FB_VFRAME_FREQ 60 /* frame rate freq */
++#endif
++
++#define S3C_FB_PIXEL_CLOCK (S3C_FB_VFRAME_FREQ * (S3C_FB_HFP + S3C_FB_HSW + S3C_FB_HBP + S3C_FB_HRES) * (S3C_FB_VFP + S3C_FB_VSW + S3C_FB_VBP + S3C_FB_VRES))
++
++static void s3cfb_set_fimd_info(void)
++{
++ s3c_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL;
++ s3c_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3C_FB_VBP - 1) | S3C_VIDTCON0_VFPD(S3C_FB_VFP - 1) | S3C_VIDTCON0_VSPW(S3C_FB_VSW - 1);
++ s3c_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3C_FB_HBP - 1) | S3C_VIDTCON1_HFPD(S3C_FB_HFP - 1) | S3C_VIDTCON1_HSPW(S3C_FB_HSW - 1);
++ s3c_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3C_FB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3C_FB_HRES - 1);
++
++ s3c_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES - 1);
++
++ s3c_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES_OSD - 1);
++
++ s3c_fimd.width = S3C_FB_HRES;
++ s3c_fimd.height = S3C_FB_VRES;
++ s3c_fimd.xres = S3C_FB_HRES;
++ s3c_fimd.yres = S3C_FB_VRES;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_fimd.xres_virtual = S3C_FB_HRES_VIRTUAL;
++ s3c_fimd.yres_virtual = S3C_FB_VRES_VIRTUAL;
++#else
++ s3c_fimd.xres_virtual = S3C_FB_HRES;
++ s3c_fimd.yres_virtual = S3C_FB_VRES;
++#endif
++
++ s3c_fimd.osd_width = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_height = S3C_FB_VRES_OSD;
++ s3c_fimd.osd_xres = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres = S3C_FB_VRES_OSD;
++
++ s3c_fimd.osd_xres_virtual = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres_virtual = S3C_FB_VRES_OSD;
++
++ s3c_fimd.pixclock = S3C_FB_PIXEL_CLOCK;
++
++ s3c_fimd.hsync_len = S3C_FB_HSW;
++ s3c_fimd.vsync_len = S3C_FB_VSW;
++ s3c_fimd.left_margin = S3C_FB_HFP;
++ s3c_fimd.upper_margin = S3C_FB_VFP;
++ s3c_fimd.right_margin = S3C_FB_HBP;
++ s3c_fimd.lower_margin = S3C_FB_VBP;
++}
++
++void s3cfb_spi_write(int address, int data)
++{
++ unsigned int delay = 50;
++ unsigned char dev_id = 0x1d;
++ int i;
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 1);
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 0);
++ udelay(delay);
++
++ for (i = 5; i >= 0; i--) {
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++
++ if ((dev_id >> i) & 0x1)
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ else
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++ }
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ for (i = 15; i >= 0; i--) {
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++
++ if ((address >> i) & 0x1)
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ else
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++ }
++
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 1);
++ udelay(delay * 10);
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 0);
++ udelay(delay);
++
++ for (i = 5; i >= 0; i--) {
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++
++ if ((dev_id >> i) & 0x1)
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ else
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ }
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ for (i = 15; i >= 0; i--) {
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 0);
++
++ if ((data >> i) & 0x1)
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++ else
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 0);
++
++ udelay(delay);
++
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++
++ }
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 1);
++ udelay(delay);
++}
++
++static void s3cfb_init_ldi(void)
++{
++ s3cfb_spi_set_lcd_data(S3C_FB_SPI_CH);
++ mdelay(5);
++
++ s3cfb_spi_lcd_den(S3C_FB_SPI_CH, 1);
++ s3cfb_spi_lcd_dclk(S3C_FB_SPI_CH, 1);
++ s3cfb_spi_lcd_dseri(S3C_FB_SPI_CH, 1);
++
++ s3cfb_spi_write(0x01, 0x001d);
++ s3cfb_spi_write(0x02, 0x0000);
++ s3cfb_spi_write(0x03, 0x0000);
++ s3cfb_spi_write(0x04, 0x0000);
++ s3cfb_spi_write(0x05, 0x50a3);
++ s3cfb_spi_write(0x06, 0x0000);
++ s3cfb_spi_write(0x07, 0x0000);
++ s3cfb_spi_write(0x08, 0x0000);
++ s3cfb_spi_write(0x09, 0x0000);
++ s3cfb_spi_write(0x0a, 0x0000);
++ s3cfb_spi_write(0x10, 0x0000);
++ s3cfb_spi_write(0x11, 0x0000);
++ s3cfb_spi_write(0x12, 0x0000);
++ s3cfb_spi_write(0x13, 0x0000);
++ s3cfb_spi_write(0x14, 0x0000);
++ s3cfb_spi_write(0x15, 0x0000);
++ s3cfb_spi_write(0x16, 0x0000);
++ s3cfb_spi_write(0x17, 0x0000);
++ s3cfb_spi_write(0x18, 0x0000);
++ s3cfb_spi_write(0x19, 0x0000);
++
++ mdelay(10);
++
++ s3cfb_spi_write(0x09, 0x4055);
++ s3cfb_spi_write(0x0a, 0x0000);
++
++ mdelay(10);
++
++ s3cfb_spi_write(0x0a, 0x2000);
++
++ mdelay(50);
++
++ s3cfb_spi_write(0x01, 0x409d);
++ s3cfb_spi_write(0x02, 0x0204);
++ s3cfb_spi_write(0x03, 0x2100);
++ s3cfb_spi_write(0x04, 0x1000);
++ s3cfb_spi_write(0x05, 0x5003);
++ s3cfb_spi_write(0x06, 0x0009);
++ s3cfb_spi_write(0x07, 0x000f);
++ s3cfb_spi_write(0x08, 0x0800);
++ s3cfb_spi_write(0x10, 0x0000);
++ s3cfb_spi_write(0x11, 0x0000);
++ s3cfb_spi_write(0x12, 0x000f);
++ s3cfb_spi_write(0x13, 0x1f00);
++ s3cfb_spi_write(0x14, 0x0000);
++ s3cfb_spi_write(0x15, 0x0000);
++ s3cfb_spi_write(0x16, 0x0000);
++ s3cfb_spi_write(0x17, 0x0000);
++ s3cfb_spi_write(0x18, 0x0000);
++ s3cfb_spi_write(0x19, 0x0000);
++
++ mdelay(50);
++
++ s3cfb_spi_write(0x09, 0x4a55);
++ s3cfb_spi_write(0x0a, 0x2000);
++}
++
++void s3cfb_init_hw(void)
++{
++ printk(KERN_INFO "LCD TYPE :: LTV350QV will be initialized\n");
++
++ s3cfb_set_fimd_info();
++ s3cfb_set_gpio();
++ s3cfb_init_ldi();
++}
++
+diff --git a/drivers/video/s3c/s3cfb_spi.c b/drivers/video/s3c/s3cfb_spi.c
+new file mode 100644
+index 0000000..6fae264
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_spi.c
+@@ -0,0 +1,129 @@
++/*
++ * drivers/video/s3c/s3c24xxfb_spi.c
++ *
++ * $Id: s3cfb_spi.c,v 1.4 2008/08/27 01:04:36 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/delay.h>
++
++#include <asm/mach/map.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#if defined(CONFIG_PLAT_S3C24XX)
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
++
++#define S3C_FB_SPI_CLK(x) (S3C2443_GPL10 + (ch * 0))
++#define S3C_FB_SPI_MOSI(x) (S3C2443_GPL11 + (ch * 0))
++#define S3C_FB_SPI_CS(x) (S3C2443_GPL14 + (ch * 0))
++
++static inline void s3cfb_spi_lcd_dclk(int ch, int value)
++{
++ s3c2410_gpio_setpin(S3C_FB_SPI_CLK(ch), value);
++}
++
++static inline void s3cfb_spi_lcd_dseri(int ch, int value)
++{
++ s3c2410_gpio_setpin(S3C_FB_SPI_MOSI(ch), value);
++}
++
++static inline void s3cfb_spi_lcd_den(int ch, int value)
++{
++ s3c2410_gpio_setpin(S3C_FB_SPI_CS(ch), value);
++}
++
++static inline void s3cfb_spi_set_lcd_data(int ch)
++{
++ s3c2410_gpio_cfgpin(S3C_FB_SPI_CLK(ch), 1);
++ s3c2410_gpio_cfgpin(S3C_FB_SPI_MOSI(ch), 1);
++ s3c2410_gpio_cfgpin(S3C_FB_SPI_CS(ch), 1);
++
++ s3c2410_gpio_pullup(S3C_FB_SPI_CLK(ch), 2);
++ s3c2410_gpio_pullup(S3C_FB_SPI_MOSI(ch), 2);
++ s3c2410_gpio_pullup(S3C_FB_SPI_CS(ch), 2);
++}
++
++#elif defined(CONFIG_PLAT_S3C64XX)
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
++
++#define S3C_FB_SPI_CLK(x) (S3C_GPC1 + (ch * 4))
++#define S3C_FB_SPI_MOSI(x) (S3C_GPC2 + (ch * 4))
++#define S3C_FB_SPI_CS(x) (S3C_GPC3 + (ch * 4))
++
++inline void s3cfb_spi_lcd_dclk(int ch, int value)
++{
++ gpio_set_value(S3C_FB_SPI_CLK(ch), value);
++}
++
++inline void s3cfb_spi_lcd_dseri(int ch, int value)
++{
++ gpio_set_value(S3C_FB_SPI_MOSI(ch), value);
++}
++
++inline void s3cfb_spi_lcd_den(int ch, int value)
++{
++ gpio_set_value(S3C_FB_SPI_CS(ch), value);
++}
++
++inline void s3cfb_spi_set_lcd_data(int ch)
++{
++ gpio_direction_output(S3C_FB_SPI_CLK(ch), 1);
++ gpio_direction_output(S3C_FB_SPI_MOSI(ch), 1);
++ gpio_direction_output(S3C_FB_SPI_CS(ch), 1);
++
++ gpio_pullup(S3C_FB_SPI_CLK(ch), 0);
++ gpio_pullup(S3C_FB_SPI_MOSI(ch), 0);
++ gpio_pullup(S3C_FB_SPI_CS(ch), 0);
++}
++
++#elif defined(CONFIG_PLAT_S5PC1XX)
++
++#include <asm/plat-s5p/regs-gpio.h>
++
++#define S5P_FB_SPI_MISO(x) (S5P_GPB0 + (ch * 4))
++#define S5P_FB_SPI_CLK(x) (S5P_GPB1 + (ch * 4))
++#define S5P_FB_SPI_MOSI(x) (S5P_GPB2 + (ch * 4))
++#define S5P_FB_SPI_nSS(x) (S5P_GPB3 + (ch * 4))
++
++inline void s3cfb_spi_lcd_dclk(int ch, int value)
++{
++ gpio_set_value(S5P_FB_SPI_CLK(ch), value);
++}
++
++inline void s3cfb_spi_lcd_dseri(int ch, int value)
++{
++ gpio_set_value(S5P_FB_SPI_MOSI(ch), value);
++}
++
++inline void s3cfb_spi_lcd_den(int ch, int value)
++{
++ gpio_set_value(S5P_FB_SPI_nSS(ch), value);
++}
++
++inline void s3cfb_spi_set_lcd_data(int ch)
++{
++ gpio_direction_output(S5P_FB_SPI_CLK(ch), 1);
++ gpio_direction_output(S5P_FB_SPI_MOSI(ch), 1);
++ gpio_direction_output(S5P_FB_SPI_nSS(ch), 1);
++
++ gpio_pullup(S5P_FB_SPI_CLK(ch), S5P_GPIO_PUD_DISABLE);
++ gpio_pullup(S5P_FB_SPI_MOSI(ch), S5P_GPIO_PUD_DISABLE);
++ gpio_pullup(S5P_FB_SPI_nSS(ch), S5P_GPIO_PUD_DISABLE);
++}
++
++#endif
++
+diff --git a/drivers/video/s3c/s5pfb_fimd5x.c b/drivers/video/s3c/s5pfb_fimd5x.c
+new file mode 100644
+index 0000000..099c192
+--- /dev/null
++++ b/drivers/video/s3c/s5pfb_fimd5x.c
+@@ -0,0 +1,1259 @@
++/*
++ * drivers/video/s3c/s3c64xxfb.c
++ *
++ * $Id: s5pfb_fimd5x.c,v 1.6 2008/09/19 06:15:38 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/dma-mapping.h>
++#include <linux/string.h>
++#include <linux/ioctl.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#include <asm/mach/map.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/regs-lcd.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/plat-s5p/regs-gpio.h>
++
++#if defined(CONFIG_PM)
++#include <asm/plat-s3c24xx/pm.h>
++#endif
++
++#include "s3cfb.h"
++
++int s3c_vs_offset = S3C_FB_DEFAULT_DISPLAY_OFFSET;
++int s3c_osd_alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++int s3c_display_brightness = S3C_FB_DEFAULT_BRIGHTNESS;
++static int s3c_palette_win;
++
++s3c_fimd_info_t s3c_fimd = {
++ .vidcon0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_L1_DATA16_SUB_16_MODE | \
++ S3C_VIDCON0_L0_DATA16_MAIN_16_MODE | S3C_VIDCON0_PNRMODE_RGB_P | \
++ S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK | \
++ S3C_VIDCON0_ENVID_DISABLE | S3C_VIDCON0_ENVID_F_DISABLE,
++
++ .dithmode = (S3C_DITHMODE_RDITHPOS_5BIT | S3C_DITHMODE_GDITHPOS_6BIT | S3C_DITHMODE_BDITHPOS_5BIT ) & S3C_DITHMODE_DITHERING_DISABLE,
++
++#if defined (CONFIG_FB_S3C_BPP_8)
++ .wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL,
++ .wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .bpp = S3C_FB_PIXEL_BPP_8,
++ .bytes_per_pixel = 1,
++ .wpalcon = S3C_WPALCON_W0PAL_16BIT,
++
++#elif defined (CONFIG_FB_S3C_BPP_16)
++ .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_1 | S3C_WINCONx_BUFAUTOEN_DISABLE | \
++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon1 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | \
++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | \
++ S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon2 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | \
++ S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | \
++ S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon3 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | \
++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .wincon4 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \
++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE |
++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
++
++ .bpp = S3C_FB_PIXEL_BPP_16,
++ .bytes_per_pixel = 2,
++ .wpalcon = S3C_WPALCON_W0PAL_16BIT,
++
++#elif defined (CONFIG_FB_S3C_BPP_24)
++ .wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888,
++ .wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
++ .bpp = S3C_FB_PIXEL_BPP_24,
++ .bytes_per_pixel = 4,
++ .wpalcon = S3C_WPALCON_W0PAL_24BIT,
++#endif
++
++ .vidosd1c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++ .vidosd2c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++ .vidosd3c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++ .vidosd4c = S3C_VIDOSDxC_ALPHA1_B(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3C_FB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3C_FB_MAX_ALPHA_LEVEL),
++
++ .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | \
++ S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_ENABLE,
++ .vidintcon1 = 0,
++
++ .xoffset = 0,
++ .yoffset = 0,
++
++ .w1keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w1keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w2keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w2keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w3keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w3keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++ .w4keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0),
++ .w4keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff),
++
++ .sync = 0,
++ .cmap_static = 1,
++};
++
++/* should be fixed for c100 */
++#if defined(CONFIG_S3C6410_PWM)
++void s3cfb_set_brightness(int val)
++{
++ int channel = 1; /* must use channel-1 */
++ int usec = 0; /* don't care value */
++ unsigned long tcnt = 1000;
++ unsigned long tcmp = 0;
++
++ if (val < 0)
++ val = 0;
++
++ if (val > S3C_FB_MAX_BRIGHTNESS)
++ val = S3C_FB_MAX_BRIGHTNESS;
++
++ s3c_display_brightness = val;
++ tcmp = val * 50;
++
++ s3c6410_timer_setup(channel, usec, tcnt, tcmp);
++}
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++
++static void s3cfb_change_buff(int req_win, int req_fb)
++{
++ switch (req_win) {
++ case 0:
++ if (req_fb == 0)
++ s3c_fimd.wincon0 &= ~(1 << 20);
++ else
++ s3c_fimd.wincon0 |= (1 << 20);
++
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++ break;
++
++ case 1:
++ if (req_fb == 0)
++ s3c_fimd.wincon1 &= ~(1 << 20);
++ else
++ s3c_fimd.wincon1 |= (1 << 20);
++
++ writel(s3c_fimd.wincon1 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON1);
++ break;
++
++ default:
++ break;
++ }
++}
++
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++static int s3cfb_set_vs_registers(int vs_cmd)
++{
++ int page_width, offset;
++ int shift_value;
++
++ page_width = s3c_fimd.xres * s3c_fimd.bytes_per_pixel;
++ offset = (s3c_fimd.xres_virtual - s3c_fimd.xres) * s3c_fimd.bytes_per_pixel;
++
++ switch (vs_cmd){
++ case S3C_FB_VS_SET:
++ /* size of buffer */
++ s3c_fimd.vidw00add2 = S3C_VIDWxxADD2_OFFSIZE_F(offset) | S3C_VIDWxxADD2_PAGEWIDTH_F(page_width);
++ writel(s3c_fimd.vidw00add2, S3C_VIDW00ADD2);
++ break;
++
++ case S3C_FB_VS_MOVE_LEFT:
++ if (s3c_fimd.xoffset < s3c_vs_offset)
++ shift_value = s3c_fimd.xoffset;
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.xoffset -= shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 - (s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 - (s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_RIGHT:
++ if ((s3c_vs_info.v_width - (s3c_fimd.xoffset + s3c_vs_info.width)) < (s3c_vs_offset))
++ shift_value = s3c_vs_info.v_width - (s3c_fimd.xoffset + s3c_vs_info.width);
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.xoffset += shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 + (s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 + (s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_UP:
++ if (s3c_fimd.yoffset < s3c_vs_offset)
++ shift_value = s3c_fimd.yoffset;
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.yoffset -= shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 - (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 - (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ case S3C_FB_VS_MOVE_DOWN:
++ if ((s3c_vs_info.v_height - (s3c_fimd.yoffset + s3c_vs_info.height)) < (s3c_vs_offset))
++ shift_value = s3c_vs_info.v_height - (s3c_fimd.yoffset + s3c_vs_info.height);
++ else
++ shift_value = s3c_vs_offset;
++
++ s3c_fimd.yoffset += shift_value;
++
++ /* For buffer start address */
++ s3c_fimd.vidw00add0b0 = s3c_fimd.vidw00add0b0 + (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ s3c_fimd.vidw00add0b1 = s3c_fimd.vidw00add0b1 + (s3c_fimd.xres_virtual * s3c_fimd.bytes_per_pixel * shift_value);
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ /* End address */
++ s3c_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(s3c_fimd.vidw00add0b0 + (page_width + offset) * (s3c_fimd.yres));
++ s3c_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(s3c_fimd.vidw00add0b1 + (page_width + offset) * (s3c_fimd.yres));
++
++ writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ writel(s3c_fimd.vidw00add0b1, S3C_VIDW00ADD0B1);
++ writel(s3c_fimd.vidw00add1b0, S3C_VIDW00ADD1B0);
++ writel(s3c_fimd.vidw00add1b1, S3C_VIDW00ADD1B1);
++
++ return 0;
++}
++#endif
++
++void s3cfb_write_palette(s3c_fb_info_t *fbi)
++{
++ unsigned int i;
++ unsigned long ent;
++ unsigned int win_num = fbi->win_id;
++
++ fbi->palette_ready = 0;
++
++ writel((s3c_fimd.wpalcon | S3C_WPALCON_PALUPDATEEN), S3C_WPALCON);
++
++ for (i = 0; i < 256; i++) {
++ if ((ent = fbi->palette_buffer[i]) == S3C_FB_PALETTE_BUFF_CLEAR)
++ continue;
++
++ writel(ent, S3C_TFTPAL0(i) + 0x400 * win_num);
++
++ /* it seems the only way to know exactly
++ * if the palette wrote ok, is to check
++ * to see if the value verifies ok
++ */
++ if (readl(S3C_TFTPAL0(i) + 0x400 * win_num) == ent) {
++ fbi->palette_buffer[i] = S3C_FB_PALETTE_BUFF_CLEAR;
++ } else {
++ fbi->palette_ready = 1; /* retry */
++ printk("Retry writing into the palette\n");
++ }
++ }
++
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++}
++
++irqreturn_t s3cfb_irq(int irqno, void *param)
++{
++ unsigned long buffer_size = 0;
++ unsigned int i;
++ unsigned int buffer_page_offset, buffer_page_width;
++ unsigned int fb_start_address, fb_end_address;
++
++ if (s3c_fb_info[s3c_palette_win].palette_ready)
++ s3cfb_write_palette(&s3c_fb_info[s3c_palette_win]);
++
++ for (i = 0; i < CONFIG_FB_S3C_NUM; i++) {
++ if (s3c_fb_info[i].next_fb_info_change_req) {
++ /* fb variable setting */
++ s3c_fb_info[i].fb.fix.smem_start = s3c_fb_info[i].next_fb_info.phy_start_addr;
++
++ s3c_fb_info[i].fb.fix.line_length = s3c_fb_info[i].next_fb_info.xres_virtual *
++ s3c_fimd.bytes_per_pixel;
++
++ s3c_fb_info[i].fb.fix.smem_len = s3c_fb_info[i].next_fb_info.xres_virtual *
++ s3c_fb_info[i].next_fb_info.yres_virtual *
++ s3c_fimd.bytes_per_pixel;
++
++ s3c_fb_info[i].fb.var.xres = s3c_fb_info[i].next_fb_info.xres;
++ s3c_fb_info[i].fb.var.yres = s3c_fb_info[i].next_fb_info.yres;
++ s3c_fb_info[i].fb.var.xres_virtual = s3c_fb_info[i].next_fb_info.xres_virtual;
++ s3c_fb_info[i].fb.var.yres_virtual= s3c_fb_info[i].next_fb_info.yres_virtual;
++ s3c_fb_info[i].fb.var.xoffset = s3c_fb_info[i].next_fb_info.xoffset;
++ s3c_fb_info[i].fb.var.yoffset = s3c_fb_info[i].next_fb_info.yoffset;
++
++ s3c_fb_info[i].lcd_offset_x= s3c_fb_info[i].next_fb_info.lcd_offset_x;
++ s3c_fb_info[i].lcd_offset_y= s3c_fb_info[i].next_fb_info.lcd_offset_y;
++
++
++ /* fb start / end address setting */
++ fb_start_address = s3c_fb_info[i].next_fb_info.phy_start_addr +
++ s3c_fb_info[i].fb.fix.line_length * s3c_fb_info[i].next_fb_info.yoffset +
++ s3c_fb_info[i].next_fb_info.xoffset * s3c_fimd.bytes_per_pixel;
++
++ fb_end_address = fb_start_address + s3c_fb_info[i].fb.fix.line_length *
++ s3c_fb_info[i].next_fb_info.yres;
++
++ writel(fb_start_address, S3C_VIDW00ADD0B0 + 0x8 * i);
++ writel(S3C_VIDWxxADD1_VBASEL_F(fb_end_address), S3C_VIDW00ADD1B0 + 0x8 * i);
++
++
++ /* fb virtual / visible size setting */
++ buffer_page_width = s3c_fb_info[i].next_fb_info.xres * s3c_fimd.bytes_per_pixel;
++
++ buffer_page_offset = (s3c_fb_info[i].next_fb_info.xres_virtual -
++ s3c_fb_info[i].next_fb_info.xres) * s3c_fimd.bytes_per_pixel;
++
++ buffer_size = S3C_VIDWxxADD2_OFFSIZE_F(buffer_page_offset) |
++ (S3C_VIDWxxADD2_PAGEWIDTH_F(buffer_page_width));
++
++ writel(buffer_size, S3C_VIDW00ADD2 + 0x04 * i);
++
++ /* LCD position setting */
++ writel(S3C_VIDOSDxA_OSD_LTX_F(s3c_fb_info[i].next_fb_info.lcd_offset_x) |
++ S3C_VIDOSDxA_OSD_LTY_F(s3c_fb_info[i].next_fb_info.lcd_offset_y), S3C_VIDOSD0A+(0x10 * i));
++
++ writel(S3C_VIDOSDxB_OSD_RBX_F(s3c_fb_info[i].next_fb_info.lcd_offset_x - 1 + s3c_fb_info[i].next_fb_info.xres) |
++ S3C_VIDOSDxB_OSD_RBY_F(s3c_fb_info[i].next_fb_info.lcd_offset_y - 1 + s3c_fb_info[i].next_fb_info.yres),
++ S3C_VIDOSD0B + (0x10 * i));
++
++
++ /* fb size setting */
++ if (i == 0)
++ writel(S3C_VIDOSD0C_OSDSIZE(s3c_fb_info[i].next_fb_info.xres * s3c_fb_info[i].next_fb_info.yres), S3C_VIDOSD0C);
++ else if (i == 1)
++ writel(S3C_VIDOSD0C_OSDSIZE(s3c_fb_info[i].next_fb_info.xres * s3c_fb_info[i].next_fb_info.yres), S3C_VIDOSD1D);
++ else if (i == 2)
++ writel(S3C_VIDOSD0C_OSDSIZE(s3c_fb_info[i].next_fb_info.xres * s3c_fb_info[i].next_fb_info.yres), S3C_VIDOSD2D);
++
++ s3c_fb_info[i].next_fb_info_change_req = 0;
++ }
++ }
++
++ /* for clearing the interrupt source */
++ writel(readl(S3C_VIDINTCON1), S3C_VIDINTCON1);
++
++ s3c_vsync_info.count++;
++ wake_up_interruptible(&s3c_vsync_info.wait_queue);
++
++ return IRQ_HANDLED;
++}
++
++void s3cfb_enable_local_post(int in_yuv)
++{
++ unsigned int value;
++
++ s3c_fimd.wincon0 &= ~(1 << 22 | 1 << 13);
++ value = S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_ENWIN_F_ENABLE;
++
++ if (in_yuv)
++ value |= S3C_WINCONx_INRGB_YUV;
++
++ writel(s3c_fimd.wincon0 | value, S3C_WINCON0);
++}
++
++EXPORT_SYMBOL(s3cfb_enable_local_post);
++
++void s3cfb_enable_dma(void)
++{
++ u32 value;
++
++ s3c_fimd.wincon0 &= ~((1<<22)| (1<<13));
++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_ENWIN_F_ENABLE;
++
++ __raw_writel(s3c_fimd.wincon0 | value, S3C_WINCON0);
++}
++
++EXPORT_SYMBOL(s3cfb_enable_dma);
++
++int s3cfb_init_registers(s3c_fb_info_t *fbi)
++{
++ struct clk *lcd_clock;
++ struct fb_var_screeninfo *var = &fbi->fb.var;
++ unsigned long flags = 0, page_width = 0, offset = 0;
++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1;
++ unsigned long video_phy_temp_f2 = fbi->screen_dma_f2;
++ int win_num = fbi->win_id;
++
++ /* Initialise LCD with values from hare */
++ local_irq_save(flags);
++
++ page_width = var->xres * s3c_fimd.bytes_per_pixel;
++ offset = (var->xres_virtual - var->xres) * s3c_fimd.bytes_per_pixel;
++
++ if (win_num == 0) {
++ s3c_fimd.vidcon0 = s3c_fimd.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE);
++ writel(s3c_fimd.vidcon0, S3C_VIDCON0);
++
++ lcd_clock = clk_get(NULL, "lcd");
++ s3c_fimd.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int) ((clk_get_rate(lcd_clock) / s3c_fimd.pixclock) - 1));
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ offset = 0;
++ s3c_fimd.vidw00add0b0 = video_phy_temp_f1;
++ s3c_fimd.vidw00add0b1 = video_phy_temp_f2;
++ s3c_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres));
++ s3c_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres));
++#endif
++ }
++
++ writel(video_phy_temp_f1, S3C_VIDW00ADD0B0 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)), S3C_VIDW00ADD2 + (0x04 * win_num));
++
++ if (win_num < 2) {
++ writel(video_phy_temp_f2, S3C_VIDW00ADD0B1 + (0x08 * win_num));
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num));
++ }
++
++ switch (win_num) {
++ case 0:
++ writel(s3c_fimd.wincon0, S3C_WINCON0);
++ writel(s3c_fimd.vidcon0, S3C_VIDCON0);
++ writel(s3c_fimd.vidcon1, S3C_VIDCON1);
++ writel(s3c_fimd.vidtcon0, S3C_VIDTCON0);
++ writel(s3c_fimd.vidtcon1, S3C_VIDTCON1);
++ writel(s3c_fimd.vidtcon2, S3C_VIDTCON2);
++ writel(s3c_fimd.dithmode, S3C_DITHMODE);
++ writel(s3c_fimd.vidintcon0, S3C_VIDINTCON0);
++ writel(s3c_fimd.vidintcon1, S3C_VIDINTCON1);
++ writel(s3c_fimd.vidosd0a, S3C_VIDOSD0A);
++ writel(s3c_fimd.vidosd0b, S3C_VIDOSD0B);
++ writel(s3c_fimd.vidosd0c, S3C_VIDOSD0C);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, ON);
++ break;
++
++ case 1:
++ writel(s3c_fimd.wincon1, S3C_WINCON1);
++ writel(s3c_fimd.vidosd1a, S3C_VIDOSD1A);
++ writel(s3c_fimd.vidosd1b, S3C_VIDOSD1B);
++ writel(s3c_fimd.vidosd1c, S3C_VIDOSD1C);
++ writel(s3c_fimd.vidosd1d, S3C_VIDOSD1D);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case 2:
++ writel(s3c_fimd.wincon2, S3C_WINCON2);
++ writel(s3c_fimd.vidosd2a, S3C_VIDOSD2A);
++ writel(s3c_fimd.vidosd2b, S3C_VIDOSD2B);
++ writel(s3c_fimd.vidosd2c, S3C_VIDOSD2C);
++ writel(s3c_fimd.vidosd2d, S3C_VIDOSD2D);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case 3:
++ writel(s3c_fimd.wincon3, S3C_WINCON3);
++ writel(s3c_fimd.vidosd3a, S3C_VIDOSD3A);
++ writel(s3c_fimd.vidosd3b, S3C_VIDOSD3B);
++ writel(s3c_fimd.vidosd3c, S3C_VIDOSD3C);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case 4:
++ writel(s3c_fimd.wincon4, S3C_WINCON4);
++ writel(s3c_fimd.vidosd4a, S3C_VIDOSD4A);
++ writel(s3c_fimd.vidosd4b, S3C_VIDOSD4B);
++ writel(s3c_fimd.vidosd4c, S3C_VIDOSD4C);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++ }
++
++ local_irq_restore(flags);
++
++ return 0;
++ }
++
++void s3cfb_activate_var(s3c_fb_info_t *fbi, struct fb_var_screeninfo *var)
++{
++ DPRINTK("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ s3c_fimd.wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_8;
++ s3c_fimd.bytes_per_pixel = 1;
++ s3c_fimd.wpalcon = S3C_WPALCON_W0PAL_16BIT;
++ break;
++
++ case 16:
++ s3c_fimd.wincon0 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_16;
++ s3c_fimd.bytes_per_pixel = 2;
++ break;
++
++ case 24:
++ s3c_fimd.wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888;
++ s3c_fimd.wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1;
++ s3c_fimd.bpp = S3C_FB_PIXEL_BPP_24;
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++
++ case 32:
++ s3c_fimd.bytes_per_pixel = 4;
++ break;
++ }
++
++ /* write new registers */
++ writel(s3c_fimd.wincon0, S3C_WINCON0);
++ writel(s3c_fimd.wincon1, S3C_WINCON1);
++ writel(s3c_fimd.wincon2, S3C_WINCON2);
++ writel(s3c_fimd.wincon3, S3C_WINCON3);
++ writel(s3c_fimd.wincon4, S3C_WINCON4);
++ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++ writel(s3c_fimd.vidcon0 | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
++}
++
++/* JJNAHM comment.
++ * We had some problems related to frame buffer address.
++ * We used 2 frame buffers (FB0 and FB1) and GTK used FB1.
++ * When GTK launched, GTK set FB0's address to FB1's address.
++ * (GTK calls s3c_fb_pan_display() and then it calls this s3c_fb_set_lcdaddr())
++ * Even though fbi->win_id is not 0, above original codes set ONLY FB0's address.
++ * So, I modified the codes like below.
++ * It works by fbi->win_id value.
++ * Below codes are not verified yet
++ * and there are nothing about Double buffering features
++ */
++void s3cfb_set_fb_addr(s3c_fb_info_t *fbi)
++{
++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1;
++ unsigned long start_address, end_address;
++ unsigned int start;
++
++ start = fbi->fb.fix.line_length * fbi->fb.var.yoffset;
++
++ /* for buffer start address and end address */
++ start_address = video_phy_temp_f1 + start;
++ end_address = start_address + (fbi->fb.fix.line_length * fbi->fb.var.yres);
++
++ switch (fbi->win_id)
++ {
++ case 0:
++ s3c_fimd.vidw00add0b0 = start_address;
++ s3c_fimd.vidw00add1b0 = end_address;
++ __raw_writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ __raw_writel(s3c_fimd.vidw00add1b0, S3C_VIDW00ADD1B0);
++ break;
++
++ case 1:
++ s3c_fimd.vidw01add0b0 = start_address;
++ s3c_fimd.vidw01add1b0 = end_address;
++ __raw_writel(s3c_fimd.vidw01add0b0, S3C_VIDW01ADD0B0);
++ __raw_writel(s3c_fimd.vidw01add1b0, S3C_VIDW01ADD1B0);
++ break;
++
++ case 2:
++ s3c_fimd.vidw02add0 = start_address;
++ s3c_fimd.vidw02add1 = end_address;
++ __raw_writel(s3c_fimd.vidw02add0, S3C_VIDW02ADD0);
++ __raw_writel(s3c_fimd.vidw02add1, S3C_VIDW02ADD1);
++ break;
++
++ case 3:
++ s3c_fimd.vidw03add0 = start_address;
++ s3c_fimd.vidw03add1 = end_address;
++ __raw_writel(s3c_fimd.vidw03add0, S3C_VIDW03ADD0);
++ __raw_writel(s3c_fimd.vidw03add1, S3C_VIDW03ADD1);
++ break;
++
++ case 4:
++ s3c_fimd.vidw04add0 = start_address;
++ s3c_fimd.vidw04add1 = end_address;
++ __raw_writel(s3c_fimd.vidw04add0, S3C_VIDW04ADD0);
++ __raw_writel(s3c_fimd.vidw04add1, S3C_VIDW04ADD1);
++ break;
++ }
++}
++
++static int s3cfb_set_alpha_level(s3c_fb_info_t *fbi, unsigned int level, unsigned int alpha_index)
++{
++ unsigned long alpha_val;
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support alpha blending.\n");
++ return -1;
++ }
++
++ alpha_val = readl(S3C_VIDOSD0C+(0x10 * win_num));
++
++ if (alpha_index == 0) {
++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA0_B(0xf) | S3C_VIDOSDxC_ALPHA0_G(0xf) | S3C_VIDOSDxC_ALPHA0_R(0xf));
++ alpha_val |= S3C_VIDOSDxC_ALPHA0_B(level) | S3C_VIDOSDxC_ALPHA0_G(level) | S3C_VIDOSDxC_ALPHA0_R(level);
++ } else {
++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA1_B(0xf) | S3C_VIDOSDxC_ALPHA1_G(0xf) | S3C_VIDOSDxC_ALPHA1_R(0xf));
++ alpha_val = S3C_VIDOSDxC_ALPHA1_B(level) | S3C_VIDOSDxC_ALPHA1_G(level) | S3C_VIDOSDxC_ALPHA1_R(level);
++ }
++
++ writel(alpha_val, S3C_VIDOSD0C + (0x10 * win_num));
++
++ return 0;
++}
++
++int s3cfb_set_alpha_mode(s3c_fb_info_t *fbi, int mode)
++{
++ unsigned long alpha_mode;
++ int win_num = fbi->win_id;
++
++ if (win_num == 0) {
++ printk("WIN0 do not support alpha blending.\n");
++ return -1;
++ }
++
++ alpha_mode = readl(S3C_WINCON0 + (0x04 * win_num));
++ alpha_mode &= ~(S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1);
++
++ switch (mode) {
++ case 0: /* Plane Blending */
++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, S3C_WINCON0 + (0x04 * win_num));
++ break;
++
++ case 1: /* Pixel Blending & chroma(color) key */
++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_0, S3C_WINCON0 + (0x04 * win_num));
++ break;
++ }
++
++ return 0;
++}
++
++int s3cfb_set_win_position(s3c_fb_info_t *fbi, int left_x, int top_y, int width, int height)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++
++ writel(S3C_VIDOSDxA_OSD_LTX_F(left_x) | S3C_VIDOSDxA_OSD_LTY_F(top_y), S3C_VIDOSD0A + (0x10 * win_num));
++ writel(S3C_VIDOSDxB_OSD_RBX_F(width - 1 + left_x) | S3C_VIDOSDxB_OSD_RBY_F(height - 1 + top_y), S3C_VIDOSD0B + (0x10 * win_num));
++
++ var->xoffset = left_x;
++ var->yoffset = top_y;
++
++ return 0;
++}
++
++int s3cfb_set_win_size(s3c_fb_info_t *fbi, int width, int height)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++
++ if (win_num == 1)
++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD1D);
++
++ else if (win_num == 2)
++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD2D);
++
++ var->xres = width;
++ var->yres = height;
++ var->xres_virtual = width;
++ var->yres_virtual = height;
++
++ return 0;
++}
++
++int s3cfb_set_fb_size(s3c_fb_info_t *fbi)
++{
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ int win_num = fbi->win_id;
++ unsigned long offset = 0;
++ unsigned long page_width = 0;
++ unsigned long fb_size = 0;
++
++ page_width = var->xres * s3c_fimd.bytes_per_pixel;
++ offset = (var->xres_virtual - var->xres) * s3c_fimd.bytes_per_pixel;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ if (win_num == 0)
++ offset=0;
++#endif
++
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B0 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num));
++
++ if (win_num == 1)
++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B1 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num));
++
++ /* size of frame buffer */
++ fb_size = S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width));
++
++ writel(fb_size, S3C_VIDW00ADD2 + (0x04 * win_num));
++
++ return 0;
++}
++
++void s3cfb_set_output_path(int out)
++{
++ unsigned int tmp;
++
++ tmp = readl(S3C_VIDCON0);
++
++ /* if output mode is LCD mode, Scan mode always should be progressive mode */
++ if (out == S3C_FB_OUTPUT_TV)
++ tmp &= ~(1 << 29);
++
++ tmp &= ~(0x7 << 26);
++ tmp |= (out << 26);
++
++ writel(tmp, S3C_VIDCON0);
++}
++
++EXPORT_SYMBOL(s3cfb_set_output_path);
++
++void s3cfb_enable_rgbport(int on)
++{
++ if (on)
++ writel(0x380, S3C_VIDCON2);
++ else
++ writel(0x0, S3C_VIDCON2);
++}
++
++EXPORT_SYMBOL(s3cfb_enable_rgbport);
++
++int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
++{
++ s3c_fb_info_t *fbi = container_of(info, s3c_fb_info_t, fb);
++ s3c_win_info_t win_info;
++ s3c_color_key_info_t colkey_info;
++ s3c_color_val_info_t colval_info;
++ s3c_fb_dma_info_t dma_info;
++ s3c_fb_next_info_t next_fb_info;
++ struct fb_var_screeninfo *var= &fbi->fb.var;
++ unsigned int crt, alpha_level, alpha_mode;
++
++/* should be fixed for c100 */
++#if defined(CONFIG_S3C6410_PWM)
++ int brightness;
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ unsigned int f_num_val;
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_vs_info_t vs_info;
++#endif
++
++ switch(cmd){
++ case S3C_FB_GET_INFO:
++ dma_info.map_dma_f1 = fbi->map_dma_f1;
++ dma_info.map_dma_f2 = fbi->map_dma_f2;
++
++ if(copy_to_user((void *) arg, (const void *) &dma_info, sizeof(s3c_fb_dma_info_t)))
++ return -EFAULT;
++ break;
++
++ case S3C_FB_OSD_SET_INFO:
++ if (copy_from_user(&win_info, (s3c_win_info_t *) arg, sizeof(s3c_win_info_t)))
++ return -EFAULT;
++
++ s3cfb_init_win(fbi, win_info.bpp, win_info.left_x, win_info.top_y, win_info.width, win_info.height, OFF);
++ break;
++
++ case S3C_FB_OSD_START:
++ s3cfb_onoff_win(fbi, ON);
++ break;
++
++ case S3C_FB_OSD_STOP:
++ if (fbi->win_id > 0)
++ s3cfb_set_alpha_level(fbi, S3C_FB_MAX_ALPHA_LEVEL, 1);
++
++ s3cfb_onoff_win(fbi, OFF);
++ break;
++
++ case S3C_FB_OSD_ALPHA_UP:
++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf;
++
++ if (alpha_level < S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level++;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 1);
++ break;
++
++ case S3C_FB_OSD_ALPHA_DOWN:
++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf;
++
++ if (alpha_level > 0)
++ alpha_level--;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 1);
++ break;
++
++ case S3C_FB_OSD_ALPHA0_SET:
++ alpha_level = arg;
++
++ if (alpha_level > S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++ else if(alpha_level < 0)
++ alpha_level = 0;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 0);
++ break;
++
++ case S3C_FB_OSD_ALPHA_SET:
++ if (copy_from_user(&alpha_level, (int *) arg, sizeof(int)))
++ return -EFAULT;
++
++ if (alpha_level > S3C_FB_MAX_ALPHA_LEVEL)
++ alpha_level = S3C_FB_MAX_ALPHA_LEVEL;
++ else if (alpha_level < 0)
++ alpha_level = 0;
++
++ s3cfb_set_alpha_level(fbi, alpha_level, 1);
++ break;
++
++ case S3C_FB_OSD_ALPHA_MODE:
++ alpha_mode = arg;
++ s3cfb_set_alpha_mode(fbi, alpha_mode);
++ break;
++
++ case S3C_FB_OSD_MOVE_LEFT:
++ if (var->xoffset > 0)
++ var->xoffset--;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_RIGHT:
++ if (var->xoffset < (s3c_fimd.width - var->xres))
++ var->xoffset++;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_UP:
++ if (var->yoffset > 0)
++ var->yoffset--;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case S3C_FB_OSD_MOVE_DOWN:
++ if (var->yoffset < (s3c_fimd.height - var->yres))
++ var->yoffset++;
++
++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
++ break;
++
++ case FBIO_WAITFORVSYNC:
++ if (get_user(crt, (unsigned int __user *)arg))
++ return -EFAULT;
++
++ return s3cfb_wait_for_vsync();
++
++ case S3C_FB_COLOR_KEY_START:
++ s3cfb_onoff_color_key(fbi, ON);
++ break;
++
++ case S3C_FB_COLOR_KEY_STOP:
++ s3cfb_onoff_color_key(fbi, OFF);
++ break;
++
++ case S3C_FB_COLOR_KEY_ALPHA_START:
++ s3cfb_onoff_color_key_alpha(fbi, ON);
++ break;
++
++ case S3C_FB_COLOR_KEY_ALPHA_STOP:
++ s3cfb_onoff_color_key_alpha(fbi, OFF);
++ break;
++
++ case S3C_FB_COLOR_KEY_SET_INFO:
++ if (copy_from_user(&colkey_info, (s3c_color_key_info_t *) arg, sizeof(s3c_color_key_info_t)))
++ return -EFAULT;
++
++ s3cfb_set_color_key_registers(fbi, colkey_info);
++ break;
++
++ case S3C_FB_COLOR_KEY_VALUE:
++ if (copy_from_user(&colval_info, (s3c_color_val_info_t *) arg, sizeof(s3c_color_val_info_t)))
++ return -EFAULT;
++
++ s3cfb_set_color_value(fbi, colval_info);
++ break;
++
++ case S3C_FB_SET_VSYNC_INT:
++ s3c_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK;
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC;
++
++ if (arg)
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
++ else
++ s3c_fimd.vidintcon0 &= ~S3C_VIDINTCON0_INTFRMEN_ENABLE;
++
++ writel(s3c_fimd.vidintcon0, S3C_VIDINTCON0);
++ break;
++
++ case S3C_FB_SET_NEXT_FB_INFO:
++ if (copy_from_user(&next_fb_info, (s3c_fb_next_info_t *) arg, sizeof(s3c_fb_next_info_t)))
++ return -EFAULT;
++
++ /* check arguments */
++ if ((next_fb_info.xres + next_fb_info.xoffset) > next_fb_info.xres_virtual ||
++ (next_fb_info.yres + next_fb_info.yoffset) > next_fb_info.yres_virtual ||
++ (next_fb_info.xres + next_fb_info.lcd_offset_x ) > s3c_fimd.width ||
++ (next_fb_info.yres + next_fb_info.lcd_offset_y ) > s3c_fimd.height)
++ return -EINVAL;
++
++ fbi->next_fb_info = next_fb_info;
++ fbi->next_fb_info_change_req = 1;
++ break;
++
++ case S3C_FB_GET_CURR_FB_INFO:
++ next_fb_info.phy_start_addr = fbi->fb.fix.smem_start;
++ next_fb_info.xres = fbi->fb.var.xres;
++ next_fb_info.yres = fbi->fb.var.yres;
++ next_fb_info.xres_virtual = fbi->fb.var.xres_virtual;
++ next_fb_info.yres_virtual = fbi->fb.var.yres_virtual;
++ next_fb_info.xoffset = fbi->fb.var.xoffset;
++ next_fb_info.yoffset = fbi->fb.var.yoffset;
++ next_fb_info.lcd_offset_x = fbi->lcd_offset_x;
++ next_fb_info.lcd_offset_y = fbi->lcd_offset_y;
++
++ if (copy_to_user((void *)arg, (s3c_fb_next_info_t *) &next_fb_info, sizeof(s3c_fb_next_info_t)))
++ return -EFAULT;
++ break;
++
++ case S3C_FB_GET_BRIGHTNESS:
++ if (copy_to_user((void *)arg, (const void *) &s3c_display_brightness, sizeof(int)))
++ return -EFAULT;
++ break;
++
++/* should be fixed for c100 */
++#if defined(CONFIG_S3C6410_PWM)
++ case S3C_FB_SET_BRIGHTNESS:
++ if (copy_from_user(&brightness, (int *) arg, sizeof(int)))
++ return -EFAULT;
++
++ s3cfb_set_brightness(brightness);
++ break;
++#endif
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ case S3C_FB_VS_START:
++ s3c_fimd.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE);
++ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++
++ case S3C_FB_VS_STOP:
++ s3c_fimd.vidw00add0b0 = fbi->screen_dma_f1;
++ s3c_fimd.vidw00add0b1 = fbi->screen_dma_f2;
++ fbi->fb.var.xoffset = 0;
++ fbi->fb.var.yoffset = 0;
++
++ writel(s3c_fimd.vidw00add0b0, S3C_VIDW00ADD0B0);
++ writel(s3c_fimd.vidw00add0b1, S3C_VIDW00ADD0B1);
++
++ break;
++
++ case S3C_FB_VS_SET_INFO:
++ if (copy_from_user(&vs_info, (s3c_vs_info_t *) arg, sizeof(s3c_vs_info_t)))
++ return -EFAULT;
++
++ if (s3cfb_set_vs_info(vs_info)) {
++ printk("Error S3C_FB_VS_SET_INFO\n");
++ return -EINVAL;
++ }
++
++ s3cfb_set_vs_registers(S3C_FB_VS_SET);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++
++ case S3C_FB_VS_MOVE:
++ s3cfb_set_vs_registers(arg);
++
++ fbi->fb.var.xoffset = s3c_fimd.xoffset;
++ fbi->fb.var.yoffset = s3c_fimd.yoffset;
++ break;
++#endif
++
++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
++ case S3C_FB_GET_NUM:
++ if (copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int)))
++ return -EFAULT;
++
++ if (copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int)))
++ return -EFAULT;
++
++ break;
++
++ case S3C_FB_CHANGE_REQ:
++ s3cfb_change_buff(0, (int) arg);
++ break;
++#endif
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++void s3cfb_pre_init(void)
++{
++ /* initialize the fimd specific */
++ s3c_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK;
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC;
++ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
++
++ writel(s3c_fimd.vidintcon0, S3C_VIDINTCON0);
++}
++
++void s3cfb_set_gpio(void)
++{
++ /* LCD_HSYNC, LCD_VSYNC, LCD_VDEN, LCD_VCLK, VD[23:0] */
++ writel(0x22222222, S5P_GPF0_CON);
++ writel(0x22222222, S5P_GPF1_CON);
++ writel(0x22222222, S5P_GPF2_CON);
++ writel(0x00002222, S5P_GPF3_CON);
++
++ /* module reset */
++ gpio_direction_output(S5P_GPH3_6, 1);
++ mdelay(100);
++
++ gpio_set_value(S5P_GPH3_6, 0);
++ mdelay(10);
++
++ gpio_set_value(S5P_GPH3_6, 1);
++ mdelay(10);
++}
++
++#if defined(CONFIG_PM)
++
++static struct sleep_save s3c_lcd_save[] = {
++ SAVE_ITEM(S3C_VIDCON0),
++ SAVE_ITEM(S3C_VIDCON1),
++
++ SAVE_ITEM(S3C_VIDTCON0),
++ SAVE_ITEM(S3C_VIDTCON1),
++ SAVE_ITEM(S3C_VIDTCON2),
++ SAVE_ITEM(S3C_VIDTCON3),
++
++ SAVE_ITEM(S3C_WINCON0),
++ SAVE_ITEM(S3C_WINCON1),
++ SAVE_ITEM(S3C_WINCON2),
++ SAVE_ITEM(S3C_WINCON3),
++ SAVE_ITEM(S3C_WINCON4),
++
++ SAVE_ITEM(S3C_VIDOSD0A),
++ SAVE_ITEM(S3C_VIDOSD0B),
++ SAVE_ITEM(S3C_VIDOSD0C),
++
++ SAVE_ITEM(S3C_VIDOSD1A),
++ SAVE_ITEM(S3C_VIDOSD1B),
++ SAVE_ITEM(S3C_VIDOSD1C),
++ SAVE_ITEM(S3C_VIDOSD1D),
++
++ SAVE_ITEM(S3C_VIDOSD2A),
++ SAVE_ITEM(S3C_VIDOSD2B),
++ SAVE_ITEM(S3C_VIDOSD2C),
++ SAVE_ITEM(S3C_VIDOSD2D),
++
++ SAVE_ITEM(S3C_VIDOSD3A),
++ SAVE_ITEM(S3C_VIDOSD3B),
++ SAVE_ITEM(S3C_VIDOSD3C),
++
++ SAVE_ITEM(S3C_VIDOSD4A),
++ SAVE_ITEM(S3C_VIDOSD4B),
++ SAVE_ITEM(S3C_VIDOSD4C),
++
++ SAVE_ITEM(S3C_VIDW00ADD0B0),
++ SAVE_ITEM(S3C_VIDW00ADD0B1),
++ SAVE_ITEM(S3C_VIDW01ADD0B0),
++ SAVE_ITEM(S3C_VIDW01ADD0B1),
++ SAVE_ITEM(S3C_VIDW02ADD0),
++ SAVE_ITEM(S3C_VIDW03ADD0),
++ SAVE_ITEM(S3C_VIDW04ADD0),
++ SAVE_ITEM(S3C_VIDW00ADD1B0),
++ SAVE_ITEM(S3C_VIDW00ADD1B1),
++ SAVE_ITEM(S3C_VIDW01ADD1B0),
++ SAVE_ITEM(S3C_VIDW01ADD1B1),
++ SAVE_ITEM(S3C_VIDW02ADD1),
++ SAVE_ITEM(S3C_VIDW03ADD1),
++ SAVE_ITEM(S3C_VIDW04ADD1),
++ SAVE_ITEM(S3C_VIDW00ADD2),
++ SAVE_ITEM(S3C_VIDW01ADD2),
++ SAVE_ITEM(S3C_VIDW02ADD2),
++ SAVE_ITEM(S3C_VIDW03ADD2),
++ SAVE_ITEM(S3C_VIDW04ADD2),
++
++ SAVE_ITEM(S3C_VIDINTCON0),
++ SAVE_ITEM(S3C_VIDINTCON1),
++ SAVE_ITEM(S3C_W1KEYCON0),
++ SAVE_ITEM(S3C_W1KEYCON1),
++ SAVE_ITEM(S3C_W2KEYCON0),
++ SAVE_ITEM(S3C_W2KEYCON1),
++
++ SAVE_ITEM(S3C_W3KEYCON0),
++ SAVE_ITEM(S3C_W3KEYCON1),
++ SAVE_ITEM(S3C_W4KEYCON0),
++ SAVE_ITEM(S3C_W4KEYCON1),
++ SAVE_ITEM(S3C_DITHMODE),
++
++ SAVE_ITEM(S3C_WIN0MAP),
++ SAVE_ITEM(S3C_WIN1MAP),
++ SAVE_ITEM(S3C_WIN2MAP),
++ SAVE_ITEM(S3C_WIN3MAP),
++ SAVE_ITEM(S3C_WIN4MAP),
++ SAVE_ITEM(S3C_WPALCON),
++
++ SAVE_ITEM(S3C_TRIGCON),
++ SAVE_ITEM(S3C_I80IFCONA0),
++ SAVE_ITEM(S3C_I80IFCONA1),
++ SAVE_ITEM(S3C_I80IFCONB0),
++ SAVE_ITEM(S3C_I80IFCONB1),
++ SAVE_ITEM(S3C_LDI_CMDCON0),
++ SAVE_ITEM(S3C_LDI_CMDCON1),
++ SAVE_ITEM(S3C_SIFCCON0),
++ SAVE_ITEM(S3C_SIFCCON1),
++ SAVE_ITEM(S3C_SIFCCON2),
++
++ SAVE_ITEM(S3C_LDI_CMD0),
++ SAVE_ITEM(S3C_LDI_CMD1),
++ SAVE_ITEM(S3C_LDI_CMD2),
++ SAVE_ITEM(S3C_LDI_CMD3),
++ SAVE_ITEM(S3C_LDI_CMD4),
++ SAVE_ITEM(S3C_LDI_CMD5),
++ SAVE_ITEM(S3C_LDI_CMD6),
++ SAVE_ITEM(S3C_LDI_CMD7),
++ SAVE_ITEM(S3C_LDI_CMD8),
++ SAVE_ITEM(S3C_LDI_CMD9),
++ SAVE_ITEM(S3C_LDI_CMD10),
++ SAVE_ITEM(S3C_LDI_CMD11),
++
++ SAVE_ITEM(S3C_W2PDATA01),
++ SAVE_ITEM(S3C_W2PDATA23),
++ SAVE_ITEM(S3C_W2PDATA45),
++ SAVE_ITEM(S3C_W2PDATA67),
++ SAVE_ITEM(S3C_W2PDATA89),
++ SAVE_ITEM(S3C_W2PDATAAB),
++ SAVE_ITEM(S3C_W2PDATACD),
++ SAVE_ITEM(S3C_W2PDATAEF),
++ SAVE_ITEM(S3C_W3PDATA01),
++ SAVE_ITEM(S3C_W3PDATA23),
++ SAVE_ITEM(S3C_W3PDATA45),
++ SAVE_ITEM(S3C_W3PDATA67),
++ SAVE_ITEM(S3C_W3PDATA89),
++ SAVE_ITEM(S3C_W3PDATAAB),
++ SAVE_ITEM(S3C_W3PDATACD),
++ SAVE_ITEM(S3C_W3PDATAEF),
++ SAVE_ITEM(S3C_W4PDATA01),
++ SAVE_ITEM(S3C_W4PDATA23),
++};
++
++/*
++ * Suspend
++ */
++int s3cfb_suspend(struct platform_device *dev, pm_message_t state)
++{
++ struct fb_info *fbinfo = platform_get_drvdata(dev);
++ s3c_fb_info_t *info = fbinfo->par;
++
++ s3cfb_stop_lcd();
++ s3c2410_pm_do_save(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
++
++ /* sleep before disabling the clock, we need to ensure
++ * the LCD DMA engine is not going to get back on the bus
++ * before the clock goes off again (bjd) */
++
++ msleep(1);
++ clk_disable(info->clk);
++
++ return 0;
++}
++
++/*
++ * Resume
++ */
++int s3cfb_resume(struct platform_device *dev)
++{
++ struct fb_info *fbinfo = platform_get_drvdata(dev);
++ s3c_fb_info_t *info = fbinfo->par;
++
++ clk_enable(info->clk);
++ msleep(1);
++ s3c2410_pm_do_restore(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
++
++ s3cfb_init_hw();
++ s3cfb_start_lcd();
++
++ return 0;
++}
++
++#else
++
++int s3cfb_suspend(struct platform_device *dev, pm_message_t state)
++{
++ return 0;
++}
++
++int s3cfb_resume(struct platform_device *dev)
++{
++ return 0;
++}
++
++#endif
++
+diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
+index b3c31d9..8900ad9 100644
+--- a/drivers/video/s3c2410fb.c
++++ b/drivers/video/s3c2410fb.c
+@@ -598,7 +598,7 @@ static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
+
+ dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
+
+- if (blank_mode == FB_BLANK_UNBLANK)
++ if (blank_mode == FB_BLANK_UNBLANK || blank_mode == FB_BLANK_NORMAL)
+ writel(0x0, regs + S3C2410_TPAL);
+ else {
+ dprintk("setting TPAL to output 0x000000\n");
+diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c
+index 272872d..745e1c5 100644
+--- a/fs/jffs2/scan.c
++++ b/fs/jffs2/scan.c
+@@ -646,8 +646,8 @@ scan_more:
+ inbuf_ofs = ofs - buf_ofs;
+ while (inbuf_ofs < scan_end) {
+ if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) {
+- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
+- empty_start, ofs);
++ /* printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
++ empty_start, ofs); */
+ if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start)))
+ return err;
+ goto scan_more;
+@@ -834,8 +834,8 @@ scan_more:
+ case JFFS2_NODETYPE_CLEANMARKER:
+ D1(printk(KERN_DEBUG "CLEANMARKER node found at 0x%08x\n", ofs));
+ if (je32_to_cpu(node->totlen) != c->cleanmarker_size) {
+- printk(KERN_NOTICE "CLEANMARKER node found at 0x%08x has totlen 0x%x != normal 0x%x\n",
+- ofs, je32_to_cpu(node->totlen), c->cleanmarker_size);
++ /* printk(KERN_NOTICE "CLEANMARKER node found at 0x%08x has totlen 0x%x != normal 0x%x\n",
++ ofs, je32_to_cpu(node->totlen), c->cleanmarker_size); */
+ if ((err = jffs2_scan_dirty_space(c, jeb, PAD(sizeof(struct jffs2_unknown_node)))))
+ return err;
+ ofs += PAD(sizeof(struct jffs2_unknown_node));
+diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
+index c6e8d8f..cc52214 100644
+--- a/include/asm-arm/arch-s3c2410/dma.h
++++ b/include/asm-arm/arch-s3c2410/dma.h
+@@ -34,6 +34,8 @@ enum dma_ch {
+ DMACH_XD1,
+ DMACH_SDI,
+ DMACH_SPI0,
++ DMACH_SPI_TX,
++ DMACH_SPI_RX,
+ DMACH_SPI1,
+ DMACH_UART0,
+ DMACH_UART1,
+@@ -41,6 +43,10 @@ enum dma_ch {
+ DMACH_TIMER,
+ DMACH_I2S_IN,
+ DMACH_I2S_OUT,
++ DMACH_I2S_IN_1, /* s3c2450 iis_1 rx */
++ DMACH_I2S_OUT_1, /* s3c2450 iis_1 tx */
++ DMACH_I2S_V40_IN,
++ DMACH_I2S_V40_OUT,
+ DMACH_PCM_IN,
+ DMACH_PCM_OUT,
+ DMACH_MIC_IN,
+@@ -53,16 +59,38 @@ enum dma_ch {
+ DMACH_UART2_SRC2,
+ DMACH_UART3, /* s3c2443 has extra uart */
+ DMACH_UART3_SRC2,
++ DMACH_I2S1_IN, /* S3C6400 */
++ DMACH_I2S1_OUT,
++ DMACH_SPI0_IN,
++ DMACH_SPI0_OUT,
++ DMACH_SPI1_IN,
++ DMACH_SPI1_OUT,
++ DMACH_AC97_PCM_OUT,
++ DMACH_AC97_PCM_IN,
++ DMACH_AC97_MIC_IN,
++ DMACH_ONENAND_IN,
++ DMACH_3D_M2M,
+ DMACH_MAX, /* the end entry */
+ };
+
+ #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
+
+-/* we have 4 dma channels */
+-#ifndef CONFIG_CPU_S3C2443
+-#define S3C2410_DMA_CHANNELS (4)
+-#else
++/* Number of dma channels */
++#if defined (CONFIG_CPU_S3C2443)
+ #define S3C2410_DMA_CHANNELS (6)
++
++#elif defined (CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C2410_DMA_CHANNELS (8)
++
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++/* We have 4 dma controllers - DMA0, DMA1, SDMA0, SDMA1 */
++#define S3C_DMA_CONTROLLERS (4)
++#define S3C_CHANNELS_PER_DMA (8)
++#define S3C_CANDIDATE_CHANNELS_PER_DMA (16)
++#define S3C2410_DMA_CHANNELS (S3C_DMA_CONTROLLERS*S3C_CHANNELS_PER_DMA)
++
++#else
++#define S3C2410_DMA_CHANNELS (4)
+ #endif
+
+ /* types */
+@@ -117,7 +145,10 @@ enum s3c2410_dma_buffresult {
+
+ enum s3c2410_dmasrc {
+ S3C2410_DMASRC_HW, /* source is memory */
+- S3C2410_DMASRC_MEM /* source is hardware */
++ S3C2410_DMASRC_MEM, /* source is hardware */
++ S3C_DMA_MEM2MEM, /* source is memory - READ/WRITE */
++ S3C_DMA_MEM2MEM_P, /* source is hardware - READ/WRITE */
++ S3C_DMA_PER2PER /* source is hardware - READ/WRITE */
+ };
+
+ /* enum s3c2410_chan_op
+@@ -195,6 +226,35 @@ struct s3c2410_dma_map;
+ * full state information for each DMA channel
+ */
+
++/*========================== S3C6400 ===========================================*/
++typedef struct s3c_dma_controller s3c_dma_controller_t;
++struct s3c_dma_controller {
++ /* channel state flags and information */
++ unsigned char number; /* number of this dma channel */
++ unsigned char in_use; /* channel allocated and how many channel are used */
++ unsigned char irq_claimed; /* irq claimed for channel */
++ unsigned char irq_enabled; /* irq enabled for channel */
++ unsigned char xfer_unit; /* size of an transfer */
++
++ /* channel state */
++
++ enum s3c2410_dma_state state;
++ enum s3c2410_dma_loadst load_state;
++ struct s3c2410_dma_client *client;
++
++ /* channel configuration */
++ unsigned long dev_addr;
++ unsigned long load_timeout;
++ unsigned int flags; /* channel flags */
++
++ /* channel's hardware position and configuration */
++ void __iomem *regs; /* channels registers */
++ void __iomem *addr_reg; /* data address register */
++ unsigned int irq; /* channel irq */
++ unsigned long dcon; /* default value of DCON */
++
++};
++
+ struct s3c2410_dma_chan {
+ /* channel state flags and information */
+ unsigned char number; /* number of this dma channel */
+@@ -238,6 +298,13 @@ struct s3c2410_dma_chan {
+
+ /* system device */
+ struct sys_device dev;
++
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++ unsigned int index; /* channel index */
++ unsigned int config_flags; /* channel flags */
++ unsigned int control_flags; /* channel flags */
++ s3c_dma_controller_t *dma_con;
++#endif
+ };
+
+ /* the currently allocated channel information */
+@@ -246,6 +313,18 @@ extern struct s3c2410_dma_chan s3c2410_chans[];
+ /* note, we don't really use dma_device_t at the moment */
+ typedef unsigned long dma_device_t;
+
++
++struct s3c_pl080_sg_list {
++ unsigned long uSrcAddr;
++ unsigned long uDstAddr;
++ unsigned long uNextLLI;
++ unsigned long uCxControl0;
++ unsigned long uCxControl1;
++};
++
++#define s3c_pl080_sg_address(sg) (virt_to_phys(sg))
++
++
+ /* functions --------------------------------------------------------------- */
+
+ /* s3c2410_dma_request
+@@ -264,6 +343,7 @@ extern int s3c2410_dma_request(dmach_t channel,
+
+ extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
+
++
+ /* s3c2410_dma_setflags
+ *
+ * set the channel's flags to a given state
+@@ -272,6 +352,7 @@ extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
+ extern int s3c2410_dma_setflags(dmach_t channel,
+ unsigned int flags);
+
++
+ /* s3c2410_dma_free
+ *
+ * free the dma channel (will also abort any outstanding operations)
+@@ -279,6 +360,7 @@ extern int s3c2410_dma_setflags(dmach_t channel,
+
+ extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
+
++
+ /* s3c2410_dma_enqueue
+ *
+ * place the given buffer onto the queue of operations for the channel.
+@@ -289,6 +371,9 @@ extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
+ extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
+ dma_addr_t data, int size);
+
++extern int s3c2410_dma_enqueue_sg(dmach_t channel, void *id,
++ dma_addr_t data, int size, struct s3c_pl080_sg_list *sg_list);
++
+ /* s3c2410_dma_config
+ *
+ * configure the dma channel
+@@ -312,9 +397,11 @@ extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
+ extern int s3c2410_dma_getposition(dmach_t channel,
+ dma_addr_t *src, dma_addr_t *dest);
+
++
+ extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
+ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
+
++
+ /* DMA Register definitions */
+
+ #define S3C2410_DMA_DISRC (0x00)
+@@ -449,4 +536,189 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
+ #define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
+ #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
+
++
++/*=================================================*/
++/* DMA Register Definitions for S3C6400 */
++
++#define S3C_DMAC_INT_STATUS (0x00)
++#define S3C_DMAC_INT_TCSTATUS (0x04)
++#define S3C_DMAC_INT_TCCLEAR (0x08)
++#define S3C_DMAC_INT_ERRORSTATUS (0x0c)
++#define S3C_DMAC_INT_ERRORCLEAR (0x10)
++#define S3C_DMAC_RAW_INTTCSTATUS (0x14)
++#define S3C_DMAC_RAW_INTERRORSTATUS (0x18)
++#define S3C_DMAC_ENBLD_CHANNELS (0x1c)
++#define S3C_DMAC_SOFTBREQ (0x20)
++#define S3C_DMAC_SOFTSREQ (0x24)
++#define S3C_DMAC_SOFTLBREQ (0x28)
++#define S3C_DMAC_SOFTLSREQ (0x2c)
++#define S3C_DMAC_CONFIGURATION (0x30)
++#define S3C_DMAC_SYNC (0x34)
++
++#define S3C_DMAC_CxSRCADDR (0x00)
++#define S3C_DMAC_CxDESTADDR (0x04)
++#define S3C_DMAC_CxLLI (0x08)
++#define S3C_DMAC_CxCONTROL0 (0x0C)
++#define S3C_DMAC_CxCONTROL1 (0x10)
++#define S3C_DMAC_CxCONFIGURATION (0x14)
++
++#define S3C_DMAC_C0SRCADDR (0x100)
++#define S3C_DMAC_C0DESTADDR (0x104)
++#define S3C_DMAC_C0LLI (0x108)
++#define S3C_DMAC_C0CONTROL0 (0x10C)
++#define S3C_DMAC_C0CONTROL1 (0x110)
++#define S3C_DMAC_C0CONFIGURATION (0x114)
++
++#define S3C_DMAC_C1SRCADDR (0x120)
++#define S3C_DMAC_C1DESTADDR (0x124)
++#define S3C_DMAC_C1LLI (0x128)
++#define S3C_DMAC_C1CONTROL0 (0x12C)
++#define S3C_DMAC_C1CONTROL1 (0x130)
++#define S3C_DMAC_C1CONFIGURATION (0x134)
++
++#define S3C_DMAC_C2SRCADDR (0x140)
++#define S3C_DMAC_C2DESTADDR (0x144)
++#define S3C_DMAC_C2LLI (0x148)
++#define S3C_DMAC_C2CONTROL0 (0x14C)
++#define S3C_DMAC_C2CONTROL1 (0x150)
++#define S3C_DMAC_C2CONFIGURATION (0x154)
++
++#define S3C_DMAC_C3SRCADDR (0x160)
++#define S3C_DMAC_C3DESTADDR (0x164)
++#define S3C_DMAC_C3LLI (0x168)
++#define S3C_DMAC_C3CONTROL0 (0x16C)
++#define S3C_DMAC_C3CONTROL1 (0x170)
++#define S3C_DMAC_C3CONFIGURATION (0x174)
++
++#define S3C_DMAC_C4SRCADDR (0x180)
++#define S3C_DMAC_C4DESTADDR (0x184)
++#define S3C_DMAC_C4LLI (0x188)
++#define S3C_DMAC_C4CONTROL0 (0x18C)
++#define S3C_DMAC_C4CONTROL1 (0x190)
++#define S3C_DMAC_C4CONFIGURATION (0x194)
++
++#define S3C_DMAC_C5SRCADDR (0x1A0)
++#define S3C_DMAC_C5DESTADDR (0x1A4)
++#define S3C_DMAC_C5LLI (0x1A8)
++#define S3C_DMAC_C5CONTROL0 (0x1AC)
++#define S3C_DMAC_C5CONTROL1 (0x1B0)
++#define S3C_DMAC_C5CONFIGURATION (0x1B4)
++
++#define S3C_DMAC_C6SRCADDR (0x1C0)
++#define S3C_DMAC_C6DESTADDR (0x1C4)
++#define S3C_DMAC_C6LLI (0x1C8)
++#define S3C_DMAC_C6CONTROL0 (0x1CC)
++#define S3C_DMAC_C6CONTROL1 (0x1D0)
++#define S3C_DMAC_C6CONFIGURATION (0x1D4)
++
++#define S3C_DMAC_C7SRCADDR (0x1E0)
++#define S3C_DMAC_C7DESTADDR (0x1E4)
++#define S3C_DMAC_C7LLI (0x1E8)
++#define S3C_DMAC_C7CONTROL0 (0x1EC)
++#define S3C_DMAC_C7CONTROL1 (0x1F0)
++#define S3C_DMAC_C7CONFIGURATION (0x1F4)
++
++/*DMACConfiguration(0x30)*/
++#define S3C_DMA_CONTROLLER_ENABLE (1<<0)
++
++/*DMACCxControl0 : Channel control register 0*/
++#define S3C_DMACONTROL_TC_INT_ENABLE (1<<31)
++#define S3C_DMACONTROL_DEST_NO_INC (0<<27)
++#define S3C_DMACONTROL_DEST_INC (1<<27)
++#define S3C_DMACONTROL_SRC_NO_INC (0<<26)
++#define S3C_DMACONTROL_SRC_INC (1<<26)
++#define S3C_DMACONTROL_DEST_AXI_SPINE (0<<25)
++#define S3C_DMACONTROL_DEST_AXI_PERI (1<<25)
++#define S3C_DMACONTROL_SRC_AXI_SPINE (0<<24)
++#define S3C_DMACONTROL_SRC_AXI_PERI (1<<24)
++#define S3C_DMACONTROL_DEST_WIDTH_BYTE (0<<21)
++#define S3C_DMACONTROL_DEST_WIDTH_HWORD (1<<21)
++#define S3C_DMACONTROL_DEST_WIDTH_WORD (2<<21)
++#define S3C_DMACONTROL_SRC_WIDTH_BYTE (0<<18)
++#define S3C_DMACONTROL_SRC_WIDTH_HWORD (1<<18)
++#define S3C_DMACONTROL_SRC_WIDTH_WORD (2<<18)
++
++#define S3C_DMACONTROL_DBSIZE_1 (0<<15)
++#define S3C_DMACONTROL_DBSIZE_4 (1<<15)
++#define S3C_DMACONTROL_DBSIZE_8 (2<<15)
++#define S3C_DMACONTROL_DBSIZE_16 (3<<15)
++#define S3C_DMACONTROL_DBSIZE_32 (4<<15)
++#define S3C_DMACONTROL_DBSIZE_64 (5<<15)
++#define S3C_DMACONTROL_DBSIZE_128 (6<<15)
++#define S3C_DMACONTROL_DBSIZE_256 (7<<15)
++
++#define S3C_DMACONTROL_SBSIZE_1 (0<<12)
++#define S3C_DMACONTROL_SBSIZE_4 (1<<12)
++#define S3C_DMACONTROL_SBSIZE_8 (2<<12)
++#define S3C_DMACONTROL_SBSIZE_16 (3<<12)
++#define S3C_DMACONTROL_SBSIZE_32 (4<<12)
++#define S3C_DMACONTROL_SBSIZE_64 (5<<12)
++#define S3C_DMACONTROL_SBSIZE_128 (6<<12)
++#define S3C_DMACONTROL_SBSIZE_256 (7<<12)
++
++
++/*Channel configuration register, DMACCxConfiguration*/
++#define S3C_DMACONFIG_HALT (1<<18) /*The contents of the channels FIFO are drained*/
++#define S3C_DMACONFIG_ACTIVE (1<<17) /*Check channel fifo has data or not*/
++#define S3C_DMACONFIG_LOCK (1<<16)
++#define S3C_DMACONFIG_TCMASK (1<<15) /*Terminal count interrupt mask*/
++#define S3C_DMACONFIG_ERRORMASK (1<<14) /*Interrup error mask*/
++#define S3C_DMACONFIG_FLOWCTRL_MEM2MEM (0<<11)
++#define S3C_DMACONFIG_FLOWCTRL_MEM2PER (1<<11)
++#define S3C_DMACONFIG_FLOWCTRL_PER2MEM (2<<11)
++#define S3C_DMACONFIG_FLOWCTRL_PER2PER (3<<11)
++#define S3C_DMACONFIG_ONENANDMODEDST (1<<10) /* Reserved: OneNandModeDst */
++#define S3C_DMACONFIG_DESTPERIPHERAL(x) ((x)<<6)
++#define S3C_DMACONFIG_ONENANDMODESRC (1<<5) /* Reserved: OneNandModeSrc */
++#define S3C_DMACONFIG_SRCPERIPHERAL(x) ((x)<<1)
++#define S3C_DMACONFIG_CHANNEL_ENABLE (1<<0)
++
++/* DMAC0 DMA request sources */
++#define S3C_DMA0_UART0CH0 0
++#define S3C_DMA0_UART0CH1 1
++#define S3C_DMA0_UART1CH0 2
++#define S3C_DMA0_UART1CH1 3
++#define S3C_DMA0_ONENAND_RX 3 /* Memory to Memory DMA */
++#define S3C_DMA0_UART2CH0 4
++#define S3C_DMA0_UART2CH1 5
++#define S3C_DMA0_UART3CH0 6
++#define S3C_DMA0_UART3CH1 7
++#define S3C_DMA0_PCM0_TX 8
++#define S3C_DMA0_PCM0_RX 9
++#define S3C_DMA0_I2S0_TX 10
++#define S3C_DMA0_I2S0_RX 11
++#define S3C_DMA0_SPI0_TX 12
++#define S3C_DMA0_SPI0_RX 13
++#define S3C_DMA0_HSI_TX 14
++#define S3C_DMA0_HSI_RX 15
++
++/* DMAC1 DMA request sources */
++#define S3C_DMA1_PCM1_TX 0
++#define S3C_DMA1_PCM1_RX 1
++#define S3C_DMA1_I2S1_TX 2
++#define S3C_DMA1_I2S1_RX 3
++#define S3C_DMA1_SPI1_TX 4
++#define S3C_DMA1_SPI1_RX 5
++#define S3C_DMA1_AC97_PCMOUT 6
++#define S3C_DMA1_AC97_PCMIN 7
++#define S3C_DMA1_AC97_MICIN 8
++#define S3C_DMA1_PWM 9
++#define S3C_DMA1_IRDA 10
++#define S3C_DMA1_EXT 11
++
++#define S3C_DMA1 16
++
++#define S3C_DEST_SHIFT 6
++#define S3C_SRC_SHIFT 1
++
++
++//#define S3C_DMAC_CSRCADDR(ch) S3C_DMAC_C##ch##SRCADDR
++#define S3C_DMAC_CSRCADDR(ch) (S3C_DMAC_C0SRCADDR+ch*0x20)
++#define S3C_DMAC_CDESTADDR(ch) (S3C_DMAC_C0DESTADDR+ch*0x20)
++#define S3C_DMAC_CLLI(ch) (S3C_DMAC_C0LLI+ch*0x20)
++#define S3C_DMAC_CCONTROL0(ch) (S3C_DMAC_C0CONTROL0+ch*0x20)
++#define S3C_DMAC_CCONTROL1(ch) (S3C_DMAC_C0CONTROL1+ch*0x20)
++#define S3C_DMAC_CCONFIGURATION(ch) (S3C_DMAC_C0CONFIGURATION+ch*0x20)
++
+ #endif /* __ASM_ARCH_DMA_H */
++
+diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
+index bbec0a8..a703348 100644
+--- a/include/asm-arm/arch-s3c2410/entry-macro.S
++++ b/include/asm-arm/arch-s3c2410/entry-macro.S
+@@ -22,6 +22,43 @@
+ #include <asm/hardware.h>
+ #include <asm/irq.h>
+
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++
++ .macro get_irqnr_preamble, base, tmp
++ .endm
++
++ .macro arch_ret_to_user, tmp1, tmp2
++ .endm
++
++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
++ mov \tmp, #0
++ ldr \base, =S3C24XX_VA_IRQ
++ ldr \irqstat, [\base, #0] @ get masked status
++ cmp \irqstat, \tmp
++ addeq \base, \base, #0x100000
++ ldreq \irqstat, [\base, #0] @ get masked status
++ cmpeq \irqstat, #0
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++ addeq \base, \base, #0x100000
++ ldreq \irqstat, [\base, #0] @ get masked status
++ cmpeq \irqstat, #0
++#endif
++
++ ldr \irqnr, [\base, #0xF00] @ read for VICADDR[01]
++ @ exit irq routine
++ .endm
++
++ /* currently don't need an disable_fiq macro */
++ .macro disable_fiq
++ .endm
++
++ /* we don't have an irq priority table */
++ .macro irq_prio_table
++ .endm
++
++#else
++
+ .macro get_irqnr_preamble, base, tmp
+ .endm
+
+@@ -76,3 +113,5 @@
+
+ .macro disable_fiq
+ .endm
++
++#endif
+diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h
+index 7583895..c1b9a09 100644
+--- a/include/asm-arm/arch-s3c2410/gpio.h
++++ b/include/asm-arm/arch-s3c2410/gpio.h
+@@ -24,27 +24,32 @@
+ #ifndef __ASM_ARCH_S3C2410_GPIO_H
+ #define __ASM_ARCH_S3C2410_GPIO_H
+
++#include <linux/kernel.h>
++
+ #include <asm/irq.h>
+ #include <asm/hardware.h>
++
++#if defined(CONFIG_PLAT_S3C24XX)
++
+ #include <asm/arch/regs-gpio.h>
+
+-static inline int gpio_request(unsigned gpio, const char *label)
++static inline int gpio_request(unsigned int gpio, const char *label)
+ {
+ return 0;
+ }
+
+-static inline void gpio_free(unsigned gpio)
++static inline void gpio_free(unsigned int gpio)
+ {
+ return;
+ }
+
+-static inline int gpio_direction_input(unsigned gpio)
++static inline int gpio_direction_input(unsigned int gpio)
+ {
+ s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_INPUT);
+ return 0;
+ }
+
+-static inline int gpio_direction_output(unsigned gpio, int value)
++static inline int gpio_direction_output(unsigned int gpio, int value)
+ {
+ s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_OUTPUT);
+ /* REVISIT can we write the value first, to avoid glitching? */
+@@ -65,4 +70,111 @@ static inline int gpio_direction_output(unsigned gpio, int value)
+
+ /* FIXME implement irq_to_gpio() */
+
+-#endif
++#elif defined(CONFIG_PLAT_S3C64XX)
++
++#include <asm/arch/regs-gpio.h>
++
++static inline int gpio_request(unsigned int gpio, const char *label)
++{
++ return 0;
++}
++
++static inline void gpio_free(unsigned int gpio)
++{
++ return;
++}
++
++static inline int gpio_direction_input(unsigned int gpio)
++{
++ s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
++
++ return 0;
++}
++
++static inline int gpio_direction_output(unsigned int gpio, int value)
++{
++ s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
++
++ /* REVISIT can we write the value first, to avoid glitching? */
++ s3c_gpio_setpin(gpio, value);
++
++ return 0;
++}
++
++static inline void gpio_set_pin(unsigned int gpio, int function)
++{
++ s3c_gpio_cfgpin(gpio, function);
++}
++
++static inline int gpio_get_pin(unsigned int gpio)
++{
++ return s3c_gpio_getcfg(gpio);
++}
++
++static inline void gpio_pullup(unsigned int gpio, unsigned int to)
++{
++ s3c_gpio_pullup(gpio, to);
++}
++
++#define gpio_get_value(gpio) s3c_gpio_getpin(gpio)
++#define gpio_set_value(gpio, value) s3c_gpio_setpin(gpio, value)
++
++#include <asm-generic/gpio.h> /* cansleep wrappers */
++
++#define gpio_to_irq(gpio) s3c_gpio_getirq(gpio)
++
++/* FIXME implement irq_to_gpio() */
++
++#elif defined(CONFIG_PLAT_S5PC1XX)
++
++#include <asm/plat-s5p/regs-gpio.h>
++
++static inline int gpio_request(unsigned int gpio, const char *label)
++{
++ return 0;
++}
++
++static inline void gpio_free(unsigned int gpio)
++{
++ return;
++}
++
++static inline int gpio_direction_input(unsigned int gpio)
++{
++ s5p_gpio_cfgpin(gpio, S5P_GPIO_INPUT);
++
++ return 0;
++}
++
++static inline int gpio_direction_output(unsigned int gpio, int value)
++{
++ s5p_gpio_cfgpin(gpio, S5P_GPIO_OUTPUT);
++
++ /* REVISIT can we write the value first, to avoid glitching? */
++ s5p_gpio_setpin(gpio, value);
++
++ return 0;
++}
++
++static inline void gpio_set_pin(unsigned int gpio, int function)
++{
++ s5p_gpio_cfgpin(gpio, function);
++}
++
++static inline void gpio_pullup(unsigned int gpio, unsigned int to)
++{
++ s5p_gpio_pullup(gpio, to);
++}
++
++#define gpio_get_value(gpio) s5p_gpio_getpin(gpio)
++#define gpio_set_value(gpio, value) s5p_gpio_setpin(gpio, value)
++
++#include <asm-generic/gpio.h> /* cansleep wrappers */
++
++#define gpio_to_irq(gpio) s5p_gpio_getirq(gpio)
++
++/* FIXME implement irq_to_gpio() */
++
++#endif /* end of CONFIG_PLAT_XXX */
++
++#endif /* end of __ASM_ARCH_S3C2410_GPIO_H */
+diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
+index 6dadf58..4c305ba 100644
+--- a/include/asm-arm/arch-s3c2410/hardware.h
++++ b/include/asm-arm/arch-s3c2410/hardware.h
+@@ -13,6 +13,168 @@
+ #ifndef __ASM_ARCH_HARDWARE_H
+ #define __ASM_ARCH_HARDWARE_H
+
++#if defined (CONFIG_PLAT_S5PC1XX)
++
++#ifndef __ASSEMBLY__
++
++/* external functions for GPIO support
++ *
++ * These allow various different clients to access the same GPIO
++ * registers without conflicting. If your driver only owns the entire
++ * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
++*/
++
++/* s3c_gpio_cfgpin
++ *
++ * set the configuration of the given pin to the value passed.
++ *
++ * eg:
++ * s3c_gpio_cfgpin(S3C2413_GPA0, S3C2413_GPA0_ADDR0);
++ * s3c_gpio_cfgpin(S3C2413_GPE8, S3C2413_GPE8_SDDAT1);
++*/
++
++extern void s5p_gpio_cfgpin(unsigned int pin, unsigned int function);
++extern unsigned int s5p_gpio_getcfg(unsigned int pin);
++
++/* s3c_gpio_getirq
++ *
++ * turn the given pin number into the corresponding IRQ number
++ *
++ * returns:
++ * < 0 = no interrupt for this pin
++ * >=0 = interrupt number for the pin
++*/
++
++//extern int s3c_gpio_getirq(unsigned int pin);
++
++/* s3c_gpio_irqfilter
++ *
++ * set the irq filtering on the given pin
++ *
++ * on = 0 => disable filtering
++ * 1 => enable filtering
++ *
++ * config = S3C2413_EINTFLT_PCLK or S3C2413_EINTFLT_EXTCLK orred with
++ * width of filter (0 through 63)
++ *
++ *
++*/
++
++//extern int s3c_gpio_irqfilter(unsigned int pin, unsigned int on,
++// unsigned int config);
++
++/* s3c_gpio_pullup
++ *
++ * configure the pull-up control on the given pin
++ *
++ * to = 1 => disable the pull-up
++ * 0 => enable the pull-up
++ *
++ * eg;
++ *
++ * s3c_gpio_pullup(S3C_GPB0, 0);
++ * s3c_gpio_pullup(S3C_GPE8, 0);
++*/
++
++extern void s5p_gpio_pullup(unsigned int pin, unsigned int to);
++extern void s5p_gpio_setpin(unsigned int pin, unsigned int to);
++extern unsigned int s5p_gpio_getpin(unsigned int pin);
++
++//extern unsigned int s3c_modify_misccr(unsigned int clr, unsigned int chg);
++
++#endif /* __ASSEMBLY__ */
++
++#include <asm/sizes.h>
++#include <asm/arch/map.h>
++
++/* machine specific hardware definitions should go after this */
++
++/* currently here until moved into config (todo) */
++#define CONFIG_NO_MULTIWORD_IO
++
++#endif /* PLAT_S5PC1XX */
++
++#if defined (CONFIG_PLAT_S3C64XX)
++
++#ifndef __ASSEMBLY__
++
++/* external functions for GPIO support
++ *
++ * These allow various different clients to access the same GPIO
++ * registers without conflicting. If your driver only owns the entire
++ * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
++*/
++
++/* s3c_gpio_cfgpin
++ *
++ * set the configuration of the given pin to the value passed.
++ *
++ * eg:
++ * s3c_gpio_cfgpin(S3C2413_GPA0, S3C2413_GPA0_ADDR0);
++ * s3c_gpio_cfgpin(S3C2413_GPE8, S3C2413_GPE8_SDDAT1);
++*/
++
++extern void s3c_gpio_cfgpin(unsigned int pin, unsigned int function);
++extern unsigned int s3c_gpio_getcfg(unsigned int pin);
++
++/* s3c_gpio_getirq
++ *
++ * turn the given pin number into the corresponding IRQ number
++ *
++ * returns:
++ * < 0 = no interrupt for this pin
++ * >=0 = interrupt number for the pin
++*/
++
++//extern int s3c_gpio_getirq(unsigned int pin);
++
++/* s3c_gpio_irqfilter
++ *
++ * set the irq filtering on the given pin
++ *
++ * on = 0 => disable filtering
++ * 1 => enable filtering
++ *
++ * config = S3C2413_EINTFLT_PCLK or S3C2413_EINTFLT_EXTCLK orred with
++ * width of filter (0 through 63)
++ *
++ *
++*/
++
++//extern int s3c_gpio_irqfilter(unsigned int pin, unsigned int on,
++// unsigned int config);
++
++/* s3c_gpio_pullup
++ *
++ * configure the pull-up control on the given pin
++ *
++ * to = 1 => disable the pull-up
++ * 0 => enable the pull-up
++ *
++ * eg;
++ *
++ * s3c_gpio_pullup(S3C_GPB0, 0);
++ * s3c_gpio_pullup(S3C_GPE8, 0);
++*/
++
++extern void s3c_gpio_pullup(unsigned int pin, unsigned int to);
++extern void s3c_gpio_setpin(unsigned int pin, unsigned int to);
++extern unsigned int s3c_gpio_getpin(unsigned int pin);
++
++//extern unsigned int s3c_modify_misccr(unsigned int clr, unsigned int chg);
++
++#endif /* __ASSEMBLY__ */
++
++#include <asm/sizes.h>
++#include <asm/arch/map.h>
++
++/* machine specific hardware definitions should go after this */
++
++/* currently here until moved into config (todo) */
++#define CONFIG_NO_MULTIWORD_IO
++
++#endif /* PLAT_S3C64XX */
++
+ #ifndef __ASM_HARDWARE_H
+ #error "Do not include this directly, instead #include <asm/hardware.h>"
+ #endif
+diff --git a/include/asm-arm/arch-s3c2410/hsmmc.h b/include/asm-arm/arch-s3c2410/hsmmc.h
+new file mode 100644
+index 0000000..5700206
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/hsmmc.h
+@@ -0,0 +1,51 @@
++#ifndef __ASM_S3C_HSMMC_H
++#define __ASM_S3C_HSMMC_H
++
++#ifndef __ASSEMBLY__
++
++#include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++
++#if defined(CONFIG_CPU_S3C6410)
++#define NUM_OF_HSMMC_CLKSOURCES 1
++#else
++#define NUM_OF_HSMMC_CLKSOURCES 3
++#endif
++
++#define SPEED_NORMAL 0
++#define SPEED_HIGH 1
++
++struct s3c_hsmmc_fd_cfg {
++ ulong ctrl2;
++ ulong ctrl3[2]; /* 0: low speed, 1: high speed */
++ ulong ctrl4;
++};
++
++struct s3c_hsmmc_clk_cfg {
++ char *name;
++ u32 src;
++};
++
++struct s3c_hsmmc_cfg {
++ u32 hwport; /* hardware port number */
++ u32 enabled; /* if port is used, set 1 */
++ u32 host_caps; /* host capabilities */
++ u32 bus_width; /* bus width */
++
++ void *base; /* base address of host */
++
++ u8 highspeed; /* ENHIGHSPD bit configuration */
++
++ /* feedback delay control configuration (0: mmc, 1: sd) */
++ struct s3c_hsmmc_fd_cfg fd_ctrl[2];
++
++ /* clock source control */
++ struct s3c_hsmmc_clk_cfg clocks[NUM_OF_HSMMC_CLKSOURCES];
++};
++
++extern void hsmmc_set_gpio(uint channel, uint width);
++
++#endif /* __ASSEMBLY__ */
++
++#endif /* __ASM_S3C_HSMMC_H */
++
+diff --git a/include/asm-arm/arch-s3c2410/irqs-s5pc100.h b/include/asm-arm/arch-s3c2410/irqs-s5pc100.h
+new file mode 100644
+index 0000000..b769025
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/irqs-s5pc100.h
+@@ -0,0 +1,132 @@
++/* linux/include/asm-arm/arch-s3c2410/irqs-x5pc100.h
++ *
++ * Copyright (c) 2008-2009 Samsung Electronics
++ * Ryu Euiyoul <real.ryu@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++
++#ifndef __ASM_ARCH_IRQS_H
++#define __ASM_ARCH_IRQS_H __FILE__
++
++#ifndef __ASM_ARM_IRQ_H
++#error "Do not include this directly, instead #include <asm/irq.h>"
++#endif
++
++#define S5PC100_CPUIRQ_OFFSET (0)
++
++#define S5PC100_IRQ(x) ((x) + S5PC100_CPUIRQ_OFFSET)
++
++/*
++ * VIC0: system, DMA, timer
++ */
++#define IRQ_EINT0 S5PC100_IRQ(0)
++#define IRQ_EINT1 S5PC100_IRQ(1)
++#define IRQ_EINT2 S5PC100_IRQ(2)
++#define IRQ_EINT3 S5PC100_IRQ(3)
++#define IRQ_EINT4 S5PC100_IRQ(4)
++#define IRQ_EINT5 S5PC100_IRQ(5)
++#define IRQ_EINT6 S5PC100_IRQ(6)
++#define IRQ_EINT7 S5PC100_IRQ(7)
++#define IRQ_EINT8 S5PC100_IRQ(8)
++#define IRQ_EINT9 S5PC100_IRQ(9)
++#define IRQ_EINT10 S5PC100_IRQ(10)
++#define IRQ_EINT11 S5PC100_IRQ(11)
++#define IRQ_EINT12 S5PC100_IRQ(12)
++#define IRQ_EINT13 S5PC100_IRQ(13)
++#define IRQ_EINT14 S5PC100_IRQ(14)
++#define IRQ_EINT15 S5PC100_IRQ(15)
++#define IRQ_EINT16_31 S5PC100_IRQ(16)
++#define IRQ_BATF S5PC100_IRQ(17)
++#define IRQ_MDMA S5PC100_IRQ(18)
++#define IRQ_PDMA0 S5PC100_IRQ(19)
++#define IRQ_PDMA1 S5PC100_IRQ(20)
++#define IRQ_TIMER0 S5PC100_IRQ(21)
++#define IRQ_TIMER1 S5PC100_IRQ(22)
++#define IRQ_TIMER2 S5PC100_IRQ(23)
++#define IRQ_TIMER3 S5PC100_IRQ(24)
++#define IRQ_TIMER4 S5PC100_IRQ(25)
++#define IRQ_SYSTIMER S5PC100_IRQ(26)
++#define IRQ_WDT S5PC100_IRQ(27)
++#define IRQ_RTC_ALARM S5PC100_IRQ(28)
++#define IRQ_RTC_TIC S5PC100_IRQ(29)
++#define IRQ_GPIOINT S5PC100_IRQ(30)
++
++/*
++ * VIC1: ARM, power, memory, connectivity
++ */
++#define IRQ_CORTEX0 S5PC100_IRQ(32)
++#define IRQ_CORTEX1 S5PC100_IRQ(33)
++#define IRQ_CORTEX2 S5PC100_IRQ(34)
++#define IRQ_CORTEX3 S5PC100_IRQ(35)
++#define IRQ_CORTEX4 S5PC100_IRQ(36)
++#define IRQ_IEMAPC S5PC100_IRQ(37)
++#define IRQ_IEMIEC S5PC100_IRQ(38)
++#define IRQ_ONENAND S5PC100_IRQ(39)
++#define IRQ_NFC S5PC100_IRQ(40)
++#define IRQ_CFC S5PC100_IRQ(41)
++#define IRQ_UART0 S5PC100_IRQ(42)
++#define IRQ_UART1 S5PC100_IRQ(43)
++#define IRQ_UART2 S5PC100_IRQ(44)
++#define IRQ_UART3 S5PC100_IRQ(45)
++#define IRQ_IIC S5PC100_IRQ(46)
++#define IRQ_SPI0 S5PC100_IRQ(47)
++#define IRQ_SPI1 S5PC100_IRQ(48)
++#define IRQ_SPI2 S5PC100_IRQ(49)
++#define IRQ_IRDA S5PC100_IRQ(50)
++#define IRQ_CAN0 S5PC100_IRQ(51)
++#define IRQ_CAN1 S5PC100_IRQ(52)
++#define IRQ_HSIRX S5PC100_IRQ(53)
++#define IRQ_HSITX S5PC100_IRQ(54)
++#define IRQ_UHOST S5PC100_IRQ(55)
++#define IRQ_OTG S5PC100_IRQ(56)
++#define IRQ_MSM S5PC100_IRQ(57)
++#define IRQ_HSMMC0 S5PC100_IRQ(58)
++#define IRQ_HSMMC1 S5PC100_IRQ(59)
++#define IRQ_HSMMC2 S5PC100_IRQ(60)
++#define IRQ_MIPICSI S5PC100_IRQ(61)
++#define IRQ_MIPIDSI S5PC100_IRQ(62)
++
++/*
++ * VIC2: multimedia, audio, security
++ */
++#define IRQ_LCD0 S5PC100_IRQ(64)
++#define IRQ_LCD1 S5PC100_IRQ(65)
++#define IRQ_LCD2 S5PC100_IRQ(66)
++#define IRQ_LCD3 S5PC100_IRQ(67)
++#define IRQ_ROTATOR S5PC100_IRQ(68)
++#define IRQ_FIMC0 S5PC100_IRQ(69)
++#define IRQ_FIMC1 S5PC100_IRQ(70)
++#define IRQ_FIMC2 S5PC100_IRQ(71)
++#define IRQ_JPEG S5PC100_IRQ(72)
++#define IRQ_2D S5PC100_IRQ(73)
++#define IRQ_3D S5PC100_IRQ(74)
++#define IRQ_MIXER S5PC100_IRQ(75)
++#define IRQ_HDMI S5PC100_IRQ(76)
++#define IRQ_HDMI_I2C S5PC100_IRQ(77)
++#define IRQ_MFC S5PC100_IRQ(78)
++#define IRQ_TVENC S5PC100_IRQ(79)
++#define IRQ_I2S0 S5PC100_IRQ(80)
++#define IRQ_I2S1 S5PC100_IRQ(81)
++#define IRQ_I2S2 S5PC100_IRQ(82)
++#define IRQ_AC97 S5PC100_IRQ(83)
++#define IRQ_PCM0 S5PC100_IRQ(84)
++#define IRQ_PCM1 S5PC100_IRQ(85)
++#define IRQ_SPDIF S5PC100_IRQ(86)
++#define IRQ_ADC S5PC100_IRQ(87)
++#define IRQ_PENDN S5PC100_IRQ(88)
++#define IRQ_TC IRQ_PENDN
++#define IRQ_KEYPAD S5PC100_IRQ(89)
++#define IRQ_CG S5PC100_IRQ(90)
++#define IRQ_SEC S5PC100_IRQ(91)
++#define IRQ_SECRX S5PC100_IRQ(92)
++#define IRQ_SECTX S5PC100_IRQ(93)
++#define IRQ_SDMIRQ S5PC100_IRQ(94)
++#define IRQ_SDMFIQ S5PC100_IRQ(95)
++
++#define NR_IRQS (IRQ_SDMFIQ+1)
++
++#endif /* __ASM_ARCH_IRQ_H */
+diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
+index 996f654..8df27fb 100644
+--- a/include/asm-arm/arch-s3c2410/irqs.h
++++ b/include/asm-arm/arch-s3c2410/irqs.h
+@@ -16,6 +16,8 @@
+ #error "Do not include this directly, instead #include <asm/irq.h>"
+ #endif
+
++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410)
++
+ /* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+@@ -132,6 +134,7 @@
+ #define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
+ #define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
+ #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
++#define IRQ_S3C2443_SDI1 S3C2410_IRQ(20) /* IRQ_SDI */
+ #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
+
+ #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
+@@ -146,6 +149,11 @@
+ #define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
+ #define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
+
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define IRQ_S3C2443_DMA6 S3C2410_IRQSUB(29)
++#define IRQ_S3C2443_DMA7 S3C2410_IRQSUB(30)
++#endif
++
+ /* UART3 */
+ #define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
+ #define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
+@@ -154,10 +162,152 @@
+ #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
+ #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
+
+-#ifdef CONFIG_CPU_S3C2443
++#if defined (CONFIG_CPU_S3C2443) || defined (CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define IRQ_CFCON S3C2410_IRQ(19)
++#define IRQ_SDI_1 S3C2410_IRQ(20)
++#define IRQ_SDI_0 S3C2410_IRQ(21)
++
++#if defined(CONFIG_CPU_S3C2450) || defined (CONFIG_CPU_S3C2416)
++#define IRQ_S3C2450_2D S3C2410_IRQSUB(31)
++#define IRQ_S3C2450_IIC1 S3C2410_IRQSUB(32)
++#define IRQ_S3C2450_GIB S3C2410_IRQSUB(33)
++#define IRQ_S3C2450_Reserved S3C2410_IRQSUB(34)
++#define IRQ_S3C2450_PCM0 S3C2410_IRQSUB(35)
++#define IRQ_S3C2450_PCM1 S3C2410_IRQSUB(36)
++#define IRQ_S3C2450_I2S0 S3C2410_IRQSUB(37)
++#define IRQ_S3C2450_I2S1 S3C2410_IRQSUB(38)
++
++#define NR_IRQS (IRQ_S3C2450_I2S1+1)
++#else
+ #define NR_IRQS (IRQ_S3C2443_AC97+1)
++#endif
++
+ #else
+ #define NR_IRQS (IRQ_S3C2440_AC97+1)
+ #endif
+
++
++#else /* CONFIG_CPU_S3C6400 || CONFIG_CPU_S3C6410 */
++
++#define S3C6400_CPUIRQ_OFFSET (0)
++
++#define S3C6400_IRQ(x) ((x) + S3C6400_CPUIRQ_OFFSET)
++
++/******** TZIC0/VIC0 *****************/
++/* main cpu interrupts */
++#define IRQ_EINT0_3 S3C6400_IRQ(0)
++#define IRQ_EINT4_11 S3C6400_IRQ(1)
++#define IRQ_RTC_TIC S3C6400_IRQ(2)
++#define IRQ_CAMIF_C S3C6400_IRQ(3)
++#define IRQ_CAMIF_P S3C6400_IRQ(4)
++#define IRQ_IIC1 S3C6400_IRQ(5)
++
++#ifdef CONFIG_CPU_S3C6410
++#define IRQ_IIS S3C6400_IRQ(6)
++#else
++#define IRQ_CAMIF_MP S3C6400_IRQ(6)
++#endif
++
++#define IRQ_CAMIF_WE_C S3C6400_IRQ(7)
++#if defined(CONFIG_CPU_S3C6410)
++#define IRQ_3D S3C6400_IRQ(8)
++#else
++#define IRQ_CAMIF_WE_P S3C6400_IRQ(8)
++#endif
++
++#define IRQ_POST0 S3C6400_IRQ(9)
++#define IRQ_ROTATOR S3C6400_IRQ(10)
++#define IRQ_2D S3C6400_IRQ(11)
++#define IRQ_TVENC S3C6400_IRQ(12)
++#define IRQ_SCALER S3C6400_IRQ(13)
++#define IRQ_BATF S3C6400_IRQ(14)
++#define IRQ_JPEG S3C6400_IRQ(15)
++#define IRQ_MFC S3C6400_IRQ(16)
++#define IRQ_SDMA0 S3C6400_IRQ(17)
++#define IRQ_SDMA1 S3C6400_IRQ(18)
++#define IRQ_ARM_DMAERR S3C6400_IRQ(19)
++#define IRQ_ARM_DMA S3C6400_IRQ(20)
++#define IRQ_ARM_DMAS S3C6400_IRQ(21)
++#define IRQ_KEYPAD S3C6400_IRQ(22)
++#define IRQ_TIMER0 S3C6400_IRQ(23)
++#define IRQ_TIMER1 S3C6400_IRQ(24)
++#define IRQ_TIMER2 S3C6400_IRQ(25)
++#define IRQ_WDT S3C6400_IRQ(26)
++#define IRQ_TIMER3 S3C6400_IRQ(27)
++#define IRQ_TIMER4 S3C6400_IRQ(28)
++#define IRQ_LCD_FIFO S3C6400_IRQ(29)
++#define IRQ_LCD_VSYNC S3C6400_IRQ(30)
++#define IRQ_LCD_SYSTEM S3C6400_IRQ(31)
++
++/******** TZIC1/VIC1 *****************/
++#define IRQ_EINT12_19 S3C6400_IRQ(32)
++#define IRQ_EINT20_27 S3C6400_IRQ(33)
++#define IRQ_PCM0 S3C6400_IRQ(34)
++#define IRQ_PCM1 S3C6400_IRQ(35)
++#define IRQ_AC97 S3C6400_IRQ(36)
++#define IRQ_UART0 S3C6400_IRQ(37)
++#define IRQ_UART1 S3C6400_IRQ(38)
++#define IRQ_UART2 S3C6400_IRQ(39)
++#define IRQ_UART3 S3C6400_IRQ(40)
++#define IRQ_DMA0 S3C6400_IRQ(41)
++#define IRQ_DMA1 S3C6400_IRQ(42)
++#define IRQ_ONENAND0 S3C6400_IRQ(43)
++#define IRQ_ONENAND1 S3C6400_IRQ(44)
++#define IRQ_NFC S3C6400_IRQ(45)
++#define IRQ_CFCON S3C6400_IRQ(46)
++#define IRQ_UHOST S3C6400_IRQ(47)
++#define IRQ_SPI0 S3C6400_IRQ(48)
++#define IRQ_SPI1 S3C6400_IRQ(49)
++#define IRQ_IIC0 S3C6400_IRQ(50)
++#define IRQ_HSItx S3C6400_IRQ(51)
++#define IRQ_HSIrx S3C6400_IRQ(52)
++#define IRQ_RESERVED S3C6400_IRQ(53)
++#define IRQ_MSM S3C6400_IRQ(54)
++#define IRQ_HOSTIF S3C6400_IRQ(55)
++#define IRQ_HSMMC0 S3C6400_IRQ(56)
++#define IRQ_HSMMC1 S3C6400_IRQ(57)
++#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
++#define IRQ_OTG S3C6400_IRQ(58)
++#define IRQ_IRDA S3C6400_IRQ(59)
++#define IRQ_RTC_ALARM S3C6400_IRQ(60)
++#define IRQ_SEC S3C6400_IRQ(61)
++#define IRQ_PENDN S3C6400_IRQ(62)
++#define IRQ_TC IRQ_PENDN
++#define IRQ_ADC S3C6400_IRQ(63)
++
++/* EINT 0 ~27 */
++#define IRQ_EINT0 S3C6400_IRQ(64)
++#define IRQ_EINT1 S3C6400_IRQ(65)
++#define IRQ_EINT2 S3C6400_IRQ(66)
++#define IRQ_EINT3 S3C6400_IRQ(67)
++#define IRQ_EINT4 S3C6400_IRQ(68)
++#define IRQ_EINT5 S3C6400_IRQ(69)
++#define IRQ_EINT6 S3C6400_IRQ(70)
++#define IRQ_EINT7 S3C6400_IRQ(71)
++#define IRQ_EINT8 S3C6400_IRQ(72)
++#define IRQ_EINT9 S3C6400_IRQ(73)
++#define IRQ_EINT10 S3C6400_IRQ(74)
++#define IRQ_EINT11 S3C6400_IRQ(75)
++#define IRQ_EINT12 S3C6400_IRQ(76)
++#define IRQ_EINT13 S3C6400_IRQ(77)
++#define IRQ_EINT14 S3C6400_IRQ(78)
++#define IRQ_EINT15 S3C6400_IRQ(79)
++#define IRQ_EINT16 S3C6400_IRQ(80)
++#define IRQ_EINT17 S3C6400_IRQ(81)
++#define IRQ_EINT18 S3C6400_IRQ(82)
++#define IRQ_EINT19 S3C6400_IRQ(83)
++#define IRQ_EINT20 S3C6400_IRQ(84)
++#define IRQ_EINT21 S3C6400_IRQ(85)
++#define IRQ_EINT22 S3C6400_IRQ(86)
++#define IRQ_EINT23 S3C6400_IRQ(87)
++#define IRQ_EINT24 S3C6400_IRQ(88)
++#define IRQ_EINT25 S3C6400_IRQ(89)
++#define IRQ_EINT26 S3C6400_IRQ(90)
++#define IRQ_EINT27 S3C6400_IRQ(91)
++
++
++#define NR_IRQS (IRQ_EINT27+1)
++#endif
++
++
+ #endif /* __ASM_ARCH_IRQ_H */
+diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
+index b33ed3b..366ab4e 100644
+--- a/include/asm-arm/arch-s3c2410/map.h
++++ b/include/asm-arm/arch-s3c2410/map.h
+@@ -15,27 +15,41 @@
+
+ #include <asm/plat-s3c/map.h>
+
+-#define S3C2410_ADDR(x) S3C_ADDR(x)
+-
+ /* interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+ #define S3C24XX_VA_IRQ S3C_VA_IRQ
+ #define S3C2410_PA_IRQ (0x4A000000)
+-#define S3C24XX_SZ_IRQ SZ_1M
++#define S3C6400_PA_IRQ (0x71200000)
++#define S5PC100_PA_IRQ (0xE4000000)
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_IRQ SZ_4M
++#else
++#define S3C24XX_SZ_IRQ SZ_2M
++#endif
+
+ /* memory controller registers */
+ #define S3C24XX_VA_MEMCTRL S3C_VA_MEM
+ #define S3C2410_PA_MEMCTRL (0x48000000)
+-#define S3C24XX_SZ_MEMCTRL SZ_1M
++#define S3C24XX_SZ_MEMCTRL SZ_8K
+
+ /* USB host controller */
+ #define S3C2410_PA_USBHOST (0x49000000)
++#define S3C6400_PA_USBHOST (0x74300000)
++#define S5PC100_PA_USBHOST (0xED400000)
+ #define S3C24XX_SZ_USBHOST SZ_1M
+
+ /* DMA controller */
+ #define S3C2410_PA_DMA (0x4B000000)
+-#define S3C24XX_SZ_DMA SZ_1M
++#define S3C6400_PA_DMA (0x75000000)
++#define S5PC100_PA_DMA (0xE8000000)
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_DMA SZ_8M
++#else
++#define S3C24XX_SZ_DMA SZ_2M
++#endif
+
+ /* Clock and Power management */
+ #define S3C24XX_VA_CLKPWR S3C_VA_SYS
+@@ -43,39 +57,71 @@
+ #define S3C24XX_SZ_CLKPWR SZ_1M
+
+ /* LCD controller */
++#define S3C24XX_VA_LCD S3C_VA_LCD
+ #define S3C2410_PA_LCD (0x4D000000)
++#define S3C2443_PA_LCD (0x4C800000)
++#define S3C6400_PA_LCD (0x77100000)
++#define S5PC100_PA_LCD (0xEE000000)
+ #define S3C24XX_SZ_LCD SZ_1M
+
+ /* NAND flash controller */
+ #define S3C2410_PA_NAND (0x4E000000)
++#define S3C6400_PA_NAND (0x70200000)
++#define S5PC100_PA_NAND (0xE7200000)
+ #define S3C24XX_SZ_NAND SZ_1M
+
+ /* UARTs */
+ #define S3C24XX_VA_UART S3C_VA_UART
+ #define S3C2410_PA_UART (0x50000000)
++#define S3C6400_PA_UART (0x7F005000)
++#define S5PC100_PA_UART (0xEC000000)
++
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_UART SZ_4K
++#else
+ #define S3C24XX_SZ_UART SZ_1M
++#endif
+
+-/* Timers */
++/* PWM Timers */
+ #define S3C24XX_VA_TIMER S3C_VA_TIMER
+ #define S3C2410_PA_TIMER (0x51000000)
+-#define S3C24XX_SZ_TIMER SZ_1M
++#define S3C6400_PA_TIMER (0x7F006000)
++#define S5PC100_PA_TIMER (0xEA000000)
++#define S3C24XX_SZ_TIMER SZ_4K
+
+ /* USB Device port */
++#define S3C24XX_VA_USBDEV S3C_VA_USBDEV
+ #define S3C2410_PA_USBDEV (0x52000000)
++#define S3C2443_PA_USBDEV (0x49800000)
+ #define S3C24XX_SZ_USBDEV SZ_1M
+
+ /* Watchdog */
+ #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
+ #define S3C2410_PA_WATCHDOG (0x53000000)
+-#define S3C24XX_SZ_WATCHDOG SZ_1M
++#define S3C6400_PA_WATCHDOG (0x7E004000)
++#define S5PC100_PA_WATCHDOG (0xEA200000)
++#define S3C24XX_SZ_WATCHDOG SZ_4K
+
+ /* IIC hardware controller */
+ #define S3C2410_PA_IIC (0x54000000)
+-#define S3C24XX_SZ_IIC SZ_1M
++#define S3C6400_PA_IIC0 (0x7F004000)
++#define S3C6400_PA_IIC1 (0x7F00F000)
++#define S5PC100_PA_IIC (0xEC100000)
++#define S3C24XX_SZ_IIC SZ_4K
+
+ /* IIS controller */
+ #define S3C2410_PA_IIS (0x55000000)
+-#define S3C24XX_SZ_IIS SZ_1M
++#define S3C2450_PA_IIS (0x55000000)
++#define S3C2450_PA_IIS1 (0x55000100)
++#define S3C6400_PA_IIS (0x7F002000)
++#define S3C6410_PA_IIS_V40 (0x7F00D000)
++#define S5PC100_PA_IIS (0xF2000000)
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_IIS SZ_1M
++#else
++#define S3C24XX_SZ_IIS SZ_8K
++#endif
+
+ /* GPIO ports */
+
+@@ -86,22 +132,53 @@
+ * 0xFA800000, which is not in the way of any current mapping
+ * by the base system.
+ */
+-
+-#define S3C2410_PA_GPIO (0x56000000)
+-#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
+-#define S3C24XX_SZ_GPIO SZ_1M
++#if defined(CONFIG_PLAT_S3C64XX)
++#define S3C24XX_VA_GPIO S3C_VA_GPIO
++#define S3C6400_PA_GPIO (0x7F008000)
++#define S3C24XX_SZ_GPIO SZ_4K
++#elif defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_VA_GPIO S3C_VA_GPIO
++#define S5PC100_PA_GPIO (0xE0300000)
++#define S3C24XX_SZ_GPIO SZ_1M
++#else
++#define S3C2410_PA_GPIO (0x56000000)
++#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
++#define S3C24XX_SZ_GPIO SZ_1M
++#endif
+
+ /* RTC */
+ #define S3C2410_PA_RTC (0x57000000)
+-#define S3C24XX_SZ_RTC SZ_1M
++#define S3C2450_PA_RTC (0x57005000)
++#define S3C6400_PA_RTC (0x7E005000)
++#define S5PC100_PA_RTC (0xEA300000)
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_RTC SZ_1M
++#else
++#define S3C24XX_SZ_RTC SZ_4K
++#endif
+
+ /* ADC */
+ #define S3C2410_PA_ADC (0x58000000)
+-#define S3C24XX_SZ_ADC SZ_1M
++#define S3C6400_PA_ADC (0x7E00B000)
++#define S5PC100_PA_ADC (0xF3000000)
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_ADC SZ_1M
++#else
++#define S3C24XX_SZ_ADC SZ_4K
++#endif
+
+ /* SPI */
+ #define S3C2410_PA_SPI (0x59000000)
+-#define S3C24XX_SZ_SPI SZ_1M
++#define S3C6400_PA_SPI (0x7F00B000)
++#define S5PC100_PA_SPI (0xEC300000)
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_SPI SZ_1M
++#else
++#define S3C24XX_SZ_SPI SZ_8K
++#endif
+
+ /* SDI */
+ #define S3C2410_PA_SDI (0x5A000000)
+@@ -109,55 +186,286 @@
+
+ /* CAMIF */
+ #define S3C2440_PA_CAMIF (0x4F000000)
++#define S3C2443_PA_CAMIF (0x4D800000)
++#define S3C6400_PA_CAMIF (0x78000000)
++#define S5PC100_PA_CAMIF (0xEE200000)
+ #define S3C2440_SZ_CAMIF SZ_1M
++#define S3C2443_SZ_CAMIF SZ_1M
++#define S3C24XX_SZ_CAMIF SZ_1M
+
+ /* AC97 */
+-
+ #define S3C2440_PA_AC97 (0x5B000000)
++#define S3C6400_PA_AC97 (0x7F001000)
++#define S5PC100_PA_AC97 (0xF2300000)
+ #define S3C2440_SZ_AC97 SZ_1M
+
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_SZ_AC97 SZ_1M
++#else
++#define S3C24XX_SZ_AC97 SZ_4K
++#endif
++
++/* Host I/F Indirect & Direct */
++#define S3C24XX_VA_HOSTIFA S3C_VA_HOSTIFA
++#define S3C24XX_PA_HOSTIFA (0x74000000)
++#define S3C24XX_SZ_HOSTIFA SZ_1M
++
++#define S3C24XX_VA_HOSTIFB S3C_VA_HOSTIFB
++#define S3C24XX_PA_HOSTIFB (0x74100000)
++#define S3C24XX_SZ_HOSTIFB SZ_1M
++
++/* CHIP_ID */
++#define S3C24XX_VA_CHIP_ID S3C_VA_CHIP_ID
++#define S3C64XX_PA_CHIP_ID (0x7E00E000)
++#define S5PC100_PA_CHIP_ID (0xE0000000)
++#define S3C24XX_SZ_CHIP_ID SZ_4K
++
++/* System Controller */
++#define S3C24XX_VA_SYSCON S3C_VA_SYSCON
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_PA_SYSCON (0xE0100000)
++#define S3C24XX_SZ_SYSCON SZ_2M
++#else
++#define S3C24XX_PA_SYSCON (0x7E00F000)
++#define S3C24XX_SZ_SYSCON SZ_4K
++#endif
++
++/* AXI */
++#define S3C6410_PA_AXI_SYS (0x7E003000)
++#define S3C6410_PA_AXI_PERI (0x7E008000)
++#define S3C6410_PA_AXI_SFR (0x7E009000)
++
++/* Ethernet */
++#define S3C24XX_VA_CS8900 S3C_VA_CS8900
++#define S3C2443_PA_CS8900 (0x09000000)
++#define S3C6400_PA_CS8900 (0x18800000)
++#define S3C24XX_SZ_CS8900 SZ_1M
++
++#define S3C6410_PA_SMC9115 (0x18000000)
++#define S3C2450_PA_SMC9115 (0x20000000)
++
++/* SROM SFR */
++#define S3C24XX_VA_SROMC S3C_VA_SROMC
++#define S3C2443_PA_SROMC (0x4F000000)
++#define S3C6400_PA_SROMC (0x70000000)
++#define S5PC100_PA_SROMC (0xE7000000)
++#define S3C24XX_SZ_SROMC SZ_1M
++
+ /* S3C2443 High-speed SD/MMC */
+-#define S3C2443_PA_HSMMC (0x4A800000)
+-#define S3C2443_SZ_HSMMC (256)
++#define S3C2443_PA_HSMMC (0x4A800000)
++#define S3C6400_PA_HSMMC (0x7C200000)
++#define S5PC100_PA_HSMMC (0xED800000)
++#define S3C2443_SZ_HSMMC SZ_1M
++#define S3C_SZ_HSMMC SZ_1M
++
++/* MMC controller - available on the S3C2400 */
++#define S3C2400_PA_MMC (0x15A00000)
++#define S3C2400_SZ_MMC SZ_1M
++
++/* CF/ATA controller - available on the S3C2443/S3C6400 */
++#define S3C2443_PA_CFATA (0x4B800000)
++#define S3C6400_PA_CFATA (0x70300000)
++#define S5PC100_PA_CFATA (0xE7800000)
++#define S3C_SZ_CFATA SZ_1M
++
++/* DRAM controller 0 */
++#define S3C24XX_VA_DMC0 S3C_VA_DMC0
++
++#if defined(CONFIG_PLAT_S3C64XX)
++#define S3C24XX_PA_DMC0 (0x7E000000)
++#elif defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_PA_DMC0 (0xE6000000)
++#endif
++
++#define S3C24XX_SZ_DMC0 SZ_4K
++
++#if !defined(CONFIG_PLAT_S5PC1XX)
++/* DRAM controller 1 */
++#define S3C24XX_VA_DMC1 S3C_VA_DMC1
++#define S3C24XX_PA_DMC1 (0x7E001000)
++#define S3C24XX_SZ_DMC1 SZ_4K
++#endif
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++/* USB OTG */
++#define S3C24XX_VA_OTG S3C_VA_OTG
++#define S3C24XX_PA_OTG (0x7C000000)
++#define S3C24XX_SZ_OTG SZ_1M
++
++/* USB OTG SFR */
++#define S3C24XX_VA_OTGSFR S3C_VA_OTGSFR
++#define S3C24XX_PA_OTGSFR (0x7C100000)
++#define S3C24XX_SZ_OTGSFR SZ_1M
++#endif
++
++/* 2D Graphics */
++#define S3C6400_PA_G2D (0x76100000)
++#define S3C_SZ_G2D SZ_1M
++
++#define S3C6400_PA_ROTATOR (0x77200000)
++#define S3C_SZ_ROTATOR SZ_1M
++
++#if defined(CONFIG_CPU_S3C6410)
++/* G3D */
++#define S3C6410_PA_G3D (0x72000000)
++#define S3C6410_SZ_G3D SZ_4K
++#endif
++
++/* TV-ENCODER */
++#define S3C6400_PA_TVENC (0x76200000)
++#define S5PC100_PA_TVENC (0xF0000000)
++#define S3C_SZ_TVENC SZ_1M
++
++/* TV-SCALER*/
++#define S3C6400_PA_TVSCALER (0x76300000)
++#define S3C_SZ_TVSCALER SZ_1M
++
++/* VPP */
++#define S3C6400_PA_VPP (0x77000000)
++#define S5PC100_PA_VPP (0xF0100000)
++#define S3C_SZ_VPP SZ_1M
++
++/* MFC */
++#define S3C6400_PA_MFC (0x7E002000)
++#define S5PC100_PA_MFC (0xF1000000)
++#define S3C_SZ_MFC SZ_4K
++
++/* JPEG */
++#define S3C6400_PA_JPEG (0x78800000)
++#define S5PC100_PA_JPEG (0xEE500000)
++
++#if defined(CONFIG_PLAT_S5PC1XX)
++#define S3C_SZ_JPEG SZ_1M
++#else
++#define S3C_SZ_JPEG SZ_4M
++#endif
++
++/* OneNAND */
++#define S3C6400_PA_ONENAND (0x70100000)
++#define S5PC100_PA_ONENAND (0xE7100000)
++#define S3C_SZ_ONENAND SZ_1M
++
++/* Keypad IF */
++#define S3C6400_PA_KEYPAD (0x7E00A000)
++#define S5PC100_PA_KEYPAD (0xF3100000)
++#define S3C24XX_SZ_KEYPAD SZ_4K
++
++/* EBI registers for 2443 */
++#define S3C24XX_VA_EBI S3C_VA_EBI
++#define S3C24XX_PA_EBI (0x4E800000)
++#define S3C24XX_SZ_EBI SZ_1M
+
+ /* ISA style IO, for each machine to sort out mappings for, if it
+ * implements it. We reserve two 16M regions for ISA.
+ */
+
+-#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
+-#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
++#define S3C24XX_VA_ISA_WORD S3C_ADDR(0x02000000)
++#define S3C24XX_VA_ISA_BYTE S3C_ADDR(0x03000000)
+
+ /* physical addresses of all the chip-select areas */
+
+-#define S3C2410_CS0 (0x00000000)
+-#define S3C2410_CS1 (0x08000000)
+-#define S3C2410_CS2 (0x10000000)
+-#define S3C2410_CS3 (0x18000000)
+-#define S3C2410_CS4 (0x20000000)
+-#define S3C2410_CS5 (0x28000000)
+-#define S3C2410_CS6 (0x30000000)
+-#define S3C2410_CS7 (0x38000000)
++#define S3C2410_CS0 (0x00000000)
++#define S3C2410_CS1 (0x08000000)
++#define S3C2410_CS2 (0x10000000)
++#define S3C2410_CS3 (0x18000000)
++#define S3C2410_CS4 (0x20000000)
++#define S3C2410_CS5 (0x28000000)
++#define S3C2410_CS6 (0x30000000)
++#define S3C2410_CS7 (0x38000000)
+
+ #define S3C2410_SDRAM_PA (S3C2410_CS6)
++#define S3C_SDRAM_PA (0x50000000)
++#define S5PC1XX_SDRAM_PA (0x20000000)
+
+-/* Use a single interface for common resources between S3C24XX cpus */
+
+-#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
+-#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
+-#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
+-#define S3C24XX_PA_DMA S3C2410_PA_DMA
+-#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
+-#define S3C24XX_PA_LCD S3C2410_PA_LCD
+-#define S3C24XX_PA_UART S3C2410_PA_UART
+-#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
+-#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
+-#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
+-#define S3C24XX_PA_IIC S3C2410_PA_IIC
+-#define S3C24XX_PA_IIS S3C2410_PA_IIS
+-#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
+-#define S3C24XX_PA_RTC S3C2410_PA_RTC
+-#define S3C24XX_PA_ADC S3C2410_PA_ADC
+-#define S3C24XX_PA_SPI S3C2410_PA_SPI
++/* Use a single interface for common resources between S3C24XX cpus */
++#if defined(CONFIG_PLAT_S3C64XX)
++#define S3C24XX_PA_ADC S3C6400_PA_ADC
++#define S3C24XX_PA_CAMIF S3C6400_PA_CAMIF
++#define S3C24XX_PA_DMA S3C6400_PA_DMA
++#define S3C24XX_PA_IRQ S3C6400_PA_IRQ
++#define S3C24XX_PA_LCD S3C6400_PA_LCD
++#define S3C24XX_PA_UART S3C6400_PA_UART
++#define S3C24XX_PA_USBHOST S3C6400_PA_USBHOST
++#define S3C24XX_PA_WATCHDOG S3C6400_PA_WATCHDOG
++#define S3C24XX_PA_IIS S3C6400_PA_IIS
++#define S3C24XX_PA_RTC S3C6400_PA_RTC
++#define S3C24XX_PA_SPI S3C6400_PA_SPI
++#define S3C24XX_PA_TIMER S3C6400_PA_TIMER
++#define S3C24XX_PA_NAND S3C6400_PA_NAND
++#define S3C24XX_PA_ONENAND S3C6400_PA_ONENAND
++#define S3C24XX_PA_GPIO S3C6400_PA_GPIO
++#define S3C24XX_PA_CS8900 S3C6400_PA_CS8900
++#define S3C24XX_PA_TVENC S3C6400_PA_TVENC
++#define S3C24XX_PA_TVSCALER S3C6400_PA_TVSCALER
++#define S3C24XX_PA_CFATA S3C6400_PA_CFATA
++#define S3C24XX_PA_AC97 S3C6400_PA_AC97
++#define S3C24XX_PA_KEYPAD S3C6400_PA_KEYPAD
++#define S3C24XX_PA_SROMC S3C6400_PA_SROMC
++#define S3C_PA_SMC9115 S3C6410_PA_SMC9115
++#define S3C_PA_HSMMC S3C6400_PA_HSMMC
++#define S3C_PA_CFATA S3C6400_PA_CFATA
++#elif defined(CONFIG_PLAT_S5PC1XX)
++#define S3C24XX_PA_ADC S5PC100_PA_ADC
++#define S3C24XX_PA_CAMIF S5PC100_PA_CAMIF
++#define S3C24XX_PA_DMA S5PC100_PA_DMA
++#define S3C24XX_PA_IRQ S5PC100_PA_IRQ
++#define S3C24XX_PA_LCD S5PC100_PA_LCD
++#define S3C24XX_PA_UART S5PC100_PA_UART
++#define S3C24XX_PA_USBHOST S5PC100_PA_USBHOST
++#define S3C24XX_PA_WATCHDOG S5PC100_PA_WATCHDOG
++#define S3C24XX_PA_IIS S5PC100_PA_IIS
++#define S3C24XX_PA_IIC S5PC100_PA_IIC
++#define S3C24XX_PA_RTC S5PC100_PA_RTC
++#define S3C24XX_PA_SPI S5PC100_PA_SPI
++#define S3C24XX_PA_TIMER S5PC100_PA_TIMER
++#define S3C24XX_PA_NAND S5PC100_PA_NAND
++#define S3C24XX_PA_ONENAND S5PC100_PA_ONENAND
++#define S3C24XX_PA_GPIO S5PC100_PA_GPIO
++#define S3C24XX_PA_CS8900 S5PC100_PA_CS8900
++#define S3C24XX_PA_TVENC S5PC100_PA_TVENC
++#define S3C24XX_PA_TVSCALER S5PC100_PA_TVSCALER
++#define S3C24XX_PA_CFATA S5PC100_PA_CFATA
++#define S3C24XX_PA_AC97 S5PC100_PA_AC97
++#define S3C24XX_PA_KEYPAD S5PC100_PA_KEYPAD
++#define S3C24XX_PA_SROMC S5PC100_PA_SROMC
++#define S3C_PA_SMC9115 S3C6410_PA_SMC9115
++#define S3C_PA_HSMMC S5PC100_PA_HSMMC
++#define S3C_PA_CFATA S5PC100_PA_CFATA
++#define S3C24XX_PA_CHIP_ID S5PC100_PA_CHIP_ID
++#else
++#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
++#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
++#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
++#define S3C24XX_PA_DMA S3C2410_PA_DMA
++#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C24XX_PA_LCD S3C2443_PA_LCD
++#define S3C24XX_PA_CS8900 S3C2443_PA_CS8900
++#define S3C24XX_PA_USBDEV S3C2443_PA_USBDEV
++#define S3C24XX_PA_CAMIF S3C2443_PA_CAMIF
++#define S3C_PA_HSMMC S3C2443_PA_HSMMC
++#define S3C_PA_CFATA S3C2443_PA_CFATA
++#define S3C24XX_PA_SROMC S3C2443_PA_SROMC
++#define S3C_PA_SPI_0 (0x52000000)
++#define S3C_SZ_SPI_0 SZ_1M
++#define S3C_PA_SMC9115 S3C2450_PA_SMC9115
++#else
++#define S3C24XX_PA_LCD S3C2410_PA_LCD
++#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
++#endif
++#define S3C24XX_PA_UART S3C2410_PA_UART
++#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
++#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
++#define S3C24XX_PA_IIC S3C2410_PA_IIC
++#define S3C24XX_PA_IIS S3C2410_PA_IIS
++#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
++#define S3C24XX_PA_RTC S3C2410_PA_RTC
++#define S3C24XX_PA_ADC S3C2410_PA_ADC
++#define S3C24XX_PA_SPI S3C2410_PA_SPI
++#define S3C24XX_PA_NAND S3C2410_PA_NAND
++#define S3C24XX_PA_AC97 S3C2440_PA_AC97
++#endif
+
+ /* deal with the registers that move under the 2412/2413 */
+
+diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
+index 533e243..28143f2 100644
+--- a/include/asm-arm/arch-s3c2410/memory.h
++++ b/include/asm-arm/arch-s3c2410/memory.h
+@@ -11,7 +11,24 @@
+ #ifndef __ASM_ARCH_MEMORY_H
+ #define __ASM_ARCH_MEMORY_H
+
++#if defined (CONFIG_PLAT_S5PC1XX)
++#define PHYS_OFFSET UL(0x20000000)
++
++#elif defined (CONFIG_PLAT_S3C64XX)
++#define PHYS_OFFSET UL(0x50000000)
++
++#else
++/*
++ * DRAM starts at 0x30000000 for S3C2410/S3C2440
++ * and at 0x0C000000 for S3C2400
++ */
++#ifdef CONFIG_CPU_S3C2400
++#define PHYS_OFFSET UL(0x0C000000)
++#else
+ #define PHYS_OFFSET UL(0x30000000)
++#endif
++
++#endif
+
+ #define __virt_to_bus(x) __virt_to_phys(x)
+ #define __bus_to_virt(x) __phys_to_virt(x)
+diff --git a/include/asm-arm/arch-s3c2410/regs-camif.h b/include/asm-arm/arch-s3c2410/regs-camif.h
+new file mode 100644
+index 0000000..5946cf2
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-camif.h
+@@ -0,0 +1,460 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-lcd.h
++ *
++ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
++ * http://www.simtec.co.uk/products/SWLINUX/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++
++#ifndef ___ASM_ARCH_REGS_CAMIF_H
++#define ___ASM_ARCH_REGS_CAMIF_H
++
++#define S3C_CAMIFREG(x) (x)
++
++/*************************************************************************
++ * Macro part
++ ************************************************************************/
++#define S3C_CISRCFMT_SOURCEHSIZE(x) ((x) << 16)
++#define S3C_CISRCFMT_GET_SOURCEHSIZE(x) (((x) >> 16) & 0x1FFFF)
++#define S3C_CISRCFMT_SOURCEVSIZE(x) ((x) << 0)
++#define S3C_CISRCFMT_GET_SOURCEVSIZE(x) (((x) >> 0) & 0x1FFF)
++
++#define S3C_CIWDOFST_WINHOROFST(x) ((x) << 16)
++#define S3C_CIWDOFST_GET_WINHOROFST(x) (((x) >> 16) & 0x7FF)
++#define S3C_CIWDOFST_WINVEROFST(x) ((x) << 0)
++#define S3C_CIWDOFST_GET_WINVEROFST(x) (((x) >> 0) & 0x7FF)
++
++#define S3C_CIDOWSFT2_WINHOROFST2(x) ((x) << 16)
++#define S3C_CIDOWSFT2_GET_WINHOROFST2(x) (((x) >> 16) & 0x7FF)
++#define S3C_CIDOWSFT2_WINVEROFST2(x) ((x) << 0)
++#define S3C_CIDOWSFT2_GET_WINVEROFST2(x) (((x) >> 0) & 0x7FF)
++
++#define S3C_CICOTRGFMT_TARGETHSIZE_CO(x) ((x) << 16)
++#define S3C_CICOTRGFMT_GET_TARGETHSIZE_CO(x) (((x) >> 16) & 0x1FFF)
++
++#define S3C_CICOTRGFMT_TARGETVSIZE_CO(x) ((x) << 0)
++#define S3C_CICOTRGFMT_GET_TARGETVSIZE_CO(x) (((x) >> 0) & 0x1FFF)
++
++#define S3C_CICOCTRL_YBURST1_CO(x) ((x) << 19)
++#define S3C_CICOCTRL_YBURST2_CO(x) ((x) << 14)
++#define S3C_CICOCTRL_CBURST1_CO(x) ((x) << 9)
++#define S3C_CICOCTRL_CBURST2_CO(x) ((x) << 4)
++
++#define S3C_CICOSCPRERATIO_SHFACTOR_CO(x) ((x) << 28)
++#define S3C_CICOSCPRERATIO_GET_SHFACTOR_CO(x) (((x) >> 28) & 0x7F)
++#define S3C_CICOSCPRERATIO_PREHORRATIO_CO(x) ((x) << 16)
++#define S3C_CICOSCPRERATIO_GET_PREHORRATIO_CO(x) (((x) >> 16) & 0x7F)
++#define S3C_CICOSCPRERATIO_PREVERRATIO_CO(x) ((x) << 0)
++#define S3C_CICOSCPRERATIO_GET_PREVERRATIO_CO(x) (((x) >> 0) & 0x7F)
++
++#define S3C_CICOSCPREDST_PREDSTWIDTH_CO(x) ((x) << 16)
++#define S3C_CICOSCPREDST_GET_PREDSTWIDTH_CO(x) (((x) >> 16) & 0x7FF)
++#define S3C_CICOSCPREDST_PREDSTHEIGHT_CO(x) ((x) << 0)
++#define S3C_CICOSCPREDST_GET_PREDSTHEIGHT_CO(x) (((x) >> 0) & 0x7FF)
++
++#define S3C_CICOSCCTRL_MAINHORRATIO_CO(x) ((x) << 16)
++#define S3C_CICOSCCTRL_GET_MAINHORRATIO_CO(x) (((x) >> 16) & 0x1FF)
++#define S3C_CICOSCCTRL_MAINVERRATIO_CO(x) ((x) << 0)
++
++#define S3C_CICOSTATUS_FRAMECNT_CO(x) ((x) << 26)
++#define S3C_CICOSTATUS_GET_FRAMECNT_CO(x) (((x) >> 26) & 0x3)
++
++#define S3C_CIPRTRGFMT_TARGETHSIZE_PR(x) ((x) << 16)
++#define S3C_CIPRTRGFMT_GET_TARGETHSIZE_PR(x) (((x) >> 16) & 0x1FFF)
++
++#define S3C_CIPRTRGFMT_GET_ROT90_PR(x) (((x) >> 13) & 0x1)
++
++#define S3C_CIPRTRGFMT_TARGETVSIZE_PR(x) ((x) << 0)
++#define S3C_CIPRTRGFMT_GET_TARGETVSIZE_PR(x) (((x) >> 0) & 0x1FFF)
++
++#define S3C_CIPRSCPRERATIO_SHFACTOR_PR(x) ((x) << 28)
++#define S3C_CIPRSCPRERATIO_GET_SHFACTOR_PR(x) (((x) >> 28) & 0xF)
++#define S3C_CIPRSCPRERATIO_PREHORRATIO_PR(x) ((x) << 16)
++#define S3C_CIPRSCPRERATIO_GET_PREHORRATIO_PR(x) (((x) >> 16) & 0x7F)
++#define S3C_CIPRSCPRERATIO_PREVERRATIO_PR(x) ((x) << 0)
++#define S3C_CIPRSCPRERATIO_GET_PREVERRATIO_PR(x) (((x) >> 0) & 0x7F)
++
++#define S3C_CIPRSCPREDST_PREDSTWIDTH_PR(x) ((x) << 16)
++#define S3C_CIPRSCPREDST_GET_PREDSTWIDTH_PR(x) (((x) >> 16) & 0xFFF)
++#define S3C_CIPRSCPREDST_PREDSTHEIGHT_PR(x) ((x) << 0)
++#define S3C_CIPRSCPREDST_GET_PREDSTHEIGHT_PR(x) (((x) >> 0) & 0xFFF)
++
++#define S3C_CIPRSCCTRL_MAINHORRATIO_PR(x) ((x) << 16)
++#define S3C_CIPRSCCTRL_GET_MAINHORRATIO_PR(x) (((x) >> 16) && 0x1FF)
++#define S3C_CIPRSCCTRL_MAINVERRATIO_PR(x) ((x) << 0)
++#define S3C_CIPRSCCTRL_GET_MAINVERRATIO_PR(x) (((x) >> 0) && 0x1FF)
++
++/*************************************************************************
++ * Bit definition part
++ ************************************************************************/
++/* Windows Offset Register */
++#define S3C_CIWDOFST_WINOFSEN (1 << 31)
++#define S3C_CIWDOFST_CLROVCOFIY (1 << 30)
++#define S3C_CIWDOFST_CLROVRLB_CO (1 << 29)
++#define S3C_CIWDOFST_CLROVRLB_PR (1 << 28)
++#define S3C_CIWDOFST_CLROVPRFIY (1 << 27)
++#define S3C_CIWDOFST_CLROVCOFICB (1 << 15)
++#define S3C_CIWDOFST_CLROVCOFICR (1 << 14)
++#define S3C_CIWDOFST_CLROVPRFICB (1 << 13)
++#define S3C_CIWDOFST_CLROVPRFICR (1 << 12)
++
++/* Global Control Register */
++#define S3C_CIGCTRL_SWRST (1 << 31)
++#define S3C_CIGCTRL_CAMRST (1 << 30)
++
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20)
++#endif
++
++#define S3C_CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
++#define S3C_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
++#define S3C_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
++#define S3C_CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
++
++#define S3C_CIGCTRL_INVPOLPCLK (1 << 26)
++#define S3C_CIGCTRL_INVPOLVSYNC (1 << 25)
++#define S3C_CIGCTRL_INVPOLHREF (1 << 24)
++#define S3C_CIGCTRL_IRQ_OVFEN (1 << 22)
++#define S3C_CIGCTRL_HREF_MASK (1 << 21)
++#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20)
++#define S3C_CIGCTRL_IRQ_CLR_C (1 << 19)
++#define S3C_CIGCTRL_IRQ_CLR_P (1 << 18)
++
++/* Codec Target Format Register */
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++#define S3C_CICOTRGFMT_IN422_422 (1 << 31)
++#define S3C_CICOTRGFMT_IN422_420 (0 << 31)
++#define S3C_CICOTRGFMT_OUT422_422 (1 << 30)
++#define S3C_CICOTRGFMT_OUT422_420 (0 << 30)
++
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410 )
++#define S3C_CICOTRGFMT_OUTFORMAT_RGBOUT (3 << 29)
++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUTINTERLEAVE (2 << 29)
++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422OUT (1 << 29)
++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR420OUT (0 << 29)
++#endif
++
++#define S3C_CICOTRGFMT_INTERLEAVE_ON (1 << 29)
++#define S3C_CICOTRGFMT_INTERLEAVE_OFF (0 << 29)
++
++#define S3C_CICOTRGFMT_FLIP_180 (3 << 14)
++#define S3C_CICOTRGFMT_FLIP_Y_MIRROR (2 << 14)
++#define S3C_CICOTRGFMT_FLIP_X_MIRROR (1 << 14)
++#define S3C_CICOTRGFMT_FLIP_NORMAL (0 << 14)
++
++/* Codec DMA Control Register */
++#define S3C_CICOCTRL_LASTIRQEN (1 << 2)
++#define S3C_CICOCTRL_ORDER422_CRYCBY (3 << 0)
++#define S3C_CICOCTRL_ORDER422_CBYCRY (2 << 0)
++#define S3C_CICOCTRL_ORDER422_YCRYCB (1 << 0)
++#define S3C_CICOCTRL_ORDER422_YCBYCR (0 << 0)
++
++/* Codec Main-Scaler Control Register */
++#define S3C_CICOSCCTRL_SCALERBYPASS_CO (1 << 31)
++#define S3C_CICOSCCTRL_SCALEUP_H (1 << 30)
++#define S3C_CICOSCCTRL_SCALEUP_V (1 << 29)
++
++#define S3C_CICOSCCTRL_CSCR2Y_WIDE (1 << 28)
++#define S3C_CICOSCCTRL_CSCR2Y_NARROW (0 << 28)
++
++#define S3C_CICOSCCTRL_CSCY2R_WIDE (1 << 27)
++#define S3C_CICOSCCTRL_CSCY2R_NARROW (0 << 27)
++
++#define S3C_CICOSCCTRL_LCDPATHEN_FIFO (1 << 26)
++#define S3C_CICOSCCTRL_LCDPATHEN_DMA (0 << 26)
++
++#define S3C_CICOSCCTRL_INTERLACE_INTERLACE (1 << 25)
++#define S3C_CICOSCCTRL_INTERLACE_PROGRESSIVE (0 << 25)
++
++#define S3C_CICOSCCTRL_COSCALERSTART (1 << 15)
++
++#define S3C_CICOSCCTRL_INRGB_FMT_RGB888 (2 << 13)
++#define S3C_CICOSCCTRL_INRGB_FMT_RGB666 (1 << 13)
++#define S3C_CICOSCCTRL_INRGB_FMT_RGB565 (0 << 13)
++
++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
++
++#define S3C_CICOSCCTRL_EXTRGB_EXTENSION (1 << 10)
++#define S3C_CICOSCCTRL_EXTRGB_NORMAL (0 << 10)
++
++/* Codec Status Register */
++#define S3C_CICOSTATUS_OVFIY_CO (1 << 31)
++#define S3C_CICOSTATUS_OVFICB_CO (1 << 30)
++#define S3C_CICOSTATUS_OVFICR_CO (1 << 29)
++#define S3C_CICOSTATUS_VSYNC (1 << 28)
++#define S3C_CICOSTATUS_WINOFSTEN_CO (1 << 25)
++#define S3C_CICOSTATUS_IMGCPTEN_CAMIF (1 << 22)
++#define S3C_CICOSTATUS_IMGCPTEN_COSC (1 << 21)
++#define S3C_CICOSTATUS_VSYNC_A (1 << 20)
++#define S3C_CICOSTATUS_VSYNC_B (1 << 19)
++#define S3C_CICOSTATUS_OVRLB_CO (1 << 18)
++#define S3C_CICOSTATUS_FRAMEEND_CO (1 << 17)
++
++/* Preview Target Format Register */
++#define S3C_CIPRTRGFMT_FLIPMD_180ROT (3 << 14)
++#define S3C_CIPRTRGFMT_FLIPMD_YMIRROR (2 << 14)
++#define S3C_CIPRTRGFMT_FLIPMD_XMIRROR (1 << 14)
++#define S3C_CIPRTRGFMT_FLIPMD_NORMAL (0 << 14)
++
++#define S3C_CIPRTRGFMT_ROT90_ROTATE (1 << 13)
++#define S3C_CIPRTRGFMT_ROT90_BYPASS (0 << 13)
++
++/* Preview DMA Control Register */
++#define S3C_CIPRCTRL_LASTIRQEN_ENABLE (1 << 2)
++#define S3C_CIPRCTRL_LASTIRQEN_NORMAL (0 << 2)
++
++#define S3C_CIPRCTRL_ORDER422_CRYCBY (3 << 0)
++#define S3C_CIPRCTRL_ORDER422_CBYCRY (2 << 0)
++#define S3C_CIPRCTRL_ORDER422_YCRYCB (1 << 0)
++#define S3C_CIPRCTRL_ORDER422_YCBYCR (0 << 0)
++
++/* Preview Main-Scaler Control Register */
++#define S3C_CIPRSCCTRL_SAMPLE_PR (1 << 31)
++
++#define S3C_CIPRSCCTRL_RGBFORMAT_24 (1 << 30)
++#define S3C_CIPRSCCTRL_RGBFORMAT_16 (0 << 30)
++
++#define S3C_CIPRSCCTRL_START (1 << 15)
++
++#define S3C_CIPRSCCTRL_INRGB_FMT_PR_RGB888 (2 << 13)
++#define S3C_CIPRSCCTRL_INRGB_FMT_PR_RGB666 (1 << 13)
++#define S3C_CIPRSCCTRL_INRGB_FMT_PR_RGB565 (0 << 13)
++
++#define S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB888 (2 << 11)
++#define S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB666 (1 << 11)
++#define S3C_CIPRSCCTRL_OUTRGB_FMT_PR_RGB565 (0 << 11)
++
++/* Preview Status Register */
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++#define S3C_CIPRSTATUS_OVFICB_PR (1 << 31)
++#define S3C_CIPRSTATUS_OVFICR_PR (1 << 30)
++
++#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
++#define S3C_CIPRSTATUS_OVFIY_PR (1 << 31)
++#define S3C_CIPRSTATUS_OVFICB_PR (1 << 30)
++#define S3C_CIPRSTATUS_OVFICR_PR (1 << 29)
++#endif
++
++/* Image Capture Enable Register */
++#define S3C_CIIMGCPT_IMGCPTEN (1 << 31)
++#define S3C_CIIMGCPT_IMGCPTEN_COSC (1 << 30)
++#define S3C_CIIMGCPT_IMGCPTEN_PRSC (1 << 29)
++
++#define S3C_CIIMGCPT_CPT_CODMA_SEL_RGB (1 << 26)
++#define S3C_CIIMGCPT_CPT_CODMA_SEL_YUV (0 << 26)
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++#define S3C_CIIMGCPT_CPT_CODMA_RGBFMT_24 (1 << 25)
++#define S3C_CIIMGCPT_CPT_CODMA_RGBFMT_16 (0 << 25)
++#define S3C_CIIMGCPT_CPT_CODMA_ENABLE (1 << 24)
++#define S3C_CIIMGCPT_CPT_CODMA_DISABLE (0 << 24)
++#define S3C_CIIMGCPT_CPT_CODMA_MOD_CNT (1 << 18)
++#define S3C_CIIMGCPT_CPT_CODMA_MOD_EN (0 << 18)
++
++#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
++#define S3C_CIIMGCPT_CPT_FREN_CO_ENABLE (1 << 25)
++#define S3C_CIIMGCPT_CPT_FREN_CO_DISABLE (0 << 25)
++#define S3C_CIIMGCPT_CPT_FREN_PR_ENABLE (1 << 24)
++#define S3C_CIIMGCPT_CPT_FREN_PR_DISABLE (0 << 24)
++#define S3C_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
++#define S3C_CIIMGCPT_CPT_FRMOD_EN (0 << 18)
++#endif
++
++/* Image Effects Register */
++#define S3C_CIIMGEFF_IE_ON_PR_ENABLE (1 << 31)
++#define S3C_CIIMGEFF_IE_ON_PR_DISABLE (0 << 31)
++
++#define S3C_CIIMGEFF_IE_ON_CO_ENABLE (1 << 30)
++#define S3C_CIIMGEFF_IE_ON_CO_DISABLE (0 << 30)
++
++#define S3C_CIIMGEFF_IE_AFTER_SC_BEFORE (0 << 29)
++#define S3C_CIIMGEFF_IE_AFTER_SC_AFTER (1 << 29)
++
++#define S3C_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
++#define S3C_CIIMGEFF_FIN_EMBOSSING (4 << 26)
++#define S3C_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
++#define S3C_CIIMGEFF_FIN_NEGATIVE (2 << 26)
++#define S3C_CIIMGEFF_FIN_ARBITRARY (1 << 26)
++#define S3C_CIIMGEFF_FIN_BYPASS (0 << 26)
++
++/* MSDMA for Codec Source Image Width Register */
++#define S3C_MSCOWIDTH_AUTOLOAD_ENABLE (1 << 31)
++#define S3C_MSCOWIDTH_AUTOLOAD_DISABLE (0 << 31)
++
++#define S3C_MSCOWIDTH_ADDR_CH_ENABLE (1 << 30)
++#define S3C_MSCOWIDTH_ADDR_CH_DISABLE (0 << 30)
++
++/* MSDMA Control Register */
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++#define S3C_CIMSCTRL_INTERLEAVE_MS_INTERLEAVE (1 << 5)
++#define S3C_CIMSCTRL_INTERLEAVE_MS_NONINTERLEAVE (0 << 5)
++#define S3C_CIMSCTRL_ORDER422_MS_CRYCBY (3 << 3)
++#define S3C_CIMSCTRL_ORDER422_MS_CBYCRY (2 << 3)
++#define S3C_CIMSCTRL_ORDER422_MS_YCRYCB (1 << 3)
++#define S3C_CIMSCTRL_ORDER422_MS_YCBYCR (0 << 3)
++#define S3C_CIMSCTRL_SEL_DMA_CAM_MEMORY (1 << 2)
++#define S3C_CIMSCTRL_SEL_DMA_CAM_EXTCAM (0 << 2)
++#define S3C_CIMSCTRL_SRC420_MS_420 (1 << 1)
++#define S3C_CIMSCTRL_SRC420_MS_422 (0 << 1)
++#define S3C_CIMSCTRL_ENVID_MS_SET (1 << 0)
++
++#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
++#define S3C_MSCOCTRL_BC_SEL_FRAME (0 << 10)
++#define S3C_MSCOCTRL_BC_SEL_FIELD (1 << 10)
++#define S3C_MSCOCTRL_BUFFER_INI_0 (0 << 8)
++#define S3C_MSCOCTRL_BUFFER_INI_1 (1 << 8)
++#define S3C_MSCOCTRL_TRG_MODE_SOFT (0 << 7)
++#define S3C_MSCOCTRL_TRG_MODE_HARD (1 << 7)
++#define S3C_MSCOCTRL_ORDER422_M_C_YCBYCR (0 << 4)
++#define S3C_MSCOCTRL_ORDER422_M_C_YCRYCB (1 << 4)
++#define S3C_MSCOCTRL_ORDER422_M_C_CBYCRY (2 << 4)
++#define S3C_MSCOCTRL_ORDER422_M_C_CRYCBY (3 << 4)
++#define S3C_MSCOCTRL_SEL_DMA_CAM_C_EXTCAM (0 << 3)
++#define S3C_MSCOCTRL_SEL_DMA_CAM_C_MEMORY (1 << 3)
++#define S3C_MSCOCTRL_INFORMAT_M_C_420 (0 << 1)
++#define S3C_MSCOCTRL_INFORMAT_M_C_422 (1 << 1)
++#define S3C_MSCOCTRL_INFORMAT_M_C_422_INT (2 << 1)
++#define S3C_MSCOCTRL_INFORMAT_M_C_RGB (3 << 1)
++#define S3C_MSCOCTRL_ENVID_M_C_SET (1 << 0)
++#define S3C_MSPRCTRL_BC_SEL_FIELD (0 << 10)
++#define S3C_MSPRCTRL_BC_SEL_FRAME (1 << 10)
++#define S3C_MSPRCTRL_BUFFER_INI_0 (0 << 8)
++#define S3C_MSPRCTRL_BUFFER_INI_1 (1 << 8)
++#define S3C_MSPRCTRL_TRG_MODE_SOFT (0 << 7)
++#define S3C_MSPRCTRL_TRG_MODE_HARD (1 << 7)
++#define S3C_MSPRCTRL_ORDER422_M_P_YCBYCR (0 << 4)
++#define S3C_MSPRCTRL_ORDER422_M_P_YCRYCB (1 << 4)
++#define S3C_MSPRCTRL_ORDER422_M_P_CBYCRY (2 << 4)
++#define S3C_MSPRCTRL_ORDER422_M_P_CRYCBY (3 << 4)
++#define S3C_MSPRCTRL_SEL_DMA_CAM_P_EXTCAM (0 << 3)
++#define S3C_MSPRCTRL_SEL_DMA_CAM_P_MEMORY (1 << 3)
++#define S3C_MSPRCTRL_INFORMAT_M_P_420 (0 << 1)
++#define S3C_MSPRCTRL_INFORMAT_M_P_422 (1 << 1)
++#define S3C_MSPRCTRL_INFORMAT_M_P_422_INT (2 << 1)
++#define S3C_MSPRCTRL_INFORMAT_M_P_RGB (3 << 1)
++#define S3C_MSPRCTRL_ENVID_M_P_SET (1 << 0)
++#endif
++
++/*************************************************************************
++ * Register part
++ ************************************************************************/
++#define S3C_CICOYSA(__x) S3C_CAMIFREG(0x18 + (__x) * 4)
++#define S3C_CICOCBSA(__x) S3C_CAMIFREG(0x28 + (__x) * 4)
++#define S3C_CICOCRSA(__x) S3C_CAMIFREG(0x38 + (__x) * 4)
++#define S3C_CIPRCLRSA(__x) S3C_CAMIFREG(0x6C + (__x) * 4)
++#define S3C_CIPRYSA(__x) S3C_CAMIFREG(0x6C + (__x) * 4)
++#define S3C_CIPRCBSA(__x) S3C_CAMIFREG(0x7C + (__x) * 4)
++#define S3C_CIPRCRSA(__x) S3C_CAMIFREG(0x8C + (__x) * 4)
++
++#define S3C_CISRCFMT S3C_CAMIFREG(0x00)
++#define S3C_CIWDOFST S3C_CAMIFREG(0x04)
++#define S3C_CIGCTRL S3C_CAMIFREG(0x08)
++#define S3C_CIDOWSFT2 S3C_CAMIFREG(0x14)
++#define S3C_CICOYSA1 S3C_CAMIFREG(0x18)
++#define S3C_CICOYSA2 S3C_CAMIFREG(0x1C)
++#define S3C_CICOYSA3 S3C_CAMIFREG(0x20)
++#define S3C_CICOYSA4 S3C_CAMIFREG(0x24)
++#define S3C_CICOCBSA1 S3C_CAMIFREG(0x28)
++#define S3C_CICOCBSA2 S3C_CAMIFREG(0x2C)
++#define S3C_CICOCBSA3 S3C_CAMIFREG(0x30)
++#define S3C_CICOCBSA4 S3C_CAMIFREG(0x34)
++#define S3C_CICOCRSA1 S3C_CAMIFREG(0x38)
++#define S3C_CICOCRSA2 S3C_CAMIFREG(0x3C)
++#define S3C_CICOCRSA3 S3C_CAMIFREG(0x40)
++#define S3C_CICOCRSA4 S3C_CAMIFREG(0x44)
++#define S3C_CICOTRGFMT S3C_CAMIFREG(0x48) /* CODEC target format */
++#define S3C_CICOCTRL S3C_CAMIFREG(0x4C) /* CODEC DMA control register */
++#define S3C_CICOSCPRERATIO S3C_CAMIFREG(0x50) /* CODEC pre-scaler control register 1 */
++#define S3C_CICOSCPREDST S3C_CAMIFREG(0x54) /* CODEC pre-scaler control register 2 */
++#define S3C_CICOSCCTRL S3C_CAMIFREG(0x58) /* CODEC main-scaler control */
++#define S3C_CICOTAREA S3C_CAMIFREG(0x5C) /* CODEC DMA target area register */
++#define S3C_CICOSTATUS S3C_CAMIFREG(0x64) /* CODEC status register */
++
++#if defined (CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
++#define S3C_CIPRCLRSA1 S3C_CAMIFREG(0x6C) /* RGB 1st frame start address for preview DMA */
++#define S3C_CIPRCLRSA2 S3C_CAMIFREG(0x70) /* RGB 2nd frame start address for preview DMA */
++#define S3C_CIPRCLRSA3 S3C_CAMIFREG(0x74) /* RGB 3rd frame start address for preview DMA */
++#define S3C_CIPRCLRSA4 S3C_CAMIFREG(0x78) /* RGB 4th frame start address for preview DMA */
++#define S3C_CIPRTRGFMT S3C_CAMIFREG(0x7C) /* PREVIEW target format register */
++#define S3C_CIPRCTRL S3C_CAMIFREG(0x80) /* PREVIEW DMA control register */
++#define S3C_CIPRSCPRERATIO S3C_CAMIFREG(0x84) /* PREVIEW pre-scaler control register 1 */
++#define S3C_CIPRSCPREDST S3C_CAMIFREG(0x88) /* PREVIEW pre-scaler control register 2 */
++#define S3C_CIPRSCCTRL S3C_CAMIFREG(0x8C) /* PREVIEW main-scaler control register */
++#define S3C_CIPRTAREA S3C_CAMIFREG(0x90) /* PREVIEW DMA target area register */
++#define S3C_CIPRSTATUS S3C_CAMIFREG(0x98) /* PREVIEW status register */
++#define S3C_CIIMGCPT S3C_CAMIFREG(0xA0) /* image capture enable register */
++#define S3C_CICOCPTSEQ S3C_CAMIFREG(0xA4) /* CODEC capture sequence register */
++#define S3C_CICOSCOS S3C_CAMIFREG(0xA8) /* CODEC scan line offset register */
++#define S3C_CIIMGEFF S3C_CAMIFREG(0xB0) /* image effect register */
++#define S3C_CIMSYSA S3C_CAMIFREG(0xB4) /* MSDMA Y start address register */
++#define S3C_CIMSCBSA S3C_CAMIFREG(0xB8) /* MSDMA CB start address register */
++#define S3C_CIMSCRSA S3C_CAMIFREG(0xBC) /* MSDMA CR start address register */
++#define S3C_CIMSYEND S3C_CAMIFREG(0xC0) /* MSDMA Y end address register */
++#define S3C_CIMSCBEND S3C_CAMIFREG(0xC4) /* MSDMA CB end address register */
++#define S3C_CIMSCREND S3C_CAMIFREG(0xC8) /* MSDMA CR end address register */
++#define S3C_CIMSYOFF S3C_CAMIFREG(0xCC) /* MSDMA Y offset register */
++#define S3C_CIMSCBOFF S3C_CAMIFREG(0xD0) /* MSDMA CB offset register */
++#define S3C_CIMSCROFF S3C_CAMIFREG(0xD4) /* MSDMA CR offset register */
++#define S3C_CIMSWIDTH S3C_CAMIFREG(0xD8) /* MSDMA source image width register */
++#define S3C_CIMSCTRL S3C_CAMIFREG(0xDC) /* MSDMA control register */
++
++#elif defined CONFIG_CPU_S3C6400 || defined CONFIG_CPU_S3C6410
++#define S3C_CIPRYSA1 S3C_CAMIFREG(0x6C) /* 1st frame start address for preview DMA */
++#define S3C_CIPRYSA2 S3C_CAMIFREG(0x70) /* 2nd frame start address for preview DMA */
++#define S3C_CIPRYSA3 S3C_CAMIFREG(0x74) /* 3rd frame start address for preview DMA */
++#define S3C_CIPRYSA4 S3C_CAMIFREG(0x78) /* 4th frame start address for preview DMA */
++#define S3C_CIPRCBSA1 S3C_CAMIFREG(0x7C) /* 1st frame start address for preview DMA */
++#define S3C_CIPRCBSA2 S3C_CAMIFREG(0x80) /* 2nd frame start address for preview DMA */
++#define S3C_CIPRCBSA3 S3C_CAMIFREG(0x84) /* 3rd frame start address for preview DMA */
++#define S3C_CIPRCBSA4 S3C_CAMIFREG(0x88) /* 4th frame start address for preview DMA */
++#define S3C_CIPRCRSA1 S3C_CAMIFREG(0x8C) /* 1st frame start address for preview DMA */
++#define S3C_CIPRCRSA2 S3C_CAMIFREG(0x90) /* 2nd frame start address for preview DMA */
++#define S3C_CIPRCRSA3 S3C_CAMIFREG(0x94) /* 3rd frame start address for preview DMA */
++#define S3C_CIPRCRSA4 S3C_CAMIFREG(0x98) /* 4th frame start address for preview DMA */
++#define S3C_CIPRTRGFMT S3C_CAMIFREG(0x9C) /* PREVIEW target format register */
++#define S3C_CIPRCTRL S3C_CAMIFREG(0xA0) /* PREVIEW DMA control register */
++#define S3C_CIPRSCPRERATIO S3C_CAMIFREG(0xA4) /* PREVIEW pre-scaler control register 1 */
++#define S3C_CIPRSCPREDST S3C_CAMIFREG(0xA8) /* PREVIEW pre-scaler control register 2 */
++#define S3C_CIPRSCCTRL S3C_CAMIFREG(0xAC) /* PREVIEW main-scaler control register */
++#define S3C_CIPRTAREA S3C_CAMIFREG(0xB0) /* PREVIEW DMA target area register */
++#define S3C_CIPRSTATUS S3C_CAMIFREG(0xB8) /* PREVIEW status register */
++#define S3C_CIIMGCPT S3C_CAMIFREG(0xC0) /* image capture enable register */
++#define S3C_CICOCPTSEQ S3C_CAMIFREG(0xC4) /* CODEC capture sequence register */
++#define S3C_CIIMGEFF S3C_CAMIFREG(0xD0) /* image effect register */
++#define S3C_MSCOY0SA S3C_CAMIFREG(0xD4) /* MSDMA for CODEC Y start address register */
++#define S3C_MSCOCB0SA S3C_CAMIFREG(0xD8) /* MSDMA for CODEC CB start address register */
++#define S3C_MSCOCR0SA S3C_CAMIFREG(0xDC) /* MSDMA for CODEC CR start address register */
++#define S3C_MSCOY0END S3C_CAMIFREG(0xE0) /* MSDMA for CODEC Y end address register */
++#define S3C_MSCOCB0END S3C_CAMIFREG(0xE4) /* MSDMA for CODEC CB end address register */
++#define S3C_MSCOCR0END S3C_CAMIFREG(0xE8) /* MSDMA for CODEC CR end address register */
++#define S3C_MSCOYOFF S3C_CAMIFREG(0xEC) /* MSDMA for CODEC Y offset register */
++#define S3C_MSCOCBOFF S3C_CAMIFREG(0xF0) /* MSDMA for CODEC CB offset register */
++#define S3C_MSCOCROFF S3C_CAMIFREG(0xF4) /* MSDMA for CODEC CR offset register */
++#define S3C_MSCOWIDTH S3C_CAMIFREG(0xF8) /* MSDMA for CODEC source image width register */
++#define S3C_MSCOCTRL S3C_CAMIFREG(0xFC) /* MSDMA for CODEC control register */
++#define S3C_MSPRY0SA S3C_CAMIFREG(0x100) /* MSDMA for PREVIEW Y0 start address register */
++#define S3C_MSPRCB0SA S3C_CAMIFREG(0x104) /* MSDMA for PREVIEW CB0 start address register */
++#define S3C_MSPRCR0SA S3C_CAMIFREG(0x108) /* MSDMA for PREVIEW CR0 start address register */
++#define S3C_MSPRY0END S3C_CAMIFREG(0x10C) /* MSDMA for PREVIEW Y0 end address register */
++#define S3C_MSPRCB0END S3C_CAMIFREG(0x110) /* MSDMA for PREVIEW CB0 end address register */
++#define S3C_MSPRCR0END S3C_CAMIFREG(0x114) /* MSDMA for PREVIEW CR0 end address register */
++#define S3C_MSPRYOFF S3C_CAMIFREG(0x118) /* MSDMA for PREVIEW Y offset register */
++#define S3C_MSPRCBOFF S3C_CAMIFREG(0x11C) /* MSDMA for PREVIEW CB offset register */
++#define S3C_MSPRCROFF S3C_CAMIFREG(0x120) /* MSDMA for PREVIEW CR offset register */
++#define S3C_MSPRWIDTH S3C_CAMIFREG(0x124) /* MSDMA for PREVIEW source image width register */
++#define S3C_CIMSCTRL S3C_CAMIFREG(0x128) /* MSDMA for PREVIEW control register */
++#define S3C_CICOSCOSY S3C_CAMIFREG(0x12C) /* CODEC scan line Y offset register */
++#define S3C_CICOSCOSCB S3C_CAMIFREG(0x130) /* CODEC scan line CB offset register */
++#define S3C_CICOSCOSCR S3C_CAMIFREG(0x134) /* CODEC scan line CR offset register */
++#define S3C_CIPRSCOSY S3C_CAMIFREG(0x138) /* PREVIEW scan line Y offset register */
++#define S3C_CIPRSCOSCB S3C_CAMIFREG(0x13C) /* PREVIEW scan line CB offset register */
++#define S3C_CIPRSCOSCR S3C_CAMIFREG(0x140) /* PREVIEW scan line CR offset register */
++#endif
++
++#endif /* ___ASM_ARCH_REGS_CAMIF_H */
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
+index e39656b..dbf0cf9 100644
+--- a/include/asm-arm/arch-s3c2410/regs-clock.h
++++ b/include/asm-arm/arch-s3c2410/regs-clock.h
+@@ -11,9 +11,10 @@
+ */
+
+ #ifndef __ASM_ARM_REGS_CLOCK
+-#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
++#define __ASM_ARM_REGS_CLOCK "$Id: regs-clock.h,v 1.1.1.1 2008/02/18 02:22:54 ihlee215 Exp $"
+
+ #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
++#define S3C_CLKREG(x) ((x) + S3C24XX_VA_SYSCON)
+
+ #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
+
+diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
+index b693158..7a27150 100644
+--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
++++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
+@@ -1,5 +1,7 @@
+ /* linux/include/asm-arm/arch-s3c2410/regs-gpio.h
+ *
++ * "$Id: regs-gpio.h,v 1.8 2008/07/30 11:03:03 dasan Exp $"
++ *
+ * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+@@ -12,8 +14,7 @@
+
+
+ #ifndef __ASM_ARCH_REGS_GPIO_H
+-#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
+-
++#define __ASM_ARCH_REGS_GPIO_H
+ #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
+
+ #define S3C2410_GPIO_BANKA (32*0)
+@@ -25,12 +26,16 @@
+ #define S3C2410_GPIO_BANKG (32*6)
+ #define S3C2410_GPIO_BANKH (32*7)
+
++#define S3C2410_GPIO_BANKJ (32*13)
++#define S3C2410_GPIO_BANKL (32*15)
++
+ #ifdef CONFIG_CPU_S3C2400
+ #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
+ #define S3C24XX_MISCCR S3C2400_MISCCR
+ #else
+ #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
+ #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
++#define S3C24XX_MISCCR_SPISEL (1<<31) /* SET SPI on S3C2443 */
+ #endif /* CONFIG_CPU_S3C2400 */
+
+
+@@ -201,6 +206,8 @@
+ #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
+ #define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
+
++#define S3C2450_GPBSEL S3C2410_GPIOREG(0x1C)
++
+ /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
+
+ #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
+@@ -557,6 +564,8 @@
+ #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
+ #define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
+
++#define S3C2450_GPESEL S3C2410_GPIOREG(0x4C)
++
+ #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
+ #define S3C2410_GPE0_INP (0x00 << 0)
+ #define S3C2410_GPE0_OUTP (0x01 << 0)
+@@ -607,6 +616,7 @@
+ #define S3C2410_GPE5_OUTP (0x01 << 10)
+ #define S3C2410_GPE5_SDCLK (0x02 << 10)
+ #define S3C2443_GPE5_SD1_CLK (0x02 << 10)
++#define S3C2450_GPE5_SD0_CLK (0x02 << 10)
+ #define S3C2400_GPE5_EINT5 (0x02 << 10)
+ #define S3C2400_GPE5_TCLK1 (0x03 << 10)
+
+@@ -615,6 +625,7 @@
+ #define S3C2410_GPE6_OUTP (0x01 << 12)
+ #define S3C2410_GPE6_SDCMD (0x02 << 12)
+ #define S3C2443_GPE6_SD1_CMD (0x02 << 12)
++#define S3C2450_GPE6_SD0_CMD (0x02 << 12)
+ #define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
+ #define S3C2400_GPE6_EINT6 (0x02 << 12)
+
+@@ -622,7 +633,8 @@
+ #define S3C2410_GPE7_INP (0x00 << 14)
+ #define S3C2410_GPE7_OUTP (0x01 << 14)
+ #define S3C2410_GPE7_SDDAT0 (0x02 << 14)
+-#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
++#define S3C2443_GPE7_SD1_DAT0 (0x02 << 14)
++#define S3C2450_GPE7_SD0_DAT0 (0x02 << 14)
+ #define S3C2443_GPE7_AC_SDI (0x03 << 14)
+ #define S3C2400_GPE7_EINT7 (0x02 << 14)
+
+@@ -631,6 +643,7 @@
+ #define S3C2410_GPE8_OUTP (0x01 << 16)
+ #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
+ #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
++#define S3C2450_GPE8_SD0_DAT1 (0x02 << 16)
+ #define S3C2443_GPE8_AC_SDO (0x03 << 16)
+ #define S3C2400_GPE8_nXDACK0 (0x02 << 16)
+
+@@ -639,6 +652,7 @@
+ #define S3C2410_GPE9_OUTP (0x01 << 18)
+ #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
+ #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
++#define S3C2450_GPE9_SD0_DAT2 (0x02 << 18)
+ #define S3C2443_GPE9_AC_SYNC (0x03 << 18)
+ #define S3C2400_GPE9_nXDACK1 (0x02 << 18)
+ #define S3C2400_GPE9_nXBACK (0x03 << 18)
+@@ -648,6 +662,7 @@
+ #define S3C2410_GPE10_OUTP (0x01 << 20)
+ #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
+ #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
++#define S3C2450_GPE10_SD0_DAT3 (0x02 << 20)
+ #define S3C2443_GPE10_AC_nRESET (0x03 << 20)
+ #define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
+
+@@ -970,6 +985,115 @@
+ #define S3C2410_GPH10_OUTP (0x01 << 20)
+ #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+
++#define S3C2443_GPH13 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 13)
++#define S3C2443_GPH13_INP (0x00 << 26)
++#define S3C2443_GPH13_OUTP (0x01 << 26)
++#define S3C2443_GPH13_CLKOUT0 (0x02 << 26)
++
++#define S3C2443_GPH14 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 14)
++#define S3C2443_GPH14_INP (0x00 << 28)
++#define S3C2443_GPH14_OUTP (0x01 << 28)
++#define S3C2443_GPH14_CLKOUT1 (0x02 << 28)
++
++
++
++/* Port L consists of14 SPI1/Misc pins
++ *
++ * GPLCON has 2 bits for each of the input pins on port L
++ * 00 = 0 input, 1 output,
++ *
++ * pull up works like all other ports.
++*/
++
++#define S3C2410_GPLCON S3C2410_GPIOREG(0xf0)
++#define S3C2410_GPLDAT S3C2410_GPIOREG(0xf4)
++#define S3C2410_GPLUP S3C2410_GPIOREG(0xf8)
++
++#define S3C2450_GPLSEL S3C2410_GPIOREG(0xfC)
++
++#define S3C2410_GPL0 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 0)
++#define S3C2410_GPL0_INP (0x00 << 0)
++#define S3C2410_GPL0_OUTP (0x01 << 0)
++#define S3C2410_GPL0_SD0_DAT0 (0x02 << 0)
++
++#define S3C2410_GPL1 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 1)
++#define S3C2410_GPL1_INP (0x00 << 2)
++#define S3C2410_GPL1_OUTP (0x01 << 2)
++#define S3C2410_GPL1_SD0_DAT1 (0x02 << 2)
++
++#define S3C2410_GPL2 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 2)
++#define S3C2410_GPL2_INP (0x00 << 4)
++#define S3C2410_GPL2_OUTP (0x01 << 4)
++#define S3C2410_GPL2_SD0_DAT02 (0x02 << 4)
++
++#define S3C2410_GPL3 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 3)
++#define S3C2410_GPL3_INP (0x00 << 6)
++#define S3C2410_GPL3_OUTP (0x01 << 6)
++#define S3C2410_GPL3_SD0_DAT3 (0x02 << 6)
++
++#define S3C2410_GPL4 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 4)
++#define S3C2410_GPL4_INP (0x00 << 8)
++#define S3C2410_GPL4_OUTP (0x01 << 8)
++#define S3C2410_GPL4_SD0_DAT4 (0x02 << 8)
++#define S3C2450_GPL4_I2S1_SCLK (0x03 << 8)
++
++#define S3C2410_GPL5 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 5)
++#define S3C2410_GPL5_INP (0x00 << 10)
++#define S3C2410_GPL5_OUTP (0x01 << 10)
++#define S3C2410_GPL5_SD0_DAT5 (0x02 << 10)
++#define S3C2450_GPL5_I2S1_CDCLK (0x03 << 10)
++
++#define S3C2410_GPL6 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 6)
++#define S3C2410_GPL6_INP (0x00 << 12)
++#define S3C2410_GPL6_OUTP (0x01 << 12)
++#define S3C2410_GPL6_TXD2 (0x02 << 12)
++#define S3C2410_GPL6_SD0_DAT6 (0x03 << 12)
++#define S3C2450_GPL6_I2S1_SDI (0x03 << 12)
++
++#define S3C2410_GPL7 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 7)
++#define S3C2410_GPL7_INP (0x00 << 14)
++#define S3C2410_GPL7_OUTP (0x01 << 14)
++#define S3C2410_GPL7_RXD2 (0x02 << 14)
++#define S3C2410_GPL7_SD0_DAT7 (0x03 << 14)
++#define S3C2450_GPL7_I2S1_SDO (0x03 << 14)
++
++#define S3C2410_GPL8 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 8)
++#define S3C2410_GPL8_INP (0x00 << 16)
++#define S3C2410_GPL8_OUTP (0x01 << 16)
++#define S3C2410_GPL8_SD0_CMD (0x02 << 16)
++
++#define S3C2410_GPL9 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 9)
++#define S3C2410_GPL9_INP (0x00 << 18)
++#define S3C2410_GPL9_OUTP (0x01 << 18)
++#define S3C2410_GPL9_SD0_CLK (0x02 << 18)
++#define S3C2442_GPL9_nSPICS0 (0x03 << 18)
++
++#define S3C2410_GPL10 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 10)
++#define S3C2410_GPL10_INP (0x00 << 20)
++#define S3C2410_GPL10_OUTP (0x01 << 20)
++#define S3C2410_GPL10_SPICLK1 (0x02 << 20)
++
++#define S3C2410_GPL11 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 11)
++#define S3C2410_GPL11_INP (0x00 << 22)
++#define S3C2410_GPL11_OUTP (0x01 << 22)
++#define S3C2410_GPL11_SPIMOSI1 (0x02 << 22)
++
++#define S3C2410_GPL12 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 12)
++#define S3C2410_GPL12_INP (0x00 << 24)
++#define S3C2410_GPL12_OUTP (0x01 << 24)
++#define S3C2410_GPL12_SPIMISO1 (0x02 << 24)
++
++#define S3C2410_GPL13 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 13)
++#define S3C2410_GPL13_INP (0x00 << 26)
++#define S3C2410_GPL13_OUTP (0x01 << 26)
++#define S3C2410_GPL13_SS0 (0x02 << 26)
++
++#define S3C2410_GPL14 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 14)
++#define S3C2410_GPL14_INP (0x00 << 28)
++#define S3C2410_GPL14_OUTP (0x01 << 28)
++#define S3C2410_GPL14_SS1 (0x02 << 28)
++
++
+ /* The S3C2412 and S3C2413 move the GPJ register set to after
+ * GPH, which means all registers after 0x80 are now offset by 0x10
+ * for the 2412/2413 from the 2410/2440/2442
+@@ -1151,5 +1275,1441 @@
+ #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)
+ #define S3C2412_SLPCON_ALL_PULL (0x33333333)
+
++#if defined (CONFIG_PLAT_S3C64XX) || defined (CONFIG_PLAT_S5PC1XX)
++
++/* configure GPIO ports A..G */
++
++#define S3C_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
++
++/* GPIO */
++#define S3C_GPIONO(bank,offset) ((bank) + (offset))
++
++#define S3C_GPIO_BANKA (32*0)
++#define S3C_GPIO_BANKB (32*1)
++#define S3C_GPIO_BANKC (32*2)
++#define S3C_GPIO_BANKD (32*3)
++#define S3C_GPIO_BANKE (32*4)
++#define S3C_GPIO_BANKF (32*5)
++#define S3C_GPIO_BANKG (32*6)
++#define S3C_GPIO_BANKH (32*7)
++#define S3C_GPIO_BANKI (32*8)
++#define S3C_GPIO_BANKJ (32*9)
++#define S3C_GPIO_BANKO (32*10)
++#define S3C_GPIO_BANKP (32*11)
++#define S3C_GPIO_BANKQ (32*12)
++
++#define S3C_GPIO_BANKK (32*13)
++#define S3C_GPIO_BANKL (32*14)
++#define S3C_GPIO_BANKM (32*15)
++#define S3C_GPIO_BANKN (32*16)
++
++#define S3C_GPIO_INPUT (0)
++#define S3C_GPIO_OUTPUT (1)
++#define S3C_GPIO_BASE(pin) ((pin & ~31) >> 5)
++#define S3C_GPIO_OFFSET(pin) (pin & 31)
++
++/* general configuration options */
++
++#define S3C_GPIO_LEAVE (0xFFFFFFFF)
++
++/* GPA : 8 in/out port . UART */
++#define S3C_GPADAT S3C_GPIOREG(0x04)
++#define S3C_GPACON S3C_GPIOREG(0x00)
++#define S3C_GPAPU S3C_GPIOREG(0x08)
++#define S3C_GPASLPCON S3C_GPIOREG(0x0C)
++
++#define S3C_GPA0 S3C_GPIONO(S3C_GPIO_BANKA, 0)
++#define S3C_GPA0_INP (0)
++#define S3C_GPA0_OUTP (1)
++#define S3C_GPA0_UART_RXD0 (2)
++#define S3C_GPA0_EXT_INT_G1_0 (7)
++
++#define S3C_GPA1 S3C_GPIONO(S3C_GPIO_BANKA, 1)
++#define S3C_GPA1_INP (0)
++#define S3C_GPA1_OUTP (1)
++#define S3C_GPA1_UART_TXD0 (2)
++#define S3C_GPA1_EXT_INT_G1_1 (7)
++
++#define S3C_GPA2 S3C_GPIONO(S3C_GPIO_BANKA, 2)
++#define S3C_GPA2_INP (0)
++#define S3C_GPA2_OUTP (1)
++#define S3C_GPA2_UART_CTS0 (2)
++#define S3C_GPA2_ADDR_CF0 (5)
++#define S3C_GPA2_EXT_INT_G1_2 (7)
++
++#define S3C_GPA3 S3C_GPIONO(S3C_GPIO_BANKA, 3)
++#define S3C_GPA3_INP (0)
++#define S3C_GPA3_OUTP (1)
++#define S3C_GPA3_UART_RTS0 (2)
++#define S3C_GPA3_ADDR_CF1 (5)
++#define S3C_GPA3_EXT_INT_G1_3 (7)
++
++#define S3C_GPA4 S3C_GPIONO(S3C_GPIO_BANKA, 4)
++#define S3C_GPA4_INP (0)
++#define S3C_GPA4_OUTP (1)
++#define S3C_GPA4_UART_RXD1 (2)
++#define S3C_GPA4_EXT_INT_G1_4 (7)
++
++#define S3C_GPA5 S3C_GPIONO(S3C_GPIO_BANKA, 5)
++#define S3C_GPA5_INP (0)
++#define S3C_GPA5_OUTP (1)
++#define S3C_GPA5_UART_TXD1 (2)
++#define S3C_GPA5_EXT_INT_G1_5 (7)
++
++#define S3C_GPA6 S3C_GPIONO(S3C_GPIO_BANKA, 6)
++#define S3C_GPA6_INP (0)
++#define S3C_GPA6_OUTP (1)
++#define S3C_GPA6_UART_CTS1 (2)
++#define S3C_GPA6_ADDR_CF0 (5)
++#define S3C_GPA6_EXT_INT_G1_6 (7)
++
++#define S3C_GPA7 S3C_GPIONO(S3C_GPIO_BANKA, 7)
++#define S3C_GPA7_INP (0)
++#define S3C_GPA7_OUTP (1)
++#define S3C_GPA7_UART_RTS1 (2)
++#define S3C_GPA7_ADDR_CF1 (5)
++#define S3C_GPA7_EXT_INT_G1_7 (7)
++
++
++/* GPB : 7 in/out port . UART, IrDA, External DMA, I2C */
++#define S3C_GPBDAT S3C_GPIOREG(0x24)
++#define S3C_GPBCON S3C_GPIOREG(0x20)
++#define S3C_GPBPU S3C_GPIOREG(0x28)
++#define S3C_GPBSLPCON S3C_GPIOREG(0x2C)
++
++#define S3C_GPB0 S3C_GPIONO(S3C_GPIO_BANKB, 0)
++#define S3C_GPB0_INP (0)
++#define S3C_GPB0_OUTP (1)
++#define S3C_GPB0_UART_RXD2 (2)
++#define S3C_GPB0_EXT_DMA_REQ (3)
++#define S3C_GPB0_IRDA_RXD (4)
++#define S3C_GPB0_ADDR_CF0 (5)
++#define S3C_GPB0_RESERVED (6)
++#define S3C_GPB0_EXT_INT_G1_8 (7)
++
++#define S3C_GPB1 S3C_GPIONO(S3C_GPIO_BANKB, 1)
++#define S3C_GPB1_INP (0)
++#define S3C_GPB1_OUTP (1)
++#define S3C_GPB1_UART_TXD2 (2)
++#define S3C_GPB1_EXT_DMA_ACK (3)
++#define S3C_GPB1_IRDA_TXD (4)
++#define S3C_GPB1_ADDR_CF1 (5)
++#define S3C_GPB1_RESERVED (6)
++#define S3C_GPB1_EXT_INT_G1_9 (7)
++
++#define S3C_GPB2 S3C_GPIONO(S3C_GPIO_BANKB, 2)
++#define S3C_GPB2_INP (0)
++#define S3C_GPB2_OUTP (1)
++#define S3C_GPB2_UART_RXD3 (2)
++#define S3C_GPB2_IRDA_RXD (3)
++#define S3C_GPB2_EXT_DMA_REQ (4)
++#define S3C_GPB2_ADDR_CF2 (5)
++#define S3C_GPB2_I2C_SCL1 (6)
++#define S3C_GPB2_EXT_INT_G1_10 (7)
++
++#define S3C_GPB3 S3C_GPIONO(S3C_GPIO_BANKB, 3)
++#define S3C_GPB3_INP (0)
++#define S3C_GPB3_OUTP (1)
++#define S3C_GPB3_UART_TXD3 (2)
++#define S3C_GPB3_IRDA_RXD (3)
++#define S3C_GPB3_EXT_DMA_ACK (4)
++#define S3C_GPB3_RESERVED1 (5)
++#define S3C_GPB3_I2C_SDA1 (6)
++#define S3C_GPB3_EXT_INT_G1_11 (7)
++
++#define S3C_GPB4 S3C_GPIONO(S3C_GPIO_BANKB, 4)
++#define S3C_GPB4_INP (0)
++#define S3C_GPB4_OUTP (1)
++#define S3C_GPB4_IRDA_SDBW (2)
++#define S3C_GPB4_RESERVED1 (3)
++#define S3C_GPB4_CF_DATA_DIR (4)
++#define S3C_GPB4_RESERVED2 (5)
++#define S3C_GPB4_RESERVED3 (6)
++#define S3C_GPB4_EXT_INT_G1_12 (7)
++
++#define S3C_GPB5 S3C_GPIONO(S3C_GPIO_BANKB, 5)
++#define S3C_GPB5_INP (0)
++#define S3C_GPB5_OUTP (1)
++#define S3C_GPB5_I2C_SCL0 (2)
++#define S3C_GPB5_RESERVED1 (3)
++#define S3C_GPB5_RESERVED2 (4)
++#define S3C_GPB5_RESERVED3 (5)
++#define S3C_GPB5_RESERVED4 (6)
++#define S3C_GPB5_EXT_INT_G1_13 (7)
++
++#define S3C_GPB6 S3C_GPIONO(S3C_GPIO_BANKB, 6)
++#define S3C_GPB6_INP (0)
++#define S3C_GPB6_OUTP (1)
++#define S3C_GPB6_I2C_SDA0 (2)
++#define S3C_GPB6_RESERVED1 (3)
++#define S3C_GPB6_RESERVED2 (4)
++#define S3C_GPB6_RESERVED3 (5)
++#define S3C_GPB6_RESERVED (6)
++#define S3C_GPB6_EXT_INT_G1_14 (7)
++
++
++/* GPC : 8 in/out port . SPI */
++#define S3C_GPCDAT S3C_GPIOREG(0x44)
++#define S3C_GPCCON S3C_GPIOREG(0x40)
++#define S3C_GPCPU S3C_GPIOREG(0x48)
++#define S3C_GPCSLPCON S3C_GPIOREG(0x4C)
++
++#define S3C_GPC0 S3C_GPIONO(S3C_GPIO_BANKC, 0)
++#define S3C_GPC0_INP (0)
++#define S3C_GPC0_OUTP (1)
++#define S3C_GPC0_SPI_MISO0 (2)
++#define S3C_GPC0_RESERVED1 (3)
++#define S3C_GPC0_RESERVED2 (4)
++#define S3C_GPC0_ADDR_CF0 (5)
++#define S3C_GBP0_RESERVED3 (6)
++#define S3C_GPC0_EXT_INT_G2_0 (7)
++
++#define S3C_GPC1 S3C_GPIONO(S3C_GPIO_BANKC, 1)
++#define S3C_GPC1_INP (0)
++#define S3C_GPC1_OUTP (1)
++#define S3C_GPC1_SPI_CLK0 (2)
++#define S3C_GPC1_RESERVED1 (3)
++#define S3C_GPC1_RESERVED2 (4)
++#define S3C_GPC1_ADDR_CF1 (5)
++#define S3C_GPC1_RESERVED3 (6)
++#define S3C_GPC1_EXT_INT_G2_1 (7)
++
++#define S3C_GPC2 S3C_GPIONO(S3C_GPIO_BANKC, 2)
++#define S3C_GPC2_INP (0)
++#define S3C_GPC2_OUTP (1)
++#define S3C_GPC2_SPI_MOSI0 (2)
++#define S3C_GPC2_RESERVED1 (3)
++#define S3C_GPC2_RESERVED2 (4)
++#define S3C_GPC2_ADDR_CF2 (5)
++#define S3C_GPC2_RESERVED3 (6)
++#define S3C_GPC2_EXT_INT_G2_2 (7)
++
++#define S3C_GPC3 S3C_GPIONO(S3C_GPIO_BANKC, 3)
++#define S3C_GPC3_INP (0)
++#define S3C_GPC3_OUTP (1)
++#define S3C_GPC3_SPI_CS0 (2)
++#define S3C_GPC3_RESERVED1 (3)
++#define S3C_GPC3_RESERVED2 (4)
++#define S3C_GPC3_RESERVED3 (5)
++#define S3C_GPC3_RESERVED4 (6)
++#define S3C_GPC3_EXT_INT_G2_3 (7)
++
++#define S3C_GPC4 S3C_GPIONO(S3C_GPIO_BANKC, 4)
++#define S3C_GPC4_INP (0)
++#define S3C_GPC4_OUTP (1)
++#define S3C_GPC4_SPI_MISO1 (2)
++#define S3C_GPC4_MMC_CMD2 (3)
++#define S3C_GPC4_RESERVED1 (4)
++#define S3C_GPC4_I2S_V40_DO0 (5)
++#define S3C_GPC4_RESERVED3 (6)
++#define S3C_GPC4_EXT_INT_G2_4 (7)
++
++#define S3C_GPC5 S3C_GPIONO(S3C_GPIO_BANKC, 5)
++#define S3C_GPC5_INP (0)
++#define S3C_GPC5_OUTP (1)
++#define S3C_GPC5_SPI_CLK1 (2)
++#define S3C_GPC5_MMC_CLK2 (3)
++#define S3C_GPC5_RESERVED2 (4)
++#define S3C_GPC5_I2S_V40_DO1 (5)
++#define S3C_GPC5_RESERVED4 (6)
++#define S3C_GPC5_EXT_INT_G2_5 (7)
++
++#define S3C_GPC6 S3C_GPIONO(S3C_GPIO_BANKC, 6)
++#define S3C_GPC6_INP (0)
++#define S3C_GPC6_OUTP (1)
++#define S3C_GPC6_SPI_MOSI1 (2)
++#define S3C_GPC6_RESERVED1 (3)
++#define S3C_GPC6_RESERVED2 (4)
++#define S3C_GPC6_RESERVED3 (5)
++#define S3C_GPC6_RESERVED4 (6)
++#define S3C_GPC6_EXT_INT_G2_6 (7)
++
++#define S3C_GPC7 S3C_GPIONO(S3C_GPIO_BANKC, 7)
++#define S3C_GPC7_INP (0)
++#define S3C_GPC7_OUTP (1)
++#define S3C_GPC7_SPI_CS1 (2)
++#define S3C_GPC7_RESERVED1 (3)
++#define S3C_GPC7_RESERVED2 (4)
++#define S3C_GPC7_I2S_V40_DO2 (5)
++#define S3C_GPC7_RESERVED4 (6)
++#define S3C_GPC7_EXT_INT_G2_7 (7)
++
++
++/* GPD : 5 in/out port . PCM, I2S, AC97 */
++#define S3C_GPDDAT S3C_GPIOREG(0x64)
++#define S3C_GPDCON S3C_GPIOREG(0x60)
++#define S3C_GPDPU S3C_GPIOREG(0x68)
++#define S3C_GPDSLPCON S3C_GPIOREG(0x6C)
++
++#define S3C_GPD0 S3C_GPIONO(S3C_GPIO_BANKD, 0)
++#define S3C_GPD0_INP (0)
++#define S3C_GPD0_OUTP (1)
++#define S3C_GPD0_PCM_DCLK0 (2)
++#define S3C_GPD0_I2S_CLK0 (3)
++#define S3C_GPD0_AC97_BITCLK (4)
++#define S3C_GPD0_ADDR_CF0 (5)
++#define S3C_GBP0_RESERVED1 (6)
++#define S3C_GPD0_EXT_INT_G3_0 (7)
++
++#define S3C_GPD1 S3C_GPIONO(S3C_GPIO_BANKD, 1)
++#define S3C_GPD1_INP (0)
++#define S3C_GPD1_OUTP (1)
++#define S3C_GPD1_PCM_EXTCLK0 (2)
++#define S3C_GPD1_I2S_CDCLK0 (3)
++#define S3C_GPD1_AC97_RESET (4)
++#define S3C_GPD1_ADDR_CF1 (5)
++#define S3C_GPD1_RESERVED1 (6)
++#define S3C_GPD1_EXT_INT_G3_1 (7)
++
++#define S3C_GPD2 S3C_GPIONO(S3C_GPIO_BANKD, 2)
++#define S3C_GPD2_INP (0)
++#define S3C_GPD2_OUTP (1)
++#define S3C_GPD2_PCM_FSYNC0 (2)
++#define S3C_GPD2_I2S_LRCLK0 (3)
++#define S3C_GPD2_AC97_SYNC (4)
++#define S3C_GPD2_ADDR_CF2 (5)
++#define S3C_GPD2_RESERVED1 (6)
++#define S3C_GPD2_EXT_INT_G3_2 (7)
++
++#define S3C_GPD3 S3C_GPIONO(S3C_GPIO_BANKD, 3)
++#define S3C_GPD3_INP (0)
++#define S3C_GPD3_OUTP (1)
++#define S3C_GPD3_PCM_SIN0 (2)
++#define S3C_GPD3_I2S_DI0 (3)
++#define S3C_GPD3_AC97_SDI (4)
++#define S3C_GPD3_RESERVED1 (5)
++#define S3C_GPD3_RESERVED2 (6)
++#define S3C_GPD3_EXT_INT_G3_3 (7)
++
++#define S3C_GPD4 S3C_GPIONO(S3C_GPIO_BANKD, 4)
++#define S3C_GPD4_INP (0)
++#define S3C_GPD4_OUTP (1)
++#define S3C_GPD4_PCM_SOUT0 (2)
++#define S3C_GPD4_I2S_DO0 (3)
++#define S3C_GPD4_AC97_SDO (4)
++#define S3C_GPD4_RESERVED1 (5)
++#define S3C_GPD4_RESERVED2 (6)
++#define S3C_GPD4_EXT_INT_G3_4 (7)
++
++
++/* GPE : 5 in/out port . PCM, I2S, AC97 */
++#define S3C_GPEDAT S3C_GPIOREG(0x84)
++#define S3C_GPECON S3C_GPIOREG(0x80)
++#define S3C_GPEPU S3C_GPIOREG(0x88)
++#define S3C_GPESLPCON S3C_GPIOREG(0x8C)
++
++#define S3C_GPE0 S3C_GPIONO(S3C_GPIO_BANKE, 0)
++#define S3C_GPE0_INP (0)
++#define S3C_GPE0_OUTP (1)
++#define S3C_GPE0_PCM_DCLK1 (2)
++#define S3C_GPE0_I2S_CLK1 (3)
++#define S3C_GPE0_AC97_BITCLK (4)
++#define S3C_GPE0_RESERVED1 (5)
++#define S3C_GPE0_RESERVED2 (6)
++#define S3C_GPE0_EXT_INT_G3_5 (7)
++
++#define S3C_GPE1 S3C_GPIONO(S3C_GPIO_BANKE, 1)
++#define S3C_GPE1_INP (0)
++#define S3C_GPE1_OUTP (1)
++#define S3C_GPE1_PCM_EXTCLK1 (2)
++#define S3C_GPE1_I2S_CDCLK1 (3)
++#define S3C_GPE1_AC97_RESET (4)
++#define S3C_GPE1_RESERVED1 (5)
++#define S3C_GPE1_RESERVED2 (6)
++#define S3C_GPE1_EXT_INT_G3_6 (7)
++
++#define S3C_GPE2 S3C_GPIONO(S3C_GPIO_BANKE, 2)
++#define S3C_GPE2_INP (0)
++#define S3C_GPE2_OUTP (1)
++#define S3C_GPE2_PCM_FSYNC1 (2)
++#define S3C_GPE2_I2S_LRCLK1 (3)
++#define S3C_GPE2_AC97_SYNC (4)
++#define S3C_GPE2_RESERVED1 (5)
++#define S3C_GPE2_RESERVED2 (6)
++#define S3C_GPE2_EXT_INT_G3_7 (7)
++
++#define S3C_GPE3 S3C_GPIONO(S3C_GPIO_BANKE, 3)
++#define S3C_GPE3_INP (0)
++#define S3C_GPE3_OUTP (1)
++#define S3C_GPE3_PCM_SIN1 (2)
++#define S3C_GPE3_I2S_DI1 (3)
++#define S3C_GPE3_AC97_SDI (4)
++#define S3C_GPE3_RESERVED1 (5)
++#define S3C_GPE3_RESERVED2 (6)
++#define S3C_GPE3_EXT_INT_G3_8 (7)
++
++#define S3C_GPE4 S3C_GPIONO(S3C_GPIO_BANKE, 4)
++#define S3C_GPE4_INP (0)
++#define S3C_GPE4_OUTP (1)
++#define S3C_GPE4_PCM_SOUT1 (2)
++#define S3C_GPE4_I2S_DO1 (3)
++#define S3C_GPE4_AC97_SDO (4)
++#define S3C_GPE4_RESERVED1 (5)
++#define S3C_GPE4_RESERVED2 (6)
++#define S3C_GPE4_EXT_INT_G3_9 (7)
++
++#define S3C_GPE11 S3C_GPIONO(S3C_GPIO_BANKE, 11)
++#define S3C_GPE11_INP (0)
++#define S3C_GPE11_OUTP (1)
++#define S3C_GPE11_SPI_MISO0 (2)
++#define S3C_GPE11_I2S_DO1 (3)
++#define S3C_GPE11_AC97_SDO (4)
++#define S3C_GPE11_RESERVED1 (5)
++#define S3C_GPE11_RESERVED2 (6)
++#define S3C_GPE11_EXT_INT_G3_9 (7)
++
++#define S3C_GPE12 S3C_GPIONO(S3C_GPIO_BANKE, 12)
++#define S3C_GPE12_INP (0)
++#define S3C_GPE12_OUTP (1)
++#define S3C_GPE12_SPI_MOSI0 (2)
++#define S3C_GPE12_I2S_DO1 (3)
++#define S3C_GPE12_AC97_SDO (4)
++#define S3C_GPE12_RESERVED1 (5)
++#define S3C_GPE12_RESERVED2 (6)
++#define S3C_GPE12_EXT_INT_G3_9 (7)
++
++#define S3C_GPE13 S3C_GPIONO(S3C_GPIO_BANKE, 13)
++#define S3C_GPE13_INP (0)
++#define S3C_GPE13_OUTP (1)
++#define S3C_GPE13_SPI_CLK0 (2)
++#define S3C_GPE13_I2S_DO1 (3)
++#define S3C_GPE13_AC97_SDO (4)
++#define S3C_GPE13_RESERVED1 (5)
++#define S3C_GPE13_RESERVED2 (6)
++#define S3C_GPE13_EXT_INT_G3_9 (7)
++
++
++/* GPF : 16 in/out port . Camera I/F, PWM, Clock Out */
++#define S3C_GPFDAT S3C_GPIOREG(0xA4)
++#define S3C_GPFCON S3C_GPIOREG(0xA0)
++#define S3C_GPFPU S3C_GPIOREG(0xA8)
++#define S3C_GPFSLPCON S3C_GPIOREG(0xAC)
++
++#define S3C_GPF0 S3C_GPIONO(S3C_GPIO_BANKF, 0)
++#define S3C_GPF0_INP (0)
++#define S3C_GPF0_OUTP (1)
++#define S3C_GPF0_CAMIF_CLK (2)
++#define S3C_GPF0_EXT_INT_G4_0 (3)
++
++#define S3C_GPF1 S3C_GPIONO(S3C_GPIO_BANKF, 1)
++#define S3C_GPF1_INP (0)
++#define S3C_GPF1_OUTP (1)
++#define S3C_GPF1_CAMIF_HREF (2)
++#define S3C_GPF1_EXT_INT_G4_1 (3)
++
++#define S3C_GPF2 S3C_GPIONO(S3C_GPIO_BANKF, 2)
++#define S3C_GPF2_INP (0)
++#define S3C_GPF2_OUTP (1)
++#define S3C_GPF2_CAMIF_CLK (2)
++#define S3C_GPF2_EXT_INT_G4_2 (3)
++
++#define S3C_GPF3 S3C_GPIONO(S3C_GPIO_BANKF, 3)
++#define S3C_GPF3_INP (0)
++#define S3C_GPF3_OUTP (1)
++#define S3C_GPF3_CAMIF_RST (2)
++#define S3C_GPF3_EXT_INT_G4_3 (3)
++
++#define S3C_GPF4 S3C_GPIONO(S3C_GPIO_BANKF, 4)
++#define S3C_GPF4_INP (0)
++#define S3C_GPF4_OUTP (1)
++#define S3C_GPF4_CAMIF_VSYNC (2)
++#define S3C_GPF4_EXT_INT_G4_4 (3)
++
++#define S3C_GPF5 S3C_GPIONO(S3C_GPIO_BANKF, 5)
++#define S3C_GPF5_INP (0)
++#define S3C_GPF5_OUTP (1)
++#define S3C_GPF5_CAMIF_YDATA0 (2)
++#define S3C_GPF5_EXT_INT_G4_5 (3)
++
++#define S3C_GPF6 S3C_GPIONO(S3C_GPIO_BANKF, 6)
++#define S3C_GPF6_INP (0)
++#define S3C_GPF6_OUTP (1)
++#define S3C_GPF6_CAMIF_YDATA1 (2)
++#define S3C_GPF6_EXT_INT_G4_6 (3)
++
++#define S3C_GPF7 S3C_GPIONO(S3C_GPIO_BANKF, 7)
++#define S3C_GPF7_INP (0)
++#define S3C_GPF7_OUTP (1)
++#define S3C_GPF7_CAMIF_YDATA2 (2)
++#define S3C_GPF7_EXT_INT_G4_7 (3)
++
++#define S3C_GPF8 S3C_GPIONO(S3C_GPIO_BANKF, 8)
++#define S3C_GPF8_INP (0)
++#define S3C_GPF8_OUTP (1)
++#define S3C_GPF8_CAMIF_YDATA03 (2)
++#define S3C_GPF8_EXT_INT_G4_8 (3)
++
++#define S3C_GPF9 S3C_GPIONO(S3C_GPIO_BANKF, 9)
++#define S3C_GPF9_INP (0)
++#define S3C_GPF9_OUTP (1)
++#define S3C_GPF9_CAMIF_YDATA4 (2)
++#define S3C_GPF9_EXT_INT_G4_9 (3)
++
++#define S3C_GPF10 S3C_GPIONO(S3C_GPIO_BANKF, 10)
++#define S3C_GPF10_INP (0)
++#define S3C_GPF10_OUTP (1)
++#define S3C_GPF10_CAMIF_YDATA5 (2)
++#define S3C_GPF10_EXT_INT_G4_10 (3)
++
++#define S3C_GPF11 S3C_GPIONO(S3C_GPIO_BANKF, 11)
++#define S3C_GPF11_INP (0)
++#define S3C_GPF11_OUTP (1)
++#define S3C_GPF11_CAMIF_YDATA06 (2)
++#define S3C_GPF11_EXT_INT_G4_11 (3)
++
++#define S3C_GPF12 S3C_GPIONO(S3C_GPIO_BANKF, 12)
++#define S3C_GPF12_INP (0)
++#define S3C_GPF12_OUTP (1)
++#define S3C_GPF12_CAMIF_YDATA7 (2)
++#define S3C_GPF12_EXT_INT_G4_12 (3)
++
++#define S3C_GPF13 S3C_GPIONO(S3C_GPIO_BANKF, 13)
++#define S3C_GPF13_INP (0)
++#define S3C_GPF13_OUTP (1)
++#define S3C_GPF13_PWM_ECLK (2)
++#define S3C_GPF13_EXT_INT_G4_13 (3)
++
++#define S3C_GPF14 S3C_GPIONO(S3C_GPIO_BANKF, 14)
++#define S3C_GPF14_INP (0)
++#define S3C_GPF14_OUTP (1)
++#define S3C_GPF14_PWM_TOUT0 (2)
++#define S3C_GPF14_CLKOUT0 (3)
++
++#define S3C_GPF15 S3C_GPIONO(S3C_GPIO_BANKF, 15)
++#define S3C_GPF15_INP (0)
++#define S3C_GPF15_OUTP (1)
++#define S3C_GPF15_PWM_TOUT1 (2)
++#define S3C_GPF15_RESERVED (3)
++
++
++/* GPG : 7 in/out port . MMC channel 0 */
++#define S3C_GPGDAT S3C_GPIOREG(0xC4)
++#define S3C_GPGCON S3C_GPIOREG(0xC0)
++#define S3C_GPGPU S3C_GPIOREG(0xC8)
++#define S3C_GPGSLPCON S3C_GPIOREG(0xCC)
++
++#define S3C_GPG0 S3C_GPIONO(S3C_GPIO_BANKG, 0)
++#define S3C_GPG0_INP (0)
++#define S3C_GPG0_OUTP (1)
++#define S3C_GPG0_MMC_CLK0 (2)
++#define S3C_GPG0_RESERVED1 (3)
++#define S3C_GPG0_RESERVED2 (4)
++#define S3C_GPG0_ADDR_CF0 (5)
++#define S3C_GPG0_RESERVED3 (6)
++#define S3C_GPG0_EXT_INT_G5_1 (7)
++
++#define S3C_GPG1 S3C_GPIONO(S3C_GPIO_BANKG, 1)
++#define S3C_GPG1_INP (0)
++#define S3C_GPG1_OUTP (1)
++#define S3C_GPG1_MMC_CMD0 (2)
++#define S3C_GPG1_EXT_DMA_ACK (3)
++#define S3C_GPG1_RESERVED1 (4)
++#define S3C_GPG1_ADDR_CF1 (5)
++#define S3C_GPG1_RESERVED2 (6)
++#define S3C_GPG1_EXT_INT_G5_2 (7)
++
++#define S3C_GPG2 S3C_GPIONO(S3C_GPIO_BANKG, 2)
++#define S3C_GPG2_INP (0)
++#define S3C_GPG2_OUTP (1)
++#define S3C_GPG2_MMC_DATA0_0 (2)
++#define S3C_GPG2_RESERVED1 (3)
++#define S3C_GPG2_RESERVED2 (4)
++#define S3C_GPG2_RESERVED3 (5)
++#define S3C_GPG2_RESERVED4 (6)
++#define S3C_GPG2_EXT_INT_G5_3 (7)
++
++#define S3C_GPG3 S3C_GPIONO(S3C_GPIO_BANKG, 3)
++#define S3C_GPG3_INP (0)
++#define S3C_GPG3_OUTP (1)
++#define S3C_GPG3_MMC_DATA0_1 (2)
++#define S3C_GPG3_RESERVED1 (3)
++#define S3C_GPG3_RESERVED2 (4)
++#define S3C_GPG3_RESERVED3 (5)
++#define S3C_GPG3_RESERVED4 (6)
++#define S3C_GPG3_EXT_INT_G5_4 (7)
++
++#define S3C_GPG4 S3C_GPIONO(S3C_GPIO_BANKG, 4)
++#define S3C_GPG4_INP (0)
++#define S3C_GPG4_OUTP (1)
++#define S3C_GPG4_MMC_DATA0_2 (2)
++#define S3C_GPG4_RESERVED1 (3)
++#define S3C_GPG4_RESERVED2 (4)
++#define S3C_GPG4_RESERVED3 (5)
++#define S3C_GPG4_RESERVED4 (6)
++#define S3C_GPG4_EXT_INT_G5_5 (7)
++
++#define S3C_GPG5 S3C_GPIONO(S3C_GPIO_BANKG, 5)
++#define S3C_GPG5_INP (0)
++#define S3C_GPG5_OUTP (1)
++#define S3C_GPG5_MMC_DATA0_3 (2)
++#define S3C_GPG5_RESERVED1 (3)
++#define S3C_GPG5_RESERVED2 (4)
++#define S3C_GPG5_RESERVED3 (5)
++#define S3C_GPG5_RESERVED4 (6)
++#define S3C_GPG5_EXT_INT_G5_6 (7)
++
++#define S3C_GPG6 S3C_GPIONO(S3C_GPIO_BANKG, 6)
++#define S3C_GPG6_INP (0)
++#define S3C_GPG6_OUTP (1)
++#define S3C_GPG6_MMC_CD0 (2)
++#define S3C_GPG6_MMC_CD1 (3)
++#define S3C_GPG6_RESERVED2 (4)
++#define S3C_GPG6_RESERVED3 (5)
++#define S3C_GPG6_RESERVED4 (6)
++#define S3C_GPG6_EXT_INT_G5_7 (7)
++
++
++/*GPH : 10 in/out port . MMC channel 1 */
++/* Notice!!! Watch out GPIO data register address*/
++#define S3C_GPHDAT S3C_GPIOREG(0xE8)
++#define S3C_GPH0CON S3C_GPIOREG(0xE0)
++#define S3C_GPH1CON S3C_GPIOREG(0xE4)
++#define S3C_GPHPU S3C_GPIOREG(0xEC)
++#define S3C_GPHSLPCON S3C_GPIOREG(0xF0)
++
++#define S3C_GPH0 S3C_GPIONO(S3C_GPIO_BANKH, 0)
++#define S3C_GPH0_INP (0)
++#define S3C_GPH0_OUTP (1)
++#define S3C_GPH0_MMC_CLK1 (2)
++#define S3C_GPH0_RESERVED1 (3)
++#define S3C_GPH0_KEYPAD_COL0 (4)
++#define S3C_GPH0_ADDR_CF0 (5)
++#define S3C_GPH0_RESERVED2 (6)
++#define S3C_GPH0_EXT_INT_G6_0 (7)
++
++#define S3C_GPH1 S3C_GPIONO(S3C_GPIO_BANKH, 1)
++#define S3C_GPH1_INP (0)
++#define S3C_GPH1_OUTP (1)
++#define S3C_GPH1_MMC_CMD1 (2)
++#define S3C_GPH1_RESERVED1 (3)
++#define S3C_GPH1_KEYPAD_COL1 (4)
++#define S3C_GPH1_ADDR_CF1 (5)
++#define S3C_GPH1_RESERVED2 (6)
++#define S3C_GPH1_EXT_INT_G6_1 (7)
++
++#define S3C_GPH2 S3C_GPIONO(S3C_GPIO_BANKH, 2)
++#define S3C_GPH2_INP (0)
++#define S3C_GPH2_OUTP (1)
++#define S3C_GPH2_MMC_DATA1_0 (2)
++#define S3C_GPH2_RESERVED1 (3)
++#define S3C_GPH2_KEYPAD_COL2 (4)
++#define S3C_GPH2_RESERVED3 (5)
++#define S3C_GPH2_RESERVED4 (6)
++#define S3C_GPH2_EXT_INT_G6_2 (7)
++
++#define S3C_GPH3 S3C_GPIONO(S3C_GPIO_BANKH, 3)
++#define S3C_GPH3_INP (0)
++#define S3C_GPH3_OUTP (1)
++#define S3C_GPH3_MMC_DATA1_1 (2)
++#define S3C_GPH3_RESERVED1 (3)
++#define S3C_GPH3_KEYPAD_COL3 (4)
++#define S3C_GPH3_RESERVED3 (5)
++#define S3C_GPH3_RESERVED4 (6)
++#define S3C_GPH3_EXT_INT_G6_3 (7)
++
++#define S3C_GPH4 S3C_GPIONO(S3C_GPIO_BANKH, 4)
++#define S3C_GPH4_INP (0)
++#define S3C_GPH4_OUTP (1)
++#define S3C_GPH4_MMC_DATA1_2 (2)
++#define S3C_GPH4_RESERVED1 (3)
++#define S3C_GPH4_KEYPAD_COL4 (4)
++#define S3C_GPH4_RESERVED3 (5)
++#define S3C_GPH4_RESERVED4 (6)
++#define S3C_GPH4_EXT_INT_G6_4 (7)
++
++#define S3C_GPH5 S3C_GPIONO(S3C_GPIO_BANKH, 5)
++#define S3C_GPH5_INP (0)
++#define S3C_GPH5_OUTP (1)
++#define S3C_GPH5_MMC_DATA1_3 (2)
++#define S3C_GPH5_RESERVED1 (3)
++#define S3C_GPH5_KEYPAD_COL5 (4)
++#define S3C_GPH5_RESERVED3 (5)
++#define S3C_GPH5_RESERVED4 (6)
++#define S3C_GPH5_EXT_INT_G6_5 (7)
++
++#define S3C_GPH6 S3C_GPIONO(S3C_GPIO_BANKH, 6)
++#define S3C_GPH6_INP (0)
++#define S3C_GPH6_OUTP (1)
++#define S3C_GPH6_MMC_DATA1_4 (2)
++#define S3C_GPH6_MMC_DATA2_0 (3)
++#define S3C_GPH6_KEYPAD_COL6 (4)
++#define S3C_GPH6_I2S_V40_BCLK (5)
++#define S3C_GPH6_ADDR_CF0 (6)
++#define S3C_GPH6_EXT_INT_G6_6 (7)
++
++#define S3C_GPH7 S3C_GPIONO(S3C_GPIO_BANKH, 7)
++#define S3C_GPH7_INP (0)
++#define S3C_GPH7_OUTP (1)
++#define S3C_GPH7_MMC_DATA1_5 (2)
++#define S3C_GPH7_MMC_DATA2_1 (3)
++#define S3C_GPH7_KEYPAD_COL7 (4)
++#define S3C_GPH7_I2S_V40_CDCLK (5)
++#define S3C_GPH7_ADDR_CF1 (6)
++#define S3C_GPH7_EXT_INT_G6_7 (7)
++
++#define S3C_GPH8 S3C_GPIONO(S3C_GPIO_BANKH, 8)
++#define S3C_GPH8_INP (0)
++#define S3C_GPH8_OUTP (1)
++#define S3C_GPH8_MMC_DATA1_6 (2)
++#define S3C_GPH8_MMC_DATA2_2 (3)
++#define S3C_GPH8_RESERVED2 (4)
++#define S3C_GPH8_I2S_V40_LRCLK (5)
++#define S3C_GPH8_ADDR_CF2 (6)
++#define S3C_GPH8_EXT_INT_G6_8 (7)
++
++#define S3C_GPH9 S3C_GPIONO(S3C_GPIO_BANKH, 9)
++#define S3C_GPH9_INP (0)
++#define S3C_GPH9_OUTP (1)
++#define S3C_GPH9_MMC_DATA1_7 (2)
++#define S3C_GPH9_MMC_DATA2_3 (3)
++#define S3C_GPH9_RESERVED2 (4)
++#define S3C_GPH9_I2S_V40_DI (5)
++#define S3C_GPH9_RESERVED4 (6)
++#define S3C_GPH9_EXT_INT_G6_9 (7)
++
++
++/* GPI : 16 in/out port . LCD Video Out[15:0] */
++#define S3C_GPIDAT S3C_GPIOREG(0x104)
++#define S3C_GPICON S3C_GPIOREG(0x100)
++#define S3C_GPIPU S3C_GPIOREG(0x108)
++#define S3C_GPISLPCON S3C_GPIOREG(0x10C)
++
++#define S3C_GPI0 S3C_GPIONO(S3C_GPIO_BANKI, 0)
++#define S3C_GPI0_INP (0)
++#define S3C_GPI0_OUTP (1)
++#define S3C_GPI0_LCD_VD0 (2)
++#define S3C_GPI0_RESERVED (3)
++
++#define S3C_GPI1 S3C_GPIONO(S3C_GPIO_BANKI, 1)
++#define S3C_GPI1_INP (0)
++#define S3C_GPI1_OUTP (1)
++#define S3C_GPI1_LCD_VD1 (2)
++#define S3C_GPI1_RESERVED (3)
++
++#define S3C_GPI2 S3C_GPIONO(S3C_GPIO_BANKI, 2)
++#define S3C_GPI2_INP (0)
++#define S3C_GPI2_OUTP (1)
++#define S3C_GPI2_LCD_VD2 (2)
++#define S3C_GPI2_RESERVED (3)
++
++#define S3C_GPI3 S3C_GPIONO(S3C_GPIO_BANKI, 3)
++#define S3C_GPI3_INP (0)
++#define S3C_GPI3_OUTP (1)
++#define S3C_GPI3_LCD_VD3 (2)
++#define S3C_GPI3_RESERVED (3)
++
++#define S3C_GPI4 S3C_GPIONO(S3C_GPIO_BANKI, 4)
++#define S3C_GPI4_INP (0)
++#define S3C_GPI4_OUTP (1)
++#define S3C_GPI4_LCD_VD4 (2)
++#define S3C_GPI4_RESERVED (3)
++
++#define S3C_GPI5 S3C_GPIONO(S3C_GPIO_BANKI, 5)
++#define S3C_GPI5_INP (0)
++#define S3C_GPI5_OUTP (1)
++#define S3C_GPI5_LCD_VD5 (2)
++#define S3C_GPI5_RESERVED (3)
++
++#define S3C_GPI6 S3C_GPIONO(S3C_GPIO_BANKI, 6)
++#define S3C_GPI6_INP (0)
++#define S3C_GPI6_OUTP (1)
++#define S3C_GPI6_LCD_VD6 (2)
++#define S3C_GPI6_RESERVED (3)
++
++#define S3C_GPI7 S3C_GPIONO(S3C_GPIO_BANKI, 7)
++#define S3C_GPI7_INP (0)
++#define S3C_GPI7_OUTP (1)
++#define S3C_GPI7_LCD_VD7 (2)
++#define S3C_GPI7_RESERVED (3)
++
++#define S3C_GPI8 S3C_GPIONO(S3C_GPIO_BANKI, 8)
++#define S3C_GPI8_INP (0)
++#define S3C_GPI8_OUTP (1)
++#define S3C_GPI8_LCD_VD8 (2)
++#define S3C_GPI8_RESERVED (3)
++
++#define S3C_GPI9 S3C_GPIONO(S3C_GPIO_BANKI, 9)
++#define S3C_GPI9_INP (0)
++#define S3C_GPI9_OUTP (1)
++#define S3C_GPI9_LCD_VD9 (2)
++#define S3C_GPI9_RESERVED (3)
++
++#define S3C_GPI10 S3C_GPIONO(S3C_GPIO_BANKI, 10)
++#define S3C_GPI10_INP (0)
++#define S3C_GPI10_OUTP (1)
++#define S3C_GPI10_LCD_VD10 (2)
++#define S3C_GPI10_RESERVED (3)
++
++#define S3C_GPI11 S3C_GPIONO(S3C_GPIO_BANKI, 11)
++#define S3C_GPI11_INP (0)
++#define S3C_GPI11_OUTP (1)
++#define S3C_GPI11_LCD_VD11 (2)
++#define S3C_GPI11_RESERVED (3)
++
++#define S3C_GPI12 S3C_GPIONO(S3C_GPIO_BANKI, 12)
++#define S3C_GPI12_INP (0)
++#define S3C_GPI12_OUTP (1)
++#define S3C_GPI12_LCD_VD12 (2)
++#define S3C_GPI12_RESERVED (3)
++
++#define S3C_GPI13 S3C_GPIONO(S3C_GPIO_BANKI, 13)
++#define S3C_GPI13_INP (0)
++#define S3C_GPI13_OUTP (1)
++#define S3C_GPI13_LCD_VD13 (2)
++#define S3C_GPI13_RESERVED (3)
++
++#define S3C_GPI14 S3C_GPIONO(S3C_GPIO_BANKI, 14)
++#define S3C_GPI14_INP (0)
++#define S3C_GPI14_OUTP (1)
++#define S3C_GPI14_LCD_VD14 (2)
++#define S3C_GPI14_RESERVED (3)
++
++#define S3C_GPI15 S3C_GPIONO(S3C_GPIO_BANKI, 15)
++#define S3C_GPI15_INP (0)
++#define S3C_GPI15_OUTP (1)
++#define S3C_GPI15_LCD_VD15 (2)
++#define S3C_GPI15_RESERVED (3)
++
++
++/* GPJ : 12 in/out port . LCD Video Out[23:16], Control signals */
++#define S3C_GPJDAT S3C_GPIOREG(0x124)
++#define S3C_GPJCON S3C_GPIOREG(0x120)
++#define S3C_GPJPU S3C_GPIOREG(0x128)
++#define S3C_GPJSLPCON S3C_GPIOREG(0x12C)
++
++#define S3C_GPJ0 S3C_GPIONO(S3C_GPIO_BANKJ, 0)
++#define S3C_GPJ0_INP (0)
++#define S3C_GPJ0_OUTP (1)
++#define S3C_GPJ0_LCD_VD16 (2)
++#define S3C_GPJ0_RESERVED (3)
++
++#define S3C_GPJ1 S3C_GPIONO(S3C_GPIO_BANKJ, 1)
++#define S3C_GPJ1_INP (0)
++#define S3C_GPJ1_OUTP (1)
++#define S3C_GPJ1_LCD_VD17 (2)
++#define S3C_GPJ1_RESERVED (3)
++
++#define S3C_GPJ2 S3C_GPIONO(S3C_GPIO_BANKJ, 2)
++#define S3C_GPJ2_INP (0)
++#define S3C_GPJ2_OUTP (1)
++#define S3C_GPJ2_LCD_VD18 (2)
++#define S3C_GPJ2_RESERVED (3)
++
++#define S3C_GPJ3 S3C_GPIONO(S3C_GPIO_BANKJ, 3)
++#define S3C_GPJ3_INP (0)
++#define S3C_GPJ3_OUTP (1)
++#define S3C_GPJ3_LCD_VD19 (2)
++#define S3C_GPJ3_RESERVED (3)
++
++#define S3C_GPJ4 S3C_GPIONO(S3C_GPIO_BANKJ, 4)
++#define S3C_GPJ4_INP (0)
++#define S3C_GPJ4_OUTP (1)
++#define S3C_GPJ4_LCD_VD20 (2)
++#define S3C_GPJ4_RESERVED (3)
++
++#define S3C_GPJ5 S3C_GPIONO(S3C_GPIO_BANKJ, 5)
++#define S3C_GPJ5_INP (0)
++#define S3C_GPJ5_OUTP (1)
++#define S3C_GPJ5_LCD_VD21 (2)
++#define S3C_GPJ5_RESERVED (3)
++
++#define S3C_GPJ6 S3C_GPIONO(S3C_GPIO_BANKJ, 6)
++#define S3C_GPJ6_INP (0)
++#define S3C_GPJ6_OUTP (1)
++#define S3C_GPJ6_LCD_VD22 (2)
++#define S3C_GPJ6_RESERVED (3)
++
++#define S3C_GPJ7 S3C_GPIONO(S3C_GPIO_BANKJ, 7)
++#define S3C_GPJ7_INP (0)
++#define S3C_GPJ7_OUTP (1)
++#define S3C_GPJ7_LCD_VD23 (2)
++#define S3C_GPJ7_RESERVED (3)
++
++#define S3C_GPJ8 S3C_GPIONO(S3C_GPIO_BANKJ, 8)
++#define S3C_GPJ8_INP (0)
++#define S3C_GPJ8_OUTP (1)
++#define S3C_GPJ8_LCD_HSYNC (2)
++#define S3C_GPJ8_RESERVED (3)
++
++#define S3C_GPJ9 S3C_GPIONO(S3C_GPIO_BANKJ, 9)
++#define S3C_GPJ9_INP (0)
++#define S3C_GPJ9_OUTP (1)
++#define S3C_GPJ9_LCD_VSYNC (2)
++#define S3C_GPJ9_RESERVED (3)
++
++#define S3C_GPJ10 S3C_GPIONO(S3C_GPIO_BANKJ, 10)
++#define S3C_GPJ10_INP (0)
++#define S3C_GPJ10_OUTP (1)
++#define S3C_GPJ10_LCD_VDEN (2)
++#define S3C_GPJ10_RESERVED (3)
++
++#define S3C_GPJ11 S3C_GPIONO(S3C_GPIO_BANKJ, 11)
++#define S3C_GPJ11_INP (0)
++#define S3C_GPJ11_OUTP (1)
++#define S3C_GPJ11_LCD_VCLK (2)
++#define S3C_GPJ11_RESERVED (3)
++
++
++/* GPK : 16 in/out port . Host I/F, HSI, Key pad I/F */
++#define S3C_GPKDAT S3C_GPIOREG(0x808)
++#define S3C_GPK0CON S3C_GPIOREG(0x800)
++#define S3C_GPK1CON S3C_GPIOREG(0x804)
++#define S3C_GPKPU S3C_GPIOREG(0x80C)
++
++#define S3C_GPK0 S3C_GPIONO(S3C_GPIO_BANKK, 0)
++#define S3C_GPK0_INP (0)
++#define S3C_GPK0_OUTP (1)
++#define S3C_GPK0_HOSTIF_DATA0 (2)
++#define S3C_GPK0_HSI_RX_RDY (3)
++#define S3C_GPK0_RESERVED1 (4)
++#define S3C_GPK0_DATA_CF0 (5)
++#define S3C_GPK0_RESERVED2 (6)
++#define S3C_GPK0_RESERVED3 (7)
++
++#define S3C_GPK1 S3C_GPIONO(S3C_GPIO_BANKK, 1)
++#define S3C_GPK1_INP (0)
++#define S3C_GPK1_OUTP (1)
++#define S3C_GPK1_HOSTIF_DATA1 (2)
++#define S3C_GPK1_HSI_RX_WAKE (3)
++#define S3C_GPK1_RESERVED1 (4)
++#define S3C_GPK1_DATA_CF1 (5)
++#define S3C_GPK1_RESERVED2 (6)
++#define S3C_GPK1_RESERVED3 (7)
++
++#define S3C_GPK2 S3C_GPIONO(S3C_GPIO_BANKK, 2)
++#define S3C_GPK2_INP (0)
++#define S3C_GPK2_OUTP (1)
++#define S3C_GPK2_HOSTIF_DATA2 (2)
++#define S3C_GPK2_HSI_RX_FLAG (3)
++#define S3C_GPK2_RESERVED1 (4)
++#define S3C_GPK2_DATA_CF2 (5)
++#define S3C_GPK2_RESERVED2 (6)
++#define S3C_GPK2_RESERVED3 (7)
++
++#define S3C_GPK3 S3C_GPIONO(S3C_GPIO_BANKK, 3)
++#define S3C_GPK3_INP (0)
++#define S3C_GPK3_OUTP (1)
++#define S3C_GPK3_HOSTIF_DATA3 (2)
++#define S3C_GPK3_HSI_RX_DATA (3)
++#define S3C_GPK3_RESERVED1 (4)
++#define S3C_GPK3_DATA_CF3 (5)
++#define S3C_GPK3_RESERVED2 (6)
++#define S3C_GPK3_RESERVED3 (7)
++
++#define S3C_GPK4 S3C_GPIONO(S3C_GPIO_BANKK, 4)
++#define S3C_GPK4_INP (0)
++#define S3C_GPK4_OUTP (1)
++#define S3C_GPK4_HOSTIF_DATA4 (2)
++#define S3C_GPK4_HSI_TX_RDY (3)
++#define S3C_GPK4_RESERVED1 (4)
++#define S3C_GPK4_DATA_CF4 (5)
++#define S3C_GPK4_RESERVED2 (6)
++#define S3C_GPK4_RESERVED3 (7)
++
++#define S3C_GPK5 S3C_GPIONO(S3C_GPIO_BANKK, 5)
++#define S3C_GPK5_INP (0)
++#define S3C_GPK5_OUTP (1)
++#define S3C_GPK5_HOSTIF_DATA5 (2)
++#define S3C_GPK5_HSI_TX_WAKE (3)
++#define S3C_GPK5_RESERVED1 (4)
++#define S3C_GPK5_DATA_CF5 (5)
++#define S3C_GPK5_RESERVED2 (6)
++#define S3C_GPK5_RESERVED3 (7)
++
++#define S3C_GPK6 S3C_GPIONO(S3C_GPIO_BANKK, 6)
++#define S3C_GPK6_INP (0)
++#define S3C_GPK6_OUTP (1)
++#define S3C_GPK6_HOSTIF_DATA6 (2)
++#define S3C_GPK6_HSI_TX_FLAG (3)
++#define S3C_GPK6_RESERVED1 (4)
++#define S3C_GPK6_DATA_CF6 (5)
++#define S3C_GPK6_RESERVED2 (6)
++#define S3C_GPK6_RESERVED3 (7)
++
++#define S3C_GPK7 S3C_GPIONO(S3C_GPIO_BANKK, 7)
++#define S3C_GPK7_INP (0)
++#define S3C_GPK7_OUTP (1)
++#define S3C_GPK7_HOSTIF_DATA7 (2)
++#define S3C_GPK7_HSI_TX_DATA (3)
++#define S3C_GPK7_RESERVED1 (4)
++#define S3C_GPK7_DATA_CF7 (5)
++#define S3C_GPK7_RESERVED2 (6)
++#define S3C_GPK7_RESERVED3 (7)
++
++#define S3C_GPK8 S3C_GPIONO(S3C_GPIO_BANKK, 8)
++#define S3C_GPK8_INP (0)
++#define S3C_GPK8_OUTP (1)
++#define S3C_GPK8_HOSTIF_DATA8 (2)
++#define S3C_GPK8_KEYPAD_ROW0 (3)
++#define S3C_GPK8_RESERVED1 (4)
++#define S3C_GPK8_DATA_CF8 (5)
++#define S3C_GPK8_RESERVED2 (6)
++#define S3C_GPK8_RESERVED3 (7)
++
++#define S3C_GPK9 S3C_GPIONO(S3C_GPIO_BANKK, 9)
++#define S3C_GPK9_INP (0)
++#define S3C_GPK9_OUTP (1)
++#define S3C_GPK9_HOSTIF_DATA9 (2)
++#define S3C_GPK9_KEYPAD_ROW1 (3)
++#define S3C_GPK9_RESERVED1 (4)
++#define S3C_GPK9_DATA_CF9 (5)
++#define S3C_GPK9_RESERVED2 (6)
++#define S3C_GPK9_RESERVED3 (7)
++
++#define S3C_GPK10 S3C_GPIONO(S3C_GPIO_BANKK, 10)
++#define S3C_GPK10_INP (0)
++#define S3C_GPK10_OUTP (1)
++#define S3C_GPK10_HOSTIF_DATA10 (2)
++#define S3C_GPK10_KEYPAD_ROW2 (3)
++#define S3C_GPK10_RESERVED1 (4)
++#define S3C_GPK10_DATA_CF9 (5)
++#define S3C_GPK10_RESERVED2 (6)
++#define S3C_GPK10_RESERVED3 (7)
++
++#define S3C_GPK11 S3C_GPIONO(S3C_GPIO_BANKK, 11)
++#define S3C_GPK11_INP (0)
++#define S3C_GPK11_OUTP (1)
++#define S3C_GPK11_HOSTIF_DATA11 (2)
++#define S3C_GPK11_KEYPAD_ROW3 (3)
++#define S3C_GPK11_RESERVED1 (4)
++#define S3C_GPK11_DATA_CF11 (5)
++#define S3C_GPK11_RESERVED2 (6)
++#define S3C_GPK11_RESERVED3 (7)
++
++#define S3C_GPK12 S3C_GPIONO(S3C_GPIO_BANKK, 12)
++#define S3C_GPK12_INP (0)
++#define S3C_GPK12_OUTP (1)
++#define S3C_GPK12_HOSTIF_DATA12 (2)
++#define S3C_GPK12_KEYPAD_ROW4 (3)
++#define S3C_GPK12_RESERVED1 (4)
++#define S3C_GPK12_DATA_CF12 (5)
++#define S3C_GPK12_RESERVED2 (6)
++#define S3C_GPK12_RESERVED3 (7)
++
++#define S3C_GPK13 S3C_GPIONO(S3C_GPIO_BANKK, 13)
++#define S3C_GPK13_INP (0)
++#define S3C_GPK13_OUTP (1)
++#define S3C_GPK13_HOSTIF_DATA13 (2)
++#define S3C_GPK13_KEYPAD_ROW5 (3)
++#define S3C_GPK13_RESERVED1 (4)
++#define S3C_GPK13_DATA_CF8 (5)
++#define S3C_GPK13_RESERVED2 (6)
++#define S3C_GPK13_RESERVED3 (7)
++
++#define S3C_GPK14 S3C_GPIONO(S3C_GPIO_BANKK, 14)
++#define S3C_GPK14_INP (0)
++#define S3C_GPK14_OUTP (1)
++#define S3C_GPK14_HOSTIF_DATA14 (2)
++#define S3C_GPK14_KEYPAD_ROW6 (3)
++#define S3C_GPK14_RESERVED1 (4)
++#define S3C_GPK14_DATA_CF14 (5)
++#define S3C_GPK14_RESERVED2 (6)
++#define S3C_GPK14_RESERVED3 (7)
++
++#define S3C_GPK15 S3C_GPIONO(S3C_GPIO_BANKK, 15)
++#define S3C_GPK15_INP (0)
++#define S3C_GPK15_OUTP (1)
++#define S3C_GPK15_HOSTIF_DATA15 (2)
++#define S3C_GPK15_KEYPAD_ROW7 (3)
++#define S3C_GPK15_RESERVED1 (4)
++#define S3C_GPK15_DATA_CF15 (5)
++#define S3C_GPK15_RESERVED2 (6)
++#define S3C_GPK15_RESERVED3 (7)
++
++
++/* GPL : 16 in/out port . Host I/F, HSI, Key pad I/F */
++#define S3C_GPLDAT S3C_GPIOREG(0x818)
++#define S3C_GPL0CON S3C_GPIOREG(0x810)
++#define S3C_GPL1CON S3C_GPIOREG(0x814)
++#define S3C_GPLPU S3C_GPIOREG(0x81C)
++
++#define S3C_GPL0 S3C_GPIONO(S3C_GPIO_BANKL, 0)
++#define S3C_GPL0_INP (0)
++#define S3C_GPL0_OUTP (1)
++#define S3C_GPL0_HOSTIF_ADDR0 (2)
++#define S3C_GPL0_KEYPAD_COL0 (3)
++#define S3C_GPL0_RESERVED1 (4)
++#define S3C_GPL0_RESERVED2 (5)
++#define S3C_GPL0_ADDR_CF0 (6)
++#define S3C_GPL0_OTG_ULPI_DATA0 (7)
++
++#define S3C_GPL1 S3C_GPIONO(S3C_GPIO_BANKL, 1)
++#define S3C_GPL1_INP (0)
++#define S3C_GPL1_OUTP (1)
++#define S3C_GPL1_HOSTIF_ADDR1 (2)
++#define S3C_GPL1_KEYPAD_COL1 (3)
++#define S3C_GPL1_RESERVED1 (4)
++#define S3C_GPL1_RESERVED2 (5)
++#define S3C_GPL1_ADDR_CF1 (6)
++#define S3C_GPL1_OTG_ULPI_DATA1 (7)
++
++#define S3C_GPL2 S3C_GPIONO(S3C_GPIO_BANKL, 2)
++#define S3C_GPL2_INP (0)
++#define S3C_GPL2_OUTP (1)
++#define S3C_GPL2_HOSTIF_ADDR2 (2)
++#define S3C_GPL2_KEYPAD_COL2 (3)
++#define S3C_GPL2_RESERVED1 (4)
++#define S3C_GPL2_RESERVED2 (5)
++#define S3C_GPL2_ADDR_CF2 (6)
++#define S3C_GPL2_OTG_ULPI_DATA2 (7)
++
++#define S3C_GPL3 S3C_GPIONO(S3C_GPIO_BANKL, 3)
++#define S3C_GPL3_INP (0)
++#define S3C_GPL3_OUTP (1)
++#define S3C_GPL3_HOSTIF_ADDR3 (2)
++#define S3C_GPL3_KEYPAD_COL3 (3)
++#define S3C_GPL3_RESERVED1 (4)
++#define S3C_GPL3_RESERVED2 (5)
++#define S3C_GPL3_RESERVED3 (6)
++#define S3C_GPL3_OTG_ULPI_DATA3 (7)
++
++#define S3C_GPL4 S3C_GPIONO(S3C_GPIO_BANKL, 4)
++#define S3C_GPL4_INP (0)
++#define S3C_GPL4_OUTP (1)
++#define S3C_GPL4_HOSTIF_ADDR4 (2)
++#define S3C_GPL4_KEYPAD_COL4 (3)
++#define S3C_GPL4_RESERVED1 (4)
++#define S3C_GPL4_RESERVED2 (5)
++#define S3C_GPL4_RESERVED3 (6)
++#define S3C_GPL4_OTG_ULPI_DATA4 (7)
++
++#define S3C_GPL5 S3C_GPIONO(S3C_GPIO_BANKL, 5)
++#define S3C_GPL5_INP (0)
++#define S3C_GPL5_OUTP (1)
++#define S3C_GPL5_HOSTIF_ADDR5 (2)
++#define S3C_GPL5_KEYPAD_COL5 (3)
++#define S3C_GPL5_RESERVED1 (4)
++#define S3C_GPL5_RESERVED2 (5)
++#define S3C_GPL5_RESERVED3 (6)
++#define S3C_GPL5_OTG_ULPI_DATA5 (7)
++
++#define S3C_GPL6 S3C_GPIONO(S3C_GPIO_BANKL, 6)
++#define S3C_GPL6_INP (0)
++#define S3C_GPL6_OUTP (1)
++#define S3C_GPL6_HOSTIF_ADDR6 (2)
++#define S3C_GPL6_KEYPAD_COL6 (3)
++#define S3C_GPL6_RESERVED1 (4)
++#define S3C_GPL6_RESERVED2 (5)
++#define S3C_GPL6_RESERVED3 (6)
++#define S3C_GPL6_OTG_ULPI_DATA6 (7)
++
++#define S3C_GPL7 S3C_GPIONO(S3C_GPIO_BANKL, 7)
++#define S3C_GPL7_INP (0)
++#define S3C_GPL7_OUTP (1)
++#define S3C_GPL7_HOSTIF_ADDR7 (2)
++#define S3C_GPL7_KEYPAD_COL7 (3)
++#define S3C_GPL7_RESERVED1 (4)
++#define S3C_GPL7_RESERVED2 (5)
++#define S3C_GPL7_RESERVED3 (6)
++#define S3C_GPL7_OTG_ULPI_DATA (7)
++
++#define S3C_GPL8 S3C_GPIONO(S3C_GPIO_BANKL, 8)
++#define S3C_GPL8_INP (0)
++#define S3C_GPL8_OUTP (1)
++#define S3C_GPL8_HOSTIF_ADDR8 (2)
++#define S3C_GPL8_EXTINT16 (3)
++#define S3C_GPL8_RESERVED1 (4)
++#define S3C_GPL8_CE_CF0 (5)
++#define S3C_GPL8_RESERVED2 (6)
++#define S3C_GPL8_OTG_ULPI_STP (7)
++
++#define S3C_GPL9 S3C_GPIONO(S3C_GPIO_BANKL, 9)
++#define S3C_GPL9_INP (0)
++#define S3C_GPL9_OUTP (1)
++#define S3C_GPL9_HOSTIF_ADDR9 (2)
++#define S3C_GPL9_EXTINT17 (3)
++#define S3C_GPL9_RESERVED1 (4)
++#define S3C_GPL9_CE_CF1 (5)
++#define S3C_GPL9_RESERVED2 (6)
++#define S3C_GPL9_OTG_ULPI_CLK (7)
++
++#define S3C_GPL10 S3C_GPIONO(S3C_GPIO_BANKL, 10)
++#define S3C_GPL10_INP (0)
++#define S3C_GPL10_OUTP (1)
++#define S3C_GPL10_SPI_CLK1 (2)
++#define S3C_GPL10_EXTINT18 (3)
++#define S3C_GPL10_RESERVED1 (4)
++#define S3C_GPL10_IORD_CF (5)
++#define S3C_GPL10_RESERVED2 (6)
++#define S3C_GPL10_OTG_ULPI_NXT (7)
++
++#define S3C_GPL11 S3C_GPIONO(S3C_GPIO_BANKL, 11)
++#define S3C_GPL11_INP (0)
++#define S3C_GPL11_OUTP (1)
++#define S3C_GPL11_SPI_MOSI1 (2)
++#define S3C_GPL11_EXTINT19 (3)
++#define S3C_GPL11_RESERVED1 (4)
++#define S3C_GPL11_IOWR_CF (5)
++#define S3C_GPL11_RESERVED2 (6)
++#define S3C_GPL11_OTG_ULPI_DIR (7)
++
++#define S3C_GPL12 S3C_GPIONO(S3C_GPIO_BANKL, 12)
++#define S3C_GPL12_INP (0)
++#define S3C_GPL12_OUTP (1)
++#define S3C_GPL12_SPI_MISO1 (2)
++#define S3C_GPL12_EXTINT20 (3)
++#define S3C_GPL12_RESERVED1 (4)
++#define S3C_GPL12_IORDY_CF (5)
++#define S3C_GPL12_RESERVED2 (6)
++#define S3C_GPL12_RESERVED3 (7)
++
++#define S3C_GPL13 S3C_GPIONO(S3C_GPIO_BANKL, 13)
++#define S3C_GPL13_INP (0)
++#define S3C_GPL13_OUTP (1)
++#define S3C_GPL14_nSS0 (2)
++#define S3C_GPL13_EXTINT21 (3)
++#define S3C_GPL13_RESERVED1 (4)
++#define S3C_GPL13_DATA_CF8 (5)
++#define S3C_GPL13_RESERVED2 (6)
++#define S3C_GPL13_RESERVED3 (7)
++
++#define S3C_GPL14 S3C_GPIONO(S3C_GPIO_BANKL, 14)
++#define S3C_GPL14_INP (0)
++#define S3C_GPL14_OUTP (1)
++#define S3C_GPL14_nSS1 (2)
++#define S3C_GPL14_EXTINT22 (3)
++#define S3C_GPL14_RESERVED1 (4)
++#define S3C_GPL14_DATA_CF9 (5)
++#define S3C_GPL14_RESERVED2 (6)
++#define S3C_GPL14_RESERVED3 (7)
++
++
++/* GPM : 6 in/out port . Host I/F, EINT */
++#define S3C_GPMDAT S3C_GPIOREG(0x824)
++#define S3C_GPMCON S3C_GPIOREG(0x820)
++#define S3C_GPMPU S3C_GPIOREG(0x828)
++
++#define S3C_GPM0 S3C_GPIONO(S3C_GPIO_BANKM, 0)
++#define S3C_GPM0_INP (0)
++#define S3C_GPM0_OUTP (1)
++#define S3C_GPM0_HOSTIF_CS (2)
++#define S3C_GPM0_EXTINT23 (3)
++#define S3C_GPM0_RESERVED1 (4)
++#define S3C_GPM0_DATA_CF10 (5)
++#define S3C_GPM0_CE_CF0 (6)
++#define S3C_GPM0_RESERVED2 (7)
++
++#define S3C_GPM1 S3C_GPIONO(S3C_GPIO_BANKM, 1)
++#define S3C_GPM1_INP (0)
++#define S3C_GPM1_OUTP (1)
++#define S3C_GPM1_HOSTIF_CS_M (2)
++#define S3C_GPM1_EXTINT24 (3)
++#define S3C_GPM1_RESERVED1 (4)
++#define S3C_GPM1_DATA_CF11 (5)
++#define S3C_GPM1_CE_CF1 (6)
++#define S3C_GPM1_RESERVED2 (7)
++
++#define S3C_GPM2 S3C_GPIONO(S3C_GPIO_BANKM, 2)
++#define S3C_GPM2_INP (0)
++#define S3C_GPM2_OUTP (1)
++#define S3C_GPM2_HOST_IF_CS_S (2)
++#define S3C_GPM2_EXTINT25 (3)
++#define S3C_GPM2_HOSTIF_MDP_VSYNC (4)
++#define S3C_GPM2_DATA_CF12 (5)
++#define S3C_GPM2_IORD_CF (6)
++#define S3C_GPM2_RESERVED2 (7)
++
++#define S3C_GPM3 S3C_GPIONO(S3C_GPIO_BANKM, 3)
++#define S3C_GPM3_INP (0)
++#define S3C_GPM3_OUTP (1)
++#define S3C_GPM3_HOSTIF_WE (2)
++#define S3C_GPM3_EXTINT26 (3)
++#define S3C_GPM3_RESERVED1 (4)
++#define S3C_GPM3_DATA_CF13 (5)
++#define S3C_GPM3_IOWR_CF (6)
++#define S3C_GPM3_RESERVED2 (7)
++
++#define S3C_GPM4 S3C_GPIONO(S3C_GPIO_BANKM, 4)
++#define S3C_GPM4_INP (0)
++#define S3C_GPM4_OUTP (1)
++#define S3C_GPM4_HOSTIF_OE (2)
++#define S3C_GPM4_EXTINT27 (3)
++#define S3C_GPM4_RESERVED1 (4)
++#define S3C_GPM4_DATA_CF14 (5)
++#define S3C_GPM4_IORDY_CF (6)
++#define S3C_GPM4_RESERVED2 (7)
++
++#define S3C_GPM5 S3C_GPIONO(S3C_GPIO_BANKM, 5)
++#define S3C_GPM5_INP (0)
++#define S3C_GPM5_OUTP (1)
++#define S3C_GPM5_HOSTIF_INTR (2)
++#define S3C_GPM5_CF_DATA_DIR (3)
++#define S3C_GPM5_RESERVED1 (4)
++#define S3C_GPM5_DATA_CF15 (5)
++#define S3C_GPM5_RESERVED2 (6)
++#define S3C_GPM5_RESERVED3 (7)
++
++
++/* GPN : 16 in/out port . EINT */
++#define S3C_GPNDAT S3C_GPIOREG(0x834)
++#define S3C_GPNCON S3C_GPIOREG(0x830)
++#define S3C_GPNPU S3C_GPIOREG(0x838)
++
++#define S3C_GPN0 S3C_GPIONO(S3C_GPIO_BANKN, 0)
++#define S3C_GPN0_INP (0)
++#define S3C_GPN0_OUTP (1)
++#define S3C_GPN0_EXTINT0 (2)
++#define S3C_GPN0_KEYPAD_ROW0 (3)
++
++#define S3C_GPN1 S3C_GPIONO(S3C_GPIO_BANKN, 1)
++#define S3C_GPN1_INP (0)
++#define S3C_GPN1_OUTP (1)
++#define S3C_GPN1_EXTINT1 (2)
++#define S3C_GPN1_KEYPAD_ROW1 (3)
++
++#define S3C_GPN2 S3C_GPIONO(S3C_GPIO_BANKN, 2)
++#define S3C_GPN2_INP (0)
++#define S3C_GPN2_OUTP (1)
++#define S3C_GPN2_EXTINT2 (2)
++#define S3C_GPN2_KEYPAD_ROW2 (3)
++
++#define S3C_GPN3 S3C_GPIONO(S3C_GPIO_BANKN, 3)
++#define S3C_GPN3_INP (0)
++#define S3C_GPN3_OUTP (1)
++#define S3C_GPN3_EXTINT3 (2)
++#define S3C_GPN3_KEYPAD_ROW3 (3)
++
++#define S3C_GPN4 S3C_GPIONO(S3C_GPIO_BANKN, 4)
++#define S3C_GPN4_INP (0)
++#define S3C_GPN4_OUTP (1)
++#define S3C_GPN4_EXTINT4 (2)
++#define S3C_GPN4_KEYPAD_ROW4 (3)
++
++#define S3C_GPN5 S3C_GPIONO(S3C_GPIO_BANKN, 5)
++#define S3C_GPN5_INP (0)
++#define S3C_GPN5_OUTP (1)
++#define S3C_GPN5_EXTINT5 (2)
++#define S3C_GPN5_KEYPAD_ROW5 (3)
++
++#define S3C_GPN6 S3C_GPIONO(S3C_GPIO_BANKN, 6)
++#define S3C_GPN6_INP (0)
++#define S3C_GPN6_OUTP (1)
++#define S3C_GPN6_EXTINT6 (2)
++#define S3C_GPN6_KEYPAD_ROW6 (3)
++
++#define S3C_GPN7 S3C_GPIONO(S3C_GPIO_BANKN, 7)
++#define S3C_GPN7_INP (0)
++#define S3C_GPN7_OUTP (1)
++#define S3C_GPN7_EXTINT7 (2)
++#define S3C_GPN7_KEYPAD_ROW7 (3)
++
++#define S3C_GPN8 S3C_GPIONO(S3C_GPIO_BANKN, 8)
++#define S3C_GPN8_INP (0)
++#define S3C_GPN8_OUTP (1)
++#define S3C_GPN8_EXTINT8 (2)
++#define S3C_GPN8_ADDR_CF0 (3)
++
++#define S3C_GPN9 S3C_GPIONO(S3C_GPIO_BANKN, 9)
++#define S3C_GPN9_INP (0)
++#define S3C_GPN9_OUTP (1)
++#define S3C_GPN9_EXTINT9 (2)
++#define S3C_GPN9_ADDR_CF1 (3)
++
++#define S3C_GPN10 S3C_GPIONO(S3C_GPIO_BANKN, 10)
++#define S3C_GPN10_INP (0)
++#define S3C_GPN10_OUTP (1)
++#define S3C_GPN10_EXTINT10 (2)
++#define S3C_GPN10_ADDR_CF2 (3)
++
++#define S3C_GPN11 S3C_GPIONO(S3C_GPIO_BANKN, 11)
++#define S3C_GPN11_INP (0)
++#define S3C_GPN11_OUTP (1)
++#define S3C_GPN11_EXTINT11 (2)
++#define S3C_GPN11_RESERVED (3)
++
++#define S3C_GPN12 S3C_GPIONO(S3C_GPIO_BANKN, 12)
++#define S3C_GPN12_INP (0)
++#define S3C_GPN12_OUTP (1)
++#define S3C_GPN12_EXTINT12 (2)
++#define S3C_GPN12_RESERVED (3)
++
++#define S3C_GPN13 S3C_GPIONO(S3C_GPIO_BANKN, 13)
++#define S3C_GPN13_INP (0)
++#define S3C_GPN13_OUTP (1)
++#define S3C_GPN13_EXTINT13 (2)
++#define S3C_GPN13_RESERVED (3)
++
++#define S3C_GPN14 S3C_GPIONO(S3C_GPIO_BANKN, 14)
++#define S3C_GPN14_INP (0)
++#define S3C_GPN14_OUTP (1)
++#define S3C_GPN14_EXTINT14 (2)
++#define S3C_GPN14_RESERVED (3)
++
++#define S3C_GPN15 S3C_GPIONO(S3C_GPIO_BANKN, 15)
++#define S3C_GPN15_INP (0)
++#define S3C_GPN15_OUTP (1)
++#define S3C_GPN15_EXTINT15 (2)
++#define S3C_GPN15_RESERVED (3)
++
++
++/* GPO : 16 in/out port . Memory Port 0 */
++#define S3C_GPODAT S3C_GPIOREG(0x144)
++#define S3C_GPOCON S3C_GPIOREG(0x140)
++#define S3C_GPOPU S3C_GPIOREG(0x148)
++
++/* GPP : 15 in/out port . Memory Port 0 */
++#define S3C_GPPDAT S3C_GPIOREG(0x164)
++#define S3C_GPPCON S3C_GPIOREG(0x160)
++#define S3C_GPPPU S3C_GPIOREG(0x168)
++
++/* GPQ : 9 in/out port . Memory Port 0 Dram part */
++#define S3C_GPQDAT S3C_GPIOREG(0x184)
++#define S3C_GPQCON S3C_GPIOREG(0x180)
++#define S3C_GPQPU S3C_GPIOREG(0x188)
++
++
++#define S3C_MEM0CONSTOP S3C_GPIOREG(0x1B0)
++#define S3C_MEM1CONSTOP S3C_GPIOREG(0x1B4)
++#define S3C_MEM0CONSLP0 S3C_GPIOREG(0x1C0)
++#define S3C_MEM0CONSLP1 S3C_GPIOREG(0x1C4)
++#define S3C_MEM1CONSLP S3C_GPIOREG(0x1C8)
++#define S3C_MEM0DRVCON S3C_GPIOREG(0x1D0)
++#define S3C_MEM1DRVCON S3C_GPIOREG(0x1D4)
++
++#define S3C_EINTCON0 S3C_GPIOREG(0x900)
++#define S3C_EINTCON1 S3C_GPIOREG(0x904)
++#define S3C_EINTFLTCON0 S3C_GPIOREG(0x910)
++#define S3C_EINTFLTCON1 S3C_GPIOREG(0x914)
++#define S3C_EINTFLTCON2 S3C_GPIOREG(0x918)
++#define S3C_EINTFLTCON3 S3C_GPIOREG(0x91C)
++#define S3C_EINTMASK S3C_GPIOREG(0x920)
++#define S3C_EINTPEND S3C_GPIOREG(0x924) /* External Interrupt Pending Register */
++#define S3C_EINT12CON S3C_GPIOREG(0x200) /* External Interrupt 1,2 Configuration Register */
++#define S3C_EINT34CON S3C_GPIOREG(0x204) /* External Interrupt 3,4 Configuration Register */
++#define S3C_EINT56CON S3C_GPIOREG(0x208) /* External Interrupt 5,6 Configuration Register */
++#define S3C_EINT78CON S3C_GPIOREG(0x20C) /* External Interrupt 7,8 Configuration Register */
++#define S3C_EINT9CON S3C_GPIOREG(0x210) /* External Interrupt 9 Configuration Register */
++#define S3C_EINT12FLTCON S3C_GPIOREG(0x220) /* External Interrupt 1,2 Filter Control Register */
++#define S3C_EINT34FLTCON S3C_GPIOREG(0x224) /* External Interrupt 3,4 Filter Control Register */
++#define S3C_EINT56FLTCON S3C_GPIOREG(0x228) /* External Interrupt 5,6 Filter Control Register */
++#define S3C_EINT78FLTCON S3C_GPIOREG(0x22C) /* External Interrupt 7,8 Filter Control Register */
++#define S3C_EINT9FLTCON S3C_GPIOREG(0x230) /* External Interrupt 9 Filter Control Register */
++#define S3C_EINT12MASK S3C_GPIOREG(0x240) /* External Interrupt 1,2 Mask Register */
++#define S3C_EINT34MASK S3C_GPIOREG(0x244) /* External Interrupt 3,4 Mask Register */
++#define S3C_EINT56MASK S3C_GPIOREG(0x248) /* External Interrupt 5,6 Mask Register */
++#define S3C_EINT78MASK S3C_GPIOREG(0x24C) /* External Interrupt 7,8 Mask Register */
++#define S3C_EINT9MASK S3C_GPIOREG(0x250) /* External Interrupt 9 Mask Register */
++#define S3C_EINT12PEND S3C_GPIOREG(0x260) /* External Interrupt 1,2 Pending Register */
++#define S3C_EINT34PEND S3C_GPIOREG(0x264) /* External Interrupt 3,4 Pending Register */
++#define S3C_EINT56PEND S3C_GPIOREG(0x268) /* External Interrupt 5,6 Pending Register */
++#define S3C_EINT78PEND S3C_GPIOREG(0x26C) /* External Interrupt 7,8 Pending Register */
++#define S3C_EINT9PEND S3C_GPIOREG(0x270) /* External Interrupt 9 Pending Register */
++#define S3C_PRIORITY S3C_GPIOREG(0x280) /* Priority Control Register */
++#define S3C_SERVICE S3C_GPIOREG(0x284) /* Current Service Register */
++#define S3C_SERVICEPEND S3C_GPIOREG(0x288) /* Current Service Pending Register */
++
++/* values for S3C_EXTINT0 */
++#define S3C_EXTINT_LOWLEV (0x00)
++#define S3C_EXTINT_HILEV (0x01)
++#define S3C_EXTINT_FALLEDGE (0x02)
++#define S3C_EXTINT_RISEEDGE (0x04)
++#define S3C_EXTINT_BOTHEDGE (0x06)
++
++/* Special port control register*/
++#define S3C_SPCON S3C_GPIOREG(0x1A0)
++#define S3C_SPONSLP S3C_GPIOREG(0x880)
++#define S3C_SLPEN S3C_GPIOREG(0x934)
++
++#endif
+ #endif /* __ASM_ARCH_REGS_GPIO_H */
+
+diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
+index 0362332..2694e4e 100644
+--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
++++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
+@@ -99,8 +99,123 @@
+ #define S3C2440_GPJ12_CAMRESET (0x02 << 24)
+
+ #define S3C2443_GPJ13 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
+-#define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
+-#define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
++#define S3C2443_GPJ13_INP (0x00 << 26)
++#define S3C2443_GPJ13_OUTP (0x01 << 26)
++#define S3C2443_GPJ13_SD0LED (0x02 << 26)
++#define S3C2450_GPJ13_SD1LED (0x02 << 26)
++#define S3C2450_GPJ13_I2S1_LRCK (0x03 << 26)
++
++#define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
++#define S3C2443_GPJ14_INP (0x00 << 28)
++#define S3C2443_GPJ14_OUTP (0x01 << 28)
++#define S3C2443_GPJ14_nSD0CD (0x02 << 28)
++#define S3C2450_GPJ14_nSD1CD (0x02 << 28)
++
++#define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
++#define S3C2443_GPJ15_INP (0x00 << 30)
++#define S3C2443_GPJ15_OUTP (0x01 << 30)
++#define S3C2443_GPJ15_nSD0WP (0x02 << 30)
++#define S3C2450_GPJ15_nSD1WP (0x02 << 30)
++
++#define S3C2443_GPJDN S3C2410_GPIOREG(0xd8)
++
++/* Port L consists of 14 GPIO
++ *
++ * GPLCON has 2 bits for each of the input pins on port K
++ * 00 = 0 input, 1 output, 2 SD
++ *
++ * pull down works like all other ports.
++*/
++#define S3C2443_GPLCON S3C2410_GPIOREG(0xf0)
++#define S3C2443_GPLDAT S3C2410_GPIOREG(0xf4)
++#define S3C2443_GPLUDP S3C2410_GPIOREG(0xf8)
++#define S3C2443_GPLDN S3C2410_GPIOREG(0xf8)
++
++#define S3C2443_GPL0 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 0)
++#define S3C3443_GPL0_INP (0x00 << 0)
++#define S3C2443_GPL0_OUTP (0x01 << 0)
++#define S3C2443_GPL0_SD0DAT0 (0x02 << 0)
++#define S3C2450_GPL0_SD1DAT0 (0x02 << 0)
++
++#define S3C2443_GPL1 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 1)
++#define S3C2443_GPL1_INP (0x00 << 2)
++#define S3C2443_GPL1_OUTP (0x01 << 2)
++#define S3C2443_GPL1_SD0DAT1 (0x02 << 2)
++#define S3C2450_GPL1_SD1DAT1 (0x02 << 2)
++
++#define S3C2443_GPL2 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 2)
++#define S3C2443_GPL2_INP (0x00 << 4)
++#define S3C2443_GPL2_OUTP (0x01 << 4)
++#define S3C2443_GPL2_SD0DAT2 (0x02 << 4)
++#define S3C2450_GPL2_SD1DAT2 (0x02 << 4)
++
++#define S3C2443_GPL3 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 3)
++#define S3C2443_GPL3_INP (0x00 << 6)
++#define S3C2443_GPL3_OUTP (0x01 << 6)
++#define S3C2443_GPL3_SD0DAT3 (0x02 << 6)
++#define S3C2450_GPL3_SD1DAT3 (0x02 << 6)
++
++#define S3C2443_GPL4 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 4)
++#define S3C2443_GPL4_INP (0x00 << 8)
++#define S3C2443_GPL4_OUTP (0x01 << 8)
++#define S3C2443_GPL4_SD0DAT4 (0x02 << 8)
++#define S3C2450_GPL4_SD1DAT4 (0x02 << 8)
++
++#define S3C2443_GPL5 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 5)
++#define S3C2443_GPL5_INP (0x00 << 10)
++#define S3C2443_GPL5_OUTP (0x01 << 10)
++#define S3C2443_GPL5_SD0DAT5 (0x02 << 10)
++#define S3C2450_GPL5_SD1DAT5 (0x02 << 10)
++
++#define S3C2443_GPL6 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 6)
++#define S3C2443_GPL6_INP (0x00 << 12)
++#define S3C2443_GPL6_OUTP (0x01 << 12)
++#define S3C2443_GPL6_SD0DAT6 (0x02 << 12)
++#define S3C2450_GPL6_SD1DAT6 (0x02 << 12)
++
++#define S3C2443_GPL7 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 7)
++#define S3C2443_GPL7_INP (0x00 << 14)
++#define S3C2443_GPL7_OUTP (0x01 << 14)
++#define S3C2443_GPL7_SD0DAT7 (0x02 << 14)
++#define S3C2450_GPL7_SD1DAT7 (0x02 << 14)
++
++#define S3C2443_GPL8 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 8)
++#define S3C2443_GPL8_INP (0x00 << 16)
++#define S3C2443_GPL8_OUTP (0x01 << 16)
++#define S3C2443_GPL8_SD0CMD (0x02 << 16)
++#define S3C2450_GPL8_SD1CMD (0x02 << 16)
++
++#define S3C2443_GPL9 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 9)
++#define S3C2443_GPL9_INP (0x00 << 18)
++#define S3C2443_GPL9_OUTP (0x01 << 18)
++#define S3C2443_GPL9_SD0CLK (0x02 << 18)
++#define S3C2450_GPL9_SD1CLK (0x02 << 18)
++
++#define S3C2443_GPL10 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 10)
++#define S3C2443_GPL10_INP (0x00 << 20)
++#define S3C2443_GPL10_OUTP (0x01 << 20)
++#define S3C2443_GPL10_SPICLK1 (00x2 << 20)
++
++#define S3C2443_GPL11 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 11)
++#define S3C2443_GPL11_INP (0x00 << 22)
++#define S3C2443_GPL11_OUTP (0x01 << 22)
++#define S3C2443_GPL11_SPIMOSI1 (0x02 << 22)
++
++#define S3C2443_GPL12 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 12)
++#define S3C2443_GPL12_INP (0x00 << 24)
++#define S3C2443_GPL12_OUTP (0x01 << 24)
++#define S3C2443_GPL12_SPIMISO1 (0x02 << 24)
++
++#define S3C2443_GPL13 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 13)
++#define S3C2443_GPL13_INP (00x0 << 26)
++#define S3C2443_GPL13_OUTP (0x01 << 26)
++#define S3C2443_GPL13_nSS0 (0x02 << 26)
++
++#define S3C2443_GPL14 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 14)
++#define S3C2443_GPL14_INP (0x00 << 28)
++#define S3C2443_GPL14_OUTP (0x01 << 28)
++#define S3C2443_GPL14_nSS1 (0x02 << 28)
++
+
+ #endif /* __ASM_ARCH_REGS_GPIOJ_H */
+
+diff --git a/include/asm-arm/arch-s3c2410/regs-hsmmc.h b/include/asm-arm/arch-s3c2410/regs-hsmmc.h
+new file mode 100644
+index 0000000..b25a756
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-hsmmc.h
+@@ -0,0 +1,210 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-hsmmc.h
++ *
++ * Copyright (c) 2004 Samsung Electronics
++ * http://www.samsung.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C HS-MMC Controller
++*/
++
++#ifndef __ASM_ARCH_REGS_HSMMC_H
++#define __ASM_ARCH_REGS_HSMMC_H __FILE__
++
++/*
++ * HS MMC Interface
++ */
++#define S3C_HSMMC_REG(x) (x)
++
++#define S3C_HSMMC_SYSAD (0x00)
++
++#define S3C_HSMMC_BLKSIZE (0x04)
++#define S3C_HSMMC_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
++
++#define S3C_HSMMC_BLKCNT (0x06)
++#define S3C_HSMMC_ARGUMENT (0x08)
++
++#define S3C_HSMMC_TRNMOD (0x0c)
++#define S3C_HSMMC_TRNS_DMA 0x01
++#define S3C_HSMMC_TRNS_BLK_CNT_EN 0x02
++#define S3C_HSMMC_TRNS_ACMD12 0x04
++#define S3C_HSMMC_TRNS_READ 0x10
++#define S3C_HSMMC_TRNS_MULTI 0x20
++
++#define S3C_HSMMC_CMDREG (0x0e)
++#define S3C_HSMMC_RSPREG0 (0x10)
++#define S3C_HSMMC_RSPREG1 (0x14)
++#define S3C_HSMMC_RSPREG2 (0x18)
++#define S3C_HSMMC_RSPREG3 (0x1c)
++#define S3C_HSMMC_CMD_RESP_MASK 0x03
++#define S3C_HSMMC_CMD_CRC 0x08
++#define S3C_HSMMC_CMD_INDEX 0x10
++#define S3C_HSMMC_CMD_DATA 0x20
++#define S3C_HSMMC_CMD_RESP_NONE 0x00
++#define S3C_HSMMC_CMD_RESP_LONG 0x01
++#define S3C_HSMMC_CMD_RESP_SHORT 0x02
++#define S3C_HSMMC_CMD_RESP_SHORT_BUSY 0x03
++#define S3C_HSMMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
++
++#define S3C_HSMMC_BDATA (0x20)
++
++#define S3C_HSMMC_PRNSTS (0x24)
++#define S3C_HSMMC_CMD_INHIBIT 0x00000001
++#define S3C_HSMMC_DATA_INHIBIT 0x00000002
++#define S3C_HSMMC_DOING_WRITE 0x00000100
++#define S3C_HSMMC_DOING_READ 0x00000200
++#define S3C_HSMMC_SPACE_AVAILABLE 0x00000400
++#define S3C_HSMMC_DATA_AVAILABLE 0x00000800
++#define S3C_HSMMC_CARD_PRESENT 0x00010000
++#define S3C_HSMMC_WRITE_PROTECT 0x00080000
++
++#define S3C_HSMMC_HOSTCTL (0x28)
++#define S3C_HSMMC_CTRL_LED 0x01
++#define S3C_HSMMC_CTRL_4BITBUS 0x02
++#define S3C_HSMMC_CTRL_HIGHSPEED 0x04
++#define S3C_HSMMC_CTRL_1BIT 0x00
++#define S3C_HSMMC_CTRL_4BIT 0x02
++#define S3C_HSMMC_CTRL_8BIT 0x20
++#define S3C_HSMMC_CTRL_SDMA 0x00
++#define S3C_HSMMC_CTRL_ADMA2_32 0x10
++
++#define S3C_HSMMC_PWRCON (0x29)
++#define S3C_HSMMC_POWER_OFF 0x00
++#define S3C_HSMMC_POWER_ON 0x01
++#define S3C_HSMMC_POWER_180 0x0A
++#define S3C_HSMMC_POWER_300 0x0C
++#define S3C_HSMMC_POWER_330 0x0E
++#define S3C_HSMMC_POWER_ON_ALL 0xFF
++
++#define S3C_HSMMC_BLKGAP (0x2a)
++#define S3C_HSMMC_WAKCON (0x2b)
++
++#define S3C_HSMMC_CLKCON (0x2c)
++#define S3C_HSMMC_DIVIDER_SHIFT 8
++#define S3C_HSMMC_CLOCK_EXT_STABLE 0x0008
++#define S3C_HSMMC_CLOCK_CARD_EN 0x0004
++#define S3C_HSMMC_CLOCK_INT_STABLE 0x0002
++#define S3C_HSMMC_CLOCK_INT_EN 0x0001
++
++#define S3C_HSMMC_TIMEOUTCON (0x2e)
++#define S3C_HSMMC_TIMEOUT_MAX 0x0E
++
++#define S3C_HSMMC_SWRST (0x2f)
++#define S3C_HSMMC_RESET_ALL 0x01
++#define S3C_HSMMC_RESET_CMD 0x02
++#define S3C_HSMMC_RESET_DATA 0x04
++
++#define S3C_HSMMC_NORINTSTS (0x30)
++#define S3C_HSMMC_NIS_ERR 0x00008000
++#define S3C_HSMMC_NIS_CMDCMP 0x00000001
++#define S3C_HSMMC_NIS_TRSCMP 0x00000002
++#define S3C_HSMMC_NIS_DMA 0x00000008
++
++#define S3C_HSMMC_ERRINTSTS (0x32)
++#define S3C_HSMMC_EIS_CMDTIMEOUT 0x00000001
++#define S3C_HSMMC_EIS_CMDERR 0x0000000E
++#define S3C_HSMMC_EIS_DATATIMEOUT 0x00000010
++#define S3C_HSMMC_EIS_DATAERR 0x00000060
++#define S3C_HSMMC_EIS_CMD12ERR 0x00000100
++#define S3C_HSMMC_EIS_ADMAERR 0x00000200
++
++#define S3C_HSMMC_NORINTSTSEN (0x34)
++#define S3C_HSMMC_ERRINTSTSEN (0x36)
++
++#define S3C_HSMMC_NORINTSIGEN (0x38)
++#define S3C_HSMMC_INT_MASK_ALL 0x0000
++#define S3C_HSMMC_INT_RESPONSE 0x00000001
++#define S3C_HSMMC_INT_DATA_END 0x00000002
++#define S3C_HSMMC_INT_DMA_END 0x00000008
++#define S3C_HSMMC_INT_SPACE_AVAIL 0x00000010
++#define S3C_HSMMC_INT_DATA_AVAIL 0x00000020
++#define S3C_HSMMC_INT_CARD_INSERT 0x00000040
++#define S3C_HSMMC_INT_CARD_REMOVE 0x00000080
++#define S3C_HSMMC_INT_CARD_CHANGE 0x000000c0 /* oring of above two */
++#define S3C_HSMMC_INT_CARD_INT 0x00000100
++#define S3C_HSMMC_INT_TIMEOUT 0x00010000
++#define S3C_HSMMC_INT_CRC 0x00020000
++#define S3C_HSMMC_INT_END_BIT 0x00040000
++#define S3C_HSMMC_INT_INDEX 0x00080000
++#define S3C_HSMMC_INT_DATA_TIMEOUT 0x00100000
++#define S3C_HSMMC_INT_DATA_CRC 0x00200000
++#define S3C_HSMMC_INT_DATA_END_BIT 0x00400000
++#define S3C_HSMMC_INT_BUS_POWER 0x00800000
++#define S3C_HSMMC_INT_ACMD12ERR 0x01000000
++#define S3C_HSMMC_INT_ADMAERR 0x02000000
++
++#define S3C_HSMMC_INT_NORMAL_MASK 0x00007FFF
++#define S3C_HSMMC_INT_ERROR_MASK 0xFFFF8000
++
++#define S3C_HSMMC_INT_CMD_MASK (S3C_HSMMC_INT_RESPONSE | \
++ S3C_HSMMC_INT_TIMEOUT | \
++ S3C_HSMMC_INT_CRC | \
++ S3C_HSMMC_INT_END_BIT | \
++ S3C_HSMMC_INT_INDEX | \
++ S3C_HSMMC_NIS_ERR \
++ )
++#define S3C_HSMMC_INT_DATA_MASK (S3C_HSMMC_INT_DATA_END | \
++ S3C_HSMMC_INT_DMA_END | \
++ S3C_HSMMC_INT_DATA_AVAIL | \
++ S3C_HSMMC_INT_SPACE_AVAIL | \
++ S3C_HSMMC_INT_DATA_TIMEOUT | \
++ S3C_HSMMC_INT_DATA_CRC | \
++ S3C_HSMMC_INT_DATA_END_BIT \
++ )
++
++#define S3C_HSMMC_ERRINTSIGEN (0x3a)
++#define S3C_HSMMC_ACMD12ERRSTS (0x3c)
++
++#define S3C_HSMMC_CAPAREG (0x40)
++#define S3C_HSMMC_TIMEOUT_CLK_MASK 0x0000003F
++#define S3C_HSMMC_TIMEOUT_CLK_SHIFT 0
++#define S3C_HSMMC_TIMEOUT_CLK_UNIT 0x00000080
++#define S3C_HSMMC_CLOCK_BASE_MASK 0x00003F00
++#define S3C_HSMMC_CLOCK_BASE_SHIFT 8
++#define S3C_HSMMC_MAX_BLOCK_MASK 0x00030000
++#define S3C_HSMMC_MAX_BLOCK_SHIFT 16
++#define S3C_HSMMC_CAN_DO_DMA 0x00400000
++#define S3C_HSMMC_CAN_DO_ADMA2 0x00080000
++#define S3C_HSMMC_CAN_VDD_330 0x01000000
++#define S3C_HSMMC_CAN_VDD_300 0x02000000
++#define S3C_HSMMC_CAN_VDD_180 0x04000000
++
++#define S3C_HSMMC_MAXCURR (0x48)
++
++/* For ADMA2 */
++#define S3C_HSMMC_FEAER (0x50)
++#define S3C_HSMMC_FEERR (0x52)
++
++#define S3C_HSMMC_ADMAERR (0x54)
++#define S3C_HSMMC_ADMAERR_CONTINUE_REQUEST (1<<9)
++#define S3C_HSMMC_ADMAERR_INTRRUPT_STATUS (1<<8)
++#define S3C_HSMMC_ADMAERR_LENGTH_MISMATCH (1<<2)
++#define S3C_HSMMC_ADMAERR_STATE_ST_STOP (0<<0)
++#define S3C_HSMMC_ADMAERR_STATE_ST_FDS (1<<0)
++#define S3C_HSMMC_ADMAERR_STATE_ST_TFR (3<<0)
++
++#define S3C_HSMMC_ADMASYSADDR (0x58)
++#define S3C_HSMMC_ADMA_ATTR_MSK 0x3F
++#define S3C_HSMMC_ADMA_ATTR_ACT_NOP (0<<4)
++#define S3C_HSMMC_ADMA_ATTR_ACT_RSV (1<<4)
++#define S3C_HSMMC_ADMA_ATTR_ACT_TRAN (2<<4)
++#define S3C_HSMMC_ADMA_ATTR_ACT_LINK (3<<4)
++#define S3C_HSMMC_ADMA_ATTR_INT (1<<2)
++#define S3C_HSMMC_ADMA_ATTR_END (1<<1)
++#define S3C_HSMMC_ADMA_ATTR_VALID (1<<0)
++
++#define S3C_HSMMC_CONTROL2 (0x80)
++#define S3C_HSMMC_CONTROL3 (0x84)
++#define S3C_HSMMC_CONTROL4 (0x8C)
++#define S3C_HSMMC_DEBUG (0x88)
++
++#define S3C_HSMMC_HCVER (0xfe)
++#define S3C_HSMMC_VENDOR_VER_MASK 0xFF00
++#define S3C_HSMMC_VENDOR_VER_SHIFT 8
++#define S3C_HSMMC_SPEC_VER_MASK 0x00FF
++#define S3C_HSMMC_SPEC_VER_SHIFT 0
++
++#endif /* __ASM_ARCH_REGS_HSMMC_H */
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-ide.h b/include/asm-arm/arch-s3c2410/regs-ide.h
+new file mode 100644
+index 0000000..5fdb4fd
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-ide.h
+@@ -0,0 +1,58 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
++ *
++ * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
++ * http://www.simtec.co.uk/products/SWLINUX/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C2410 NAND register definitions
++*/
++
++#ifndef __ASM_ARM_REGS_IDE
++#define __ASM_ARM_REGS_IDE "$Id: "
++
++
++#define S3C_CFATA_REG(x) (x)
++
++#define S3C_CFATA_MUX S3C_CFATA_REG(0x1800)
++#define S3C_CF_CFG S3C_CFATA_REG(0x1820)
++#define S3C_CF_INTMSK S3C_CFATA_REG(0x1824)
++#define S3C_CF_ATTR S3C_CFATA_REG(0x1828)
++#define S3C_CF_IO S3C_CFATA_REG(0x182c)
++#define S3C_CF_COMM S3C_CFATA_REG(0x1830)
++
++#define S3C_ATA_CTRL S3C_CFATA_REG(0x1900)
++#define S3C_ATA_STATUS S3C_CFATA_REG(0x1904)
++#define S3C_ATA_CMD S3C_CFATA_REG(0x1908)
++#define S3C_ATA_SWRST S3C_CFATA_REG(0x190c)
++#define S3C_ATA_IRQ S3C_CFATA_REG(0x1910)
++#define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x1914)
++#define S3C_ATA_CFG S3C_CFATA_REG(0x1918)
++
++#define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x192c)
++#define S3C_ATA_UDMA_TIME S3C_CFATA_REG(0x1930)
++#define S3C_ATA_XFR_NUM S3C_CFATA_REG(0x1934)
++#define S3C_ATA_XFR_CNT S3C_CFATA_REG(0x1938)
++#define S3C_ATA_TBUF_START S3C_CFATA_REG(0x193c)
++#define S3C_ATA_TBUF_SIZE S3C_CFATA_REG(0x1940)
++#define S3C_ATA_SBUF_START S3C_CFATA_REG(0x1944)
++#define S3C_ATA_SBUF_SIZE S3C_CFATA_REG(0x1948)
++#define S3C_ATA_CADR_TBUF S3C_CFATA_REG(0x194c)
++#define S3C_ATA_CADR_SBUF S3C_CFATA_REG(0x1950)
++#define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x1954)
++#define S3C_ATA_PIO_FED S3C_CFATA_REG(0x1958)
++#define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x195c)
++#define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x1960)
++#define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x1964)
++#define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x1968)
++#define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x196c)
++#define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x1970)
++#define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x1974)
++#define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x197c)
++#define S3C_BUS_FIFO_STATUS S3C_CFATA_REG(0x1990)
++#define S3C_ATA_FIFO_STATUS S3C_CFATA_REG(0x1994)
++
++#endif /* __ASM_ARM_REGS_NAND */
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
+index 498184c..0481bd5 100644
+--- a/include/asm-arm/arch-s3c2410/regs-irq.h
++++ b/include/asm-arm/arch-s3c2410/regs-irq.h
+@@ -10,7 +10,7 @@
+
+
+ #ifndef ___ASM_ARCH_REGS_IRQ_H
+-#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
++#define ___ASM_ARCH_REGS_IRQ_H "$Id: regs-irq.h,v 1.2 2008/07/31 06:51:59 eyryu Exp $"
+
+ /* interrupt controller */
+
+@@ -21,12 +21,25 @@
+ #define S3C2410_SRCPND S3C2410_IRQREG(0x000)
+ #define S3C2410_INTMOD S3C2410_IRQREG(0x004)
+ #define S3C2410_INTMSK S3C2410_IRQREG(0x008)
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C2410_PRIORITY S3C2410_IRQREG(0x030)
++#else
+ #define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
++#endif
+ #define S3C2410_INTPND S3C2410_IRQREG(0x010)
+ #define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
+ #define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
+ #define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
+
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C2450_SRCPND S3C2410_IRQREG(0x040)
++#define S3C2450_INTMOD S3C2410_IRQREG(0x044)
++#define S3C2450_INTMSK S3C2410_IRQREG(0x048)
++#define S3C2450_INTPND S3C2410_IRQREG(0x050)
++#define S3C2450_INTOFFSET S3C2410_IRQREG(0x054)
++#define S3C2450_PRIORITY S3C2410_IRQREG(0x070)
++#endif
++
+ /* mask: 0=enable, 1=disable
+ * 1 bit EINT, 4=EINT4, 23=EINT23
+ * EINT0,1,2,3 are not handled here.
+@@ -40,4 +53,80 @@
+ #define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
+ #define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
+
++#if defined (CONFIG_PLAT_S3C64XX) || defined (CONFIG_PLAT_S5PC1XX)
++
++/* interrupt controller */
++#define S3C_VIC0REG(x) ((x) + S3C24XX_VA_IRQ)
++#define S3C_VIC1REG(x) ((x) + S3C24XX_VA_IRQ+0x100000)
++#define S3C_VIC2REG(x) ((x) + S3C24XX_VA_IRQ+0x200000)
++
++#define S3C_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
++
++#define S3C_EINT0CON0 S3C_EINTREG(0x900)
++#define S3C_EINT0MASK S3C_EINTREG(0x924)
++
++#define S3C_VIC0IRQSTATUS S3C_VIC0REG(0x000)
++#define S3C_VIC1IRQSTATUS S3C_VIC1REG(0x000)
++#define S3C_VIC2IRQSTATUS S3C_VIC2REG(0x000)
++
++#define S3C_VIC0FIQSTATUS S3C_VIC0REG(0x004)
++#define S3C_VIC1FIQSTATUS S3C_VIC1REG(0x004)
++#define S3C_VIC2FIQSTATUS S3C_VIC2REG(0x004)
++
++#define S3C_VIC0RAWINTR S3C_VIC0REG(0x008)
++#define S3C_VIC1RAWINTR S3C_VIC1REG(0x008)
++#define S3C_VIC2RAWINTR S3C_VIC2REG(0x008)
++
++#define S3C_VIC0INTSELECT S3C_VIC0REG(0x00C)
++#define S3C_VIC1INTSELECT S3C_VIC1REG(0x00C)
++#define S3C_VIC2INTSELECT S3C_VIC2REG(0x00C)
++
++#define S3C_VIC0INTENABLE S3C_VIC0REG(0x010)
++#define S3C_VIC1INTENABLE S3C_VIC1REG(0x010)
++#define S3C_VIC2INTENABLE S3C_VIC2REG(0x010)
++
++#define S3C_VIC0INTENCLEAR S3C_VIC0REG(0x014)
++#define S3C_VIC1INTENCLEAR S3C_VIC1REG(0x014)
++#define S3C_VIC2INTENCLEAR S3C_VIC2REG(0x014)
++
++#define S3C_VIC0SOFTINT S3C_VIC0REG(0x018)
++#define S3C_VIC1SOFTINT S3C_VIC1REG(0x018)
++#define S3C_VIC2SOFTINT S3C_VIC2REG(0x018)
++
++#define S3C_VIC0SOFTINTCLEAR S3C_VIC0REG(0x01C)
++#define S3C_VIC1SOFTINTCLEAR S3C_VIC1REG(0x01C)
++#define S3C_VIC2SOFTINTCLEAR S3C_VIC2REG(0x01C)
++
++#define S3C_VIC0PROTECTION S3C_VIC0REG(0x020)
++#define S3C_VIC1PROTECTION S3C_VIC1REG(0x020)
++#define S3C_VIC2PROTECTION S3C_VIC2REG(0x020)
++
++#define S3C_VIC0SWPRIORITYMASK S3C_VIC0REG(0x024)
++#define S3C_VIC1SWPRIORITYMASK S3C_VIC1REG(0x024)
++#define S3C_VIC2SWPRIORITYMASK S3C_VIC2REG(0x024)
++
++#define S3C_VIC0PRIORITYDAISY S3C_VIC0REG(0x028)
++#define S3C_VIC1PRIORITYDAISY S3C_VIC1REG(0x028)
++#define S3C_VIC2PRIORITYDAISY S3C_VIC2REG(0x028)
++
++#define S3C_VIC0VECTADDR0 S3C_VIC0REG(0x100)
++#define S3C_VIC1VECTADDR0 S3C_VIC1REG(0x100)
++#define S3C_VIC2VECTADDR0 S3C_VIC2REG(0x100)
++
++#define S3C_VIC0VECTADDR1 S3C_VIC0REG(0x104)
++#define S3C_VIC1VECTADDR1 S3C_VIC1REG(0x104)
++#define S3C_VIC2VECTADDR1 S3C_VIC2REG(0x104)
++
++#define S3C_VIC0VECTADDR2 S3C_VIC0REG(0x108)
++#define S3C_VIC1VECTADDR2 S3C_VIC1REG(0x108)
++#define S3C_VIC2VECTADDR2 S3C_VIC2REG(0x108)
++
++#define S3C_VIC0ADDRESS S3C_VIC0REG(0xF00)
++#define S3C_VIC1ADDRESS S3C_VIC1REG(0xF00)
++#define S3C_VIC2ADDRESS S3C_VIC2REG(0xF00)
++
++#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C_PRIORITY S3C2410_PRIORITY
++#endif
++
+ #endif /* ___ASM_ARCH_REGS_IRQ_H */
+diff --git a/include/asm-arm/arch-s3c2410/regs-keypad.h b/include/asm-arm/arch-s3c2410/regs-keypad.h
+new file mode 100644
+index 0000000..a513aeb
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-keypad.h
+@@ -0,0 +1,49 @@
++/* linux/include/asm/arch-s3c2460/regs-keyif.h
++ *
++ * $Id: regs-keypad.h,v 1.2 2008/02/21 11:18:55 jsgood Exp $
++ *
++ * S3C2460 Key Interface register definitions
++ *
++ * Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
++ * All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ *
++ */
++
++
++#ifndef __ASM_ARCH_REGS_KEYPAD_H
++#define __ASM_ARCH_REGS_KEYPAD_H
++
++/*
++ * Keypad Interface
++ */
++#define S3C_KEYPADREG(x) (x)
++//#define S3C_KEYPADREG(x) ((x) + S3C24XX_VA_KEYPAD)
++
++#define S3C_KEYIFCON S3C_KEYPADREG(0x00)
++#define S3C_KEYIFSTSCLR S3C_KEYPADREG(0x04)
++#define S3C_KEYIFCOL S3C_KEYPADREG(0x08)
++#define S3C_KEYIFROW S3C_KEYPADREG(0x0C)
++#define S3C_KEYIFFC S3C_KEYPADREG(0x10)
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#define KEYCOL_DMASK (0xff)
++#define KEYROW_DMASK (0xff)
++#define INT_F_EN (1<<0) /*falling edge(key-pressed) interuppt enable*/
++#define INT_R_EN (1<<1) /*rising edge(key-released) interuppt enable*/
++#define DF_EN (1<<2) /*debouncing filter enable*/
++#define FC_EN (1<<3) /*filter clock enable*/
++#define KEYIFCON_INIT (KEYIFCON_CLEAR |INT_F_EN|INT_R_EN|DF_EN|FC_EN)
++#define KEYIFSTSCLR_CLEAR (0xffff)
++
++#else
++#error "Not supported S3C Configuration!!"
++#endif
++
++#endif /* __ASM_ARCH_REGS_KEYPAD_H */
++
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
+index 76fe5f6..2f43563 100644
+--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
++++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
+@@ -10,7 +10,7 @@
+
+
+ #ifndef ___ASM_ARCH_REGS_LCD_H
+-#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
++#define ___ASM_ARCH_REGS_LCD_H "$Id: regs-lcd.h,v 1.6 2008/09/09 01:39:49 eyryu Exp $"
+
+ #define S3C2410_LCDREG(x) (x)
+
+@@ -147,6 +147,486 @@
+
+ #define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
+
++
++/***************************************************************************/
++/* LCD Registers for S3C2443/2450/S3C6400/6410 */
++#define S3C_LCDREG(x) ((x) + S3C24XX_VA_LCD)
++
++/* LCD control registers */
++#define S3C_VIDCON0 S3C_LCDREG(0x00) /* Video control 0 register */
++#define S3C_VIDCON1 S3C_LCDREG(0x04) /* Video control 1 register */
++
++
++#if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C_VIDTCON0 S3C_LCDREG(0x08) /* LCD CONTROL 1 */
++#define S3C_VIDTCON1 S3C_LCDREG(0x0C) /* LCD CONTROL 1 */
++#define S3C_VIDTCON2 S3C_LCDREG(0x10) /* LCD CONTROL 1 */
++#define S3C_WINCON0 S3C_LCDREG(0x14) /* LCD CONTROL 1 */
++#define S3C_WINCON1 S3C_LCDREG(0x18) /* LCD CONTROL 1 */
++#define S3C_VIDOSD0A S3C_LCDREG(0x28) /* LCD CONTROL 1 */
++#define S3C_VIDOSD0B S3C_LCDREG(0x2C) /* LCD CONTROL 1 */
++#define S3C_VIDOSD0C S3C_LCDREG(0x30) /* LCD CONTROL 1 */
++#define S3C_VIDOSD1A S3C_LCDREG(0x34) /* LCD CONTROL 1 */
++#define S3C_VIDOSD1B S3C_LCDREG(0x38) /* LCD CONTROL 1 */
++#define S3C_VIDOSD1C S3C_LCDREG(0x3C) /* LCD CONTROL 1 */
++#define S3C_VIDW00ADD0B0 S3C_LCDREG(0x64) /* LCD CONTROL 1 */
++#define S3C_VIDW00ADD0B1 S3C_LCDREG(0x68) /* LCD CONTROL 1 */
++#define S3C_VIDW01ADD0 S3C_LCDREG(0x6C) /* LCD CONTROL 1 */
++#define S3C_VIDW00ADD1B0 S3C_LCDREG(0x7C) /* LCD CONTROL 1 */
++#define S3C_VIDW00ADD1B1 S3C_LCDREG(0x80) /* LCD CONTROL 1 */
++#define S3C_VIDW01ADD1 S3C_LCDREG(0x84) /* LCD CONTROL 1 */
++#define S3C_VIDW00ADD2B0 S3C_LCDREG(0x94) /* LCD CONTROL 1 */
++#define S3C_VIDW00ADD2B1 S3C_LCDREG(0x98) /* LCD CONTROL 1 */
++#define S3C_VIDW01ADD2 S3C_LCDREG(0x9C) /* LCD CONTROL 1 */
++#define S3C_VIDINTCON S3C_LCDREG(0xAC) /* LCD CONTROL 1 */
++#define S3C_W1KEYCON0 S3C_LCDREG(0xB0) /* LCD CONTROL 1 */
++#define S3C_W1KEYCON1 S3C_LCDREG(0xB4) /* LCD CONTROL 1 */
++#define S3C_WIN0MAP S3C_LCDREG(0xD0) /* LCD CONTROL 1 */
++#define S3C_WIN1MAP S3C_LCDREG(0xD4) /* LCD CONTROL 1 */
++#define S3C_WPALCON S3C_LCDREG(0xE4) /* LCD CONTROL 1 */
++#define S3C_SYSIFCON0 S3C_LCDREG(0x130) /* LCD CONTROL 1 */
++#define S3C_SYSIFCON1 S3C_LCDREG(0x134) /* LCD CONTROL 1 */
++#define S3C_DITHMODE S3C_LCDREG(0x138) /* LCD CONTROL 1 */
++#define S3C_SIFCCON0 S3C_LCDREG(0x13C) /* LCD CONTROL 1 */
++#define S3C_SIFCCON1 S3C_LCDREG(0x140) /* LCD CONTROL 1 */
++#define S3C_SIFCCON2 S3C_LCDREG(0x144) /* LCD CONTROL 1 */
++#define S3C_CPUTRIGCON2 S3C_LCDREG(0x160) /* LCD CONTROL 1 */
++
++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100)
++#define S3C_VIDCON2 S3C_LCDREG(0x08) /* Video control 2 register */
++#define S3C_VIDTCON0 S3C_LCDREG(0x10) /* Video time control 0 register */
++#define S3C_VIDTCON1 S3C_LCDREG(0x14) /* Video time control 1 register */
++#define S3C_VIDTCON2 S3C_LCDREG(0x18) /* Video time control 2 register */
++#define S3C_VIDTCON3 S3C_LCDREG(0x1C) /* Video time control 3 register */
++
++#define S3C_WINCON0 S3C_LCDREG(0x20) /* Window control 0 register */
++#define S3C_WINCON1 S3C_LCDREG(0x24) /* Window control 1 register */
++#define S3C_WINCON2 S3C_LCDREG(0x28) /* Window control 2 register */
++#define S3C_WINCON3 S3C_LCDREG(0x2C) /* Window control 3 register */
++#define S3C_WINCON4 S3C_LCDREG(0x30) /* Window control 4 register*/
++
++
++#define S3C_VIDOSD0A S3C_LCDREG(0x40) /* Video Window 0 position control register */
++#define S3C_VIDOSD0B S3C_LCDREG(0x44) /* Video Window 0 position control register1 */
++#define S3C_VIDOSD0C S3C_LCDREG(0x48) /* Video Window 0 position control register */
++
++#define S3C_VIDOSD1A S3C_LCDREG(0x50) /* Video Window 1 position control register */
++#define S3C_VIDOSD1B S3C_LCDREG(0x54) /* Video Window 1 position control register */
++#define S3C_VIDOSD1C S3C_LCDREG(0x58) /* Video Window 1 position control register */
++#define S3C_VIDOSD1D S3C_LCDREG(0x5C) /* Video Window 1 position control register */
++
++#define S3C_VIDOSD2A S3C_LCDREG(0x60) /* Video Window 2 position control register */
++#define S3C_VIDOSD2B S3C_LCDREG(0x64) /* Video Window 2 position control register */
++#define S3C_VIDOSD2C S3C_LCDREG(0x68) /* Video Window 2 position control register */
++#define S3C_VIDOSD2D S3C_LCDREG(0x6C) /* Video Window 2 position control register */
++
++#define S3C_VIDOSD3A S3C_LCDREG(0x70) /* Video Window 3 position control register */
++#define S3C_VIDOSD3B S3C_LCDREG(0x74) /* Video Window 3 position control register */
++#define S3C_VIDOSD3C S3C_LCDREG(0x78) /* Video Window 3 position control register */
++
++#define S3C_VIDOSD4A S3C_LCDREG(0x80) /* Video Window 4 position control register */
++#define S3C_VIDOSD4B S3C_LCDREG(0x84) /* Video Window 4 position control register */
++#define S3C_VIDOSD4C S3C_LCDREG(0x88) /* Video Window 4 position control register */
++
++#define S3C_VIDW00ADD2B0 S3C_LCDREG(0x94) /* LCD CONTROL 1 */
++#define S3C_VIDW00ADD2B1 S3C_LCDREG(0x98) /* LCD CONTROL 1 */
++
++#define S3C_VIDW00ADD0B0 S3C_LCDREG(0x0A0) /* Window 0 buffer start address register, buffer 0 */
++#define S3C_VIDW00ADD0B1 S3C_LCDREG(0x0A4) /* Window 0 buffer start address register, buffer 1 */
++#define S3C_VIDW01ADD0B0 S3C_LCDREG(0x0A8) /* Window 1 buffer start address register, buffer 0 */
++#define S3C_VIDW01ADD0B1 S3C_LCDREG(0x0AC) /* Window 1 buffer start address register, buffer 1 */
++#define S3C_VIDW02ADD0 S3C_LCDREG(0x0B0) /* Window 2 buffer start address register */
++#define S3C_VIDW03ADD0 S3C_LCDREG(0x0B8) /* Window 3 buffer start address register */
++#define S3C_VIDW04ADD0 S3C_LCDREG(0x0C0) /* Window 4 buffer start address register */
++#define S3C_VIDW00ADD1B0 S3C_LCDREG(0x0D0) /* Window 0 buffer end address register, buffer 0 */
++#define S3C_VIDW00ADD1B1 S3C_LCDREG(0x0D4) /* Window 0 buffer end address register, buffer 1 */
++#define S3C_VIDW01ADD1B0 S3C_LCDREG(0x0D8) /* Window 1 buffer end address register, buffer 0 */
++#define S3C_VIDW01ADD1B1 S3C_LCDREG(0x0DC) /* Window 1 buffer end address register, buffer 1 */
++#define S3C_VIDW02ADD1 S3C_LCDREG(0x0E0) /* Window 2 buffer end address register */
++#define S3C_VIDW03ADD1 S3C_LCDREG(0x0E8) /* Window 3 buffer end address register */
++#define S3C_VIDW04ADD1 S3C_LCDREG(0x0F0) /* Window 4 buffer end address register */
++#define S3C_VIDW00ADD2 S3C_LCDREG(0x100) /* Window 0 buffer size register */
++#define S3C_VIDW01ADD2 S3C_LCDREG(0x104) /* Window 1 buffer size register */
++
++#define S3C_VIDW02ADD2 S3C_LCDREG(0x108) /* Window 2 buffer size register */
++#define S3C_VIDW03ADD2 S3C_LCDREG(0x10C) /* Window 3 buffer size register */
++#define S3C_VIDW04ADD2 S3C_LCDREG(0x110) /* Window 4 buffer size register */
++
++#define S3C_VIDINTCON0 S3C_LCDREG(0x130) /* Indicate the Video interrupt control register */
++#define S3C_VIDINTCON1 S3C_LCDREG(0x134) /* Video Interrupt Pending register */
++#define S3C_W1KEYCON0 S3C_LCDREG(0x140) /* Color key control register */
++#define S3C_W1KEYCON1 S3C_LCDREG(0x144) /* Color key value ( transparent value) register */
++#define S3C_W2KEYCON0 S3C_LCDREG(0x148) /* Color key control register */
++#define S3C_W2KEYCON1 S3C_LCDREG(0x14C) /* Color key value (transparent value) register */
++
++#define S3C_W3KEYCON0 S3C_LCDREG(0x150) /* Color key control register */
++#define S3C_W3KEYCON1 S3C_LCDREG(0x154) /* Color key value (transparent value) register */
++#define S3C_W4KEYCON0 S3C_LCDREG(0x158) /* Color key control register */
++#define S3C_W4KEYCON1 S3C_LCDREG(0x15C) /* Color key value (transparent value) register */
++#define S3C_DITHMODE S3C_LCDREG(0x170) /* Dithering mode register. */
++
++#define S3C_WIN0MAP S3C_LCDREG(0x180) /* Window color control */
++#define S3C_WIN1MAP S3C_LCDREG(0x184) /* Window color control */
++#define S3C_WIN2MAP S3C_LCDREG(0x188) /* Window color control */
++#define S3C_WIN3MAP S3C_LCDREG(0x18C) /* Window color control */
++#define S3C_WIN4MAP S3C_LCDREG(0x190) /* Window color control */
++#define S3C_WPALCON S3C_LCDREG(0x1A0) /* Window Palette control register */
++
++#define S3C_TRIGCON S3C_LCDREG(0x1A4) /* I80 / RGB Trigger Control Regiter */
++#define S3C_I80IFCONA0 S3C_LCDREG(0x1B0) /* I80 Interface control 0 for Main LDI */
++#define S3C_I80IFCONA1 S3C_LCDREG(0x1B4) /* I80 Interface control 0 for Sub LDI */
++#define S3C_I80IFCONB0 S3C_LCDREG(0x1B8) /* I80 Inteface control 1 for Main LDI */
++#define S3C_I80IFCONB1 S3C_LCDREG(0x1BC) /* I80 Inteface control 1 for Sub LDI */
++#define S3C_LDI_CMDCON0 S3C_LCDREG(0x1D0) /* I80 Interface LDI Command Control 0 */
++#define S3C_LDI_CMDCON1 S3C_LCDREG(0x1D4) /* I80 Interface LDI Command Control 1 */
++#define S3C_SIFCCON0 S3C_LCDREG(0x1E0) /* LCD i80 System Interface Command Control 0 */
++#define S3C_SIFCCON1 S3C_LCDREG(0x1E4) /* LCD i80 System Interface Command Control 1 */
++#define S3C_SIFCCON2 S3C_LCDREG(0x1E8) /* LCD i80 System Interface Command Control 2 */
++
++#define S3C_LDI_CMD0 S3C_LCDREG(0x280) /* I80 Inteface LDI Command 0 */
++#define S3C_LDI_CMD1 S3C_LCDREG(0x284) /* I80 Inteface LDI Command 1 */
++#define S3C_LDI_CMD2 S3C_LCDREG(0x288) /* I80 Inteface LDI Command 2 */
++#define S3C_LDI_CMD3 S3C_LCDREG(0x28C) /* I80 Inteface LDI Command 3 */
++#define S3C_LDI_CMD4 S3C_LCDREG(0x290) /* I80 Inteface LDI Command 4 */
++#define S3C_LDI_CMD5 S3C_LCDREG(0x294) /* I80 Inteface LDI Command 5 */
++#define S3C_LDI_CMD6 S3C_LCDREG(0x298) /* I80 Inteface LDI Command 6 */
++#define S3C_LDI_CMD7 S3C_LCDREG(0x29C) /* I80 Inteface LDI Command 7 */
++#define S3C_LDI_CMD8 S3C_LCDREG(0x2A0) /* I80 Inteface LDI Command 8 */
++#define S3C_LDI_CMD9 S3C_LCDREG(0x2A4) /* I80 Inteface LDI Command 9 */
++#define S3C_LDI_CMD10 S3C_LCDREG(0x2A8) /* I80 Inteface LDI Command 10 */
++#define S3C_LDI_CMD11 S3C_LCDREG(0x2AC) /* I80 Inteface LDI Command 11 */
++
++#define S3C_W2PDATA01 S3C_LCDREG(0x300) /* Window 2 Palette Data of the Index 0,1 */
++#define S3C_W2PDATA23 S3C_LCDREG(0x304) /* Window 2 Palette Data of the Index 2,3 */
++#define S3C_W2PDATA45 S3C_LCDREG(0x308) /* Window 2 Palette Data of the Index 4,5 */
++#define S3C_W2PDATA67 S3C_LCDREG(0x30C) /* Window 2 Palette Data of the Index 6,7 */
++#define S3C_W2PDATA89 S3C_LCDREG(0x310) /* Window 2 Palette Data of the Index 8,9 */
++#define S3C_W2PDATAAB S3C_LCDREG(0x314) /* Window 2 Palette Data of the Index A, B */
++#define S3C_W2PDATACD S3C_LCDREG(0x318) /* Window 2 Palette Data of the Index C, D */
++#define S3C_W2PDATAEF S3C_LCDREG(0x31C) /* Window 2 Palette Data of the Index E, F */
++#define S3C_W3PDATA01 S3C_LCDREG(0x320) /* Window 3 Palette Data of the Index 0,1 */
++#define S3C_W3PDATA23 S3C_LCDREG(0x324) /* Window 3 Palette Data of the Index 2,3 */
++#define S3C_W3PDATA45 S3C_LCDREG(0x328) /* Window 3 Palette Data of the Index 4,5 */
++#define S3C_W3PDATA67 S3C_LCDREG(0x32C) /* Window 3 Palette Data of the Index 6,7 */
++#define S3C_W3PDATA89 S3C_LCDREG(0x330) /* Window 3 Palette Data of the Index 8,9 */
++#define S3C_W3PDATAAB S3C_LCDREG(0x334) /* Window 3 Palette Data of the Index A, B */
++#define S3C_W3PDATACD S3C_LCDREG(0x338) /* Window 3 Palette Data of the Index C, D */
++#define S3C_W3PDATAEF S3C_LCDREG(0x33C) /* Window 3 Palette Data of the Index E, F */
++#define S3C_W4PDATA01 S3C_LCDREG(0x340) /* Window 3 Palette Data of the Index 0,1 */
++#define S3C_W4PDATA23 S3C_LCDREG(0x344) /* Window 3 Palette Data of the Index 2,3 */
++#endif
++
++#define S3C_TFTPAL2(x) S3C_LCDREG((0x300 + (x)*4))
++#define S3C_TFTPAL3(x) S3C_LCDREG((0x320 + (x)*4))
++#define S3C_TFTPAL4(x) S3C_LCDREG((0x340 + (x)*4))
++#define S3C_TFTPAL0(x) S3C_LCDREG((0x400 + (x)*4))
++#define S3C_TFTPAL1(x) S3C_LCDREG((0x800 + (x)*4))
++
++/*--------------------------------------------------------------*/
++/* Video Main Control 0 register - VIDCON0 */
++#define S3C_VIDCON0_INTERLACE_F_PROGRESSIVE (0<<29)
++#define S3C_VIDCON0_INTERLACE_F_INTERLACE (1<<29)
++#define S3C_VIDCON0_VIDOUT(x) (((x)&0x7)<<26)
++#define S3C_VIDCON0_VIDOUT_RGB_IF (0<<26)
++#define S3C_VIDCON0_VIDOUT_TV (1<<26)
++#define S3C_VIDCON0_VIDOUT_I80IF0 (2<<26)
++#define S3C_VIDCON0_VIDOUT_I80IF1 (3<<26)
++#define S3C_VIDCON0_VIDOUT_TVNRGBIF (4<<26)
++#define S3C_VIDCON0_VIDOUT_TVNI80IF0 (6<<26)
++#define S3C_VIDCON0_VIDOUT_TVNI80IF1 (7<<26)
++#define S3C_VIDCON0_L1_DATA16(x) (((x)&0x7)<<23)
++#define S3C_VIDCON0_L1_DATA16_SUB_16_MODE (0<<23)
++#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS2_MODE (1<<23)
++#define S3C_VIDCON0_L1_DATA16_SUB_9PLUS9_MODE (2<<23)
++#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE (3<<23)
++#define S3C_VIDCON0_L1_DATA16_SUB_18_MODE (4<<23)
++#define S3C_VIDCON0_L0_DATA16(x) (((x)&0x7)<<20)
++#define S3C_VIDCON0_L0_DATA16_MAIN_16_MODE (0<<20)
++#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS2_MODE (1<<20)
++#define S3C_VIDCON0_L0_DATA16_MAIN_9PLUS9_MODE (2<<20)
++#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE (3<<20)
++#define S3C_VIDCON0_L0_DATA16_MAIN_18_MODE (4<<20)
++#define S3C_VIDCON0_PNRMODE(x) (((x)&0x3)<<17)
++#define S3C_VIDCON0_PNRMODE_RGB_P (0<<17)
++#define S3C_VIDCON0_PNRMODE_BGR_P (1<<17)
++#define S3C_VIDCON0_PNRMODE_RGB_S (2<<17)
++#define S3C_VIDCON0_PNRMODE_BGR_S (3<<17)
++#define S3C_VIDCON0_PNRMODE_MASK (3<<17)
++#define S3C_VIDCON0_CLKVALUP_ALWAYS (0<<16)
++#define S3C_VIDCON0_CLKVALUP_ST_FRM (1<<16)
++#define S3C_VIDCON0_CLKVAL_F(x) (((x)&0xFF)<<6)
++#define S3C_VIDCON0_VCLKEN_ENABLE (1<<5)
++#define S3C_VIDCON0_CLKDIR_DIVIDED (1<<4)
++#define S3C_VIDCON0_CLKDIR_DIRECTED (0<<4)
++#define S3C_VIDCON0_CLKSEL(x) (((x)&0x3)<<2)
++#define S3C_VIDCON0_CLKSEL_F_HCLK (0<<2)
++#define S3C_VIDCON0_ENVID_ENABLE (1 << 1) /* 0:Disable 1:Enable LCD video output and logic immediatly */
++#define S3C_VIDCON0_ENVID_DISABLE (0 << 1) /* 0:Disable 1:Enable LCD video output and logic immediatly */
++#define S3C_VIDCON0_ENVID_F_ENABLE (1 << 0) /* 0:Dis 1:Ena wait until Current frame end. */
++#define S3C_VIDCON0_ENVID_F_DISABLE (0 << 0) /* 0:Dis 1:Ena wait until Current frame end. */
++
++/* Video Main Control 1 register - VIDCON1 */
++#define S3C_VIDCON1_IVCLK_FALL_EDGE (0<<7)
++#define S3C_VIDCON1_IVCLK_RISE_EDGE (1<<7)
++#define S3C_VIDCON1_IHSYNC_NORMAL (0<<6)
++#define S3C_VIDCON1_IHSYNC_INVERT (1<<6)
++#define S3C_VIDCON1_IVSYNC_NORMAL (0<<5)
++#define S3C_VIDCON1_IVSYNC_INVERT (1<<5)
++#define S3C_VIDCON1_IVDEN_NORMAL (0<<4)
++#define S3C_VIDCON1_IVDEN_INVERT (1<<4)
++
++/* Video Main Control 2 register - VIDCON2 */
++#define S3C_VIDCON2_TVLFFORMAT(x) (((x)&0x7)<<7)
++
++/* VIDEO Time Control 0 register - VIDTCON0 */
++#define S3C_VIDTCON0_VBPDE(x) (((x)&0xFF)<<24)
++#define S3C_VIDTCON0_VBPD(x) (((x)&0xFF)<<16)
++#define S3C_VIDTCON0_VFPD(x) (((x)&0xFF)<<8)
++#define S3C_VIDTCON0_VSPW(x) (((x)&0xFF)<<0)
++
++/* VIDEO Time Control 1 register - VIDTCON1 */
++#define S3C_VIDTCON1_VFPDE(x) (((x)&0xFF)<<24)
++#define S3C_VIDTCON1_HBPD(x) (((x)&0xFF)<<16)
++#define S3C_VIDTCON1_HFPD(x) (((x)&0xFF)<<8)
++#define S3C_VIDTCON1_HSPW(x) (((x)&0xFF)<<0)
++
++/* VIDEO Time Control 2 register - VIDTCON2 */
++#define S3C_VIDTCON2_LINEVAL(x) (((x)&0x7FF)<<11) /* these bits determine the vertical size of lcd panel */
++#define S3C_VIDTCON2_HOZVAL(x) (((x)&0x7FF)<<0) /* these bits determine the horizontal size of lcd panel*/
++
++
++/* Window 0~4 Control register - WINCONx */
++#define S3C_WINCONx_WIDE_NARROW(x) (((x)&0x3)<<26)
++#define S3C_WINCONx_ENLOCAL_DMA (0<<22)
++#define S3C_WINCONx_ENLOCAL_POST (1<<22)
++#define S3C_WINCONx_BUFSEL_0 (0<<20)
++#define S3C_WINCONx_BUFSEL_1 (1<<20)
++#define S3C_WINCONx_BUF_MASK (1<<20)
++#define S3C_WINCONx_BUFAUTOEN_DISABLE (0<<19)
++#define S3C_WINCONx_BUFAUTOEN_ENABLE (1<<19)
++#define S3C_WINCONx_BUFAUTOEN_MASK (1<<19)
++#define S3C_WINCONx_BITSWP_DISABLE (0<<18)
++#define S3C_WINCONx_BITSWP_ENABLE (1<<18)
++#define S3C_WINCONx_BYTSWP_DISABLE (0<<17)
++#define S3C_WINCONx_BYTSWP_ENABLE (1<<17)
++#define S3C_WINCONx_HAWSWP_DISABLE (0<<16)
++#define S3C_WINCONx_HAWSWP_ENABLE (1<<16)
++#define S3C_WINCONx_INRGB_RGB (0<<13)
++#define S3C_WINCONx_INRGB_YUV (1<<13)
++#define S3C_WINCONx_INRGB_MASK (1<<13)
++#define S3C_WINCONx_BURSTLEN_16WORD (0<<9)
++#define S3C_WINCONx_BURSTLEN_8WORD (1<<9)
++#define S3C_WINCONx_BURSTLEN_4WORD (2<<9)
++#define S3C_WINCONx_BLD_PIX_PLANE (0<<6)
++#define S3C_WINCONx_BLD_PIX_PIXEL (1<<6)
++#define S3C_WINCONx_BLD_PIX_MASK (1<<6)
++#define S3C_WINCONx_BPPMODE_F_1BPP (0<<2)
++#define S3C_WINCONx_BPPMODE_F_2BPP (1<<2)
++#define S3C_WINCONx_BPPMODE_F_4BPP (2<<2)
++#define S3C_WINCONx_BPPMODE_F_8BPP_PAL (3<<2)
++#define S3C_WINCONx_BPPMODE_F_8BPP_NOPAL (4<<2)
++#define S3C_WINCONx_BPPMODE_F_16BPP_565 (5<<2)
++#define S3C_WINCONx_BPPMODE_F_16BPP_A555 (6<<2)
++#define S3C_WINCONx_BPPMODE_F_18BPP_666 (8<<2)
++#define S3C_WINCONx_BPPMODE_F_24BPP_888 (11<<2)
++#define S3C_WINCONx_BPPMODE_F_24BPP_A887 (0xc<<2)
++#define S3C_WINCONx_BPPMODE_F_25BPP_A888 (0xd<<2)
++#define S3C_WINCONx_BPPMODE_F_28BPP_A888 (0xd<<2)
++#define S3C_WINCONx_BPPMODE_F_MASK (0xf<<2)
++#define S3C_WINCONx_ALPHA_SEL_0 (0<<1)
++#define S3C_WINCONx_ALPHA_SEL_1 (1<<1)
++#define S3C_WINCONx_ALPHA_SEL_MASK (1<<1)
++#define S3C_WINCONx_ENWIN_F_DISABLE (0<<0)
++#define S3C_WINCONx_ENWIN_F_ENABLE (1<<0)
++
++/* Window 1-2 Control register - WINCON1 */
++#define S3C_WINCON1_LOCALSEL_TV (0<<23)
++#define S3C_WINCON1_LOCALSEL_CAMERA (1<<23)
++#define S3C_WINCON2_LOCALSEL_TV (0<<23)
++#define S3C_WINCON2_LOCALSEL_CAMERA (1<<23)
++
++/* Window 0~4 Position Control A register - VIDOSDxA */
++#define S3C_VIDOSDxA_OSD_LTX_F(x) (((x)&0x7FF)<<11)
++#define S3C_VIDOSDxA_OSD_LTY_F(x) (((x)&0x7FF)<<0)
++
++/* Window 0~4 Position Control B register - VIDOSDxB */
++#define S3C_VIDOSDxB_OSD_RBX_F(x) (((x)&0x7FF)<<11)
++#define S3C_VIDOSDxB_OSD_RBY_F(x) (((x)&0x7FF)<<0)
++
++/* Window 0 Position Control C register - VIDOSD0C */
++#define S3C_VIDOSD0C_OSDSIZE(x) (((x)&0xFFFFFF)<<0)
++
++/* Window 1~4 Position Control C register - VIDOSDxC */
++#define S3C_VIDOSDxC_ALPHA0_R(x) (((x)&0xF)<<20)
++#define S3C_VIDOSDxC_ALPHA0_G(x) (((x)&0xF)<<16)
++#define S3C_VIDOSDxC_ALPHA0_B(x) (((x)&0xF)<<12)
++#define S3C_VIDOSDxC_ALPHA1_R(x) (((x)&0xF)<<8)
++#define S3C_VIDOSDxC_ALPHA1_G(x) (((x)&0xF)<<4)
++#define S3C_VIDOSDxC_ALPHA1_B(x) (((x)&0xF)<<0)
++
++/* Window 1~2 Position Control D register - VIDOSDxD */
++#define S3C_VIDOSDxD_OSDSIZE(x) (((x)&0xFFFFFF)<<0)
++
++/* Frame buffer Start Address register - VIDWxxADD0 */
++#define S3C_VIDWxxADD0_VBANK_F(x) (((x)&0xFF)<<23) /* the end address of the LCD frame buffer. */
++#define S3C_VIDWxxADD0_VBASEU_F(x) (((x)&0xFFFFFF)<<0) /* Virtual screen offset size (the number of byte). */
++
++/* Frame buffer End Address register - VIDWxxADD1 */
++#define S3C_VIDWxxADD1_VBASEL_F(x) (((x)&0xFFFFFF)<<0) /* the end address of the LCD frame buffer. */
++
++/* Frame buffer Size register - VIDWxxADD2 */
++#define S3C_VIDWxxADD2_OFFSIZE_F(x) (((x)&0x1FFF)<<13) /* Virtual screen offset size (the number of byte). */
++#define S3C_VIDWxxADD2_PAGEWIDTH_F(x) (((x)&0x1FFF)<<0) /* Virtual screen page width (the number of byte). */
++
++/* VIDEO Interrupt Control 0 register - VIDINTCON0 */
++#define S3C_VIDINTCON0_FIFOINTERVAL(x) (((x)&0x3F)<<20)
++#define S3C_VIDINTCON0_SYSMAINCON_DISABLE (0<<19)
++#define S3C_VIDINTCON0_SYSMAINCON_ENABLE (1<<19)
++#define S3C_VIDINTCON0_SYSSUBCON_DISABLE (0<<18)
++#define S3C_VIDINTCON0_SYSSUBCON_ENABLE (1<<18)
++#define S3C_VIDINTCON0_SYSIFDONE_DISABLE (0<<17)
++#define S3C_VIDINTCON0_SYSIFDONE_ENABLE (1<<17)
++#define S3C_VIDINTCON0_FRAMESEL0_BACK (0<<15)
++#define S3C_VIDINTCON0_FRAMESEL0_VSYNC (1<<15)
++#define S3C_VIDINTCON0_FRAMESEL0_ACTIVE (2<<15)
++#define S3C_VIDINTCON0_FRAMESEL0_FRONT (3<<15)
++#define S3C_VIDINTCON0_FRAMESEL0_MASK (3<<15)
++#define S3C_VIDINTCON0_FRAMESEL1_NONE (0<<13)
++#define S3C_VIDINTCON0_FRAMESEL1_BACK (1<<13)
++#define S3C_VIDINTCON0_FRAMESEL1_VSYNC (2<<13)
++#define S3C_VIDINTCON0_FRAMESEL1_FRONT (3<<13)
++#define S3C_VIDINTCON0_INTFRMEN_DISABLE (0<<12)
++#define S3C_VIDINTCON0_INTFRMEN_ENABLE (1<<12)
++#define S3C_VIDINTCON0_FRAMEINT_MASK (0x1F<<12)
++#define S3C_VIDINTCON0_FIFOSEL_WIN4 (1<<11)
++#define S3C_VIDINTCON0_FIFOSEL_WIN3 (1<<10)
++#define S3C_VIDINTCON0_FIFOSEL_WIN2 (1<<9)
++#define S3C_VIDINTCON0_FIFOSEL_WIN1 (1<<6)
++#define S3C_VIDINTCON0_FIFOSEL_WIN0 (1<<5)
++#define S3C_VIDINTCON0_FIFOSEL_ALL (0x73<<5)
++#define S3C_VIDINTCON0_FIFOLEVEL_25 (0<<2)
++#define S3C_VIDINTCON0_FIFOLEVEL_50 (1<<2)
++#define S3C_VIDINTCON0_FIFOLEVEL_75 (2<<2)
++#define S3C_VIDINTCON0_FIFOLEVEL_EMPTY (3<<2)
++#define S3C_VIDINTCON0_FIFOLEVEL_FULL (4<<2)
++#define S3C_VIDINTCON0_INTFIFOEN_DISABLE (0<<1)
++#define S3C_VIDINTCON0_INTFIFOEN_ENABLE (1<<1)
++#define S3C_VIDINTCON0_INTEN_DISABLE (0<<0)
++#define S3C_VIDINTCON0_INTEN_ENABLE (1<<0)
++#define S3C_VIDINTCON0_INTEN_MASK (1<<0)
++
++/* VIDEO Interrupt Control 1 register - VIDINTCON1 */
++#define S3C_VIDINTCON1_INTI80PEND (0<<2)
++#define S3C_VIDINTCON1_INTFRMPEND (1<<1)
++#define S3C_VIDINTCON1_INTFIFOPEND (1<<0)
++
++/* WIN 1~4 Color Key 0 register - WxKEYCON0 */
++#define S3C_WxKEYCON0_KEYBLEN_DISABLE (0<<26)
++#define S3C_WxKEYCON0_KEYBLEN_ENABLE (1<<26)
++#define S3C_WxKEYCON0_KEYEN_F_DISABLE (0<<25)
++#define S3C_WxKEYCON0_KEYEN_F_ENABLE (1<<25)
++#define S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE (0<<24)
++#define S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE (1<<24)
++#define S3C_WxKEYCON0_COMPKEY(x) (((x)&0xFFFFFF)<<0)
++
++/* WIN 1~4 Color Key 1 register - WxKEYCON1 */
++#define S3C_WxKEYCON1_COLVAL(x) (((x)&0xFFFFFF)<<0)
++
++/* Dithering Control 1 register - DITHMODE */
++#define S3C_DITHMODE_RDITHPOS_8BIT (0<<5)
++#define S3C_DITHMODE_RDITHPOS_6BIT (1<<5)
++#define S3C_DITHMODE_RDITHPOS_5BIT (2<<5)
++#define S3C_DITHMODE_GDITHPOS_8BIT (0<<3)
++#define S3C_DITHMODE_GDITHPOS_6BIT (1<<3)
++#define S3C_DITHMODE_GDITHPOS_5BIT (2<<3)
++#define S3C_DITHMODE_BDITHPOS_8BIT (0<<1)
++#define S3C_DITHMODE_BDITHPOS_6BIT (1<<1)
++#define S3C_DITHMODE_BDITHPOS_5BIT (2<<1)
++#define S3C_DITHMODE_RGB_DITHPOS_MASK (0x3f<<1)
++#define S3C_DITHMODE_DITHERING_DISABLE (0<<0)
++#define S3C_DITHMODE_DITHERING_ENABLE (1<<0)
++#define S3C_DITHMODE_DITHERING_MASK (1<<0)
++
++/* Window 0~4 Color map register - WINxMAP */
++#define S3C_WINxMAP_MAPCOLEN_F_ENABLE (1<<24)
++#define S3C_WINxMAP_MAPCOLEN_F_DISABLE (0<<24)
++#define S3C_WINxMAP_MAPCOLOR (((x)&0xFFFFFF)<<0)
++
++/* Window Palette Control register - WPALCON */
++#define S3C_WPALCON_PALUPDATEEN (1<<9)
++#define S3C_WPALCON_W4PAL_16BIT_A (1<<8) /* A:5:5:5 */
++#define S3C_WPALCON_W4PAL_16BIT (0<<8) /* 5:6:5 */
++#define S3C_WPALCON_W3PAL_16BIT_A (1<<7) /* A:5:5:5 */
++#define S3C_WPALCON_W3PAL_16BIT (0<<7) /* 5:6:5 */
++#define S3C_WPALCON_W2PAL_16BIT_A (1<<6) /* A:5:5:5 */
++#define S3C_WPALCON_W2PAL_16BIT (0<<6) /* 5:6:5 */
++#define S3C_WPALCON_W1PAL_25BIT_A (0<<3) /* A:8:8:8 */
++#define S3C_WPALCON_W1PAL_24BIT (1<<3) /* 8:8:8 */
++#define S3C_WPALCON_W1PAL_19BIT_A (2<<3) /* A:6:6:6 */
++#define S3C_WPALCON_W1PAL_18BIT_A (3<<3) /* A:6:6:5 */
++#define S3C_WPALCON_W1PAL_18BIT (4<<3) /* 6:6:6 */
++#define S3C_WPALCON_W1PAL_16BIT_A (5<<3) /* A:5:5:5 */
++#define S3C_WPALCON_W1PAL_16BIT (6<<3) /* 5:6:5 */
++#define S3C_WPALCON_W0PAL_25BIT_A (0<<0) /* A:8:8:8 */
++#define S3C_WPALCON_W0PAL_24BIT (1<<0) /* 8:8:8 */
++#define S3C_WPALCON_W0PAL_19BIT_A (2<<0) /* A:6:6:6 */
++#define S3C_WPALCON_W0PAL_18BIT_A (3<<0) /* A:6:6:5 */
++#define S3C_WPALCON_W0PAL_18BIT (4<<0) /* 6:6:6 */
++#define S3C_WPALCON_W0PAL_16BIT_A (5<<0) /* A:5:5:5 */
++#define S3C_WPALCON_W0PAL_16BIT (6<<0) /* 5:6:5 */
++
++/* I80/RGB Trigger Control register - TRIGCON */
++#define S3C_TRIGCON_SWFRSTATUS_REQUESTED (1<<2)
++#define S3C_TRIGCON_SWFRSTATUS_NOT_REQUESTED (0<<2)
++#define S3C_TRIGCON_SWTRGCMD (1<<1)
++#define S3C_TRIGCON_TRGMODE_ENABLE (1<<0)
++#define S3C_TRIGCON_TRGMODE_DISABLE (0<<0)
++
++/* LCD I80 Interface Control 0 register - I80IFCONA0 */
++#define S3C_I80IFCONAx_LCD_CS_SETUP(x) (((x)&0xF)<<16)
++#define S3C_I80IFCONAx_LCD_WR_SETUP(x) (((x)&0xF)<<12)
++#define S3C_I80IFCONAx_LCD_WR_ACT(x) (((x)&0xF)<<8)
++#define S3C_I80IFCONAx_LCD_WR_HOLD(x) (((x)&0xF)<<4)
++
++
++/***************************************************************************/
++/*HOST IF registers */
++/* Host I/F A - */
++#define S3C_HOSTIFAREG(x) ((x) + S3C24XX_VA_HOSTIFA)
++#define S3C_HOSTIFAREG_PHYS(x) ((x) + S3C24XX_PA_HOSTIFA)
++
++/* Host I/F B - Modem I/F */
++#define S3C_HOSTIFBREG(x) ((x) + S3C24XX_VA_HOSTIFB)
++#define S3C_HOSTIFBREG_PHYS(x) ((x) + S3C24XX_PA_HOSTIFB)
++
++#define S3C_HOSTIFB_INT2AP S3C_HOSTIFBREG(0x8000)
++#define S3C_HOSTIFB_INT2MSM S3C_HOSTIFBREG(0x8004)
++#define S3C_HOSTIFB_MIFCON S3C_HOSTIFBREG(0x8008)
++#define S3C_HOSTIFB_MIFPCON S3C_HOSTIFBREG(0x800C)
++#define S3C_HOSTIFB_MSMINTCLR S3C_HOSTIFBREG(0x8010)
++
++#define S3C_HOSTIFB_MIFCON_INT2MSM_DIS (0x0<<3)
++#define S3C_HOSTIFB_MIFCON_INT2MSM_EN (0x1<<3)
++#define S3C_HOSTIFB_MIFCON_INT2AP_DIS (0x0<<2)
++#define S3C_HOSTIFB_MIFCON_INT2AP_EN (0x1<<2)
++#define S3C_HOSTIFB_MIFCON_WAKEUP_DIS (0x0<<1)
++#define S3C_HOSTIFB_MIFCON_WAKEUP_EN (0x1<<1)
++
++#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_OUT (0x0<<5)
++#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_IN (0x1<<5)
++#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_DIS (0x0<<4)
++#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_EN (0x1<<4)
++#define S3C_HOSTIFB_MIFPCON_SEL_NORMAL (0x0<<3)
++#define S3C_HOSTIFB_MIFPCON_SEL_BYPASS (0x1<<3)
++
++#define S3C_HOSTIFB_MIFPCON_SEL_RS0 0
++#define S3C_HOSTIFB_MIFPCON_SEL_RS1 1
++#define S3C_HOSTIFB_MIFPCON_SEL_RS2 2
++#define S3C_HOSTIFB_MIFPCON_SEL_RS3 3
++#define S3C_HOSTIFB_MIFPCON_SEL_RS4 4
++#define S3C_HOSTIFB_MIFPCON_SEL_RS5 5
++#define S3C_HOSTIFB_MIFPCON_SEL_RS6 6
++
+ #endif /* ___ASM_ARCH_REGS_LCD_H */
+
+
+diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
+index e4d8234..3da2681 100644
+--- a/include/asm-arm/arch-s3c2410/regs-mem.h
++++ b/include/asm-arm/arch-s3c2410/regs-mem.h
+@@ -11,7 +11,7 @@
+ */
+
+ #ifndef __ASM_ARM_MEMREGS_H
+-#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
++#define __ASM_ARM_MEMREGS_H "$Id: regs-mem.h,v 1.2 2008/02/22 03:01:30 ihlee215 Exp $"
+
+ #ifndef S3C2410_MEMREG
+ #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+@@ -211,4 +211,122 @@
+ #define S3C2410_BANKSIZE_SCKE_EN (1<<5)
+ #define S3C2410_BANKSIZE_BURST (1<<7)
+
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C_SSMCREG(x) (S3C24XX_VA_SROMC + (x))
++
++/* Bank Idle Cycle Control Registers 0-5 */
++#define S3C_SSMC_SMBIDCYR0 S3C_SSMCREG(0x0000)
++#define S3C_SSMC_SMBIDCYR1 S3C_SSMCREG(0x0020)
++#define S3C_SSMC_SMBIDCYR2 S3C_SSMCREG(0x0040)
++#define S3C_SSMC_SMBIDCYR3 S3C_SSMCREG(0x0060)
++#define S3C_SSMC_SMBIDCYR4 S3C_SSMCREG(0x0080)
++#define S3C_SSMC_SMBIDCYR5 S3C_SSMCREG(0x00A0)
++#define S3C_SSMC_SMBIDCYR6 S3C_SSMCREG(0x00C0)
++#define S3C_SSMC_SMBIDCYR7 S3C_SSMCREG(0x00E0)
++
++/* Bank Read Wait State Contro, Registers 0-5 */
++#define S3C_SSMC_SMBWSTRDR0 S3C_SSMCREG(0x0004)
++#define S3C_SSMC_SMBWSTRDR1 S3C_SSMCREG(0x0024)
++#define S3C_SSMC_SMBWSTRDR2 S3C_SSMCREG(0x0044)
++#define S3C_SSMC_SMBWSTRDR3 S3C_SSMCREG(0x0064)
++#define S3C_SSMC_SMBWSTRDR4 S3C_SSMCREG(0x0084)
++#define S3C_SSMC_SMBWSTRDR5 S3C_SSMCREG(0x00A4)
++#define S3C_SSMC_SMBWSTRDR6 S3C_SSMCREG(0x00C4)
++#define S3C_SSMC_SMBWSTRDR7 S3C_SSMCREG(0x00E4)
++
++/* Bank Write Wait State Control, Registers 0-5 */
++#define S3C_SSMC_SMBWSTWRR0 S3C_SSMCREG(0x0008)
++#define S3C_SSMC_SMBWSTWRR1 S3C_SSMCREG(0x0028)
++#define S3C_SSMC_SMBWSTWRR2 S3C_SSMCREG(0x0048)
++#define S3C_SSMC_SMBWSTWRR3 S3C_SSMCREG(0x0068)
++#define S3C_SSMC_SMBWSTWRR4 S3C_SSMCREG(0x0088)
++#define S3C_SSMC_SMBWSTWRR5 S3C_SSMCREG(0x00A8)
++#define S3C_SSMC_SMBWSTWRR6 S3C_SSMCREG(0x00C8)
++#define S3C_SSMC_SMBWSTWRR7 S3C_SSMCREG(0x00E8)
++
++/* Bank OutPut enable Assertion Delay Control Registers 0-5 */
++#define S3C_SSMC_SMBWSTOENR0 S3C_SSMCREG(0x000C)
++#define S3C_SSMC_SMBWSTOENR1 S3C_SSMCREG(0x002C)
++#define S3C_SSMC_SMBWSTOENR2 S3C_SSMCREG(0x004C)
++#define S3C_SSMC_SMBWSTOENR3 S3C_SSMCREG(0x006C)
++#define S3C_SSMC_SMBWSTOENR4 S3C_SSMCREG(0x008C)
++#define S3C_SSMC_SMBWSTOENR5 S3C_SSMCREG(0x00AC)
++#define S3C_SSMC_SMBWSTOENR6 S3C_SSMCREG(0x00CC)
++#define S3C_SSMC_SMBWSTOENR7 S3C_SSMCREG(0x00EC)
++
++/* Bank Write enable Assertion Delay Control Registers 0-5 */
++#define S3C_SSMC_SMBWSTWENR0 S3C_SSMCREG(0x0010)
++#define S3C_SSMC_SMBWSTWENR1 S3C_SSMCREG(0x0030)
++#define S3C_SSMC_SMBWSTWENR2 S3C_SSMCREG(0x0050)
++#define S3C_SSMC_SMBWSTWENR3 S3C_SSMCREG(0x0070)
++#define S3C_SSMC_SMBWSTWENR4 S3C_SSMCREG(0x0090)
++#define S3C_SSMC_SMBWSTWENR5 S3C_SSMCREG(0x00B0)
++#define S3C_SSMC_SMBWSTWENR6 S3C_SSMCREG(0x00D0)
++#define S3C_SSMC_SMBWSTWENR7 S3C_SSMCREG(0x00F0)
++
++/* Bank Control Registers 0-5 */
++#define S3C_SSMC_SMBCR0 S3C_SSMCREG(0x0014)
++#define S3C_SSMC_SMBCR1 S3C_SSMCREG(0x0034)
++#define S3C_SSMC_SMBCR2 S3C_SSMCREG(0x0054)
++#define S3C_SSMC_SMBCR3 S3C_SSMCREG(0x0074)
++#define S3C_SSMC_SMBCR4 S3C_SSMCREG(0x0094)
++#define S3C_SSMC_SMBCR5 S3C_SSMCREG(0x00B4)
++#define S3C_SSMC_SMBCR6 S3C_SSMCREG(0x00D4)
++#define S3C_SSMC_SMBCR7 S3C_SSMCREG(0x00F4)
++
++/* Bank Status Registers 0-5 */
++#define S3C_SSMC_SMBSR0 S3C_SSMCREG(0x0018)
++#define S3C_SSMC_SMBSR1 S3C_SSMCREG(0x0038)
++#define S3C_SSMC_SMBSR2 S3C_SSMCREG(0x0058)
++#define S3C_SSMC_SMBSR3 S3C_SSMCREG(0x0078)
++#define S3C_SSMC_SMBSR4 S3C_SSMCREG(0x0098)
++#define S3C_SSMC_SMBSR5 S3C_SSMCREG(0x00B8)
++#define S3C_SSMC_SMBSR6 S3C_SSMCREG(0x00D8)
++#define S3C_SSMC_SMBSR7 S3C_SSMCREG(0x00F8)
++
++/* Bank Burst Read Wait delay Control Registers 0-5 */
++#define S3C_SSMC_SMBWSTBRDR0 S3C_SSMCREG(0x001C)
++#define S3C_SSMC_SMBWSTBRDR1 S3C_SSMCREG(0x003C)
++#define S3C_SSMC_SMBWSTBRDR2 S3C_SSMCREG(0x005C)
++#define S3C_SSMC_SMBWSTBRDR3 S3C_SSMCREG(0x007C)
++#define S3C_SSMC_SMBWSTBRDR4 S3C_SSMCREG(0x009C)
++#define S3C_SSMC_SMBWSTBRDR5 S3C_SSMCREG(0x00BC)
++#define S3C_SSMC_SMBWSTBRDR6 S3C_SSMCREG(0x00DC)
++#define S3C_SSMC_SMBWSTBRDR7 S3C_SSMCREG(0x00FC)
++
++/* SROMC status register */
++#define S3C_SSMC_SSMCSR S3C_SSMCREG(0x0200)
++/* SROMC control register */
++#define S3C_SSMC_SSMCCR S3C_SSMCREG(0x0204)
++
++#define S3C_EBIREG(x) (S3C24XX_VA_EBI + (x))
++
++/* bus priority decision */
++#define S3C_EBIPR S3C_EBIREG(0x0000)
++
++/* Bank configuration register */
++#define S3C_BANK_CFG S3C_EBIREG(0x0008)
++
++
++#endif
++
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++/* SROM */
++
++#ifndef S3C_MEMREG
++#define S3C_MEMREG(x) (S3C24XX_VA_SROMC + (x))
++#endif
++
++
++/* Bank Idle Cycle Control Registers 0-5 */
++#define S3C_SROM_BW S3C_MEMREG(0x00)
++
++#define S3C_SROM_BC0 S3C_MEMREG(0x04)
++#define S3C_SROM_BC1 S3C_MEMREG(0x08)
++#define S3C_SROM_BC2 S3C_MEMREG(0x0C)
++#define S3C_SROM_BC3 S3C_MEMREG(0x10)
++#define S3C_SROM_BC4 S3C_MEMREG(0x14)
++#define S3C_SROM_BC5 S3C_MEMREG(0x18)
++#endif
+ #endif /* __ASM_ARM_MEMREGS_H */
+diff --git a/include/asm-arm/arch-s3c2410/regs-onenand.h b/include/asm-arm/arch-s3c2410/regs-onenand.h
+new file mode 100644
+index 0000000..7803e29
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-onenand.h
+@@ -0,0 +1,358 @@
++#ifndef __ASM_ARCH_REGS_ONENAND_H
++#define __ASM_ARCH_REGS_ONENAND_H __FILE__
++
++/*
++ * DMA for OneNAND
++ */
++#define ONENAND_DMA_CON (0)
++#define ONENAND_DMA_BASE (0x75000000)
++#define ONENAND_DMA_TRANSFER_WORD (4)
++
++/*
++ * S3C6400 SFRs
++ */
++#define ONENAND_REG_MEM_CFG (0x000)
++#define ONENAND_REG_BURST_LEN (0x010)
++#define ONENAND_REG_MEM_RESET (0x020)
++#define ONENAND_REG_INT_ERR_STAT (0x030)
++#define ONENAND_REG_INT_ERR_MASK (0x040)
++#define ONENAND_REG_INT_ERR_ACK (0x050)
++#define ONENAND_REG_ECC_ERR_STAT (0x060)
++#define ONENAND_REG_MANUFACT_ID (0x070)
++#define ONENAND_REG_DEVICE_ID (0x080)
++#define ONENAND_REG_DATA_BUF_SIZE (0x090)
++#define ONENAND_REG_BOOT_BUF_SIZE (0x0A0)
++#define ONENAND_REG_BUF_AMOUNT (0x0B0)
++#define ONENAND_REG_TECH (0x0C0)
++#define ONENAND_REG_FBA_WIDTH (0x0D0)
++#define ONENAND_REG_FPA_WIDTH (0x0E0)
++#define ONENAND_REG_FSA_WIDTH (0x0F0)
++#define ONENAND_REG_REVISION (0x100)
++#define ONENAND_REG_DATARAM0 (0x110)
++#define ONENAND_REG_DATARAM1 (0x120)
++#define ONENAND_REG_SYNC_MODE (0x130)
++#define ONENAND_REG_TRANS_SPARE (0x140)
++#define ONENAND_REG_LOCK_BIT (0x150)
++#define ONENAND_REG_DBS_DFS_WIDTH (0x160)
++#define ONENAND_REG_PAGE_CNT (0x170)
++#define ONENAND_REG_ERR_PAGE_ADDR (0x180)
++#define ONENAND_REG_BURST_RD_LAT (0x190)
++#define ONENAND_REG_INT_PIN_ENABLE (0x1A0)
++#define ONENAND_REG_INT_MON_CYC (0x1B0)
++#define ONENAND_REG_ACC_CLOCK (0x1C0)
++#define ONENAND_REG_SLOW_RD_PATH (0x1D0)
++#define ONENAND_REG_ERR_BLK_ADDR (0x1E0)
++#define ONENAND_REG_FLASH_VER_ID (0x1F0)
++
++#if defined(CONFIG_CPU_S3C6410)
++#define ONENAND_REG_FLASH_AUX_CNTRL (0x300)
++#endif
++
++/*
++ * S3C6400 SFR values
++ */
++#define ONENAND_MEM_CFG_SYNC_READ (1 << 15)
++#define ONENAND_MEM_CFG_BRL_7 (7 << 12)
++#define ONENAND_MEM_CFG_BRL_6 (6 << 12)
++#define ONENAND_MEM_CFG_BRL_5 (5 << 12)
++#define ONENAND_MEM_CFG_BRL_4 (4 << 12)
++#define ONENAND_MEM_CFG_BRL_3 (3 << 12)
++#define ONENAND_MEM_CFG_BRL_10 (2 << 12)
++#define ONENAND_MEM_CFG_BRL_9 (1 << 12)
++#define ONENAND_MEM_CFG_BRL_8 (0 << 12)
++#define ONENAND_MEM_CFG_BRL_SHIFT (12)
++#define ONENAND_MEM_CFG_BL_1K (5 << 9)
++#define ONENAND_MEM_CFG_BL_32 (4 << 9)
++#define ONENAND_MEM_CFG_BL_16 (3 << 9)
++#define ONENAND_MEM_CFG_BL_8 (2 << 9)
++#define ONENAND_MEM_CFG_BL_4 (1 << 9)
++#define ONENAND_MEM_CFG_BL_CONT (0 << 9)
++#define ONENAND_MEM_CFG_BL_SHIFT (9)
++#define ONENAND_MEM_CFG_NO_ECC (1 << 8)
++#define ONENAND_MEM_CFG_RDY_HIGH (1 << 7)
++#define ONENAND_MEM_CFG_INT_HIGH (1 << 6)
++#define ONENAND_MEM_CFG_IOBE (1 << 5)
++#define ONENAND_MEM_CFG_RDY_CONF (1 << 4)
++#define ONENAND_MEM_CFG_HF (1 << 2)
++#define ONENAND_MEM_CFG_WM_SYNC (1 << 1)
++#define ONENAND_MEM_CFG_BWPS_UNLOCK (1 << 0)
++
++#define ONENAND_BURST_LEN_CONT (0)
++#define ONENAND_BURST_LEN_4 (4)
++#define ONENAND_BURST_LEN_8 (8)
++#define ONENAND_BURST_LEN_16 (16)
++
++#define ONENAND_MEM_RESET_WARM (0x1)
++#define ONENAND_MEM_RESET_COLD (0x2)
++#define ONENAND_MEM_RESET_HOT (0x3)
++
++#define ONENAND_INT_ERR_CACHE_OP_ERR (1 << 13)
++#define ONENAND_INT_ERR_RST_CMP (1 << 12)
++#define ONENAND_INT_ERR_RDY_ACT (1 << 11)
++#define ONENAND_INT_ERR_INT_ACT (1 << 10)
++#define ONENAND_INT_ERR_UNSUP_CMD (1 << 9)
++#define ONENAND_INT_ERR_LOCKED_BLK (1 << 8)
++#define ONENAND_INT_ERR_BLK_RW_CMP (1 << 7)
++#define ONENAND_INT_ERR_ERS_CMP (1 << 6)
++#define ONENAND_INT_ERR_PGM_CMP (1 << 5)
++#define ONENAND_INT_ERR_LOAD_CMP (1 << 4)
++#define ONENAND_INT_ERR_ERS_FAIL (1 << 3)
++#define ONENAND_INT_ERR_PGM_FAIL (1 << 2)
++#define ONENAND_INT_ERR_INT_TO (1 << 1)
++#define ONENAND_INT_ERR_LD_FAIL_ECC_ERR (1 << 0)
++
++#define ONENAND_DEVICE_DENSITY_SHIFT (4)
++#define ONENAND_DEVICE_IS_DDP (1 << 3)
++#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
++#define ONENAND_DEVICE_VCC_MASK (0x3)
++#define ONENAND_DEVICE_DENSITY_128Mb (0x000)
++#define ONENAND_DEVICE_DENSITY_256Mb (0x001)
++#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
++#define ONENAND_DEVICE_DENSITY_1Gb (0x003)
++#define ONENAND_DEVICE_DENSITY_2Gb (0x004)
++#define ONENAND_DEVICE_DENSITY_4Gb (0x005)
++
++#define ONENAND_SYNC_MODE_RM_SYNC (1 << 1)
++#define ONENAND_SYNC_MODE_WM_SYNC (1 << 0)
++
++#define ONENAND_TRANS_SPARE_TSRF_INC (1 << 0)
++
++#define ONENAND_INT_PIN_ENABLE (1 << 0)
++
++#define ONENAND_ACC_CLOCK_266_133 (0x5)
++#define ONENAND_ACC_CLOCK_166_83 (0x3)
++#define ONENAND_ACC_CLOCK_134_67 (0x3)
++#define ONENAND_ACC_CLOCK_100_50 (0x2)
++#define ONENAND_ACC_CLOCK_60_30 (0x2)
++
++#if defined(CONFIG_CPU_S3C6410)
++#define ONENAND_FLASH_AUX_WD_DISABLE (1 << 0)
++#endif
++
++/*
++ * Datain values for mapped commands
++ */
++#define ONENAND_DATAIN_ERASE_STATUS (0x00)
++#define ONENAND_DATAIN_ERASE_MULTI (0x01)
++#define ONENAND_DATAIN_ERASE_SINGLE (0x03)
++#define ONENAND_DATAIN_ERASE_VERIFY (0x15)
++#define ONENAND_DATAIN_UNLOCK_START (0x08)
++#define ONENAND_DATAIN_UNLOCK_END (0x09)
++#define ONENAND_DATAIN_LOCK_START (0x0A)
++#define ONENAND_DATAIN_LOCK_END (0x0B)
++#define ONENAND_DATAIN_LOCKTIGHT_START (0x0C)
++#define ONENAND_DATAIN_LOCKTIGHT_END (0x0D)
++#define ONENAND_DATAIN_UNLOCK_ALL (0x0E)
++#define ONENAND_DATAIN_COPYBACK_SRC (0x1000)
++#define ONENAND_DATAIN_COPYBACK_DST (0x2000)
++#define ONENAND_DATAIN_ACCESS_OTP (0x12)
++#define ONENAND_DATAIN_ACCESS_MAIN (0x14)
++#define ONENAND_DATAIN_PIPELINE_READ (0x4000)
++#define ONENAND_DATAIN_PIPELINE_WRITE (0x4100)
++#define ONENAND_DATAIN_RMW_LOAD (0x10)
++#define ONENAND_DATAIN_RMW_MODIFY (0x11)
++
++/*
++ * Device ID Register F001h (R)
++ */
++#define ONENAND_DEVICE_DENSITY_SHIFT (4)
++#define ONENAND_DEVICE_IS_DDP (1 << 3)
++#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
++#define ONENAND_DEVICE_VCC_MASK (0x3)
++
++/*
++ * Version ID Register F002h (R)
++ */
++#define ONENAND_VERSION_PROCESS_SHIFT (8)
++
++/*
++ * Start Address 1 F100h (R/W)
++ */
++#define ONENAND_DDP_SHIFT (15)
++#define ONENAND_DDP_CHIP0 (0)
++#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT)
++
++/*
++ * Start Buffer Register F200h (R/W)
++ */
++#define ONENAND_BSA_MASK (0x03)
++#define ONENAND_BSA_SHIFT (8)
++#define ONENAND_BSA_BOOTRAM (0 << 2)
++#define ONENAND_BSA_DATARAM0 (2 << 2)
++#define ONENAND_BSA_DATARAM1 (3 << 2)
++#define ONENAND_BSC_MASK (0x03)
++
++/*
++ * Command Register F220h (R/W)
++ */
++#define ONENAND_CMD_READ (0x00)
++#define ONENAND_CMD_READOOB (0x13)
++#define ONENAND_CMD_PROG (0x80)
++#define ONENAND_CMD_PROGOOB (0x1A)
++#define ONENAND_CMD_UNLOCK (0x23)
++#define ONENAND_CMD_LOCK (0x2A)
++#define ONENAND_CMD_LOCK_TIGHT (0x2C)
++#define ONENAND_CMD_UNLOCK_ALL (0x27)
++#define ONENAND_CMD_ERASE (0x94)
++#define ONENAND_CMD_RESET (0xF0)
++#define ONENAND_CMD_OTP_ACCESS (0x65)
++#define ONENAND_CMD_READID (0x90)
++#define ONENAND_CMD_STARTADDR1 (0xE0)
++#define ONENAND_CMD_WP_STATUS (0xE1)
++#define ONENAND_CMD_PIPELINE_READ (0x01)
++#define ONENAND_CMD_PIPELINE_WRITE (0x81)
++
++/*
++ * Command Mapping for S3C6400 OneNAND Controller
++ */
++#define ONENAND_AHB_ADDR (0x20000000)
++#define ONENAND_DUMMY_ADDR (0x20400000)
++#define ONENAND_CMD_MAP_00 (0x0)
++#define ONENAND_CMD_MAP_01 (0x1)
++#define ONENAND_CMD_MAP_10 (0x2)
++#define ONENAND_CMD_MAP_11 (0x3)
++#define ONENAND_CMD_MAP_FF (0xF)
++
++#if defined(CONFIG_CPU_S3C6400)
++
++#define ONENAND_CMD_SHIFT (22)
++#define ONENAND_MEM_ADDR_MASK (0x3fffff)
++#define ONENAND_DDP_SHIFT_1Gb (19)
++#define ONENAND_DDP_SHIFT_2Gb (20)
++#define ONENAND_DDP_SHIFT_4Gb (21)
++
++#define ONENAND_FBA_SHIFT_128Mb (9)
++#define ONENAND_FBA_SHIFT_256Mb (9)
++#define ONENAND_FBA_SHIFT_512Mb (10)
++#define ONENAND_FBA_SHIFT_1Gb_DDP (10)
++#define ONENAND_FBA_SHIFT_1Gb (10)
++#define ONENAND_FBA_SHIFT_2Gb_DDP (10)
++#define ONENAND_FBA_SHIFT_2Gb (10)
++#define ONENAND_FBA_SHIFT_4Gb_DDP (10)
++#define ONENAND_FBA_SHIFT_4Gb (10)
++
++#define ONENAND_FPA_SHIFT_128Mb (3)
++#define ONENAND_FPA_SHIFT_256Mb (3)
++#define ONENAND_FPA_SHIFT_512Mb (4)
++#define ONENAND_FPA_SHIFT_1Gb_DDP (4)
++#define ONENAND_FPA_SHIFT_1Gb (4)
++#define ONENAND_FPA_SHIFT_2Gb_DDP (4)
++#define ONENAND_FPA_SHIFT_2Gb (4)
++#define ONENAND_FPA_SHIFT_4Gb_DDP (4)
++#define ONENAND_FPA_SHIFT_4Gb (4)
++
++#define ONENAND_FSA_SHIFT (2)
++#define ONENAND_FBA_MASK_128Mb (0xff)
++#define ONENAND_FBA_MASK_256Mb (0x1ff)
++#define ONENAND_FBA_MASK_512Mb (0x1ff)
++#define ONENAND_FBA_MASK_1Gb_DDP (0x1ff)
++#define ONENAND_FBA_MASK_1Gb (0x3ff)
++#define ONENAND_FBA_MASK_2Gb_DDP (0x3ff)
++#define ONENAND_FBA_MASK_2Gb (0x7ff)
++#define ONENAND_FBA_MASK_4Gb_DDP (0x7ff)
++#define ONENAND_FBA_MASK_4Gb (0xfff)
++#define ONENAND_FPA_MASK (0x3f)
++#define ONENAND_FSA_MASK (0x3)
++
++#elif defined(CONFIG_CPU_S3C6410)
++
++#define ONENAND_CMD_SHIFT (24)
++#define ONENAND_MEM_ADDR_MASK (0xffffff)
++#define ONENAND_DDP_SHIFT_1Gb (21)
++#define ONENAND_DDP_SHIFT_2Gb (22)
++#define ONENAND_DDP_SHIFT_4Gb (23)
++#define ONENAND_FBA_SHIFT (12)
++#define ONENAND_FPA_SHIFT (6)
++#define ONENAND_FSA_SHIFT (4)
++#define ONENAND_FBA_MASK_128Mb (0xff)
++#define ONENAND_FBA_MASK_256Mb (0x1ff)
++#define ONENAND_FBA_MASK_512Mb (0x1ff)
++#define ONENAND_FBA_MASK_1Gb_DDP (0x1ff)
++#define ONENAND_FBA_MASK_1Gb (0x3ff)
++#define ONENAND_FBA_MASK_2Gb_DDP (0x3ff)
++#define ONENAND_FBA_MASK_2Gb (0x7ff)
++#define ONENAND_FBA_MASK_4Gb_DDP (0x7ff)
++#define ONENAND_FBA_MASK_4Gb (0xfff)
++#define ONENAND_FPA_MASK (0x3f)
++#define ONENAND_FSA_MASK (0x3)
++
++#else
++
++/*
++ * Start Address 8 F107h (R/W)
++ */
++#define ONENAND_FPA_MASK (0x3f)
++#define ONENAND_FPA_SHIFT (2)
++#define ONENAND_FSA_MASK (0x03)
++
++#endif
++
++/*
++ * System Configuration 1 Register F221h (R, R/W)
++ */
++#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
++#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
++#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
++#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
++#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
++#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
++#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
++#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
++#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
++#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
++#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
++#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
++#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
++#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
++#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
++#define ONENAND_SYS_CFG1_BL_SHIFT (9)
++#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
++#define ONENAND_SYS_CFG1_RDY (1 << 7)
++#define ONENAND_SYS_CFG1_INT (1 << 6)
++#define ONENAND_SYS_CFG1_IOBE (1 << 5)
++#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
++
++/*
++ * Controller Status Register F240h (R)
++ */
++#define ONENAND_CTRL_ONGO (1 << 15)
++#define ONENAND_CTRL_LOCK (1 << 14)
++#define ONENAND_CTRL_LOAD (1 << 13)
++#define ONENAND_CTRL_PROGRAM (1 << 12)
++#define ONENAND_CTRL_ERASE (1 << 11)
++#define ONENAND_CTRL_ERROR (1 << 10)
++#define ONENAND_CTRL_RSTB (1 << 7)
++#define ONENAND_CTRL_OTP_L (1 << 6)
++#define ONENAND_CTRL_OTP_BL (1 << 5)
++
++/*
++ * Interrupt Status Register F241h (R)
++ */
++#define ONENAND_INT_MASTER (1 << 15)
++#define ONENAND_INT_READ (1 << 7)
++#define ONENAND_INT_WRITE (1 << 6)
++#define ONENAND_INT_ERASE (1 << 5)
++#define ONENAND_INT_RESET (1 << 4)
++#define ONENAND_INT_CLEAR (0 << 0)
++
++/*
++ * NAND Flash Write Protection Status Register F24Eh (R)
++ */
++#define ONENAND_WP_US (1 << 2)
++#define ONENAND_WP_LS (1 << 1)
++#define ONENAND_WP_LTS (1 << 0)
++
++/*
++ * ECC Status Register FF00h (R)
++ */
++#define ONENAND_ECC_1BIT (1 << 0)
++#define ONENAND_ECC_1BIT_ALL (0x5555)
++#define ONENAND_ECC_2BIT (1 << 1)
++#define ONENAND_ECC_2BIT_ALL (0xAAAA)
++
++/*
++ * One-Time Programmable (OTP)
++ */
++#define ONENAND_OTP_LOCK_OFFSET (14)
++
++#endif /* __ASM_ARCH_REGS_ONENAND_H */
+diff --git a/include/asm-arm/arch-s3c2410/regs-pp.h b/include/asm-arm/arch-s3c2410/regs-pp.h
+new file mode 100644
+index 0000000..dc44526
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-pp.h
+@@ -0,0 +1,80 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-hsmmc.h
++ *
++ * Copyright (c) 2004 Samsung Electronics
++ * http://www.samsung.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C HSMMC Controller
++*/
++
++#ifndef __ASM_ARCH_REGS_PP_H
++#define __ASM_ARCH_REGS_PP_H __FILE__
++
++#define S3C_VPP(x) ((x))
++
++#define S3C_VPP_MODE S3C_VPP(0x00)
++#define S3C_VPP_PRESCALE_RATIO S3C_VPP(0x04)
++#define S3C_VPP_PRESCALEIMGSIZE S3C_VPP(0x08)
++#define S3C_VPP_SRCIMGSIZE S3C_VPP(0x0C)
++#define S3C_VPP_MAINSCALE_H_RATIO S3C_VPP(0x10)
++#define S3C_VPP_MAINSCALE_V_RATIO S3C_VPP(0x14)
++#define S3C_VPP_DSTIMGSIZE S3C_VPP(0x18)
++#define S3C_VPP_PRESCALE_SHFACTOR S3C_VPP(0x1C)
++#define S3C_VPP_ADDRSTART_Y S3C_VPP(0x20)
++#define S3C_VPP_ADDRSTART_CB S3C_VPP(0x24)
++#define S3C_VPP_ADDRSTART_CR S3C_VPP(0x28)
++#define S3C_VPP_ADDRSTART_RGB S3C_VPP(0x2C)
++#define S3C_VPP_ADDREND_Y S3C_VPP(0x30)
++#define S3C_VPP_ADDREND_CB S3C_VPP(0x34)
++#define S3C_VPP_ADDREND_CR S3C_VPP(0x38)
++#define S3C_VPP_ADDREND_RGB S3C_VPP(0x3C)
++#define S3C_VPP_OFFSET_Y S3C_VPP(0x40)
++#define S3C_VPP_OFFSET_CB S3C_VPP(0x44)
++#define S3C_VPP_OFFSET_CR S3C_VPP(0x48)
++#define S3C_VPP_OFFSET_RGB S3C_VPP(0x4C)
++#define S3C_VPP_NXTADDRSTART_Y S3C_VPP(0x54)
++#define S3C_VPP_NXTADDRSTART_CB S3C_VPP(0x58)
++#define S3C_VPP_NXTADDRSTART_CR S3C_VPP(0x5C)
++#define S3C_VPP_NXTADDRSTART_RGB S3C_VPP(0x60)
++#define S3C_VPP_NXTADDREND_Y S3C_VPP(0x64)
++#define S3C_VPP_NXTADDREND_CB S3C_VPP(0x68)
++#define S3C_VPP_NXTADDREND_CR S3C_VPP(0x6C)
++#define S3C_VPP_NXTADDREND_RGB S3C_VPP(0x70)
++#define S3C_VPP_ADDRSTART_OCB S3C_VPP(0x74)
++#define S3C_VPP_ADDRSTART_OCR S3C_VPP(0x78)
++#define S3C_VPP_ADDREND_OCB S3C_VPP(0x7C)
++#define S3C_VPP_ADDREND_OCR S3C_VPP(0x80)
++#define S3C_VPP_OFFSET_OCB S3C_VPP(0x84)
++#define S3C_VPP_OFFSET_OCR S3C_VPP(0x88)
++#define S3C_VPP_NXTADDRSTART_OCB S3C_VPP(0x8C)
++#define S3C_VPP_NXTADDRSTART_OCR S3C_VPP(0x90)
++#define S3C_VPP_NXTADDREND_OCB S3C_VPP(0x94)
++#define S3C_VPP_NXTADDREND_OCR S3C_VPP(0x98)
++#define S3C_VPP_POSTENVID S3C_VPP(0x9C)
++#define S3C_VPP_MODE_2 S3C_VPP(0xA0)
++
++//POSTENVID
++#define S3C_POSTENVID_ENABLE (0x1<<31) // khlee
++#define S3C_POSTENVID_DISABLE (0x0<<31)
++
++//MODE Control register
++#define S3C_MODE_AUTOLOAD_ENABLE (0x1<<14)
++#define S3C_MODE_POST_INT_ENABLE (0x1<<7)
++#define S3C_MODE_POST_PENDING (0x1<<6)
++#define S3C_MODE_IRQ_LEVEL (0x1<<5)
++#define S3C_MODE_H_CLK_INPUT (0x0<<2)
++#define S3C_MODE_EXT_CLK_0_INPUT (0x1<<2)
++#define S3C_MODE_EXT_CLK_1_INPUT (0x3<<2)
++
++//MODE Control register 2
++#define S3C_MODE2_ADDR_CHANGE_ENABLE (0x0<<4)
++#define S3C_MODE2_ADDR_CHANGE_DISABLE (0x1<<4)
++#define S3C_MODE2_CHANGE_AT_FIELD_END (0x0<<3)
++#define S3C_MODE2_CHANGE_AT_FRAME_END (0x1<<3)
++#define S3C_MODE2_SOFTWARE_TRIGGER (0x0<<0)
++#define S3C_MODE2_HARDWARE_TRIGGER (0x1<<0)
++
++#endif /* __ASM_ARCH_REGS_HSMMC_H */
+diff --git a/include/asm-arm/arch-s3c2410/regs-s3c-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c-clock.h
+new file mode 100644
+index 0000000..8e168e0
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-s3c-clock.h
+@@ -0,0 +1,13 @@
++#ifndef _REGS_S3C_CLOCK_H_
++#define _REGS_S3C_CLOCK_H_
++
++#if defined(CONFIG_PLAT_S3C24XX)
++#include <asm/arch/regs-s3c2443-clock.h>
++#elif defined(CONFIG_PLAT_S3C64XX)
++#include <asm/arch/regs-s3c6400-clock.h>
++#elif defined(CONFIG_PLAT_S5PC1XX)
++#include <asm/arch/regs-s5pc100-clock.h>
++#endif
++
++#endif
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
+index c141465..08f3c75 100644
+--- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
++++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
+@@ -16,6 +16,16 @@
+
+ #define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
+
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C2443_PLLCON_MDIVSHIFT 14
++#define S3C2443_PLLCON_PDIVSHIFT 5
++#define S3C2443_PLLCON_SDIVSHIFT 0
++#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-14)))-1)
++#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(10-5)))-1)
++#define S3C2443_PLLCON_SDIVMASK (7)
++
++#define S3C2443_EPLLCON_SDIVMASK (7)
++#else
+ #define S3C2443_PLLCON_MDIVSHIFT 16
+ #define S3C2443_PLLCON_PDIVSHIFT 8
+ #define S3C2443_PLLCON_SDIVSHIFT 0
+@@ -23,8 +33,18 @@
+ #define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
+ #define S3C2443_PLLCON_SDIVMASK (3)
+
++#define S3C2443_EPLLCON_SDIVMASK (3)
++#endif
++
++#define S3C2443_EPLLCON_MDIVSHIFT 16
++#define S3C2443_EPLLCON_PDIVSHIFT 8
++#define S3C2443_EPLLCON_SDIVSHIFT 0
++#define S3C2443_EPLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
++#define S3C2443_EPLLCON_PDIVMASK ((1<<(1+(13-8)))-1)
++
+ #define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
+ #define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
++#define S3C2450_EPLLCON_K S3C2443_CLKREG(0x1C)
+ #define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
+ #define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
+ #define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
+@@ -37,6 +57,11 @@
+ #define S3C2443_SYSID S3C2443_CLKREG(0x5C)
+ #define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
+ #define S3C2443_RSTCON S3C2443_CLKREG(0x64)
++#define S3C2443_RSTSTAT S3C2443_CLKREG(0x68)
++#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
++#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
++#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
++#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
+
+ #define S3C2443_SWRST_RESET (0x533c2443)
+
+@@ -73,11 +98,22 @@
+ #define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
+ #define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
+ #define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
++
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
++#define S3C2443_CLKDIV0_ARMDIV_2 (1<<9)
++#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
++#define S3C2443_CLKDIV0_ARMDIV_4 (3<<9)
++#define S3C2443_CLKDIV0_ARMDIV_6 (5<<9)
++#define S3C2443_CLKDIV0_ARMDIV_8 (7<<9)
++#else
+ #define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
+ #define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
+ #define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
+ #define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
+ #define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
++#endif
++
+ #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
+ #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
+
+@@ -112,6 +148,8 @@
+ #define S3C2443_HCLKCON_DMA3 (1<<3)
+ #define S3C2443_HCLKCON_DMA4 (1<<4)
+ #define S3C2443_HCLKCON_DMA5 (1<<5)
++#define S3C2443_HCLKCON_DMA6 (1<<6)
++#define S3C2443_HCLKCON_DMA7 (1<<7)
+ #define S3C2443_HCLKCON_CAMIF (1<<8)
+ #define S3C2443_HCLKCON_DISP (1<<9)
+ #define S3C2443_HCLKCON_LCDC (1<<10)
+@@ -164,8 +202,11 @@ s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
+ mdiv &= S3C2443_PLLCON_MDIVMASK;
+ pdiv &= S3C2443_PLLCON_PDIVMASK;
+ sdiv &= S3C2443_PLLCON_SDIVMASK;
+-
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ fvco = (uint64_t)baseclk * (mdiv);
++#else
+ fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
++#endif
+ do_div(fvco, pdiv << sdiv);
+
+ return (unsigned int)fvco;
+@@ -177,17 +218,21 @@ s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
+ unsigned int mdiv, pdiv, sdiv;
+ uint64_t fvco;
+
+- mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
+- pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
+- sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
++ mdiv = pllval >> S3C2443_EPLLCON_MDIVSHIFT;
++ pdiv = pllval >> S3C2443_EPLLCON_PDIVSHIFT;
++ sdiv = pllval >> S3C2443_EPLLCON_SDIVSHIFT;
+
+- mdiv &= S3C2443_PLLCON_MDIVMASK;
+- pdiv &= S3C2443_PLLCON_PDIVMASK;
+- sdiv &= S3C2443_PLLCON_SDIVMASK;
++ mdiv &= S3C2443_EPLLCON_MDIVMASK;
++ pdiv &= S3C2443_EPLLCON_PDIVMASK;
++ sdiv &= S3C2443_EPLLCON_SDIVMASK;
+
++#if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++ fvco = (uint64_t)baseclk * (mdiv);
++ do_div(fvco, pdiv << sdiv);
++#else
+ fvco = (uint64_t)baseclk * (mdiv + 8);
+ do_div(fvco, (pdiv + 2) << sdiv);
+-
++#endif
+ return (unsigned int)fvco;
+ }
+
+diff --git a/include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h
+new file mode 100644
+index 0000000..6226656
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h
+@@ -0,0 +1,268 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h
++ *
++ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
++ * http://armlinux.simtec.co.uk/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C6400 clock register definitions
++*/
++
++#ifndef __ASM_ARM_REGS_CLOCK
++#define __ASM_ARM_REGS_CLOCK "$Id: regs-s3c6400-clock.h,v 1.2 2008/03/20 07:12:45 ihlee215 Exp $"
++
++#define S3C_CLKREG(x) ((x) + S3C24XX_VA_SYSCON)
++
++#define S3C_PLLVAL(_m,_p,_s) ((_m) << 16 | ((_p) << 8) | ((_s)))
++
++#define S3C_APLL_LOCK S3C_CLKREG(0x00)
++#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
++#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
++#define S3C_APLL_CON S3C_CLKREG(0x0C)
++#define S3C_MPLL_CON S3C_CLKREG(0x10)
++#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
++#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
++#define S3C_CLK_SRC S3C_CLKREG(0x1C)
++#define S3C_CLK_SRC2 S3C_CLKREG(0x10C)
++#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
++#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
++#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
++#define S3C_CLK_OUT S3C_CLKREG(0x2C)
++#define S3C_HCLK_GATE S3C_CLKREG(0x30)
++#define S3C_PCLK_GATE S3C_CLKREG(0x34)
++#define S3C_SCLK_GATE S3C_CLKREG(0x38)
++#define S3C_AHB_CON0 S3C_CLKREG(0x100)
++#define S3C_AHB_CON1 S3C_CLKREG(0x104)
++#define S3C_AHB_CON2 S3C_CLKREG(0x108)
++#define S3C_SDMA_SEL S3C_CLKREG(0x110)
++#define S3C_SW_RST S3C_CLKREG(0x114)
++#define S3C_SYS_ID S3C_CLKREG(0x118)
++#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
++#define S3C_QOS_OVERRIDE0 S3C_CLKREG(0x124)
++#define S3C_QOS_OVERRIDE1 S3C_CLKREG(0x128)
++#define S3C_MEM_CFG_STAT S3C_CLKREG(0x12C)
++#define S3C_PWR_CFG S3C_CLKREG(0x804)
++#define S3C_EINT_MASK S3C_CLKREG(0x808)
++#define S3C_NORMAL_CFG S3C_CLKREG(0x810)
++#define S3C_STOP_CFG S3C_CLKREG(0x814)
++#define S3C_SLEEP_CFG S3C_CLKREG(0x818)
++#define S3C_OSC_FREQ S3C_CLKREG(0x820)
++#define S3C_OSC_STABLE S3C_CLKREG(0x824)
++#define S3C_PWR_STABLE S3C_CLKREG(0x828)
++#define S3C_FPC_STABLE S3C_CLKREG(0x82C)
++#define S3C_MTC_STABLE S3C_CLKREG(0x830)
++#define S3C_OTHERS S3C_CLKREG(0x900)
++#define S3C_RST_STAT S3C_CLKREG(0x904)
++#define S3C_WAKEUP_STAT S3C_CLKREG(0x908)
++#define S3C_BLK_PWR_STAT S3C_CLKREG(0x90C)
++#define S3C_INFORM0 S3C_CLKREG(0xA00)
++#define S3C_INFORM1 S3C_CLKREG(0xA04)
++#define S3C_INFORM2 S3C_CLKREG(0xA08)
++#define S3C_INFORM3 S3C_CLKREG(0xA0C)
++#define S3C_INFORM4 S3C_CLKREG(0xA10)
++#define S3C_INFORM5 S3C_CLKREG(0xA14)
++#define S3C_INFORM6 S3C_CLKREG(0xA18)
++#define S3C_INFORM7 S3C_CLKREG(0xA1C)
++
++/* Block power status register bit field */
++#define S3C_BLK_ETM (1<<6)
++#define S3C_BLK_S (1<<5)
++#define S3C_BLK_F (1<<4)
++#define S3C_BLK_P (1<<3)
++#define S3C_BLK_I (1<<2)
++#define S3C_BLK_V (1<<1)
++#define S3C_BLK_TOP (1<<0)
++
++/* Power gating registers */
++#define S3C_PWRGATE_IROM (1<<30)
++#define S3C_PWRGATE_DOMAIN_ETM (1<<16)
++#define S3C_PWRGATE_DOMAIN_S (1<<15)
++#define S3C_PWRGATE_DOMAIN_F (1<<14)
++#define S3C_PWRGATE_DOMAIN_P (1<<13)
++#define S3C_PWRGATE_DOMAIN_I (1<<12)
++#define S3C_PWRGATE_DOMAIN_V (1<<9)
++
++/* MTC stable registers */
++#define S3C_STABLE_DOMAIN_ETM (0xF<<24)
++#define S3C_STABLE_DOMAIN_S (0xF<<20)
++#define S3C_STABLE_DOMAIN_F (0xF<<16)
++#define S3C_STABLE_DOMAIN_P (0xF<<12)
++#define S3C_STABLE_DOMAIN_I (0xF<<8)
++#define S3C_STABLE_DOMAIN_V (0xF<<4)
++#define S3C_STABLE_DOMAIN_TOP (0xF<<0)
++
++/* HCLK GATE Registers */
++#define S3C_CLKCON_HCLK_BUS (1<<30)
++#define S3C_CLKCON_HCLK_SECUR (1<<29)
++#define S3C_CLKCON_HCLK_SDMA1 (1<<28)
++#define S3C_CLKCON_HCLK_SDMA2 (1<<27)
++#define S3C_CLKCON_HCLK_UHOST (1<<26)
++#define S3C_CLKCON_HCLK_IROM (1<<25)
++#define S3C_CLKCON_HCLK_DDR1 (1<<24)
++#define S3C_CLKCON_HCLK_DDR0 (1<<23)
++#define S3C_CLKCON_HCLK_MEM1 (1<<22)
++#define S3C_CLKCON_HCLK_MEM0 (1<<21)
++#define S3C_CLKCON_HCLK_USB (1<<20)
++#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
++#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
++#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
++#define S3C_CLKCON_HCLK_MDP (1<<16)
++#define S3C_CLKCON_HCLK_DHOST (1<<15)
++#define S3C_CLKCON_HCLK_IHOST (1<<14)
++#define S3C_CLKCON_HCLK_DMA1 (1<<13)
++#define S3C_CLKCON_HCLK_DMA0 (1<<12)
++#define S3C_CLKCON_HCLK_JPEG (1<<11)
++#define S3C_CLKCON_HCLK_CAMIF (1<<10)
++#define S3C_CLKCON_HCLK_SCALER (1<<9)
++#define S3C_CLKCON_HCLK_2D (1<<8)
++#define S3C_CLKCON_HCLK_TV (1<<7)
++#define S3C_CLKCON_HCLK_POST0 (1<<5)
++#define S3C_CLKCON_HCLK_ROT (1<<4)
++#define S3C_CLKCON_HCLK_LCD (1<<3)
++#define S3C_CLKCON_HCLK_TZIC (1<<2)
++#define S3C_CLKCON_HCLK_INTC (1<<1)
++#define S3C_CLKCON_HCLK_MFC (1<<0)
++
++/* PCLK GATE Registers */
++#define S3C_CLKCON_PCLK_IIC1 (1<<27)
++#define S3C_CLKCON_PCLK_IIS2 (1<<26)
++#define S3C_CLKCON_PCLK_SKEY (1<<24)
++#define S3C_CLKCON_PCLK_CHIPID (1<<23)
++#define S3C_CLKCON_PCLK_SPI1 (1<<22)
++#define S3C_CLKCON_PCLK_SPI0 (1<<21)
++#define S3C_CLKCON_PCLK_HSIRX (1<<20)
++#define S3C_CLKCON_PCLK_HSITX (1<<19)
++#define S3C_CLKCON_PCLK_GPIO (1<<18)
++#define S3C_CLKCON_PCLK_IIC (1<<17)
++#define S3C_CLKCON_PCLK_IIS1 (1<<16)
++#define S3C_CLKCON_PCLK_IIS0 (1<<15)
++#define S3C_CLKCON_PCLK_AC97 (1<<14)
++#define S3C_CLKCON_PCLK_TZPC (1<<13)
++#define S3C_CLKCON_PCLK_TSADC (1<<12)
++#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
++#define S3C_CLKCON_PCLK_IRDA (1<<10)
++#define S3C_CLKCON_PCLK_PCM1 (1<<9)
++#define S3C_CLKCON_PCLK_PCM0 (1<<8)
++#define S3C_CLKCON_PCLK_PWM (1<<7)
++#define S3C_CLKCON_PCLK_RTC (1<<6)
++#define S3C_CLKCON_PCLK_WDT (1<<5)
++#define S3C_CLKCON_PCLK_UART3 (1<<4)
++#define S3C_CLKCON_PCLK_UART2 (1<<3)
++#define S3C_CLKCON_PCLK_UART1 (1<<2)
++#define S3C_CLKCON_PCLK_UART0 (1<<1)
++#define S3C_CLKCON_PCLK_MFC (1<<0)
++
++/* SCLK GATE Registers */
++#define S3C_CLKCON_SCLK_UHOST (1<<30)
++#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
++#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
++#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
++#define S3C_CLKCON_SCLK_MMC2 (1<<26)
++#define S3C_CLKCON_SCLK_MMC1 (1<<25)
++#define S3C_CLKCON_SCLK_MMC0 (1<<24)
++#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
++#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
++#define S3C_CLKCON_SCLK_SPI1 (1<<21)
++#define S3C_CLKCON_SCLK_SPI0 (1<<20)
++#define S3C_CLKCON_SCLK_DAC27 (1<<19)
++#define S3C_CLKCON_SCLK_TV27 (1<<18)
++#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
++#define S3C_CLKCON_SCLK_SCALER (1<<16)
++#define S3C_CLKCON_SCLK_LCD27 (1<<15)
++#define S3C_CLKCON_SCLK_LCD (1<<14)
++#if defined(CONFIG_CPU_S3C6410)
++#define S3C_CLKCON_SCLK_FIMC (1<<13)
++#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
++#define S3C_CLKCON_SCLK_AUDIO2 (1<<11)
++#else
++#define S3C_CLKCON_SCLK_POST1_27 (1<<13)
++#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
++#define S3C_CLKCON_SCLK_POST1 (1<<11)
++#endif
++#define S3C_CLKCON_SCLK_POST0 (1<<10)
++#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
++#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
++#define S3C_CLKCON_SCLK_SECUR (1<<7)
++#define S3C_CLKCON_SCLK_IRDA (1<<6)
++#define S3C_CLKCON_SCLK_UART (1<<5)
++#define S3C_CLKCON_SCLK_ONENAND (1<<4)
++#define S3C_CLKCON_SCLK_MFC (1<<3)
++#define S3C_CLKCON_SCLK_CAM (1<<2)
++#define S3C_CLKCON_SCLK_JPEG (1<<1)
++
++/*OTHERS Resgister */
++#define S3C_OTHERS_USB_SIG_MASK (1<<16)
++
++/*CLK SRC BITS*/
++#define S3C_CLKSRC_APLL_CLKSEL (1<<0)
++#define S3C_CLKSRC_MPLL_CLKSEL (1<<1)
++#define S3C_CLKSRC_EPLL_CLKSEL (1<<2)
++#define S3C_CLKSRC_UHOST_EPLL (1<<5)
++#define S3C_CLKSRC_UHOST_MASK (3<<5)
++#if 0
++#define S3C_CLKSRC_CAM_CLKSEL_HCLK (1<<9)
++#define S3C_CLKSRC_I2SDIV_CLKSRC (1<<10)
++#define S3C_CLKSRC_I2SCLK_CLKSEL (1<<11)
++#define S3C_CLKSRC_UARTDIV_CLKSRC (1<<12)
++#define S3C_CLKSRC_SPIDIV_CLKSRC (1<<13)
++#endif
++
++/*CLKDIV1 Reg bits */
++#define S3C_CLKDIV1_USBDIV2 (1<<20)
++
++#define S3C_CLKDIV1_HSMMCDIV2_MASK (0xf<<8)
++#define S3C_CLKDIV1_HSMMCDIV2_SHIFT (8)
++#define S3C_CLKDIV1_HSMMCDIV1_MASK (0xf<<4)
++#define S3C_CLKDIV1_HSMMCDIV1_SHIFT (4)
++#define S3C_CLKDIV1_HSMMCDIV0_MASK (0xf<<0)
++#define S3C_CLKDIV1_HSMMCDIV0_SHIFT (0)
++#define S3C_CLKDIV1_HSMMCDIV_MASK (0xfff<<0)
++#define S3C_CLKDIV1_HSMMCDIV_SHIFT (0)
++
++/*EPLL_CON0 Reg bits */
++#define S3C_EPLL_EN (1<<31)
++#define S3C_EPLLVAL(_m,_p,_s) ((_m) << 16 | ((_p) << 8) | ((_s)))
++
++
++
++#define S3C_CLKDIVN_APLL_MASK (0xF<<0)
++#define S3C_CLKDIVN_MPLL_MASK (0x1<<4)
++#define S3C_CLKDIVN_HCLK_MASK (0x1<<8)
++#define S3C_CLKDIVN_HCLKX2_MASK (0x7<<9)
++#define S3C_CLKDIVN_PCLK_MASK (0xF<<12)
++#define S3C_CLKDIVN_UHOST_MASK (0xF<<20)
++
++static inline unsigned int
++s3c6400_get_pll(unsigned long pllval, unsigned long baseclk)
++{
++ unsigned long mdiv, pdiv, sdiv;
++
++ /* To prevent overflow in calculation -JaeCheol Lee */
++ baseclk /= 1000;
++
++ mdiv = (pllval & (0x3ff << 16))>>16;
++ pdiv = (pllval & (0x3f << 8))>>8;
++ sdiv = (pllval & (0x03 << 0))>>0;
++ return (baseclk * (mdiv)) / ((pdiv) << sdiv)*1000;
++}
++
++static inline unsigned int
++s3c6400_get_epll(unsigned long baseclk)
++{
++ unsigned long pllval, mdiv, pdiv, sdiv, kdiv;
++
++ /* To prevent overflow in calculation -JaeCheol Lee */
++ baseclk /= 1000;
++
++ pllval = readl(S3C_EPLL_CON0);
++ mdiv = (pllval & (0x3ff << 16))>>16;
++ pdiv = (pllval & (0x3f << 8))>>8;
++ sdiv = (pllval & (0x03 << 0))>>0;
++ kdiv = readl(S3C_EPLL_CON1) & (0xffff);
++
++ return (baseclk * (mdiv+kdiv/65536) / (pdiv << sdiv))*1000;
++}
++
++#endif /* __ASM_ARM_REGS_CLOCK */
+diff --git a/include/asm-arm/arch-s3c2410/regs-s5pc100-clock.h b/include/asm-arm/arch-s3c2410/regs-s5pc100-clock.h
+new file mode 100644
+index 0000000..e2373be
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-s5pc100-clock.h
+@@ -0,0 +1,323 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h
++ *
++ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
++ * http://armlinux.simtec.co.uk/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C6400 clock register definitions
++*/
++
++#ifndef __ASM_ARM_REGS_CLOCK
++#define __ASM_ARM_REGS_CLOCK
++
++#define S5P_CLKREG(x) ((x) + S3C24XX_VA_SYSCON)
++
++#define S5P_PLLVAL(_m,_p,_s) ((_m) << 16 | ((_p) << 8) | ((_s)))
++
++#define S5P_APLL_LOCK S5P_CLKREG(0x00)
++#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
++#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
++#define S5P_HPLL_LOCK S5P_CLKREG(0x0C)
++
++#define S5P_APLL_CON S5P_CLKREG(0x100)
++#define S5P_MPLL_CON S5P_CLKREG(0x104)
++#define S5P_EPLL_CON S5P_CLKREG(0x108)
++#define S5P_HPLL_CON S5P_CLKREG(0x10C)
++
++#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
++#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
++#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
++#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
++
++#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
++#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
++#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
++#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
++#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
++#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
++
++#define S5P_CLK_OUT S5P_CLKREG(0x400)
++
++#define S5P_CLK_GATE_D0_0 S5P_CLKREG(0x500)
++#define S5P_CLK_GATE_D0_1 S5P_CLKREG(0x504)
++#define S5P_CLK_GATE_D0_2 S5P_CLKREG(0x508)
++
++#define S5P_CLK_GATE_D1_0 S5P_CLKREG(0x520)
++#define S5P_CLK_GATE_D1_1 S5P_CLKREG(0x524)
++#define S5P_CLK_GATE_D1_2 S5P_CLKREG(0x528)
++#define S5P_CLK_GATE_D1_3 S5P_CLKREG(0x52C)
++#define S5P_CLK_GATE_D1_4 S5P_CLKREG(0x530)
++#define S5P_CLK_GATE_D1_5 S5P_CLKREG(0x534)
++
++#define S5P_CLK_GATE_D2_0 S5P_CLKREG(0x540)
++
++#define S5P_SCLK_GATE_0 S5P_CLKREG(0x560)
++#define S5P_SCLK_GATE_1 S5P_CLKREG(0x564)
++
++#if 0
++#define S5P_AHB_CON0 S5P_CLKREG(0x100)
++#define S5P_AHB_CON1 S5P_CLKREG(0x104)
++#define S5P_AHB_CON2 S5P_CLKREG(0x108)
++#define S5P_SDMA_SEL S5P_CLKREG(0x110)
++#define S5P_SW_RST S5P_CLKREG(0x114)
++#define S5P_SYS_ID S5P_CLKREG(0x118)
++#define S5P_MEM_SYS_CFG S5P_CLKREG(0x120)
++#define S5P_QOS_OVERRIDE0 S5P_CLKREG(0x124)
++#define S5P_QOS_OVERRIDE1 S5P_CLKREG(0x128)
++#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C)
++#define S5P_PWR_CFG S5P_CLKREG(0x804)
++#define S5P_EINT_MASK S5P_CLKREG(0x808)
++#define S5P_NORMAL_CFG S5P_CLKREG(0x810)
++#define S5P_STOP_CFG S5P_CLKREG(0x814)
++#define S5P_SLEEP_CFG S5P_CLKREG(0x818)
++#define S5P_OSC_FREQ S5P_CLKREG(0x820)
++#define S5P_OSC_STABLE S5P_CLKREG(0x824)
++#define S5P_PWR_STABLE S5P_CLKREG(0x828)
++#define S5P_FPC_STABLE S5P_CLKREG(0x82C)
++#define S5P_MTC_STABLE S5P_CLKREG(0x830)
++#define S5P_OTHERS S5P_CLKREG(0x900)
++#define S5P_RST_STAT S5P_CLKREG(0x904)
++#define S5P_WAKEUP_STAT S5P_CLKREG(0x908)
++#define S5P_BLK_PWR_STAT S5P_CLKREG(0x90C)
++#define S5P_INFORM0 S5P_CLKREG(0xA00)
++#define S5P_INFORM1 S5P_CLKREG(0xA04)
++#define S5P_INFORM2 S5P_CLKREG(0xA08)
++#define S5P_INFORM3 S5P_CLKREG(0xA0C)
++#define S5P_INFORM4 S5P_CLKREG(0xA10)
++#define S5P_INFORM5 S5P_CLKREG(0xA14)
++#define S5P_INFORM6 S5P_CLKREG(0xA18)
++#define S5P_INFORM7 S5P_CLKREG(0xA1C)
++
++/* Block power status register bit field */
++#define S5P_BLK_ETM (1<<6)
++#define S5P_BLK_S (1<<5)
++#define S5P_BLK_F (1<<4)
++#define S5P_BLK_P (1<<3)
++#define S5P_BLK_I (1<<2)
++#define S5P_BLK_V (1<<1)
++#define S5P_BLK_TOP (1<<0)
++
++/* Power gating registers */
++#define S5P_PWRGATE_IROM (1<<30)
++#define S5P_PWRGATE_DOMAIN_ETM (1<<16)
++#define S5P_PWRGATE_DOMAIN_S (1<<15)
++#define S5P_PWRGATE_DOMAIN_F (1<<14)
++#define S5P_PWRGATE_DOMAIN_P (1<<13)
++#define S5P_PWRGATE_DOMAIN_I (1<<12)
++#define S5P_PWRGATE_DOMAIN_V (1<<9)
++
++/* MTC stable registers */
++#define S5P_STABLE_DOMAIN_ETM (0xF<<24)
++#define S5P_STABLE_DOMAIN_S (0xF<<20)
++#define S5P_STABLE_DOMAIN_F (0xF<<16)
++#define S5P_STABLE_DOMAIN_P (0xF<<12)
++#define S5P_STABLE_DOMAIN_I (0xF<<8)
++#define S5P_STABLE_DOMAIN_V (0xF<<4)
++#define S5P_STABLE_DOMAIN_TOP (0xF<<0)
++
++/* HCLK GATE Registers */
++#define S5P_CLKCON_HCLK_BUS (1<<30)
++#define S5P_CLKCON_HCLK_SECUR (1<<29)
++#define S5P_CLKCON_HCLK_SDMA1 (1<<28)
++#define S5P_CLKCON_HCLK_SDMA2 (1<<27)
++#define S5P_CLKCON_HCLK_UHOST (1<<26)
++#define S5P_CLKCON_HCLK_IROM (1<<25)
++#define S5P_CLKCON_HCLK_DDR1 (1<<24)
++#define S5P_CLKCON_HCLK_DDR0 (1<<23)
++#define S5P_CLKCON_HCLK_MEM1 (1<<22)
++#define S5P_CLKCON_HCLK_MEM0 (1<<21)
++#define S5P_CLKCON_HCLK_USB (1<<20)
++#define S5P_CLKCON_HCLK_HSMMC2 (1<<19)
++#define S5P_CLKCON_HCLK_HSMMC1 (1<<18)
++#define S5P_CLKCON_HCLK_HSMMC0 (1<<17)
++#define S5P_CLKCON_HCLK_MDP (1<<16)
++#define S5P_CLKCON_HCLK_DHOST (1<<15)
++#define S5P_CLKCON_HCLK_IHOST (1<<14)
++#define S5P_CLKCON_HCLK_DMA1 (1<<13)
++#define S5P_CLKCON_HCLK_DMA0 (1<<12)
++#define S5P_CLKCON_HCLK_JPEG (1<<11)
++#define S5P_CLKCON_HCLK_CAMIF (1<<10)
++#define S5P_CLKCON_HCLK_SCALER (1<<9)
++#define S5P_CLKCON_HCLK_2D (1<<8)
++#define S5P_CLKCON_HCLK_TV (1<<7)
++#define S5P_CLKCON_HCLK_POST0 (1<<5)
++#define S5P_CLKCON_HCLK_ROT (1<<4)
++#define S5P_CLKCON_HCLK_LCD (1<<3)
++#define S5P_CLKCON_HCLK_TZIC (1<<2)
++#define S5P_CLKCON_HCLK_INTC (1<<1)
++#define S5P_CLKCON_HCLK_MFC (1<<0)
++
++/* PCLK GATE Registers */
++#define S5P_CLKCON_PCLK_IIC1 (1<<27)
++#define S5P_CLKCON_PCLK_IIS2 (1<<26)
++#define S5P_CLKCON_PCLK_SKEY (1<<24)
++#define S5P_CLKCON_PCLK_CHIPID (1<<23)
++#define S5P_CLKCON_PCLK_SPI1 (1<<22)
++#define S5P_CLKCON_PCLK_SPI0 (1<<21)
++#define S5P_CLKCON_PCLK_HSIRX (1<<20)
++#define S5P_CLKCON_PCLK_HSITX (1<<19)
++#define S5P_CLKCON_PCLK_GPIO (1<<18)
++#define S5P_CLKCON_PCLK_IIC (1<<17)
++#define S5P_CLKCON_PCLK_IIS1 (1<<16)
++#define S5P_CLKCON_PCLK_IIS0 (1<<15)
++#define S5P_CLKCON_PCLK_AC97 (1<<14)
++#define S5P_CLKCON_PCLK_TZPC (1<<13)
++#define S5P_CLKCON_PCLK_TSADC (1<<12)
++#define S5P_CLKCON_PCLK_KEYPAD (1<<11)
++#define S5P_CLKCON_PCLK_IRDA (1<<10)
++#define S5P_CLKCON_PCLK_PCM1 (1<<9)
++#define S5P_CLKCON_PCLK_PCM0 (1<<8)
++#define S5P_CLKCON_PCLK_PWM (1<<7)
++#define S5P_CLKCON_PCLK_RTC (1<<6)
++#define S5P_CLKCON_PCLK_WDT (1<<5)
++#define S5P_CLKCON_PCLK_UART3 (1<<4)
++#define S5P_CLKCON_PCLK_UART2 (1<<3)
++#define S5P_CLKCON_PCLK_UART1 (1<<2)
++#define S5P_CLKCON_PCLK_UART0 (1<<1)
++#define S5P_CLKCON_PCLK_MFC (1<<0)
++
++/* SCLK GATE Registers */
++#define S5P_CLKCON_SCLK_UHOST (1<<30)
++#define S5P_CLKCON_SCLK_MMC2_48 (1<<29)
++#define S5P_CLKCON_SCLK_MMC1_48 (1<<28)
++#define S5P_CLKCON_SCLK_MMC0_48 (1<<27)
++#define S5P_CLKCON_SCLK_MMC2 (1<<26)
++#define S5P_CLKCON_SCLK_MMC1 (1<<25)
++#define S5P_CLKCON_SCLK_MMC0 (1<<24)
++#define S5P_CLKCON_SCLK_SPI1_48 (1<<23)
++#define S5P_CLKCON_SCLK_SPI0_48 (1<<22)
++#define S5P_CLKCON_SCLK_SPI1 (1<<21)
++#define S5P_CLKCON_SCLK_SPI0 (1<<20)
++#define S5P_CLKCON_SCLK_DAC27 (1<<19)
++#define S5P_CLKCON_SCLK_TV27 (1<<18)
++#define S5P_CLKCON_SCLK_SCALER27 (1<<17)
++#define S5P_CLKCON_SCLK_SCALER (1<<16)
++#define S5P_CLKCON_SCLK_LCD27 (1<<15)
++#define S5P_CLKCON_SCLK_LCD (1<<14)
++#if defined(CONFIG_CPU_S3C6410)
++#define S5P_CLKCON_SCLK_FIMC (1<<13)
++#define S5P_CLKCON_SCLK_POST0_27 (1<<12)
++#define S5P_CLKCON_SCLK_AUDIO2 (1<<11)
++#else
++#define S5P_CLKCON_SCLK_POST1_27 (1<<13)
++#define S5P_CLKCON_SCLK_POST0_27 (1<<12)
++#define S5P_CLKCON_SCLK_POST1 (1<<11)
++#endif
++#define S5P_CLKCON_SCLK_POST0 (1<<10)
++#define S5P_CLKCON_SCLK_AUDIO1 (1<<9)
++#define S5P_CLKCON_SCLK_AUDIO0 (1<<8)
++#define S5P_CLKCON_SCLK_SECUR (1<<7)
++#define S5P_CLKCON_SCLK_IRDA (1<<6)
++#define S5P_CLKCON_SCLK_UART (1<<5)
++#define S5P_CLKCON_SCLK_ONENAND (1<<4)
++#define S5P_CLKCON_SCLK_MFC (1<<3)
++#define S5P_CLKCON_SCLK_CAM (1<<2)
++#define S5P_CLKCON_SCLK_JPEG (1<<1)
++
++/*OTHERS Resgister */
++#define S5P_OTHERS_USB_SIG_MASK (1<<16)
++
++/*CLK SRC BITS*/
++#define S5P_CLKSRC_APLL_CLKSEL (1<<0)
++#define S5P_CLKSRC_MPLL_CLKSEL (1<<1)
++#define S5P_CLKSRC_EPLL_CLKSEL (1<<2)
++#define S5P_CLKSRC_UHOST_EPLL (1<<5)
++#define S5P_CLKSRC_UHOST_MASK (3<<5)
++#if 0
++#define S5P_CLKSRC_CAM_CLKSEL_HCLK (1<<9)
++#define S5P_CLKSRC_I2SDIV_CLKSRC (1<<10)
++#define S5P_CLKSRC_I2SCLK_CLKSEL (1<<11)
++#define S5P_CLKSRC_UARTDIV_CLKSRC (1<<12)
++#define S5P_CLKSRC_SPIDIV_CLKSRC (1<<13)
++#endif
++
++/*CLKDIV1 Reg bits */
++#define S5P_CLKDIV1_USBDIV2 (1<<20)
++
++#define S5P_CLKDIV1_HSMMCDIV2_MASK (0xf<<8)
++#define S5P_CLKDIV1_HSMMCDIV2_SHIFT (8)
++#define S5P_CLKDIV1_HSMMCDIV1_MASK (0xf<<4)
++#define S5P_CLKDIV1_HSMMCDIV1_SHIFT (4)
++#define S5P_CLKDIV1_HSMMCDIV0_MASK (0xf<<0)
++#define S5P_CLKDIV1_HSMMCDIV0_SHIFT (0)
++#define S5P_CLKDIV1_HSMMCDIV_MASK (0xfff<<0)
++#define S5P_CLKDIV1_HSMMCDIV_SHIFT (0)
++
++/*EPLL_CON0 Reg bits */
++#define S5P_EPLL_EN (1<<31)
++#define S5P_EPLLVAL(_m,_p,_s) ((_m) << 16 | ((_p) << 8) | ((_s)))
++
++
++
++#define S5P_CLKDIVN_APLL_MASK (0xF<<0)
++#define S5P_CLKDIVN_MPLL_MASK (0x1<<4)
++#define S5P_CLKDIVN_HCLK_MASK (0x1<<8)
++#define S5P_CLKDIVN_HCLKX2_MASK (0x7<<9)
++#define S5P_CLKDIVN_PCLK_MASK (0xF<<12)
++#define S5P_CLKDIVN_UHOST_MASK (0xF<<20)
++
++#endif
++
++#define S5P_CLKDIV0_APLL_MASK (0x1<<0)
++#define S5P_CLKDIV0_ARM_MASK (0x7<<4)
++#define S5P_CLKDIV0_D0_MASK (0x7<<8)
++#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12)
++#define S5P_CLKDIV0_SECSS_MASK (0x7<<16)
++
++#define S5P_CLKDIV1_AM_MASK (0x7<<0)
++#define S5P_CLKDIV1_MPLL_MASK (0x3<<4)
++#define S5P_CLKDIV1_MPLL2_MASK (0x1<<8)
++#define S5P_CLKDIV1_D1_MASK (0x7<<12)
++#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
++#define S5P_CLKDIV1_ONENAND_MASK (0x3<<20)
++#define S5P_CLKDIV1_CAM_MASK (0x1F<<24)
++
++static inline unsigned int
++s5p_get_apll(unsigned long pllval, unsigned long baseclk)
++{
++ unsigned long mdiv, pdiv, sdiv;
++
++ baseclk /= 1000;
++
++ mdiv = (pllval & (0x3ff << 16))>>16;
++ pdiv = (pllval & (0x3f << 8))>>8;
++ sdiv = (pllval & (0x03 << 0))>>0;
++
++ return (baseclk * (mdiv)) / ((pdiv) << sdiv)*1000;
++}
++
++static inline unsigned int
++s5p_get_mpll(unsigned long pllval, unsigned long baseclk)
++{
++ unsigned long mdiv, pdiv, sdiv;
++
++ baseclk /= 1000;
++
++ mdiv = (pllval & (0xff << 16))>>16;
++ pdiv = (pllval & (0x3f << 8))>>8;
++ sdiv = (pllval & (0x03 << 0))>>0;
++
++ return (baseclk * (mdiv)) / ((pdiv) << sdiv)*1000;
++}
++#if 0
++static inline unsigned int
++s5p_get_mpll(unsigned long baseclk)
++{
++ unsigned long pllval, mdiv, pdiv, sdiv, kdiv;
++
++ baseclk /= 1000;
++
++ pllval = readl(S5P_EPLL_CON0);
++ mdiv = (pllval & (0x3ff << 16))>>16;
++ pdiv = (pllval & (0x3f << 8))>>8;
++ sdiv = (pllval & (0x03 << 0))>>0;
++ kdiv = readl(S5P_EPLL_CON1) & (0xffff);
++
++ return (baseclk * (mdiv+kdiv/65536) / (pdiv << sdiv))*1000;
++}
++#endif
++
++#endif /* __ASM_ARM_REGS_CLOCK */
+diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
+new file mode 100644
+index 0000000..7799cbc
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-serial.h
+@@ -0,0 +1,415 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
++ *
++ * From linux/include/asm-arm/hardware/serial_s3c2410.h
++ *
++ * Internal header file for Samsung S3C2410 serial ports (UART0-2)
++ *
++ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
++ *
++ * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
++ *
++ * Adapted from:
++ *
++ * Internal header file for MX1ADS serial ports (UART1 & 2)
++ *
++ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++*/
++
++#ifndef __ASM_ARM_REGS_SERIAL_H
++#define __ASM_ARM_REGS_SERIAL_H
++
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++#define S3C24XX_VA_UART0 (S3C24XX_VA_UART)
++#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x400 )
++#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x800 )
++#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC00 )
++
++#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
++#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x400 )
++#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x800 )
++#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC00 )
++#else
++#define S3C24XX_VA_UART0 (S3C24XX_VA_UART)
++#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 )
++#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 )
++#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 )
++
++#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
++#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
++#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
++#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
++#endif
++
++#define S3C2410_URXH (0x24)
++#define S3C2410_UTXH (0x20)
++#define S3C2410_ULCON (0x00)
++#define S3C2410_UCON (0x04)
++#define S3C2410_UFCON (0x08)
++#define S3C2410_UMCON (0x0C)
++#define S3C2410_UBRDIV (0x28)
++#define S3C2410_UTRSTAT (0x10)
++#define S3C2410_UERSTAT (0x14)
++#define S3C2410_UFSTAT (0x18)
++#define S3C2410_UMSTAT (0x1C)
++
++#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
++
++#define S3C2410_LCON_CS5 (0x0)
++#define S3C2410_LCON_CS6 (0x1)
++#define S3C2410_LCON_CS7 (0x2)
++#define S3C2410_LCON_CS8 (0x3)
++#define S3C2410_LCON_CSMASK (0x3)
++
++#define S3C2410_LCON_PNONE (0x0)
++#define S3C2410_LCON_PEVEN (0x5 << 3)
++#define S3C2410_LCON_PODD (0x4 << 3)
++#define S3C2410_LCON_PMASK (0x7 << 3)
++
++#define S3C2410_LCON_STOPB (1<<2)
++#define S3C2410_LCON_IRM (1<<6)
++
++#define S3C2440_UCON_CLKMASK (3<<10)
++#define S3C2440_UCON_PCLK (0<<10)
++#define S3C2440_UCON_UCLK (1<<10)
++#define S3C2440_UCON_PCLK2 (2<<10)
++#define S3C2440_UCON_FCLK (3<<10)
++#define S3C2443_UCON_EPLL (3<<10)
++
++#define S3C2440_UCON2_FCLK_EN (1<<15)
++#define S3C2440_UCON0_DIVMASK (15 << 12)
++#define S3C2440_UCON1_DIVMASK (15 << 12)
++#define S3C2440_UCON2_DIVMASK (7 << 12)
++#define S3C2440_UCON_DIVSHIFT (12)
++
++#define S3C2412_UCON_CLKMASK (3<<10)
++#define S3C2412_UCON_UCLK (1<<10)
++#define S3C2412_UCON_USYSCLK (3<<10)
++#define S3C2412_UCON_PCLK (0<<10)
++#define S3C2412_UCON_PCLK2 (2<<10)
++
++#define S3C2410_UCON_UCLK (1<<10)
++#define S3C2410_UCON_SBREAK (1<<4)
++
++#define S3C2410_UCON_TXILEVEL (1<<9)
++#define S3C2410_UCON_RXILEVEL (1<<8)
++#define S3C2410_UCON_TXIRQMODE (1<<2)
++#define S3C2410_UCON_RXIRQMODE (1<<0)
++#define S3C2410_UCON_RXFIFO_TOI (1<<7)
++#define S3C2443_UCON_RXERR_IRQEN (1<<6)
++#define S3C2443_UCON_LOOPBACK (1<<5)
++
++#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
++ S3C2410_UCON_RXILEVEL | \
++ S3C2410_UCON_TXIRQMODE | \
++ S3C2410_UCON_RXIRQMODE | \
++ S3C2410_UCON_RXFIFO_TOI)
++
++#define S3C2410_UFCON_FIFOMODE (1<<0)
++#define S3C2410_UFCON_TXTRIG0 (0<<6)
++#define S3C2410_UFCON_RXTRIG8 (1<<4)
++#define S3C2410_UFCON_RXTRIG12 (2<<4)
++
++/* S3C2440 FIFO trigger levels */
++#define S3C2440_UFCON_RXTRIG1 (0<<4)
++#define S3C2440_UFCON_RXTRIG8 (1<<4)
++#define S3C2440_UFCON_RXTRIG16 (2<<4)
++#define S3C2440_UFCON_RXTRIG32 (3<<4)
++
++#define S3C2440_UFCON_TXTRIG0 (0<<6)
++#define S3C2440_UFCON_TXTRIG16 (1<<6)
++#define S3C2440_UFCON_TXTRIG32 (2<<6)
++#define S3C2440_UFCON_TXTRIG48 (3<<6)
++
++#define S3C2410_UFCON_RESETBOTH (3<<1)
++#define S3C2410_UFCON_RESETTX (1<<2)
++#define S3C2410_UFCON_RESETRX (1<<1)
++
++#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
++ S3C2410_UFCON_TXTRIG0 | \
++ S3C2410_UFCON_RXTRIG8 )
++
++#define S3C2410_UMCOM_AFC (1<<4)
++#define S3C2410_UMCOM_RTS_LOW (1<<0)
++
++#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
++#define S3C2412_UMCON_AFC_56 (1<<5)
++#define S3C2412_UMCON_AFC_48 (2<<5)
++#define S3C2412_UMCON_AFC_40 (3<<5)
++#define S3C2412_UMCON_AFC_32 (4<<5)
++#define S3C2412_UMCON_AFC_24 (5<<5)
++#define S3C2412_UMCON_AFC_16 (6<<5)
++#define S3C2412_UMCON_AFC_8 (7<<5)
++
++#define S3C2410_UFSTAT_TXFULL (1<<9)
++#define S3C2410_UFSTAT_RXFULL (1<<8)
++#define S3C2410_UFSTAT_TXMASK (15<<4)
++#define S3C2410_UFSTAT_TXSHIFT (4)
++#define S3C2410_UFSTAT_RXMASK (15<<0)
++#define S3C2410_UFSTAT_RXSHIFT (0)
++
++/* UFSTAT S3C2443 same as S3C2440 */
++#define S3C2440_UFSTAT_TXFULL (1<<14)
++#define S3C2440_UFSTAT_RXFULL (1<<6)
++#define S3C2440_UFSTAT_TXSHIFT (8)
++#define S3C2440_UFSTAT_RXSHIFT (0)
++#define S3C2440_UFSTAT_TXMASK (63<<8)
++#define S3C2440_UFSTAT_RXMASK (63)
++
++#define S3C2410_UTRSTAT_TXE (1<<2)
++#define S3C2410_UTRSTAT_TXFE (1<<1)
++#define S3C2410_UTRSTAT_RXDR (1<<0)
++
++#define S3C2410_UERSTAT_OVERRUN (1<<0)
++#define S3C2410_UERSTAT_FRAME (1<<2)
++#define S3C2410_UERSTAT_BREAK (1<<3)
++#define S3C2443_UERSTAT_PARITY (1<<1)
++
++#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
++ S3C2410_UERSTAT_FRAME | \
++ S3C2410_UERSTAT_BREAK)
++
++#define S3C2410_UMSTAT_CTS (1<<0)
++#define S3C2410_UMSTAT_DeltaCTS (1<<2)
++
++#define S3C2443_DIVSLOT (0x2C)
++
++
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++
++
++/* UART */
++#if 0
++#define S3C_VA_UART0 (S3C24XX_VA_UART)
++#define S3C_VA_UART1 (S3C24XX_VA_UART + 0x400 )
++#define S3C_VA_UART2 (S3C24XX_VA_UART + 0x800 )
++#define S3C_VA_UART3 (S3C24XX_VA_UART + 0xC00 )
++
++#define S3C_PA_UART0 (S3C24XX_PA_UART)
++#define S3C_PA_UART1 (S3C24XX_PA_UART + 0x400 )
++#define S3C_PA_UART2 (S3C24XX_PA_UART + 0x800 )
++#define S3C_PA_UART3 (S3C24XX_PA_UART + 0xC00 )
++#endif
++
++#define S3C_IRQ_UART0 IRQ_UART0
++#define S3C_IRQ_UART1 IRQ_UART1
++#define S3C_IRQ_UART2 IRQ_UART2
++#define S3C_IRQ_UART3 IRQ_UART3
++
++#define S3C_ULCON (0x00)
++#define S3C_UCON (0x04)
++#define S3C_UFCON (0x08)
++#define S3C_UMCON (0x0C)
++#define S3C_UTRSTAT (0x10)
++#define S3C_UERSTAT (0x14)
++#define S3C_UFSTAT (0x18)
++#define S3C_UMSTAT (0x1C)
++#define S3C_UTXH (0x20)
++#define S3C_URXH (0x24)
++#define S3C_UBRDIV (0x28)
++#define S3C_UDIVSLOT (0x2C)
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#define S3C_UINTPND (0x30)
++#define S3C_UINTSP (0x34)
++#define S3C_UINTMSK (0x38)
++#else
++#define S3C_UINTPND (S3C24XX_VA_IRQ + 0x18 )
++#define S3C_UINTMSK (S3C24XX_VA_IRQ + 0x1c )
++#endif
++
++/* base definitions for UART Line Control Register */
++#define S3C_LCON_CFGMASK (0x7f)
++
++#define S3C_LCON_CS5 (0x0)
++#define S3C_LCON_CS6 (0x1)
++#define S3C_LCON_CS7 (0x2)
++#define S3C_LCON_CS8 (0x3)
++#define S3C_LCON_CSMASK (0x3)
++
++#define S3C_LCON_PNONE (0x0)
++#define S3C_LCON_PEVEN (0x5 << 3)
++#define S3C_LCON_PODD (0x4 << 3)
++#define S3C_LCON_PMASK (0x7 << 3)
++
++#define S3C_LCON_STOPB (1<<2)
++#define S3C_LCON_IRM (1<<6)
++
++#define S3C_UCON_CLKMASK (3<<10)
++#define S3C_UCON_PCLK (0<<10)
++#define S3C_UCON_UCLK (1<<10)
++#define S3C_UCON_PCLK2 (2<<10)
++#define S3C_UCON_FCLK (3<<10)
++#define S3C_UCON_SBREAK (1<<4)
++
++#define S3C_UCON_TXILEVEL (1<<9)
++#define S3C_UCON_RXILEVEL (1<<8)
++#define S3C_UCON_TXIRQMODE (1<<2)
++#define S3C_UCON_RXIRQMODE (1<<0)
++#define S3C_UCON_RXFIFO_TOI (1<<7)
++#define S3C_UCON_RX_ESIE (1<<6)
++#define S3C_UCON_LOOP_OPERATION (0<<5)
++#define S3C_UCON_NO_SBS (0<<4)
++
++
++#define S3C_UCON_DEFAULT (S3C_UCON_TXILEVEL | \
++ S3C_UCON_RXILEVEL | \
++ S3C_UCON_TXIRQMODE | \
++ S3C_UCON_RXIRQMODE | \
++ S3C_UCON_RXFIFO_TOI)
++
++/* base definitions for UART FIFO Control Register */
++#define S3C_UFCON_FIFOMODE (1<<0)
++#define S3C2410_UFCON_TXTRIG0 (0<<6)
++#define S3C2410_UFCON_RXTRIG8 (1<<4)
++#define S3C_UFCON_RXTRIG12 (2<<4)
++
++/* S3C2413 FIFO trigger levels */
++#define S3C_UFCON_RXTRIG1 (0<<4)
++#define S3C_UFCON_RXTRIG8 (1<<4)
++#define S3C_UFCON_RXTRIG16 (2<<4)
++#define S3C_UFCON_RXTRIG32 (3<<4)
++
++#define S3C_UFCON_TXTRIG0 (0<<6)
++#define S3C_UFCON_TXTRIG16 (1<<6)
++#define S3C_UFCON_TXTRIG32 (2<<6)
++#define S3C_UFCON_TXTRIG48 (3<<6)
++
++#define S3C_UFCON_RESETBOTH (3<<1)
++#define S3C_UFCON_RESETTX (1<<2)
++#define S3C_UFCON_RESETRX (1<<1)
++#define S3C_UFCON_FIFO_ENABLE (1<<0)
++
++#define S3C_UFCON_DEFAULT (S3C_UFCON_FIFOMODE | \
++ S3C_UFCON_TXTRIG0 | \
++ S3C_UFCON_RXTRIG8 )
++
++#define S3C_UMCOM_AFC (1<<4)
++#define S3C_UMCOM_RTS_LOW (1<<0)
++
++#define S3C2410_UFSTAT_TXFULL (1<<9)
++#define S3C2410_UFSTAT_RXFULL (1<<8)
++#define S3C2410_UFSTAT_TXMASK (15<<4)
++#define S3C2410_UFSTAT_TXSHIFT (4)
++#define S3C2410_UFSTAT_RXMASK (15<<0)
++#define S3C2410_UFSTAT_RXSHIFT (0)
++
++#define S3C_UFSTAT_TXFULL (1<<14)
++#define S3C_UFSTAT_RXFULL (1<<6)
++#define S3C_UFSTAT_TXSHIFT (8)
++#define S3C_UFSTAT_RXSHIFT (0)
++#define S3C_UFSTAT_TXMASK (63<<8)
++#define S3C_UFSTAT_RXMASK (63)
++
++#define S3C_UTRSTAT_TXE (1<<2)
++#define S3C_UTRSTAT_TXFE (1<<1)
++#define S3C_UTRSTAT_RXDR (1<<0)
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#define UART_RX_INT (1<<0)
++#define UART_TX_INT (1<<2)
++#define UART_ERR_INT (1<<1)
++#define UART_MODEM_INT (1<<3)
++#else
++#define UART_RX_INT (1<<6)
++#define UART_TX_INT (1<<7)
++#define UART_ERR_INT (1<<8)
++#endif
++
++#define S3C_UERSTAT_OVERRUN (1<<0)
++#define S3C_UERSTAT_FRAME (1<<2)
++#define S3C_UERSTAT_BREAK (1<<3)
++#define S3C_UERSTAT_ANY (S3C_UERSTAT_OVERRUN | \
++ S3C_UERSTAT_FRAME | \
++ S3C_UERSTAT_BREAK)
++
++#define S3C_UMSTAT_CTS (1<<0)
++#define S3C_UMSTAT_DeltaCTS (1<<2)
++
++#endif
++
++
++#ifndef __ASSEMBLY__
++
++/* struct s3c24xx_uart_clksrc
++ *
++ * this structure defines a named clock source that can be used for the
++ * uart, so that the best clock can be selected for the requested baud
++ * rate.
++ *
++ * min_baud and max_baud define the range of baud-rates this clock is
++ * acceptable for, if they are both zero, it is assumed any baud rate that
++ * can be generated from this clock will be used.
++ *
++ * divisor gives the divisor from the clock to the one seen by the uart
++*/
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++#define NR_PORTS (4)
++#define UART_FIFO_SIZE 64
++#define UART_HAS_INTMSK
++#define UART_C_CFLAG
++#define UART_UMCON
++#define UART_CLK 115200
++#else
++#define NR_PORTS (3)
++#endif
++
++
++struct s3c24xx_uart_clksrc {
++ const char *name;
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++ unsigned int clock_src;
++#endif
++ unsigned int divisor;
++ unsigned int min_baud;
++ unsigned int max_baud;
++};
++
++/* configuration structure for per-machine configurations for the
++ * serial port
++ *
++ * the pointer is setup by the machine specific initialisation from the
++ * arch/arm/mach-s3c2410/ directory.
++*/
++
++struct s3c2410_uartcfg {
++ unsigned char hwport; /* hardware port number */
++ unsigned char unused;
++ unsigned short flags;
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ unsigned int uart_flags; /* default uart flags */
++#else
++ unsigned long uart_flags; /* default uart flags */
++#endif
++ unsigned long ucon; /* value of ucon for port */
++ unsigned long ulcon; /* value of ulcon for port */
++ unsigned long ufcon; /* value of ufcon for port */
++
++ struct s3c24xx_uart_clksrc *clocks;
++ unsigned int clocks_size;
++};
++
++/* s3c24xx_uart_devs
++ *
++ * this is exported from the core as we cannot use driver_register(),
++ * or platform_add_device() before the console_initcall()
++*/
++
++extern struct platform_device *s3c24xx_uart_devs[NR_PORTS];
++
++#endif /* __ASSEMBLY__ */
++
++#endif /* __ASM_ARM_REGS_SERIAL_H */
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-tvenc.h b/include/asm-arm/arch-s3c2410/regs-tvenc.h
+new file mode 100644
+index 0000000..4877611
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-tvenc.h
+@@ -0,0 +1,198 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-tvenc.h
++ *
++ * Copyright (c) 2007 Samsung Electronics
++ * http://www.samsungsemi.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.*/
++
++#ifndef __ASM_ARM_REGS_TVENC_H
++#define __ASM_ARM_REGS_TVENC_H
++
++#define S3C_TVCTRL (0x00)
++#define S3C_VBPORCH (0x04)
++#define S3C_HBPORCH (0x08)
++#define S3C_HENHOFFSET (0x0C)
++#define S3C_VDEMOWINSIZE (0x10)
++#define S3C_HDEMOWINSIZE (0x14)
++#define S3C_INIMAGESIZE (0x18)
++#define S3C_PEDCTRL (0x1C)
++#define S3C_YCFILTERBW (0x20)
++#define S3C_HUECTRL (0x24)
++#define S3C_FSCCTRL (0x28)
++#define S3C_FSCDTOMANCTRL (0x2C)
++#define S3C_BGCTRL (0x34)
++#define S3C_BGHVAVCTRL (0x38)
++#define S3C_CONTRABRIGHT (0x44)
++#define S3C_CBCRGAINCTRL (0x48)
++#define S3C_DEMOWINCTRL (0x4C)
++#define S3C_FTCA (0x50)
++#define S3C_BWGAIN (0x58)
++#define S3C_SHARPCTRL (0x60)
++#define S3C_GAMMACTRL (0x64)
++#define S3C_FSCAUXCTRL (0x68)
++#define S3C_SYNCSIZECTRL (0x6C)
++#define S3C_BURSTCTRL (0x70)
++#define S3C_MACROBURSTCTRL (0x74)
++#define S3C_ACTVIDPOCTRL (0x78)
++#define S3C_ENCCTRL (0x7C)
++#define S3C_MUTECTRL (0x80)
++#define S3C_MACROVISION0 (0x84)
++#define S3C_MACROVISION1 (0x88)
++#define S3C_MACROVISION2 (0x8C)
++#define S3C_MACROVISION3 (0x90)
++#define S3C_MACROVISION4 (0x94)
++#define S3C_MACROVISION5 (0x98)
++#define S3C_MACROVISION6 (0x9C)
++
++
++#define S3C_TVCTRL_FIFOURINT_DIS 0<<16
++#define S3C_TVCTRL_FIFOURINT_ENA 1<<16
++#define S3C_TVCTRL_FIFOURINT_OCCUR 1<<12
++#define S3C_TVCTRL_OUTTYPE_C 0<<8
++#define S3C_TVCTRL_OUTTYPE_S 1<<8
++#define S3C_TVCTRL_OUTFMT_NTSC_M 0<<4
++#define S3C_TVCTRL_OUTFMT_NTSC_J 1<<4
++#define S3C_TVCTRL_OUTFMT_PAL_BDG 2<<4
++#define S3C_TVCTRL_OUTFMT_PAL_M 3<<4
++#define S3C_TVCTRL_OUTFMT_PAL_NC 4<<4
++#define S3C_TVCTRL_OFF 0<<0
++#define S3C_TVCTRL_ON 1<<0
++
++// vertical back porch control
++#define VBP_VEFBPD(n) (((n)&0x1FF)<<16)
++#define VBP_VOFBPD(n) (((n)&0xFF)<<0)
++
++#define VBP_VEFBPD_NTSC 0x11C<<16
++#define VBP_VEFBPD_PAL 0x14F<<16
++#define VBP_VOFBPD_NTSC 0x15<<0
++#define VBP_VOFBPD_PAL 0x16<<0
++
++
++// horizontal back porch end point
++#define HBP_HSPW(n) (((n)&0xFF)<<16)
++#define HBP_HBPD(n) (((n)&0x7FF)<<0)
++
++#define HBP_HSPW_NTSC 0x80<<16
++#define HBP_HSPW_PAL 0x80<<16
++#define HBP_HBPD_NTSC 0xF4<<0
++#define HBP_HBPD_PAL 0x108<<0
++
++// horizontal enhancer offset
++#define HEO_VAWCC(n) (((n)&0x3F)<<24)
++#define HEO_HAWCC(n) (((n)&0xFF)<<16)
++#define HEO_DTO(n) (((n)&0x7)<<8)
++#define HEO_HEOV(n) (((n)&0x1F)<<0)
++
++#define HEO_DTO_NTSC 0x4<<8
++#define HEO_DTO_PAL 0x4<<8
++#define HEO_HEOV_NTSC 0x1A<<0
++#define HEO_HEOV_PAL 0x1A<<0
++
++
++// vertical demo window size
++#define VDW_VDWS(n) (((n)&0x1FF)<<16)
++#define VDW_VDWSP(n) (((n)&0x1FF)<<0)
++
++#define VDW_VDWS_DEF 0xF0<<16
++#define VDW_VDWSP_DEF 0x0<<0
++
++
++// horizontal demo window size
++#define HDW_HDWEP(n) (((n)&0x7FF)<<16)
++#define HDW_HDWSP(n) (((n)&0x7FF)<<0)
++
++#define HDW_HDWEP_DEF 0x5A0<<16
++#define HDW_HDWSP_DEF 0x0<<0
++
++
++// input image size
++#define IIS_HEIGHT(n) (((n)&0x3FF)<<16)
++#define IIS_WIDTH(n) (((n)&0x7FF)<<0)
++
++// encoder pedestal control
++#define EPC_PED_ON 0<<0
++#define EPC_PED_OFF 1<<0
++
++// yc filter bandwidth control
++#define YFB_YBW_60 0<<4
++#define YFB_YBW_38 1<<4
++#define YFB_YBW_31 2<<4
++#define YFB_YBW_26 3<<4
++#define YFB_YBW_21 4<<4
++#define YFB_CBW_12 0<<0
++#define YFB_CBW_10 1<<0
++#define YFB_CBW_08 2<<0
++#define YFB_CBW_06 3<<0
++
++// hue control
++#define HUE_CTRL(n) (((n)&0xFF)<<0)
++
++// fsc control
++#define FSC_CTRL(n) (((n)&0x7FFF)<<0)
++
++// fsc dto manually control enable
++#define FDM_CTRL(n) (((n)&0x7FFFFFFF)<<0)
++
++// background control
++#define BGC_BGYOFS(n) (((n)&0xF)<<0)
++
++#define BGC_SME_DIS 0<<8
++#define BGC_SME_ENA 1<<8
++#define BGC_BGCS_BLACK 0<<4
++#define BGC_BGCS_BLUE 1<<4
++#define BGC_BGCS_RED 2<<4
++#define BGC_BGCS_MAGENTA 3<<4
++#define BGC_BGCS_GREEN 4<<4
++#define BGC_BGCS_CYAN 5<<4
++#define BGC_BGCS_YELLOW 6<<4
++#define BGC_BGCS_WHITE 7<<4
++
++// background vav & hav control
++#define BVH_BG_HL(n) (((n)&0xFF)<<24)
++#define BVH_BG_HS(n) (((n)&0xFF)<<16)
++#define BVH_BG_VL(n) (((n)&0xFF)<<8)
++#define BVH_BG_VS(n) (((n)&0xFF)<<0)
++
++// sync size control
++#define SSC_HSYNC(n) (((n)&0x3FF)<<0)
++
++#define SSC_HSYNC_NTSC 0x3D<<0
++#define SSC_HSYNC_PAL 0x3E<<0
++
++// burst signal control
++#define BSC_BEND(n) (((n)&0x3FF)<<16)
++#define BSC_BSTART(n) (((n)&0x3FF)<<0)
++
++#define BSC_BEND_NTSC 0x69<<16
++#define BSC_BEND_PAL 0x6A<<16
++#define BSC_BSTART_NTSC 0x49<<0
++#define BSC_BSTART_PAL 0x4A<<0
++
++// macrovision burst signal control
++#define MBS_BSTART(n) (((n)&0x3FF)<<0)
++
++#define MBS_BSTART_NTSC 0x41<<0
++#define MBS_BSTART_PAL 0x42<<0
++
++// active video position control
++#define AVP_AVEND(n) (((n)&0x3FF)<<16)
++#define AVP_AVSTART(n) (((n)&0x3FF)<<0)
++
++#define AVP_AVEND_NTSC 0x348<<16
++#define AVP_AVEND_PAL 0x352<<16
++#define AVP_AVSTART_NTSC 0x78<<0
++#define AVP_AVSTART_PAL 0x82<<0
++
++// encoder control
++#define ENC_BGEN_DIS 0<<0
++#define ENC_BGEN_ENA 1<<0
++
++#define NTSC_WIDTH (720)
++#define NTSC_HEIGHT (480)
++#define PAL_WIDTH (720)
++#define PAL_HEIGHT (576)
++
++#endif /* __ASM_ARM_REGS_TVENC_H */
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-tvscaler.h b/include/asm-arm/arch-s3c2410/regs-tvscaler.h
+new file mode 100644
+index 0000000..678d0f5
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-tvscaler.h
+@@ -0,0 +1,78 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-tvscaler.h
++ *
++ * Copyright (c) 2007 Samsung Electronics
++ * http://www.samsungsemi.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C6400 TV SCALER register definitions
++*/
++
++#ifndef __ASM_ARM_REGS_TVSCALER
++#define __ASM_ARM_REGS_TVSCALER "regs-tvscaler.h"
++
++#define S3C_MODE (0x00)
++#define S3C_PRESCALE_RATIO (0x04)
++#define S3C_PRESCALEIMGSIZE (0x08)
++#define S3C_SRCIMGSIZE (0x0C)
++#define S3C_MAINSCALE_H_RATIO (0x10)
++#define S3C_MAINSCALE_V_RATIO (0x14)
++#define S3C_DSTIMGSIZE (0x18)
++#define S3C_PRESCALE_SHFACTOR (0x1C)
++#define S3C_ADDRSTART_Y (0x20)
++#define S3C_ADDRSTART_CB (0x24)
++#define S3C_ADDRSTART_CR (0x28)
++#define S3C_ADDRSTART_RGB (0x2C)
++#define S3C_ADDREND_Y (0x30)
++#define S3C_ADDREND_CB (0x34)
++#define S3C_ADDREND_CR (0x38)
++#define S3C_ADDREND_RGB (0x3C)
++#define S3C_OFFSET_Y (0x40)
++#define S3C_OFFSET_CB (0x44)
++#define S3C_OFFSET_CR (0x48)
++#define S3C_OFFSET_RGB (0x4C)
++#define S3C_NXTADDRSTART_Y (0x54)
++#define S3C_NXTADDRSTART_CB (0x58)
++#define S3C_NXTADDRSTART_CR (0x5C)
++#define S3C_NXTADDRSTART_RGB (0x60)
++#define S3C_NXTADDREND_Y (0x64)
++#define S3C_NXTADDREND_CB (0x68)
++#define S3C_NXTADDREND_CR (0x6C)
++#define S3C_NXTADDREND_RGB (0x70)
++#define S3C_ADDRSTART_OCB (0x74)
++#define S3C_ADDRSTART_OCR (0x78)
++#define S3C_ADDREND_OCB (0x7C)
++#define S3C_ADDREND_OCR (0x80)
++#define S3C_OFFSET_OCB (0x84)
++#define S3C_OFFSET_OCR (0x88)
++#define S3C_NXTADDRSTART_OCB (0x8C)
++#define S3C_NXTADDRSTART_OCR (0x90)
++#define S3C_NXTADDREND_OCB (0x94)
++#define S3C_NXTADDREND_OCR (0x98)
++#define S3C_POSTENVID (0x9C)
++#define S3C_MODE2 (0xA0)
++
++//POSTENVID
++#define S3C_POSTENVID_ENABLE (0x1<<31)
++#define S3C_POSTENVID_DISABLE (0x0<<31)
++
++//MODE Control register
++#define S3C_MODE_AUTOLOAD_ENABLE (0x1<<14)
++#define S3C_MODE_POST_INT_ENABLE (0x1<<7)
++#define S3C_MODE_POST_PENDING (0x1<<6)
++#define S3C_MODE_IRQ_LEVEL (0x1<<5)
++#define S3C_MODE_H_CLK_INPUT (0x0<<2)
++#define S3C_MODE_EXT_CLK_0_INPUT (0x1<<2)
++#define S3C_MODE_EXT_CLK_1_INPUT (0x3<<2)
++
++//MODE Control register 2
++#define S3C_MODE2_ADDR_CHANGE_ENABLE (0x0<<4)
++#define S3C_MODE2_ADDR_CHANGE_DISABLE (0x1<<4)
++#define S3C_MODE2_CHANGE_AT_FIELD_END (0x0<<3)
++#define S3C_MODE2_CHANGE_AT_FRAME_END (0x1<<3)
++#define S3C_MODE2_SOFTWARE_TRIGGER (0x0<<0)
++#define S3C_MODE2_HARDWARE_TRIGGER (0x1<<0)
++
++#endif /* __ASM_ARM_REGS_TVSCALER */
+diff --git a/include/asm-arm/arch-s3c2410/regs-udc-hs.h b/include/asm-arm/arch-s3c2410/regs-udc-hs.h
+new file mode 100644
+index 0000000..a15c7a8
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-udc-hs.h
+@@ -0,0 +1,153 @@
++/*
++ * include/asm/arch-s3c2410/regs-udc-hs.h
++ *
++ * $Id: regs-udc-hs.h,v 1.2 2008/03/26 07:14:30 ihlee215 Exp $*
++ *
++ * Copyright (C) 2007 for Samsung Electronics
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#ifndef __ASM_ARCH_REGS_UDC_HS_H
++#define __ASM_ARCH_REGS_UDC_HS_H
++
++
++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C_PWRCFG S3C2443_PWRCFG
++#define S3C_RSTCON S3C2443_RSTCON
++#define S3C_RSTSTAT S3C2443_RSTSTAT
++#define S3C_PHYCTRL S3C2443_PHYCTRL
++#define S3C_PHYPWR S3C2443_PHYPWR
++#define S3C_URSTCON S3C2443_URSTCON
++#define S3C_UCLKCON S3C2443_UCLKCON
++#endif
++
++/* USB2.0 Device Controller register */
++#define S3C_USBDREG(x) ((x) + S3C24XX_VA_USBDEV)
++
++/* Non-Indexed Registers */
++#define S3C_UDC_INDEX_REG S3C_USBDREG(0x00) /* Index register */
++#define S3C_UDC_EP_INT_REG S3C_USBDREG(0x04) /* EP Interrupt pending and clear */
++#define S3C_UDC_EP_INT_EN_REG S3C_USBDREG(0x08) /* EP Interrupt enable */
++#define S3C_UDC_FUNC_ADDR_REG S3C_USBDREG(0x0c) /* Function address */
++#define S3C_UDC_FRAME_NUM_REG S3C_USBDREG(0x10) /* Frame number */
++#define S3C_UDC_EP_DIR_REG S3C_USBDREG(0x14) /* Endpoint direction */
++#define S3C_UDC_TEST_REG S3C_USBDREG(0x18) /* Test register */
++#define S3C_UDC_SYS_STATUS_REG S3C_USBDREG(0x1c) /* System status */
++#define S3C_UDC_SYS_CON_REG S3C_USBDREG(0x20) /* System control */
++#define S3C_UDC_EP0_STATUS_REG S3C_USBDREG(0x24) /* Endpoint 0 status */
++#define S3C_UDC_EP0_CON_REG S3C_USBDREG(0x28) /* Endpoint 0 control */
++#define S3C_UDC_EP0_FIFO_REG S3C_USBDREG(0x60) /* Endpoint 0 Buffer */
++#define S3C_UDC_EP1_FIFO_REG S3C_USBDREG(0x64) /* Endpoint 1 Buffer */
++#define S3C_UDC_EP2_FIFO_REG S3C_USBDREG(0x68) /* Endpoint 2 Buffer */
++#define S3C_UDC_EP3_FIFO_REG S3C_USBDREG(0x6c) /* Endpoint 3 Buffer */
++#define S3C_UDC_EP4_FIFO_REG S3C_USBDREG(0x70) /* Endpoint 4 Buffer */
++#define S3C_UDC_EP5_FIFO_REG S3C_USBDREG(0x74) /* Endpoint 5 Buffer */
++#define S3C_UDC_EP6_FIFO_REG S3C_USBDREG(0x78) /* Endpoint 6 Buffer */
++#define S3C_UDC_EP7_FIFO_REG S3C_USBDREG(0x7c) /* Endpoint 7 Buffer */
++#define S3C_UDC_EP8_FIFO_REG S3C_USBDREG(0x80) /* Endpoint 8 Buffer */
++#define S3C_UDC_FIFO_CON_REG S3C_USBDREG(0x100) /* Burst FIFO-DMA Control */
++#define S3C_UDC_FIFO_STATUS_REG S3C_USBDREG(0x104) /* Burst FIFO Status */
++
++/* Indexed Registers */
++#define S3C_UDC_EP_STATUS_REG S3C_USBDREG(0x2c) /* Endpoints status */
++#define S3C_UDC_EP_CON_REG S3C_USBDREG(0x30) /* Endpoints control */
++#define S3C_UDC_BYTE_READ_CNT_REG S3C_USBDREG(0x34) /* Byte read count */
++#define S3C_UDC_BYTE_WRITE_CNT_REG S3C_USBDREG(0x38) /* Byte write count */
++#define S3C_UDC_MAXP_REG S3C_USBDREG(0x3c) /* Max packet size */
++#define S3C_UDC_DMA_CON_REG S3C_USBDREG(0x40) /* DMA control */
++#define S3C_UDC_DMA_CNT_REG S3C_USBDREG(0x44) /* DMA count */
++#define S3C_UDC_DMA_FIFO_CNT_REG S3C_USBDREG(0x48) /* DMA FIFO count */
++#define S3C_UDC_DMA_TOTAL_CNT1_REG S3C_USBDREG(0x4c) /* DMA Total Transfer count1 */
++#define S3C_UDC_DMA_TOTAL_CNT2_REG S3C_USBDREG(0x50) /* DMA Total Transfer count2 */
++#define S3C_UDC_DMA_IF_CON_REG S3C_USBDREG(0x84) /* DMA interface Control */
++#define S3C_UDC_DMA_MEM_BASE_ADDR_REG S3C_USBDREG(0x88) /* Mem Base Addr */
++#define S3C_UDC_DMA_MEM_CURRENT_ADDR_REG S3C_USBDREG(0x8c) /* Mem current Addr */
++
++#define S3C_UDC_FCON_REG S3C_USBDREG(0x100) /* Mem current Addr */
++#define S3C_UDC_FSTAT_REG S3C_USBDREG(0x104) /* Mem current Addr */
++
++
++/* EP interrupt register Bits */
++#define S3C_UDC_INT_EP3 (1<<3) // R/C
++#define S3C_UDC_INT_EP2 (1<<2) // R/C
++#define S3C_UDC_INT_EP1 (1<<1) // R/C
++#define S3C_UDC_INT_EP0 (1<<0) // R/C
++
++/* System status register Bits */
++#define S3C_UDC_INT_CHECK (0xff8f)
++#define S3C_UDC_INT_ERR (0xff80) // R/C
++#define S3C_UDC_INT_VBUSON (1<<8) // R/C
++#define S3C_UDC_INT_HSP (1<<4) // R
++#define S3C_UDC_INT_SDE (1<<3) // R/C
++#define S3C_UDC_INT_RESUME (1<<2) // R/C
++#define S3C_UDC_INT_SUSPEND (1<<1) // R/C
++#define S3C_UDC_INT_RESET (1<<0) // R/C
++
++/* system control register Bits */
++#define S3C_UDC_DTZIEN_EN (1<<14)
++#define S3C_UDC_RRD_EN (1<<5)
++#define S3C_UDC_SUS_EN (1<<1)
++#define S3C_UDC_RST_EN (1<<0)
++
++/* EP0 status register Bits */
++#define S3C_UDC_EP0_LWO (1<<6)
++#define S3C_UDC_EP0_STALL (1<<4)
++#define S3C_UDC_EP0_TX_SUCCESS (1<<1)
++#define S3C_UDC_EP0_RX_SUCCESS (1<<0)
++
++/* EP status register Bits */
++#define S3C_UDC_EP_FPID (1<<11)
++#define S3C_UDC_EP_OSD (1<<10)
++#define S3C_UDC_EP_DTCZ (1<<9)
++#define S3C_UDC_EP_SPT (1<<8)
++
++#define S3C_UDC_EP_DOM (1<<7)
++#define S3C_UDC_EP_FIFO_FLUSH (1<<6)
++#define S3C_UDC_EP_STALL (1<<5)
++#define S3C_UDC_EP_LWO (1<<4)
++#define S3C_UDC_EP_PSIF_ONE (1<<2)
++#define S3C_UDC_EP_PSIF_TWO (2<<2)
++#define S3C_UDC_EP_TX_SUCCESS (1<<1)
++#define S3C_UDC_EP_RX_SUCCESS (1<<0)
++
++// USB2.0 DMA Operation
++#define S3C_DMA_AUTO_RX_ENABLE (0x0<<5)
++#define S3C_DMA_AUTO_RX_DISABLE (0x1<<5)
++#define S3C_DMA_FLY_ENABLE (0x1<<4)
++#define S3C_DMA_FLY_DISABLE (0x0<<4)
++#define S3C_DMA_DEMEND_ENABLE (0x1<<3)
++#define S3C_DMA_DEMEND_DISABLE (0x0<<3)
++#define S3C_DMA_TX_START (0x1<<2)
++#define S3C_DMA_TX_STOP (0x0<<2)
++#define S3C_DMA_RX_START (0x1<<1)
++#define S3C_DMA_RX_STOP (0x0<<1)
++#define S3C_USB_DMA_MODE (0x1<<0)
++#define S3C_USB_INT_MODE (0x0<<0)
++
++#define S3C_MAX_BURST_INCR16 (0x3<<0)
++#define S3C_MAX_BURST_INCR8 (0x2<<0)
++#define S3C_MAX_BURST_INCR4 (0x1<<0)
++#define S3C_MAX_BURST_SINGLE (0x0<<0)
++
++#define S3C_DMA_ENABLE (0x1<<8)
++#define S3C_DMA_DISABLE (0x0<<8)
++#define S3C_DMA_TFCLR (0x1<<4)
++#define S3C_DMA_RFCLR (0x1<<0)
++
++#endif
++
+diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h
+new file mode 100644
+index 0000000..3c83546
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-udc.h
+@@ -0,0 +1,157 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
++ *
++ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
++ *
++ * This include file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++*/
++
++#ifndef __ASM_ARCH_REGS_UDC_H
++#define __ASM_ARCH_REGS_UDC_H
++
++#define S3C2410_USBDREG(x) (x)
++
++#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
++#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
++#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
++
++#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
++#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
++
++#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
++
++#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
++#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
++
++#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
++#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
++#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
++#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
++#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
++
++#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
++#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
++#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
++#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
++#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
++#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
++
++#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
++#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
++#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
++#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
++#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
++#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
++
++#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
++#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
++#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
++#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
++#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
++#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
++
++#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
++#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
++#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
++#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
++#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
++#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
++
++#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
++
++/* indexed registers */
++
++#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
++
++#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
++
++#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
++#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
++
++#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
++#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
++#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
++#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
++
++
++
++#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
++#define S3C2410_UDC_PWR_RESET (1<<3) // R
++#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
++#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
++#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
++
++#define S3C2410_UDC_PWR_DEFAULT 0x00
++
++#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
++#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
++#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
++#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
++#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
++
++#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
++#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
++#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
++
++#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
++#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
++#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
++#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
++#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
++
++#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
++#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
++
++
++#define S3C2410_UDC_INDEX_EP0 (0x00)
++#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
++#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
++#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
++#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
++
++#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
++#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
++#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
++#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
++#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
++#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
++
++#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
++#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
++#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
++#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
++
++#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
++#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
++#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
++#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
++#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
++#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
++#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
++
++#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
++#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
++#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
++
++#define S3C2410_UDC_SETIX(base,x) \
++ writel(S3C2410_UDC_INDEX_ ## x, base+S3C2410_UDC_INDEX_REG);
++
++
++#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
++#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
++#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
++#define S3C2410_UDC_EP0_CSR_DE (1<<3)
++#define S3C2410_UDC_EP0_CSR_SE (1<<4)
++#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
++#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
++#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
++
++#define S3C2410_UDC_MAXP_8 (1<<0)
++#define S3C2410_UDC_MAXP_16 (1<<1)
++#define S3C2410_UDC_MAXP_32 (1<<2)
++#define S3C2410_UDC_MAXP_64 (1<<3)
++
++
++#endif
+diff --git a/include/asm-arm/arch-s3c2410/regs-usb-otg-hs.h b/include/asm-arm/arch-s3c2410/regs-usb-otg-hs.h
+new file mode 100644
+index 0000000..7020a76
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-usb-otg-hs.h
+@@ -0,0 +1,307 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-udc.h
++ *
++ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
++ *
++ * This include file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++*/
++
++#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
++#define __ASM_ARCH_REGS_USB_OTG_HS_H
++
++/* USB2.0 OTG Controller register */
++#define S3C_USBOTG_PHYREG(x) ((x) + S3C24XX_VA_OTGSFR)
++#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0)
++#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4)
++#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8)
++
++
++/* USB2.0 OTG Controller register */
++#define S3C_USBOTGREG(x) ((x) + S3C24XX_VA_OTG)
++//==============================================================================================
++ // Core Global Registers
++#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) // OTG Control & Status
++#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) // OTG Interrupt
++#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) // Core AHB Configuration
++#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) // Core USB Configuration
++#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) // Core Reset
++#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) // Core Interrupt
++#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) // Core Interrupt Mask
++#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) // Receive Status Debug Read/Status Read
++#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) // Receive Status Debug Pop/Status Pop
++#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) // Receive FIFO Size
++#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) // Non-Periodic Transmit FIFO Size
++#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) // Non-Periodic Transmit FIFO/Queue Status
++
++#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) // Host Periodic Transmit FIFO Size
++#define S3C_UDC_OTG_DPTXFSIZ1 S3C_USBOTGREG(0x104) // Device Periodic Transmit FIFO-1 Size
++#define S3C_UDC_OTG_DPTXFSIZ2 S3C_USBOTGREG(0x108) // Device Periodic Transmit FIFO-2 Size
++#define S3C_UDC_OTG_DPTXFSIZ3 S3C_USBOTGREG(0x10C) // Device Periodic Transmit FIFO-3 Size
++#define S3C_UDC_OTG_DPTXFSIZ4 S3C_USBOTGREG(0x110) // Device Periodic Transmit FIFO-4 Size
++#define S3C_UDC_OTG_DPTXFSIZ5 S3C_USBOTGREG(0x114) // Device Periodic Transmit FIFO-5 Size
++#define S3C_UDC_OTG_DPTXFSIZ6 S3C_USBOTGREG(0x118) // Device Periodic Transmit FIFO-6 Size
++#define S3C_UDC_OTG_DPTXFSIZ7 S3C_USBOTGREG(0x11C) // Device Periodic Transmit FIFO-7 Size
++#define S3C_UDC_OTG_DPTXFSIZ8 S3C_USBOTGREG(0x120) // Device Periodic Transmit FIFO-8 Size
++#define S3C_UDC_OTG_DPTXFSIZ9 S3C_USBOTGREG(0x124) // Device Periodic Transmit FIFO-9 Size
++#define S3C_UDC_OTG_DPTXFSIZ10 S3C_USBOTGREG(0x128) // Device Periodic Transmit FIFO-10 Size
++#define S3C_UDC_OTG_DPTXFSIZ11 S3C_USBOTGREG(0x12C) // Device Periodic Transmit FIFO-11 Size
++#define S3C_UDC_OTG_DPTXFSIZ12 S3C_USBOTGREG(0x130) // Device Periodic Transmit FIFO-12 Size
++#define S3C_UDC_OTG_DPTXFSIZ13 S3C_USBOTGREG(0x134) // Device Periodic Transmit FIFO-13 Size
++#define S3C_UDC_OTG_DPTXFSIZ14 S3C_USBOTGREG(0x138) // Device Periodic Transmit FIFO-14 Size
++#define S3C_UDC_OTG_DPTXFSIZ15 S3C_USBOTGREG(0x13C) // Device Periodic Transmit FIFO-15 Size
++
++//==============================================================================================
++// Host Mode Registers
++//------------------------------------------------
++// Host Global Registers
++#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) // Host Configuration
++#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) // Host Frame Interval
++#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) // Host Frame Number/Frame Time Remaining
++#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) // Host Periodic Transmit FIFO/Queue Status
++#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) // Host All Channels Interrupt
++#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) // Host All Channels Interrupt Mask
++
++//------------------------------------------------
++// Host Port Control & Status Registers
++#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) // Host Port Control & Status
++
++//------------------------------------------------
++// Host Channel-Specific Registers
++#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) // Host Channel-0 Characteristics
++#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) // Host Channel-0 Split Control
++#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) // Host Channel-0 Interrupt
++#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) // Host Channel-0 Interrupt Mask
++#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) // Host Channel-0 Transfer Size
++#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) // Host Channel-0 DMA Address
++
++
++//==============================================================================================
++// Device Mode Registers
++//------------------------------------------------
++// Device Global Registers
++#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) // Device Configuration
++#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) // Device Control
++#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) // Device Status
++#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) // Device IN Endpoint Common Interrupt Mask
++#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) // Device OUT Endpoint Common Interrupt Mask
++#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) // Device All Endpoints Interrupt
++#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) // Device All Endpoints Interrupt Mask
++#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) // Device IN Token Sequence Learning Queue Read 1
++#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) // Device IN Token Sequence Learning Queue Read 2
++#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) // Device VBUS Discharge Time
++#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) // Device VBUS Pulsing Time
++#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) // Device IN Token Sequence Learning Queue Read 3
++#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) // Device IN Token Sequence Learning Queue Read 4
++
++//------------------------------------------------
++// Device Logical IN Endpoint-Specific Registers
++#define S3C_UDC_OTG_DIEPCTL0 S3C_USBOTGREG(0x900) // Device IN Endpoint 0 Control
++#define S3C_UDC_OTG_DIEPINT0 S3C_USBOTGREG(0x908) // Device IN Endpoint 0 Interrupt
++#define S3C_UDC_OTG_DIEPTSIZ0 S3C_USBOTGREG(0x910) // Device IN Endpoint 0 Transfer Size
++#define S3C_UDC_OTG_DIEPDMA0 S3C_USBOTGREG(0x914) // Device IN Endpoint 0 DMA Address
++
++#define S3C_UDC_OTG_DIEPCTL1 S3C_USBOTGREG(0x920) // Device IN Endpoint 2 Control
++#define S3C_UDC_OTG_DIEPINT1 S3C_USBOTGREG(0x928) // Device IN Endpoint 2 Interrupt
++#define S3C_UDC_OTG_DIEPTSIZ1 S3C_USBOTGREG(0x930) // Device IN Endpoint 2 Transfer Size
++#define S3C_UDC_OTG_DIEPDMA1 S3C_USBOTGREG(0x934) // Device IN Endpoint 2 DMA Address
++
++#define S3C_UDC_OTG_DIEPCTL2 S3C_USBOTGREG(0x940) // Device IN Endpoint 2 Control
++#define S3C_UDC_OTG_DIEPINT2 S3C_USBOTGREG(0x948) // Device IN Endpoint 2 Interrupt
++#define S3C_UDC_OTG_DIEPTSIZ2 S3C_USBOTGREG(0x950) // Device IN Endpoint 2 Transfer Size
++#define S3C_UDC_OTG_DIEPDMA2 S3C_USBOTGREG(0x954) // Device IN Endpoint 2 DMA Address
++
++#define S3C_UDC_OTG_DIEPCTL3 S3C_USBOTGREG(0x960) // Device IN Endpoint 3 Control
++#define S3C_UDC_OTG_DIEPINT3 S3C_USBOTGREG(0x968) // Device IN Endpoint 3 Interrupt
++#define S3C_UDC_OTG_DIEPTSIZ3 S3C_USBOTGREG(0x970) // Device IN Endpoint 3 Transfer Size
++#define S3C_UDC_OTG_DIEPDMA3 S3C_USBOTGREG(0x974) // Device IN Endpoint 3 DMA Address
++
++#define S3C_UDC_OTG_DIEPCTL4 S3C_USBOTGREG(0x980) // Device IN Endpoint 4 Control
++#define S3C_UDC_OTG_DIEPINT4 S3C_USBOTGREG(0x988) // Device IN Endpoint 4 Interrupt
++#define S3C_UDC_OTG_DIEPTSIZ4 S3C_USBOTGREG(0x990) // Device IN Endpoint 4 Transfer Size
++#define S3C_UDC_OTG_DIEPDMA4 S3C_USBOTGREG(0x994) // Device IN Endpoint 4 DMA Address
++
++#define S3C_UDC_OTG_DIEPCTL5 S3C_USBOTGREG(0xa00) // Device IN Endpoint 5 Control
++#define S3C_UDC_OTG_DIEPINT5 S3C_USBOTGREG(0xa08) // Device IN Endpoint 5 Interrupt
++#define S3C_UDC_OTG_DIEPTSIZ5 S3C_USBOTGREG(0xa10) // Device IN Endpoint 5 Transfer Size
++#define S3C_UDC_OTG_DIEPDMA5 S3C_USBOTGREG(0xa14) // Device IN Endpoint 5 DMA Address
++
++#define S3C_UDC_OTG_DIEPCTL6 S3C_USBOTGREG(0xa20) // Device IN Endpoint 6 Control
++#define S3C_UDC_OTG_DIEPINT6 S3C_USBOTGREG(0xa28) // Device IN Endpoint 6 Interrupt
++#define S3C_UDC_OTG_DIEPTSIZ6 S3C_USBOTGREG(0xa30) // Device IN Endpoint 6 Transfer Size
++#define S3C_UDC_OTG_DIEPDMA6 S3C_USBOTGREG(0xa34) // Device IN Endpoint 6 DMA Address
++
++//------------------------------------------------
++// Device Logical OUT Endpoint-Specific Registers
++#define S3C_UDC_OTG_DOEPCTL0 S3C_USBOTGREG(0xB00) // Device OUT Endpoint 0 Control
++#define S3C_UDC_OTG_DOEPINT0 S3C_USBOTGREG(0xB08) // Device OUT Endpoint 0 Interrupt
++#define S3C_UDC_OTG_DOEPTSIZ0 S3C_USBOTGREG(0xB10) // Device OUT Endpoint 0 Transfer Size
++#define S3C_UDC_OTG_DOEPDMA0 S3C_USBOTGREG(0xB14) // Device OUT Endpoint 0 DMA Address
++
++#define S3C_UDC_OTG_DOEPCTL1 S3C_USBOTGREG(0xB20) // Device OUT Endpoint 1 Control
++#define S3C_UDC_OTG_DOEPINT1 S3C_USBOTGREG(0xB28) // Device OUT Endpoint 1 Interrupt
++#define S3C_UDC_OTG_DOEPTSIZ1 S3C_USBOTGREG(0xB30) // Device OUT Endpoint 1 Transfer Size
++#define S3C_UDC_OTG_DOEPDMA1 S3C_USBOTGREG(0xB34) // Device OUT Endpoint 1 DMA Address
++
++#define S3C_UDC_OTG_DOEPCTL2 S3C_USBOTGREG(0xB40) // Device OUT Endpoint 2 Control
++#define S3C_UDC_OTG_DOEPINT2 S3C_USBOTGREG(0xB48) // Device OUT Endpoint 2 Interrupt
++#define S3C_UDC_OTG_DOEPTSIZ2 S3C_USBOTGREG(0xB50) // Device OUT Endpoint 2 Transfer Size
++#define S3C_UDC_OTG_DOEPDMA2 S3C_USBOTGREG(0xB54) // Device OUT Endpoint 2 DMA Address
++
++#define S3C_UDC_OTG_DOEPCTL3 S3C_USBOTGREG(0xB60) // Device OUT Endpoint 3 Control
++#define S3C_UDC_OTG_DOEPINT3 S3C_USBOTGREG(0xB68) // Device OUT Endpoint 3 Interrupt
++#define S3C_UDC_OTG_DOEPTSIZ3 S3C_USBOTGREG(0xB70) // Device OUT Endpoint 3 Transfer Size
++#define S3C_UDC_OTG_DOEPDMA3 S3C_USBOTGREG(0xB74) // Device OUT Endpoint 3 DMA Address
++
++#define S3C_UDC_OTG_DOEPCTL4 S3C_USBOTGREG(0xB80) // Device OUT Endpoint 4 Control
++#define S3C_UDC_OTG_DOEPINT4 S3C_USBOTGREG(0xB88) // Device OUT Endpoint 4 Interrupt
++#define S3C_UDC_OTG_DOEPTSIZ4 S3C_USBOTGREG(0xB90) // Device OUT Endpoint 4 Transfer Size
++#define S3C_UDC_OTG_DOEPDMA4 S3C_USBOTGREG(0xB94) // Device OUT Endpoint 4 DMA Address
++
++//------------------------------------------------
++// Endpoint FIFO address
++#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000)
++#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000)
++#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000)
++#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000)
++#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000)
++#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000)
++#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000)
++#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000)
++#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000)
++
++//=====================================================================
++//definitions related to CSR setting
++
++// S3C_UDC_OTG_GOTGCTL
++#define B_SESSION_VALID (0x1<<19)
++#define A_SESSION_VALID (0x1<<18)
++
++// S3C_UDC_OTG_GAHBCFG
++#define PTXFE_HALF (0<<8)
++#define PTXFE_ZERO (1<<8)
++#define NPTXFE_HALF (0<<7)
++#define NPTXFE_ZERO (1<<7)
++#define MODE_SLAVE (0<<5)
++#define MODE_DMA (1<<5)
++#define BURST_SINGLE (0<<1)
++#define BURST_INCR (1<<1)
++#define BURST_INCR4 (3<<1)
++#define BURST_INCR8 (5<<1)
++#define BURST_INCR16 (7<<1)
++#define GBL_INT_UNMASK (1<<0)
++#define GBL_INT_MASK (0<<0)
++
++// S3C_UDC_OTG_GRSTCTL
++#define AHB_MASTER_IDLE (1u<<31)
++#define CORE_SOFT_RESET (0x1<<0)
++
++// S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register
++#define INT_RESUME (1u<<31)
++#define INT_DISCONN (0x1<<29)
++#define INT_CONN_ID_STS_CNG (0x1<<28)
++#define INT_OUT_EP (0x1<<19)
++#define INT_IN_EP (0x1<<18)
++#define INT_ENUMDONE (0x1<<13)
++#define INT_RESET (0x1<<12)
++#define INT_SUSPEND (0x1<<11)
++#define INT_EARLY_SUSPEND (0x1<<10)
++#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
++#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
++#define INT_SOF (0x1<<3)
++#define INT_DEV_MODE (0x0<<0)
++#define INT_HOST_MODE (0x1<<1)
++#define INT_GOUTNakEff (0x01<<7)
++#define INT_GINNakEff (0x01<<6)
++
++#define FULL_SPEED_CONTROL_PKT_SIZE 8
++#define FULL_SPEED_BULK_PKT_SIZE 64
++
++#define HIGH_SPEED_CONTROL_PKT_SIZE 64
++#define HIGH_SPEED_BULK_PKT_SIZE 512
++
++#define RX_FIFO_SIZE 2048
++#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE
++#define NPTX_FIFO_SIZE 2048
++#define PTX_FIFO_SIZE 2048
++
++#define DEPCTL_TXFNUM_0 (0x0<<22)
++#define DEPCTL_TXFNUM_1 (0x1<<22)
++#define DEPCTL_TXFNUM_2 (0x2<<22)
++#define DEPCTL_TXFNUM_3 (0x3<<22)
++#define DEPCTL_TXFNUM_4 (0x4<<22)
++
++
++// Enumeration speed
++#define USB_HIGH_30_60MHZ (0x0<<1)
++#define USB_FULL_30_60MHZ (0x1<<1)
++#define USB_LOW_6MHZ (0x2<<1)
++#define USB_FULL_48MHZ (0x3<<1)
++
++// S3C_UDC_OTG_GRXSTSP STATUS
++#define OUT_PKT_RECEIVED (0x2<<17)
++#define OUT_TRANSFER_COMPLELTED (0x3<<17)
++#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
++#define SETUP_PKT_RECEIVED (0x6<<17)
++#define GLOBAL_OUT_NAK (0x1<<17)
++
++
++// S3C_UDC_OTG_DCTL device control register
++#define NORMAL_OPERATION (0x1<<0)
++#define SOFT_DISCONNECT (0x1<<1)
++
++// S3C_UDC_OTG_DAINT device all endpoint interrupt register
++#define S3C_UDC_INT_IN_EP0 (0x1<<0)
++#define S3C_UDC_INT_IN_EP2 (0x1<<2)
++#define S3C_UDC_INT_IN_EP3 (0x1<<3)
++#define S3C_UDC_INT_OUT_EP0 (0x1<<16)
++#define S3C_UDC_INT_OUT_EP1 (0x1<<17)
++#define S3C_UDC_INT_OUT_EP4 (0x1<<20)
++
++
++
++// S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register
++#define DEPCTL_EPENA (0x1<<31)
++#define DEPCTL_EPDIS (0x1<<30)
++#define DEPCTL_SNAK (0x1<<27)
++#define DEPCTL_CNAK (0x1<<26)
++#define DEPCTL_CTRL_TYPE (0x0<<18)
++#define DEPCTL_ISO_TYPE (0x1<<18)
++#define DEPCTL_BULK_TYPE (0x2<<18)
++#define DEPCTL_INTR_TYPE (0x3<<18)
++#define DEPCTL_USBACTEP (0x1<<15)
++#define DEPCTL0_MPS_64 (0x0<<0)
++#define DEPCTL0_MPS_32 (0x1<<0)
++#define DEPCTL0_MPS_16 (0x2<<0)
++#define DEPCTL0_MPS_8 (0x3<<0)
++#define DEPCTL_MPS_BULK_512 (512<<0)
++#define DEPCTL_MPS_INT_MPS_16 (16<<0)
++
++#define DIEPCTL0_NEXT_EP_BIT (11)
++
++// S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register
++
++// S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register
++// S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register
++#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
++#define INTKNEPMIS (0x1<<5)
++#define INTKN_TXFEMP (0x1<<4)
++#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
++#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
++#define AHB_ERROR (0x1<<2)
++#define EPDISBLD (0x1<<1)
++#define TRANSFER_DONE (0x1<<0)
++
++//DIEPTSIZ0 / DOEPTSIZ0
++
++// DEPTSIZ common bit
++#define DEPTSIZ_PKT_CNT_BIT (19)
++#define DEPTSIZ_XFER_SIZE_BIT (0)
++
++#define DEPTSIZ_SETUP_PKCNT_1 (1<<29)
++#define DEPTSIZ_SETUP_PKCNT_2 (2<<29)
++#define DEPTSIZ_SETUP_PKCNT_3 (3<<29)
++
++
++#endif
+diff --git a/include/asm-arm/arch-s3c2410/reserved_mem.h b/include/asm-arm/arch-s3c2410/reserved_mem.h
+new file mode 100644
+index 0000000..4fa5611
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/reserved_mem.h
+@@ -0,0 +1,89 @@
++#ifndef _ASM_ARM_ARCH_RESERVED_MEM_H
++#define _ASM_ARM_ARCH_RESERVED_MEM_H
++
++
++/*
++ * Default reserved memory size
++ * MFC : 6 MB
++ * Post : 8 MB
++ * JPEG : 8 MB
++ * CMM : 8 MB
++ * TV : 8 MB
++ * Camera : 15 MB
++ * These sizes can be modified
++ */
++
++
++//#define CONFIG_RESERVED_MEM_JPEG
++//#define CONFIG_RESERVED_MEM_JPEG_POST
++//#define CONFIG_RESERVED_MEM_MFC
++//#define CONFIG_RESERVED_MEM_MFC_POST
++//#define CONFIG_RESERVED_MEM_JPEG_MFC_POST
++//#define CONFIG_RESERVED_MEM_JPEG_CAMERA
++//#define CONFIG_RESERVED_MEM_JPEG_POST_CAMERA
++//#define CONFIG_RESERVED_MEM_MFC_CAMERA
++//#define CONFIG_RESERVED_MEM_MFC_POST_CAMERA
++//#define CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA
++//#define CONFIG_RESERVED_MEM_CMM_MFC_POST
++//#define CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA
++//#define CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA
++
++#if defined(CONFIG_RESERVED_MEM_JPEG)
++#define JPEG_RESERVED_MEM_START 0x57800000
++
++#elif defined(CONFIG_RESERVED_MEM_JPEG_POST)
++#define JPEG_RESERVED_MEM_START 0x57000000
++#define POST_RESERVED_MEM_START 0x57800000
++
++#elif defined(CONFIG_RESERVED_MEM_MFC)
++#define MFC_RESERVED_MEM_START 0x57A00000
++
++#elif defined(CONFIG_RESERVED_MEM_MFC_POST)
++#define MFC_RESERVED_MEM_START 0x57200000
++#define POST_RESERVED_MEM_START 0x57800000
++
++#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST)
++#define JPEG_RESERVED_MEM_START 0x56A00000
++#define MFC_RESERVED_MEM_START 0x57200000
++#define POST_RESERVED_MEM_START 0x57800000
++
++#elif defined(CONFIG_RESERVED_MEM_JPEG_CAMERA)
++#define JPEG_RESERVED_MEM_START 0x56900000
++
++#elif defined(CONFIG_RESERVED_MEM_JPEG_POST_CAMERA)
++#define JPEG_RESERVED_MEM_START 0x56100000
++#define POST_RESERVED_MEM_START 0x56900000
++
++#elif defined(CONFIG_RESERVED_MEM_MFC_CAMERA)
++#define MFC_RESERVED_MEM_START 0x56B00000
++
++#elif defined(CONFIG_RESERVED_MEM_MFC_POST_CAMERA)
++#define MFC_RESERVED_MEM_START 0x56300000
++#define POST_RESERVED_MEM_START 0x56900000
++
++#elif defined(CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA)
++#define JPEG_RESERVED_MEM_START 0x55B00000
++#define MFC_RESERVED_MEM_START 0x56300000
++#define POST_RESERVED_MEM_START 0x56900000
++
++#elif defined (CONFIG_RESERVED_MEM_CMM_MFC_POST)
++#define CMM_RESERVED_MEM_START 0x56A00000
++#define MFC_RESERVED_MEM_START 0x57200000
++#define POST_RESERVED_MEM_START 0x57800000
++
++#elif defined (CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA)
++#define CMM_RESERVED_MEM_START 0x55300000
++#define JPEG_RESERVED_MEM_START 0x55B00000
++#define MFC_RESERVED_MEM_START 0x56300000
++#define POST_RESERVED_MEM_START 0x56900000
++
++#elif defined (CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA)
++#define TV_RESERVED_MEM_START 0x55B00000
++#define MFC_RESERVED_MEM_START 0x56300000
++#define POST_RESERVED_MEM_START 0x56900000
++
++#endif
++
++
++#endif /* _ASM_ARM_ARCH_RESERVED_MEM_H */
++
+diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
+index 6389178..91a0d0c 100644
+--- a/include/asm-arm/arch-s3c2410/system.h
++++ b/include/asm-arm/arch-s3c2410/system.h
+@@ -56,6 +56,7 @@ static void arch_idle(void)
+ s3c24xx_default_idle();
+ }
+
++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410)
+ static void
+ arch_reset(char mode)
+ {
+@@ -86,3 +87,28 @@ arch_reset(char mode)
+ /* we'll take a jump through zero as a poor second */
+ cpu_reset(0);
+ }
++#else
++#define S3C6400_SW_RESET_OFF 0x114
++static void
++arch_reset(char mode)
++{
++ if (mode == 's') {
++ cpu_reset(0);
++ }
++
++ if (s3c24xx_reset_hook)
++ s3c24xx_reset_hook();
++
++ printk("arch_reset: attempting watchdog reset\n");
++
++ __raw_writel(0x6400, S3C24XX_VA_SYSCON + S3C6400_SW_RESET_OFF);
++
++ /* wait for reset to assert... */
++ mdelay(5000);
++
++ printk(KERN_ERR "Watchdog reset failed to assert reset\n");
++
++ /* we'll take a jump through zero as a poor second */
++ cpu_reset(0);
++}
++#endif
+diff --git a/include/asm-arm/arch-s3c2410/timex.h b/include/asm-arm/arch-s3c2410/timex.h
+index c16a99c..13a2a27 100644
+--- a/include/asm-arm/arch-s3c2410/timex.h
++++ b/include/asm-arm/arch-s3c2410/timex.h
+@@ -18,9 +18,20 @@
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+ */
++#if defined (CONFIG_PLAT_S3C64XX) || defined (CONFIG_PLAT_S5PC1XX)
+
++#define PRESCALER 4
++#define DIVIDER 1
++
++#define PCLK_INPUT 51000000
++/* CLOCK_TICK_RATE is the time of a timer count desence, minsung says*/
++#define CLOCK_TICK_RATE (PCLK_INPUT / ((PRESCALER + 1) * DIVIDER))
++
++
++#else
+
+ #define CLOCK_TICK_RATE 12000000
+
++#endif
+
+ #endif /* __ASM_ARCH_TIMEX_H */
+diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
+index 1b882a2..8bf9c64 100644
+--- a/include/asm-arm/irq.h
++++ b/include/asm-arm/irq.h
+@@ -1,7 +1,11 @@
+ #ifndef __ASM_ARM_IRQ_H
+ #define __ASM_ARM_IRQ_H
+
++#ifdef CONFIG_CPU_S5PC100
++#include <asm/arch/irqs-s5pc100.h>
++#else
+ #include <asm/arch/irqs.h>
++#endif
+
+ #ifndef irq_canonicalize
+ #define irq_canonicalize(i) (i)
+diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
+index d9bfb39..2487829 100644
+--- a/include/asm-arm/memory.h
++++ b/include/asm-arm/memory.h
+@@ -114,7 +114,7 @@
+ * between 2MB and 14MB inclusive.
+ */
+ #ifndef CONSISTENT_DMA_SIZE
+-#define CONSISTENT_DMA_SIZE SZ_2M
++#define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M)
+ #endif
+
+ /*
+diff --git a/include/asm-arm/plat-s3c/adc.h b/include/asm-arm/plat-s3c/adc.h
+new file mode 100644
+index 0000000..9224e37
+--- /dev/null
++++ b/include/asm-arm/plat-s3c/adc.h
+@@ -0,0 +1,29 @@
++/* linux/include/asm-arm/plat-s3c/adc.h
++ *
++ * Copyright (c) 2008 Jongpill Lee <Jongpill.Lee>
++ *
++ * This program is header file for ADC Driver in s3c64xx of SAMSUNG ELECTRONICS
++ *
++ */
++
++extern unsigned int s3c_adc_convert(void __iomem * reg_base, unsigned int s3c_adc_port);
++extern struct s3c_adc_cfg s3c_adc_platform;
++
++struct s3c_adc_request
++{
++ /* for linked list */
++ struct list_head *list;
++ /* after finish ADC sampling, s3c_adc_request function call this function with three parameter */
++ void (*callback)( int channel, unsigned long int param, unsigned short sample);
++ /* for private data */
++ unsigned long int param;
++ /* selected channel for ADC sampling */
++ int channel;
++};
++
++struct s3c_adc_cfg{
++ /* if you need to use some platform data, add in here*/
++ int delay;
++ int presc;
++ int resolution;
++};
+diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h
+index 71211c8..e7e0e16 100644
+--- a/include/asm-arm/plat-s3c/iic.h
++++ b/include/asm-arm/plat-s3c/iic.h
+@@ -21,12 +21,15 @@
+ */
+
+ struct s3c2410_platform_i2c {
++ int bus_num; /* bus number to use */
+ unsigned int flags;
+ unsigned int slave_addr; /* slave address for controller */
+ unsigned long bus_freq; /* standard bus frequency */
+ unsigned long max_freq; /* max frequency for the bus */
+ unsigned long min_freq; /* min frequency for the bus */
+ unsigned int sda_delay; /* pclks (s3c2440 only) */
++
++ void (*cfg_gpio)(struct platform_device *dev);
+ };
+
+ #endif /* __ASM_ARCH_IIC_H */
+diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
+index b84289d..20801c5 100644
+--- a/include/asm-arm/plat-s3c/map.h
++++ b/include/asm-arm/plat-s3c/map.h
+@@ -30,11 +30,34 @@
+ #define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
+ #endif
+
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++#define S3C_VA_IRQ S3C_ADDR(0x00700000) /* irq controller(s) in size of 2 or 4 MB */
++#else
+ #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
++#endif
++
+ #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
+-#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
++#define S3C_VA_MEM S3C_ADDR(0x00200000) /* mem control */
+ #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
+ #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
+ #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
+
++/* For S3C2450/S3C6400/S3C6410 */
++#define S3C_VA_LCD S3C_ADDR(0x00500000) /* LCD */
++#define S3C_VA_GPIO S3C_ADDR(0x00600000) /* GPIO */
++#define S3C_VA_HOSTIFA S3C_ADDR(0x00B00000) /* Host I/F Indirect & Direct */
++#define S3C_VA_HOSTIFB S3C_ADDR(0x00C00000) /* Host I/F Indirect & Direct */
++#define S3C_VA_SYSCON S3C_ADDR(0x02800000) /* System Controller */
++#define S3C_VA_CS8900 S3C_ADDR(0x03600000) /* Ethernet */
++#define S3C_VA_SROMC S3C_ADDR(0x03700000) /* SROM SFR */
++#define S3C_VA_DMC0 S3C_ADDR(0x01f00000) /* DRAM controller 0 */
++#if !defined(CONFIG_PLAT_S5PC1XX)
++#define S3C_VA_DMC1 S3C_ADDR(0x03800000) /* DRAM controller 1 */
++#endif
++#define S3C_VA_OTG S3C_ADDR(0x03900000) /* USB OTG */
++#define S3C_VA_OTGSFR S3C_ADDR(0x03a00000) /* USB OTG SFR */
++#define S3C_VA_EBI S3C_ADDR(0x03c00000) /* EBI registers */
++#define S3C_VA_USBDEV S3C_ADDR(0x03d00000) /* EBI registers */
++
++#define S3C_VA_CHIP_ID S3C_ADDR(0x03f00000) /* Chip ID */
+ #endif /* __ASM_PLAT_MAP_H */
+diff --git a/include/asm-arm/plat-s3c/nand.h b/include/asm-arm/plat-s3c/nand.h
+index 8816f7f..e61c927 100644
+--- a/include/asm-arm/plat-s3c/nand.h
++++ b/include/asm-arm/plat-s3c/nand.h
+@@ -43,3 +43,9 @@ struct s3c2410_platform_nand {
+ int chip);
+ };
+
++struct s3c_nand_mtd_info {
++ uint chip_nr;
++ uint mtd_part_nr;
++ struct mtd_partition *partition;
++};
++
+diff --git a/include/asm-arm/plat-s3c/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
+index c7f2319..aa86c3e 100644
+--- a/include/asm-arm/plat-s3c/regs-adc.h
++++ b/include/asm-arm/plat-s3c/regs-adc.h
+@@ -19,15 +19,24 @@
+ #define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
+ #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
+ #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
++#define S3C2410_ADCUPDN S3C2410_ADCREG(0x14)
++#define S3C2443_ADCMUX S3C2410_ADCREG(0x18)
++#define S3C6400_ADCCLRINT S3C2410_ADCREG(0x18)
++#define S3C6400_ADCCLRWK S3C2410_ADCREG(0x20)
+
+
+ /* ADCCON Register Bits */
++#define S3C6410_ADCCON_RESSEL_10BIT (0x0<<16)
++#define S3C6410_ADCCON_RESSEL_12BIT (0x1<<16)
+ #define S3C2410_ADCCON_ECFLG (1<<15)
+ #define S3C2410_ADCCON_PRSCEN (1<<14)
+ #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
+ #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
+ #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
++#define S3C2443_ADCCON_SELMUX(x) (((x)&0xF)<<0)
+ #define S3C2410_ADCCON_MUXMASK (0x7<<3)
++#define S3C2450_ADCCON_RESSEL_10BIT (0x0<<3)
++#define S3C2450_ADCCON_RESSEL_12BIT (0x1<<3)
+ #define S3C2410_ADCCON_STDBM (1<<2)
+ #define S3C2410_ADCCON_READ_START (1<<1)
+ #define S3C2410_ADCCON_ENABLE_START (1<<0)
+@@ -35,6 +44,7 @@
+
+
+ /* ADCTSC Register Bits */
++#define S3C2410_ADCTSC_UD_SEN (1<<8)
+ #define S3C2410_ADCTSC_YM_SEN (1<<7)
+ #define S3C2410_ADCTSC_YP_SEN (1<<6)
+ #define S3C2410_ADCTSC_XM_SEN (1<<5)
+@@ -48,12 +58,14 @@
+ #define S3C2410_ADCDAT0_AUTO_PST (1<<14)
+ #define S3C2410_ADCDAT0_XY_PST (0x3<<12)
+ #define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
++#define S3C_ADCDAT0_XPDATA_MASK_12BIT (0x0FFF)
+
+ /* ADCDAT1 Bits */
+ #define S3C2410_ADCDAT1_UPDOWN (1<<15)
+ #define S3C2410_ADCDAT1_AUTO_PST (1<<14)
+ #define S3C2410_ADCDAT1_XY_PST (0x3<<12)
+ #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
++#define S3C_ADCDAT1_YPDATA_MASK_12BIT (0x0FFF)
+
+ #endif /* __ASM_ARCH_REGS_ADC_H */
+
+diff --git a/include/asm-arm/plat-s3c/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
+index 2ae2952..e54ace4 100644
+--- a/include/asm-arm/plat-s3c/regs-iic.h
++++ b/include/asm-arm/plat-s3c/regs-iic.h
+@@ -15,6 +15,8 @@
+
+ /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
+
++#ifndef CONFIG_PLAT_S3C64XX
++
+ #define S3C2410_IICREG(x) (x)
+
+ #define S3C2410_IICCON S3C2410_IICREG(0x00)
+@@ -53,4 +55,46 @@
+
+ #define S3C2410_IICLC_FILTER_ON (1<<2)
+
++#else
++
++#define S3C64XX_IICREG(x) (x)
++
++#define S3C64XX_IICCON S3C64XX_IICREG(0x00)
++#define S3C64XX_IICSTAT S3C64XX_IICREG(0x04)
++#define S3C64XX_IICADD S3C64XX_IICREG(0x08)
++#define S3C64XX_IICDS S3C64XX_IICREG(0x0C)
++#define S3C2440_IICLC S3C64XX_IICREG(0x10)
++
++#define S3C64XX_IICCON_ACKEN (1<<7)
++#define S3C64XX_IICCON_TXDIV_16 (0<<6)
++#define S3C64XX_IICCON_TXDIV_512 (1<<6)
++#define S3C64XX_IICCON_IRQEN (1<<5)
++#define S3C64XX_IICCON_IRQPEND (1<<4)
++#define S3C64XX_IICCON_SCALE(x) ((x)&15)
++#define S3C64XX_IICCON_SCALEMASK (0xf)
++
++#define S3C64XX_IICSTAT_MASTER_RX (2<<6)
++#define S3C64XX_IICSTAT_MASTER_TX (3<<6)
++#define S3C64XX_IICSTAT_SLAVE_RX (0<<6)
++#define S3C64XX_IICSTAT_SLAVE_TX (1<<6)
++#define S3C64XX_IICSTAT_MODEMASK (3<<6)
++
++#define S3C64XX_IICSTAT_START (1<<5)
++#define S3C64XX_IICSTAT_BUSBUSY (1<<5)
++#define S3C64XX_IICSTAT_TXRXEN (1<<4)
++#define S3C64XX_IICSTAT_ARBITR (1<<3)
++#define S3C64XX_IICSTAT_ASSLAVE (1<<2)
++#define S3C64XX_IICSTAT_ADDR0 (1<<1)
++#define S3C64XX_IICSTAT_LASTBIT (1<<0)
++
++#define S3C64XX_IICLC_SDA_DELAY0 (0 << 0)
++#define S3C64XX_IICLC_SDA_DELAY5 (1 << 0)
++#define S3C64XX_IICLC_SDA_DELAY10 (2 << 0)
++#define S3C64XX_IICLC_SDA_DELAY15 (3 << 0)
++#define S3C64XX_IICLC_SDA_DELAY_MASK (3 << 0)
++
++#define S3C64XX_IICLC_FILTER_ON (1<<2)
++
++#endif
++
+ #endif /* __ASM_ARCH_REGS_IIC_H */
+diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
+index d742205..a010b85 100644
+--- a/include/asm-arm/plat-s3c/regs-nand.h
++++ b/include/asm-arm/plat-s3c/regs-nand.h
+@@ -11,7 +11,7 @@
+ */
+
+ #ifndef __ASM_ARM_REGS_NAND
+-#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
++#define __ASM_ARM_REGS_NAND "$Id: regs-nand.h,v 1.3 2008/09/12 05:19:53 jsgood Exp $"
+
+
+ #define S3C2410_NFREG(x) (x)
+@@ -85,6 +85,13 @@
+ #define S3C2412_NFCONF_NANDBOOT (1<<31)
+ #define S3C2412_NFCONF_ECCCLKCON (1<<30)
+ #define S3C2412_NFCONF_ECC_MLC (1<<24)
++
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++#define S3C_NFCONF_ECC_1BIT (0<<23)
++#define S3C_NFCONF_ECC_4BIT (2<<23)
++#define S3C_NFCONF_ECC_8BIT (1<<23)
++#endif
++
+ #define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
+
+ #define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
+@@ -117,6 +124,15 @@
+ #define S3C2412_NFECCERR_MULTIBIT (2)
+ #define S3C2412_NFECCERR_ECCAREA (3)
+
++#define S3C_NFMLCBITPT S3C2410_NFREG(0x40)
++
++#define S3C_NFCONF_PAGESIZE (1<<2)
++#define S3C_NFCONF_ADDRCYCLE (1<<1)
++#define S3C_NFSTAT0_ECCBUSY (1<<31)
++#define S3C_NFCONT_SECC_LOCK (1<<6)
++#define S3C_NFCONT_INITMECC (1<<5)
++#define S3C_NFCONT_INITSECC (1<<4)
++#define S3C_NFCONT_INITECC (S3C_NFCONT_INITSECC | S3C_NFCONT_INITMECC)
+
+
+ #endif /* __ASM_ARM_REGS_NAND */
+diff --git a/include/asm-arm/plat-s3c/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
+index 93b03c4..d81eedb 100644
+--- a/include/asm-arm/plat-s3c/regs-rtc.h
++++ b/include/asm-arm/plat-s3c/regs-rtc.h
+@@ -21,6 +21,22 @@
+ #define S3C2410_RTCCON_CNTSEL (1<<2)
+ #define S3C2410_RTCCON_CLKRST (1<<3)
+
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
++#define S3C_MAX_CNT 32768
++#define S3C_RTCCON_TICEN (1<<8)
++#define S3C_RTC_TICNT S3C2410_RTCREG(0x40)
++#else
++#define S3C_INTP_ALM (1<<1)
++#define S3C_MAX_CNT 128
++#define S3C_RTCCON_TICEN (1<<7)
++#define S3C_RTC_TICNT S3C2410_RTCREG(0x44)
++#endif
++
++/* Common Reg for samsung AP*/
++#define S3C_INTP S3C2410_RTCREG(0x30)
++#define S3C_INTP_ALM (1<<1)
++#define S3C_INTP_TIC (1<<0)
++
+ #define S3C2410_TICNT S3C2410_RTCREG(0x44)
+ #define S3C2410_TICNT_ENABLE (1<<7)
+
+diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
+index 923e114..78f50da 100644
+--- a/include/asm-arm/plat-s3c/regs-serial.h
++++ b/include/asm-arm/plat-s3c/regs-serial.h
+@@ -32,15 +32,27 @@
+ #ifndef __ASM_ARM_REGS_SERIAL_H
+ #define __ASM_ARM_REGS_SERIAL_H
+
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
+ #define S3C24XX_VA_UART0 (S3C_VA_UART)
+-#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
+-#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
+-#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
++#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x400)
++#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x800)
++#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC00)
+
+ #define S3C2410_PA_UART0 (S3C24XX_PA_UART)
+-#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
+-#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
+-#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
++#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x400)
++#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x800)
++#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC00)
++#else
++#define S3C24XX_VA_UART0 (S3C_VA_UART)
++#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000)
++#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000)
++#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000)
++
++#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
++#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000)
++#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000)
++#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000)
++#endif
+
+ #define S3C2410_URXH (0x24)
+ #define S3C2410_UTXH (0x20)
+@@ -175,6 +187,124 @@
+
+ #define S3C2443_DIVSLOT (0x2C)
+
++
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100)
++#define S3C_IRQ_UART0 IRQ_UART0
++#define S3C_IRQ_UART1 IRQ_UART1
++#define S3C_IRQ_UART2 IRQ_UART2
++#define S3C_IRQ_UART3 IRQ_UART3
++
++#define S3C_ULCON (0x00)
++#define S3C_UCON (0x04)
++#define S3C_UFCON (0x08)
++#define S3C_UMCON (0x0C)
++#define S3C_UTRSTAT (0x10)
++#define S3C_UERSTAT (0x14)
++#define S3C_UFSTAT (0x18)
++#define S3C_UMSTAT (0x1C)
++#define S3C_UTXH (0x20)
++#define S3C_URXH (0x24)
++#define S3C_UBRDIV (0x28)
++#define S3C_UDIVSLOT (0x2C)
++#define S3C_UINTPND (0x30)
++#define S3C_UINTSP (0x34)
++#define S3C_UINTMSK (0x38)
++
++/* base definitions for UART Line Control Register */
++#define S3C_LCON_CFGMASK (0x7f)
++
++#define S3C_LCON_CS5 (0x0)
++#define S3C_LCON_CS6 (0x1)
++#define S3C_LCON_CS7 (0x2)
++#define S3C_LCON_CS8 (0x3)
++#define S3C_LCON_CSMASK (0x3)
++
++#define S3C_LCON_PNONE (0x0)
++#define S3C_LCON_PEVEN (0x5 << 3)
++#define S3C_LCON_PODD (0x4 << 3)
++#define S3C_LCON_PMASK (0x7 << 3)
++
++#define S3C_LCON_STOPB (1<<2)
++#define S3C_LCON_IRM (1<<6)
++
++#define S3C_UCON_CLKMASK (3<<10)
++#define S3C_UCON_PCLK (0<<10)
++#define S3C_UCON_UCLK (1<<10)
++#define S3C_UCON_PCLK2 (2<<10)
++#define S3C_UCON_FCLK (3<<10)
++#define S3C_UCON_SBREAK (1<<4)
++
++#define S3C_UCON_TXILEVEL (1<<9)
++#define S3C_UCON_RXILEVEL (1<<8)
++#define S3C_UCON_TXIRQMODE (1<<2)
++#define S3C_UCON_RXIRQMODE (1<<0)
++#define S3C_UCON_RXFIFO_TOI (1<<7)
++#define S3C_UCON_RX_ESIE (1<<6)
++#define S3C_UCON_LOOP_OPERATION (0<<5)
++#define S3C_UCON_NO_SBS (0<<4)
++
++
++#define S3C_UCON_DEFAULT (S3C_UCON_TXILEVEL | \
++ S3C_UCON_RXILEVEL | \
++ S3C_UCON_TXIRQMODE | \
++ S3C_UCON_RXIRQMODE | \
++ S3C_UCON_RXFIFO_TOI)
++
++/* base definitions for UART FIFO Control Register */
++#define S3C_UFCON_FIFOMODE (1<<0)
++#define S3C_UFCON_RXTRIG12 (2<<4)
++
++/* S3C2413 FIFO trigger levels */
++#define S3C_UFCON_RXTRIG1 (0<<4)
++#define S3C_UFCON_RXTRIG8 (1<<4)
++#define S3C_UFCON_RXTRIG16 (2<<4)
++#define S3C_UFCON_RXTRIG32 (3<<4)
++
++#define S3C_UFCON_TXTRIG0 (0<<6)
++#define S3C_UFCON_TXTRIG16 (1<<6)
++#define S3C_UFCON_TXTRIG32 (2<<6)
++#define S3C_UFCON_TXTRIG48 (3<<6)
++
++#define S3C_UFCON_RESETBOTH (3<<1)
++#define S3C_UFCON_RESETTX (1<<2)
++#define S3C_UFCON_RESETRX (1<<1)
++#define S3C_UFCON_FIFO_ENABLE (1<<0)
++
++#define S3C_UFCON_DEFAULT (S3C_UFCON_FIFOMODE | \
++ S3C_UFCON_TXTRIG0 | \
++ S3C_UFCON_RXTRIG8 )
++
++#define S3C_UMCOM_AFC (1<<4)
++#define S3C_UMCOM_RTS_LOW (1<<0)
++
++#define S3C_UFSTAT_TXFULL (1<<14)
++#define S3C_UFSTAT_RXFULL (1<<6)
++#define S3C_UFSTAT_TXSHIFT (8)
++#define S3C_UFSTAT_RXSHIFT (0)
++#define S3C_UFSTAT_TXMASK (63<<8)
++#define S3C_UFSTAT_RXMASK (63)
++
++#define S3C_UTRSTAT_TXE (1<<2)
++#define S3C_UTRSTAT_TXFE (1<<1)
++#define S3C_UTRSTAT_RXDR (1<<0)
++
++#define UART_RX_INT (1<<0)
++#define UART_TX_INT (1<<2)
++#define UART_ERR_INT (1<<1)
++#define UART_MODEM_INT (1<<3)
++
++#define S3C_UERSTAT_OVERRUN (1<<0)
++#define S3C_UERSTAT_FRAME (1<<2)
++#define S3C_UERSTAT_BREAK (1<<3)
++#define S3C_UERSTAT_ANY (S3C_UERSTAT_OVERRUN | \
++ S3C_UERSTAT_FRAME | \
++ S3C_UERSTAT_BREAK)
++
++#define S3C_UMSTAT_CTS (1<<0)
++#define S3C_UMSTAT_DeltaCTS (1<<2)
++#endif
++
++
+ #ifndef __ASSEMBLY__
+
+ /* struct s3c24xx_uart_clksrc
+@@ -189,9 +319,23 @@
+ *
+ * divisor gives the divisor from the clock to the one seen by the uart
+ */
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100)
++#define NR_PORTS (4)
++#define UART_FIFO_SIZE 64
++#define UART_HAS_INTMSK
++#define UART_C_CFLAG
++#define UART_UMCON
++#define UART_CLK 115200
++#else
++#define NR_PORTS (3)
++#endif
++
+
+ struct s3c24xx_uart_clksrc {
+ const char *name;
++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100)
++ unsigned int clock_src;
++#endif
+ unsigned int divisor;
+ unsigned int min_baud;
+ unsigned int max_baud;
+@@ -208,8 +352,11 @@ struct s3c2410_uartcfg {
+ unsigned char hwport; /* hardware port number */
+ unsigned char unused;
+ unsigned short flags;
++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410) && !defined(CONFIG_CPU_S5PC100)
+ upf_t uart_flags; /* default uart flags */
+-
++#else
++ unsigned long uart_flags; /* default uart flags */
++#endif
+ unsigned long ucon; /* value of ucon for port */
+ unsigned long ulcon; /* value of ulcon for port */
+ unsigned long ufcon; /* value of ufcon for port */
+@@ -224,7 +371,7 @@ struct s3c2410_uartcfg {
+ * or platform_add_device() before the console_initcall()
+ */
+
+-extern struct platform_device *s3c24xx_uart_devs[3];
++extern struct platform_device *s3c24xx_uart_devs[NR_PORTS];
+
+ #endif /* __ASSEMBLY__ */
+
+diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
+index 8b0d594..fb08b15 100644
+--- a/include/asm-arm/plat-s3c/regs-timer.h
++++ b/include/asm-arm/plat-s3c/regs-timer.h
+@@ -12,7 +12,7 @@
+
+
+ #ifndef __ASM_ARCH_REGS_TIMER_H
+-#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
++#define __ASM_ARCH_REGS_TIMER_H "$Id: regs-timer.h,v 1.2 2008/07/31 06:51:59 eyryu Exp $"
+
+ #define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
+ #define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+@@ -100,6 +100,110 @@
+ #define S3C2410_TCON_T0MANUALUPD (1<<1)
+ #define S3C2410_TCON_T0START (1<<0)
+
++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX)
++#define S3C_TCFG0 S3C_TIMERREG(0x00)
++#define S3C_TCFG1 S3C_TIMERREG(0x04)
++#define S3C_TCON S3C_TIMERREG(0x08)
++#define S3C_TINT_CSTAT S3C_TIMERREG(0x44)
++
++#define S3C_TCFG_PRESCALER0_MASK (255<<0)
++#define S3C_TCFG_PRESCALER1_MASK (255<<8)
++#define S3C_TCFG_PRESCALER1_SHIFT (8)
++#define S3C_TCFG_PRESCALER0_SHIFT (0)
++#define S3C_TCFG_DEADZONE_MASK (255<<16)
++#define S3C_TCFG_DEADZONE_SHIFT (16)
++
++#define S3C_TCFG1_MUX4_DIV1 (0<<16)
++#define S3C_TCFG1_MUX4_DIV2 (1<<16)
++#define S3C_TCFG1_MUX4_DIV4 (2<<16)
++#define S3C_TCFG1_MUX4_DIV8 (3<<16)
++#define S3C_TCFG1_MUX4_DIV16 (4<<16)
++#define S3C_TCFG1_MUX4_TCLK1 (5<<16)
++#define S3C_TCFG1_MUX4_MASK (15<<16)
++
++#define S3C_TCFG1_MUX3_DIV1 (0<<12)
++#define S3C_TCFG1_MUX3_DIV2 (1<<12)
++#define S3C_TCFG1_MUX3_DIV4 (2<<12)
++#define S3C_TCFG1_MUX3_DIV8 (3<<12)
++#define S3C_TCFG1_MUX3_DIV16 (4<<12)
++#define S3C_TCFG1_MUX3_TCLK1 (5<<12)
++#define S3C_TCFG1_MUX3_MASK (15<<12)
++
++#define S3C_TCFG1_MUX2_DIV1 (0<<8)
++#define S3C_TCFG1_MUX2_DIV2 (1<<8)
++#define S3C_TCFG1_MUX2_DIV4 (2<<8)
++#define S3C_TCFG1_MUX2_DIV8 (3<<8)
++#define S3C_TCFG1_MUX2_DIV16 (4<<8)
++#define S3C_TCFG1_MUX2_TCLK1 (5<<8)
++#define S3C_TCFG1_MUX2_MASK (15<<8)
++
++#define S3C_TCFG1_MUX1_DIV1 (0<<4)
++#define S3C_TCFG1_MUX1_DIV2 (1<<4)
++#define S3C_TCFG1_MUX1_DIV4 (2<<4)
++#define S3C_TCFG1_MUX1_DIV8 (3<<4)
++#define S3C_TCFG1_MUX1_DIV16 (4<<4)
++#define S3C_TCFG1_MUX1_TCLK0 (5<<4)
++#define S3C_TCFG1_MUX1_MASK (15<<4)
++
++#define S3C_TCFG1_MUX0_DIV1 (0<<0)
++#define S3C_TCFG1_MUX0_DIV2 (1<<0)
++#define S3C_TCFG1_MUX0_DIV4 (2<<0)
++#define S3C_TCFG1_MUX0_DIV8 (3<<0)
++#define S3C_TCFG1_MUX0_DIV16 (4<<0)
++#define S3C_TCFG1_MUX0_TCLK0 (5<<0)
++#define S3C_TCFG1_MUX0_MASK (15<<0)
++
++/* for each timer, we have an count buffer, an compare buffer and
++ * an observation buffer
++*/
++
++/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
++/* 32bit timer used */
++
++#define S3C_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
++#define S3C_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
++#define S3C_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
++
++#define S3C_TCON_T4RELOAD (1<<22)
++#define S3C_TCON_T4MANUALUPD (1<<21)
++#define S3C_TCON_T4START (1<<20)
++
++#define S3C_TCON_T3RELOAD (1<<19)
++#define S3C_TCON_T3INVERT (1<<18)
++#define S3C_TCON_T3MANUALUPD (1<<17)
++#define S3C_TCON_T3START (1<<16)
++
++#define S3C_TCON_T2RELOAD (1<<15)
++#define S3C_TCON_T2INVERT (1<<14)
++#define S3C_TCON_T2MANUALUPD (1<<13)
++#define S3C_TCON_T2START (1<<12)
++
++#define S3C_TCON_T1RELOAD (1<<11)
++#define S3C_TCON_T1INVERT (1<<10)
++#define S3C_TCON_T1MANUALUPD (1<<9)
++#define S3C_TCON_T1START (1<<8)
++
++#define S3C_TCON_T0DEADZONE (1<<4)
++#define S3C_TCON_T0RELOAD (1<<3)
++#define S3C_TCON_T0INVERT (1<<2)
++#define S3C_TCON_T0MANUALUPD (1<<1)
++#define S3C_TCON_T0START (1<<0)
++
++/* Interrupt Control and Status register*/
++#define S3C_TINT_CSTAT_T4INT (1<<9)
++#define S3C_TINT_CSTAT_T3INT (1<<8)
++#define S3C_TINT_CSTAT_T2INT (1<<7)
++#define S3C_TINT_CSTAT_T1INT (1<<6)
++#define S3C_TINT_CSTAT_T0INT (1<<5)
++#define S3C_TINT_CSTAT_T4INTEN (1<<4)
++#define S3C_TINT_CSTAT_T3INTEN (1<<3)
++#define S3C_TINT_CSTAT_T2INTEN (1<<2)
++#define S3C_TINT_CSTAT_T1INTEN (1<<1)
++#define S3C_TINT_CSTAT_T0INTEN (1<<0)
++
++
++#endif
++
+ #endif /* __ASM_ARCH_REGS_TIMER_H */
+
+
+diff --git a/include/asm-arm/plat-s3c/ts.h b/include/asm-arm/plat-s3c/ts.h
+new file mode 100644
+index 0000000..ec2e6f6
+--- /dev/null
++++ b/include/asm-arm/plat-s3c/ts.h
+@@ -0,0 +1,31 @@
++/* arch/arm/plat-s3c/include/plat/ts.h
++ *
++ * Copyright (c) 2004 Simtec Electronics
++ * Ben Dooks <ben@simtec.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#ifndef __ASM_ARCH_TS_H
++#define __ASM_ARCH_TS_H __FILE__
++
++struct s3c_ts_mach_info {
++ int delay;
++ int presc;
++ int oversampling_shift;
++ int resol_bit;
++};
++
++struct s3c_ts {
++ struct input_dev *dev;
++ long xp;
++ long yp;
++ int count;
++ int shift;
++ char phys[32];
++};
++
++
++#endif /* __ASM_ARCH_TS_H */
+diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
+index b5e6208..02eb2b1 100644
+--- a/include/asm-arm/plat-s3c/uncompress.h
++++ b/include/asm-arm/plat-s3c/uncompress.h
+@@ -37,7 +37,11 @@ static void arch_detect_cpu(void);
+ /* how many bytes we allow into the FIFO at a time in FIFO mode */
+ #define FIFO_MAX (14)
+
++#if defined(CONFIG_PLAT_S3C24XX)
+ #define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
++#else
++#define uart_base S3C24XX_PA_UART + (0x400*CONFIG_S3C_LOWLEVEL_UART_PORT)
++#endif
+
+ static __inline__ void
+ uart_wr(unsigned int reg, unsigned int val)
+diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h
+index 235b753..bd3d626 100644
+--- a/include/asm-arm/plat-s3c24xx/clock.h
++++ b/include/asm-arm/plat-s3c24xx/clock.h
+@@ -46,6 +46,7 @@ extern struct clk clk_mpll;
+ extern struct clk clk_upll;
+ extern struct clk clk_xtal;
+
++
+ /* exports for arch/arm/mach-s3c2410
+ *
+ * Please DO NOT use these outside of arch/arm/mach-s3c2410
+@@ -62,3 +63,4 @@ extern int s3c24xx_setup_clocks(unsigned long xtal,
+ unsigned long fclk,
+ unsigned long hclk,
+ unsigned long pclk);
++
+diff --git a/include/asm-arm/plat-s3c24xx/common-smdk.h b/include/asm-arm/plat-s3c24xx/common-smdk.h
+index 58d9094..efc1927 100644
+--- a/include/asm-arm/plat-s3c24xx/common-smdk.h
++++ b/include/asm-arm/plat-s3c24xx/common-smdk.h
+@@ -12,4 +12,10 @@
+ * published by the Free Software Foundation.
+ */
+
++extern struct platform_device s3c_device_lcd;
++extern struct platform_device s3c_device_nand;
++
++extern struct platform_device s3c_device_onenand;
++extern struct flash_platform_data s3c_onenand_data;
++
+ extern void smdk_machine_init(void);
+diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h
+index 23e420e..4d65f92 100644
+--- a/include/asm-arm/plat-s3c24xx/cpu.h
++++ b/include/asm-arm/plat-s3c24xx/cpu.h
+@@ -28,6 +28,9 @@ struct map_desc;
+
+ /* core initialisation functions */
+
++#if defined (CONFIG_PLAT_S3C64XX) || defined (CONFIG_PLAT_S5PC1XX)
++extern void s3c_init_irq(void);
++#endif
+ extern void s3c24xx_init_irq(void);
+
+ extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
+@@ -40,6 +43,22 @@ extern void s3c24xx_init_uartdevs(char *name,
+ struct s3c24xx_uart_resources *res,
+ struct s3c2410_uartcfg *cfg, int no);
+
++/* the board structure is used at first initialsation time
++ * to get info such as the devices to register for this
++ * board. This is done because platfrom_add_devices() cannot
++ * be called from the map_io entry.
++*/
++
++struct s3c24xx_board {
++ struct platform_device **devices;
++ unsigned int devices_count;
++
++ struct clk **clocks;
++ unsigned int clocks_count;
++};
++
++extern void s3c24xx_set_board(struct s3c24xx_board *board);
++
+ /* timer for 2410/2440 */
+
+ struct sys_timer;
+@@ -52,3 +71,9 @@ extern struct sysdev_class s3c2412_sysclass;
+ extern struct sysdev_class s3c2440_sysclass;
+ extern struct sysdev_class s3c2442_sysclass;
+ extern struct sysdev_class s3c2443_sysclass;
++extern struct sysdev_class s3c2450_sysclass;
++extern struct sysdev_class s3c2416_sysclass;
++
++extern struct sysdev_class s3c6400_sysclass;
++extern struct sysdev_class s3c6410_sysclass;
++extern struct sysdev_class s5pc100_sysclass;
+diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
+index f9d6f03..5dc27eb 100644
+--- a/include/asm-arm/plat-s3c24xx/devs.h
++++ b/include/asm-arm/plat-s3c24xx/devs.h
+@@ -21,32 +21,58 @@ extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
+ extern struct platform_device *s3c24xx_uart_devs[];
+ extern struct platform_device *s3c24xx_uart_src[];
+
++/* 1 channel devices */
+ extern struct platform_device s3c_device_usb;
+-extern struct platform_device s3c_device_lcd;
+ extern struct platform_device s3c_device_wdt;
+ extern struct platform_device s3c_device_i2c;
+ extern struct platform_device s3c_device_iis;
+ extern struct platform_device s3c_device_rtc;
+ extern struct platform_device s3c_device_adc;
++extern struct platform_device s3c_device_ts;
+ extern struct platform_device s3c_device_sdi;
+-extern struct platform_device s3c_device_hsmmc;
+-
+-extern struct platform_device s3c_device_spi0;
+-extern struct platform_device s3c_device_spi1;
++extern struct platform_device s3c_device_usbgadget;
++extern struct platform_device s3c_device_ac97;
++extern struct platform_device s3c_device_tvenc;
++extern struct platform_device s3c_device_tvscaler;
++extern struct platform_device s3c_device_camif;
++extern struct platform_device s3c_device_jpeg;
++extern struct platform_device s3c_device_vpp;
++extern struct platform_device s3c_device_ide;
+
+-extern struct platform_device s3c_device_nand;
++extern struct platform_device s3c_device_g2d;
++extern struct platform_device s3c_device_keypad;
+
++/* Multiple channel devices */
+ extern struct platform_device s3c_device_timer0;
+ extern struct platform_device s3c_device_timer1;
+ extern struct platform_device s3c_device_timer2;
+ extern struct platform_device s3c_device_timer3;
+
+-extern struct platform_device s3c_device_usbgadget;
++extern struct platform_device s3c_device_spi0;
++extern struct platform_device s3c_device_spi1;
+
+-/* s3c2440 specific devices */
++#if defined(CONFIG_CPU_S3C2443)
++extern struct platform_device s3c_device_hsmmc;
+
+-#ifdef CONFIG_CPU_S3C2440
++#elif defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++extern struct platform_device s3c_device_hsmmc0;
++extern struct platform_device s3c_device_hsmmc1;
++#else
++extern struct platform_device s3c_device_hsmmc0;
++extern struct platform_device s3c_device_hsmmc1;
++extern struct platform_device s3c_device_hsmmc2;
++#endif
+
+-extern struct platform_device s3c_device_camif;
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C6400)
++extern struct platform_device s3c_device_g3d;
++extern struct platform_device s3c_device_mfc;
++extern struct platform_device s3c_device_rotator;
++#endif
++
++#if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
++extern struct platform_device s3c_device_smc911x;
++#endif
+
++#ifdef CONFIG_PLAT_S3C64XX
++extern struct platform_device s3c_device_usb_otghcd;
+ #endif
+diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
+index 2c59406..ef7c1dc 100644
+--- a/include/asm-arm/plat-s3c24xx/dma.h
++++ b/include/asm-arm/plat-s3c24xx/dma.h
+@@ -32,6 +32,9 @@ struct s3c24xx_dma_map {
+ struct s3c24xx_dma_addr hw_addr;
+
+ unsigned long channels[S3C2410_DMA_CHANNELS];
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++ unsigned long sdma_sel;
++#endif
+ };
+
+ struct s3c24xx_dma_selection {
+diff --git a/include/asm-arm/plat-s3c24xx/pm.h b/include/asm-arm/plat-s3c24xx/pm.h
+index cc62366..1a43ff5 100644
+--- a/include/asm-arm/plat-s3c24xx/pm.h
++++ b/include/asm-arm/plat-s3c24xx/pm.h
+@@ -58,9 +58,16 @@ struct sleep_save {
+ unsigned long val;
+ };
+
++struct sleep_save_phy {
++ unsigned long reg;
++ unsigned long val;
++};
++
+ #define SAVE_ITEM(x) \
+ { .reg = (x) }
+
++extern void s3c2410_pm_do_save_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count);
++extern void s3c2410_pm_do_restore_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count);
+ extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
+ extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
+
+diff --git a/include/asm-arm/plat-s3c24xx/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h
+index eaf7791..97cb89d 100644
+--- a/include/asm-arm/plat-s3c24xx/regs-iis.h
++++ b/include/asm-arm/plat-s3c24xx/regs-iis.h
+@@ -73,5 +73,99 @@
+ #define S3C2400_IISFCON_RXMASK (0x07)
+ #define S3C2400_IISFCON_RXSHIFT (0)
+
+-#define S3C2410_IISFIFO (0x10)
++#define S3C2410_IISFIFO (0x10)
++#define S3C2410_IISFIFORX (0x14)
++
++/* 2450 IIS Definitions */
++
++#define S3C2450_IIS0CON (0x00)
++#define S3C2450_IIS0MOD (0x04)
++#define S3C2450_IIS0FIC (0x08)
++#define S3C2450_IIS0PSR (0x0C)
++#define S3C2450_IIS0TXD (0x10)
++#define S3C2450_IIS0RXD (0x14)
++
++#define S3C2450_IIS0TXD_PHYS S3C_IIS0REG_PHYS(0x10)
++#define S3C2450_IIS0RXD_PHYS S3C_IIS0REG_PHYS(0x14)
++
++#define S3C2450_IISFIFO (0x10)
++#define S3C2450_IISFIFORX (0x14)
++
++#define S3C2450_IISCON_FTXURINTEN (0x1<<16)
++#define S3C2450_IISCON_LRINDEX (0x1<<11)
++#define S3C2450_IIS0CON_TXDMAPAUSE (0x1<<6)
++#define S3C2450_IIS0CON_RXDMAPAUSE (0x1<<5)
++#define S3C2450_IIS0CON_TXCHPAUSE (0x1<<4)
++#define S3C2450_IIS0CON_RXCHPAUSE (0x1<<3)
++#define S3C2450_IIS0CON_TXDMACTIVE (0x1<<2)
++#define S3C2450_IIS0CON_RXDMACTIVE (0x1<<1)
++#define S3C2450_IIS0CON_I2SACTIVE (0x1<<0)
++
++#define S3C2450_IIS0MOD_DCE_MASK (0x3<<16)
++#define S3C2450_IIS0MOD_DCE_SD2 (0x1<<17)
++#define S3C2450_IIS0MOD_DCE_SD1 (0x1<<16)
++#define S3C2450_IIS0MOD_BLC_MASK (0x3<<13)
++#define S3C2450_IIS0MOD_BLC_16BIT (0x0<<13)
++#define S3C2450_IIS0MOD_BLC_08BIT (0x1<<13)
++#define S3C2450_IIS0MOD_BLC_24BIT (0x2<<13)
++#define S3C2450_IIS0MOD_CLK_MASK (0x7<<10)
++#define S3C2450_IIS0MOD_INTERNAL_CLK (0x0<<12)
++#define S3C2450_IIS0MOD_EXTERNAL_CLK (0x1<<12)
++#define S3C2450_IIS0MOD_IMS_INTERNAL_MASTER (0x0<<10)
++#define S3C2450_IIS0MOD_IMS_EXTERNAL_MASTER (0x1<<10)
++#define S3C2450_IIS0MOD_IMS_SLAVE (0x2<<10)
++#define S3C2450_IIS0MOD_MODE_MASK (0x3<<8)
++#define S3C2450_IIS0MOD_TXMODE (0x0<<8)
++#define S3C2450_IIS0MOD_RXMODE (0x1<<8)
++#define S3C2450_IIS0MOD_TXRXMODE (0x2<<8)
++#define S3C2450_IIS0MOD_FM_MASK (0x3<<5)
++#define S3C2450_IIS0MOD_IIS (0x0<<5)
++#define S3C2450_IIS0MOD_MSB (0x1<<5)
++#define S3C2450_IIS0MOD_LSB (0x2<<5)
++#define S3C2450_IIS0MOD_FS_MASK (0x3<<3)
++#define S3C2450_IIS0MOD_768FS (0x3<<3)
++#define S3C2450_IIS0MOD_384FS (0x2<<3)
++#define S3C2450_IIS0MOD_512FS (0x1<<3)
++#define S3C2450_IIS0MOD_256FS (0x0<<3)
++#define S3C2450_IIS0MOD_BFS_MASK (0x3<<1)
++#define S3C2450_IIS0MOD_48FS (0x1<<1)
++#define S3C2450_IIS0MOD_32FS (0x0<<1)
++
++#define S3C2450_IIS0MOD_24BIT (0x2<<13)
++#define S3C2450_IIS0MOD_8BIT (0x1<<13)
++#define S3C2450_IIS0MOD_16BIT (0x0<<13)
++
++#define S3C2450_IIS_TX_FLUSH (0x1<<15)
++#define S3C2450_IIS_RX_FLUSH (0x1<<7)
++
++#define S3C2450_IISPSR_PSRAEN (1<<15)
++#define S3C2450_IISPSR_PS_MASK (0x3F<<8)
++/* IIS CH1*/
++
++#define S3C2450_IIS1CON S3C_IIS1REG(0x00)
++#define S3C2450_IIS1MOD S3C_IIS1REG(0x04)
++#define S3C2450_IIS1FIC S3C_IIS1REG(0x08)
++#define S3C2450_IIS1PSR S3C_IIS1REG(0x0C)
++#define S3C2450_IIS1TXD S3C_IIS1REG(0x10)
++#define S3C2450_IIS1RXD S3C_IIS1REG(0x14)
++
++#define S3C2450_IIS1TXD_PHYS S3C_IIS1REG_PHYS(0x10)
++#define S3C2450_IIS1RXD_PHYS S3C_IIS1REG_PHYS(0x14)
++
++#define S3C2450_IIS1CON_TXDMACTIVE (0x1<<2)
++#define S3C2450_IIS1CON_RXDMACTIVE (0x1<<1)
++#define S3C2450_IIS1CON_I2SACTIVE (0x1<<0)
++
++#define S3C2450_IIS1MOD_IMS_INTERNAL_MASTER (0x0<<10)
++#define S3C2450_IIS1MOD_TXRXMODE (0x2<<8)
++#define S3C2450_IIS1MOD_IIS (0x0<<5)
++#define S3C2450_IIS1MOD_384FS (0x2<<3)
++#define S3C2450_IIS1MOD_32FS (0x0<<1)
++#define S3C2450_IIS1MOD_16BIT (0x0)
++
++#define I2SPSR_VAL_SHIFT (0x8)
++
++#define S3C2450_IISPSR_INTSHIFT (8)
++/*----------------------*/
++
+ #endif /* __ASM_ARCH_REGS_IIS_H */
+diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
+index 4a499a1..ff3f3dc 100644
+--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
++++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
+@@ -12,8 +12,6 @@
+ #ifndef __ASM_ARCH_REGS_SPI_H
+ #define __ASM_ARCH_REGS_SPI_H
+
+-#define S3C2410_SPI1 (0x20)
+-#define S3C2412_SPI1 (0x100)
+
+ #define S3C2410_SPCON (0x00)
+
+@@ -21,8 +19,7 @@
+ #define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
+ #define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
+ #define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
+-#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
+- 0: slave, 1: master */
++#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select 0: slave, 1: master */
+ #define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
+ #define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
+
+@@ -51,4 +48,220 @@
+ #define S3C2410_SPTDAT (0x10)
+ #define S3C2410_SPRDAT (0x14)
+
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++/*
++ * SPI(High speed) Registers
++ */
++
++#define S3C_SPI_REG_CH0(x) ((x) + S3C_VA_SPI0)
++#define S3C_SPI_REG_CH1(x) ((x) + S3C_VA_SPI1)
++
++#define S3C_CH_CFG (0x00) //SPI configuration
++#define S3C_CLK_CFG (0x04) //Clock configuration
++#define S3C_MODE_CFG (0x08) //SPI FIFO control
++#define S3C_SLAVE_SEL (0x0C) //Slave selection
++#define S3C_SPI_INT_EN (0x10) //SPI interrupt enable
++#define S3C_SPI_STATUS (0x14) //SPI status
++#define S3C_SPI_TX_DATA (0x18) //SPI TX data
++#define S3C_SPI_RX_DATA (0x1C) //SPI RX data
++#define S3C_PACKET_CNT (0x20) //count how many data master gets
++#define S3C_PENDING_CLR (0x24) //Pending clear
++#define S3C_SWAP_CFG (0x28) //SWAP config register
++#define S3C_FB_CLK (0x28) //SWAP FB config register
++
++
++#define SPI_CH_SW_RST (1<<5)
++#define SPI_CH_MASTER (0<<4)
++#define SPI_CH_SLAVE (1<<4)
++#define SPI_CH_RISING (0<<3)
++#define SPI_CH_FALLING (1<<3)
++#define SPI_CH_FORMAT_A (0<<2)
++#define SPI_CH_FORMAT_B (1<<2)
++#define SPI_CH_RXCH_OFF (0<<1)
++#define SPI_CH_RXCH_ON (1<<1)
++#define SPI_CH_TXCH_OFF (0<<0)
++#define SPI_CH_TXCH_ON (1<<0)
++
++#define SPI_CLKSEL_PCLK (0<<9)
++#define SPI_CLKSEL_USBCLK (1<<9)
++#define SPI_CLKSEL_ECLK (2<<9)
++#define SPI_ENCLK_DISABLE (0<<8)
++#define SPI_ENCLK_ENABLE (1<<8)
++
++#define SPI_MODE_CH_TSZ_BYTE (0<<29)
++#define SPI_MODE_CH_TSZ_HALFWORD (1<<29)
++#define SPI_MODE_CH_TSZ_WORD (2<<29)
++#define SPI_MODE_BUS_TSZ_BYTE (0<<17)
++#define SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
++#define SPI_MODE_BUS_TSZ_WORD (2<<17)
++#define SPI_MODE_RXDMA_OFF (0<<2)
++#define SPI_MODE_RXDMA_ON (1<<2)
++#define SPI_MODE_TXDMA_OFF (0<<1)
++#define SPI_MODE_TXDMA_ON (1<<1)
++#define SPI_MODE_SINGLE (0<<0)
++#define SPI_MODE_4BURST (1<<0)
++
++#define SPI_SLAVE_MAN (0<<1)
++#define SPI_SLAVE_AUTO (1<<1)
++#define SPI_SLAVE_SIG_ACT (0<<0)
++#define SPI_SLAVE_SIG_INACT (1<<0)
++
++#define SPI_INT_TRAILING_DIS (0<<6)
++#define SPI_INT_TRAILING_EN (1<<6)
++#define SPI_INT_RX_OVERRUN_DIS (0<<5)
++#define SPI_INT_RX_OVERRUN_EN (1<<5)
++#define SPI_INT_RX_UNDERRUN_DIS (0<<4)
++#define SPI_INT_RX_UNDERRUN_EN (1<<4)
++#define SPI_INT_TX_OVERRUN_DIS (0<<3)
++#define SPI_INT_TX_OVERRUN_EN (1<<3)
++#define SPI_INT_TX_UNDERRUN_DIS (0<<2)
++#define SPI_INT_TX_UNDERRUN_EN (1<<2)
++#define SPI_INT_RX_FIFORDY_DIS (0<<1)
++#define SPI_INT_RX_FIFORDY_EN (1<<1)
++#define SPI_INT_TX_FIFORDY_DIS (0<<0)
++#define SPI_INT_TX_FIFORDY_EN (1<<0)
++
++#define SPI_STUS_TX_DONE (1<<21)
++#define SPI_STUS_TRAILCNT_ZERO (1<<20)
++#define SPI_STUS_RX_OVERRUN_ERR (1<<5)
++#define SPI_STUS_RX_UNDERRUN_ERR (1<<4)
++#define SPI_STUS_TX_OVERRUN_ERR (1<<3)
++#define SPI_STUS_TX_UNDERRUN_ERR (1<<2)
++#define SPI_STUS_RX_FIFORDY (1<<1)
++#define SPI_STUS_TX_FIFORDY (1<<0)
++
++#define SPI_PACKET_CNT_DIS (0<<16)
++#define SPI_PACKET_CNT_EN (1<<16)
++
++#define SPI_PND_TX_UNDERRUN_CLR (1<<4)
++#define SPI_PND_TX_OVERRUN_CLR (1<<3)
++#define SPI_PND_RX_UNDERRUN_CLR (1<<2)
++#define SPI_PND_RX_OVERRUN_CLR (1<<1)
++#define SPI_PND_TRAILING_CLR (1<<0)
++
++#define SPI_SWAP_RX_HALF_WORD (1<<7)
++#define SPI_SWAP_RX_BYTE (1<<6)
++#define SPI_SWAP_RX_BIT (1<<5)
++#define SPI_SWAP_RX_EN (1<<4)
++#define SPI_SWAP_TX_HALF_WORD (1<<3)
++#define SPI_SWAP_TX_BYTE (1<<2)
++#define SPI_SWAP_TX_BIT (1<<1)
++#define SPI_SWAP_TX_EN (1<<0)
++
++#define SPI_FBCLK_0NS (0<<0)
++#define SPI_FBCLK_2NS (1<<4)
++#define SPI_FBCLK_4NS (2<<4)
++#define SPI_FBCLK_6NS (3<<4)
++
++#endif
++
++#if defined (CONFIG_CPU_S3C2450) || defined (CONFIG_CPU_S3C2416)
++/*
++ * SPI(High speed) Registers
++ */
++
++#define S3C_SPI_REG_CH0(x) ((x) + S3C_VA_SPI0)
++#define S3C_SPI_REG_CH1(x) ((x) + S3C_VA_SPI1)
++
++#define S3C_CH_CFG (0x00) //SPI configuration
++#define S3C_CLK_CFG (0x04) //Clock configuration
++#define S3C_MODE_CFG (0x08) //SPI FIFO control
++#define S3C_SLAVE_SEL (0x0C) //Slave selection
++#define S3C_SPI_INT_EN (0x10) //SPI interrupt enable
++#define S3C_SPI_STATUS (0x14) //SPI status
++#define S3C_SPI_TX_DATA (0x18) //SPI TX data
++#define S3C_SPI_RX_DATA (0x1C) //SPI RX data
++#define S3C_PACKET_CNT (0x20) //count how many data master gets
++#define S3C_PENDING_CLR (0x24) //Pending clear
++#define S3C_SWAP_CFG (0x28) //SWAP config register
++#define S3C_FB_CLK (0x28) //SWAP FB config register
++
++
++#define SPI_CH_SW_RST (1<<5)
++#define SPI_CH_MASTER (0<<4)
++#define SPI_CH_SLAVE (1<<4)
++#define SPI_CH_RISING (0<<3)
++#define SPI_CH_FALLING (1<<3)
++#define SPI_CH_FORMAT_A (0<<2)
++#define SPI_CH_FORMAT_B (1<<2)
++#define SPI_CH_RXCH_OFF (0<<1)
++#define SPI_CH_RXCH_ON (1<<1)
++#define SPI_CH_TXCH_OFF (0<<0)
++#define SPI_CH_TXCH_ON (1<<0)
++
++#define SPI_CLKSEL_PCLK (0<<9)
++#define SPI_CLKSEL_USBCLK (1<<9)
++#define SPI_CLKSEL_ECLK (2<<9)
++#define SPI_ENCLK_DISABLE (0<<8)
++#define SPI_ENCLK_ENABLE (1<<8)
++
++#define SPI_MODE_CH_TSZ_BYTE (0<<18)
++#define SPI_MODE_CH_TSZ_HALFWORD (1<<29)
++#define SPI_MODE_CH_TSZ_WORD (2<<18)
++#define SPI_MODE_BUS_TSZ_BYTE (0<<17)
++#define SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
++#define SPI_MODE_BUS_TSZ_WORD (2<<17)
++#define SPI_MODE_RXDMA_OFF (0<<2)
++#define SPI_MODE_RXDMA_ON (1<<2)
++#define SPI_MODE_TXDMA_OFF (0<<1)
++#define SPI_MODE_TXDMA_ON (1<<1)
++#define SPI_MODE_SINGLE (0<<0)
++#define SPI_MODE_4BURST (1<<0)
++
++#define SPI_SLAVE_MAN (0<<1)
++#define SPI_SLAVE_AUTO (1<<1)
++#define SPI_SLAVE_SIG_ACT (0<<0)
++#define SPI_SLAVE_SIG_INACT (1<<0)
++
++#define SPI_INT_TRAILING_DIS (0<<6)
++#define SPI_INT_TRAILING_EN (1<<6)
++#define SPI_INT_RX_OVERRUN_DIS (0<<5)
++#define SPI_INT_RX_OVERRUN_EN (1<<5)
++#define SPI_INT_RX_UNDERRUN_DIS (0<<4)
++#define SPI_INT_RX_UNDERRUN_EN (1<<4)
++#define SPI_INT_TX_OVERRUN_DIS (0<<3)
++#define SPI_INT_TX_OVERRUN_EN (1<<3)
++#define SPI_INT_TX_UNDERRUN_DIS (0<<2)
++#define SPI_INT_TX_UNDERRUN_EN (1<<2)
++#define SPI_INT_RX_FIFORDY_DIS (0<<1)
++#define SPI_INT_RX_FIFORDY_EN (1<<1)
++#define SPI_INT_TX_FIFORDY_DIS (0<<0)
++#define SPI_INT_TX_FIFORDY_EN (1<<0)
++
++#define SPI_STUS_TX_DONE (1<<21)
++#define SPI_STUS_TRAILCNT_ZERO (1<<20)
++#define SPI_STUS_RX_OVERRUN_ERR (1<<5)
++#define SPI_STUS_RX_UNDERRUN_ERR (1<<4)
++#define SPI_STUS_TX_OVERRUN_ERR (1<<3)
++#define SPI_STUS_TX_UNDERRUN_ERR (1<<2)
++#define SPI_STUS_RX_FIFORDY (1<<1)
++#define SPI_STUS_TX_FIFORDY (1<<0)
++
++#define SPI_PACKET_CNT_DIS (0<<16)
++#define SPI_PACKET_CNT_EN (1<<16)
++
++#define SPI_PND_TX_UNDERRUN_CLR (1<<4)
++#define SPI_PND_TX_OVERRUN_CLR (1<<3)
++#define SPI_PND_RX_UNDERRUN_CLR (1<<2)
++#define SPI_PND_RX_OVERRUN_CLR (1<<1)
++#define SPI_PND_TRAILING_CLR (1<<0)
++
++#define SPI_SWAP_RX_HALF_WORD (1<<7)
++#define SPI_SWAP_RX_BYTE (1<<6)
++#define SPI_SWAP_RX_BIT (1<<5)
++#define SPI_SWAP_RX_EN (1<<4)
++#define SPI_SWAP_TX_HALF_WORD (1<<3)
++#define SPI_SWAP_TX_BYTE (1<<2)
++#define SPI_SWAP_TX_BIT (1<<1)
++#define SPI_SWAP_TX_EN (1<<0)
++
++#define SPI_FBCLK_0NS (0<<0)
++#define SPI_FBCLK_2NS (1<<4)
++#define SPI_FBCLK_4NS (2<<4)
++#define SPI_FBCLK_6NS (3<<4)
++
++#endif
++
++
+ #endif /* __ASM_ARCH_REGS_SPI_H */
++
+diff --git a/include/asm-arm/plat-s3c24xx/s3c2416.h b/include/asm-arm/plat-s3c24xx/s3c2416.h
+new file mode 100644
+index 0000000..6c6b258
+--- /dev/null
++++ b/include/asm-arm/plat-s3c24xx/s3c2416.h
+@@ -0,0 +1,30 @@
++/* linux/include/asm-arm/plat-s3c24xx/s3c2416.h
++ *
++ * Copyright (c) 2008 Samsung Electronics
++ * Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * Header file for s3c2416 cpu support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#if defined(CONFIG_CPU_S3C2416)
++
++struct s3c2410_uartcfg;
++
++extern int s3c2416_init(void);
++
++extern void s3c2416_map_io(struct map_desc *mach_desc, int size);
++
++extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
++
++extern void s3c2416_init_clocks(int xtal);
++
++#else
++#define s3c2416_init_clocks NULL
++#define s3c2416_init_uarts NULL
++#define s3c2416_map_io NULL
++#define s3c2416_init NULL
++#endif
+diff --git a/include/asm-arm/plat-s3c24xx/s3c2443.h b/include/asm-arm/plat-s3c24xx/s3c2443.h
+index 11d83b5..68b85f6 100644
+--- a/include/asm-arm/plat-s3c24xx/s3c2443.h
++++ b/include/asm-arm/plat-s3c24xx/s3c2443.h
+@@ -10,7 +10,7 @@
+ * published by the Free Software Foundation.
+ */
+
+-#ifdef CONFIG_CPU_S3C2443
++#if defined(CONFIG_CPU_S3C2443)
+
+ struct s3c2410_uartcfg;
+
+@@ -22,8 +22,6 @@ extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+ extern void s3c2443_init_clocks(int xtal);
+
+-extern int s3c2443_baseclk_add(void);
+-
+ #else
+ #define s3c2443_init_clocks NULL
+ #define s3c2443_init_uarts NULL
+diff --git a/include/asm-arm/plat-s3c24xx/s3c2450.h b/include/asm-arm/plat-s3c24xx/s3c2450.h
+new file mode 100644
+index 0000000..71f747b
+--- /dev/null
++++ b/include/asm-arm/plat-s3c24xx/s3c2450.h
+@@ -0,0 +1,30 @@
++/* linux/include/asm-arm/plat-s3c24xx/s3c2450.h
++ *
++ * Copyright (c) 2008 Samsung Electronics
++ * Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * Header file for s3c2450 cpu support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++#if defined(CONFIG_CPU_S3C2450)
++
++struct s3c2410_uartcfg;
++
++extern int s3c2450_init(void);
++
++extern void s3c2450_map_io(struct map_desc *mach_desc, int size);
++
++extern void s3c2450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
++
++extern void s3c2450_init_clocks(int xtal);
++
++#else
++#define s3c2450_init_clocks NULL
++#define s3c2450_init_uarts NULL
++#define s3c2450_map_io NULL
++#define s3c2450_init NULL
++#endif
+diff --git a/include/asm-arm/plat-s3c64xx/clock.h b/include/asm-arm/plat-s3c64xx/clock.h
+new file mode 100644
+index 0000000..c83b750
+--- /dev/null
++++ b/include/asm-arm/plat-s3c64xx/clock.h
+@@ -0,0 +1,65 @@
++/* linux/include/asm-arm/plat-s3c24xx/clock.h
++ * linux/arch/arm/mach-s3c2410/clock.h
++ *
++ * Copyright (c) 2004-2005 Simtec Electronics
++ * http://www.simtec.co.uk/products/SWLINUX/
++ * Written by Ben Dooks, <ben@simtec.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++struct clk {
++ struct list_head list;
++ struct module *owner;
++ struct clk *parent;
++ const char *name;
++ int id;
++ int usage;
++ unsigned long rate;
++ unsigned long ctrlbit;
++
++ int (*enable)(struct clk *, int enable);
++ int (*set_rate)(struct clk *c, unsigned long rate);
++ unsigned long (*get_rate)(struct clk *c);
++ unsigned long (*round_rate)(struct clk *c, unsigned long rate);
++ int (*set_parent)(struct clk *c, struct clk *parent);
++};
++
++
++/* core clock support */
++
++extern struct clk clk_f;
++extern struct clk clk_h;
++extern struct clk clk_p;
++extern struct clk clk_mpll;
++extern struct clk clk_xtal;
++
++extern struct clk clk_epll;
++
++/* exports for arch/arm/mach-s3c2410
++ *
++ * Please DO NOT use these outside of arch/arm/mach-s3c2410
++*/
++
++extern struct mutex clocks_mutex;
++
++void s3c_clk_enable (uint clocks, uint enable, ulong gate_reg);
++
++extern int s3c64xx_register_clock(struct clk *clk);
++extern int s3c64xx_register_clocks(struct clk **clk, int nr_clks);
++
++extern int s3c64xx_setup_clocks(unsigned long xtal,
++ unsigned long fclk,
++ unsigned long hclk,
++ unsigned long pclk);
++
++
++extern struct clk clk_48m;
++extern struct clk clk_s;
++extern struct clk clk_u;
++extern struct clk clk_27m;
++extern struct clk clk_hx2;
++
++
+diff --git a/include/asm-arm/plat-s3c64xx/regs-iis.h b/include/asm-arm/plat-s3c64xx/regs-iis.h
+new file mode 100644
+index 0000000..785549d
+--- /dev/null
++++ b/include/asm-arm/plat-s3c64xx/regs-iis.h
+@@ -0,0 +1,126 @@
++/* linux/include/asm-arm/arch-s3c64XX/regs-iis.h
++ *
++ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
++ * http://www.simtec.co.uk/products/SWLINUX/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C64XX IIS register definition
++*/
++
++#ifndef __ASM_ARCH_REGS_IIS_H
++#define __ASM_ARCH_REGS_IIS_H
++
++#define S3C64XX_IIS0REG(x) ((x) + S3C6410_PA_IIS_V40)
++
++//#define S3C_IIS0CON S3C64XX_IIS0REG(0x00)
++//#define S3C_IIS0MOD S3C64XX_IIS0REG(0x04)
++//#define S3C_IIS0FIC S3C64XX_IIS0REG(0x08)
++//#define S3C_IIS0PSR S3C64XX_IIS0REG(0x0C)
++//#define S3C_IIS0TXD S3C64XX_IIS0REG(0x10)
++//#define S3C_IIS0RXD S3C64XX_IIS0REG(0x14)
++
++#define S3C64XX_IIS0CON (0x00)
++#define S3C64XX_IIS0MOD (0x04)
++#define S3C64XX_IIS0FIC (0x08)
++#define S3C64XX_IIS0PSR (0x0C)
++#define S3C64XX_IIS0TXD (0x10)
++#define S3C64XX_IIS0RXD (0x14)
++
++#define S3C64XX_IISCON_LRINDEX (1<<8)
++#define S3C64XX_IISCON_TXFIFORDY (1<<7)
++#define S3C64XX_IISCON_RXFIFORDY (1<<6)
++#define S3C64XX_IISCON_TXDMAEN (1<<5)
++#define S3C64XX_IISCON_RXDMAEN (1<<4)
++#define S3C64XX_IISCON_TXIDLE (1<<3)
++#define S3C64XX_IISCON_RXIDLE (1<<2)
++#define S3C64XX_IISCON_PSCEN (1<<1)
++#define S3C64XX_IISCON_IISEN (1<<0)
++
++//#define S3C64XX_IISMOD_MPLL (1<<9)
++#define S3C64XX_IISMOD_MPLL (0x01<<10)
++#define S3C64XX_IISMOD_SLAVE (1<<8)
++#define S3C64XX_IISMOD_NOXFER (0<<6)
++#define S3C64XX_IISMOD_RXMODE (1<<6)
++#define S3C64XX_IISMOD_TXMODE (2<<6)
++#define S3C64XX_IISMOD_TXRXMODE (3<<6)
++#define S3C64XX_IISMOD_LR_LLOW (0<<5)
++#define S3C64XX_IISMOD_LR_RLOW (1<<5)
++#define S3C64XX_IISMOD_IIS (0<<4)
++#define S3C64XX_IISMOD_MSB (1<<4)
++#define S3C64XX_IISMOD_8BIT (0<<3)
++#define S3C64XX_IISMOD_16BIT (1<<3)
++#define S3C64XX_IISMOD_BITMASK (1<<3)
++#define S3C64XX_IISMOD_256FS (0<<2)
++#define S3C64XX_IISMOD_384FS (1<<2)
++#define S3C64XX_IISMOD_16FS (0<<0)
++#define S3C64XX_IISMOD_32FS (1<<0)
++#define S3C64XX_IISMOD_48FS (2<<0)
++#define S3C64XX_IISMOD_FS_MASK (3<<0)
++
++#define S3C64XX_IIS0MOD_DCE_MASK (0x3<<16)
++#define S3C64XX_IIS0MOD_DCE_SD2 (0x1<<17)
++#define S3C64XX_IIS0MOD_DCE_SD1 (0x1<<16)
++#define S3C64XX_IIS0MOD_BLC_MASK (0x3<<13)
++#define S3C64XX_IIS0MOD_BLC_16BIT (0x0<<13)
++#define S3C64XX_IIS0MOD_BLC_08BIT (0x1<<13)
++#define S3C64XX_IIS0MOD_BLC_24BIT (0x2<<13)
++#define S3C64XX_IIS0MOD_CLK_MASK (0x7<<10)
++#define S3C64XX_IIS0MOD_INTERNAL_CLK (0x0<<12)
++#define S3C64XX_IIS0MOD_EXTERNAL_CLK (0x1<<12)
++#define S3C64XX_IIS0MOD_IMS_INTERNAL_MASTER (0x0<<10)
++#define S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER (0x1<<10)
++#define S3C64XX_IIS0MOD_IMS_SLAVE (0x2<<10)
++#define S3C64XX_IIS0MOD_MODE_MASK (0x3<<8)
++#define S3C64XX_IIS0MOD_TXMODE (0x0<<8)
++#define S3C64XX_IIS0MOD_RXMODE (0x1<<8)
++#define S3C64XX_IIS0MOD_TXRXMODE (0x2<<8)
++#define S3C64XX_IIS0MOD_FM_MASK (0x3<<5)
++#define S3C64XX_IIS0MOD_IIS (0x0<<5)
++#define S3C64XX_IIS0MOD_MSB (0x1<<5)
++#define S3C64XX_IIS0MOD_LSB (0x2<<5)
++#define S3C64XX_IIS0MOD_FS_MASK (0x3<<3)
++#define S3C64XX_IIS0MOD_768FS (0x3<<3)
++#define S3C64XX_IIS0MOD_384FS (0x2<<3)
++#define S3C64XX_IIS0MOD_512FS (0x1<<3)
++#define S3C64XX_IIS0MOD_256FS (0x0<<3)
++#define S3C64XX_IIS0MOD_BFS_MASK (0x3<<1)
++#define S3C64XX_IIS0MOD_48FS (0x1<<1)
++#define S3C64XX_IIS0MOD_32FS (0x0<<1)
++
++#define S3C64XX_IISPSR (0x08)
++#define S3C64XX_IISPSR_INTMASK (31<<5)
++#define S3C64XX_IISPSR_INTSHIFT (5)
++#define S3C64XX_IISPSR_EXTMASK (31<<0)
++#define S3C64XX_IISPSR_EXTSHFIT (0)
++
++#define S3C64XX_IISFCON (0x0c)
++
++#define S3C64XX_IISFCON_TXDMA (1<<15)
++#define S3C64XX_IISFCON_RXDMA (1<<14)
++#define S3C64XX_IISFCON_TXENABLE (1<<13)
++#define S3C64XX_IISFCON_RXENABLE (1<<12)
++#define S3C64XX_IISFCON_TXMASK (0x3f << 6)
++#define S3C64XX_IISFCON_TXSHIFT (6)
++#define S3C64XX_IISFCON_RXMASK (0x3f)
++#define S3C64XX_IISFCON_RXSHIFT (0)
++
++#define S3C64XX_IISFIFO (0x10)
++#define S3C64XX_IISFIFORX (0x14)
++
++#define S3C64XX_IIS0CON_I2SACTIVE (0x1<<0)
++#define S3C64XX_IIS0CON_RXDMACTIVE (0x1<<1)
++#define S3C64XX_IIS0CON_I2SACTIVE (0x1<<0)
++#define S3C64XX_IIS0CON_TXDMACTIVE (0x1<<2)
++
++#define S3C64XX_IIS_TX_FLUSH (0x1<<15)
++#define S3C64XX_IIS_RX_FLUSH (0x1<<7)
++
++#define S3C64XX_IISCON_FTXURINTEN (0x1<<16)
++
++#define S3C64XX_IIS0MOD_24BIT (0x2<<13)
++#define S3C64XX_IIS0MOD_8BIT (0x1<<13)
++#define S3C64XX_IIS0MOD_16BIT (0x0<<13)
++#endif /* __ASM_ARCH_REGS_IIS_H */
+diff --git a/include/asm-arm/plat-s3c64xx/s3c6400.h b/include/asm-arm/plat-s3c64xx/s3c6400.h
+new file mode 100644
+index 0000000..09f3a6d
+--- /dev/null
++++ b/include/asm-arm/plat-s3c64xx/s3c6400.h
+@@ -0,0 +1,27 @@
++/* arch/arm/plat-s3c64xx/s3c6400.h
++ *
++ * Copyright (c) 2004-2005 Samsung Electronics
++ *
++ * Header file for s3c6400 cpu support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Modifications:
++*/
++
++#if defined(CONFIG_CPU_S3C6400)
++
++extern int s3c6400_init(void);
++extern void s3c6400_map_io(struct map_desc *mach_desc, int size);
++extern void s3c6400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
++extern void s3c6400_init_clocks(int xtal);
++
++#else
++#define s3c6400_init NULL
++#define s3c6400_map_io NULL
++#define s3c6400_init_uarts NULL
++#define s3c6400_init_clocks NULL
++#endif
++
+diff --git a/include/asm-arm/plat-s3c64xx/s3c6410.h b/include/asm-arm/plat-s3c64xx/s3c6410.h
+new file mode 100644
+index 0000000..5030d2b
+--- /dev/null
++++ b/include/asm-arm/plat-s3c64xx/s3c6410.h
+@@ -0,0 +1,31 @@
++/* arch/arm/plat-s3c64xx/s3c64.h
++ *
++ * Copyright (c) 2004-2005 Samsung Electronics
++ *
++ *
++ * Header file for s3c6410 cpu support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Modifications:
++*/
++
++#if defined(CONFIG_CPU_S3C6410)
++
++extern int s3c6410_init(void);
++
++extern void s3c6410_map_io(struct map_desc *mach_desc, int size);
++
++extern void s3c6410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
++
++extern void s3c6410_init_clocks(int xtal);
++
++#else
++#define s3c6410_init NULL
++#define s3c6410_map_io NULL
++#define s3c6410_init_uarts NULL
++#define s3c6410_init_clocks NULL
++#endif
++
+diff --git a/include/asm-arm/plat-s5p/clock.h b/include/asm-arm/plat-s5p/clock.h
+new file mode 100644
+index 0000000..c8aa85a
+--- /dev/null
++++ b/include/asm-arm/plat-s5p/clock.h
+@@ -0,0 +1,67 @@
++/* linux/include/asm-arm/plat-s3c24xx/clock.h
++ * linux/arch/arm/mach-s3c2410/clock.h
++ *
++ * Copyright (c) 2004-2005 Simtec Electronics
++ * http://www.simtec.co.uk/products/SWLINUX/
++ * Written by Ben Dooks, <ben@simtec.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++*/
++
++struct clk {
++ struct list_head list;
++ struct module *owner;
++ struct clk *parent;
++ const char *name;
++ int id;
++ int usage;
++ unsigned long rate;
++ unsigned long ctrlbit;
++
++ int (*enable)(struct clk *, int enable);
++ int (*set_rate)(struct clk *c, unsigned long rate);
++ unsigned long (*get_rate)(struct clk *c);
++ unsigned long (*round_rate)(struct clk *c, unsigned long rate);
++ int (*set_parent)(struct clk *c, struct clk *parent);
++};
++
++/* exports for arch/arm/mach-s3c2410
++ *
++ * Please DO NOT use these outside of arch/arm/mach-s3c2410
++ */
++void s3c_clk_enable (uint clocks, uint enable, ulong gate_reg);
++
++extern int s5pc1xx_register_clock(struct clk *clk);
++extern int s5pc1xx_register_clocks(struct clk **clk, int nr_clks);
++
++extern int s5pc1xx_setup_clocks(unsigned long xtal,
++ unsigned long armclk,
++ unsigned long hclkd0,
++ unsigned long pclkd0,
++ unsigned long hclkd1,
++ unsigned long pclkd1);
++
++extern struct mutex clocks_mutex;
++
++/* core clock support */
++
++extern struct clk clk_xtal;
++extern struct clk clk_arm;
++extern struct clk clk_hd0;
++extern struct clk clk_pd0;
++extern struct clk clk_hd1;
++extern struct clk clk_pd1;
++
++#if 0
++extern struct clk clk_epll;
++
++extern struct clk clk_48m;
++extern struct clk clk_s;
++extern struct clk clk_u;
++extern struct clk clk_27m;
++extern struct clk clk_hx2;
++#endif
++
++
+diff --git a/include/asm-arm/plat-s5p/regs-gpio.h b/include/asm-arm/plat-s5p/regs-gpio.h
+new file mode 100644
+index 0000000..a1ddf37
+--- /dev/null
++++ b/include/asm-arm/plat-s5p/regs-gpio.h
+@@ -0,0 +1,2115 @@
++/* linux/include/asm-arm/plat-s5p/regs-gpio.h
++ *
++ * Copyright (c) 2008 Samsung Electronics
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S5PC1XX GPIO register definitions
++ */
++
++#ifndef _ASM_PLAT_REGS_GPIO_H_
++#define _ASM_PLAT_REGS_GPIO_H_
++
++/* utility macros */
++#define S5P_GPIO_REG(x) (S3C24XX_VA_GPIO + (x))
++#define S5P_GPIO_NO(bank, offset) ((bank) + (offset))
++#define S5P_GPIO_BASE(pin) ((pin & ~0x1F) >> 5)
++#define S5P_GPIO_OFFSET(pin) (pin & 0x1F)
++
++/* input/output */
++#define S5P_GPIO_INPUT (0x0)
++#define S5P_GPIO_OUTPUT (0x1)
++
++/* pull up/down bit values */
++#define S5P_GPIO_PUD_DISABLE (0x0)
++#define S5P_GPIO_PD_ENABLE (0x1)
++#define S5P_GPIO_PU_ENABLE (0x2)
++
++/* drive strength bit values */
++#define S5P_GPIO_DRV_1X (0x0)
++#define S5P_GPIO_DRV_2X (0x1)
++#define S5P_GPIO_DRV_3X (0x2)
++#define S5P_GPIO_DRV_4X (0x3)
++
++/* power down control */
++#define S5P_GPIO_PDNCON_OUTPUT0 (0x0)
++#define S5P_GPIO_PDNCON_OUTPUT1 (0x1)
++#define S5P_GPIO_PDNCON_INPUT (0x2)
++#define S5P_GPIO_PDNCON_PREV_STATE (0x3)
++
++/* external interrupt trigger bit values */
++#define S5P_GPIO_EINT_LOW (0x0)
++#define S5P_GPIO_EINT_HIGH (0x1)
++#define S5P_GPIO_EINT_FALLING (0x2)
++#define S5P_GPIO_EINT_RISING (0x3)
++#define S5P_GPIO_EINT_BOTH (0x4)
++
++/* bank list */
++#define S5P_GPIO_BANK_A0 (32 * 0)
++#define S5P_GPIO_BANK_A1 (32 * 1)
++#define S5P_GPIO_BANK_B (32 * 2)
++#define S5P_GPIO_BANK_C (32 * 3)
++#define S5P_GPIO_BANK_D (32 * 4)
++#define S5P_GPIO_BANK_E0 (32 * 5)
++#define S5P_GPIO_BANK_E1 (32 * 6)
++#define S5P_GPIO_BANK_F0 (32 * 7)
++#define S5P_GPIO_BANK_F1 (32 * 8)
++#define S5P_GPIO_BANK_F2 (32 * 9)
++#define S5P_GPIO_BANK_F3 (32 * 10)
++#define S5P_GPIO_BANK_G0 (32 * 11)
++#define S5P_GPIO_BANK_G1 (32 * 12)
++#define S5P_GPIO_BANK_G2 (32 * 13)
++#define S5P_GPIO_BANK_G3 (32 * 14)
++#define S5P_GPIO_BANK_H0 (32 * 15)
++#define S5P_GPIO_BANK_H1 (32 * 16)
++#define S5P_GPIO_BANK_H2 (32 * 17)
++#define S5P_GPIO_BANK_H3 (32 * 18)
++#define S5P_GPIO_BANK_I (32 * 19)
++#define S5P_GPIO_BANK_J0 (32 * 20)
++#define S5P_GPIO_BANK_J1 (32 * 21)
++#define S5P_GPIO_BANK_J2 (32 * 22)
++#define S5P_GPIO_BANK_J3 (32 * 23)
++#define S5P_GPIO_BANK_J4 (32 * 24)
++#define S5P_GPIO_BANK_K0 (32 * 25)
++#define S5P_GPIO_BANK_K1 (32 * 26)
++#define S5P_GPIO_BANK_K2 (32 * 27)
++#define S5P_GPIO_BANK_K3 (32 * 28)
++#define S5P_GPIO_BANK_MP0_0 (32 * 29)
++#define S5P_GPIO_BANK_MP0_1 (32 * 30)
++#define S5P_GPIO_BANK_MP0_2 (32 * 31)
++#define S5P_GPIO_BANK_MP0_3 (32 * 32)
++#define S5P_GPIO_BANK_MP0_4 (32 * 33)
++#define S5P_GPIO_BANK_MP1_0 (32 * 34)
++#define S5P_GPIO_BANK_MP1_1 (32 * 35)
++#define S5P_GPIO_BANK_MP1_2 (32 * 36)
++#define S5P_GPIO_BANK_MP1_3 (32 * 37)
++#define S5P_GPIO_BANK_MP1_4 (32 * 38)
++#define S5P_GPIO_BANK_MP1_5 (32 * 39)
++#define S5P_GPIO_BANK_MP1_6 (32 * 40)
++#define S5P_GPIO_BANK_MP1_7 (32 * 41)
++#define S5P_GPIO_BANK_MP1_8 (32 * 42)
++#define S5P_GPIO_BANK_ETC0 (32 * 43)
++#define S5P_GPIO_BANK_ETC1 (32 * 44)
++#define S5P_GPIO_BANK_ETC2 (32 * 45)
++#define S5P_GPIO_BANK_ETC3 (32 * 46)
++#define S5P_GPIO_BANK_ETC4 (32 * 47)
++
++/* GPA0 */
++#define S5P_GPA0_CON S5P_GPIO_REG(0x00)
++#define S5P_GPA0_DAT S5P_GPIO_REG(0x04)
++#define S5P_GPA0_PUD S5P_GPIO_REG(0x08)
++#define S5P_GPA0_DRV S5P_GPIO_REG(0x0C)
++#define S5P_GPA0_CONPDN S5P_GPIO_REG(0x10)
++#define S5P_GPA0_PUDPDN S5P_GPIO_REG(0x14)
++
++#define S5P_GPA0_0 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 0)
++#define S5P_GPA0_0_IN (0x0)
++#define S5P_GPA0_0_OUT (0x1)
++#define S5P_GPA0_0_UART0_RXD (0x2)
++#define S5P_GPA0_0_EXT_INT1_0 (0xF)
++
++#define S5P_GPA0_1 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 1)
++#define S5P_GPA0_1_IN (0x0)
++#define S5P_GPA0_1_OUT (0x1)
++#define S5P_GPA0_1_UART0_TXD (0x2)
++#define S5P_GPA0_1_EXT_INT1_1 (0xF)
++
++#define S5P_GPA0_2 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 2)
++#define S5P_GPA0_2_IN (0x0)
++#define S5P_GPA0_2_OUT (0x1)
++#define S5P_GPA0_2_UART0_CTSn (0x2)
++#define S5P_GPA0_2_EXT_INT1_2 (0xF)
++
++#define S5P_GPA0_3 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 3)
++#define S5P_GPA0_3_IN (0x0)
++#define S5P_GPA0_3_OUT (0x1)
++#define S5P_GPA0_3_UART0_RTSn (0x2)
++#define S5P_GPA0_3_EXT_INT1_3 (0xF)
++
++#define S5P_GPA0_4 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 4)
++#define S5P_GPA0_4_IN (0x0)
++#define S5P_GPA0_4_OUT (0x1)
++#define S5P_GPA0_4_UART1_RXD (0x2)
++#define S5P_GPA0_4_EXT_INT1_4 (0xF)
++
++#define S5P_GPA0_5 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 5)
++#define S5P_GPA0_5_IN (0x0)
++#define S5P_GPA0_5_OUT (0x1)
++#define S5P_GPA0_5_UART1_TXD (0x2)
++#define S5P_GPA0_5_EXT_INT1_5 (0xF)
++
++#define S5P_GPA0_6 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 6)
++#define S5P_GPA0_6_IN (0x0)
++#define S5P_GPA0_6_OUT (0x1)
++#define S5P_GPA0_6_UART1_CTSn (0x2)
++#define S5P_GPA0_6_EXT_INT1_6 (0xF)
++
++#define S5P_GPA0_7 S5P_GPIO_NO(S5P_GPIO_BANK_A0, 7)
++#define S5P_GPA0_7_IN (0x0)
++#define S5P_GPA0_7_OUT (0x1)
++#define S5P_GPA0_7_UART1_RTSn (0x2)
++#define S5P_GPA0_7_EXT_INT1_7 (0xF)
++
++/* GPA1 */
++#define S5P_GPA1_CON S5P_GPIO_REG(0x20)
++#define S5P_GPA1_DAT S5P_GPIO_REG(0x24)
++#define S5P_GPA1_PUD S5P_GPIO_REG(0x28)
++#define S5P_GPA1_DRV S5P_GPIO_REG(0x2C)
++#define S5P_GPA1_CONPDN S5P_GPIO_REG(0x30)
++#define S5P_GPA1_PUDPDN S5P_GPIO_REG(0x34)
++
++#define S5P_GPA1_0 S5P_GPIO_NO(S5P_GPIO_BANK_A1, 0)
++#define S5P_GPA1_0_IN (0x0)
++#define S5P_GPA1_0_OUT (0x1)
++#define S5P_GPA1_0_UART2_RXD (0x2)
++#define S5P_GPA1_0_EXT_INT2_0 (0xF)
++
++#define S5P_GPA1_1 S5P_GPIO_NO(S5P_GPIO_BANK_A1, 1)
++#define S5P_GPA1_1_IN (0x0)
++#define S5P_GPA1_1_OUT (0x1)
++#define S5P_GPA1_1_UART2_TXD (0x2)
++#define S5P_GPA1_1_EXT_INT2_1 (0xF)
++
++#define S5P_GPA1_2 S5P_GPIO_NO(S5P_GPIO_BANK_A1, 2)
++#define S5P_GPA1_2_IN (0x0)
++#define S5P_GPA1_2_OUT (0x1)
++#define S5P_GPA1_2_UART3_RXD (0x2)
++#define S5P_GPA1_2_UART2_CTSn (0x3)
++#define S5P_GPA1_2_IRDA_RX_DATA (0x4)
++#define S5P_GPA1_2_EXT_INT2_2 (0xF)
++
++#define S5P_GPA1_3 S5P_GPIO_NO(S5P_GPIO_BANK_A1, 3)
++#define S5P_GPA1_3_IN (0x0)
++#define S5P_GPA1_3_OUT (0x1)
++#define S5P_GPA1_3_UART3_TXD (0x2)
++#define S5P_GPA1_3_UART2_RTSn (0x3)
++#define S5P_GPA1_3_IRDA_TX_DATA (0x4)
++#define S5P_GPA1_3_EXT_INT2_3 (0xF)
++
++#define S5P_GPA1_4 S5P_GPIO_NO(S5P_GPIO_BANK_A1, 4)
++#define S5P_GPA1_4_IN (0x0)
++#define S5P_GPA1_4_OUT (0x1)
++#define S5P_GPA1_4_UARTCLK (0x2)
++#define S5P_GPA1_4_IRDA_SDBW (0x4)
++#define S5P_GPA1_4_EXT_INT2_4 (0xF)
++
++/* GPB */
++#define S5P_GPB0_CON S5P_GPIO_REG(0x40)
++#define S5P_GPB0_DAT S5P_GPIO_REG(0x44)
++#define S5P_GPB0_PUD S5P_GPIO_REG(0x48)
++#define S5P_GPB0_DRV S5P_GPIO_REG(0x4C)
++#define S5P_GPB0_CONPDN S5P_GPIO_REG(0x50)
++#define S5P_GPB0_PUDPDN S5P_GPIO_REG(0x54)
++
++#define S5P_GPB0 S5P_GPIO_NO(S5P_GPIO_BANK_B, 0)
++#define S5P_GPB0_IN (0x0)
++#define S5P_GPB0_OUT (0x1)
++#define S5P_GPB0_SPI0_MISO (0x2)
++#define S5P_GPB0_EXT_INT3_0 (0xF)
++
++#define S5P_GPB1 S5P_GPIO_NO(S5P_GPIO_BANK_B, 1)
++#define S5P_GPB1_IN (0x0)
++#define S5P_GPB1_OUT (0x1)
++#define S5P_GPB1_SPI0_CLK (0x2)
++#define S5P_GPB1_EXT_INT3_1 (0xF)
++
++#define S5P_GPB2 S5P_GPIO_NO(S5P_GPIO_BANK_B, 2)
++#define S5P_GPB2_IN (0x0)
++#define S5P_GPB2_OUT (0x1)
++#define S5P_GPB2_SPI0_MOSI (0x2)
++#define S5P_GPB2_EXT_INT3_2 (0xF)
++
++#define S5P_GPB3 S5P_GPIO_NO(S5P_GPIO_BANK_B, 3)
++#define S5P_GPB3_IN (0x0)
++#define S5P_GPB3_OUT (0x1)
++#define S5P_GPB3_SPI0_nSS (0x2)
++#define S5P_GPB3_EXT_INT3_3 (0xF)
++
++#define S5P_GPB4 S5P_GPIO_NO(S5P_GPIO_BANK_B, 4)
++#define S5P_GPB4_IN (0x0)
++#define S5P_GPB4_OUT (0x1)
++#define S5P_GPB4_SPI1_MISO (0x2)
++#define S5P_GPB4_EXT_INT3_4 (0xF)
++
++#define S5P_GPB5 S5P_GPIO_NO(S5P_GPIO_BANK_B, 5)
++#define S5P_GPB5_IN (0x0)
++#define S5P_GPB5_OUT (0x1)
++#define S5P_GPB5_SPI1_CLK (0x2)
++#define S5P_GPB5_EXT_INT3_5 (0xF)
++
++#define S5P_GPB6 S5P_GPIO_NO(S5P_GPIO_BANK_B, 6)
++#define S5P_GPB6_IN (0x0)
++#define S5P_GPB6_OUT (0x1)
++#define S5P_GPB6_SPI1_MOSI (0x2)
++#define S5P_GPB6_EXT_INT3_6 (0xF)
++
++#define S5P_GPB7 S5P_GPIO_NO(S5P_GPIO_BANK_B, 7)
++#define S5P_GPB7_IN (0x0)
++#define S5P_GPB7_OUT (0x1)
++#define S5P_GPB7_SPI1_nSS (0x2)
++#define S5P_GPB7_EXT_INT3_7 (0xF)
++
++/* GPC */
++#define S5P_GPC0_CON S5P_GPIO_REG(0x60)
++#define S5P_GPC0_DAT S5P_GPIO_REG(0x64)
++#define S5P_GPC0_PUD S5P_GPIO_REG(0x68)
++#define S5P_GPC0_DRV S5P_GPIO_REG(0x6C)
++#define S5P_GPC0_CONPDN S5P_GPIO_REG(0x70)
++#define S5P_GPC0_PUDPDN S5P_GPIO_REG(0x74)
++
++#define S5P_GPC0 S5P_GPIO_NO(S5P_GPIO_BANK_C, 0)
++#define S5P_GPC0_IN (0x0)
++#define S5P_GPC0_OUT (0x1)
++#define S5P_GPC0_I2S1_SCLK (0x2)
++#define S5P_GPC0_PCM1_SCLK (0x3)
++#define S5P_GPC0_AC97_BITCLK (0x4)
++#define S5P_GPC0_EXT_INT4_0 (0xF)
++
++#define S5P_GPC1 S5P_GPIO_NO(S5P_GPIO_BANK_C, 1)
++#define S5P_GPC1_IN (0x0)
++#define S5P_GPC1_OUT (0x1)
++#define S5P_GPC1_I2S1_CDCLK (0x2)
++#define S5P_GPC1_PCM1_EXTCLK (0x3)
++#define S5P_GPC1_AC97_RESETn (0x4)
++#define S5P_GPC1_EXT_INT4_1 (0xF)
++
++#define S5P_GPC2 S5P_GPIO_NO(S5P_GPIO_BANK_C, 2)
++#define S5P_GPC2_IN (0x0)
++#define S5P_GPC2_OUT (0x1)
++#define S5P_GPC2_I2S1_LRCK (0x2)
++#define S5P_GPC2_PCM1_FSYNC (0x3)
++#define S5P_GPC2_AC97_SYNC (0x4)
++#define S5P_GPC2_EXT_INT4_2 (0xF)
++
++#define S5P_GPC3 S5P_GPIO_NO(S5P_GPIO_BANK_C, 3)
++#define S5P_GPC3_IN (0x0)
++#define S5P_GPC3_OUT (0x1)
++#define S5P_GPC3_I2S1_SDI (0x2)
++#define S5P_GPC3_PCM1_SIN (0x3)
++#define S5P_GPC3_AC97_SDI (0x4)
++#define S5P_GPC3_EXT_INT4_3 (0xF)
++
++#define S5P_GPC4 S5P_GPIO_NO(S5P_GPIO_BANK_C, 4)
++#define S5P_GPC4_IN (0x0)
++#define S5P_GPC4_OUT (0x1)
++#define S5P_GPC4_I2S1_SDO (0x2)
++#define S5P_GPC4_PCM1_SOUT (0x3)
++#define S5P_GPC4_AC97_SDO (0x4)
++#define S5P_GPC4_EXT_INT4_4 (0xF)
++
++/* GPD */
++#define S5P_GPD0_CON S5P_GPIO_REG(0x80)
++#define S5P_GPD0_DAT S5P_GPIO_REG(0x84)
++#define S5P_GPD0_PUD S5P_GPIO_REG(0x88)
++#define S5P_GPD0_DRV S5P_GPIO_REG(0x8C)
++#define S5P_GPD0_CONPDN S5P_GPIO_REG(0x90)
++#define S5P_GPD0_PUDPDN S5P_GPIO_REG(0x94)
++
++#define S5P_GPD0 S5P_GPIO_NO(S5P_GPIO_BANK_D, 0)
++#define S5P_GPD0_IN (0x0)
++#define S5P_GPD0_OUT (0x1)
++#define S5P_GPD0_TOUT0 (0x2)
++#define S5P_GPD0_PWM_TCLK (0x3)
++#define S5P_GPD0_EXT_INT5_0 (0xF)
++
++#define S5P_GPD1 S5P_GPIO_NO(S5P_GPIO_BANK_D, 1)
++#define S5P_GPD1_IN (0x0)
++#define S5P_GPD1_OUT (0x1)
++#define S5P_GPD1_TOUT1 (0x2)
++#define S5P_GPD1_EX_DMA_REQn (0x3)
++#define S5P_GPD1_EXT_INT5_1 (0xF)
++
++#define S5P_GPD2 S5P_GPIO_NO(S5P_GPIO_BANK_D, 2)
++#define S5P_GPD2_IN (0x0)
++#define S5P_GPD2_OUT (0x1)
++#define S5P_GPD2_TOUT2 (0x2)
++#define S5P_GPD2_EX_DMA_ACKn (0x3)
++#define S5P_GPD2_EXT_INT5_2 (0xF)
++
++#define S5P_GPD3 S5P_GPIO_NO(S5P_GPIO_BANK_D, 3)
++#define S5P_GPD3_IN (0x0)
++#define S5P_GPD3_OUT (0x1)
++#define S5P_GPD3_I2C0_SDA (0x2)
++#define S5P_GPD3_EXT_INT5_3 (0xF)
++
++#define S5P_GPD4 S5P_GPIO_NO(S5P_GPIO_BANK_D, 4)
++#define S5P_GPD4_IN (0x0)
++#define S5P_GPD4_OUT (0x1)
++#define S5P_GPD4_I2C0_SCL (0x2)
++#define S5P_GPD4_EXT_INT5_4 (0xF)
++
++#define S5P_GPD5 S5P_GPIO_NO(S5P_GPIO_BANK_D, 5)
++#define S5P_GPD5_IN (0x0)
++#define S5P_GPD5_OUT (0x1)
++#define S5P_GPD5_I2C1_SDA (0x2)
++#define S5P_GPD5_SPDIF0_OUT (0x3)
++#define S5P_GPD5_EXT_INT5_5 (0xF)
++
++#define S5P_GPD6 S5P_GPIO_NO(S5P_GPIO_BANK_D, 6)
++#define S5P_GPD6_IN (0x0)
++#define S5P_GPD6_OUT (0x1)
++#define S5P_GPD6_I2C1_SCL (0x2)
++#define S5P_GPD5_SPDIF_EXTCLK (0x3)
++#define S5P_GPD6_EXT_INT5_6 (0xF)
++
++/* GPE0 */
++#define S5P_GPE0_CON S5P_GPIO_REG(0xA0)
++#define S5P_GPE0_DAT S5P_GPIO_REG(0xA4)
++#define S5P_GPE0_PUD S5P_GPIO_REG(0xA8)
++#define S5P_GPE0_DRV S5P_GPIO_REG(0xAC)
++#define S5P_GPE0_CONPDN S5P_GPIO_REG(0xB0)
++#define S5P_GPE0_PUDPDN S5P_GPIO_REG(0xB4)
++
++#define S5P_GPE0_0 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 0)
++#define S5P_GPE0_0_IN (0x0)
++#define S5P_GPE0_0_OUT (0x1)
++#define S5P_GPE0_0_CAM_A_PCLK (0x2)
++#define S5P_GPE0_0_SD1_CLK (0x3)
++#define S5P_GPE0_0_EXT_INT6_0 (0xF)
++
++#define S5P_GPE0_1 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 1)
++#define S5P_GPE0_1_IN (0x0)
++#define S5P_GPE0_1_OUT (0x1)
++#define S5P_GPE0_1_CAM_A_VSYNC (0x2)
++#define S5P_GPE0_1_SD1_CDn (0x3)
++#define S5P_GPE0_1_EXT_INT6_1 (0xF)
++
++#define S5P_GPE0_2 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 2)
++#define S5P_GPE0_2_IN (0x0)
++#define S5P_GPE0_2_OUT (0x1)
++#define S5P_GPE0_2_CAM_A_HREF (0x2)
++#define S5P_GPE0_2_SD1_CMD (0x3)
++#define S5P_GPE0_2_EXT_INT6_2 (0xF)
++
++#define S5P_GPE0_3 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 3)
++#define S5P_GPE0_3_IN (0x0)
++#define S5P_GPE0_3_OUT (0x1)
++#define S5P_GPE0_3_CAM_A_DATA0 (0x2)
++#define S5P_GPE0_3_SD1_DATA0 (0x3)
++#define S5P_GPE0_3_EXT_INT6_3 (0xF)
++
++#define S5P_GPE0_4 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 4)
++#define S5P_GPE0_4_IN (0x0)
++#define S5P_GPE0_4_OUT (0x1)
++#define S5P_GPE0_4_CAM_A_DATA1 (0x2)
++#define S5P_GPE0_4_SD1_DATA1 (0x3)
++#define S5P_GPE0_4_EXT_INT6_4 (0xF)
++
++#define S5P_GPE0_5 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 5)
++#define S5P_GPE0_5_IN (0x0)
++#define S5P_GPE0_5_OUT (0x1)
++#define S5P_GPE0_5_CAM_A_DATA2 (0x2)
++#define S5P_GPE0_5_SD1_DATA2 (0x3)
++#define S5P_GPE0_5_EXT_INT6_5 (0xF)
++
++#define S5P_GPE0_6 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 6)
++#define S5P_GPE0_6_IN (0x0)
++#define S5P_GPE0_6_OUT (0x1)
++#define S5P_GPE0_6_CAM_A_DATA3 (0x2)
++#define S5P_GPE0_6_SD1_DATA3 (0x3)
++#define S5P_GPE0_6_EXT_INT6_6 (0xF)
++
++#define S5P_GPE0_7 S5P_GPIO_NO(S5P_GPIO_BANK_E0, 7)
++#define S5P_GPE0_7_IN (0x0)
++#define S5P_GPE0_7_OUT (0x1)
++#define S5P_GPE0_7_CAM_A_DATA4 (0x2)
++#define S5P_GPE0_7_SD1_DATA4 (0x3)
++#define S5P_GPE0_7_EXT_INT6_7 (0xF)
++
++/* GPE1 */
++#define S5P_GPE1_CON S5P_GPIO_REG(0xC0)
++#define S5P_GPE1_DAT S5P_GPIO_REG(0xC4)
++#define S5P_GPE1_PUD S5P_GPIO_REG(0xC8)
++#define S5P_GPE1_DRV S5P_GPIO_REG(0xDC)
++#define S5P_GPE1_CONPDN S5P_GPIO_REG(0xD0)
++#define S5P_GPE1_PUDPDN S5P_GPIO_REG(0xD4)
++
++#define S5P_GPE1_0 S5P_GPIO_NO(S5P_GPIO_BANK_E1, 0)
++#define S5P_GPE1_0_IN (0x0)
++#define S5P_GPE1_0_OUT (0x1)
++#define S5P_GPE1_0_CAM_A_DATA5 (0x2)
++#define S5P_GPE1_0_SD1_DATA5 (0x3)
++#define S5P_GPE1_0_EXT_INT7_0 (0xF)
++
++#define S5P_GPE1_1 S5P_GPIO_NO(S5P_GPIO_BANK_E1, 1)
++#define S5P_GPE1_1_IN (0x0)
++#define S5P_GPE1_1_OUT (0x1)
++#define S5P_GPE1_1_CAM_A_DATA6 (0x2)
++#define S5P_GPE1_1_SD1_DATA6 (0x3)
++#define S5P_GPE1_1_EXT_INT7_1 (0xF)
++
++#define S5P_GPE1_2 S5P_GPIO_NO(S5P_GPIO_BANK_E1, 2)
++#define S5P_GPE1_2_IN (0x0)
++#define S5P_GPE1_2_OUT (0x1)
++#define S5P_GPE1_2_CAM_A_DATA7 (0x2)
++#define S5P_GPE1_2_SD1_DATA7 (0x3)
++#define S5P_GPE1_2_EXT_INT7_2 (0xF)
++
++#define S5P_GPE1_3 S5P_GPIO_NO(S5P_GPIO_BANK_E1, 3)
++#define S5P_GPE1_3_IN (0x0)
++#define S5P_GPE1_3_OUT (0x1)
++#define S5P_GPE1_3_CAM_A_CLKOUT (0x2)
++#define S5P_GPE1_3_EXT_INT7_3 (0xF)
++
++#define S5P_GPE1_4 S5P_GPIO_NO(S5P_GPIO_BANK_E1, 4)
++#define S5P_GPE1_4_IN (0x0)
++#define S5P_GPE1_4_OUT (0x1)
++#define S5P_GPE1_4_CAM_A_RESET (0x2)
++#define S5P_GPE1_4_EXT_INT7_4 (0xF)
++
++#define S5P_GPE1_5 S5P_GPIO_NO(S5P_GPIO_BANK_E1, 5)
++#define S5P_GPE1_5_IN (0x0)
++#define S5P_GPE1_5_OUT (0x1)
++#define S5P_GPE1_5_CAM_A_FLASH (0x2)
++#define S5P_GPE1_5_EXT_INT7_4 (0xF)
++
++/* GPF0 */
++#define S5P_GPF0_CON S5P_GPIO_REG(0xE0)
++#define S5P_GPF0_DAT S5P_GPIO_REG(0xE4)
++#define S5P_GPF0_PUD S5P_GPIO_REG(0xE8)
++#define S5P_GPF0_DRV S5P_GPIO_REG(0xEC)
++#define S5P_GPF0_CONPDN S5P_GPIO_REG(0xF0)
++#define S5P_GPF0_PUDPDN S5P_GPIO_REG(0xF4)
++
++#define S5P_GPF0_0 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 0)
++#define S5P_GPF0_0_IN (0x0)
++#define S5P_GPF0_0_OUT (0x1)
++#define S5P_GPF0_0_LCD_HSYNC (0x2)
++#define S5P_GPF0_0_SYS_CS0 (0x3)
++#define S5P_GPF0_0_VEN_HSYNC (0x4)
++#define S5P_GPF0_0_EXT_INT8_0 (0xF)
++
++#define S5P_GPF0_1 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 1)
++#define S5P_GPF0_1_IN (0x0)
++#define S5P_GPF0_1_OUT (0x1)
++#define S5P_GPF0_1_LCD_VSYNC (0x2)
++#define S5P_GPF0_1_SYS_CS1 (0x3)
++#define S5P_GPF0_1_VEN_VSYNC (0x4)
++#define S5P_GPF0_1_EXT_INT8_1 (0xF)
++
++#define S5P_GPF0_2 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 2)
++#define S5P_GPF0_2_IN (0x0)
++#define S5P_GPF0_2_OUT (0x1)
++#define S5P_GPF0_2_LCD_VDEN (0x2)
++#define S5P_GPF0_2_SYS_RS (0x3)
++#define S5P_GPF0_2_VEN_HREF (0x4)
++#define S5P_GPF0_2_EXT_INT8_2 (0xF)
++
++#define S5P_GPF0_3 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 3)
++#define S5P_GPF0_3_IN (0x0)
++#define S5P_GPF0_3_OUT (0x1)
++#define S5P_GPF0_3_LCD_VCLK (0x2)
++#define S5P_GPF0_3_SYS_WE (0x3)
++#define S5P_GPF0_3_V601_CLK (0x4)
++#define S5P_GPF0_3_EXT_INT8_3 (0xF)
++
++#define S5P_GPF0_4 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 4)
++#define S5P_GPF0_4_IN (0x0)
++#define S5P_GPF0_4_OUT (0x1)
++#define S5P_GPF0_4_LCD_VD0 (0x2)
++#define S5P_GPF0_4_SYS_VD0 (0x3)
++#define S5P_GPF0_4_VEN_DATA0 (0x4)
++#define S5P_GPF0_4_EXT_INT8_4 (0xF)
++
++#define S5P_GPF0_5 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 5)
++#define S5P_GPF0_5_IN (0x0)
++#define S5P_GPF0_5_OUT (0x1)
++#define S5P_GPF0_5_LCD_VD1 (0x2)
++#define S5P_GPF0_5_SYS_VD1 (0x3)
++#define S5P_GPF0_5_VEN_DATA1 (0x4)
++#define S5P_GPF0_5_EXT_INT8_5 (0xF)
++
++#define S5P_GPF0_6 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 6)
++#define S5P_GPF0_6_IN (0x0)
++#define S5P_GPF0_6_OUT (0x1)
++#define S5P_GPF0_6_LCD_VD2 (0x2)
++#define S5P_GPF0_6_SYS_VD2 (0x3)
++#define S5P_GPF0_6_VEN_DATA2 (0x4)
++#define S5P_GPF0_6_EXT_INT8_6 (0xF)
++
++#define S5P_GPF0_7 S5P_GPIO_NO(S5P_GPIO_BANK_F0, 7)
++#define S5P_GPF0_7_IN (0x0)
++#define S5P_GPF0_7_OUT (0x1)
++#define S5P_GPF0_7_LCD_VD3 (0x2)
++#define S5P_GPF0_7_SYS_VD3 (0x3)
++#define S5P_GPF0_7_VEN_DATA3 (0x4)
++#define S5P_GPF0_7_EXT_INT8_7 (0xF)
++
++/* GPF1 */
++#define S5P_GPF1_CON S5P_GPIO_REG(0x100)
++#define S5P_GPF1_DAT S5P_GPIO_REG(0x104)
++#define S5P_GPF1_PUD S5P_GPIO_REG(0x108)
++#define S5P_GPF1_DRV S5P_GPIO_REG(0x10C)
++#define S5P_GPF1_CONPDN S5P_GPIO_REG(0x110)
++#define S5P_GPF1_PUDPDN S5P_GPIO_REG(0x114)
++
++#define S5P_GPF1_0 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 0)
++#define S5P_GPF1_0_IN (0x0)
++#define S5P_GPF1_0_OUT (0x1)
++#define S5P_GPF1_0_LCD_VD4 (0x2)
++#define S5P_GPF1_0_SYS_VD4 (0x3)
++#define S5P_GPF1_0_VEN_DATA4 (0x4)
++#define S5P_GPF1_0_EXT_INT9_0 (0xF)
++
++#define S5P_GPF1_1 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 1)
++#define S5P_GPF1_1_IN (0x0)
++#define S5P_GPF1_1_OUT (0x1)
++#define S5P_GPF1_1_LCD_VD5 (0x2)
++#define S5P_GPF1_1_SYS_VD5 (0x3)
++#define S5P_GPF1_1_VEN_DATA5 (0x4)
++#define S5P_GPF1_1_EXT_INT9_1 (0xF)
++
++#define S5P_GPF1_2 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 2)
++#define S5P_GPF1_2_IN (0x0)
++#define S5P_GPF1_2_OUT (0x1)
++#define S5P_GPF1_2_LCD_VD6 (0x2)
++#define S5P_GPF1_2_SYS_VD6 (0x3)
++#define S5P_GPF1_2_VEN_DATA6 (0x4)
++#define S5P_GPF1_2_EXT_INT9_2 (0xF)
++
++#define S5P_GPF1_3 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 3)
++#define S5P_GPF1_3_IN (0x0)
++#define S5P_GPF1_3_OUT (0x1)
++#define S5P_GPF1_3_LCD_VD7 (0x2)
++#define S5P_GPF1_3_SYS_VD7 (0x3)
++#define S5P_GPF1_3_VEN_DATA7 (0x4)
++#define S5P_GPF1_3_EXT_INT9_3 (0xF)
++
++#define S5P_GPF1_4 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 4)
++#define S5P_GPF1_4_IN (0x0)
++#define S5P_GPF1_4_OUT (0x1)
++#define S5P_GPF1_4_LCD_VD8 (0x2)
++#define S5P_GPF1_4_SYS_VD8 (0x3)
++#define S5P_GPF1_4_V656_DATA0 (0x4)
++#define S5P_GPF1_4_EXT_INT9_4 (0xF)
++
++#define S5P_GPF1_5 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 5)
++#define S5P_GPF1_5_IN (0x0)
++#define S5P_GPF1_5_OUT (0x1)
++#define S5P_GPF1_5_LCD_VD9 (0x2)
++#define S5P_GPF1_5_SYS_VD9 (0x3)
++#define S5P_GPF1_5_V656_DATA1 (0x4)
++#define S5P_GPF1_5_EXT_INT9_5 (0xF)
++
++#define S5P_GPF1_6 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 6)
++#define S5P_GPF1_6_IN (0x0)
++#define S5P_GPF1_6_OUT (0x1)
++#define S5P_GPF1_6_LCD_VD10 (0x2)
++#define S5P_GPF1_6_SYS_VD10 (0x3)
++#define S5P_GPF1_6_V656_DATA2 (0x4)
++#define S5P_GPF1_6_EXT_INT9_6 (0xF)
++
++#define S5P_GPF1_7 S5P_GPIO_NO(S5P_GPIO_BANK_F1, 7)
++#define S5P_GPF1_7_IN (0x0)
++#define S5P_GPF1_7_OUT (0x1)
++#define S5P_GPF1_7_LCD_VD11 (0x2)
++#define S5P_GPF1_7_SYS_VD11 (0x3)
++#define S5P_GPF1_7_V656_DATA3 (0x4)
++#define S5P_GPF1_7_EXT_INT9_7 (0xF)
++
++/* GPF2 */
++#define S5P_GPF2_CON S5P_GPIO_REG(0x120)
++#define S5P_GPF2_DAT S5P_GPIO_REG(0x124)
++#define S5P_GPF2_PUD S5P_GPIO_REG(0x128)
++#define S5P_GPF2_DRV S5P_GPIO_REG(0x12C)
++#define S5P_GPF2_CONPDN S5P_GPIO_REG(0x130)
++#define S5P_GPF2_PUDPDN S5P_GPIO_REG(0x134)
++
++#define S5P_GPF2_0 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 0)
++#define S5P_GPF2_0_IN (0x0)
++#define S5P_GPF2_0_OUT (0x1)
++#define S5P_GPF2_0_LCD_VD12 (0x2)
++#define S5P_GPF2_0_SYS_VD12 (0x3)
++#define S5P_GPF2_0_V656_DATA4 (0x4)
++#define S5P_GPF2_0_EXT_INT10_0 (0xF)
++
++#define S5P_GPF2_1 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 1)
++#define S5P_GPF2_1_IN (0x0)
++#define S5P_GPF2_1_OUT (0x1)
++#define S5P_GPF2_1_LCD_VD13 (0x2)
++#define S5P_GPF2_1_SYS_VD13 (0x3)
++#define S5P_GPF2_1_V656_DATA5 (0x4)
++#define S5P_GPF2_1_EXT_INT10_1 (0xF)
++
++#define S5P_GPF2_2 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 2)
++#define S5P_GPF2_2_IN (0x0)
++#define S5P_GPF2_2_OUT (0x1)
++#define S5P_GPF2_2_LCD_VD14 (0x2)
++#define S5P_GPF2_2_SYS_VD14 (0x3)
++#define S5P_GPF2_2_V656_DATA6 (0x4)
++#define S5P_GPF2_2_EXT_INT10_2 (0xF)
++
++#define S5P_GPF2_3 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 3)
++#define S5P_GPF2_3_IN (0x0)
++#define S5P_GPF2_3_OUT (0x1)
++#define S5P_GPF2_3_LCD_VD15 (0x2)
++#define S5P_GPF2_3_SYS_VD15 (0x3)
++#define S5P_GPF2_3_V656_DATA7 (0x4)
++#define S5P_GPF2_3_EXT_INT10_3 (0xF)
++
++#define S5P_GPF2_4 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 4)
++#define S5P_GPF2_4_IN (0x0)
++#define S5P_GPF2_4_OUT (0x1)
++#define S5P_GPF2_4_LCD_VD16 (0x2)
++#define S5P_GPF2_4_SYS_VD16 (0x3)
++#define S5P_GPF2_4_EXT_INT10_4 (0xF)
++
++#define S5P_GPF2_5 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 5)
++#define S5P_GPF2_5_IN (0x0)
++#define S5P_GPF2_5_OUT (0x1)
++#define S5P_GPF2_5_LCD_VD17 (0x2)
++#define S5P_GPF2_5_SYS_VD17 (0x3)
++#define S5P_GPF2_5_EXT_INT10_5 (0xF)
++
++#define S5P_GPF2_6 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 6)
++#define S5P_GPF2_6_IN (0x0)
++#define S5P_GPF2_6_OUT (0x1)
++#define S5P_GPF2_6_LCD_VD18 (0x2)
++#define S5P_GPF2_6_EXT_INT10_6 (0xF)
++
++#define S5P_GPF2_7 S5P_GPIO_NO(S5P_GPIO_BANK_F2, 7)
++#define S5P_GPF2_7_IN (0x0)
++#define S5P_GPF2_7_OUT (0x1)
++#define S5P_GPF2_7_LCD_VD19 (0x2)
++#define S5P_GPF2_7_EXT_INT10_7 (0xF)
++
++/* GPF3 */
++#define S5P_GPF3_CON S5P_GPIO_REG(0x140)
++#define S5P_GPF3_DAT S5P_GPIO_REG(0x144)
++#define S5P_GPF3_PUD S5P_GPIO_REG(0x148)
++#define S5P_GPF3_DRV S5P_GPIO_REG(0x14C)
++#define S5P_GPF3_CONPDN S5P_GPIO_REG(0x150)
++#define S5P_GPF3_PUDPDN S5P_GPIO_REG(0x154)
++
++#define S5P_GPF3_0 S5P_GPIO_NO(S5P_GPIO_BANK_F3, 0)
++#define S5P_GPF3_0_IN (0x0)
++#define S5P_GPF3_0_OUT (0x1)
++#define S5P_GPF3_0_LCD_VD20 (0x2)
++#define S5P_GPF3_0_EXT_INT11_0 (0xF)
++
++#define S5P_GPF3_1 S5P_GPIO_NO(S5P_GPIO_BANK_F3, 1)
++#define S5P_GPF3_1_IN (0x0)
++#define S5P_GPF3_1_OUT (0x1)
++#define S5P_GPF3_1_LCD_VD21 (0x2)
++#define S5P_GPF3_1_EXT_INT11_1 (0xF)
++
++#define S5P_GPF3_2 S5P_GPIO_NO(S5P_GPIO_BANK_F3, 2)
++#define S5P_GPF3_2_IN (0x0)
++#define S5P_GPF3_2_OUT (0x1)
++#define S5P_GPF3_2_LCD_VD22 (0x2)
++#define S5P_GPF3_2_VSYNC_LDI (0x3)
++#define S5P_GPF3_2_V656_CLK (0x4)
++#define S5P_GPF3_2_EXT_INT11_2 (0xF)
++
++#define S5P_GPF3_3 S5P_GPIO_NO(S5P_GPIO_BANK_F3, 3)
++#define S5P_GPF3_3_IN (0x0)
++#define S5P_GPF3_3_OUT (0x1)
++#define S5P_GPF3_3_LCD_VD23 (0x2)
++#define S5P_GPF3_3_SYS_OE (0x3)
++#define S5P_GPF3_3_VEN_FIELD (0x4)
++#define S5P_GPF3_3_EXT_INT11_3 (0xF)
++
++/* GPG0 */
++#define S5P_GPG0_CON S5P_GPIO_REG(0x160)
++#define S5P_GPG0_DAT S5P_GPIO_REG(0x164)
++#define S5P_GPG0_PUD S5P_GPIO_REG(0x168)
++#define S5P_GPG0_DRV S5P_GPIO_REG(0x16C)
++#define S5P_GPG0_CONPDN S5P_GPIO_REG(0x170)
++#define S5P_GPG0_PUDPDN S5P_GPIO_REG(0x174)
++
++#define S5P_GPG0_0 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 0)
++#define S5P_GPG0_0_IN (0x0)
++#define S5P_GPG0_0_OUT (0x1)
++#define S5P_GPG0_0_SD0_CLK (0x2)
++#define S5P_GPG0_0_EXT_INT12_0 (0xF)
++
++#define S5P_GPG0_1 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 1)
++#define S5P_GPG0_1_IN (0x0)
++#define S5P_GPG0_1_OUT (0x1)
++#define S5P_GPG0_1_SD0_CMD (0x2)
++#define S5P_GPG0_1_EXT_INT12_1 (0xF)
++
++#define S5P_GPG0_2 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 2)
++#define S5P_GPG0_2_IN (0x0)
++#define S5P_GPG0_2_OUT (0x1)
++#define S5P_GPG0_2_SD0_DATA0 (0x2)
++#define S5P_GPG0_2_EXT_INT12_2 (0xF)
++
++#define S5P_GPG0_3 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 3)
++#define S5P_GPG0_3_IN (0x0)
++#define S5P_GPG0_3_OUT (0x1)
++#define S5P_GPG0_3_SD0_DATA1 (0x2)
++#define S5P_GPG0_3_EXT_INT12_3 (0xF)
++
++#define S5P_GPG0_4 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 4)
++#define S5P_GPG0_4_IN (0x0)
++#define S5P_GPG0_4_OUT (0x1)
++#define S5P_GPG0_4_SD0_DATA2 (0x2)
++#define S5P_GPG0_4_EXT_INT12_4 (0xF)
++
++#define S5P_GPG0_5 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 5)
++#define S5P_GPG0_5_IN (0x0)
++#define S5P_GPG0_5_OUT (0x1)
++#define S5P_GPG0_5_SD0_DATA3 (0x2)
++#define S5P_GPG0_5_EXT_INT12_5 (0xF)
++
++#define S5P_GPG0_6 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 6)
++#define S5P_GPG0_6_IN (0x0)
++#define S5P_GPG0_6_OUT (0x1)
++#define S5P_GPG0_6_SD0_DATA4 (0x2)
++#define S5P_GPG0_6_EXT_INT12_6 (0xF)
++
++#define S5P_GPG0_7 S5P_GPIO_NO(S5P_GPIO_BANK_G0, 7)
++#define S5P_GPG0_7_IN (0x0)
++#define S5P_GPG0_7_OUT (0x1)
++#define S5P_GPG0_7_SD0_DATA5 (0x2)
++#define S5P_GPG0_7_EXT_INT12_7 (0xF)
++
++/* GPG1 */
++#define S5P_GPG1_CON S5P_GPIO_REG(0x180)
++#define S5P_GPG1_DAT S5P_GPIO_REG(0x184)
++#define S5P_GPG1_PUD S5P_GPIO_REG(0x188)
++#define S5P_GPG1_DRV S5P_GPIO_REG(0x18C)
++#define S5P_GPG1_CONPDN S5P_GPIO_REG(0x190)
++#define S5P_GPG1_PUDPDN S5P_GPIO_REG(0x194)
++
++#define S5P_GPG1_0 S5P_GPIO_NO(S5P_GPIO_BANK_G1, 0)
++#define S5P_GPG1_0_IN (0x0)
++#define S5P_GPG1_0_OUT (0x1)
++#define S5P_GPG1_0_SD0_DATA6 (0x2)
++#define S5P_GPG1_0_EXT_INT13_0 (0xF)
++
++#define S5P_GPG1_1 S5P_GPIO_NO(S5P_GPIO_BANK_G1, 1)
++#define S5P_GPG1_1_IN (0x0)
++#define S5P_GPG1_1_OUT (0x1)
++#define S5P_GPG1_1_SD0_DATA7 (0x2)
++#define S5P_GPG1_1_EXT_INT13_1 (0xF)
++
++#define S5P_GPG1_2 S5P_GPIO_NO(S5P_GPIO_BANK_G1, 2)
++#define S5P_GPG1_2_IN (0x0)
++#define S5P_GPG1_2_OUT (0x1)
++#define S5P_GPG1_2_SD0_CDn (0x2)
++#define S5P_GPG1_2_EXT_INT13_2 (0xF)
++
++/* GPG2 */
++#define S5P_GPG2_CON S5P_GPIO_REG(0x1A0)
++#define S5P_GPG2_DAT S5P_GPIO_REG(0x1A4)
++#define S5P_GPG2_PUD S5P_GPIO_REG(0x1A8)
++#define S5P_GPG2_DRV S5P_GPIO_REG(0x1AC)
++#define S5P_GPG2_CONPDN S5P_GPIO_REG(0x1B0)
++#define S5P_GPG2_PUDPDN S5P_GPIO_REG(0x1B4)
++
++#define S5P_GPG2_0 S5P_GPIO_NO(S5P_GPIO_BANK_G2, 0)
++#define S5P_GPG2_0_IN (0x0)
++#define S5P_GPG2_0_OUT (0x1)
++#define S5P_GPG2_0_SD1_CLK (0x2)
++#define S5P_GPG2_0_EXT_INT14_0 (0xF)
++
++#define S5P_GPG2_1 S5P_GPIO_NO(S5P_GPIO_BANK_G2, 1)
++#define S5P_GPG2_1_IN (0x0)
++#define S5P_GPG2_1_OUT (0x1)
++#define S5P_GPG2_1_SD1_CMD (0x2)
++#define S5P_GPG2_1_EXT_INT14_1 (0xF)
++
++#define S5P_GPG2_2 S5P_GPIO_NO(S5P_GPIO_BANK_G2, 2)
++#define S5P_GPG2_2_IN (0x0)
++#define S5P_GPG2_2_OUT (0x1)
++#define S5P_GPG2_2_SD1_DATA0 (0x2)
++#define S5P_GPG2_2_EXT_INT14_2 (0xF)
++
++#define S5P_GPG2_3 S5P_GPIO_NO(S5P_GPIO_BANK_G2, 3)
++#define S5P_GPG2_3_IN (0x0)
++#define S5P_GPG2_3_OUT (0x1)
++#define S5P_GPG2_3_SD1_DATA1 (0x2)
++#define S5P_GPG2_3_EXT_INT14_3 (0xF)
++
++#define S5P_GPG2_4 S5P_GPIO_NO(S5P_GPIO_BANK_G2, 4)
++#define S5P_GPG2_4_IN (0x0)
++#define S5P_GPG2_4_OUT (0x1)
++#define S5P_GPG2_4_SD1_DATA2 (0x2)
++#define S5P_GPG2_4_EXT_INT14_4 (0xF)
++
++#define S5P_GPG2_5 S5P_GPIO_NO(S5P_GPIO_BANK_G2, 5)
++#define S5P_GPG2_5_IN (0x0)
++#define S5P_GPG2_5_OUT (0x1)
++#define S5P_GPG2_5_SD1_DATA3 (0x2)
++#define S5P_GPG2_5_EXT_INT14_5 (0xF)
++
++#define S5P_GPG2_6 S5P_GPIO_NO(S5P_GPIO_BANK_G2, 6)
++#define S5P_GPG2_6_IN (0x0)
++#define S5P_GPG2_6_OUT (0x1)
++#define S5P_GPG2_6_SD1_CDn (0x2)
++#define S5P_GPG2_6_EXT_INT14_6 (0xF)
++
++/* GPG3 */
++#define S5P_GPG3_CON S5P_GPIO_REG(0x1C0)
++#define S5P_GPG3_DAT S5P_GPIO_REG(0x1C4)
++#define S5P_GPG3_PUD S5P_GPIO_REG(0x1C8)
++#define S5P_GPG3_DRV S5P_GPIO_REG(0x1CC)
++#define S5P_GPG3_CONPDN S5P_GPIO_REG(0x1D0)
++#define S5P_GPG3_PUDPDN S5P_GPIO_REG(0x1D4)
++
++#define S5P_GPG3_0 S5P_GPIO_NO(S5P_GPIO_BANK_G3, 0)
++#define S5P_GPG3_0_IN (0x0)
++#define S5P_GPG3_0_OUT (0x1)
++#define S5P_GPG3_0_SD2_CLK (0x2)
++#define S5P_GPG3_0_SPI2_CLK (0x3)
++#define S5P_GPG3_0_I2S2_SCLK (0x4)
++#define S5P_GPG3_0_PCM0_SCLK (0x5)
++#define S5P_GPG3_0_EXT_INT15_0 (0xF)
++
++#define S5P_GPG3_1 S5P_GPIO_NO(S5P_GPIO_BANK_G3, 1)
++#define S5P_GPG3_1_IN (0x0)
++#define S5P_GPG3_1_OUT (0x1)
++#define S5P_GPG3_1_SD2_CMD (0x2)
++#define S5P_GPG3_1_SPI2_nSS (0x3)
++#define S5P_GPG3_1_I2S2_CDCLK (0x4)
++#define S5P_GPG3_1_PCM0_EXTCLK (0x5)
++#define S5P_GPG3_1_EXT_INT15_1 (0xF)
++
++#define S5P_GPG3_2 S5P_GPIO_NO(S5P_GPIO_BANK_G3, 2)
++#define S5P_GPG3_2_IN (0x0)
++#define S5P_GPG3_2_OUT (0x1)
++#define S5P_GPG3_2_SD2_DATA0 (0x2)
++#define S5P_GPG3_2_SPI2_MISO (0x3)
++#define S5P_GPG3_2_I2S2_LRCK (0x4)
++#define S5P_GPG3_2_PCM0_FSYNC (0x5)
++#define S5P_GPG3_2_EXT_INT15_2 (0xF)
++
++#define S5P_GPG3_3 S5P_GPIO_NO(S5P_GPIO_BANK_G3, 3)
++#define S5P_GPG3_3_IN (0x0)
++#define S5P_GPG3_3_OUT (0x1)
++#define S5P_GPG3_3_SD2_DATA1 (0x2)
++#define S5P_GPG3_3_SPI2_MOSI (0x3)
++#define S5P_GPG3_3_I2S2_SDI (0x4)
++#define S5P_GPG3_3_PCM0_SIN (0x5)
++#define S5P_GPG3_3_EXT_INT15_3 (0xF)
++
++#define S5P_GPG3_4 S5P_GPIO_NO(S5P_GPIO_BANK_G3, 4)
++#define S5P_GPG3_4_IN (0x0)
++#define S5P_GPG3_4_OUT (0x1)
++#define S5P_GPG3_4_SD2_DATA2 (0x2)
++#define S5P_GPG3_4_I2S2_SDO (0x4)
++#define S5P_GPG3_4_PCM0_SOUT (0x5)
++#define S5P_GPG3_4_EXT_INT15_4 (0xF)
++
++#define S5P_GPG3_5 S5P_GPIO_NO(S5P_GPIO_BANK_G3, 5)
++#define S5P_GPG3_5_IN (0x0)
++#define S5P_GPG3_5_OUT (0x1)
++#define S5P_GPG3_5_SD2_DATA3 (0x2)
++#define S5P_GPG3_5_SPDIF0_OUT (0x5)
++#define S5P_GPG3_5_EXT_INT15_5 (0xF)
++
++#define S5P_GPG3_6 S5P_GPIO_NO(S5P_GPIO_BANK_G3, 6)
++#define S5P_GPG3_6_IN (0x0)
++#define S5P_GPG3_6_OUT (0x1)
++#define S5P_GPG3_6_SD2_CDn (0x2)
++#define S5P_GPG3_6_SPDIF_EXTCLK (0x5)
++#define S5P_GPG3_6_EXT_INT15_6 (0xF)
++
++/* GPH0 */
++#define S5P_GPH0_CON S5P_GPIO_REG(0xC00)
++#define S5P_GPH0_DAT S5P_GPIO_REG(0xC04)
++#define S5P_GPH0_PUD S5P_GPIO_REG(0xC08)
++#define S5P_GPH0_DRV S5P_GPIO_REG(0xC0C)
++#define S5P_GPH0_CONPDN S5P_GPIO_REG(0xC10)
++#define S5P_GPH0_PUDPDN S5P_GPIO_REG(0xC14)
++
++#define S5P_GPH0_0 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 0)
++#define S5P_GPH0_0_IN (0x0)
++#define S5P_GPH0_0_OUT (0x1)
++#define S5P_GPH0_0_EXT_INT_0 (0x2)
++
++#define S5P_GPH0_1 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 1)
++#define S5P_GPH0_1_IN (0x0)
++#define S5P_GPH0_1_OUT (0x1)
++#define S5P_GPH0_1_EXT_INT_1 (0x2)
++
++#define S5P_GPH0_2 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 2)
++#define S5P_GPH0_2_IN (0x0)
++#define S5P_GPH0_2_OUT (0x1)
++#define S5P_GPH0_2_EXT_INT_2 (0x2)
++
++#define S5P_GPH0_3 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 3)
++#define S5P_GPH0_3_IN (0x0)
++#define S5P_GPH0_3_OUT (0x1)
++#define S5P_GPH0_3_EXT_INT_3 (0x2)
++
++#define S5P_GPH0_4 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 4)
++#define S5P_GPH0_4_IN (0x0)
++#define S5P_GPH0_4_OUT (0x1)
++#define S5P_GPH0_4_EXT_INT_4 (0x2)
++
++#define S5P_GPH0_5 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 5)
++#define S5P_GPH0_5_IN (0x0)
++#define S5P_GPH0_5_OUT (0x1)
++#define S5P_GPH0_5_EXT_INT_5 (0x2)
++
++#define S5P_GPH0_6 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 6)
++#define S5P_GPH0_6_IN (0x0)
++#define S5P_GPH0_6_OUT (0x1)
++#define S5P_GPH0_6_EXT_INT_6 (0x2)
++
++#define S5P_GPH0_7 S5P_GPIO_NO(S5P_GPIO_BANK_H0, 7)
++#define S5P_GPH0_7_IN (0x0)
++#define S5P_GPH0_7_OUT (0x1)
++#define S5P_GPH0_7_EXT_INT_7 (0x2)
++
++/* GPH1 */
++#define S5P_GPH1_CON S5P_GPIO_REG(0xC20)
++#define S5P_GPH1_DAT S5P_GPIO_REG(0xC24)
++#define S5P_GPH1_PUD S5P_GPIO_REG(0xC28)
++#define S5P_GPH1_DRV S5P_GPIO_REG(0xC2C)
++
++#define S5P_GPH1_0 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 0)
++#define S5P_GPH1_0_IN (0x0)
++#define S5P_GPH1_0_OUT (0x1)
++#define S5P_GPH1_0_EXT_INT_8 (0x2)
++
++#define S5P_GPH1_1 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 1)
++#define S5P_GPH1_1_IN (0x0)
++#define S5P_GPH1_1_OUT (0x1)
++#define S5P_GPH1_1_EXT_INT_9 (0x2)
++
++#define S5P_GPH1_2 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 2)
++#define S5P_GPH1_2_IN (0x0)
++#define S5P_GPH1_2_OUT (0x1)
++#define S5P_GPH1_2_EXT_INT_10 (0x2)
++#define S5P_GPH1_2_CG_REALIN (0x3)
++
++#define S5P_GPH1_3 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 3)
++#define S5P_GPH1_3_IN (0x0)
++#define S5P_GPH1_3_OUT (0x1)
++#define S5P_GPH1_3_EXT_INT_11 (0x2)
++#define S5P_GPH1_3_CG_IMGIN (0x3)
++
++#define S5P_GPH1_4 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 4)
++#define S5P_GPH1_4_IN (0x0)
++#define S5P_GPH1_4_OUT (0x1)
++#define S5P_GPH1_4_EXT_INT_12 (0x2)
++#define S5P_GPH1_4_CG_GPO0 (0x3)
++
++#define S5P_GPH1_5 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 5)
++#define S5P_GPH1_5_IN (0x0)
++#define S5P_GPH1_5_OUT (0x1)
++#define S5P_GPH1_5_EXT_INT_13 (0x2)
++#define S5P_GPH1_5_CG_GPO1 (0x3)
++
++#define S5P_GPH1_6 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 6)
++#define S5P_GPH1_6_IN (0x0)
++#define S5P_GPH1_6_OUT (0x1)
++#define S5P_GPH1_6_EXT_INT_14 (0x2)
++#define S5P_GPH1_6_CG_GPO2 (0x3)
++
++#define S5P_GPH1_7 S5P_GPIO_NO(S5P_GPIO_BANK_H1, 7)
++#define S5P_GPH1_7_IN (0x0)
++#define S5P_GPH1_7_OUT (0x1)
++#define S5P_GPH1_7_EXT_INT_15 (0x2)
++#define S5P_GPH1_7_CG_GPO3 (0x3)
++
++/* GPH2 */
++#define S5P_GPH2_CON S5P_GPIO_REG(0xC40)
++#define S5P_GPH2_DAT S5P_GPIO_REG(0xC44)
++#define S5P_GPH2_PUD S5P_GPIO_REG(0xC48)
++#define S5P_GPH2_DRV S5P_GPIO_REG(0xC4C)
++
++#define S5P_GPH2_0 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 0)
++#define S5P_GPH2_0_IN (0x0)
++#define S5P_GPH2_0_OUT (0x1)
++#define S5P_GPH2_0_EXT_INT_16 (0x2)
++#define S5P_GPH2_0_KP_COL0 (0x3)
++#define S5P_GPH2_0_CAM_B_DATA0 (0x4)
++
++#define S5P_GPH2_1 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 1)
++#define S5P_GPH2_1_IN (0x0)
++#define S5P_GPH2_1_OUT (0x1)
++#define S5P_GPH2_1_EXT_INT_17 (0x2)
++#define S5P_GPH2_1_KP_COL1 (0x3)
++#define S5P_GPH2_1_CAM_B_DATA1 (0x4)
++
++#define S5P_GPH2_2 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 2)
++#define S5P_GPH2_2_IN (0x0)
++#define S5P_GPH2_2_OUT (0x1)
++#define S5P_GPH2_2_EXT_INT_18 (0x2)
++#define S5P_GPH2_2_KP_COL2 (0x3)
++#define S5P_GPH2_2_CAM_B_DATA2 (0x4)
++
++#define S5P_GPH2_3 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 3)
++#define S5P_GPH2_3_IN (0x0)
++#define S5P_GPH2_3_OUT (0x1)
++#define S5P_GPH2_3_EXT_INT_19 (0x2)
++#define S5P_GPH2_3_KP_COL3 (0x3)
++#define S5P_GPH2_3_CAM_B_DATA3 (0x4)
++
++#define S5P_GPH2_4 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 4)
++#define S5P_GPH2_4_IN (0x0)
++#define S5P_GPH2_4_OUT (0x1)
++#define S5P_GPH2_4_EXT_INT_20 (0x2)
++#define S5P_GPH2_4_KP_COL4 (0x3)
++#define S5P_GPH2_4_CAM_B_DATA4 (0x4)
++
++#define S5P_GPH2_5 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 5)
++#define S5P_GPH2_5_IN (0x0)
++#define S5P_GPH2_5_OUT (0x1)
++#define S5P_GPH2_5_EXT_INT_21 (0x2)
++#define S5P_GPH2_5_KP_COL5 (0x3)
++#define S5P_GPH2_5_CAM_B_DATA5 (0x4)
++
++#define S5P_GPH2_6 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 6)
++#define S5P_GPH2_6_IN (0x0)
++#define S5P_GPH2_6_OUT (0x1)
++#define S5P_GPH2_6_EXT_INT_22 (0x2)
++#define S5P_GPH2_6_KP_COL6 (0x3)
++#define S5P_GPH2_6_CAM_B_DATA6 (0x4)
++
++#define S5P_GPH2_7 S5P_GPIO_NO(S5P_GPIO_BANK_H2, 7)
++#define S5P_GPH2_7_IN (0x0)
++#define S5P_GPH2_7_OUT (0x1)
++#define S5P_GPH2_7_EXT_INT_23 (0x2)
++#define S5P_GPH2_7_KP_COL7 (0x3)
++#define S5P_GPH2_7_CAM_B_DATA7 (0x4)
++
++/* GPH3 */
++#define S5P_GPH3_CON S5P_GPIO_REG(0xC60)
++#define S5P_GPH3_DAT S5P_GPIO_REG(0xC64)
++#define S5P_GPH3_PUD S5P_GPIO_REG(0xC68)
++#define S5P_GPH3_DRV S5P_GPIO_REG(0xC6C)
++
++#define S5P_GPH3_0 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 0)
++#define S5P_GPH3_0_IN (0x0)
++#define S5P_GPH3_0_OUT (0x1)
++#define S5P_GPH3_0_EXT_INT_24 (0x2)
++#define S5P_GPH3_0_KP_ROW0 (0x3)
++#define S5P_GPH3_0_CAM_B_PCLK (0x4)
++
++#define S5P_GPH3_1 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 1)
++#define S5P_GPH3_1_IN (0x0)
++#define S5P_GPH3_1_OUT (0x1)
++#define S5P_GPH3_1_EXT_INT_25 (0x2)
++#define S5P_GPH3_1_KP_ROW1 (0x3)
++#define S5P_GPH3_1_CAM_B_VSYNC (0x4)
++
++#define S5P_GPH3_2 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 2)
++#define S5P_GPH3_2_IN (0x0)
++#define S5P_GPH3_2_OUT (0x1)
++#define S5P_GPH3_2_EXT_INT_26 (0x2)
++#define S5P_GPH3_2_KP_ROW2 (0x3)
++#define S5P_GPH3_2_CAM_B_HREF (0x4)
++
++#define S5P_GPH3_3 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 3)
++#define S5P_GPH3_3_IN (0x0)
++#define S5P_GPH3_3_OUT (0x1)
++#define S5P_GPH3_3_EXT_INT_27 (0x2)
++#define S5P_GPH3_3_KP_ROW3 (0x3)
++#define S5P_GPH3_3_CAM_B_FIELD (0x4)
++
++#define S5P_GPH3_4 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 4)
++#define S5P_GPH3_4_IN (0x0)
++#define S5P_GPH3_4_OUT (0x1)
++#define S5P_GPH3_4_EXT_INT_28 (0x2)
++#define S5P_GPH3_4_KP_ROW4 (0x3)
++#define S5P_GPH3_4_CAN0_TX (0x4)
++
++#define S5P_GPH3_5 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 5)
++#define S5P_GPH3_5_IN (0x0)
++#define S5P_GPH3_5_OUT (0x1)
++#define S5P_GPH3_5_EXT_INT_29 (0x2)
++#define S5P_GPH3_5_KP_ROW5 (0x3)
++#define S5P_GPH3_5_CAN0_RX (0x4)
++
++#define S5P_GPH3_6 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 6)
++#define S5P_GPH3_6_IN (0x0)
++#define S5P_GPH3_6_OUT (0x1)
++#define S5P_GPH3_6_EXT_INT_30 (0x2)
++#define S5P_GPH3_6_KP_ROW6 (0x3)
++#define S5P_GPH3_6_CAN1_TX (0x4)
++
++#define S5P_GPH3_7 S5P_GPIO_NO(S5P_GPIO_BANK_H3, 6)
++#define S5P_GPH3_7_IN (0x0)
++#define S5P_GPH3_7_OUT (0x1)
++#define S5P_GPH3_7_EXT_INT_31 (0x2)
++#define S5P_GPH3_7_KP_ROW7 (0x3)
++#define S5P_GPH3_7_CAN1_RX (0x4)
++
++/* GPI */
++#define S5P_GPI0_CON S5P_GPIO_REG(0x1E0)
++#define S5P_GPI0_DAT S5P_GPIO_REG(0x1E4)
++#define S5P_GPI0_PUD S5P_GPIO_REG(0x1E8)
++#define S5P_GPI0_DRV S5P_GPIO_REG(0x1EC)
++#define S5P_GPI0_CONPDN S5P_GPIO_REG(0x1F0)
++#define S5P_GPI0_PUDPDN S5P_GPIO_REG(0x1F4)
++
++#define S5P_GPI0 S5P_GPIO_NO(S5P_GPIO_BANK_I, 0)
++#define S5P_GPI0_IN (0x0)
++#define S5P_GPI0_OUT (0x1)
++#define S5P_GPI0_IEM_SCLK (0x2)
++#define S5P_GPI0_EXT_INT20_0 (0xF)
++
++#define S5P_GPI1 S5P_GPIO_NO(S5P_GPIO_BANK_I, 1)
++#define S5P_GPI1_IN (0x0)
++#define S5P_GPI1_OUT (0x1)
++#define S5P_GPI1_IEM_SPWI (0x2)
++#define S5P_GPI1_EXT_INT20_1 (0xF)
++
++#define S5P_GPI2 S5P_GPIO_NO(S5P_GPIO_BANK_I, 2)
++#define S5P_GPI3 S5P_GPIO_NO(S5P_GPIO_BANK_I, 3)
++
++#define S5P_GPI4 S5P_GPIO_NO(S5P_GPIO_BANK_I, 4)
++#define S5P_GPI4_IN (0x0)
++#define S5P_GPI4_OUT (0x1)
++#define S5P_GPI4_NFMOD2 (0x2)
++#define S5P_GPI4_EXT_INT20_4 (0xF)
++
++#define S5P_GPI5 S5P_GPIO_NO(S5P_GPIO_BANK_I, 5)
++#define S5P_GPI5_IN (0x0)
++#define S5P_GPI5_OUT (0x1)
++#define S5P_GPI5_NFMOD3 (0x2)
++#define S5P_GPI5_EXT_INT20_5 (0xF)
++
++#define S5P_GPI6 S5P_GPIO_NO(S5P_GPIO_BANK_I, 6)
++#define S5P_GPI6_IN (0x0)
++#define S5P_GPI6_OUT (0x1)
++#define S5P_GPI6_NFMOD4 (0x2)
++#define S5P_GPI6_EXT_INT20_6 (0xF)
++
++#define S5P_GPI7 S5P_GPIO_NO(S5P_GPIO_BANK_I, 7)
++#define S5P_GPI7_IN (0x0)
++#define S5P_GPI7_OUT (0x1)
++#define S5P_GPI7_NFMOD5 (0x2)
++#define S5P_GPI7_EXT_INT20_7 (0xF)
++
++/* GPJ0 */
++#define S5P_GPJ0_CON S5P_GPIO_REG(0x200)
++#define S5P_GPJ0_DAT S5P_GPIO_REG(0x204)
++#define S5P_GPJ0_PUD S5P_GPIO_REG(0x208)
++#define S5P_GPJ0_DRV S5P_GPIO_REG(0x20C)
++#define S5P_GPJ0_CONPDN S5P_GPIO_REG(0x210)
++#define S5P_GPJ0_PUDPDN S5P_GPIO_REG(0x214)
++
++#define S5P_GPJ0_0 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 0)
++#define S5P_GPJ0_0_IN (0x0)
++#define S5P_GPJ0_0_OUT (0x1)
++#define S5P_GPJ0_0_MSM_ADDR0 (0x2)
++#define S5P_GPJ0_0_HSI_TX_DATA (0x3)
++#define S5P_GPJ0_0_CF_ADDR0 (0x4)
++#define S5P_GPJ0_0_LCD1_HSYNC (0x5)
++#define S5P_GPJ0_0_EXT_INT21_0 (0xF)
++
++#define S5P_GPJ0_1 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 1)
++#define S5P_GPJ0_1_IN (0x0)
++#define S5P_GPJ0_1_OUT (0x1)
++#define S5P_GPJ0_1_MSM_ADDR1 (0x2)
++#define S5P_GPJ0_1_HSI_TX_FLAG (0x3)
++#define S5P_GPJ0_1_CF_ADDR1 (0x4)
++#define S5P_GPJ0_1_LCD1_VSYNC (0x5)
++#define S5P_GPJ0_1_EXT_INT21_1 (0xF)
++
++#define S5P_GPJ0_2 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 2)
++#define S5P_GPJ0_2_IN (0x0)
++#define S5P_GPJ0_2_OUT (0x1)
++#define S5P_GPJ0_2_MSM_ADDR2 (0x2)
++#define S5P_GPJ0_2_HSI_TX_WAKE (0x3)
++#define S5P_GPJ0_2_CF_ADDR2 (0x4)
++#define S5P_GPJ0_2_LCD1_VDEN (0x5)
++#define S5P_GPJ0_2_EXT_INT21_2 (0xF)
++
++#define S5P_GPJ0_3 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 3)
++#define S5P_GPJ0_3_IN (0x0)
++#define S5P_GPJ0_3_OUT (0x1)
++#define S5P_GPJ0_3_MSM_ADDR3 (0x2)
++#define S5P_GPJ0_3_HSI_TX_READY (0x3)
++#define S5P_GPJ0_3_CF_IORDY (0x4)
++#define S5P_GPJ0_3_LCD1_VCLK (0x5)
++#define S5P_GPJ0_3_EXT_INT21_3 (0xF)
++
++#define S5P_GPJ0_4 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 4)
++#define S5P_GPJ0_4_IN (0x0)
++#define S5P_GPJ0_4_OUT (0x1)
++#define S5P_GPJ0_4_MSM_ADDR4 (0x2)
++#define S5P_GPJ0_4_HSI_RX_DATA (0x3)
++#define S5P_GPJ0_4_CF_INTRQ (0x4)
++#define S5P_GPJ0_4_LCD1_VD0 (0x5)
++#define S5P_GPJ0_4_EXT_INT21_4 (0xF)
++
++#define S5P_GPJ0_5 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 5)
++#define S5P_GPJ0_5_IN (0x0)
++#define S5P_GPJ0_5_OUT (0x1)
++#define S5P_GPJ0_5_MSM_ADDR5 (0x2)
++#define S5P_GPJ0_5_HSI_RX_FLAG (0x3)
++#define S5P_GPJ0_5_CF_INPACKn (0x4)
++#define S5P_GPJ0_5_LCD1_VD1 (0x5)
++#define S5P_GPJ0_5_EXT_INT21_5 (0xF)
++
++#define S5P_GPJ0_6 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 6)
++#define S5P_GPJ0_6_IN (0x0)
++#define S5P_GPJ0_6_OUT (0x1)
++#define S5P_GPJ0_6_MSM_ADDR6 (0x2)
++#define S5P_GPJ0_6_HSI_RX_WAKE (0x3)
++#define S5P_GPJ0_6_CF_RESET (0x4)
++#define S5P_GPJ0_6_LCD1_VD2 (0x5)
++#define S5P_GPJ0_6_EXT_INT21_6 (0xF)
++
++#define S5P_GPJ0_7 S5P_GPIO_NO(S5P_GPIO_BANK_J0, 7)
++#define S5P_GPJ0_7_IN (0x0)
++#define S5P_GPJ0_7_OUT (0x1)
++#define S5P_GPJ0_7_MSM_ADDR7 (0x2)
++#define S5P_GPJ0_7_HSI_RX_READY (0x3)
++#define S5P_GPJ0_7_CF_REG (0x4)
++#define S5P_GPJ0_7_LCD1_VD3 (0x5)
++#define S5P_GPJ0_7_EXT_INT21_7 (0xF)
++
++/* GPJ1 */
++#define S5P_GPJ1_CON S5P_GPIO_REG(0x220)
++#define S5P_GPJ1_DAT S5P_GPIO_REG(0x224)
++#define S5P_GPJ1_PUD S5P_GPIO_REG(0x228)
++#define S5P_GPJ1_DRV S5P_GPIO_REG(0x22C)
++#define S5P_GPJ1_CONPDN S5P_GPIO_REG(0x230)
++#define S5P_GPJ1_PUDPDN S5P_GPIO_REG(0x234)
++
++#define S5P_GPJ1_0 S5P_GPIO_NO(S5P_GPIO_BANK_J1, 0)
++#define S5P_GPJ1_0_IN (0x0)
++#define S5P_GPJ1_0_OUT (0x1)
++#define S5P_GPJ1_0_MSM_ADDR8 (0x2)
++#define S5P_GPJ1_0_LCD1_VD4 (0x5)
++#define S5P_GPJ1_0_EXT_INT22_0 (0xF)
++
++#define S5P_GPJ1_1 S5P_GPIO_NO(S5P_GPIO_BANK_J1, 1)
++#define S5P_GPJ1_1_IN (0x0)
++#define S5P_GPJ1_1_OUT (0x1)
++#define S5P_GPJ1_1_MSM_ADDR9 (0x2)
++#define S5P_GPJ1_1_LCD1_VD5 (0x5)
++#define S5P_GPJ1_1_EXT_INT22_1 (0xF)
++
++#define S5P_GPJ1_2 S5P_GPIO_NO(S5P_GPIO_BANK_J1, 2)
++#define S5P_GPJ1_2_IN (0x0)
++#define S5P_GPJ1_2_OUT (0x1)
++#define S5P_GPJ1_2_MSM_ADDR10 (0x2)
++#define S5P_GPJ1_2_LCD1_VD6 (0x5)
++#define S5P_GPJ1_2_EXT_INT22_2 (0xF)
++
++#define S5P_GPJ1_3 S5P_GPIO_NO(S5P_GPIO_BANK_J1, 3)
++#define S5P_GPJ1_3_IN (0x0)
++#define S5P_GPJ1_3_OUT (0x1)
++#define S5P_GPJ1_3_MSM_ADDR11 (0x2)
++#define S5P_GPJ1_3_LCD1_VD7 (0x5)
++#define S5P_GPJ1_3_EXT_INT22_3 (0xF)
++
++#define S5P_GPJ1_4 S5P_GPIO_NO(S5P_GPIO_BANK_J1, 4)
++#define S5P_GPJ1_4_IN (0x0)
++#define S5P_GPJ1_4_OUT (0x1)
++#define S5P_GPJ1_4_MSM_ADDR12 (0x2)
++#define S5P_GPJ1_4_LCD1_VD8 (0x5)
++#define S5P_GPJ1_4_EXT_INT22_4 (0xF)
++
++/* GPJ2 */
++#define S5P_GPJ2_CON S5P_GPIO_REG(0x240)
++#define S5P_GPJ2_DAT S5P_GPIO_REG(0x244)
++#define S5P_GPJ2_PUD S5P_GPIO_REG(0x248)
++#define S5P_GPJ2_DRV S5P_GPIO_REG(0x24C)
++#define S5P_GPJ2_CONPDN S5P_GPIO_REG(0x250)
++#define S5P_GPJ2_PUDPDN S5P_GPIO_REG(0x254)
++
++#define S5P_GPJ2_0 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 0)
++#define S5P_GPJ2_0_IN (0x0)
++#define S5P_GPJ2_0_OUT (0x1)
++#define S5P_GPJ2_0_MSM_DATA0 (0x2)
++#define S5P_GPJ2_0_CF_DATA0 (0x4)
++#define S5P_GPJ2_0_LCD1_VD9 (0x5)
++#define S5P_GPJ2_0_EXT_INT23_0 (0xF)
++
++#define S5P_GPJ2_1 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 1)
++#define S5P_GPJ2_1_IN (0x0)
++#define S5P_GPJ2_1_OUT (0x1)
++#define S5P_GPJ2_1_MSM_DATA1 (0x2)
++#define S5P_GPJ2_1_CF_DATA1 (0x4)
++#define S5P_GPJ2_1_LCD1_VD10 (0x5)
++#define S5P_GPJ2_1_EXT_INT23_1 (0xF)
++
++#define S5P_GPJ2_2 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 2)
++#define S5P_GPJ2_2_IN (0x0)
++#define S5P_GPJ2_2_OUT (0x1)
++#define S5P_GPJ2_2_MSM_DATA2 (0x2)
++#define S5P_GPJ2_2_CF_DATA2 (0x4)
++#define S5P_GPJ2_2_LCD1_VD11 (0x5)
++#define S5P_GPJ2_2_EXT_INT23_2 (0xF)
++
++#define S5P_GPJ2_3 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 3)
++#define S5P_GPJ2_3_IN (0x0)
++#define S5P_GPJ2_3_OUT (0x1)
++#define S5P_GPJ2_3_MSM_DATA3 (0x2)
++#define S5P_GPJ2_3_CF_DATA3 (0x4)
++#define S5P_GPJ2_3_LCD1_VD12 (0x5)
++#define S5P_GPJ2_3_EXT_INT23_3 (0xF)
++
++#define S5P_GPJ2_4 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 4)
++#define S5P_GPJ2_4_IN (0x0)
++#define S5P_GPJ2_4_OUT (0x1)
++#define S5P_GPJ2_4_MSM_DATA4 (0x2)
++#define S5P_GPJ2_4_CF_DATA4 (0x4)
++#define S5P_GPJ2_4_LCD1_VD13 (0x5)
++#define S5P_GPJ2_4_EXT_INT23_4 (0xF)
++
++#define S5P_GPJ2_5 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 5)
++#define S5P_GPJ2_5_IN (0x0)
++#define S5P_GPJ2_5_OUT (0x1)
++#define S5P_GPJ2_5_MSM_DATA5 (0x2)
++#define S5P_GPJ2_5_CF_DATA5 (0x4)
++#define S5P_GPJ2_5_LCD1_VD14 (0x5)
++#define S5P_GPJ2_5_EXT_INT23_5 (0xF)
++
++#define S5P_GPJ2_6 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 6)
++#define S5P_GPJ2_6_IN (0x0)
++#define S5P_GPJ2_6_OUT (0x1)
++#define S5P_GPJ2_6_MSM_DATA6 (0x2)
++#define S5P_GPJ2_6_CF_DATA6 (0x4)
++#define S5P_GPJ2_6_LCD1_VD15 (0x5)
++#define S5P_GPJ2_6_EXT_INT23_6 (0xF)
++
++#define S5P_GPJ2_7 S5P_GPIO_NO(S5P_GPIO_BANK_J2, 7)
++#define S5P_GPJ2_7_IN (0x0)
++#define S5P_GPJ2_7_OUT (0x1)
++#define S5P_GPJ2_7_MSM_DATA7 (0x2)
++#define S5P_GPJ2_7_CF_DATA7 (0x4)
++#define S5P_GPJ2_7_LCD1_VD16 (0x5)
++#define S5P_GPJ2_7_EXT_INT23_7 (0xF)
++
++/* GPJ3 */
++#define S5P_GPJ3_CON S5P_GPIO_REG(0x260)
++#define S5P_GPJ3_DAT S5P_GPIO_REG(0x264)
++#define S5P_GPJ3_PUD S5P_GPIO_REG(0x268)
++#define S5P_GPJ3_DRV S5P_GPIO_REG(0x26C)
++#define S5P_GPJ3_CONPDN S5P_GPIO_REG(0x270)
++#define S5P_GPJ3_PUDPDN S5P_GPIO_REG(0x274)
++
++#define S5P_GPJ3_0 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 0)
++#define S5P_GPJ3_0_IN (0x0)
++#define S5P_GPJ3_0_OUT (0x1)
++#define S5P_GPJ3_0_MSM_DATA8 (0x2)
++#define S5P_GPJ3_0_CF_DATA8 (0x4)
++#define S5P_GPJ3_0_LCD1_VD17 (0x5)
++#define S5P_GPJ3_0_EXT_INT24_0 (0xF)
++
++#define S5P_GPJ3_1 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 1)
++#define S5P_GPJ3_1_IN (0x0)
++#define S5P_GPJ3_1_OUT (0x1)
++#define S5P_GPJ3_1_MSM_DATA9 (0x2)
++#define S5P_GPJ3_1_CF_DATA9 (0x4)
++#define S5P_GPJ3_1_LCD1_VD18 (0x5)
++#define S5P_GPJ3_1_EXT_INT24_1 (0xF)
++
++#define S5P_GPJ3_2 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 2)
++#define S5P_GPJ3_2_IN (0x0)
++#define S5P_GPJ3_2_OUT (0x1)
++#define S5P_GPJ3_2_MSM_DATA10 (0x2)
++#define S5P_GPJ3_2_CF_DATA10 (0x4)
++#define S5P_GPJ3_2_LCD1_VD19 (0x5)
++#define S5P_GPJ3_2_EXT_INT24_2 (0xF)
++
++#define S5P_GPJ3_3 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 3)
++#define S5P_GPJ3_3_IN (0x0)
++#define S5P_GPJ3_3_OUT (0x1)
++#define S5P_GPJ3_3_MSM_DATA11 (0x2)
++#define S5P_GPJ3_3_CF_DATA11 (0x4)
++#define S5P_GPJ3_3_LCD1_VD20 (0x5)
++#define S5P_GPJ3_3_EXT_INT24_3 (0xF)
++
++#define S5P_GPJ3_4 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 4)
++#define S5P_GPJ3_4_IN (0x0)
++#define S5P_GPJ3_4_OUT (0x1)
++#define S5P_GPJ3_4_MSM_DATA12 (0x2)
++#define S5P_GPJ3_4_CF_DATA12 (0x4)
++#define S5P_GPJ3_4_LCD1_VD21 (0x5)
++#define S5P_GPJ3_4_EXT_INT24_4 (0xF)
++
++#define S5P_GPJ3_5 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 5)
++#define S5P_GPJ3_5_IN (0x0)
++#define S5P_GPJ3_5_OUT (0x1)
++#define S5P_GPJ3_5_MSM_DATA13 (0x2)
++#define S5P_GPJ3_5_CF_DATA13 (0x4)
++#define S5P_GPJ3_5_LCD1_VD22 (0x5)
++#define S5P_GPJ3_5_EXT_INT24_5 (0xF)
++
++#define S5P_GPJ3_6 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 6)
++#define S5P_GPJ3_6_IN (0x0)
++#define S5P_GPJ3_6_OUT (0x1)
++#define S5P_GPJ3_6_MSM_DATA14 (0x2)
++#define S5P_GPJ3_6_CF_DATA14 (0x4)
++#define S5P_GPJ3_6_LCD1_VD23 (0x5)
++#define S5P_GPJ3_6_EXT_INT24_6 (0xF)
++
++#define S5P_GPJ3_7 S5P_GPIO_NO(S5P_GPIO_BANK_J3, 7)
++#define S5P_GPJ3_7_IN (0x0)
++#define S5P_GPJ3_7_OUT (0x1)
++#define S5P_GPJ3_7_MSM_DATA15 (0x2)
++#define S5P_GPJ3_7_CF_DATA15 (0x4)
++#define S5P_GPJ3_7_EXT_INT24_7 (0xF)
++
++/* GPJ4 */
++#define S5P_GPJ4_CON S5P_GPIO_REG(0x280)
++#define S5P_GPJ4_DAT S5P_GPIO_REG(0x284)
++#define S5P_GPJ4_PUD S5P_GPIO_REG(0x288)
++#define S5P_GPJ4_DRV S5P_GPIO_REG(0x28C)
++#define S5P_GPJ4_CONPDN S5P_GPIO_REG(0x290)
++#define S5P_GPJ4_PUDPDN S5P_GPIO_REG(0x294)
++
++#define S5P_GPJ4_0 S5P_GPIO_NO(S5P_GPIO_BANK_J4, 0)
++#define S5P_GPJ4_0_IN (0x0)
++#define S5P_GPJ4_0_OUT (0x1)
++#define S5P_GPJ4_0_MSM_CSn (0x2)
++#define S5P_GPJ4_0_CF_CSn0 (0x4)
++#define S5P_GPJ4_0_EXT_INT25_0 (0xF)
++
++#define S5P_GPJ4_1 S5P_GPIO_NO(S5P_GPIO_BANK_J4, 1)
++#define S5P_GPJ4_1_IN (0x0)
++#define S5P_GPJ4_1_OUT (0x1)
++#define S5P_GPJ4_1_MSM_WEn (0x2)
++#define S5P_GPJ4_1_CF_CSn1 (0x4)
++#define S5P_GPJ4_1_EXT_INT25_1 (0xF)
++
++#define S5P_GPJ4_2 S5P_GPIO_NO(S5P_GPIO_BANK_J4, 2)
++#define S5P_GPJ4_2_IN (0x0)
++#define S5P_GPJ4_2_OUT (0x1)
++#define S5P_GPJ4_2_MSM_Rn (0x2)
++#define S5P_GPJ4_2_CF_IORD_CFn (0x4)
++#define S5P_GPJ4_2_EXT_INT25_2 (0xF)
++
++#define S5P_GPJ4_3 S5P_GPIO_NO(S5P_GPIO_BANK_J4, 3)
++#define S5P_GPJ4_3_IN (0x0)
++#define S5P_GPJ4_3_OUT (0x1)
++#define S5P_GPJ4_3_MSM_IRQn (0x2)
++#define S5P_GPJ4_3_CF_IOWR_CFn (0x4)
++#define S5P_GPJ4_3_EXT_INT25_3 (0xF)
++
++/* GPK0 */
++#define S5P_GPK0_CON S5P_GPIO_REG(0x2A0)
++#define S5P_GPK0_DAT S5P_GPIO_REG(0x2A4)
++#define S5P_GPK0_PUD S5P_GPIO_REG(0x2A8)
++#define S5P_GPK0_DRV S5P_GPIO_REG(0x2AC)
++#define S5P_GPK0_CONPDN S5P_GPIO_REG(0x2B0)
++#define S5P_GPK0_PUDPDN S5P_GPIO_REG(0x2B4)
++
++#define S5P_GPK0_0 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 0)
++#define S5P_GPK0_0_IN (0x0)
++#define S5P_GPK0_0_OUT (0x1)
++#define S5P_GPK0_0_SROM_CSn0 (0x2)
++
++#define S5P_GPK0_1 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 1)
++#define S5P_GPK0_1_IN (0x0)
++#define S5P_GPK0_1_OUT (0x1)
++#define S5P_GPK0_1_SROM_CSn1 (0x2)
++
++#define S5P_GPK0_2 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 2)
++#define S5P_GPK0_2_IN (0x0)
++#define S5P_GPK0_2_OUT (0x1)
++#define S5P_GPK0_2_SROM_CSn2 (0x2)
++#define S5P_GPK0_2_NF_CSn0 (0x3)
++#define S5P_GPK0_2_ONENAND_CSn0 (0x5)
++
++#define S5P_GPK0_3 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 3)
++#define S5P_GPK0_3_IN (0x0)
++#define S5P_GPK0_3_OUT (0x1)
++#define S5P_GPK0_3_SROM_CSn3 (0x2)
++#define S5P_GPK0_3_NF_CSn1 (0x3)
++#define S5P_GPK0_3_ONENAND_CSn1 (0x5)
++
++#define S5P_GPK0_4 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 4)
++#define S5P_GPK0_4_IN (0x0)
++#define S5P_GPK0_4_OUT (0x1)
++#define S5P_GPK0_4_SROM_CSn4 (0x2)
++#define S5P_GPK0_4_NF_CSn2 (0x3)
++#define S5P_GPK0_4_CF_CSn0 (0x4)
++
++#define S5P_GPK0_5 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 5)
++#define S5P_GPK0_5_IN (0x0)
++#define S5P_GPK0_5_OUT (0x1)
++#define S5P_GPK0_5_SROM_CSn5 (0x2)
++#define S5P_GPK0_5_NF_CSn3 (0x3)
++#define S5P_GPK0_5_CF_CSn1 (0x4)
++
++#define S5P_GPK0_6 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 6)
++#define S5P_GPK0_6_IN (0x0)
++#define S5P_GPK0_6_OUT (0x1)
++#define S5P_GPK0_6_EBI_OEn (0x2)
++
++#define S5P_GPK0_7 S5P_GPIO_NO(S5P_GPIO_BANK_K0, 7)
++#define S5P_GPK0_7_IN (0x0)
++#define S5P_GPK0_7_OUT (0x1)
++#define S5P_GPK0_7_EBI_WEn (0x2)
++
++/* GPK1 */
++#define S5P_GPK1_CON S5P_GPIO_REG(0x2C0)
++#define S5P_GPK1_DAT S5P_GPIO_REG(0x2C4)
++#define S5P_GPK1_PUD S5P_GPIO_REG(0x2C8)
++#define S5P_GPK1_DRV S5P_GPIO_REG(0x2CC)
++#define S5P_GPK1_CONPDN S5P_GPIO_REG(0x2D0)
++#define S5P_GPK1_PUDPDN S5P_GPIO_REG(0x2D4)
++
++#define S5P_GPK1_0 S5P_GPIO_NO(S5P_GPIO_BANK_K1, 0)
++#define S5P_GPK1_0_IN (0x0)
++#define S5P_GPK1_0_OUT (0x1)
++#define S5P_GPK1_0_EBI_BEn0 (0x2)
++
++#define S5P_GPK1_1 S5P_GPIO_NO(S5P_GPIO_BANK_K1, 1)
++#define S5P_GPK1_1_IN (0x0)
++#define S5P_GPK1_1_OUT (0x1)
++#define S5P_GPK1_1_EBI_BEn1 (0x2)
++
++#define S5P_GPK1_2 S5P_GPIO_NO(S5P_GPIO_BANK_K1, 2)
++#define S5P_GPK1_2_IN (0x0)
++#define S5P_GPK1_2_OUT (0x1)
++#define S5P_GPK1_2_SROM_WAITn (0x2)
++
++#define S5P_GPK1_3 S5P_GPIO_NO(S5P_GPIO_BANK_K1, 3)
++#define S5P_GPK1_3_IN (0x0)
++#define S5P_GPK1_3_OUT (0x1)
++#define S5P_GPK1_3_EBI_DATA_RDn (0x2)
++
++#define S5P_GPK1_4 S5P_GPIO_NO(S5P_GPIO_BANK_K1, 4)
++#define S5P_GPK1_4_IN (0x0)
++#define S5P_GPK1_4_OUT (0x1)
++#define S5P_GPK1_4_CF_OEn (0x2)
++
++#define S5P_GPK1_5 S5P_GPIO_NO(S5P_GPIO_BANK_K1, 5)
++#define S5P_GPK1_5_IN (0x0)
++#define S5P_GPK1_5_OUT (0x1)
++#define S5P_GPK1_5_CF_WEn (0x2)
++
++/* GPK2 */
++#define S5P_GPK2_CON S5P_GPIO_REG(0x2E0)
++#define S5P_GPK2_DAT S5P_GPIO_REG(0x2E4)
++#define S5P_GPK2_PUD S5P_GPIO_REG(0x2E8)
++#define S5P_GPK2_DRV S5P_GPIO_REG(0x2EC)
++#define S5P_GPK2_CONPDN S5P_GPIO_REG(0x2F0)
++#define S5P_GPK2_PUDPDN S5P_GPIO_REG(0x2F4)
++
++#define S5P_GPK2_0 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 0)
++#define S5P_GPK2_0_IN (0x0)
++#define S5P_GPK2_0_OUT (0x1)
++#define S5P_GPK2_0_NF_CLE (0x3)
++#define S5P_GPK2_0_ONENAND_ADDRVALID (0x5)
++
++#define S5P_GPK2_1 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 1)
++#define S5P_GPK2_1_IN (0x0)
++#define S5P_GPK2_1_OUT (0x1)
++#define S5P_GPK2_1_NF_ALE (0x3)
++#define S5P_GPK2_1_ONENAND_SMCLK (0x5)
++
++#define S5P_GPK2_2 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 2)
++#define S5P_GPK2_2_IN (0x0)
++#define S5P_GPK2_2_OUT (0x1)
++#define S5P_GPK2_2_NF_FWEn (0x3)
++#define S5P_GPK2_2_ONENAND_RPn (0x5)
++
++#define S5P_GPK2_3 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 3)
++#define S5P_GPK2_3_IN (0x0)
++#define S5P_GPK2_3_OUT (0x1)
++#define S5P_GPK2_3_NF_FREn (0x3)
++
++#define S5P_GPK2_4 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 4)
++#define S5P_GPK2_4_IN (0x0)
++#define S5P_GPK2_4_OUT (0x1)
++#define S5P_GPK2_4_NF_RnB0 (0x2)
++#define S5P_GPK2_4_ONENAND_INT0 (0x5)
++
++#define S5P_GPK2_5 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 5)
++#define S5P_GPK2_5_IN (0x0)
++#define S5P_GPK2_5_OUT (0x1)
++#define S5P_GPK2_5_NF_RnB1 (0x2)
++#define S5P_GPK2_5_ONENAND_INT1 (0x5)
++
++#define S5P_GPK2_6 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 6)
++#define S5P_GPK2_6_IN (0x0)
++#define S5P_GPK2_6_OUT (0x1)
++#define S5P_GPK2_6_NF_RnB2 (0x2)
++
++#define S5P_GPK2_7 S5P_GPIO_NO(S5P_GPIO_BANK_K2, 7)
++#define S5P_GPK2_7_IN (0x0)
++#define S5P_GPK2_7_OUT (0x1)
++#define S5P_GPK2_7_NF_RnB3 (0x2)
++
++/* GPK3 */
++#define S5P_GPK3_CON S5P_GPIO_REG(0x300)
++#define S5P_GPK3_DAT S5P_GPIO_REG(0x304)
++#define S5P_GPK3_PUD S5P_GPIO_REG(0x308)
++#define S5P_GPK3_DRV S5P_GPIO_REG(0x30C)
++#define S5P_GPK3_CONPDN S5P_GPIO_REG(0x310)
++#define S5P_GPK3_PUDPDN S5P_GPIO_REG(0x314)
++
++#define S5P_GPK3_0 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 0)
++#define S5P_GPK3_0_IN (0x0)
++#define S5P_GPK3_0_OUT (0x1)
++#define S5P_GPK3_0_CF_IORDY (0x2)
++
++#define S5P_GPK3_1 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 1)
++#define S5P_GPK3_1_IN (0x0)
++#define S5P_GPK3_1_OUT (0x1)
++#define S5P_GPK3_1_CF_INTRQ (0x2)
++
++#define S5P_GPK3_2 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 2)
++#define S5P_GPK3_2_IN (0x0)
++#define S5P_GPK3_2_OUT (0x1)
++#define S5P_GPK3_2_CF_RESET (0x2)
++
++#define S5P_GPK3_3 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 3)
++#define S5P_GPK3_3_IN (0x0)
++#define S5P_GPK3_3_OUT (0x1)
++#define S5P_GPK3_3_CF_INPACKn (0x2)
++
++#define S5P_GPK3_4 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 4)
++#define S5P_GPK3_4_IN (0x0)
++#define S5P_GPK3_4_OUT (0x1)
++#define S5P_GPK3_4_CF_REG (0x2)
++
++#define S5P_GPK3_5 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 5)
++#define S5P_GPK3_5_IN (0x0)
++#define S5P_GPK3_5_OUT (0x1)
++#define S5P_GPK3_5_CF_CDn (0x2)
++
++#define S5P_GPK3_6 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 6)
++#define S5P_GPK3_6_IN (0x0)
++#define S5P_GPK3_6_OUT (0x1)
++#define S5P_GPK3_6_CF_IORD_CFn (0x2)
++
++#define S5P_GPK3_7 S5P_GPIO_NO(S5P_GPIO_BANK_K3, 7)
++#define S5P_GPK3_7_IN (0x0)
++#define S5P_GPK3_7_OUT (0x1)
++#define S5P_GPK3_7_CF_IOWR_CFn (0x2)
++
++/* MP0_0 */
++#define S5P_MP0_0CON S5P_GPIO_REG(0x320)
++#define S5P_MP0_0DAT S5P_GPIO_REG(0x324)
++#define S5P_MP0_0PUD S5P_GPIO_REG(0x328)
++#define S5P_MP0_0DRV S5P_GPIO_REG(0x32C)
++#define S5P_MP0_0CONPDN S5P_GPIO_REG(0x330)
++#define S5P_MP0_0PUDPDN S5P_GPIO_REG(0x334)
++
++#define S5P_MP0_00 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 0)
++#define S5P_MP0_00_IN (0x0)
++#define S5P_MP0_00_OUT (0x1)
++#define S5P_MP0_00_EBI_ADDR0 (0x2)
++
++#define S5P_MP0_01 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 1)
++#define S5P_MP0_01_IN (0x0)
++#define S5P_MP0_01_OUT (0x1)
++#define S5P_MP0_01_EBI_ADDR1 (0x2)
++
++#define S5P_MP0_02 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 2)
++#define S5P_MP0_02_IN (0x0)
++#define S5P_MP0_02_OUT (0x1)
++#define S5P_MP0_02_EBI_ADDR2 (0x2)
++
++#define S5P_MP0_03 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 3)
++#define S5P_MP0_03_IN (0x0)
++#define S5P_MP0_03_OUT (0x1)
++#define S5P_MP0_03_EBI_ADDR3 (0x2)
++
++#define S5P_MP0_04 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 4)
++#define S5P_MP0_04_IN (0x0)
++#define S5P_MP0_04_OUT (0x1)
++#define S5P_MP0_04_EBI_ADDR4 (0x2)
++
++#define S5P_MP0_05 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 5)
++#define S5P_MP0_05_IN (0x0)
++#define S5P_MP0_05_OUT (0x1)
++#define S5P_MP0_05_EBI_ADDR5 (0x2)
++
++#define S5P_MP0_06 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 6)
++#define S5P_MP0_06_IN (0x0)
++#define S5P_MP0_06_OUT (0x1)
++#define S5P_MP0_06_EBI_ADDR6 (0x2)
++
++#define S5P_MP0_07 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_0, 7)
++#define S5P_MP0_07_IN (0x0)
++#define S5P_MP0_07_OUT (0x1)
++#define S5P_MP0_07_EBI_ADDR7 (0x2)
++
++/* MP0_1 */
++#define S5P_MP0_1CON S5P_GPIO_REG(0x340)
++#define S5P_MP0_1DAT S5P_GPIO_REG(0x344)
++#define S5P_MP0_1PUD S5P_GPIO_REG(0x348)
++#define S5P_MP0_1DRV S5P_GPIO_REG(0x34C)
++#define S5P_MP0_1CONPDN S5P_GPIO_REG(0x350)
++#define S5P_MP0_1PUDPDN S5P_GPIO_REG(0x354)
++
++#define S5P_MP0_10 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 0)
++#define S5P_MP0_10_IN (0x0)
++#define S5P_MP0_10_OUT (0x1)
++#define S5P_MP0_10_EBI_ADDR8 (0x2)
++
++#define S5P_MP0_11 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 1)
++#define S5P_MP0_11_IN (0x0)
++#define S5P_MP0_11_OUT (0x1)
++#define S5P_MP0_11_EBI_ADDR9 (0x2)
++
++#define S5P_MP0_12 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 2)
++#define S5P_MP0_12_IN (0x0)
++#define S5P_MP0_12_OUT (0x1)
++#define S5P_MP0_12_EBI_ADDR10 (0x2)
++
++#define S5P_MP0_13 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 3)
++#define S5P_MP0_13_IN (0x0)
++#define S5P_MP0_13_OUT (0x1)
++#define S5P_MP0_13_EBI_ADDR11 (0x2)
++
++#define S5P_MP0_14 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 4)
++#define S5P_MP0_14_IN (0x0)
++#define S5P_MP0_14_OUT (0x1)
++#define S5P_MP0_14_EBI_ADDR12 (0x2)
++
++#define S5P_MP0_15 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 5)
++#define S5P_MP0_15_IN (0x0)
++#define S5P_MP0_15_OUT (0x1)
++#define S5P_MP0_15_EBI_ADDR13 (0x2)
++
++#define S5P_MP0_16 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 6)
++#define S5P_MP0_16_IN (0x0)
++#define S5P_MP0_16_OUT (0x1)
++#define S5P_MP0_16_EBI_ADDR14 (0x2)
++
++#define S5P_MP0_17 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_1, 7)
++#define S5P_MP0_17_IN (0x0)
++#define S5P_MP0_17_OUT (0x1)
++#define S5P_MP0_17_EBI_ADDR15 (0x2)
++
++/* MP0_2 */
++#define S5P_MP0_2CON S5P_GPIO_REG(0x360)
++#define S5P_MP0_2DAT S5P_GPIO_REG(0x364)
++#define S5P_MP0_2PUD S5P_GPIO_REG(0x368)
++#define S5P_MP0_2DRV S5P_GPIO_REG(0x36C)
++#define S5P_MP0_2CONPDN S5P_GPIO_REG(0x370)
++#define S5P_MP0_2PUDPDN S5P_GPIO_REG(0x374)
++
++#define S5P_MP0_20 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 0)
++#define S5P_MP0_20_IN (0x0)
++#define S5P_MP0_20_OUT (0x1)
++#define S5P_MP0_20_EBI_ADDR16 (0x2)
++
++#define S5P_MP0_21 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 1)
++#define S5P_MP0_21_IN (0x0)
++#define S5P_MP0_21_OUT (0x1)
++#define S5P_MP0_21_EBI_ADDR17 (0x2)
++
++#define S5P_MP0_22 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 2)
++#define S5P_MP0_22_IN (0x0)
++#define S5P_MP0_22_OUT (0x1)
++#define S5P_MP0_22_EBI_ADDR18 (0x2)
++
++#define S5P_MP0_23 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 3)
++#define S5P_MP0_23_IN (0x0)
++#define S5P_MP0_23_OUT (0x1)
++#define S5P_MP0_23_EBI_ADDR19 (0x2)
++
++#define S5P_MP0_24 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 4)
++#define S5P_MP0_24_IN (0x0)
++#define S5P_MP0_24_OUT (0x1)
++#define S5P_MP0_24_EBI_ADDR20 (0x2)
++
++#define S5P_MP0_25 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 5)
++#define S5P_MP0_25_IN (0x0)
++#define S5P_MP0_25_OUT (0x1)
++#define S5P_MP0_25_EBI_DATA0 (0x2)
++
++#define S5P_MP0_26 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 6)
++#define S5P_MP0_26_IN (0x0)
++#define S5P_MP0_26_OUT (0x1)
++#define S5P_MP0_26_EBI_DATA1 (0x2)
++
++#define S5P_MP0_27 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_2, 7)
++#define S5P_MP0_27_IN (0x0)
++#define S5P_MP0_27_OUT (0x1)
++#define S5P_MP0_27_EBI_DATA2 (0x2)
++
++/* MP0_3 */
++#define S5P_MP0_3CON S5P_GPIO_REG(0x380)
++#define S5P_MP0_3DAT S5P_GPIO_REG(0x384)
++#define S5P_MP0_3PUD S5P_GPIO_REG(0x388)
++#define S5P_MP0_3DRV S5P_GPIO_REG(0x38C)
++#define S5P_MP0_3CONPDN S5P_GPIO_REG(0x390)
++#define S5P_MP0_3PUDPDN S5P_GPIO_REG(0x394)
++
++#define S5P_MP0_30 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 0)
++#define S5P_MP0_30_IN (0x0)
++#define S5P_MP0_30_OUT (0x1)
++#define S5P_MP0_30_EBI_DATA3 (0x2)
++
++#define S5P_MP0_31 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 1)
++#define S5P_MP0_31_IN (0x0)
++#define S5P_MP0_31_OUT (0x1)
++#define S5P_MP0_31_EBI_DATA4 (0x2)
++
++#define S5P_MP0_32 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 2)
++#define S5P_MP0_32_IN (0x0)
++#define S5P_MP0_32_OUT (0x1)
++#define S5P_MP0_32_EBI_DATA5 (0x2)
++
++#define S5P_MP0_33 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 3)
++#define S5P_MP0_33_IN (0x0)
++#define S5P_MP0_33_OUT (0x1)
++#define S5P_MP0_33_EBI_DATA6 (0x2)
++
++#define S5P_MP0_34 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 4)
++#define S5P_MP0_34_IN (0x0)
++#define S5P_MP0_34_OUT (0x1)
++#define S5P_MP0_34_EBI_DATA7 (0x2)
++
++#define S5P_MP0_35 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 5)
++#define S5P_MP0_35_IN (0x0)
++#define S5P_MP0_35_OUT (0x1)
++#define S5P_MP0_35_EBI_DATA8 (0x2)
++
++#define S5P_MP0_36 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 6)
++#define S5P_MP0_36_IN (0x0)
++#define S5P_MP0_36_OUT (0x1)
++#define S5P_MP0_36_EBI_DATA9 (0x2)
++
++#define S5P_MP0_37 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_3, 7)
++#define S5P_MP0_37_IN (0x0)
++#define S5P_MP0_37_OUT (0x1)
++#define S5P_MP0_37_EBI_DATA10 (0x2)
++
++/* MP0_4 */
++#define S5P_MP0_4CON S5P_GPIO_REG(0x3A0)
++#define S5P_MP0_4DAT S5P_GPIO_REG(0x3A4)
++#define S5P_MP0_4PUD S5P_GPIO_REG(0x3A8)
++#define S5P_MP0_4DRV S5P_GPIO_REG(0x3AC)
++#define S5P_MP0_4CONPDN S5P_GPIO_REG(0x3B0)
++#define S5P_MP0_4PUDPDN S5P_GPIO_REG(0x3B4)
++
++#define S5P_MP0_40 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_4, 0)
++#define S5P_MP0_40_IN (0x0)
++#define S5P_MP0_40_OUT (0x1)
++#define S5P_MP0_40_EBI_DATA11 (0x2)
++
++#define S5P_MP0_41 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_4, 1)
++#define S5P_MP0_41_IN (0x0)
++#define S5P_MP0_41_OUT (0x1)
++#define S5P_MP0_41_EBI_DATA12 (0x2)
++
++#define S5P_MP0_42 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_4, 2)
++#define S5P_MP0_42_IN (0x0)
++#define S5P_MP0_42_OUT (0x1)
++#define S5P_MP0_42_EBI_DATA13 (0x2)
++
++#define S5P_MP0_43 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_4, 3)
++#define S5P_MP0_43_IN (0x0)
++#define S5P_MP0_43_OUT (0x1)
++#define S5P_MP0_43_EBI_DATA14 (0x2)
++
++#define S5P_MP0_44 S5P_GPIO_NO(S5P_GPIO_BANK_MP0_4, 4)
++#define S5P_MP0_44_IN (0x0)
++#define S5P_MP0_44_OUT (0x1)
++#define S5P_MP0_44_EBI_DATA15 (0x2)
++
++/* MP1_0 */
++#define S5P_MP1_0PUD S5P_GPIO_REG(0x3C8)
++#define S5P_MP1_0DRV S5P_GPIO_REG(0x3CC)
++#define S5P_MP1_0CONPDN S5P_GPIO_REG(0x3D0)
++#define S5P_MP1_0PUDPDN S5P_GPIO_REG(0x3D4)
++
++/* MP1_1 */
++#define S5P_MP1_1PUD S5P_GPIO_REG(0x3E8)
++#define S5P_MP1_1DRV S5P_GPIO_REG(0x3EC)
++#define S5P_MP1_1CONPDN S5P_GPIO_REG(0x3F0)
++#define S5P_MP1_1PUDPDN S5P_GPIO_REG(0x3F4)
++
++/* MP1_2 */
++#define S5P_MP1_2PUD S5P_GPIO_REG(0x408)
++#define S5P_MP1_2DRV S5P_GPIO_REG(0x40C)
++#define S5P_MP1_2CONPDN S5P_GPIO_REG(0x410)
++#define S5P_MP1_2PUDPDN S5P_GPIO_REG(0x414)
++
++/* MP1_3 */
++#define S5P_MP1_3PUD S5P_GPIO_REG(0x428)
++#define S5P_MP1_3DRV S5P_GPIO_REG(0x42C)
++#define S5P_MP1_3CONPDN S5P_GPIO_REG(0x430)
++#define S5P_MP1_3PUDPDN S5P_GPIO_REG(0x434)
++
++/* MP1_4 */
++#define S5P_MP1_4PUD S5P_GPIO_REG(0x448)
++#define S5P_MP1_4DRV S5P_GPIO_REG(0x44C)
++#define S5P_MP1_4CONPDN S5P_GPIO_REG(0x450)
++#define S5P_MP1_4PUDPDN S5P_GPIO_REG(0x454)
++
++/* MP1_5 */
++#define S5P_MP1_5PUD S5P_GPIO_REG(0x468)
++#define S5P_MP1_5DRV S5P_GPIO_REG(0x46C)
++#define S5P_MP1_5CONPDN S5P_GPIO_REG(0x470)
++#define S5P_MP1_5PUDPDN S5P_GPIO_REG(0x474)
++
++/* MP1_6 */
++#define S5P_MP1_6PUD S5P_GPIO_REG(0x488)
++#define S5P_MP1_6DRV S5P_GPIO_REG(0x48C)
++#define S5P_MP1_6CONPDN S5P_GPIO_REG(0x490)
++#define S5P_MP1_6PUDPDN S5P_GPIO_REG(0x494)
++
++/* MP1_7*/
++#define S5P_MP1_7PUD S5P_GPIO_REG(0x4A8)
++#define S5P_MP1_7DRV S5P_GPIO_REG(0x4AC)
++#define S5P_MP1_7CONPDN S5P_GPIO_REG(0x4B0)
++#define S5P_MP1_7PUDPDN S5P_GPIO_REG(0x4B4)
++
++/* MP1_8*/
++#define S5P_MP1_8PUD S5P_GPIO_REG(0x4C8)
++#define S5P_MP1_8DRV S5P_GPIO_REG(0x4CC)
++#define S5P_MP1_8CONPDN S5P_GPIO_REG(0x4D0)
++#define S5P_MP1_8PUDPDN S5P_GPIO_REG(0x4D4)
++
++/* ETC0 */
++#define S5P_ETC0_PUD S5P_GPIO_REG(0x4E8)
++#define S5P_ETC0_DRV S5P_GPIO_REG(0x4EC)
++
++/* ETC1 */
++#define S5P_ETC1_PUD S5P_GPIO_REG(0x508)
++#define S5P_ETC1_DRV S5P_GPIO_REG(0x50C)
++
++/* ETC2 */
++#define S5P_ETC2_PUD S5P_GPIO_REG(0x528)
++#define S5P_ETC2_DRV S5P_GPIO_REG(0x52C)
++
++/* ETC3 */
++#define S5P_ETC3_PUD S5P_GPIO_REG(0x548)
++#define S5P_ETC3_DRV S5P_GPIO_REG(0x54C)
++
++/* ETC4 */
++#define S5P_ETC4_PUD S5P_GPIO_REG(0x568)
++#define S5P_ETC4_DRV S5P_GPIO_REG(0x56C)
++
++/* External Interrupt Control Registers */
++#define S5P_EXT_INT1_CON S5P_GPIO_REG(0x700)
++#define S5P_EXT_INT2_CON S5P_GPIO_REG(0x704)
++#define S5P_EXT_INT3_CON S5P_GPIO_REG(0x708)
++#define S5P_EXT_INT4_CON S5P_GPIO_REG(0x70C)
++#define S5P_EXT_INT5_CON S5P_GPIO_REG(0x710)
++#define S5P_EXT_INT6_CON S5P_GPIO_REG(0x714)
++#define S5P_EXT_INT7_CON S5P_GPIO_REG(0x718)
++#define S5P_EXT_INT8_CON S5P_GPIO_REG(0x71C)
++#define S5P_EXT_INT9_CON S5P_GPIO_REG(0x720)
++#define S5P_EXT_INT10_CON S5P_GPIO_REG(0x724)
++#define S5P_EXT_INT11_CON S5P_GPIO_REG(0x728)
++#define S5P_EXT_INT12_CON S5P_GPIO_REG(0x72C)
++#define S5P_EXT_INT13_CON S5P_GPIO_REG(0x730)
++#define S5P_EXT_INT14_CON S5P_GPIO_REG(0x734)
++#define S5P_EXT_INT15_CON S5P_GPIO_REG(0x738)
++#define S5P_EXT_INT20_CON S5P_GPIO_REG(0x73C)
++#define S5P_EXT_INT21_CON S5P_GPIO_REG(0x740)
++#define S5P_EXT_INT22_CON S5P_GPIO_REG(0x744)
++#define S5P_EXT_INT23_CON S5P_GPIO_REG(0x748)
++#define S5P_EXT_INT24_CON S5P_GPIO_REG(0x74C)
++#define S5P_EXT_INT25_CON S5P_GPIO_REG(0x750)
++#define S5P_EXT_INT1_FLTCON0 S5P_GPIO_REG(0x800)
++#define S5P_EXT_INT1_FLTCON1 S5P_GPIO_REG(0x804)
++#define S5P_EXT_INT2_FLTCON0 S5P_GPIO_REG(0x808)
++#define S5P_EXT_INT2_FLTCON1 S5P_GPIO_REG(0x80C)
++#define S5P_EXT_INT3_FLTCON0 S5P_GPIO_REG(0x810)
++#define S5P_EXT_INT3_FLTCON1 S5P_GPIO_REG(0x814)
++#define S5P_EXT_INT4_FLTCON0 S5P_GPIO_REG(0x818)
++#define S5P_EXT_INT4_FLTCON1 S5P_GPIO_REG(0x81C)
++#define S5P_EXT_INT5_FLTCON0 S5P_GPIO_REG(0x820)
++#define S5P_EXT_INT5_FLTCON1 S5P_GPIO_REG(0x824)
++#define S5P_EXT_INT6_FLTCON0 S5P_GPIO_REG(0x828)
++#define S5P_EXT_INT6_FLTCON1 S5P_GPIO_REG(0x82C)
++#define S5P_EXT_INT7_FLTCON0 S5P_GPIO_REG(0x830)
++#define S5P_EXT_INT7_FLTCON1 S5P_GPIO_REG(0x834)
++#define S5P_EXT_INT8_FLTCON0 S5P_GPIO_REG(0x838)
++#define S5P_EXT_INT8_FLTCON1 S5P_GPIO_REG(0x83C)
++#define S5P_EXT_INT9_FLTCON0 S5P_GPIO_REG(0x840)
++#define S5P_EXT_INT9_FLTCON1 S5P_GPIO_REG(0x844)
++#define S5P_EXT_INT10_FLTCON0 S5P_GPIO_REG(0x848)
++#define S5P_EXT_INT10_FLTCON1 S5P_GPIO_REG(0x84C)
++#define S5P_EXT_INT11_FLTCON0 S5P_GPIO_REG(0x850)
++#define S5P_EXT_INT11_FLTCON1 S5P_GPIO_REG(0x854)
++#define S5P_EXT_INT12_FLTCON0 S5P_GPIO_REG(0x858)
++#define S5P_EXT_INT12_FLTCON1 S5P_GPIO_REG(0x85C)
++#define S5P_EXT_INT13_FLTCON0 S5P_GPIO_REG(0x860)
++#define S5P_EXT_INT13_FLTCON1 S5P_GPIO_REG(0x864)
++#define S5P_EXT_INT14_FLTCON0 S5P_GPIO_REG(0x868)
++#define S5P_EXT_INT14_FLTCON1 S5P_GPIO_REG(0x86C)
++#define S5P_EXT_INT15_FLTCON0 S5P_GPIO_REG(0x870)
++#define S5P_EXT_INT15_FLTCON1 S5P_GPIO_REG(0x874)
++#define S5P_EXT_INT20_FLTCON0 S5P_GPIO_REG(0x878)
++#define S5P_EXT_INT20_FLTCON1 S5P_GPIO_REG(0x87C)
++#define S5P_EXT_INT21_FLTCON0 S5P_GPIO_REG(0x880)
++#define S5P_EXT_INT21_FLTCON1 S5P_GPIO_REG(0x884)
++#define S5P_EXT_INT22_FLTCON0 S5P_GPIO_REG(0x888)
++#define S5P_EXT_INT22_FLTCON1 S5P_GPIO_REG(0x88C)
++#define S5P_EXT_INT23_FLTCON0 S5P_GPIO_REG(0x890)
++#define S5P_EXT_INT23_FLTCON1 S5P_GPIO_REG(0x894)
++#define S5P_EXT_INT24_FLTCON0 S5P_GPIO_REG(0x898)
++#define S5P_EXT_INT24_FLTCON1 S5P_GPIO_REG(0x89C)
++#define S5P_EXT_INT25_FLTCON0 S5P_GPIO_REG(0x8A0)
++#define S5P_EXT_INT25_FLTCON1 S5P_GPIO_REG(0x8A4)
++#define S5P_EXT_INT1_MASK S5P_GPIO_REG(0x900)
++#define S5P_EXT_INT2_MASK S5P_GPIO_REG(0x904)
++#define S5P_EXT_INT3_MASK S5P_GPIO_REG(0x908)
++#define S5P_EXT_INT4_MASK S5P_GPIO_REG(0x90C)
++#define S5P_EXT_INT5_MASK S5P_GPIO_REG(0x910)
++#define S5P_EXT_INT6_MASK S5P_GPIO_REG(0x914)
++#define S5P_EXT_INT7_MASK S5P_GPIO_REG(0x918)
++#define S5P_EXT_INT8_MASK S5P_GPIO_REG(0x91C)
++#define S5P_EXT_INT9_MASK S5P_GPIO_REG(0x920)
++#define S5P_EXT_INT10_MASK S5P_GPIO_REG(0x924)
++#define S5P_EXT_INT11_MASK S5P_GPIO_REG(0x928)
++#define S5P_EXT_INT12_MASK S5P_GPIO_REG(0x92C)
++#define S5P_EXT_INT13_MASK S5P_GPIO_REG(0x930)
++#define S5P_EXT_INT14_MASK S5P_GPIO_REG(0x934)
++#define S5P_EXT_INT15_MASK S5P_GPIO_REG(0x938)
++#define S5P_EXT_INT20_MASK S5P_GPIO_REG(0x93C)
++#define S5P_EXT_INT21_MASK S5P_GPIO_REG(0x940)
++#define S5P_EXT_INT22_MASK S5P_GPIO_REG(0x944)
++#define S5P_EXT_INT23_MASK S5P_GPIO_REG(0x948)
++#define S5P_EXT_INT24_MASK S5P_GPIO_REG(0x94C)
++#define S5P_EXT_INT25_MASK S5P_GPIO_REG(0x950)
++#define S5P_EXT_INT1_PEND S5P_GPIO_REG(0xA00)
++#define S5P_EXT_INT2_PEND S5P_GPIO_REG(0xA04)
++#define S5P_EXT_INT3_PEND S5P_GPIO_REG(0xA08)
++#define S5P_EXT_INT4_PEND S5P_GPIO_REG(0xA0C)
++#define S5P_EXT_INT5_PEND S5P_GPIO_REG(0xA10)
++#define S5P_EXT_INT6_PEND S5P_GPIO_REG(0xA14)
++#define S5P_EXT_INT7_PEND S5P_GPIO_REG(0xA18)
++#define S5P_EXT_INT8_PEND S5P_GPIO_REG(0xA1C)
++#define S5P_EXT_INT9_PEND S5P_GPIO_REG(0xA20)
++#define S5P_EXT_INT10_PEND S5P_GPIO_REG(0xA24)
++#define S5P_EXT_INT11_PEND S5P_GPIO_REG(0xA28)
++#define S5P_EXT_INT12_PEND S5P_GPIO_REG(0xA2C)
++#define S5P_EXT_INT13_PEND S5P_GPIO_REG(0xA30)
++#define S5P_EXT_INT14_PEND S5P_GPIO_REG(0xA34)
++#define S5P_EXT_INT15_PEND S5P_GPIO_REG(0xA38)
++#define S5P_EXT_INT20_PEND S5P_GPIO_REG(0xA3C)
++#define S5P_EXT_INT21_PEND S5P_GPIO_REG(0xA40)
++#define S5P_EXT_INT22_PEND S5P_GPIO_REG(0xA44)
++#define S5P_EXT_INT23_PEND S5P_GPIO_REG(0xA48)
++#define S5P_EXT_INT24_PEND S5P_GPIO_REG(0xA4C)
++#define S5P_EXT_INT25_PEND S5P_GPIO_REG(0xA50)
++#define S5P_EXT_INT_GRPPRI S5P_GPIO_REG(0xB00)
++#define S5P_EXT_INT_PRIORITY S5P_GPIO_REG(0xB04)
++#define S5P_EXT_INT_SERVICE S5P_GPIO_REG(0xB08)
++#define S5P_EXT_INT_SERVICE_PEND S5P_GPIO_REG(0xB0C)
++#define S5P_EXT_INT_GRPFIXPRI S5P_GPIO_REG(0xB10)
++#define S5P_EXT_INT1_FIXPRI S5P_GPIO_REG(0xB14)
++#define S5P_EXT_INT2_FIXPRI S5P_GPIO_REG(0xB18)
++#define S5P_EXT_INT3_FIXPRI S5P_GPIO_REG(0xB1C)
++#define S5P_EXT_INT4_FIXPRI S5P_GPIO_REG(0xB20)
++#define S5P_EXT_INT5_FIXPRI S5P_GPIO_REG(0xB24)
++#define S5P_EXT_INT6_FIXPRI S5P_GPIO_REG(0xB28)
++#define S5P_EXT_INT7_FIXPRI S5P_GPIO_REG(0xB2C)
++#define S5P_EXT_INT8_FIXPRI S5P_GPIO_REG(0xB30)
++#define S5P_EXT_INT9_FIXPRI S5P_GPIO_REG(0xB34)
++#define S5P_EXT_INT10_FIXPRI S5P_GPIO_REG(0xB38)
++#define S5P_EXT_INT11_FIXPRI S5P_GPIO_REG(0xB3C)
++#define S5P_EXT_INT12_FIXPRI S5P_GPIO_REG(0xB40)
++#define S5P_EXT_INT13_FIXPRI S5P_GPIO_REG(0xB44)
++#define S5P_EXT_INT14_FIXPRI S5P_GPIO_REG(0xB48)
++#define S5P_EXT_INT15_FIXPRI S5P_GPIO_REG(0xB4C)
++#define S5P_EXT_INT20_FIXPRI S5P_GPIO_REG(0xB50)
++#define S5P_EXT_INT21_FIXPRI S5P_GPIO_REG(0xB54)
++#define S5P_EXT_INT22_FIXPRI S5P_GPIO_REG(0xB58)
++#define S5P_EXT_INT23_FIXPRI S5P_GPIO_REG(0xB5C)
++#define S5P_EXT_INT24_FIXPRI S5P_GPIO_REG(0xB60)
++#define S5P_EXT_INT25_FIXPRI S5P_GPIO_REG(0xB64)
++#define S5P_UHOST S5P_GPIO_REG(0xB68)
++#define S5P_PDNEN S5P_GPIO_REG(0xF80)
++
++#endif
++
+diff --git a/include/asm-arm/plat-s5p/regs-iis.h b/include/asm-arm/plat-s5p/regs-iis.h
+new file mode 100644
+index 0000000..785549d
+--- /dev/null
++++ b/include/asm-arm/plat-s5p/regs-iis.h
+@@ -0,0 +1,126 @@
++/* linux/include/asm-arm/arch-s3c64XX/regs-iis.h
++ *
++ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
++ * http://www.simtec.co.uk/products/SWLINUX/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C64XX IIS register definition
++*/
++
++#ifndef __ASM_ARCH_REGS_IIS_H
++#define __ASM_ARCH_REGS_IIS_H
++
++#define S3C64XX_IIS0REG(x) ((x) + S3C6410_PA_IIS_V40)
++
++//#define S3C_IIS0CON S3C64XX_IIS0REG(0x00)
++//#define S3C_IIS0MOD S3C64XX_IIS0REG(0x04)
++//#define S3C_IIS0FIC S3C64XX_IIS0REG(0x08)
++//#define S3C_IIS0PSR S3C64XX_IIS0REG(0x0C)
++//#define S3C_IIS0TXD S3C64XX_IIS0REG(0x10)
++//#define S3C_IIS0RXD S3C64XX_IIS0REG(0x14)
++
++#define S3C64XX_IIS0CON (0x00)
++#define S3C64XX_IIS0MOD (0x04)
++#define S3C64XX_IIS0FIC (0x08)
++#define S3C64XX_IIS0PSR (0x0C)
++#define S3C64XX_IIS0TXD (0x10)
++#define S3C64XX_IIS0RXD (0x14)
++
++#define S3C64XX_IISCON_LRINDEX (1<<8)
++#define S3C64XX_IISCON_TXFIFORDY (1<<7)
++#define S3C64XX_IISCON_RXFIFORDY (1<<6)
++#define S3C64XX_IISCON_TXDMAEN (1<<5)
++#define S3C64XX_IISCON_RXDMAEN (1<<4)
++#define S3C64XX_IISCON_TXIDLE (1<<3)
++#define S3C64XX_IISCON_RXIDLE (1<<2)
++#define S3C64XX_IISCON_PSCEN (1<<1)
++#define S3C64XX_IISCON_IISEN (1<<0)
++
++//#define S3C64XX_IISMOD_MPLL (1<<9)
++#define S3C64XX_IISMOD_MPLL (0x01<<10)
++#define S3C64XX_IISMOD_SLAVE (1<<8)
++#define S3C64XX_IISMOD_NOXFER (0<<6)
++#define S3C64XX_IISMOD_RXMODE (1<<6)
++#define S3C64XX_IISMOD_TXMODE (2<<6)
++#define S3C64XX_IISMOD_TXRXMODE (3<<6)
++#define S3C64XX_IISMOD_LR_LLOW (0<<5)
++#define S3C64XX_IISMOD_LR_RLOW (1<<5)
++#define S3C64XX_IISMOD_IIS (0<<4)
++#define S3C64XX_IISMOD_MSB (1<<4)
++#define S3C64XX_IISMOD_8BIT (0<<3)
++#define S3C64XX_IISMOD_16BIT (1<<3)
++#define S3C64XX_IISMOD_BITMASK (1<<3)
++#define S3C64XX_IISMOD_256FS (0<<2)
++#define S3C64XX_IISMOD_384FS (1<<2)
++#define S3C64XX_IISMOD_16FS (0<<0)
++#define S3C64XX_IISMOD_32FS (1<<0)
++#define S3C64XX_IISMOD_48FS (2<<0)
++#define S3C64XX_IISMOD_FS_MASK (3<<0)
++
++#define S3C64XX_IIS0MOD_DCE_MASK (0x3<<16)
++#define S3C64XX_IIS0MOD_DCE_SD2 (0x1<<17)
++#define S3C64XX_IIS0MOD_DCE_SD1 (0x1<<16)
++#define S3C64XX_IIS0MOD_BLC_MASK (0x3<<13)
++#define S3C64XX_IIS0MOD_BLC_16BIT (0x0<<13)
++#define S3C64XX_IIS0MOD_BLC_08BIT (0x1<<13)
++#define S3C64XX_IIS0MOD_BLC_24BIT (0x2<<13)
++#define S3C64XX_IIS0MOD_CLK_MASK (0x7<<10)
++#define S3C64XX_IIS0MOD_INTERNAL_CLK (0x0<<12)
++#define S3C64XX_IIS0MOD_EXTERNAL_CLK (0x1<<12)
++#define S3C64XX_IIS0MOD_IMS_INTERNAL_MASTER (0x0<<10)
++#define S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER (0x1<<10)
++#define S3C64XX_IIS0MOD_IMS_SLAVE (0x2<<10)
++#define S3C64XX_IIS0MOD_MODE_MASK (0x3<<8)
++#define S3C64XX_IIS0MOD_TXMODE (0x0<<8)
++#define S3C64XX_IIS0MOD_RXMODE (0x1<<8)
++#define S3C64XX_IIS0MOD_TXRXMODE (0x2<<8)
++#define S3C64XX_IIS0MOD_FM_MASK (0x3<<5)
++#define S3C64XX_IIS0MOD_IIS (0x0<<5)
++#define S3C64XX_IIS0MOD_MSB (0x1<<5)
++#define S3C64XX_IIS0MOD_LSB (0x2<<5)
++#define S3C64XX_IIS0MOD_FS_MASK (0x3<<3)
++#define S3C64XX_IIS0MOD_768FS (0x3<<3)
++#define S3C64XX_IIS0MOD_384FS (0x2<<3)
++#define S3C64XX_IIS0MOD_512FS (0x1<<3)
++#define S3C64XX_IIS0MOD_256FS (0x0<<3)
++#define S3C64XX_IIS0MOD_BFS_MASK (0x3<<1)
++#define S3C64XX_IIS0MOD_48FS (0x1<<1)
++#define S3C64XX_IIS0MOD_32FS (0x0<<1)
++
++#define S3C64XX_IISPSR (0x08)
++#define S3C64XX_IISPSR_INTMASK (31<<5)
++#define S3C64XX_IISPSR_INTSHIFT (5)
++#define S3C64XX_IISPSR_EXTMASK (31<<0)
++#define S3C64XX_IISPSR_EXTSHFIT (0)
++
++#define S3C64XX_IISFCON (0x0c)
++
++#define S3C64XX_IISFCON_TXDMA (1<<15)
++#define S3C64XX_IISFCON_RXDMA (1<<14)
++#define S3C64XX_IISFCON_TXENABLE (1<<13)
++#define S3C64XX_IISFCON_RXENABLE (1<<12)
++#define S3C64XX_IISFCON_TXMASK (0x3f << 6)
++#define S3C64XX_IISFCON_TXSHIFT (6)
++#define S3C64XX_IISFCON_RXMASK (0x3f)
++#define S3C64XX_IISFCON_RXSHIFT (0)
++
++#define S3C64XX_IISFIFO (0x10)
++#define S3C64XX_IISFIFORX (0x14)
++
++#define S3C64XX_IIS0CON_I2SACTIVE (0x1<<0)
++#define S3C64XX_IIS0CON_RXDMACTIVE (0x1<<1)
++#define S3C64XX_IIS0CON_I2SACTIVE (0x1<<0)
++#define S3C64XX_IIS0CON_TXDMACTIVE (0x1<<2)
++
++#define S3C64XX_IIS_TX_FLUSH (0x1<<15)
++#define S3C64XX_IIS_RX_FLUSH (0x1<<7)
++
++#define S3C64XX_IISCON_FTXURINTEN (0x1<<16)
++
++#define S3C64XX_IIS0MOD_24BIT (0x2<<13)
++#define S3C64XX_IIS0MOD_8BIT (0x1<<13)
++#define S3C64XX_IIS0MOD_16BIT (0x0<<13)
++#endif /* __ASM_ARCH_REGS_IIS_H */
+diff --git a/include/asm-arm/plat-s5p/s5pc100.h b/include/asm-arm/plat-s5p/s5pc100.h
+new file mode 100644
+index 0000000..359d223
+--- /dev/null
++++ b/include/asm-arm/plat-s5p/s5pc100.h
+@@ -0,0 +1,31 @@
++/* arch/arm/plat-s5pc100/s3c64.h
++ *
++ * Copyright (c) 2004-2005 Samsung Electronics
++ *
++ *
++ * Header file for s5pc100 cpu support
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Modifications:
++*/
++
++#if defined(CONFIG_CPU_S5PC100)
++
++extern int s5pc100_init(void);
++
++extern void s5pc100_map_io(struct map_desc *mach_desc, int size);
++
++extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
++
++extern void s5pc100_init_clocks(int xtal);
++
++#else
++#define s5pc100_init NULL
++#define s5pc100_map_io NULL
++#define s5pc100_init_uarts NULL
++#define s5pc100_init_clocks NULL
++#endif
++
+diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
+index e18017d..29b81de 100644
+--- a/include/linux/i2c-id.h
++++ b/include/linux/i2c-id.h
+@@ -125,6 +125,7 @@
+ #define I2C_DRIVERID_LM4857 92 /* LM4857 Audio Amplifier */
+ #define I2C_DRIVERID_VP27SMPX 93 /* Panasonic VP27s tuner internal MPX */
+ #define I2C_DRIVERID_CS4270 94 /* Cirrus Logic 4270 audio codec */
++#define I2C_DRIVERID_WM8580 95 /* Wolfson WM8580 audio codec */
+
+ #define I2C_DRIVERID_I2CDEV 900
+ #define I2C_DRIVERID_ARP 902 /* SMBus ARP Client */
+@@ -167,7 +168,12 @@
+ #define I2C_DRIVERID_FSCHER 1046
+ #define I2C_DRIVERID_W83L785TS 1047
+ #define I2C_DRIVERID_OV7670 1048 /* Omnivision 7670 camera */
+-
++#define I2C_DRIVERID_S5K3XA 1500 /* Samsung MobileAP I2C adapter */
++#define I2C_DRIVERID_S5K_53BEA 1501 /* Samsung MobileAP I2C adapter */
++#define I2C_DRIVERID_S5K3AA 1502 /* Samsung MobileAP I2C adapter */
++#define I2C_DRIVERID_S5K3BA 1503 /* Samsung MobileAP I2C adapter */
++#define I2C_DRIVERID_S5K4XA 1504 /* Samsung MobileAP I2C adapter */
++#define I2C_DRIVERID_MT9P012 1505 /* Samsung MobileAP I2C adapter */
+ /*
+ * ---- Adapter types ----------------------------------------------------
+ */
+diff --git a/include/linux/i2c.h b/include/linux/i2c.h
+index a100c9f..a65e090 100644
+--- a/include/linux/i2c.h
++++ b/include/linux/i2c.h
+@@ -182,6 +182,7 @@ struct i2c_client {
+ char driver_name[KOBJ_NAME_LEN];
+ struct list_head list;
+ struct completion released;
++ void * data;
+ };
+ #define to_i2c_client(d) container_of(d, struct i2c_client, dev)
+
+diff --git a/include/linux/ide.h b/include/linux/ide.h
+index 9a6a41e..7ea0ddc 100644
+--- a/include/linux/ide.h
++++ b/include/linux/ide.h
+@@ -202,7 +202,7 @@ enum { ide_unknown, ide_generic, ide_pci,
+ ide_rz1000, ide_trm290,
+ ide_cmd646, ide_cy82c693, ide_4drives,
+ ide_pmac, ide_etrax100, ide_acorn,
+- ide_au1xxx, ide_forced
++ ide_au1xxx, ide_s3c, ide_forced
+ };
+
+ typedef u8 hwif_chipset_t;
+@@ -659,6 +659,7 @@ typedef struct hwif_s {
+ unsigned long sata_scr[SATA_NR_PORTS];
+ unsigned long sata_misc[SATA_NR_PORTS];
+
++ hw_regs_t hw; /* Hardware info */
+ ide_drive_t drives[MAX_DRIVES]; /* drive info */
+
+ u8 major; /* our major number */
+@@ -714,6 +715,10 @@ typedef struct hwif_s {
+ u8 (*udma_filter)(ide_drive_t *);
+
+ void (*fixup)(struct hwif_s *);
++
++#ifdef CONFIG_IDE_HOOK_IRQ
++ int (*ide_irq_hook)(void *);
++#endif
+
+ void (*ata_input_data)(ide_drive_t *, void *, u32);
+ void (*ata_output_data)(ide_drive_t *, void *, u32);
+diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
+index 2306920..fe4b40e 100644
+--- a/include/linux/interrupt.h
++++ b/include/linux/interrupt.h
+@@ -55,6 +55,22 @@
+ #define IRQF_NOBALANCING 0x00000800
+ #define IRQF_IRQPOLL 0x00001000
+
++/*
++ * Migration helpers. Scheduled for removal in 1/2007
++ * Do not use for new code !
++ */
++#define SA_INTERRUPT IRQF_DISABLED
++#define SA_SAMPLE_RANDOM IRQF_SAMPLE_RANDOM
++#define SA_SHIRQ IRQF_SHARED
++#define SA_PROBEIRQ IRQF_PROBE_SHARED
++#define SA_PERCPU IRQF_PERCPU
++
++#define SA_TRIGGER_LOW IRQF_TRIGGER_LOW
++#define SA_TRIGGER_HIGH IRQF_TRIGGER_HIGH
++#define SA_TRIGGER_FALLING IRQF_TRIGGER_FALLING
++#define SA_TRIGGER_RISING IRQF_TRIGGER_RISING
++#define SA_TRIGGER_MASK IRQF_TRIGGER_MASK
++
+ typedef irqreturn_t (*irq_handler_t)(int, void *);
+
+ struct irqaction {
+@@ -326,7 +342,7 @@ static inline int tasklet_trylock(struct tasklet_struct *t)
+
+ static inline void tasklet_unlock(struct tasklet_struct *t)
+ {
+- smp_mb__before_clear_bit();
++ smp_mb__before_clear_bit();
+ clear_bit(TASKLET_STATE_RUN, &(t)->state);
+ }
+
+@@ -415,7 +431,7 @@ extern void tasklet_init(struct tasklet_struct *t,
+ * if more than one irq occurred.
+ */
+
+-#if defined(CONFIG_GENERIC_HARDIRQS) && !defined(CONFIG_GENERIC_IRQ_PROBE)
++#if defined(CONFIG_GENERIC_HARDIRQS) && !defined(CONFIG_GENERIC_IRQ_PROBE)
+ static inline unsigned long probe_irq_on(void)
+ {
+ return 0;
+diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
+index 0d508ac..218f7b1 100644
+--- a/include/linux/mmc/card.h
++++ b/include/linux/mmc/card.h
+@@ -89,6 +89,7 @@ struct mmc_card {
+ #define MMC_TYPE_MMC 0 /* MMC card */
+ #define MMC_TYPE_SD 1 /* SD card */
+ #define MMC_TYPE_SDIO 2 /* SDIO card */
++
+ unsigned int state; /* (our) card state */
+ #define MMC_STATE_PRESENT (1<<0) /* present in sysfs */
+ #define MMC_STATE_READONLY (1<<1) /* card is read-only */
+diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
+index 7ab962f..7ab2bde 100644
+--- a/include/linux/mmc/host.h
++++ b/include/linux/mmc/host.h
+@@ -41,6 +41,7 @@ struct mmc_ios {
+
+ #define MMC_BUS_WIDTH_1 0
+ #define MMC_BUS_WIDTH_4 2
++#define MMC_BUS_WIDTH_8 3
+
+ unsigned char timing; /* timing specification used */
+
+@@ -94,6 +95,7 @@ struct mmc_host {
+ #define MMC_CAP_SD_HIGHSPEED (1 << 3) /* Can do SD high-speed timing */
+ #define MMC_CAP_SDIO_IRQ (1 << 4) /* Can signal pending SDIO IRQs */
+ #define MMC_CAP_SPI (1 << 5) /* Talks only SPI protocols */
++#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
+
+ /* host specific block data */
+ unsigned int max_seg_size; /* see blk_queue_max_segment_size */
+diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
+index 4c4522a..0343c5b 100644
+--- a/include/linux/mmzone.h
++++ b/include/linux/mmzone.h
+@@ -20,7 +20,8 @@
+
+ /* Free memory management - zoned buddy allocator. */
+ #ifndef CONFIG_FORCE_MAX_ZONEORDER
+-#define MAX_ORDER 11
++//#define MAX_ORDER 11
++#define MAX_ORDER 12
+ #else
+ #define MAX_ORDER CONFIG_FORCE_MAX_ZONEORDER
+ #endif
+diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
+index 6169438..a7304c3 100644
+--- a/include/linux/usb/ch9.h
++++ b/include/linux/usb/ch9.h
+@@ -87,6 +87,7 @@
+ #define USB_REQ_GET_INTERFACE 0x0A
+ #define USB_REQ_SET_INTERFACE 0x0B
+ #define USB_REQ_SYNCH_FRAME 0x0C
++#define USB_REQ_GET_MAX_LUN 0xFE
+
+ #define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */
+ #define USB_REQ_GET_ENCRYPTION 0x0E
+diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
+index 2b1ae8e..bc05a54 100644
+--- a/include/sound/soc-dapm.h
++++ b/include/sound/soc-dapm.h
+@@ -150,6 +150,15 @@
+ .put = snd_soc_dapm_put_enum_double, \
+ .private_value = (unsigned long)&xenum }
+
++#define SOC_DAPM_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
++ .info = snd_soc_info_volsw, \
++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\
++ .tlv.p = (tlv_array), \
++ .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \
++ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
++
++
+ /* dapm stream operations */
+ #define SND_SOC_DAPM_STREAM_NOP 0x0
+ #define SND_SOC_DAPM_STREAM_START 0x1
+diff --git a/include/sound/soc.h b/include/sound/soc.h
+index f47ef1f..a9df0fe 100644
+--- a/include/sound/soc.h
++++ b/include/sound/soc.h
+@@ -77,6 +77,13 @@
+ .get = xhandler_get, .put = xhandler_put, \
+ .private_value = (unsigned long)&xenum }
+
++#define SOC_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\
++ .tlv.p = (tlv_array), \
++ .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
++ .put = snd_soc_put_volsw, \
++ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
+ /*
+ * Digital Audio Interface (DAI) types
+ */
+diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig
+index 8e186c6..e98b5ce 100644
+--- a/kernel/power/Kconfig
++++ b/kernel/power/Kconfig
+@@ -195,3 +195,16 @@ config APM_EMULATION
+ random kernel OOPSes or reboots that don't seem to be related to
+ anything, try disabling/enabling this option (or disabling/enabling
+ APM in your BIOS).
++
++menu "DVFS support"
++
++config S3C64XX_DVFS
++ tristate "Support for DVFS on SMDK64xx Board"
++ depends on CPU_S3C6400 || CPU_S3C6410
++
++config S3C24XX_DVFS
++ tristate "Support for DVFS on SMDK64xx Board"
++ depends on CPU_S3C2450 || CPU_S3C2416
++
++endmenu
++
+diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
+index 97b2552..07f949c 100644
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -6,7 +6,8 @@ menu "System on Chip audio support"
+ depends on SND!=n
+
+ config SND_SOC_AC97_BUS
+- bool
++ #bool
++ tristate
+
+ config SND_SOC
+ tristate "ALSA for SoC audio support"
+@@ -27,7 +28,8 @@ config SND_SOC
+ source "sound/soc/at91/Kconfig"
+ source "sound/soc/pxa/Kconfig"
+ source "sound/soc/s3c24xx/Kconfig"
+-source "sound/soc/sh/Kconfig"
++source "sound/soc/s3c64xx/Kconfig"
++#source "sound/soc/sh/Kconfig"
+
+ # Supported codecs
+ source "sound/soc/codecs/Kconfig"
+diff --git a/sound/soc/Makefile b/sound/soc/Makefile
+index 3041403..05056d5 100644
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -1,4 +1,4 @@
+ snd-soc-core-objs := soc-core.o soc-dapm.o
+
+ obj-$(CONFIG_SND_SOC) += snd-soc-core.o
+-obj-$(CONFIG_SND_SOC) += codecs/ at91/ pxa/ s3c24xx/ sh/
++obj-$(CONFIG_SND_SOC) += codecs/ at91/ pxa/ s3c24xx/ s3c64xx/ sh/
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 7824880..7be7510 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -2,6 +2,10 @@ config SND_SOC_AC97_CODEC
+ tristate
+ depends on SND_SOC
+
++config SND_SOC_WM8580
++ tristate
++ depends on SND_SOC
++
+ config SND_SOC_WM8731
+ tristate
+ depends on SND_SOC
+@@ -13,11 +17,19 @@ config SND_SOC_WM8750
+ config SND_SOC_WM8753
+ tristate
+ depends on SND_SOC
++
++config SND_SOC_WM8990
++ tristate
++ depends on SND_SOC
+
+ config SND_SOC_WM9712
+ tristate
+ depends on SND_SOC
+
++config SND_SOC_WM9713
++ tristate
++ depends on SND_SOC
++
+ # Cirrus Logic CS4270 Codec
+ config SND_SOC_CS4270
+ tristate
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index 7ad78e3..ca67a02 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -1,13 +1,42 @@
+ snd-soc-ac97-objs := ac97.o
++snd-soc-wm8580-objs := wm8580.o
+ snd-soc-wm8731-objs := wm8731.o
+ snd-soc-wm8750-objs := wm8750.o
+ snd-soc-wm8753-objs := wm8753.o
++snd-soc-wm8772-objs := wm8772.o
++snd-soc-wm8900-objs := wm8900.o
++snd-soc-wm8950-objs := wm8950.o
++snd-soc-wm8951-objs := wm8951.o
++snd-soc-wm8956-objs := wm8956.o
++snd-soc-wm8960-objs := wm8960.o
++snd-soc-wm8971-objs := wm8971.o
++snd-soc-wm8974-objs := wm8974.o
++snd-soc-wm8976-objs := wm8976.o
++snd-soc-wm8978-objs := wm8978.o
++snd-soc-wm8980-objs := wm8980.o
++snd-soc-wm8990-objs := wm8990.o
++snd-soc-wm8991-objs := wm8991.o
++snd-soc-wm9713-objs := wm9713.o
+ snd-soc-wm9712-objs := wm9712.o
+ snd-soc-cs4270-objs := cs4270.o
+
+ obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o
++obj-$(CONFIG_SND_SOC_WM8580) += snd-soc-wm8580.o
+ obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o
+ obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o
+ obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o
++obj-$(CONFIG_SND_SOC_WM8772) += snd-soc-wm8772.o
++obj-$(CONFIG_SND_SOC_WM8950) += snd-soc-wm8950.o
++obj-$(CONFIG_SND_SOC_WM8951) += snd-soc-wm8951.o
++obj-$(CONFIG_SND_SOC_WM8956) += snd-soc-wm8956.o
++obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o
++obj-$(CONFIG_SND_SOC_WM8971) += snd-soc-wm8971.o
++obj-$(CONFIG_SND_SOC_WM8974) += snd-soc-wm8974.o
++obj-$(CONFIG_SND_SOC_WM8976) += snd-soc-wm8976.o
++obj-$(CONFIG_SND_SOC_WM8978) += snd-soc-wm8978.o
++obj-$(CONFIG_SND_SOC_WM8980) += snd-soc-wm8980.o
++obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
++obj-$(CONFIG_SND_SOC_WM8991) += snd-soc-wm8991.o
+ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
++obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
+ obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
+diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
+new file mode 100644
+index 0000000..f50cb46
+--- /dev/null
++++ b/sound/soc/codecs/wm8580.c
+@@ -0,0 +1,963 @@
++/*
++ * wm8580.c -- WM8580 ALSA Soc Audio driver
++ *
++ * Copyright 2008 Wolfson Microelectronics PLC.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Notes:
++ * The WM8580 is a multichannel codec with S/PDIF support, featuring six
++ * DAC channels and two ADC channels.
++ *
++ * Currently only the primary audio interface is supported - S/PDIF and
++ * the secondary audio interfaces are not.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++#include <sound/initval.h>
++#include <asm/div64.h>
++
++#include "wm8580.h"
++
++#define AUDIO_NAME "wm8580"
++#define WM8580_VERSION "0.1"
++
++/*
++ * Debug
++ */
++
++#define WM8580_DEBUG 0
++
++#ifdef WM8580_DEBUG
++#define dbg(format, arg...) \
++ printk(KERN_DEBUG AUDIO_NAME ": " format , ## arg)
++#else
++#define dbg(format, arg...) do {} while (0)
++#endif
++#define err(format, arg...) \
++ printk(KERN_ERR AUDIO_NAME ": " format , ## arg)
++#define info(format, arg...) \
++ printk(KERN_INFO AUDIO_NAME ": " format , ## arg)
++#define warn(format, arg...) \
++ printk(KERN_WARNING AUDIO_NAME ": " format , ## arg)
++
++struct pll_state {
++ unsigned int in;
++ unsigned int out;
++};
++
++/* codec private data */
++struct wm8580_priv {
++ struct pll_state a;
++ struct pll_state b;
++};
++
++/*
++ * wm8580 register cache
++ * We can't read the WM8580 register space when we
++ * are using 2 wire for device control, so we cache them instead.
++ */
++static const u16 wm8580_reg[] = {
++ 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
++ 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
++ 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
++ 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
++ 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
++ 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
++ 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
++ 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
++ 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
++ 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
++ 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
++ 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
++ 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
++ 0x0000, 0x0000 /*R53*/
++};
++
++/*
++ * read wm8580 register cache
++ */
++static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec *codec,
++ unsigned int reg)
++{
++ u16 *cache = codec->reg_cache;
++ BUG_ON(reg > ARRAY_SIZE(wm8580_reg));
++ return cache[reg];
++}
++
++/*
++ * write wm8580 register cache
++ */
++static inline void wm8580_write_reg_cache(struct snd_soc_codec *codec,
++ unsigned int reg, unsigned int value)
++{
++ u16 *cache = codec->reg_cache;
++
++ cache[reg] = value;
++}
++
++/*
++ * write to the WM8580 register space
++ */
++static int wm8580_write(struct snd_soc_codec *codec, unsigned int reg,
++ unsigned int value)
++{
++// printk("%s,%d : reg : 0x%x, value : 0x%x\n",__FUNCTION__,__LINE__,reg,value);
++ u8 data[2];
++
++ BUG_ON(reg > ARRAY_SIZE(wm8580_reg));
++
++ /* Registers are 9 bits wide */
++ value &= 0x1ff;
++
++ switch (reg) {
++ case WM8580_RESET:
++ /* Uncached */
++ break;
++ default:
++ if (value == wm8580_read_reg_cache(codec, reg))
++ return 0;
++ }
++
++ /* data is
++ * D15..D9 WM8580 register offset
++ * D8...D0 register data
++ */
++ data[0] = (reg << 1) | ((value >> 8) & 0x0001);
++ data[1] = value & 0x00ff;
++
++ wm8580_write_reg_cache(codec, reg, value);
++ if (codec->hw_write(codec->control_data, data, 2) == 2)
++ return 0;
++ else
++ return -EIO;
++}
++
++static inline unsigned int wm8580_read(struct snd_soc_codec *codec,
++ unsigned int reg)
++{
++ switch (reg) {
++ default:
++ return wm8580_read_reg_cache(codec, reg);
++ }
++}
++
++static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
++
++static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++ int reg = kcontrol->private_value & 0xff;
++ int ret;
++ u16 val;
++
++ /* Clear the register cache so we write without VU set */
++ wm8580_write_reg_cache(codec, reg, 0);
++
++ ret = snd_soc_put_volsw(kcontrol, ucontrol);
++ if (ret < 0)
++ return ret;
++
++ /* Now write again with the volume update bit set */
++ val = wm8580_read_reg_cache(codec, reg);
++ return wm8580_write(codec, reg, val | 0x0100);
++}
++
++#define SOC_WM8580_OUT_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\
++ .tlv.p = (tlv_array), \
++ .info = snd_soc_info_volsw, \
++ .get = snd_soc_get_volsw, .put = wm8580_out_vu, \
++ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
++
++static const struct snd_kcontrol_new wm8580_snd_controls[] = {
++SOC_WM8580_OUT_SINGLE_R_TLV("Left DAC1 Playback Volume",
++ WM8580_DIGITAL_ATTENUATION_DACL1,
++ 0, 0xff, 0, dac_tlv),
++SOC_WM8580_OUT_SINGLE_R_TLV("Right DAC1 Playback Volume",
++ WM8580_DIGITAL_ATTENUATION_DACR1,
++ 0, 0xff, 0, dac_tlv),
++SOC_WM8580_OUT_SINGLE_R_TLV("Left DAC2 Playback Volume",
++ WM8580_DIGITAL_ATTENUATION_DACL2,
++ 0, 0xff, 0, dac_tlv),
++SOC_WM8580_OUT_SINGLE_R_TLV("Right DAC2 Playback Volume",
++ WM8580_DIGITAL_ATTENUATION_DACR2,
++ 0, 0xff, 0, dac_tlv),
++SOC_WM8580_OUT_SINGLE_R_TLV("Left DAC3 Playback Volume",
++ WM8580_DIGITAL_ATTENUATION_DACL3,
++ 0, 0xff, 0, dac_tlv),
++SOC_WM8580_OUT_SINGLE_R_TLV("Right DAC3 Playback Volume",
++ WM8580_DIGITAL_ATTENUATION_DACR3,
++ 0, 0xff, 0, dac_tlv),
++
++SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
++SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
++SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
++
++SOC_SINGLE("DAC1 Left Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 0),
++SOC_SINGLE("DAC1 Right Invert Switch", WM8580_DAC_CONTROL4, 1, 1, 0),
++SOC_SINGLE("DAC2 Left Invert Switch", WM8580_DAC_CONTROL4, 2, 1, 0),
++SOC_SINGLE("DAC2 Right Invert Switch", WM8580_DAC_CONTROL4, 3, 1, 0),
++SOC_SINGLE("DAC3 Left Invert Switch", WM8580_DAC_CONTROL4, 4, 1, 0),
++SOC_SINGLE("DAC3 Right Invert Switch", WM8580_DAC_CONTROL4, 5, 1, 0),
++
++SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
++SOC_SINGLE("DAC1 Mute Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
++SOC_SINGLE("DAC2 Mute Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
++SOC_SINGLE("DAC3 Mute Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
++
++SOC_SINGLE("ADCL Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 0),
++SOC_SINGLE("ADCR Mute Switch", WM8580_ADC_CONTROL1, 1, 1, 0),
++SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
++};
++
++/* Add non-DAPM controls */
++static int wm8580_add_controls(struct snd_soc_codec *codec)
++{
++ int err, i;
++
++ for (i = 0; i < ARRAY_SIZE(wm8580_snd_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm8580_snd_controls[i],
++ codec, NULL));
++ if (err < 0)
++ return err;
++ }
++ return 0;
++}
++static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
++SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
++SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
++SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
++
++SND_SOC_DAPM_OUTPUT("VOUT1L"),
++SND_SOC_DAPM_OUTPUT("VOUT1R"),
++SND_SOC_DAPM_OUTPUT("VOUT2L"),
++SND_SOC_DAPM_OUTPUT("VOUT2R"),
++SND_SOC_DAPM_OUTPUT("VOUT3L"),
++SND_SOC_DAPM_OUTPUT("VOUT3R"),
++
++SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
++
++SND_SOC_DAPM_INPUT("AINL"),
++SND_SOC_DAPM_INPUT("AINR"),
++};
++
++static const char *audio_map[][3] = {
++ { "VOUT1L", NULL, "DAC1" },
++ { "VOUT1R", NULL, "DAC1" },
++
++ { "VOUT2L", NULL, "DAC2" },
++ { "VOUT2R", NULL, "DAC2" },
++
++ { "VOUT3L", NULL, "DAC3" },
++ { "VOUT3R", NULL, "DAC3" },
++
++ { "ADC", NULL, "AINL" },
++ { "ADC", NULL, "AINR" },
++
++ { NULL, NULL, NULL }
++};
++
++static int wm8580_add_widgets(struct snd_soc_codec *codec)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(wm8580_dapm_widgets); i++)
++ snd_soc_dapm_new_control(codec, &wm8580_dapm_widgets[i]);
++
++ for (i = 0; audio_map[i][0] != NULL; i++)
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++
++ snd_soc_dapm_new_widgets(codec);
++ return 0;
++}
++
++/* PLL divisors */
++struct _pll_div {
++ u32 prescale:1;
++ u32 postscale:1;
++ u32 freqmode:2;
++ u32 n:4;
++ u32 k:24;
++};
++
++/* The size in bits of the pll divide */
++#define FIXED_PLL_SIZE (1 << 22)
++
++/* PLL rate to output rate divisions */
++static struct {
++ unsigned int div;
++ unsigned int freqmode;
++ unsigned int postscale;
++} post_table[] = {
++ { 2, 0, 0 },
++ { 4, 0, 1 },
++ { 4, 1, 0 },
++ { 8, 1, 1 },
++ { 8, 2, 0 },
++ { 16, 2, 1 },
++ { 12, 3, 0 },
++ { 24, 3, 1 }
++};
++
++static int pll_factors(struct _pll_div *pll_div, unsigned int target,
++ unsigned int source)
++{
++ u64 Kpart;
++ unsigned int K, Ndiv, Nmod;
++ int i;
++
++ dbg("wm8580: PLL %dHz->%dHz\n", source, target);
++
++ /* Scale the output frequency up; the PLL should run in the
++ * region of 90-100MHz.
++ */
++ for (i = 0; i < ARRAY_SIZE(post_table); i++) {
++ if (target * post_table[i].div >= 90000000 &&
++ target * post_table[i].div <= 100000000) {
++ pll_div->freqmode = post_table[i].freqmode;
++ pll_div->postscale = post_table[i].postscale;
++ target *= post_table[i].div;
++ break;
++ }
++ }
++
++ if (i == ARRAY_SIZE(post_table)) {
++ printk(KERN_ERR "wm8580: Unable to scale output frequency "
++ "%u\n", target);
++ return -EINVAL;
++ }
++
++ Ndiv = target / source;
++
++ if (Ndiv < 5) {
++ source /= 2;
++ pll_div->prescale = 1;
++ Ndiv = target / source;
++ } else
++ pll_div->prescale = 0;
++
++ if ((Ndiv < 5) || (Ndiv > 13)) {
++ printk(KERN_ERR
++ "WM8580 N=%d outside supported range\n", Ndiv);
++ return -EINVAL;
++ }
++
++ pll_div->n = Ndiv;
++ Nmod = target % source;
++ Kpart = FIXED_PLL_SIZE * (long long)Nmod;
++
++ do_div(Kpart, source);
++
++ K = Kpart & 0xFFFFFFFF;
++
++ pll_div->k = K;
++
++ dbg("PLL %x.%x prescale %d freqmode %d postscale %d\n",
++ pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
++ pll_div->postscale);
++
++ return 0;
++}
++
++static int wm8580_set_dai_pll(struct snd_soc_codec_dai *codec_dai,
++ int pll_id, unsigned int freq_in, unsigned int freq_out)
++{
++ int offset;
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct wm8580_priv *wm8580 = codec->private_data;
++ struct pll_state *state;
++ struct _pll_div pll_div;
++ unsigned int reg;
++ unsigned int pwr_mask;
++ int ret;
++
++ switch (pll_id) {
++ case WM8580_PLLA:
++ state = &wm8580->a;
++ offset = 0;
++ pwr_mask = WM8580_PWRDN2_PLLAPD;
++ break;
++ case WM8580_PLLB:
++ state = &wm8580->b;
++ offset = 4;
++ pwr_mask = WM8580_PWRDN2_PLLBPD;
++ break;
++ default:
++ return -ENODEV;
++ }
++
++ if (freq_in && freq_out) {
++ ret = pll_factors(&pll_div, freq_out, freq_in);
++ if (ret != 0)
++ return ret;
++ }
++
++ state->in = freq_in;
++ state->out = freq_out;
++
++ /* Always disable the PLL - it is not safe to leave it running
++ * while reprogramming it.
++ */
++ reg = wm8580_read(codec, WM8580_PWRDN2);
++ wm8580_write(codec, WM8580_PWRDN2, reg | pwr_mask);
++
++ if (!freq_in || !freq_out)
++ return 0;
++
++ wm8580_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
++ wm8580_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff);
++ wm8580_write(codec, WM8580_PLLA3 + offset,
++ (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
++
++ reg = wm8580_read(codec, WM8580_PLLA4 + offset);
++ reg &= ~0x3f;
++ reg |= pll_div.prescale | pll_div.postscale << 1 |
++ pll_div.freqmode << 4;
++
++ wm8580_write(codec, WM8580_PLLA4 + offset, reg);
++
++ /* All done, turn it on */
++ reg = wm8580_read(codec, WM8580_PWRDN2);
++ wm8580_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
++
++ return 0;
++}
++
++/*
++ * Set PCM DAI bit size and sample rate.
++ */
++static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai_link *dai = rtd->dai;
++ struct snd_soc_device *socdev = rtd->socdev;
++ struct snd_soc_codec *codec = socdev->codec;
++
++ u16 paifb = wm8580_read(codec, WM8580_PAIF3 + dai->codec_dai->id);
++
++ paifb &= ~WM8580_AIF_LENGTH_MASK;
++
++ /* bit size */
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ printk(KERN_CRIT "16 bit\n");
++ paifb |= WM8580_AIF_LENGTH_16;
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ printk(KERN_CRIT "20 bit\n");
++ paifb |= WM8580_AIF_LENGTH_20;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ printk(KERN_CRIT "24 bit\n");
++ paifb |= WM8580_AIF_LENGTH_24;
++ break;
++ case SNDRV_PCM_FORMAT_S32_LE:
++ printk(KERN_CRIT "32 bit\n");
++ paifb |= WM8580_AIF_LENGTH_24;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ wm8580_write(codec, WM8580_PAIF3 + dai->codec_dai->id, paifb);
++ return 0;
++}
++
++static int wm8580_set_paif_dai_fmt(struct snd_soc_codec_dai *codec_dai,
++ unsigned int fmt)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ unsigned int aifa;
++ unsigned int aifb;
++ int can_invert_lrclk;
++
++ aifa = wm8580_read(codec, WM8580_PAIF1 + codec_dai->id);
++ aifb = wm8580_read(codec, WM8580_PAIF3 + codec_dai->id);
++
++ aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
++
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ aifa &= ~WM8580_AIF_MS;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ aifa |= WM8580_AIF_MS;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ can_invert_lrclk = 1;
++ aifb |= WM8580_AIF_FMT_I2S;
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ can_invert_lrclk = 1;
++ aifb |= WM8580_AIF_FMT_RIGHTJ;
++ break;
++ case SND_SOC_DAIFMT_LEFT_J:
++ can_invert_lrclk = 1;
++ aifb |= WM8580_AIF_FMT_LEFTJ;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ can_invert_lrclk = 0;
++ aifb |= WM8580_AIF_FMT_DSP;
++ break;
++ case SND_SOC_DAIFMT_DSP_B:
++ can_invert_lrclk = 0;
++ aifb |= WM8580_AIF_FMT_DSP;
++ aifb |= WM8580_AIF_LRP;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_NB_NF:
++ break;
++
++ case SND_SOC_DAIFMT_IB_IF:
++ if (!can_invert_lrclk)
++ return -EINVAL;
++ aifb |= WM8580_AIF_BCP;
++ aifb |= WM8580_AIF_LRP;
++ break;
++
++ case SND_SOC_DAIFMT_IB_NF:
++ aifb |= WM8580_AIF_BCP;
++ break;
++
++ case SND_SOC_DAIFMT_NB_IF:
++ if (!can_invert_lrclk)
++ return -EINVAL;
++ aifb |= WM8580_AIF_LRP;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ wm8580_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
++ wm8580_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
++
++ return 0;
++}
++
++static int wm8580_set_dai_clkdiv(struct snd_soc_codec_dai *codec_dai,
++ int div_id, int div)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ unsigned int reg;
++
++ switch (div_id) {
++ case WM8580_MCLK:
++ reg = wm8580_read(codec, WM8580_PLLB4);
++ reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
++
++ switch (div) {
++ case WM8580_CLKSRC_MCLK:
++ /* Input */
++ break;
++
++ case WM8580_CLKSRC_PLLA:
++ reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
++ break;
++ case WM8580_CLKSRC_PLLB:
++ reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
++ break;
++
++ case WM8580_CLKSRC_OSC:
++ reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++ wm8580_write(codec, WM8580_PLLB4, reg);
++ break;
++
++ case WM8580_DAC_CLKSEL:
++ reg = wm8580_read(codec, WM8580_CLKSEL);
++ reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
++
++ switch (div) {
++ case WM8580_CLKSRC_MCLK:
++ break;
++
++ case WM8580_CLKSRC_PLLA:
++ reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
++ break;
++
++ case WM8580_CLKSRC_PLLB:
++ reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++ wm8580_write(codec, WM8580_CLKSEL, reg);
++ break;
++
++ case WM8580_CLKOUTSRC:
++ reg = wm8580_read(codec, WM8580_PLLB4);
++ reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
++
++ switch (div) {
++ case WM8580_CLKSRC_NONE:
++ break;
++
++ case WM8580_CLKSRC_PLLA:
++ reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
++ break;
++
++ case WM8580_CLKSRC_PLLB:
++ reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
++ break;
++
++ case WM8580_CLKSRC_OSC:
++ reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++ wm8580_write(codec, WM8580_PLLB4, reg);
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int wm8580_dapm_event(struct snd_soc_codec *codec, int event)
++{
++ u16 reg;
++ switch (event) {
++ case SNDRV_CTL_POWER_D0: /* full On */
++ case SNDRV_CTL_POWER_D1: /* partial On */
++ case SNDRV_CTL_POWER_D2: /* partial On */
++ break;
++ case SNDRV_CTL_POWER_D3hot: /* Off, with power */
++ break;
++ case SNDRV_CTL_POWER_D3cold: /* Off, without power */
++ reg = wm8580_read(codec, WM8580_PWRDN1);
++ wm8580_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
++ break;
++ }
++ codec->dapm_state = event;
++ return 0;
++}
++
++#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
++ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
++
++struct snd_soc_codec_dai wm8580_dai[] = {
++ {
++ .name = "WM8580 PAIFRX",
++ .id = 0,
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 1,
++ .channels_max = 6,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = WM8580_FORMATS,
++ },
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = WM8580_FORMATS,
++ },
++ .ops = {
++ .hw_params = wm8580_paif_hw_params,
++ },
++ .dai_ops = {
++ .set_fmt = wm8580_set_paif_dai_fmt,
++ .set_clkdiv = wm8580_set_dai_clkdiv,
++ .set_pll = wm8580_set_dai_pll,
++ },
++ },
++#if 0
++ {
++ .name = "WM8580 PAIFTX",
++ .id = 1,
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = WM8580_FORMATS,
++ },
++ .ops = {
++ .hw_params = wm8580_paif_hw_params,
++ },
++ .dai_ops = {
++ .set_fmt = wm8580_set_paif_dai_fmt,
++ .set_clkdiv = wm8580_set_dai_clkdiv,
++ .set_pll = wm8580_set_dai_pll,
++ },
++ },
++#endif
++};
++EXPORT_SYMBOL_GPL(wm8580_dai);
++
++/*
++ * initialise the WM8580 driver
++ * register the mixer and dsp interfaces with the kernel
++ */
++static int wm8580_init(struct snd_soc_device *socdev)
++{
++ struct snd_soc_codec *codec = socdev->codec;
++ int ret = 0;
++ int i;
++
++ codec->name = "WM8580";
++ codec->owner = THIS_MODULE;
++ codec->read = wm8580_read_reg_cache;
++ codec->write = wm8580_write;
++ codec->dapm_event = wm8580_dapm_event;
++ codec->dai = wm8580_dai;
++ codec->num_dai = ARRAY_SIZE(wm8580_dai);
++ codec->reg_cache_size = ARRAY_SIZE(wm8580_reg);
++ codec->reg_cache = kmemdup(wm8580_reg, sizeof(wm8580_reg),
++ GFP_KERNEL);
++
++ if (codec->reg_cache == NULL)
++ return -ENOMEM;
++
++ /* Get the codec into a known state */
++ wm8580_write(codec, WM8580_RESET, 0);
++
++ /* Power up and get individual control of the DACs */
++ wm8580_write(codec, WM8580_PWRDN1, wm8580_read(codec, WM8580_PWRDN1) &
++ ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD));
++
++ /* Make VMID high impedence */
++ wm8580_write(codec, WM8580_ADC_CONTROL1,
++ wm8580_read(codec, WM8580_ADC_CONTROL1) & ~0x100);
++
++ /* register pcms */
++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1,
++ SNDRV_DEFAULT_STR1);
++ if (ret < 0) {
++ printk(KERN_ERR "wm8580: failed to create pcms\n");
++ goto pcm_err;
++ }
++
++/* Added : For Capture Path..*/
++ u16 reg;
++/* Line-In */
++ wm8580_write(codec, WM8580_ADC_CONTROL1, wm8580_read(codec,WM8580_ADC_CONTROL1) | 0x60);
++ wm8580_write(codec, WM8580_SAIF2, wm8580_read(codec,WM8580_SAIF2) & (0<<3) | 0xc2);
++
++ wm8580_add_controls(codec);
++ wm8580_add_widgets(codec);
++
++ ret = snd_soc_register_card(socdev);
++ if (ret < 0) {
++ printk(KERN_ERR "wm8580: failed to register card\n");
++ goto card_err;
++ }
++ return ret;
++
++card_err:
++ snd_soc_free_pcms(socdev);
++ snd_soc_dapm_free(socdev);
++pcm_err:
++ kfree(codec->reg_cache);
++ return ret;
++}
++
++/* If the i2c layer weren't so broken, we could pass this kind of data
++ around */
++static struct snd_soc_device *wm8580_socdev;
++
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++
++/*
++ * WM8580 2 wire address is determined by GPIO5
++ * state during powerup.
++ * low = 0x1a
++ * high = 0x1b
++ */
++static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
++
++/* Magic definition of all other variables and things */
++I2C_CLIENT_INSMOD;
++
++static struct i2c_driver wm8580_i2c_driver;
++static struct i2c_client client_template;
++
++static int wm8580_codec_probe(struct i2c_adapter *adap, int addr, int kind)
++{
++ struct snd_soc_device *socdev = wm8580_socdev;
++ struct wm8580_setup_data *setup = socdev->codec_data;
++ struct snd_soc_codec *codec = socdev->codec;
++ struct i2c_client *i2c;
++ int ret;
++
++ if (addr != setup->i2c_address)
++ return -ENODEV;
++
++ client_template.adapter = adap;
++ client_template.addr = addr;
++
++ i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
++ if (i2c == NULL){
++ kfree(codec);
++ return -ENOMEM;
++ }
++ i2c_set_clientdata(i2c, codec);
++ codec->control_data = i2c;
++
++ ret = i2c_attach_client(i2c);
++ if (ret < 0) {
++ err("failed to attach codec at addr %x\n", addr);
++ goto err;
++ }
++
++ ret = wm8580_init(socdev);
++ if (ret < 0) {
++ err("failed to initialise WM8580\n");
++ goto err;
++ }
++
++ return ret;
++
++err:
++ kfree(codec);
++ kfree(i2c);
++ return ret;
++}
++
++static int wm8580_i2c_detach(struct i2c_client *client)
++{
++ struct snd_soc_codec *codec = i2c_get_clientdata(client);
++ i2c_detach_client(client);
++ kfree(codec->reg_cache);
++ kfree(client);
++ return 0;
++}
++
++static int wm8580_i2c_attach(struct i2c_adapter *adap)
++{
++ return i2c_probe(adap, &addr_data, wm8580_codec_probe);
++}
++
++/* corgi i2c codec control layer */
++static struct i2c_driver wm8580_i2c_driver = {
++ .driver = {
++ .name = "WM8580 I2C Codec",
++ .owner = THIS_MODULE,
++ },
++ .id = I2C_DRIVERID_WM8580,
++ .attach_adapter = wm8580_i2c_attach,
++ .detach_client = wm8580_i2c_detach,
++ .command = NULL,
++};
++
++static struct i2c_client client_template = {
++ .name = "WM8580",
++ .driver = &wm8580_i2c_driver,
++};
++#endif
++
++static int wm8580_probe(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct wm8580_setup_data *setup;
++ struct snd_soc_codec *codec;
++ struct wm8580_priv *wm8580;
++ int ret = 0;
++
++ info("WM8580 Audio Codec %s\n", WM8580_VERSION);
++
++ setup = socdev->codec_data;
++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
++ if (codec == NULL)
++ return -ENOMEM;
++
++ wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
++ if (wm8580 == NULL) {
++ kfree(codec);
++ return -ENOMEM;
++ }
++
++ codec->private_data = wm8580;
++ socdev->codec = codec;
++ mutex_init(&codec->mutex);
++ INIT_LIST_HEAD(&codec->dapm_widgets);
++ INIT_LIST_HEAD(&codec->dapm_paths);
++ wm8580_socdev = socdev;
++
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++ if (setup->i2c_address) {
++ normal_i2c[0] = setup->i2c_address;
++ codec->hw_write = (hw_write_t)i2c_master_send;
++ ret = i2c_add_driver(&wm8580_i2c_driver);
++ if (ret != 0)
++ printk(KERN_ERR "can't add i2c driver");
++ }
++#else
++ /* Add other interfaces here */
++#endif
++ return ret;
++}
++
++/* power down chip */
++static int wm8580_remove(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++
++ if (codec->control_data)
++ wm8580_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
++ snd_soc_free_pcms(socdev);
++ snd_soc_dapm_free(socdev);
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++ i2c_del_driver(&wm8580_i2c_driver);
++#endif
++ kfree(codec->private_data);
++ kfree(codec);
++
++ return 0;
++}
++
++struct snd_soc_codec_device soc_codec_dev_wm8580 = {
++ .probe = wm8580_probe,
++ .remove = wm8580_remove,
++};
++
++EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
++
++MODULE_DESCRIPTION("ASoC WM8580 driver");
++MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h
+new file mode 100644
+index 0000000..0f1aa77
+--- /dev/null
++++ b/sound/soc/codecs/wm8580.h
+@@ -0,0 +1,165 @@
++/*
++ * wm8580.h -- audio driver for WM8580
++ *
++ * Copyright 2008 Samsung Electronics.
++ * Author: Ryu Euiyoul
++ * ryu.real@gmail.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#ifndef _WM8580_H
++#define _WM8580_H
++
++#define WM8580_PLLA 1
++#define WM8580_PLLB 2
++
++#define WM8580_MCLK 1
++#define WM8580_DAC_CLKSEL 2
++#define WM8580_CLKOUTSRC 3
++
++#define WM8580_CLKSRC_MCLK 1
++#define WM8580_CLKSRC_PLLA 2
++#define WM8580_CLKSRC_PLLB 3
++#define WM8580_CLKSRC_OSC 4
++#define WM8580_CLKSRC_NONE 5
++
++/* WM8580 register space */
++#define WM8580_PLLA1 0x00
++#define WM8580_PLLA2 0x01
++#define WM8580_PLLA3 0x02
++#define WM8580_PLLA4 0x03
++#define WM8580_PLLB1 0x04
++#define WM8580_PLLB2 0x05
++#define WM8580_PLLB3 0x06
++#define WM8580_PLLB4 0x07
++#define WM8580_CLKSEL 0x08
++#define WM8580_PAIF1 0x09
++#define WM8580_PAIF2 0x0A
++#define WM8580_SAIF1 0x0B
++#define WM8580_PAIF3 0x0C
++#define WM8580_PAIF4 0x0D
++#define WM8580_SAIF2 0x0E
++#define WM8580_DAC_CONTROL1 0x0F
++#define WM8580_DAC_CONTROL2 0x10
++#define WM8580_DAC_CONTROL3 0x11
++#define WM8580_DAC_CONTROL4 0x12
++#define WM8580_DAC_CONTROL5 0x13
++#define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
++#define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
++#define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
++#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
++#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
++#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
++#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
++#define WM8580_ADC_CONTROL1 0x1D
++#define WM8580_SPDTXCHAN0 0x1E
++#define WM8580_SPDTXCHAN1 0x1F
++#define WM8580_SPDTXCHAN2 0x20
++#define WM8580_SPDTXCHAN3 0x21
++#define WM8580_SPDTXCHAN4 0x22
++#define WM8580_SPDTXCHAN5 0x23
++#define WM8580_SPDMODE 0x24
++#define WM8580_INTMASK 0x25
++#define WM8580_GPO1 0x26
++#define WM8580_GPO2 0x27
++#define WM8580_GPO3 0x28
++#define WM8580_GPO4 0x29
++#define WM8580_GPO5 0x2A
++#define WM8580_INTSTAT 0x2B
++#define WM8580_SPDRXCHAN1 0x2C
++#define WM8580_SPDRXCHAN2 0x2D
++#define WM8580_SPDRXCHAN3 0x2E
++#define WM8580_SPDRXCHAN4 0x2F
++#define WM8580_SPDRXCHAN5 0x30
++#define WM8580_SPDSTAT 0x31
++#define WM8580_PWRDN1 0x32
++#define WM8580_PWRDN2 0x33
++#define WM8580_READBACK 0x34
++#define WM8580_RESET 0x35
++
++/* PLLB4 (register 7h) */
++#define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
++#define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
++#define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
++#define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
++
++#define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
++#define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
++#define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
++#define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
++
++/* CLKSEL (register 8h) */
++#define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
++#define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
++#define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
++
++/* AIF control 1 (registers 9h-bh) */
++#define WM8580_AIF_RATE_MASK 0x7
++#define WM8580_AIF_RATE_128 0x0
++#define WM8580_AIF_RATE_192 0x1
++#define WM8580_AIF_RATE_256 0x2
++#define WM8580_AIF_RATE_384 0x3
++#define WM8580_AIF_RATE_512 0x4
++#define WM8580_AIF_RATE_768 0x5
++#define WM8580_AIF_RATE_1152 0x6
++
++#define WM8580_AIF_BCLKSEL_MASK 0x18
++#define WM8580_AIF_BCLKSEL_64 0x00
++#define WM8580_AIF_BCLKSEL_128 0x08
++#define WM8580_AIF_BCLKSEL_256 0x10
++#define WM8580_AIF_BCLKSEL_SYSCLK 0x18
++
++#define WM8580_AIF_MS 0x20
++
++#define WM8580_AIF_CLKSRC_MASK 0xc0
++#define WM8580_AIF_CLKSRC_PLLA 0x40
++#define WM8580_AIF_CLKSRC_PLLB 0x40
++#define WM8580_AIF_CLKSRC_MCLK 0xc0
++
++/* AIF control 2 (registers ch-eh) */
++#define WM8580_AIF_FMT_MASK 0x03
++#define WM8580_AIF_FMT_RIGHTJ 0x00
++#define WM8580_AIF_FMT_LEFTJ 0x01
++#define WM8580_AIF_FMT_I2S 0x02
++#define WM8580_AIF_FMT_DSP 0x03
++
++#define WM8580_AIF_LENGTH_MASK 0x0c
++#define WM8580_AIF_LENGTH_16 0x00
++#define WM8580_AIF_LENGTH_20 0x04
++#define WM8580_AIF_LENGTH_24 0x08
++#define WM8580_AIF_LENGTH_32 0x0c
++
++#define WM8580_AIF_LRP 0x10
++#define WM8580_AIF_BCP 0x20
++
++/* Powerdown Register 1 (register 32h) */
++#define WM8580_PWRDN1_PWDN 0x001
++#define WM8580_PWRDN1_ALLDACPD 0x040
++
++/* Powerdown Register 2 (register 33h) */
++#define WM8580_PWRDN2_OSSCPD 0x001
++#define WM8580_PWRDN2_PLLAPD 0x002
++#define WM8580_PWRDN2_PLLBPD 0x004
++#define WM8580_PWRDN2_SPDIFPD 0x008
++#define WM8580_PWRDN2_SPDIFTXD 0x010
++#define WM8580_PWRDN2_SPDIFRXD 0x020
++
++extern struct snd_soc_codec_device soc_codec_dev_wm8580;
++
++struct wm8580_setup_data {
++ unsigned short i2c_address;
++};
++
++#define WM8580_DAI_PAIFRX 0
++#define WM8580_DAI_PAIFTX 1
++
++extern struct snd_soc_codec_dai wm8580_dai[];
++extern struct snd_soc_codec_device soc_codec_dev_wm8580;
++
++#endif
++
+diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c
+index efced93..a817581 100644
+--- a/sound/soc/codecs/wm8753.c
++++ b/sound/soc/codecs/wm8753.c
+@@ -1604,6 +1604,46 @@ static int wm8753_init(struct snd_soc_device *socdev)
+ reg = wm8753_read_reg_cache(codec, WM8753_RINVOL);
+ wm8753_write(codec, WM8753_RINVOL, reg | 0x0100);
+
++ /* Right Mixer Right Playback Swit on*/
++ reg = wm8753_read_reg_cache(codec, WM8753_ROUTM1);
++ wm8753_write(codec, WM8753_ROUTM1, reg | 0x0100);
++
++ /* Left Mixer Left Playback Swit on*/
++ reg = wm8753_read_reg_cache(codec, WM8753_LOUTM1);
++ wm8753_write(codec, WM8753_LOUTM1, reg | 0x0100);
++
++ /* Start Line Record Setting */
++ wm8753_write(codec, WM8753_IOCTL, 0x3b);
++
++ wm8753_write(codec, WM8753_ADC, 0x80);
++
++#ifdef CONFIG_SOUND_WM8753_INPUT_STREAM_LINE_IN
++ // ADC Input Select
++ wm8753_write(codec, WM8753_ADCIN, 0x35);
++ // ALC Select
++ wm8753_write(codec, WM8753_INCTL1, 0x00);
++ // ALC Select
++ wm8753_write(codec, WM8753_INCTL2, 0x08);
++ // Left Input Control
++ wm8753_write(codec, WM8753_LINVOL, 0x13f);
++ // Right Input Control
++ wm8753_write(codec, WM8753_MICBIAS, 0x100);
++ // Record Mixer 1
++ wm8753_write(codec, WM8753_RECMIX1, 0x000);
++ // Record Mixer 2
++ wm8753_write(codec, WM8753_RECMIX2, 0x00c);
++ // Mono out Mixser
++ wm8753_write(codec, WM8753_MOUTM1, 0x00);
++
++#elif CONFIG_SOUND_WM8753_INPUT_STREAM_MIC_IN
++ wm8753_write(codec, WM8753_ADCIN, 0x3c);
++ wm8753_write(codec, WM8753_INCTL1, 0x60);
++ wm8753_write(codec, WM8753_INCTL2, 0x02);
++ wm8753_write(codec, WM8753_LINVOL, 0x13f);
++ wm8753_write(codec, WM8753_MICBIAS, 0x100);
++#endif
++ /* End Line Record Setting */
++
+ wm8753_add_controls(codec);
+ wm8753_add_widgets(codec);
+ ret = snd_soc_register_card(socdev);
+diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
+new file mode 100644
+index 0000000..f088329
+--- /dev/null
++++ b/sound/soc/codecs/wm8990.c
+@@ -0,0 +1,1657 @@
++/*
++ * wm8990.c -- WM8990 ALSA Soc Audio driver
++ *
++ * Copyright 2008 Wolfson Microelectronics PLC.
++ * Author: Liam Girdwood
++ * lg@opensource.wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 6th Mar 2008 Initial version.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++#include <asm/div64.h>
++
++#include "wm8990.h"
++
++#define AUDIO_NAME "wm8990"
++#define WM8990_VERSION "0.1"
++
++/*
++ * Debug
++ */
++
++#define WM8753_DEBUG 0
++
++#ifdef WM8753_DEBUG
++#define dbg(format, arg...) \
++ printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg)
++#else
++#define dbg(format, arg...) do {} while (0)
++#endif
++#define err(format, arg...) \
++ printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
++#define info(format, arg...) \
++ printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
++#define warn(format, arg...) \
++ printk(KERN_WARNING AUDIO_NAME ": " format "\n" , ## arg)
++
++/* codec private data */
++struct wm8990_priv {
++ unsigned int sysclk;
++ unsigned int pcmclk;
++};
++
++/*
++ * wm8990 register cache
++ * We can't read the WM8990 register space when we
++ * are using 2 wire for device control, so we cache them instead.
++ */
++static const u16 wm8990_reg[] = WM8990_REGISTER_DEFAULTS;
++
++/*
++ * read wm8990 register cache
++ */
++static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec,
++ unsigned int reg)
++{
++ u16 *cache = codec->reg_cache;
++ if (reg < 1 || reg > (ARRAY_SIZE(wm8990_reg) + 1))
++ return -1;
++ return cache[reg - 1];
++}
++
++/*
++ * write wm8990 register cache
++ */
++static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec,
++ unsigned int reg, unsigned int value)
++{
++ u16 *cache = codec->reg_cache;
++ if (reg < 1 || reg > 0x3f)
++ return;
++ cache[reg - 1] = value;
++}
++
++/*
++ * write to the wm8990 register space
++ */
++static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg,
++ unsigned int value)
++{
++ u8 data[3];
++
++ data[0] = reg & 0xFF;
++ data[1] = (value >> 8) & 0xFF;
++ data[2] = value & 0xFF;
++
++ wm8990_write_reg_cache (codec, reg, value);
++ if (codec->hw_write(codec->control_data, data, 3) == 2)
++ return 0;
++ else
++ return -EIO;
++}
++
++#define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0)
++
++static const unsigned int rec_mix_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 7, TLV_DB_LINEAR_ITEM(-1500, 600),
++};
++
++static const unsigned int in_pga_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 0x1F, TLV_DB_LINEAR_ITEM(-1650, 3000),
++};
++
++static const unsigned int out_mix_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 7, TLV_DB_LINEAR_ITEM(0, -2100),
++};
++
++static const unsigned int out_pga_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 127, TLV_DB_LINEAR_ITEM(-7300, 600),
++};
++
++static const unsigned int out_omix_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 7, TLV_DB_LINEAR_ITEM(-600, 0),
++};
++
++static const unsigned int out_dac_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 255, TLV_DB_LINEAR_ITEM(-7163, 0),
++};
++
++static const unsigned int in_adc_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 255, TLV_DB_LINEAR_ITEM(-7163, 1763),
++};
++
++static const unsigned int out_sidetone_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0, 31, TLV_DB_LINEAR_ITEM(-3600, 0),
++};
++
++static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++ int reg = kcontrol->private_value & 0xff;
++ int ret;
++ u16 val;
++
++ ret = snd_soc_put_volsw(kcontrol, ucontrol);
++ if (ret < 0)
++ return ret;
++
++ /* now hit the volume update bits (always bit 8) */
++ val = wm8990_read_reg_cache(codec, reg);
++ return wm8990_write(codec, reg, val | 0x0100);
++}
++
++#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\
++ .tlv.p = (tlv_array), \
++ .info = snd_soc_info_volsw, \
++ .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
++ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
++
++
++static const char *wm8990_digital_sidetone[] =
++ {"None", "Left ADC", "Right ADC", "Reserved"};
++
++static const struct soc_enum wm8990_left_digital_sidetone_enum =
++SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
++ WM8990_ADC_TO_DACL_SHIFT,
++ WM8990_ADC_TO_DACL_MASK,
++ wm8990_digital_sidetone);
++
++static const struct soc_enum wm8990_right_digital_sidetone_enum =
++SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
++ WM8990_ADC_TO_DACR_SHIFT,
++ WM8990_ADC_TO_DACR_MASK,
++ wm8990_digital_sidetone);
++
++static const char *wm8990_adcmode[] =
++ {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
++
++static const struct soc_enum wm8990_right_adcmode_enum =
++SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
++ WM8990_ADC_HPF_CUT_SHIFT,
++ WM8990_ADC_HPF_CUT_MASK,
++ wm8990_adcmode);
++
++static const struct snd_kcontrol_new wm8990_snd_controls[] = {
++/* INMIXL */
++SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
++SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
++/* INMIXR */
++SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
++SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
++
++/* LOMIX */
++SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
++ WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
++ WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
++ WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
++ WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
++ WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
++ WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
++
++/* ROMIX */
++SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
++ WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
++ WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
++ WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
++ WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
++ WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
++SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
++ WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
++
++/* LOUT */
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
++ WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
++SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
++
++/* ROUT */
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
++ WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
++SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
++
++/* LOPGA */
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
++ WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
++SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
++ WM8990_LOPGAZC_BIT, 1, 0),
++
++/* ROPGA */
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
++ WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
++SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
++ WM8990_ROPGAZC_BIT, 1, 0),
++
++SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
++ WM8990_LONMUTE_BIT, 1, 0),
++SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
++ WM8990_LOPMUTE_BIT, 1, 0),
++SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
++ WM8990_LOATTN_BIT, 1, 0),
++SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
++ WM8990_RONMUTE_BIT, 1, 0),
++SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
++ WM8990_ROPMUTE_BIT, 1, 0),
++SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
++ WM8990_ROATTN_BIT, 1, 0),
++
++SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
++ WM8990_OUT3MUTE_BIT, 1, 0),
++SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
++ WM8990_OUT3ATTN_BIT, 1, 0),
++
++SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
++ WM8990_OUT4MUTE_BIT, 1, 0),
++SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
++ WM8990_OUT4ATTN_BIT, 1, 0),
++
++SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
++ WM8990_CDMODE_BIT, 1, 0),
++
++SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
++ WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0),
++SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
++ WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
++SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
++ WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
++ WM8990_LEFT_DAC_DIGITAL_VOLUME,
++ WM8990_DACL_VOL_SHIFT,
++ WM8990_DACL_VOL_MASK,
++ 0,
++ out_dac_tlv),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
++ WM8990_RIGHT_DAC_DIGITAL_VOLUME,
++ WM8990_DACR_VOL_SHIFT,
++ WM8990_DACR_VOL_MASK,
++ 0,
++ out_dac_tlv),
++
++SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
++SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
++
++SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
++ WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
++ out_sidetone_tlv),
++SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
++ WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
++ out_sidetone_tlv),
++
++SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
++ WM8990_ADC_HPF_ENA_BIT, 1, 0),
++
++SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
++ WM8990_LEFT_ADC_DIGITAL_VOLUME,
++ WM8990_ADCL_VOL_SHIFT,
++ WM8990_ADCL_VOL_MASK,
++ 0,
++ in_adc_tlv),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
++ WM8990_RIGHT_ADC_DIGITAL_VOLUME,
++ WM8990_ADCR_VOL_SHIFT,
++ WM8990_ADCR_VOL_MASK,
++ 0,
++ in_adc_tlv),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
++ WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
++ WM8990_LIN12VOL_SHIFT,
++ WM8990_LIN12VOL_MASK,
++ 0,
++ in_pga_tlv),
++
++SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
++ WM8990_LI12ZC_BIT, 1, 0),
++
++SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
++ WM8990_LI12MUTE_BIT, 1, 0),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
++ WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
++ WM8990_LIN34VOL_SHIFT,
++ WM8990_LIN34VOL_MASK,
++ 0,
++ in_pga_tlv),
++
++SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
++ WM8990_LI34ZC_BIT, 1, 0),
++
++SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
++ WM8990_LI34MUTE_BIT, 1, 0),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
++ WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
++ WM8990_RIN12VOL_SHIFT,
++ WM8990_RIN12VOL_MASK,
++ 0,
++ in_pga_tlv),
++
++SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
++ WM8990_RI12ZC_BIT, 1, 0),
++
++SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
++ WM8990_RI12MUTE_BIT, 1, 0),
++
++SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
++ WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
++ WM8990_RIN34VOL_SHIFT,
++ WM8990_RIN34VOL_MASK,
++ 0,
++ in_pga_tlv),
++
++SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
++ WM8990_RI34ZC_BIT, 1, 0),
++
++SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
++ WM8990_RI34MUTE_BIT, 1, 0),
++
++};
++
++/* add non dapm controls */
++static int wm8990_add_controls(struct snd_soc_codec *codec)
++{
++ int err, i;
++
++ for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm8990_snd_controls[i],codec,
++ NULL));
++ if (err < 0)
++ return err;
++ }
++ return 0;
++}
++
++/*
++ * _DAPM_ Controls
++ */
++
++static int inmixer_event (struct snd_soc_dapm_widget *w,
++ struct snd_kcontrol *kcontrol, int event)
++{
++ u16 reg, fakepower;
++
++ reg=wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2);
++ fakepower=wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS);
++
++ if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
++ (1 << WM8990_AINLMUX_PWR_BIT))) {
++ reg |= WM8990_AINL_ENA;
++ } else {
++ reg &= ~WM8990_AINL_ENA;
++ }
++
++ if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
++ (1 << WM8990_AINRMUX_PWR_BIT))) {
++ reg |= WM8990_AINR_ENA;
++ } else {
++ reg &= ~WM8990_AINL_ENA;
++ }
++ wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
++
++ return 0;
++}
++
++static int outmixer_event (struct snd_soc_dapm_widget *w,
++ struct snd_kcontrol * kcontrol, int event)
++{
++ u32 reg_shift = kcontrol->private_value & 0xfff;
++ int ret = 0;
++ u16 reg;
++
++// printk("reg_shift %4.4x\n", reg_shift);
++
++ switch (reg_shift) {
++ case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
++ reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1);
++ printk("reg %4.4x\n", reg);
++ if (reg & WM8990_LDLO) {
++ printk(KERN_WARNING
++ "Cannot set as Output Mixer 1 LDLO Set\n");
++ ret = -1;
++ }
++ break;
++ case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
++ reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2);
++ if (reg & WM8990_RDRO) {
++ printk(KERN_WARNING
++ "Cannot set as Output Mixer 2 RDRO Set\n");
++ ret = -1;
++ }
++ break;
++ case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
++ reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
++ if (reg & WM8990_LDSPK) {
++ printk(KERN_WARNING
++ "Cannot set as Speaker Mixer LDSPK Set\n");
++ ret = -1;
++ }
++ break;
++ case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
++ reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
++ if (reg & WM8990_RDSPK) {
++ printk(KERN_WARNING
++ "Cannot set as Speaker Mixer RDSPK Set\n");
++ ret = -1;
++ }
++ break;
++ }
++
++ return ret;
++}
++
++/* INMIX dB values */
++static const unsigned int in_mix_tlv[] = {
++ TLV_DB_RANGE_HEAD(1),
++ 0,7, TLV_DB_LINEAR_ITEM(-1200, 600),
++};
++
++/* Left In PGA Connections */
++static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
++SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
++SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
++};
++
++static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
++SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
++SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
++};
++
++/* Right In PGA Connections */
++static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
++SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
++SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
++};
++
++static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
++SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
++SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
++};
++
++/* INMIXL */
++static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
++SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
++ WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
++SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
++ 7, 0, in_mix_tlv),
++SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 1, 0),
++SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 1, 0),
++};
++
++/* INMIXR */
++static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
++SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
++ WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
++SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
++ 7, 0, in_mix_tlv),
++SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
++ 1, 0),
++SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
++ 1, 0),
++};
++
++/* AINLMUX */
++static const char *wm8990_ainlmux[] =
++ {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
++
++static const struct soc_enum wm8990_ainlmux_enum =
++SOC_ENUM_SINGLE( WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
++ ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
++
++static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
++SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
++
++/* DIFFINL */
++
++/* AINRMUX */
++static const char *wm8990_ainrmux[] =
++ {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
++
++static const struct soc_enum wm8990_ainrmux_enum =
++SOC_ENUM_SINGLE( WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
++ ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
++
++static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
++SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
++
++/* RXVOICE */
++static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
++SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
++ WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
++SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
++ WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
++};
++
++/* LOMIX */
++static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
++SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
++ WM8990_LRBLO_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
++ WM8990_LLBLO_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
++ WM8990_LRI3LO_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
++ WM8990_LLI3LO_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
++ WM8990_LR12LO_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
++ WM8990_LL12LO_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
++ WM8990_LDLO_BIT, 1, 0),
++};
++
++/* ROMIX */
++static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
++SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
++ WM8990_RLBRO_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
++ WM8990_RRBRO_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
++ WM8990_RLI3RO_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
++ WM8990_RRI3RO_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
++ WM8990_RL12RO_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
++ WM8990_RR12RO_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
++ WM8990_RDRO_BIT, 1, 0),
++};
++
++/* LONMIX */
++static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
++SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
++ WM8990_LLOPGALON_BIT, 1, 0),
++SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
++ WM8990_LROPGALON_BIT, 1, 0),
++SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
++ WM8990_LOPLON_BIT, 1, 0),
++};
++
++/* LOPMIX */
++static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
++SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
++ WM8990_LR12LOP_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
++ WM8990_LL12LOP_BIT, 1, 0),
++SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
++ WM8990_LLOPGALOP_BIT, 1, 0),
++};
++
++/* RONMIX */
++static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
++SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
++ WM8990_RROPGARON_BIT, 1, 0),
++SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
++ WM8990_RLOPGARON_BIT, 1, 0),
++SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
++ WM8990_ROPRON_BIT, 1, 0),
++};
++
++/* ROPMIX */
++static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
++SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
++ WM8990_RL12ROP_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
++ WM8990_RR12ROP_BIT, 1, 0),
++SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
++ WM8990_RROPGAROP_BIT, 1, 0),
++};
++
++/* OUT3MIX */
++static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
++SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
++ WM8990_LI4O3_BIT, 1, 0),
++SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
++ WM8990_LPGAO3_BIT, 1, 0),
++};
++
++/* OUT4MIX */
++static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
++SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
++ WM8990_RPGAO4_BIT, 1, 0),
++SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
++ WM8990_RI4O4_BIT, 1, 0),
++};
++
++/* SPKMIX */
++static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
++SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
++ WM8990_LI2SPK_BIT, 1, 0),
++SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
++ WM8990_LB2SPK_BIT, 1, 0),
++SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
++ WM8990_LOPGASPK_BIT, 1, 0),
++SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
++ WM8990_LDSPK_BIT, 1, 0),
++SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
++ WM8990_RDSPK_BIT, 1, 0),
++SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
++ WM8990_ROPGASPK_BIT, 1, 0),
++SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
++ WM8990_RL12ROP_BIT, 1, 0),
++SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
++ WM8990_RI2SPK_BIT, 1, 0),
++};
++
++static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
++/* Input Side */
++/* Input Lines */
++SND_SOC_DAPM_INPUT("LIN1"),
++SND_SOC_DAPM_INPUT("LIN2"),
++SND_SOC_DAPM_INPUT("LIN3"),
++SND_SOC_DAPM_INPUT("LIN4/RXN"),
++SND_SOC_DAPM_INPUT("RIN3"),
++SND_SOC_DAPM_INPUT("RIN4/RXP"),
++SND_SOC_DAPM_INPUT("RIN1"),
++SND_SOC_DAPM_INPUT("RIN2"),
++SND_SOC_DAPM_INPUT("Internal ADC Source"),
++
++/* DACs */
++SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
++ WM8990_ADCL_ENA_BIT, 0),
++SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
++ WM8990_ADCR_ENA_BIT, 0),
++
++/* Input PGAs */
++SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
++ 0, &wm8990_dapm_lin12_pga_controls[0],
++ ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
++SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
++ 0, &wm8990_dapm_lin34_pga_controls[0],
++ ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
++SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
++ 0, &wm8990_dapm_rin12_pga_controls[0],
++ ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
++SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
++ 0, &wm8990_dapm_rin34_pga_controls[0],
++ ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
++
++/* INMIXL */
++SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
++ &wm8990_dapm_inmixl_controls[0],
++ ARRAY_SIZE(wm8990_dapm_inmixl_controls),
++ inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++
++/* AINLMUX */
++SND_SOC_DAPM_MUX_E("AILNMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
++ &wm8990_dapm_ainlmux_controls, inmixer_event,
++ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++
++/* INMIXR */
++SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
++ &wm8990_dapm_inmixr_controls[0],
++ ARRAY_SIZE(wm8990_dapm_inmixr_controls),
++ inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++
++/* AINRMUX */
++SND_SOC_DAPM_MUX_E("AIRNMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
++ &wm8990_dapm_ainrmux_controls, inmixer_event,
++ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++
++/* Output Side */
++/* DACs */
++SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
++ WM8990_DACL_ENA_BIT, 0),
++SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
++ WM8990_DACR_ENA_BIT, 0),
++
++/* LOMIX */
++SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
++ 0, &wm8990_dapm_lomix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_lomix_controls),
++ outmixer_event, SND_SOC_DAPM_PRE_REG),
++
++/* LONMIX */
++SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
++ &wm8990_dapm_lonmix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
++
++/* LOPMIX */
++SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
++ &wm8990_dapm_lopmix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
++
++/* OUT3MIX */
++SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
++ &wm8990_dapm_out3mix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
++
++/* SPKMIX */
++SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
++ &wm8990_dapm_spkmix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
++ SND_SOC_DAPM_PRE_REG),
++
++/* OUT4MIX */
++SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
++ &wm8990_dapm_out4mix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
++
++/* ROPMIX */
++SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
++ &wm8990_dapm_ropmix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
++
++/* RONMIX */
++SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
++ &wm8990_dapm_ronmix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
++
++/* ROMIX */
++SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
++ 0, &wm8990_dapm_romix_controls[0],
++ ARRAY_SIZE(wm8990_dapm_romix_controls),
++ outmixer_event, SND_SOC_DAPM_PRE_REG),
++
++/* LOUT PGA */
++SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
++ NULL, 0),
++
++/* ROUT PGA */
++SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
++ NULL, 0),
++
++/* LOPGA */
++SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
++ NULL, 0),
++
++/* ROPGA */
++SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
++ NULL, 0),
++
++/* MICBIAS */
++SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
++ WM8990_MICBIAS_ENA_BIT, 0),
++
++SND_SOC_DAPM_OUTPUT("LON"),
++SND_SOC_DAPM_OUTPUT("LOP"),
++SND_SOC_DAPM_OUTPUT("OUT3"),
++SND_SOC_DAPM_OUTPUT("LOUT"),
++SND_SOC_DAPM_OUTPUT("SPKN"),
++SND_SOC_DAPM_OUTPUT("SPKP"),
++SND_SOC_DAPM_OUTPUT("ROUT"),
++SND_SOC_DAPM_OUTPUT("OUT4"),
++SND_SOC_DAPM_OUTPUT("ROP"),
++SND_SOC_DAPM_OUTPUT("RON"),
++
++SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
++};
++
++static const char *audio_map[][3] = {
++ /* Make DACs turn on when playing even if not mixed into any outputs */
++ {"Internal DAC Sink", NULL, "Left DAC"},
++ {"Internal DAC Sink", NULL, "Right DAC"},
++
++ /* Make ADCs turn on when recording even if not mixed from any inputs */
++ {"Left ADC", NULL, "Internal ADC Source"},
++ {"Right ADC", NULL, "Internal ADC Source"},
++
++ /* Input Side */
++ /* LIN12 PGA */
++ {"LIN12 PGA", "LIN1 Switch", "LIN1"},
++ {"LIN12 PGA", "LIN2 Switch", "LIN2"},
++ /* LIN34 PGA */
++ {"LIN34 PGA", "LIN3 Switch", "LIN3"},
++ {"LIN34 PGA", "LIN4 Switch", "LIN4"},
++ /* INMIXL */
++ {"INMIXL", "Record Left Volume", "LOMIX"},
++ {"INMIXL", "LIN2 Volume", "LIN2"},
++ {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
++ {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
++ /* AILNMUX */
++ {"AILNMUX", "INMIXL Mix", "INMIXL"},
++ {"AILNMUX", "DIFFINL Mix", "LIN12PGA"},
++ {"AILNMUX", "DIFFINL Mix", "LIN34PGA"},
++ {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
++ {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
++ /* ADC */
++ {"Left ADC", NULL, "AILNMUX"},
++
++ /* RIN12 PGA */
++ {"RIN12 PGA", "RIN1 Switch", "RIN1"},
++ {"RIN12 PGA", "RIN2 Switch", "RIN2"},
++ /* RIN34 PGA */
++ {"RIN34 PGA", "RIN3 Switch", "RIN3"},
++ {"RIN34 PGA", "RIN4 Switch", "RIN4"},
++ /* INMIXL */
++ {"INMIXR", "Record Right Volume", "ROMIX"},
++ {"INMIXR", "RIN2 Volume", "RIN2"},
++ {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
++ {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
++ /* AIRNMUX */
++ {"AIRNMUX", "INMIXR Mix", "INMIXR"},
++ {"AIRNMUX", "DIFFINR Mix", "RIN12PGA"},
++ {"AIRNMUX", "DIFFINR Mix", "RIN34PGA"},
++ {"AIRNMUX", "RXVOICE Mix", "RIN4/RXN"},
++ {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
++ /* ADC */
++ {"Right ADC", NULL, "AIRNMUX"},
++
++ /* LOMIX */
++ {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
++ {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
++ {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
++ {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
++ {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
++ {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
++ {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
++
++ /* ROMIX */
++ {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
++ {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
++ {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
++ {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
++ {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
++ {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
++ {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
++
++ /* SPKMIX */
++ {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
++ {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
++ {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
++ {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
++ {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
++ {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
++ {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
++ {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
++
++ /* LONMIX */
++ {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
++ {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
++ {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
++
++ /* LOPMIX */
++ {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
++ {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
++ {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
++
++ /* OUT3MIX */
++ {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXP"},
++ {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
++
++ /* OUT4MIX */
++ {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
++ {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
++
++ /* RONMIX */
++ {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
++ {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
++ {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
++
++ /* ROPMIX */
++ {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
++ {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
++ {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
++
++ /* Out Mixer PGAs */
++ {"LOPGA", NULL, "LOMIX"},
++ {"ROPGA", NULL, "ROMIX"},
++
++ {"LOUT PGA", NULL, "LOMIX"},
++ {"ROUT PGA", NULL, "ROMIX"},
++
++ /* Output Pins */
++ {"LON", NULL, "LONMIX"},
++ {"LOP", NULL, "LOPMIX"},
++ {"OUT", NULL, "OUT3MIX"},
++ {"LOUT", NULL, "LOUT PGA"},
++ {"SPKN", NULL, "SPKMIX"},
++ {"ROUT", NULL, "ROUT PGA"},
++ {"OUT4", NULL, "OUT4MIX"},
++ {"ROP", NULL, "ROPMIX"},
++ {"RON", NULL, "RONMIX"},
++
++ /* terminator */
++ {NULL, NULL, NULL},
++};
++
++static int wm8990_add_widgets(struct snd_soc_codec *codec)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(wm8990_dapm_widgets); i++)
++ snd_soc_dapm_new_control(codec, &wm8990_dapm_widgets[i]);
++
++ /* set up the WM8990 audio map */
++ for (i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ snd_soc_dapm_new_widgets(codec);
++ return 0;
++}
++
++/* PLL divisors */
++struct _pll_div {
++ u32 div2;
++ u32 n;
++ u32 k;
++};
++
++/* The size in bits of the pll divide multiplied by 10
++ * to allow rounding later */
++#define FIXED_PLL_SIZE ((1 << 16) * 10)
++
++static void pll_factors(struct _pll_div *pll_div, unsigned int target,
++ unsigned int source)
++{
++ u64 Kpart;
++ unsigned int K, Ndiv, Nmod;
++
++
++ Ndiv = target / source;
++ if (Ndiv < 6) {
++ source >>= 1;
++ pll_div->div2 = 1;
++ Ndiv = target / source;
++ } else
++ pll_div->div2 = 0;
++
++ if ((Ndiv < 6) || (Ndiv > 12))
++ printk(KERN_WARNING
++ "WM8990 N value outwith recommended range! N = %d\n",Ndiv);
++
++ pll_div->n = Ndiv;
++ Nmod = target % source;
++ Kpart = FIXED_PLL_SIZE * (long long)Nmod;
++
++ do_div(Kpart, source);
++
++ K = Kpart & 0xFFFFFFFF;
++
++ /* Check if we need to round */
++ if ((K % 10) >= 5)
++ K += 5;
++
++ /* Move down to proper range now rounding is done */
++ K /= 10;
++
++ pll_div->k = K;
++}
++
++static int wm8990_set_dai_pll(struct snd_soc_codec_dai *codec_dai,
++ int pll_id, unsigned int freq_in, unsigned int freq_out)
++{
++ u16 reg;
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct _pll_div pll_div;
++
++ if (freq_in && freq_out) {
++ pll_factors(&pll_div, freq_out * 4, freq_in);
++
++ /* Turn on PLL */
++ reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
++ reg |= WM8990_PLL_ENA;
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
++
++ /* sysclk comes from PLL */
++ reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2);
++ wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
++
++ /* set up N , fractional mode and pre-divisor if neccessary */
++ wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
++ (pll_div.div2?WM8990_PRESCALE:0));
++ wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
++ wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
++ } else {
++ /* Turn on PLL */
++ reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
++ reg &= ~WM8990_PLL_ENA;
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
++ }
++ return 0;
++}
++
++/*
++ * Clock after PLL and dividers
++ */
++static int wm8990_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct wm8990_priv *wm8990 = codec->private_data;
++
++ wm8990->sysclk = freq;
++ return 0;
++}
++
++/*
++ * Set's ADC and Voice DAC format.
++ */
++static int wm8990_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
++ unsigned int fmt)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ u16 audio1, audio3;
++
++ audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
++ audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3);
++
++ /* set master/slave audio interface */
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ audio3 &= ~WM8990_AIF_MSTR1;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ audio3 |= WM8990_AIF_MSTR1;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ audio1 &= ~WM8990_AIF_FMT_MASK;
++
++ /* interface format */
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ audio1 |= WM8990_AIF_TMF_I2S;
++ audio1 &= ~WM8990_AIF_LRCLK_INV;
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ audio1 |= WM8990_AIF_TMF_RIGHTJ;
++ audio1 &= ~WM8990_AIF_LRCLK_INV;
++ break;
++ case SND_SOC_DAIFMT_LEFT_J:
++ audio1 |= WM8990_AIF_TMF_LEFTJ;
++ audio1 &= ~WM8990_AIF_LRCLK_INV;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ audio1 |= WM8990_AIF_TMF_DSP;
++ audio1 &= ~WM8990_AIF_LRCLK_INV;
++ break;
++ case SND_SOC_DAIFMT_DSP_B:
++ audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
++ wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
++ return 0;
++}
++
++static int wm8990_set_dai_clkdiv(struct snd_soc_codec_dai *codec_dai,
++ int div_id, int div)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ u16 reg;
++
++ switch (div_id) {
++ case WM8990_MCLK_DIV:
++ reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
++ ~WM8990_MCLK_DIV_MASK;
++ wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
++ break;
++ case WM8990_DACCLK_DIV:
++ reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
++ ~WM8990_DAC_CLKDIV_MASK;
++ wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
++ break;
++ case WM8990_ADCCLK_DIV:
++ reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
++ ~WM8990_ADC_CLKDIV_MASK;
++ wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
++ break;
++ case WM8990_BCLK_DIV:
++ reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) &
++ ~WM8990_BCLK_DIV_MASK;
++ wm8990_write(codec, WM8990_CLOCKING_1, reg | div);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * Set PCM DAI bit size and sample rate.
++ */
++static int wm8990_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_device *socdev = rtd->socdev;
++ struct snd_soc_codec *codec = socdev->codec;
++ u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
++
++ audio1 &= ~WM8990_AIF_WL_MASK;
++
++ /* bit size */
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ audio1 |= WM8990_AIF_WL_16BITS;
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ audio1 |= WM8990_AIF_WL_20BITS;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ audio1 |= WM8990_AIF_WL_24BITS;
++ break;
++ case SNDRV_PCM_FORMAT_S32_LE:
++ audio1 |= WM8990_AIF_WL_32BITS;
++ break;
++ }
++
++ wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
++ //wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, 0x4010);
++ return 0;
++}
++
++static int wm8990_mute(struct snd_soc_codec_dai *dai, int mute)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ u16 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
++
++ if (mute)
++ wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
++ else
++ wm8990_write(codec, WM8990_DAC_CTRL, val);
++
++ return 0;
++}
++
++/* TODO: set bias for best performance at standby */
++static int wm8990_dapm_event(struct snd_soc_codec *codec, int event)
++{
++ u16 val;
++
++ switch (event) {
++ case SNDRV_CTL_POWER_D0: /* full On */
++
++ break;
++ case SNDRV_CTL_POWER_D1: /* partial On */
++ case SNDRV_CTL_POWER_D2: /* partial On */
++
++ break;
++ case SNDRV_CTL_POWER_D3hot: /* Off, with power */
++ if (codec->dapm_state == SNDRV_CTL_POWER_D3cold) {
++ /* OFF -> standby */
++
++ /* Enable all output discharge bits */
++ wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
++ WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
++ WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
++ WM8990_DIS_ROUT);
++
++ /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
++ wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
++ WM8990_BUFDCOPEN | WM8990_POBCTRL);
++
++ /* Delay 250ms to allow output caps to discharge */
++ schedule_timeout_interruptible(msecs_to_jiffies(250));
++
++ /* disable all output discharge bits */
++ wm8990_write(codec, WM8990_ANTIPOP1, 0);
++
++ /* Enable VMID SEL = 2x50K Ohm Divider */
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x2);
++
++ /* Delay 100ms to allow VMID to initially charge */
++ schedule_timeout_interruptible(msecs_to_jiffies(250));
++
++ /* Enable VREF (VMID SEL = 2x50K Ohm Divider */
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
++
++ /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
++ wm8990_write(codec, WM8990_ANTIPOP2, 0x0);
++
++ } else {
++ /* ON -> standby */
++
++ }
++ break;
++ case SNDRV_CTL_POWER_D3cold: /* Off, without power */
++
++ /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
++ wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
++ WM8990_BUFDCOPEN | WM8990_POBCTRL);
++
++ /* mute DAC */
++ val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL);
++ wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
++
++ /* Disable VMID SEL = 2x50K Ohm Divider */
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1);
++
++ /* Enable all output discharge bits */
++ wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
++ WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
++ WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
++ WM8990_DIS_ROUT);
++
++ /* Disable VREF (VMID SEL = 2x50K Ohm Divider */
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
++
++ /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
++ wm8990_write(codec, WM8990_ANTIPOP2, 0x0);
++ }
++ codec->dapm_state = event;
++ return 0;
++}
++
++#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
++
++#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
++ SNDRV_PCM_FMTBIT_S24_LE)
++
++/*
++ * The WM8990 supports 2 different and mutually exclusive DAI
++ * configurations.
++ *
++ * 1. ADC/DAC on Primary Interface
++ * 2. ADC on Primary Interface/DAC on secondary
++ */
++struct snd_soc_codec_dai wm8990_dai = {
++/* ADC/DAC on primary */
++ .name = "WM8990 ADC/DAC Primary",
++ .id = 1,
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = WM8990_RATES,
++ .formats = WM8990_FORMATS,},
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = WM8990_RATES,
++ .formats = WM8990_FORMATS,},
++ .ops = {
++ .hw_params = wm8990_hw_params,},
++ .dai_ops = {
++ .digital_mute = wm8990_mute,
++ .set_fmt = wm8990_set_dai_fmt,
++ .set_clkdiv = wm8990_set_dai_clkdiv,
++ .set_pll = wm8990_set_dai_pll,
++ .set_sysclk = wm8990_set_dai_sysclk,
++ },
++};
++EXPORT_SYMBOL_GPL(wm8990_dai);
++
++static int wm8990_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++
++ /* we only need to suspend if we are a valid card */
++ if(!codec->card)
++ return 0;
++
++ wm8990_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
++ return 0;
++}
++
++static int wm8990_resume(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++ int i;
++ u8 data[2];
++ u16 *cache = codec->reg_cache;
++
++ /* we only need to resume if we are a valid card */
++ if (!codec->card)
++ return 0;
++
++ /* Sync reg_cache with the hardware */
++ for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
++ if (i + 1 == WM8990_RESET)
++ continue;
++ data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
++ data[1] = cache[i] & 0x00ff;
++ codec->hw_write(codec->control_data, data, 2);
++ }
++
++ wm8990_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
++ return 0;
++}
++
++/*
++ * initialise the WM8990 driver
++ * register the mixer and dsp interfaces with the kernel
++ */
++static int wm8990_init(struct snd_soc_device *socdev)
++{
++ struct snd_soc_codec *codec = socdev->codec;
++ u16 reg;
++ int ret = 0;
++
++ codec->name = "WM8990";
++ codec->owner = THIS_MODULE;
++ codec->read = wm8990_read_reg_cache;
++ codec->write = wm8990_write;
++ codec->dapm_event = wm8990_dapm_event;
++ codec->dai = &wm8990_dai;
++ codec->num_dai = 2;
++ codec->reg_cache_size = sizeof(wm8990_reg);
++ codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL);
++
++ if (codec->reg_cache == NULL)
++ return -ENOMEM;
++
++ wm8990_reset(codec);
++
++#if (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) || (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990_MODULE)
++ /* Enable the left and right output mixers by default so a
++ headphone output path will work */
++ printk("Entered : %s, %d 8990 write..\n",__FUNCTION__,__LINE__);
++ wm8990_write(codec, WM8990_OUTPUT_MIXER1, WM8990_LDLO);
++ wm8990_write(codec, WM8990_OUTPUT_MIXER2, WM8990_RDRO);
++#endif
++
++#if (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) || (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990_MODULE)
++ /* Enable the left and right output mixers by default so a
++ headphone output path will work */
++ wm8990_write(codec, WM8990_OUTPUT_MIXER1, WM8990_LDLO);
++ wm8990_write(codec, WM8990_OUTPUT_MIXER2, WM8990_RDRO);
++#endif
++
++#if (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) || (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990_MODULE)
++ /* Enable the left and right output mixers by default so a
++ headphone output path will work */
++ wm8990_write(codec, WM8990_OUTPUT_MIXER1, WM8990_LDLO);
++ wm8990_write(codec, WM8990_OUTPUT_MIXER2, WM8990_RDRO);
++#endif
++
++ /* register pcms */
++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
++ if (ret < 0) {
++ printk(KERN_ERR "wm8990: failed to create pcms\n");
++ goto pcm_err;
++ }
++
++ /* charge output caps */
++ codec->dapm_state = SNDRV_CTL_POWER_D3cold;
++ wm8990_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
++
++ /* set up ADCLR clock internally */
++ //reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4);
++ //wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
++
++ /* set GPIO1 as clk output */
++ //reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) &
++// ~WM8990_GPIO1_SEL_MASK;
++// wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
++
++// set Line-In and Mic-In Path.
++//
++ reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
++
++ wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
++ wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
++
++ reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_AINR_ENA | WM8990_ADCR_ENA | WM8990_ADCL_ENA);
++
++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER5);
++ wm8990_write(codec, WM8990_INPUT_MIXER5, (reg & ~WM8990_LI2BVOL_MASK) | (0x50 | (1<<8)));
++
++ wm8990_write(codec, WM8990_LEFT_ADC_DIGITAL_VOLUME, 0xff | (1<<8));
++
++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER6);
++ wm8990_write(codec, WM8990_INPUT_MIXER6, (reg & ~WM8990_RI2BVOL_MASK) | (0x50 | (1<<8)));
++
++ wm8990_write(codec, WM8990_RIGHT_ADC_DIGITAL_VOLUME, 0xff | (1<<8));
++
++ reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_LIN12_ENA | WM8990_AINL_ENA);
++
++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER2);
++ wm8990_write(codec, WM8990_INPUT_MIXER2, reg | WM8990_LMN1);
++
++ reg = wm8990_read_reg_cache(codec, WM8990_LEFT_LINE_INPUT_1_2_VOLUME);
++ wm8990_write(codec, WM8990_LEFT_LINE_INPUT_1_2_VOLUME, (reg & ~WM8990_LIN12VOL_MASK) | (0x5f | (1<<8)));
++
++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER4);
++ wm8990_write(codec, WM8990_INPUT_MIXER4, (reg & ~WM8990_RDBVOL_MASK) | (0x5f | (1<<8)));
++
++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER3);
++ wm8990_write(codec, WM8990_INPUT_MIXER3, reg | WM8990_L12MNB);
++
++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER3);
++ wm8990_write(codec, WM8990_INPUT_MIXER3, reg | WM8990_L12MNBST);
++
++#if defined(CONFIG_SOUND_WM8990_INPUT_STREAM_MIC_IN)
++ /* For Mono MIC-In */
++ reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
++ wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, reg & (0<<14));
++
++#endif
++
++ wm8990_add_controls(codec);
++ wm8990_add_widgets(codec);
++ ret = snd_soc_register_card(socdev);
++ if (ret < 0) {
++ printk(KERN_ERR "wm8990: failed to register card\n");
++ goto card_err;
++ }
++ return ret;
++
++card_err:
++ snd_soc_free_pcms(socdev);
++ snd_soc_dapm_free(socdev);
++pcm_err:
++ kfree(codec->reg_cache);
++ return ret;
++}
++
++/* If the i2c layer weren't so broken, we could pass this kind of data
++ around */
++static struct snd_soc_device *wm8990_socdev;
++
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++
++/*
++ * WM8912 wire address is determined by GPIO5
++ * state during powerup.
++ * low = 0x34
++ * high = 0x36
++ */
++static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
++
++/* Magic definition of all other variables and things */
++I2C_CLIENT_INSMOD;
++
++static struct i2c_driver wm8990_i2c_driver;
++static struct i2c_client client_template;
++
++static int wm8990_codec_probe(struct i2c_adapter *adap, int addr, int kind)
++{
++ struct snd_soc_device *socdev = wm8990_socdev;
++ struct wm8990_setup_data *setup = socdev->codec_data;
++ struct snd_soc_codec *codec = socdev->codec;
++ struct i2c_client *i2c;
++ int ret;
++
++ if (addr != setup->i2c_address)
++ return -ENODEV;
++
++ client_template.adapter = adap;
++ client_template.addr = addr;
++
++ i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
++ if (i2c == NULL){
++ kfree(codec);
++ return -ENOMEM;
++ }
++ i2c_set_clientdata(i2c, codec);
++ codec->control_data = i2c;
++
++ ret = i2c_attach_client(i2c);
++ if (ret < 0) {
++ err("failed to attach codec at addr %x\n", addr);
++ goto err;
++ }
++
++ ret = wm8990_init(socdev);
++ if (ret < 0) {
++ err("failed to initialise WM8990\n");
++ goto err;
++ }
++ return ret;
++
++err:
++ kfree(codec);
++ kfree(i2c);
++ return ret;
++}
++
++static int wm8990_i2c_detach(struct i2c_client *client)
++{
++ struct snd_soc_codec *codec = i2c_get_clientdata(client);
++ i2c_detach_client(client);
++ kfree(codec->reg_cache);
++ kfree(client);
++ return 0;
++}
++
++static int wm8990_i2c_attach(struct i2c_adapter *adap)
++{
++ return i2c_probe(adap, &addr_data, wm8990_codec_probe);
++}
++
++/* corgi i2c codec control layer */
++static struct i2c_driver wm8990_i2c_driver = {
++ .driver = {
++ .name = "WM8990 I2C Codec",
++ .owner = THIS_MODULE,
++ },
++ .id = I2C_DRIVERID_WM8753,
++ .attach_adapter = wm8990_i2c_attach,
++ .detach_client = wm8990_i2c_detach,
++ .command = NULL,
++};
++
++static struct i2c_client client_template = {
++ .name = "WM8990",
++ .driver = &wm8990_i2c_driver,
++};
++#endif
++
++static int wm8990_probe(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct wm8990_setup_data *setup;
++ struct snd_soc_codec *codec;
++ struct wm8990_priv *wm8990;
++ int ret = 0;
++
++ info("WM8990 Audio Codec %s", WM8990_VERSION);
++
++ setup = socdev->codec_data;
++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
++ if (codec == NULL)
++ return -ENOMEM;
++
++ wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
++ if (wm8990 == NULL) {
++ kfree(codec);
++ return -ENOMEM;
++ }
++
++ codec->private_data = wm8990;
++ socdev->codec = codec;
++ mutex_init(&codec->mutex);
++ INIT_LIST_HEAD(&codec->dapm_widgets);
++ INIT_LIST_HEAD(&codec->dapm_paths);
++ wm8990_socdev = socdev;
++
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++ if (setup->i2c_address) {
++ normal_i2c[0] = setup->i2c_address;
++ codec->hw_write = (hw_write_t)i2c_master_send;
++ ret = i2c_add_driver(&wm8990_i2c_driver);
++ if (ret != 0)
++ printk(KERN_ERR "can't add i2c driver");
++ }
++#else
++ /* Add other interfaces here */
++#endif
++ return ret;
++}
++
++/* power down chip */
++static int wm8990_remove(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++
++ if (codec->control_data)
++ wm8990_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
++ snd_soc_free_pcms(socdev);
++ snd_soc_dapm_free(socdev);
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++ i2c_del_driver(&wm8990_i2c_driver);
++#endif
++ kfree(codec->private_data);
++ kfree(codec);
++
++ return 0;
++}
++
++struct snd_soc_codec_device soc_codec_dev_wm8990 = {
++ .probe = wm8990_probe,
++ .remove = wm8990_remove,
++ .suspend = wm8990_suspend,
++ .resume = wm8990_resume,
++};
++
++EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990);
++
++MODULE_DESCRIPTION("ASoC WM8990 driver");
++MODULE_AUTHOR("Liam Girdwood");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/codecs/wm8990.h b/sound/soc/codecs/wm8990.h
+new file mode 100644
+index 0000000..f98c026
+--- /dev/null
++++ b/sound/soc/codecs/wm8990.h
+@@ -0,0 +1,904 @@
++/*
++ * wm8753.h -- audio driver for WM8753
++ *
++ * Copyright 2007 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#ifndef __WM8990REGISTERDEFS_H__
++#define __WM8990REGISTERDEFS_H__
++
++/*
++ * Register values.
++ */
++#define WM8990_RESET 0x00
++#define WM8990_POWER_MANAGEMENT_1 0x01
++#define WM8990_POWER_MANAGEMENT_2 0x02
++#define WM8990_POWER_MANAGEMENT_3 0x03
++#define WM8990_AUDIO_INTERFACE_1 0x04
++#define WM8990_AUDIO_INTERFACE_2 0x05
++#define WM8990_CLOCKING_1 0x06
++#define WM8990_CLOCKING_2 0x07
++#define WM8990_AUDIO_INTERFACE_3 0x08
++#define WM8990_AUDIO_INTERFACE_4 0x09
++#define WM8990_DAC_CTRL 0x0A
++#define WM8990_LEFT_DAC_DIGITAL_VOLUME 0x0B
++#define WM8990_RIGHT_DAC_DIGITAL_VOLUME 0x0C
++#define WM8990_DIGITAL_SIDE_TONE 0x0D
++#define WM8990_ADC_CTRL 0x0E
++#define WM8990_LEFT_ADC_DIGITAL_VOLUME 0x0F
++#define WM8990_RIGHT_ADC_DIGITAL_VOLUME 0x10
++#define WM8990_GPIO_CTRL_1 0x12
++#define WM8990_GPIO1_GPIO2 0x13
++#define WM8990_GPIO3_GPIO4 0x14
++#define WM8990_GPIO5_GPIO6 0x15
++#define WM8990_GPIOCTRL_2 0x16
++#define WM8990_GPIO_POL 0x17
++#define WM8990_LEFT_LINE_INPUT_1_2_VOLUME 0x18
++#define WM8990_LEFT_LINE_INPUT_3_4_VOLUME 0x19
++#define WM8990_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
++#define WM8990_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
++#define WM8990_LEFT_OUTPUT_VOLUME 0x1C
++#define WM8990_RIGHT_OUTPUT_VOLUME 0x1D
++#define WM8990_LINE_OUTPUTS_VOLUME 0x1E
++#define WM8990_OUT3_4_VOLUME 0x1F
++#define WM8990_LEFT_OPGA_VOLUME 0x20
++#define WM8990_RIGHT_OPGA_VOLUME 0x21
++#define WM8990_SPEAKER_VOLUME 0x22
++#define WM8990_CLASSD1 0x23
++#define WM8990_CLASSD3 0x25
++#define WM8990_INPUT_MIXER1 0x27
++#define WM8990_INPUT_MIXER2 0x28
++#define WM8990_INPUT_MIXER3 0x29
++#define WM8990_INPUT_MIXER4 0x2A
++#define WM8990_INPUT_MIXER5 0x2B
++#define WM8990_INPUT_MIXER6 0x2C
++#define WM8990_OUTPUT_MIXER1 0x2D
++#define WM8990_OUTPUT_MIXER2 0x2E
++#define WM8990_OUTPUT_MIXER3 0x2F
++#define WM8990_OUTPUT_MIXER4 0x30
++#define WM8990_OUTPUT_MIXER5 0x31
++#define WM8990_OUTPUT_MIXER6 0x32
++#define WM8990_OUT3_4_MIXER 0x33
++#define WM8990_LINE_MIXER1 0x34
++#define WM8990_LINE_MIXER2 0x35
++#define WM8990_SPEAKER_MIXER 0x36
++#define WM8990_ADDITIONAL_CONTROL 0x37
++#define WM8990_ANTIPOP1 0x38
++#define WM8990_ANTIPOP2 0x39
++#define WM8990_MICBIAS 0x3A
++#define WM8990_PLL1 0x3C
++#define WM8990_PLL2 0x3D
++#define WM8990_PLL3 0x3E
++#define WM8990_INTDRIVBITS 0x3F
++
++#define WM8990_REGISTER_COUNT 60
++#define WM8990_MAX_REGISTER 0x3F
++
++/*
++ * Field Definitions.
++ */
++
++/*
++ * R0 (0x00) - Reset
++ */
++#define WM8990_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID - [15:0] */
++
++/*
++ * R1 (0x01) - Power Management (1)
++ */
++#define WM8990_SPK_ENA 0x1000 /* SPK_ENA */
++#define WM8990_SPK_ENA_BIT 12
++#define WM8990_OUT3_ENA 0x0800 /* OUT3_ENA */
++#define WM8990_OUT3_ENA_BIT 11
++#define WM8990_OUT4_ENA 0x0400 /* OUT4_ENA */
++#define WM8990_OUT4_ENA_BIT 10
++#define WM8990_LOUT_ENA 0x0200 /* LOUT_ENA */
++#define WM8990_LOUT_ENA_BIT 9
++#define WM8990_ROUT_ENA 0x0100 /* ROUT_ENA */
++#define WM8990_ROUT_ENA_BIT 8
++#define WM8990_MICBIAS_ENA 0x0010 /* MICBIAS_ENA */
++#define WM8990_MICBIAS_ENA_BIT 4
++#define WM8990_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
++#define WM8990_VREF_ENA 0x0001 /* VREF_ENA */
++#define WM8990_VREF_ENA_BIT 0
++
++/*
++ * R2 (0x02) - Power Management (2)
++ */
++#define WM8990_PLL_ENA 0x8000 /* PLL_ENA */
++#define WM8990_PLL_ENA_BIT 15
++#define WM8990_TSHUT_ENA 0x4000 /* TSHUT_ENA */
++#define WM8990_TSHUT_ENA_BIT 14
++#define WM8990_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
++#define WM8990_TSHUT_OPDIS_BIT 13
++#define WM8990_OPCLK_ENA 0x0800 /* OPCLK_ENA */
++#define WM8990_OPCLK_ENA_BIT 11
++#define WM8990_AINL_ENA 0x0200 /* AINL_ENA */
++#define WM8990_AINL_ENA_BIT 9
++#define WM8990_AINR_ENA 0x0100 /* AINR_ENA */
++#define WM8990_AINR_ENA_BIT 8
++#define WM8990_LIN34_ENA 0x0080 /* LIN34_ENA */
++#define WM8990_LIN34_ENA_BIT 7
++#define WM8990_LIN12_ENA 0x0040 /* LIN12_ENA */
++#define WM8990_LIN12_ENA_BIT 6
++#define WM8990_RIN34_ENA 0x0020 /* RIN34_ENA */
++#define WM8990_RIN34_ENA_BIT 5
++#define WM8990_RIN12_ENA 0x0010 /* RIN12_ENA */
++#define WM8990_RIN12_ENA_BIT 4
++#define WM8990_ADCL_ENA 0x0002 /* ADCL_ENA */
++#define WM8990_ADCL_ENA_BIT 1
++#define WM8990_ADCR_ENA 0x0001 /* ADCR_ENA */
++#define WM8990_ADCR_ENA_BIT 0
++
++/*
++ * R3 (0x03) - Power Management (3)
++ */
++#define WM8990_LON_ENA 0x2000 /* LON_ENA */
++#define WM8990_LON_ENA_BIT 13
++#define WM8990_LOP_ENA 0x1000 /* LOP_ENA */
++#define WM8990_LOP_ENA_BIT 12
++#define WM8990_RON_ENA 0x0800 /* RON_ENA */
++#define WM8990_RON_ENA_BIT 11
++#define WM8990_ROP_ENA 0x0400 /* ROP_ENA */
++#define WM8990_ROP_ENA_BIT 10
++#define WM8990_LOPGA_ENA 0x0080 /* LOPGA_ENA */
++#define WM8990_LOPGA_ENA_BIT 7
++#define WM8990_ROPGA_ENA 0x0040 /* ROPGA_ENA */
++#define WM8990_ROPGA_ENA_BIT 6
++#define WM8990_LOMIX_ENA 0x0020 /* LOMIX_ENA */
++#define WM8990_LOMIX_ENA_BIT 5
++#define WM8990_ROMIX_ENA 0x0010 /* ROMIX_ENA */
++#define WM8990_ROMIX_ENA_BIT 4
++#define WM8990_DACL_ENA 0x0002 /* DACL_ENA */
++#define WM8990_DACL_ENA_BIT 1
++#define WM8990_DACR_ENA 0x0001 /* DACR_ENA */
++#define WM8990_DACR_ENA_BIT 0
++
++/*
++ * R4 (0x04) - Audio Interface (1)
++ */
++#define WM8990_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
++#define WM8990_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
++#define WM8990_AIFADC_TDM 0x2000 /* AIFADC_TDM */
++#define WM8990_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
++#define WM8990_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
++#define WM8990_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
++#define WM8990_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
++#define WM8990_AIF_WL_16BITS (0 << 5)
++#define WM8990_AIF_WL_20BITS (1 << 5)
++#define WM8990_AIF_WL_24BITS (2 << 5)
++#define WM8990_AIF_WL_32BITS (3 << 5)
++#define WM8990_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
++#define WM8990_AIF_TMF_RIGHTJ (0 << 3)
++#define WM8990_AIF_TMF_LEFTJ (1 << 3)
++#define WM8990_AIF_TMF_I2S (2 << 3)
++#define WM8990_AIF_TMF_DSP (3 << 3)
++
++/*
++ * R5 (0x05) - Audio Interface (2)
++ */
++#define WM8990_DACL_SRC 0x8000 /* DACL_SRC */
++#define WM8990_DACR_SRC 0x4000 /* DACR_SRC */
++#define WM8990_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
++#define WM8990_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
++#define WM8990_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */
++#define WM8990_DAC_COMP 0x0010 /* DAC_COMP */
++#define WM8990_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
++#define WM8990_ADC_COMP 0x0004 /* ADC_COMP */
++#define WM8990_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
++#define WM8990_LOOPBACK 0x0001 /* LOOPBACK */
++
++/*
++ * R6 (0x06) - Clocking (1)
++ */
++#define WM8990_TOCLK_RATE 0x8000 /* TOCLK_RATE */
++#define WM8990_TOCLK_ENA 0x4000 /* TOCLK_ENA */
++#define WM8990_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
++#define WM8990_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
++#define WM8990_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
++#define WM8990_BCLK_DIV_1 (0x0 << 1)
++#define WM8990_BCLK_DIV_1_5 (0x1 << 1)
++#define WM8990_BCLK_DIV_2 (0x2 << 1)
++#define WM8990_BCLK_DIV_3 (0x3 << 1)
++#define WM8990_BCLK_DIV_4 (0x4 << 1)
++#define WM8990_BCLK_DIV_5_5 (0x5 << 1)
++#define WM8990_BCLK_DIV_6 (0x6 << 1)
++#define WM8990_BCLK_DIV_8 (0x7 << 1)
++#define WM8990_BCLK_DIV_11 (0x8 << 1)
++#define WM8990_BCLK_DIV_12 (0x9 << 1)
++#define WM8990_BCLK_DIV_16 (0xA << 1)
++#define WM8990_BCLK_DIV_22 (0xB << 1)
++#define WM8990_BCLK_DIV_24 (0xC << 1)
++#define WM8990_BCLK_DIV_32 (0xD << 1)
++#define WM8990_BCLK_DIV_44 (0xE << 1)
++#define WM8990_BCLK_DIV_48 (0xF << 1)
++
++/*
++ * R7 (0x07) - Clocking (2)
++ */
++#define WM8990_MCLK_SRC 0x8000 /* MCLK_SRC */
++#define WM8990_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
++#define WM8990_CLK_FORCE 0x2000 /* CLK_FORCE */
++#define WM8990_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
++#define WM8990_MCLK_DIV_1 ( 0 << 11)
++#define WM8990_MCLK_DIV_2 ( 2 << 11)
++#define WM8990_MCLK_INV 0x0400 /* MCLK_INV */
++#define WM8990_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */
++#define WM8990_ADC_CLKDIV_1 ( 0 << 5)
++#define WM8990_ADC_CLKDIV_1_5 ( 1 << 5)
++#define WM8990_ADC_CLKDIV_2 ( 2 << 5)
++#define WM8990_ADC_CLKDIV_3 ( 3 << 5)
++#define WM8990_ADC_CLKDIV_4 ( 4 << 5)
++#define WM8990_ADC_CLKDIV_5_5 ( 5 << 5)
++#define WM8990_ADC_CLKDIV_6 ( 6 << 5)
++#define WM8990_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
++#define WM8990_DAC_CLKDIV_1 ( 0 << 2)
++#define WM8990_DAC_CLKDIV_1_5 ( 1 << 2)
++#define WM8990_DAC_CLKDIV_2 ( 2 << 2)
++#define WM8990_DAC_CLKDIV_3 ( 3 << 2)
++#define WM8990_DAC_CLKDIV_4 ( 4 << 2)
++#define WM8990_DAC_CLKDIV_5_5 ( 5 << 2)
++#define WM8990_DAC_CLKDIV_6 ( 6 << 2)
++
++/*
++ * R8 (0x08) - Audio Interface (3)
++ */
++#define WM8990_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
++#define WM8990_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
++#define WM8990_AIF_SEL 0x2000 /* AIF_SEL */
++#define WM8990_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
++#define WM8990_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */
++
++/*
++ * R9 (0x09) - Audio Interface (4)
++ */
++#define WM8990_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
++#define WM8990_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
++#define WM8990_AIF_TRIS 0x2000 /* AIF_TRIS */
++#define WM8990_DACLRC_DIR 0x0800 /* DACLRC_DIR */
++#define WM8990_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */
++
++/*
++ * R10 (0x0A) - DAC CTRL
++ */
++#define WM8990_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
++#define WM8990_DAC_MONO 0x0200 /* DAC_MONO */
++#define WM8990_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */
++#define WM8990_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */
++#define WM8990_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */
++#define WM8990_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */
++#define WM8990_DAC_MUTE 0x0004 /* DAC_MUTE */
++#define WM8990_DACL_DATINV 0x0002 /* DACL_DATINV */
++#define WM8990_DACR_DATINV 0x0001 /* DACR_DATINV */
++
++/*
++ * R11 (0x0B) - Left DAC Digital Volume
++ */
++#define WM8990_DAC_VU 0x0100 /* DAC_VU */
++#define WM8990_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
++#define WM8990_DACL_VOL_SHIFT 0
++/*
++ * R12 (0x0C) - Right DAC Digital Volume
++ */
++#define WM8990_DAC_VU 0x0100 /* DAC_VU */
++#define WM8990_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
++#define WM8990_DACR_VOL_SHIFT 0
++/*
++ * R13 (0x0D) - Digital Side Tone
++ */
++#define WM8990_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL - [12:9] */
++#define WM8990_ADCL_DAC_SVOL_SHIFT 9
++#define WM8990_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL - [8:5] */
++#define WM8990_ADCR_DAC_SVOL_SHIFT 5
++#define WM8990_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */
++#define WM8990_ADC_TO_DACL_SHIFT 2
++#define WM8990_ADC_TO_DACR_MASK 0x03 /* ADC_TO_DACR - [1:0] */
++#define WM8990_ADC_TO_DACR_SHIFT 0
++
++/*
++ * R14 (0x0E) - ADC CTRL
++ */
++#define WM8990_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */
++#define WM8990_ADC_HPF_ENA_BIT 8
++#define WM8990_ADC_HPF_CUT_MASK 0x03 /* ADC_HPF_CUT - [6:5] */
++#define WM8990_ADC_HPF_CUT_SHIFT 5
++#define WM8990_ADCL_DATINV 0x0002 /* ADCL_DATINV */
++#define WM8990_ADCL_DATINV_BIT 1
++#define WM8990_ADCR_DATINV 0x0001 /* ADCR_DATINV */
++#define WM8990_ADCR_DATINV_BIT 0
++
++/*
++ * R15 (0x0F) - Left ADC Digital Volume
++ */
++#define WM8990_ADC_VU 0x0100 /* ADC_VU */
++#define WM8990_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
++#define WM8990_ADCL_VOL_SHIFT 0
++
++/*
++ * R16 (0x10) - Right ADC Digital Volume
++ */
++#define WM8990_ADC_VU 0x0100 /* ADC_VU */
++#define WM8990_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
++#define WM8990_ADCR_VOL_SHIFT 0
++
++/*
++ * R18 (0x12) - GPIO CTRL 1
++ */
++#define WM8990_IRQ 0x1000 /* IRQ */
++#define WM8990_TEMPOK 0x0800 /* TEMPOK */
++#define WM8990_MICSHRT 0x0400 /* MICSHRT */
++#define WM8990_MICDET 0x0200 /* MICDET */
++#define WM8990_PLL_LCK 0x0100 /* PLL_LCK */
++#define WM8990_GPI8_STATUS 0x0080 /* GPI8_STATUS */
++#define WM8990_GPI7_STATUS 0x0040 /* GPI7_STATUS */
++#define WM8990_GPIO6_STATUS 0x0020 /* GPIO6_STATUS */
++#define WM8990_GPIO5_STATUS 0x0010 /* GPIO5_STATUS */
++#define WM8990_GPIO4_STATUS 0x0008 /* GPIO4_STATUS */
++#define WM8990_GPIO3_STATUS 0x0004 /* GPIO3_STATUS */
++#define WM8990_GPIO2_STATUS 0x0002 /* GPIO2_STATUS */
++#define WM8990_GPIO1_STATUS 0x0001 /* GPIO1_STATUS */
++
++/*
++ * R19 (0x13) - GPIO1 & GPIO2
++ */
++#define WM8990_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
++#define WM8990_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
++#define WM8990_GPIO2_PU 0x2000 /* GPIO2_PU */
++#define WM8990_GPIO2_PD 0x1000 /* GPIO2_PD */
++#define WM8990_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
++#define WM8990_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
++#define WM8990_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
++#define WM8990_GPIO1_PU 0x0020 /* GPIO1_PU */
++#define WM8990_GPIO1_PD 0x0010 /* GPIO1_PD */
++#define WM8990_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
++
++/*
++ * R20 (0x14) - GPIO3 & GPIO4
++ */
++#define WM8990_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
++#define WM8990_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
++#define WM8990_GPIO4_PU 0x2000 /* GPIO4_PU */
++#define WM8990_GPIO4_PD 0x1000 /* GPIO4_PD */
++#define WM8990_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
++#define WM8990_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
++#define WM8990_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
++#define WM8990_GPIO3_PU 0x0020 /* GPIO3_PU */
++#define WM8990_GPIO3_PD 0x0010 /* GPIO3_PD */
++#define WM8990_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
++
++/*
++ * R21 (0x15) - GPIO5 & GPIO6
++ */
++#define WM8990_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
++#define WM8990_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
++#define WM8990_GPIO6_PU 0x2000 /* GPIO6_PU */
++#define WM8990_GPIO6_PD 0x1000 /* GPIO6_PD */
++#define WM8990_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
++#define WM8990_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
++#define WM8990_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
++#define WM8990_GPIO5_PU 0x0020 /* GPIO5_PU */
++#define WM8990_GPIO5_PD 0x0010 /* GPIO5_PD */
++#define WM8990_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
++
++/*
++ * R22 (0x16) - GPIOCTRL 2
++ */
++#define WM8990_RD_3W_ENA 0x8000 /* RD_3W_ENA */
++#define WM8990_MODE_3W4W 0x4000 /* MODE_3W4W */
++#define WM8990_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
++#define WM8990_MICSHRT_IRQ_ENA 0x0400 /* MICSHRT_IRQ_ENA */
++#define WM8990_MICDET_IRQ_ENA 0x0200 /* MICDET_IRQ_ENA */
++#define WM8990_PLL_LCK_IRQ_ENA 0x0100 /* PLL_LCK_IRQ_ENA */
++#define WM8990_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
++#define WM8990_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
++#define WM8990_GPI8_ENA 0x0010 /* GPI8_ENA */
++#define WM8990_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
++#define WM8990_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
++#define WM8990_GPI7_ENA 0x0001 /* GPI7_ENA */
++
++/*
++ * R23 (0x17) - GPIO_POL
++ */
++#define WM8990_IRQ_INV 0x1000 /* IRQ_INV */
++#define WM8990_TEMPOK_POL 0x0800 /* TEMPOK_POL */
++#define WM8990_MICSHRT_POL 0x0400 /* MICSHRT_POL */
++#define WM8990_MICDET_POL 0x0200 /* MICDET_POL */
++#define WM8990_PLL_LCK_POL 0x0100 /* PLL_LCK_POL */
++#define WM8990_GPI8_POL 0x0080 /* GPI8_POL */
++#define WM8990_GPI7_POL 0x0040 /* GPI7_POL */
++#define WM8990_GPIO6_POL 0x0020 /* GPIO6_POL */
++#define WM8990_GPIO5_POL 0x0010 /* GPIO5_POL */
++#define WM8990_GPIO4_POL 0x0008 /* GPIO4_POL */
++#define WM8990_GPIO3_POL 0x0004 /* GPIO3_POL */
++#define WM8990_GPIO2_POL 0x0002 /* GPIO2_POL */
++#define WM8990_GPIO1_POL 0x0001 /* GPIO1_POL */
++
++/*
++ * R24 (0x18) - Left Line Input 1&2 Volume
++ */
++#define WM8990_IPVU 0x0100 /* IPVU */
++#define WM8990_LI12MUTE 0x0080 /* LI12MUTE */
++#define WM8990_LI12MUTE_BIT 7
++#define WM8990_LI12ZC 0x0040 /* LI12ZC */
++#define WM8990_LI12ZC_BIT 6
++#define WM8990_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */
++#define WM8990_LIN12VOL_SHIFT 0
++/*
++ * R25 (0x19) - Left Line Input 3&4 Volume
++ */
++#define WM8990_IPVU 0x0100 /* IPVU */
++#define WM8990_LI34MUTE 0x0080 /* LI34MUTE */
++#define WM8990_LI34MUTE_BIT 7
++#define WM8990_LI34ZC 0x0040 /* LI34ZC */
++#define WM8990_LI34ZC_BIT 6
++#define WM8990_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */
++#define WM8990_LIN34VOL_SHIFT 0
++
++/*
++ * R26 (0x1A) - Right Line Input 1&2 Volume
++ */
++#define WM8990_IPVU 0x0100 /* IPVU */
++#define WM8990_RI12MUTE 0x0080 /* RI12MUTE */
++#define WM8990_RI12MUTE_BIT 7
++#define WM8990_RI12ZC 0x0040 /* RI12ZC */
++#define WM8990_RI12ZC_BIT 6
++#define WM8990_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */
++#define WM8990_RIN12VOL_SHIFT 0
++
++/*
++ * R27 (0x1B) - Right Line Input 3&4 Volume
++ */
++#define WM8990_IPVU 0x0100 /* IPVU */
++#define WM8990_RI34MUTE 0x0080 /* RI34MUTE */
++#define WM8990_RI34MUTE_BIT 7
++#define WM8990_RI34ZC 0x0040 /* RI34ZC */
++#define WM8990_RI34ZC_BIT 6
++#define WM8990_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */
++#define WM8990_RIN34VOL_SHIFT 0
++
++/*
++ * R28 (0x1C) - Left Output Volume
++ */
++#define WM8990_OPVU 0x0100 /* OPVU */
++#define WM8990_LOZC 0x0080 /* LOZC */
++#define WM8990_LOZC_BIT 7
++#define WM8990_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */
++#define WM8990_LOUTVOL_SHIFT 0
++/*
++ * R29 (0x1D) - Right Output Volume
++ */
++#define WM8990_OPVU 0x0100 /* OPVU */
++#define WM8990_ROZC 0x0080 /* ROZC */
++#define WM8990_ROZC_BIT 7
++#define WM8990_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */
++#define WM8990_ROUTVOL_SHIFT 0
++/*
++ * R30 (0x1E) - Line Outputs Volume
++ */
++#define WM8990_LONMUTE 0x0040 /* LONMUTE */
++#define WM8990_LONMUTE_BIT 6
++#define WM8990_LOPMUTE 0x0020 /* LOPMUTE */
++#define WM8990_LOPMUTE_BIT 5
++#define WM8990_LOATTN 0x0010 /* LOATTN */
++#define WM8990_LOATTN_BIT 4
++#define WM8990_RONMUTE 0x0004 /* RONMUTE */
++#define WM8990_RONMUTE_BIT 2
++#define WM8990_ROPMUTE 0x0002 /* ROPMUTE */
++#define WM8990_ROPMUTE_BIT 1
++#define WM8990_ROATTN 0x0001 /* ROATTN */
++#define WM8990_ROATTN_BIT 0
++
++/*
++ * R31 (0x1F) - Out3/4 Volume
++ */
++#define WM8990_OUT3MUTE 0x0020 /* OUT3MUTE */
++#define WM8990_OUT3MUTE_BIT 5
++#define WM8990_OUT3ATTN 0x0010 /* OUT3ATTN */
++#define WM8990_OUT3ATTN_BIT 4
++#define WM8990_OUT4MUTE 0x0002 /* OUT4MUTE */
++#define WM8990_OUT4MUTE_BIT 1
++#define WM8990_OUT4ATTN 0x0001 /* OUT4ATTN */
++#define WM8990_OUT4ATTN_BIT 0
++
++/*
++ * R32 (0x20) - Left OPGA Volume
++ */
++#define WM8990_OPVU 0x0100 /* OPVU */
++#define WM8990_LOPGAZC 0x0080 /* LOPGAZC */
++#define WM8990_LOPGAZC_BIT 7
++#define WM8990_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */
++#define WM8990_LOPGAVOL_SHIFT 0
++
++/*
++ * R33 (0x21) - Right OPGA Volume
++ */
++#define WM8990_OPVU 0x0100 /* OPVU */
++#define WM8990_ROPGAZC 0x0080 /* ROPGAZC */
++#define WM8990_ROPGAZC_BIT 7
++#define WM8990_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */
++#define WM8990_ROPGAVOL_SHIFT 0
++/*
++ * R34 (0x22) - Speaker Volume
++ */
++#define WM8990_SPKVOL_MASK 0x0003 /* SPKVOL - [1:0] */
++#define WM8990_SPKVOL_SHIFT 0
++
++/*
++ * R35 (0x23) - ClassD1
++ */
++#define WM8990_CDMODE 0x0100 /* CDMODE */
++#define WM8990_CDMODE_BIT 8
++
++/*
++ * R37 (0x25) - ClassD3
++ */
++#define WM8990_DCGAIN_MASK 0x0007 /* DCGAIN - [5:3] */
++#define WM8990_DCGAIN_SHIFT 3
++#define WM8990_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */
++#define WM8990_ACGAIN_SHIFT 0
++/*
++ * R39 (0x27) - Input Mixer1
++ */
++#define WM8990_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */
++#define WM8990_AINLMODE_SHIFT 2
++#define WM8990_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */
++#define WM8990_AINRMODE_SHIFT 0
++
++/*
++ * R40 (0x28) - Input Mixer2
++ */
++#define WM8990_LMP4 0x0080 /* LMP4 */
++#define WM8990_LMP4_BIT 7 /* LMP4 */
++#define WM8990_LMN3 0x0040 /* LMN3 */
++#define WM8990_LMN3_BIT 6 /* LMN3 */
++#define WM8990_LMP2 0x0020 /* LMP2 */
++#define WM8990_LMP2_BIT 5 /* LMP2 */
++#define WM8990_LMN1 0x0010 /* LMN1 */
++#define WM8990_LMN1_BIT 4 /* LMN1 */
++#define WM8990_RMP4 0x0008 /* RMP4 */
++#define WM8990_RMP4_BIT 3 /* RMP4 */
++#define WM8990_RMN3 0x0004 /* RMN3 */
++#define WM8990_RMN3_BIT 2 /* RMN3 */
++#define WM8990_RMP2 0x0002 /* RMP2 */
++#define WM8990_RMP2_BIT 1 /* RMP2 */
++#define WM8990_RMN1 0x0001 /* RMN1 */
++#define WM8990_RMN1_BIT 0 /* RMN1 */
++
++/*
++ * R41 (0x29) - Input Mixer3
++ */
++#define WM8990_L34MNB 0x0100 /* L34MNB */
++#define WM8990_L34MNB_BIT 8
++#define WM8990_L34MNBST 0x0080 /* L34MNBST */
++#define WM8990_L34MNBST_BIT 7
++#define WM8990_L12MNB 0x0020 /* L12MNB */
++#define WM8990_L12MNB_BIT 5
++#define WM8990_L12MNBST 0x0010 /* L12MNBST */
++#define WM8990_L12MNBST_BIT 4
++#define WM8990_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */
++#define WM8990_LDBVOL_SHIFT 0
++
++/*
++ * R42 (0x2A) - Input Mixer4
++ */
++#define WM8990_R34MNB 0x0100 /* R34MNB */
++#define WM8990_R34MNB_BIT 8
++#define WM8990_R34MNBST 0x0080 /* R34MNBST */
++#define WM8990_R34MNBST_BIT 7
++#define WM8990_R12MNB 0x0020 /* R12MNB */
++#define WM8990_R12MNB_BIT 5
++#define WM8990_R12MNBST 0x0010 /* R12MNBST */
++#define WM8990_R12MNBST_BIT 4
++#define WM8990_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */
++#define WM8990_RDBVOL_SHIFT 0
++
++/*
++ * R43 (0x2B) - Input Mixer5
++ */
++#define WM8990_LI2BVOL_MASK 0x07 /* LI2BVOL - [8:6] */
++#define WM8990_LI2BVOL_SHIFT 6
++#define WM8990_LR4BVOL_MASK 0x07 /* LR4BVOL - [5:3] */
++#define WM8990_LR4BVOL_SHIFT 3
++#define WM8990_LL4BVOL_MASK 0x07 /* LL4BVOL - [2:0] */
++#define WM8990_LL4BVOL_SHIFT 0
++
++/*
++ * R44 (0x2C) - Input Mixer6
++ */
++#define WM8990_RI2BVOL_MASK 0x07 /* RI2BVOL - [8:6] */
++#define WM8990_RI2BVOL_SHIFT 6
++#define WM8990_RL4BVOL_MASK 0x07 /* RL4BVOL - [5:3] */
++#define WM8990_RL4BVOL_SHIFT 3
++#define WM8990_RR4BVOL_MASK 0x07 /* RR4BVOL - [2:0] */
++#define WM8990_RR4BVOL_SHIFT 0
++
++/*
++ * R45 (0x2D) - Output Mixer1
++ */
++#define WM8990_LRBLO 0x0080 /* LRBLO */
++#define WM8990_LRBLO_BIT 7
++#define WM8990_LLBLO 0x0040 /* LLBLO */
++#define WM8990_LLBLO_BIT 6
++#define WM8990_LRI3LO 0x0020 /* LRI3LO */
++#define WM8990_LRI3LO_BIT 5
++#define WM8990_LLI3LO 0x0010 /* LLI3LO */
++#define WM8990_LLI3LO_BIT 4
++#define WM8990_LR12LO 0x0008 /* LR12LO */
++#define WM8990_LR12LO_BIT 3
++#define WM8990_LL12LO 0x0004 /* LL12LO */
++#define WM8990_LL12LO_BIT 2
++#define WM8990_LDLO 0x0001 /* LDLO */
++#define WM8990_LDLO_BIT 0
++
++/*
++ * R46 (0x2E) - Output Mixer2
++ */
++#define WM8990_RLBRO 0x0080 /* RLBRO */
++#define WM8990_RLBRO_BIT 7
++#define WM8990_RRBRO 0x0040 /* RRBRO */
++#define WM8990_RRBRO_BIT 6
++#define WM8990_RLI3RO 0x0020 /* RLI3RO */
++#define WM8990_RLI3RO_BIT 5
++#define WM8990_RRI3RO 0x0010 /* RRI3RO */
++#define WM8990_RRI3RO_BIT 4
++#define WM8990_RL12RO 0x0008 /* RL12RO */
++#define WM8990_RL12RO_BIT 3
++#define WM8990_RR12RO 0x0004 /* RR12RO */
++#define WM8990_RR12RO_BIT 2
++#define WM8990_RDRO 0x0001 /* RDRO */
++#define WM8990_RDRO_BIT 0
++
++/*
++ * R47 (0x2F) - Output Mixer3
++ */
++#define WM8990_LLI3LOVOL_MASK 0x07 /* LLI3LOVOL - [8:6] */
++#define WM8990_LLI3LOVOL_SHIFT 6
++#define WM8990_LR12LOVOL_MASK 0x07 /* LR12LOVOL - [5:3] */
++#define WM8990_LR12LOVOL_SHIFT 3
++#define WM8990_LL12LOVOL_MASK 0x07 /* LL12LOVOL - [2:0] */
++#define WM8990_LL12LOVOL_SHIFT 0
++
++/*
++ * R48 (0x30) - Output Mixer4
++ */
++#define WM8990_RRI3ROVOL_MASK 0x07 /* RRI3ROVOL - [8:6] */
++#define WM8990_RRI3ROVOL_SHIFT 6
++#define WM8990_RL12ROVOL_MASK 0x07 /* RL12ROVOL - [5:3] */
++#define WM8990_RL12ROVOL_SHIFT 3
++#define WM8990_RR12ROVOL_MASK 0x07 /* RR12ROVOL - [2:0] */
++#define WM8990_RR12ROVOL_SHIFT 0
++
++/*
++ * R49 (0x31) - Output Mixer5
++ */
++#define WM8990_LRI3LOVOL_MASK 0x07 /* LRI3LOVOL - [8:6] */
++#define WM8990_LRI3LOVOL_SHIFT 6
++#define WM8990_LRBLOVOL_MASK 0x07 /* LRBLOVOL - [5:3] */
++#define WM8990_LRBLOVOL_SHIFT 3
++#define WM8990_LLBLOVOL_MASK 0x07 /* LLBLOVOL - [2:0] */
++#define WM8990_LLBLOVOL_SHIFT 0
++
++/*
++ * R50 (0x32) - Output Mixer6
++ */
++#define WM8990_RLI3ROVOL_MASK 0x07 /* RLI3ROVOL - [8:6] */
++#define WM8990_RLI3ROVOL_SHIFT 6
++#define WM8990_RLBROVOL_MASK 0x07 /* RLBROVOL - [5:3] */
++#define WM8990_RLBROVOL_SHIFT 3
++#define WM8990_RRBROVOL_MASK 0x07 /* RRBROVOL - [2:0] */
++#define WM8990_RRBROVOL_SHIFT 0
++
++/*
++ * R51 (0x33) - Out3/4 Mixer
++ */
++#define WM8990_VSEL_MASK 0x0180 /* VSEL - [8:7] */
++#define WM8990_LI4O3 0x0020 /* LI4O3 */
++#define WM8990_LI4O3_BIT 5
++#define WM8990_LPGAO3 0x0010 /* LPGAO3 */
++#define WM8990_LPGAO3_BIT 4
++#define WM8990_RI4O4 0x0002 /* RI4O4 */
++#define WM8990_RI4O4_BIT 1
++#define WM8990_RPGAO4 0x0001 /* RPGAO4 */
++#define WM8990_RPGAO4_BIT 0
++/*
++ * R52 (0x34) - Line Mixer1
++ */
++#define WM8990_LLOPGALON 0x0040 /* LLOPGALON */
++#define WM8990_LLOPGALON_BIT 6
++#define WM8990_LROPGALON 0x0020 /* LROPGALON */
++#define WM8990_LROPGALON_BIT 5
++#define WM8990_LOPLON 0x0010 /* LOPLON */
++#define WM8990_LOPLON_BIT 4
++#define WM8990_LR12LOP 0x0004 /* LR12LOP */
++#define WM8990_LR12LOP_BIT 2
++#define WM8990_LL12LOP 0x0002 /* LL12LOP */
++#define WM8990_LL12LOP_BIT 1
++#define WM8990_LLOPGALOP 0x0001 /* LLOPGALOP */
++#define WM8990_LLOPGALOP_BIT 0
++/*
++ * R53 (0x35) - Line Mixer2
++ */
++#define WM8990_RROPGARON 0x0040 /* RROPGARON */
++#define WM8990_RROPGARON_BIT 6
++#define WM8990_RLOPGARON 0x0020 /* RLOPGARON */
++#define WM8990_RLOPGARON_BIT 5
++#define WM8990_ROPRON 0x0010 /* ROPRON */
++#define WM8990_ROPRON_BIT 4
++#define WM8990_RL12ROP 0x0004 /* RL12ROP */
++#define WM8990_RL12ROP_BIT 2
++#define WM8990_RR12ROP 0x0002 /* RR12ROP */
++#define WM8990_RR12ROP_BIT 1
++#define WM8990_RROPGAROP 0x0001 /* RROPGAROP */
++#define WM8990_RROPGAROP_BIT 0
++
++/*
++ * R54 (0x36) - Speaker Mixer
++ */
++#define WM8990_LB2SPK 0x0080 /* LB2SPK */
++#define WM8990_LB2SPK_BIT 7
++#define WM8990_RB2SPK 0x0040 /* RB2SPK */
++#define WM8990_RB2SPK_BIT 6
++#define WM8990_LI2SPK 0x0020 /* LI2SPK */
++#define WM8990_LI2SPK_BIT 5
++#define WM8990_RI2SPK 0x0010 /* RI2SPK */
++#define WM8990_RI2SPK_BIT 4
++#define WM8990_LOPGASPK 0x0008 /* LOPGASPK */
++#define WM8990_LOPGASPK_BIT 3
++#define WM8990_ROPGASPK 0x0004 /* ROPGASPK */
++#define WM8990_ROPGASPK_BIT 2
++#define WM8990_LDSPK 0x0002 /* LDSPK */
++#define WM8990_LDSPK_BIT 1
++#define WM8990_RDSPK 0x0001 /* RDSPK */
++#define WM8990_RDSPK_BIT 0
++
++/*
++ * R55 (0x37) - Additional Control
++ */
++#define WM8990_VROI 0x0001 /* VROI */
++
++/*
++ * R56 (0x38) - AntiPOP1
++ */
++#define WM8990_DIS_LLINE 0x0020 /* DIS_LLINE */
++#define WM8990_DIS_RLINE 0x0010 /* DIS_RLINE */
++#define WM8990_DIS_OUT3 0x0008 /* DIS_OUT3 */
++#define WM8990_DIS_OUT4 0x0004 /* DIS_OUT4 */
++#define WM8990_DIS_LOUT 0x0002 /* DIS_LOUT */
++#define WM8990_DIS_ROUT 0x0001 /* DIS_ROUT */
++
++/*
++ * R57 (0x39) - AntiPOP2
++ */
++#define WM8990_SOFTST 0x0040 /* SOFTST */
++#define WM8990_BUFIOEN 0x0008 /* BUFIOEN */
++#define WM8990_BUFDCOPEN 0x0004 /* BUFDCOPEN */
++#define WM8990_POBCTRL 0x0002 /* POBCTRL */
++#define WM8990_VMIDTOG 0x0001 /* VMIDTOG */
++
++/*
++ * R58 (0x3A) - MICBIAS
++ */
++#define WM8990_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */
++#define WM8990_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */
++#define WM8990_MCD 0x0004 /* MCD */
++#define WM8990_MBSEL 0x0001 /* MBSEL */
++
++/*
++ * R60 (0x3C) - PLL1
++ */
++#define WM8990_SDM 0x0080 /* SDM */
++#define WM8990_PRESCALE 0x0040 /* PRESCALE */
++#define WM8990_PLLN_MASK 0x000F /* PLLN - [3:0] */
++
++/*
++ * R61 (0x3D) - PLL2
++ */
++#define WM8990_PLLK1_MASK 0x00FF /* PLLK1 - [7:0] */
++
++/*
++ * R62 (0x3E) - PLL3
++ */
++#define WM8990_PLLK2_MASK 0x00FF /* PLLK2 - [7:0] */
++
++/*
++ * R63 (0x3F) - Internal Driver Bits
++*/
++#define WM8990_INMIXL_PWR_BIT 0
++#define WM8990_AINLMUX_PWR_BIT 1
++#define WM8990_INMIXR_PWR_BIT 2
++#define WM8990_AINRMUX_PWR_BIT 3
++
++/*
++ * Default values.
++ */
++#define WM8990_REGISTER_DEFAULTS \
++{ \
++ /*0x8990,*/ /* R0 - Reset */ \
++ 0x0000, /* R1 - Power Management (1) */ \
++ 0x6000, /* R2 - Power Management (2) */ \
++ 0x0000, /* R3 - Power Management (3) */ \
++ 0x4050, /* R4 - Audio Interface (1) */ \
++ 0x4000, /* R5 - Audio Interface (2) */ \
++ 0x01C8, /* R6 - Clocking (1) */ \
++ 0x0000, /* R7 - Clocking (2) */ \
++ 0x0040, /* R8 - Audio Interface (3) */ \
++ 0x0040, /* R9 - Audio Interface (4) */ \
++ 0x0004, /* R10 - DAC CTRL */ \
++ 0x00C0, /* R11 - Left DAC Digital Volume */ \
++ 0x00C0, /* R12 - Right DAC Digital Volume */ \
++ 0x0000, /* R13 - Digital Side Tone */ \
++ 0x0100, /* R14 - ADC CTRL */ \
++ 0x00C0, /* R15 - Left ADC Digital Volume */ \
++ 0x00C0, /* R16 - Right ADC Digital Volume */ \
++ 0x0000, /* R17 */ \
++ 0x0000, /* R18 - GPIO CTRL 1 */ \
++ 0x1000, /* R19 - GPIO1 & GPIO2 */ \
++ 0x1010, /* R20 - GPIO3 & GPIO4 */ \
++ 0x1010, /* R21 - GPIO5 & GPIO6 */ \
++ 0x8000, /* R22 - GPIOCTRL 2 */ \
++ 0x0800, /* R23 - GPIO_POL */ \
++ 0x008B, /* R24 - Left Line Input 1&2 Volume */ \
++ 0x008B, /* R25 - Left Line Input 3&4 Volume */ \
++ 0x008B, /* R26 - Right Line Input 1&2 Volume */ \
++ 0x008B, /* R27 - Right Line Input 3&4 Volume */ \
++ 0x0000, /* R28 - Left Output Volume */ \
++ 0x0000, /* R29 - Right Output Volume */ \
++ 0x0066, /* R30 - Line Outputs Volume */ \
++ 0x0022, /* R31 - Out3/4 Volume */ \
++ 0x0079, /* R32 - Left OPGA Volume */ \
++ 0x0079, /* R33 - Right OPGA Volume */ \
++ 0x0003, /* R34 - Speaker Volume */ \
++ 0x0003, /* R35 - ClassD1 */ \
++ 0x0000, /* R36 */ \
++ 0x0100, /* R37 - ClassD3 */ \
++ 0x0000, /* R38 */ \
++ 0x0000, /* R39 - Input Mixer1 */ \
++ 0x0000, /* R40 - Input Mixer2 */ \
++ 0x0000, /* R41 - Input Mixer3 */ \
++ 0x0000, /* R42 - Input Mixer4 */ \
++ 0x0000, /* R43 - Input Mixer5 */ \
++ 0x0000, /* R44 - Input Mixer6 */ \
++ 0x0000, /* R45 - Output Mixer1 */ \
++ 0x0000, /* R46 - Output Mixer2 */ \
++ 0x0000, /* R47 - Output Mixer3 */ \
++ 0x0000, /* R48 - Output Mixer4 */ \
++ 0x0000, /* R49 - Output Mixer5 */ \
++ 0x0000, /* R50 - Output Mixer6 */ \
++ 0x0180, /* R51 - Out3/4 Mixer */ \
++ 0x0000, /* R52 - Line Mixer1 */ \
++ 0x0000, /* R53 - Line Mixer2 */ \
++ 0x0000, /* R54 - Speaker Mixer */ \
++ 0x0000, /* R55 - Additional Control */ \
++ 0x0000, /* R56 - AntiPOP1 */ \
++ 0x0000, /* R57 - AntiPOP2 */ \
++ 0x0000, /* R58 - MICBIAS */ \
++ 0x0000, /* R59 */ \
++ 0x0008, /* R60 - PLL1 */ \
++ 0x0031, /* R61 - PLL2 */ \
++ 0x0026, /* R62 - PLL3 */ \
++}
++
++struct wm8990_setup_data {
++ unsigned short i2c_address;
++};
++
++#define WM8990_MCLK_DIV 0
++#define WM8990_DACCLK_DIV 1
++#define WM8990_ADCCLK_DIV 2
++#define WM8990_BCLK_DIV 3
++
++#define WM8990_MCLK 0
++
++extern struct snd_soc_codec_dai wm8990_dai;
++extern struct snd_soc_codec_device soc_codec_dev_wm8990;
++
++#endif /* __WM8990REGISTERDEFS_H__ */
++/*------------------------------ END OF FILE ---------------------------------*/
+diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c
+new file mode 100644
+index 0000000..05a1c31
+--- /dev/null
++++ b/sound/soc/codecs/wm9713.c
+@@ -0,0 +1,1224 @@
++/*
++ * wm9713.c -- ALSA Soc WM9713 codec support
++ *
++ * Copyright 2006 Wolfson Microelectronics PLC.
++ * Author: Liam Girdwood
++ * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 4th Feb 2006 Initial version.
++ *
++ * Features:-
++ *
++ * o Support for AC97 Codec, Voice DAC and Aux DAC
++ * o Support for DAPM
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/ac97_codec.h>
++#include <sound/initval.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include "wm9713.h"
++
++#define WM9713_VERSION "0.12"
++
++struct wm9713_priv {
++ u32 pll_in; /* PLL input frequency */
++ u32 pll_out; /* PLL output frequency */
++};
++
++static unsigned int ac97_read(struct snd_soc_codec *codec,
++ unsigned int reg);
++static int ac97_write(struct snd_soc_codec *codec,
++ unsigned int reg, unsigned int val);
++
++/*
++ * WM9713 register cache
++ * Reg 0x3c bit 15 is used by touch driver.
++ */
++static const u16 wm9713_reg[] = {
++ 0x6174, 0x8080, 0x8080, 0x8080, // 6
++ 0xc880, 0xe808, 0xe808, 0x0808, // e
++ 0x00da, 0x8000, 0xd600, 0xaaa0, // 16
++ 0xaaa0, 0xaaa0, 0x0000, 0x0000, // 1e
++ 0x0f0f, 0x0040, 0x0000, 0x7f00, // 26
++ 0x0405, 0x0410, 0xbb80, 0xbb80, // 2e
++ 0x0000, 0xbb80, 0x0000, 0x4523, // 36
++ 0x0000, 0x2000, 0x7eff, 0xffff, // 3e
++ 0x0000, 0x0000, 0x0080, 0x0000, // 46
++ 0x0000, 0x0000, 0xfffe, 0xffff, // 4e
++ 0x0000, 0x0000, 0x0000, 0xfffe, // 56
++ 0x4000, 0x0000, 0x0000, 0x0000, // 5e
++ 0xb032, 0x3e00, 0x0000, 0x0000, // 66
++ 0x0000, 0x0000, 0x0000, 0x0000, // 6e
++ 0x0000, 0x0000, 0x0000, 0x0006, // 76
++ 0x0001, 0x0000, 0x574d, 0x4c13, // 7e
++ 0x0000, 0x0000, 0x0000 // virtual hp & mic mixers
++};
++
++/* virtual HP mixers regs */
++#define HPL_MIXER 0x80
++#define HPR_MIXER 0x82
++#define MICB_MUX 0x82
++
++static const char *wm9713_mic_mixer[] = {"Stereo", "Mic 1", "Mic 2", "Mute"};
++static const char *wm9713_rec_mux[] = {"Stereo", "Left", "Right", "Mute"};
++static const char *wm9713_rec_src[] =
++ {"Mic 1", "Mic 2", "Line", "Mono In", "Headphone", "Speaker",
++ "Mono Out", "Zh"};
++static const char *wm9713_rec_gain[] = {"+1.5dB Steps", "+0.75dB Steps"};
++static const char *wm9713_alc_select[] = {"None", "Left", "Right", "Stereo"};
++static const char *wm9713_mono_pga[] = {"Vmid", "Zh", "Mono", "Inv",
++ "Mono Vmid", "Inv Vmid"};
++static const char *wm9713_spk_pga[] =
++ {"Vmid", "Zh", "Headphone", "Speaker", "Inv", "Headphone Vmid",
++ "Speaker Vmid", "Inv Vmid"};
++static const char *wm9713_hp_pga[] = {"Vmid", "Zh", "Headphone",
++ "Headphone Vmid"};
++static const char *wm9713_out3_pga[] = {"Vmid", "Zh", "Inv 1", "Inv 1 Vmid"};
++static const char *wm9713_out4_pga[] = {"Vmid", "Zh", "Inv 2", "Inv 2 Vmid"};
++static const char *wm9713_dac_inv[] =
++ {"Off", "Mono", "Speaker", "Left Headphone", "Right Headphone",
++ "Headphone Mono", "NC", "Vmid"};
++static const char *wm9713_bass[] = {"Linear Control", "Adaptive Boost"};
++static const char *wm9713_ng_type[] = {"Constant Gain", "Mute"};
++static const char *wm9713_mic_select[] = {"Mic 1", "Mic 2 A", "Mic 2 B"};
++static const char *wm9713_micb_select[] = {"MPB", "MPA"};
++
++static const struct soc_enum wm9713_enum[] = {
++SOC_ENUM_SINGLE(AC97_LINE, 3, 4, wm9713_mic_mixer), /* record mic mixer 0 */
++SOC_ENUM_SINGLE(AC97_VIDEO, 14, 4, wm9713_rec_mux), /* record mux hp 1 */
++SOC_ENUM_SINGLE(AC97_VIDEO, 9, 4, wm9713_rec_mux), /* record mux mono 2 */
++SOC_ENUM_SINGLE(AC97_VIDEO, 3, 8, wm9713_rec_src), /* record mux left 3 */
++SOC_ENUM_SINGLE(AC97_VIDEO, 0, 8, wm9713_rec_src), /* record mux right 4*/
++SOC_ENUM_DOUBLE(AC97_CD, 14, 6, 2, wm9713_rec_gain), /* record step size 5 */
++SOC_ENUM_SINGLE(AC97_PCI_SVID, 14, 4, wm9713_alc_select), /* alc source select 6*/
++SOC_ENUM_SINGLE(AC97_REC_GAIN, 14, 4, wm9713_mono_pga), /* mono input select 7 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN, 11, 8, wm9713_spk_pga), /* speaker left input select 8 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN, 8, 8, wm9713_spk_pga), /* speaker right input select 9 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN, 6, 3, wm9713_hp_pga), /* headphone left input 10 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN, 4, 3, wm9713_hp_pga), /* headphone right input 11 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN, 2, 4, wm9713_out3_pga), /* out 3 source 12 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN, 0, 4, wm9713_out4_pga), /* out 4 source 13 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN_MIC, 13, 8, wm9713_dac_inv), /* dac invert 1 14 */
++SOC_ENUM_SINGLE(AC97_REC_GAIN_MIC, 10, 8, wm9713_dac_inv), /* dac invert 2 15 */
++SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 15, 2, wm9713_bass), /* bass control 16 */
++SOC_ENUM_SINGLE(AC97_PCI_SVID, 5, 2, wm9713_ng_type), /* noise gate type 17 */
++SOC_ENUM_SINGLE(AC97_3D_CONTROL, 12, 3, wm9713_mic_select), /* mic selection 18 */
++SOC_ENUM_SINGLE(MICB_MUX, 0, 2, wm9713_micb_select), /* mic selection 19 */
++};
++
++static const struct snd_kcontrol_new wm9713_snd_ac97_controls[] = {
++SOC_DOUBLE("Speaker Playback Volume", AC97_MASTER, 8, 0, 31, 1),
++SOC_DOUBLE("Speaker Playback Switch", AC97_MASTER, 15, 7, 1, 1),
++SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1),
++SOC_DOUBLE("Headphone Playback Switch", AC97_HEADPHONE,15, 7, 1, 1),
++SOC_DOUBLE("Line In Volume", AC97_PC_BEEP, 8, 0, 31, 1),
++SOC_DOUBLE("PCM Playback Volume", AC97_PHONE, 8, 0, 31, 1),
++SOC_SINGLE("Mic 1 Volume", AC97_MIC, 8, 31, 1),
++SOC_SINGLE("Mic 2 Volume", AC97_MIC, 0, 31, 1),
++
++SOC_SINGLE("Mic Boost (+20dB) Switch", AC97_LINE, 5, 1, 0),
++SOC_SINGLE("Mic Headphone Mixer Volume", AC97_LINE, 0, 7, 1),
++
++SOC_SINGLE("Capture Switch", AC97_CD, 15, 1, 1),
++SOC_ENUM("Capture Volume Steps", wm9713_enum[5]),
++SOC_DOUBLE("Capture Volume", AC97_CD, 8, 0, 31, 0),
++SOC_SINGLE("Capture ZC Switch", AC97_CD, 7, 1, 0),
++
++SOC_SINGLE("Capture to Headphone Volume", AC97_VIDEO, 11, 7, 1),
++SOC_SINGLE("Capture to Mono Boost (+20dB) Switch", AC97_VIDEO, 8, 1, 0),
++SOC_SINGLE("Capture ADC Boost (+20dB) Switch", AC97_VIDEO, 6, 1, 0),
++
++SOC_SINGLE("ALC Target Volume", AC97_CODEC_CLASS_REV, 12, 15, 0),
++SOC_SINGLE("ALC Hold Time", AC97_CODEC_CLASS_REV, 8, 15, 0),
++SOC_SINGLE("ALC Decay Time ", AC97_CODEC_CLASS_REV, 4, 15, 0),
++SOC_SINGLE("ALC Attack Time", AC97_CODEC_CLASS_REV, 0, 15, 0),
++SOC_ENUM("ALC Function", wm9713_enum[6]),
++SOC_SINGLE("ALC Max Volume", AC97_PCI_SVID, 11, 7, 0),
++SOC_SINGLE("ALC ZC Timeout", AC97_PCI_SVID, 9, 3, 0),
++SOC_SINGLE("ALC ZC Switch", AC97_PCI_SVID, 8, 1, 0),
++SOC_SINGLE("ALC NG Switch", AC97_PCI_SVID, 7, 1, 0),
++SOC_ENUM("ALC NG Type", wm9713_enum[17]),
++SOC_SINGLE("ALC NG Threshold", AC97_PCI_SVID, 0, 31, 0),
++
++SOC_DOUBLE("Speaker Playback ZC Switch", AC97_MASTER, 14, 6, 1, 0),
++SOC_DOUBLE("Headphone Playback ZC Switch", AC97_HEADPHONE, 14, 6, 1, 0),
++
++SOC_SINGLE("Out4 Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
++SOC_SINGLE("Out4 Playback ZC Switch", AC97_MASTER_MONO, 14, 1, 0),
++SOC_SINGLE("Out4 Playback Volume", AC97_MASTER_MONO, 8, 63, 1),
++
++SOC_SINGLE("Out3 Playback Switch", AC97_MASTER_MONO, 7, 1, 1),
++SOC_SINGLE("Out3 Playback ZC Switch", AC97_MASTER_MONO, 6, 1, 0),
++SOC_SINGLE("Out3 Playback Volume", AC97_MASTER_MONO, 0, 63, 1),
++
++SOC_SINGLE("Mono Capture Volume", AC97_MASTER_TONE, 8, 31, 1),
++SOC_SINGLE("Mono Playback Switch", AC97_MASTER_TONE, 7, 1, 1),
++SOC_SINGLE("Mono Playback ZC Switch", AC97_MASTER_TONE, 6, 1, 0),
++SOC_SINGLE("Mono Playback Volume", AC97_MASTER_TONE, 0, 31, 1),
++
++SOC_SINGLE("PC Beep Playback Headphone Volume", AC97_AUX, 12, 7, 1),
++SOC_SINGLE("PC Beep Playback Speaker Volume", AC97_AUX, 8, 7, 1),
++SOC_SINGLE("PC Beep Playback Mono Volume", AC97_AUX, 4, 7, 1),
++
++SOC_SINGLE("Voice Playback Headphone Volume", AC97_PCM, 12, 7, 1),
++SOC_SINGLE("Voice Playback Master Volume", AC97_PCM, 8, 7, 1),
++SOC_SINGLE("Voice Playback Mono Volume", AC97_PCM, 4, 7, 1),
++
++SOC_SINGLE("Aux Playback Headphone Volume", AC97_REC_SEL, 12, 7, 1),
++SOC_SINGLE("Aux Playback Master Volume", AC97_REC_SEL, 8, 7, 1),
++SOC_SINGLE("Aux Playback Mono Volume", AC97_REC_SEL, 4, 7, 1),
++
++SOC_ENUM("Bass Control", wm9713_enum[16]),
++SOC_SINGLE("Bass Cut-off Switch", AC97_GENERAL_PURPOSE, 12, 1, 1),
++SOC_SINGLE("Tone Cut-off Switch", AC97_GENERAL_PURPOSE, 4, 1, 1),
++SOC_SINGLE("Playback Attenuate (-6dB) Switch", AC97_GENERAL_PURPOSE, 6, 1, 0),
++SOC_SINGLE("Bass Volume", AC97_GENERAL_PURPOSE, 8, 15, 1),
++SOC_SINGLE("Tone Volume", AC97_GENERAL_PURPOSE, 0, 15, 1),
++
++SOC_SINGLE("3D Upper Cut-off Switch", AC97_REC_GAIN_MIC, 5, 1, 0),
++SOC_SINGLE("3D Lower Cut-off Switch", AC97_REC_GAIN_MIC, 4, 1, 0),
++SOC_SINGLE("3D Depth", AC97_REC_GAIN_MIC, 0, 15, 1),
++};
++
++/* add non dapm controls */
++static int wm9713_add_controls(struct snd_soc_codec *codec)
++{
++ int err, i;
++
++ for (i = 0; i < ARRAY_SIZE(wm9713_snd_ac97_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm9713_snd_ac97_controls[i],codec, NULL));
++ if (err < 0)
++ return err;
++ }
++ return 0;
++}
++
++/* We have to create a fake left and right HP mixers because
++ * the codec only has a single control that is shared by both channels.
++ * This makes it impossible to determine the audio path using the current
++ * register map, thus we add a new (virtual) register to help determine the
++ * audio route within the device.
++ */
++static int mixer_event (struct snd_soc_dapm_widget *w,
++ struct snd_kcontrol *kcontrol, int event)
++{
++ u16 l, r, beep, tone, phone, rec, pcm, aux;
++
++ l = ac97_read(w->codec, HPL_MIXER);
++ r = ac97_read(w->codec, HPR_MIXER);
++ beep = ac97_read(w->codec, AC97_PC_BEEP);
++ tone = ac97_read(w->codec, AC97_MASTER_TONE);
++ phone = ac97_read(w->codec, AC97_PHONE);
++ rec = ac97_read(w->codec, AC97_REC_SEL);
++ pcm = ac97_read(w->codec, AC97_PCM);
++ aux = ac97_read(w->codec, AC97_AUX);
++
++ if (event & SND_SOC_DAPM_PRE_REG)
++ return 0;
++ if (l & 0x1 || r & 0x1)
++ ac97_write(w->codec, AC97_PC_BEEP, beep & 0x7fff);
++ else
++ ac97_write(w->codec, AC97_PC_BEEP, beep | 0x8000);
++
++ if (l & 0x2 || r & 0x2)
++ ac97_write(w->codec, AC97_MASTER_TONE, tone & 0x7fff);
++ else
++ ac97_write(w->codec, AC97_MASTER_TONE, tone | 0x8000);
++
++ if (l & 0x4 || r & 0x4)
++ ac97_write(w->codec, AC97_PHONE, phone & 0x7fff);
++ else
++ ac97_write(w->codec, AC97_PHONE, phone | 0x8000);
++
++ if (l & 0x8 || r & 0x8)
++ ac97_write(w->codec, AC97_REC_SEL, rec & 0x7fff);
++ else
++ ac97_write(w->codec, AC97_REC_SEL, rec | 0x8000);
++
++ if (l & 0x10 || r & 0x10)
++ ac97_write(w->codec, AC97_PCM, pcm & 0x7fff);
++ else
++ ac97_write(w->codec, AC97_PCM, pcm | 0x8000);
++
++ if (l & 0x20 || r & 0x20)
++ ac97_write(w->codec, AC97_AUX, aux & 0x7fff);
++ else
++ ac97_write(w->codec, AC97_AUX, aux | 0x8000);
++
++ return 0;
++}
++
++/* Left Headphone Mixers */
++static const struct snd_kcontrol_new wm9713_hpl_mixer_controls[] = {
++SOC_DAPM_SINGLE("PC Beep Playback Switch", HPL_MIXER, 5, 1, 0),
++SOC_DAPM_SINGLE("Voice Playback Switch", HPL_MIXER, 4, 1, 0),
++SOC_DAPM_SINGLE("Aux Playback Switch", HPL_MIXER, 3, 1, 0),
++SOC_DAPM_SINGLE("PCM Playback Switch", HPL_MIXER, 2, 1, 0),
++SOC_DAPM_SINGLE("MonoIn Playback Switch", HPL_MIXER, 1, 1, 0),
++SOC_DAPM_SINGLE("Bypass Playback Switch", HPL_MIXER, 0, 1, 0),
++};
++
++/* Right Headphone Mixers */
++static const struct snd_kcontrol_new wm9713_hpr_mixer_controls[] = {
++SOC_DAPM_SINGLE("PC Beep Playback Switch", HPR_MIXER, 5, 1, 0),
++SOC_DAPM_SINGLE("Voice Playback Switch", HPR_MIXER, 4, 1, 0),
++SOC_DAPM_SINGLE("Aux Playback Switch", HPR_MIXER, 3, 1, 0),
++SOC_DAPM_SINGLE("PCM Playback Switch", HPR_MIXER, 2, 1, 0),
++SOC_DAPM_SINGLE("MonoIn Playback Switch", HPR_MIXER, 1, 1, 0),
++SOC_DAPM_SINGLE("Bypass Playback Switch", HPR_MIXER, 0, 1, 0),
++};
++
++/* headphone capture mux */
++static const struct snd_kcontrol_new wm9713_hp_rec_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[1]);
++
++/* headphone mic mux */
++static const struct snd_kcontrol_new wm9713_hp_mic_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[0]);
++
++/* Speaker Mixer */
++static const struct snd_kcontrol_new wm9713_speaker_mixer_controls[] = {
++SOC_DAPM_SINGLE("PC Beep Playback Switch", AC97_AUX, 11, 1, 1),
++SOC_DAPM_SINGLE("Voice Playback Switch", AC97_PCM, 11, 1, 1),
++SOC_DAPM_SINGLE("Aux Playback Switch", AC97_REC_SEL, 11, 1, 1),
++SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PHONE, 14, 1, 1),
++SOC_DAPM_SINGLE("MonoIn Playback Switch", AC97_MASTER_TONE, 14, 1, 1),
++SOC_DAPM_SINGLE("Bypass Playback Switch", AC97_PC_BEEP, 14, 1, 1),
++};
++
++/* Mono Mixer */
++static const struct snd_kcontrol_new wm9713_mono_mixer_controls[] = {
++SOC_DAPM_SINGLE("PC Beep Playback Switch", AC97_AUX, 7, 1, 1),
++SOC_DAPM_SINGLE("Voice Playback Switch", AC97_PCM, 7, 1, 1),
++SOC_DAPM_SINGLE("Aux Playback Switch", AC97_REC_SEL, 7, 1, 1),
++SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PHONE, 13, 1, 1),
++SOC_DAPM_SINGLE("MonoIn Playback Switch", AC97_MASTER_TONE, 13, 1, 1),
++SOC_DAPM_SINGLE("Bypass Playback Switch", AC97_PC_BEEP, 13, 1, 1),
++SOC_DAPM_SINGLE("Mic 1 Sidetone Switch", AC97_LINE, 7, 1, 1),
++SOC_DAPM_SINGLE("Mic 2 Sidetone Switch", AC97_LINE, 6, 1, 1),
++};
++
++/* mono mic mux */
++static const struct snd_kcontrol_new wm9713_mono_mic_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[2]);
++
++/* mono output mux */
++static const struct snd_kcontrol_new wm9713_mono_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[7]);
++
++/* speaker left output mux */
++static const struct snd_kcontrol_new wm9713_hp_spkl_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[8]);
++
++/* speaker right output mux */
++static const struct snd_kcontrol_new wm9713_hp_spkr_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[9]);
++
++/* headphone left output mux */
++static const struct snd_kcontrol_new wm9713_hpl_out_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[10]);
++
++/* headphone right output mux */
++static const struct snd_kcontrol_new wm9713_hpr_out_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[11]);
++
++/* Out3 mux */
++static const struct snd_kcontrol_new wm9713_out3_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[12]);
++
++/* Out4 mux */
++static const struct snd_kcontrol_new wm9713_out4_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[13]);
++
++/* DAC inv mux 1 */
++static const struct snd_kcontrol_new wm9713_dac_inv1_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[14]);
++
++/* DAC inv mux 2 */
++static const struct snd_kcontrol_new wm9713_dac_inv2_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[15]);
++
++/* Capture source left */
++static const struct snd_kcontrol_new wm9713_rec_srcl_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[3]);
++
++/* Capture source right */
++static const struct snd_kcontrol_new wm9713_rec_srcr_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[4]);
++
++/* mic source */
++static const struct snd_kcontrol_new wm9713_mic_sel_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[18]);
++
++/* mic source B virtual control */
++static const struct snd_kcontrol_new wm9713_micb_sel_mux_controls =
++SOC_DAPM_ENUM("Route", wm9713_enum[19]);
++
++static const struct snd_soc_dapm_widget wm9713_dapm_widgets[] = {
++SND_SOC_DAPM_MUX("Capture Headphone Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_hp_rec_mux_controls),
++SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_hp_mic_mux_controls),
++SND_SOC_DAPM_MUX("Capture Mono Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_mono_mic_mux_controls),
++SND_SOC_DAPM_MUX("Mono Out Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_mono_mux_controls),
++SND_SOC_DAPM_MUX("Left Speaker Out Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_hp_spkl_mux_controls),
++SND_SOC_DAPM_MUX("Right Speaker Out Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_hp_spkr_mux_controls),
++SND_SOC_DAPM_MUX("Left Headphone Out Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_hpl_out_mux_controls),
++SND_SOC_DAPM_MUX("Right Headphone Out Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_hpr_out_mux_controls),
++SND_SOC_DAPM_MUX("Out 3 Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_out3_mux_controls),
++SND_SOC_DAPM_MUX("Out 4 Mux", SND_SOC_NOPM, 0, 0,
++ &wm9713_out4_mux_controls),
++SND_SOC_DAPM_MUX("DAC Inv Mux 1", SND_SOC_NOPM, 0, 0,
++ &wm9713_dac_inv1_mux_controls),
++SND_SOC_DAPM_MUX("DAC Inv Mux 2", SND_SOC_NOPM, 0, 0,
++ &wm9713_dac_inv2_mux_controls),
++SND_SOC_DAPM_MUX("Left Capture Source", SND_SOC_NOPM, 0, 0,
++ &wm9713_rec_srcl_mux_controls),
++SND_SOC_DAPM_MUX("Right Capture Source", SND_SOC_NOPM, 0, 0,
++ &wm9713_rec_srcr_mux_controls),
++SND_SOC_DAPM_MUX("Mic A Source", SND_SOC_NOPM, 0, 0,
++ &wm9713_mic_sel_mux_controls ),
++SND_SOC_DAPM_MUX("Mic B Source", SND_SOC_NOPM, 0, 0,
++ &wm9713_micb_sel_mux_controls ),
++SND_SOC_DAPM_MIXER_E("Left HP Mixer", AC97_EXTENDED_MID, 3, 1,
++ &wm9713_hpl_mixer_controls[0], ARRAY_SIZE(wm9713_hpl_mixer_controls),
++ mixer_event, SND_SOC_DAPM_POST_REG),
++SND_SOC_DAPM_MIXER_E("Right HP Mixer", AC97_EXTENDED_MID, 2, 1,
++ &wm9713_hpr_mixer_controls[0], ARRAY_SIZE(wm9713_hpr_mixer_controls),
++ mixer_event, SND_SOC_DAPM_POST_REG),
++SND_SOC_DAPM_MIXER("Mono Mixer", AC97_EXTENDED_MID, 0, 1,
++ &wm9713_mono_mixer_controls[0], ARRAY_SIZE(wm9713_mono_mixer_controls)),
++SND_SOC_DAPM_MIXER("Speaker Mixer", AC97_EXTENDED_MID, 1, 1,
++ &wm9713_speaker_mixer_controls[0],
++ ARRAY_SIZE(wm9713_speaker_mixer_controls)),
++SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", AC97_EXTENDED_MID, 7, 1),
++SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", AC97_EXTENDED_MID, 6, 1),
++SND_SOC_DAPM_MIXER("AC97 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
++SND_SOC_DAPM_MIXER("HP Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
++SND_SOC_DAPM_MIXER("Capture Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
++SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", AC97_EXTENDED_MID, 12, 1),
++SND_SOC_DAPM_DAC("Aux DAC", "Aux Playback", AC97_EXTENDED_MID, 11, 1),
++SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", AC97_EXTENDED_MID, 5, 1),
++SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", AC97_EXTENDED_MID, 4, 1),
++SND_SOC_DAPM_PGA("Left Headphone", AC97_EXTENDED_MSTATUS, 10, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Right Headphone", AC97_EXTENDED_MSTATUS, 9, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Left Speaker", AC97_EXTENDED_MSTATUS, 8, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Right Speaker", AC97_EXTENDED_MSTATUS, 7, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Out 3", AC97_EXTENDED_MSTATUS, 11, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Out 4", AC97_EXTENDED_MSTATUS, 12, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Mono Out", AC97_EXTENDED_MSTATUS, 13, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Left Line In", AC97_EXTENDED_MSTATUS, 6, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Right Line In", AC97_EXTENDED_MSTATUS, 5, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Mono In", AC97_EXTENDED_MSTATUS, 4, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Mic A PGA", AC97_EXTENDED_MSTATUS, 3, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Mic B PGA", AC97_EXTENDED_MSTATUS, 2, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Mic A Pre Amp", AC97_EXTENDED_MSTATUS, 1, 1, NULL, 0),
++SND_SOC_DAPM_PGA("Mic B Pre Amp", AC97_EXTENDED_MSTATUS, 0, 1, NULL, 0),
++SND_SOC_DAPM_MICBIAS("Mic Bias", AC97_EXTENDED_MSTATUS, 14, 1),
++SND_SOC_DAPM_OUTPUT("MONO"),
++SND_SOC_DAPM_OUTPUT("HPL"),
++SND_SOC_DAPM_OUTPUT("HPR"),
++SND_SOC_DAPM_OUTPUT("SPKL"),
++SND_SOC_DAPM_OUTPUT("SPKR"),
++SND_SOC_DAPM_OUTPUT("OUT3"),
++SND_SOC_DAPM_OUTPUT("OUT4"),
++SND_SOC_DAPM_INPUT("LINEL"),
++SND_SOC_DAPM_INPUT("LINER"),
++SND_SOC_DAPM_INPUT("MONOIN"),
++SND_SOC_DAPM_INPUT("PCBEEP"),
++SND_SOC_DAPM_INPUT("MIC1"),
++SND_SOC_DAPM_INPUT("MIC2A"),
++SND_SOC_DAPM_INPUT("MIC2B"),
++SND_SOC_DAPM_VMID("VMID"),
++};
++
++static const char *audio_map[][3] = {
++ /* left HP mixer */
++ {"Left HP Mixer", "PC Beep Playback Switch", "PCBEEP"},
++ {"Left HP Mixer", "Voice Playback Switch", "Voice DAC"},
++ {"Left HP Mixer", "Aux Playback Switch", "Aux DAC"},
++ {"Left HP Mixer", "Bypass Playback Switch", "Left Line In"},
++ {"Left HP Mixer", "PCM Playback Switch", "Left DAC"},
++ {"Left HP Mixer", "MonoIn Playback Switch", "Mono In"},
++ {"Left HP Mixer", NULL, "Capture Headphone Mux"},
++
++ /* right HP mixer */
++ {"Right HP Mixer", "PC Beep Playback Switch", "PCBEEP"},
++ {"Right HP Mixer", "Voice Playback Switch", "Voice DAC"},
++ {"Right HP Mixer", "Aux Playback Switch", "Aux DAC"},
++ {"Right HP Mixer", "Bypass Playback Switch", "Right Line In"},
++ {"Right HP Mixer", "PCM Playback Switch", "Right DAC"},
++ {"Right HP Mixer", "MonoIn Playback Switch", "Mono In"},
++ {"Right HP Mixer", NULL, "Capture Headphone Mux"},
++
++ /* virtual mixer - mixes left & right channels for spk and mono */
++ {"AC97 Mixer", NULL, "Left DAC"},
++ {"AC97 Mixer", NULL, "Right DAC"},
++ {"Line Mixer", NULL, "Right Line In"},
++ {"Line Mixer", NULL, "Left Line In"},
++ {"HP Mixer", NULL, "Left HP Mixer"},
++ {"HP Mixer", NULL, "Right HP Mixer"},
++ {"Capture Mixer", NULL, "Left Capture Source"},
++ {"Capture Mixer", NULL, "Right Capture Source"},
++
++ /* speaker mixer */
++ {"Speaker Mixer", "PC Beep Playback Switch", "PCBEEP"},
++ {"Speaker Mixer", "Voice Playback Switch", "Voice DAC"},
++ {"Speaker Mixer", "Aux Playback Switch", "Aux DAC"},
++ {"Speaker Mixer", "Bypass Playback Switch", "Line Mixer"},
++ {"Speaker Mixer", "PCM Playback Switch", "AC97 Mixer"},
++ {"Speaker Mixer", "MonoIn Playback Switch", "Mono In"},
++
++ /* mono mixer */
++ {"Mono Mixer", "PC Beep Playback Switch", "PCBEEP"},
++ {"Mono Mixer", "Voice Playback Switch", "Voice DAC"},
++ {"Mono Mixer", "Aux Playback Switch", "Aux DAC"},
++ {"Mono Mixer", "Bypass Playback Switch", "Line Mixer"},
++ {"Mono Mixer", "PCM Playback Switch", "AC97 Mixer"},
++ {"Mono Mixer", NULL, "Capture Mono Mux"},
++
++ /* DAC inv mux 1 */
++ {"DAC Inv Mux 1", "Mono", "Mono Mixer"},
++ {"DAC Inv Mux 1", "Speaker", "Speaker Mixer"},
++ {"DAC Inv Mux 1", "Left Headphone", "Left HP Mixer"},
++ {"DAC Inv Mux 1", "Right Headphone", "Right HP Mixer"},
++ {"DAC Inv Mux 1", "Headphone Mono", "HP Mixer"},
++
++ /* DAC inv mux 2 */
++ {"DAC Inv Mux 2", "Mono", "Mono Mixer"},
++ {"DAC Inv Mux 2", "Speaker", "Speaker Mixer"},
++ {"DAC Inv Mux 2", "Left Headphone", "Left HP Mixer"},
++ {"DAC Inv Mux 2", "Right Headphone", "Right HP Mixer"},
++ {"DAC Inv Mux 2", "Headphone Mono", "HP Mixer"},
++
++ /* headphone left mux */
++ {"Left Headphone Out Mux", "Headphone", "Left HP Mixer"},
++
++ /* headphone right mux */
++ {"Right Headphone Out Mux", "Headphone", "Right HP Mixer"},
++
++ /* speaker left mux */
++ {"Left Speaker Out Mux", "Headphone", "Left HP Mixer"},
++ {"Left Speaker Out Mux", "Speaker", "Speaker Mixer"},
++ {"Left Speaker Out Mux", "Inv", "DAC Inv Mux 1"},
++
++ /* speaker right mux */
++ {"Right Speaker Out Mux", "Headphone", "Right HP Mixer"},
++ {"Right Speaker Out Mux", "Speaker", "Speaker Mixer"},
++ {"Right Speaker Out Mux", "Inv", "DAC Inv Mux 2"},
++
++ /* mono mux */
++ {"Mono Out Mux", "Mono", "Mono Mixer"},
++ {"Mono Out Mux", "Inv", "DAC Inv Mux 1"},
++
++ /* out 3 mux */
++ {"Out 3 Mux", "Inv 1", "DAC Inv Mux 1"},
++
++ /* out 4 mux */
++ {"Out 4 Mux", "Inv 2", "DAC Inv Mux 2"},
++
++ /* output pga */
++ {"HPL", NULL, "Left Headphone"},
++ {"Left Headphone", NULL, "Left Headphone Out Mux"},
++ {"HPR", NULL, "Right Headphone"},
++ {"Right Headphone", NULL, "Right Headphone Out Mux"},
++ {"OUT3", NULL, "Out 3"},
++ {"Out 3", NULL, "Out 3 Mux"},
++ {"OUT4", NULL, "Out 4"},
++ {"Out 4", NULL, "Out 4 Mux"},
++ {"SPKL", NULL, "Left Speaker"},
++ {"Left Speaker", NULL, "Left Speaker Out Mux"},
++ {"SPKR", NULL, "Right Speaker"},
++ {"Right Speaker", NULL, "Right Speaker Out Mux"},
++ {"MONO", NULL, "Mono Out"},
++ {"Mono Out", NULL, "Mono Out Mux"},
++
++ /* input pga */
++ {"Left Line In", NULL, "LINEL"},
++ {"Right Line In", NULL, "LINER"},
++ {"Mono In", NULL, "MONOIN"},
++ {"Mic A PGA", NULL, "Mic A Pre Amp"},
++ {"Mic B PGA", NULL, "Mic B Pre Amp"},
++
++ /* left capture select */
++ {"Left Capture Source", "Mic 1", "Mic A Pre Amp"},
++ {"Left Capture Source", "Mic 2", "Mic B Pre Amp"},
++ {"Left Capture Source", "Line", "LINEL"},
++ {"Left Capture Source", "Mono In", "MONOIN"},
++ {"Left Capture Source", "Headphone", "Left HP Mixer"},
++ {"Left Capture Source", "Speaker", "Speaker Mixer"},
++ {"Left Capture Source", "Mono Out", "Mono Mixer"},
++
++ /* right capture select */
++ {"Right Capture Source", "Mic 1", "Mic A Pre Amp"},
++ {"Right Capture Source", "Mic 2", "Mic B Pre Amp"},
++ {"Right Capture Source", "Line", "LINER"},
++ {"Right Capture Source", "Mono In", "MONOIN"},
++ {"Right Capture Source", "Headphone", "Right HP Mixer"},
++ {"Right Capture Source", "Speaker", "Speaker Mixer"},
++ {"Right Capture Source", "Mono Out", "Mono Mixer"},
++
++ /* left ADC */
++ {"Left ADC", NULL, "Left Capture Source"},
++
++ /* right ADC */
++ {"Right ADC", NULL, "Right Capture Source"},
++
++ /* mic */
++ {"Mic A Pre Amp", NULL, "Mic A Source"},
++ {"Mic A Source", "Mic 1", "MIC1"},
++ {"Mic A Source", "Mic 2 A", "MIC2A"},
++ {"Mic A Source", "Mic 2 B", "Mic B Source"},
++ {"Mic B Pre Amp", "MPB", "Mic B Source"},
++ {"Mic B Source", NULL, "MIC2B"},
++
++ /* headphone capture */
++ {"Capture Headphone Mux", "Stereo", "Capture Mixer"},
++ {"Capture Headphone Mux", "Left", "Left Capture Source"},
++ {"Capture Headphone Mux", "Right", "Right Capture Source"},
++
++ /* mono capture */
++ {"Capture Mono Mux", "Stereo", "Capture Mixer"},
++ {"Capture Mono Mux", "Left", "Left Capture Source"},
++ {"Capture Mono Mux", "Right", "Right Capture Source"},
++
++ {NULL, NULL, NULL},
++};
++
++static int wm9713_add_widgets(struct snd_soc_codec *codec)
++{
++ int i;
++
++ for(i = 0; i < ARRAY_SIZE(wm9713_dapm_widgets); i++) {
++ snd_soc_dapm_new_control(codec, &wm9713_dapm_widgets[i]);
++ }
++
++ /* set up audio path audio_mapnects */
++ for(i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ snd_soc_dapm_new_widgets(codec);
++ return 0;
++}
++
++static unsigned int ac97_read(struct snd_soc_codec *codec,
++ unsigned int reg)
++{
++ u16 *cache = codec->reg_cache;
++
++ if (reg == AC97_RESET || reg == AC97_GPIO_STATUS ||
++ reg == AC97_VENDOR_ID1 || reg == AC97_VENDOR_ID2 ||
++ reg == AC97_CD)
++ return soc_ac97_ops.read(codec->ac97, reg);
++ else {
++ reg = reg >> 1;
++
++ if (reg > (ARRAY_SIZE(wm9713_reg)))
++ return -EIO;
++
++ return cache[reg];
++ }
++}
++
++static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
++ unsigned int val)
++{
++ u16 *cache = codec->reg_cache;
++ if (reg < 0x7c)
++ soc_ac97_ops.write(codec->ac97, reg, val);
++ reg = reg >> 1;
++ if (reg <= (ARRAY_SIZE(wm9713_reg)))
++ cache[reg] = val;
++
++ return 0;
++}
++
++struct pll_ {
++ unsigned int in_hz;
++ unsigned int lf:1; /* allows low frequency use */
++ unsigned int sdm:1; /* allows fraction n div */
++ unsigned int divsel:1; /* enables input clock div */
++ unsigned int divctl:1; /* input clock divider */
++ unsigned int n:4;
++ unsigned int k;
++};
++
++struct pll_ pll[] = {
++ {13000000, 0, 1, 0, 0, 7, 0x23f488},
++ {2048000, 1, 0, 0, 0, 12, 0x0},
++ {4096000, 1, 0, 0, 0, 6, 0x0},
++ {12288000, 0, 0, 0, 0, 8, 0x0},
++ /* liam - add more entries */
++};
++
++static int wm9713_set_pll(struct snd_soc_codec *codec,
++ int pll_id, unsigned int freq_in, unsigned int freq_out)
++{
++ struct wm9713_priv *wm9713 = codec->private_data;
++ int i;
++ u16 reg, reg2;
++
++ /* turn PLL off ? */
++ if (freq_in == 0 || freq_out == 0) {
++ /* disable PLL power and select ext source */
++ reg = ac97_read(codec, AC97_HANDSET_RATE);
++ ac97_write(codec, AC97_HANDSET_RATE, reg | 0x0080);
++ reg = ac97_read(codec, AC97_EXTENDED_MID);
++ ac97_write(codec, AC97_EXTENDED_MID, reg | 0x0200);
++ wm9713->pll_out = 0;
++ return 0;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(pll); i++) {
++ if (pll[i].in_hz == freq_in)
++ goto found;
++ }
++ return -EINVAL;
++
++found:
++ if (pll[i].sdm == 0) {
++ reg = (pll[i].n << 12) | (pll[i].lf << 11) |
++ (pll[i].divsel << 9) | (pll[i].divctl << 8);
++ ac97_write(codec, AC97_LINE1_LEVEL, reg);
++ } else {
++ /* write the fractional k to the reg 0x46 pages */
++ reg2 = (pll[i].n << 12) | (pll[i].lf << 11) | (pll[i].sdm << 10) |
++ (pll[i].divsel << 9) | (pll[i].divctl << 8);
++
++ reg = reg2 | (0x5 << 4) | (pll[i].k >> 20); /* K [21:20] */
++ ac97_write(codec, AC97_LINE1_LEVEL, reg);
++
++ reg = reg2 | (0x4 << 4) | ((pll[i].k >> 16) & 0xf); /* K [19:16] */
++ ac97_write(codec, AC97_LINE1_LEVEL, reg);
++
++ reg = reg2 | (0x3 << 4) | ((pll[i].k >> 12) & 0xf); /* K [15:12] */
++ ac97_write(codec, AC97_LINE1_LEVEL, reg);
++
++ reg = reg2 | (0x2 << 4) | ((pll[i].k >> 8) & 0xf); /* K [11:8] */
++ ac97_write(codec, AC97_LINE1_LEVEL, reg);
++
++ reg = reg2 | (0x1 << 4) | ((pll[i].k >> 4) & 0xf); /* K [7:4] */
++ ac97_write(codec, AC97_LINE1_LEVEL, reg);
++
++ reg = reg2 | (0x0 << 4) | (pll[i].k & 0xf); /* K [3:0] */
++ ac97_write(codec, AC97_LINE1_LEVEL, reg);
++ }
++
++ /* turn PLL on and select as source */
++ reg = ac97_read(codec, AC97_EXTENDED_MID);
++ ac97_write(codec, AC97_EXTENDED_MID, reg & 0xfdff);
++ reg = ac97_read(codec, AC97_HANDSET_RATE);
++ ac97_write(codec, AC97_HANDSET_RATE, reg & 0xff7f);
++ wm9713->pll_out = freq_out;
++ wm9713->pll_in = freq_in;
++
++ /* wait 10ms AC97 link frames for the link to stabilise */
++ schedule_timeout_interruptible(msecs_to_jiffies(10));
++ return 0;
++}
++
++static int wm9713_set_dai_pll(struct snd_soc_codec_dai *codec_dai,
++ int pll_id, unsigned int freq_in, unsigned int freq_out)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ return wm9713_set_pll(codec, pll_id, freq_in, freq_out);
++}
++
++/*
++ * Tristate the PCM DAI lines, tristate can be disabled by calling
++ * wm9713_set_dai_fmt()
++ */
++static int wm9713_set_dai_tristate(struct snd_soc_codec_dai *codec_dai,
++ int tristate)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ u16 reg = ac97_read(codec, AC97_CENTER_LFE_MASTER) & 0x9fff;
++
++ if (tristate)
++ ac97_write(codec, AC97_CENTER_LFE_MASTER, reg);
++
++ return 0;
++}
++
++/*
++ * Configure WM9713 clock dividers.
++ * Voice DAC needs 256 FS
++ */
++static int wm9713_set_dai_clkdiv(struct snd_soc_codec_dai *codec_dai,
++ int div_id, int div)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ u16 reg;
++
++ switch (div_id) {
++ case WM9713_PCMCLK_DIV:
++ reg = ac97_read(codec, AC97_HANDSET_RATE) & 0xf0ff;
++ ac97_write(codec, AC97_HANDSET_RATE, reg | div);
++ break;
++ case WM9713_CLKA_MULT:
++ reg = ac97_read(codec, AC97_HANDSET_RATE) & 0xfffd;
++ ac97_write(codec, AC97_HANDSET_RATE, reg | div);
++ break;
++ case WM9713_CLKB_MULT:
++ reg = ac97_read(codec, AC97_HANDSET_RATE) & 0xfffb;
++ ac97_write(codec, AC97_HANDSET_RATE, reg | div);
++ break;
++ case WM9713_HIFI_DIV:
++ reg = ac97_read(codec, AC97_HANDSET_RATE) & 0x8fff;
++ ac97_write(codec, AC97_HANDSET_RATE, reg | div);
++ break;
++ case WM9713_PCMBCLK_DIV:
++ reg = ac97_read(codec, AC97_CENTER_LFE_MASTER) & 0xf1ff;
++ ac97_write(codec, AC97_CENTER_LFE_MASTER, reg | div);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++};
++
++static int wm9713_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
++ unsigned int fmt)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ u16 gpio = ac97_read(codec, AC97_GPIO_CFG) & 0xffe2;
++ u16 reg = 0x8000;
++
++ /* clock masters */
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK){
++ case SND_SOC_DAIFMT_CBM_CFM:
++ reg |= 0x4000;
++ gpio |= 0x0008;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFS:
++ reg |= 0x6000;
++ gpio |= 0x000c;
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ reg |= 0x0200;
++ gpio |= 0x000d;
++ break;
++ case SND_SOC_DAIFMT_CBS_CFM:
++ gpio |= 0x0009;
++ break;
++ }
++
++ /* clock inversion */
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_IB_IF:
++ reg |= 0x00c0;
++ break;
++ case SND_SOC_DAIFMT_IB_NF:
++ reg |= 0x0080;
++ break;
++ case SND_SOC_DAIFMT_NB_IF:
++ reg |= 0x0040;
++ break;
++ }
++
++ /* DAI format */
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ reg |= 0x0002;
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ break;
++ case SND_SOC_DAIFMT_LEFT_J:
++ reg |= 0x0001;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ reg |= 0x0003;
++ break;
++ case SND_SOC_DAIFMT_DSP_B:
++ reg |= 0x0043;
++ break;
++ }
++
++ ac97_write(codec, AC97_GPIO_CFG, gpio);
++ ac97_write(codec, AC97_CENTER_LFE_MASTER, reg);
++ return 0;
++}
++
++static int wm9713_pcm_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_device *socdev = rtd->socdev;
++ struct snd_soc_codec *codec = socdev->codec;
++ u16 reg = ac97_read(codec, AC97_CENTER_LFE_MASTER) & 0xfff3;
++
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ reg |= 0x0004;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ reg |= 0x0008;
++ break;
++ case SNDRV_PCM_FORMAT_S32_LE:
++ reg |= 0x000c;
++ break;
++ }
++
++ /* enable PCM interface in master mode */
++ ac97_write(codec, AC97_CENTER_LFE_MASTER, reg);
++ return 0;
++}
++
++static void wm9713_voiceshutdown(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_device *socdev = rtd->socdev;
++ struct snd_soc_codec *codec = socdev->codec;
++ u16 status;
++
++ /* Gracefully shut down the voice interface. */
++ status = ac97_read(codec, AC97_EXTENDED_STATUS) | 0x1000;
++ ac97_write(codec,AC97_HANDSET_RATE,0x0280);
++ schedule_timeout_interruptible(msecs_to_jiffies(1));
++ ac97_write(codec,AC97_HANDSET_RATE,0x0F80);
++ ac97_write(codec,AC97_EXTENDED_MID,status);
++}
++
++static int ac97_hifi_prepare(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_device *socdev = rtd->socdev;
++ struct snd_soc_codec *codec = socdev->codec;
++ int reg;
++ u16 vra;
++
++ vra = ac97_read(codec, AC97_EXTENDED_STATUS);
++ ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ reg = AC97_PCM_FRONT_DAC_RATE;
++ else
++ reg = AC97_PCM_LR_ADC_RATE;
++
++ return ac97_write(codec, reg, runtime->rate);
++}
++
++static int ac97_aux_prepare(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_device *socdev = rtd->socdev;
++ struct snd_soc_codec *codec = socdev->codec;
++ u16 vra, xsle;
++
++ vra = ac97_read(codec, AC97_EXTENDED_STATUS);
++ ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1);
++ xsle = ac97_read(codec, AC97_PCI_SID);
++ ac97_write(codec, AC97_PCI_SID, xsle | 0x8000);
++
++ if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
++ return -ENODEV;
++
++ return ac97_write(codec, AC97_PCM_SURR_DAC_RATE, runtime->rate);
++}
++
++#define WM9713_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
++
++#define WM9713_PCM_FORMATS \
++ (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
++ SNDRV_PCM_FORMAT_S24_LE)
++
++struct snd_soc_codec_dai wm9713_dai[] = {
++{
++ .name = "AC97 HiFi",
++ .type = SND_SOC_DAI_AC97_BUS,
++ .playback = {
++ .stream_name = "HiFi Playback",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = WM9713_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .capture = {
++ .stream_name = "HiFi Capture",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = WM9713_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .prepare = ac97_hifi_prepare,},
++ },
++ {
++ .name = "AC97 Aux",
++ .playback = {
++ .stream_name = "Aux Playback",
++ .channels_min = 1,
++ .channels_max = 1,
++ .rates = WM9713_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .prepare = ac97_aux_prepare,},
++ },
++ {
++ .name = "WM9713 Voice",
++ .playback = {
++ .stream_name = "Voice Playback",
++ .channels_min = 1,
++ .channels_max = 1,
++ .rates = WM9713_RATES,
++ .formats = WM9713_PCM_FORMATS,},
++ .capture = {
++ .stream_name = "Voice Capture",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = WM9713_RATES,
++ .formats = WM9713_PCM_FORMATS,},
++ .ops = {
++ .hw_params = wm9713_pcm_hw_params,
++ .shutdown = wm9713_voiceshutdown,},
++ .dai_ops = {
++ .set_clkdiv = wm9713_set_dai_clkdiv,
++ .set_pll = wm9713_set_dai_pll,
++ .set_fmt = wm9713_set_dai_fmt,
++ .set_tristate = wm9713_set_dai_tristate,
++ },
++ },
++};
++EXPORT_SYMBOL_GPL(wm9713_dai);
++
++int wm9713_reset(struct snd_soc_codec *codec, int try_warm)
++{
++ if (try_warm && soc_ac97_ops.warm_reset) {
++ soc_ac97_ops.warm_reset(codec->ac97);
++ if (!(ac97_read(codec, 0) & 0x8000))
++ return 1;
++ }
++
++ soc_ac97_ops.reset(codec->ac97);
++
++ if (ac97_read(codec, 0) & 0x8000)
++ return -EIO;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(wm9713_reset);
++
++static int wm9713_dapm_event(struct snd_soc_codec *codec, int event)
++{
++ u16 reg;
++
++ switch (event) {
++ case SNDRV_CTL_POWER_D0: /* full On */
++ /* enable thermal shutdown */
++ reg = ac97_read(codec, AC97_EXTENDED_MID) & 0x1bff;
++/*TODO: for init event*/
++#if 0
++ ac97_write(codec, AC97_EXTENDED_MID, reg);
++#endif
++ break;
++ case SNDRV_CTL_POWER_D1: /* partial On */
++ case SNDRV_CTL_POWER_D2: /* partial On */
++ break;
++ case SNDRV_CTL_POWER_D3hot: /* Off, with power */
++ /* enable master bias and vmid */
++ reg = ac97_read(codec, AC97_EXTENDED_MID) & 0x3bff;
++ ac97_write(codec, AC97_EXTENDED_MID, reg);
++ ac97_write(codec, AC97_POWERDOWN, 0x0000);
++ break;
++ case SNDRV_CTL_POWER_D3cold: /* Off, without power */
++ /* disable everything including AC link */
++ ac97_write(codec, AC97_EXTENDED_MID, 0xffff);
++ ac97_write(codec, AC97_EXTENDED_MSTATUS, 0xffff);
++ ac97_write(codec, AC97_POWERDOWN, 0xffff);
++ break;
++ }
++ codec->dapm_state = event;
++ return 0;
++}
++
++static int wm9713_soc_suspend(struct platform_device *pdev,
++ pm_message_t state)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++
++ wm9713_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
++ return 0;
++}
++
++static int wm9713_soc_resume(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++ struct wm9713_priv *wm9713 = codec->private_data;
++ int i, ret;
++ u16 *cache = codec->reg_cache;
++
++ wm9713_reset(codec, 0);
++ if ((ret = wm9713_reset(codec, 1)) < 0){
++ printk(KERN_ERR "could not reset AC97 codec\n");
++ return ret;
++ }
++
++ wm9713_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
++
++ /* do we need to re-start the PLL ? */
++ if (wm9713->pll_out)
++ wm9713_set_pll(codec, 0, wm9713->pll_in, wm9713->pll_out);
++
++ /* only synchronise the codec if warm reset failed */
++ if (ret == 0) {
++ for (i = 2; i < ARRAY_SIZE(wm9713_reg) << 1; i+=2) {
++ if (i == AC97_POWERDOWN || i == AC97_EXTENDED_MID ||
++ i == AC97_EXTENDED_MSTATUS || i > 0x66)
++ continue;
++ soc_ac97_ops.write(codec->ac97, i, cache[i>>1]);
++ }
++ }
++
++ if (codec->suspend_dapm_state == SNDRV_CTL_POWER_D0)
++ wm9713_dapm_event(codec, SNDRV_CTL_POWER_D0);
++
++ return ret;
++}
++
++static int wm9713_soc_probe(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec;
++ int ret = 0, reg;
++
++ printk(KERN_INFO "WM9713/WM9714 SoC Audio Codec %s\n", WM9713_VERSION);
++
++ socdev->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
++ if (socdev->codec == NULL)
++ return -ENOMEM;
++ codec = socdev->codec;
++ mutex_init(&codec->mutex);
++
++ codec->reg_cache = kmemdup(wm9713_reg, sizeof(wm9713_reg), GFP_KERNEL);
++ if (codec->reg_cache == NULL){
++ ret = -ENOMEM;
++ goto cache_err;
++ }
++ codec->reg_cache_size = sizeof(wm9713_reg);
++ codec->reg_cache_step = 2;
++
++ codec->private_data = kzalloc(sizeof(struct wm9713_priv), GFP_KERNEL);
++ if (codec->private_data == NULL) {
++ ret = -ENOMEM;
++ goto priv_err;
++ }
++
++ codec->name = "WM9713";
++ codec->owner = THIS_MODULE;
++ codec->dai = wm9713_dai;
++ codec->num_dai = ARRAY_SIZE(wm9713_dai);
++ codec->write = ac97_write;
++ codec->read = ac97_read;
++ codec->dapm_event = wm9713_dapm_event;
++ INIT_LIST_HEAD(&codec->dapm_widgets);
++ INIT_LIST_HEAD(&codec->dapm_paths);
++
++ ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
++ if (ret < 0)
++ goto codec_err;
++
++ /* register pcms */
++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
++ if (ret < 0)
++ goto pcm_err;
++
++ /* do a cold reset for the controller and then try
++ * a warm reset followed by an optional cold reset for codec */
++ wm9713_reset(codec, 0);
++ ret = wm9713_reset(codec, 1);
++ if (ret < 0) {
++ printk(KERN_ERR "AC97 link error\n");
++ goto reset_err;
++ }
++ wm9713_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
++
++ /* unmute the adc - move to kcontrol */
++ reg = ac97_read(codec, AC97_CD) & 0x7fff;
++ ac97_write(codec, AC97_CD, reg);
++
++ wm9713_add_controls(codec);
++ wm9713_add_widgets(codec);
++ ret = snd_soc_register_card(socdev);
++ if (ret < 0)
++ goto reset_err;
++ return 0;
++
++reset_err:
++ snd_soc_free_pcms(socdev);
++
++pcm_err:
++ snd_soc_free_ac97_codec(codec);
++
++codec_err:
++ kfree(codec->private_data);
++
++priv_err:
++ kfree(codec->reg_cache);
++
++cache_err:
++ kfree(socdev->codec);
++ socdev->codec = NULL;
++ return ret;
++}
++
++static int wm9713_soc_remove(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++
++ if (codec == NULL)
++ return 0;
++
++ snd_soc_dapm_free(socdev);
++ snd_soc_free_pcms(socdev);
++ snd_soc_free_ac97_codec(codec);
++ kfree(codec->private_data);
++ kfree(codec->reg_cache);
++ kfree(codec->dai);
++ kfree(codec);
++ return 0;
++}
++
++struct snd_soc_codec_device soc_codec_dev_wm9713 = {
++ .probe = wm9713_soc_probe,
++ .remove = wm9713_soc_remove,
++ .suspend = wm9713_soc_suspend,
++ .resume = wm9713_soc_resume,
++};
++
++EXPORT_SYMBOL_GPL(soc_codec_dev_wm9713);
++
++MODULE_DESCRIPTION("ASoC WM9713/WM9714 driver");
++MODULE_AUTHOR("Liam Girdwood");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/codecs/wm9713.h b/sound/soc/codecs/wm9713.h
+new file mode 100644
+index 0000000..b9d95a2
+--- /dev/null
++++ b/sound/soc/codecs/wm9713.h
+@@ -0,0 +1,51 @@
++/*
++ * wm9713.h -- WM9713 Soc Audio driver
++ */
++
++#ifndef _WM9713_H
++#define _WM9713_H
++
++/* clock inputs */
++#define WM9713_CLKA_PIN 0
++#define WM9713_CLKB_PIN 1
++
++/* clock divider ID's */
++#define WM9713_PCMCLK_DIV 0
++#define WM9713_CLKA_MULT 1
++#define WM9713_CLKB_MULT 2
++#define WM9713_HIFI_DIV 3
++#define WM9713_PCMBCLK_DIV 4
++
++/* PCM clk div */
++#define WM9713_PCMDIV(x) ((x - 1) << 8)
++
++/* HiFi Div */
++#define WM9713_HIFIDIV(x) ((x - 1) << 12)
++
++/* MCLK clock mulitipliers */
++#define WM9713_CLKA_X1 (0 << 1)
++#define WM9713_CLKA_X2 (1 << 1)
++#define WM9713_CLKB_X1 (0 << 2)
++#define WM9713_CLKB_X2 (1 << 2)
++
++/* MCLK clock MUX */
++#define WM9713_CLK_MUX_A (0 << 0)
++#define WM9713_CLK_MUX_B (1 << 0)
++
++/* Voice DAI BCLK divider */
++#define WM9713_PCMBCLK_DIV_1 (0 << 9)
++#define WM9713_PCMBCLK_DIV_2 (1 << 9)
++#define WM9713_PCMBCLK_DIV_4 (2 << 9)
++#define WM9713_PCMBCLK_DIV_8 (3 << 9)
++#define WM9713_PCMBCLK_DIV_16 (4 << 9)
++
++#define WM9713_DAI_AC97_HIFI 0
++#define WM9713_DAI_AC97_AUX 1
++#define WM9713_DAI_PCM_VOICE 2
++
++extern struct snd_soc_codec_device soc_codec_dev_wm9713;
++extern struct snd_soc_codec_dai wm9713_dai[3];
++
++int wm9713_reset(struct snd_soc_codec *codec, int try_warm);
++
++#endif
+diff --git a/sound/soc/s3c24xx/Kconfig b/sound/soc/s3c24xx/Kconfig
+index 5632a2e..c4910e6 100644
+--- a/sound/soc/s3c24xx/Kconfig
++++ b/sound/soc/s3c24xx/Kconfig
+@@ -1,13 +1,22 @@
+-config SND_S3C24XX_SOC
+- tristate "SoC Audio for the Samsung S3C24XX chips"
++menu "SoC Audio for the Samsung S3C"
++ depends on PLAT_S3C24XX && ARCH_S3C2410 && SND_SOC
++
++config SND_S3C_SOC
++ tristate "SoC Audio for the Samsung S3C chips"
+ depends on ARCH_S3C2410 && SND_SOC
+ select SND_PCM
+ help
+ Say Y or M if you want to add support for codecs attached to
+- the S3C24XX AC97, I2S or SSP interface. You will also need
++ the S3C AC97, I2S or SSP interface. You will also need
+ to select the audio interfaces to support below.
+
+-config SND_S3C24XX_SOC_I2S
++config SND_S3C_SOC_I2S
++ tristate
++
++config SND_S3C2450_SOC_I2S
++ tristate
++
++config SND_SOC_I2S_V40
+ tristate
+
+ config SND_S3C2443_SOC_AC97
+@@ -16,10 +25,43 @@ config SND_S3C2443_SOC_AC97
+ select SND_AC97_CODEC
+ select SND_SOC_AC97_BUS
+
++config SND_S3C2450_SOC_AC97
++ tristate
++ select AC97_BUS
++ select SND_AC97_CODEC
++ select SND_SOC_AC97_BUS
++
++config SND_S3C24XX_SOC_SMDK2450_WM9713
++ tristate "SoC AC97 Audio support for SMDK2450 - WM9713"
++ depends on SND_S3C_SOC && (CPU_S3C2450 || CPU_S3C2416)
++ select SND_S3C2450_SOC_AC97
++ select SND_SOC_WM9713
++ help
++ Say Y if you want to add support for SoC audio on smdk2450
++ with the WM9713.
++choice
++ prompt "SMDK Record Path Select"
++ depends on SND_S3C24XX_SOC_SMDK2450_WM9713
++
++config SOUND_WM9713_INPUT_STREAM_LINE
++ bool "Input Stream is LINE-IN"
++ depends on SND_S3C24XX_SOC_SMDK2450_WM9713
++ help
++ Say Y here to make input stream as LINE-IN.
++
++config SOUND_WM9713_INPUT_STREAM_MIC
++ bool "Input Stream is MIC"
++ depends on SND_S3C24XX_SOC_SMDK2450_WM9713
++ help
++ Say Y here to make input stream as MIC.
++endchoice
++
++
++
+ config SND_S3C24XX_SOC_NEO1973_WM8753
+ tristate "SoC I2S Audio support for NEO1973 - WM8753"
+- depends on SND_S3C24XX_SOC && MACH_NEO1973_GTA01
+- select SND_S3C24XX_SOC_I2S
++ depends on SND_S3C_SOC && MACH_NEO1973_GTA01
++ select SND_S3C_SOC_I2S
+ select SND_SOC_WM8753
+ help
+ Say Y if you want to add support for SoC audio on smdk2440
+@@ -27,11 +69,21 @@ config SND_S3C24XX_SOC_NEO1973_WM8753
+
+ config SND_S3C24XX_SOC_SMDK2443_WM9710
+ tristate "SoC AC97 Audio support for SMDK2443 - WM9710"
+- depends on SND_S3C24XX_SOC && MACH_SMDK2443
++ depends on SND_S3C_SOC && MACH_SMDK2443
+ select SND_S3C2443_SOC_AC97
+ select SND_SOC_AC97_CODEC
+ help
+ Say Y if you want to add support for SoC audio on smdk2443
+ with the WM9710.
+
++config SND_S3C24XX_SOC_SMDK2450_WM8580
++ tristate "SoC I2S Audio support for SMDK2450 - WM8580"
++ depends on SND_S3C_SOC && (CPU_S3C2450 || CPU_S3C2416)
++ select SND_S3C2450_SOC_I2S
++ select SND_SOC_WM8580
++ select SND_SOC_I2S_V40
++ help
++ Say Y if you want to add support for SoC audio on smdk2450
++ with the WM8580.
+
++endmenu
+diff --git a/sound/soc/s3c24xx/Makefile b/sound/soc/s3c24xx/Makefile
+index 13c92f0..3739c67 100644
+--- a/sound/soc/s3c24xx/Makefile
++++ b/sound/soc/s3c24xx/Makefile
+@@ -1,15 +1,24 @@
+ # S3c24XX Platform Support
+-snd-soc-s3c24xx-objs := s3c24xx-pcm.o
+ snd-soc-s3c24xx-i2s-objs := s3c24xx-i2s.o
++snd-soc-s3c-objs := s3c-pcm.o
++snd-soc-s3c-i2s-objs := s3c-i2s.o
+ snd-soc-s3c2443-ac97-objs := s3c2443-ac97.o
++snd-soc-s3c2450-ac97-objs := s3c2450-ac97.o
++snd-soc-s3c2450-i2s-objs := s3c2450-i2s.o
+
+-obj-$(CONFIG_SND_S3C24XX_SOC) += snd-soc-s3c24xx.o
+-obj-$(CONFIG_SND_S3C24XX_SOC_I2S) += snd-soc-s3c24xx-i2s.o
++obj-$(CONFIG_SND_S3C_SOC) += snd-soc-s3c.o
++obj-$(CONFIG_SND_S3C_SOC_I2S) += snd-soc-s3c-i2s.o
+ obj-$(CONFIG_SND_S3C2443_SOC_AC97) += snd-soc-s3c2443-ac97.o
++obj-$(CONFIG_SND_S3C2450_SOC_AC97) += snd-soc-s3c2450-ac97.o
++obj-$(CONFIG_SND_S3C2450_SOC_I2S) += snd-soc-s3c2450-i2s.o
+
+ # S3C24XX Machine Support
+ snd-soc-neo1973-wm8753-objs := neo1973_wm8753.o
+ snd-soc-smdk2443-wm9710-objs := smdk2443_wm9710.o
++snd-soc-smdk2450-wm9713-objs := smdk2450_wm9713.o
++snd-soc-smdk2450-wm8580-objs := smdk2450_wm8580.o
+
+ obj-$(CONFIG_SND_S3C24XX_SOC_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
+ obj-$(CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o
++obj-$(CONFIG_SND_S3C24XX_SOC_SMDK2450_WM9713) += snd-soc-smdk2450-wm9713.o
++obj-$(CONFIG_SND_S3C24XX_SOC_SMDK2450_WM8580) += snd-soc-smdk2450-wm8580.o
+diff --git a/sound/soc/s3c24xx/neo1973_wm8753.c b/sound/soc/s3c24xx/neo1973_wm8753.c
+index d5a8fc2..3bbe312 100644
+--- a/sound/soc/s3c24xx/neo1973_wm8753.c
++++ b/sound/soc/s3c24xx/neo1973_wm8753.c
+@@ -39,7 +39,7 @@
+ #include <asm/arch/spi-gpio.h>
+ #include "../codecs/wm8753.h"
+ #include "lm4857.h"
+-#include "s3c24xx-pcm.h"
++#include "s3c-pcm.h"
+ #include "s3c24xx-i2s.h"
+
+ /* define the scenarios */
+diff --git a/sound/soc/s3c24xx/s3c-i2s.c b/sound/soc/s3c24xx/s3c-i2s.c
+new file mode 100644
+index 0000000..e4ce2c9
+--- /dev/null
++++ b/sound/soc/s3c24xx/s3c-i2s.c
+@@ -0,0 +1,619 @@
++/*
++ * s3c-i2s.c -- ALSA Soc Audio Layer
++ *
++ * (c) 2006 Wolfson Microelectronics PLC.
++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * (c) 2004-2005 Simtec Electronics
++ * http://armlinux.simtec.co.uk/
++ * Ben Dooks <ben@simtec.co.uk>
++ * Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ *
++ * Revision history
++ * 11th Dec 2006 Merged with Simtec driver
++ * 10th Nov 2006 Initial version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm-arm/plat-s3c64xx/regs-iis.h>
++//#include <asm/arch/regs-iis.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/audio.h>
++#include <asm/arch/dma.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#include "s3c-pcm.h"
++#include "s3c-i2s.h"
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++/* used to disable sysclk if external crystal is used */
++static int extclk = 0;
++module_param(extclk, int, 0);
++MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk");
++
++static struct s3c2410_dma_client s3c24xx_dma_client_out = {
++ .name = "I2S PCM Stereo out"
++};
++
++static struct s3c2410_dma_client s3c24xx_dma_client_in = {
++ .name = "I2S PCM Stereo in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
++ .client = &s3c24xx_dma_client_out,
++ .channel = DMACH_I2S_OUT,
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
++ .dma_size = 2,
++#else
++ .dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFO,
++ .dma_size = 4,
++#endif
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
++ .client = &s3c24xx_dma_client_in,
++ .channel = DMACH_I2S_IN,
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFORX,
++ .dma_size = 2,
++#else
++ .dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFORX,
++ .dma_size = 4,
++#endif
++};
++
++struct s3c24xx_i2s_info {
++ void __iomem *regs;
++ struct clk *iis_clk;
++ int master;
++};
++static struct s3c24xx_i2s_info s3c24xx_i2s;
++
++static void s3c24xx_snd_txctrl(int on)
++{
++ u32 iisfcon;
++ u32 iiscon;
++ u32 iismod;
++
++ s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on);
++
++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
++ iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
++
++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++
++ if (on) {
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
++ iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
++ iiscon &= ~S3C2410_IISCON_TXIDLE;
++ iismod |= S3C2410_IISMOD_TXMODE;
++#else
++ iiscon |= S3C_IIS0CON_I2SACTIVE;
++#endif
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iisfcon &= ~S3C2410_IISFCON_TXENABLE;
++ iisfcon &= ~S3C2410_IISFCON_TXDMA;
++ iiscon |= S3C2410_IISCON_TXIDLE;
++ iiscon &= ~S3C2410_IISCON_TXDMAEN;
++ iismod &= ~S3C2410_IISMOD_TXMODE;
++#else
++ iiscon &=~(S3C_IIS0CON_I2SACTIVE);
++ iismod &= ~S3C_IIS0MOD_TXMODE;
++#endif
++
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ }
++
++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++}
++
++static void s3c24xx_snd_rxctrl(int on)
++{
++ u32 iisfcon;
++ u32 iiscon;
++ u32 iismod;
++
++ s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on);
++
++ iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
++
++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++
++ if (on) {
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
++ iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
++ iiscon &= ~S3C2410_IISCON_RXIDLE;
++ iismod |= S3C2410_IISMOD_RXMODE;
++#else
++ iiscon |= S3C_IIS0CON_I2SACTIVE;
++#endif
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iisfcon &= ~S3C2410_IISFCON_RXENABLE;
++ iisfcon &= ~S3C2410_IISFCON_RXDMA;
++ iiscon |= S3C2410_IISCON_RXIDLE;
++ iiscon &= ~S3C2410_IISCON_RXDMAEN;
++ iismod &= ~S3C2410_IISMOD_RXMODE;
++#else
++ iiscon &=~ S3C_IIS0CON_I2SACTIVE;
++ iismod &= ~S3C_IIS0MOD_RXMODE;
++#endif
++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++
++ }
++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++}
++
++/*
++ * Wait for the LR signal to allow synchronisation to the L/R clock
++ * from the codec. May only be needed for slave mode.
++ */
++static int s3c24xx_snd_lrsync(void)
++{
++ u32 iiscon;
++ unsigned long timeout = jiffies + msecs_to_jiffies(5);
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ while (1) {
++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++ if (iiscon & S3C2410_IISCON_LRINDEX)
++ break;
++
++ if (timeout < jiffies)
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++/*
++ * Check whether CPU is the master or slave
++ */
++static inline int s3c24xx_snd_is_clkmaster(void)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
++}
++
++/*
++ * Set S3C24xx I2S DAI format
++ */
++static int s3c_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
++ unsigned int fmt)
++{
++#if 0
++ u32 iismod;
++
++ s3cdbg("Entered %s: fmt = %d\n", __FUNCTION__, fmt);
++
++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
++
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBM_CFM:
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iismod |= S3C2410_IISMOD_SLAVE;
++#else
++ iismod |= S3C2410_IISMOD_MASTER;
++#endif
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_LEFT_J:
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iismod |= S3C2410_IISMOD_MSB;
++#else
++ iismod |= S3C_IIS0MOD_MSB;
++#endif
++ break;
++ case SND_SOC_DAIFMT_I2S:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++#endif
++ return 0;
++
++}
++
++static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++
++ unsigned long iiscon;
++ unsigned long iismod;
++ unsigned long iisfcon;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ /*Set I2C port to controll WM8753 codec*/
++ gpio_pullup(S3C_GPB5, 0);
++ gpio_pullup(S3C_GPB6, 0);
++ gpio_set_pin(S3C_GPB5, S3C_GPB5_I2C_SCL);
++ gpio_set_pin(S3C_GPB6, S3C_GPB6_I2C_SDA);
++
++ s3c24xx_i2s.master = 1;
++
++ /* Configure the I2S pins in correct mode */
++ gpio_set_pin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0);
++
++ if (s3c24xx_i2s.master && !extclk){
++ s3cdbg("Setting Clock Output as we are Master\n");
++ gpio_set_pin(S3C_GPD0,S3C_GPD0_I2S_CLK0);
++
++ }
++ gpio_set_pin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0);
++ gpio_set_pin(S3C_GPD3,S3C_GPD3_I2S_DI0);
++ gpio_set_pin(S3C_GPD4,S3C_GPD4_I2S_DO0);
++
++ /* pull-up-enable, pull-down-disable*/
++ gpio_pullup(S3C_GPD0, 0x2);
++ gpio_pullup(S3C_GPD1, 0x2);
++ gpio_pullup(S3C_GPD2, 0x2);
++ gpio_pullup(S3C_GPD3, 0x2);
++ gpio_pullup(S3C_GPD4, 0x2);
++
++ s3cdbg("substream->stream : %d\n", substream->stream);
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
++ } else {
++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
++ }
++
++ /* Working copies of registers */
++ iiscon = readl(Ss3c24xx_i2s.regs + S3C_IIS0CON);
++ iismod = readl(S3C_IIS0MOD);
++ iisfcon = readl(S3C_IIS0FIC);
++ /* is port used by another stream */
++ if (!(iiscon & S3C_IIS0CON_I2SACTIVE)) {
++
++ // Clear BFS field [2:1]
++ iismod &= ~(0x3<<1);
++ iismod |= S3C_IIS0MOD_32FS | S3C_IIS0MOD_INTERNAL_CLK;
++
++ if (!s3c24xx_i2s.master)
++ iismod |= S3C_IIS0MOD_IMS_SLAVE;
++ else
++ iismod |= S3C_IIS0MOD_IMS_EXTERNAL_MASTER;
++ }
++
++ /* enable TX & RX all to support Full-duplex */
++ iismod |= S3C_IIS0MOD_TXRXMODE;
++ iiscon |= S3C_IIS0CON_TXDMACTIVE;
++ iisfcon |= S3C_IIS_TX_FLUSH;
++ iiscon |= S3C_IIS0CON_RXDMACTIVE;
++ iisfcon |= S3C_IIS_RX_FLUSH;
++
++ writel(iiscon, S3C_IIS0CON);
++ writel(iismod, S3C_IIS0MOD);
++ writel(iisfcon, S3C_IIS0FIC);
++
++ // Tx, Rx fifo flush bit clear
++ iisfcon &= ~(S3C_IIS_TX_FLUSH | S3C_IIS_RX_FLUSH);
++ writel(iisfcon, S3C_IIS0FIC);
++
++ s3cdbg("IISCON: %lx IISMOD: %lx", iiscon, iismod);
++
++ return 0;
++
++}
++
++static int s3c_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ int ret = 0;
++
++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (!s3c24xx_snd_is_clkmaster()) {
++ ret = s3c24xx_snd_lrsync();
++ if (ret)
++ goto exit_err;
++ }
++
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(1);
++ else
++ s3c24xx_snd_txctrl(1);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(0);
++ else
++ s3c24xx_snd_txctrl(0);
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++exit_err:
++ return ret;
++}
++
++static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream)
++{
++ unsigned long iismod, iiscon;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ iismod=readl(S3C_IIS0MOD);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ iismod &= ~S3C_IIS0MOD_TXMODE;
++ } else {
++ iismod &= ~S3C_IIS0MOD_RXMODE;
++ }
++
++ writel(iismod,S3C_IIS0MOD);
++
++ iiscon=readl(S3C_IIS0CON);
++ iiscon &= !S3C_IIS0CON_I2SACTIVE;
++ writel(iiscon,S3C_IIS0CON);
++
++ /* Clock disable
++ * PCLK & SCLK gating disable
++ */
++ __raw_writel(__raw_readl(S3C_PCLK_GATE)&~(S3C_CLKCON_PCLK_IIS0), S3C_PCLK_GATE);
++ __raw_writel(__raw_readl(S3C_SCLK_GATE)&~(S3C_CLKCON_SCLK_AUDIO0), S3C_SCLK_GATE);
++
++ /* EPLL disable */
++ __raw_writel(__raw_readl(S3C_EPLL_CON0)&~(1<<31) ,S3C_EPLL_CON0);
++
++}
++
++
++/*
++ * Set S3C24xx Clock source
++ */
++static int s3c_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
++
++ s3cdbg("Entered %s : clk_id = %d\n", __FUNCTION__, clk_id);
++
++ iismod &= ~S3C2440_IISMOD_MPLL;
++
++ switch (clk_id) {
++ case S3C24XX_CLKSRC_PCLK:
++ break;
++ case S3C24XX_CLKSRC_MPLL:
++ iismod |= S3C2440_IISMOD_MPLL;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ return 0;
++}
++
++/*
++ * Set S3C24xx Clock dividers
++ */
++static int s3c_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
++ int div_id, int div)
++{
++ u32 reg;
++
++ s3cdbg("Entered %s : div_id = %d, div = %d\n", __FUNCTION__, div_id, div);
++
++ switch (div_id) {
++ case S3C24XX_DIV_MCLK:
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
++ writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
++#endif
++ break;
++ case S3C24XX_DIV_BCLK:
++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
++ writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ break;
++ case S3C24XX_DIV_PRESCALER:
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++ writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
++#else
++ writel(div|(1<<15),S3C_IIS0PSR);
++#endif
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++/*
++ * To avoid duplicating clock code, allow machine driver to
++ * get the clockrate from here.
++ */
++u32 s3c24xx_i2s_get_clockrate(void)
++{
++ return clk_get_rate(s3c24xx_i2s.iis_clk);
++}
++EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
++#endif
++
++static int s3c_i2s_probe(struct platform_device *pdev)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ s3c24xx_i2s.regs = ioremap(S3C24XX_PA_IIS, 0x100);
++ if (s3c24xx_i2s.regs == NULL)
++ return -ENXIO;
++
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
++ if (s3c24xx_i2s.iis_clk == NULL) {
++ s3cdbg("failed to get iis_clock\n");
++ return -ENODEV;
++ }
++ clk_enable(s3c24xx_i2s.iis_clk);
++
++ /* Configure the I2S pins in correct mode */
++ s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
++ s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
++
++ writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
++
++ /* Configure the I2S pins in correct mode */
++ gpio_set_pin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0);
++
++ gpio_set_pin(S3C_GPD0,S3C_GPD0_I2S_CLK0);
++
++ gpio_set_pin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0);
++ gpio_set_pin(S3C_GPD3,S3C_GPD3_I2S_DI0);
++ gpio_set_pin(S3C_GPD4,S3C_GPD4_I2S_DO0);
++
++ /* pull-up-enable, pull-down-disable*/
++ gpio_pullup(S3C_GPD0, 0x2);
++ gpio_pullup(S3C_GPD1, 0x2);
++ gpio_pullup(S3C_GPD2, 0x2);
++ gpio_pullup(S3C_GPD3, 0x2);
++ gpio_pullup(S3C_GPD4, 0x2);
++
++ writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
++ s3c24xx_snd_txctrl(0);
++ s3c24xx_snd_rxctrl(0);
++#endif
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_i2s_suspend(struct platform_device *dev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++static int s3c_i2s_resume(struct platform_device *pdev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++#else
++#define s3c_i2s_suspend NULL
++#define s3c_i2s_resume NULL
++#endif
++
++
++#define S3C24XX_I2S_RATES \
++ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
++
++struct snd_soc_cpu_dai s3c_i2s_dai = {
++ .name = "s3c-i2s",
++ .id = 0,
++ .type = SND_SOC_DAI_I2S,
++ .probe = s3c_i2s_probe,
++ .suspend = s3c_i2s_suspend,
++ .resume = s3c_i2s_resume,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
++ .capture = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .shutdown = s3c64xx_i2s_shutdown,
++ .trigger = s3c_i2s_trigger,
++ .hw_params = s3c_i2s_hw_params,},
++ .dai_ops = {
++ .set_fmt = s3c_i2s_set_fmt,
++ .set_clkdiv = s3c_i2s_set_clkdiv,
++ .set_sysclk = s3c_i2s_set_sysclk,
++ },
++};
++EXPORT_SYMBOL_GPL(s3c_i2s_dai);
++
++/* Module information */
++MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
++MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c24xx/s3c-i2s.h b/sound/soc/s3c24xx/s3c-i2s.h
+new file mode 100644
+index 0000000..534f3be
+--- /dev/null
++++ b/sound/soc/s3c24xx/s3c-i2s.h
+@@ -0,0 +1,43 @@
++/*
++ * s3c24xx-i2s.c -- ALSA Soc Audio Layer
++ *
++ * Copyright 2005 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 10th Nov 2006 Initial version.
++ */
++
++#ifndef S3C24XXI2S_H_
++#define S3C24XXI2S_H_
++
++/* clock sources */
++#define S3C24XX_CLKSRC_PCLK 0
++#define S3C24XX_CLKSRC_MPLL 1
++
++/* Clock dividers */
++#define S3C24XX_DIV_MCLK 0
++#define S3C24XX_DIV_BCLK 1
++#define S3C24XX_DIV_PRESCALER 2
++
++/* prescaler */
++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410)
++#define S3C24XX_PRESCALE(a,b) \
++ (((a - 1) << S3C2410_IISPSR_INTSHIFT) | ((b - 1) << S3C2410_IISPSR_EXTSHFIT))
++#else
++#define S3C24XX_PRESCALE(a,b) \
++ (((a - 1) << S3C_IISPSR_INTSHIFT) | ((b - 1) << S3C_IISPSR_INTSHIFT))
++#endif
++
++u32 s3c24xx_i2s_get_clockrate(void);
++
++extern struct snd_soc_cpu_dai s3c_i2s_dai;
++extern struct snd_soc_cpu_dai s3c_i2s_v40_dai;
++
++#endif /*S3C24XXI2S_H_*/
+diff --git a/sound/soc/s3c24xx/s3c-pcm.c b/sound/soc/s3c24xx/s3c-pcm.c
+new file mode 100644
+index 0000000..a0d4d37
+--- /dev/null
++++ b/sound/soc/s3c24xx/s3c-pcm.c
+@@ -0,0 +1,544 @@
++/*
++ * s3c-pcm.c -- ALSA Soc Audio Layer
++ *
++ * (c) 2006 Wolfson Microelectronics PLC.
++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * (c) 2004-2005 Simtec Electronics
++ * http://armlinux.simtec.co.uk/
++ * Ben Dooks <ben@simtec.co.uk>
++ * Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 11th Dec 2006 Merged with Simtec driver
++ * 10th Nov 2006 Initial version.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#include <asm/dma.h>
++#include <asm/io.h>
++#include <asm/hardware.h>
++#include <asm/arch/dma.h>
++#include <asm/arch/audio.h>
++
++#include "s3c-pcm.h"
++
++#if defined CONFIG_SND_S3C6400_SOC_AC97
++#define MAIN_DMA_CH 1
++#else /*S3C6400 I2S */
++#define MAIN_DMA_CH 0
++#endif
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++static const struct snd_pcm_hardware s3c24xx_pcm_hardware = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE |
++ SNDRV_PCM_FMTBIT_U16_LE |
++ SNDRV_PCM_FMTBIT_U8 |
++ SNDRV_PCM_FMTBIT_S24_LE |
++ SNDRV_PCM_FMTBIT_S8,
++ .channels_min = 2,
++ .channels_max = 2,
++ .buffer_bytes_max = 128*1024,
++ .period_bytes_min = PAGE_SIZE,
++ .period_bytes_max = PAGE_SIZE*2,
++ .periods_min = 2,
++ .periods_max = 128,
++ .fifo_size = 32,
++};
++
++struct s3c24xx_runtime_data {
++ spinlock_t lock;
++ int state;
++ unsigned int dma_loaded;
++ unsigned int dma_limit;
++ unsigned int dma_period;
++ dma_addr_t dma_start;
++ dma_addr_t dma_pos;
++ dma_addr_t dma_end;
++ struct s3c24xx_pcm_dma_params *params;
++};
++
++/* s3c24xx_pcm_enqueue
++ *
++ * place a dma buffer onto the queue for the dma system
++ * to handle.
++*/
++static void s3c24xx_pcm_enqueue(struct snd_pcm_substream *substream)
++{
++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
++ dma_addr_t pos = prtd->dma_pos;
++ int ret;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ while (prtd->dma_loaded < prtd->dma_limit) {
++ unsigned long len = prtd->dma_period;
++
++ s3cdbg("dma_loaded: %d\n",prtd->dma_loaded);
++
++ if ((pos + len) > prtd->dma_end) {
++ len = prtd->dma_end - pos;
++ s3cdbg(KERN_DEBUG "%s: corrected dma len %ld\n",
++ __FUNCTION__, len);
++ }
++
++ ret = s3c2410_dma_enqueue(prtd->params->channel,
++ substream, pos, len);
++
++ if (ret == 0) {
++ prtd->dma_loaded++;
++ pos += prtd->dma_period;
++ if (pos >= prtd->dma_end)
++ pos = prtd->dma_start;
++ } else
++ break;
++ }
++
++ prtd->dma_pos = pos;
++}
++
++static void s3c24xx_audio_buffdone(struct s3c2410_dma_chan *channel,
++ void *dev_id, int size,
++ enum s3c2410_dma_buffresult result)
++{
++ struct snd_pcm_substream *substream = dev_id;
++ struct s3c24xx_runtime_data *prtd;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ if (result == S3C2410_RES_ABORT || result == S3C2410_RES_ERR)
++ return;
++ else {
++ prtd = substream->runtime->private_data;
++
++ if (substream)
++ snd_pcm_period_elapsed(substream);
++ else
++ return;
++
++ spin_lock(&prtd->lock);
++ if (prtd->state & ST_RUNNING) {
++ prtd->dma_loaded--;
++ s3c24xx_pcm_enqueue(substream);
++ }
++
++ spin_unlock(&prtd->lock);
++ }
++#if 0
++ struct snd_pcm_substream *substream = dev_id;
++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ if (result == S3C2410_RES_ABORT || result == S3C2410_RES_ERR)
++ return;
++
++ snd_pcm_period_elapsed(substream);
++
++ spin_lock(&prtd->lock);
++ if (prtd->state & ST_RUNNING) {
++ prtd->dma_loaded--;
++ s3c24xx_pcm_enqueue(substream);
++ }
++
++ spin_unlock(&prtd->lock);
++#endif
++}
++
++static int s3c24xx_pcm_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct s3c24xx_runtime_data *prtd = runtime->private_data;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct s3c24xx_pcm_dma_params *dma = rtd->dai->cpu_dai->dma_data;
++ unsigned long totbytes = params_buffer_bytes(params);
++ int ret=0;
++
++ s3cdbg("Entered %s, params = %p \n", __FUNCTION__, prtd->params);
++
++ /* return if this is a bufferless transfer e.g.
++ * codec <--> BT codec or GSM modem -- lg FIXME */
++ if (!dma)
++ return 0;
++
++ /* this may get called several times by oss emulation
++ * with different params */
++ if (prtd->params == NULL) {
++ prtd->params = dma;
++ s3cdbg("params %p, client %p, channel %d\n", prtd->params,
++ prtd->params->client, prtd->params->channel);
++
++
++ /* prepare DMA */
++ ret = s3c2410_dma_request(prtd->params->channel,
++ prtd->params->client, NULL);
++
++ if (ret) {
++ printk(KERN_ERR "failed to get dma channel\n");
++ return ret;
++ }
++ } else if (prtd->params != dma) {
++ s3c2410_dma_free(prtd->params->channel, prtd->params->client);
++ prtd->params = dma;
++ s3cdbg("params %p, client %p, channel %d\n", prtd->params,
++ prtd->params->client, prtd->params->channel);
++
++
++ /* prepare DMA */
++ ret = s3c2410_dma_request(prtd->params->channel,
++ prtd->params->client, NULL);
++
++ if (ret) {
++ printk(KERN_ERR "failed to get dma channel\n");
++ return ret;
++ }
++ }
++
++ /* channel needs configuring for mem=>device, increment memory addr,
++ * sync to pclk, half-word transfers to the IIS-FIFO. */
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ s3c2410_dma_devconfig(prtd->params->channel,
++ S3C2410_DMASRC_MEM, S3C2410_DISRCC_INC |
++ S3C2410_DISRCC_APB, prtd->params->dma_addr);
++
++ s3c2410_dma_config(prtd->params->channel,
++ prtd->params->dma_size,
++ S3C2410_DCON_SYNC_PCLK |
++ S3C2410_DCON_HANDSHAKE);
++ } else {
++ s3c2410_dma_config(prtd->params->channel,
++ prtd->params->dma_size,
++ S3C2410_DCON_HANDSHAKE |
++ S3C2410_DCON_SYNC_PCLK);
++
++ s3c2410_dma_devconfig(prtd->params->channel,
++ S3C2410_DMASRC_HW, 0x3,
++ prtd->params->dma_addr);
++ }
++
++#else
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ s3c2410_dma_devconfig(prtd->params->channel,
++ S3C2410_DMASRC_MEM, 0,
++ prtd->params->dma_addr);
++
++ s3c2410_dma_config(prtd->params->channel,
++ prtd->params->dma_size, 0);
++ } else {
++ s3c2410_dma_devconfig(prtd->params->channel,
++ S3C2410_DMASRC_HW, 0,
++ prtd->params->dma_addr);
++
++ s3c2410_dma_config(prtd->params->channel,
++ prtd->params->dma_size, 0);
++ }
++#endif
++
++ s3c2410_dma_set_buffdone_fn(prtd->params->channel,
++ s3c24xx_audio_buffdone);
++
++ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
++
++ runtime->dma_bytes = totbytes;
++
++ spin_lock_irq(&prtd->lock);
++ prtd->dma_loaded = 0;
++ prtd->dma_limit = runtime->hw.periods_min;
++ prtd->dma_period = params_period_bytes(params);
++ prtd->dma_start = runtime->dma_addr;
++ prtd->dma_pos = prtd->dma_start;
++ prtd->dma_end = prtd->dma_start + totbytes;
++ spin_unlock_irq(&prtd->lock);
++
++ s3cdbg("Entered %s, line %d \n", __FUNCTION__, __LINE__);
++ return 0;
++}
++
++static int s3c24xx_pcm_hw_free(struct snd_pcm_substream *substream)
++{
++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ /* TODO - do we need to ensure DMA flushed */
++ snd_pcm_set_runtime_buffer(substream, NULL);
++
++ if (prtd->params) {
++ s3c2410_dma_free(prtd->params->channel, prtd->params->client);
++ prtd->params = NULL;
++ }
++
++ return 0;
++}
++
++static int s3c24xx_pcm_prepare(struct snd_pcm_substream *substream)
++{
++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
++ int ret = 0;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ /* return if this is a bufferless transfer e.g.
++ * codec <--> BT codec or GSM modem -- lg FIXME */
++ if (!prtd->params)
++ return 0;
++#endif
++
++ /* flush the DMA channel */
++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH);
++
++ prtd->dma_loaded = 0;
++
++ prtd->dma_pos = prtd->dma_start;
++
++ /* enqueue dma buffers */
++ s3c24xx_pcm_enqueue(substream);
++
++ return ret;
++}
++
++static int s3c24xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data;
++ int ret = 0;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ spin_lock(&prtd->lock);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ prtd->state |= ST_RUNNING;
++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_START);
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_STARTED);
++#endif
++ break;
++
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ prtd->state &= ~ST_RUNNING;
++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_STOP);
++ break;
++
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ spin_unlock(&prtd->lock);
++
++ return ret;
++}
++
++static snd_pcm_uframes_t
++ s3c24xx_pcm_pointer(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct s3c24xx_runtime_data *prtd = runtime->private_data;
++ unsigned long res;
++ dma_addr_t src, dst;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ spin_lock(&prtd->lock);
++
++ s3c2410_dma_getposition(prtd->params->channel, &src, &dst);
++
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ res = dst - prtd->dma_start;
++ else
++ res = src - prtd->dma_start;
++
++ spin_unlock(&prtd->lock);
++
++ s3cdbg("Pointer %x %x\n",src,dst);
++
++ /* we seem to be getting the odd error from the pcm library due
++ * to out-of-bounds pointers. this is maybe due to the dma engine
++ * not having loaded the new values for the channel before being
++ * callled... (todo - fix )
++ */
++
++ if (res >= snd_pcm_lib_buffer_bytes(substream)) {
++ if (res == snd_pcm_lib_buffer_bytes(substream))
++ res = 0;
++ }
++
++ return bytes_to_frames(substream->runtime, res);
++}
++
++static int s3c24xx_pcm_open(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct s3c24xx_runtime_data *prtd;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ snd_soc_set_runtime_hwparams(substream, &s3c24xx_pcm_hardware);
++
++ prtd = kzalloc(sizeof(struct s3c24xx_runtime_data), GFP_KERNEL);
++ if (prtd == NULL)
++ return -ENOMEM;
++
++ spin_lock_init(&prtd->lock);
++
++ runtime->private_data = prtd;
++ return 0;
++}
++
++static int s3c24xx_pcm_close(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct s3c24xx_runtime_data *prtd = runtime->private_data;
++
++ s3cdbg("Entered %s, prtd = %p\n", __FUNCTION__, prtd);
++
++ if (prtd)
++ kfree(prtd);
++ else
++ printk("s3c24xx_pcm_close called with prtd == NULL\n");
++
++ return 0;
++}
++
++static int s3c24xx_pcm_mmap(struct snd_pcm_substream *substream,
++ struct vm_area_struct *vma)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ return dma_mmap_writecombine(substream->pcm->card->dev, vma,
++ runtime->dma_area,
++ runtime->dma_addr,
++ runtime->dma_bytes);
++}
++
++static struct snd_pcm_ops s3c24xx_pcm_ops = {
++ .open = s3c24xx_pcm_open,
++ .close = s3c24xx_pcm_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = s3c24xx_pcm_hw_params,
++ .hw_free = s3c24xx_pcm_hw_free,
++ .prepare = s3c24xx_pcm_prepare,
++ .trigger = s3c24xx_pcm_trigger,
++ .pointer = s3c24xx_pcm_pointer,
++ .mmap = s3c24xx_pcm_mmap,
++};
++
++static int s3c24xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
++{
++ struct snd_pcm_substream *substream = pcm->streams[stream].substream;
++ struct snd_dma_buffer *buf = &substream->dma_buffer;
++ size_t size = s3c24xx_pcm_hardware.buffer_bytes_max;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ buf->dev.type = SNDRV_DMA_TYPE_DEV;
++ buf->dev.dev = pcm->card->dev;
++ buf->private_data = NULL;
++ buf->area = dma_alloc_writecombine(pcm->card->dev, size,
++ &buf->addr, GFP_KERNEL);
++ if (!buf->area)
++ return -ENOMEM;
++ buf->bytes = size;
++ return 0;
++}
++
++static void s3c24xx_pcm_free_dma_buffers(struct snd_pcm *pcm)
++{
++ struct snd_pcm_substream *substream;
++ struct snd_dma_buffer *buf;
++ int stream;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ for (stream = 0; stream < 2; stream++) {
++ substream = pcm->streams[stream].substream;
++ if (!substream)
++ continue;
++
++ buf = &substream->dma_buffer;
++ if (!buf->area)
++ continue;
++
++ dma_free_writecombine(pcm->card->dev, buf->bytes,
++ buf->area, buf->addr);
++ buf->area = NULL;
++ }
++}
++
++static u64 s3c24xx_pcm_dmamask = DMA_32BIT_MASK;
++
++static int s3c24xx_pcm_new(struct snd_card *card,
++ struct snd_soc_codec_dai *dai, struct snd_pcm *pcm)
++{
++ int ret = 0;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ if (!card->dev->dma_mask)
++ card->dev->dma_mask = &s3c24xx_pcm_dmamask;
++ if (!card->dev->coherent_dma_mask)
++ card->dev->coherent_dma_mask = 0xffffffff;
++
++ if (dai->playback.channels_min) {
++ ret = s3c24xx_pcm_preallocate_dma_buffer(pcm,
++ SNDRV_PCM_STREAM_PLAYBACK);
++ if (ret)
++ goto out;
++ }
++
++ if (dai->capture.channels_min) {
++ ret = s3c24xx_pcm_preallocate_dma_buffer(pcm,
++ SNDRV_PCM_STREAM_CAPTURE);
++ if (ret)
++ goto out;
++ }
++ out:
++ return ret;
++}
++
++struct snd_soc_platform s3c24xx_soc_platform = {
++ .name = "s3c24xx-audio",
++ .pcm_ops = &s3c24xx_pcm_ops,
++ .pcm_new = s3c24xx_pcm_new,
++ .pcm_free = s3c24xx_pcm_free_dma_buffers,
++};
++
++EXPORT_SYMBOL_GPL(s3c24xx_soc_platform);
++
++MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
++MODULE_DESCRIPTION("Samsung S3C24XX PCM DMA module");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c24xx/s3c-pcm.h b/sound/soc/s3c24xx/s3c-pcm.h
+new file mode 100644
+index 0000000..674d010
+--- /dev/null
++++ b/sound/soc/s3c24xx/s3c-pcm.h
+@@ -0,0 +1,40 @@
++/*
++ * s3c24xx-pcm.h --
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * ALSA PCM interface for the Samsung S3C24xx CPU
++ */
++
++#ifndef _S3C24XX_PCM_H
++#define _S3C24XX_PCM_H
++
++#define ST_RUNNING (1<<0)
++#define ST_OPENED (1<<1)
++
++struct s3c24xx_pcm_dma_params {
++ struct s3c2410_dma_client *client; /* stream identifier */
++ int channel; /* Channel ID */
++ dma_addr_t dma_addr;
++ int dma_size; /* Size of the DMA transfer */
++};
++
++#define S3C24XX_DAI_I2S 0
++
++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
++#define S3CPCM_DCON 0
++#define S3CPCM_HWCFG 0
++#else
++//#include <asm/arch/dma.h>
++#define S3CPCM_DCON S3C2410_DCON_SYNC_PCLK|S3C2410_DCON_HANDSHAKE
++#define S3CPCM_HWCFG S3C2410_DISRCC_INC|S3C2410_DISRCC_APB
++#endif
++
++/* platform data */
++extern struct snd_soc_platform s3c24xx_soc_platform;
++extern struct snd_ac97_bus_ops s3c24xx_ac97_ops;
++
++#endif
+diff --git a/sound/soc/s3c24xx/s3c2443-ac97.c b/sound/soc/s3c24xx/s3c2443-ac97.c
+index 758a263..f9a5c78 100644
+--- a/sound/soc/s3c24xx/s3c2443-ac97.c
++++ b/sound/soc/s3c24xx/s3c2443-ac97.c
+@@ -39,7 +39,7 @@
+ #include <asm/dma.h>
+ #include <asm/arch/dma.h>
+
+-#include "s3c24xx-pcm.h"
++#include "s3c-pcm.h"
+ #include "s3c24xx-ac97.h"
+
+ struct s3c24xx_ac97_info {
+diff --git a/sound/soc/s3c24xx/s3c2450-ac97.c b/sound/soc/s3c24xx/s3c2450-ac97.c
+new file mode 100644
+index 0000000..1f0378c
+--- /dev/null
++++ b/sound/soc/s3c24xx/s3c2450-ac97.c
+@@ -0,0 +1,561 @@
++/*
++ * s3c2450-ac97.c -- ALSA Soc Audio Layer
++ *
++ * (c) 2007 Wolfson Microelectronics PLC.
++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ * All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Revision history
++ * 21st Mar 2007 Initial Version
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/wait.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/ac97_codec.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm-arm/plat-s3c/regs-ac97.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm-arm/arch/regs-s3c-clock.h>
++#include <asm/arch/audio.h>
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++
++#include "s3c-pcm.h"
++#include "s3c24xx-ac97.h"
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++extern struct clk *clk_get(struct device *dev, const char *id);
++extern int clk_enable(struct clk *clk);
++extern void clk_disable(struct clk *clk);
++
++struct s3c24xx_ac97_info {
++ void __iomem *regs;
++ struct clk *ac97_clk;
++};
++static struct s3c24xx_ac97_info s3c24xx_ac97;
++
++static u32 codec_ready;
++static DEFINE_MUTEX(ac97_mutex);
++static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
++
++static unsigned short s3c24xx_ac97_read(struct snd_ac97 *ac97,
++ unsigned short reg)
++{
++ u32 ac_glbctrl;
++ u32 ac_codec_cmd;
++ u32 stat, addr, data;
++
++ s3cdbg("Entered %s: reg=0x%x\n", __FUNCTION__, reg);
++
++ mutex_lock(&ac97_mutex);
++
++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
++ ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++
++ udelay(1000);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
++ addr = (stat >> 16) & 0x7f;
++ data = (stat & 0xffff);
++
++ wait_event_timeout(gsr_wq,addr==reg,1);
++ if(addr!=reg){
++ printk(KERN_ERR"AC97: read error (ac97_reg=%x addr=%x)\n", reg, addr);
++ printk(KERN_ERR"Check audio codec jumpper settings\n\n");
++ goto out;
++ }
++
++out: mutex_unlock(&ac97_mutex);
++ return (unsigned short)data;
++}
++
++static void s3c24xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
++ unsigned short val)
++{
++ u32 ac_glbctrl;
++ u32 ac_codec_cmd;
++ u32 stat, data;
++
++ s3cdbg("Entered %s: reg=0x%x, val=0x%x\n", __FUNCTION__,reg,val);
++
++ mutex_lock(&ac97_mutex);
++
++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
++ ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++
++ udelay(50);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++
++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++ data = (stat & 0xffff);
++
++ wait_event_timeout(gsr_wq,data==val,1);
++ if(data!=val){
++ printk("%s: write error (ac97_val=%x data=%x)\n",
++ __FUNCTION__, val, data);
++ }
++
++ mutex_unlock(&ac97_mutex);
++}
++
++static void s3c24xx_ac97_warm_reset(struct snd_ac97 *ac97)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_WARMRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_WARMRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
++ S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_ACLINKON;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ udelay(1000);
++}
++
++static void s3c24xx_ac97_cold_reset(struct snd_ac97 *ac97)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++}
++
++static irqreturn_t s3c24xx_ac97_irq(int irq, void *dev_id)
++{
++ int status;
++ u32 ac_glbctrl, ac_glbstat;
++
++ ac_glbstat = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT);
++
++ s3cdbg("Entered %s: AC_GLBSTAT = 0x%x\n", __FUNCTION__, ac_glbstat);
++
++ status = ac_glbstat & codec_ready;
++
++
++ if (status) {
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ wake_up(&gsr_wq);
++ }
++ return IRQ_HANDLED;
++}
++
++struct snd_ac97_bus_ops soc_ac97_ops = {
++ .read = s3c24xx_ac97_read,
++ .write = s3c24xx_ac97_write,
++ .warm_reset = s3c24xx_ac97_warm_reset,
++ .reset = s3c24xx_ac97_cold_reset,
++};
++
++static struct s3c2410_dma_client s3c24xx_dma_client_out = {
++ .name = "AC97 PCM Stereo out"
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_ac97_pcm_stereo_out = {
++ .client = &s3c24xx_dma_client_out,
++ .channel = DMACH_PCM_OUT,
++ .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
++ .dma_size = 4,
++};
++
++#ifdef CONFIG_SOUND_INPUT_STREAM_MIC
++static struct s3c2410_dma_client s3c24xx_dma_client_micin = {
++ .name = "AC97 Mic Mono in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_ac97_mic_mono_in = {
++ .client = &s3c24xx_dma_client_micin,
++ .channel = DMACH_MIC_IN,
++ .dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
++ .dma_size = 4,
++};
++#else /* Input Stream is LINE-IN */
++static struct s3c2410_dma_client s3c24xx_dma_client_in = {
++ .name = "AC97 PCM Stereo Line in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_ac97_pcm_stereo_in = {
++ .client = &s3c24xx_dma_client_in,
++ .channel = DMACH_PCM_IN,
++ .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
++ .dma_size = 4,
++};
++#endif
++
++static int s3c24xx_ac97_probe(struct platform_device *pdev)
++{
++ int ret;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
++ if (s3c24xx_ac97.regs == NULL)
++ return -ENXIO;
++
++ s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
++ if (s3c24xx_ac97.ac97_clk == NULL) {
++ printk(KERN_ERR "s3c24xx-ac97 failed to get ac97_clock\n");
++ iounmap(s3c24xx_ac97.regs);
++ return -ENODEV;
++ }
++ clk_enable(s3c24xx_ac97.ac97_clk);
++
++ s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
++ s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
++ s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
++ s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
++
++ ret = request_irq(IRQ_S3C2443_AC97, s3c24xx_ac97_irq,
++ IRQF_DISABLED, "AC97", NULL);
++ if (ret < 0) {
++ printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
++ clk_disable(s3c24xx_ac97.ac97_clk);
++ clk_put(s3c24xx_ac97.ac97_clk);
++ iounmap(s3c24xx_ac97.regs);
++ }
++
++ return ret;
++}
++
++static void s3c24xx_ac97_remove(struct platform_device *pdev)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ free_irq(IRQ_S3C2443_AC97, NULL);
++ clk_disable(s3c24xx_ac97.ac97_clk);
++ clk_put(s3c24xx_ac97.ac97_clk);
++ iounmap(s3c24xx_ac97.regs);
++}
++
++static int s3c24xx_ac97_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ cpu_dai->dma_data = &s3c24xx_ac97_pcm_stereo_out;
++ else
++#ifdef CONFIG_SOUND_INPUT_STREAM_MIC
++ cpu_dai->dma_data = &s3c24xx_ac97_mic_mono_in;
++#else /* Input Stream is LINE-IN */
++ cpu_dai->dma_data = &s3c24xx_ac97_pcm_stereo_in;
++#endif
++
++ return 0;
++}
++
++static int s3c24xx_ac97_hifi_prepare(struct snd_pcm_substream *substream)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ /*
++ * register 26h : standard power down control register
++ * now set 0x0 is all power on. Need to optimize if reduce power condition
++ */
++ s3c24xx_ac97_write(0,0x26,0x0);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ /*
++ * register 02h : speaker volume
++ * now set 0x8080 is mute speaker left and right.
++ */
++ s3c24xx_ac97_write(0,0x02,0x8080);
++
++ /*
++ * register 04h : Headphone volume
++ * now set 0x0606 is Un-Mute headphone and volume set.
++ */
++ s3c24xx_ac97_write(0,0x04,0x0606);
++
++ /*
++ * register 0Ch : DAC Volume
++ * now set 0x6808 is only ON the path to headphone mixer
++ * and set the DAC volume.
++ */
++ s3c24xx_ac97_write(0,0x0c,0x6808);
++
++ /*
++ * register 1Ch : Output PGA Mux select
++ * now set 0x00aa is headphone mixer and OUT3, OUT4 enable
++ * to roud sound?
++ */
++ s3c24xx_ac97_write(0,0x1c,0x00aa);
++
++ /*
++ * register 3Ch : Power management
++ * now set 0xf933 enables headphone mixer, DAC, PLL and Vref.
++ */
++ s3c24xx_ac97_write(0,0x3c,0xf933);
++
++ /*
++ * register 3Eh : Power management
++ * now set 0xf9ff only enables headphone output PGA.
++ */
++ s3c24xx_ac97_write(0,0x3e,0xf9ff);
++ }
++ else
++ {
++ /*
++ * register 0Ch : DAC Volume
++ * now set 0xe808 is Mute DAC path to headphone,speaker,mono mixer
++ * and set the DAC volume.
++ */
++ s3c24xx_ac97_write(0,0x0c,0xe808);
++
++ /*
++ * register 12h : Record Gain
++ * 0x0F0F set right and left ADC recording volume as +22.5dB.
++ */
++ s3c24xx_ac97_write(0,0x12,0x0f0f);
++
++ /*
++ * register 3Ch : Power management
++ * now set 0xf933 enables ADC, PLL and Vref.
++ */
++ s3c24xx_ac97_write(0,0x3c,0xf8cf);
++
++#ifdef CONFIG_SOUND_INPUT_STREAM_MIC
++ /*
++ * register 5Ch : ADC SLOT Mapping
++ * now set 0x2 is Left = slot7, Right = slot8.
++ */
++ s3c24xx_ac97_write(0,0x5c,0x2);
++
++ /*
++ * register 22h : MIC input select
++ */
++ s3c24xx_ac97_write(0,0x22,0x4060);
++
++ /*
++ * register 10h : MIC Routing
++ */
++ s3c24xx_ac97_write(0,0x10,0x68);
++
++ /*
++ * register 14h : Record Routing & Mux select
++ * Default value 0xD600 is MIC
++ */
++ s3c24xx_ac97_write(0,0x14,0xfe00);
++
++ /*
++ * register 3Eh : Power management
++ * now set 0xff9f only enables LINE PGA.
++ */
++ s3c24xx_ac97_write(0,0x3e,0xbff0);
++#else /* Input Stream is LINE-IN */
++ /*
++ * register 14h : Record Routing & Mux select
++ * 0xD612 set record mux source as LINE
++ * and mute headphone, mono mixer path.
++ * Default value 0xD600 is MIC
++ */
++ s3c24xx_ac97_write(0,0x14,0xd612);
++
++ /*
++ * register 3Eh : Power management
++ * now set 0xff9f only enables LINE PGA.
++ */
++ s3c24xx_ac97_write(0,0x3e,0xff9f);
++#endif
++ }
++
++ return 0;
++}
++
++static int s3c24xx_ac97_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ switch(cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
++ else
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
++ else
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
++ break;
++ }
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ return 0;
++}
++
++#if 0
++static int s3c24xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ return -ENODEV;
++ else
++ cpu_dai->dma_data = &s3c24xx_ac97_mic_mono_in;
++
++ return 0;
++}
++
++static int s3c24xx_ac97_mic_trigger(struct snd_pcm_substream *substream,
++ int cmd)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ switch(cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
++ }
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ return 0;
++}
++#endif
++
++#define s3c24xx_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
++
++struct snd_soc_cpu_dai s3c24xx_ac97_dai[] = {
++{
++ .name = "s3c24xx-ac97",
++ .id = 0,
++ .type = SND_SOC_DAI_AC97,
++ .probe = s3c24xx_ac97_probe,
++ .remove = s3c24xx_ac97_remove,
++ .playback = {
++ .stream_name = "AC97 Playback",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = s3c24xx_AC97_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .capture = {
++ .stream_name = "AC97 Capture",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = s3c24xx_AC97_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .hw_params = s3c24xx_ac97_hw_params,
++ .prepare = s3c24xx_ac97_hifi_prepare,
++ .trigger = s3c24xx_ac97_trigger},
++},
++#if 0
++{
++ .name = "s3c24xx-ac97-mic",
++ .id = 1,
++ .type = SND_SOC_DAI_AC97,
++ .capture = {
++ .stream_name = "AC97 Mic Capture",
++ .channels_min = 1,
++ .channels_max = 1,
++ .rates = s3c24xx_AC97_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .hw_params = s3c24xx_ac97_hw_mic_params,
++ .trigger = s3c24xx_ac97_mic_trigger,},
++},
++#endif
++};
++
++EXPORT_SYMBOL_GPL(s3c24xx_ac97_dai);
++EXPORT_SYMBOL_GPL(soc_ac97_ops);
++
++MODULE_AUTHOR("Ryu Euiyoul");
++MODULE_DESCRIPTION("AC97 driver for the Samsung s3c24xx chip");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c24xx/s3c2450-i2s.c b/sound/soc/s3c24xx/s3c2450-i2s.c
+new file mode 100644
+index 0000000..f67caaf
+--- /dev/null
++++ b/sound/soc/s3c24xx/s3c2450-i2s.c
+@@ -0,0 +1,556 @@
++/*
++ * s3c-i2s.c -- ALSA Soc Audio Layer
++ *
++ * (c) 2006 Wolfson Microelectronics PLC.
++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * (c) 2004-2005 Simtec Electronics
++ * http://armlinux.simtec.co.uk/
++ * Ben Dooks <ben@simtec.co.uk>
++ * Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ *
++ * Revision history
++ * 11th Dec 2006 Merged with Simtec driver
++ * 10th Nov 2006 Initial version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++//#include <asm/arch/regs-iis.h>
++#include <asm-arm/plat-s3c24xx/regs-iis.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-gpioj.h>
++#include <asm/arch/audio.h>
++#include <asm/arch/dma.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++//#include <asm/arch/regs-s3c2450-clock.h>
++
++#include "s3c-pcm.h"
++#include "s3c-i2s.h"
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++/* used to disable sysclk if external crystal is used */
++static int extclk = 0;
++module_param(extclk, int, 0);
++MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk");
++
++static struct s3c2410_dma_client s3c24xx_dma_client_out = {
++ .name = "I2S PCM Stereo out"
++};
++
++static struct s3c2410_dma_client s3c24xx_dma_client_in = {
++ .name = "I2S PCM Stereo in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
++ .client = &s3c24xx_dma_client_out,
++#if defined CONFIG_SND_SOC_I2S_V32
++ .channel = DMACH_I2S_OUT_1,
++ .dma_addr = S3C2450_PA_IIS_1 + S3C2410_IISFIFO,
++#elif defined CONFIG_SND_SOC_I2S_V40
++ .channel = DMACH_I2S_OUT,
++ .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
++#endif
++ .dma_size = 4,
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
++ .client = &s3c24xx_dma_client_in,
++#if defined CONFIG_SND_SOC_I2S_V32
++ .channel = DMACH_I2S_IN_1,
++ .dma_addr = S3C2450_PA_IIS_1 + S3C2410_IISFIFORX,
++#elif defined CONFIG_SND_SOC_I2S_V40
++ .channel = DMACH_I2S_IN,
++ .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFORX,
++#endif
++ .dma_size = 4,
++};
++
++struct s3c24xx_i2s_info {
++ void __iomem *regs;
++ struct clk *iis_clk;
++ int master;
++};
++static struct s3c24xx_i2s_info s3c24xx_i2s;
++
++static void s3c24xx_snd_txctrl(int on)
++{
++ u32 iiscon;
++
++ s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on);
++
++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++
++ if (on) {
++
++ iiscon |= S3C2450_IIS0CON_I2SACTIVE;
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++
++ iiscon &= ~S3C2450_IIS0CON_I2SACTIVE;
++
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ }
++}
++
++static void s3c24xx_snd_rxctrl(int on)
++{
++ u32 iiscon;
++
++ s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on);
++
++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++
++ if (on) {
++ iiscon |= S3C2450_IIS0CON_I2SACTIVE;
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++ iiscon &= ~S3C2450_IIS0CON_I2SACTIVE;
++
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ }
++}
++
++/*
++ * Wait for the LR signal to allow synchronisation to the L/R clock
++ * from the codec. May only be needed for slave mode.
++ */
++static int s3c24xx_snd_lrsync(void)
++{
++ u32 iiscon;
++ unsigned long timeout = jiffies + msecs_to_jiffies(5);
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ while (1) {
++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++ if (iiscon & S3C2450_IISCON_LRINDEX)
++ break;
++
++ if (timeout < jiffies)
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++/*
++ * Check whether CPU is the master or slave
++ */
++static inline int s3c24xx_snd_is_clkmaster(void)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2450_IIS0MOD_IMS_SLAVE) ? 0:1;
++}
++
++/*
++ * Set S3C24xx I2S DAI format
++ */
++static int s3c_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
++ unsigned int fmt)
++{
++ u32 iismod;
++
++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
++
++ iismod &= ~S3C2450_IIS0MOD_FS_MASK;
++ iismod |= S3C2450_IIS0MOD_384FS;
++
++#if defined CONFIG_SND_SOC_I2S_V40
++ /* 24bit enable */
++// iismod &= ~S3C2450_IIS0MOD_BLC_MASK;
++// iismod |= S3C_IIS0MOD_BLC_24BIT;
++#endif
++
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++
++ return 0;
++
++}
++
++static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++
++ unsigned long iiscon;
++ unsigned long iismod;
++ unsigned long iisfcon;
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ writel((readl(S3C2410_MISCCR) & ~(7<<8))|(1<<8), S3C2410_MISCCR);
++
++ /*Set I2C port to controll WM8753 codec*/
++ s3c2410_gpio_pullup(S3C2410_GPE15, 0);
++ s3c2410_gpio_pullup(S3C2410_GPE14, 0);
++ s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
++ s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
++
++#if defined CONFIG_SND_SOC_I2S_V40
++ /* Configure the I2S pins in correct mode */
++ writel(0x0, S3C2450_GPESEL);
++
++ s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
++ s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
++
++ writel(readl(S3C2410_GPEUP)| 0x3ff, S3C2410_GPEUP);
++
++ writel(readl(S3C2450_GPBSEL)|(0x3<<3), S3C2450_GPBSEL);
++ writel(readl(S3C2410_GPBUP)|(0xF<<18), S3C2410_GPBUP);
++
++#elif defined CONFIG_SND_SOC_I2S_V32
++ /* Configure the I2S pins in correct mode */
++ writel(0x0, S3C2450_GPLSEL);
++
++ s3c2410_gpio_cfgpin(S3C2410_GPL4, S3C2450_GPL4_I2S1_SCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPL5, S3C2450_GPL5_I2S1_CDCLK);
++ s3c2410_gpio_cfgpin(S3C2410_GPL6, S3C2450_GPL6_I2S1_SDI);
++ s3c2410_gpio_cfgpin(S3C2410_GPL7, S3C2450_GPL7_I2S1_SDO);
++ s3c2410_gpio_cfgpin(S3C2443_GPJ13, S3C2450_GPJ13_I2S1_LRCK);
++
++ writel(readl(S3C2410_GPLUP)| (0xf<<4), S3C2410_GPLUP);
++ writel(readl(S3C2443_GPJDN)| (0x3<<26), S3C2443_GPJDN);
++
++#else
++ printk("Error: S3C2450 I2S configration \n",);
++#endif
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
++ } else {
++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
++ }
++
++ /* Working copies of registers */
++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
++ iisfcon = readl(s3c24xx_i2s.regs + S3C2450_IIS0FIC);
++
++ iiscon |= S3C2450_IIS0CON_TXDMACTIVE;
++ iiscon |= S3C2450_IIS0CON_RXDMACTIVE;
++
++ iismod &= ~S3C2450_IIS0MOD_CLK_MASK;
++ iismod |= S3C2450_IIS0MOD_IMS_EXTERNAL_MASTER | S3C2450_IIS0MOD_INTERNAL_CLK;
++ iismod &= ~S3C2450_IIS0MOD_MODE_MASK;
++ iismod |= S3C2450_IIS0MOD_TXRXMODE;
++
++ /* Multi channel enable */
++ iismod &= ~S3C2450_IIS0MOD_DCE_MASK;
++ switch (params_channels(params)) {
++ case 6:
++ printk("s3c i2s: 5.1channel\n");
++ iismod |= S3C2450_IIS0MOD_DCE_SD1;
++ iismod |= S3C2450_IIS0MOD_DCE_SD2;
++ break;
++ case 4:
++ printk("s3c i2s: 4 channel\n");
++ iismod |= S3C2450_IIS0MOD_DCE_SD1;
++ break;
++ case 2:
++ printk("s3c i2s: 2 channel\n");
++ break;
++ default:
++ printk(KERN_ERR "s3c-i2s-v40: %d channels unsupported\n",
++ params_channels(params));
++ return -EINVAL;
++ }
++
++ /* Set the bit rate */
++#if 0
++ iismod &= ~0x6000;
++#endif
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S8:
++ iismod |= S3C2450_IIS0MOD_BLC_08BIT;
++ iismod &= ~S3C2450_IIS0MOD_BFS_MASK;
++ iismod |= S3C2450_IIS0MOD_32FS;
++ iismod &= ~S3C2450_IIS0MOD_FS_MASK;
++ iismod |= S3C2450_IIS0MOD_384FS;
++ break;
++ case SNDRV_PCM_FORMAT_S16_LE:
++ iismod &= ~S3C2450_IIS0MOD_FS_MASK;
++ iismod &= ~S3C2450_IIS0MOD_BFS_MASK;
++ iismod |= S3C2450_IIS0MOD_384FS | S3C2450_IIS0MOD_32FS;
++ iismod &= ~S3C2450_IIS0MOD_BLC_MASK;
++ iismod |= S3C2450_IIS0MOD_16BIT;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ iismod &= ~S3C2450_IIS0MOD_FS_MASK;
++ iismod &= ~S3C2450_IIS0MOD_BFS_MASK;
++ iismod |= S3C2450_IIS0MOD_384FS | S3C2450_IIS0MOD_48FS;
++ iismod &= ~S3C2450_IIS0MOD_BLC_MASK;
++ iismod |= S3C2450_IIS0MOD_24BIT;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++
++ iisfcon |= S3C2450_IIS_TX_FLUSH;
++ iisfcon |= S3C2450_IIS_RX_FLUSH;
++
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++ iismod &= ~S3C2450_IIS0MOD_FM_MASK;
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C2450_IIS0FIC);
++
++ /* Tx, Rx fifo flush bit clear */
++ iisfcon &= ~(S3C2450_IIS_TX_FLUSH | S3C2450_IIS_RX_FLUSH);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C2450_IIS0FIC);
++
++ s3cdbg("s3c iis mode: 0x%08x\n", readl(s3c24xx_i2s.regs + S3C2410_IISMOD));
++ s3cdbg("s3c: params_channels %d\n", params_channels(params));
++ s3cdbg("s3c: params_format %d\n", params_format(params));
++ s3cdbg("s3c: params_subformat %d\n", params_subformat(params));
++ s3cdbg("s3c: params_period_size %d\n", params_period_size(params));
++ s3cdbg("s3c: params_period_bytes %d\n", params_period_bytes(params));
++ s3cdbg("s3c: params_periods %d\n", params_periods(params));
++ s3cdbg("s3c: params_buffer_size %d\n", params_buffer_size(params));
++ s3cdbg("s3c: params_buffer_bytes %d\n", params_buffer_bytes(params));
++ s3cdbg("s3c: params_tick_time %d\n", params_tick_time(params));
++
++ return 0;
++}
++
++static int s3c_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ int ret = 0;
++
++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (!s3c24xx_snd_is_clkmaster()) {
++ ret = s3c24xx_snd_lrsync();
++ if (ret)
++ goto exit_err;
++ }
++
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(1);
++ else
++ s3c24xx_snd_txctrl(1);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(0);
++ else
++ s3c24xx_snd_txctrl(0);
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++exit_err:
++ return ret;
++}
++
++static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream)
++{
++ unsigned long iiscon;
++
++ iiscon=readl(s3c24xx_i2s.regs + S3C2410_IISCON);
++ iiscon &= ~S3C2450_IIS0CON_I2SACTIVE;
++
++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
++}
++
++
++/*
++ * Set S3C24xx Clock source
++ */
++static int s3c_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
++
++ switch (clk_id) {
++ case S3C24XX_CLKSRC_PCLK:
++ break;
++ case S3C24XX_CLKSRC_MPLL:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ return 0;
++}
++
++/*
++ * Set S3C24xx Clock dividers
++ */
++static int s3c_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
++ int div_id, int div)
++{
++ u32 reg;
++
++ s3cdbg("Entered %s : div_id = %d, div = %d\n", __FUNCTION__, div_id, div);
++
++ switch (div_id) {
++ case S3C24XX_DIV_MCLK:
++ //reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_BFS_MASK;
++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2450_IIS0MOD_BFS_MASK;
++ writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ break;
++ case S3C24XX_DIV_BCLK:
++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2450_IIS0MOD_FS_MASK);
++ writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
++ break;
++ case S3C24XX_DIV_PRESCALER:
++ reg = readl(s3c24xx_i2s.regs + S3C2450_IIS0PSR);
++ reg &= ~(S3C2450_IISPSR_PS_MASK|S3C2450_IISPSR_PSRAEN);
++ writel(reg , s3c24xx_i2s.regs + S3C2450_IIS0PSR);
++ reg |= (div|S3C2450_IISPSR_PSRAEN);
++ writel(reg, s3c24xx_i2s.regs + S3C2450_IIS0PSR);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * To avoid duplicating clock code, allow machine driver to
++ * get the clockrate from here.
++ */
++u32 s3c_i2s_get_clockrate(void)
++{
++ return clk_get_rate(s3c24xx_i2s.iis_clk);
++}
++EXPORT_SYMBOL_GPL(s3c_i2s_get_clockrate);
++
++static int s3c_i2s_probe(struct platform_device *pdev)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++#if defined CONFIG_SND_SOC_I2S_V32
++ s3c24xx_i2s.regs = ioremap(S3C2450_PA_IIS_1, 0x100);
++ if (s3c24xx_i2s.regs == NULL)
++ return -ENXIO;
++#elif defined CONFIG_SND_SOC_I2S_V40
++ s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
++ if (s3c24xx_i2s.regs == NULL)
++ return -ENXIO;
++#endif
++
++ s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
++ if (s3c24xx_i2s.iis_clk == NULL) {
++ s3cdbg("failed to get iis_clock\n");
++ return -ENODEV;
++ }
++ clk_enable(s3c24xx_i2s.iis_clk);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_i2s_suspend(struct platform_device *dev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++static int s3c_i2s_resume(struct platform_device *pdev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++#else
++#define s3c_i2s_suspend NULL
++#define s3c_i2s_resume NULL
++#endif
++
++
++#define S3C24XX_I2S_RATES \
++ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
++
++struct snd_soc_cpu_dai s3c_i2s_dai = {
++ .name = "s3c-i2s",
++ .id = 0,
++ .type = SND_SOC_DAI_I2S,
++ .probe = s3c_i2s_probe,
++ .suspend = s3c_i2s_suspend,
++ .resume = s3c_i2s_resume,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 6,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,},
++
++ .capture = {
++ .channels_min = 2,
++ .channels_max = 6,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,},
++
++ .ops = {
++ .shutdown = s3c64xx_i2s_shutdown,
++ .trigger = s3c_i2s_trigger,
++ .hw_params = s3c_i2s_hw_params,},
++ .dai_ops = {
++ .set_fmt = s3c_i2s_set_fmt,
++ .set_clkdiv = s3c_i2s_set_clkdiv,
++ .set_sysclk = s3c_i2s_set_sysclk,
++ },
++};
++EXPORT_SYMBOL_GPL(s3c_i2s_dai);
++
++/* Module information */
++MODULE_AUTHOR("Ryu, <ryu.real@gmail.com>");
++MODULE_DESCRIPTION("s3c2450 I2S SoC Interface");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c24xx/s3c24xx-ac97.h b/sound/soc/s3c24xx/s3c24xx-ac97.h
+index 2b835e8..daa58eb 100644
+--- a/sound/soc/s3c24xx/s3c24xx-ac97.h
++++ b/sound/soc/s3c24xx/s3c24xx-ac97.h
+@@ -22,4 +22,6 @@
+
+ extern struct snd_soc_cpu_dai s3c2443_ac97_dai[];
+
++extern struct snd_soc_cpu_dai s3c24xx_ac97_dai[];
++
+ #endif /*S3C24XXAC97_H_*/
+diff --git a/sound/soc/s3c24xx/s3c24xx-i2s.c b/sound/soc/s3c24xx/s3c24xx-i2s.c
+index cd89c41..6674db4 100644
+--- a/sound/soc/s3c24xx/s3c24xx-i2s.c
++++ b/sound/soc/s3c24xx/s3c24xx-i2s.c
+@@ -40,7 +40,7 @@
+ #include <asm/dma.h>
+ #include <asm/arch/dma.h>
+
+-#include "s3c24xx-pcm.h"
++#include "s3c-pcm.h"
+ #include "s3c24xx-i2s.h"
+
+ #define S3C24XX_I2S_DEBUG 0
+diff --git a/sound/soc/s3c24xx/smdk2443_wm9710.c b/sound/soc/s3c24xx/smdk2443_wm9710.c
+index d46cd81..17f7026 100644
+--- a/sound/soc/s3c24xx/smdk2443_wm9710.c
++++ b/sound/soc/s3c24xx/smdk2443_wm9710.c
+@@ -24,7 +24,7 @@
+ #include <sound/soc-dapm.h>
+
+ #include "../codecs/ac97.h"
+-#include "s3c24xx-pcm.h"
++#include "s3c-pcm.h"
+ #include "s3c24xx-ac97.h"
+
+ static struct snd_soc_machine smdk2443;
+diff --git a/sound/soc/s3c24xx/smdk2450_wm8580.c b/sound/soc/s3c24xx/smdk2450_wm8580.c
+new file mode 100644
+index 0000000..a39e25b
+--- /dev/null
++++ b/sound/soc/s3c24xx/smdk2450_wm8580.c
+@@ -0,0 +1,395 @@
++/*
++ * smdk2450_wm8580.c -- SoC audio for Neo1973
++ *
++ * Copyright 2007 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 20th Jan 2007 Initial version.
++ * 05th Feb 2007 Rename all to Neo1973
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/timer.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware/scoop.h>
++#include <asm-arm/plat-s3c24xx/regs-iis.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/hardware.h>
++#include <asm/arch/audio.h>
++#include <asm/io.h>
++#include <asm/arch/spi-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#include "../codecs/wm8580.h"
++#include "s3c-pcm.h"
++#include "s3c-i2s.h"
++
++/* define the scenarios */
++#define SMDK_AUDIO_OFF 0
++#define SMDK_CAPTURE_MIC1 3
++#define SMDK_STEREO_TO_HEADPHONES 2
++#define SMDK_CAPTURE_LINE_IN 1
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++static int smdk_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ //struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++ unsigned int pll_out = 0;
++ int ret = 0;
++ unsigned int regs;
++ unsigned int prescaler=0;
++
++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params));
++
++ /* Select Clock source EPLL */
++ regs = readl(S3C2443_CLKSRC);
++ regs &= ~(3<<14);
++ regs |= S3C2443_CLKSRC_I2S_EPLLDIV;
++ regs = (regs & ~(3<<7))|(2<<7);
++ writel(regs, S3C2443_CLKSRC);
++ regs |= (1<<6);
++ writel(regs, S3C2443_CLKSRC);
++
++ regs = readl(S3C2443_SCLKCON);
++ regs |= S3C2443_SCLKCON_I2SCLK;
++ writel(regs, S3C2443_SCLKCON);
++
++ s3cdbg("%s: %d , params = %d \n", __FUNCTION__, __LINE__, params_rate(params));
++
++ switch (params_rate(params)) {
++ case 8000:
++ case 16000:
++ case 32000:
++ case 48000:
++ case 64000:
++ case 96000:
++ writel(9962, S3C2450_EPLLCON_K);
++ writel((49<<16)|(1<<8)|(3<<0) ,S3C2443_EPLLCON);
++ break;
++ case 11025:
++ case 22050:
++ case 44100:
++ case 88200:
++ writel(10381, S3C2450_EPLLCON_K);
++ writel((45<<16)|(1<<8)|(2<<0) ,S3C2443_EPLLCON);
++ break;
++ default:
++ printk("Unsupported rate = %d\n", params_rate(params));
++ break;
++ }
++
++ switch (params_rate(params)) {
++ case 8000:
++ pll_out = 18432000;
++ prescaler = 24;
++ break;
++ case 11025:
++ pll_out = 16934400;
++ prescaler = 32;
++ break;
++ case 16000:
++ pll_out = 18432000;
++ prescaler = 12;
++ break;
++ case 22050:
++ pll_out = 16934400;
++ prescaler = 16;
++ break;
++ case 32000:
++ pll_out = 18432000;
++ prescaler = 6;
++ break;
++ case 44100:
++ pll_out = 16934400;
++ prescaler = 8;
++ break;
++ case 48000:
++ pll_out = 18432000;
++ prescaler = 4;
++ break;
++ case 64000:
++ pll_out = 18432000;
++ prescaler = 3;
++ break;
++ case 88200:
++ pll_out = 16934400;
++ prescaler = 4;
++ break;
++ case 96000:
++ pll_out = 18432000;
++ prescaler = 2;
++ break;
++ }
++
++ /* set cpu DAI configuration */
++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS );
++ if (ret < 0)
++ return ret;
++
++ /* set MCLK division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK,
++ S3C2410_IISMOD_32FS );
++ if (ret < 0)
++ return ret;
++
++ /* set prescaler division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
++ // ((prescaler/2 - 1) << 0x8));
++ ((prescaler - 1) << 0x8));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++
++}
++
++static int smdk_hifi_hw_free(struct snd_pcm_substream *substream)
++{
++// struct snd_soc_pcm_runtime *rtd = substream->private_data;
++// struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++
++ /* disable the PLL */
++ //return codec_dai->dai_ops.set_pll(codec_dai, WM8580_PLL1, 0, 0);
++ //return codec_dai->dai_ops.set_pll(codec_dai, 0, 0, 0);
++ return 0;
++}
++
++/*
++ * Neo1973 WM8580 HiFi DAI opserations.
++ */
++static struct snd_soc_ops smdk_hifi_ops = {
++ .hw_params = smdk_hifi_hw_params,
++ .hw_free = smdk_hifi_hw_free,
++};
++
++static int smdk_scenario = 0;
++
++static int smdk_get_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ ucontrol->value.integer.value[0] = smdk_scenario;
++ return 0;
++}
++
++static int set_scenario_endpoints(struct snd_soc_codec *codec, int scenario)
++{
++ switch(smdk_scenario) {
++ case SMDK_AUDIO_OFF:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK_STEREO_TO_HEADPHONES:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK_CAPTURE_MIC1:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK_CAPTURE_LINE_IN:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ default:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ }
++
++ snd_soc_dapm_sync_endpoints(codec);
++
++ return 0;
++}
++
++static int smdk_set_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++
++ if (smdk_scenario == ucontrol->value.integer.value[0])
++ return 0;
++
++ smdk_scenario = ucontrol->value.integer.value[0];
++ set_scenario_endpoints(codec, smdk_scenario);
++ return 1;
++}
++
++static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headphone Jack", NULL),
++ SND_SOC_DAPM_MIC("Mic1 Jack", NULL),
++ SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++
++/* example machine audio_mapnections */
++static const char* audio_map[][3] = {
++
++ {"Headphone Jack", NULL, "LOUT1"},
++ {"Headphone Jack", NULL, "ROUT1"},
++
++ /* mic is connected to mic1 - with bias */
++ /* mic is connected to mic1 - with bias */
++ {"MIC1", NULL, "Mic1 Jack"},
++
++ {"LINE1", NULL, "Line In Jack"},
++ {"LINE2", NULL, "Line In Jack"},
++
++ /* Connect the ALC pins */
++ {"ACIN", NULL, "ACOP"},
++
++ {NULL, NULL, NULL},
++};
++
++static const char *smdk_scenarios[] = {
++ "Off",
++ "Capture Line In",
++ "Headphones",
++ "Capture Mic1",
++};
++
++static const struct soc_enum smdk_scenario_enum[] = {
++ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(smdk_scenarios),smdk_scenarios),
++};
++
++static const struct snd_kcontrol_new wm8580_smdk_controls[] = {
++ SOC_ENUM_EXT("SMDK Mode", smdk_scenario_enum[0],
++ smdk_get_scenario, smdk_set_scenario),
++};
++
++/*
++ * This is an example machine initialisation for a wm8580 connected to a
++ * smdk2450. It is missing logic to detect hp/mic insertions and logic
++ * to re-route the audio in such an event.
++ */
++static int smdk_wm8580_init(struct snd_soc_codec *codec)
++{
++ int i, err;
++
++ /* set endpoints to default mode */
++ set_scenario_endpoints(codec, SMDK_AUDIO_OFF);
++
++ /* Add smdk2450 specific widgets */
++ for (i = 0; i < ARRAY_SIZE(wm8580_dapm_widgets); i++)
++ snd_soc_dapm_new_control(codec, &wm8580_dapm_widgets[i]);
++
++ /* add smdk2450 specific controls */
++ for (i = 0; i < ARRAY_SIZE(wm8580_smdk_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm8580_smdk_controls[i],
++ codec, NULL));
++ if (err < 0)
++ return err;
++ }
++
++ /* set up smdk2450 specific audio path audio_mapnects */
++ for (i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ /* always connected */
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++
++ snd_soc_dapm_sync_endpoints(codec);
++ return 0;
++}
++
++static struct snd_soc_dai_link smdk_dai[] = {
++{ /* Hifi Playback - for similatious use with voice below */
++ .name = "WM8580",
++ .stream_name = "WM8580 HiFi",
++ .cpu_dai = &s3c_i2s_dai,
++ .codec_dai = &wm8580_dai[0],
++ .init = smdk_wm8580_init,
++ .ops = &smdk_hifi_ops,
++},
++};
++
++static struct snd_soc_machine smdk2450 = {
++ .name = "smdk2450",
++ .dai_link = smdk_dai,
++ .num_links = ARRAY_SIZE(smdk_dai),
++};
++
++static struct wm8580_setup_data smdk_wm8580_setup = {
++ /* wm8580 i2c address 0x36 for write*/
++ .i2c_address = 0x1b,
++};
++
++static struct snd_soc_device smdk_snd_devdata = {
++ .machine = &smdk2450,
++ .platform = &s3c24xx_soc_platform,
++ .codec_dev = &soc_codec_dev_wm8580,
++ .codec_data = &smdk_wm8580_setup,
++};
++
++static struct platform_device *smdk_snd_device;
++
++static int __init s3c_init(void)
++{
++ int ret;
++
++ smdk_snd_device = platform_device_alloc("soc-audio", -1);
++ if (!smdk_snd_device)
++ return -ENOMEM;
++
++ platform_set_drvdata(smdk_snd_device, &smdk_snd_devdata);
++ smdk_snd_devdata.dev = &smdk_snd_device->dev;
++ ret = platform_device_add(smdk_snd_device);
++
++ if (ret)
++ platform_device_put(smdk_snd_device);
++
++ return ret;
++}
++
++static void __exit s3c_exit(void)
++{
++ platform_device_unregister(smdk_snd_device);
++}
++
++module_init(s3c_init);
++module_exit(s3c_exit);
++
++/* Module information */
++MODULE_AUTHOR("Ryu Euiyoul");
++MODULE_DESCRIPTION("ALSA SoC WM8580 SMDK");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c24xx/smdk2450_wm9713.c b/sound/soc/s3c24xx/smdk2450_wm9713.c
+new file mode 100644
+index 0000000..1377764
+--- /dev/null
++++ b/sound/soc/s3c24xx/smdk2450_wm9713.c
+@@ -0,0 +1,88 @@
++/*
++ * smdk2450_wm9713.c -- SoC audio for smdk2450
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * Copyright 2007 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 8th Mar 2007 Initial version.
++ * 20th Sep 2007 Apply at smdk2450
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include "../codecs/wm9713.h"
++#include "s3c-pcm.h"
++#include "s3c24xx-ac97.h"
++
++static struct snd_soc_machine smdk2450;
++
++static struct snd_soc_dai_link smdk2450_dai[] = {
++{
++ .name = "AC97",
++ .stream_name = "AC97 HiFi",
++ .cpu_dai = &s3c24xx_ac97_dai[0],
++ .codec_dai = &wm9713_dai[WM9713_DAI_AC97_HIFI],
++},
++};
++
++static struct snd_soc_machine smdk2450 = {
++ .name = "SMDK2450",
++ .dai_link = smdk2450_dai,
++ .num_links = ARRAY_SIZE(smdk2450_dai),
++};
++
++static struct snd_soc_device smdk2450_snd_ac97_devdata = {
++ .machine = &smdk2450,
++ .platform = &s3c24xx_soc_platform,
++ .codec_dev = &soc_codec_dev_wm9713,
++};
++
++static struct platform_device *smdk2450_snd_ac97_device;
++
++static int __init smdk2450_init(void)
++{
++ int ret;
++
++ smdk2450_snd_ac97_device = platform_device_alloc("soc-audio", -1);
++ if (!smdk2450_snd_ac97_device)
++ return -ENOMEM;
++
++ platform_set_drvdata(smdk2450_snd_ac97_device,
++ &smdk2450_snd_ac97_devdata);
++ smdk2450_snd_ac97_devdata.dev = &smdk2450_snd_ac97_device->dev;
++ ret = platform_device_add(smdk2450_snd_ac97_device);
++
++ if (ret)
++ platform_device_put(smdk2450_snd_ac97_device);
++
++ return ret;
++}
++
++static void __exit smdk2450_exit(void)
++{
++ platform_device_unregister(smdk2450_snd_ac97_device);
++}
++
++module_init(smdk2450_init);
++module_exit(smdk2450_exit);
++
++/* Module information */
++MODULE_AUTHOR("Ryu Euiyoul");
++MODULE_DESCRIPTION("ALSA SoC WM9713 SMDK2450");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c64xx/Kconfig b/sound/soc/s3c64xx/Kconfig
+new file mode 100644
+index 0000000..705c677
+--- /dev/null
++++ b/sound/soc/s3c64xx/Kconfig
+@@ -0,0 +1,110 @@
++menu "SoC Audio for the Samsung S3C"
++ depends on PLAT_S3C64XX && ARCH_S3C2410 && SND_SOC
++
++config SND_S3C_SOC
++ tristate "SoC Audio for the Samsung S3C chips"
++ depends on ARCH_S3C2410 && SND_SOC
++ select SND_PCM
++ help
++ Say Y or M if you want to add support for codecs attached to
++ the S3C AC97, I2S or SSP interface. You will also need
++ to select the audio interfaces to support below.
++
++
++config SND_S3C_SOC_I2S
++ tristate
++
++config SND_S3C6410_SOC_I2S_V32
++ tristate
++
++config SND_S3C6410_SOC_I2S
++ tristate
++
++config SND_SOC_I2S_V40
++ tristate
++
++config SND_S3C64XX_SOC_SMDK6410_WM9713
++ tristate "SoC AC97 Audio support for SMDK6410 - WM9713"
++ depends on SND_S3C_SOC && (MACH_SMDK6410)
++ select SND_S3C6410_SOC_AC97
++ select SND_SOC_WM9713
++ help
++ Say Y if you want to add support for SoC audio on smdk6410
++ with the WM9713.
++
++choice
++ prompt "SMDK Record Path Select"
++ depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713
++
++config SOUND_WM9713_INPUT_STREAM_LINE
++ bool "Input Stream is LINE-IN"
++ depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713
++ help
++ Say Y here to make input stream as LINE-IN.
++
++config SOUND_WM9713_INPUT_STREAM_MIC
++ bool "Input Stream is MIC"
++ depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713
++ help
++ Say Y here to make input stream as MIC.
++endchoice
++
++config SND_S3C6410_SOC_AC97
++ tristate
++ select AC97_BUS
++ select SND_AC97_CODEC
++ select SND_SOC_AC97_BUS
++
++config SND_S3C6410_SOC_SMDK6410_WM8580
++ tristate "SoC I2S Audio support for SMDK6410 - WM8580"
++ depends on SND_S3C_SOC && (MACH_SMDK6410 || MACH_SMDK6430)
++ select SND_S3C6410_SOC_I2S
++ select SND_SOC_WM8580
++ help
++ Say Y if you want to add support for SoC audio on smdk6410
++ with the WM8580.
++
++choice
++ prompt "SMDK Record Path Select"
++ depends on SND_S3C6410_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580
++
++config SOUND_WM8580_INPUT_STREAM_LINE
++ bool "Input Stream is LINE-IN"
++ depends on SND_S3C6410_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580
++ help
++ Say Y here to make input stream as LINE-IN.
++
++config SOUND_WM8580_INPUT_STREAM_MIC
++ bool "Input Stream is MIC"
++ depends on SND_S3C6410_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580
++ help
++ Say Y here to make input stream as MIC.
++endchoice
++
++config SND_S3C64XX_SOC_SMDK6410_WM8990
++ tristate "SoC I2S Audio support for SMDK6410 - WM8990"
++ depends on SND_S3C_SOC && (MACH_SMDK6410)
++ select SND_S3C6410_SOC_I2S_V32
++ select SND_SOC_WM8990
++ help
++ Say Y if you want to add support for SoC audio on smdk6410
++ with the WM8990.
++
++choice
++ prompt "SMDK Record Path Select"
++ depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990
++
++config SOUND_WM8990_INPUT_STREAM_LINE_IN
++ bool "Input Stream is LINE-IN"
++ depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990
++ help
++ Say Y here to make input stream as LINE-IN.
++
++config SOUND_WM8990_INPUT_STREAM_MIC_IN
++ bool "Input Stream is MIC"
++ depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990
++ help
++ Say Y here to make input stream as MIC.
++endchoice
++
++endmenu
+diff --git a/sound/soc/s3c64xx/Makefile b/sound/soc/s3c64xx/Makefile
+new file mode 100644
+index 0000000..2865391
+--- /dev/null
++++ b/sound/soc/s3c64xx/Makefile
+@@ -0,0 +1,18 @@
++# S3c24XX Platform Support
++snd-soc-s3c64xx-ac97-objs := s3c64xx-ac97.o
++snd-soc-s3c6410-i2s-objs := s3c6410-i2s-v40.o
++snd-soc-s3c6410-i2s-v32-objs := s3c6410-i2s-v32.o
++
++obj-$(CONFIG_SND_S3C6410_SOC_AC97) += snd-soc-s3c64xx-ac97.o
++obj-$(CONFIG_SND_S3C6410_SOC_I2S) += snd-soc-s3c6410-i2s.o
++obj-$(CONFIG_SND_S3C6410_SOC_I2S_V32) += snd-soc-s3c6410-i2s-v32.o
++
++# S3C24XX Machine Support
++snd-soc-neo1973-wm8753-objs := neo1973_wm8753.o
++snd-soc-smdk64xx-wm9713-objs := smdk64xx_wm9713.o
++snd-soc-smdk6410-wm8580-objs := smdk6410_wm8580.o
++snd-soc-smdk6410-wm8990-objs := smdk6410_wm8990.o
++
++obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713) += snd-soc-smdk64xx-wm9713.o
++obj-$(CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580) += snd-soc-smdk6410-wm8580.o
++obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) += snd-soc-smdk6410-wm8990.o
+diff --git a/sound/soc/s3c64xx/s3c6410-i2s-v32.c b/sound/soc/s3c64xx/s3c6410-i2s-v32.c
+new file mode 100644
+index 0000000..6c7446e
+--- /dev/null
++++ b/sound/soc/s3c64xx/s3c6410-i2s-v32.c
+@@ -0,0 +1,528 @@
++/*
++ * s3c-i2s.c -- ALSA Soc Audio Layer
++ *
++ * (c) 2006 Wolfson Microelectronics PLC.
++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * (c) 2004-2005 Simtec Electronics
++ * http://armlinux.simtec.co.uk/
++ * Ben Dooks <ben@simtec.co.uk>
++ * Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ *
++ * Revision history
++ * 11th Dec 2006 Merged with Simtec driver
++ * 10th Nov 2006 Initial version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm-arm/plat-s3c64xx/regs-iis.h>
++//#include <asm/arch/regs-iis.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/audio.h>
++#include <asm/arch/dma.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#include "../s3c24xx/s3c-pcm.h"
++#include "../s3c24xx/s3c-i2s.h"
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++/* used to disable sysclk if external crystal is used */
++static int extclk = 0;
++module_param(extclk, int, 0);
++MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk");
++
++static struct s3c2410_dma_client s3c24xx_dma_client_out = {
++ .name = "I2S PCM Stereo out"
++};
++
++static struct s3c2410_dma_client s3c24xx_dma_client_in = {
++ .name = "I2S PCM Stereo in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
++ .client = &s3c24xx_dma_client_out,
++ .channel = DMACH_I2S_OUT,
++ .dma_addr = S3C6400_PA_IIS + S3C64XX_IISFIFO,
++ .dma_size = 4,
++};
++
++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
++ .client = &s3c24xx_dma_client_in,
++ .channel = DMACH_I2S_IN,
++ .dma_addr = S3C6400_PA_IIS + S3C64XX_IISFIFORX,
++ .dma_size = 4,
++};
++
++struct s3c24xx_i2s_info {
++ void __iomem *regs;
++ struct clk *iis_clk;
++ int master;
++};
++static struct s3c24xx_i2s_info s3c24xx_i2s;
++
++static void s3c24xx_snd_txctrl(int on)
++{
++ u32 iisfcon;
++ u32 iiscon;
++ u32 iismod;
++
++ s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on);
++
++ iiscon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ iismod = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ iisfcon = readl(s3c24xx_i2s.regs + S3C64XX_IISFCON);
++
++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++
++ if (on) {
++ iiscon |= S3C64XX_IIS0CON_I2SACTIVE;
++ writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IISFCON);
++ writel(iiscon, s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++
++ iiscon &=~(S3C64XX_IIS0CON_I2SACTIVE);
++ iismod &= ~S3C64XX_IIS0MOD_TXMODE;
++
++ writel(iiscon, s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IISFCON);
++ writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ }
++
++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++}
++
++static void s3c24xx_snd_rxctrl(int on)
++{
++ u32 iisfcon;
++ u32 iiscon;
++ u32 iismod;
++
++ s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on);
++
++ iisfcon = readl(s3c24xx_i2s.regs + S3C64XX_IISFCON);
++ iiscon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ iismod = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++
++ if (on) {
++
++ iiscon |= S3C64XX_IIS0CON_I2SACTIVE;
++
++ writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IISFCON);
++ writel(iiscon, s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iisfcon &= ~S3C2410_IISFCON_RXENABLE;
++ iisfcon &= ~S3C2410_IISFCON_RXDMA;
++ iiscon |= S3C2410_IISCON_RXIDLE;
++ iiscon &= ~S3C2410_IISCON_RXDMAEN;
++ iismod &= ~S3C2410_IISMOD_RXMODE;
++#else
++ iiscon &=~ S3C64XX_IIS0CON_I2SACTIVE;
++ iismod &= ~S3C64XX_IIS0MOD_RXMODE;
++#endif
++ writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IISFCON);
++ writel(iiscon, s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ }
++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++}
++
++/*
++ * Wait for the LR signal to allow synchronisation to the L/R clock
++ * from the codec. May only be needed for slave mode.
++ */
++static int s3c24xx_snd_lrsync(void)
++{
++ u32 iiscon;
++ unsigned long timeout = jiffies + msecs_to_jiffies(5);
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ while (1) {
++ iiscon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ if (iiscon & S3C64XX_IISCON_LRINDEX)
++ break;
++
++ if (timeout < jiffies)
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++/*
++ * Check whether CPU is the master or slave
++ */
++static inline int s3c24xx_snd_is_clkmaster(void)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ return (readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD) & S3C64XX_IISMOD_SLAVE) ? 0:1;
++}
++
++/*
++ * Set S3C24xx I2S DAI format
++ */
++static int s3c_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
++ unsigned int fmt)
++{
++#if 0
++ u32 iismod;
++
++ s3cdbg("Entered %s: fmt = %d\n", __FUNCTION__, fmt);
++
++ iismod = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBM_CFM:
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iismod |= S3C64XX_IISMOD_SLAVE;
++#else
++ iismod |= S3C2410_IISMOD_MASTER;
++#endif
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_LEFT_J:
++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
++ iismod |= S3C2410_IISMOD_MSB;
++#else
++ iismod |= S3C_IIS0MOD_MSB;
++#endif
++ break;
++ case SND_SOC_DAIFMT_I2S:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++#endif
++ return 0;
++
++}
++
++static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++
++ unsigned long iiscon;
++ unsigned long iismod;
++ unsigned long iisfcon;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ /*Set I2C port to controll WM8753 codec*/
++ s3c_gpio_pullup(S3C_GPB5, 0);
++ s3c_gpio_pullup(S3C_GPB6, 0);
++ s3c_gpio_cfgpin(S3C_GPB5, S3C_GPB5_I2C_SCL);
++ s3c_gpio_cfgpin(S3C_GPB6, S3C_GPB6_I2C_SDA);
++
++ s3c24xx_i2s.master = 1;
++
++ /* Configure the I2S pins in correct mode */
++ s3c_gpio_cfgpin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0);
++
++ if (s3c24xx_i2s.master && !extclk){
++ s3cdbg("Setting Clock Output as we are Master\n");
++ s3c_gpio_cfgpin(S3C_GPD0,S3C_GPD0_I2S_CLK0);
++
++ }
++ s3c_gpio_cfgpin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0);
++ s3c_gpio_cfgpin(S3C_GPD3,S3C_GPD3_I2S_DI0);
++ s3c_gpio_cfgpin(S3C_GPD4,S3C_GPD4_I2S_DO0);
++
++ /* pull-up-enable, pull-down-disable*/
++ s3c_gpio_pullup(S3C_GPD0, 0x2);
++ s3c_gpio_pullup(S3C_GPD1, 0x2);
++ s3c_gpio_pullup(S3C_GPD2, 0x2);
++ s3c_gpio_pullup(S3C_GPD3, 0x2);
++ s3c_gpio_pullup(S3C_GPD4, 0x2);
++
++ s3cdbg("substream->stream : %d\n", substream->stream);
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
++ } else {
++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
++ }
++
++ /* Working copies of registers */
++ iiscon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ iismod = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ iisfcon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
++ /* is port used by another stream */
++ if (!(iiscon & S3C64XX_IIS0CON_I2SACTIVE)) {
++
++ // Clear BFS field [2:1]
++ iismod &= ~(0x3<<1);
++ iismod |= S3C64XX_IIS0MOD_32FS | S3C64XX_IIS0MOD_INTERNAL_CLK;
++
++ if (!s3c24xx_i2s.master)
++ iismod |= S3C64XX_IIS0MOD_IMS_SLAVE;
++ else
++ iismod |= S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER;
++ }
++
++ /* enable TX & RX all to support Full-duplex */
++ iismod |= S3C64XX_IIS0MOD_TXRXMODE;
++ iiscon |= S3C64XX_IIS0CON_TXDMACTIVE;
++ iisfcon |= S3C64XX_IIS_TX_FLUSH;
++ iiscon |= S3C64XX_IIS0CON_RXDMACTIVE;
++ iisfcon |= S3C64XX_IIS_RX_FLUSH;
++
++ writel(iiscon, s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
++
++ // Tx, Rx fifo flush bit clear
++ iisfcon &= ~(S3C64XX_IIS_TX_FLUSH | S3C64XX_IIS_RX_FLUSH);
++ writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
++
++ s3cdbg("IISCON: %lx IISMOD: %lx", iiscon, iismod);
++
++ return 0;
++
++}
++
++static int s3c_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ int ret = 0;
++
++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (!s3c24xx_snd_is_clkmaster()) {
++ ret = s3c24xx_snd_lrsync();
++ if (ret)
++ goto exit_err;
++ }
++
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(1);
++ else
++ s3c24xx_snd_txctrl(1);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(0);
++ else
++ s3c24xx_snd_txctrl(0);
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++exit_err:
++ return ret;
++}
++
++static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream)
++{
++ unsigned long iismod, iiscon;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ iismod=readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ iismod &= ~S3C64XX_IIS0MOD_TXMODE;
++ } else {
++ iismod &= ~S3C64XX_IIS0MOD_RXMODE;
++ }
++
++ writel(iismod,s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ iiscon=readl(s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++ iiscon &= !S3C64XX_IIS0CON_I2SACTIVE;
++ writel(iiscon,s3c24xx_i2s.regs + S3C64XX_IIS0CON);
++
++ /* Clock disable
++ * PCLK & SCLK gating disable
++ */
++ __raw_writel(__raw_readl(S3C_PCLK_GATE)&~(S3C_CLKCON_PCLK_IIS0), S3C_PCLK_GATE);
++ __raw_writel(__raw_readl(S3C_SCLK_GATE)&~(S3C_CLKCON_SCLK_AUDIO0), S3C_SCLK_GATE);
++
++ /* EPLL disable */
++ __raw_writel(__raw_readl(S3C_EPLL_CON0)&~(1<<31) ,S3C_EPLL_CON0);
++
++}
++
++
++/*
++ * Set S3C24xx Clock source
++ */
++static int s3c_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ u32 iismod = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ s3cdbg("Entered %s : clk_id = %d\n", __FUNCTION__, clk_id);
++
++ iismod &= ~S3C64XX_IISMOD_MPLL;
++
++ switch (clk_id) {
++ case S3C24XX_CLKSRC_PCLK:
++ break;
++ case S3C24XX_CLKSRC_MPLL:
++ iismod |= S3C64XX_IISMOD_MPLL;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ return 0;
++}
++
++/*
++ * Set S3C24xx Clock dividers
++ */
++static int s3c_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
++ int div_id, int div)
++{
++ u32 reg;
++
++ s3cdbg("Entered %s : div_id = %d, div = %d\n", __FUNCTION__, div_id, div);
++
++ switch (div_id) {
++ case S3C24XX_DIV_MCLK:
++ break;
++ case S3C24XX_DIV_BCLK:
++ reg = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD) & ~(S3C64XX_IISMOD_384FS);
++ writel(reg | div, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
++ break;
++ case S3C24XX_DIV_PRESCALER:
++ writel(div|(1<<15),s3c24xx_i2s.regs + S3C64XX_IIS0PSR);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int s3c_i2s_probe(struct platform_device *pdev)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ s3c24xx_i2s.regs = ioremap(S3C24XX_PA_IIS, 0x100);
++ if (s3c24xx_i2s.regs == NULL)
++ return -ENXIO;
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_i2s_suspend(struct platform_device *dev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++static int s3c_i2s_resume(struct platform_device *pdev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++#else
++#define s3c_i2s_suspend NULL
++#define s3c_i2s_resume NULL
++#endif
++
++
++#define S3C24XX_I2S_RATES \
++ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
++
++struct snd_soc_cpu_dai s3c_i2s_dai = {
++ .name = "s3c-i2s",
++ .id = 0,
++ .type = SND_SOC_DAI_I2S,
++ .probe = s3c_i2s_probe,
++ .suspend = s3c_i2s_suspend,
++ .resume = s3c_i2s_resume,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
++ .capture = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .shutdown = s3c64xx_i2s_shutdown,
++ .trigger = s3c_i2s_trigger,
++ .hw_params = s3c_i2s_hw_params,},
++ .dai_ops = {
++ .set_fmt = s3c_i2s_set_fmt,
++ .set_clkdiv = s3c_i2s_set_clkdiv,
++ .set_sysclk = s3c_i2s_set_sysclk,
++ },
++};
++EXPORT_SYMBOL_GPL(s3c_i2s_dai);
++
++/* Module information */
++MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
++MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c64xx/s3c6410-i2s-v40.c b/sound/soc/s3c64xx/s3c6410-i2s-v40.c
+new file mode 100644
+index 0000000..8a32afe
+--- /dev/null
++++ b/sound/soc/s3c64xx/s3c6410-i2s-v40.c
+@@ -0,0 +1,604 @@
++/*
++ * s3c-i2s.c -- ALSA Soc Audio Layer
++ *
++ * (c) 2006 Wolfson Microelectronics PLC.
++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * (c) 2004-2005 Simtec Electronics
++ * http://armlinux.simtec.co.uk/
++ * Ben Dooks <ben@simtec.co.uk>
++ * Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ *
++ * Revision history
++ * 11th Dec 2006 Merged with Simtec driver
++ * 10th Nov 2006 Initial version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm-arm/plat-s3c64xx/regs-iis.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/audio.h>
++#include <asm/arch/dma.h>
++
++#include <asm/arch/regs-s3c-clock.h>
++
++#include "../s3c24xx/s3c-pcm.h"
++#include "../s3c24xx/s3c-i2s.h"
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++/* used to disable sysclk if external crystal is used */
++static int extclk = 0;
++module_param(extclk, int, 0);
++MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk");
++
++static struct s3c2410_dma_client s3c24xx_dma_client_out = {
++ .name = "I2S PCM Stereo out"
++};
++
++static struct s3c2410_dma_client s3c24xx_dma_client_in = {
++ .name = "I2S PCM Stereo in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c64xx_i2s_pcm_stereo_out = {
++ .client = &s3c24xx_dma_client_out,
++ .channel = DMACH_I2S_V40_OUT,
++ .dma_addr = S3C6410_PA_IIS_V40 + S3C64XX_IISFIFO,
++ .dma_size = 4,
++};
++
++static struct s3c24xx_pcm_dma_params s3c64xx_i2s_pcm_stereo_in = {
++ .client = &s3c24xx_dma_client_in,
++ .channel = DMACH_I2S_V40_IN,
++ .dma_addr = S3C6410_PA_IIS_V40 + S3C64XX_IISFIFORX,
++ .dma_size = 4,
++};
++
++struct s3c64xx_i2s_info {
++ void __iomem *regs;
++ struct clk *iis_clk;
++ int master;
++};
++static struct s3c64xx_i2s_info s3c64xx_i2s;
++
++static void s3c24xx_snd_txctrl(int on)
++{
++ u32 iiscon;
++ u32 iismod;
++
++ s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on);
++
++ iiscon = readl(s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ iismod = readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ s3cdbg("r: IISCON: %x IISMOD: %x\n", iiscon, iismod);
++
++ if (on) {
++ iiscon |= S3C64XX_IIS0CON_I2SACTIVE;
++
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++ writel(iiscon, s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++ iiscon &=~(S3C64XX_IIS0CON_I2SACTIVE);
++ iismod &= ~S3C64XX_IIS0MOD_TXMODE;
++
++ writel(iiscon, s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++ }
++
++ s3cdbg("w: IISCON: %x IISMOD: %x\n", iiscon, iismod);
++}
++
++static void s3c24xx_snd_rxctrl(int on)
++{
++ u32 iisfcon;
++ u32 iiscon;
++ u32 iismod;
++
++ s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on);
++
++ iisfcon = readl(s3c64xx_i2s.regs + S3C64XX_IIS0FIC);
++ iiscon = readl(s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ iismod = readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++
++ if (on) {
++ iiscon |= S3C64XX_IIS0CON_I2SACTIVE;
++
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++ writel(iisfcon, s3c64xx_i2s.regs + S3C64XX_IIS0FIC);
++ writel(iiscon, s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ } else {
++ /* note, we have to disable the FIFOs otherwise bad things
++ * seem to happen when the DMA stops. According to the
++ * Samsung supplied kernel, this should allow the DMA
++ * engine and FIFOs to reset. If this isn't allowed, the
++ * DMA engine will simply freeze randomly.
++ */
++
++ iiscon &=~ S3C64XX_IIS0CON_I2SACTIVE;
++ iismod &= ~S3C64XX_IIS0MOD_RXMODE;
++
++ writel(iisfcon, s3c64xx_i2s.regs + S3C64XX_IIS0FIC);
++ writel(iiscon, s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ }
++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
++}
++
++/*
++ * Wait for the LR signal to allow synchronisation to the L/R clock
++ * from the codec. May only be needed for slave mode.
++ */
++static int s3c24xx_snd_lrsync(void)
++{
++ u32 iiscon;
++ unsigned long timeout = jiffies + msecs_to_jiffies(5);
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ while (1) {
++ iiscon = readl(s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ if (iiscon & S3C64XX_IISCON_LRINDEX)
++ break;
++
++ if (timeout < jiffies)
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++/*
++ * Check whether CPU is the master or slave
++ */
++static inline int s3c24xx_snd_is_clkmaster(void)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ return (readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD) & S3C64XX_IISMOD_SLAVE) ? 0:1;
++}
++
++/*
++ * Set S3C24xx I2S DAI format
++ */
++static int s3c_i2s_v40_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
++ unsigned int fmt)
++{
++#if 0
++ u32 iismod;
++
++ s3cdbg("Entered %s: fmt = %d\n", __FUNCTION__, fmt);
++
++ iismod = readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBM_CFM:
++#ifndef CONFIG_CPU_S3C6400
++ iismod |= S3C_IIS0MOD_SLAVE;
++#else
++ iismod |= S3C_IIS0MOD_MASTER;
++#endif
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_LEFT_J:
++#ifndef CONFIG_CPU_S3C6400
++ iismod |= S3C_IIS0MOD_MSB;
++#else
++ iismod |= S3C_IIS0MOD_MSB;
++#endif
++ break;
++ case SND_SOC_DAIFMT_I2S:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++#endif
++ return 0;
++
++}
++
++static int s3c_i2s_v40_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++
++ unsigned long iiscon;
++ unsigned long iismod;
++ unsigned long iisfcon;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ s3c64xx_i2s.master = 1;
++
++ /* Configure the I2S pins in correct mode */
++ s3c_gpio_cfgpin(S3C_GPH8,S3C_GPH8_I2S_V40_LRCLK);
++
++ if (s3c64xx_i2s.master && !extclk){
++ s3cdbg("Setting Clock Output as we are Master\n");
++ s3c_gpio_cfgpin(S3C_GPH6,S3C_GPH6_I2S_V40_BCLK);
++ }
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ rtd->dai->cpu_dai->dma_data = &s3c64xx_i2s_pcm_stereo_out;
++ } else {
++ rtd->dai->cpu_dai->dma_data = &s3c64xx_i2s_pcm_stereo_in;
++ }
++
++ /* Working copies of registers */
++ iiscon = readl(s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ iismod = readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++ iisfcon = readl(s3c64xx_i2s.regs + S3C64XX_IIS0FIC);
++
++ /* is port used by another stream */
++ if (!(iiscon & S3C64XX_IIS0CON_I2SACTIVE)) {
++
++ /* Clear BFS field [2:1] */
++ iismod &= ~(0x3<<1);
++ iismod |= S3C64XX_IIS0MOD_32FS | S3C64XX_IIS0MOD_INTERNAL_CLK;
++
++ if (!s3c64xx_i2s.master)
++ iismod |= S3C64XX_IISMOD_SLAVE;
++ else
++ iismod |= S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER;
++ }
++
++ iiscon |= S3C64XX_IISCON_FTXURINTEN;
++ iiscon |= S3C64XX_IIS0CON_TXDMACTIVE;
++ iiscon |= S3C64XX_IIS0CON_RXDMACTIVE;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ iismod |= S3C64XX_IIS0MOD_TXMODE;
++ iisfcon |= S3C64XX_IIS_TX_FLUSH;
++ } else {
++ iismod |= S3C64XX_IIS0MOD_RXMODE;
++ iisfcon |= S3C64XX_IIS_RX_FLUSH;
++ }
++
++ /* Multi channel enable */
++ iismod &= ~S3C64XX_IIS0MOD_DCE_MASK;
++ switch (params_channels(params)) {
++ case 6:
++ printk("s3c i2s: 5.1channel\n");
++ iismod |= S3C64XX_IIS0MOD_DCE_SD2;
++ iismod |= S3C64XX_IIS0MOD_DCE_SD2;
++ break;
++ case 4:
++ printk("s3c i2s: 4 channel\n");
++ iismod |= S3C64XX_IIS0MOD_DCE_SD2;
++ break;
++ case 2:
++ printk("s3c i2s: 2 channel\n");
++ break;
++ default:
++ printk(KERN_ERR "s3c-i2s-v40: %d channels unsupported\n",
++ params_channels(params));
++ return -EINVAL;
++ }
++
++ /* Set the bit rate */
++ iismod &= ~0x6000;
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ iismod &= ~S3C64XX_IIS0MOD_FS_MASK;
++ iismod |= S3C64XX_IIS0MOD_256FS | S3C64XX_IIS0MOD_32FS;
++ iismod &= ~(0x3<<13);
++ iismod |= S3C64XX_IIS0MOD_16BIT;
++ break;
++ case SNDRV_PCM_FORMAT_S8:
++ iismod |= S3C64XX_IIS0MOD_8BIT;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ iismod &= ~S3C64XX_IIS0MOD_FS_MASK;
++ iismod |= S3C64XX_IIS0MOD_384FS | S3C64XX_IIS0MOD_48FS;
++ iismod &= ~(0x3<<13);
++ iismod |= S3C64XX_IIS0MOD_24BIT;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iisfcon, s3c64xx_i2s.regs + S3C64XX_IIS0FIC);
++ writel(iiscon, s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ // Tx, Rx fifo flush bit clear
++ iisfcon &= ~(S3C64XX_IIS_TX_FLUSH | S3C64XX_IIS_RX_FLUSH);
++ writel(iisfcon, s3c64xx_i2s.regs + S3C64XX_IIS0FIC);
++
++ s3cdbg("s3c iis mode: 0x%08x\n", readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD));
++ s3cdbg("s3c: params_channels %d\n", params_channels(params));
++ s3cdbg("s3c: params_format %d\n", params_format(params));
++ s3cdbg("s3c: params_subformat %d\n", params_subformat(params));
++ s3cdbg("s3c: params_period_size %d\n", params_period_size(params));
++ s3cdbg("s3c: params_period_bytes %d\n", params_period_bytes(params));
++ s3cdbg("s3c: params_periods %d\n", params_periods(params));
++ s3cdbg("s3c: params_buffer_size %d\n", params_buffer_size(params));
++ s3cdbg("s3c: params_buffer_bytes %d\n", params_buffer_bytes(params));
++ s3cdbg("s3c: params_tick_time %d\n", params_tick_time(params));
++ s3cdbg("hw_params: IISCON: %lx IISMOD: %lx\n", iiscon, iismod);
++
++ return 0;
++
++}
++
++static int s3c_i2s_v40_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ int ret = 0;
++
++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (!s3c24xx_snd_is_clkmaster()) {
++ ret = s3c24xx_snd_lrsync();
++ if (ret)
++ goto exit_err;
++ }
++
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(1);
++ else
++ s3c24xx_snd_txctrl(1);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ s3c24xx_snd_rxctrl(0);
++ else
++ s3c24xx_snd_txctrl(0);
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++exit_err:
++ return ret;
++}
++
++static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream)
++{
++ unsigned long iismod, iiscon;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ iismod=readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ iismod &= ~S3C64XX_IIS0MOD_TXMODE;
++ } else {
++ iismod &= ~S3C64XX_IIS0MOD_RXMODE;
++ }
++
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ iiscon=readl(s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ iiscon &= !S3C64XX_IIS0CON_I2SACTIVE;
++ writel(iiscon, s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++
++ /* Clock disable
++ * PCLK & SCLK gating disable
++ */
++ __raw_writel(__raw_readl(S3C_PCLK_GATE)&~(S3C_CLKCON_PCLK_IIS0), S3C_PCLK_GATE);
++ __raw_writel(__raw_readl(S3C_SCLK_GATE)&~(S3C_CLKCON_SCLK_AUDIO0), S3C_SCLK_GATE);
++
++ /* EPLL disable */
++ __raw_writel(__raw_readl(S3C_EPLL_CON0)&~(1<<31) ,S3C_EPLL_CON0);
++
++}
++
++
++/*
++ * Set S3C24xx Clock source
++ */
++static int s3c_i2s_v40_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ u32 iismod = readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++
++ s3cdbg("Entered %s : clk_id = %d\n", __FUNCTION__, clk_id);
++
++ iismod &= ~S3C64XX_IISMOD_MPLL;
++
++ switch (clk_id) {
++ case S3C24XX_CLKSRC_PCLK:
++ break;
++ case S3C24XX_CLKSRC_MPLL:
++ iismod |= S3C64XX_IISMOD_MPLL;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(iismod, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++ return 0;
++}
++
++/*
++ * Set S3C24xx Clock dividers
++ */
++static int s3c_i2s_v40_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
++ int div_id, int div)
++{
++ u32 reg;
++
++ s3cdbg("Entered %s : div_id = %d, div = %x\n", __FUNCTION__, div_id, div);
++
++ switch (div_id) {
++ case S3C24XX_DIV_MCLK:
++ break;
++ case S3C24XX_DIV_BCLK:
++ reg = readl(s3c64xx_i2s.regs + S3C64XX_IIS0MOD) & ~(S3C64XX_IIS0MOD_FS_MASK);
++ writel(reg | div, s3c64xx_i2s.regs + S3C64XX_IIS0MOD);
++ break;
++ case S3C24XX_DIV_PRESCALER:
++ if (div)
++ div |= 1 << 15;
++ writel(div, s3c64xx_i2s.regs + S3C64XX_IIS0PSR);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * To avoid duplicating clock code, allow machine driver to
++ * get the clockrate from here.
++ */
++u32 s3c_i2s_v40_get_clockrate(void)
++{
++ return clk_get_rate(s3c64xx_i2s.iis_clk);
++}
++EXPORT_SYMBOL_GPL(s3c_i2s_v40_get_clockrate);
++
++static irqreturn_t s3c_iis_irq(int irqno, void *dev_id)
++{
++ u32 iiscon;
++
++ iiscon = readl(s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ if((1<<17) & iiscon) {
++ iiscon &= ~(1<<16);
++ iiscon |= (1<<17);
++ writel(iiscon, s3c64xx_i2s.regs + S3C64XX_IIS0CON);
++ printk("underrun interrupt IISCON = 0x%08x\n", readl(s3c64xx_i2s.regs + S3C64XX_IIS0CON));
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int s3c_i2s_v40_probe(struct platform_device *pdev)
++{
++ int ret;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ s3c64xx_i2s.regs = ioremap(S3C6410_PA_IIS_V40, 0x100);
++ if (s3c64xx_i2s.regs == NULL)
++ return -ENXIO;
++
++ s3c64xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
++ if (s3c64xx_i2s.iis_clk == NULL) {
++ printk("failed to get iis_clock\n");
++ iounmap(s3c64xx_i2s.regs);
++ return -ENODEV;
++ }
++ clk_enable(s3c64xx_i2s.iis_clk);
++
++ ret = request_irq(IRQ_IIS, s3c_iis_irq, 0,
++ "s3c-i2s-v40", pdev);
++ if (ret < 0) {
++ printk("fail to claim i2s irq , ret = %d\n", ret);
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int s3c_i2s_v40_suspend(struct platform_device *dev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++static int s3c_i2s_v40_resume(struct platform_device *pdev,
++ struct snd_soc_cpu_dai *dai)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++ return 0;
++}
++
++#else
++#define s3c_i2s_v40_suspend NULL
++#define s3c_i2s_v40_resume NULL
++#endif
++
++
++#define S3C24XX_I2S_RATES \
++ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
++
++struct snd_soc_cpu_dai s3c_i2s_v40_dai = {
++ .name = "s3c-i2s-v40",
++ .id = 0,
++ .type = SND_SOC_DAI_I2S,
++ .probe = s3c_i2s_v40_probe,
++ .suspend = s3c_i2s_v40_suspend,
++ .resume = s3c_i2s_v40_resume,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 6,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,},
++ .capture = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = S3C24XX_I2S_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,},
++ .ops = {
++ .shutdown = s3c64xx_i2s_shutdown,
++ .trigger = s3c_i2s_v40_trigger,
++ .hw_params = s3c_i2s_v40_hw_params,},
++ .dai_ops = {
++ .set_fmt = s3c_i2s_v40_set_fmt,
++ .set_clkdiv = s3c_i2s_v40_set_clkdiv,
++ .set_sysclk = s3c_i2s_v40_set_sysclk,
++ },
++};
++EXPORT_SYMBOL_GPL(s3c_i2s_v40_dai);
++
++/* Module information */
++MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
++MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c64xx/s3c64xx-ac97.c b/sound/soc/s3c64xx/s3c64xx-ac97.c
+new file mode 100644
+index 0000000..c274b1c
+--- /dev/null
++++ b/sound/soc/s3c64xx/s3c64xx-ac97.c
+@@ -0,0 +1,487 @@
++/*
++ * s3c6400-ac97.c -- ALSA Soc Audio Layer
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * (c) 2007 Wolfson Microelectronics PLC.
++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ * All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Revision history
++ * 21st Mar 2007 Initial Version
++ * 20th Sep 2007 Apply at s3c6400
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/wait.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/ac97_codec.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/plat-s3c/regs-ac97.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++#include <asm/arch/audio.h>
++#include <asm/dma.h>
++#include <asm/arch/dma.h>
++
++#include "../s3c24xx/s3c-pcm.h"
++#include "s3c64xx-ac97.h"
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++extern struct clk *clk_get(struct device *dev, const char *id);
++extern int clk_enable(struct clk *clk);
++extern void clk_disable(struct clk *clk);
++
++struct s3c24xx_ac97_info {
++ void __iomem *regs;
++ struct clk *ac97_clk;
++};
++static struct s3c24xx_ac97_info s3c24xx_ac97;
++
++static u32 codec_ready;
++static DEFINE_MUTEX(ac97_mutex);
++static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
++
++static unsigned short s3c6400_ac97_read(struct snd_ac97 *ac97,
++ unsigned short reg)
++{
++ u32 ac_glbctrl;
++ u32 ac_codec_cmd;
++ u32 stat, addr, data;
++
++ s3cdbg("Entered %s: reg=0x%x\n", __FUNCTION__, reg);
++
++ mutex_lock(&ac97_mutex);
++
++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
++ ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++
++ udelay(1000);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
++ addr = (stat >> 16) & 0x7f;
++ data = (stat & 0xffff);
++
++ wait_event_timeout(gsr_wq,addr==reg,1);
++ if(addr!=reg){
++ printk(KERN_ERR"AC97: read error (ac97_reg=%x addr=%x)\n", reg, addr);
++ printk(KERN_ERR"Check audio codec jumpper settings\n\n");
++ goto out;
++ }
++
++out: mutex_unlock(&ac97_mutex);
++ return (unsigned short)data;
++}
++
++static void s3c6400_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
++ unsigned short val)
++{
++ u32 ac_glbctrl;
++ u32 ac_codec_cmd;
++ u32 stat, data;
++
++ s3cdbg("Entered %s: reg=0x%x, val=0x%x\n", __FUNCTION__,reg,val);
++
++ mutex_lock(&ac97_mutex);
++
++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
++ ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++
++ udelay(50);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++
++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
++ data = (stat & 0xffff);
++
++ wait_event_timeout(gsr_wq,data==val,1);
++ if(data!=val){
++ printk("%s: write error (ac97_val=%x data=%x)\n",
++ __FUNCTION__, val, data);
++ }
++
++ mutex_unlock(&ac97_mutex);
++}
++
++static void s3c6400_ac97_warm_reset(struct snd_ac97 *ac97)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_WARMRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_WARMRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
++ S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl |= S3C_AC97_GLBCTRL_ACLINKON;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ udelay(1000);
++}
++
++static void s3c6400_ac97_cold_reset(struct snd_ac97 *ac97)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ msleep(1);
++}
++
++static irqreturn_t s3c6400_ac97_irq(int irq, void *dev_id)
++{
++ int status;
++ u32 ac_glbctrl, ac_glbstat;
++
++ ac_glbstat = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT);
++
++ s3cdbg("Entered %s: AC_GLBSTAT = 0x%x\n", __FUNCTION__, ac_glbstat);
++
++ status = ac_glbstat & codec_ready;
++
++
++ if (status) {
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ wake_up(&gsr_wq);
++ }
++ return IRQ_HANDLED;
++}
++
++struct snd_ac97_bus_ops soc_ac97_ops = {
++ .read = s3c6400_ac97_read,
++ .write = s3c6400_ac97_write,
++ .warm_reset = s3c6400_ac97_warm_reset,
++ .reset = s3c6400_ac97_cold_reset,
++};
++
++static struct s3c2410_dma_client s3c6400_dma_client_out = {
++ .name = "AC97 PCM Stereo out"
++};
++
++static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_out = {
++ .client = &s3c6400_dma_client_out,
++ .channel = DMACH_AC97_PCM_OUT,
++ .dma_addr = S3C6400_PA_AC97 + S3C_AC97_PCM_DATA,
++ .dma_size = 4,
++};
++
++#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
++static struct s3c2410_dma_client s3c6400_dma_client_micin = {
++ .name = "AC97 Mic Mono in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c6400_ac97_mic_mono_in = {
++ .client = &s3c6400_dma_client_micin,
++ .channel = DMACH_AC97_MIC_IN,
++ .dma_addr = S3C6400_PA_AC97 + S3C_AC97_MIC_DATA,
++ .dma_size = 4,
++};
++#else /* Input Stream is LINE-IN */
++static struct s3c2410_dma_client s3c6400_dma_client_in = {
++ .name = "AC97 PCM Stereo Line in"
++};
++
++static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_in = {
++ .client = &s3c6400_dma_client_in,
++ .channel = DMACH_AC97_PCM_IN,
++ .dma_addr = S3C6400_PA_AC97 + S3C_AC97_PCM_DATA,
++ .dma_size = 4,
++};
++#endif
++
++static int s3c6400_ac97_probe(struct platform_device *pdev)
++{
++ int ret;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ s3c24xx_ac97.regs = ioremap(S3C6400_PA_AC97, 0x100);
++ if (s3c24xx_ac97.regs == NULL)
++ return -ENXIO;
++
++ s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
++ if (s3c24xx_ac97.ac97_clk == NULL) {
++ printk(KERN_ERR "s3c6400-ac97 failed to get ac97_clock\n");
++ iounmap(s3c24xx_ac97.regs);
++ return -ENODEV;
++ }
++ clk_enable(s3c24xx_ac97.ac97_clk);
++
++ s3c_gpio_cfgpin(S3C_GPD0,S3C_GPD0_AC97_BITCLK);
++ s3c_gpio_cfgpin(S3C_GPD1,S3C_GPD1_AC97_RESET);
++ s3c_gpio_cfgpin(S3C_GPD2,S3C_GPD2_AC97_SYNC);
++ s3c_gpio_cfgpin(S3C_GPD3,S3C_GPD3_AC97_SDI);
++ s3c_gpio_cfgpin(S3C_GPD4,S3C_GPD4_AC97_SDO);
++
++ s3c_gpio_pullup(S3C_GPD0,0);
++ s3c_gpio_pullup(S3C_GPD1,0);
++ s3c_gpio_pullup(S3C_GPD2,0);
++ s3c_gpio_pullup(S3C_GPD3,0);
++ s3c_gpio_pullup(S3C_GPD4,0);
++
++ ret = request_irq(IRQ_AC97, s3c6400_ac97_irq,
++ IRQF_DISABLED, "AC97", NULL);
++ if (ret < 0) {
++ printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
++ clk_disable(s3c24xx_ac97.ac97_clk);
++ clk_put(s3c24xx_ac97.ac97_clk);
++ iounmap(s3c24xx_ac97.regs);
++ }
++
++ return ret;
++}
++
++static void s3c6400_ac97_remove(struct platform_device *pdev)
++{
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ free_irq(IRQ_AC97, NULL);
++ clk_disable(s3c24xx_ac97.ac97_clk);
++ clk_put(s3c24xx_ac97.ac97_clk);
++ iounmap(s3c24xx_ac97.regs);
++}
++
++static int s3c6400_ac97_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_out;
++ else
++#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
++ cpu_dai->dma_data = &s3c6400_ac97_mic_mono_in;
++#else /* Input Stream is LINE-IN */
++ cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_in;
++#endif
++
++
++ return 0;
++}
++
++static int s3c6400_ac97_hifi_prepare(struct snd_pcm_substream *substream)
++{
++ /*
++ * To support full duplex
++ * Tested by cat /dev/dsp > /dev/dsp
++ */
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ s3c6400_ac97_write(0,0x26,0x0);
++ s3c6400_ac97_write(0, 0x0c, 0x0808);
++ s3c6400_ac97_write(0,0x3c, 0xf803);
++ s3c6400_ac97_write(0,0x3e,0xb990);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ s3c6400_ac97_write(0,0x02, 0x8080);
++ s3c6400_ac97_write(0, 0x04, 0x0606);
++ s3c6400_ac97_write(0,0x1c, 0x00aa);
++ }
++ else
++ {
++ s3c6400_ac97_write(0, 0x12, 0x0f0f);
++#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
++ s3c6400_ac97_write(0,0x5c,0x2);
++ s3c6400_ac97_write(0,0x10,0x68);
++ s3c6400_ac97_write(0,0x14,0xfe00);
++#else /* Input Stream is LINE-IN */
++ s3c6400_ac97_write(0, 0x14, 0xd612);
++#endif
++ }
++
++ return 0;
++}
++
++
++static int s3c6400_ac97_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ switch(cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
++ else
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
++ else
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
++ break;
++ }
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ return 0;
++}
++
++#if 0
++static int s3c6400_ac97_hw_mic_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ return -ENODEV;
++ else
++ cpu_dai->dma_data = &s3c6400_ac97_mic_mono_in;
++
++ return 0;
++}
++
++static int s3c6400_ac97_mic_trigger(struct snd_pcm_substream *substream,
++ int cmd)
++{
++ u32 ac_glbctrl;
++
++ s3cdbg("Entered %s\n", __FUNCTION__);
++
++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++ switch(cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
++ }
++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
++
++ return 0;
++}
++#endif
++
++#define s3c6400_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
++
++struct snd_soc_cpu_dai s3c6400_ac97_dai[] = {
++{
++ .name = "s3c64xx-ac97",
++ .id = 0,
++ .type = SND_SOC_DAI_AC97,
++ .probe = s3c6400_ac97_probe,
++ .remove = s3c6400_ac97_remove,
++ .playback = {
++ .stream_name = "AC97 Playback",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = s3c6400_AC97_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .capture = {
++ .stream_name = "AC97 Capture",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = s3c6400_AC97_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .hw_params = s3c6400_ac97_hw_params,
++ .prepare = s3c6400_ac97_hifi_prepare,
++ .trigger = s3c6400_ac97_trigger},
++},
++#if 0
++{
++ .name = "s3c6400-ac97-mic",
++ .id = 1,
++ .type = SND_SOC_DAI_AC97,
++ .capture = {
++ .stream_name = "AC97 Mic Capture",
++ .channels_min = 1,
++ .channels_max = 1,
++ .rates = s3c6400_AC97_RATES,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
++ .ops = {
++ .hw_params = s3c6400_ac97_hw_mic_params,
++ .trigger = s3c6400_ac97_mic_trigger,},
++},
++#endif
++};
++
++EXPORT_SYMBOL_GPL(s3c6400_ac97_dai);
++EXPORT_SYMBOL_GPL(soc_ac97_ops);
++
++MODULE_AUTHOR("Ryu Euiyoul");
++MODULE_DESCRIPTION("AC97 driver for the Samsung s3c6400 chip");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c64xx/s3c64xx-ac97.h b/sound/soc/s3c64xx/s3c64xx-ac97.h
+new file mode 100644
+index 0000000..9cc4ca9
+--- /dev/null
++++ b/sound/soc/s3c64xx/s3c64xx-ac97.h
+@@ -0,0 +1,25 @@
++/*
++ * s3c24xx-ac97.c -- ALSA Soc Audio Layer
++ *
++ * (c) 2007 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 10th Nov 2006 Initial version.
++ */
++
++#ifndef S3C6400AC97_H_
++#define S3C6400AC97_H_
++
++#define AC_CMD_ADDR(x) (x << 16)
++#define AC_CMD_DATA(x) (x & 0xffff)
++
++extern struct snd_soc_cpu_dai s3c6400_ac97_dai[];
++
++#endif /*S3C6400AC97_H_*/
+diff --git a/sound/soc/s3c64xx/smdk6400_wm8753.c b/sound/soc/s3c64xx/smdk6400_wm8753.c
+new file mode 100644
+index 0000000..da26913
+--- /dev/null
++++ b/sound/soc/s3c64xx/smdk6400_wm8753.c
+@@ -0,0 +1,436 @@
++/*
++ * smdk6400_wm8753.c -- SoC audio for Neo1973
++ *
++ * Copyright 2007 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 20th Jan 2007 Initial version.
++ * 05th Feb 2007 Rename all to Neo1973
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/timer.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware/scoop.h>
++#include <asm/arch/regs-iis.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/hardware.h>
++#include <asm/arch/audio.h>
++#include <asm/io.h>
++#include <asm/arch/spi-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++
++#include "../codecs/wm8753.h"
++#include "s3c-pcm.h"
++#include "s3c-i2s.h"
++
++/* define the scenarios */
++#define SMDK6400_AUDIO_OFF 0
++#define SMDK6400_CAPTURE_MIC1 3
++#define SMDK6400_STEREO_TO_HEADPHONES 2
++#define SMDK6400_CAPTURE_LINE_IN 1
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++static int smdk6400_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++ unsigned int pll_out = 0, bclk = 0;
++ int ret = 0;
++ unsigned int iispsr, iismod;
++ unsigned int prescaler = 4;
++
++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params));
++
++ /*PCLK & SCLK gating enable*/
++ writel(readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_IIS0, S3C_PCLK_GATE);
++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE);
++
++ iismod = readl(S3C_IIS0MOD);
++ iismod &=~(0x3<<3);
++
++ /*Clear I2S prescaler value [13:8] and disable prescaler*/
++ iispsr = readl(S3C_IIS0PSR);
++ iispsr &=~((0x3f<<8)|(1<<15));
++ writel(iispsr, S3C_IIS0PSR);
++
++ s3cdbg("%s: %d , params = %d \n", __FUNCTION__, __LINE__, params_rate(params));
++
++ switch (params_rate(params)) {
++ case 16000:
++ case 32000:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++ break;
++ //case 8000:
++ // prescaler = 0xe;
++ case 48000:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(192<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++ break;
++ case 11025:
++ prescaler = 9;
++ case 8000:
++ case 22050:
++ case 44100:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(254<<16)|(9<<8)|(2<<0) ,S3C_EPLL_CON0);
++ break;
++ default:
++ /* somtimes 32000 rate comes to 96000
++ default values are same as 32000 */
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++
++ /* for 96000 rate : error 0.3%
++ * prescaler = 1;
++ * writel((1<<31)|(154<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++ */
++ break;
++ }
++
++ s3cdbg("%s, IISCON: %x IISMOD: %x,IISFIC: %x,IISPSR: %x",
++ __FUNCTION__ , readl(S3C_IIS0CON), readl(S3C_IIS0MOD),
++ readl(S3C_IIS0FIC), readl(S3C_IIS0PSR));
++
++ while(!(__raw_readl(S3C_EPLL_CON0)&(1<<30)));
++
++ /* MUXepll : FOUTepll */
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++ /* AUDIO0 sel : FOUTepll */
++ writel((readl(S3C_CLK_SRC)&~(0x7<<7))|(0<<7), S3C_CLK_SRC);
++
++ /* CLK_DIV2 setting */
++ writel(0x0,S3C_CLK_DIV2);
++
++ switch (params_rate(params)) {
++// case 8000:
++// iismod |= S3C_IIS0MOD_768FS;
++// pll_out = 12288000;
++// break;
++ case 11025:
++ iismod |= S3C_IIS0MOD_768FS;
++ bclk = WM8753_BCLK_DIV_16;
++ pll_out = 16934400;
++ break;
++ case 16000:
++ iismod |= S3C_IIS0MOD_768FS;
++ bclk = WM8753_BCLK_DIV_2;
++ pll_out = 12288000;
++ break;
++ case 22050:
++ iismod |= S3C_IIS0MOD_768FS;
++ bclk = WM8753_BCLK_DIV_8;
++ pll_out = 16934400;
++ break;
++ case 32000:
++ iismod |= S3C_IIS0MOD_384FS;
++ bclk = WM8753_BCLK_DIV_2;
++ pll_out = 12288000;
++ break;
++ case 44100:
++ case 8000:
++ iismod |= S3C_IIS0MOD_384FS;
++ bclk = WM8753_BCLK_DIV_4;
++ pll_out = 16934400;
++ break;
++ case 48000:
++ iismod |= S3C_IIS0MOD_384FS;
++ bclk = WM8753_BCLK_DIV_4;
++ pll_out = 18432000;
++ break;
++ default:
++ /* somtimes 32000 rate comes to 96000
++ default values are same as 32000 */
++ iismod |= S3C_IIS0MOD_384FS;
++ bclk = WM8753_BCLK_DIV_2;
++ pll_out = 12288000;
++ break;
++ }
++
++ writel(iismod , S3C_IIS0MOD);
++
++ /* set codec DAI configuration */
++ ret = codec_dai->dai_ops.set_fmt(codec_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS );
++ if (ret < 0)
++ return ret;
++
++ /* set cpu DAI configuration */
++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS );
++ if (ret < 0)
++ return ret;
++
++ /* set the codec system clock for DAC and ADC */
++ ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_MCLK, pll_out,
++ SND_SOC_CLOCK_IN);
++ if (ret < 0)
++ return ret;
++
++ /* set MCLK division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK,
++ S3C2410_IISMOD_32FS );
++ if (ret < 0)
++ return ret;
++
++ /* set codec BCLK division for sample rate */
++ ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8753_BCLKDIV, bclk);
++ if (ret < 0)
++ return ret;
++
++ /* set prescaler division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
++ (prescaler << 0x8));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int smdk6400_hifi_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++
++ /* disable the PLL */
++ return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1, 0, 0);
++}
++
++/*
++ * Neo1973 WM8753 HiFi DAI opserations.
++ */
++static struct snd_soc_ops smdk6400_hifi_ops = {
++ .hw_params = smdk6400_hifi_hw_params,
++ .hw_free = smdk6400_hifi_hw_free,
++};
++
++static int smdk6400_scenario = 0;
++
++static int smdk6400_get_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ ucontrol->value.integer.value[0] = smdk6400_scenario;
++ return 0;
++}
++
++static int set_scenario_endpoints(struct snd_soc_codec *codec, int scenario)
++{
++ switch(smdk6400_scenario) {
++ case SMDK6400_AUDIO_OFF:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6400_STEREO_TO_HEADPHONES:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6400_CAPTURE_MIC1:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6400_CAPTURE_LINE_IN:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ default:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ }
++
++ snd_soc_dapm_sync_endpoints(codec);
++
++ return 0;
++}
++
++static int smdk6400_set_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++
++ if (smdk6400_scenario == ucontrol->value.integer.value[0])
++ return 0;
++
++ smdk6400_scenario = ucontrol->value.integer.value[0];
++ set_scenario_endpoints(codec, smdk6400_scenario);
++ return 1;
++}
++
++static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headphone Jack", NULL),
++ SND_SOC_DAPM_MIC("Mic1 Jack", NULL),
++ SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++
++/* example machine audio_mapnections */
++static const char* audio_map[][3] = {
++
++ {"Headphone Jack", NULL, "LOUT1"},
++ {"Headphone Jack", NULL, "ROUT1"},
++
++ /* mic is connected to mic1 - with bias */
++ /* mic is connected to mic1 - with bias */
++ {"MIC1", NULL, "Mic1 Jack"},
++
++ {"LINE1", NULL, "Line In Jack"},
++ {"LINE2", NULL, "Line In Jack"},
++
++ /* Connect the ALC pins */
++ {"ACIN", NULL, "ACOP"},
++
++ {NULL, NULL, NULL},
++};
++
++static const char *smdk_scenarios[] = {
++ "Off",
++ "Capture Line In",
++ "Headphones",
++ "Capture Mic1",
++};
++
++static const struct soc_enum smdk_scenario_enum[] = {
++ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(smdk_scenarios),smdk_scenarios),
++};
++
++static const struct snd_kcontrol_new wm8753_smdk6400_controls[] = {
++ SOC_ENUM_EXT("SMDK Mode", smdk_scenario_enum[0],
++ smdk6400_get_scenario, smdk6400_set_scenario),
++};
++
++/*
++ * This is an example machine initialisation for a wm8753 connected to a
++ * smdk6400. It is missing logic to detect hp/mic insertions and logic
++ * to re-route the audio in such an event.
++ */
++static int smdk6400_wm8753_init(struct snd_soc_codec *codec)
++{
++ int i, err;
++
++ /* set endpoints to default mode */
++ set_scenario_endpoints(codec, SMDK6400_AUDIO_OFF);
++
++ /* Add smdk6400 specific widgets */
++ for (i = 0; i < ARRAY_SIZE(wm8753_dapm_widgets); i++)
++ snd_soc_dapm_new_control(codec, &wm8753_dapm_widgets[i]);
++
++ /* add smdk6400 specific controls */
++ for (i = 0; i < ARRAY_SIZE(wm8753_smdk6400_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm8753_smdk6400_controls[i],
++ codec, NULL));
++ if (err < 0)
++ return err;
++ }
++
++ /* set up smdk6400 specific audio path audio_mapnects */
++ for (i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ /* always connected */
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++
++ snd_soc_dapm_sync_endpoints(codec);
++ return 0;
++}
++
++static struct snd_soc_dai_link smdk6400_dai[] = {
++{ /* Hifi Playback - for similatious use with voice below */
++ .name = "WM8753",
++ .stream_name = "WM8753 HiFi",
++ .cpu_dai = &s3c_i2s_dai,
++ .codec_dai = &wm8753_dai[WM8753_DAI_HIFI],
++ .init = smdk6400_wm8753_init,
++ .ops = &smdk6400_hifi_ops,
++},
++};
++
++static struct snd_soc_machine smdk6400 = {
++ .name = "smdk6400",
++ .dai_link = smdk6400_dai,
++ .num_links = ARRAY_SIZE(smdk6400_dai),
++};
++
++static struct wm8753_setup_data smdk6400_wm8753_setup = {
++ .i2c_address = 0x1a,
++};
++
++static struct snd_soc_device smdk6400_snd_devdata = {
++ .machine = &smdk6400,
++ .platform = &s3c24xx_soc_platform,
++ .codec_dev = &soc_codec_dev_wm8753,
++ .codec_data = &smdk6400_wm8753_setup,
++};
++
++static struct platform_device *smdk6400_snd_device;
++
++static int __init smdk6400_init(void)
++{
++ int ret;
++
++ smdk6400_snd_device = platform_device_alloc("soc-audio", -1);
++ if (!smdk6400_snd_device)
++ return -ENOMEM;
++
++ platform_set_drvdata(smdk6400_snd_device, &smdk6400_snd_devdata);
++ smdk6400_snd_devdata.dev = &smdk6400_snd_device->dev;
++ ret = platform_device_add(smdk6400_snd_device);
++
++ if (ret)
++ platform_device_put(smdk6400_snd_device);
++
++ return ret;
++}
++
++static void __exit smdk6400_exit(void)
++{
++ platform_device_unregister(smdk6400_snd_device);
++}
++
++module_init(smdk6400_init);
++module_exit(smdk6400_exit);
++
++/* Module information */
++MODULE_AUTHOR("Ryu Euiyoul");
++MODULE_DESCRIPTION("ALSA SoC WM8753 Neo1973");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c64xx/smdk6410_wm8580.c b/sound/soc/s3c64xx/smdk6410_wm8580.c
+new file mode 100644
+index 0000000..9b78cfe
+--- /dev/null
++++ b/sound/soc/s3c64xx/smdk6410_wm8580.c
+@@ -0,0 +1,365 @@
++/*
++ * smdk6400_wm8580.c
++ *
++ * Copyright 2007, 2008 Wolfson Microelectronics PLC.
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/timer.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <asm-arm/plat-s3c64xx/regs-iis.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/hardware.h>
++#include <asm/arch/audio.h>
++#include <asm/io.h>
++#include <asm/arch/spi-gpio.h>
++#include <asm-arm/arch-s3c2410/regs-s3c-clock.h>
++
++#include "../codecs/wm8580.h"
++#include "../s3c24xx/s3c-pcm.h"
++#include "../s3c24xx/s3c-i2s.h"
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++static int smdk6410_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ //struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++ unsigned int pll_out = 0; /*bclk = 0; */
++ int ret = 0;
++ unsigned int prescaler;
++
++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params));
++
++ /*PCLK & SCLK gating enable*/
++ writel(readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_IIS2, S3C_PCLK_GATE);
++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE);
++
++ /*Clear I2S prescaler value [13:8] and disable prescaler*/
++ /* set prescaler division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, 0);
++ if (ret < 0)
++ return ret;
++
++ s3cdbg("%s: %d , params = %d\n", __FUNCTION__, __LINE__, params_rate(params));
++
++ switch (params_rate(params)) {
++ case 8000:
++ case 16000:
++ case 32000:
++ case 64100:
++ writel(50332, S3C_EPLL_CON1);
++ writel((1<<31)|(32<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
++ break;
++ case 11025:
++ case 22050:
++ case 44100:
++ case 88200:
++ /* K=10398, M=45, P=1, S=3 -- Fout=67.738 */
++ writel(10398, S3C_EPLL_CON1);
++ writel((1<<31)|(45<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
++ break;
++ case 48000:
++ case 96000:
++ /* K=9961, M=49, P=1, S=3 -- Fin=12, Fout=73.728; r=1536 */
++ writel(9961, S3C_EPLL_CON1);
++ writel((1<<31)|(49<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
++ break;
++ default:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++ break;
++ }
++
++ while(!(__raw_readl(S3C_EPLL_CON0)&(1<<30)));
++
++ /* MUXepll : FOUTepll */
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++
++ /* AUDIO2 sel : FOUTepll */
++ writel((readl(S3C_CLK_SRC2)&~(0x7<<0))|(0<<0), S3C_CLK_SRC2);
++
++ /* CLK_DIV2 setting */
++ writel(0x0,S3C_CLK_DIV2);
++
++ switch (params_rate(params)) {
++ case 8000:
++ pll_out = 2048000;
++ prescaler = 8;
++ break;
++ case 11025:
++ pll_out = 2822400;
++ prescaler = 8;
++ break;
++ case 16000:
++ pll_out = 4096000;
++ prescaler = 4;
++ break;
++ case 22050:
++ pll_out = 5644800;
++ prescaler = 4;
++ break;
++ case 32000:
++ pll_out = 8192000;
++ prescaler = 2;
++ break;
++ case 44100:
++ /* Fout=73.728 */
++ pll_out = 11289600;
++ prescaler = 2;
++ break;
++ case 48000:
++ /* Fout=67.738 */
++ pll_out = 12288000;
++ prescaler = 2;
++ break;
++ case 88200:
++ pll_out = 22579200;
++ prescaler = 1;
++ break;
++ case 96000:
++ pll_out = 24576000;
++ prescaler = 1;
++ break;
++ default:
++ /* somtimes 32000 rate comes to 96000
++ default values are same as 32000 */
++ prescaler = 4;
++ pll_out = 12288000;
++ break;
++ }
++
++ /* set MCLK division for sample rate */
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S8:
++ case SNDRV_PCM_FORMAT_S16_LE:
++ prescaler *= 3;
++ break;
++ case SNDRV_PCM_FORMAT_S24_3LE:
++ prescaler *= 2;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ prescaler *= 2;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ prescaler = prescaler - 1;
++
++#if 0
++ /* set codec DAI configuration */
++ ret = codec_dai->dai_ops.set_fmt(codec_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS);
++ if (ret < 0)
++ return ret;
++#endif
++
++ /* set cpu DAI configuration */
++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS);
++ if (ret < 0)
++ return ret;
++
++#if 0
++ ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8580_DAC_CLKSEL,
++ WM8580_CLKSRC_MCLK);
++ if (ret < 0)
++ return ret;
++#endif
++
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK,
++ S3C64XX_IIS0MOD_256FS);
++ if (ret < 0)
++ return ret;
++
++ /* set prescaler division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
++ (prescaler << 0x8));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++/*
++ * WM8580 HiFi DAI opserations.
++ */
++static struct snd_soc_ops smdk6410_hifi_ops = {
++ .hw_params = smdk6410_hifi_hw_params,
++};
++
++static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
++ SND_SOC_DAPM_LINE("I2S Front Jack", NULL),
++ SND_SOC_DAPM_LINE("I2S Center Jack", NULL),
++ SND_SOC_DAPM_LINE("I2S Rear Jack", NULL),
++ SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++/* example machine audio_mapnections */
++static const char* audio_map[][3] = {
++
++ { "I2S Front Jack", NULL, "VOUT1L" },
++ { "I2S Front Jack", NULL, "VOUT1R" },
++
++ { "I2S Center Jack", NULL, "VOUT2L" },
++ { "I2S Center Jack", NULL, "VOUT2R" },
++
++ { "I2S Rear Jack", NULL, "VOUT3L" },
++ { "I2S Rear Jack", NULL, "VOUT3R" },
++
++ { "AINL", NULL, "Line In Jack" },
++ { "AINR", NULL, "Line In Jack" },
++
++ {NULL, NULL, NULL},
++};
++
++static int smdk6410_wm8580_init(struct snd_soc_codec *codec)
++{
++ int i;
++
++ /* Add smdk6410 specific widgets */
++ for (i = 0; i < ARRAY_SIZE(wm8580_dapm_widgets); i++)
++ snd_soc_dapm_new_control(codec, &wm8580_dapm_widgets[i]);
++
++ /* set up smdk6410 specific audio paths */
++ for (i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ /* No jack detect - mark all jacks as enabled */
++ for (i = 0; i < ARRAY_SIZE(wm8580_dapm_widgets); i++)
++ snd_soc_dapm_set_endpoint(codec,
++ wm8580_dapm_widgets[i].name, 1);
++
++ snd_soc_dapm_sync_endpoints(codec);
++
++ return 0;
++}
++
++static struct snd_soc_dai_link smdk6410_dai[] = {
++{
++ .name = "WM8580",
++ .stream_name = "WM8580 HiFi Playback",
++ .cpu_dai = &s3c_i2s_v40_dai,
++ .codec_dai = &wm8580_dai[WM8580_DAI_PAIFRX],
++ .init = smdk6410_wm8580_init,
++ .ops = &smdk6410_hifi_ops,
++},
++#if 0
++{
++ .name = "WM8580",
++ .stream_name = "WM8580 HiFi Capture",
++ .cpu_dai = &s3c_i2s_v40_dai,
++ .codec_dai = &wm8580_dai[WM8580_DAI_PAIFTX],
++ .init = smdk6410_wm8580_init,
++ .ops = &smdk6410_hifi_ops,
++},
++#endif
++};
++
++static struct snd_soc_machine smdk6410 = {
++ .name = "smdk6410",
++ .dai_link = smdk6410_dai,
++ .num_links = ARRAY_SIZE(smdk6410_dai),
++};
++
++static struct wm8580_setup_data smdk6410_wm8580_setup = {
++ .i2c_address = 0x1b,
++};
++
++static struct snd_soc_device smdk6410_snd_devdata = {
++ .machine = &smdk6410,
++ .platform = &s3c24xx_soc_platform,
++ .codec_dev = &soc_codec_dev_wm8580,
++ .codec_data = &smdk6410_wm8580_setup,
++};
++
++static struct platform_device *smdk6410_snd_device;
++
++static int __init smdk6410_init(void)
++{
++ int ret;
++
++#if 0
++ /* Set up GPIOs to enable I2SV40 pin */
++ s3c_gpio_cfgpin(S3C_GPC4, S3C_GPC4_I2S_V40_DO0);
++ s3c_gpio_cfgpin(S3C_GPC5, S3C_GPC5_I2S_V40_DO1);
++ s3c_gpio_cfgpin(S3C_GPC7, S3C_GPC7_I2S_V40_DO2);
++ s3c_gpio_cfgpin(S3C_GPH6, S3C_GPH6_I2S_V40_BCLK);
++ s3c_gpio_cfgpin(S3C_GPH7, S3C_GPH7_I2S_V40_CDCLK);
++ s3c_gpio_cfgpin(S3C_GPH8, S3C_GPH8_I2S_V40_LRCLK);
++ s3c_gpio_cfgpin(S3C_GPH9, S3C_GPH9_I2S_V40_DI);
++#endif
++
++ s3c_gpio_cfgpin(S3C_GPH6, S3C_GPH6_I2S_V40_BCLK);
++ s3c_gpio_cfgpin(S3C_GPH7, S3C_GPH7_I2S_V40_CDCLK);
++ s3c_gpio_cfgpin(S3C_GPH8, S3C_GPH8_I2S_V40_LRCLK);
++ s3c_gpio_cfgpin(S3C_GPH9, S3C_GPH9_I2S_V40_DI);
++ s3c_gpio_cfgpin(S3C_GPC4, S3C_GPC4_I2S_V40_DO0);
++ s3c_gpio_cfgpin(S3C_GPC5, S3C_GPC5_I2S_V40_DO1);
++ s3c_gpio_cfgpin(S3C_GPC7, S3C_GPC7_I2S_V40_DO2);
++
++ /* pull-up-enable, pull-down-disable*/
++ s3c_gpio_pullup(S3C_GPH6, 0x2);
++ s3c_gpio_pullup(S3C_GPH7, 0x2);
++ s3c_gpio_pullup(S3C_GPH8, 0x2);
++ s3c_gpio_pullup(S3C_GPH9, 0x2);
++ s3c_gpio_pullup(S3C_GPC4, 0x2);
++ s3c_gpio_pullup(S3C_GPC5, 0x2);
++ s3c_gpio_pullup(S3C_GPC7, 0x2);
++
++ smdk6410_snd_device = platform_device_alloc("soc-audio", -1);
++ if (!smdk6410_snd_device)
++ return -ENOMEM;
++
++ platform_set_drvdata(smdk6410_snd_device, &smdk6410_snd_devdata);
++ smdk6410_snd_devdata.dev = &smdk6410_snd_device->dev;
++ ret = platform_device_add(smdk6410_snd_device);
++
++ if (ret)
++ platform_device_put(smdk6410_snd_device);
++
++ return ret;
++}
++
++static void __exit smdk6410_exit(void)
++{
++ platform_device_unregister(smdk6410_snd_device);
++}
++
++module_init(smdk6410_init);
++module_exit(smdk6410_exit);
++
++/* Module information */
++MODULE_AUTHOR("Mark Brown");
++MODULE_DESCRIPTION("ALSA SoC SMDK6410 WM8580");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c64xx/smdk6410_wm8990.c b/sound/soc/s3c64xx/smdk6410_wm8990.c
+new file mode 100644
+index 0000000..0d75100
+--- /dev/null
++++ b/sound/soc/s3c64xx/smdk6410_wm8990.c
+@@ -0,0 +1,439 @@
++/*
++* smdk6410_wm8990.c -- SoC audio for SMDK6410 with WM8990
++ *
++ * Copyright 2007, 2008 Wolfson Microelectronics PLC.
++ * Author: Liam Girdwood
++ * lg@opensource.wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 28th Feb 2008 Initial version.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/timer.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware/scoop.h>
++#include <asm-arm/plat-s3c64xx/regs-iis.h>
++//#include <asm/arch/regs-iis.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/hardware.h>
++#include <asm/arch/audio.h>
++#include <asm/io.h>
++#include <asm/arch/spi-gpio.h>
++#include <asm/arch/regs-s3c-clock.h>
++//#include <asm/arch/regs-s3c6410-clock.h>
++
++#include "../codecs/wm8990.h"
++#include "../s3c24xx/s3c-pcm.h"
++#include "../s3c24xx/s3c-i2s.h"
++
++/* define the scenarios */
++#define SMDK6410_AUDIO_OFF 0
++#define SMDK6410_CAPTURE_MIC1 3
++#define SMDK6410_STEREO_TO_HEADPHONES 2
++#define SMDK6410_CAPTURE_LINE_IN 1
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++/*
++ * TODO: - We need to work out PLL values for 256FS for every rate.
++ */
++static int smdk6410_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++ unsigned int pll_out = 0, bclk = 0;
++ int ret = 0;
++ unsigned int iispsr, iismod;
++ unsigned int prescaler = 4;
++
++ u32* regs;
++ regs = ioremap(S3C6400_PA_IIS, 0x100);
++
++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params));
++
++ /*PCLK & SCLK gating enable*/
++ writel(readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_IIS0, S3C_PCLK_GATE);
++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE);
++
++ iismod = readl(regs + S3C64XX_IIS0MOD);
++ iismod &= ~S3C64XX_IIS0MOD_FS_MASK;
++ iismod &= ~S3C64XX_IIS0MOD_BFS_MASK;
++
++ /*Clear I2S prescaler value [13:8] and disable prescaler*/
++ iispsr = readl(regs + S3C64XX_IIS0PSR);
++ iispsr &=~((0x3f<<8)|(1<<15));
++ writel(iispsr, regs + S3C64XX_IIS0PSR);
++
++ s3cdbg("%s: %d , params = %d\n", __FUNCTION__, __LINE__, params_rate(params));
++
++ switch (params_rate(params)) {
++ case 8000:
++ case 16000:
++ case 32000:
++ case 64100:
++ writel(50332, S3C_EPLL_CON1);
++ writel((1<<31)|(32<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
++ break;
++ case 11025:
++ case 22050:
++ case 44100:
++ case 88200:
++ writel(10398, S3C_EPLL_CON1);
++ writel((1<<31)|(45<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
++ break;
++ case 48000:
++ case 96000:
++ writel(9961, S3C_EPLL_CON1);
++ writel((1<<31)|(49<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0);
++ break;
++ default:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++ break;
++ }
++
++ s3cdbg("%s, IISCON: %x IISMOD: %x,IISFIC: %x,IISPSR: %x\n",
++ __FUNCTION__ , readl(S3C_IIS0CON), readl(S3C_IIS0MOD),
++ readl(S3C_IIS0FIC), readl(S3C_IIS0PSR));
++
++ while(!(__raw_readl(S3C_EPLL_CON0)&(1<<30)));
++
++ /* MUXepll : FOUTepll */
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++ /* AUDIO0 sel : FOUTepll */
++ writel((readl(S3C_CLK_SRC)&~(0x7<<7))|(0<<7), S3C_CLK_SRC);
++
++ /* CLK_DIV2 setting */
++ writel(0x0,S3C_CLK_DIV2);
++
++ switch (params_rate(params)) {
++ case 8000:
++ pll_out = 2048000;
++ prescaler = 8;
++ break;
++ case 11025:
++ pll_out = 2822400;
++ prescaler = 8;
++ break;
++ case 16000:
++ pll_out = 4096000;
++ prescaler = 4;
++ break;
++ case 22050:
++ pll_out = 5644800;
++ prescaler = 4;
++ break;
++ case 32000:
++ pll_out = 8192000;
++ prescaler = 2;
++ break;
++ case 44100:
++ pll_out = 11289600;
++ //prescaler = 6;
++ prescaler = 2;
++ break;
++ case 48000:
++ pll_out = 12288000;
++ prescaler = 2;
++ break;
++ case 88200:
++ pll_out = 22579200;
++ prescaler = 1;
++ break;
++ case 96000:
++ pll_out = 24576000;
++ prescaler = 1;
++ break;
++ default:
++ /* somtimes 32000 rate comes to 96000
++ default values are same as 32000 */
++ iismod |= S3C64XX_IIS0MOD_384FS;
++ pll_out = 12288000;
++ break;
++ }
++
++ /* set MCLK division for sample rate */
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S8:
++ case SNDRV_PCM_FORMAT_S16_LE:
++ iismod |= S3C64XX_IIS0MOD_256FS | S3C64XX_IIS0MOD_32FS;
++ prescaler *= 3;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ iismod |= S3C64XX_IIS0MOD_384FS | S3C64XX_IIS0MOD_48FS;
++ prescaler *= 2;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ prescaler = prescaler - 1;
++ writel(iismod , regs + S3C64XX_IIS0MOD);
++
++ /* set codec DAI configuration */
++ ret = codec_dai->dai_ops.set_fmt(codec_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS );
++ if (ret < 0)
++ return ret;
++
++ /* set cpu DAI configuration */
++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS );
++ if (ret < 0)
++ return ret;
++
++ /* set the codec system clock for DAC and ADC */
++ ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8990_MCLK, pll_out,
++ SND_SOC_CLOCK_IN);
++ if (ret < 0)
++ return ret;
++
++ /* set prescaler division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
++ (prescaler << 0x8));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++/*
++ * Neo1973 WM8990 HiFi DAI opserations.
++ */
++static struct snd_soc_ops smdk6410_hifi_ops = {
++ .hw_params = smdk6410_hifi_hw_params,
++};
++
++static int smdk6410_scenario = 0;
++
++static int smdk6410_get_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ ucontrol->value.integer.value[0] = smdk6410_scenario;
++ return 0;
++}
++
++static int set_scenario_endpoints(struct snd_soc_codec *codec, int scenario)
++{
++ smdk6410_scenario = scenario;
++ switch (smdk6410_scenario) {
++ case SMDK6410_AUDIO_OFF:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6410_STEREO_TO_HEADPHONES:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6410_CAPTURE_MIC1:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6410_CAPTURE_LINE_IN:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ default:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ }
++
++ snd_soc_dapm_sync_endpoints(codec);
++ return 0;
++}
++
++static int smdk6410_set_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++
++ if (smdk6410_scenario == ucontrol->value.integer.value[0])
++ return 0;
++
++ set_scenario_endpoints(codec, ucontrol->value.integer.value[0]);
++ return 1;
++}
++
++static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headphone Jack", NULL),
++ SND_SOC_DAPM_MIC("Mic1 Jack", NULL),
++ SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++/* example machine audio_mapnections */
++static const char* audio_map[][3] = {
++
++ /* no irq jack detect */
++ {"Headphone Jack", NULL, "LOUT"},
++ {"Headphone Jack", NULL, "ROUT"},
++
++ /* mic is connected to LIN1 and LIN2 - with bias */
++ {"LIN1", NULL, "Mic1 Jack"},
++ //{"LIN2", NULL, "Mic1 Jack"},
++
++ {"LIN2", NULL, "Line In Jack"},
++ {"RIN2", NULL, "Line In Jack"},
++
++ {NULL, NULL, NULL},
++};
++
++static const char *smdk_scenarios[] = {
++ "Off",
++ "Capture Line In",
++ "Headphones",
++ "Capture Mic1",
++};
++
++static const struct soc_enum smdk_scenario_enum[] = {
++ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(smdk_scenarios),smdk_scenarios),
++};
++
++static const struct snd_kcontrol_new wm8990_smdk6410_controls[] = {
++ SOC_ENUM_EXT("SMDK Mode", smdk_scenario_enum[0],
++ smdk6410_get_scenario, smdk6410_set_scenario),
++};
++
++/*
++ * This is an example machine initialisation for a wm8990 connected to a
++ * smdk6410. It is missing logic to detect hp/mic insertions and logic
++ * to re-route the audio in such an event.
++ */
++static int smdk6410_wm8990_init(struct snd_soc_codec *codec)
++{
++ int i, err;
++
++ /* Add smdk6410 specific widgets */
++ for (i = 0; i < ARRAY_SIZE(wm8990_dapm_widgets); i++)
++ snd_soc_dapm_new_control(codec, &wm8990_dapm_widgets[i]);
++
++ /* add smdk6410 specific controls */
++ for (i = 0; i < ARRAY_SIZE(wm8990_smdk6410_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm8990_smdk6410_controls[i],
++ codec, NULL));
++ if (err < 0)
++ return err;
++ }
++
++ /* set up smdk6410 specific audio paths */
++ for (i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ /* not connected */
++ snd_soc_dapm_set_endpoint(codec, "RIN1", 0);
++ snd_soc_dapm_set_endpoint(codec, "LIN3", 0);
++ snd_soc_dapm_set_endpoint(codec, "LIN4", 0);
++ snd_soc_dapm_set_endpoint(codec, "RIN3", 0);
++ snd_soc_dapm_set_endpoint(codec, "RIN4", 0);
++ snd_soc_dapm_set_endpoint(codec, "OUT3", 0);
++ snd_soc_dapm_set_endpoint(codec, "OUT4", 0);
++ snd_soc_dapm_set_endpoint(codec, "SPKP", 0);
++ snd_soc_dapm_set_endpoint(codec, "SPKN", 0);
++ snd_soc_dapm_set_endpoint(codec, "ROP", 0);
++ snd_soc_dapm_set_endpoint(codec, "RON", 0);
++ snd_soc_dapm_set_endpoint(codec, "LOP", 0);
++ snd_soc_dapm_set_endpoint(codec, "LON", 0);
++
++ /* set endpoints to default mode & sync with DAPM */
++ set_scenario_endpoints(codec, SMDK6410_STEREO_TO_HEADPHONES);
++
++ return 0;
++}
++
++static struct snd_soc_dai_link smdk6410_dai[] = {
++{ /* Hifi Playback - for similatious use with voice below */
++ .name = "WM8990",
++ .stream_name = "WM8990 HiFi",
++ .cpu_dai = &s3c_i2s_dai,
++ .codec_dai = &wm8990_dai,
++ .init = smdk6410_wm8990_init,
++ .ops = &smdk6410_hifi_ops,
++},
++};
++
++static struct snd_soc_machine smdk6410 = {
++ .name = "smdk6410",
++ .dai_link = smdk6410_dai,
++ .num_links = ARRAY_SIZE(smdk6410_dai),
++};
++
++static struct wm8990_setup_data smdk6410_wm8990_setup = {
++ .i2c_address = 0x1b,
++};
++
++static struct snd_soc_device smdk6410_snd_devdata = {
++ .machine = &smdk6410,
++ .platform = &s3c24xx_soc_platform,
++ .codec_dev = &soc_codec_dev_wm8990,
++ .codec_data = &smdk6410_wm8990_setup,
++};
++
++static struct platform_device *smdk6410_snd_device;
++
++static int __init smdk6410_init(void)
++{
++ int ret;
++
++ smdk6410_snd_device = platform_device_alloc("soc-audio", -1);
++ if (!smdk6410_snd_device)
++ return -ENOMEM;
++
++ platform_set_drvdata(smdk6410_snd_device, &smdk6410_snd_devdata);
++ smdk6410_snd_devdata.dev = &smdk6410_snd_device->dev;
++ ret = platform_device_add(smdk6410_snd_device);
++
++ if (ret)
++ platform_device_put(smdk6410_snd_device);
++
++ return ret;
++}
++
++static void __exit smdk6410_exit(void)
++{
++ platform_device_unregister(smdk6410_snd_device);
++}
++
++module_init(smdk6410_init);
++module_exit(smdk6410_exit);
++
++/* Module information */
++MODULE_AUTHOR("Liam Girdwood");
++MODULE_DESCRIPTION("ALSA SoC WM8990 SMDK6410");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/s3c64xx/smdk64xx_wm9713.c b/sound/soc/s3c64xx/smdk64xx_wm9713.c
+new file mode 100644
+index 0000000..09e44d2
+--- /dev/null
++++ b/sound/soc/s3c64xx/smdk64xx_wm9713.c
+@@ -0,0 +1,88 @@
++/*
++ * smdk6400_wm9713.c -- SoC audio for smdk6400
++ *
++ * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
++ *
++ * Copyright 2007 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 8th Mar 2007 Initial version.
++ * 20th Sep 2007 Apply at smdk6400
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include "../codecs/wm9713.h"
++#include "../s3c24xx/s3c-pcm.h"
++#include "s3c64xx-ac97.h"
++
++static struct snd_soc_machine smdk6400;
++
++static struct snd_soc_dai_link smdk6400_dai[] = {
++{
++ .name = "AC97",
++ .stream_name = "AC97 HiFi",
++ .cpu_dai = &s3c6400_ac97_dai[0],
++ .codec_dai = &wm9713_dai[WM9713_DAI_AC97_HIFI],
++},
++};
++
++static struct snd_soc_machine smdk6400 = {
++ .name = "SMDK6400",
++ .dai_link = smdk6400_dai,
++ .num_links = ARRAY_SIZE(smdk6400_dai),
++};
++
++static struct snd_soc_device smdk6400_snd_ac97_devdata = {
++ .machine = &smdk6400,
++ .platform = &s3c24xx_soc_platform,
++ .codec_dev = &soc_codec_dev_wm9713,
++};
++
++static struct platform_device *smdk6400_snd_ac97_device;
++
++static int __init smdk6400_init(void)
++{
++ int ret;
++
++ smdk6400_snd_ac97_device = platform_device_alloc("soc-audio", -1);
++ if (!smdk6400_snd_ac97_device)
++ return -ENOMEM;
++
++ platform_set_drvdata(smdk6400_snd_ac97_device,
++ &smdk6400_snd_ac97_devdata);
++ smdk6400_snd_ac97_devdata.dev = &smdk6400_snd_ac97_device->dev;
++ ret = platform_device_add(smdk6400_snd_ac97_device);
++
++ if (ret)
++ platform_device_put(smdk6400_snd_ac97_device);
++
++ return ret;
++}
++
++static void __exit smdk6400_exit(void)
++{
++ platform_device_unregister(smdk6400_snd_ac97_device);
++}
++
++module_init(smdk6400_init);
++module_exit(smdk6400_exit);
++
++/* Module information */
++MODULE_AUTHOR("Samsung: Ryu");
++MODULE_DESCRIPTION("ALSA SoC WM9713 SMDK6400");
++MODULE_LICENSE("GPL");
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/base/0002-Apply-smartq-patch.patch b/recipes/linux/linux-2.6.24/smartq5/base/0002-Apply-smartq-patch.patch
new file mode 100644
index 0000000000..142250db3c
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/base/0002-Apply-smartq-patch.patch
@@ -0,0 +1,94756 @@
+From 00f370ce61f903ba8697709d58dc459fd65579f5 Mon Sep 17 00:00:00 2001
+From: YouSheng <david.ysh@gmail.com>
+Date: Tue, 21 Jul 2009 14:56:03 +0800
+Subject: [PATCH 2/4] Apply smartq patch
+
+---
+ .gitignore | 3 +
+ Makefile | 6 +-
+ arch/arm/Makefile | 4 +
+ arch/arm/boot/.gitignore | 3 +
+ arch/arm/configs/hhs3c6410_4_3_defconfig | 1592 ++++
+ arch/arm/configs/hhs3c6410_7_defconfig | 1592 ++++
+ arch/arm/mach-s3c6400/Makefile | 4 +-
+ arch/arm/mach-s3c6400/leds-s3c6400.c | 2 +-
+ arch/arm/mach-s3c6400/leds.c | 12 +-
+ arch/arm/mach-s3c6400/mach-smdk6400.c | 68 +-
+ arch/arm/mach-s3c6410/Makefile | 4 +-
+ arch/arm/mach-s3c6410/clock.c | 22 +-
+ arch/arm/mach-s3c6410/leds-s3c6410.c | 2 +-
+ arch/arm/mach-s3c6410/leds.c | 12 +-
+ arch/arm/mach-s3c6410/mach-smdk6410.c | 228 +-
+ arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c | 5 +-
+ arch/arm/plat-s3c24xx/devs.c | 11 +
+ arch/arm/plat-s3c24xx/gpio.c | 21 +-
+ arch/arm/plat-s3c64xx/Makefile | 2 +-
+ arch/arm/plat-s3c64xx/irq-pl192.c | 94 +-
+ arch/arm/plat-s3c64xx/pm.c | 80 +-
+ arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c | 7 +-
+ arch/arm/vfp/entry.S | 8 +-
+ arch/arm/vfp/vfp.h | 6 +-
+ arch/arm/vfp/vfphw.S | 96 +-
+ arch/arm/vfp/vfpinstr.h | 6 +-
+ arch/arm/vfp/vfpmodule.c | 164 +-
+ drivers/Makefile | 2 +-
+ drivers/bluetooth/Kconfig | 11 +-
+ drivers/bluetooth/bcm203x.c | 9 +-
+ drivers/bluetooth/bfusb.c | 13 +-
+ drivers/bluetooth/bluecard_cs.c | 10 +-
+ drivers/bluetooth/bpa10x.c | 17 +-
+ drivers/bluetooth/bt3c_cs.c | 136 +-
+ drivers/bluetooth/btsdio.c | 6 +-
+ drivers/bluetooth/btuart_cs.c | 134 +-
+ drivers/bluetooth/btusb.c | 482 ++-
+ drivers/bluetooth/dtl1_cs.c | 74 +-
+ drivers/bluetooth/hci_bcsp.c | 62 +-
+ drivers/bluetooth/hci_ldisc.c | 24 +-
+ drivers/bluetooth/hci_usb.c | 44 +-
+ drivers/bluetooth/hci_usb.h | 26 +-
+ drivers/bluetooth/hci_vhci.c | 16 +-
+ drivers/char/Kconfig | 13 +
+ drivers/char/Makefile | 4 +-
+ drivers/char/apm-emulation.c | 8 +
+ drivers/char/hhtech_gpio.c | 883 +++
+ drivers/input/keyboard/gpio_keys.c | 158 +-
+ drivers/input/keyboard/s3c-keypad.c | 9 +-
+ drivers/input/keyboard/s3c-keypad.h | 37 +-
+ drivers/input/mousedev.c | 3 +
+ drivers/input/touchscreen/s3c-ts.c | 90 +-
+ drivers/misc/Kconfig | 5 +
+ drivers/misc/Makefile | 1 +
+ drivers/misc/smartq5_encrypt/Makefile | 3 +
+ drivers/misc/smartq5_encrypt/lib_Crypto.h | 1426 ++++
+ drivers/misc/smartq5_encrypt/smartq5_encrypt.c | 117 +
+ drivers/mmc/card/block.c | 13 +
+ drivers/mmc/core/sdio_cis.c | 4 +
+ drivers/mmc/host/s3c-hsmmc.c | 58 +-
+ drivers/net/dm9000.c | 13 +-
+ drivers/net/wireless/Kconfig | 22 +
+ drivers/net/wireless/Makefile | 2 +
+ drivers/net/wireless/libertas/Makefile | 2 +-
+ drivers/net/wireless/libertas/cmd.c | 6 +
+ drivers/net/wireless/libertas/cmdresp.c | 5 +-
+ drivers/net/wireless/libertas/ioctl.c | 1046 +++
+ drivers/net/wireless/libertas/main.c | 8 +-
+ drivers/net/wireless/libertas/scan.c | 4 +-
+ drivers/net/wireless/libertas/wext.c | 151 +-
+ drivers/net/wireless/libertas/wext.h | 41 +
+ drivers/net/wireless/marvell8686/Makefile | 15 +
+ drivers/net/wireless/marvell8686/README | 1587 ++++
+ drivers/net/wireless/marvell8686/host.h | 349 +
+ drivers/net/wireless/marvell8686/hostcmd.h | 1052 +++
+ drivers/net/wireless/marvell8686/if_sdio.c | 1379 ++++
+ drivers/net/wireless/marvell8686/if_sdio.h | 97 +
+ drivers/net/wireless/marvell8686/include.h | 42 +
+ drivers/net/wireless/marvell8686/os_defs.h | 42 +
+ drivers/net/wireless/marvell8686/os_headers.h | 69 +
+ drivers/net/wireless/marvell8686/os_macros.h | 165 +
+ drivers/net/wireless/marvell8686/os_timers.h | 83 +
+ drivers/net/wireless/marvell8686/release_version.h | 5 +
+ drivers/net/wireless/marvell8686/sbi.h | 111 +
+ drivers/net/wireless/marvell8686/sdio.h | 112 +
+ drivers/net/wireless/marvell8686/wlan_11d.c | 893 +++
+ drivers/net/wireless/marvell8686/wlan_11d.h | 110 +
+ drivers/net/wireless/marvell8686/wlan_cmd.c | 2501 ++++++
+ drivers/net/wireless/marvell8686/wlan_cmdresp.c | 1595 ++++
+ drivers/net/wireless/marvell8686/wlan_debug.c | 281 +
+ drivers/net/wireless/marvell8686/wlan_decl.h | 109 +
+ drivers/net/wireless/marvell8686/wlan_defs.h | 623 ++
+ drivers/net/wireless/marvell8686/wlan_dev.h | 468 ++
+ drivers/net/wireless/marvell8686/wlan_fops.c | 217 +
+ drivers/net/wireless/marvell8686/wlan_fw.c | 532 ++
+ drivers/net/wireless/marvell8686/wlan_join.c | 2031 +++++
+ drivers/net/wireless/marvell8686/wlan_join.h | 84 +
+ drivers/net/wireless/marvell8686/wlan_main.c | 1359 ++++
+ drivers/net/wireless/marvell8686/wlan_proc.c | 213 +
+ drivers/net/wireless/marvell8686/wlan_rx.c | 367 +
+ drivers/net/wireless/marvell8686/wlan_scan.c | 3226 ++++++++
+ drivers/net/wireless/marvell8686/wlan_scan.h | 284 +
+ drivers/net/wireless/marvell8686/wlan_thread.h | 58 +
+ drivers/net/wireless/marvell8686/wlan_tx.c | 286 +
+ drivers/net/wireless/marvell8686/wlan_types.h | 1050 +++
+ drivers/net/wireless/marvell8686/wlan_version.h | 18 +
+ drivers/net/wireless/marvell8686/wlan_wext.c | 8045 ++++++++++++++++++++
+ drivers/net/wireless/marvell8686/wlan_wext.h | 406 +
+ drivers/net/wireless/marvell8686/wlan_wmm.c | 1666 ++++
+ drivers/net/wireless/marvell8686/wlan_wmm.h | 111 +
+ drivers/rtc/rtc-s3c.c | 18 +-
+ drivers/serial/s3c6400.c | 10 +-
+ drivers/usb/core/driver.c | 11 +-
+ drivers/usb/gadget/Kconfig | 6 +-
+ drivers/usb/gadget/s3c-udc-otg-hs.c | 2 +-
+ drivers/usb/host/ohci-s3c2410.c | 61 +-
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c | 49 +-
+ drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h | 2 +-
+ drivers/usb/host/s3c-otg/s3c-otg-isr.c | 10 +
+ drivers/usb/host/s3c-otg/s3c-otg-oci.c | 2 +-
+ drivers/usb/host/s3c-otg/s3c-otg-roothub.c | 12 +-
+ drivers/usb/misc/Kconfig | 9 +
+ drivers/usb/misc/Makefile | 1 +
+ drivers/usb/serial/option.c | 442 +-
+ drivers/video/Kconfig | 10 +
+ drivers/video/s3c/Makefile | 2 +
+ drivers/video/s3c/colorbar.c | 423 +
+ drivers/video/s3c/s3cfb.c | 49 +-
+ drivers/video/s3c/s3cfb.h | 5 +-
+ drivers/video/s3c/s3cfb_a070vw04.c | 263 +
+ drivers/video/s3c/s3cfb_fimd4x.c | 27 +-
+ drivers/video/s3c/s3cfb_td043mtex.c | 279 +
+ drivers/watchdog/s3c2410_wdt.c | 15 +
+ fs/Kconfig | 7 +
+ fs/Makefile | 6 +
+ fs/aufs/Kconfig | 283 +
+ fs/aufs/Makefile | 70 +
+ fs/aufs/aufs.h | 118 +
+ fs/aufs/br_fuse.c | 80 +
+ fs/aufs/br_nfs.c | 390 +
+ fs/aufs/br_xfs.c | 74 +
+ fs/aufs/branch.c | 1036 +++
+ fs/aufs/branch.h | 443 ++
+ fs/aufs/cpup.c | 1138 +++
+ fs/aufs/cpup.h | 95 +
+ fs/aufs/dcsub.c | 250 +
+ fs/aufs/dcsub.h | 54 +
+ fs/aufs/debug.c | 539 ++
+ fs/aufs/debug.h | 337 +
+ fs/aufs/dentry.c | 960 +++
+ fs/aufs/dentry.h | 398 +
+ fs/aufs/dinfo.c | 436 ++
+ fs/aufs/dir.c | 558 ++
+ fs/aufs/dir.h | 154 +
+ fs/aufs/dlgt.c | 112 +
+ fs/aufs/export.c | 809 ++
+ fs/aufs/f_op.c | 813 ++
+ fs/aufs/file.c | 806 ++
+ fs/aufs/file.h | 262 +
+ fs/aufs/finfo.c | 186 +
+ fs/aufs/getattr.c | 133 +
+ fs/aufs/hin_or_dlgt.c | 736 ++
+ fs/aufs/hinode.h | 184 +
+ fs/aufs/hinotify.c | 1146 +++
+ fs/aufs/i_op.c | 954 +++
+ fs/aufs/i_op_add.c | 757 ++
+ fs/aufs/i_op_del.c | 566 ++
+ fs/aufs/i_op_ren.c | 1261 +++
+ fs/aufs/iinfo.c | 284 +
+ fs/aufs/inode.c | 430 ++
+ fs/aufs/inode.h | 593 ++
+ fs/aufs/misc.c | 325 +
+ fs/aufs/misc.h | 244 +
+ fs/aufs/module.c | 295 +
+ fs/aufs/module.h | 81 +
+ fs/aufs/opts.c | 1622 ++++
+ fs/aufs/opts.h | 269 +
+ fs/aufs/plink.c | 364 +
+ fs/aufs/robr.c | 117 +
+ fs/aufs/sbinfo.c | 223 +
+ fs/aufs/super.c | 1032 +++
+ fs/aufs/super.h | 579 ++
+ fs/aufs/sysaufs.c | 752 ++
+ fs/aufs/sysaufs.h | 211 +
+ fs/aufs/sysrq.c | 296 +
+ fs/aufs/vdir.c | 941 +++
+ fs/aufs/vfsub.c | 682 ++
+ fs/aufs/vfsub.h | 600 ++
+ fs/aufs/wbr_policy.c | 702 ++
+ fs/aufs/whout.c | 1162 +++
+ fs/aufs/whout.h | 134 +
+ fs/aufs/wkq.c | 385 +
+ fs/aufs/wkq.h | 128 +
+ fs/aufs/xino.c | 1276 ++++
+ fs/yaffs2/Kconfig | 156 +
+ fs/yaffs2/Makefile | 10 +
+ fs/yaffs2/devextras.h | 199 +
+ fs/yaffs2/moduleconfig.h | 65 +
+ fs/yaffs2/yaffs_checkptrw.c | 405 +
+ fs/yaffs2/yaffs_checkptrw.h | 35 +
+ fs/yaffs2/yaffs_ecc.c | 331 +
+ fs/yaffs2/yaffs_ecc.h | 44 +
+ fs/yaffs2/yaffs_fs.c | 2393 ++++++
+ fs/yaffs2/yaffs_getblockinfo.h | 34 +
+ fs/yaffs2/yaffs_guts.c | 7676 +++++++++++++++++++
+ fs/yaffs2/yaffs_guts.h | 906 +++
+ fs/yaffs2/yaffs_mtdif.c | 241 +
+ fs/yaffs2/yaffs_mtdif.h | 32 +
+ fs/yaffs2/yaffs_mtdif1.c | 369 +
+ fs/yaffs2/yaffs_mtdif1.h | 28 +
+ fs/yaffs2/yaffs_mtdif2.c | 248 +
+ fs/yaffs2/yaffs_mtdif2.h | 29 +
+ fs/yaffs2/yaffs_nand.c | 135 +
+ fs/yaffs2/yaffs_nand.h | 44 +
+ fs/yaffs2/yaffs_nandemul2k.h | 39 +
+ fs/yaffs2/yaffs_packedtags1.c | 52 +
+ fs/yaffs2/yaffs_packedtags1.h | 37 +
+ fs/yaffs2/yaffs_packedtags2.c | 208 +
+ fs/yaffs2/yaffs_packedtags2.h | 43 +
+ fs/yaffs2/yaffs_qsort.c | 160 +
+ fs/yaffs2/yaffs_qsort.h | 23 +
+ fs/yaffs2/yaffs_tagscompat.c | 547 ++
+ fs/yaffs2/yaffs_tagscompat.h | 41 +
+ fs/yaffs2/yaffs_tagsvalidity.c | 28 +
+ fs/yaffs2/yaffs_tagsvalidity.h | 24 +
+ fs/yaffs2/yaffsinterface.h | 21 +
+ fs/yaffs2/yportenv.h | 202 +
+ include/asm-arm/arch-s3c2410/gpio.h | 1 +
+ include/asm-arm/arch-s3c2410/hardware.h | 4 +-
+ include/asm-arm/arch-s3c2410/hsmmc.h | 5 +-
+ include/asm-arm/arch-s3c2410/regs-s3c6410-clock.h | 262 +
+ include/asm-arm/arch-s3c2410/reserved_mem.h | 2 +-
+ include/asm-arm/arch-s3c2410/system.h | 3 +-
+ include/asm-arm/plat-s3c24xx/devs.h | 2 +
+ include/asm-arm/plat-s3c64xx/hhtech_gpio.h | 64 +
+ include/asm-arm/vfp.h | 36 +-
+ include/asm-arm/vfpmacros.h | 20 +-
+ include/linux/aufs_type.h | 127 +
+ include/linux/gpio_keys.h | 2 +
+ kernel/power/main.c | 38 +-
+ sound/soc/codecs/Kconfig | 6 +-
+ sound/soc/codecs/Makefile | 2 +
+ sound/soc/codecs/wm8987.c | 1330 ++++
+ sound/soc/codecs/wm8987.h | 110 +
+ sound/soc/s3c64xx/Kconfig | 25 +-
+ sound/soc/s3c64xx/Makefile | 2 +
+ sound/soc/s3c64xx/s3c6410-i2s-v32.c | 4 +-
+ sound/soc/s3c64xx/smdk6410_wm8987.c | 623 ++
+ 248 files changed, 89139 insertions(+), 813 deletions(-)
+ create mode 100644 arch/arm/configs/hhs3c6410_4_3_defconfig
+ create mode 100644 arch/arm/configs/hhs3c6410_7_defconfig
+ create mode 100644 drivers/char/hhtech_gpio.c
+ create mode 100644 drivers/misc/smartq5_encrypt/Makefile
+ create mode 100644 drivers/misc/smartq5_encrypt/lib_Crypto.h
+ create mode 100644 drivers/misc/smartq5_encrypt/smartq5_encrypt.c
+ create mode 100644 drivers/net/wireless/libertas/ioctl.c
+ create mode 100644 drivers/net/wireless/marvell8686/Makefile
+ create mode 100644 drivers/net/wireless/marvell8686/README
+ create mode 100644 drivers/net/wireless/marvell8686/host.h
+ create mode 100644 drivers/net/wireless/marvell8686/hostcmd.h
+ create mode 100644 drivers/net/wireless/marvell8686/if_sdio.c
+ create mode 100644 drivers/net/wireless/marvell8686/if_sdio.h
+ create mode 100644 drivers/net/wireless/marvell8686/include.h
+ create mode 100644 drivers/net/wireless/marvell8686/os_defs.h
+ create mode 100644 drivers/net/wireless/marvell8686/os_headers.h
+ create mode 100644 drivers/net/wireless/marvell8686/os_macros.h
+ create mode 100644 drivers/net/wireless/marvell8686/os_timers.h
+ create mode 100644 drivers/net/wireless/marvell8686/release_version.h
+ create mode 100644 drivers/net/wireless/marvell8686/sbi.h
+ create mode 100644 drivers/net/wireless/marvell8686/sdio.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_11d.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_11d.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_cmd.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_cmdresp.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_debug.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_decl.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_defs.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_dev.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_fops.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_fw.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_join.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_join.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_main.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_proc.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_rx.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_scan.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_scan.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_thread.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_tx.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_types.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_version.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_wext.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_wext.h
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_wmm.c
+ create mode 100644 drivers/net/wireless/marvell8686/wlan_wmm.h
+ create mode 100644 drivers/video/s3c/colorbar.c
+ create mode 100644 drivers/video/s3c/s3cfb_a070vw04.c
+ create mode 100644 drivers/video/s3c/s3cfb_td043mtex.c
+ create mode 100644 fs/aufs/Kconfig
+ create mode 100644 fs/aufs/Makefile
+ create mode 100644 fs/aufs/aufs.h
+ create mode 100644 fs/aufs/br_fuse.c
+ create mode 100644 fs/aufs/br_nfs.c
+ create mode 100644 fs/aufs/br_xfs.c
+ create mode 100644 fs/aufs/branch.c
+ create mode 100644 fs/aufs/branch.h
+ create mode 100644 fs/aufs/cpup.c
+ create mode 100644 fs/aufs/cpup.h
+ create mode 100644 fs/aufs/dcsub.c
+ create mode 100644 fs/aufs/dcsub.h
+ create mode 100644 fs/aufs/debug.c
+ create mode 100644 fs/aufs/debug.h
+ create mode 100644 fs/aufs/dentry.c
+ create mode 100644 fs/aufs/dentry.h
+ create mode 100644 fs/aufs/dinfo.c
+ create mode 100644 fs/aufs/dir.c
+ create mode 100644 fs/aufs/dir.h
+ create mode 100644 fs/aufs/dlgt.c
+ create mode 100644 fs/aufs/export.c
+ create mode 100644 fs/aufs/f_op.c
+ create mode 100644 fs/aufs/file.c
+ create mode 100644 fs/aufs/file.h
+ create mode 100644 fs/aufs/finfo.c
+ create mode 100644 fs/aufs/getattr.c
+ create mode 100644 fs/aufs/hin_or_dlgt.c
+ create mode 100644 fs/aufs/hinode.h
+ create mode 100644 fs/aufs/hinotify.c
+ create mode 100644 fs/aufs/i_op.c
+ create mode 100644 fs/aufs/i_op_add.c
+ create mode 100644 fs/aufs/i_op_del.c
+ create mode 100644 fs/aufs/i_op_ren.c
+ create mode 100644 fs/aufs/iinfo.c
+ create mode 100644 fs/aufs/inode.c
+ create mode 100644 fs/aufs/inode.h
+ create mode 100644 fs/aufs/misc.c
+ create mode 100644 fs/aufs/misc.h
+ create mode 100644 fs/aufs/module.c
+ create mode 100644 fs/aufs/module.h
+ create mode 100644 fs/aufs/opts.c
+ create mode 100644 fs/aufs/opts.h
+ create mode 100644 fs/aufs/plink.c
+ create mode 100644 fs/aufs/robr.c
+ create mode 100644 fs/aufs/sbinfo.c
+ create mode 100644 fs/aufs/super.c
+ create mode 100644 fs/aufs/super.h
+ create mode 100644 fs/aufs/sysaufs.c
+ create mode 100644 fs/aufs/sysaufs.h
+ create mode 100644 fs/aufs/sysrq.c
+ create mode 100644 fs/aufs/vdir.c
+ create mode 100644 fs/aufs/vfsub.c
+ create mode 100644 fs/aufs/vfsub.h
+ create mode 100644 fs/aufs/wbr_policy.c
+ create mode 100644 fs/aufs/whout.c
+ create mode 100644 fs/aufs/whout.h
+ create mode 100644 fs/aufs/wkq.c
+ create mode 100644 fs/aufs/wkq.h
+ create mode 100644 fs/aufs/xino.c
+ create mode 100644 fs/yaffs2/Kconfig
+ create mode 100644 fs/yaffs2/Makefile
+ create mode 100644 fs/yaffs2/devextras.h
+ create mode 100644 fs/yaffs2/moduleconfig.h
+ create mode 100644 fs/yaffs2/yaffs_checkptrw.c
+ create mode 100644 fs/yaffs2/yaffs_checkptrw.h
+ create mode 100644 fs/yaffs2/yaffs_ecc.c
+ create mode 100644 fs/yaffs2/yaffs_ecc.h
+ create mode 100644 fs/yaffs2/yaffs_fs.c
+ create mode 100644 fs/yaffs2/yaffs_getblockinfo.h
+ create mode 100644 fs/yaffs2/yaffs_guts.c
+ create mode 100644 fs/yaffs2/yaffs_guts.h
+ create mode 100644 fs/yaffs2/yaffs_mtdif.c
+ create mode 100644 fs/yaffs2/yaffs_mtdif.h
+ create mode 100644 fs/yaffs2/yaffs_mtdif1.c
+ create mode 100644 fs/yaffs2/yaffs_mtdif1.h
+ create mode 100644 fs/yaffs2/yaffs_mtdif2.c
+ create mode 100644 fs/yaffs2/yaffs_mtdif2.h
+ create mode 100644 fs/yaffs2/yaffs_nand.c
+ create mode 100644 fs/yaffs2/yaffs_nand.h
+ create mode 100644 fs/yaffs2/yaffs_nandemul2k.h
+ create mode 100644 fs/yaffs2/yaffs_packedtags1.c
+ create mode 100644 fs/yaffs2/yaffs_packedtags1.h
+ create mode 100644 fs/yaffs2/yaffs_packedtags2.c
+ create mode 100644 fs/yaffs2/yaffs_packedtags2.h
+ create mode 100644 fs/yaffs2/yaffs_qsort.c
+ create mode 100644 fs/yaffs2/yaffs_qsort.h
+ create mode 100644 fs/yaffs2/yaffs_tagscompat.c
+ create mode 100644 fs/yaffs2/yaffs_tagscompat.h
+ create mode 100644 fs/yaffs2/yaffs_tagsvalidity.c
+ create mode 100644 fs/yaffs2/yaffs_tagsvalidity.h
+ create mode 100644 fs/yaffs2/yaffsinterface.h
+ create mode 100644 fs/yaffs2/yportenv.h
+ create mode 100644 include/asm-arm/arch-s3c2410/regs-s3c6410-clock.h
+ create mode 100644 include/asm-arm/plat-s3c64xx/hhtech_gpio.h
+ create mode 100644 include/linux/aufs_type.h
+ create mode 100644 sound/soc/codecs/wm8987.c
+ create mode 100644 sound/soc/codecs/wm8987.h
+ create mode 100644 sound/soc/s3c64xx/smdk6410_wm8987.c
+
+diff --git a/.gitignore b/.gitignore
+index 8d14531..7320219 100644
+--- a/.gitignore
++++ b/.gitignore
+@@ -52,3 +52,6 @@ cscope.*
+
+ *.orig
+ *.rej
++
++*.order
++
+diff --git a/Makefile b/Makefile
+index 21bd152..e63ae19 100644
+--- a/Makefile
++++ b/Makefile
+@@ -2,9 +2,9 @@ VERSION = 2
+ PATCHLEVEL = 6
+ SUBLEVEL = 24
+ EXTRAVERSION = .7
+-EXTRAVERSION += $(shell echo ''; \
+- sed -n '/[dr][e][vl]-*[0-9]-*[0-9]-*[0-9]/p' Changelog | \
+- awk 'BEGIN {FS=":"} {last=$$1} END {print last}')
++#EXTRAVERSION += $(shell echo ''; \
++# sed -n '/[dr][e][vl]-*[0-9]-*[0-9]-*[0-9]/p' Changelog | \
++# awk 'BEGIN {FS=":"} {last=$$1} END {print last}')
+ NAME = Err Metey! A Heury Beelge-a Ret!
+
+ # *DOCUMENTATION*
+diff --git a/arch/arm/Makefile b/arch/arm/Makefile
+index d19cd22..4073783 100644
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -76,7 +76,11 @@ tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
+ tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
+ tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+ tune-$(CONFIG_CPU_XSC3) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
++ifeq ($(CONFIG_PLAT_S3C64XX),y)
++tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1176jzf-s,-mtune=strongarm)
++else
+ tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
++endif
+
+ ifeq ($(CONFIG_AEABI),y)
+ CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork
+diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
+index ce1c5ff..1e6d563 100644
+--- a/arch/arm/boot/.gitignore
++++ b/arch/arm/boot/.gitignore
+@@ -3,3 +3,6 @@ zImage
+ xipImage
+ bootpImage
+ uImage
++
++rootfs.*
++
+diff --git a/arch/arm/configs/hhs3c6410_4_3_defconfig b/arch/arm/configs/hhs3c6410_4_3_defconfig
+new file mode 100644
+index 0000000..aa1758a
+--- /dev/null
++++ b/arch/arm/configs/hhs3c6410_4_3_defconfig
+@@ -0,0 +1,1592 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.7
++# Tue Jun 16 10:48:11 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_LOCK_KERNEL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++CONFIG_IKCONFIG=m
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=13
++# CONFIG_CGROUPS is not set
++# CONFIG_FAIR_GROUP_SCHED is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_EMBEDDED=y
++# CONFIG_UID16 is not set
++CONFIG_SYSCTL_SYSCALL=y
++# CONFIG_KALLSYMS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++# CONFIG_BUG is not set
++# CONFIG_ELF_CORE is not set
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++# CONFIG_SHMEM is not set
++# CONFIG_VM_EVENT_COUNTERS is not set
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_TINY_SHMEM=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_AS is not set
++# CONFIG_IOSCHED_DEADLINE is not set
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_AS is not set
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++# CONFIG_S3C64XX_ADC is not set
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++CONFIG_S3C_BOOT_ERROR_RESET=y
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++# CONFIG_MACH_SMDK6430 is not set
++CONFIG_S3C6410_PDFW=m
++CONFIG_S3C6410_PDFW_PROC=y
++CONFIG_S3C6410_KDPMD=m
++CONFIG_CPU_S3C6410=y
++CONFIG_S3C6410_PM=y
++
++#
++# S5PC100 Machines
++#
++# CONFIG_MACH_SMDKC100 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++CONFIG_PREEMPT=y
++CONFIG_NO_IDLE_HZ=y
++CONFIG_HZ=200
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rootwait splash"
++# CONFIG_XIP_KERNEL is not set
++CONFIG_KEXEC=y
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_TABLE=y
++# CONFIG_CPU_FREQ_DEBUG is not set
++CONFIG_CPU_FREQ_STAT=y
++# CONFIG_CPU_FREQ_STAT_DETAILS is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_GOV_USERSPACE=m
++CONFIG_CPU_FREQ_GOV_ONDEMAND=m
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_VFP=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=m
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++CONFIG_APM_EMULATION=m
++
++#
++# DVFS support
++#
++CONFIG_S3C64XX_DVFS=m
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=m
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++CONFIG_INET_LRO=m
++CONFIG_INET_DIAG=m
++CONFIG_INET_TCP_DIAG=m
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IP_VS is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++
++#
++# Core Netfilter Configuration
++#
++# CONFIG_NETFILTER_NETLINK is not set
++# CONFIG_NF_CONNTRACK_ENABLED is not set
++# CONFIG_NF_CONNTRACK is not set
++CONFIG_NETFILTER_XTABLES=m
++# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
++# CONFIG_NETFILTER_XT_TARGET_MARK is not set
++# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
++# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
++# CONFIG_NETFILTER_XT_MATCH_ESP is not set
++# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
++# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_MAC is not set
++# CONFIG_NETFILTER_XT_MATCH_MARK is not set
++# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
++# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
++# CONFIG_NETFILTER_XT_MATCH_REALM is not set
++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
++# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
++# CONFIG_NETFILTER_XT_MATCH_STRING is not set
++# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
++# CONFIG_NETFILTER_XT_MATCH_TIME is not set
++# CONFIG_NETFILTER_XT_MATCH_U32 is not set
++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_IP_NF_QUEUE is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++CONFIG_NET_SCH_FIFO=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++CONFIG_BT=m
++CONFIG_BT_L2CAP=m
++CONFIG_BT_SCO=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++
++#
++# Bluetooth device drivers
++#
++CONFIG_BT_HCIBTUSB=m
++# CONFIG_BT_HCIBTSDIO is not set
++# CONFIG_BT_HCIUART is not set
++# CONFIG_BT_HCIBCM203X is not set
++# CONFIG_BT_HCIBPA10X is not set
++# CONFIG_BT_HCIBFUSB is not set
++# CONFIG_BT_HCIVHCI is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++CONFIG_CFG80211=m
++CONFIG_NL80211=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_MAC80211=m
++CONFIG_MAC80211_RCSIMPLE=y
++CONFIG_MAC80211_LEDS=y
++# CONFIG_MAC80211_DEBUG is not set
++CONFIG_IEEE80211=m
++# CONFIG_IEEE80211_DEBUG is not set
++CONFIG_IEEE80211_CRYPT_WEP=m
++# CONFIG_IEEE80211_CRYPT_CCMP is not set
++# CONFIG_IEEE80211_CRYPT_TKIP is not set
++# CONFIG_IEEE80211_SOFTMAC is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++# CONFIG_SYS_HYPERVISOR is not set
++CONFIG_CONNECTOR=m
++# CONFIG_MTD is not set
++# CONFIG_PARPORT is not set
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=m
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=2
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++CONFIG_SMARTQ5_ENCRYPT=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=m
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=m
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++CONFIG_BLK_DEV_SR=m
++# CONFIG_BLK_DEV_SR_VENDOR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++CONFIG_TUN=m
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=m
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++CONFIG_DM9000=m
++# CONFIG_SMC911X is not set
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_NET_PCI is not set
++# CONFIG_B44 is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++CONFIG_WLAN_80211=y
++# CONFIG_LIBERTAS is not set
++CONFIG_MARVELL_8686_SDIO=m
++CONFIG_MARVELL_8686_PROC_FS=y
++CONFIG_MARVELL_8686_DEBUG=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_RTL8187 is not set
++# CONFIG_P54_COMMON is not set
++# CONFIG_HOSTAP is not set
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_RT2X00 is not set
++
++#
++# USB Network Adapters
++#
++CONFIG_USB_CATC=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_USBNET=m
++CONFIG_USB_NET_AX8817X=m
++CONFIG_USB_NET_CDCETHER=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_NET1080=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_NET_RNDIS_HOST=m
++CONFIG_USB_NET_CDC_SUBSET=m
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_AN2720=y
++CONFIG_USB_BELKIN=y
++CONFIG_USB_ARMLINUX=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++CONFIG_USB_NET_ZAURUS=m
++# CONFIG_WAN is not set
++CONFIG_PPP=m
++# CONFIG_PPP_MULTILINK is not set
++# CONFIG_PPP_FILTER is not set
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_MPPE=m
++# CONFIG_PPPOE is not set
++# CONFIG_PPPOL2TP is not set
++# CONFIG_SLIP is not set
++CONFIG_SLHC=m
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYPAD_S3C=m
++CONFIG_INPUT_MOUSE=y
++# CONFIG_MOUSE_PS2 is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++CONFIG_INPUT_TABLET=y
++# CONFIG_TABLET_USB_ACECAD is not set
++# CONFIG_TABLET_USB_AIPTEK is not set
++# CONFIG_TABLET_USB_GTCO is not set
++# CONFIG_TABLET_USB_KBTAB is not set
++# CONFIG_TABLET_USB_WACOM is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_NEW is not set
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_ATI_REMOTE is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++CONFIG_INPUT_UINPUT=m
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_S3C_MEM=y
++CONFIG_LCD_4=y
++# CONFIG_LCD_7 is not set
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C64XX=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_SENSORS_EEPROM is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++# CONFIG_W1 is not set
++CONFIG_POWER_SUPPLY=m
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++CONFIG_PDA_POWER=m
++CONFIG_APM_POWER=m
++# CONFIG_BATTERY_DS2760 is not set
++CONFIG_HWMON=m
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM75 is not set
++# CONFIG_SENSORS_LM77 is not set
++# CONFIG_SENSORS_LM78 is not set
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++# CONFIG_SENSORS_LM85 is not set
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++CONFIG_VIDEO_OUTPUT_CONTROL=m
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTE480WV is not set
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++# CONFIG_FB_S3C_A070VW04 is not set
++CONFIG_FB_S3C_TD043MTEX=y
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_UVESA is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=m
++CONFIG_BACKLIGHT_CLASS_DEVICE=m
++# CONFIG_BACKLIGHT_CORGI is not set
++CONFIG_BACKLIGHT_SMDK=m
++
++#
++# Display device support
++#
++CONFIG_DISPLAY_SUPPORT=m
++
++#
++# Display hardware drivers
++#
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=m
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++# CONFIG_SND_SEQUENCER is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_VERBOSE_PROCFS is not set
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++# CONFIG_SND_USB_CAIAQ is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC=y
++CONFIG_SND_S3C_SOC=y
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C6410_SOC_I2S_V32=y
++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713 is not set
++# CONFIG_SND_S3C6410_SOC_AC97 is not set
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8987=y
++CONFIG_AUDIO_CODEC_PROCFS=y
++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set
++CONFIG_SND_SOC_WM8987=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=m
++CONFIG_HID_DEBUG=y
++CONFIG_HIDRAW=y
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=m
++# CONFIG_USB_HIDINPUT_POWERBOOK is not set
++# CONFIG_HID_FF is not set
++CONFIG_USB_HIDDEV=y
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_DEVICE_CLASS is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_SUSPEND=y
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=m
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++CONFIG_USB_S3C_OTG_HOST=m
++
++#
++# USB Device Class drivers
++#
++CONFIG_USB_ACM=m
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++CONFIG_USB_STORAGE_FREECOM=y
++CONFIG_USB_STORAGE_ISD200=y
++# CONFIG_USB_STORAGE_DPCM is not set
++CONFIG_USB_STORAGE_USBAT=y
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++
++#
++# USB Serial Converter support
++#
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++# CONFIG_USB_SERIAL_AIRCABLE is not set
++# CONFIG_USB_SERIAL_AIRPRIME is not set
++# CONFIG_USB_SERIAL_ARK3116 is not set
++# CONFIG_USB_SERIAL_BELKIN is not set
++# CONFIG_USB_SERIAL_CH341 is not set
++# CONFIG_USB_SERIAL_WHITEHEAT is not set
++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
++# CONFIG_USB_SERIAL_CP2101 is not set
++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
++# CONFIG_USB_SERIAL_EMPEG is not set
++# CONFIG_USB_SERIAL_FTDI_SIO is not set
++# CONFIG_USB_SERIAL_FUNSOFT is not set
++# CONFIG_USB_SERIAL_VISOR is not set
++# CONFIG_USB_SERIAL_IPAQ is not set
++# CONFIG_USB_SERIAL_IR is not set
++# CONFIG_USB_SERIAL_EDGEPORT is not set
++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
++# CONFIG_USB_SERIAL_GARMIN is not set
++# CONFIG_USB_SERIAL_IPW is not set
++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
++# CONFIG_USB_SERIAL_KEYSPAN is not set
++# CONFIG_USB_SERIAL_KLSI is not set
++# CONFIG_USB_SERIAL_KOBIL_SCT is not set
++# CONFIG_USB_SERIAL_MCT_U232 is not set
++# CONFIG_USB_SERIAL_MOS7720 is not set
++# CONFIG_USB_SERIAL_MOS7840 is not set
++# CONFIG_USB_SERIAL_NAVMAN is not set
++# CONFIG_USB_SERIAL_PL2303 is not set
++# CONFIG_USB_SERIAL_OTI6858 is not set
++# CONFIG_USB_SERIAL_HP4X is not set
++# CONFIG_USB_SERIAL_SAFE is not set
++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
++# CONFIG_USB_SERIAL_TI is not set
++# CONFIG_USB_SERIAL_CYBERJACK is not set
++# CONFIG_USB_SERIAL_XIRCOM is not set
++CONFIG_USB_SERIAL_OPTION=m
++# CONFIG_USB_SERIAL_OMNINET is not set
++# CONFIG_USB_SERIAL_DEBUG is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_JZ4755 is not set
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_PXA2XX is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_S3C_FS is not set
++# CONFIG_USB_GADGET_S3C_HS is not set
++CONFIG_USB_GADGET_S3C_OTGD_HS=y
++CONFIG_USB_S3C=y
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++
++#
++# NOTE: S3C OTG device role enables the controller driver below
++#
++CONFIG_USB_S3C_OTGD_HS=y
++CONFIG_USB_GADGET_S3C_OTGD_HS_DMA_MODE=y
++# CONFIG_USB_GADGET_S3C_OTGD_HS_SLAVE_MODE is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_GADGETFS is not set
++CONFIG_USB_FILE_STORAGE=m
++# CONFIG_USB_FILE_STORAGE_TEST is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_UNSAFE_RESUME=y
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++# CONFIG_MMC_BLOCK_BOUNCE is not set
++CONFIG_SDIO_UART=m
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++CONFIG_USE_MMC_AS_ROOT=y
++CONFIG_HSMMC_S3C_IRQ_WORKAROUND=y
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++# CONFIG_LEDS_S3C24XX is not set
++CONFIG_LEDS_GPIO=m
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# Pulse Width Modulation Timer
++#
++CONFIG_PWM=y
++CONFIG_S3C6410_PWM=y
++
++#
++# File systems
++#
++# CONFIG_EXT2_FS is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++CONFIG_FUSE_FS=m
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=m
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++# CONFIG_MSDOS_FS is not set
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="cp437"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++# CONFIG_TMPFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=m
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_AUFS=y
++
++#
++# These options are for 2.6.24.7
++#
++CONFIG_AUFS_BRANCH_MAX_127=y
++# CONFIG_AUFS_BRANCH_MAX_511 is not set
++# CONFIG_AUFS_BRANCH_MAX_1023 is not set
++# CONFIG_AUFS_BRANCH_MAX_32767 is not set
++CONFIG_AUFS_SYSAUFS=y
++# CONFIG_AUFS_HINOTIFY is not set
++
++#
++# EXPORTFS and AUFS_EXPORT are disabled
++#
++# CONFIG_AUFS_ROBR is not set
++# CONFIG_AUFS_DLGT is not set
++# CONFIG_AUFS_SHWH is not set
++CONFIG_AUFS_RR_SQUASHFS=y
++
++#
++# SECURITY and AUFS_SEC_PERM_PATCH are disabled
++#
++# CONFIG_AUFS_SPLICE_PATCH is not set
++# CONFIG_AUFS_LHASH_PATCH is not set
++
++#
++# NFS_V4 and AUFS_PUT_FILP_PATCH are disabled
++#
++# CONFIG_AUFS_WORKAROUND_FUSE is not set
++# CONFIG_AUFS_DEBUG is not set
++# CONFIG_AUFS_COMPAT is not set
++# CONFIG_AUFS_UNIONFS23_PATCH is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=m
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++# CONFIG_NFS_V4 is not set
++CONFIG_NFS_DIRECTIO=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=m
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=m
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++# CONFIG_NLS_ISO8859_1 is not set
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++# CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_KERNEL is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_SAMPLES is not set
++# CONFIG_DEBUG_USER is not set
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++CONFIG_CRYPTO_ALGAPI=m
++CONFIG_CRYPTO_BLKCIPHER=m
++CONFIG_CRYPTO_MANAGER=m
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++CONFIG_CRYPTO_SHA1=m
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_WP512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_ECB=m
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++# CONFIG_CRYPTO_SERPENT is not set
++CONFIG_CRYPTO_AES=m
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_TEA is not set
++CONFIG_CRYPTO_ARC4=m
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_TEST is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=m
++CONFIG_CRC_CCITT=m
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=m
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=m
++CONFIG_ZLIB_DEFLATE=m
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/configs/hhs3c6410_7_defconfig b/arch/arm/configs/hhs3c6410_7_defconfig
+new file mode 100644
+index 0000000..2d3147a
+--- /dev/null
++++ b/arch/arm/configs/hhs3c6410_7_defconfig
+@@ -0,0 +1,1592 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.24.7
++# Tue Jun 16 10:44:09 2009
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++# CONFIG_GENERIC_TIME is not set
++# CONFIG_GENERIC_CLOCKEVENTS is not set
++CONFIG_MMU=y
++CONFIG_NO_IOPORT=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++# CONFIG_ARCH_HAS_ILOG2_U32 is not set
++# CONFIG_ARCH_HAS_ILOG2_U64 is not set
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ZONE_DMA=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_LOCK_KERNEL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_USER_NS is not set
++# CONFIG_PID_NS is not set
++# CONFIG_AUDIT is not set
++CONFIG_IKCONFIG=m
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=13
++# CONFIG_CGROUPS is not set
++# CONFIG_FAIR_GROUP_SCHED is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_EMBEDDED=y
++# CONFIG_UID16 is not set
++CONFIG_SYSCTL_SYSCALL=y
++# CONFIG_KALLSYMS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++# CONFIG_BUG is not set
++# CONFIG_ELF_CORE is not set
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_ANON_INODES=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_EVENTFD=y
++# CONFIG_SHMEM is not set
++# CONFIG_VM_EVENT_COUNTERS is not set
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_TINY_SHMEM=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++CONFIG_BLOCK=y
++# CONFIG_LBD is not set
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++# CONFIG_IOSCHED_AS is not set
++# CONFIG_IOSCHED_DEADLINE is not set
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_AS is not set
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++
++#
++# System Type
++#
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP23XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_NS9XXX is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++CONFIG_ARCH_S3C2410=y
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++CONFIG_PLAT_S3C64XX=y
++CONFIG_S3C64XX_DMA=y
++# CONFIG_S3C64XX_ADC is not set
++CONFIG_PLAT_S3C=y
++
++#
++# Boot options
++#
++# CONFIG_S3C_BOOT_WATCHDOG is not set
++CONFIG_S3C_BOOT_ERROR_RESET=y
++
++#
++# Power management
++#
++# CONFIG_S3C2410_PM_DEBUG is not set
++# CONFIG_S3C2410_PM_CHECK is not set
++CONFIG_S3C_LOWLEVEL_UART_PORT=0
++CONFIG_MACH_SMDK=y
++
++#
++# S3C2400 Machines
++#
++
++#
++# S3C2410 Machines
++#
++# CONFIG_ARCH_SMDK2410 is not set
++# CONFIG_ARCH_H1940 is not set
++# CONFIG_MACH_N30 is not set
++# CONFIG_ARCH_BAST is not set
++# CONFIG_MACH_OTOM is not set
++# CONFIG_MACH_AML_M5900 is not set
++# CONFIG_MACH_VR1000 is not set
++# CONFIG_MACH_QT2410 is not set
++
++#
++# S3C2412 Machines
++#
++# CONFIG_MACH_SMDK2413 is not set
++# CONFIG_MACH_SMDK2412 is not set
++# CONFIG_MACH_VSTMS is not set
++
++#
++# S3C2440 Machines
++#
++# CONFIG_MACH_ANUBIS is not set
++# CONFIG_MACH_OSIRIS is not set
++# CONFIG_MACH_RX3715 is not set
++# CONFIG_ARCH_S3C2440 is not set
++# CONFIG_MACH_NEXCODER_2440 is not set
++
++#
++# S3C2442 Machines
++#
++
++#
++# S3C2443 Machines
++#
++# CONFIG_MACH_SMDK2443 is not set
++
++#
++# S3C2450 Machines
++#
++# CONFIG_MACH_SMDK2450 is not set
++
++#
++# S3C2416 Machines
++#
++# CONFIG_MACH_SMDK2416 is not set
++
++#
++# S3C6400 Machines
++#
++# CONFIG_MACH_SMDK6400 is not set
++
++#
++# S3C6410 Machines
++#
++CONFIG_MACH_SMDK6410=y
++# CONFIG_MACH_SMDK6430 is not set
++CONFIG_S3C6410_PDFW=m
++CONFIG_S3C6410_PDFW_PROC=y
++CONFIG_S3C6410_KDPMD=m
++CONFIG_CPU_S3C6410=y
++CONFIG_S3C6410_PM=y
++
++#
++# S5PC100 Machines
++#
++# CONFIG_MACH_SMDKC100 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_V6=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v6=y
++CONFIG_CPU_ABRT_EV6=y
++CONFIG_CPU_CACHE_V6=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V6=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++CONFIG_ARM_THUMB=y
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++# CONFIG_OUTER_CACHE is not set
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++# CONFIG_PCI_SYSCALL is not set
++# CONFIG_ARCH_SUPPORTS_MSI is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++# CONFIG_TICK_ONESHOT is not set
++CONFIG_PREEMPT=y
++CONFIG_NO_IDLE_HZ=y
++CONFIG_HZ=200
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_RESOURCES_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_LEDS is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rootwait splash"
++# CONFIG_XIP_KERNEL is not set
++CONFIG_KEXEC=y
++
++#
++# CPU Frequency scaling
++#
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_TABLE=y
++# CONFIG_CPU_FREQ_DEBUG is not set
++CONFIG_CPU_FREQ_STAT=y
++# CONFIG_CPU_FREQ_STAT_DETAILS is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
++CONFIG_CPU_FREQ_GOV_USERSPACE=m
++CONFIG_CPU_FREQ_GOV_ONDEMAND=m
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_VFP=y
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=m
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND_UP_POSSIBLE=y
++CONFIG_SUSPEND=y
++CONFIG_APM_EMULATION=m
++
++#
++# DVFS support
++#
++CONFIG_S3C64XX_DVFS=m
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=m
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++CONFIG_INET_LRO=m
++CONFIG_INET_DIAG=m
++CONFIG_INET_TCP_DIAG=m
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IP_VS is not set
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++
++#
++# Core Netfilter Configuration
++#
++# CONFIG_NETFILTER_NETLINK is not set
++# CONFIG_NF_CONNTRACK_ENABLED is not set
++# CONFIG_NF_CONNTRACK is not set
++CONFIG_NETFILTER_XTABLES=m
++# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
++# CONFIG_NETFILTER_XT_TARGET_MARK is not set
++# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
++# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
++# CONFIG_NETFILTER_XT_MATCH_ESP is not set
++# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
++# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_MAC is not set
++# CONFIG_NETFILTER_XT_MATCH_MARK is not set
++# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
++# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
++# CONFIG_NETFILTER_XT_MATCH_REALM is not set
++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
++# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
++# CONFIG_NETFILTER_XT_MATCH_STRING is not set
++# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
++# CONFIG_NETFILTER_XT_MATCH_TIME is not set
++# CONFIG_NETFILTER_XT_MATCH_U32 is not set
++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_IP_NF_QUEUE is not set
++# CONFIG_IP_NF_IPTABLES is not set
++# CONFIG_IP_NF_ARPTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_NET_SCHED is not set
++CONFIG_NET_SCH_FIFO=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++CONFIG_BT=m
++CONFIG_BT_L2CAP=m
++CONFIG_BT_SCO=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++
++#
++# Bluetooth device drivers
++#
++CONFIG_BT_HCIBTUSB=m
++# CONFIG_BT_HCIBTSDIO is not set
++# CONFIG_BT_HCIUART is not set
++# CONFIG_BT_HCIBCM203X is not set
++# CONFIG_BT_HCIBPA10X is not set
++# CONFIG_BT_HCIBFUSB is not set
++# CONFIG_BT_HCIVHCI is not set
++# CONFIG_AF_RXRPC is not set
++
++#
++# Wireless
++#
++CONFIG_CFG80211=m
++CONFIG_NL80211=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_MAC80211=m
++CONFIG_MAC80211_RCSIMPLE=y
++CONFIG_MAC80211_LEDS=y
++# CONFIG_MAC80211_DEBUG is not set
++CONFIG_IEEE80211=m
++# CONFIG_IEEE80211_DEBUG is not set
++CONFIG_IEEE80211_CRYPT_WEP=m
++# CONFIG_IEEE80211_CRYPT_CCMP is not set
++# CONFIG_IEEE80211_CRYPT_TKIP is not set
++# CONFIG_IEEE80211_SOFTMAC is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++# CONFIG_SYS_HYPERVISOR is not set
++CONFIG_CONNECTOR=m
++# CONFIG_MTD is not set
++# CONFIG_PARPORT is not set
++# CONFIG_PNP is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=m
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=2
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++CONFIG_MISC_DEVICES=y
++CONFIG_SMARTQ5_ENCRYPT=y
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=m
++CONFIG_SCSI_DMA=y
++# CONFIG_SCSI_TGT is not set
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=m
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++CONFIG_BLK_DEV_SR=m
++# CONFIG_BLK_DEV_SR_VENDOR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++CONFIG_NETDEVICES=y
++# CONFIG_NETDEVICES_MULTIQUEUE is not set
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_EQUALIZER is not set
++CONFIG_TUN=m
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++# CONFIG_PHYLIB is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=m
++# CONFIG_AX88796 is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++CONFIG_DM9000=m
++# CONFIG_SMC911X is not set
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_NET_PCI is not set
++# CONFIG_B44 is not set
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++CONFIG_WLAN_80211=y
++# CONFIG_LIBERTAS is not set
++CONFIG_MARVELL_8686_SDIO=m
++CONFIG_MARVELL_8686_PROC_FS=y
++CONFIG_MARVELL_8686_DEBUG=y
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_RTL8187 is not set
++# CONFIG_P54_COMMON is not set
++# CONFIG_HOSTAP is not set
++# CONFIG_B43 is not set
++# CONFIG_B43LEGACY is not set
++# CONFIG_RT2X00 is not set
++
++#
++# USB Network Adapters
++#
++CONFIG_USB_CATC=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_USBNET=m
++CONFIG_USB_NET_AX8817X=m
++CONFIG_USB_NET_CDCETHER=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_NET1080=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_NET_RNDIS_HOST=m
++CONFIG_USB_NET_CDC_SUBSET=m
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_AN2720=y
++CONFIG_USB_BELKIN=y
++CONFIG_USB_ARMLINUX=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++CONFIG_USB_NET_ZAURUS=m
++# CONFIG_WAN is not set
++CONFIG_PPP=m
++# CONFIG_PPP_MULTILINK is not set
++# CONFIG_PPP_FILTER is not set
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_MPPE=m
++# CONFIG_PPPOE is not set
++# CONFIG_PPPOL2TP is not set
++# CONFIG_SLIP is not set
++CONFIG_SLHC=m
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYPAD_S3C=m
++CONFIG_INPUT_MOUSE=y
++# CONFIG_MOUSE_PS2 is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_INPORT is not set
++# CONFIG_MOUSE_LOGIBM is not set
++# CONFIG_MOUSE_PC110PAD is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_INPUT_JOYSTICK is not set
++CONFIG_INPUT_TABLET=y
++# CONFIG_TABLET_USB_ACECAD is not set
++# CONFIG_TABLET_USB_AIPTEK is not set
++# CONFIG_TABLET_USB_GTCO is not set
++# CONFIG_TABLET_USB_KBTAB is not set
++# CONFIG_TABLET_USB_WACOM is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_S3C=y
++# CONFIG_TOUCHSCREEN_NEW is not set
++# CONFIG_TOUCHSCREEN_FUJITSU is not set
++# CONFIG_TOUCHSCREEN_GUNZE is not set
++# CONFIG_TOUCHSCREEN_ELO is not set
++# CONFIG_TOUCHSCREEN_MTOUCH is not set
++# CONFIG_TOUCHSCREEN_MK712 is not set
++# CONFIG_TOUCHSCREEN_PENMOUNT is not set
++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
++# CONFIG_TOUCHSCREEN_UCB1400 is not set
++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_ATI_REMOTE is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++CONFIG_INPUT_UINPUT=m
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_S3C2410 is not set
++CONFIG_SERIAL_S3C6400=y
++CONFIG_SERIAL_S3C64XX_CONSOLE=y
++# CONFIG_SERIAL_S3C64XX_HS_UART is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_HW_RANDOM is not set
++# CONFIG_NVRAM is not set
++# CONFIG_S3C_ADC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_S3C_MEM=y
++# CONFIG_LCD_4 is not set
++CONFIG_LCD_7=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ELEKTOR is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++CONFIG_I2C_S3C64XX=y
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_TINY_USB is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_SENSORS_EEPROM is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++# CONFIG_W1 is not set
++CONFIG_POWER_SUPPLY=m
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++CONFIG_PDA_POWER=m
++CONFIG_APM_POWER=m
++# CONFIG_BATTERY_DS2760 is not set
++CONFIG_HWMON=m
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM75 is not set
++# CONFIG_SENSORS_LM77 is not set
++# CONFIG_SENSORS_LM78 is not set
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++# CONFIG_SENSORS_LM85 is not set
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_S3C2410_WATCHDOG=y
++
++#
++# ISA-based Watchdog Cards
++#
++# CONFIG_PCWATCHDOG is not set
++# CONFIG_MIXCOMWD is not set
++# CONFIG_WDT is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_SM501 is not set
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_DVB_CORE is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGASTATE is not set
++CONFIG_VIDEO_OUTPUT_CONTROL=m
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_S3C=y
++# CONFIG_FB_S3C_LTE480WV is not set
++# CONFIG_FB_S3C_LTV350QV is not set
++# CONFIG_FB_S3C_LTS222QV is not set
++CONFIG_FB_S3C_A070VW04=y
++# CONFIG_FB_S3C_TD043MTEX is not set
++CONFIG_FB_S3C_BPP=y
++# CONFIG_FB_S3C_BPP_8 is not set
++CONFIG_FB_S3C_BPP_16=y
++# CONFIG_FB_S3C_BPP_24 is not set
++# CONFIG_FB_S3C_BPP_32 is not set
++CONFIG_FB_S3C_NUM=1
++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
++# CONFIG_FB_UVESA is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_S3C2410 is not set
++# CONFIG_FB_VIRTUAL is not set
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=m
++CONFIG_BACKLIGHT_CLASS_DEVICE=m
++# CONFIG_BACKLIGHT_CORGI is not set
++CONFIG_BACKLIGHT_SMDK=m
++
++#
++# Display device support
++#
++CONFIG_DISPLAY_SUPPORT=m
++
++#
++# Display hardware drivers
++#
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=m
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++# CONFIG_LOGO_LINUX_CLUT224 is not set
++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++# CONFIG_SND_SEQUENCER is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++# CONFIG_SND_DYNAMIC_MINORS is not set
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_VERBOSE_PROCFS is not set
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++
++#
++# Generic devices
++#
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++
++#
++# ALSA ARM devices
++#
++
++#
++# USB devices
++#
++# CONFIG_SND_USB_AUDIO is not set
++# CONFIG_SND_USB_CAIAQ is not set
++
++#
++# System on Chip audio support
++#
++CONFIG_SND_SOC=y
++CONFIG_SND_S3C_SOC=y
++
++#
++# SoC Audio for the Samsung S3C
++#
++CONFIG_SND_S3C6410_SOC_I2S_V32=y
++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713 is not set
++# CONFIG_SND_S3C6410_SOC_AC97 is not set
++# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8987=y
++CONFIG_AUDIO_CODEC_PROCFS=y
++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set
++CONFIG_SND_SOC_WM8987=y
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=m
++CONFIG_HID_DEBUG=y
++CONFIG_HIDRAW=y
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=m
++# CONFIG_USB_HIDINPUT_POWERBOOK is not set
++# CONFIG_HID_FF is not set
++CONFIG_USB_HIDDEV=y
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB_ARCH_HAS_EHCI is not set
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_DEVICE_CLASS is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_SUSPEND=y
++# CONFIG_USB_PERSIST is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=m
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++CONFIG_USB_S3C_OTG_HOST=m
++
++#
++# USB Device Class drivers
++#
++CONFIG_USB_ACM=m
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=m
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++CONFIG_USB_STORAGE_FREECOM=y
++CONFIG_USB_STORAGE_ISD200=y
++# CONFIG_USB_STORAGE_DPCM is not set
++CONFIG_USB_STORAGE_USBAT=y
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++CONFIG_USB_MON=y
++
++#
++# USB port drivers
++#
++
++#
++# USB Serial Converter support
++#
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++# CONFIG_USB_SERIAL_AIRCABLE is not set
++# CONFIG_USB_SERIAL_AIRPRIME is not set
++# CONFIG_USB_SERIAL_ARK3116 is not set
++# CONFIG_USB_SERIAL_BELKIN is not set
++# CONFIG_USB_SERIAL_CH341 is not set
++# CONFIG_USB_SERIAL_WHITEHEAT is not set
++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
++# CONFIG_USB_SERIAL_CP2101 is not set
++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
++# CONFIG_USB_SERIAL_EMPEG is not set
++# CONFIG_USB_SERIAL_FTDI_SIO is not set
++# CONFIG_USB_SERIAL_FUNSOFT is not set
++# CONFIG_USB_SERIAL_VISOR is not set
++# CONFIG_USB_SERIAL_IPAQ is not set
++# CONFIG_USB_SERIAL_IR is not set
++# CONFIG_USB_SERIAL_EDGEPORT is not set
++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
++# CONFIG_USB_SERIAL_GARMIN is not set
++# CONFIG_USB_SERIAL_IPW is not set
++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
++# CONFIG_USB_SERIAL_KEYSPAN is not set
++# CONFIG_USB_SERIAL_KLSI is not set
++# CONFIG_USB_SERIAL_KOBIL_SCT is not set
++# CONFIG_USB_SERIAL_MCT_U232 is not set
++# CONFIG_USB_SERIAL_MOS7720 is not set
++# CONFIG_USB_SERIAL_MOS7840 is not set
++# CONFIG_USB_SERIAL_NAVMAN is not set
++# CONFIG_USB_SERIAL_PL2303 is not set
++# CONFIG_USB_SERIAL_OTI6858 is not set
++# CONFIG_USB_SERIAL_HP4X is not set
++# CONFIG_USB_SERIAL_SAFE is not set
++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
++# CONFIG_USB_SERIAL_TI is not set
++# CONFIG_USB_SERIAL_CYBERJACK is not set
++# CONFIG_USB_SERIAL_XIRCOM is not set
++CONFIG_USB_SERIAL_OPTION=m
++# CONFIG_USB_SERIAL_OMNINET is not set
++# CONFIG_USB_SERIAL_DEBUG is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_JZ4755 is not set
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_BERRY_CHARGE is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGET is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++CONFIG_USB_GADGET_SELECTED=y
++# CONFIG_USB_GADGET_AMD5536UDC is not set
++# CONFIG_USB_GADGET_ATMEL_USBA is not set
++# CONFIG_USB_GADGET_FSL_USB2 is not set
++# CONFIG_USB_GADGET_NET2280 is not set
++# CONFIG_USB_GADGET_PXA2XX is not set
++# CONFIG_USB_GADGET_M66592 is not set
++# CONFIG_USB_GADGET_GOKU is not set
++# CONFIG_USB_GADGET_LH7A40X is not set
++# CONFIG_USB_GADGET_OMAP is not set
++# CONFIG_USB_GADGET_S3C_FS is not set
++# CONFIG_USB_GADGET_S3C_HS is not set
++CONFIG_USB_GADGET_S3C_OTGD_HS=y
++CONFIG_USB_S3C=y
++# CONFIG_USB_GADGET_S3C2410 is not set
++# CONFIG_USB_GADGET_AT91 is not set
++# CONFIG_USB_GADGET_DUMMY_HCD is not set
++
++#
++# NOTE: S3C OTG device role enables the controller driver below
++#
++CONFIG_USB_S3C_OTGD_HS=m
++CONFIG_USB_GADGET_S3C_OTGD_HS_DMA_MODE=y
++# CONFIG_USB_GADGET_S3C_OTGD_HS_SLAVE_MODE is not set
++CONFIG_USB_GADGET_DUALSPEED=y
++# CONFIG_USB_ZERO is not set
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_RNDIS=y
++# CONFIG_USB_GADGETFS is not set
++CONFIG_USB_FILE_STORAGE=m
++# CONFIG_USB_FILE_STORAGE_TEST is not set
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_UNSAFE_RESUME=y
++
++#
++# MMC/SD Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++# CONFIG_MMC_BLOCK_BOUNCE is not set
++CONFIG_SDIO_UART=m
++
++#
++# MMC/SD Host Controller Drivers
++#
++CONFIG_HSMMC_S3C=y
++CONFIG_USE_MMC_AS_ROOT=y
++CONFIG_HSMMC_S3C_IRQ_WORKAROUND=y
++CONFIG_HSMMC_SCATTERGATHER=y
++# CONFIG_S3CMMC_DEBUG is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=m
++
++#
++# LED drivers
++#
++# CONFIG_LEDS_S3C24XX is not set
++CONFIG_LEDS_GPIO=m
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++
++#
++# SPI RTC drivers
++#
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++
++#
++# on-CPU RTC drivers
++#
++CONFIG_RTC_DRV_S3C=y
++
++#
++# Pulse Width Modulation Timer
++#
++CONFIG_PWM=y
++CONFIG_S3C6410_PWM=y
++
++#
++# File systems
++#
++# CONFIG_EXT2_FS is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
++CONFIG_JBD=y
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++CONFIG_FUSE_FS=m
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=m
++# CONFIG_JOLIET is not set
++# CONFIG_ZISOFS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++# CONFIG_MSDOS_FS is not set
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="cp437"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_SYSFS=y
++# CONFIG_TMPFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=m
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_AUFS=y
++
++#
++# These options are for 2.6.24.7
++#
++CONFIG_AUFS_BRANCH_MAX_127=y
++# CONFIG_AUFS_BRANCH_MAX_511 is not set
++# CONFIG_AUFS_BRANCH_MAX_1023 is not set
++# CONFIG_AUFS_BRANCH_MAX_32767 is not set
++CONFIG_AUFS_SYSAUFS=y
++# CONFIG_AUFS_HINOTIFY is not set
++
++#
++# EXPORTFS and AUFS_EXPORT are disabled
++#
++# CONFIG_AUFS_ROBR is not set
++# CONFIG_AUFS_DLGT is not set
++# CONFIG_AUFS_SHWH is not set
++CONFIG_AUFS_RR_SQUASHFS=y
++
++#
++# SECURITY and AUFS_SEC_PERM_PATCH are disabled
++#
++# CONFIG_AUFS_SPLICE_PATCH is not set
++# CONFIG_AUFS_LHASH_PATCH is not set
++
++#
++# NFS_V4 and AUFS_PUT_FILP_PATCH are disabled
++#
++# CONFIG_AUFS_WORKAROUND_FUSE is not set
++# CONFIG_AUFS_DEBUG is not set
++# CONFIG_AUFS_COMPAT is not set
++# CONFIG_AUFS_UNIONFS23_PATCH is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=m
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++# CONFIG_NFS_V4 is not set
++CONFIG_NFS_DIRECTIO=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=m
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=m
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++# CONFIG_NLS_ISO8859_1 is not set
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++CONFIG_INSTRUMENTATION=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_ENABLE_WARN_DEPRECATED=y
++CONFIG_ENABLE_MUST_CHECK=y
++# CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++# CONFIG_DEBUG_FS is not set
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_KERNEL is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_SAMPLES is not set
++# CONFIG_DEBUG_USER is not set
++CONFIG_DEBUG_S3C_UART=0
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++CONFIG_CRYPTO_ALGAPI=m
++CONFIG_CRYPTO_BLKCIPHER=m
++CONFIG_CRYPTO_MANAGER=m
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++CONFIG_CRYPTO_SHA1=m
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_WP512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_GF128MUL is not set
++CONFIG_CRYPTO_ECB=m
++# CONFIG_CRYPTO_CBC is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++# CONFIG_CRYPTO_SERPENT is not set
++CONFIG_CRYPTO_AES=m
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_TEA is not set
++CONFIG_CRYPTO_ARC4=m
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_TEST is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++CONFIG_CRYPTO_HW=y
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=m
++CONFIG_CRC_CCITT=m
++# CONFIG_CRC16 is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=m
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=m
++CONFIG_ZLIB_DEFLATE=m
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_DMA=y
+diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile
+index 8319eb1..9aa12da 100644
+--- a/arch/arm/mach-s3c6400/Makefile
++++ b/arch/arm/mach-s3c6400/Makefile
+@@ -5,7 +5,7 @@
+
+ # Object file lists.
+ obj-y :=
+-led-y := leds.o
++led-y :=
+ obj-n :=
+ obj- :=
+
+@@ -20,6 +20,6 @@ obj-$(CONFIG_S3C6400_PM) += pm.o
+ obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
+
+ # LEDs support
+-led-$(CONFIG_MACH_SMDK6400) += leds-s3c6400.o
++led-$(CONFIG_MACH_SMDK6400) += leds.o leds-s3c6400.o
+ obj-$(CONFIG_LEDS) += $(led-y)
+
+diff --git a/arch/arm/mach-s3c6400/leds-s3c6400.c b/arch/arm/mach-s3c6400/leds-s3c6400.c
+index 96e7774..4baa7e2 100644
+--- a/arch/arm/mach-s3c6400/leds-s3c6400.c
++++ b/arch/arm/mach-s3c6400/leds-s3c6400.c
+@@ -19,7 +19,7 @@
+ #include <asm/system.h>
+ #include <asm/mach-types.h>
+
+-#include <asm/arch/regs-gpio.h>
++#include <asm/arch/gpio.h>
+
+ #include "leds.h"
+
+diff --git a/arch/arm/mach-s3c6400/leds.c b/arch/arm/mach-s3c6400/leds.c
+index 557bd42..33fe606 100644
+--- a/arch/arm/mach-s3c6400/leds.c
++++ b/arch/arm/mach-s3c6400/leds.c
+@@ -22,12 +22,12 @@
+ #include <asm/leds.h>
+ #include <asm/mach-types.h>
+
+-#include <asm/arch/regs-gpio.h>
++#include <asm/arch/gpio.h>
+ #include <asm/arch/irqs.h>
+ #include <asm/mach/irq.h>
+ #include "leds.h"
+
+-static irqreturn_t eint9_switch(int irq, void *dev_id, struct pt_regs *regs)
++static irqreturn_t eint9_switch(int irq, void *dev_id)
+ {
+
+ printk("EINT9 interrupt occures!!!\n");
+@@ -47,25 +47,25 @@ s3c6400_leds_init(void)
+ {
+ /*GPN12~15 used for LED*/
+ /*Set GPN12~15 to output mode */
+- gpio_direction_output(S3C_GPN12);
++ gpio_direction_output(S3C_GPN12, 1);
+ if (gpio_get_pin(S3C_GPN12) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN12 output mode\n");
+ }
+
+- gpio_direction_output(S3C_GPN13);
++ gpio_direction_output(S3C_GPN13, 1);
+ if (gpio_get_pin(S3C_GPN13) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN13 output mode\n");
+ }
+
+- gpio_direction_output(S3C_GPN14);
++ gpio_direction_output(S3C_GPN14, 1);
+ if (gpio_get_pin(S3C_GPN14) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN14 output mode\n");
+ }
+
+- gpio_direction_output(S3C_GPN15);
++ gpio_direction_output(S3C_GPN15, 1);
+ if (gpio_get_pin(S3C_GPN15) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN15 output mode\n");
+diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c6400/mach-smdk6400.c
+index 6284fd7..e76a10d 100644
+--- a/arch/arm/mach-s3c6400/mach-smdk6400.c
++++ b/arch/arm/mach-s3c6400/mach-smdk6400.c
+@@ -65,14 +65,6 @@
+ #include <asm/plat-s3c24xx/common-smdk.h>
+ #include <asm/arch-s3c2410/reserved_mem.h>
+
+-#if defined(CONFIG_RTC_DRV_S3C)
+-#include <asm/plat-s3c/regs-rtc.h>
+-#endif
+-
+-#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS) || defined(CONFIG_USB_OHCI_HCD)
+-#include <asm/arch-s3c2410/regs-usb-otg-hs.h>
+-#endif
+-
+ #include <asm/plat-s3c/regs-adc.h>
+ #include <asm/plat-s3c/ts.h>
+
+@@ -146,6 +138,46 @@ static struct s3c2410_uartcfg smdk6400_uartcfgs[] = {
+
+ };
+
++static struct resource s3c64xx_i2c0_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_IIC0,
++ .end = S3C6400_PA_IIC0 + S3C24XX_SZ_IIC - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_IIC0,
++ .end = IRQ_IIC0,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device s3c64xx_device_i2c0 = {
++ .name = "s3c64xx-i2c",
++ .id = 0, /* This is so the driver gets forced to use bus 0. */
++ .num_resources = ARRAY_SIZE(s3c64xx_i2c0_resource),
++ .resource = s3c64xx_i2c0_resource,
++};
++
++static struct resource s3c64xx_i2c1_resource[] = {
++ [0] = {
++ .start = S3C6400_PA_IIC1,
++ .end = S3C6400_PA_IIC1 + S3C24XX_SZ_IIC - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_IIC1,
++ .end = IRQ_IIC1,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device s3c64xx_device_i2c1 = {
++ .name = "s3c64xx-i2c",
++ .id = 1, /* This is so the driver gets forced to use bus 0. */
++ .num_resources = ARRAY_SIZE(s3c64xx_i2c1_resource),
++ .resource = s3c64xx_i2c1_resource,
++};
++
+
+
+ /*add devices as drivers are integrated*/
+@@ -155,7 +187,8 @@ static struct platform_device *smdk6400_devices[] __initdata = {
+ &s3c_device_iis,
+ &s3c_device_adc,
+ &s3c_device_ts,
+- &s3c_device_i2c,
++ &s3c64xx_device_i2c0,
++ //&s3c64xx_device_i2c1,
+ &s3c_device_usb,
+ &s3c_device_usbgadget,
+ &s3c_device_usb_otghcd,
+@@ -467,7 +500,9 @@ struct s3c_hsmmc_cfg s3c_hsmmc2_platform = {
+ },
+ };
+
+-#if defined(CONFIG_RTC_DRV_S3C)
++#if defined(CONFIG_RTC_DRV_S3C) || defined(CONFIG_RTC_DRV_S3C_MODULE)
++#include <asm/plat-s3c/regs-rtc.h>
++
+ /* rtc function */
+ unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val)
+ {
+@@ -475,11 +510,13 @@ unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val)
+
+ return 0;
+ }
++EXPORT_SYMBOL(s3c_rtc_set_bit_byte);
+
+ unsigned int s3c_rtc_read_alarm_status(void __iomem *base)
+ {
+ return 1;
+ }
++EXPORT_SYMBOL(s3c_rtc_read_alarm_status);
+
+ void s3c_rtc_set_pie(void __iomem *base, uint to)
+ {
+@@ -493,6 +530,7 @@ void s3c_rtc_set_pie(void __iomem *base, uint to)
+ writew(tmp, base + S3C2410_RTCCON);
+
+ }
++EXPORT_SYMBOL(s3c_rtc_set_pie);
+
+ void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint *s3c_freq)
+ {
+@@ -504,6 +542,7 @@ void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint *s3c_freq)
+ tmp = (32768 / freq)-1;
+ writew(tmp, base + S3C2410_TICNT);
+ }
++EXPORT_SYMBOL(s3c_rtc_set_freq_regs);
+
+ void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en)
+ {
+@@ -536,9 +575,13 @@ void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en)
+ }
+ }
+ }
++EXPORT_SYMBOL(s3c_rtc_enable_set);
+ #endif
+
+-#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS) || defined(CONFIG_USB_OHCI_HCD)
++#if defined(CONFIG_USB_GADGET_S3C_OTGD_HS) || \
++ defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
++#include <asm/arch-s3c2410/regs-usb-otg-hs.h>
++
+ /* Initializes OTG Phy. */
+ void otg_phy_init(u32 otg_phy_clk) {
+
+@@ -561,7 +604,7 @@ void otg_phy_off(void) {
+ }
+ #endif
+
+-#ifdef CONFIG_USB_OHCI_HCD
++#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+ void usb_host_clk_en(int usb_host_clksrc, u32 otg_phy_clk) {
+ switch (usb_host_clksrc) {
+ case 0: /* epll clk */
+@@ -591,6 +634,7 @@ void usb_host_clk_en(int usb_host_clksrc, u32 otg_phy_clk) {
+ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_UHOST, S3C_SCLK_GATE);
+
+ }
++EXPORT_SYMBOL(usb_host_clk_en);
+ #endif
+
+ /* smdk6410 adc common function */
+diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
+index 7e65ecb..287c6a6 100644
+--- a/arch/arm/mach-s3c6410/Makefile
++++ b/arch/arm/mach-s3c6410/Makefile
+@@ -5,7 +5,7 @@
+
+ # Object file lists.
+ obj-y :=
+-led-y := leds.o
++led-y :=
+ obj-n :=
+ obj- :=
+
+@@ -20,7 +20,7 @@ obj-$(CONFIG_S3C6410_PM) += pm.o
+ # Power Management support
+
+ # LEDs support
+-led-$(CONFIG_MACH_SMDK6410) += leds-s3c6410.o
++led-$(CONFIG_MACH_SMDK6410) += leds.o leds-s3c6410.o
+ obj-$(CONFIG_LEDS) += $(led-y)
+
+ # PWM Support
+diff --git a/arch/arm/mach-s3c6410/clock.c b/arch/arm/mach-s3c6410/clock.c
+index 235c07a..1268a73 100644
+--- a/arch/arm/mach-s3c6410/clock.c
++++ b/arch/arm/mach-s3c6410/clock.c
+@@ -56,7 +56,7 @@
+ #include <asm/arch/regs-usb-otg-hs.h>
+ #endif
+
+-#define HCLK_GATING_ON_LIST S3C_CLKCON_HCLK_BUS | S3C_CLKCON_HCLK_DDR1 | S3C_CLKCON_HCLK_DDR0 |\
++#define HCLK_GATING_ON_LIST /*S3C_CLKCON_HCLK_BUS |*/ S3C_CLKCON_HCLK_DDR1 | S3C_CLKCON_HCLK_DDR0 |\
+ S3C_CLKCON_HCLK_MEM1 | S3C_CLKCON_HCLK_MEM0 | S3C_CLKCON_HCLK_DMA0 |\
+ S3C_CLKCON_HCLK_DMA1 | S3C_CLKCON_HCLK_INTC | S3C_CLKCON_HCLK_LCD |\
+ S3C_CLKCON_HCLK_DHOST | S3C_CLKCON_HCLK_POST0 | S3C_CLKCON_HCLK_MFC
+@@ -349,7 +349,7 @@ static unsigned long s3c6410_getrate_DOUTmpll_hsmmc_clk(struct clk *clk)
+ {
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long div = readl(S3C_CLK_DIV1);
+- div &= ~S3C_CLKDIV1_HSMMCDIV_MASK;
++ div &= ~S3C_CLKDIV1_HSMMCDIV0_MASK;
+
+ /* MMC_RATIO = 2+1 */
+ div |= 0x2;
+@@ -373,6 +373,22 @@ static unsigned long s3c6410_getrate_DOUTmpll_hsmmc1_clk(struct clk *clk)
+ return parent_rate / (0x2 + 1);
+ }
+
++static unsigned long s3c6410_getrate_DOUTmpll_hsmmc2_clk(struct clk *clk)
++{
++ unsigned long parent_rate = clk_get_rate(clk->parent);
++ unsigned long div = readl(S3C_CLK_DIV1);
++ div &= ~S3C_CLKDIV1_HSMMCDIV2_MASK;
++
++ /* MMC1_RATIO = 2+1 */
++ div |= (0x2<<S3C_CLKDIV1_HSMMCDIV2_SHIFT);
++
++ writel(div, S3C_CLK_DIV1);
++
++ return parent_rate / (0x2 + 1);
++}
++
++
++
+ static struct clk clk_hsmmc_DOUTmpll_mmc0 = {
+ .name = "sclk_DOUTmpll_mmc0",
+ .id = -1,
+@@ -399,7 +415,7 @@ static struct clk clk_hsmmc_DOUTmpll_mmc2 = {
+ .parent = &clk_mpll_dout,
+ .enable = s3c6410_clkcon_enable_s,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC2,
+- .get_rate = s3c6410_getrate_DOUTmpll_hsmmc_clk,
++ .get_rate = s3c6410_getrate_DOUTmpll_hsmmc2_clk,
+ .usage = 0,
+ };
+
+diff --git a/arch/arm/mach-s3c6410/leds-s3c6410.c b/arch/arm/mach-s3c6410/leds-s3c6410.c
+index bc1347f..ce7e54d 100644
+--- a/arch/arm/mach-s3c6410/leds-s3c6410.c
++++ b/arch/arm/mach-s3c6410/leds-s3c6410.c
+@@ -19,7 +19,7 @@
+ #include <asm/system.h>
+ #include <asm/mach-types.h>
+
+-#include <asm/arch/regs-gpio.h>
++#include <asm/arch/gpio.h>
+
+ #include "leds.h"
+
+diff --git a/arch/arm/mach-s3c6410/leds.c b/arch/arm/mach-s3c6410/leds.c
+index 8113540..07435b9 100644
+--- a/arch/arm/mach-s3c6410/leds.c
++++ b/arch/arm/mach-s3c6410/leds.c
+@@ -22,12 +22,12 @@
+ #include <asm/leds.h>
+ #include <asm/mach-types.h>
+
+-#include <asm/arch/regs-gpio.h>
++#include <asm/arch/gpio.h>
+ #include <asm/arch/irqs.h>
+ #include <asm/mach/irq.h>
+ #include "leds.h"
+
+-static irqreturn_t eint9_switch(int irq, void *dev_id, struct pt_regs *regs)
++static irqreturn_t eint9_switch(int irq, void *dev_id)
+ {
+
+ printk("EINT9 interrupt occures!!!\n");
+@@ -47,25 +47,25 @@ s3c6410_leds_init(void)
+ {
+ /*GPN12~15 used for LED*/
+ /*Set GPN12~15 to output mode */
+- gpio_direction_output(S3C_GPN12);
++ gpio_direction_output(S3C_GPN12, 1);
+ if(gpio_get_pin(S3C_GPN12) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN12 output mode\n");
+ }
+
+- gpio_direction_output(S3C_GPN13);
++ gpio_direction_output(S3C_GPN13, 1);
+ if(gpio_get_pin(S3C_GPN13) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN13 output mode\n");
+ }
+
+- gpio_direction_output(S3C_GPN14);
++ gpio_direction_output(S3C_GPN14, 1);
+ if(gpio_get_pin(S3C_GPN14) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN14 output mode\n");
+ }
+
+- gpio_direction_output(S3C_GPN15);
++ gpio_direction_output(S3C_GPN15, 1);
+ if(gpio_get_pin(S3C_GPN15) == 0)
+ {
+ printk(KERN_WARNING "LED: can't set GPN15 output mode\n");
+diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
+index ec86f3e..74dadd1 100644
+--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
++++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
+@@ -80,6 +80,10 @@
+
+ #include <asm/plat-s3c/regs-adc.h>
+ #include <asm/plat-s3c/ts.h>
++#include <linux/gpio_keys.h> //HHTECH wk
++#include <linux/input.h> //HHTECH wk
++#include <linux/reboot.h>
++#include <asm/plat-s3c64xx/hhtech_gpio.h>
+
+ extern struct sys_timer s3c_timer;
+
+@@ -264,6 +268,138 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
+ { I2C_BOARD_INFO("24c128", 0x57), },
+ };
+
++#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
++static struct resource dm9000_resources[] = {
++ [0] = {
++ .start = S3C24XX_VA_CS8900 + 0x300,
++ .end = S3C24XX_VA_CS8900 + S3C24XX_SZ_CS8900 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_EINT10,
++ .end = IRQ_EINT10,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device s3c_device_dm9000 = {
++ .name = "dm9000",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(dm9000_resources),
++ .resource = dm9000_resources,
++};
++#endif
++/////////////////////////////////////////////////////HHTECH wk////////////////
++/*
++ * GPIO Buttons
++ */
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++//static struct gpio_keys_button hhmid_buttons[] __initdata = {
++static struct gpio_keys_button hhmid_buttons[] = {
++#if defined (CONFIG_LCD_4)
++ {
++ .gpio = S3C_GPN2, //32*16 + 2
++ .code = KEY_PAGEDOWN,
++ .desc = "Button 0",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++ {
++ .gpio = S3C_GPN12,
++ .code = KEY_PAGEUP,
++ .desc = "Button 3",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++ {
++ .gpio = S3C_GPN15,
++ .code = KEY_LEFTALT,
++ .desc = "Button 4",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++#else
++ {
++ .gpio = S3C_GPN4,
++ .code = KEY_PAGEUP,
++ .desc = "Button 0",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++ {
++ .gpio = S3C_GPN3,
++ .code = KEY_PAGEDOWN,
++ .desc = "Button 1",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++ {
++ .gpio = S3C_GPN2, //32*16 + 2
++ .code = KEY_LEFTALT,
++ .desc = "Button 2",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++ {
++ .gpio = S3C_GPN15,
++ .code = KEY_ENTER,
++ .desc = "Button 3",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++ {
++ .gpio = S3C_GPN12,
++ .code = KEY_ESC,
++ .desc = "Button 4",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++#endif
++};
++
++//static struct gpio_keys_platform_data hhmid_button_data __initdata = {
++static struct gpio_keys_platform_data hhmid_button_data = {
++ .buttons = hhmid_buttons,
++ .nbuttons = ARRAY_SIZE(hhmid_buttons),
++};
++
++static struct platform_device hhmid_button_device = {
++ .name = "gpio-keys",
++ .id = 0,
++ .num_resources = 0,
++ .dev = {
++ .platform_data = &hhmid_button_data,
++ }
++};
++
++//*************************************************************************************
++static struct gpio_keys_button hhmid_buttons_2[] = {
++ {
++ .gpio = S3C_GPL14,
++ .code = KEY_POWER,
++ .desc = "Button 5",
++ .active_low = 1,
++ .debounce_interval = 5,
++ },
++
++};
++static struct gpio_keys_platform_data hhmid_button_data_2 = {
++ .buttons = hhmid_buttons_2,
++ .nbuttons = ARRAY_SIZE(hhmid_buttons_2),
++ .rep = 1,
++};
++
++static struct platform_device hhmid_button_device_2 = {
++ .name = "gpio-keys",
++ .id = 1,
++ .num_resources = 0,
++ .dev = {
++ .platform_data = &hhmid_button_data_2,
++ }
++};
++#endif
++/* HHTECH wk */
++
+ /* Add devices as drivers are integrated */
+ static struct platform_device *smdk6410_devices[] __initdata = {
+ &s3c_device_rtc,
+@@ -273,13 +409,16 @@ static struct platform_device *smdk6410_devices[] __initdata = {
+ &s3c_device_adc,
+ &s3c64xx_device_i2c0,
+ &s3c64xx_device_i2c1,
++ &hhmid_button_device,
++ &hhmid_button_device_2,
++ &s3c_gpio,
+ &s3c_device_usb,
+ &s3c_device_usbgadget,
+ &s3c_device_usb_otghcd,
+ &s3c_device_tvenc,
+ &s3c_device_tvscaler,
++ &s3c_device_hsmmc1, /* INAND initialize before SD card */
+ &s3c_device_hsmmc0,
+- &s3c_device_hsmmc1,
+ &s3c_device_hsmmc2,
+ &s3c_device_wdt,
+ &s3c_device_jpeg,
+@@ -294,11 +433,33 @@ static struct platform_device *smdk6410_devices[] __initdata = {
+ &s3c_device_mfc,
+ &s3c_device_g3d,
+ &s3c_device_rotator,
++#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
++ &s3c_device_dm9000,
++#endif
+ };
+
++extern void s3cfb_clear_lcd(int flag);
++
++static void s3c6410_power_off(void)
++{
++ int dc_status = 0;
++#if defined (CONFIG_LCD_4)
++ dc_status = gpio_get_value(GPIO_DC_DETE);
++#else
++ dc_status = !gpio_get_value(GPIO_DC_DETE);
++#endif
++
++ if(dc_status)
++ machine_restart(NULL);
++ else {
++ s3cfb_clear_lcd(0); // clear the LCD screen to white
++ gpio_direction_output(S3C_GPK15, 1);
++ }
++}
+
+ static void __init smdk6410_map_io(void)
+ {
++ pm_power_off = s3c6410_power_off;
+ s3c24xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
+ s3c24xx_init_clocks(0);
+ s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+@@ -366,14 +527,16 @@ static void __init smdk6410_fixup (struct machine_desc *desc, struct tag *tags,
+ static void smdk6410_hsmmc_init (void)
+ {
+ /* hsmmc data strength */
+- writel(readl(S3C_SPCON) | (0x3 << 26), S3C_SPCON);
++ writel(readl(S3C_SPCON) | (0x3 << 26) | (0x3 << 18), S3C_SPCON);
+
+ /* jsgood: hsmmc0/1 card detect pin should be high before setup gpio. (GPG6 to Input) */
+ writel(readl(S3C_GPGCON) & 0xf0ffffff, S3C_GPGCON);
+
++ #if 0
+ /* GPIO N 13 (external interrupt) : Chip detect */
+ gpio_set_pin(S3C_GPN13, S3C_GPN13_EXTINT13); /* GPN13 to EINT13 */
+ gpio_pullup(S3C_GPN13, 0x2); /* Pull-up Enable */
++ #endif
+
+ /* jsgood: MUXmmc# to DOUTmpll for MPLL Clock Source */
+ writel((readl(S3C_CLK_SRC) & ~(0x3f << 18)) | (0x15 << 18), S3C_CLK_SRC);
+@@ -433,7 +596,6 @@ static void __init smdk6410_machine_init (void)
+ }
+
+ smdk_machine_init();
+-
+ smdk6410_hsmmc_init();
+ smdk6410_set_qos();
+ }
+@@ -473,7 +635,7 @@ void hsmmc_set_gpio (uint channel, uint width)
+ gpio_pullup(S3C_GPG1, 0x0); /* Pull-up/down disable */
+
+ /* GPIO G : Chip detect + LED */
+- gpio_set_pin(S3C_GPG6, S3C_GPG6_MMC_CD1);
++ gpio_set_pin(S3C_GPG6, S3C_GPG6_MMC_CD0);
+ gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
+
+ if (width == 1) {
+@@ -506,8 +668,10 @@ void hsmmc_set_gpio (uint channel, uint width)
+ gpio_pullup(S3C_GPH1, 0x0); /* Pull-up/down disable */
+
+ /* GPIO G : Chip detect + LED */
++ #if 0
+ gpio_set_pin(S3C_GPG6, S3C_GPG6_MMC_CD1);
+ gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
++ #endif
+
+ if (width == 1) {
+ /* GPIO H : MMC DATA1[0] */
+@@ -552,15 +716,18 @@ void hsmmc_set_gpio (uint channel, uint width)
+ /* can supports 1 and 4 bit bus, no irq_cd */
+ case 2:
+ /* GPIO H : Command, Clock */
+- gpio_set_pin(S3C_GPH0, S3C_GPH0_MMC_CLK1);
+- gpio_set_pin(S3C_GPH1, S3C_GPH1_MMC_CMD1);
+
+- gpio_pullup(S3C_GPH0, 0x0); /* Pull-up/down disable */
+- gpio_pullup(S3C_GPH1, 0x0); /* Pull-up/down disable */
++ gpio_set_pin(S3C_GPC4, S3C_GPC4_MMC_CMD2);
++ gpio_set_pin(S3C_GPC5, S3C_GPC5_MMC_CLK2);
+
++ gpio_pullup(S3C_GPC4, 0x0); /* Pull-up/down disable */
++ gpio_pullup(S3C_GPC5, 0x0); /* Pull-up/down disable */
++
++ #if 0
+ /* GPIO G : Chip detect + LED */
+ gpio_set_pin(S3C_GPG6, S3C_GPG6_MMC_CD1);
+ gpio_pullup(S3C_GPG6, 0x2); /* Pull-up Enable */
++ #endif
+
+ if (width == 1) {
+ /* GPIO H : MMC DATA1[0] */
+@@ -580,7 +747,6 @@ void hsmmc_set_gpio (uint channel, uint width)
+ gpio_pullup(S3C_GPH8, 0x0); /* Pull-up/down disable */
+ gpio_pullup(S3C_GPH9, 0x0); /* Pull-up/down disable */
+ }
+-
+ break;
+
+ default:
+@@ -596,10 +762,11 @@ EXPORT_SYMBOL(hsmmc_set_gpio);
+
+ struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
+ .hwport = 0,
+- .enabled = 0,
++ .enabled = 1,
+ .host_caps = HOST_CAPS,
+ .bus_width = 4,
+- .highspeed = 0,
++ .highspeed = 0, /* High speed for mmc channel 0, SD clock up to 50M*/
++ .max_clock = 50 * 1000 * 1000,
+
+ /* ctrl for mmc */
+ .fd_ctrl[MMC_TYPE_MMC] = {
+@@ -617,6 +784,13 @@ struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
+ .ctrl4 = 0x3,
+ },
+
++ .fd_ctrl[MMC_TYPE_SDIO] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for sdio */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
+ .clocks[0] = {
+ .name = "sclk_DOUTmpll_mmc0",
+ .src = 0x2,
+@@ -632,6 +806,7 @@ struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
+ //.bus_width = 8,
+
+ .highspeed = 0,
++ .max_clock = 25 * 1000 * 1000,
+
+ /* ctrl for mmc */
+ .fd_ctrl[MMC_TYPE_MMC] = {
+@@ -649,6 +824,13 @@ struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
+ .ctrl4 = 0x3,
+ },
+
++ .fd_ctrl[MMC_TYPE_SDIO] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for sdio */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
+ .clocks[0] = {
+ .name = "sclk_DOUTmpll_mmc1",
+ .src = 0x2,
+@@ -657,10 +839,11 @@ struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
+
+ struct s3c_hsmmc_cfg s3c_hsmmc2_platform = {
+ .hwport = 2,
+- .enabled = 0,
+- .host_caps = HOST_CAPS,
++ .enabled = 1,
++ .host_caps = HOST_CAPS | MMC_CAP_SDIO_IRQ,
+ .bus_width = 4,
+ .highspeed = 0,
++ .max_clock = 25 * 1000 * 1000,
+
+ /* ctrl for mmc */
+ .fd_ctrl[MMC_TYPE_MMC] = {
+@@ -678,6 +861,13 @@ struct s3c_hsmmc_cfg s3c_hsmmc2_platform = {
+ .ctrl4 = 0x3,
+ },
+
++ .fd_ctrl[MMC_TYPE_SDIO] = {
++ .ctrl2 = 0xC0004100, /* ctrl2 for sdio */
++ .ctrl3[SPEED_NORMAL] = 0x80808080, /* ctrl3 for low speed */
++ .ctrl3[SPEED_HIGH] = 0x00008080, /* ctrl3 for high speed */
++ .ctrl4 = 0x3,
++ },
++
+ .clocks[0] = {
+ .name = "sclk_DOUTmpll_mmc2",
+ .src = 0x2,
+@@ -774,7 +964,6 @@ void otg_phy_init(u32 otg_phy_clk) {
+ writel(0x0, S3C_USBOTG_RSTCON);
+ udelay(50);
+ }
+-
+ EXPORT_SYMBOL(otg_phy_init);
+
+ /* USB Control request data struct must be located here for DMA transfer */
+@@ -783,10 +972,11 @@ EXPORT_SYMBOL(usb_ctrl);
+
+ /* OTG PHY Power Off */
+ void otg_phy_off(void) {
++#if 0 /* Prevent usb host can't work by BXL */
+ writel(readl(S3C_USBOTG_PHYPWR)|(0x1F<<1), S3C_USBOTG_PHYPWR);
+ writel(readl(S3C_OTHERS)&~S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS);
++#endif
+ }
+-
+ EXPORT_SYMBOL(otg_phy_off);
+ #endif
+
+@@ -828,7 +1018,7 @@ EXPORT_SYMBOL(usb_host_clk_en);
+ struct s3c_adc_cfg s3c_adc_platform={
+ /* s3c6410 support 12-bit resolution */
+ .delay = 10000,
+- .presc = 49,
++ .presc = 99,
+ .resolution = 12,
+ };
+
+@@ -860,9 +1050,9 @@ EXPORT_SYMBOL(s3c_adc_convert);
+
+
+ struct s3c_ts_mach_info s3c_ts_platform = {
+- .delay = 10000,
+- .presc = 49,
+- .oversampling_shift = 2,
++ .delay = 65535,
++ .presc = 99,
++ .oversampling_shift = 4,
+ .resol_bit = 12,
+ };
+
+diff --git a/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c b/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c
+index f6203ce..17a4fe2 100644
+--- a/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c
++++ b/arch/arm/mach-s3c6410/pwm/pwm-s3c6410.c
+@@ -93,7 +93,7 @@ int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned l
+ unsigned long pclk;
+ struct clk *clk;
+
+- printk("PWM channel %d set g_tcnt = %ld, g_tcmp = %ld \n", channel, g_tcnt, g_tcmp);
++ //printk("PWM channel %d set g_tcnt = %ld, g_tcmp = %ld \n", channel, g_tcnt, g_tcmp);
+
+ tcnt = 0xffffffff; /* default value for tcnt */
+
+@@ -134,7 +134,7 @@ int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned l
+ tcfg1 |= S3C_TCFG1_MUX1_DIV2;
+
+ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK;
+- tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER0_SHIFT;
++ tcfg0 |= (0) << S3C_TCFG_PRESCALER0_SHIFT;
+
+ tcon &= ~(7<<8);
+ tcon |= S3C_TCON_T1RELOAD;
+@@ -216,6 +216,7 @@ int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned l
+
+ return 0;
+ }
++EXPORT_SYMBOL(s3c6410_timer_setup);
+
+
+ static irqreturn_t s3c6410_pwm_irq(int irq, void *devpw)
+diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
+index 10007c8..5a69455 100644
+--- a/arch/arm/plat-s3c24xx/devs.c
++++ b/arch/arm/plat-s3c24xx/devs.c
+@@ -1078,12 +1078,14 @@ static struct resource s3c_hsmmc0_resource[] = {
+ .end = IRQ_HSMMC0,
+ .flags = IORESOURCE_IRQ,
+ },
++ #if 0
+ /* To detect a card inserted, use an external interrupt */
+ [2] = {
+ .start = IRQ_EINT13,
+ .end = IRQ_EINT13,
+ .flags = IORESOURCE_IRQ,
+ }
++ #endif
+ };
+
+ static struct resource s3c_hsmmc1_resource[] = {
+@@ -1110,11 +1112,13 @@ static struct resource s3c_hsmmc2_resource[] = {
+ .end = IRQ_HSMMC2,
+ .flags = IORESOURCE_IRQ,
+ },
++ #if 0
+ [2] = {
+ .start = IRQ_EINT15,
+ .end = IRQ_EINT15,
+ .flags = IORESOURCE_IRQ,
+ }
++ #endif
+ };
+
+ struct platform_device s3c_device_hsmmc0 = {
+@@ -1453,5 +1457,12 @@ struct platform_device s3c_device_smc911x = {
+ .resource = s3c_smc911x_resources,
+ };
+ EXPORT_SYMBOL(s3c_device_smc911x);
++
++struct platform_device s3c_gpio = {
++ .name = "hhtech_gpio",
++ .id = -1,
++ .num_resources = 0,
++};
++EXPORT_SYMBOL(s3c_gpio);
+ #endif
+
+diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
+index 28f1dc0..b2c986b 100644
+--- a/arch/arm/plat-s3c24xx/gpio.c
++++ b/arch/arm/plat-s3c24xx/gpio.c
+@@ -377,6 +377,7 @@ unsigned int s3c_gpio_getpin(unsigned int pin)
+ {
+ void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
+ unsigned long offs = S3C_GPIO_OFFSET(pin);
++ unsigned long dat; //HHTECH wk
+
+ if((pin>=S3C_GPH0 && pin<=S3C_GPH9)||\
+ (pin>=S3C_GPK0 && pin<=S3C_GPK15)||\
+@@ -384,17 +385,29 @@ unsigned int s3c_gpio_getpin(unsigned int pin)
+ {
+ base = base+0x04;
+ }
+- return __raw_readl(base + 0x04) & (1<< offs);
++ //return __raw_readl(base + 0x04) & (1<< offs); //HHTECH wk orign
++ dat = __raw_readl(base + 0x04) & (1<< offs); //HHTECH wk
++// printk("get GPXDAT pin status!\n"); //HHTECH wk
++ return (dat >> offs);
+ }
+-
+ EXPORT_SYMBOL(s3c_gpio_getpin);
+
+ int s3c_gpio_getirq(unsigned int pin)
+ {
+-
+ /* mandatory */
+ /* Implement this function */
+- return 0;
++//return 0;
++// printk("gpio->irq begin *****************************\n"); //HHTECH wk
++ if (pin >=S3C_GPN0 && pin <=S3C_GPN15)
++ return ((pin-S3C_GPN0) + 64);
++ else
++ {if(pin >= S3C_GPL8 && pin <= S3C_GPL14)
++ return ((pin - S3C_GPL8) + 80); // include/asm-arm/arch-s3c2410/irqs.h
++ else
++ { printk("Plese implement other GPIO interrupts except GPN0~GPN15\n");
++ return -1;
++ }
++ }
+ }
+
+ EXPORT_SYMBOL(s3c_gpio_getirq);
+diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
+index bce4072..0e442b5 100644
+--- a/arch/arm/plat-s3c64xx/Makefile
++++ b/arch/arm/plat-s3c64xx/Makefile
+@@ -28,4 +28,4 @@ obj-$(CONFIG_PM) += pm.o
+ obj-$(CONFIG_PM) += sleep.o
+ obj-$(CONFIG_S3C64XX_DVFS) += s3c64xx-dvfs.o
+ obj-$(CONFIG_CPU_FREQ) += s3c64xx-cpufreq.o
+-obj-$(CONFIG_CPU_FREQ) += ltc3714.o
++#obj-$(CONFIG_CPU_FREQ) += ltc3714.o
+diff --git a/arch/arm/plat-s3c64xx/irq-pl192.c b/arch/arm/plat-s3c64xx/irq-pl192.c
+index 52d0234..e078316 100644
+--- a/arch/arm/plat-s3c64xx/irq-pl192.c
++++ b/arch/arm/plat-s3c64xx/irq-pl192.c
+@@ -270,6 +270,61 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
+ }
+
+ switch (irq) {
++////////////////////////////////HHTECH wk //////////////////////////////////
++
++ case IRQ_EINT0:
++ gpio_set_pin(S3C_GPN0, S3C_GPN0_EXTINT0);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 0)) |
++ (newvalue << 0), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT1:
++ gpio_set_pin(S3C_GPN1, S3C_GPN1_EXTINT1);
++ __raw_writel((__raw_readl(S3C_EINTCON1) & ~(0x7 << 0)) |
++ (newvalue << 0), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT2:
++ gpio_set_pin(S3C_GPN2, S3C_GPN2_EXTINT2);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 4)) |
++ (newvalue << 4), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT3:
++ gpio_set_pin(S3C_GPN3, S3C_GPN3_EXTINT3);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 4)) |
++ (newvalue << 4), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT4:
++ gpio_set_pin(S3C_GPN4, S3C_GPN4_EXTINT4);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 8)) |
++ (newvalue << 8), S3C_EINTCON0);
++ break;
++ case IRQ_EINT5:
++ gpio_set_pin(S3C_GPN5, S3C_GPN5_EXTINT5);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 8)) |
++ (newvalue << 8), S3C_EINTCON0);
++ break;
++ case IRQ_EINT6:
++ gpio_set_pin(S3C_GPN6, S3C_GPN6_EXTINT6);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 12)) |
++ (newvalue << 12), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT7:
++ gpio_set_pin(S3C_GPN7, S3C_GPN7_EXTINT7);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 12)) |
++ (newvalue << 12), S3C_EINTCON0);
++ break;
++
++ case IRQ_EINT8:
++ gpio_set_pin(S3C_GPN8, S3C_GPN8_EXTINT8);
++ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 16)) |
++ (newvalue << 16), S3C_EINTCON0);
++ break;
++////////////////////////////////HHTECH wk //////////////////////////////////
++
+ case IRQ_EINT9:
+ gpio_set_pin(S3C_GPN9, S3C_GPN9_EXTINT9);
+ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 16)) |
+@@ -293,26 +348,39 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
+ (newvalue << 24), S3C_EINTCON0);
+ break;
+
+- case IRQ_EINT13:
+- gpio_set_pin(S3C_GPN13, S3C_GPN13_EXTINT13);
+- __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 24)) |
+- (newvalue << 24), S3C_EINTCON0);
+- break;
+-
+- case IRQ_EINT14:
+- gpio_set_pin(S3C_GPN14, S3C_GPN14_EXTINT14);
+- __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 28)) |
+- (newvalue << 28), S3C_EINTCON0);
+- break;
+-
+ case IRQ_EINT15:
+ gpio_set_pin(S3C_GPN15, S3C_GPN15_EXTINT15);
+ __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 28)) |
+ (newvalue << 28), S3C_EINTCON0);
+ break;
++////////////////////////////////////////////////////////////////
++ case IRQ_EINT18:
++ gpio_set_pin(S3C_GPL10, S3C_GPL10_EXTINT18);
++ __raw_writel((__raw_readl(S3C_EINTCON1) & ~(0xf << 4)) |
++ (newvalue << 4), S3C_EINTCON1);
++ break;
++
++ case IRQ_EINT19:
++ gpio_set_pin(S3C_GPL11, S3C_GPL11_EXTINT19);
++ __raw_writel((__raw_readl(S3C_EINTCON1) & ~(0xf << 4)) |
++ (newvalue << 4), S3C_EINTCON1);
++ break;
++
++ case IRQ_EINT20:
++ gpio_set_pin(S3C_GPL12, S3C_GPL12_EXTINT20);
++ __raw_writel((__raw_readl(S3C_EINTCON1) & ~(0xf << 8)) |
++ (newvalue << 8), S3C_EINTCON1);
++ break;
++
++ case IRQ_EINT22:
++ gpio_set_pin(S3C_GPL14, S3C_GPL14_EXTINT22);
++ __raw_writel((__raw_readl(S3C_EINTCON1) & ~(0xf << 12)) |
++ (newvalue << 12), S3C_EINTCON1);
++ break;
++/////////////////////////////////////////////////////////////////////////
+ default:
+ printk(KERN_ERR
+- "s3c_irqext_type : Only support EINT9,10,11,12,13,14,15 interrupt.\n");
++ "ttttttttttttttttttttt s3c_irqext_type : Only support EINT9,10,11,12,13,14,15,22 interrupt.\n");
+ break;
+
+ }
+diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c
+index 08efe07..8f8ce9a 100644
+--- a/arch/arm/plat-s3c64xx/pm.c
++++ b/arch/arm/plat-s3c64xx/pm.c
+@@ -30,6 +30,7 @@
+ #include <linux/suspend.h>
+ #include <linux/errno.h>
+ #include <linux/time.h>
++#include <linux/jiffies.h>
+ #include <linux/interrupt.h>
+ #include <linux/crc32.h>
+ #include <linux/ioport.h>
+@@ -53,6 +54,8 @@
+
+ #include <asm/plat-s3c24xx/pm.h>
+ #include <asm/mach/irq.h>
++#include <linux/rtc.h>
++#include <asm/plat-s3c64xx/hhtech_gpio.h>
+
+ /* for external use */
+
+@@ -237,6 +240,22 @@ static struct sleep_save sromc_save[] = {
+ SAVE_ITEM(S3C_SROM_BC5),
+ };
+
++static struct sleep_save clock_save[] = {
++ SAVE_ITEM(S3C_APLL_CON),
++ SAVE_ITEM(S3C_MPLL_CON),
++ SAVE_ITEM(S3C_EPLL_CON0),
++ SAVE_ITEM(S3C_EPLL_CON1),
++ SAVE_ITEM(S3C_CLK_SRC),
++ SAVE_ITEM(S3C_CLK_SRC2),
++ SAVE_ITEM(S3C_CLK_DIV0),
++ SAVE_ITEM(S3C_CLK_DIV1),
++ SAVE_ITEM(S3C_CLK_DIV2),
++ SAVE_ITEM(S3C_CLK_OUT),
++ SAVE_ITEM(S3C_HCLK_GATE),
++ SAVE_ITEM(S3C_PCLK_GATE),
++ SAVE_ITEM(S3C_SCLK_GATE),
++};
++
+ #endif
+
+ #ifdef CONFIG_S3C2410_PM_DEBUG
+@@ -603,26 +622,46 @@ static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
+ extern int s3c_irqext_type(unsigned int irq, unsigned int type);
+ extern void s3c_irqext_unmaskack(unsigned int irqno);
+ #endif
++extern void s3c_rtc_setaie(int to);
++extern int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm);
++extern int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm);
++extern unsigned long rtc_wakeup_time;
+
+ static void s3c6410_pm_configure_extint(void)
+ {
++ int dc_status;
++ struct timeval tv;
++ unsigned long now_seconds, alrm_seconds;
++ struct rtc_time now_time, alrm_time;
++ struct rtc_wkalrm wkalrm;
++
++#if defined (CONFIG_LCD_4)
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 1 : 0;
++#else
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 0 : 1;
++#endif
+
+- /* for each of the external interrupts (EINT0..EINT15) we
+- * need to check wether it is an external interrupt source,
+- * and then configure it as an input if it is not
+- */
+-
+- gpio_set_pin(S3C_GPN10, S3C_GPN10_EXTINT10);
+- gpio_pullup(S3C_GPN10, 2);
+- udelay(50);
+-
+- __raw_writel((__raw_readl(S3C_EINTCON0) & ~(0x7 << 20)) |
+- (S3C_EXTINT_FALLEDGE << 20), S3C_EINTCON0);
+-
+- __raw_writel(1UL << (IRQ_EINT10 - IRQ_EINT0), S3C_EINTPEND);
+- __raw_writel(__raw_readl(S3C_EINTMASK)&~(1UL << (IRQ_EINT10 - IRQ_EINT0)), S3C_EINTMASK);
++ if(0 == dc_status) {
++ /* make system wake up after rtc_wakeup_time seconds by RTC alarm */
++ s3c_rtc_gettime(NULL, &now_time);
++ rtc_tm_to_time(&now_time, &now_seconds);
++ alrm_seconds = now_seconds + rtc_wakeup_time;
++ rtc_time_to_tm(alrm_seconds, &alrm_time);
++ wkalrm.enabled = 1;
++ wkalrm.pending = 0;
++ wkalrm.time = alrm_time;
++ s3c_rtc_setalarm(NULL, &wkalrm);
++ s3c_rtc_setaie(1);
++ }
+
+- __raw_writel((0x0fffffff&~(3<<9)), S3C_EINT_MASK);
++ /* make the POWER key: GPL14 the wakeup source, but the other keys are excluded */
++ set_irq_wake(IRQ_EINT12, 0); // GPN12 is excluded
++ set_irq_wake(IRQ_EINT15, 0); // GPN15 is excluded
++ set_irq_wake(IRQ_EINT2, 0); // GPN2 is excluded
++#if defined (CONFIG_LCD_7)
++ set_irq_wake(IRQ_EINT3, 0); // GPN3 is excluded
++ set_irq_wake(IRQ_EINT4, 0); // GPN4 is excluded
++#endif
+ }
+
+ void (*pm_cpu_prep)(void);
+@@ -654,10 +693,12 @@ static int s3c6410_pm_enter(suspend_state_t state)
+ s3c2410_sleep_save_phys = virt_to_phys(regs_save);
+
+ /* save all necessary core registers not covered by the drivers */
++ //gpio_direction_output(S3C_GPF15, 0); // close the backlight of LCD
+ s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
+ s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+ s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
+ s3c2410_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save));
++ s3c2410_pm_do_save(clock_save, ARRAY_SIZE(clock_save));
+
+ /* ensure INF_REG0 has the resume address */
+ __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C_INFORM0);
+@@ -721,6 +762,7 @@ static int s3c6410_pm_enter(suspend_state_t state)
+ cpu_init();
+
+ /* restore the system state */
++ s3c2410_pm_do_restore(clock_save, ARRAY_SIZE(clock_save));
+ s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
+ s3c2410_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save));
+ s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
+@@ -733,6 +775,14 @@ static int s3c6410_pm_enter(suspend_state_t state)
+
+ s3c2410_pm_check_restore();
+
++ /* Enable all the keys function after waken up from sleep mode */
++ set_irq_wake(IRQ_EINT12, 1);
++ set_irq_wake(IRQ_EINT15, 1);
++ set_irq_wake(IRQ_EINT2, 1);
++#if defined (CONFIG_LCD_7)
++ set_irq_wake(IRQ_EINT3, 1);
++ set_irq_wake(IRQ_EINT4, 1);
++#endif
+ /* ok, let's return from sleep */
+ DBG("S3C6400 PM Resume (post-restore)\n");
+ return 0;
+diff --git a/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c b/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
+index 2e10ea9..a509071 100644
+--- a/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
++++ b/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
+@@ -27,9 +27,10 @@
+ #include <asm/system.h>
+
+ #define USE_FREQ_TABLE
+-#define USE_DVS
++//#define USE_DVS
+ #define VERY_HI_RATE 532*1000*1000
+ #define APLL_GEN_CLK 532*1000 //khz
++#define APLL_GEN_CLK2 400*1000 //khz
+ #define KHZ_T 1000
+
+ #define MPU_CLK "fclk"
+@@ -43,9 +44,13 @@ extern int ltc3714_init(void);
+
+ /* frequency */
+ static struct cpufreq_frequency_table s3c6410_freq_table[] = {
++ {APLL_GEN_CLK, 667*1000},
+ {APLL_GEN_CLK, APLL_GEN_CLK},
++ {APLL_GEN_CLK, APLL_GEN_CLK2},
+ {APLL_GEN_CLK, APLL_GEN_CLK/2},
++ {APLL_GEN_CLK, APLL_GEN_CLK2/2},
+ {APLL_GEN_CLK, APLL_GEN_CLK/4},
++ {APLL_GEN_CLK, APLL_GEN_CLK2/4},
+ {0, CPUFREQ_TABLE_END},
+ };
+
+diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
+index 806ce26..ba592a9 100644
+--- a/arch/arm/vfp/entry.S
++++ b/arch/arm/vfp/entry.S
+@@ -21,13 +21,13 @@
+ #include <asm/assembler.h>
+ #include <asm/vfpmacros.h>
+
+- .globl do_vfp
+-do_vfp:
++ENTRY(do_vfp)
+ enable_irq
+ ldr r4, .LCvfp
+ ldr r11, [r10, #TI_CPU] @ CPU number
+ add r10, r10, #TI_VFPSTATE @ r10 = workspace
+ ldr pc, [r4] @ call VFP entry point
++ENDPROC(do_vfp)
+
+ ENTRY(vfp_null_entry)
+ mov pc, lr
+@@ -40,11 +40,11 @@ ENDPROC(vfp_null_entry)
+ @ failure to the VFP initialisation code.
+
+ __INIT
+- .globl vfp_testing_entry
+-vfp_testing_entry:
++ENTRY(vfp_testing_entry)
+ ldr r0, VFP_arch_address
+ str r5, [r0] @ known non-zero value
+ mov pc, r9 @ we have handled the fault
++ENDPROC(vfp_testing_entry)
+
+ VFP_arch_address:
+ .word VFP_arch
+diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
+index 791d023..8de86e4 100644
+--- a/arch/arm/vfp/vfp.h
++++ b/arch/arm/vfp/vfp.h
+@@ -265,7 +265,11 @@ struct vfp_double {
+ * which returns (double)0.0. This is useful for the compare with
+ * zero instructions.
+ */
++#ifdef CONFIG_VFPv3
++#define VFP_REG_ZERO 32
++#else
+ #define VFP_REG_ZERO 16
++#endif
+ extern u64 vfp_get_double(unsigned int reg);
+ extern void vfp_put_double(u64 val, unsigned int reg);
+
+@@ -373,6 +377,6 @@ struct op {
+ u32 flags;
+ };
+
+-#ifdef CONFIG_SMP
++#if defined(CONFIG_SMP) || defined(CONFIG_PM)
+ extern void vfp_save_state(void *location, u32 fpexc);
+ #endif
+diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
+index 0ac022f..c92a08b 100644
+--- a/arch/arm/vfp/vfphw.S
++++ b/arch/arm/vfp/vfphw.S
+@@ -68,8 +68,7 @@
+ @ r11 = CPU number
+ @ lr = failure return
+
+- .globl vfp_support_entry
+-vfp_support_entry:
++ENTRY(vfp_support_entry)
+ DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
+
+ VFPFMRX r1, FPEXC @ Is the VFP enabled?
+@@ -99,12 +98,15 @@ vfp_support_entry:
+ DBGSTR1 "save old state %p", r4
+ cmp r4, #0
+ beq no_old_VFP_process
++ VFPFSTMIA r4, r5 @ save the working registers
+ VFPFMRX r5, FPSCR @ current status
+- VFPFMRX r6, FPINST @ FPINST (always there, rev0 onwards)
+- tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
+- VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading
+- @ nonexistant reg on rev0
+- VFPFSTMIA r4 @ save the working registers
++ tst r1, #FPEXC_EX @ is there additional state to save?
++ beq 1f
++ VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
++ tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
++ beq 1f
++ VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
++1:
+ stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
+ @ and point r4 at the word at the
+ @ start of the register dump
+@@ -114,13 +116,16 @@ no_old_VFP_process:
+ DBGSTR1 "load state %p", r10
+ str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer
+ @ Load the saved state back into the VFP
+- VFPFLDMIA r10 @ reload the working registers while
++ VFPFLDMIA r10, r5 @ reload the working registers while
+ @ FPEXC is in a safe state
+ ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
+- tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write?
+- VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing
+- @ nonexistant reg on rev0
+- VFPFMXR FPINST, r6
++ tst r1, #FPEXC_EX @ is there additional state to restore?
++ beq 1f
++ VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
++ tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
++ beq 1f
++ VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
++1:
+ VFPFMXR FPSCR, r5 @ restore status
+
+ check_for_exception:
+@@ -136,10 +141,14 @@ check_for_exception:
+
+
+ look_for_VFP_exceptions:
+- tst r1, #FPEXC_EX
++ @ Check for synchronous or asynchronous exception
++ tst r1, #FPEXC_EX | FPEXC_DEX
+ bne process_exception
++ @ On some implementations of the VFP subarch 1, setting FPSCR.IXE
++ @ causes all the CDP instructions to be bounced synchronously without
++ @ setting the FPEXC.EX bit
+ VFPFMRX r5, FPSCR
+- tst r5, #FPSCR_IXE @ IXE doesn't set FPEXC_EX !
++ tst r5, #FPSCR_IXE
+ bne process_exception
+
+ @ Fall into hand on to next handler - appropriate coproc instr
+@@ -150,10 +159,6 @@ look_for_VFP_exceptions:
+
+ process_exception:
+ DBGSTR "bounce"
+- sub r2, r2, #4
+- str r2, [sp, #S_PC] @ retry the instruction on exit from
+- @ the imprecise exception handling in
+- @ the support code
+ mov r2, sp @ nothing stacked - regdump is at TOS
+ mov lr, r9 @ setup for a return to the user code.
+
+@@ -161,34 +166,36 @@ process_exception:
+ @ r0 holds the trigger instruction
+ @ r1 holds the FPEXC value
+ @ r2 pointer to register dump
+- b VFP9_bounce @ we have handled this - the support
++ b VFP_bounce @ we have handled this - the support
+ @ code will raise an exception if
+ @ required. If not, the user code will
+ @ retry the faulted instruction
++ENDPROC(vfp_support_entry)
+
+-#ifdef CONFIG_SMP
+- .globl vfp_save_state
+- .type vfp_save_state, %function
+-vfp_save_state:
++#if defined(CONFIG_SMP) || defined(CONFIG_PM)
++ENTRY(vfp_save_state)
+ @ Save the current VFP state
+ @ r0 - save location
+ @ r1 - FPEXC
+ DBGSTR1 "save VFP state %p", r0
++ VFPFSTMIA r0, r2 @ save the working registers
+ VFPFMRX r2, FPSCR @ current status
+- VFPFMRX r3, FPINST @ FPINST (always there, rev0 onwards)
+- tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
+- VFPFMRX r12, FPINST2, NE @ FPINST2 if needed - avoids reading
+- @ nonexistant reg on rev0
+- VFPFSTMIA r0 @ save the working registers
++ tst r1, #FPEXC_EX @ is there additional state to save?
++ beq 1f
++ VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
++ tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
++ beq 1f
++ VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
++1:
+ stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
+ mov pc, lr
++ENDPROC(vfp_save_state)
+ #endif
+
+ last_VFP_context_address:
+ .word last_VFP_context
+
+- .globl vfp_get_float
+-vfp_get_float:
++ENTRY(vfp_get_float)
+ add pc, pc, r0, lsl #3
+ mov r0, r0
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+@@ -197,9 +204,9 @@ vfp_get_float:
+ mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
+ mov pc, lr
+ .endr
++ENDPROC(vfp_get_float)
+
+- .globl vfp_put_float
+-vfp_put_float:
++ENTRY(vfp_put_float)
+ add pc, pc, r1, lsl #3
+ mov r0, r0
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+@@ -208,26 +215,41 @@ vfp_put_float:
+ mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
+ mov pc, lr
+ .endr
++ENDPROC(vfp_put_float)
+
+- .globl vfp_get_double
+-vfp_get_double:
++ENTRY(vfp_get_double)
+ add pc, pc, r0, lsl #3
+ mov r0, r0
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+ fmrrd r0, r1, d\dr
+ mov pc, lr
+ .endr
++#ifdef CONFIG_VFPv3
++ @ d16 - d31 registers
++ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
++ mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
++ mov pc, lr
++ .endr
++#endif
+
+- @ virtual register 16 for compare with zero
++ @ virtual register 16 (or 32 if VFPv3) for compare with zero
+ mov r0, #0
+ mov r1, #0
+ mov pc, lr
++ENDPROC(vfp_get_double)
+
+- .globl vfp_put_double
+-vfp_put_double:
++ENTRY(vfp_put_double)
+ add pc, pc, r2, lsl #3
+ mov r0, r0
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+ fmdrr d\dr, r0, r1
+ mov pc, lr
+ .endr
++#ifdef CONFIG_VFPv3
++ @ d16 - d31 registers
++ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
++ mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr
++ mov pc, lr
++ .endr
++#endif
++ENDPROC(vfp_put_double)
+diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
+index 7f343a4..15b95b5 100644
+--- a/arch/arm/vfp/vfpinstr.h
++++ b/arch/arm/vfp/vfpinstr.h
+@@ -52,11 +52,11 @@
+ #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
+
+ #define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
+-#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12)
++#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
+ #define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
+-#define vfp_get_dm(inst) ((inst & 0x0000000f))
++#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
+ #define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
+-#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16)
++#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
+
+ #define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
+
+diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
+index b4e210d..00d2562 100644
+--- a/arch/arm/vfp/vfpmodule.c
++++ b/arch/arm/vfp/vfpmodule.c
+@@ -125,13 +125,13 @@ void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
+ send_sig_info(SIGFPE, &info, current);
+ }
+
+-static void vfp_panic(char *reason)
++static void vfp_panic(char *reason, u32 inst)
+ {
+ int i;
+
+ printk(KERN_ERR "VFP: Error: %s\n", reason);
+ printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
+- fmrx(FPEXC), fmrx(FPSCR), fmrx(FPINST));
++ fmrx(FPEXC), fmrx(FPSCR), inst);
+ for (i = 0; i < 32; i += 2)
+ printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
+ i, vfp_get_float(i), i+1, vfp_get_float(i+1));
+@@ -147,19 +147,16 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
+ pr_debug("VFP: raising exceptions %08x\n", exceptions);
+
+ if (exceptions == VFP_EXCEPTION_ERROR) {
+- vfp_panic("unhandled bounce");
++ vfp_panic("unhandled bounce", inst);
+ vfp_raise_sigfpe(0, regs);
+ return;
+ }
+
+ /*
+- * If any of the status flags are set, update the FPSCR.
++ * Update the FPSCR with the additional exception flags.
+ * Comparison instructions always return at least one of
+ * these flags set.
+ */
+- if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
+- fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
+-
+ fpscr |= exceptions;
+
+ fmxr(FPSCR, fpscr);
+@@ -220,35 +217,64 @@ static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
+ /*
+ * Package up a bounce condition.
+ */
+-void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
++void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
+ {
+- u32 fpscr, orig_fpscr, exceptions, inst;
++ u32 fpscr, orig_fpscr, fpsid, exceptions;
+
+ pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
+
+ /*
+- * Enable access to the VFP so we can handle the bounce.
++ * At this point, FPEXC can have the following configuration:
++ *
++ * EX DEX IXE
++ * 0 1 x - synchronous exception
++ * 1 x 0 - asynchronous exception
++ * 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later
++ * 0 0 1 - synchronous on VFP9 (non-standard subarch 1
++ * implementation), undefined otherwise
++ *
++ * Clear various bits and enable access to the VFP so we can
++ * handle the bounce.
+ */
+- fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_FPV2|FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC));
++ fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK));
+
++ fpsid = fmrx(FPSID);
+ orig_fpscr = fpscr = fmrx(FPSCR);
+
+ /*
+- * If we are running with inexact exceptions enabled, we need to
+- * emulate the trigger instruction. Note that as we're emulating
+- * the trigger instruction, we need to increment PC.
++ * Check for the special VFP subarch 1 and FPSCR.IXE bit case
+ */
+- if (fpscr & FPSCR_IXE) {
+- regs->ARM_pc += 4;
++ if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT)
++ && (fpscr & FPSCR_IXE)) {
++ /*
++ * Synchronous exception, emulate the trigger instruction
++ */
+ goto emulate;
+ }
+
+- barrier();
++ if (fpexc & FPEXC_EX) {
++ /*
++ * Asynchronous exception. The instruction is read from FPINST
++ * and the interrupted instruction has to be restarted.
++ */
++ trigger = fmrx(FPINST);
++ regs->ARM_pc -= 4;
++ } else if (!(fpexc & FPEXC_DEX)) {
++ /*
++ * Illegal combination of bits. It can be caused by an
++ * unallocated VFP instruction but with FPSCR.IXE set and not
++ * on VFP subarch 1.
++ */
++ vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs);
++ return;
++ }
+
+ /*
+- * Modify fpscr to indicate the number of iterations remaining
++ * Modify fpscr to indicate the number of iterations remaining.
++ * If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates
++ * whether FPEXC.VECITR or FPSCR.LEN is used.
+ */
+- if (fpexc & FPEXC_EX) {
++ if (fpexc & (FPEXC_EX | FPEXC_VV)) {
+ u32 len;
+
+ len = fpexc + (1 << FPEXC_LENGTH_BIT);
+@@ -262,15 +288,15 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
+ * FPEXC bounce reason, but this appears to be unreliable.
+ * Emulate the bounced instruction instead.
+ */
+- inst = fmrx(FPINST);
+- exceptions = vfp_emulate_instruction(inst, fpscr, regs);
++ exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
+ if (exceptions)
+- vfp_raise_exceptions(exceptions, inst, orig_fpscr, regs);
++ vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
+
+ /*
+- * If there isn't a second FP instruction, exit now.
++ * If there isn't a second FP instruction, exit now. Note that
++ * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1.
+ */
+- if (!(fpexc & FPEXC_FPV2))
++ if (fpexc ^ (FPEXC_EX | FPEXC_FP2V))
+ return;
+
+ /*
+@@ -279,10 +305,9 @@ void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
+ */
+ barrier();
+ trigger = fmrx(FPINST2);
+- orig_fpscr = fpscr = fmrx(FPSCR);
+
+ emulate:
+- exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
++ exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs);
+ if (exceptions)
+ vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
+ }
+@@ -297,6 +322,62 @@ static void vfp_enable(void *unused)
+ set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
+ }
+
++#ifdef CONFIG_PM
++#include <linux/sysdev.h>
++
++static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state)
++{
++ struct thread_info *ti = current_thread_info();
++ u32 fpexc = fmrx(FPEXC);
++
++ /* if vfp is on, then save state for resumption */
++ if (fpexc & FPEXC_EN) {
++ printk(KERN_DEBUG "%s: saving vfp state\n", __func__);
++ vfp_save_state(&ti->vfpstate, fpexc);
++
++ /* disable, just in case */
++ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
++ }
++
++ /* clear any information we had about last context state */
++ memset(last_VFP_context, 0, sizeof(last_VFP_context));
++
++ return 0;
++}
++
++static int vfp_pm_resume(struct sys_device *dev)
++{
++ /* ensure we have access to the vfp */
++ vfp_enable(NULL);
++
++ /* and disable it to ensure the next usage restores the state */
++ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
++
++ return 0;
++}
++
++static struct sysdev_class vfp_pm_sysclass = {
++ //.name = "vfp",
++ set_kset_name("vfp"),
++ .suspend = vfp_pm_suspend,
++ .resume = vfp_pm_resume,
++};
++
++static struct sys_device vfp_pm_sysdev = {
++ .cls = &vfp_pm_sysclass,
++};
++
++static void vfp_pm_init(void)
++{
++ sysdev_class_register(&vfp_pm_sysclass);
++ sysdev_register(&vfp_pm_sysdev);
++}
++
++
++#else
++static inline void vfp_pm_init(void) { }
++#endif /* CONFIG_PM */
++
+ #include <linux/smp.h>
+
+ /*
+@@ -306,16 +387,9 @@ static int __init vfp_init(void)
+ {
+ unsigned int vfpsid;
+ unsigned int cpu_arch = cpu_architecture();
+- u32 access = 0;
+-
+- if (cpu_arch >= CPU_ARCH_ARMv6) {
+- access = get_copro_access();
+
+- /*
+- * Enable full access to VFP (cp10 and cp11)
+- */
+- set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
+- }
++ if (cpu_arch >= CPU_ARCH_ARMv6)
++ vfp_enable(NULL);
+
+ /*
+ * First check that there is a VFP that we can use.
+@@ -329,15 +403,9 @@ static int __init vfp_init(void)
+ vfp_vector = vfp_null_entry;
+
+ printk(KERN_INFO "VFP support v0.3: ");
+- if (VFP_arch) {
++ if (VFP_arch)
+ printk("not present\n");
+-
+- /*
+- * Restore the copro access register.
+- */
+- if (cpu_arch >= CPU_ARCH_ARMv6)
+- set_copro_access(access);
+- } else if (vfpsid & FPSID_NODOUBLE) {
++ else if (vfpsid & FPSID_NODOUBLE) {
+ printk("no double precision support\n");
+ } else {
+ smp_call_function(vfp_enable, NULL, 1, 1);
+@@ -353,12 +421,22 @@ static int __init vfp_init(void)
+ vfp_vector = vfp_support_entry;
+
+ thread_register_notifier(&vfp_notifier_block);
++ vfp_pm_init();
+
+ /*
+ * We detected VFP, and the support code is
+ * in place; report VFP support to userspace.
+ */
+ elf_hwcap |= HWCAP_VFP;
++#ifdef CONFIG_NEON
++ /*
++ * Check for the presence of the Advanced SIMD
++ * load/store instructions, integer and single
++ * precision floating point operations.
++ */
++ if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
++ elf_hwcap |= HWCAP_NEON;
++#endif
+ }
+ return 0;
+ }
+diff --git a/drivers/Makefile b/drivers/Makefile
+index 8cb37e3..3672a9f 100644
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -19,6 +19,7 @@ obj-$(CONFIG_XEN) += xen/
+
+ # char/ comes before serial/ etc so that the VT console is the boot-time
+ # default.
++obj-$(CONFIG_INPUT) += input/
+ obj-y += char/
+
+ obj-$(CONFIG_CONNECTOR) += connector/
+@@ -58,7 +59,6 @@ obj-$(CONFIG_PCI) += usb/
+ obj-$(CONFIG_USB_GADGET) += usb/gadget/
+ obj-$(CONFIG_SERIO) += input/serio/
+ obj-$(CONFIG_GAMEPORT) += input/gameport/
+-obj-$(CONFIG_INPUT) += input/
+ obj-$(CONFIG_I2O) += message/
+ obj-$(CONFIG_RTC_LIB) += rtc/
+ obj-y += i2c/
+diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
+index 075598e..7cb4029 100644
+--- a/drivers/bluetooth/Kconfig
++++ b/drivers/bluetooth/Kconfig
+@@ -3,8 +3,8 @@ menu "Bluetooth device drivers"
+ depends on BT
+
+ config BT_HCIUSB
+- tristate "HCI USB driver"
+- depends on USB
++ tristate "HCI USB driver (old version)"
++ depends on USB && BT_HCIBTUSB=n
+ help
+ Bluetooth HCI USB driver.
+ This driver is required if you want to use Bluetooth devices with
+@@ -23,15 +23,13 @@ config BT_HCIUSB_SCO
+ Say Y here to compile support for SCO over HCI USB.
+
+ config BT_HCIBTUSB
+- tristate "HCI USB driver (alternate version)"
+- depends on USB && EXPERIMENTAL && BT_HCIUSB=n
++ tristate "HCI USB driver"
++ depends on USB
+ help
+ Bluetooth HCI USB driver.
+ This driver is required if you want to use Bluetooth devices with
+ USB interface.
+
+- This driver is still experimental and has no SCO support.
+-
+ Say Y here to compile support for Bluetooth USB devices into the
+ kernel or say M to compile it as module (btusb).
+
+@@ -71,6 +69,7 @@ config BT_HCIUART_H4
+ config BT_HCIUART_BCSP
+ bool "BCSP protocol support"
+ depends on BT_HCIUART
++ select BITREVERSE
+ help
+ BCSP (BlueCore Serial Protocol) is serial protocol for communication
+ between Bluetooth device and host. This protocol is required for non
+diff --git a/drivers/bluetooth/bcm203x.c b/drivers/bluetooth/bcm203x.c
+index 8919ccf..ee40201 100644
+--- a/drivers/bluetooth/bcm203x.c
++++ b/drivers/bluetooth/bcm203x.c
+@@ -42,9 +42,7 @@
+ #define BT_DBG(D...)
+ #endif
+
+-#define VERSION "1.1"
+-
+-static int ignore = 0;
++#define VERSION "1.2"
+
+ static struct usb_device_id bcm203x_table[] = {
+ /* Broadcom Blutonium (BCM2033) */
+@@ -175,7 +173,7 @@ static int bcm203x_probe(struct usb_interface *intf, const struct usb_device_id
+
+ BT_DBG("intf %p id %p", intf, id);
+
+- if (ignore || (intf->cur_altsetting->desc.bInterfaceNumber != 0))
++ if (intf->cur_altsetting->desc.bInterfaceNumber != 0)
+ return -ENODEV;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+@@ -300,9 +298,6 @@ static void __exit bcm203x_exit(void)
+ module_init(bcm203x_init);
+ module_exit(bcm203x_exit);
+
+-module_param(ignore, bool, 0644);
+-MODULE_PARM_DESC(ignore, "Ignore devices from the matching table");
+-
+ MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("Broadcom Blutonium firmware driver ver " VERSION);
+ MODULE_VERSION(VERSION);
+diff --git a/drivers/bluetooth/bfusb.c b/drivers/bluetooth/bfusb.c
+index b990805..90a0946 100644
+--- a/drivers/bluetooth/bfusb.c
++++ b/drivers/bluetooth/bfusb.c
+@@ -43,9 +43,7 @@
+ #define BT_DBG(D...)
+ #endif
+
+-#define VERSION "1.1"
+-
+-static int ignore = 0;
++#define VERSION "1.2"
+
+ static struct usb_driver bfusb_driver;
+
+@@ -566,7 +564,8 @@ static int bfusb_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg
+ return -ENOIOCTLCMD;
+ }
+
+-static int bfusb_load_firmware(struct bfusb_data *data, unsigned char *firmware, int count)
++static int bfusb_load_firmware(struct bfusb_data *data,
++ const unsigned char *firmware, int count)
+ {
+ unsigned char *buf;
+ int err, pipe, len, size, sent = 0;
+@@ -655,9 +654,6 @@ static int bfusb_probe(struct usb_interface *intf, const struct usb_device_id *i
+
+ BT_DBG("intf %p id %p", intf, id);
+
+- if (ignore)
+- return -ENODEV;
+-
+ /* Check number of endpoints */
+ if (intf->cur_altsetting->desc.bNumEndpoints < 2)
+ return -EIO;
+@@ -794,9 +790,6 @@ static void __exit bfusb_exit(void)
+ module_init(bfusb_init);
+ module_exit(bfusb_exit);
+
+-module_param(ignore, bool, 0644);
+-MODULE_PARM_DESC(ignore, "Ignore devices from the matching table");
+-
+ MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("BlueFRITZ! USB driver ver " VERSION);
+ MODULE_VERSION(VERSION);
+diff --git a/drivers/bluetooth/bluecard_cs.c b/drivers/bluetooth/bluecard_cs.c
+index bcf5792..b0e569b 100644
+--- a/drivers/bluetooth/bluecard_cs.c
++++ b/drivers/bluetooth/bluecard_cs.c
+@@ -867,7 +867,7 @@ static int bluecard_probe(struct pcmcia_device *link)
+
+ link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
+ link->io.NumPorts1 = 8;
+- link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
++ link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT;
+ link->irq.IRQInfo1 = IRQ_LEVEL_ID;
+
+ link->irq.Handler = bluecard_interrupt;
+@@ -901,23 +901,23 @@ static int bluecard_config(struct pcmcia_device *link)
+ for (n = 0; n < 0x400; n += 0x40) {
+ link->io.BasePort1 = n ^ 0x300;
+ i = pcmcia_request_io(link, &link->io);
+- if (i == CS_SUCCESS)
++ if (i == 0)
+ break;
+ }
+
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestIO, i);
+ goto failed;
+ }
+
+ i = pcmcia_request_irq(link, &link->irq);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestIRQ, i);
+ link->irq.AssignedIRQ = 0;
+ }
+
+ i = pcmcia_request_configuration(link, &link->conf);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestConfiguration, i);
+ goto failed;
+ }
+diff --git a/drivers/bluetooth/bpa10x.c b/drivers/bluetooth/bpa10x.c
+index 1375b53..b936d8c 100644
+--- a/drivers/bluetooth/bpa10x.c
++++ b/drivers/bluetooth/bpa10x.c
+@@ -40,9 +40,7 @@
+ #define BT_DBG(D...)
+ #endif
+
+-#define VERSION "0.9"
+-
+-static int ignore = 0;
++#define VERSION "0.10"
+
+ static struct usb_device_id bpa10x_table[] = {
+ /* Tektronix BPA 100/105 (Digianswer) */
+@@ -258,7 +256,6 @@ static inline int bpa10x_submit_intr_urb(struct hci_dev *hdev)
+ BT_ERR("%s urb %p submission failed (%d)",
+ hdev->name, urb, -err);
+ usb_unanchor_urb(urb);
+- kfree(buf);
+ }
+
+ usb_free_urb(urb);
+@@ -300,7 +297,6 @@ static inline int bpa10x_submit_bulk_urb(struct hci_dev *hdev)
+ BT_ERR("%s urb %p submission failed (%d)",
+ hdev->name, urb, -err);
+ usb_unanchor_urb(urb);
+- kfree(buf);
+ }
+
+ usb_free_urb(urb);
+@@ -423,6 +419,7 @@ static int bpa10x_send_frame(struct sk_buff *skb)
+ break;
+
+ default:
++ usb_free_urb(urb);
+ return -EILSEQ;
+ }
+
+@@ -446,8 +443,8 @@ static void bpa10x_destruct(struct hci_dev *hdev)
+
+ BT_DBG("%s", hdev->name);
+
+- kfree(data->rx_skb[0]);
+- kfree(data->rx_skb[1]);
++ kfree_skb(data->rx_skb[0]);
++ kfree_skb(data->rx_skb[1]);
+ kfree(data);
+ }
+
+@@ -459,9 +456,6 @@ static int bpa10x_probe(struct usb_interface *intf, const struct usb_device_id *
+
+ BT_DBG("intf %p id %p", intf, id);
+
+- if (ignore)
+- return -ENODEV;
+-
+ if (intf->cur_altsetting->desc.bInterfaceNumber != 0)
+ return -ENODEV;
+
+@@ -545,9 +539,6 @@ static void __exit bpa10x_exit(void)
+ module_init(bpa10x_init);
+ module_exit(bpa10x_exit);
+
+-module_param(ignore, bool, 0644);
+-MODULE_PARM_DESC(ignore, "Ignore devices from the matching table");
+-
+ MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("Digianswer Bluetooth USB driver ver " VERSION);
+ MODULE_VERSION(VERSION);
+diff --git a/drivers/bluetooth/bt3c_cs.c b/drivers/bluetooth/bt3c_cs.c
+index a18f9b8..b3e4d07 100644
+--- a/drivers/bluetooth/bt3c_cs.c
++++ b/drivers/bluetooth/bt3c_cs.c
+@@ -60,7 +60,7 @@
+ /* ======================== Module parameters ======================== */
+
+
+-MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>, Jose Orlando Pereira <jop@di.uminho.pt>");
++MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("Bluetooth driver for the 3Com Bluetooth PCMCIA card");
+ MODULE_LICENSE("GPL");
+ MODULE_FIRMWARE("BT3CPCC.bin");
+@@ -343,6 +343,7 @@ static irqreturn_t bt3c_interrupt(int irq, void *dev_inst)
+ bt3c_info_t *info = dev_inst;
+ unsigned int iobase;
+ int iir;
++ irqreturn_t r = IRQ_NONE;
+
+ BUG_ON(!info->hdev);
+
+@@ -374,11 +375,12 @@ static irqreturn_t bt3c_interrupt(int irq, void *dev_inst)
+
+ outb(iir, iobase + CONTROL);
+ }
++ r = IRQ_HANDLED;
+ }
+
+ spin_unlock(&(info->lock));
+
+- return IRQ_HANDLED;
++ return r;
+ }
+
+
+@@ -470,7 +472,8 @@ static int bt3c_hci_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long
+ /* ======================== Card services HCI interaction ======================== */
+
+
+-static int bt3c_load_firmware(bt3c_info_t *info, unsigned char *firmware, int count)
++static int bt3c_load_firmware(bt3c_info_t *info, const unsigned char *firmware,
++ int count)
+ {
+ char *ptr = (char *) firmware;
+ char b[9];
+@@ -656,7 +659,7 @@ static int bt3c_probe(struct pcmcia_device *link)
+
+ link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
+ link->io.NumPorts1 = 8;
+- link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
++ link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT;
+ link->irq.IRQInfo1 = IRQ_LEVEL_ID;
+
+ link->irq.Handler = bt3c_interrupt;
+@@ -677,101 +680,78 @@ static void bt3c_detach(struct pcmcia_device *link)
+ kfree(info);
+ }
+
+-static int get_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
++static int bt3c_check_config(struct pcmcia_device *p_dev,
++ cistpl_cftable_entry_t *cf,
++ cistpl_cftable_entry_t *dflt,
++ unsigned int vcc,
++ void *priv_data)
+ {
+- int i;
+-
+- i = pcmcia_get_tuple_data(handle, tuple);
+- if (i != CS_SUCCESS)
+- return i;
+-
+- return pcmcia_parse_tuple(handle, tuple, parse);
+-}
+-
+-static int first_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
+-{
+- if (pcmcia_get_first_tuple(handle, tuple) != CS_SUCCESS)
+- return CS_NO_MORE_ITEMS;
+- return get_tuple(handle, tuple, parse);
++ unsigned long try = (unsigned long) priv_data;
++
++ if (cf->vpp1.present & (1 << CISTPL_POWER_VNOM))
++ p_dev->conf.Vpp = cf->vpp1.param[CISTPL_POWER_VNOM] / 10000;
++ if ((cf->io.nwin > 0) && (cf->io.win[0].len == 8) &&
++ (cf->io.win[0].base != 0)) {
++ p_dev->io.BasePort1 = cf->io.win[0].base;
++ p_dev->io.IOAddrLines = (try == 0) ? 16 :
++ cf->io.flags & CISTPL_IO_LINES_MASK;
++ if (!pcmcia_request_io(p_dev, &p_dev->io))
++ return 0;
++ }
++ return -ENODEV;
+ }
+
+-static int next_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
++static int bt3c_check_config_notpicky(struct pcmcia_device *p_dev,
++ cistpl_cftable_entry_t *cf,
++ cistpl_cftable_entry_t *dflt,
++ unsigned int vcc,
++ void *priv_data)
+ {
+- if (pcmcia_get_next_tuple(handle, tuple) != CS_SUCCESS)
+- return CS_NO_MORE_ITEMS;
+- return get_tuple(handle, tuple, parse);
++ static unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
++ int j;
++
++ if ((cf->io.nwin > 0) && ((cf->io.flags & CISTPL_IO_LINES_MASK) <= 3)) {
++ for (j = 0; j < 5; j++) {
++ p_dev->io.BasePort1 = base[j];
++ p_dev->io.IOAddrLines = base[j] ? 16 : 3;
++ if (!pcmcia_request_io(p_dev, &p_dev->io))
++ return 0;
++ }
++ }
++ return -ENODEV;
+ }
+
+ static int bt3c_config(struct pcmcia_device *link)
+ {
+- static kio_addr_t base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
+ bt3c_info_t *info = link->priv;
+- tuple_t tuple;
+- u_short buf[256];
+- cisparse_t parse;
+- cistpl_cftable_entry_t *cf = &parse.cftable_entry;
+- int i, j, try;
+-
+- /* First pass: look for a config entry that looks normal. */
+- tuple.TupleData = (cisdata_t *)buf;
+- tuple.TupleOffset = 0;
+- tuple.TupleDataMax = 255;
+- tuple.Attributes = 0;
+- tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
+- /* Two tries: without IO aliases, then with aliases */
+- for (try = 0; try < 2; try++) {
+- i = first_tuple(link, &tuple, &parse);
+- while (i != CS_NO_MORE_ITEMS) {
+- if (i != CS_SUCCESS)
+- goto next_entry;
+- if (cf->vpp1.present & (1 << CISTPL_POWER_VNOM))
+- link->conf.Vpp = cf->vpp1.param[CISTPL_POWER_VNOM] / 10000;
+- if ((cf->io.nwin > 0) && (cf->io.win[0].len == 8) && (cf->io.win[0].base != 0)) {
+- link->conf.ConfigIndex = cf->index;
+- link->io.BasePort1 = cf->io.win[0].base;
+- link->io.IOAddrLines = (try == 0) ? 16 : cf->io.flags & CISTPL_IO_LINES_MASK;
+- i = pcmcia_request_io(link, &link->io);
+- if (i == CS_SUCCESS)
+- goto found_port;
+- }
+-next_entry:
+- i = next_tuple(link, &tuple, &parse);
+- }
+- }
++ int i;
++ unsigned long try;
++
++ /* First pass: look for a config entry that looks normal.
++ Two tries: without IO aliases, then with aliases */
++ for (try = 0; try < 2; try++)
++ if (!pcmcia_loop_config(link, bt3c_check_config, (void *) try))
++ goto found_port;
+
+ /* Second pass: try to find an entry that isn't picky about
+ its base address, then try to grab any standard serial port
+ address, and finally try to get any free port. */
+- i = first_tuple(link, &tuple, &parse);
+- while (i != CS_NO_MORE_ITEMS) {
+- if ((i == CS_SUCCESS) && (cf->io.nwin > 0) && ((cf->io.flags & CISTPL_IO_LINES_MASK) <= 3)) {
+- link->conf.ConfigIndex = cf->index;
+- for (j = 0; j < 5; j++) {
+- link->io.BasePort1 = base[j];
+- link->io.IOAddrLines = base[j] ? 16 : 3;
+- i = pcmcia_request_io(link, &link->io);
+- if (i == CS_SUCCESS)
+- goto found_port;
+- }
+- }
+- i = next_tuple(link, &tuple, &parse);
+- }
++ if (!pcmcia_loop_config(link, bt3c_check_config_notpicky, NULL))
++ goto found_port;
+
+-found_port:
+- if (i != CS_SUCCESS) {
+- BT_ERR("No usable port range found");
+- cs_error(link, RequestIO, i);
+- goto failed;
+- }
++ BT_ERR("No usable port range found");
++ cs_error(link, RequestIO, -ENODEV);
++ goto failed;
+
++found_port:
+ i = pcmcia_request_irq(link, &link->irq);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestIRQ, i);
+ link->irq.AssignedIRQ = 0;
+ }
+
+ i = pcmcia_request_configuration(link, &link->conf);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestConfiguration, i);
+ goto failed;
+ }
+diff --git a/drivers/bluetooth/btsdio.c b/drivers/bluetooth/btsdio.c
+index b786f61..cda6c7c 100644
+--- a/drivers/bluetooth/btsdio.c
++++ b/drivers/bluetooth/btsdio.c
+@@ -152,7 +152,7 @@ static int btsdio_rx_packet(struct btsdio_data *data)
+
+ err = sdio_readsb(data->func, skb->data, REG_RDAT, len - 4);
+ if (err < 0) {
+- kfree(skb);
++ kfree_skb(skb);
+ return err;
+ }
+
+@@ -162,10 +162,8 @@ static int btsdio_rx_packet(struct btsdio_data *data)
+ bt_cb(skb)->pkt_type = hdr[3];
+
+ err = hci_recv_frame(skb);
+- if (err < 0) {
+- kfree(skb);
++ if (err < 0)
+ return err;
+- }
+
+ sdio_writeb(data->func, 0x00, REG_PC_RRT, NULL);
+
+diff --git a/drivers/bluetooth/btuart_cs.c b/drivers/bluetooth/btuart_cs.c
+index 08f48d5..efd689a 100644
+--- a/drivers/bluetooth/btuart_cs.c
++++ b/drivers/bluetooth/btuart_cs.c
+@@ -293,6 +293,7 @@ static irqreturn_t btuart_interrupt(int irq, void *dev_inst)
+ unsigned int iobase;
+ int boguscount = 0;
+ int iir, lsr;
++ irqreturn_t r = IRQ_NONE;
+
+ BUG_ON(!info->hdev);
+
+@@ -302,6 +303,7 @@ static irqreturn_t btuart_interrupt(int irq, void *dev_inst)
+
+ iir = inb(iobase + UART_IIR) & UART_IIR_ID;
+ while (iir) {
++ r = IRQ_HANDLED;
+
+ /* Clear interrupt */
+ lsr = inb(iobase + UART_LSR);
+@@ -335,7 +337,7 @@ static irqreturn_t btuart_interrupt(int irq, void *dev_inst)
+
+ spin_unlock(&(info->lock));
+
+- return IRQ_HANDLED;
++ return r;
+ }
+
+
+@@ -383,7 +385,7 @@ static void btuart_change_speed(btuart_info_t *info, unsigned int speed)
+ outb(lcr, iobase + UART_LCR); /* Set 8N1 */
+ outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
+
+- /* Turn on interrups */
++ /* Turn on interrupts */
+ outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
+
+ spin_unlock_irqrestore(&(info->lock), flags);
+@@ -586,7 +588,7 @@ static int btuart_probe(struct pcmcia_device *link)
+
+ link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
+ link->io.NumPorts1 = 8;
+- link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
++ link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT;
+ link->irq.IRQInfo1 = IRQ_LEVEL_ID;
+
+ link->irq.Handler = btuart_interrupt;
+@@ -607,102 +609,78 @@ static void btuart_detach(struct pcmcia_device *link)
+ kfree(info);
+ }
+
+-static int get_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
+-{
+- int i;
+-
+- i = pcmcia_get_tuple_data(handle, tuple);
+- if (i != CS_SUCCESS)
+- return i;
+-
+- return pcmcia_parse_tuple(handle, tuple, parse);
+-}
+-
+-static int first_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
++static int btuart_check_config(struct pcmcia_device *p_dev,
++ cistpl_cftable_entry_t *cf,
++ cistpl_cftable_entry_t *dflt,
++ unsigned int vcc,
++ void *priv_data)
+ {
+- if (pcmcia_get_first_tuple(handle, tuple) != CS_SUCCESS)
+- return CS_NO_MORE_ITEMS;
+- return get_tuple(handle, tuple, parse);
++ int *try = priv_data;
++
++ if (cf->vpp1.present & (1 << CISTPL_POWER_VNOM))
++ p_dev->conf.Vpp = cf->vpp1.param[CISTPL_POWER_VNOM] / 10000;
++ if ((cf->io.nwin > 0) && (cf->io.win[0].len == 8) &&
++ (cf->io.win[0].base != 0)) {
++ p_dev->io.BasePort1 = cf->io.win[0].base;
++ p_dev->io.IOAddrLines = (*try == 0) ? 16 :
++ cf->io.flags & CISTPL_IO_LINES_MASK;
++ if (!pcmcia_request_io(p_dev, &p_dev->io))
++ return 0;
++ }
++ return -ENODEV;
+ }
+
+-static int next_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
++static int btuart_check_config_notpicky(struct pcmcia_device *p_dev,
++ cistpl_cftable_entry_t *cf,
++ cistpl_cftable_entry_t *dflt,
++ unsigned int vcc,
++ void *priv_data)
+ {
+- if (pcmcia_get_next_tuple(handle, tuple) != CS_SUCCESS)
+- return CS_NO_MORE_ITEMS;
+- return get_tuple(handle, tuple, parse);
++ static unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
++ int j;
++
++ if ((cf->io.nwin > 0) && ((cf->io.flags & CISTPL_IO_LINES_MASK) <= 3)) {
++ for (j = 0; j < 5; j++) {
++ p_dev->io.BasePort1 = base[j];
++ p_dev->io.IOAddrLines = base[j] ? 16 : 3;
++ if (!pcmcia_request_io(p_dev, &p_dev->io))
++ return 0;
++ }
++ }
++ return -ENODEV;
+ }
+
+ static int btuart_config(struct pcmcia_device *link)
+ {
+- static kio_addr_t base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
+ btuart_info_t *info = link->priv;
+- tuple_t tuple;
+- u_short buf[256];
+- cisparse_t parse;
+- cistpl_cftable_entry_t *cf = &parse.cftable_entry;
+- int i, j, try;
+-
+- /* First pass: look for a config entry that looks normal. */
+- tuple.TupleData = (cisdata_t *) buf;
+- tuple.TupleOffset = 0;
+- tuple.TupleDataMax = 255;
+- tuple.Attributes = 0;
+- tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
+- /* Two tries: without IO aliases, then with aliases */
+- for (try = 0; try < 2; try++) {
+- i = first_tuple(link, &tuple, &parse);
+- while (i != CS_NO_MORE_ITEMS) {
+- if (i != CS_SUCCESS)
+- goto next_entry;
+- if (cf->vpp1.present & (1 << CISTPL_POWER_VNOM))
+- link->conf.Vpp = cf->vpp1.param[CISTPL_POWER_VNOM] / 10000;
+- if ((cf->io.nwin > 0) && (cf->io.win[0].len == 8) && (cf->io.win[0].base != 0)) {
+- link->conf.ConfigIndex = cf->index;
+- link->io.BasePort1 = cf->io.win[0].base;
+- link->io.IOAddrLines = (try == 0) ? 16 : cf->io.flags & CISTPL_IO_LINES_MASK;
+- i = pcmcia_request_io(link, &link->io);
+- if (i == CS_SUCCESS)
+- goto found_port;
+- }
+-next_entry:
+- i = next_tuple(link, &tuple, &parse);
+- }
+- }
++ int i;
++ int try;
++
++ /* First pass: look for a config entry that looks normal.
++ Two tries: without IO aliases, then with aliases */
++ for (try = 0; try < 2; try++)
++ if (!pcmcia_loop_config(link, btuart_check_config, &try))
++ goto found_port;
+
+ /* Second pass: try to find an entry that isn't picky about
+ its base address, then try to grab any standard serial port
+ address, and finally try to get any free port. */
+- i = first_tuple(link, &tuple, &parse);
+- while (i != CS_NO_MORE_ITEMS) {
+- if ((i == CS_SUCCESS) && (cf->io.nwin > 0)
+- && ((cf->io.flags & CISTPL_IO_LINES_MASK) <= 3)) {
+- link->conf.ConfigIndex = cf->index;
+- for (j = 0; j < 5; j++) {
+- link->io.BasePort1 = base[j];
+- link->io.IOAddrLines = base[j] ? 16 : 3;
+- i = pcmcia_request_io(link, &link->io);
+- if (i == CS_SUCCESS)
+- goto found_port;
+- }
+- }
+- i = next_tuple(link, &tuple, &parse);
+- }
++ if (!pcmcia_loop_config(link, btuart_check_config_notpicky, NULL))
++ goto found_port;
+
+-found_port:
+- if (i != CS_SUCCESS) {
+- BT_ERR("No usable port range found");
+- cs_error(link, RequestIO, i);
+- goto failed;
+- }
++ BT_ERR("No usable port range found");
++ cs_error(link, RequestIO, -ENODEV);
++ goto failed;
+
++found_port:
+ i = pcmcia_request_irq(link, &link->irq);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestIRQ, i);
+ link->irq.AssignedIRQ = 0;
+ }
+
+ i = pcmcia_request_configuration(link, &link->conf);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestConfiguration, i);
+ goto failed;
+ }
+diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
+index 12e1089..64238b0 100644
+--- a/drivers/bluetooth/btusb.c
++++ b/drivers/bluetooth/btusb.c
+@@ -2,7 +2,7 @@
+ *
+ * Generic Bluetooth USB driver
+ *
+- * Copyright (C) 2005-2007 Marcel Holtmann <marcel@holtmann.org>
++ * Copyright (C) 2005-2008 Marcel Holtmann <marcel@holtmann.org>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -41,27 +41,144 @@
+ #define BT_DBG(D...)
+ #endif
+
+-#define VERSION "0.1"
++#define VERSION "0.3"
++
++static int ignore_dga;
++static int ignore_csr;
++static int ignore_sniffer;
++static int disable_scofix;
++static int force_scofix;
++static int reset;
++
++static struct usb_driver btusb_driver;
++
++#define BTUSB_IGNORE 0x01
++#define BTUSB_RESET 0x02
++#define BTUSB_DIGIANSWER 0x04
++#define BTUSB_CSR 0x08
++#define BTUSB_SNIFFER 0x10
++#define BTUSB_BCM92035 0x20
++#define BTUSB_BROKEN_ISOC 0x40
++#define BTUSB_WRONG_SCO_MTU 0x80
+
+ static struct usb_device_id btusb_table[] = {
+ /* Generic Bluetooth USB device */
+ { USB_DEVICE_INFO(0xe0, 0x01, 0x01) },
+
++ /* AVM BlueFRITZ! USB v2.0 */
++ { USB_DEVICE(0x057c, 0x3800) },
++
++ /* Bluetooth Ultraport Module from IBM */
++ { USB_DEVICE(0x04bf, 0x030a) },
++
++ /* ALPS Modules with non-standard id */
++ { USB_DEVICE(0x044e, 0x3001) },
++ { USB_DEVICE(0x044e, 0x3002) },
++
++ /* Ericsson with non-standard id */
++ { USB_DEVICE(0x0bdb, 0x1002) },
++
++ /* Canyon CN-BTU1 with HID interfaces */
++ { USB_DEVICE(0x0c10, 0x0000), .driver_info = BTUSB_RESET },
++
+ { } /* Terminating entry */
+ };
+
+ MODULE_DEVICE_TABLE(usb, btusb_table);
+
+ static struct usb_device_id blacklist_table[] = {
++ /* CSR BlueCore devices */
++ { USB_DEVICE(0x0a12, 0x0001), .driver_info = BTUSB_CSR },
++
++ /* Broadcom BCM2033 without firmware */
++ { USB_DEVICE(0x0a5c, 0x2033), .driver_info = BTUSB_IGNORE },
++
++ /* Broadcom BCM2035 */
++ { USB_DEVICE(0x0a5c, 0x2035), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++ { USB_DEVICE(0x0a5c, 0x200a), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Broadcom BCM2045 */
++ { USB_DEVICE(0x0a5c, 0x2039), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++ { USB_DEVICE(0x0a5c, 0x2101), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Broadcom BCM2046 */
++ { USB_DEVICE(0x0a5c, 0x2146), .driver_info = BTUSB_RESET },
++ { USB_DEVICE(0x0a5c, 0x2151), .driver_info = BTUSB_RESET },
++
++ /* Apple MacBook Pro with Broadcom chip */
++ { USB_DEVICE(0x05ac, 0x820f), .driver_info = BTUSB_RESET },
++
++ /* IBM/Lenovo ThinkPad with Broadcom chip */
++ { USB_DEVICE(0x0a5c, 0x201e), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++ { USB_DEVICE(0x0a5c, 0x2110), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Targus ACB10US */
++ { USB_DEVICE(0x0a5c, 0x2100), .driver_info = BTUSB_RESET },
++ { USB_DEVICE(0x0a5c, 0x2154), .driver_info = BTUSB_RESET },
++
++ /* ANYCOM Bluetooth USB-200 and USB-250 */
++ { USB_DEVICE(0x0a5c, 0x2111), .driver_info = BTUSB_RESET },
++
++ /* HP laptop with Broadcom chip */
++ { USB_DEVICE(0x03f0, 0x171d), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Dell laptop with Broadcom chip */
++ { USB_DEVICE(0x413c, 0x8126), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Dell Wireless 370 */
++ { USB_DEVICE(0x413c, 0x8156), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Dell Wireless 410 */
++ { USB_DEVICE(0x413c, 0x8152), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Microsoft Wireless Transceiver for Bluetooth 2.0 */
++ { USB_DEVICE(0x045e, 0x009c), .driver_info = BTUSB_RESET },
++
++ /* Kensington Bluetooth USB adapter */
++ { USB_DEVICE(0x047d, 0x105d), .driver_info = BTUSB_RESET },
++ { USB_DEVICE(0x047d, 0x105e), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* ISSC Bluetooth Adapter v3.1 */
++ { USB_DEVICE(0x1131, 0x1001), .driver_info = BTUSB_RESET },
++
++ /* RTX Telecom based adapters with buggy SCO support */
++ { USB_DEVICE(0x0400, 0x0807), .driver_info = BTUSB_BROKEN_ISOC },
++ { USB_DEVICE(0x0400, 0x080a), .driver_info = BTUSB_BROKEN_ISOC },
++
++ /* CONWISE Technology based adapters with buggy SCO support */
++ { USB_DEVICE(0x0e5e, 0x6622), .driver_info = BTUSB_BROKEN_ISOC },
++
++ /* Belkin F8T012 and F8T013 devices */
++ { USB_DEVICE(0x050d, 0x0012), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++ { USB_DEVICE(0x050d, 0x0013), .driver_info = BTUSB_RESET | BTUSB_WRONG_SCO_MTU },
++
++ /* Belkin F8T016 device */
++ { USB_DEVICE(0x050d, 0x016a), .driver_info = BTUSB_RESET },
++
++ /* Digianswer devices */
++ { USB_DEVICE(0x08fd, 0x0001), .driver_info = BTUSB_DIGIANSWER },
++ { USB_DEVICE(0x08fd, 0x0002), .driver_info = BTUSB_IGNORE },
++
++ /* CSR BlueCore Bluetooth Sniffer */
++ { USB_DEVICE(0x0a12, 0x0002), .driver_info = BTUSB_SNIFFER },
++
++ /* Frontline ComProbe Bluetooth Sniffer */
++ { USB_DEVICE(0x16d3, 0x0002), .driver_info = BTUSB_SNIFFER },
++
+ { } /* Terminating entry */
+ };
+
++#define BTUSB_MAX_ISOC_FRAMES 10
++
+ #define BTUSB_INTR_RUNNING 0
+ #define BTUSB_BULK_RUNNING 1
++#define BTUSB_ISOC_RUNNING 2
+
+ struct btusb_data {
+ struct hci_dev *hdev;
+ struct usb_device *udev;
++ struct usb_interface *intf;
++ struct usb_interface *isoc;
+
+ spinlock_t lock;
+
+@@ -72,10 +189,15 @@ struct btusb_data {
+ struct usb_anchor tx_anchor;
+ struct usb_anchor intr_anchor;
+ struct usb_anchor bulk_anchor;
++ struct usb_anchor isoc_anchor;
+
+ struct usb_endpoint_descriptor *intr_ep;
+ struct usb_endpoint_descriptor *bulk_tx_ep;
+ struct usb_endpoint_descriptor *bulk_rx_ep;
++ struct usb_endpoint_descriptor *isoc_tx_ep;
++ struct usb_endpoint_descriptor *isoc_rx_ep;
++
++ int isoc_altsetting;
+ };
+
+ static void btusb_intr_complete(struct urb *urb)
+@@ -91,6 +213,8 @@ static void btusb_intr_complete(struct urb *urb)
+ return;
+
+ if (urb->status == 0) {
++ hdev->stat.byte_rx += urb->actual_length;
++
+ if (hci_recv_fragment(hdev, HCI_EVENT_PKT,
+ urb->transfer_buffer,
+ urb->actual_length) < 0) {
+@@ -112,7 +236,7 @@ static void btusb_intr_complete(struct urb *urb)
+ }
+ }
+
+-static inline int btusb_submit_intr_urb(struct hci_dev *hdev)
++static int btusb_submit_intr_urb(struct hci_dev *hdev)
+ {
+ struct btusb_data *data = hdev->driver_data;
+ struct urb *urb;
+@@ -122,6 +246,9 @@ static inline int btusb_submit_intr_urb(struct hci_dev *hdev)
+
+ BT_DBG("%s", hdev->name);
+
++ if (!data->intr_ep)
++ return -ENODEV;
++
+ urb = usb_alloc_urb(0, GFP_ATOMIC);
+ if (!urb)
+ return -ENOMEM;
+@@ -149,7 +276,6 @@ static inline int btusb_submit_intr_urb(struct hci_dev *hdev)
+ BT_ERR("%s urb %p submission failed (%d)",
+ hdev->name, urb, -err);
+ usb_unanchor_urb(urb);
+- kfree(buf);
+ }
+
+ usb_free_urb(urb);
+@@ -170,6 +296,8 @@ static void btusb_bulk_complete(struct urb *urb)
+ return;
+
+ if (urb->status == 0) {
++ hdev->stat.byte_rx += urb->actual_length;
++
+ if (hci_recv_fragment(hdev, HCI_ACLDATA_PKT,
+ urb->transfer_buffer,
+ urb->actual_length) < 0) {
+@@ -191,7 +319,7 @@ static void btusb_bulk_complete(struct urb *urb)
+ }
+ }
+
+-static inline int btusb_submit_bulk_urb(struct hci_dev *hdev)
++static int btusb_submit_bulk_urb(struct hci_dev *hdev)
+ {
+ struct btusb_data *data = hdev->driver_data;
+ struct urb *urb;
+@@ -201,6 +329,9 @@ static inline int btusb_submit_bulk_urb(struct hci_dev *hdev)
+
+ BT_DBG("%s", hdev->name);
+
++ if (!data->bulk_rx_ep)
++ return -ENODEV;
++
+ urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!urb)
+ return -ENOMEM;
+@@ -227,7 +358,126 @@ static inline int btusb_submit_bulk_urb(struct hci_dev *hdev)
+ BT_ERR("%s urb %p submission failed (%d)",
+ hdev->name, urb, -err);
+ usb_unanchor_urb(urb);
+- kfree(buf);
++ }
++
++ usb_free_urb(urb);
++
++ return err;
++}
++
++static void btusb_isoc_complete(struct urb *urb)
++{
++ struct hci_dev *hdev = urb->context;
++ struct btusb_data *data = hdev->driver_data;
++ int i, err;
++
++ BT_DBG("%s urb %p status %d count %d", hdev->name,
++ urb, urb->status, urb->actual_length);
++
++ if (!test_bit(HCI_RUNNING, &hdev->flags))
++ return;
++
++ if (urb->status == 0) {
++ for (i = 0; i < urb->number_of_packets; i++) {
++ unsigned int offset = urb->iso_frame_desc[i].offset;
++ unsigned int length = urb->iso_frame_desc[i].actual_length;
++
++ if (urb->iso_frame_desc[i].status)
++ continue;
++
++ hdev->stat.byte_rx += length;
++
++ if (hci_recv_fragment(hdev, HCI_SCODATA_PKT,
++ urb->transfer_buffer + offset,
++ length) < 0) {
++ BT_ERR("%s corrupted SCO packet", hdev->name);
++ hdev->stat.err_rx++;
++ }
++ }
++ }
++
++ if (!test_bit(BTUSB_ISOC_RUNNING, &data->flags))
++ return;
++
++ usb_anchor_urb(urb, &data->isoc_anchor);
++
++ err = usb_submit_urb(urb, GFP_ATOMIC);
++ if (err < 0) {
++ BT_ERR("%s urb %p failed to resubmit (%d)",
++ hdev->name, urb, -err);
++ usb_unanchor_urb(urb);
++ }
++}
++
++static void inline __fill_isoc_descriptor(struct urb *urb, int len, int mtu)
++{
++ int i, offset = 0;
++
++ BT_DBG("len %d mtu %d", len, mtu);
++
++ for (i = 0; i < BTUSB_MAX_ISOC_FRAMES && len >= mtu;
++ i++, offset += mtu, len -= mtu) {
++ urb->iso_frame_desc[i].offset = offset;
++ urb->iso_frame_desc[i].length = mtu;
++ }
++
++ if (len && i < BTUSB_MAX_ISOC_FRAMES) {
++ urb->iso_frame_desc[i].offset = offset;
++ urb->iso_frame_desc[i].length = len;
++ i++;
++ }
++
++ urb->number_of_packets = i;
++}
++
++static int btusb_submit_isoc_urb(struct hci_dev *hdev)
++{
++ struct btusb_data *data = hdev->driver_data;
++ struct urb *urb;
++ unsigned char *buf;
++ unsigned int pipe;
++ int err, size;
++
++ BT_DBG("%s", hdev->name);
++
++ if (!data->isoc_rx_ep)
++ return -ENODEV;
++
++ urb = usb_alloc_urb(BTUSB_MAX_ISOC_FRAMES, GFP_KERNEL);
++ if (!urb)
++ return -ENOMEM;
++
++ size = le16_to_cpu(data->isoc_rx_ep->wMaxPacketSize) *
++ BTUSB_MAX_ISOC_FRAMES;
++
++ buf = kmalloc(size, GFP_KERNEL);
++ if (!buf) {
++ usb_free_urb(urb);
++ return -ENOMEM;
++ }
++
++ pipe = usb_rcvisocpipe(data->udev, data->isoc_rx_ep->bEndpointAddress);
++
++ urb->dev = data->udev;
++ urb->pipe = pipe;
++ urb->context = hdev;
++ urb->complete = btusb_isoc_complete;
++ urb->interval = data->isoc_rx_ep->bInterval;
++
++ urb->transfer_flags = URB_FREE_BUFFER | URB_ISO_ASAP;
++ urb->transfer_buffer = buf;
++ urb->transfer_buffer_length = size;
++
++ __fill_isoc_descriptor(urb, size,
++ le16_to_cpu(data->isoc_rx_ep->wMaxPacketSize));
++
++ usb_anchor_urb(urb, &data->isoc_anchor);
++
++ err = usb_submit_urb(urb, GFP_KERNEL);
++ if (err < 0) {
++ BT_ERR("%s urb %p submission failed (%d)",
++ hdev->name, urb, -err);
++ usb_unanchor_urb(urb);
+ }
+
+ usb_free_urb(urb);
+@@ -272,7 +522,7 @@ static int btusb_open(struct hci_dev *hdev)
+
+ err = btusb_submit_intr_urb(hdev);
+ if (err < 0) {
+- clear_bit(BTUSB_INTR_RUNNING, &hdev->flags);
++ clear_bit(BTUSB_INTR_RUNNING, &data->flags);
+ clear_bit(HCI_RUNNING, &hdev->flags);
+ }
+
+@@ -288,6 +538,11 @@ static int btusb_close(struct hci_dev *hdev)
+ if (!test_and_clear_bit(HCI_RUNNING, &hdev->flags))
+ return 0;
+
++ cancel_work_sync(&data->work);
++
++ clear_bit(BTUSB_ISOC_RUNNING, &data->flags);
++ usb_kill_anchored_urbs(&data->isoc_anchor);
++
+ clear_bit(BTUSB_BULK_RUNNING, &data->flags);
+ usb_kill_anchored_urbs(&data->bulk_anchor);
+
+@@ -349,6 +604,9 @@ static int btusb_send_frame(struct sk_buff *skb)
+ break;
+
+ case HCI_ACLDATA_PKT:
++ if (!data->bulk_tx_ep || hdev->conn_hash.acl_num < 1)
++ return -ENODEV;
++
+ urb = usb_alloc_urb(0, GFP_ATOMIC);
+ if (!urb)
+ return -ENOMEM;
+@@ -363,9 +621,31 @@ static int btusb_send_frame(struct sk_buff *skb)
+ break;
+
+ case HCI_SCODATA_PKT:
++ if (!data->isoc_tx_ep || hdev->conn_hash.sco_num < 1)
++ return -ENODEV;
++
++ urb = usb_alloc_urb(BTUSB_MAX_ISOC_FRAMES, GFP_ATOMIC);
++ if (!urb)
++ return -ENOMEM;
++
++ pipe = usb_sndisocpipe(data->udev,
++ data->isoc_tx_ep->bEndpointAddress);
++
++ urb->dev = data->udev;
++ urb->pipe = pipe;
++ urb->context = skb;
++ urb->complete = btusb_tx_complete;
++ urb->interval = data->isoc_tx_ep->bInterval;
++
++ urb->transfer_flags = URB_ISO_ASAP;
++ urb->transfer_buffer = skb->data;
++ urb->transfer_buffer_length = skb->len;
++
++ __fill_isoc_descriptor(urb, skb->len,
++ le16_to_cpu(data->isoc_tx_ep->wMaxPacketSize));
++
+ hdev->stat.sco_tx++;
+- kfree_skb(skb);
+- return 0;
++ break;
+
+ default:
+ return -EILSEQ;
+@@ -404,22 +684,86 @@ static void btusb_notify(struct hci_dev *hdev, unsigned int evt)
+ schedule_work(&data->work);
+ }
+
++static int inline __set_isoc_interface(struct hci_dev *hdev, int altsetting)
++{
++ struct btusb_data *data = hdev->driver_data;
++ struct usb_interface *intf = data->isoc;
++ struct usb_endpoint_descriptor *ep_desc;
++ int i, err;
++
++ if (!data->isoc)
++ return -ENODEV;
++
++ err = usb_set_interface(data->udev, 1, altsetting);
++ if (err < 0) {
++ BT_ERR("%s setting interface failed (%d)", hdev->name, -err);
++ return err;
++ }
++
++ data->isoc_altsetting = altsetting;
++
++ data->isoc_tx_ep = NULL;
++ data->isoc_rx_ep = NULL;
++
++ for (i = 0; i < intf->cur_altsetting->desc.bNumEndpoints; i++) {
++ ep_desc = &intf->cur_altsetting->endpoint[i].desc;
++
++ if (!data->isoc_tx_ep && usb_endpoint_is_isoc_out(ep_desc)) {
++ data->isoc_tx_ep = ep_desc;
++ continue;
++ }
++
++ if (!data->isoc_rx_ep && usb_endpoint_is_isoc_in(ep_desc)) {
++ data->isoc_rx_ep = ep_desc;
++ continue;
++ }
++ }
++
++ if (!data->isoc_tx_ep || !data->isoc_rx_ep) {
++ BT_ERR("%s invalid SCO descriptors", hdev->name);
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
+ static void btusb_work(struct work_struct *work)
+ {
+ struct btusb_data *data = container_of(work, struct btusb_data, work);
+ struct hci_dev *hdev = data->hdev;
+
+- if (hdev->conn_hash.acl_num == 0) {
++ if (hdev->conn_hash.acl_num > 0) {
++ if (!test_and_set_bit(BTUSB_BULK_RUNNING, &data->flags)) {
++ if (btusb_submit_bulk_urb(hdev) < 0)
++ clear_bit(BTUSB_BULK_RUNNING, &data->flags);
++ else
++ btusb_submit_bulk_urb(hdev);
++ }
++ } else {
+ clear_bit(BTUSB_BULK_RUNNING, &data->flags);
+ usb_kill_anchored_urbs(&data->bulk_anchor);
+- return;
+ }
+
+- if (!test_and_set_bit(BTUSB_BULK_RUNNING, &data->flags)) {
+- if (btusb_submit_bulk_urb(hdev) < 0)
+- clear_bit(BTUSB_BULK_RUNNING, &data->flags);
+- else
+- btusb_submit_bulk_urb(hdev);
++ if (hdev->conn_hash.sco_num > 0) {
++ if (data->isoc_altsetting != 2) {
++ clear_bit(BTUSB_ISOC_RUNNING, &data->flags);
++ usb_kill_anchored_urbs(&data->isoc_anchor);
++
++ if (__set_isoc_interface(hdev, 2) < 0)
++ return;
++ }
++
++ if (!test_and_set_bit(BTUSB_ISOC_RUNNING, &data->flags)) {
++ if (btusb_submit_isoc_urb(hdev) < 0)
++ clear_bit(BTUSB_ISOC_RUNNING, &data->flags);
++ else
++ btusb_submit_isoc_urb(hdev);
++ }
++ } else {
++ clear_bit(BTUSB_ISOC_RUNNING, &data->flags);
++ usb_kill_anchored_urbs(&data->isoc_anchor);
++
++ __set_isoc_interface(hdev, 0);
+ }
+ }
+
+@@ -433,6 +777,7 @@ static int btusb_probe(struct usb_interface *intf,
+
+ BT_DBG("intf %p id %p", intf, id);
+
++ /* interface numbers are hardcoded in the spec */
+ if (intf->cur_altsetting->desc.bInterfaceNumber != 0)
+ return -ENODEV;
+
+@@ -443,6 +788,18 @@ static int btusb_probe(struct usb_interface *intf,
+ id = match;
+ }
+
++ if (id->driver_info == BTUSB_IGNORE)
++ return -ENODEV;
++
++ if (ignore_dga && id->driver_info & BTUSB_DIGIANSWER)
++ return -ENODEV;
++
++ if (ignore_csr && id->driver_info & BTUSB_CSR)
++ return -ENODEV;
++
++ if (ignore_sniffer && id->driver_info & BTUSB_SNIFFER)
++ return -ENODEV;
++
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+@@ -472,6 +829,7 @@ static int btusb_probe(struct usb_interface *intf,
+ }
+
+ data->udev = interface_to_usbdev(intf);
++ data->intf = intf;
+
+ spin_lock_init(&data->lock);
+
+@@ -480,6 +838,7 @@ static int btusb_probe(struct usb_interface *intf,
+ init_usb_anchor(&data->tx_anchor);
+ init_usb_anchor(&data->intr_anchor);
+ init_usb_anchor(&data->bulk_anchor);
++ init_usb_anchor(&data->isoc_anchor);
+
+ hdev = hci_alloc_dev();
+ if (!hdev) {
+@@ -503,7 +862,49 @@ static int btusb_probe(struct usb_interface *intf,
+
+ hdev->owner = THIS_MODULE;
+
+- set_bit(HCI_QUIRK_RESET_ON_INIT, &hdev->quirks);
++ /* interface numbers are hardcoded in the spec */
++ data->isoc = usb_ifnum_to_if(data->udev, 1);
++
++ if (reset || id->driver_info & BTUSB_RESET)
++ set_bit(HCI_QUIRK_RESET_ON_INIT, &hdev->quirks);
++
++ if (force_scofix || id->driver_info & BTUSB_WRONG_SCO_MTU) {
++ if (!disable_scofix)
++ set_bit(HCI_QUIRK_FIXUP_BUFFER_SIZE, &hdev->quirks);
++ }
++
++ if (id->driver_info & BTUSB_BROKEN_ISOC)
++ data->isoc = NULL;
++
++ if (id->driver_info & BTUSB_SNIFFER) {
++ struct usb_device *udev = data->udev;
++
++ if (le16_to_cpu(udev->descriptor.bcdDevice) > 0x997)
++ set_bit(HCI_QUIRK_RAW_DEVICE, &hdev->quirks);
++
++ data->isoc = NULL;
++ }
++
++ if (id->driver_info & BTUSB_BCM92035) {
++ unsigned char cmd[] = { 0x3b, 0xfc, 0x01, 0x00 };
++ struct sk_buff *skb;
++
++ skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
++ if (skb) {
++ memcpy(skb_put(skb, sizeof(cmd)), cmd, sizeof(cmd));
++ skb_queue_tail(&hdev->driver_init, skb);
++ }
++ }
++
++ if (data->isoc) {
++ err = usb_driver_claim_interface(&btusb_driver,
++ data->isoc, data);
++ if (err < 0) {
++ hci_free_dev(hdev);
++ kfree(data);
++ return err;
++ }
++ }
+
+ err = hci_register_dev(hdev);
+ if (err < 0) {
+@@ -529,18 +930,45 @@ static void btusb_disconnect(struct usb_interface *intf)
+
+ hdev = data->hdev;
+
+- usb_set_intfdata(intf, NULL);
++ __hci_dev_hold(hdev);
++
++ usb_set_intfdata(data->intf, NULL);
++
++ if (data->isoc)
++ usb_set_intfdata(data->isoc, NULL);
+
+ hci_unregister_dev(hdev);
+
++ if (intf == data->isoc)
++ usb_driver_release_interface(&btusb_driver, data->intf);
++ else if (data->isoc)
++ usb_driver_release_interface(&btusb_driver, data->isoc);
++
++ __hci_dev_put(hdev);
++
+ hci_free_dev(hdev);
+ }
+
++#ifdef CONFIG_PM
++static int btusb_suspend(struct usb_interface *intf, pm_message_t message)
++{
++ return 0;
++}
++
++static int btusb_resume(struct usb_interface *intf)
++{
++ return 0;
++}
++#endif
+ static struct usb_driver btusb_driver = {
+ .name = "btusb",
+ .probe = btusb_probe,
+ .disconnect = btusb_disconnect,
+ .id_table = btusb_table,
++#ifdef CONFIG_PM
++ .suspend = btusb_suspend,
++ .resume = btusb_resume,
++#endif
+ };
+
+ static int __init btusb_init(void)
+@@ -558,6 +986,24 @@ static void __exit btusb_exit(void)
+ module_init(btusb_init);
+ module_exit(btusb_exit);
+
++module_param(ignore_dga, bool, 0644);
++MODULE_PARM_DESC(ignore_dga, "Ignore devices with id 08fd:0001");
++
++module_param(ignore_csr, bool, 0644);
++MODULE_PARM_DESC(ignore_csr, "Ignore devices with id 0a12:0001");
++
++module_param(ignore_sniffer, bool, 0644);
++MODULE_PARM_DESC(ignore_sniffer, "Ignore devices with id 0a12:0002");
++
++module_param(disable_scofix, bool, 0644);
++MODULE_PARM_DESC(disable_scofix, "Disable fixup of wrong SCO buffer size");
++
++module_param(force_scofix, bool, 0644);
++MODULE_PARM_DESC(force_scofix, "Force fixup of wrong SCO buffers size");
++
++module_param(reset, bool, 0644);
++MODULE_PARM_DESC(reset, "Send HCI reset command on initialization");
++
+ MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("Generic Bluetooth USB driver ver " VERSION);
+ MODULE_VERSION(VERSION);
+diff --git a/drivers/bluetooth/dtl1_cs.c b/drivers/bluetooth/dtl1_cs.c
+index dae45cd..901bdd9 100644
+--- a/drivers/bluetooth/dtl1_cs.c
++++ b/drivers/bluetooth/dtl1_cs.c
+@@ -297,6 +297,7 @@ static irqreturn_t dtl1_interrupt(int irq, void *dev_inst)
+ unsigned char msr;
+ int boguscount = 0;
+ int iir, lsr;
++ irqreturn_t r = IRQ_NONE;
+
+ BUG_ON(!info->hdev);
+
+@@ -307,6 +308,7 @@ static irqreturn_t dtl1_interrupt(int irq, void *dev_inst)
+ iir = inb(iobase + UART_IIR) & UART_IIR_ID;
+ while (iir) {
+
++ r = IRQ_HANDLED;
+ /* Clear interrupt */
+ lsr = inb(iobase + UART_LSR);
+
+@@ -343,11 +345,12 @@ static irqreturn_t dtl1_interrupt(int irq, void *dev_inst)
+ info->ri_latch = msr & UART_MSR_RI;
+ clear_bit(XMIT_WAITING, &(info->tx_state));
+ dtl1_write_wakeup(info);
++ r = IRQ_HANDLED;
+ }
+
+ spin_unlock(&(info->lock));
+
+- return IRQ_HANDLED;
++ return r;
+ }
+
+
+@@ -568,7 +571,7 @@ static int dtl1_probe(struct pcmcia_device *link)
+
+ link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
+ link->io.NumPorts1 = 8;
+- link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
++ link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING | IRQ_HANDLE_PRESENT;
+ link->irq.IRQInfo1 = IRQ_LEVEL_ID;
+
+ link->irq.Handler = dtl1_interrupt;
+@@ -590,75 +593,40 @@ static void dtl1_detach(struct pcmcia_device *link)
+ kfree(info);
+ }
+
+-static int get_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
++static int dtl1_confcheck(struct pcmcia_device *p_dev,
++ cistpl_cftable_entry_t *cf,
++ cistpl_cftable_entry_t *dflt,
++ unsigned int vcc,
++ void *priv_data)
+ {
+- int i;
+-
+- i = pcmcia_get_tuple_data(handle, tuple);
+- if (i != CS_SUCCESS)
+- return i;
+-
+- return pcmcia_parse_tuple(handle, tuple, parse);
+-}
+-
+-static int first_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
+-{
+- if (pcmcia_get_first_tuple(handle, tuple) != CS_SUCCESS)
+- return CS_NO_MORE_ITEMS;
+- return get_tuple(handle, tuple, parse);
+-}
+-
+-static int next_tuple(struct pcmcia_device *handle, tuple_t *tuple, cisparse_t *parse)
+-{
+- if (pcmcia_get_next_tuple(handle, tuple) != CS_SUCCESS)
+- return CS_NO_MORE_ITEMS;
+- return get_tuple(handle, tuple, parse);
++ if ((cf->io.nwin == 1) && (cf->io.win[0].len > 8)) {
++ p_dev->io.BasePort1 = cf->io.win[0].base;
++ p_dev->io.NumPorts1 = cf->io.win[0].len; /*yo */
++ p_dev->io.IOAddrLines = cf->io.flags & CISTPL_IO_LINES_MASK;
++ if (!pcmcia_request_io(p_dev, &p_dev->io))
++ return 0;
++ }
++ return -ENODEV;
+ }
+
+ static int dtl1_config(struct pcmcia_device *link)
+ {
+ dtl1_info_t *info = link->priv;
+- tuple_t tuple;
+- u_short buf[256];
+- cisparse_t parse;
+- cistpl_cftable_entry_t *cf = &parse.cftable_entry;
+ int i;
+
+- tuple.TupleData = (cisdata_t *)buf;
+- tuple.TupleOffset = 0;
+- tuple.TupleDataMax = 255;
+- tuple.Attributes = 0;
+- tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
+-
+ /* Look for a generic full-sized window */
+ link->io.NumPorts1 = 8;
+- i = first_tuple(link, &tuple, &parse);
+- while (i != CS_NO_MORE_ITEMS) {
+- if ((i == CS_SUCCESS) && (cf->io.nwin == 1) && (cf->io.win[0].len > 8)) {
+- link->conf.ConfigIndex = cf->index;
+- link->io.BasePort1 = cf->io.win[0].base;
+- link->io.NumPorts1 = cf->io.win[0].len; /*yo */
+- link->io.IOAddrLines = cf->io.flags & CISTPL_IO_LINES_MASK;
+- i = pcmcia_request_io(link, &link->io);
+- if (i == CS_SUCCESS)
+- break;
+- }
+- i = next_tuple(link, &tuple, &parse);
+- }
+-
+- if (i != CS_SUCCESS) {
+- cs_error(link, RequestIO, i);
++ if (!pcmcia_loop_config(link, dtl1_confcheck, NULL))
+ goto failed;
+- }
+
+ i = pcmcia_request_irq(link, &link->irq);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestIRQ, i);
+ link->irq.AssignedIRQ = 0;
+ }
+
+ i = pcmcia_request_configuration(link, &link->conf);
+- if (i != CS_SUCCESS) {
++ if (i != 0) {
+ cs_error(link, RequestConfiguration, i);
+ goto failed;
+ }
+diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c
+index 696f752..7938062 100644
+--- a/drivers/bluetooth/hci_bcsp.c
++++ b/drivers/bluetooth/hci_bcsp.c
+@@ -39,6 +39,8 @@
+ #include <linux/signal.h>
+ #include <linux/ioctl.h>
+ #include <linux/skbuff.h>
++#include <linux/bitrev.h>
++#include <asm/unaligned.h>
+
+ #include <net/bluetooth/bluetooth.h>
+ #include <net/bluetooth/hci_core.h>
+@@ -124,27 +126,6 @@ static void bcsp_crc_update(u16 *crc, u8 d)
+ *crc = reg;
+ }
+
+-/*
+- Get reverse of generated crc
+-
+- Implementation note
+- The crc generator (bcsp_crc_init() and bcsp_crc_update())
+- creates a reversed crc, so it needs to be swapped back before
+- being passed on.
+-*/
+-static u16 bcsp_crc_reverse(u16 crc)
+-{
+- u16 b, rev;
+-
+- for (b = 0, rev = 0; b < 16; b++) {
+- rev = rev << 1;
+- rev |= (crc & 1);
+- crc = crc >> 1;
+- }
+-
+- return (rev);
+-}
+-
+ /* ---- BCSP core ---- */
+
+ static void bcsp_slip_msgdelim(struct sk_buff *skb)
+@@ -235,10 +216,10 @@ static struct sk_buff *bcsp_prepare_pkt(struct bcsp_struct *bcsp, u8 *data,
+ }
+
+ if (hciextn && chan == 5) {
+- struct hci_command_hdr *hdr = (struct hci_command_hdr *) data;
++ __le16 opcode = ((struct hci_command_hdr *)data)->opcode;
+
+ /* Vendor specific commands */
+- if (hci_opcode_ogf(__le16_to_cpu(hdr->opcode)) == 0x3f) {
++ if (hci_opcode_ogf(__le16_to_cpu(opcode)) == 0x3f) {
+ u8 desc = *(data + HCI_COMMAND_HDR_SIZE);
+ if ((desc & 0xf0) == 0xc0) {
+ data += HCI_COMMAND_HDR_SIZE + 1;
+@@ -296,7 +277,7 @@ static struct sk_buff *bcsp_prepare_pkt(struct bcsp_struct *bcsp, u8 *data,
+
+ /* Put CRC */
+ if (bcsp->use_crc) {
+- bcsp_txmsg_crc = bcsp_crc_reverse(bcsp_txmsg_crc);
++ bcsp_txmsg_crc = bitrev16(bcsp_txmsg_crc);
+ bcsp_slip_one_byte(nskb, (u8) ((bcsp_txmsg_crc >> 8) & 0x00ff));
+ bcsp_slip_one_byte(nskb, (u8) (bcsp_txmsg_crc & 0x00ff));
+ }
+@@ -371,14 +352,14 @@ static int bcsp_flush(struct hci_uart *hu)
+ /* Remove ack'ed packets */
+ static void bcsp_pkt_cull(struct bcsp_struct *bcsp)
+ {
++ struct sk_buff *skb, *tmp;
+ unsigned long flags;
+- struct sk_buff *skb;
+ int i, pkts_to_be_removed;
+ u8 seqno;
+
+ spin_lock_irqsave(&bcsp->unack.lock, flags);
+
+- pkts_to_be_removed = bcsp->unack.qlen;
++ pkts_to_be_removed = skb_queue_len(&bcsp->unack);
+ seqno = bcsp->msgq_txseq;
+
+ while (pkts_to_be_removed) {
+@@ -392,19 +373,19 @@ static void bcsp_pkt_cull(struct bcsp_struct *bcsp)
+ BT_ERR("Peer acked invalid packet");
+
+ BT_DBG("Removing %u pkts out of %u, up to seqno %u",
+- pkts_to_be_removed, bcsp->unack.qlen, (seqno - 1) & 0x07);
++ pkts_to_be_removed, skb_queue_len(&bcsp->unack),
++ (seqno - 1) & 0x07);
+
+- for (i = 0, skb = ((struct sk_buff *) &bcsp->unack)->next; i < pkts_to_be_removed
+- && skb != (struct sk_buff *) &bcsp->unack; i++) {
+- struct sk_buff *nskb;
++ i = 0;
++ skb_queue_walk_safe(&bcsp->unack, skb, tmp) {
++ if (i++ >= pkts_to_be_removed)
++ break;
+
+- nskb = skb->next;
+ __skb_unlink(skb, &bcsp->unack);
+ kfree_skb(skb);
+- skb = nskb;
+ }
+
+- if (bcsp->unack.qlen == 0)
++ if (skb_queue_empty(&bcsp->unack))
+ del_timer(&bcsp->tbcsp);
+
+ spin_unlock_irqrestore(&bcsp->unack.lock, flags);
+@@ -566,6 +547,11 @@ static void bcsp_complete_rx_pkt(struct hci_uart *hu)
+ bcsp->rx_skb = NULL;
+ }
+
++static u16 bscp_get_crc(struct bcsp_struct *bcsp)
++{
++ return get_unaligned_be16(&bcsp->rx_skb->data[bcsp->rx_skb->len - 2]);
++}
++
+ /* Recv data */
+ static int bcsp_recv(struct hci_uart *hu, void *data, int count)
+ {
+@@ -624,14 +610,10 @@ static int bcsp_recv(struct hci_uart *hu, void *data, int count)
+ continue;
+
+ case BCSP_W4_CRC:
+- if (bcsp_crc_reverse(bcsp->message_crc) !=
+- (bcsp->rx_skb->data[bcsp->rx_skb->len - 2] << 8) +
+- bcsp->rx_skb->data[bcsp->rx_skb->len - 1]) {
+-
++ if (bitrev16(bcsp->message_crc) != bscp_get_crc(bcsp)) {
+ BT_ERR ("Checksum failed: computed %04x received %04x",
+- bcsp_crc_reverse(bcsp->message_crc),
+- (bcsp->rx_skb-> data[bcsp->rx_skb->len - 2] << 8) +
+- bcsp->rx_skb->data[bcsp->rx_skb->len - 1]);
++ bitrev16(bcsp->message_crc),
++ bscp_get_crc(bcsp));
+
+ kfree_skb(bcsp->rx_skb);
+ bcsp->rx_state = BCSP_W4_PKT_DELIMITER;
+diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c
+index e68821d..4426bb5 100644
+--- a/drivers/bluetooth/hci_ldisc.c
++++ b/drivers/bluetooth/hci_ldisc.c
+@@ -143,7 +143,7 @@ restart:
+ int len;
+
+ set_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
+- len = tty->driver->write(tty, skb->data, skb->len);
++ len = tty->ops->write(tty, skb->data, skb->len);
+ hdev->stat.byte_tx += len;
+
+ skb_pull(skb, len);
+@@ -190,8 +190,7 @@ static int hci_uart_flush(struct hci_dev *hdev)
+
+ /* Flush any pending characters in the driver and discipline. */
+ tty_ldisc_flush(tty);
+- if (tty->driver && tty->driver->flush_buffer)
+- tty->driver->flush_buffer(tty);
++ tty_driver_flush_buffer(tty);
+
+ if (test_bit(HCI_UART_PROTO_SET, &hu->flags))
+ hu->proto->flush(hu);
+@@ -208,6 +207,7 @@ static int hci_uart_close(struct hci_dev *hdev)
+ return 0;
+
+ hci_uart_flush(hdev);
++ hdev->flush = NULL;
+ return 0;
+ }
+
+@@ -282,11 +282,9 @@ static int hci_uart_tty_open(struct tty_struct *tty)
+ /* FIXME: why is this needed. Note don't use ldisc_ref here as the
+ open path is before the ldisc is referencable */
+
+- if (tty->ldisc.flush_buffer)
+- tty->ldisc.flush_buffer(tty);
+-
+- if (tty->driver && tty->driver->flush_buffer)
+- tty->driver->flush_buffer(tty);
++ if (tty->ldisc.ops->flush_buffer)
++ tty->ldisc.ops->flush_buffer(tty);
++ tty_driver_flush_buffer(tty);
+
+ return 0;
+ }
+@@ -372,9 +370,7 @@ static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, char *f
+ hu->hdev->stat.byte_rx += count;
+ spin_unlock(&hu->rx_lock);
+
+- if (test_and_clear_bit(TTY_THROTTLED, &tty->flags) &&
+- tty->driver->unthrottle)
+- tty->driver->unthrottle(tty);
++ tty_unthrottle(tty);
+ }
+
+ static int hci_uart_register_dev(struct hci_uart *hu)
+@@ -488,7 +484,7 @@ static int hci_uart_tty_ioctl(struct tty_struct *tty, struct file * file,
+ return -EUNATCH;
+
+ default:
+- err = n_tty_ioctl(tty, file, cmd, arg);
++ err = n_tty_ioctl_helper(tty, file, cmd, arg);
+ break;
+ };
+
+@@ -518,7 +514,7 @@ static unsigned int hci_uart_tty_poll(struct tty_struct *tty,
+
+ static int __init hci_uart_init(void)
+ {
+- static struct tty_ldisc hci_uart_ldisc;
++ static struct tty_ldisc_ops hci_uart_ldisc;
+ int err;
+
+ BT_INFO("HCI UART driver ver %s", VERSION);
+@@ -581,7 +577,7 @@ module_exit(hci_uart_exit);
+ module_param(reset, bool, 0644);
+ MODULE_PARM_DESC(reset, "Send HCI reset command on initialization");
+
+-MODULE_AUTHOR("Maxim Krasnyansky <maxk@qualcomm.com>, Marcel Holtmann <marcel@holtmann.org>");
++MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("Bluetooth HCI UART driver ver " VERSION);
+ MODULE_VERSION(VERSION);
+ MODULE_LICENSE("GPL");
+diff --git a/drivers/bluetooth/hci_usb.c b/drivers/bluetooth/hci_usb.c
+index 98a9cde..3c45392 100644
+--- a/drivers/bluetooth/hci_usb.c
++++ b/drivers/bluetooth/hci_usb.c
+@@ -62,19 +62,18 @@
+ #define URB_ZERO_PACKET 0
+ #endif
+
+-static int ignore = 0;
+-static int ignore_dga = 0;
+-static int ignore_csr = 0;
+-static int ignore_sniffer = 0;
+-static int disable_scofix = 0;
+-static int force_scofix = 0;
+-static int reset = 0;
++static int ignore_dga;
++static int ignore_csr;
++static int ignore_sniffer;
++static int disable_scofix;
++static int force_scofix;
++static int reset;
+
+ #ifdef CONFIG_BT_HCIUSB_SCO
+ static int isoc = 2;
+ #endif
+
+-#define VERSION "2.9"
++#define VERSION "2.10"
+
+ static struct usb_driver hci_usb_driver;
+
+@@ -111,10 +110,12 @@ static struct usb_device_id blacklist_ids[] = {
+ { USB_DEVICE(0x0a5c, 0x2033), .driver_info = HCI_IGNORE },
+
+ /* Broadcom BCM2035 */
++ { USB_DEVICE(0x0a5c, 0x2035), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
+ { USB_DEVICE(0x0a5c, 0x200a), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
+ { USB_DEVICE(0x0a5c, 0x2009), .driver_info = HCI_BCM92035 },
+
+ /* Broadcom BCM2045 */
++ { USB_DEVICE(0x0a5c, 0x2039), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
+ { USB_DEVICE(0x0a5c, 0x2101), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
+
+ /* IBM/Lenovo ThinkPad with Broadcom chip */
+@@ -132,6 +133,13 @@ static struct usb_device_id blacklist_ids[] = {
+
+ /* Dell laptop with Broadcom chip */
+ { USB_DEVICE(0x413c, 0x8126), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
++ /* Dell Wireless 370 */
++ { USB_DEVICE(0x413c, 0x8156), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
++ /* Dell Wireless 410 */
++ { USB_DEVICE(0x413c, 0x8152), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
++
++ /* Broadcom 2046 */
++ { USB_DEVICE(0x0a5c, 0x2151), .driver_info = HCI_RESET },
+
+ /* Microsoft Wireless Transceiver for Bluetooth 2.0 */
+ { USB_DEVICE(0x045e, 0x009c), .driver_info = HCI_RESET },
+@@ -147,6 +155,9 @@ static struct usb_device_id blacklist_ids[] = {
+ { USB_DEVICE(0x0400, 0x0807), .driver_info = HCI_BROKEN_ISOC },
+ { USB_DEVICE(0x0400, 0x080a), .driver_info = HCI_BROKEN_ISOC },
+
++ /* CONWISE Technology based adapters with buggy SCO support */
++ { USB_DEVICE(0x0e5e, 0x6622), .driver_info = HCI_BROKEN_ISOC },
++
+ /* Belkin F8T012 and F8T013 devices */
+ { USB_DEVICE(0x050d, 0x0012), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
+ { USB_DEVICE(0x050d, 0x0013), .driver_info = HCI_RESET | HCI_WRONG_SCO_MTU },
+@@ -260,7 +271,7 @@ static int hci_usb_intr_rx_submit(struct hci_usb *husb)
+ BT_ERR("%s intr rx submit failed urb %p err %d",
+ husb->hdev->name, urb, err);
+ _urb_unlink(_urb);
+- _urb_free(_urb);
++ kfree(_urb);
+ kfree(buf);
+ }
+ return err;
+@@ -297,7 +308,7 @@ static int hci_usb_bulk_rx_submit(struct hci_usb *husb)
+ BT_ERR("%s bulk rx submit failed urb %p err %d",
+ husb->hdev->name, urb, err);
+ _urb_unlink(_urb);
+- _urb_free(_urb);
++ kfree(_urb);
+ kfree(buf);
+ }
+ return err;
+@@ -348,7 +359,7 @@ static int hci_usb_isoc_rx_submit(struct hci_usb *husb)
+ BT_ERR("%s isoc rx submit failed urb %p err %d",
+ husb->hdev->name, urb, err);
+ _urb_unlink(_urb);
+- _urb_free(_urb);
++ kfree(_urb);
+ kfree(buf);
+ }
+ return err;
+@@ -426,7 +437,7 @@ static void hci_usb_unlink_urbs(struct hci_usb *husb)
+ husb->hdev->name, _urb, _urb->type, urb);
+ kfree(urb->setup_packet);
+ kfree(urb->transfer_buffer);
+- _urb_free(_urb);
++ kfree(_urb);
+ }
+ }
+ }
+@@ -485,7 +496,7 @@ static inline int hci_usb_send_ctrl(struct hci_usb *husb, struct sk_buff *skb)
+
+ dr = kmalloc(sizeof(*dr), GFP_ATOMIC);
+ if (!dr) {
+- _urb_free(_urb);
++ kfree(_urb);
+ return -ENOMEM;
+ }
+ } else
+@@ -789,7 +800,7 @@ static int hci_usb_probe(struct usb_interface *intf, const struct usb_device_id
+ id = match;
+ }
+
+- if (ignore || id->driver_info & HCI_IGNORE)
++ if (id->driver_info & HCI_IGNORE)
+ return -ENODEV;
+
+ if (ignore_dga && id->driver_info & HCI_DIGIANSWER)
+@@ -1096,9 +1107,6 @@ static void __exit hci_usb_exit(void)
+ module_init(hci_usb_init);
+ module_exit(hci_usb_exit);
+
+-module_param(ignore, bool, 0644);
+-MODULE_PARM_DESC(ignore, "Ignore devices from the matching table");
+-
+ module_param(ignore_dga, bool, 0644);
+ MODULE_PARM_DESC(ignore_dga, "Ignore devices with id 08fd:0001");
+
+@@ -1122,7 +1130,7 @@ module_param(isoc, int, 0644);
+ MODULE_PARM_DESC(isoc, "Set isochronous transfers for SCO over HCI support");
+ #endif
+
+-MODULE_AUTHOR("Maxim Krasnyansky <maxk@qualcomm.com>, Marcel Holtmann <marcel@holtmann.org>");
++MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("Bluetooth HCI USB driver ver " VERSION);
+ MODULE_VERSION(VERSION);
+ MODULE_LICENSE("GPL");
+diff --git a/drivers/bluetooth/hci_usb.h b/drivers/bluetooth/hci_usb.h
+index 56cd3a9..8e65991 100644
+--- a/drivers/bluetooth/hci_usb.h
++++ b/drivers/bluetooth/hci_usb.h
+@@ -60,11 +60,6 @@ struct _urb {
+ struct urb urb;
+ };
+
+-static inline void _urb_free(struct _urb *_urb)
+-{
+- kfree(_urb);
+-}
+-
+ static inline void _urb_queue_init(struct _urb_queue *q)
+ {
+ INIT_LIST_HEAD(&q->head);
+@@ -75,7 +70,8 @@ static inline void _urb_queue_head(struct _urb_queue *q, struct _urb *_urb)
+ {
+ unsigned long flags;
+ spin_lock_irqsave(&q->lock, flags);
+- list_add(&_urb->list, &q->head); _urb->queue = q;
++ /* _urb_unlink needs to know which spinlock to use, thus smp_mb(). */
++ _urb->queue = q; smp_mb(); list_add(&_urb->list, &q->head);
+ spin_unlock_irqrestore(&q->lock, flags);
+ }
+
+@@ -83,19 +79,23 @@ static inline void _urb_queue_tail(struct _urb_queue *q, struct _urb *_urb)
+ {
+ unsigned long flags;
+ spin_lock_irqsave(&q->lock, flags);
+- list_add_tail(&_urb->list, &q->head); _urb->queue = q;
++ /* _urb_unlink needs to know which spinlock to use, thus smp_mb(). */
++ _urb->queue = q; smp_mb(); list_add_tail(&_urb->list, &q->head);
+ spin_unlock_irqrestore(&q->lock, flags);
+ }
+
+ static inline void _urb_unlink(struct _urb *_urb)
+ {
+- struct _urb_queue *q = _urb->queue;
++ struct _urb_queue *q;
+ unsigned long flags;
+- if (q) {
+- spin_lock_irqsave(&q->lock, flags);
+- list_del(&_urb->list); _urb->queue = NULL;
+- spin_unlock_irqrestore(&q->lock, flags);
+- }
++
++ smp_mb();
++ q = _urb->queue;
++ /* If q is NULL, it will die at easy-to-debug NULL pointer dereference.
++ No need to BUG(). */
++ spin_lock_irqsave(&q->lock, flags);
++ list_del(&_urb->list); _urb->queue = NULL;
++ spin_unlock_irqrestore(&q->lock, flags);
+ }
+
+ struct hci_usb {
+diff --git a/drivers/bluetooth/hci_vhci.c b/drivers/bluetooth/hci_vhci.c
+index 0638730..7320a71 100644
+--- a/drivers/bluetooth/hci_vhci.c
++++ b/drivers/bluetooth/hci_vhci.c
+@@ -28,6 +28,7 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/slab.h>
++#include <linux/smp_lock.h>
+ #include <linux/types.h>
+ #include <linux/errno.h>
+ #include <linux/sched.h>
+@@ -263,9 +264,11 @@ static int vhci_open(struct inode *inode, struct file *file)
+ skb_queue_head_init(&data->readq);
+ init_waitqueue_head(&data->read_wait);
+
++ lock_kernel();
+ hdev = hci_alloc_dev();
+ if (!hdev) {
+ kfree(data);
++ unlock_kernel();
+ return -ENOMEM;
+ }
+
+@@ -286,10 +289,12 @@ static int vhci_open(struct inode *inode, struct file *file)
+ BT_ERR("Can't register HCI device");
+ kfree(data);
+ hci_free_dev(hdev);
++ unlock_kernel();
+ return -EBUSY;
+ }
+
+ file->private_data = data;
++ unlock_kernel();
+
+ return nonseekable_open(inode, file);
+ }
+@@ -313,18 +318,21 @@ static int vhci_release(struct inode *inode, struct file *file)
+ static int vhci_fasync(int fd, struct file *file, int on)
+ {
+ struct vhci_data *data = file->private_data;
+- int err;
++ int err = 0;
+
++ lock_kernel();
+ err = fasync_helper(fd, file, on, &data->fasync);
+ if (err < 0)
+- return err;
++ goto out;
+
+ if (on)
+ data->flags |= VHCI_FASYNC;
+ else
+ data->flags &= ~VHCI_FASYNC;
+
+- return 0;
++out:
++ unlock_kernel();
++ return err;
+ }
+
+ static const struct file_operations vhci_fops = {
+@@ -369,7 +377,7 @@ module_exit(vhci_exit);
+ module_param(minor, int, 0444);
+ MODULE_PARM_DESC(minor, "Miscellaneous minor device number");
+
+-MODULE_AUTHOR("Maxim Krasnyansky <maxk@qualcomm.com>, Marcel Holtmann <marcel@holtmann.org>");
++MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
+ MODULE_DESCRIPTION("Bluetooth virtual HCI driver ver " VERSION);
+ MODULE_VERSION(VERSION);
+ MODULE_LICENSE("GPL");
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index 5696162..ecdea3c 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -1055,5 +1055,18 @@ config S3C_MEM
+
+ If unsure, say Y.
+
++choice
++ prompt "HHTECH MID GPIO"
++ help
++ Select LCD either 4.3'' or 7 ''
++ config LCD_4
++ bool "Support for 4.3 inch LCD"
++ help
++ for HHTECH 4.3 inch, provide sysfs interface to APP
++ config LCD_7
++ bool "Support for 7 inch LCD"
++ help
++ for HHTECH 7 inch LCD
++endchoice
+ endmenu
+
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index 8846ea7..7e08964 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -7,7 +7,7 @@
+ #
+ FONTMAPFILE = cp437.uni
+
+-obj-y += mem.o random.o tty_io.o n_tty.o tty_ioctl.o
++obj-y += mem.o random.o tty_io.o n_tty.o tty_ioctl.o
+
+ obj-$(CONFIG_LEGACY_PTYS) += pty.o
+ obj-$(CONFIG_UNIX98_PTYS) += pty.o
+@@ -112,6 +112,8 @@ obj-$(CONFIG_JS_RTC) += js-rtc.o
+ js-rtc-y = rtc.o
+
+ obj-$(CONFIG_S3C_MEM) += s3c_mem.o
++obj-$(CONFIG_LCD_4) += hhtech_gpio.o
++obj-$(CONFIG_LCD_7) += hhtech_gpio.o
+
+ # Files generated that shall be removed upon make clean
+ clean-files := consolemap_deftbl.c defkeymap.c
+diff --git a/drivers/char/apm-emulation.c b/drivers/char/apm-emulation.c
+index 17d5431..fe9f638 100644
+--- a/drivers/char/apm-emulation.c
++++ b/drivers/char/apm-emulation.c
+@@ -108,6 +108,7 @@ static DEFINE_MUTEX(state_lock);
+ static const char driver_version[] = "1.13"; /* no spaces */
+
+
++extern unsigned int s3c_adc_value(unsigned int s3c_adc_port);
+
+ /*
+ * Compatibility cruft until the IPAQ people move over to the new
+@@ -115,6 +116,13 @@ static const char driver_version[] = "1.13"; /* no spaces */
+ */
+ static void __apm_get_power_status(struct apm_power_info *info)
+ {
++ int battery_current_charge = s3c_adc_value(0);
++ int battery_reference_charge = s3c_adc_value(1);
++ while(battery_reference_charge > 3050 || battery_reference_charge < 3020) {
++ battery_current_charge = s3c_adc_value(0);
++ battery_reference_charge = s3c_adc_value(1);
++ }
++ info->battery_life = battery_current_charge * 100 / battery_reference_charge;
+ }
+
+ /*
+diff --git a/drivers/char/hhtech_gpio.c b/drivers/char/hhtech_gpio.c
+new file mode 100644
+index 0000000..b3a2fd8
+--- /dev/null
++++ b/drivers/char/hhtech_gpio.c
+@@ -0,0 +1,883 @@
++/*
++ * S3C64XX GPIO Driver
++ *
++ * Copyright (C) 2008 - 2009 HHTECH.
++ *
++ * Author: <wk@hhcn.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this progSoftwareram; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/platform_device.h>
++#include <linux/workqueue.h>
++#include <linux/sysfs.h>
++#include <linux/sysdev.h>
++#include <linux/fs.h>
++#include <linux/gpio_keys.h>
++#include <asm/gpio.h>
++#include <linux/delay.h>
++#include <asm/io.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++
++#include <asm/plat-s3c/regs-rtc.h>
++#include <asm/plat-s3c24xx/pm.h>
++#include <linux/reboot.h>
++#include <linux/suspend.h>
++#include <asm/plat-s3c64xx/hhtech_gpio.h>
++
++#if defined(CONFIG_LCD_4)
++static unsigned int system_flag = 0;
++#else
++static unsigned int system_flag = 1;
++#endif
++
++static struct delayed_work headp_detect_work;
++static struct delayed_work battery_work;
++int current_battery = 0;
++EXPORT_SYMBOL(current_battery);
++static int user_disable_speaker = 0;
++
++unsigned long rtc_wakeup_time = 30 * 60;
++EXPORT_SYMBOL(rtc_wakeup_time);
++
++unsigned int wakeup_status = 0; // 0: waked up by external IRQ; 1: waked up by RTC
++EXPORT_SYMBOL(wakeup_status);
++
++/* ################# setting ################## */
++
++// HHTECH set system power enable
++static void set_sys_power(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_PWR_EN, 0); //power on
++ else
++ gpio_set_value(GPIO_PWR_EN, 1); //pwoer off
++}
++
++// HHTECH set Charging mode
++static void set_charge_mode(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_CHARGER_EN, 1); //860ma
++ else
++ gpio_set_value(GPIO_CHARGER_EN, 0); //200ma
++}
++
++// HHTECH set backlight MP1530 enable
++static void set_backlight_en(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_LCD_BLIGHT_EN, 1); //enable
++ else
++ gpio_set_value(GPIO_LCD_BLIGHT_EN, 0); //disable
++}
++
++
++// HHTECH set Vidoe amplifier switch
++static void set_video_amp(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_VIDEOAMP_EN, 1); //open
++ else
++ gpio_set_value(GPIO_VIDEOAMP_EN, 0); //close
++}
++
++// HHTECH set USB system (HOST and OTG) power enable
++static void set_usb_syspwr_en(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_USB_EN, 1); //open
++ else
++ gpio_set_value(GPIO_USB_EN, 0); //close
++}
++
++// HHTECH set USB HOST power enable
++static void set_usb_hostpwr_en(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_USB_HOSTPWR_EN, 1); //open
++ else
++ gpio_set_value(GPIO_USB_HOSTPWR_EN, 0); //close
++}
++
++// HHTECH set USB OTG DRV enable
++static void set_usb_otgdrv_en(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_USB_OTGDRV_EN, 1); //open
++ else
++ gpio_set_value(GPIO_USB_OTGDRV_EN, 0); //close
++}
++
++// HHTECH set power hold enable
++static void set_pwr_key(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_PWR_HOLD, 1);
++ else
++ gpio_set_value(GPIO_PWR_HOLD, 0);
++}
++
++// HHTECH set speaker
++static void set_speaker_en(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_SPEAKER_EN, 1); //open
++ else
++ gpio_set_value(GPIO_SPEAKER_EN, 0); //close
++}
++
++// HHTECH set wifi
++static void set_wifi_en(int sw)
++{
++ if (sw) {
++ gpio_set_value(GPIO_WIFI_EN, 1); //open
++ gpio_direction_output(GPIO_WIFI_RESET, 0);
++ mdelay(100);
++ gpio_set_value(GPIO_WIFI_RESET, 1);
++ //Release reset
++ gpio_direction_input(GPIO_WIFI_RESET);
++ } else
++ gpio_set_value(GPIO_WIFI_EN, 0); //close
++}
++
++// HHTECH set led1 and led2
++static void set_led1_en(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_LED1_EN, 0); //turn on
++ else
++ gpio_set_value(GPIO_LED1_EN, 1); //turn off
++}
++
++static void set_led2_en(int sw)
++{
++ if (sw)
++ gpio_set_value(GPIO_LED2_EN, 0);
++ else
++ gpio_set_value(GPIO_LED2_EN, 1);
++}
++
++/*@@@@@@@@@@@@@@@@@@@@@@@ sysfs interface @@@@@@@@@@@*/
++
++#ifdef CONFIG_SYSFS
++static ssize_t hhtech_sysfs_show_dc(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++#if defined (CONFIG_LCD_4)
++ strcpy(buf, gpio_get_value(GPIO_DC_DETE) ? "on" : "off");
++#else
++ strcpy(buf, gpio_get_value(GPIO_DC_DETE) ? "off" : "on");
++#endif
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static ssize_t hhtech_sysfs_show_sd(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, gpio_get_value(GPIO_SD_WP) ? "off" : "on");
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static ssize_t hhtech_sysfs_show_system_flag(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, system_flag ? "1" : "0");
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static ssize_t hhtech_sysfs_show_headp(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, gpio_get_value(GPIO_HEADPHONE_S) ? "on" : "off");
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static ssize_t hhtech_sysfs_show_blight_s(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, gpio_get_value(GPIO_LCD_BLIGHT_S) ? "on" : "off");
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++extern unsigned int s3c_adc_value(unsigned int s3c_adc_port);
++static int read_battery(void)
++{
++ int battery_life = 0, reference_value = 0;
++ static int old_battery_life = 0, old_reference_value = 0;
++
++ //ref voltage:2.4V,battery max :4.2V
++ if ((battery_life = s3c_adc_value(0)) == 0) {
++ if (old_battery_life == 0) {
++ while (!(battery_life = s3c_adc_value(0)));
++ old_battery_life = battery_life;
++ } else
++ battery_life = old_battery_life;
++ }
++ if ((reference_value = s3c_adc_value(1)) == 0) {
++ if (old_reference_value == 0) {
++ while (!(reference_value = s3c_adc_value(1)));
++ old_reference_value = reference_value;
++ } else
++ reference_value = old_reference_value;
++ }
++ battery_life = (battery_life * 24000) / (reference_value * 42);
++
++ return battery_life;
++}
++
++static int get_battery_life(void)
++{
++ int i;
++ int count = 0;
++ int battery_life = 1000;//Default max power
++ int battery_life_sum = 0;
++ for (i = 0; i < 10; i++) {
++ int tmp = read_battery();
++ if (tmp < 700 || tmp > 1000)
++ continue;
++ battery_life_sum += tmp;
++ count++;
++ }
++ if (count)
++ battery_life = battery_life_sum / count;
++ return battery_life;
++}
++
++extern void battery_update_work(struct work_struct* work)
++{
++ int dc_status;
++
++#if defined (CONFIG_LCD_4)
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 1 : 0;
++#else
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 0 : 1;
++#endif
++
++ current_battery = get_battery_life();
++ if (current_battery < 785 && dc_status == 0)
++ set_sys_power(0);
++ schedule_delayed_work(&battery_work, 30 * HZ);
++}
++
++static ssize_t hhtech_sysfs_show_battery(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ char s[20];
++
++ // printk("ADC voltage value=%u,conference voltage =%u \n",s3c_adc_value(0),s3c_adc_value(1));//HHTECH wk
++ sprintf(s,"%d", current_battery);
++ strcpy(buf, s);
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static ssize_t hhtech_sysfs_show_usbhost(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, gpio_get_value(GPIO_USB_HOST_STATUS) ? "on" : "off");
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static ssize_t hhtech_sysfs_show_usbotg(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, gpio_get_value(GPIO_USB_OTG_STATUS) ? "on" : "off");
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static ssize_t hhtech_sysfs_charge_s(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int s=(gpio_get_value(GPIO_CHARG_S1)<<1) + gpio_get_value(GPIO_CHARG_S2);
++ switch (s) {
++ case 0:
++ strcpy(buf,"0");
++ break;
++ case 1:
++ strcpy(buf,"1");
++ break;
++ case 2:
++ strcpy(buf,"2");
++ break;
++ case 3:
++ strcpy(buf,"3");
++ break;
++ }
++ strcat(buf, "\n");
++ return strlen(buf);
++}
++
++static int hhtech_sysfs_show_power(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_PWR_EN));
++}
++
++static ssize_t hhtech_sysfs_store_power(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++// int val = simple_strtoul(buf, NULL, 0);
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_sys_power(1); //poweron
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_sys_power(0); //poweroff
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_charge(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_CHARGER_EN));
++}
++
++static ssize_t hhtech_sysfs_store_charge(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_charge_mode(1); //860ma
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_charge_mode(0); //200ma
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_blight(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_LCD_BLIGHT_EN));
++}
++
++static ssize_t hhtech_sysfs_store_blight(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_backlight_en(1); // enable MP1530
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_backlight_en(0); //disable
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_amp(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_VIDEOAMP_EN));
++}
++
++static ssize_t hhtech_sysfs_store_amp(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_video_amp(1); // open Vidoe amplifier output
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_video_amp(0); // close
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_usbpwr(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_USB_EN));
++}
++
++static ssize_t hhtech_sysfs_store_usbpwr(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_usb_syspwr_en(1); // USB system power enable
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_usb_syspwr_en(0); // disable
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_usbhostpwr(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_USB_HOSTPWR_EN));
++}
++
++static ssize_t hhtech_sysfs_store_usbhostpwr(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_usb_hostpwr_en(1); // USB system power enable
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_usb_hostpwr_en(0); // disable
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_usbotgdrv(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_USB_OTGDRV_EN));
++}
++
++static ssize_t hhtech_sysfs_store_usbotgdrv(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_usb_otgdrv_en(1);
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_usb_otgdrv_en(0);
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_speaker(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_SPEAKER_EN));
++}
++
++static ssize_t hhtech_sysfs_store_speaker(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0) {
++ if (!gpio_get_value(GPIO_HEADPHONE_S))
++ set_speaker_en(1); // speaker enable
++ user_disable_speaker = 0;
++ } else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0) {
++ set_speaker_en(0); // disable
++ user_disable_speaker = 1;
++ } else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_wifi(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_WIFI_EN));
++}
++
++static ssize_t hhtech_sysfs_store_wifi(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_wifi_en(1); // wifi enable
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_wifi_en(0); // disable
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_led1(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_LED1_EN));
++}
++
++static ssize_t hhtech_sysfs_store_led1(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_led1_en(1);
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_led1_en(0);
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_led2(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", gpio_get_value(GPIO_LED2_EN));
++}
++
++static ssize_t hhtech_sysfs_store_led2(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ if (len < 1)
++ return -EINVAL;
++
++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0)
++ set_led2_en(1);
++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0)
++ set_led2_en(0);
++ else
++ return -EINVAL;
++ return len;
++}
++
++static int hhtech_sysfs_show_rtc_wk_time(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", rtc_wakeup_time);
++}
++
++static ssize_t hhtech_sysfs_store_rtc_wk_time(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t len)
++{
++ unsigned long value = simple_strtoul(buf, NULL, 10);
++
++ if (len < 1)
++ return -EINVAL;
++
++ if (value < 0 || value > 2 * 60 * 60)
++ return -ERANGE;
++ else
++ rtc_wakeup_time = value;
++ return len;
++}
++
++static int hhtech_sysfs_show_wk_status(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ return snprintf(buf, PAGE_SIZE, "%d\n", wakeup_status);
++}
++
++ #if defined (CONFIG_LCD_7)
++/* USB host protect status change Interrupt handle */
++static irqreturn_t usbhost_status_irq(int irq, void *dev_id)
++{
++ int pin_level = gpio_get_value(GPIO_USB_HOST_STATUS);
++ __raw_writel(__raw_readl(S3C_EINTMASK)&(~(0x1 << 18)), S3C_EINTMASK); // mask the irq
++ printk(KERN_DEBUG "Usb host status: %d\n", pin_level);
++ if (0 == pin_level) {
++ gpio_direction_output(GPIO_USB_OTGDRV_EN, 0);
++ gpio_direction_output(GPIO_USB_EN, 0);
++ __raw_writel((__raw_readl(S3C_EINTCON1) & ~(0xf << 4)) |
++ (S3C_EXTINT_FALLEDGE << 4), S3C_EINTCON1); // enable the irq again
++ }
++
++ return IRQ_HANDLED;
++}
++ #endif
++
++/* USB otg protect status change Interrupt handle */
++static irqreturn_t usbotg_status_irq(int irq, void *dev_id)
++{
++ int pin_level = gpio_get_value(GPIO_USB_OTG_STATUS);
++ __raw_writel(__raw_readl(S3C_EINTMASK)&(~(0x1 << 19)), S3C_EINTMASK); // mask the irq
++ printk(KERN_DEBUG "Usb otg status: %d\n", pin_level);
++ if (0 == pin_level) {
++ gpio_direction_output(GPIO_USB_HOSTPWR_EN, 0);
++ gpio_direction_output(GPIO_USB_EN, 0);
++ __raw_writel((__raw_readl(S3C_EINTCON1) & ~(0xf << 4)) |
++ (S3C_EXTINT_FALLEDGE << 4), S3C_EINTCON1); // enable the irq again
++ }
++
++ return IRQ_HANDLED;
++}
++
++extern void headp_update_volume(struct work_struct* work);
++
++/* headphone plug in and out Interrupt handle */
++static irqreturn_t headp_irq(int irq, void *dev_id)
++{
++ int pin_level = gpio_get_value(GPIO_HEADPHONE_S);
++ __raw_writel(__raw_readl(S3C_EINTMASK)&(~(0x1 << 20)), S3C_EINTMASK);
++ if (user_disable_speaker == 0) {
++ if (pin_level)
++ gpio_set_value(GPIO_SPEAKER_EN, 0);
++ else
++ gpio_set_value(GPIO_SPEAKER_EN, 1);
++ }
++ cancel_delayed_work(&headp_detect_work);
++ schedule_delayed_work(&headp_detect_work, msecs_to_jiffies(80));
++ return IRQ_HANDLED;
++}
++
++static DEVICE_ATTR(system_flag, 0444, hhtech_sysfs_show_system_flag, NULL);
++static DEVICE_ATTR(headphone_s, 0444, hhtech_sysfs_show_headp, NULL);
++static DEVICE_ATTR(dc_s, 0444, hhtech_sysfs_show_dc, NULL);
++static DEVICE_ATTR(sd_s, 0444, hhtech_sysfs_show_sd, NULL);
++static DEVICE_ATTR(charge_s, 0444,hhtech_sysfs_charge_s , NULL);
++static DEVICE_ATTR(backlight_s, 0444, hhtech_sysfs_show_blight_s, NULL);
++static DEVICE_ATTR(usbhost_s, 0444, hhtech_sysfs_show_usbhost, NULL);
++static DEVICE_ATTR(usbotg_s, 0444, hhtech_sysfs_show_usbotg, NULL);
++static DEVICE_ATTR(battery_s, 0444, hhtech_sysfs_show_battery, NULL);
++static DEVICE_ATTR(pwr_en, 0666, hhtech_sysfs_show_power, hhtech_sysfs_store_power);
++static DEVICE_ATTR(charge_en, 0666, hhtech_sysfs_show_charge, hhtech_sysfs_store_charge);
++static DEVICE_ATTR(backlight_en, 0666,hhtech_sysfs_show_blight, hhtech_sysfs_store_blight);
++static DEVICE_ATTR(amp_en, 0666,hhtech_sysfs_show_amp, hhtech_sysfs_store_amp);
++static DEVICE_ATTR(usbpwr_en, 0666, hhtech_sysfs_show_usbpwr, hhtech_sysfs_store_usbpwr);
++static DEVICE_ATTR(usbhostpwr_en, 0666, hhtech_sysfs_show_usbhostpwr, hhtech_sysfs_store_usbhostpwr);
++static DEVICE_ATTR(usbotgdrv_en, 0666, hhtech_sysfs_show_usbotgdrv, hhtech_sysfs_store_usbotgdrv);
++static DEVICE_ATTR(speaker_en, 0666, hhtech_sysfs_show_speaker, hhtech_sysfs_store_speaker);
++static DEVICE_ATTR(wifi_en, 0666, hhtech_sysfs_show_wifi, hhtech_sysfs_store_wifi);
++static DEVICE_ATTR(led1_en, 0666, hhtech_sysfs_show_led1, hhtech_sysfs_store_led1);
++static DEVICE_ATTR(led2_en, 0666, hhtech_sysfs_show_led2, hhtech_sysfs_store_led2);
++static DEVICE_ATTR(rtc_wk_time, 0666, hhtech_sysfs_show_rtc_wk_time, hhtech_sysfs_store_rtc_wk_time);
++static DEVICE_ATTR(wk_status, 0666, hhtech_sysfs_show_wk_status, NULL);
++
++static struct attribute *attrs[] = {
++ &dev_attr_system_flag.attr,
++ &dev_attr_headphone_s.attr,
++ &dev_attr_dc_s.attr,
++ &dev_attr_sd_s.attr,
++ &dev_attr_charge_s.attr,
++ &dev_attr_backlight_s.attr,
++ &dev_attr_usbhost_s.attr,
++ &dev_attr_usbotg_s.attr,
++ &dev_attr_battery_s.attr,
++ &dev_attr_pwr_en.attr,
++ &dev_attr_charge_en.attr,
++ &dev_attr_backlight_en.attr,
++ &dev_attr_amp_en.attr,
++ &dev_attr_usbpwr_en.attr,
++ &dev_attr_usbhostpwr_en.attr,
++ &dev_attr_usbotgdrv_en.attr,
++ &dev_attr_speaker_en.attr,
++ &dev_attr_wifi_en.attr,
++ &dev_attr_led1_en.attr,
++ &dev_attr_led2_en.attr,
++ &dev_attr_rtc_wk_time.attr,
++ &dev_attr_wk_status.attr,
++ NULL,
++};
++
++static struct attribute_group attr_group = {
++ .attrs = attrs,
++};
++
++static int hhtech_gpio_sysfs_register(struct device* dev)
++{
++ return sysfs_create_group(&dev->kobj, &attr_group);
++}
++#else
++static int hhtech_gpio_sysfs_register(struct device* dev)
++{
++ return 0;
++}
++#endif
++
++static int hhtech_gpio_probe(struct platform_device *pdev)
++{
++ int retval;
++
++ retval = hhtech_gpio_sysfs_register(&pdev->dev);
++ if (retval < 0) {
++ printk(KERN_ERR "Create sys fs fail\n");
++ return -1;
++ }
++ gpio_direction_input(GPIO_SD_WP); //S3C_GPK0
++#if defined (CONFIG_LCD_7)
++ gpio_direction_input(GPIO_USB_HOST_STATUS); //S3C_GPL10
++ gpio_set_pin(GPIO_USB_HOST_STATUS, S3C_GPL10_EXTINT18);
++#endif
++ gpio_direction_input(GPIO_USB_OTG_STATUS); //S3C_GPL11
++ gpio_set_pin(GPIO_USB_OTG_STATUS, S3C_GPL11_EXTINT19);
++ gpio_direction_input(GPIO_HEADPHONE_S); //S3C_GPL12
++ gpio_set_pin(GPIO_HEADPHONE_S, S3C_GPL12_EXTINT20);
++
++ gpio_direction_input(GPIO_LCD_BLIGHT_S); //S3C_GPM4
++ gpio_direction_input(GPIO_DC_DETE); //S3C_GPL13
++ gpio_direction_input(GPIO_CHARG_S1); //S3C_GPK4
++ gpio_direction_input(GPIO_CHARG_S2); //S3C_GPK5
++ gpio_direction_input(GPIO_PWR_HOLD); //S3C_GPL14
++#if defined (CONFIG_LCD_4)
++ gpio_direction_output(GPIO_USB_EN, 0); //S3C_GPL0 : close
++ gpio_direction_output(GPIO_USB_HOSTPWR_EN, 0); //S3C_GPL1 : close
++#else
++ gpio_direction_output(GPIO_USB_EN, 1); //S3C_GPL0 : open
++ gpio_direction_output(GPIO_USB_HOSTPWR_EN, 1); //S3C_GPL1 : open
++#endif
++ //gpio_direction_output(GPIO_LCD_BLIGHT_EN, 1); //S3C_GPM3 : open
++ gpio_direction_output(GPIO_CHARGER_EN, 0); //S3C_GPK6 : 200ma
++ gpio_direction_output(GPIO_PWR_EN, 0); //S3C_GPK15 : open normal it's low
++ gpio_direction_output(GPIO_VIDEOAMP_EN, 0); //S3C_GPK13 : close
++ gpio_direction_output(GPIO_SPEAKER_EN, 0); //S3C_GPK12 : close
++ gpio_direction_output(GPIO_WIFI_EN, 1); //S3C_GPK1 : open
++ gpio_direction_output(GPIO_WIFI_RESET, 0); //S3C_GPK2 : open
++ mdelay(100);
++ gpio_set_value(GPIO_WIFI_RESET, 1);
++ gpio_direction_input(GPIO_WIFI_RESET);
++ gpio_direction_output(GPIO_USB_OTGDRV_EN, 0); //S3C_GPL8 : close
++ gpio_direction_output(GPIO_LED1_EN, 0); //S3C_GPN8 : turn on
++ if (NULL == strstr(saved_command_line, "rdinit"))
++ gpio_direction_output(GPIO_LED2_EN, 1); //S3C_GPN9 : turn off
++ else
++ gpio_direction_output(GPIO_LED2_EN, 0); //S3C_GPN9 : turn on
++ udelay(10);
++
++ //retval = request_irq(gpio_to_irq(GPIO_HEADPHONE_S), headp_irq,
++ retval = request_irq(gpio_to_irq(GPIO_HEADPHONE_S), headp_irq,
++ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "Headphone detect", NULL);
++ if (retval) {
++ printk(KERN_ERR "Request headphone detect fail\n");
++ goto error1;
++ }
++
++ retval = request_irq(gpio_to_irq(GPIO_USB_OTG_STATUS), usbotg_status_irq,
++ IRQF_TRIGGER_FALLING, "Usb otg status detect", NULL);
++ if (retval) {
++ printk(KERN_ERR "Request usb otg status detect fail\n");
++ goto error2;
++ }
++
++#if defined (CONFIG_LCD_7)
++ /*retval = request_irq(gpio_to_irq(GPIO_USB_HOST_STATUS), usbhost_status_irq,
++ IRQF_TRIGGER_FALLING, "Usb host status detect", NULL);
++ if (retval) {
++ printk(KERN_ERR "Request usb host status detect fail\n");
++ goto error3;
++ }*/
++#endif
++ INIT_DELAYED_WORK(&headp_detect_work, headp_update_volume);
++ INIT_DELAYED_WORK(&battery_work, battery_update_work);
++ battery_update_work(NULL);
++
++ return 0;
++
++ error3:
++ free_irq(gpio_to_irq(GPIO_USB_HOST_STATUS), NULL);
++ error2:
++ free_irq(gpio_to_irq(GPIO_HEADPHONE_S), NULL);
++ error1:
++ return retval;
++}
++
++static int hhtech_gpio_remove(struct platform_device *dev)
++{
++ free_irq(gpio_to_irq(GPIO_HEADPHONE_S), NULL);
++#if defined (CONFIG_LCD_7)
++ free_irq(gpio_to_irq(GPIO_USB_HOST_STATUS), NULL);
++#endif
++ free_irq(gpio_to_irq(GPIO_USB_OTG_STATUS), NULL);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static struct sleep_save_phy save_gpio[] = {
++ SAVE_ITEM(GPIO_USB_HOSTPWR_EN),
++ SAVE_ITEM(GPIO_USB_OTGDRV_EN),
++ SAVE_ITEM(GPIO_USB_EN),
++};
++
++static void gpio_do_save(struct sleep_save_phy *ptr, int count)
++{
++ for (; count > 0; count--, ptr++)
++ ptr->val = gpio_get_value(ptr->reg);
++}
++
++static void gpio_do_load(struct sleep_save_phy *ptr, int count)
++{
++ for (; count > 0; count--, ptr++)
++ gpio_set_value(ptr->reg, ptr->val);
++}
++
++static int hhtech_gpio_suspend(struct platform_device *dev, pm_message_t state)
++{
++ /* Becareful: MMC must be suspended after this driver */
++ set_wifi_en(0);
++ /* Close USB Power */
++ gpio_do_save(save_gpio, ARRAY_SIZE(save_gpio));
++ set_usb_hostpwr_en(0);
++ set_usb_otgdrv_en(0);
++ set_usb_syspwr_en(0);
++ return 0;
++}
++extern void __iomem *s3c_rtc_base;
++
++static int hhtech_gpio_resume(struct platform_device *dev)
++{
++ int dc_status;
++
++#if defined (CONFIG_LCD_4)
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 1 : 0;
++#else
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 0 : 1;
++#endif
++ wakeup_status = 0;
++
++ if (0 == dc_status) {
++ if (get_battery_life() < 833) // battery volume < 3.5 V
++ set_sys_power(0);
++ if (readb(s3c_rtc_base + S3C_INTP) & S3C_INTP_ALM)
++ wakeup_status = 1;
++ }
++
++ gpio_do_load(save_gpio, ARRAY_SIZE(save_gpio));
++ set_wifi_en(1);
++ return 0;
++}
++#else
++#define hhtech_gpio_suspend NULL
++#define hhtech_gpio_resume NULL
++#endif
++
++
++static struct platform_driver hhtech_gpio = {
++ .probe = hhtech_gpio_probe,
++ .remove = hhtech_gpio_remove,
++ .suspend = hhtech_gpio_suspend,
++ .resume = hhtech_gpio_resume,
++ .driver = {
++ .name = "hhtech_gpio",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init hhtech_gpio_init(void)
++{
++ user_disable_speaker = 0;
++ return platform_driver_register(&hhtech_gpio);
++}
++
++static void __exit hhtech_gpio_exit(void)
++{
++ platform_driver_unregister(&hhtech_gpio);
++}
++
++module_init(hhtech_gpio_init);
++module_exit(hhtech_gpio_exit);
++
++//EXPORT_SYMBOL(set_sys_power);
++
++MODULE_AUTHOR("Wangkang");
++MODULE_DESCRIPTION("S3C64xx GPIO driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
+index 6a9ca4b..8e224fe 100644
+--- a/drivers/input/keyboard/gpio_keys.c
++++ b/drivers/input/keyboard/gpio_keys.c
+@@ -9,7 +9,6 @@
+ */
+
+ #include <linux/module.h>
+-#include <linux/version.h>
+
+ #include <linux/init.h>
+ #include <linux/fs.h>
+@@ -26,25 +25,47 @@
+
+ #include <asm/gpio.h>
+
+-static irqreturn_t gpio_keys_isr(int irq, void *dev_id)
++struct gpio_button_data {
++ struct gpio_keys_button *button;
++ struct input_dev *input;
++ struct timer_list timer;
++};
++
++struct gpio_keys_drvdata {
++ struct input_dev *input;
++ struct gpio_button_data data[0];
++};
++
++static void gpio_keys_report_event(struct gpio_button_data *bdata)
+ {
+- int i;
+- struct platform_device *pdev = dev_id;
+- struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+- struct input_dev *input = platform_get_drvdata(pdev);
++ struct gpio_keys_button *button = bdata->button;
++ struct input_dev *input = bdata->input;
++ unsigned int type = button->type ?: EV_KEY;
++ int state = (gpio_get_value(button->gpio) ? 1 : 0) ^ button->active_low;
+
+- for (i = 0; i < pdata->nbuttons; i++) {
+- struct gpio_keys_button *button = &pdata->buttons[i];
+- int gpio = button->gpio;
++ input_event(input, type, button->code, !!state);
++ input_sync(input);
++}
+
+- if (irq == gpio_to_irq(gpio)) {
+- unsigned int type = button->type ?: EV_KEY;
+- int state = (gpio_get_value(gpio) ? 1 : 0) ^ button->active_low;
++static void gpio_check_button(unsigned long _data)
++{
++ struct gpio_button_data *data = (struct gpio_button_data *)_data;
+
+- input_event(input, type, button->code, !!state);
+- input_sync(input);
+- }
+- }
++ gpio_keys_report_event(data);
++}
++
++static irqreturn_t gpio_keys_isr(int irq, void *dev_id)
++{
++ struct gpio_button_data *bdata = dev_id;
++ struct gpio_keys_button *button = bdata->button;
++
++ BUG_ON(irq != gpio_to_irq(button->gpio));
++
++ if (button->debounce_interval)
++ mod_timer(&bdata->timer,
++ jiffies + msecs_to_jiffies(button->debounce_interval));
++ else
++ gpio_keys_report_event(bdata);
+
+ return IRQ_HANDLED;
+ }
+@@ -52,17 +73,20 @@ static irqreturn_t gpio_keys_isr(int irq, void *dev_id)
+ static int __devinit gpio_keys_probe(struct platform_device *pdev)
+ {
+ struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
++ struct gpio_keys_drvdata *ddata;
+ struct input_dev *input;
+ int i, error;
+- int wakeup = 0;
+
++ ddata = kzalloc(sizeof(struct gpio_keys_drvdata) +
++ pdata->nbuttons * sizeof(struct gpio_button_data),
++ GFP_KERNEL);
+ input = input_allocate_device();
+- if (!input)
+- return -ENOMEM;
+-
+- platform_set_drvdata(pdev, input);
++ if (!ddata || !input) {
++ error = -ENOMEM;
++ goto fail1;
++ }
+
+- input->evbit[0] = BIT_MASK(EV_KEY);
++ platform_set_drvdata(pdev, ddata);
+
+ input->name = pdev->name;
+ input->phys = "gpio-keys/input0";
+@@ -73,16 +97,28 @@ static int __devinit gpio_keys_probe(struct platform_device *pdev)
+ input->id.product = 0x0001;
+ input->id.version = 0x0100;
+
++ /* Enable auto repeat feature of Linux input subsystem */
++ if (pdata->rep)
++ __set_bit(EV_REP, input->evbit);
++
++ ddata->input = input;
++
+ for (i = 0; i < pdata->nbuttons; i++) {
+ struct gpio_keys_button *button = &pdata->buttons[i];
++ struct gpio_button_data *bdata = &ddata->data[i];
+ int irq;
+ unsigned int type = button->type ?: EV_KEY;
+
++ bdata->input = input;
++ bdata->button = button;
++ setup_timer(&bdata->timer,
++ gpio_check_button, (unsigned long)bdata);
++
+ error = gpio_request(button->gpio, button->desc ?: "gpio_keys");
+ if (error < 0) {
+ pr_err("gpio-keys: failed to request GPIO %d,"
+ " error %d\n", button->gpio, error);
+- goto fail;
++ goto fail2;
+ }
+
+ error = gpio_direction_input(button->gpio);
+@@ -91,7 +127,7 @@ static int __devinit gpio_keys_probe(struct platform_device *pdev)
+ " direction for GPIO %d, error %d\n",
+ button->gpio, error);
+ gpio_free(button->gpio);
+- goto fail;
++ goto fail2;
+ }
+
+ irq = gpio_to_irq(button->gpio);
+@@ -101,24 +137,21 @@ static int __devinit gpio_keys_probe(struct platform_device *pdev)
+ " for GPIO %d, error %d\n",
+ button->gpio, error);
+ gpio_free(button->gpio);
+- goto fail;
++ goto fail2;
+ }
+
+ error = request_irq(irq, gpio_keys_isr,
+ IRQF_SAMPLE_RANDOM | IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING,
+ button->desc ? button->desc : "gpio_keys",
+- pdev);
++ bdata);
+ if (error) {
+ pr_err("gpio-keys: Unable to claim irq %d; error %d\n",
+ irq, error);
+ gpio_free(button->gpio);
+- goto fail;
++ goto fail2;
+ }
+
+- if (button->wakeup)
+- wakeup = 1;
+-
+ input_set_capability(input, type, button->code);
+ }
+
+@@ -126,21 +159,23 @@ static int __devinit gpio_keys_probe(struct platform_device *pdev)
+ if (error) {
+ pr_err("gpio-keys: Unable to register input device, "
+ "error: %d\n", error);
+- goto fail;
++ goto fail2;
+ }
+
+- device_init_wakeup(&pdev->dev, wakeup);
+-
+ return 0;
+
+- fail:
++ fail2:
+ while (--i >= 0) {
+- free_irq(gpio_to_irq(pdata->buttons[i].gpio), pdev);
++ free_irq(gpio_to_irq(pdata->buttons[i].gpio), &ddata->data[i]);
++ if (pdata->buttons[i].debounce_interval)
++ del_timer_sync(&ddata->data[i].timer);
+ gpio_free(pdata->buttons[i].gpio);
+ }
+
+ platform_set_drvdata(pdev, NULL);
++ fail1:
+ input_free_device(input);
++ kfree(ddata);
+
+ return error;
+ }
+@@ -148,14 +183,15 @@ static int __devinit gpio_keys_probe(struct platform_device *pdev)
+ static int __devexit gpio_keys_remove(struct platform_device *pdev)
+ {
+ struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+- struct input_dev *input = platform_get_drvdata(pdev);
++ struct gpio_keys_drvdata *ddata = platform_get_drvdata(pdev);
++ struct input_dev *input = ddata->input;
+ int i;
+
+- device_init_wakeup(&pdev->dev, 0);
+-
+ for (i = 0; i < pdata->nbuttons; i++) {
+ int irq = gpio_to_irq(pdata->buttons[i].gpio);
+- free_irq(irq, pdev);
++ free_irq(irq, &ddata->data[i]);
++ if (pdata->buttons[i].debounce_interval)
++ del_timer_sync(&ddata->data[i].timer);
+ gpio_free(pdata->buttons[i].gpio);
+ }
+
+@@ -165,54 +201,17 @@ static int __devexit gpio_keys_remove(struct platform_device *pdev)
+ }
+
+
+-#ifdef CONFIG_PM
+-static int gpio_keys_suspend(struct platform_device *pdev, pm_message_t state)
+-{
+- struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+- int i;
+-
+- if (device_may_wakeup(&pdev->dev)) {
+- for (i = 0; i < pdata->nbuttons; i++) {
+- struct gpio_keys_button *button = &pdata->buttons[i];
+- if (button->wakeup) {
+- int irq = gpio_to_irq(button->gpio);
+- enable_irq_wake(irq);
+- }
+- }
+- }
+-
+- return 0;
+-}
+-
+-static int gpio_keys_resume(struct platform_device *pdev)
+-{
+- struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+- int i;
+-
+- if (device_may_wakeup(&pdev->dev)) {
+- for (i = 0; i < pdata->nbuttons; i++) {
+- struct gpio_keys_button *button = &pdata->buttons[i];
+- if (button->wakeup) {
+- int irq = gpio_to_irq(button->gpio);
+- disable_irq_wake(irq);
+- }
+- }
+- }
+-
+- return 0;
+-}
+-#else
+ #define gpio_keys_suspend NULL
+ #define gpio_keys_resume NULL
+-#endif
+
+-struct platform_driver gpio_keys_device_driver = {
++static struct platform_driver gpio_keys_device_driver = {
+ .probe = gpio_keys_probe,
+ .remove = __devexit_p(gpio_keys_remove),
+ .suspend = gpio_keys_suspend,
+ .resume = gpio_keys_resume,
+ .driver = {
+ .name = "gpio-keys",
++ .owner = THIS_MODULE,
+ }
+ };
+
+@@ -226,9 +225,10 @@ static void __exit gpio_keys_exit(void)
+ platform_driver_unregister(&gpio_keys_device_driver);
+ }
+
+-module_init(gpio_keys_init);
++late_initcall(gpio_keys_init);
+ module_exit(gpio_keys_exit);
+
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Phil Blundell <pb@handhelds.org>");
+ MODULE_DESCRIPTION("Keyboard driver for CPU GPIOs");
++MODULE_ALIAS("platform:gpio-keys");
+diff --git a/drivers/input/keyboard/s3c-keypad.c b/drivers/input/keyboard/s3c-keypad.c
+index 7bd73a2..e12b83a 100644
+--- a/drivers/input/keyboard/s3c-keypad.c
++++ b/drivers/input/keyboard/s3c-keypad.c
+@@ -51,7 +51,7 @@ static int keypad_scan(u32 *keymask_low, u32 *keymask_high)
+
+ for (i=0; i<KEYPAD_COLUMNS; i++) {
+ cval = readl(key_base+S3C_KEYIFCOL) | KEYCOL_DMASK;
+- cval &= ~(1 << i);
++ cval &= ~(1 << (i + 6));
+ writel(cval, key_base+S3C_KEYIFCOL);
+
+ udelay(KEYPAD_DELAY);
+@@ -272,14 +272,15 @@ out:
+
+ static int s3c_keypad_remove(struct platform_device *pdev)
+ {
+- struct input_dev *input_dev = platform_get_drvdata(pdev);
++ struct s3c_keypad *s3c_keypad = platform_get_drvdata(pdev);
++ struct input_dev *input_dev = s3c_keypad->dev;
+ writel(KEYIFCON_CLEAR, key_base+S3C_KEYIFCON);
+
+ input_unregister_device(input_dev);
+- kfree(pdev->dev.platform_data);
++ kfree(s3c_keypad);
+ free_irq(IRQ_KEYPAD, (void *) pdev);
+
+- del_timer(&keypad_timer);
++ del_timer(&keypad_timer);
+ printk(DEVICE_NAME " Removed.\n");
+ return 0;
+ }
+diff --git a/drivers/input/keyboard/s3c-keypad.h b/drivers/input/keyboard/s3c-keypad.h
+index 4207bfa..e1e4113 100644
+--- a/drivers/input/keyboard/s3c-keypad.h
++++ b/drivers/input/keyboard/s3c-keypad.h
+@@ -9,12 +9,12 @@
+ static void __iomem *key_base;
+
+ #if defined(CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
+-#define KEYPAD_COLUMNS 8
+-#define KEYPAD_ROWS 8
+-#define MAX_KEYPAD_NR 64 /* 8*8 */
++#define KEYPAD_COLUMNS 2
++#define KEYPAD_ROWS 8
++#define MAX_KEYPAD_NR 16 /* 8*8 */
+ #define MAX_KEYMASK_NR 32
+
+-int keypad_keycode[] = {
++/*int keypad_keycode[] = {
+ 1, 2, KEY_1, KEY_Q, KEY_A, 6, 7, KEY_LEFT,
+ 9, 10, KEY_2, KEY_W, KEY_S, KEY_Z, KEY_RIGHT, 16,
+ 17, 18, KEY_3, KEY_E, KEY_D, KEY_X, 23, KEY_UP,
+@@ -24,22 +24,39 @@ int keypad_keycode[] = {
+ KEY_M, KEY_L, KEY_7, KEY_U, KEY_J, KEY_N, 55, KEY_ENTER,
+ KEY_LEFTSHIFT, KEY_9, KEY_8, KEY_I, KEY_K, KEY_B, 63, KEY_COMMA
+ };
++*/
++int keypad_keycode[] = {
++ 1,2,3,4,5,6,7,8,
++ 9,10,11,12,13,14,15,16,
++ 17,18,19,20,21,22,23,24,
++ 25,26,27,28,29,30,31,32,
++ 33,34,35,36,37,38,39,40,
++ 41,42,43,44,45,46,47,48,
++ 49,50,51,52,53,54,55,56,
++ 57,58,59,60,61,62,63,64
++ };
+
+
+ #define KEYPAD_DELAY (50)
+-#define KEYPAD_ROW_GPIOCON S3C_GPK1CON
+-#define KEYPAD_ROW_GPIOPUD S3C_GPKPU
++//#define KEYPAD_ROW_GPIOCON S3C_GPK1CON //HHTECH wk
++//#define KEYPAD_ROW_GPIOPUD S3C_GPKPU //HHTECH wk
++#define KEYPAD_ROW_GPIOCON S3C_GPNCON //HHTECH wk
++#define KEYPAD_ROW_GPIOPUD S3C_GPNPU //HHTECH wk
+ #define KEYPAD_COL_GPIOCON S3C_GPL0CON
+ #define KEYPAD_COL_GPIOPUD S3C_GPLPU
+
+ #define KEYPAD_ROW_GPIO_SET \
+- ((readl(KEYPAD_ROW_GPIOCON) & ~(0xfffffff)) | 0x33333333)
++ ((readl(KEYPAD_ROW_GPIOCON) & ~(0xffff)) | 0xffff)
++ //((readl(KEYPAD_ROW_GPIOCON) & ~(0xfffffff)) | 0x33333333)
+
+ #define KEYPAD_COL_GPIO_SET \
+- ((readl(KEYPAD_COL_GPIOCON) & ~(0xfffffff)) | 0x33333333)
++ ((readl(KEYPAD_COL_GPIOCON) & ~(0xff000000)) | 0x33000000)
++// ((readl(KEYPAD_COL_GPIOCON) & ~(0xfffffff)) | 0x33333333)
+
+-#define KEYPAD_ROW_GPIOPUD_DIS (readl(KEYPAD_ROW_GPIOPUD) & ~(0xffff<<16))
+-#define KEYPAD_COL_GPIOPUD_DIS (readl(KEYPAD_COL_GPIOPUD) & ~0xffff)
++//#define KEYPAD_ROW_GPIOPUD_DIS (readl(KEYPAD_ROW_GPIOPUD) & ~(0xffff<<16))
++#define KEYPAD_ROW_GPIOPUD_DIS (readl(KEYPAD_ROW_GPIOPUD) & ~(0xffff)) //GPN0,GPN1,...GPN7
++//#define KEYPAD_COL_GPIOPUD_DIS (readl(KEYPAD_COL_GPIOPUD) & ~0xffff)
++#define KEYPAD_COL_GPIOPUD_DIS (readl(KEYPAD_COL_GPIOPUD) & ~0xf000) //GPL6,GPL7 //HHTECH wk
+
+ #define KEYIFCOL_CLEAR (readl(key_base+S3C_KEYIFCOL) & ~0xffff)
+ #define KEYIFCON_CLEAR (readl(key_base+S3C_KEYIFCON) & ~0x1f)
+diff --git a/drivers/input/mousedev.c b/drivers/input/mousedev.c
+index be83516..5484774 100644
+--- a/drivers/input/mousedev.c
++++ b/drivers/input/mousedev.c
+@@ -131,6 +131,7 @@ static void mousedev_touchpad_event(struct input_dev *dev,
+ {
+ int size, tmp;
+ enum { FRACTION_DENOM = 128 };
++return;
+
+ switch (code) {
+
+@@ -318,6 +319,7 @@ static void mousedev_notify_readers(struct mousedev *mousedev,
+
+ static void mousedev_touchpad_touch(struct mousedev *mousedev, int value)
+ {
++return;
+ if (!value) {
+ if (mousedev->touch &&
+ time_before(jiffies,
+@@ -378,6 +380,7 @@ static void mousedev_event(struct input_handle *handle,
+ break;
+
+ case EV_SYN:
++if (test_bit(BTN_TOOL_FINGER, handle->dev->keybit)) return;
+ if (code == SYN_REPORT) {
+ if (mousedev->touch) {
+ mousedev->pkt_count++;
+diff --git a/drivers/input/touchscreen/s3c-ts.c b/drivers/input/touchscreen/s3c-ts.c
+index e04228f..c16d441 100644
+--- a/drivers/input/touchscreen/s3c-ts.c
++++ b/drivers/input/touchscreen/s3c-ts.c
+@@ -82,10 +82,10 @@
+
+ /* Touchscreen default configuration */
+ struct s3c_ts_mach_info s3c_ts_default_cfg __initdata = {
+- .delay = 10000,
++ .delay = 50000,
+ .presc = 49,
+- .oversampling_shift = 2,
+- .resol_bit = 10,
++ .oversampling_shift = 4,
++ .resol_bit = 12,
+ };
+
+ /*
+@@ -98,6 +98,70 @@ static struct resource *ts_irq;
+ static struct clk *ts_clock;
+ static struct s3c_ts *ts;
+
++static unsigned long data_for_ADCCON;
++static unsigned long data_for_ADCTSC;
++static int ts_pressed = 0;
++
++static void touch_timer_fire(unsigned long data);
++
++static struct timer_list touch_timer =
++ TIMER_INITIALIZER(touch_timer_fire, 0, 0);
++
++static void s3c_adc_save_SFR_on_ADC(void) {
++
++ data_for_ADCCON = readl(ts_base+S3C2410_ADCCON);
++ data_for_ADCTSC = readl(ts_base+S3C2410_ADCTSC);
++}
++
++static void s3c_adc_restore_SFR_on_ADC(void) {
++
++ writel(data_for_ADCCON, ts_base+S3C2410_ADCCON);
++ writel(data_for_ADCTSC, ts_base+S3C2410_ADCTSC);
++}
++
++unsigned int s3c_adc_value(unsigned int s3c_adc_port)
++{
++ unsigned int adc_return = 0;
++ unsigned long data0;
++ unsigned long data1;
++
++ if (ts_pressed)
++ return 0;
++
++ disable_irq(IRQ_ADC);
++ disable_irq(IRQ_TC);
++
++ if (timer_pending(&touch_timer) || ts_pressed)
++ goto out;
++
++ s3c_adc_save_SFR_on_ADC();
++
++ writel(0x58, ts_base+S3C2410_ADCTSC);
++
++ writel(readl(ts_base+S3C2410_ADCCON)|S3C2410_ADCCON_SELMUX(s3c_adc_port), ts_base+S3C2410_ADCCON);
++ udelay(10);
++
++ writel(readl(ts_base+S3C2410_ADCCON)|S3C2410_ADCCON_ENABLE_START, ts_base+S3C2410_ADCCON);
++
++ do {
++ data0 = readl(ts_base+S3C2410_ADCCON);
++ } while(!(data0 & S3C2410_ADCCON_ECFLG));
++
++ data1 = readl(ts_base+S3C2410_ADCDAT0);
++
++ s3c_adc_restore_SFR_on_ADC();
++
++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT;
++ __raw_writel(0x0, ts_base+S3C6400_ADCCLRWK);
++ __raw_writel(0x0, ts_base+S3C6400_ADCCLRINT);
++out:
++ enable_irq(IRQ_TC);
++ enable_irq(IRQ_ADC);
++
++ return adc_return;
++}
++EXPORT_SYMBOL(s3c_adc_value);
++
+ static void touch_timer_fire(unsigned long data)
+ {
+ unsigned long data0;
+@@ -120,8 +184,8 @@ static void touch_timer_fire(unsigned long data)
+ }
+ #endif
+
+- input_report_abs(ts->dev, ABS_X, ts->xp);
+- input_report_abs(ts->dev, ABS_Y, ts->yp);
++ input_report_abs(ts->dev, ABS_X, ts->xp / ts->count);
++ input_report_abs(ts->dev, ABS_Y, ts->yp / ts->count);
+
+ input_report_key(ts->dev, BTN_TOUCH, 1);
+ input_report_abs(ts->dev, ABS_PRESSURE, 1);
+@@ -144,12 +208,10 @@ static void touch_timer_fire(unsigned long data)
+ input_sync(ts->dev);
+
+ writel(WAIT4INT(0), ts_base+S3C2410_ADCTSC);
++ ts_pressed = 0;
+ }
+ }
+
+-static struct timer_list touch_timer =
+- TIMER_INITIALIZER(touch_timer_fire, 0, 0);
+-
+ static irqreturn_t stylus_updown(int irqno, void *param)
+ {
+ unsigned long data0;
+@@ -184,6 +246,7 @@ static irqreturn_t stylus_action(int irqno, void *param)
+ {
+ unsigned long data0;
+ unsigned long data1;
++ ts_pressed = 1;
+
+ data0 = readl(ts_base+S3C2410_ADCDAT0);
+ data1 = readl(ts_base+S3C2410_ADCDAT1);
+@@ -210,6 +273,7 @@ static irqreturn_t stylus_action(int irqno, void *param)
+ writel(WAIT4INT(1), ts_base+S3C2410_ADCTSC);
+ }
+
++end:
+ #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
+ __raw_writel(0x0, ts_base+S3C6400_ADCCLRWK);
+ __raw_writel(0x0, ts_base+S3C6400_ADCCLRINT);
+@@ -268,6 +332,8 @@ static int __init s3c_ts_probe(struct platform_device *pdev)
+ clk_enable(ts_clock);
+
+ s3c_ts_cfg = s3c_ts_get_platdata(&pdev->dev);
++
++ //writel(S3C2410_ADCCON_STDBM, ts_base+S3C2410_ADCCON); mdelay(10);
+
+ if ((s3c_ts_cfg->presc&0xff) > 0)
+ writel(S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(s3c_ts_cfg->presc&0xFF),\
+@@ -303,6 +369,7 @@ static int __init s3c_ts_probe(struct platform_device *pdev)
+
+ ts->dev->evbit[0] = ts->dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+ ts->dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
++ts->dev->keybit[BIT_WORD(BTN_TOOL_FINGER)] = BIT_MASK(BTN_TOOL_FINGER);
+
+ #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2416)
+ input_set_abs_params(ts->dev, ABS_X, 0, 0xFFF, 0, 0);
+@@ -332,14 +399,14 @@ static int __init s3c_ts_probe(struct platform_device *pdev)
+ goto err_clk;
+ }
+
+- ret = request_irq(ts_irq->start, stylus_updown, IRQF_SAMPLE_RANDOM, "s3c_updown", ts);
++ ret = request_irq(ts_irq->start, stylus_updown, IRQF_SAMPLE_RANDOM, "s3c_updown", ts->dev);
+ if (ret != 0) {
+ printk(KERN_ERR "s3c_ts.c: Could not allocate ts IRQ_TC !\n");
+ ret = -EIO;
+ goto err_clk;
+ }
+
+- ret = request_irq(ts_irq->end, stylus_action, IRQF_SAMPLE_RANDOM, "s3c_action", ts);
++ ret = request_irq(ts_irq->end, stylus_action, IRQF_SAMPLE_RANDOM, "s3c_action", ts->dev);
+ if (ret != 0) {
+ printk(KERN_ERR "s3c_ts.c: Could not allocate ts IRQ_ADC !\n");
+ ret = -EIO;
+@@ -397,6 +464,9 @@ static int s3c_ts_remove(struct platform_device *dev)
+
+ input_unregister_device(ts->dev);
+ iounmap(ts_base);
++ kfree(ts);
++ release_resource(ts_mem);
++ kfree(ts_mem);
+
+ return 0;
+ }
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index b5e67c0..2a060ce 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -13,6 +13,11 @@ menuconfig MISC_DEVICES
+
+ if MISC_DEVICES
+
++config SMARTQ5_ENCRYPT
++ tristate "AT88SC5211C CryptoMemory Device driver for SmartQ5"
++ depends on MACH_SMDK6410
++ ---help---
++
+ config IBM_ASM
+ tristate "Device driver for IBM RSA service processor"
+ depends on X86 && PCI && INPUT && EXPERIMENTAL
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index 87f2685..71f4d76 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -3,6 +3,7 @@
+ #
+ obj- := misc.o # Dummy rule to force built-in.o to be made
+
++obj-$(CONFIG_SMARTQ5_ENCRYPT) += smartq5_encrypt/
+ obj-$(CONFIG_IBM_ASM) += ibmasm/
+ obj-$(CONFIG_HDPU_FEATURES) += hdpuftrs/
+ obj-$(CONFIG_MSI_LAPTOP) += msi-laptop.o
+diff --git a/drivers/misc/smartq5_encrypt/Makefile b/drivers/misc/smartq5_encrypt/Makefile
+new file mode 100644
+index 0000000..3dd6858
+--- /dev/null
++++ b/drivers/misc/smartq5_encrypt/Makefile
+@@ -0,0 +1,3 @@
++
++obj-$(CONFIG_SMARTQ5_ENCRYPT) := smartq5_encrypt.o
++
+diff --git a/drivers/misc/smartq5_encrypt/lib_Crypto.h b/drivers/misc/smartq5_encrypt/lib_Crypto.h
+new file mode 100644
+index 0000000..9e6b634
+--- /dev/null
++++ b/drivers/misc/smartq5_encrypt/lib_Crypto.h
+@@ -0,0 +1,1426 @@
++/** \file
++ * \brief Definitions and declarations for external reference into CrytoMemory
++ * and Companion CryptoMemory Library.
++ */
++/*
++*******************************************************************************
++* |
++* File Name | lib_Crypto.h
++*------------------------------------------------------------------------------
++* Project | CryptoMemory and Companion CryptoMemory
++*------------------------------------------------------------------------------
++* Created | October 02, 2006
++*-----------------|-----------------------------------------------------------
++* Description | This file contains all the definitions and function which
++* | are used to reference to/from CryptoMemory and its
++* | Companion library.
++*-----------------|------------------------------------------------------------
++* | Copyright (c) 2006 Atmel Corp.
++* | All Rights Reserved.
++* |
++******************************************************************************
++*/
++#ifndef LIB_CRYPTO_H
++#define LIB_CRYPTO_H
++
++typedef unsigned char uchar;
++
++/** \mainpage Crypto-Memory Library Documentation
++ *
++ * \section intro_sec Introduction
++ *
++ * The CryptoMemory family is a high performance secure memory devices
++ * providing 1K to 256K bits of user memory with advanced security and
++ * cryptographic features built in. The memory is divided into 4, 8 or 16
++ * user zones each of which may be individually set with different security
++ * access rights or used together to provide space for one or multiple data
++ * files. A configuration zone contains registers to define the security
++ * rights for each user zone and space for passwords and secret keys used by
++ * the security logic of CryptoMemory.
++ *
++ * The CryptoRF family integrates a 13.56 MHz RFinterface into a CryptoMemory,
++ * resulting in a Contactless Smart Card with advanced security and
++ * cryptographic features. This device is optimized as a contactless secure
++ * memory, for multi-application RF smart card, and secure identification for
++ * electronic data transfer, without the requirement of an interal
++ * microprocessor. The CryptoRF devices provide 1K to 64K bits of user memory.
++ *
++ * The CryptoCompanion Chip is designed as the mate to Atmel`s CryptoRF and
++ * CryptoMemory chips.
++ *
++ * This Library supports the synchronous interface most useful in embedded
++ * systems. While similar to the Two Wire Interface, it is not 100% compatable.
++ *
++ * \section embedded_app Embedded Applications
++ *
++ * Through dynamic, symmetric-mutual authentication, data encryption, and
++ * the use of encrypted checksums, CryptoMemory provides a secure place for
++ * storage of sensitive information within an embedded system.
++ *
++ * A 2-wire serial interface running at 1.0 MHz is used for fast and efficient
++ * communications with up to 15 devices that may be individually addressed.
++ *
++ * \section rf_app RF Applications
++ *
++ * For communications, the RF interface utilizes the ISO 14443-2 and -3 Type B
++ * bit timing and signal modulation schemes, and the ISO 14443-3 Slot-MARKER
++ * Anticollision Protocol. Data is exchanged half duplex at a 106-kbit/s rate,
++ * with a two-byte CRC_B providing error detection capability. The maximum
++ * communication range between the reader antenna and contactless card is
++ * approximately 10 cm when used with an RFID reader that transmits the maximum
++ * ISO 14443-2 RF power level.
++ *
++ * \section detail_sec Details
++ *
++ * To enable the security features of CryptoMemory, the device must first be
++ * personalized to set up registers and load in the appropriate passwords
++ * and keys. This is accomplished though programming the configuration zone
++ * of CryptoMemory using simple write and read commands. To gain access to
++ * the configuration zone, the secure code (write 7 password) must
++ * be successfully presented. After writing and verifying data in the
++ * configuration zone, the security fuses must be blown to lock this
++ * information in the device.
++ *
++ * \subsection subsection1 Configuration Memory
++ *
++ * The configuration memory consists of 2048 bits of EEPROM memory used for
++ * storing passwords, keys, codes and defining security levels to be used for
++ * each User Zone. Access rights to the configuration memory are defined in
++ * the control logic and may not be altered by the user. These access rights
++ * include the ability to program certain portions of the Configuration Zone
++ * and then lock the data written through use of the Security Fuses. The
++ * configuration memory for each CryptoMemory device is identical with the
++ * exception of the number of Access Registers and Password/Key Registers used.
++ *
++ * Unused registers become reserved space to ensure the other components of
++ * the configuration memory remain at the same address location regardless of
++ * the number of User Zones in a device.
++ *
++ * \subsection subsection2 Communication Security Modes
++ *
++ * Communication between the device and host operates in three basic modes.
++ * Standard mode is the default mode for the device after power-up.
++ * Authentication mode is activated by a successful authentication sequence.
++ * Encryption mode is activated by a successful encryption activation following
++ * a successful authentication.
++ *
++ * \subsection subsection3 Security Operations
++ *
++ * \subsubsection subsubsection1 Password Verification
++ *
++ * Passwords may be used to protect read and write access to the user zones.
++ * Any one of 8 password sets may be assigned to any user zone through the
++ * access registers. Separate 24 bit read and write passwords are provided.
++ * A read password will only allow data to be read from the protected zone,
++ * a write password allows both read and write access. When a password is
++ * successfully presented using the verify password command it remains active
++ * until another verify password command is issued or the device is reset.
++ * Only one password may be active at a time. When an incorrect password is
++ * presented the password attempts counter (PAC) will decrement. When the
++ * PAC reaches a value of 0x00 the associated password is permanently disabled
++ * and the protected user zone(s) cannot be accessed.
++ *
++ * \subsubsection subsubsection2 Authentication Protocol
++ *
++ * An authentication protocol may be used to protect access to the user zones.
++ * Any one of 4 key sets may be assigned to any user zone through the access
++ * registers. Each key set consists of a secret seed, cryptogram and session
++ * key. When the authentication communication mode is successfully entered
++ * with the verify authentication command the specific key set remains active
++ * until another verify authentication command is issued or the device is
++ * reset. An unsuccessful verify authentication command will deactivate the
++ * key set. Only one key set may be active at a time. When an incorrect
++ * authentication attempt is made the authentication attempts counter (AAC)
++ * will decrement. When the AAC reaches a value of 0x00 the associated key set
++ * is permanently disabled and the protected user zone(s) cannot be accessed.
++ *
++ * \subsubsection subsubsection3 Data Encryption
++ *
++ * The data exchanged between the CryptoMemory device and the host logic
++ * during read, write and verify password commands may be encrypted to ensure
++ * data confidentiality. This may be accomplished at the option of the host
++ * logic by executing the verify encryption command after a successful
++ * authentication using the same key set. Encryption may be required for any
++ * data exchange to a specific user zone by the proper setting of the access
++ * registers. In this case the successful completion of verify authentication
++ * and verify encryption commands is required before any data may be read
++ * from or written to the protected user zone. Data read from the
++ * configuration zone is never encrypted.
++ *
++ * When the encryption communication mode is successfully entered with the
++ * verify encryption command the specific key set remains active until another
++ * verify authentication command is issued or the device is reset. An
++ * unsuccessful verify encryption command will deactivate the key set and
++ * reset device security. Only one key set may be active at a time. When an
++ * incorrect encryption attempt is made the authentication attempts counter
++ * (AAC) will decrement. When the AAC reaches a value of 0x00 the associated
++ * key set is permanently disabled and the protected user zone(s) cannot be
++ * accessed. The process to activate encryption is very similar to that used
++ * to verify authentication, a calculated session key replaces the secret
++ * seed in the sequence.
++ *
++ * \subsubsection subsubsection4 Encrypted Checksum
++ *
++ * CryptoMemory implements a data validity check function in the form of an
++ * encrypted checksum. This checksum provides a bi-directional data integrity
++ * check and data origin authentication capability in the form of a Message
++ * Authentication Code (MAC): only the host/device that carried out a valid
++ * authentication is capable of computing a valid MAC. When writing data to
++ * the CryptoMemory device in authentication or encryption communication modes
++ * a valid checksum must be sent to the device immediately following the write
++ * command for data to actually be written. If the checksum sent is not
++ * correct, data will not be written to the device and security will be reset
++ * requiring a new verify authentication command to be issued to continue.
++ * When reading data the use of a checksum is optional. The read checksum
++ * command will reset device security so it is recommended to only be used
++ * after all data has been read from the device.
++ *
++ * \subsection subsection_default CryptoMemory Default Values
++ *
++ * \htmlonly
++ <TABLE CELLSPACING=10 > <TBODY> <TR>
++ <TD><B>Device</B></TD> <TD><B>ATR</B></TD>
++ <TD><B>Fab Code</B></TD> <TD><B>Lot History Code</B></TD>
++ <TD><B>Write 7 Password (Secure Code)</B></TD> </TR>
++ <TR> <TD ALIGN=CENTER>AT88SC0104C</TD>
++ <TD ALIGN=CENTER>3B B2 11 00 10 80 00 01</TD>
++ <TD ALIGN=CENTER>10 10</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>DD 42 97</TD> </TR>
++ <TR> <TD ALIGN=CENTER>AT88SC0204C</TD>
++ <TD ALIGN=CENTER>3B B2 11 00 10 80 00 02</TD>
++ <TD ALIGN=CENTER>20 20</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>E5 47 47</TD> </TR>
++ <TR> <TD ALIGN=CENTER>AT88SC0404C</TD>
++ <TD ALIGN=CENTER>3B B2 11 00 10 80 00 04</TD>
++ <TD ALIGN=CENTER>40 40</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>60 57 34</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC0808C</TD>
++ <TD ALIGN=CENTER>3B B2 11 00 10 80 00 08</TD>
++ <TD ALIGN=CENTER>80 60</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>22 E8 3F</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC1616C</TD>
++ <TD ALIGN=CENTER>3B B2 11 00 10 80 00 16</TD>
++ <TD ALIGN=CENTER>16 80</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>20 0C E0</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC3216C</TD>
++ <TD ALIGN=CENTER>3B B3 11 00 00 00 00 32</TD>
++ <TD ALIGN=CENTER>32 10</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>CB 28 50</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC6416C</TD>
++ <TD ALIGN=CENTER>3B B3 11 00 00 00 00 64</TD>
++ <TD ALIGN=CENTER>64 40</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>F7 62 0B</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC12816C</TD>
++ <TD ALIGN=CENTER>3B B3 11 00 00 00 01 28</TD>
++ <TD ALIGN=CENTER>28 60</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>22 EF 67</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC25616C</TD>
++ <TD ALIGN=CENTER>3B B3 11 00 00 00 02 56</TD>
++ <TD ALIGN=CENTER>58 60</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>17 C3 3A</TD> </TR>
++ <TR></TR> </TBODY> </TABLE> \endhtmlonly
++ *
++ * \subsection subsection_default1 CryptoRF Default Values
++ *
++ * \htmlonly
++ <TABLE CELLSPACING=10 > <TBODY> <TR>
++ <TD><B>Device</B></TD> <TD><B>Density Code</B></TD>
++ <TD><B>RBmax Code</B></TD> <TD><B>Lot History Code</B></TD>
++ <TD><B>Write 7 Password (Secure Code)</B></TD> </TR>
++ <TR> <TD ALIGN=CENTER>AT88SC0104CRF</TD>
++ <TD ALIGN=CENTER>02</TD>
++ <TD ALIGN=CENTER>10</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>10 14 7C</TD> </TR>
++ <TR> <TD ALIGN=CENTER>AT88SC0204CRF</TD>
++ <TD ALIGN=CENTER>12</TD>
++ <TD ALIGN=CENTER>10</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>20 C2 8B</TD> </TR>
++ <TR> <TD ALIGN=CENTER>AT88SC0404CRF</TD>
++ <TD ALIGN=CENTER>22</TD>
++ <TD ALIGN=CENTER>10</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>30 1D D2</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC0808CRF</TD>
++ <TD ALIGN=CENTER>33</TD>
++ <TD ALIGN=CENTER>10</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>40 7F AB</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC1616CRF</TD>
++ <TD ALIGN=CENTER>44</TD>
++ <TD ALIGN=CENTER>10</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>50 44 72</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC3216CRF</TD>
++ <TD ALIGN=CENTER>54</TD>
++ <TD ALIGN=CENTER>30</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>60 78 AF</TD> </TR>
++ <TR><TD ALIGN=CENTER>AT88SC6416CRF</TD>
++ <TD ALIGN=CENTER>64</TD>
++ <TD ALIGN=CENTER>30</TD> <TD ALIGN=CENTER>Variable, locked</TD>
++ <TD ALIGN=CENTER>70 BA 2E</TD> </TR>
++ <TR></TR> </TBODY> </TABLE> \endhtmlonly
++ *
++ * \section integrate-sec Integration Guide
++ * The supplied CryptoMemory Library supports the APIs list
++ * below. The following describes how to build a simple
++ * application using this library.
++ *
++ * \subsection subsection5 Files To Include.
++ * Below are files must add to system software.\n
++ *
++ * lib_Crypto.h:
++ *
++ * In your top level source file (probably the one that
++ * interface to lib_CMC.a or lib_CM.a), you will need to include lib_Crypto.h.
++ * This header file contained all external refernce APIs,
++ * defines and enumerations which are used by library or
++ * application. This file must be retained as is and no
++ * modification should be made.\n
++ *
++ * lib_CMC.a or lib_CM.a:
++ *
++ * In your IDE or makefile, you need to add lib_CMC.a or lib_CM.a for
++ * linker to link this library into your system software. This
++ * library archived from all object files generated by GNU
++ * compiler for AVR processor. If you use different
++ * processor other than AVR, you need request Atmel to
++ * generate a library to fit your environment and processor.
++ *
++ * lib_Support.c
++ *
++ * This file contains all APIs which library refers at compiler
++ * time and calls at run-time. Since this file is used as a
++ * reference file, you might change logic within these API but
++ * must retain all API names, input and output parameters as
++ * defined. Below are definitions, tables and routines which
++ * defined and implemented by Atmel. You can use them as
++ * implemented or modify to fit your system. Below are
++ * sections in the lib_Support.c file which needed to examine
++ * to fit your system software environment.
++ *
++ * \subsection subsection6 Definitions (lib_Support.c)
++ * Below are defintions must define to fit system enviroment.
++ *
++ * CM_NUM_DEVICE\n
++ * This definition is defined how many CM devices are in system
++ * \if CMC_DOXY
++ * CMC_NUM_DEVICE\n
++ * This definition is defined how many CMC devices are in
++ * system
++ * \endif
++ * \subsection subsection7 Tables (lib_Support.c)
++ * Below are tables must define to fit system enviroment.\n
++ *
++ * cm_device_addresses[]\n
++ * This table defined all CM device addresses in system with
++ * last entry must be "0". For CM, default address is 0x0B.
++ * Each device on the bus has a unique address programmed into
++ * its DCR register. CryptoMemory device always response to
++ * address "0x0B" no matter what address is programmed into the
++ * DCR. The CM device address is defined to program from bit
++ * 0-3 only.
++ * \if CMC_DOXY
++ * cmc_device_addresses[]\n
++ * This table defined all CMC device addresses in system with
++ * last entry must be "0". The CMC device address is defined to
++ * program from bit 1-7.
++ * \endif
++ * sDeviceTypeInfoTBL[]\n
++ * This table defined all possible CM device types which are
++ * supported by Atmel.
++ *
++ * \subsection subsection8 Routines (lib_Support.c)
++ * Below are routines that can be used as implemented or
++ * modified to meet system software needed. These routines
++ * will call by library at run-time.\n
++ *
++ * cm_FindDeviceIndex(uchar ucCmDevAddr)\n
++ * This routine returns a CM index from CM device address table
++ * that based from CM device address.
++ *
++ * getCMDevAddr(uchar ucIndex)\n
++ * This rotuine returns a CM device address from CM device
++ * address table that based from CM device index.
++ *
++ * getCMDevType(uchar ucIndex)\n
++ * This routine returns a CM device type from CM device type
++ * table that based from CM device index.
++ *
++ * cmc_FindDeviceIndex(uchar ucDevAddr)\n
++ * This routine returns a CMC index from CMC device address
++ * table that based from CMC device address.
++ *
++ * getCMCDevAddr(uchar ucIndex)\n
++ * This rotuine returns a CMC device address from CMC device
++ * address table that based from CMC device index.
++ *
++ * WaitForNotBusy(uchar ucDevAddr)\n
++ * This routine waits for the CMC "BUSY" bit to CLEAR.
++ *
++ * WaitForData(uchar ucDevAddr)\n
++ * This routine waits for the CMC "DATA AVAILABLE" bit to SET.
++ *
++ * WaitForStartupDone(uchar ucDevAddr)\n
++ * This routine waits for the CMC "STARTUPDONE" bit to SET.
++ *
++ * lib_memcpy(puchar pucDesMem, puchar pucSrcMem, uint uiCnt)\n
++ * This routine calls standard C library to copy number of
++ * bytes from source to destination memory.
++ *
++ * lib_memcmp(puchar pucMem1, puchar pucMem2, uint ucCnt)\n
++ * This routine calls standard C library to compare two
++ * strings.
++ *
++ * lib_malloc(uchar ucBytes)\n
++ * This rouitne calls standard C library to allocate a buffer
++ * from memeory pool.
++ *
++ * lib_free(puchar pucBuff)\n
++ * This rouitne calls standard C library to deallocate a buffer
++ * back to memeory pool.
++ *
++ * lib_rand(void)\n
++ * This rouitne calls standard C library to get a random
++ * byte.\n
++ *
++ * \subsection subsection9 APIs in library (lib_CMC.a or lib_CM.a)
++ * Below are APIs in library which avialable for other layers
++ * to call.\n
++ *
++ * getLibVersNum(void)\n
++ * Get library version
++ *
++ * cm_Init(void)\n
++ * Initializes Crypto devices.
++ *
++ * cm_WriteUserZone(uchar ucDevAddr, uint uiCryptoAddr, puchar pucBuffer, uchar ucCount)\n
++ * Writes data into the (previously set) CM user zone
++ *
++ * cm_ReadUserZone(uchar ucDevAddr, uint uiCryptoAddr, puchar pucBuffer, uchar ucCount)\n
++ * Reads data from the (previously set) CM user
++ * zone
++ *
++ * cm_WriteConfigZone(uchar ucDevAddr, uchar ucCryptoAddr, puchar pucBuffer, uchar ucCount, uchar ucAntiTearing)\n
++ * Write data into the CM Configuration Memory
++ *
++ * cm_WriteFuse(uchar ucDevAddr, uchar ucFuze)\n
++ * Writes Fuse Byte to the specified CM device address
++ *
++ * cm_SetUserZone(uchar ucDevAddr, uchar ucZoneNumber, uchar ucAntiTearing)\n
++ * Sets CM user zone
++ *
++ * cm_ReadConfigZone(uchar ucDevAddr, uchar ucCryptoAddr, puchar pucBuffer, uchar ucCount)\n
++ * Reads data from the CM Configuration Zone
++ *
++ * cm_ReadFuse(uchar ucDevAddr, puchar pucFuze)\n
++ * Reads Fuse Byte from CM device
++ *
++ * cm_ReadChecksum(uchar ucDevAddr, puchar pucChkSum)\n
++ * Reads Checksum
++ *
++ * cm_SendChecksum(uchar ucDevAddr, puchar pucChkSum)\n
++ * Sends checksum
++ *
++ * cm_VerifyCrypto(uchar ucDevAddr, uchar ucKeySet, puchar pucBuff, puchar pucBuff2, uchar ucEncrypt)\n
++ * Activates Authentication and (optionally) Encryption mode
++ *
++ * cm_ResetCrypto(uchar ucDevAddr)\n
++ * Reset authentication and encryption and resets the
++ * cryptoengine
++ *
++ * cm_VerifyPassword(uchar ucDevAddr, puchar pucPassword, uchar ucSet, uchar ucRW)\n
++ * Verifies Password.
++ * \if CMC_DOXY
++ * cmc_VerifyFlash(uchar ucCmcDevAddr, puchar pucExtDigest, puchar pucIntDigest)\n
++ * Verifies System Digest
++ *
++ * cmc_StartChallenge(uchar ucCmcDevAddr, puchar pucCmcChallenge, puchar pucCmcSeed, puchar pucSystemSeed)\n
++ * Verify Start Challenge
++ *
++ * cmc_GetRandom(uchar ucCmcDevAddr, puchar pucData)\n
++ * Gets a 20 byte random number from the Companion Chip
++ *
++ * cmc_IncrementCounter(uchar ucCmcDevAddr, uchar ucSelector)\n
++ * Increments the value of the specified counter by 1
++ *
++ * cmc_ReadCounter(uchar ucCmcDevAddr, uchar ucSelector, puchar pucData)\n
++ * Reads 32 bits of the specified counter
++ *
++ * cmc_WriteMemory(uchar ucCmcDevAddr, uint uiAddress, uchar ucCount, puchar pucData)\n
++ * Writes the contents of the specified address
++ *
++ * cmc_WriteMemoryAuthorized(uchar ucCmcDevAddr, uint uiAddress, uchar ucData, puchar pucF0)\n
++ * Authorizes to writes a single byte in the first 16 bytes of
++ * the ReadOnly section at the specified address
++ *
++ * cmc_WriteMemoryEncrypted(uchar ucCmcDevAddr, uint uiAddress,puchar pucData, puchar pucNonce)\n
++ * Writes 16 byte page of EEPROM with encryption.
++ *
++ * cmc_ReadMemory(uchar ucCmcDevAddr, uint uiAddress, uchar ucCount, puchar pucData)\n
++ * Reads the contents of the specified address.
++ *
++ * cmc_ReadMemoryDigest(uchar ucCmcDevAddr, uint uiAddress, puchar pucData)\n
++ * Reads the specified 32 byte block and computes the SHA-1
++ * digest.
++ *
++ * cmc_ReadManufID(uchar ucCmcDevAddr, puchar pucData)\n
++ * Reads the contents of the Manufacturing ID and Lock Byte
++ *
++ * cmc_Lock(uchar ucCmcDevAddr)\n
++ * Locks the current memory values into the Companion Chip.
++ *
++ * cmc_Status(uchar ucCmcDevAddr)\n
++ * Reads Status byte from CMC
++ *
++ * cmc_SHA1(puchar pucInData, uchar ucLen, puchar pucOutData)\n
++ * Calculates digest with SHA-1 algorithm\n
++ * \endif
++ */
++
++
++/*
++****************************************************
++* Defintions for CryptoMemory and Companion
++****************************************************
++*/
++// Basic Datatypes
++typedef unsigned char *puchar;
++typedef signed char schar;
++typedef signed char *pschar;
++typedef unsigned short *pushort;
++typedef signed short sushort;
++typedef signed short *pshort;
++typedef unsigned int *puint;
++typedef signed int sint;
++typedef signed int *psint;
++
++#ifdef __AVR__
++ #ifdef __GNUC__
++ #include <avr/io.h>
++ #include <avr/pgmspace.h>
++ #define ROM_READ(addr) pgm_read_word(addr)
++///< Read of program space (flash) in AVR is different from RAM read
++ #define ROM_READ_BYTE(addr) pgm_read_byte(addr)
++///< Read of program space (flash) in AVR is different from RAM read
++ #define ROM_READ_DWORD(addr) pgm_read_dword(addr)
++///< Read of program space (flash) in AVR is different from RAM read
++ #else
++ #define ROM_READ(addr) *addr
++///< Read of program space (flash) in AVR is different from RAM read
++ #define ROM_READ_BYTE(addr) *addr
++///< Read of program space (flash) in AVR is different from RAM read
++ #define ROM_READ_DWORD(addr) *addr
++///< Read of program space (flash) in AVR is different from RAM read
++ #define PROGMEM ///< Needed in GCC to differentiate ROM from RAM
++ #endif
++#else
++ #define ROM_READ(addr) *addr
++///< Read of program space (flash) in AVR is different from RAM read
++ #define ROM_READ_BYTE(addr) *addr
++///< Read of program space (flash) in AVR is different from RAM read
++ #define ROM_READ_DWORD(addr) *addr
++///< Read of program space (flash) in AVR is different from RAM read
++ #define PROGMEM ///< Needed in GCC to differentiate ROM from RAM
++#endif
++
++
++
++// Basic Definations (if not available elsewhere)
++#ifndef FALSE
++#define FALSE (0)
++#define TRUE (!FALSE)
++#endif
++#ifndef NULL
++#define NULL ((void *)0)
++#endif
++
++/** \brief Status Return Codes */
++typedef enum {
++ SUCCESS = 0x00, ///< General OK, no error
++#ifdef CMC
++ CMC_RST_LOCKED = 0x01, ///< CMC Reset Locked, disabled until power or reset cycle
++ CMC_BAD_CMD = 0x02, ///< CMC Command format or operand bad
++ CMC_TIME_DELAY = 0x03, ///< CMC Disabled for a time delay (Power or Security)
++ CMC_AUTH_FAIL = 0x04, ///< CMC Authentication required or failed
++ CMC_PERM_LOCKED = 0x07, ///< CMC Permanently locked
++ CMC_RESPONSE_FAILED = 0x0A, ///< CMC and System fail StartUp State
++ CMC_BUSY = 0x0B, ///< CMC Busy
++ CMC_DATA_NOT_AVAIL = 0x0C, ///< CMC Data Not Available
++ CMC_STARTUP_NOT_DONE =0x0D, ///< CMC and Ssytem fail Challengence State
++#endif
++ FAILED = 0x14, ///< General failure
++ FAIL_CMDSTART = 0x15, ///< Command start failed
++ FAIL_CMDSEND = 0x16, ///< Failed to send a command
++ FAIL_WRDATA = 0x17, ///< Failed to write data
++ FAIL_RDDATA = 0x18, ///< Failed to read data
++ UNKNOWN_DEVICE = 0x19, ///< Invalid device number
++ WRITE_CMD_ERROR = 0x1A, ///< Write Command Error
++ READ_CMD_ERROR = 0x1B, ///< Read Command Error
++ PASSWORD_NOT_ACCEPTED = 0x1C, ///< Write password not accepted
++ INVALID_USER_ZONE = 0x1D, ///< Wrong user zone
++ INVALID_NUM_BYTES_2WRITE = 0x1E,///< Number of bytes to write too large
++ INVALID_NUM_BYTES_2READ = 0x1F, ///< Number of bytes to read too large
++ ERROR_MAX = 255 ///< Maximum error
++
++} RETURN_CODE;
++
++
++/** \brief Below are defined of Crypto Memory device type */
++
++typedef enum {
++ UNKNOWN_DEVICE_TYPE,
++ AT88SC0104C, /// < 1 KBits User Zone
++ AT88SC0204C, /// < 2 KBits User Zone
++ AT88SC0404C, /// < 4 KBits User Zone
++ AT88SC0808C, /// < 8 KBits User Zone
++ AT88SC1616C, /// < 16 KBits User Zone
++ AT88SC3216C, /// < 32 KBits User Zone
++ AT88SC6416C, /// < 64 KBits User Zone
++ AT88SC12816C, /// < 128 KBits User Zone
++ AT88SC25616C, /// < 256 KBits User Zone
++ AT88SCRF, /// < CM for RF
++ MAX_CM_DEVICE_TYPE /// < Maximum device type
++} CM_DEVICE_TYPE;
++
++/** \brief Maximum of CM device addresses
++*/
++#define CM_MAX_DEV_ADDR 0x0F
++
++#ifdef CMC
++/** \if CMC_DOXY
++ * \brief Maximum of CMC device addresses
++ * \endif
++*/
++#define CMC_MAX_DEV_ADDR 0xFE
++#endif
++
++/*
++****************************************************
++* CryptoMemory Function Prototypes
++****************************************************
++*/
++/** \brief Initializes the CrytpoMemory
++ *
++ * Resets the crypto engines and parameters associated with them
++ * for each device in the cm_device_addresses table.
++ * This function should be called immediately after calling the low level
++ * function ll_PowerOn(). If the return value is not SUCCESS, use of
++ * the CryptoMemory device(s) may not continue.
++ * If system runs with CryptoMemory Companion chip then this cm_Init will
++ * initialize them in this init state.
++ *
++ * \return Returns SUCCESS if device_address is in cm_device_addresses,
++ * UNKNOWN_DEVICE otherwise.
++ *
++ * \remarks Example: if (cm_Init() != SUCCESS) return 0; \n
++ * Initializes all devices in the cm_device_addresses table.
++ */
++extern RETURN_CODE cm_Init (void);
++
++/** \brief Writes data into the (previously set) user zone
++ *
++ * This function is the main memory write function, and will automatically
++ * include encryption or anti-tearing (if enabled).
++ *
++ * \param ucDevAddr - Device address (a nibble) corresponding to the default
++ * value (0xb) or the device configuration register lower nibble.
++ * \param uiCryptoAddr - 2 byte address within the zone to write
++ * \param pucBuffer - pointer to the buffer with the write data
++ * \param ucCount - how many bytes to write
++ *
++ * \return Returns the results of ll_SendCommand() and ll_SendData().
++ *
++ * \remarks Example: ucReturn = cm_WriteUserZone(DEFAULT_ADDRESS, 0, ucData,
++ * 16);\n
++ * Writes 16 bytes from ucData at address 0 to device at DEFAULT_ADDRESS.\n
++ * Return SUCCESS or the result of ll_SendCommand() or
++ * ll_SendData().
++ */
++extern RETURN_CODE cm_WriteUserZone(uchar ucDevAddr, uint uiCryptoAddr, \
++ puchar pucBuffer, uchar ucCount);
++
++/** \brief Reads data from the (previously set) user zone
++ *
++ * This function is the main memory read function, and will automatically
++ * include encryption (if enabled).
++ *
++ * \param ucDevAddr - Device address (a nibble) corresponding to the default
++ * value (0xb) or the device configuration register lower nibble.
++ * \param uiCryptoAddr - 2 byte address within the zone to read
++ * \param pucBuffer - pointer to a buffer to receive data
++ * \param ucCount - the number of bytes to read
++ *
++ * \return Returns the results of ll_SendCommand() and ll_ReceiveData().
++ *
++ * \remarks Example: ucReturn = cm_ReadUserZone(DEFAULT_ADDRESS, 0, ucData, 16);\n
++ * Reads 16 bytes into ucData from address 0 in device at DEFAULT_ADDRESS.\n
++ * Return SUCCESS or the result of ll_SendCommand() or
++ * ll_ReceiveData().
++ */
++extern RETURN_CODE cm_ReadUserZone(uchar ucDevAddr, uint uiCryptoAddr, \
++ puchar pucBuffer, uchar ucCount);
++
++/** \brief Write data into the Configuration Memory
++ *
++ * The input parameters determine which device address to write, which
++ * starting address in the configuration memory to write to, how many
++ * bytes to write, where the data to write is, and whether to use
++ * the anti-tearing option.
++ *
++ * \param ucDevAddr- Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \param ucCryptoAddr - Configuration Memory address - see the Configuration
++ * Memory map for the specific CryptoMemory Device to determine the address
++ * of the appropriate parameter.
++ * \param pucBuffer - Pointer to buffer containing write data.
++ * \param ucCount - the number of bytes to write
++ * \param ucAntiTearing - antitearing flag. If TRUE, anti-tearing is
++ * enabled. Anti-tearing should not be used unless required, as it
++ * causes more write cycles than necessary.
++ *
++ * \return Return value of ll_SendCommand() or ll_SendData().
++ *
++ * \remarks
++ * Example: \n
++ * ucReturn = cm_WriteConfigZone(DEFAULT_ADDRESS, 0x0A, ucData, 2, FALSE);\n
++ * Writes 2 bytes from ucData at CryptoMemory address 0x0A to the CryptoMemory
++ * device at DEFAULT_ADDRESS (0xb).
++ * Anti-tearing is not enabled. \n
++ * Return SUCCESS or the result of ll_SendCommand() or
++ * ll_SendData().
++ *
++ */
++extern RETURN_CODE cm_WriteConfigZone(uchar ucDevAddr, uchar ucCryptoAddr, \
++ puchar pucBuffer, uchar ucCount, \
++ uchar ucAntiTearing);
++
++/** \brief Writes Fuse Byte to the specified device address
++ *
++ * Fuse values are (in bit order from 3 to 0):
++ * - SEC (blown by Atmel before shipment, locks Lot History Code)
++ * - FAB (locks Answer to Reset and Fab Code)
++ * - CMA (locks Card Manufacturer Code)
++ * - PER (locks the remaining portions of the System Zone)
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \param ucFuze - A byte holding the fuse data
++ * \return SUCCESS or ll_SendCommand() result.
++ *
++ * \remarks Example: ucReturn = WriteFuse(DEFAULT_ADDRESS, ucData);\n
++ * Writes fuse data in ucData to device at DEFAULT_ADDRESS.
++ * Return SUCCESS or the result of ll_SendCommand()
++ */
++extern RETURN_CODE cm_WriteFuse(uchar ucDevAddr, uchar ucFuze);
++
++/** \brief System Write to set the user zone for following commands
++ *
++ * When reading or writing the main EEPROM memory of the CryptoMemory device,
++ * the supplied address refers to an offset within a user zone (refer to
++ * the User Zone map for the specific CryptoMemory Device to determine the
++ * number of zones and zone size.) This function sets the user zone.
++ *
++ * \param ucDevAddr - Device address (a nibble) corresponding to the default
++ * value (0xb) or the device configuration register lower nibble.
++ * \param ucZoneNumber - user zone number to set
++ * \param ucAntiTearing - antitearing flag. If TRUE, anti-tearing is enabled.
++ * Anti-tearing should not be used unless required, as it causes more write
++ * cycles than necessary.
++ *
++ * \return Result of ll_SendCommand().
++ *
++ * \remarks Example: ucReturn = cm_SetUserZone(DEFAULT_ADDRESS, 3, FALSE);\n
++ * Sets the device at the default address (0xb) to user zone 3; anti-tearing
++ * is not enabled.
++ * Return SUCCESS or the result of ll_SendCommand()
++ */
++extern RETURN_CODE cm_SetUserZone(uchar ucDevAddr, uchar ucZoneNumber, \
++ uchar ucAntiTearing);
++
++/** \brief Read data from the Configuration Zone
++ *
++ * The input parameters determine which device address to read, which
++ * starting address in the configuration zone to read from, how many
++ * bytes to read, and where to place the returned data.
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \param ucCryptoAddr - Configuration Zone address - see the Configuration
++ * Zone map for the specific CryptoMemory Device to determine the address
++ * of the appropriate parameter.
++ * \param pucBuffer - Pointer to buffer to contain returned data,
++ * which must be large enough to hold ucCount bytes.
++ * \param ucCount - the number of bytes to read
++ * \return SUCCESS or the result of ll_SendCommand() or ll_ReceiveData()
++ *
++ * \remarks
++ * Example: ucReturn = cm_ReadConfigZone(DEFAULT_ADDRESS, 0x0A, ucData, 2);\n
++ * Reads 2 bytes at address 0x0A from the DEFAULT_ADDRESS (0xb) into ucData.\n
++ * Return SUCCESS or the result of ll_SendCommand() or
++ * ll_ReceiveData().
++ */
++extern RETURN_CODE cm_ReadConfigZone(uchar ucDevAddr, uchar ucCryptoAddr, \
++ puchar pucBuffer, uchar ucCount);
++
++/** \brief Read Fuse Byte from the device specified by ucDevAddr
++ *
++ * Fuse values are (in bit order from 3 to 0):
++ * - SEC (blown by Atmel before shipment, locks Lot History Code)
++ * - FAB (locks Answer to Reset and Fab Code)
++ * - CMA (locks Card Manufacturer Code)
++ * - PER (locks the remaining portions of the Configuration Zone)
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \param pucFuze - A pointer to a byte to hold the fuse data
++ * \return SUCCESS or ll_SendCommand() or ll_ReceiveData() result.
++ *
++ * \remarks Example: ucReturn = ReadFuse(DEFAULT_ADDRESS, ucData);\n
++ * Reads fuse data from device at DEFAULT_ADDRESS into
++ * ucData.
++ * Return SUCCESS or the result of ll_SendCommand() or
++ * ll_ReceiveData().
++ */
++extern RETURN_CODE cm_ReadFuse(uchar ucDevAddr, puchar pucFuze);
++
++/** \brief Read Checksum
++ *
++ * If the UCR bit in the Device Configuration Register is 1, the cryptographic
++ * engine will be reset. If UCR = 0, it will not be reset.\n
++ * This function provides a method to check on the synchronicity of the host
++ * and device cryptoengines without affecting the attempts counters.
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \param pucChkSum - pointer to 2 bytes to store calculated CheckSum
++ * \return SUCCESS or the results of ll_SendCommand() or ll_ReceiveData().
++ *
++ * \remarks Example: ucReturn = cm_ReadChecksum(DEFAULT_ADDRESS, ucData);\n
++ * Reads the checksum value into ucData for the device at
++ * DEFAULT_ADDRESS.
++ * Return SUCCESS or the result of ll_SendCommand() or or
++ * ll_ReceiveData().
++ */
++extern RETURN_CODE cm_ReadChecksum(uchar ucDevAddr, puchar pucChkSum);
++
++/** \brief Send checksum.
++ *
++ * If device is in authentication mode, any user zone write must be followed
++ * with a cm_SendChecksum command with the proper checksum. Otherwise the
++ * device will not complete the write. An invalid checksum will also clear
++ * authentication.
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \param pucChkSum - pointer to 2 byte array holding checksum.
++ * Always pass NULL so that function will calculate the appropriate checksum.
++ *
++ * \return Results of ll_SendCommand() or ll_SendData()
++ *
++ * \remarks Example: ucReturn = cm_SendChecksum(DEFAULT_ADDRESS, NULL);\n
++ * Sends the correct checksum to the device at the DEFAULT_ADDRESS.
++ * Return SUCCESS or the result of ll_SendCommand() or or
++ * ll_SendData().
++ */
++extern RETURN_CODE cm_SendChecksum(uchar ucDevAddr, puchar pucChkSum);
++
++/** \brief This routine activates Authentication and (optionally)
++ * Encryption modes.
++ *
++ * When called the function:
++ * - reads the current cryptogram (C<SUB>i</SUB>) of the specified key set,
++ * \if CMC_DOXY
++ * - computes the next cryptogram (C<SUP>A</SUP>) based on the secret
++ * KID pucKey (KID) and the random number (Q).
++ * \else
++ * - computes the next cryptogram (C<SUP>A</SUP>) based on the secret
++ * seed pucKey (G) and the random number (Q).
++ * \endif
++ * - sends the (CH<SUP>A</SUP>) (crypto challenge) and the random number to the
++ * CryptoMemory device,
++ * - Reads the chip's newly calculated cryptogram (C<SUB>i</SUB><SUP>A</SUP>)
++ * and compares it with C<SUP>A</SUP>.
++ *
++ * If C<SUP>A</SUP> matches C<SUB>i</SUB><SUP>A</SUP> then
++ * authentication is successful AND:
++ * - both host (function) and device save the new Cryptogram and
++ * calculate new Session Keys.
++ *
++ * In addition, if ucEncrypt is TRUE the function, using the new Session Key
++ * and a new random number
++ * - computes a new challenge (CH<SUP>E</SUP>), a new cryptogram
++ * (C<SUP>E</SUP>) and a new Session Key (S<SUP>E</SUP>),
++ * - sends the challenge (CH<SUP>E</SUP>) and random number (Q) to the
++ * CryptoMemory device,
++ * - reads the device's newly calculated cryptogram (C<SUB>i</SUB><SUP>E</SUP>)
++ * and compares it with C<SUP>E</SUP>.
++ *
++ * If the two match then encryption is activated.
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \if CMC_DOXY
++ * \param ucKeySet - index number of the current key set to be used for
++ * authentication / encryption. Upper nible is contained F index and lower
++ * is contained G index.
++ * \param pucBuff1 - pointer to 16 bytes Secret KID.
++ * \param pucBuff2 - pointer to 8 bytes uniqui serial or
++ * identification number of CM.
++ * \else
++ * \param ucKeySet - index number of the current key set to be used for
++ * authentication / encryption. Upper nible is ignored and
++ * lower is contained G index.
++ * \param pucBuff1 - pointer to the Secret Seed (G) associated
++ * with this key set.
++ * \param pucBuff2 - random number. If NULL, the function will
++ * calculate new random numbers for both actions.)
++ * \endif
++ * \param ucEncrypt - if TRUE command the device to enter encryption mode also
++ * (with the same key set).
++ *
++ * \return SUCCESS or the results of ll_SendCommand(), ll_ReceiveData()
++ * or ll_SendData() result.
++ *
++ * \remarks Example: \n
++ * ucReturn = cm_VerifyCrypto(DEFAULT_ADDRESS, 1, ucData, NULL, TRUE);\n
++ * Enter authentication mode with key set 1, secret seed in ucData,
++ * calculate a random number for the user, and enter the encryption mode.\n
++ * Return SUCCESS or the result of ll_SendCommand() or
++ * ll_SendData() or ll_ReceiveData().
++ */
++extern RETURN_CODE cm_VerifyCrypto(uchar ucDevAddr, uchar ucKeySet, \
++ puchar pucBuff1, puchar pucBuff2, \
++ uchar ucEncrypt);
++
++/** \brief This routine reset active password
++ *
++ * When called the function:
++ * - sends the Verify Password Command with the second byte set to 0xFF.
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ *
++ * \return SUCCESS or the results of ll_SendCommand() or ll_SendData().
++ *
++ * \remarks Example: \n
++ * ucReturn = cm_ResetPassword(DEFAULT_ADDRESS);\n
++ * Reset active password for device at address
++ * DEFAULT_ADDRESS.
++ * Return SUCCESS or the result of ll_SendCommand() or or
++ * ll_SendData().
++ */
++extern RETURN_CODE cm_ResetPassword(uchar ucDevAddr);
++
++/** \brief This routine reset authentication and encryption
++ * and resets the cryptoengine.
++ *
++ * When called the function:
++ * - sends the Verify Crypto Command with no arguments and
++ * - Resets the CryptoEngine in firmware.
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ *
++ * \return SUCCESS or the results of ll_SendCommand() or ll_SendData().
++ *
++ * \remarks Example: \n
++ * ucReturn = cm_ResetCrypto(DEFAULT_ADDRESS);\n
++ * Leave authentication and encryption mode for device at address
++ * DEFAULT_ADDRESS.
++ * Return SUCCESS or the result of ll_SendCommand() or or
++ * ll_SendData().
++ */
++extern RETURN_CODE cm_ResetCrypto(uchar ucDevAddr);
++
++/** \brief Verifies Password.
++ *
++ * Using the verify password command, send either the "write" or "read"
++ * password to the appropriate address. Then read the password location
++ * in the config zone and see if the password attempts counter = 0xff
++ * (passed).\n
++ * If Authentication mode is active, then this function encrypts passwords
++ * automatically.
++ *
++ * \param ucDevAddr - Device Address (a nibble) corresponding to the
++ * default value (0xb) or the device configuration register lower
++ * nibble.
++ * \if CMC_DOXY
++ * \param pucPassword - pointer to password to verify and only valid if authentication
++ * is not required.
++ * \param ucSet - index number of the password set
++ * system with Companion devie: bit 0-3: CM password index
++ * bit 4-7: companion pwd index.
++ * \else
++ * \param pucPassword - pointer to password to verify.
++ * \param ucSet - index number of the password set
++ * system without Companion device, bit 0-3: CM password index
++ * bit 4-7 are ignore.
++ * system with Companion devie: bit 0-3: CM password index
++ * bit 4-7: companion pwd index.
++ * \endif
++ * \param ucRW - whether it's the read or write password. Read = 1, Write = 0.
++ *
++ * \return SUCCESS or the results of ll_SendCommand() or ll_SendData() or
++ * ll_ReceiveData()
++ *
++ * \remarks
++ * Example: ucReturn = cm_VerifyPassword(DEFAULT_ADDRESS, ucData, 7, 0);\n
++ * Verify the write password number 7 at the DEFAULT_ADDRESS.\n
++ * Return SUCCESS or the result of ll_SendCommand() or
++ * ll_SendData() or ll_ReceiveData().
++ */
++extern RETURN_CODE cm_VerifyPassword(uchar ucDevAddr, puchar pucPassword, \
++ uchar ucSet, uchar ucRW);
++
++#ifdef CMC
++/*
++****************************************************
++* CryptoMemory Companion (CMC) Function Prototypes
++****************************************************
++*/
++
++/**\if CMC_DOXY
++ * \brief Verifies System Digest
++ *
++ * If Mode bit 0 = 0, simply verifies that *pucDigest matches FlashDigest.
++ * If Mode bit 0 = 1, verifies that SHA-1(Digest, FlashDigest) = *pucSignature.
++ *
++ * \param ucCmcDevAddr - CMC device address
++ * \param pucExtDigest - pointer to 20 bytes of external Digest
++ * \param pucIntDigest - pointer to 20 bytes of internal EEPROM Flash Digest.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_VerifyFlash(uchar ucCmcDevAddr, puchar pucExtDigest, \
++ puchar pucIntDigest);
++
++/** \if CMC_DOXY
++ * \brief Start Challenge
++ *
++ * This API will use to verify the mutually authenticate between system processor and
++ * compnaion device. If either CMC or System secret seeds is not the same as in EEPROM,
++ * then CMC will return FAIL. If both secret seeds are the same as in EEPROM, CMC will
++ * return SUCCESS.
++ *
++ * \param ucCmcDevAddr - CMC device address
++ * \param pucCmcChallenge - pointer to 20 bytes of CMC Challenge
++ * \param pucCmcSeed - pointer to 16 bytes of CMC secret seed. This CMC secret seed bytes
++ * must be the same as CMCSeed in EEPROM
++ * \param pucSystemSeed - pointer to 16 bytes of System secret seed. This System secret
++ * seed bytes must be the same as SystemSeed in EEPROM.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_StartChallenge(uchar ucCmcDevAddr, puchar pucCmcChallenge, \
++ puchar pucCmcSeed, puchar pucSystemSeed);
++
++/** \if CMC_DOXY
++ * \brief Gets a 20 byte random number from the Companion Chip
++ *
++ * \param ucCmcDevAddr - CMC device address
++ * \param pucData - pointer to returned 20 byte random number.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_GetRandom(uchar ucCmcDevAddr, puchar pucData) ;
++
++/** \if CMC_DOXY
++ * \brief Increments the value of the specified counter by 1
++ *
++ * \param ucCmcDevAddr - CMC device address
++ * \param ucSelector - Counter to increment (0 - 3).
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_IncrementCounter(uchar ucCmcDevAddr, uchar ucSelector) ;
++
++/** \if CMC_DOXY
++ * \brief Returns the least 32 bits of the specified counter.
++ *
++ * \param ucCmcDevAddr - CMC device address
++ * \param ucSelector - Counter to read (0 - 3).
++ * \param pucData - pointer to least significant 4 bytes of counter data.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_ReadCounter(uchar ucCmcDevAddr, uchar ucSelector, \
++ puchar pucData) ;
++
++/** \if CMC_DOXY
++ * \brief Writes the contents of the specified address.
++ *
++ * Writes up to the end of the read/write memory space.
++ * After locking, only the read/write space can be written.
++ * Up to 16 bytes may be written with a single operation
++ *
++ * \param ucCmcDevAddr - CMC device address
++ * \param uiAddress - Address of first byte to write. 7 most sig. bits ignored.
++ * \param ucCount - Write ucCount bytes to EEPROM (data
++ * follows).
++ * \param pucData - pointer to clear text data to write.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_WriteMemory(uchar ucCmcDevAddr, uint uiAddress, \
++ uchar ucCount, puchar pucData) ;
++
++/** \if CMC_DOXY
++ * \brief Authorize to writes a single byte in the first 16
++ * bytes of the ReadOnly section at the specified address.
++ *
++ * Address must point to one of the first 16 bytes within the ReadOnly
++ * section of memory. This command only works if Mode:Bit2 = 1.
++ * Only one byte may be written with a each operation
++ *
++ * \param ucCmcDevAddr - CMC ddevice address
++ * \param uiAddress - Address of byte to write. 7 most sig. bits ignored.
++ * \param ucData - clear text data to write.
++ * \param pucF0 - pointer to buffer that contained 8 bytes
++ * of F0
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_WriteMemoryAuthorized(uchar ucCmcDevAddr, uint uiAddress, \
++ uchar ucData, puchar pucF0) ;
++
++/** \if CMC_DOXY
++ * \brief Writes 16 byte page of EEPROM with encryption.
++ *
++ * Writes 16 byte pages up to the end of the read/write memory space.
++ * Uses the SHA-1 of (Address || EncKey || Nonce).
++ * Smaller blocks than 16 bytes cannot be written with this command.
++ * Cannot be executed after Companion Chip is locked.
++ *
++ * \param ucCmcDevAddr - CMC ddevice address
++ * \param uiAddress - Address of the 16 byte page to write. 7 most significant
++ * and 4 least significant bits ignored.
++ * \param pucData - pointer to 16 bytes of clear data to write.
++ * \param pucNonce - Random value encryption seed.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_WriteMemoryEncrypted(uchar ucCmcDevAddr, uint uiAddress, \
++ puchar pucData, puchar pucNonce) ;
++
++/** \if CMC_DOXY
++ * \brief Read the contents of the specified address.
++ *
++ * Reads up to the end of the read/write memory space.
++ * After locking, only the read only and the read/write space can be read.
++ * Up to 16 bytes may be read with a single operation
++ *
++ * \param ucCmcDevAddr - CMC ddevice address
++ * \param uiAddress - Address of first byte to read. 7 most sig. bits ignored.
++ * \param ucCount - Read ucCount+1 bytes from EEPROM.
++ * \param pucData - pointer to clear text data read from Companion Chip.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_ReadMemory(uchar ucCmcDevAddr, uint uiAddress, \
++ uchar ucCount, puchar pucData) ;
++
++/** \if CMC_DOXY
++ * \brief Read the specified 32 byte block and computes the
++ * SHA-1 digest.
++ *
++ * Provides a mechanism of verifying that the personalization of the chip
++ * completed correctly before locked.
++ * Note that verifying the digest of 0 requires knowing EncKey.
++ * Cannot be executed after Companion Chip is locked.
++ *
++ * \param ucCmcDevAddr - CMC ddevice address
++ * \param uiAddress - Address of the 32 byte page to read. 7 most significant
++ * and 5 least significant bits ignored.
++ * \param pucData - pointer to 20 byte digest
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_ReadMemoryDigest(uchar ucCmcDevAddr, uint uiAddress, \
++ puchar pucData) ;
++
++/** \if CMC_DOXY
++ * \brief Read the contents of the Manufacturing ID and Lock
++ * Byte.
++ *
++ * \param ucCmcDevAddr - CMC ddevice address
++ *
++ * \param pucData - pointer to 16 byte Manufacturing ID and Lock Byte.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_ReadManufID(uchar ucCmcDevAddr, puchar pucData) ;
++
++/** \if CMC_DOXY
++ * \brief Lock the current memory values.
++ *
++ * \param ucCmcDevAddr - CMC ddevice address.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern RETURN_CODE cmc_Lock(uchar ucCmcDevAddr) ;
++
++/** \if CMC_DOXY
++ * \brief Returns the status byte from a CMC device.
++ *
++ * \param ucCmcDevAddr - CMC ddevice address
++ *
++ * \return uchar - status from a CMC device
++ * \endif
++*/
++extern uchar cmc_Status(uchar ucCmcDevAddr) ;
++
++#endif /* CMC */
++
++/**
++ * \brief Send command bytes to a device.
++ *
++ * This routine is external reference by library
++ *
++ * \param pucInsBuf - pointer to buffer of command bytes to
++ * send.
++ * \param ucLen - number of command bytes to send.
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ */
++extern RETURN_CODE ll_SendCommand(puchar pucInsBuf, uchar ucLen);
++
++/** \if CMC_DOXY
++ * \brief Receive data bytes from a CMC device.
++ *
++ * This routine is external reference by library.
++ *
++ * \param pucRecBuf - pointer to buffer of receving data bytes
++ * \param ucLen - number of data bytes to receive
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++#ifdef CMC
++extern RETURN_CODE ll_CmcReceiveData(puchar pucRecBuf, uchar ucLen);
++#endif
++
++/** \brief Receive data bytes from a CM device.
++ *
++ * This routine is external reference by library.
++ *
++ * \param pucRecBuf - pointer to buffer of receving data bytes
++ * \param ucLen - number of data bytes to receive
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ */
++extern RETURN_CODE ll_ReceiveData(puchar pucRecBuf, uchar ucLen);
++
++/** \brief Send data bytes to a device.
++ *
++ * This routine is external reference by library.
++ *
++ * \param pucSendBuf - pointer to buffer of data bytes to send
++ * \param ucLen - number of data bytes to send
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ */
++extern RETURN_CODE ll_SendData(puchar pucSendBuf, uchar ucLen);
++
++/**
++ * \brief Wait for number of clock ticks
++ * This routine is external reference by library.
++ *
++ * \param ucLoop - number of (Start + 15 clocks + Stop) to loop
++ */
++extern void ll_WaitClock(uchar ucLoop);
++
++/**
++ * \brief Copy number of bytes from source to destination
++ * locations.
++ *
++ * This routine is external reference by library.
++ *
++ * \param pucDestMem - destination buffer
++ * \param pucSrcMem - source buffer
++ * \param uiCnt - number of bytes to copy
++ */
++extern void lib_memcpy(puchar pucDestMem, puchar pucSrcMem, uint uiCnt);
++
++/**
++ * \brief Compare two strings.
++ *
++ * This routine is external reference by library.
++ *
++ * \param pucMem1 - string 1 buffer
++ * \param pucMem2 - string 2 buffer
++ * \param uiCnt - number of bytes to compare
++ */
++extern uchar lib_memcmp(puchar pucMem1, puchar pucMem2, uint uiCnt);
++
++/**
++ * \brief Allocate memory from memory pool.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucBytes - number of bytes to allocate
++ *
++ * \return puchar - pointer to allocated buffer
++ *
++ */
++extern puchar lib_malloc(uchar ucBytes);
++
++/** \brief Deallocate memory back to memory pool.
++ *
++ * This routine is external reference by library.
++ *
++ * \param pucBuff - pointer to deallocated buffer
++ */
++extern void lib_free(puchar pucBuff);
++
++/** \brief Get random byte.
++ *
++ * This routine is external reference by library.
++ *
++ * \return uchar - random byte
++ */
++extern uchar lib_rand(void);
++
++/** \brief Get CM device address based from device index.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucIndex - CM device index
++ *
++ * \return uchar - CM device address
++ */
++extern uchar getCMDevAddr(uchar ucIndex);
++
++/** \brief Get CM device index based from device address.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucCmDevAddr - CM device address
++ *
++ * \return uchar - CM device index
++ */
++extern uchar cm_FindDeviceIndex(uchar ucCmDevAddr);
++
++/** \brief Get CM device type based from device index.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucIndex - CM device index
++ *
++ * \return CM_DEVICE_TYPE - CM device type
++ */
++extern CM_DEVICE_TYPE getCMDevType(uchar ucIndex);
++
++/** \brief Get number CM device.
++ *
++ * This routine is external reference by library.
++ *
++ * \return uchar - number of CM devices
++ */
++extern uchar getNumCmDev(void);
++
++
++/** \brief Get library version number.
++ *
++ * \return puchar - pointer to string of characters
++ */
++extern puchar getLibVersNum(void);
++
++#ifdef CMC
++
++/** \if CMC_DOXY
++ * \brief Wait for BUSY bit from CMC status to CLEAR.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucCmcDevAddr - CMC device address
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern uchar WaitForNotBusy(uchar ucCmcDevAddr);
++
++/** \if CMC_DOXY
++ * \brief Wait for DATA bit from CMC status to SET.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucCmcDevAddr - CMC device address
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ * \endif
++ */
++extern uchar WaitForData(uchar ucCmcDevAddr);
++
++/** \brief Wait for STARTUPDONE bit from CMC status to SET.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucCmcDevAddr - CMC device address
++ *
++ * \return SUCCESS or the result of cmc_Status()
++ */
++extern uchar WaitForStartupDone(uchar ucCmcDevAddr);
++
++/** \if CMC_DOXY
++ * \brief Get CMC device index based from device address.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucCmcDevAddr - CMC device address
++ *
++ * \return uchar - CMC device index
++ * \endif
++ */
++extern uchar cmc_FindDeviceIndex(uchar ucCmcDevAddr);
++
++/** \if CMC_DOXY
++ * \brief Get CMC device address based from device index.
++ *
++ * This routine is external reference by library.
++ *
++ * \param ucIndex - CMC device index
++ *
++ * \return uchar - CMC Cdevice address
++ * \endif
++ */
++extern uchar getCMCDevAddr(uchar ucIndex);
++
++
++/** \if CMC_DOXY
++ * \brief Reset CMC device.
++ *
++ * This routine is external reference by library.
++ * \endif
++ */
++extern void cmc_Reset(void);
++
++/** \if CMC_DOXY
++ * \brief SHA-1 processing
++ *
++ * \param pucChallenge - First input to SHA-1 algorithm
++ * \param ucLen - Length of pucChallenge
++ * \param pucResponse - Output from SHA-1 algorithm
++ * \endif
++ */
++extern void cmc_SHA1(puchar pucInData, uchar ucLen, puchar pucOutData);
++#endif
++
++#endif
++
+diff --git a/drivers/misc/smartq5_encrypt/smartq5_encrypt.c b/drivers/misc/smartq5_encrypt/smartq5_encrypt.c
+new file mode 100644
+index 0000000..3626fa7
+--- /dev/null
++++ b/drivers/misc/smartq5_encrypt/smartq5_encrypt.c
+@@ -0,0 +1,117 @@
++/****************************************************************
++ * $ID: smartq5_encrypt.c Sun, 22 Mar 2009 15:48:25 +0800 root $ *
++ * *
++ * Description: *
++ * *
++ * Maintainer: (Meihui Fan) <mhfan@hhcn.com> *
++ * *
++ * Copyright (C) 2009 HHTech *
++ * www.hhcn.com, www.hhcn.org *
++ * All rights reserved. *
++ * *
++ * This file is free software; *
++ * you are free to modify and/or redistribute it *
++ * under the terms of the GNU General Public Licence (GPL). *
++ * *
++ * Last modified: Wed, 25 Mar 2009 15:38:46 +0800 by root #
++ ****************************************************************/
++#include <linux/module.h>
++#include <linux/poll.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/miscdevice.h>
++#include <linux/apm_bios.h>
++#include <linux/capability.h>
++#include <linux/sched.h>
++#include <linux/suspend.h>
++#include <linux/apm-emulation.h>
++#include <linux/freezer.h>
++#include <linux/device.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/init.h>
++#include <linux/completion.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <asm/arch/regs-gpio.h>
++#include <asm-arm/arch-s3c2410/gpio.h>
++#include <asm/system.h>
++
++typedef enum {
++ SCL_HIGH,
++ SCL_LOW,
++ SDA_HIGH,
++ SDA_LOW,
++ SDA_DATA
++} I2C_CMD;
++
++#define GPIO_SCL S3C_GPN0
++#define GPIO_SDA S3C_GPN1
++
++/*
++ * The smartq5_encrypt device is one of the misc char devices.
++ * This is its minor number.
++ */
++#define SMARTQ5_ENCRYPT_DEV_MINOR 234
++
++static int smartq5_encrypt_open(struct inode * inode, struct file * filp)
++{
++ return 0;
++}
++
++static int smartq5_encrypt_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
++{
++ int ret = 0;
++ switch (cmd) {
++ case SCL_HIGH:
++ gpio_direction_output(GPIO_SCL, 1);
++ break;
++ case SCL_LOW:
++ gpio_direction_output(GPIO_SCL, 0);
++ break;
++ case SDA_HIGH:
++ gpio_direction_input(GPIO_SDA); // important!
++ break;
++ case SDA_LOW:
++ gpio_direction_output(GPIO_SDA, 0);
++ break;
++ case SDA_DATA:
++ gpio_direction_input(GPIO_SDA);
++ ret = gpio_get_value(GPIO_SDA);
++ break;
++ }
++ return ret;
++}
++
++static struct file_operations smartq5_encrypt_fops = {
++ .owner = THIS_MODULE,
++ .ioctl = smartq5_encrypt_ioctl,
++ .open = smartq5_encrypt_open,
++};
++
++static struct miscdevice smartq5_encrypt_device = {
++ .minor = SMARTQ5_ENCRYPT_DEV_MINOR,
++ .name = "smartq5_encrypt",
++ .fops = &smartq5_encrypt_fops
++};
++
++static int __init smartq5_encrypt_init(void)
++{
++ return misc_register(&smartq5_encrypt_device);
++}
++
++static void __exit smartq5_encrypt_exit(void)
++{
++ misc_deregister(&smartq5_encrypt_device);
++}
++
++module_init(smartq5_encrypt_init);
++module_exit(smartq5_encrypt_exit);
++
++MODULE_AUTHOR("Guoqiang Wang");
++MODULE_DESCRIPTION("Encypt module for SmartQ5");
++MODULE_LICENSE("GPL");
++
++
++/**************** End Of File: smartq5_encrypt.c ****************/
++// vim:sts=4:ts=8:
+diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
+index aeb32a9..2816b81 100644
+--- a/drivers/mmc/card/block.c
++++ b/drivers/mmc/card/block.c
+@@ -424,7 +424,16 @@ static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
+ struct mmc_blk_data *md;
+ int devidx, ret;
+
++#ifdef CONFIG_MACH_SMDK6410 /* XXX: Make sure inand devidx = 0 */
++ if (card->host->index == 0) {
++ devidx = 0;
++ } else {
++ __set_bit(0, dev_use);
++ devidx = find_first_zero_bit(dev_use, MMC_NUM_MINORS);
++ }
++#else
+ devidx = find_first_zero_bit(dev_use, MMC_NUM_MINORS);
++#endif
+ if (devidx >= MMC_NUM_MINORS)
+ return ERR_PTR(-ENOSPC);
+ __set_bit(devidx, dev_use);
+@@ -470,6 +479,10 @@ static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
+ md->disk->fops = &mmc_bdops;
+ md->disk->private_data = md;
+ md->disk->queue = md->queue.queue;
++#ifdef CONFIG_MACH_SMDK6410 /* XXX: SD Card removable */
++ if (devidx != 0)
++ md->disk->flags |= GENHD_FL_REMOVABLE;
++#endif
+ md->disk->driverfs_dev = &card->dev;
+
+ /*
+diff --git a/drivers/mmc/core/sdio_cis.c b/drivers/mmc/core/sdio_cis.c
+index d5e51b1..8a92533 100644
+--- a/drivers/mmc/core/sdio_cis.c
++++ b/drivers/mmc/core/sdio_cis.c
+@@ -249,6 +249,10 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func)
+ printk(KERN_DEBUG
+ "%s: queuing CIS tuple 0x%02x length %u\n",
+ mmc_hostname(card->host), tpl_code, tpl_link);
++ /* HACK: break this loop */
++ ret = -EINVAL;
++ kfree(this);
++ /* END HACK */
+ } else {
+ const struct cis_tpl *tpl = cis_tpl_list + i;
+ if (tpl_link < tpl->min_size) {
+diff --git a/drivers/mmc/host/s3c-hsmmc.c b/drivers/mmc/host/s3c-hsmmc.c
+index 3d8c68e..236878c 100644
+--- a/drivers/mmc/host/s3c-hsmmc.c
++++ b/drivers/mmc/host/s3c-hsmmc.c
+@@ -691,6 +691,7 @@ static irqreturn_t s3c_hsmmc_irq (int irq, void *dev_id)
+ struct s3c_hsmmc_host *host = dev_id;
+ struct mmc_request *mrq;
+ u32 intsts;
++ int cardint = 0;
+
+ #ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
+ uint i, org_irq_sts;
+@@ -802,10 +803,10 @@ static irqreturn_t s3c_hsmmc_irq (int irq, void *dev_id)
+ s3c_hsmmc_finish_command(host);
+ s3c_hsmmc_data_irq(host, intsts & S3C_HSMMC_INT_DATA_MASK);
+ }
+-
+- intsts &= ~(S3C_HSMMC_INT_CMD_MASK | S3C_HSMMC_INT_DATA_MASK);
+ }
+
++ intsts &= ~(S3C_HSMMC_INT_CMD_MASK | S3C_HSMMC_INT_DATA_MASK);
++ intsts &= ~S3C_HSMMC_NIS_ERR;
+ /* XXX: fix later by scsuh */
+ #if 0
+ if (intsts & S3C_HSMMC_INT_BUS_POWER) {
+@@ -815,6 +816,12 @@ static irqreturn_t s3c_hsmmc_irq (int irq, void *dev_id)
+ }
+
+ intsts &= S3C_HSMMC_INT_BUS_POWER;
++#endif
++
++ if (intsts & S3C_HSMMC_INT_CARD_INT) {
++ intsts &= ~S3C_HSMMC_INT_CARD_INT;
++ cardint = 1;
++ }
+
+ if (intsts) {
+ printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
+@@ -822,7 +829,6 @@ static irqreturn_t s3c_hsmmc_irq (int irq, void *dev_id)
+
+ s3c_hsmmc_writel(intsts, S3C_HSMMC_NORINTSTS);
+ }
+-#endif
+
+ #ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
+ for (i=0; i<0x1000; i++) {
+@@ -838,6 +844,9 @@ insert:
+ out:
+ spin_unlock(&host->lock);
+
++ if (cardint)
++ mmc_signal_sdio_irq(host->mmc);
++
+ return result;
+ }
+
+@@ -868,7 +877,7 @@ static irqreturn_t s3c_hsmmc_irq_cd (int irq, void *dev_id)
+ return IRQ_HANDLED;
+
+
+- tasklet_schedule(&host->card_tasklet);
++ tasklet_schedule(&host->card_tasklet);
+ mmiowb();
+
+ spin_unlock(&host->lock);
+@@ -899,7 +908,8 @@ static void s3c_hsmmc_request (struct mmc_host *mmc, struct mmc_request *mrq)
+
+ host->mrq = mrq;
+
+- if ((s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT) || card_detect) {
++ if ((s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT) || card_detect
++ || host->plat_data->hwport == 2 || host->plat_data->hwport == 1) {
+ s3c_hsmmc_send_command(host, mrq->cmd);
+ } else {
+ host->mrq->cmd->error = -ENOMEDIUM;
+@@ -1085,9 +1095,41 @@ static void s3c_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ spin_unlock_irqrestore(&host->lock, iflags);
+ }
+
++static void s3c_hsmmc_sdio_irq(struct mmc_host *mmc, int enable)
++{
++ struct s3c_hsmmc_host *host;
++ unsigned long flags;
++ u16 stsen;
++ u16 sigen;
++
++ host = mmc_priv(mmc);
++
++ spin_lock_irqsave(&host->lock, flags);
++
++ stsen = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTSEN);
++ sigen = s3c_hsmmc_readw(S3C_HSMMC_NORINTSIGEN);
++
++ stsen &= ~S3C_HSMMC_INT_CARD_INT;
++ sigen &= ~S3C_HSMMC_INT_CARD_INT;
++
++ if (enable) {
++ s3c_hsmmc_writew(S3C_HSMMC_INT_CARD_INT, S3C_HSMMC_NORINTSTS);
++ stsen |= S3C_HSMMC_INT_CARD_INT;
++ sigen |= S3C_HSMMC_INT_CARD_INT;
++ }
++
++ s3c_hsmmc_writew(stsen, S3C_HSMMC_NORINTSTSEN);
++ s3c_hsmmc_writew(sigen, S3C_HSMMC_NORINTSIGEN);
++
++ mmiowb();
++
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
+ static struct mmc_host_ops s3c_hsmmc_ops = {
+ .request = s3c_hsmmc_request,
+ .set_ios = s3c_hsmmc_set_ios,
++ .enable_sdio_irq= s3c_hsmmc_sdio_irq,
+ };
+
+ static int s3c_hsmmc_probe (struct platform_device *pdev)
+@@ -1142,6 +1184,7 @@ static int s3c_hsmmc_probe (struct platform_device *pdev)
+ goto untasklet;
+ }
+
++ #if 0
+ /* To detect a card inserted on channel 0, an external interrupt is used. */
+ if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) {
+ host->irq_cd = platform_get_irq(pdev, 1);
+@@ -1156,6 +1199,7 @@ static int s3c_hsmmc_probe (struct platform_device *pdev)
+ set_irq_type(host->irq_cd, IRQT_LOW);
+ #endif
+ }
++ #endif
+
+ host->flags |= S3C_HSMMC_USE_DMA;
+
+@@ -1196,7 +1240,7 @@ static int s3c_hsmmc_probe (struct platform_device *pdev)
+ /* you must make sure that our hsmmc block can support
+ * up to 52MHz. by scsuh
+ */
+- mmc->f_max = 100 * MHZ;
++ mmc->f_max = plat_data->max_clock;
+ mmc->caps = plat_data->host_caps;
+ DBG("mmc->caps: %08x\n", mmc->caps);
+
+@@ -1249,11 +1293,13 @@ static int s3c_hsmmc_probe (struct platform_device *pdev)
+ if (ret)
+ goto untasklet;
+
++ #if 0
+ if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) {
+ ret = request_irq(host->irq_cd, s3c_hsmmc_irq_cd, 0, DRIVER_NAME, host);
+ if (ret)
+ goto untasklet;
+ }
++ #endif
+
+ s3c_hsmmc_ios_init(host);
+
+diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
+index 3286d2a..aa93ba4 100644
+--- a/drivers/net/dm9000.c
++++ b/drivers/net/dm9000.c
+@@ -112,8 +112,8 @@
+ #define writesw outsw
+ #define writesl outsl
+ #define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH)
+-#else
+-#define DM9000_IRQ_FLAGS IRQF_SHARED
++#else// XXX: for HHTech platform
++#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH)
+ #endif
+
+ /*
+@@ -588,9 +588,12 @@ dm9000_probe(struct platform_device *pdev)
+ ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
+ }
+
+- if (!is_valid_ether_addr(ndev->dev_addr))
+- printk("%s: Invalid ethernet MAC address. Please "
+- "set using ifconfig\n", ndev->name);
++ if (!is_valid_ether_addr(ndev->dev_addr)) {
++ random_ether_addr(ndev->dev_addr);
++
++ //printk("%s: Invalid ethernet MAC address. Please "
++ // "set using ifconfig\n", ndev->name);
++ } else get_random_bytes(&ndev->dev_addr[5], 1);
+
+ platform_set_drvdata(pdev, ndev);
+ ret = register_netdev(ndev);
+diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
+index 2c08c0a..784e6c0 100644
+--- a/drivers/net/wireless/Kconfig
++++ b/drivers/net/wireless/Kconfig
+@@ -295,6 +295,28 @@ config LIBERTAS_DEBUG
+ ---help---
+ Debugging support.
+
++config MARVELL_8686_SDIO
++ tristate "Official driver for Marvell SDIO 8686"
++ depends on WLAN_80211 && MMC
++ select WIRELESS_EXT
++ select IEEE80211
++ select FW_LOADER
++ ---help---
++ Official driver for Marvell 8686 devices.
++
++config MARVELL_8686_PROC_FS
++ bool "Enable proc-fs support for official marvell 8686 module."
++ depends on MARVELL_8686_SDIO
++ ---help---
++ Proc-fs support.
++
++config MARVELL_8686_DEBUG
++ bool "Enable full debugging output in the official marvell 8686 module."
++ depends on MARVELL_8686_SDIO
++ ---help---
++ Debugging support.
++
++
+ config AIRO
+ tristate "Cisco/Aironet 34X/35X/4500/4800 ISA and PCI cards"
+ depends on ISA_DMA_API && WLAN_80211 && (PCI || BROKEN)
+diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
+index 6f32b53..867b829 100644
+--- a/drivers/net/wireless/Makefile
++++ b/drivers/net/wireless/Makefile
+@@ -47,6 +47,8 @@ obj-$(CONFIG_PCMCIA_WL3501) += wl3501_cs.o
+ obj-$(CONFIG_USB_ZD1201) += zd1201.o
+ obj-$(CONFIG_LIBERTAS) += libertas/
+
++obj-$(CONFIG_MARVELL_8686_SDIO) += marvell8686/
++
+ rtl8187-objs := rtl8187_dev.o rtl8187_rtl8225.o
+ obj-$(CONFIG_RTL8187) += rtl8187.o
+
+diff --git a/drivers/net/wireless/libertas/Makefile b/drivers/net/wireless/libertas/Makefile
+index 0e27876..e4c8cd3 100644
+--- a/drivers/net/wireless/libertas/Makefile
++++ b/drivers/net/wireless/libertas/Makefile
+@@ -2,7 +2,7 @@ libertas-objs := main.o wext.o \
+ rx.o tx.o cmd.o \
+ cmdresp.o scan.o \
+ join.o 11d.o \
+- debugfs.o \
++ ioctl.o debugfs.o \
+ ethtool.o assoc.o
+
+ usb8xxx-objs += if_usb.o
+diff --git a/drivers/net/wireless/libertas/cmd.c b/drivers/net/wireless/libertas/cmd.c
+index be5cfd8..8b2c34c 100644
+--- a/drivers/net/wireless/libertas/cmd.c
++++ b/drivers/net/wireless/libertas/cmd.c
+@@ -1400,6 +1400,12 @@ int libertas_prepare_and_send_command(wlan_private * priv,
+ S_DS_GEN);
+ ret = 0;
+ break;
++ case CMD_802_11_TX_RATE_QUERY:
++ cmdptr->command = cpu_to_le16(CMD_802_11_TX_RATE_QUERY);
++ cmdptr->size = cpu_to_le16(sizeof(struct cmd_tx_rate_query) + S_DS_GEN);
++ adapter->cur_rate = 0;
++ ret = 0;
++ break;
+ default:
+ lbs_deb_host("PREP_CMD: unknown command 0x%04x\n", cmd_no);
+ ret = -1;
+diff --git a/drivers/net/wireless/libertas/cmdresp.c b/drivers/net/wireless/libertas/cmdresp.c
+index 8f90892..a413f88 100644
+--- a/drivers/net/wireless/libertas/cmdresp.c
++++ b/drivers/net/wireless/libertas/cmdresp.c
+@@ -194,6 +194,9 @@ static int wlan_ret_get_hw_spec(wlan_private * priv,
+ lbs_pr_info("unidentified region code; using the default (USA)\n");
+ }
+
++ /* HACK IT MAKE regioncode always equals 0x30 */
++ adapter->regioncode = 0x30;
++
+ if (adapter->current_addr[0] == 0xff)
+ memmove(adapter->current_addr, hwspec->permanentaddr, ETH_ALEN);
+
+@@ -310,7 +313,7 @@ static int wlan_ret_802_11_key_material(wlan_private * priv,
+ lbs_deb_enter(LBS_DEB_CMD);
+
+ /* Copy the returned key to driver private data */
+- if (action == CMD_ACT_GET) {
++ if (action == CMD_ACT_SET) {
+ u8 * buf_ptr = (u8 *) &pkeymaterial->keyParamSet;
+ u8 * resp_end = (u8 *) (resp + le16_to_cpu(resp->size));
+
+diff --git a/drivers/net/wireless/libertas/ioctl.c b/drivers/net/wireless/libertas/ioctl.c
+new file mode 100644
+index 0000000..369ffc4
+--- /dev/null
++++ b/drivers/net/wireless/libertas/ioctl.c
+@@ -0,0 +1,1046 @@
++/**
++ * This file contains ioctl functions
++ */
++
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/if.h>
++#include <linux/if_arp.h>
++#include <linux/wireless.h>
++
++#include <net/iw_handler.h>
++#include <net/ieee80211.h>
++
++#include "host.h"
++#include "radiotap.h"
++#include "decl.h"
++#include "defs.h"
++#include "dev.h"
++#include "join.h"
++#include "wext.h"
++
++#define MAX_SCAN_CELL_SIZE (IW_EV_ADDR_LEN + \
++ IW_ESSID_MAX_SIZE + \
++ IW_EV_UINT_LEN + IW_EV_FREQ_LEN + \
++ IW_EV_QUAL_LEN + IW_ESSID_MAX_SIZE + \
++ IW_EV_PARAM_LEN + 40) /* 40 for WPAIE */
++
++#define WAIT_FOR_SCAN_RRESULT_MAX_TIME (10 * HZ)
++
++#define ENTER()
++#define LEAVE()
++#define lbs_pr_debug lbs_deb_ioctl
++
++static int wlan_set_region(wlan_private * priv, u16 region_code)
++{
++ int i;
++
++ for (i = 0; i < MRVDRV_MAX_REGION_CODE; i++) {
++ // use the region code to search for the index
++ if (region_code == libertas_region_code_to_index[i]) {
++ //priv->adapter->regiontableindex = (u16) i;
++ priv->adapter->regioncode = region_code;
++ break;
++ }
++ }
++
++ // if it's unidentified region code
++ if (i >= MRVDRV_MAX_REGION_CODE) {
++ lbs_pr_debug(1, "region Code not identified\n");
++ LEAVE();
++ return -1;
++ }
++
++ if (libertas_set_regiontable(priv, priv->adapter->regioncode, 0)) {
++ LEAVE();
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static inline int hex2int(char c)
++{
++ if (c >= '0' && c <= '9')
++ return (c - '0');
++ if (c >= 'a' && c <= 'f')
++ return (c - 'a' + 10);
++ if (c >= 'A' && c <= 'F')
++ return (c - 'A' + 10);
++ return -1;
++}
++
++/* Convert a string representation of a MAC address ("xx:xx:xx:xx:xx:xx")
++ into binary format (6 bytes).
++
++ This function expects that each byte is represented with 2 characters
++ (e.g., 11:2:11:11:11:11 is invalid)
++
++ */
++static char *eth_str2addr(char *ethstr, u8 * addr)
++{
++ int i, val, val2;
++ char *pos = ethstr;
++
++ /* get rid of initial blanks */
++ while (*pos == ' ' || *pos == '\t')
++ ++pos;
++
++ for (i = 0; i < 6; i++) {
++ val = hex2int(*pos++);
++ if (val < 0)
++ return NULL;
++ val2 = hex2int(*pos++);
++ if (val2 < 0)
++ return NULL;
++ addr[i] = (val * 16 + val2) & 0xff;
++
++ if (i < 5 && *pos++ != ':')
++ return NULL;
++ }
++ return pos;
++}
++
++/* this writes xx:xx:xx:xx:xx:xx into ethstr
++ (ethstr must have space for 18 chars) */
++static int eth_addr2str(u8 * addr, char *ethstr)
++{
++ int i;
++ char *pos = ethstr;
++
++ for (i = 0; i < 6; i++) {
++ sprintf(pos, "%02x", addr[i] & 0xff);
++ pos += 2;
++ if (i < 5)
++ *pos++ = ':';
++ }
++ return 17;
++}
++
++/**
++ * @brief Add an entry to the BT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_bt_add_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char ethaddrs_str[18];
++ char *pos;
++ u8 ethaddr[ETH_ALEN];
++
++ ENTER();
++ if (copy_from_user(ethaddrs_str, wrq->u.data.pointer,
++ sizeof(ethaddrs_str)))
++ return -EFAULT;
++
++ if ((pos = eth_str2addr(ethaddrs_str, ethaddr)) == NULL) {
++ lbs_pr_info("BT_ADD: Invalid MAC address\n");
++ return -EINVAL;
++ }
++
++ lbs_pr_debug(1, "BT: adding %s\n", ethaddrs_str);
++ LEAVE();
++ return (libertas_prepare_and_send_command(priv, CMD_BT_ACCESS,
++ CMD_ACT_BT_ACCESS_ADD,
++ CMD_OPTION_WAITFORRSP, 0, ethaddr));
++}
++
++/**
++ * @brief Delete an entry from the BT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_bt_del_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char ethaddrs_str[18];
++ u8 ethaddr[ETH_ALEN];
++ char *pos;
++
++ ENTER();
++ if (copy_from_user(ethaddrs_str, wrq->u.data.pointer,
++ sizeof(ethaddrs_str)))
++ return -EFAULT;
++
++ if ((pos = eth_str2addr(ethaddrs_str, ethaddr)) == NULL) {
++ lbs_pr_info("Invalid MAC address\n");
++ return -EINVAL;
++ }
++
++ lbs_pr_debug(1, "BT: deleting %s\n", ethaddrs_str);
++
++ return (libertas_prepare_and_send_command(priv,
++ CMD_BT_ACCESS,
++ CMD_ACT_BT_ACCESS_DEL,
++ CMD_OPTION_WAITFORRSP, 0, ethaddr));
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief Reset all entries from the BT table
++ * @param priv A pointer to wlan_private structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_bt_reset_ioctl(wlan_private * priv)
++{
++ ENTER();
++
++ lbs_pr_alert( "BT: resetting\n");
++
++ return (libertas_prepare_and_send_command(priv,
++ CMD_BT_ACCESS,
++ CMD_ACT_BT_ACCESS_RESET,
++ CMD_OPTION_WAITFORRSP, 0, NULL));
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief List an entry from the BT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_bt_list_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int pos;
++ char *addr1;
++ struct iwreq *wrq = (struct iwreq *)req;
++ /* used to pass id and store the bt entry returned by the FW */
++ union {
++ int id;
++ char addr1addr2[2 * ETH_ALEN];
++ } param;
++ static char outstr[64];
++ char *pbuf = outstr;
++ int ret;
++
++ ENTER();
++
++ if (copy_from_user(outstr, wrq->u.data.pointer, sizeof(outstr))) {
++ lbs_pr_debug(1, "Copy from user failed\n");
++ return -1;
++ }
++ param.id = simple_strtoul(outstr, NULL, 10);
++ pos = sprintf(pbuf, "%d: ", param.id);
++ pbuf += pos;
++
++ ret = libertas_prepare_and_send_command(priv, CMD_BT_ACCESS,
++ CMD_ACT_BT_ACCESS_LIST,
++ CMD_OPTION_WAITFORRSP, 0,
++ (char *)&param);
++
++ if (ret == 0) {
++ addr1 = param.addr1addr2;
++
++ pos = sprintf(pbuf, "ignoring traffic from ");
++ pbuf += pos;
++ pos = eth_addr2str(addr1, pbuf);
++ pbuf += pos;
++ } else {
++ sprintf(pbuf, "(null)");
++ pbuf += pos;
++ }
++
++ wrq->u.data.length = strlen(outstr);
++ if (copy_to_user(wrq->u.data.pointer, (char *)outstr,
++ wrq->u.data.length)) {
++ lbs_pr_debug(1, "BT_LIST: Copy to user failed!\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief Find the next parameter in an input string
++ * @param ptr A pointer to the input parameter string
++ * @return A pointer to the next parameter, or 0 if no parameters left.
++ */
++static char * next_param(char * ptr)
++{
++ if (!ptr) return NULL;
++ while (*ptr == ' ' || *ptr == '\t') ++ptr;
++ return (*ptr == '\0') ? NULL : ptr;
++}
++
++/**
++ * @brief Add an entry to the FWT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_add_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char in_str[128];
++ static struct cmd_ds_fwt_access fwt_access;
++ char *ptr;
++
++ ENTER();
++ if (copy_from_user(in_str, wrq->u.data.pointer, sizeof(in_str)))
++ return -EFAULT;
++
++ if ((ptr = eth_str2addr(in_str, fwt_access.da)) == NULL) {
++ lbs_pr_alert( "FWT_ADD: Invalid MAC address 1\n");
++ return -EINVAL;
++ }
++
++ if ((ptr = eth_str2addr(ptr, fwt_access.ra)) == NULL) {
++ lbs_pr_alert( "FWT_ADD: Invalid MAC address 2\n");
++ return -EINVAL;
++ }
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.metric =
++ cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++ else
++ fwt_access.metric = FWT_DEFAULT_METRIC;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.dir = (u8)simple_strtoul(ptr, &ptr, 10);
++ else
++ fwt_access.dir = FWT_DEFAULT_DIR;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.ssn =
++ cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++ else
++ fwt_access.ssn = FWT_DEFAULT_SSN;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.dsn =
++ cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++ else
++ fwt_access.dsn = FWT_DEFAULT_DSN;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.hopcount = simple_strtoul(ptr, &ptr, 10);
++ else
++ fwt_access.hopcount = FWT_DEFAULT_HOPCOUNT;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.ttl = simple_strtoul(ptr, &ptr, 10);
++ else
++ fwt_access.ttl = FWT_DEFAULT_TTL;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.expiration =
++ cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++ else
++ fwt_access.expiration = FWT_DEFAULT_EXPIRATION;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.sleepmode = (u8)simple_strtoul(ptr, &ptr, 10);
++ else
++ fwt_access.sleepmode = FWT_DEFAULT_SLEEPMODE;
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.snr =
++ cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++ else
++ fwt_access.snr = FWT_DEFAULT_SNR;
++
++#ifdef DEBUG
++ {
++ char ethaddr1_str[18], ethaddr2_str[18];
++ eth_addr2str(fwt_access.da, ethaddr1_str);
++ eth_addr2str(fwt_access.ra, ethaddr2_str);
++ lbs_pr_debug(1, "FWT_ADD: adding (da:%s,%i,ra:%s)\n", ethaddr1_str,
++ fwt_access.dir, ethaddr2_str);
++ lbs_pr_debug(1, "FWT_ADD: ssn:%u dsn:%u met:%u hop:%u ttl:%u exp:%u slp:%u snr:%u\n",
++ fwt_access.ssn, fwt_access.dsn, fwt_access.metric,
++ fwt_access.hopcount, fwt_access.ttl, fwt_access.expiration,
++ fwt_access.sleepmode, fwt_access.snr);
++ }
++#endif
++
++ LEAVE();
++ return (libertas_prepare_and_send_command(priv, CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_ADD,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&fwt_access));
++}
++
++/**
++ * @brief Delete an entry from the FWT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_del_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char in_str[64];
++ static struct cmd_ds_fwt_access fwt_access;
++ char *ptr;
++
++ ENTER();
++ if (copy_from_user(in_str, wrq->u.data.pointer, sizeof(in_str)))
++ return -EFAULT;
++
++ if ((ptr = eth_str2addr(in_str, fwt_access.da)) == NULL) {
++ lbs_pr_alert( "FWT_DEL: Invalid MAC address 1\n");
++ return -EINVAL;
++ }
++
++ if ((ptr = eth_str2addr(ptr, fwt_access.ra)) == NULL) {
++ lbs_pr_alert( "FWT_DEL: Invalid MAC address 2\n");
++ return -EINVAL;
++ }
++
++ if ((ptr = next_param(ptr)))
++ fwt_access.dir = (u8)simple_strtoul(ptr, &ptr, 10);
++ else
++ fwt_access.dir = FWT_DEFAULT_DIR;
++
++#ifdef DEBUG
++ {
++ char ethaddr1_str[18], ethaddr2_str[18];
++ lbs_pr_debug(1, "FWT_DEL: line is %s\n", in_str);
++ eth_addr2str(fwt_access.da, ethaddr1_str);
++ eth_addr2str(fwt_access.ra, ethaddr2_str);
++ lbs_pr_debug(1, "FWT_DEL: removing (da:%s,ra:%s,dir:%d)\n", ethaddr1_str,
++ ethaddr2_str, fwt_access.dir);
++ }
++#endif
++
++ LEAVE();
++ return (libertas_prepare_and_send_command(priv,
++ CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_DEL,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&fwt_access));
++}
++
++
++/**
++ * @brief Print route parameters
++ * @param fwt_access struct cmd_ds_fwt_access with route info
++ * @param buf destination buffer for route info
++ */
++static void print_route(struct cmd_ds_fwt_access fwt_access, char *buf)
++{
++ buf += sprintf(buf, " ");
++ buf += eth_addr2str(fwt_access.da, buf);
++ buf += sprintf(buf, " ");
++ buf += eth_addr2str(fwt_access.ra, buf);
++ buf += sprintf(buf, " %u", le32_to_cpu(fwt_access.metric));
++ buf += sprintf(buf, " %u", fwt_access.dir);
++ buf += sprintf(buf, " %u", le32_to_cpu(fwt_access.ssn));
++ buf += sprintf(buf, " %u", le32_to_cpu(fwt_access.dsn));
++ buf += sprintf(buf, " %u", fwt_access.hopcount);
++ buf += sprintf(buf, " %u", fwt_access.ttl);
++ buf += sprintf(buf, " %u", le32_to_cpu(fwt_access.expiration));
++ buf += sprintf(buf, " %u", fwt_access.sleepmode);
++ buf += sprintf(buf, " %u", le32_to_cpu(fwt_access.snr));
++}
++
++/**
++ * @brief Lookup an entry in the FWT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_lookup_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char in_str[64];
++ char *ptr;
++ static struct cmd_ds_fwt_access fwt_access;
++ static char out_str[128];
++ int ret;
++
++ ENTER();
++ if (copy_from_user(in_str, wrq->u.data.pointer, sizeof(in_str)))
++ return -EFAULT;
++
++ if ((ptr = eth_str2addr(in_str, fwt_access.da)) == NULL) {
++ lbs_pr_alert( "FWT_LOOKUP: Invalid MAC address\n");
++ return -EINVAL;
++ }
++
++#ifdef DEBUG
++ {
++ char ethaddr1_str[18];
++ lbs_pr_debug(1, "FWT_LOOKUP: line is %s\n", in_str);
++ eth_addr2str(fwt_access.da, ethaddr1_str);
++ lbs_pr_debug(1, "FWT_LOOKUP: looking for (da:%s)\n", ethaddr1_str);
++ }
++#endif
++
++ ret = libertas_prepare_and_send_command(priv,
++ CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_LOOKUP,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&fwt_access);
++
++ if (ret == 0)
++ print_route(fwt_access, out_str);
++ else
++ sprintf(out_str, "(null)");
++
++ wrq->u.data.length = strlen(out_str);
++ if (copy_to_user(wrq->u.data.pointer, (char *)out_str,
++ wrq->u.data.length)) {
++ lbs_pr_debug(1, "FWT_LOOKUP: Copy to user failed!\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief Reset all entries from the FWT table
++ * @param priv A pointer to wlan_private structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_reset_ioctl(wlan_private * priv)
++{
++ lbs_pr_debug(1, "FWT: resetting\n");
++
++ return (libertas_prepare_and_send_command(priv,
++ CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_RESET,
++ CMD_OPTION_WAITFORRSP, 0, NULL));
++}
++
++/**
++ * @brief List an entry from the FWT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_list_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char in_str[8];
++ static struct cmd_ds_fwt_access fwt_access;
++ char *ptr = in_str;
++ static char out_str[128];
++ char *pbuf = out_str;
++ int ret;
++
++ ENTER();
++ if (copy_from_user(in_str, wrq->u.data.pointer, sizeof(in_str)))
++ return -EFAULT;
++
++ fwt_access.id = cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++
++#ifdef DEBUG
++ {
++ lbs_pr_debug(1, "FWT_LIST: line is %s\n", in_str);
++ lbs_pr_debug(1, "FWT_LIST: listing id:%i\n", le32_to_cpu(fwt_access.id));
++ }
++#endif
++
++ ret = libertas_prepare_and_send_command(priv, CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_LIST,
++ CMD_OPTION_WAITFORRSP, 0, (void *)&fwt_access);
++
++ if (ret == 0)
++ print_route(fwt_access, pbuf);
++ else
++ pbuf += sprintf(pbuf, " (null)");
++
++ wrq->u.data.length = strlen(out_str);
++ if (copy_to_user(wrq->u.data.pointer, (char *)out_str,
++ wrq->u.data.length)) {
++ lbs_pr_debug(1, "FWT_LIST: Copy to user failed!\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief List an entry from the FRT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_list_route_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char in_str[64];
++ static struct cmd_ds_fwt_access fwt_access;
++ char *ptr = in_str;
++ static char out_str[128];
++ char *pbuf = out_str;
++ int ret;
++
++ ENTER();
++ if (copy_from_user(in_str, wrq->u.data.pointer, sizeof(in_str)))
++ return -EFAULT;
++
++ fwt_access.id = cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++
++#ifdef DEBUG
++ {
++ lbs_pr_debug(1, "FWT_LIST_ROUTE: line is %s\n", in_str);
++ lbs_pr_debug(1, "FWT_LIST_ROUTE: listing id:%i\n", le32_to_cpu(fwt_access.id));
++ }
++#endif
++
++ ret = libertas_prepare_and_send_command(priv, CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_LIST_route,
++ CMD_OPTION_WAITFORRSP, 0, (void *)&fwt_access);
++
++ if (ret == 0) {
++ pbuf += sprintf(pbuf, " ");
++ pbuf += eth_addr2str(fwt_access.da, pbuf);
++ pbuf += sprintf(pbuf, " %u", le32_to_cpu(fwt_access.metric));
++ pbuf += sprintf(pbuf, " %u", fwt_access.dir);
++ /* note that the firmware returns the nid in the id field */
++ pbuf += sprintf(pbuf, " %u", le32_to_cpu(fwt_access.id));
++ pbuf += sprintf(pbuf, " %u", le32_to_cpu(fwt_access.ssn));
++ pbuf += sprintf(pbuf, " %u", le32_to_cpu(fwt_access.dsn));
++ pbuf += sprintf(pbuf, " hop %u", fwt_access.hopcount);
++ pbuf += sprintf(pbuf, " ttl %u", fwt_access.ttl);
++ pbuf += sprintf(pbuf, " %u", le32_to_cpu(fwt_access.expiration));
++ } else
++ pbuf += sprintf(pbuf, " (null)");
++
++ wrq->u.data.length = strlen(out_str);
++ if (copy_to_user(wrq->u.data.pointer, (char *)out_str,
++ wrq->u.data.length)) {
++ lbs_pr_debug(1, "FWT_LIST_ROUTE: Copy to user failed!\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief List an entry from the FNT table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_list_neighbor_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *)req;
++ char in_str[8];
++ static struct cmd_ds_fwt_access fwt_access;
++ char *ptr = in_str;
++ static char out_str[128];
++ char *pbuf = out_str;
++ int ret;
++
++ ENTER();
++ if (copy_from_user(in_str, wrq->u.data.pointer, sizeof(in_str)))
++ return -EFAULT;
++
++ memset(&fwt_access, 0, sizeof(fwt_access));
++ fwt_access.id = cpu_to_le32(simple_strtoul(ptr, &ptr, 10));
++
++#ifdef DEBUG
++ {
++ lbs_pr_debug(1, "FWT_LIST_NEIGHBOR: line is %s\n", in_str);
++ lbs_pr_debug(1, "FWT_LIST_NEIGHBOR: listing id:%i\n", le32_to_cpu(fwt_access.id));
++ }
++#endif
++
++ ret = libertas_prepare_and_send_command(priv, CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_LIST_neighbor,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&fwt_access);
++
++ if (ret == 0) {
++ pbuf += sprintf(pbuf, " ra ");
++ pbuf += eth_addr2str(fwt_access.ra, pbuf);
++ pbuf += sprintf(pbuf, " slp %u", fwt_access.sleepmode);
++ pbuf += sprintf(pbuf, " snr %u", le32_to_cpu(fwt_access.snr));
++ pbuf += sprintf(pbuf, " ref %u", le32_to_cpu(fwt_access.references));
++ } else
++ pbuf += sprintf(pbuf, " (null)");
++
++ wrq->u.data.length = strlen(out_str);
++ if (copy_to_user(wrq->u.data.pointer, (char *)out_str,
++ wrq->u.data.length)) {
++ lbs_pr_debug(1, "FWT_LIST_NEIGHBOR: Copy to user failed!\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief Cleans up the route (FRT) and neighbor (FNT) tables
++ * (Garbage Collection)
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_cleanup_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ static struct cmd_ds_fwt_access fwt_access;
++ int ret;
++
++ ENTER();
++
++ lbs_pr_debug(1, "FWT: cleaning up\n");
++
++ memset(&fwt_access, 0, sizeof(fwt_access));
++
++ ret = libertas_prepare_and_send_command(priv, CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_CLEANUP,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&fwt_access);
++
++ if (ret == 0)
++ req->ifr_data = (char *)(le32_to_cpu(fwt_access.references));
++ else
++ return -EFAULT;
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief Gets firmware internal time (debug purposes)
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_fwt_time_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ static struct cmd_ds_fwt_access fwt_access;
++ int ret;
++
++ ENTER();
++
++ lbs_pr_debug(1, "FWT: getting time\n");
++
++ memset(&fwt_access, 0, sizeof(fwt_access));
++
++ ret = libertas_prepare_and_send_command(priv, CMD_FWT_ACCESS,
++ CMD_ACT_FWT_ACCESS_TIME,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&fwt_access);
++
++ if (ret == 0)
++ req->ifr_data = (char *)(le32_to_cpu(fwt_access.references));
++ else
++ return -EFAULT;
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief Gets mesh ttl from firmware
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_mesh_get_ttl_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct cmd_ds_mesh_access mesh_access;
++ int ret;
++
++ ENTER();
++
++ memset(&mesh_access, 0, sizeof(mesh_access));
++
++ ret = libertas_prepare_and_send_command(priv, CMD_MESH_ACCESS,
++ CMD_ACT_MESH_GET_TTL,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&mesh_access);
++
++ if (ret == 0) {
++ req->ifr_data = (char *)(le32_to_cpu(mesh_access.data[0]));
++ }
++ else
++ return -EFAULT;
++
++ LEAVE();
++ return 0;
++}
++
++/**
++ * @brief Gets mesh ttl from firmware
++ * @param priv A pointer to wlan_private structure
++ * @param ttl New ttl value
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_mesh_set_ttl_ioctl(wlan_private * priv, int ttl)
++{
++ struct cmd_ds_mesh_access mesh_access;
++ int ret;
++
++ ENTER();
++
++ if( (ttl > 0xff) || (ttl < 0) )
++ return -EINVAL;
++
++ memset(&mesh_access, 0, sizeof(mesh_access));
++ mesh_access.data[0] = ttl;
++
++ ret = libertas_prepare_and_send_command(priv, CMD_MESH_ACCESS,
++ CMD_ACT_MESH_SET_TTL,
++ CMD_OPTION_WAITFORRSP, 0,
++ (void *)&mesh_access);
++
++ if (ret != 0)
++ ret = -EFAULT;
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set inactivity timeout
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return 0 --success, otherwise fail
++ */
++static int wlan_inactivity_timeout(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret;
++ int data = 0;
++ u16 timeout = 0;
++
++ ENTER();
++ if (wrq->u.data.length > 1)
++ return -ENOTSUPP;
++
++ if (wrq->u.data.length == 0) {
++ /* Get */
++ ret = libertas_prepare_and_send_command(priv,
++ CMD_802_11_INACTIVITY_TIMEOUT,
++ CMD_ACT_GET,
++ CMD_OPTION_WAITFORRSP, 0,
++ &timeout);
++ data = timeout;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ lbs_pr_debug(1, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ } else {
++ /* Set */
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ lbs_pr_debug(1, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ timeout = data;
++ ret = libertas_prepare_and_send_command(priv,
++ CMD_802_11_INACTIVITY_TIMEOUT,
++ CMD_ACT_SET,
++ CMD_OPTION_WAITFORRSP, 0,
++ &timeout);
++ }
++
++ wrq->u.data.length = 1;
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief ioctl function - entry point
++ *
++ * @param dev A pointer to net_device structure
++ * @param req A pointer to ifreq structure
++ * @param cmd command
++ * @return 0--success, otherwise fail
++ */
++int libertas_do_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
++{
++ int subcmd = 0;
++ int idata = 0;
++ int *pdata;
++ int ret = 0;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *adapter = priv->adapter;
++ struct iwreq *wrq = (struct iwreq *)req;
++
++ ENTER();
++
++ lbs_pr_debug(1, "libertas_do_ioctl: ioctl cmd = 0x%x\n", cmd);
++ switch (cmd) {
++ case WLAN_SETNONE_GETNONE: /* set WPA mode on/off ioctl #20 */
++ switch (wrq->u.data.flags) {
++ case WLAN_SUBCMD_BT_RESET: /* bt_reset */
++ wlan_bt_reset_ioctl(priv);
++ break;
++ case WLAN_SUBCMD_FWT_RESET: /* fwt_reset */
++ wlan_fwt_reset_ioctl(priv);
++ break;
++ } /* End of switch */
++ break;
++
++ case WLAN_SETONEINT_GETNONE:
++ /* The first 4 bytes of req->ifr_data is sub-ioctl number
++ * after 4 bytes sits the payload.
++ */
++ subcmd = wrq->u.data.flags; //from wpa_supplicant subcmd
++
++ if (!subcmd)
++ subcmd = (int)req->ifr_data; //from iwpriv subcmd
++
++ switch (subcmd) {
++ case WLANSETREGION:
++ idata = SUBCMD_DATA(wrq);
++ ret = wlan_set_region(priv, (u16) idata);
++ break;
++ case WLAN_SUBCMD_MESH_SET_TTL:
++ idata = SUBCMD_DATA(wrq);
++ ret = wlan_mesh_set_ttl_ioctl(priv, idata);
++ break;
++
++ default:
++ ret = -EOPNOTSUPP;
++ break;
++ }
++
++ break;
++
++ case WLAN_SET128CHAR_GET128CHAR:
++ switch ((int)wrq->u.data.flags) {
++ case WLAN_SUBCMD_BT_ADD:
++ ret = wlan_bt_add_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_BT_DEL:
++ ret = wlan_bt_del_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_BT_LIST:
++ ret = wlan_bt_list_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_FWT_ADD:
++ ret = wlan_fwt_add_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_FWT_DEL:
++ ret = wlan_fwt_del_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_FWT_LOOKUP:
++ ret = wlan_fwt_lookup_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_FWT_LIST_NEIGHBOR:
++ ret = wlan_fwt_list_neighbor_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_FWT_LIST:
++ ret = wlan_fwt_list_ioctl(priv, req);
++ break;
++ case WLAN_SUBCMD_FWT_LIST_ROUTE:
++ ret = wlan_fwt_list_route_ioctl(priv, req);
++ break;
++ }
++ break;
++
++ case WLAN_SETNONE_GETONEINT:
++ switch ((int)req->ifr_data) {
++ case WLANGETREGION:
++ pdata = (int *)wrq->u.name;
++ *pdata = (int)adapter->regioncode;
++ break;
++ case WLAN_SUBCMD_FWT_CLEANUP: /* fwt_cleanup */
++ ret = wlan_fwt_cleanup_ioctl(priv, req);
++ break;
++
++ case WLAN_SUBCMD_FWT_TIME: /* fwt_time */
++ ret = wlan_fwt_time_ioctl(priv, req);
++ break;
++
++ case WLAN_SUBCMD_MESH_GET_TTL:
++ ret = wlan_mesh_get_ttl_ioctl(priv, req);
++ break;
++
++ default:
++ ret = -EOPNOTSUPP;
++
++ }
++
++ break;
++
++ case WLAN_SET_GET_SIXTEEN_INT:
++ switch ((int)wrq->u.data.flags) {
++ case WLAN_LED_GPIO_CTRL:
++ {
++ int i;
++ int data[16];
++
++ struct cmd_ds_802_11_led_ctrl ctrl;
++ struct mrvlietypes_ledgpio *gpio =
++ (struct mrvlietypes_ledgpio *) ctrl.data;
++
++ memset(&ctrl, 0, sizeof(ctrl));
++ if (wrq->u.data.length > MAX_LEDS * 2)
++ return -ENOTSUPP;
++ if ((wrq->u.data.length % 2) != 0)
++ return -ENOTSUPP;
++ if (wrq->u.data.length == 0) {
++ ctrl.action =
++ cpu_to_le16
++ (CMD_ACT_GET);
++ } else {
++ if (copy_from_user
++ (data, wrq->u.data.pointer,
++ sizeof(int) *
++ wrq->u.data.length)) {
++ lbs_pr_debug(1,
++ "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ ctrl.action =
++ cpu_to_le16
++ (CMD_ACT_SET);
++ ctrl.numled = cpu_to_le16(0);
++ gpio->header.type =
++ cpu_to_le16(TLV_TYPE_LED_GPIO);
++ gpio->header.len = wrq->u.data.length;
++ for (i = 0; i < wrq->u.data.length;
++ i += 2) {
++ gpio->ledpin[i / 2].led =
++ data[i];
++ gpio->ledpin[i / 2].pin =
++ data[i + 1];
++ }
++ }
++ ret =
++ libertas_prepare_and_send_command(priv,
++ CMD_802_11_LED_GPIO_CTRL,
++ 0,
++ CMD_OPTION_WAITFORRSP,
++ 0, (void *)&ctrl);
++ for (i = 0; i < gpio->header.len; i += 2) {
++ data[i] = gpio->ledpin[i / 2].led;
++ data[i + 1] = gpio->ledpin[i / 2].pin;
++ }
++ if (copy_to_user(wrq->u.data.pointer, data,
++ sizeof(int) *
++ gpio->header.len)) {
++ lbs_pr_debug(1, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ wrq->u.data.length = gpio->header.len;
++ }
++ break;
++ case WLAN_INACTIVITY_TIMEOUT:
++ ret = wlan_inactivity_timeout(priv, wrq);
++ break;
++ }
++ break;
++
++ default:
++ ret = -EINVAL;
++ break;
++ }
++ LEAVE();
++ return ret;
++}
++
++
+diff --git a/drivers/net/wireless/libertas/main.c b/drivers/net/wireless/libertas/main.c
+index 1823b48..47b0288 100644
+--- a/drivers/net/wireless/libertas/main.c
++++ b/drivers/net/wireless/libertas/main.c
+@@ -36,6 +36,7 @@ unsigned int libertas_debug = 0;
+ module_param(libertas_debug, int, 0644);
+ EXPORT_SYMBOL_GPL(libertas_debug);
+
++int libertas_do_ioctl(struct net_device *dev, struct ifreq *req, int i);
+
+ #define WLAN_TX_PWR_DEFAULT 20 /*100mW */
+ #define WLAN_TX_PWR_US_DEFAULT 20 /*100mW */
+@@ -945,9 +946,8 @@ static int wlan_setup_firmware(wlan_private * priv)
+ libertas_set_mac_packet_filter(priv);
+
+ /* Get the supported Data rates */
+- ret = libertas_prepare_and_send_command(priv, CMD_802_11_DATA_RATE,
+- CMD_ACT_GET_TX_RATE,
+- CMD_OPTION_WAITFORRSP, 0, NULL);
++ ret = libertas_prepare_and_send_command(priv, CMD_802_11_TX_RATE_QUERY,
++ CMD_ACT_GET, CMD_OPTION_WAITFORRSP, 0, NULL);
+
+ if (ret) {
+ ret = -1;
+@@ -1156,6 +1156,7 @@ wlan_private *libertas_add_card(void *card, struct device *dmdev)
+ /* Setup the OS Interface to our functions */
+ dev->open = libertas_open;
+ dev->hard_start_xmit = libertas_pre_start_xmit;
++ dev->do_ioctl = libertas_do_ioctl;
+ dev->stop = libertas_close;
+ dev->set_mac_address = libertas_set_mac_address;
+ dev->tx_timeout = libertas_tx_timeout;
+@@ -1334,6 +1335,7 @@ int libertas_add_mesh(wlan_private *priv, struct device *dev)
+
+ mesh_dev->open = libertas_mesh_open;
+ mesh_dev->hard_start_xmit = libertas_mesh_pre_start_xmit;
++ mesh_dev->do_ioctl = libertas_do_ioctl;
+ mesh_dev->stop = libertas_mesh_close;
+ mesh_dev->get_stats = libertas_get_stats;
+ mesh_dev->set_mac_address = libertas_set_mac_address;
+diff --git a/drivers/net/wireless/libertas/scan.c b/drivers/net/wireless/libertas/scan.c
+index ad1e67d..748358e 100644
+--- a/drivers/net/wireless/libertas/scan.c
++++ b/drivers/net/wireless/libertas/scan.c
+@@ -361,7 +361,7 @@ void libertas_scan_worker(struct work_struct *work)
+ {
+ wlan_private *priv = container_of(work, wlan_private, scan_work.work);
+
+- wlan_scan_networks(priv, NULL, 0);
++ wlan_scan_networks(priv, NULL, 1);
+ }
+
+
+@@ -633,8 +633,10 @@ static int wlan_scan_channel_list(wlan_private * priv,
+ /* Set the temp channel struct pointer to the start of the desired list */
+ ptmpchan = pscanchanlist;
+
++#if 0 //We always do full scan
+ if (priv->adapter->last_scanned_channel && !puserscanin)
+ ptmpchan += priv->adapter->last_scanned_channel;
++#endif
+
+ /* Loop through the desired channel list, sending a new firmware scan
+ * commands for each maxchanperscan channels (or for 1,6,11 individually
+diff --git a/drivers/net/wireless/libertas/wext.c b/drivers/net/wireless/libertas/wext.c
+index 395b788..a1acb7c 100644
+--- a/drivers/net/wireless/libertas/wext.c
++++ b/drivers/net/wireless/libertas/wext.c
+@@ -995,8 +995,14 @@ static int wlan_set_rate(struct net_device *dev, struct iw_request_info *info,
+ adapter->auto_rate = 0;
+ }
+
+- ret = libertas_prepare_and_send_command(priv, CMD_802_11_DATA_RATE,
+- action, CMD_OPTION_WAITFORRSP, 0, NULL);
++ /* Try the newer command first (Firmware Spec 5.1 and above) */
++ ret = libertas_prepare_and_send_command(priv, CMD_802_11_RATE_ADAPT_RATESET,
++ CMD_ACT_SET, CMD_OPTION_WAITFORRSP, 0, NULL);
++
++ /* Fallback to older version */
++ if (ret)
++ ret = libertas_prepare_and_send_command(priv, CMD_802_11_DATA_RATE,
++ action, CMD_OPTION_WAITFORRSP, 0, NULL);
+
+ out:
+ lbs_deb_leave_args(LBS_DEB_WEXT, "ret %d", ret);
+@@ -2010,6 +2016,139 @@ void libertas_get_fwversion(wlan_adapter * adapter, char *fwversion, int maxlen)
+ snprintf(fwversion, maxlen, fwver);
+ }
+
++static const iw_handler wlan_private_handler[] = {
++ NULL, /* SIOCIWFIRSTPRIV */
++};
++
++static const struct iw_priv_args wlan_private_args[] = {
++ /*
++ * { cmd, set_args, get_args, name }
++ */
++ /* Using iwpriv sub-command feature */
++ {
++ WLAN_SETONEINT_GETNONE, /* IOCTL: 24 */
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ ""},
++ {
++ WLANSETREGION,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "setregioncode"},
++ {
++ WLAN_SUBCMD_MESH_SET_TTL,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "mesh_set_ttl"},
++ {
++ WLAN_SETNONE_GETONEINT,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ ""},
++ {
++ WLANGETREGION,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getregioncode"},
++ {
++ WLAN_SUBCMD_FWT_CLEANUP,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "fwt_cleanup"},
++ {
++ WLAN_SUBCMD_FWT_TIME,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "fwt_time"},
++ {
++ WLAN_SUBCMD_MESH_GET_TTL,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "mesh_get_ttl"},
++ {
++ WLAN_SETNONE_GETNONE,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ ""},
++ {
++ WLAN_SUBCMD_FWT_RESET,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "fwt_reset"},
++ {
++ WLAN_SUBCMD_BT_RESET,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "bt_reset"},
++ {
++ WLAN_SET128CHAR_GET128CHAR,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ ""},
++ /* BT Management */
++ {
++ WLAN_SUBCMD_BT_ADD,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "bt_add"},
++ {
++ WLAN_SUBCMD_BT_DEL,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "bt_del"},
++ {
++ WLAN_SUBCMD_BT_LIST,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "bt_list"},
++ /* FWT Management */
++ {
++ WLAN_SUBCMD_FWT_ADD,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "fwt_add"},
++ {
++ WLAN_SUBCMD_FWT_DEL,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "fwt_del"},
++ {
++ WLAN_SUBCMD_FWT_LOOKUP,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "fwt_lookup"},
++ {
++ WLAN_SUBCMD_FWT_LIST_NEIGHBOR,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "fwt_list_neigh"},
++ {
++ WLAN_SUBCMD_FWT_LIST,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "fwt_list"},
++ {
++ WLAN_SUBCMD_FWT_LIST_ROUTE,
++ IW_PRIV_TYPE_CHAR | 128,
++ IW_PRIV_TYPE_CHAR | 128,
++ "fwt_list_route"},
++ {
++ WLAN_SET_GET_SIXTEEN_INT,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ ""},
++ {
++ WLAN_LED_GPIO_CTRL,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "ledgpio"},
++ {
++ WLAN_INACTIVITY_TIMEOUT,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "inactivityto"},
++};
++
+
+ /*
+ * iwconfig settable callbacks
+@@ -2131,12 +2270,20 @@ static const iw_handler mesh_wlan_handler[] = {
+ };
+ struct iw_handler_def libertas_handler_def = {
+ .num_standard = ARRAY_SIZE(wlan_handler),
++ .num_private = ARRAY_SIZE(wlan_private_handler),
++ .num_private_args = ARRAY_SIZE(wlan_private_args),
+ .standard = (iw_handler *) wlan_handler,
++ .private = (iw_handler *) wlan_private_handler,
++ .private_args = (struct iw_priv_args *)wlan_private_args,
+ .get_wireless_stats = wlan_get_wireless_stats,
+ };
+
+ struct iw_handler_def mesh_handler_def = {
+ .num_standard = ARRAY_SIZE(mesh_wlan_handler),
++ .num_private = ARRAY_SIZE(wlan_private_handler),
++ .num_private_args = ARRAY_SIZE(wlan_private_args),
+ .standard = (iw_handler *) mesh_wlan_handler,
++ .private = (iw_handler *) wlan_private_handler,
++ .private_args = (struct iw_priv_args *)wlan_private_args,
+ .get_wireless_stats = wlan_get_wireless_stats,
+ };
+diff --git a/drivers/net/wireless/libertas/wext.h b/drivers/net/wireless/libertas/wext.h
+index 6aa444c..6a8c1d4 100644
+--- a/drivers/net/wireless/libertas/wext.h
++++ b/drivers/net/wireless/libertas/wext.h
+@@ -4,6 +4,47 @@
+ #ifndef _WLAN_WEXT_H_
+ #define _WLAN_WEXT_H_
+
++#define SUBCMD_OFFSET 4
++#define SUBCMD_DATA(x) *((int *)(x->u.name + SUBCMD_OFFSET))
++
++/** PRIVATE CMD ID */
++#define WLANIOCTL SIOCIWFIRSTPRIV
++
++#define WLAN_SETNONE_GETNONE (WLANIOCTL + 8)
++#define WLAN_SUBCMD_BT_RESET 13
++#define WLAN_SUBCMD_FWT_RESET 14
++
++#define WLAN_SETNONE_GETONEINT (WLANIOCTL + 15)
++#define WLANGETREGION 1
++
++#define WLAN_SUBCMD_FWT_CLEANUP 15
++#define WLAN_SUBCMD_FWT_TIME 16
++#define WLAN_SUBCMD_MESH_GET_TTL 17
++
++#define WLAN_SETONEINT_GETNONE (WLANIOCTL + 24)
++#define WLANSETREGION 8
++#define WLAN_SUBCMD_MESH_SET_TTL 18
++
++#define WLAN_SET128CHAR_GET128CHAR (WLANIOCTL + 25)
++#define WLAN_SUBCMD_BT_ADD 18
++#define WLAN_SUBCMD_BT_DEL 19
++#define WLAN_SUBCMD_BT_LIST 20
++#define WLAN_SUBCMD_FWT_ADD 21
++#define WLAN_SUBCMD_FWT_DEL 22
++#define WLAN_SUBCMD_FWT_LOOKUP 23
++#define WLAN_SUBCMD_FWT_LIST_NEIGHBOR 24
++#define WLAN_SUBCMD_FWT_LIST 25
++#define WLAN_SUBCMD_FWT_LIST_ROUTE 26
++
++#define WLAN_SET_GET_SIXTEEN_INT (WLANIOCTL + 29)
++#define WLAN_LED_GPIO_CTRL 5
++#define WLAN_INACTIVITY_TIMEOUT 9
++
++#define WLAN_LINKMODE_802_3 0
++#define WLAN_LINKMODE_802_11 2
++#define WLAN_RADIOMODE_NONE 0
++#define WLAN_RADIOMODE_RADIOTAP 2
++
+ /** wlan_ioctl_regrdwr */
+ struct wlan_ioctl_regrdwr {
+ /** Which register to access */
+diff --git a/drivers/net/wireless/marvell8686/Makefile b/drivers/net/wireless/marvell8686/Makefile
+new file mode 100644
+index 0000000..e443661
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/Makefile
+@@ -0,0 +1,15 @@
++ifeq ($(CONFIG_MARVELL_8686_PROC_FS),y)
++ sd8686-objs += wlan_proc.o
++endif
++
++ifeq ($(CONFIG_MARVELL_8686_DEBUG),y)
++ sd8686-objs += wlan_debug.o
++endif
++
++sd8686-objs += wlan_main.o wlan_fw.o \
++ wlan_wext.o wlan_rx.o wlan_tx.o \
++ wlan_cmd.o wlan_cmdresp.o wlan_scan.o \
++ wlan_join.o wlan_wmm.o wlan_11d.o wlan_fops.o \
++ if_sdio.o
++obj-$(CONFIG_MARVELL_8686_SDIO) += sd8686.o
++
+diff --git a/drivers/net/wireless/marvell8686/README b/drivers/net/wireless/marvell8686/README
+new file mode 100644
+index 0000000..5dca07e
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/README
+@@ -0,0 +1,1587 @@
++===============================================================================
++ U S E R M A N U A L
++
++1) FOR DRIVER BUILD
++
++ Goto source code directory src_xxxx.
++ make [clean] build
++ The driver and utility binaries can be found in ../bin_xxxx directory.
++
++2) FOR DRIVER INSTALL
++
++ a) Copy helper_sd.bin and sd8xxx.bin to /lib/firmware/mrvl/ directory,
++ create the directory if it doesn't exist.
++ b) insmod sdio.o (or sdio.ko) [clkrate=5|10|20] [intmode=0|1] [gpiopin=n]
++ The default SDIO clock frequency is 20 MHz. It can be changed to 10 MHz or 5 MHz.
++ intmode -- 0 for SDIO (default)
++ intmode -- 1 for GPIO, gpiopin for GPIO pin# has to be specified in this mode.
++ c) insmod sd8xxx.o (or sd8xxx.ko) helper_name=/lib/firmware/mrvl/helper_sd.bin \
++ fw_name=/lib/firmware/mrvl/sd8xxx.bin
++
++ To install SD8xxx Driver with user-specified helper file /lib/firmware/mrvl/helper_sd.bin and
++ MFG firmware file /lib/firmware/mrvl/sd8xxxmfg.bin, using the following command:
++ insmod sdio.o (or sdio.ko)
++ insmod sd8xxx.o (or sd8xxx.ko) mfgmode=1 helper_name=/lib/firmware/mrvl/helper_sd.bin \
++ fw_name=/lib/firmware/mrvl/sd8xxxmfg.bin
++
++3) FOR DRIVER PROC & DEBUG
++
++ The following info are provided in /proc/net/wlan/info,
++
++ driver_name = "wlan"
++ driver_version = <chip id, firmware version and driver version>
++ InterfaceName = "ethX"
++ Mode = "Ad-hoc" | "Managed" | "Auto" | "Unknown"
++ State = "Disconnected" | "Connected"
++ MACAddress = <6-byte adapter MAC address>
++ MCCount = <multicast address count>
++ ESSID = <current SSID>
++ Channel = <current channel>
++ region_code = <current region code>
++ MCAddr[n] = <multicast address>
++ num_tx_bytes = <number of bytes sent to device>
++ num_rx_bytes = <number of bytes received from device and sent to kernel>
++ num_tx_pkts = <number of packets sent to device>
++ num_rx_pkts = <number of packets received from device and sent to kernel>
++ num_tx_pkts_dropped = <number of tx packets dropped by driver>
++ num_rx_pkts_dropped = <number of rx packets dropped by driver>
++ num_tx_pkts_err = <number of tx packets failed to send to device>
++ num_rx_pkts_err = <number of rx packets failed to receive from device>
++ carrier "on" | "off"
++ tx queue "stopped" | "started"
++ CurCmd "NULL" | <current command id and action>
++
++ The following debug info are provided in /proc/net/wlan/debug,
++
++ IntCounter = <interrupt count, cleared when interrupt handled>
++ ConnectStatus = <0/1, disconnected/connected>
++ wmmQStp = <0/1, WMM queue started/stopped>
++ wmmPkts = <number of tx packets in WMM queues>
++ wmmAcVo = <number of packets sent to device from WMM AcVo queue>
++ wmmAcVi = <number of packets sent to device from WMM AcVi queue>
++ wmmAcBE = <number of packets sent to device from WMM AcBE queue>
++ wmmAcBK = <number of packets sent to device from WMM AcBK queue>
++ PSMode = <0/1, CAM mode/PS mode>
++ PSState = <0/1/2/3, full power state/awake state/pre-sleep state/sleep state>
++ IsDeepSleep = <0/1, not deep sleep state/deep sleep state>
++ IsAutoDeepSleepEnabled = <0/1, not auto deep sleep mode/auto deep sleep mode>
++ WakeupDevReq = <0/1, wakeup device not required/required>
++ WakeupTries = <wakeup device count, cleared when device awake>
++ HS_Configured = <0/1, host sleep not configured/configured>
++ HS_Activated = <0/1, extended host sleep not activated/activated>
++ num_tx_timeout = <number of tx timeout>
++ num_cmd_timeout = <number of timeout commands>
++ TimeoutCmdId = <command id of the last timeout command>
++ TimeoutCmdAct = <command action of the last timeout command>
++ LastCmdId = <command id of the last several commands sent to device>
++ LastCmdAct = <command action of the last several commands sent to device>
++ LastCmdIndex = <0 based last command index>
++ LastCmdRespId = <command id of the last several command responses received from device>
++ LastCmdRespIndex = <0 based last command response index>
++ LastEvent = <event id of the last several events received from device>
++ LastEventIndex = <0 based last event index>
++ num_cmd_h2c_fail = <number of commands failed to send to device>
++ num_cmd_sleep_cfm_fail = <number of sleep confirm failed to send to device>
++ num_tx_h2c_fail = <number of data packets failed to send to device>
++ num_evt_deauth = <number of deauthenticated events received from device>
++ num_evt_disassoc = <number of disassociated events received from device>
++ num_evt_link_lost = <number of link lost events received from device>
++ num_cmd_deauth = <number of deauthenticate commands sent to device>
++ num_cmd_assoc_ok = <number of associate commands with success return>
++ num_cmd_assoc_fail = <number of associate commands with failure return>
++ dnld_sent = <0/1/2, send resources available/sending data to device/sending command to device>
++
++ Use dmesg or cat /var/log/debug to check driver debug messages.
++
++ Update /proc/sys/kernel/printk to change message log levels.
++ For example,
++ echo 6 > /proc/sys/kernel/printk (messages with a higher priority than 6
++ will be printed to the console)
++ echo 15 > /proc/sys/kernel/printk (all messages will be printed to console)
++
++4) FOR IWPRIV COMMAND
++
++NAME
++ This manual describes the usage of private commands used in Marvell WLAN
++ Linux Driver. All the commands available in Wlanconfig will not be available
++ in the iwpriv.
++
++ To use parameters as hex format, a'0x' must precede it for the parameters to
++ be parsed properly.
++
++SYNOPSIS
++ iwpriv <ethX> <command> [sub-command] ...
++
++ iwpriv ethX version
++ iwpriv ethX verext
++ iwpriv ethX scantype [sub-command]
++ iwpriv ethX getSNR <n>
++ iwpriv ethX getNF <n>
++ iwpriv ethX getRSSI <n>
++ iwpriv ethX setrxant <n>
++ iwpriv ethX getrxant
++ iwpriv ethX settxant <n>
++ iwpriv ethX gettxant
++ iwpriv ethX authalgs <n>
++ iwpriv ethX encryptionmode <n>
++ iwpriv ethX setregioncode <n>
++ iwpriv ethX getregioncode
++ iwpriv ethX setbcnavg <n>
++ iwpriv ethX getbcnavg
++ iwpriv ethX setdataavg <n>
++ iwpriv ethX getdataavg
++ iwpriv ethX setlisteninter <n>
++ iwpriv ethX getlisteninter
++ iwpriv ethX setmultipledtim <n>
++ iwpriv ethX getmultipledtim
++ iwpriv ethX atimwindow <n>
++ iwpriv ethX deepsleep <n>
++ iwpriv ethX autodeepsleep <n>
++ iwpriv ethX hscfg <n>
++ iwpriv ethX hssetpara <n>
++ iwpriv ethX deauth
++ iwpriv ethX adhocstop
++ iwpriv ethX radioon
++ iwpriv ethX radiooff
++ iwpriv ethX reasso-on
++ iwpriv ethX reasso-off
++ iwpriv ethX scanmode [sub-command]
++ iwpriv ethX setwpaie <n>
++ iwpriv ethX setaeskey <n>
++ iwpriv ethX getaeskey
++ iwpriv ethX rmaeskey
++ iwpriv ethX getcis
++ iwpriv ethX getlog
++ iwpriv ethX getadhocstatus
++ iwpriv ethX adhocgrate <n>
++
++Version 4 Command:
++ iwpriv ethX inactivityto <n>
++ iwpriv ethX sleeppd <n>
++ iwpriv ethX enable11d <n>
++ iwpriv ethX bgscan <n>
++ iwpriv ethX wmm <n>
++ iwpriv ethX tpccfg <n>
++ iwpriv ethX sdioclock <n>
++
++Version 5 Command:
++ iwpriv ethX ledgpio <n>
++ iwpriv ethX wmm_qosinfo <n>
++ iwpriv ethX scanprobes <n>
++ iwpriv ethX lolisteninter <n>
++ iwpriv ethX rateadapt <n> <m> <l> <k>
++ iwpriv ethX fwwakeupmethod <n>
++ iwpriv ethX txcontrol <n>
++ iwpriv ethX uapsdnullgen <n>
++ iwpriv ethX psnullinterval <n>
++ iwpriv ethX getrxinfo
++ iwpriv ethX gettxrate
++ iwpriv ethX bcninterval [n]
++ iwpriv ethX setcoalescing <n>
++ iwpriv ethX bcnmisto <n>
++ iwpriv ethX adhocawakepd <n>
++ iwpriv ethX sdiopullctrl <m> <n>
++ iwpriv ethX scantime [s] [a] [p]
++ iwpriv ethX ldocfg [n]
++ iwpriv ethX dataevtcfg [a] [b] [c] [d] [e] [f] [g] [h] [i]
++ iwpriv ethX sdiomode [n]
++ iwpriv ethX rtsctsctrl [n]
++ iwpriv ethX drvdbg [n] [m]
++ iwpriv ethX adhocgprot [n]
++ iwpriv ethX getrate
++ iwpriv ethX associate <n>
++ iwpriv ethX getdtim
++
++DESCRIPTION
++ Those commands are used to send additional commands to the Marvell WLAN
++ card via the Linux device driver.
++
++ The ethX parameter specifies the network device that is to be used to
++ perform this command on. it could be eth0, eth1 etc.
++
++version
++ This is used to get the current version of the driver and the firmware.
++
++verext
++ Retrieve and display an extended version string from the firmware
++
++ Usage:
++ iwpriv ethX verext [#]
++
++ where [#] is an optional argument to retrieve a specific version string,
++ omission of the argument retrieves the 0 indexed string
++
++scantype
++ This command is used to set the scan type to be used by the driver in
++ the scan command. This setting will not be used while performing a scan
++ for a specific SSID, as it is always done with scan type being active.
++
++ where the sub-commands are: -
++ active -- to set the scan type to active
++ passive -- to set the scan type to passive
++ get -- to get the scan type set in the driver
++
++getSNR
++ This command gets the average and non average value of Signal to Noise
++ Ratio of Beacon and Data.
++
++ where value is:
++ 0 -- Beacon non-average.
++ 1 -- Beacon average.
++ 2 -- Data non-average.
++ 3 -- Data average.
++
++ If no value is given, all four values are returned in the order mentioned
++ above.
++
++ Note: This command is available only when STA is connected.
++
++getRSSI
++ This command gets the average and non average value os Receive Signal
++ Strength of Beacon and Data.
++
++ where value is:
++ 0 -- Beacon non-average.
++ 1 -- Beacon average.
++ 2 -- Data non-average.
++ 3 -- Data average.
++
++ Note: This command is available only when STA is connected.
++
++getNF
++ This command gets the average and non average value of Noise Floor of
++ Beacon and Data.
++
++ where value is:
++ 0 -- Beacon non-average.
++ 1 -- Beacon average.
++ 2 -- Data non-average.
++ 3 -- Data average.
++
++ Note: This command is available only when STA is connected.
++
++setrxant
++ This command is used to set the mode for Rx antenna.
++
++ The options that can be sent are:-
++ 1 -- Antenna 1.
++ 2 -- Antenna 2.
++ 0xFFFF -- Diversity.
++
++ Usage:
++ iwpriv ethX setrxant 0x01: select Antenna 1.
++
++getrxant
++ This command is used to get the mode for Rx antenna.
++
++settxant
++ This command is used to set the mode for Tx antenna.
++ The options that can be sent are:-
++ 1 -- Antenna 1.
++ 2 -- Antenna 2.
++ 0xFFFF -- Diversity.
++ Usage:
++ iwpriv ethX settxant 0x01: select Antenna 1.
++
++gettxant
++ This command is used to get the mode for Tx antenna.
++
++authalgs
++ This command is used by the WPA supplicant to set the authentication
++ algorithms in the station.
++
++encryptionmode
++ This command is used by the WPA supplicant to set the encryption algorithm.
++
++ where values can be:-
++ 0 -- NONE
++ 1 -- WEP40
++ 2 -- TKIP
++ 3 -- CCMP
++ 4 -- WEP104
++
++setregioncode
++ This command is used to set the region code in the station.
++ where value is 'region code' for various regions like
++ USA FCC, Canada IC, France, Europe ETSI, Japan ...
++
++ Usage:
++ iwpriv ethX setregioncode 0x10: set region code to USA (0x10).
++
++getregioncode
++ This command is used to get the region code information set in the
++ station.
++
++setbcnavg
++ Set the weighting factor for calculating beacon average RSSI and SNR.
++ where value can be:
++ 0 -- default beacon averaging factor (8)
++ 1-8 -- beacon averaging factor
++ Usage:
++ iwpriv ethX setbcnavg 0
++ iwpriv ethX setbcnavg 8
++
++getbcnavg
++ Get the weighting factor for calculating beacon average RSSI and SNR.
++ Usage:
++ iwpriv ethX getbcnavg
++
++setdataavg
++ Set the weighting factor for calculating data average RSSI and SNR.
++ where value can be:
++ 0 -- default data averaging factor (8)
++ 1-8 -- data averaging factor
++ Usage:
++ iwpriv ethX setdataavg 0
++ iwpriv ethX setdataavg 8
++
++getdataavg
++ Get the weighting factor for calculating data average RSSI and SNR.
++ Usage:
++ iwpriv ethX getdataavg
++
++setlisteninter
++ This command is used to set the listen interval in the
++ station.
++
++ where the value ranges between 1 - 255
++
++getlisteninter
++ This command is used to get the listen interval value set in the
++ station.
++
++setmultipledtim
++ This command is used to set the multiple dtim value in the
++ station.
++ where the value is 1,2,3,4,5,0xfffe
++ 65534 (0xfffe) means that the dtim will be ignored in firmware,
++ listen interval or local listen interval will be used.
++
++getmultipledtim
++ This command is used to get the multiple dtim value set in the station.
++
++atimwindow
++ This command is used to set atim value in the station when an argument is given,
++ return the atim value set by the user and the current atim value if adapter is in connected state.
++ The valid atimwindow is between 0 - 50.
++
++ Usage:
++ iwpriv ethX atimwindow 0 (set atimwindow to 0)
++
++ not connected:
++ iwpriv ethX atimwindow (get atimwindow value set by user)
++
++ connected:
++ iwpriv ethX atimwindow (get atimwindow set by user previously
++ and current atimwindow)
++
++deauth
++ This command is used to send the de-authentication to the AP with which
++ the station is associated. This command is valid only when
++ station is in Infrastructure mode.
++
++ Note: This command is available only when STA is connected.
++
++reasso-on
++ This command is used to enable re-association function in dirver.
++
++reasso-off
++ This command is used to disable re-association function in driver
++
++adhocstop
++ This command is used to stop beacon transmission from the station and
++ go into idle state in ad-hoc mode.
++
++ Note: This command is available only when STA is connected.
++
++radioon
++ This command is used to turn on the RF antenna.
++
++radiooff
++ This command is sued to turn off the RF antenna.
++
++scanmode
++ This command is used to set the station to scan for either IBSS
++ networks or BSS networks or both BSS and IBSS networks. This
++ command can be used with sub commands,
++
++ where the value for
++ bss -- Scan All the BSS networks.
++ ibss -- Scan All the IBSS networks.
++ any -- Scan both BSS and IBSS networks.
++
++deepsleep
++ This command is used to configure the station in deepsleep mode.
++
++ where the option is:
++ 1 -- Enable deepsleep mode
++ 0 -- Disable deepsleep mode
++ 2 -- Display deepsleep setting
++ Usage:
++ iwpriv ethX deepsleep 1
++ Enable deepsleep mode
++ iwpriv ethX deepsleep 0
++ Disable deepsleep mode
++ iwpriv ethX deepsleep 2
++ Display deepsleep setting
++
++autodeepsleep
++ This command is used to configure the station in auto deepsleep mode.
++
++ where the option is:
++ 1 -- Enable auto deepsleep mode
++ 0 -- Disable auto deepsleep mode
++ Usage:
++ iwpriv ethX autodeepsleep
++ Read the current auto deepsleep setting
++ iwpriv ethX autodeepsleep 1
++ Enable auto deepsleep mode
++ iwpriv ethX autodeepsleep 0
++ Disable auto deepsleep mode
++
++hscfg
++ This command is used to configure the host sleep parameters.
++
++ iwpriv ethX hscfg Condition [GPIO# [Gap]]
++
++ Note:
++
++ 1) This command takes one (Condition) or two (Condition and GPIO#) or three (Condition, GPIO# and gap)
++ parameters.
++
++ where Condition is:
++ bit 0 = 1 -- broadcast data
++ bit 1 = 1 -- unicast data
++ bit 2 = 1 -- mac event
++ bit 3 = 1 -- multicast packet
++
++ where GPIO is the pin number of GPIO used to wakeup the host. It could be any valid
++ GPIO pin# (e.g. 0-7) or 0xff (Interface, e.g. SDIO will be used instead).
++
++ where Gap is the gap in milli seconds between wakeup signal and wakeup event
++ or 0xff for special setting.
++
++ 2) the Host Sleep mode will be cancelled if condition is set to -1.
++
++ 3) Usage:
++ iwpriv eth1 hscfg -1 # cancel host sleep mode
++
++ iwpriv eth1 hscfg 3 # broadcast and unicast data
++ # use GPIO and GAP set previously
++
++ iwpriv eth1 hscfg 2 0x3 # unicast data
++ # use GPIO 3
++ # use GAP set previously
++
++ iwpriv eth1 hscfg 2 1 0xa0 # unicast data
++ # use GPIO 1
++ # gap: 160 ms
++
++ iwpriv eth1 hscfg 2 0xff # unicast data
++ # use Interface (e.g. SDIO)
++ # use GAP set previously
++
++ iwpriv eth1 hscfg 0x2 0x3 0xff # unicast data
++ # use GPIO 3
++ # special host sleep mode
++
++ iwpriv eth1 hscfg 0x2 0xff 0xff # unicast data
++ # use Interface (e.g. SDIO)
++ # special host sleep mode
++
++hssetpara
++ This command is used to set host sleep parameters.
++
++ iwpriv ethX hssetpara Condition [GPIO# [Gap]]
++
++ Note:
++ 1) The usages of parameters are the same as "hscfg" command.
++ 2) The parameters will be saved in the driver and be usded when host suspends.
++
++setwpaie
++ This command is used by WPA supplicant to send the WPA-IE to the driver.
++
++setaeskey
++ This command is used to set the AES key, when the station is in Ad-hoc
++ mode.
++
++ where value can be any 16 byte value.
++
++ Usage:
++ iwpriv ethX setaeskey 12345678901234567890123456789012
++
++getaeskey
++ This command is used to get the AES key, when the station is in Ad-hoc
++ mode.
++
++rmaeskey
++ This command is used to remove the Ad-Hoc AES key that is previously set.
++ It will disable ad-hoc AES as well.
++
++getcis
++ This command is used to read the Card Info Structure Table.
++
++getlog
++ This command is used to get the 802.11 statistics available in the
++ station.
++
++ Note: This command is available only when STA is connected.
++
++getadhocstatus
++ This command is used to get the ad-hoc Network Status.
++
++ The various status codes are:
++ AdhocStarted
++ AdhocJoined
++ AdhocIdle
++ InfraMode
++ AutoUnknownMode
++
++ Note: This command is available only when STA is connected.
++
++adhocgrate
++ This command is used to enable(1) g_rate, Disable(0) g_rate
++ and request(2) the status which g_rate is disabled/enabled,
++ for Ad-hoc creator.
++
++ where value is:
++ 0 -- Disable
++ 1 -- Enable
++ 2 -- Get
++
++ledgpio
++ This command is used to set/get LED settings.
++
++ iwpriv ethX ledgpio <LEDs>
++ will set the corresponding LED for the GPIO Line.
++
++ iwpriv ethX ledgpio
++ will get the current LEDs settings.
++
++ Usage:
++ iwpriv eth1 ledgpio 1 0 2 1 3 16
++ LED 1 -> GPIO 0
++ LED 2 -> GPIO 1
++ LED 3 -> disable
++
++ iwpriv eth1 ledgpio
++ shows LED information in the format as mentioned above.
++
++ Note: LED 0 is invalid
++ Maximum Number of LEDs are 3.
++
++inactivityto
++ This command is used by the host to set/get the inactivity timeout value,
++ which specifies when WLAN device is put to sleep.
++
++ Usage:
++ iwpriv ethX inactivityto [<timeout>]
++
++ where the parameter are:
++ timeout: timeout value in milliseconds.
++
++ Example:
++ iwpriv eth1 inactivityto
++ "get the timeout value"
++
++ iwpriv eth1 inactivityto X
++ "set timeout value to X ms"
++
++sleeppd
++ This command is used to configure the sleep period of the WLAN device.
++
++ Usage:
++ iwpriv ethX sleeppd [<sleep period>]
++
++ where the parameter are:
++ Period: sleep period in milliseconds. Range 10~60.
++
++ Example:
++ iwpriv eth1 sleeppd 10
++ "set period as 10 ms"
++ iwpriv eth1 sleeppd
++ "get the sleep period configuration"
++
++enable11d
++ This command is used to control 11d
++ where value is:
++ 1 -- Enable
++ 0 -- Disable
++ 2 -- Get
++
++wmm
++ This command is used to control WMM
++
++ where value is:
++ 0 -- Disable
++ 1 -- Enable
++ 2 -- Get
++
++
++bgscan
++ Enables or disables the Background scan.
++
++ The configuration for bg scan must be set using wlanconfig
++
++ Usage:
++ wlanconfig ethX bgscanconfig bg_scan_config.conf
++ iwpriv ethX bgscan 0 (disable)
++ iwpriv ethX bgscan 1 (enable)
++ iwpriv ethX bgscan 2 (display enable or disable)
++
++tpccfg
++ Enables or disables automatic transmit power control.
++
++ The first parameter turns this feature on (1) or off (0). When turning
++ on, the user must also supply four more parameters in the following
++ order:
++ -UseSNR (Use SNR (in addition to PER) for TPC algorithm),
++ -P0 (P0 power level for TPC),
++ -P1 (P1 power level for TPC),
++ -P2 (P2 power level for TPC).
++
++ Usage:
++ iwpriv ethX tpccfg: Get current configuration
++ iwpriv ethX tpccfg 0: disable auto TPC
++ iwpriv ethX tpccfg 0x01 0x00 0x05 0x0a 0x0d: enable auto TPC; do not use SNR;
++ P0=0x05; P1=0x0a; P2=0x0d;
++ iwpriv ethX tpccfg 0x01 0x01 0x05 0x0a 0x0d: enable auto TPC; use SNR;
++ P0=0x05; P1=0x0a; P2=0x0d.
++
++sdioclock
++ Turn On(1) or Off(0) the SDIO clock.
++
++ Usage:
++ iwpriv ethX sdioclock 1 (on)
++ iwpriv ethX sdioclock 0 (off)
++
++wmm_qosinfo
++ This command sets WMM IE QOS info when an argument is given, and gets current WMM
++ IE QOS info when no argument is given.
++
++ Usage:
++ iwpriv ethX wmm_qosinfo 0x0f (set WMM IE QOS info to 0x0f)
++ iwpriv ethX wmm_qosinfo (get WMM IE QOS info)
++
++scanprobes
++ This command sets number of probe requests per channel.
++
++ Usage:
++ iwpriv ethX scanprobes 3 (set scan probes to 3)
++ iwpriv ethX scanprobes (get scan probes)
++
++lolisteninter
++ This command sets the value of listen interval.
++
++ Usage:
++ iwpriv ethX lolisteninter 234 (set the lolisteninter to 234)
++ iwpriv ethX lolisteninter (get the lolisteninter value)
++
++rateadapt
++ This command sets the data rates bitmap.
++ Where <n>
++ 0: no HW rate drop
++ 1: HW table rate drop
++ 2: HW single rate drop
++ <m>
++ data rate bitmap
++ Bit Data rate
++ 0 1 Mbps
++ 1 2 Mbps
++ 2 5.5 Mbps
++ 3 11 Mbps
++ 4 Reserved
++ 5 6 Mbps
++ 6 9 Mbps
++ 7 12 Mbps
++ 8 18 Mbps
++ 9 24 Mbps
++ 10 36 Mbps
++ 11 48 Mbps
++ 12 54 Mbps
++ 12-15 Reserved
++ <l> Threshold, Number of same rate retries before switch to Final rate.
++ Used only if HW single rate drop is selected. Typical values are from 3 to 6.
++
++ <k> Final Rate, This value is used only if HW single rate drop is selected.
++ value Data rate
++ 0 1 Mbps
++ 1 2 Mbps
++ 2 5.5 Mbps
++ 3 11 Mbps
++ 4 Reserved
++ 5 6 Mbps
++ 6 9 Mbps
++ 7 12 Mbps
++ 8 18 Mbps
++ 9 24 Mbps
++ 10 36 Mbps
++ 11 48 Mbps
++ 12 54 Mbps
++ 13-15 Reserved
++ Usage:
++ iwpriv ethX rateadapt
++ read the currect data rate setting
++ iwpriv ethX rateadapt 1 0x07
++ enable hardware auto data rate adapt and
++ data rates are 1Mbps, 2Mbsp and 5.5Mbps
++ iwpriv ethX rateadapt 2 0x0f 6 2
++ use HW single rate drop, data rates are 1Mbps, 2Mbsp and 5.5Mbps, 11Mbps
++ Threshold is 6, Final Rate is 5.5 Mbps
++
++fwwakeupmethod
++ This command is used to set the firmware wakeup method.
++
++ where value <n> is:
++ 0 -- Leave the current method to wakeup firmware unchanged
++ 1 -- Firmware wakeup through the interface command interrupt
++ -- (default setting for SDIO/GSPI)
++ 2 -- Firmware wakeup through the GPIO pin
++ -- (default setting for CF)
++
++ Usage:
++ iwpriv ethX fwwakeupmethod
++ Read the current firmware wakeup method setting
++ iwpriv ethX fwwakeupmethod 0
++ Leave the current method to wakeup firmware unchanged
++ iwpriv ethX fwwakeupmethod 1
++ Firmware wakeup through the interface command interrupt
++ iwpriv ethX fwwakeupmethod 2
++ Firmware wakeup through the GPIO pin
++
++txcontrol [DefaultFlags (if no UP setting)] [UserPriority] [UserPriorityFlags]
++ This command is used to set/get the TX rate, WMM ack policy, and
++ retry limit for all packets, or selectively the packets with a specific
++ user priority.
++
++ The DefaultFlags setting is ignored for any command with 2 or more
++ arguments.
++
++ The value of the u32 txcontrol flags returned and input for
++ DefaultFlags or UserPriorityFlags specific settings is given by the
++ following bitmap:
++
++ bit[4:0], if bit[4] == 1:
++ bit[3:0] -- 0 1 2 3 4 5 6 7 8 9 10 11 12 13-16
++ Data Rate(Mbps) -- 1 2 5.5 11 Rsv 6 9 12 18 24 36 48 54 Rsv
++
++ bit[12:8]
++ if bit[12] == 1, bit[11:8] specifies the Tx retry limit.
++
++ bit[14:13] specifies per packet ack policy:
++ if bit[14] == 1, bit[13] == 1 specifies No Ack Policy
++
++ All unused and reserved bits should be set to zero for the entire
++ u32 field.
++
++ Usage:
++ Number of arguments given:
++
++ 0: Return the default setting for the txcontrol flags
++ > iwpriv eth1 txcontrol
++
++ 1: Set the default value for the txcontrol flags
++ > iwpriv eth1 txcontrol 0x6013 - No ACK, 11Mbps
++ > iwpriv eth1 txcontrol 0x151A - 5 retries, 36Mbps
++
++ 2: Return a specific User Priority setting. If the UP setting is zero,
++ the default value will be used and returned:
++ > iwpriv eth1 txcontrol 0 7 - Return UP 7 txcontrol value (UP7 = VO)
++
++ 3: Set a User Priority specific value for the txcontrol flags. A value
++ of zero will revert to the default setting:
++ > iwpriv eth1 txcontrol 0 5 0x6013 - (UP5 = VI), No ACK 11Mbps.
++
++uapsdnullgen
++ This command is used to enable(1) UAPSD null package generation,
++ Disable(0) UAPSD null package generation, and request(2) the status
++ which null package generation is disabled/enabled,
++ for Ad-hoc creator.
++
++ where value is:
++ 0 -- Disable
++ 1 -- Enable
++ 2 -- Get
++
++psnullinterval
++ This command is used to set/request NULL package interval for Power Save
++ under infrastructure mode.
++
++ where value is:
++ -1 -- Disable
++ n>0 -- Set interval as n (seconds)
++
++getrxinfo
++ This command gets non average value of Signal to Noise Ratio of Data and rate index.
++
++ The following table shows RateIndex and Rate
++
++ RateIndex Data rate
++ 0 1 Mbps
++ 1 2 Mbps
++ 2 5.5 Mbps
++ 3 11 Mbps
++ 4 Reserved
++ 5 6 Mbps
++ 6 9 Mbps
++ 7 12 Mbps
++ 8 18 Mbps
++ 9 24 Mbps
++ 10 36 Mbps
++ 11 48 Mbps
++ 12 54 Mbps
++ 13-15 Reserved
++
++gettxrate
++ This command gets current Tx rate index of the first packet associated with Rate Adaptation.
++
++ The following table shows RateIndex and Rate
++
++ RateIndex Data rate
++ 0 1 Mbps
++ 1 2 Mbps
++ 2 5.5 Mbps
++ 3 11 Mbps
++ 4 Reserved
++ 5 6 Mbps
++ 6 9 Mbps
++ 7 12 Mbps
++ 8 18 Mbps
++ 9 24 Mbps
++ 10 36 Mbps
++ 11 48 Mbps
++ 12 54 Mbps
++ 13-15 Reserved
++
++bcninterval
++ This command is used to set beacon interval in adhoc mode when an argument is given,
++ return the value set by the user and the current adhoc beacon interval if adapter is in connected state.
++ The valid beacon interval is between 20 - 1000, default beacon interval is 100.
++
++ Usage:
++ iwpriv ethX bcninterval 100 (set adhoc beacon interval to 100)
++
++ not connected:
++ iwpriv ethX bcninterval (get adhoc beacon interval set by user)
++
++ connected:
++ iwpriv ethX bcninterval (get adhoc beacon interval set by user previously
++ and current beacon interval)
++
++setcoalescing
++ This command is used to disable/enable IBSS coalescing function, and get IBSS coalescing status.
++
++ where value is:
++ 0 -- Disable IBSS coalescing function
++ 1 -- Enable IBSS coalescing function
++ 2 -- Get current IBSS coalescing status
++
++bcnmisto
++ This command is used to set/get beacon miss timeout for Power Save
++ under infrastructure mode.
++
++ where value is:
++ 0xffff -- Disabled
++ 0 -- no change
++ 1--50 (miliseconds)
++
++adhocawakepd
++ This command is used to set/get adhoc awake period for Power Save Mode.
++
++ where value is:
++ 0xff -- firmware will go to sleep after send out beacon
++ 0--no change
++ 1--31 (beacon interval)
++
++sdiopullctrl
++ This command is used to set/get seting of pulling up and pulling down of SDIO lines,
++ The PullUp is the delay before pulling SDIO lines up. The PullDown is the
++ delay before pull SDIO lines down. the unit is us for both PullUp and PullDown.
++
++ where <m> PullUp
++ 0--no delay is needed
++ 0xffff--no pulling up is needed
++
++ <n> PullDown
++ 0--no delay is needed
++ 0xffff--no pulling up is needed
++
++ Usage:
++ iwpriv ethX sdiopullctrl
++ Read the currect firmware SDIO PullUp and PullDown settings
++ iwpriv ethX sdiopullctrl 5 5
++ Set SDIO PullUp/PullDown to 5 us
++ iwpriv ethX sdiopullctrl 0xffff 0xffff
++ Disable SDIO PullUp and PullDown
++
++scantime
++ This command is used to set/get scan time per channel in milliseconds.
++ The current setting will be returned every time.
++
++ Usage:
++ iwpriv ethX scantime [s] [a] [p]
++
++ where the parameters are,
++ [s]: specific SSID/BSSID scan time, default 100 ms, max 500 ms
++ [a]: active scan time, default 100 ms, max 500 ms
++ [p]: passive scan time, default 100 ms, max 2000 ms
++ No change if the parameter is 0 or the parameter is not provided.
++
++ For example:
++ iwpriv ethX scantime 30 (set specific scan time to 30 ms)
++ iwpriv ethX scantime 0 100 (set active scan time to 100 ms)
++ iwpriv ethX scantime 30 80 200 (set specific scan time to 30 ms,
++ set active scan time to 80 ms,
++ set passive scan time to 200 ms)
++
++ldocfg
++ This command is used to set/get internal/external core power voltage source.
++ By default firmware uses internal LDO for 1.2V core power supply.
++ The current setting will be returned if no parameter provided.
++
++ Usage:
++ iwpriv ethX ldocfg [n]
++
++ where the parameter is,
++ 0 -- internal
++ 1 -- external
++
++dataevtcfg
++ This command is used to set/get the subscription of low RSSI, low SNR, high RSSI and
++ high SNR events in data packet.
++
++ Where value <a> is:
++ Events bitmap
++ Bit
++ 0 RSSI_LOW RSSI_LOW event is generated when avg data RSSI is below threshold
++ 1 SNR_LOW SNR_LOW event is generated when avg data SNR is below threshold
++ 2 RSSI_HIGH RSSI_HIGH event is generated when avg data RSSI go above threshold
++ 3 SNR_HIGH SNR_HIGH event is generated when avg data SNR go above threshold
++
++ Where value <b> is:
++ RSSI_LOW threshold (Absolute value, the actual value should be negative)
++ Where value <c> is:
++ RSSI_LOW reporting frequency. if set to 0, event will only report once.
++ if set to 1, event will be reported every time it occur.
++ if set to N, event will be reported only when the condition happens N consecutive times.
++
++ Where value <d> is:
++ SNR_LOW threshold
++ Where value <e> is:
++ SNR_LOW reporting frequency. if set to 0, event will only report once.
++ if set to 1, event will be reported every time it occur.
++ if set to N, event will be reported only when the condition happens N consecutive times.
++
++ Where value <f> is:
++ RSSI_HIGH threshold (Absolute value, the actual value should be negative)
++ Where value <g> is:
++ RSSI_HIGH reporting frequency. if set to 0, event will only report once.
++ if set to 1, event will be reported every time it occur.
++ if set to N, event will be reported only when the condition happens N consecutive times.
++
++ Where value <h> is:
++ SNR_HIGH threshold
++ Where value <i> is:
++ SNR_HIGH reporting frequency. if set to 0, event will only report once.
++ if set to 1, event will be reported every time it occur.
++ if set to N, event will be reported only when the condition happens N consecutive times.
++
++ Usage:
++ iwpriv ethX dataevtcfg (get current data subscribe event settings)
++ iwpriv ethX dataevtcfg 15 70 1 56 0 40 5 86 0
++ (set current data subscribe event,
++ when avg data RSSI below -70, such as -80,
++ RSSI_LOW event will be generated every time;
++ when avg data RSSI above -40 happens 5 consecutive times,
++ such as -30,-32,-34,-29,-33, RSSI_HIGH event will be generated 1 times;
++ when avg data SNR below 56 or above 86,
++ SNR_LOW or SNR_HIGHT event will be generated once)
++
++sdiomode
++ This command is used to set/get sdio mode.
++ The setting will take effect when next command 53 is issued.
++
++ where the parameter <n> is,
++ 1 -- set sdio to 1 bit mode
++ 4 -- set sdio to 4 bit mode
++
++ Usage:
++ iwpriv ethX sdiomode (get current sdio mode)
++ iwpriv ethX sdiomode 1 (set to 1 bit mode)
++ iwpriv ethX sdiomode 4 (set to 4 bit mode)
++
++rtsctsctrl
++ This command is used to set/get the RTS/CTS or CTS To SELF for g rate protection to the firmware.
++ where the parameter <n> is,
++ 1 -- set RTS/CTS for g rate protection to the firmware.
++ 0 -- set CTS To SELF for g rate protection to the firmware.
++
++ Usage:
++ iwpriv ethX rtsctsctrl (gets the RTS/CTS or CTS To SELF)
++ iwpriv ethX rtsctsctrl 1 (set RTS/CTS for g rate protection to the firmware.)
++ iwpriv ethX rtsctsctrl 0 (set CTS To SELF for g rate protection to the firmware.)
++
++drvdbg
++ This command is used to set/get the bit masks of driver debug message control.
++
++ Usage:
++ iwpriv ethX drvdbg [n] [m]
++
++ Where the parameter <n> is the generic debug message control bit mask.
++ The following types of driver debug messages can be dynamically enabled or
++ disabled by setting or clearing the corresponding bits,
++ bit 0: MSG PRINTM(MSG,...)
++ bit 1: FATAL PRINTM(FATAL,...)
++ bit 2: ERROR PRINTM(ERROR,...)
++ bit 3: DATA PRINTM(DATA,...)
++ bit 4: CMND PRINTM(CMND,...)
++ bit 5: EVENT PRINTM(EVENT,...)
++ bit 6: INTR PRINTM(INTR,...)
++ ...
++ bit 16: DAT_D PRINTM(DAT_D,...), DBG_HEXDUMP(DAT_D,...)
++ bit 17: CMD_D PRINTM(CMD_D,...), DBG_HEXDUMP(CMD_D,...)
++ bit 18: FW_D PRINTM(FW_D,...)
++ ...
++ bit 28: ENTRY PRINTM(ENTRY,...), ENTER(), LEAVE()
++ bit 29: WARN PRINTM(WARN,...)
++ bit 30: INFO PRINTM(INFO,...)
++
++ Where the parameter <m> is the extended interface module debug message control
++ bit mask. The following types of debug messages can be controlled.
++
++ bit 0: IF_D PRINTM(IF_D,...), DBG_HEXDUMP(IF_D,...)
++
++ If CONFIG_DEBUG=2, all kinds of debug messages can be configured.
++ By default all debug messages are enabled except for EVENT and IF_D.
++
++ If CONFIG_DEBUG=1, all kinds of debug messages can be configured except
++ for ENTRY, WARN and INFO. By default MSG and FATAL are enabled.
++
++ Some special debug messages,
++ '*' // WLAN driver ISR is called (bit 6 INTR enabled)
++ '|' // PS awake event is received (bit 5 EVENT enabled)
++ '_' // PS sleep event is received (bit 5 EVENT enabled)
++ '+' // PS sleep confirm is sent (bit 5 EVENT enabled)
++
++ For example:
++ iwpriv ethX drvdbg (get the current driver debug masks)
++ iwpriv ethX drvdbg 0 0 (disable all the debug messages)
++ iwpriv ethX drvdbg 7 (enable MSG, FATAL and ERROR messages,
++ no change for if debug control)
++ iwpriv ethX drvdbg 3 1 (enable MSG and FATAL messages,
++ enable IF_D message)
++ iwpriv ethX drvdbg -1 -1 (enable all the debug messages)
++
++adhocgprot
++ This command is used to set/get 802.11g ad-hoc protection state.
++
++ where value is:
++ 0 -- Disable
++ 1 -- Enable
++ 2 -- Get
++ Usage:
++ iwpriv ethX adhocgprot 0 (disable 802.11g ad-hoc g protection)
++ iwpriv ethX adhocgprot 1 (enable 802.11g ad-hoc g protection)
++ iwpriv ethX adhocgprot 2 (get 802.11g ad-hoc g protection state)
++
++getrate
++ This command is used to get the supported rates. Returned rates are in 0.5M unit.
++
++associate <scan table index>
++ Associate to a specific BSS entry in the scan table. The enumeration
++ of the entries in the scan table is determined by the
++ getscantable API or from the iwlist scan results. A re-scan is not
++ performed before the association attempt is made.
++
++getdtim
++ This command is used to get the current DTIM value.
++ Note: This command is available only when STA is connected.
++
++
++===============================================================================
++
++ U S E R M A N U A L F O R W L A N _ C O N F I G
++
++NAME
++wlanconfig - configure the additional parameters available for the Marvell
++ WLAN Linux Driver.
++
++SYNOPSIS
++wlanconfig -v
++wlanconfig <ethX> <command> [parameters] ...
++
++wlanconfig ethX version
++wlanconfig ethX <rdmac|rdbbp|rdrf> <offset>
++wlanconfig ethX <wrmac|wrbbp|wrrf> <offset> <n>
++wlanconfig ethX sdcmd52r <FN no.> <address>
++wlanconfig ethX sdcmd52w <FN no.> <address> <data>
++wlanconfig ethX caldataext <filename>
++wlanconfig ethX rdeeprom <offset> <length>
++wlanconfig ethX sleepparams <config values>
++wlanconfig ethX bca-ts <config values>
++wlanconfig ethX extscan <ssid>
++wlanconfig ethX getscanlist
++
++Version 4 Command:
++wlanconfig ethX bgscanconfig <filename>
++
++Version 5 Command:
++wlanconfig ethX hostcmd <hostcmd.conf> <subevent_get>
++wlanconfig ethX hostcmd <hostcmd.conf> <subevent_set>
++
++Version 6 Command:
++wlanconfig ethX setuserscan [ARGS]
++wlanconfig ethX getscantable
++wlanconfig ethX getassocrsp
++
++Version 8
++wlanconfig ethX addts <filename.conf> <section# of tspec> <timeout in ms>
++wlanconfig ethX delts <filename.conf> <section# of tspec>
++wlanconfig ethX qconfig set msdu <lifetime in TUs> [Queue Id: 0-3]
++wlanconfig ethX qconfig get [Queue Id: 0-3]
++wlanconfig ethX qconfig def [Queue Id: 0-3]
++wlanconfig ethX qstats on [Queue Id: 0-3]
++wlanconfig ethX qstats off [Queue Id: 0-3]
++wlanconfig ethX qstats get [Queue Id: 0-3]
++wlanconfig ethX hostcmd <hostcmd.conf> <pa_cfg_ext_get>
++wlanconfig ethX hostcmd <hostcmd.conf> <pa_cfg_ext_set>
++wlanconfig ethX hostcmd <hostcmd.conf> <arp_filter>
++wlanconfig ethX hostcmd <hostcmd.conf> <auto_tx_get>
++wlanconfig ethX hostcmd <hostcmd.conf> <NatKeepAlive>
++wlanconfig ethX hostcmd <hostcmd.conf> <auto_tx_unreg>
++wlanconfig ethX hostcmd <hostcmd.conf> <ledctrl_get>
++wlanconfig ethX hstest
++wlanconfig ethX getcfptable [region]
++
++Version 9
++wlanconfig ethX gettsf
++wlanconfig ethX arpfilter <arpfilter.conf>
++wlanconfig ethX txpktstats
++
++DESCRIPTION
++
++those commands are used in Marvell specic applicaion called wlanconfig.
++
++===========
++-v
++ This command is used to display the version of wlanconfig utility.
++ Usage:
++ wlanconfig -v
++
++rdmac
++rdbbp
++rdrf
++ These commands are used to read the MAC, BBP and RF registers from the
++ card. These commands take one parameter that specifies the offset
++ location that is to be read. This parameter can be specified either in
++ decimal or in hexadecimal (by preceding the number with a "0x").
++
++ Usage:
++ wlanconfig ethX rdmac 0xa123
++ wlanconfig ethX rdbbp 0x0123
++ wlanconfig ethX rdrf 0x0123
++
++wrmac
++wrbbp
++wrrf
++ These commands are used to write the MAC, BBP and RF registers in the
++ card. These commands take two parameters that specify the offset
++ location and the value that is to be written. This parameters can be
++ specified either in decimal or in hexadecimal (by preceding the number
++ with a "0x").
++
++ Usage:
++ wlanconfig ethX wrmac 0xa123 0xaa
++ wlanconfig ethX wrbbp 0x0123 0xaa
++ wlanconfig ethX wrrf 0x0123 0xaa
++
++sdcmd52r
++ This command is used to read a controller register in
++ Secure Digital I/O Interfaces.
++
++ wlanconfig eth1 sdcmd52r <function number> <register address>
++
++ Usage:
++ wlanconfig eth1 sdcmd52r 0x00 0x07
++
++sdcmd52w
++ This command is used to write to a controller register in
++ Secure Digital I/O Interfaces.
++
++ wlanconfig eth1 sdcmd52w <function number> <register address> <value>
++
++ Usage:
++ wlanconfig eth1 sdcmd52w 0x00 0x02 0x0a
++
++caldataext
++ In order to overcome the situation without EEPROM in the WLAN module,
++ we send the extension calibration command to modify the existing
++ hardware-spec command. This command takes one parameter that specifies
++ the file name of the configuration file.
++
++ Usage:
++ wlanconfig eth1 caldataext <cal_data_ext_set_<version>.conf>
++ cal_data_ext_set_<version>.conf is a configuration file to the
++ wlanconfig to set the calibration values. The 3 existing
++ versions are v5, vA and v7.
++ Example:
++ wlanconfig eth1 caldataext cal_data_ext_set_v5.conf
++ Edit this file for changing calibration values.
++
++rdeeprom
++ To read the EEPROM contents of the card.
++
++ Usage:
++ wlanconfig ethX rdeeprom 0x00 0x10
++
++sleepparams
++ This command is used to set the sleepclock configurations
++
++ Usage:
++ wlanconfig ethX sleepparams get: reads the current sleepclock configuration
++
++ wlanconfig ethX sleepparams set p1 p2 p3 p4 p5 p6: writes the sleepclock configuration.
++
++ where:
++ p1 is Sleep clock error in ppm (0-65535)
++ p2 is Wakeup offset in usec (0-65535)
++ p3 is Clock stabilization time in usec (0-65535)
++ p4 is Control periodic calibration (0-2)
++ p5 is Control the use of external sleep clock (0-2)
++ p6 is reserved for debug (0-65535)
++
++bca-ts
++ This command is used to set/get the BCA timeshare parameters.
++
++ This command only works after BCA been enabled.
++
++ Usage:
++ wlanconfig ethX bca-ts <Traffic Type> <TimeShareInterval> <BTTime>
++
++ where:
++ Traffic Type 0 - Wlan and bluetooth are low priority.
++ 1 - Wlan and bluetooth are high priority.
++
++ TimeShareInterval value is not multiple of 10 then floor value
++ is taken and the valid range is < 20 ... 60,000 > in milliseconds.
++
++ BTTime value is not multiple of 10 then floor value is
++ taken and the valid range is < 0 ... TimeShareInterval value >
++ in milliseconds.
++
++ Example:
++ wlanconfig ethX bca-ts get 1
++ get the BCA timeshare settings when wlan and bluetooth are set to high priority.
++
++ wlanconfig ethX bca-ts set 1 30 20
++ set wlan and bluetooth to high priority, wlan TimeShareInterval to 30ms, BTTime to 20ms.
++
++
++bgscanconfig
++ This will configure the various parameters for background scan.
++
++ wlanconfig ethX bgscanconfig bg_scan_config.conf
++
++ bg_scan_config.conf is the configuration file to wlanconfig
++
++ Edit this file for changing bg scan values.
++
++hostcmd <hostcmd.conf> <subevent_get>
++hostcmd <hostcmd.conf> <subevent_set>
++ This command is used to set the configurations for
++ event descriptor interface command.
++ hostcmd.conf is a generic configuration file containing multiple configuration enties
++ for subscrive event API
++ subsvent_get: get subscribed event parameters
++ subsvent_set: set subscribed event parameters
++
++ Usage:
++ wlanconfig ethX hostcmd hostcmd.conf subevent_get
++ wlanconfig ethX hostcmd hostcmd.conf subevent_set
++
++extscan
++ This command is used to do a specific scan.
++
++ Usage: wlanconfig ethX extscan <SSID>
++
++ Example:
++ wlanconfig ethX extscan LINKSYS-AP
++
++ To see the results of use getscanlist command.
++
++getscanlist
++ This command is used to get the scan results.
++
++ Usage: wlanconfig ethX getscanlist
++
++ Example:
++ wlanconfig ethX getscanlist
++
++setuserscan
++ Initiate a customized scan and retrieve the results
++
++ Usage:
++ wlanconfig ethX setuserscan [ARGS]
++
++ where [ARGS]:
++
++ chan=[chan#][band][mode] where band is [a,b,g] and mode is
++ blank for active or 'p' for passive
++ bssid=xx:xx:xx:xx:xx:xx specify a BSSID filter for the scan
++ ssid="[SSID]" specify a SSID filter for the scan
++ wc="[WILDCARD SSID]" specify a UNIX pattern matching filter (using *
++ and ?) for SSIDs found in a broadcast probe
++ keep=[0 or 1] keep the previous scan results (1), discard (0)
++ dur=[scan time] time to scan for each channel in milliseconds
++ probes=[#] number of probe requests to send on each chan
++ for each broadcast probe required and each SSID
++ specific probe required
++ type=[1,2,3] BSS type: 1 (Infra), 2(Adhoc), 3(Any)
++
++ Any combination of the above arguments can be supplied on the command line.
++ If the chan token is absent, a full channel scan will be completed by
++ the driver. If the dur or probes tokens are absent, the driver default
++ setting will be used. The bssid and ssid fields, if blank,
++ will produce an unfiltered scan. The type field will default to 3 (Any)
++ and the keep field will default to 0 (Discard).
++
++ Examples:
++ 1) Perform an active scan on channels 1, 6, and 11 in the 'g' band:
++ setuserscan chan=1g,6g,11g
++
++ 2) Perform a passive scan on channel 11 for 20 ms:
++ setuserscan chan=11gp dur=20
++
++ 3) Perform an active scan on channels 1, 6, and 11; and a passive scan on
++ channel 36 in the 'a' band:
++ setuserscan chan=1g,6g,11g,36ap
++
++ 4) Perform an active scan on channel 6 and 36 for a specific SSID:
++ setuserscan chan=6g,36a ssid="TestAP"
++
++ 5) Scan all available channels (B/G, A bands) for a specific BSSID, keep
++ the current scan table intact, update existing or append new scan data:
++ setuserscan bssid=00:50:43:20:12:82 keep=1
++
++ 6) Scan channel 6, for all infrastructure networks, sending two probe
++ requests. Keep the previous scan table intact. Update any duplicate
++ BSSID/SSID matches with the new scan data:
++ setuserscan chan=6g type=1 probes=2 keep=1
++
++ 7) Scan channel 1 and 6, for all networks matching the Mrvl*AP
++ or AP*Mrvl? patterns and for MrvlTst SSID. Generate 3 broadcast
++ probes for the patterns and 3 SSID specific probes for MrvlTst on
++ both channel 1 and channel 6.
++ chan=1g,6g probes=3 wc="Mrvl*AP" wc="AP*Mrvl?" ssid="MrvlTst"
++
++ All entries in the scan table (not just the new scan data when keep=1)
++ will be displayed upon completion by use of the getscantable ioctl.
++
++getscantable
++ Display the current contents of the driver scan table
++
++ Usage:
++ wlanconfig ethX getscantable
++ wlanconfig ethX getscantable [#]
++ wlanconfig ethX getscantable tsf
++ wlanconfig ethX getscantable help
++
++ 1) Without argument, the entire scantable is displayed.
++ 2) Specifying a # will display detailed information about a specific scan
++ table entry. '0' displays driver cached information regarding the
++ current association (if any).
++ 3) The tsf argument will display the entire scan table with the recorded
++ TSF timestamp for the entry.
++ 4) The help argument will display the legend for the capability field
++
++getassocrsp
++ Display the contents of the driver association response buffer. The
++ driver buffer is cleared after the response is returned to prevent
++ state response buffer returns.
++
++ Usage:
++ wlanconfig ethX getassocrsp
++
++setmrvltlv
++ Setup a test Marvell TLV for the driver to insert in the next
++ association command to the firmware.
++
++ wlanconfig will provision a test TLV that can be verified in the assoc.
++ response to the AP. Used to test the IOCTL functionality.
++
++ Usage:
++ wlanconfig ethX setmrvltlv
++
++addts
++ Send an ADDTS command to the associated AP.
++
++ Process a given conf file for a specific TSPEC data block. Send the
++ TSPEC along with any other IEs to the driver/firmware for transmission
++ in an ADDTS request to the associated AP.
++
++ Return the execution status of the command as well as the ADDTS response
++ from the AP if any.
++
++ Usage:
++ wlanconfig ethX addts <filename.conf> <section# of tspec> <timeout(ms)>
++
++delts
++ Send a DELTS command to the associated AP.
++
++ Process a given conf file for a specific TSPEC data block. Send the
++ TSPEC along with any other IEs to the driver/firmware for transmission
++ in a DELTS request to the associated AP.
++
++ Return the execution status of the command. There is no response to a
++ DELTS from the AP.
++
++ Usage:
++ wlanconfig ethX delts <filename.conf> <section# of tspec>
++
++qconfig
++ Send a WMM AC Queue configuration command to get/set/default params
++
++ Configure or get the parameters of a WMM AC queue. The command takes
++ an optional Queue Id as a last parameter. Without the queue id, all
++ queues will be acted upon.
++
++ Usage:
++ wlanconfig ethX qconfig set msdu <lifetime in TUs> [Queue Id: 0-3]
++ wlanconfig ethX qconfig get [Queue Id: 0-3]
++ wlanconfig ethX qconfig def [Queue Id: 0-3]
++
++qstats
++ Turn on/off or retrieve and clear the queue statistics for an AC
++
++ Turn the queue statistics collection on/off for a given AC or retrieve the
++ current accumulated stats and clear them from the firmware. The command
++ takes an optional Queue Id as a last parameter. Without the queue id,
++ all queues will be acted upon.
++
++ Usage:
++ wlanconfig ethX qstats on [Queue Id: 0-3]
++ wlanconfig ethX qstats off [Queue Id: 0-3]
++ wlanconfig ethX qstats get [Queue Id: 0-3]
++
++hostcmd <hostcmd.conf> <pa_cfg_ext_get>
++hostcmd <hostcmd.conf> <pa_cfg_ext_set>
++ This configures the power adaptation paramemters
++
++ Usage:
++ wlanconfig ethX hostcmd hostcmd.conf pa_cfg_ext_get
++ wlanconfig ethX hostcmd hostcmd.conf pa_cfg_ext_set
++
++ hostcmd.conf is a generic configuration file containing multiple configuration enties
++ for power adapation
++ pa_cfg_ext_get: get pa_cfg_ext parameters
++ pa_cfg_ext_set: set pa_cfg_ext parameters
++
++ The following table shows the bitmap of the rates (bit 0 is the least significant bit):
++
++ Bit Data rate
++ 0 1 Mbps
++ 1 2 Mbps
++ 2 5.5 Mbps
++ 3 11 Mbps
++ 4 Reserved
++ 5 6 Mbps
++ 6 9 Mbps
++ 7 12 Mbps
++ 8 18 Mbps
++ 9 24 Mbps
++ 10 36 Mbps
++ 11 48 Mbps
++ 12 54 Mbps
++ 13-15 Reserved
++
++ Up to 5 power level groups are supported.
++
++ The default power adaptation groups:
++
++ Power Level Rate Bitmap (Mbps)
++ 13 dbm 0x1800 (54, 48)
++ 15 dbm 0x07e0 (36, 24, 18, 12, 9, 6)
++ 18 dbm 0x000f (11, 5.5, 2, 1)
++
++ Edit the hostcmd.conf file to change the settings
++
++hostcmd <hostcmd.conf> <arp_filter>
++ This is an extended host_sleep_cfg command to configure the ARP filtering parameters.
++
++ Usage:
++ wlanconfig ethX hostcmd hostcmd.conf arp_filter
++
++ Edit the arp_filter section in hostcmd.conf file to change the settings
++
++hostcmd <hostcmd.conf> <auto_tx_get>
++hostcmd <hostcmd.conf> <NatKeepAlive>
++hostcmd <hostcmd.conf> <auto_tx_unreg>
++ This configures the Frame Auto Transmission paramemters
++
++ Usage:
++ wlanconfig ethX hostcmd hostcmd.conf auto_tx_get
++ wlanconfig ethX hostcmd hostcmd.conf NatKeepAlive
++ wlanconfig ethX hostcmd hostcmd.conf auto_tx_unreg
++
++ hostcmd.conf is a generic configuration file containing multiple configuration enties
++ for Frame Auto Transmission
++ auto_tx_get: get auto_tx parameters
++ NatKeepAlive: register to firmware for sending NAT Keep Alive packet
++ auto_tx_unreg: unregister to firmware auto_tx
++
++ Edit the auto_tx section in hostcmd.conf file to change the settings
++
++hostcmd <hostcmd.conf> <ledctrl_get>
++ This command is used to set/get LED control.
++
++ Usage:
++ wlanconfig ethX hostcmd hostcmd.conf ledctrl_get
++ wlanconfig ethX hostcmd hostcmd.conf ledctrl_set
++
++ hostcmd.conf is a generic configuration file containing multiple configuration enties
++ for LED Ctrl
++ led_ctrl_get: get auto_tx parameters
++ led_ctrl_set: set auto_tx parameters
++
++ Edit the ledctrl section in hostcmd.conf file to change the settings
++
++hstest
++ This command runs in the background to handle GPIO/SDIO interrupt events
++ in HOST SLEEP mode.
++
++ Usage:
++ wlanconfig ethX hstest &
++
++getcfptable
++ This command is used to get Channel-Freq-MaxTxPower table based on the region code.
++ If no parameter provided, the CFP table for current region code will be returned.
++
++ Usage:
++ wlanconfig ethX getcfptable [region]
++
++gettsf
++ Display the current MAC TSF value.
++
++arpfilter <arpfilter.conf>
++ This command is used to configure the ARP filtering parameters.
++
++ Usage:
++ wlanconfig ethX arpfilter arpfilter.conf
++
++ Edit arpfilter.conf file to change the settings
++
++txpktstats
++ Retrieve and clear transmit packet statistics collected by the firmware:
++
++ The API displays the following statistics for each rate:
++ - Number of packets initially queued using the rate
++ - Number of total attempts for the packets queued using this initial
++ rate. This includes attempts at other rates in case of hardware or
++ single rate drop modes.
++ - Number of retry exhaustion failures for packets queued using this
++ initial rate.
++ - Number of MSDU lifetime expiry failures for packets queued using
++ this initial rate.
++ - Number of packets successfully completed at this rate
++
++==============================================================================
+diff --git a/drivers/net/wireless/marvell8686/host.h b/drivers/net/wireless/marvell8686/host.h
+new file mode 100644
+index 0000000..cf4562a
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/host.h
+@@ -0,0 +1,349 @@
++/** @file host.h
++ *
++ * @brief This file contains definitions of WLAN commands.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 10/11/05: Add Doxygen format comments
++ 01/11/06: Remove assoc response codes; full IEEE assoc resp now returned
++ 04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
++ 04/10/06: Add power_adapt_cfg_ext command
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 05/03/06: Add auto_tx hostcmd
++ 05/04/06: Add IBSS coalescing related new hostcmd and event
++ 08/28/06: Add LED_CTRL hostcmd
++********************************************************/
++
++#ifndef _HOST_H_
++#define _HOST_H_
++
++/** PUBLIC DEFINITIONS */
++#define DEFAULT_AD_HOC_CHANNEL 6
++#define DEFAULT_AD_HOC_CHANNEL_A 36
++/** The first valid channel for use */
++#define FIRST_VALID_CHANNEL 0xff
++
++/** IEEE 802.11 OIDs */
++#define OID_802_11_INFRASTRUCTURE_MODE 0x00008001
++#define OID_802_11_FRAGMENTATION_THRESHOLD 0x00008002
++#define OID_802_11_RTS_THRESHOLD 0x00008003
++#define OID_802_11_ADD_WEP 0x00008004
++#define OID_802_11_REMOVE_WEP 0x00008005
++#define OID_802_11_TX_RETRYCOUNT 0x00008006
++#define OID_802_11D_ENABLE 0x00008007
++#define OID_802_11_DTIM 0x00008009
++
++#define HostCmd_OPTION_WAITFORRSP 0x0002
++
++/** Host Command ID */
++#define HostCmd_CMD_GET_HW_SPEC 0x0003
++#define HostCmd_CMD_802_11_RESET 0x0005
++#define HostCmd_CMD_802_11_SCAN 0x0006
++#define HostCmd_CMD_802_11_GET_LOG 0x000b
++#define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010
++#define HostCmd_CMD_802_11_EEPROM_ACCESS 0x0059
++#define HostCmd_CMD_802_11_ASSOCIATE 0x0012
++#define HostCmd_CMD_802_11_SET_WEP 0x0013
++#define HostCmd_CMD_802_11_SNMP_MIB 0x0016
++#define HostCmd_CMD_MAC_REG_ACCESS 0x0019
++#define HostCmd_CMD_BBP_REG_ACCESS 0x001a
++#define HostCmd_CMD_RF_REG_ACCESS 0x001b
++#define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c
++#define HostCmd_CMD_802_11_RF_CHANNEL 0x001d
++#define HostCmd_CMD_802_11_RF_TX_POWER 0x001e
++#define HostCmd_CMD_802_11_RSSI 0x001f
++#define HostCmd_CMD_802_11_RF_ANTENNA 0x0020
++
++#define HostCmd_CMD_802_11_PS_MODE 0x0021
++
++#define HostCmd_CMD_802_11_DEAUTHENTICATE 0x0024
++#define HostCmd_CMD_MAC_CONTROL 0x0028
++#define HostCmd_CMD_802_11_AD_HOC_START 0x002b
++#define HostCmd_CMD_802_11_AD_HOC_JOIN 0x002c
++
++#define HostCmd_CMD_802_11_KEY_MATERIAL 0x005e
++
++#define HostCmd_CMD_802_11_DEEP_SLEEP 0x003e
++
++#define HostCmd_CMD_802_11_AD_HOC_STOP 0x0040
++
++#define HostCmd_CMD_802_11_HOST_SLEEP_CFG 0x0043
++#define HostCmd_CMD_802_11_WAKEUP_CONFIRM 0x0044
++#define HostCmd_CMD_802_11_HOST_SLEEP_ACTIVATE 0x0045
++
++#define HostCmd_CMD_802_11_MAC_ADDRESS 0x004D
++#define HostCmd_CMD_802_11_EEPROM_ACCESS 0x0059
++
++#define HostCmd_CMD_802_11_BAND_CONFIG 0x0058
++
++#define HostCmd_CMD_802_11D_DOMAIN_INFO 0x005b
++
++#define HostCmd_CMD_802_11_SLEEP_PARAMS 0x0066
++
++#define HostCmd_CMD_802_11_INACTIVITY_TIMEOUT 0x0067
++
++#define HostCmd_CMD_802_11_SLEEP_PERIOD 0x0068
++#define HostCmd_CMD_802_11_BCA_CONFIG_TIMESHARE 0x0069
++
++#define HostCmd_CMD_802_11_BG_SCAN_CONFIG 0x006b
++#define HostCmd_CMD_802_11_BG_SCAN_QUERY 0x006c
++
++#define HostCmd_CMD_802_11_CAL_DATA_EXT 0x006d
++
++#define HostCmd_CMD_WMM_ADDTS_REQ 0x006E
++#define HostCmd_CMD_WMM_DELTS_REQ 0x006F
++#define HostCmd_CMD_WMM_QUEUE_CONFIG 0x0070
++#define HostCmd_CMD_WMM_GET_STATUS 0x0071
++
++#define HostCmd_CMD_802_11_TPC_CFG 0x0072
++
++#define HostCmd_CMD_802_11_FW_WAKE_METHOD 0x0074
++
++#define HostCmd_CMD_802_11_LED_CONTROL 0x004e
++
++#define HostCmd_CMD_802_11_SUBSCRIBE_EVENT 0x0075
++
++#define HostCmd_CMD_802_11_RATE_ADAPT_RATESET 0x0076
++
++#define HostCmd_CMD_802_11_TX_RATE_QUERY 0x007f
++
++#define HostCmd_CMD_802_11_POWER_ADAPT_CFG_EXT 0x007e
++
++#define HostCmd_CMD_GET_TSF 0x0080
++
++#define HostCmd_CMD_WMM_QUEUE_STATS 0x0081
++
++#define HostCmd_CMD_802_11_AUTO_TX 0x0082
++#define HostCmd_CMD_802_11_IBSS_COALESCING_STATUS 0x0083
++
++#define HostCmd_CMD_MEM_ACCESS 0x0086
++
++#define HostCmd_CMD_SDIO_GPIO_INT_CONFIG (0x0088)
++
++#ifdef MFG_CMD_SUPPORT
++#define HostCmd_CMD_MFG_COMMAND 0x0089
++#define HostCmd_RET_MFG_COMMAND 0x8089
++#endif
++
++#define HostCmd_CMD_TX_PKT_STATS 0x008d
++
++#define HostCmd_CMD_SDIO_PULL_CTRL 0x0093
++
++#define HostCmd_CMD_802_11_LDO_CONFIG 0x0096
++
++#define HostCmd_CMD_VERSION_EXT 0x0097
++
++/* For the IEEE Power Save */
++#define HostCmd_SubCmd_Enter_PS 0x0030
++#define HostCmd_SubCmd_Exit_PS 0x0031
++#define HostCmd_SubCmd_Sleep_Confirmed 0x0034
++#define HostCmd_SubCmd_Full_PowerDown 0x0035
++#define HostCmd_SubCmd_Full_PowerUp 0x0036
++
++/* Command RET code, MSB is set to 1 */
++#define HostCmd_RET_HW_SPEC_INFO 0x8003
++#define HostCmd_RET_802_11_RESET 0x8005
++#define HostCmd_RET_802_11_SCAN 0x8006
++#define HostCmd_RET_802_11_GET_LOG 0x800b
++#define HostCmd_RET_MAC_CONTROL 0x8028
++#define HostCmd_RET_MAC_MULTICAST_ADR 0x8010
++#define HostCmd_RET_802_11_DEAUTHENTICATE 0x8024
++#define HostCmd_RET_802_11_ASSOCIATE 0x8012
++#define HostCmd_RET_802_11_SET_WEP 0x8013
++#define HostCmd_RET_802_3_STAT 0x8015
++#define HostCmd_RET_802_11_SNMP_MIB 0x8016
++#define HostCmd_RET_MAC_REG_ACCESS 0x8019
++#define HostCmd_RET_BBP_REG_ACCESS 0x801a
++#define HostCmd_RET_RF_REG_ACCESS 0x801b
++#define HostCmd_RET_802_11_RADIO_CONTROL 0x801c
++#define HostCmd_RET_802_11_RF_CHANNEL 0x801d
++#define HostCmd_RET_802_11_RSSI 0x801f
++#define HostCmd_RET_802_11_RF_TX_POWER 0x801e
++#define HostCmd_RET_802_11_RF_ANTENNA 0x8020
++#define HostCmd_RET_802_11_PS_MODE 0x8021
++
++#define HostCmd_RET_802_11_AD_HOC_START 0x802B
++#define HostCmd_RET_802_11_AD_HOC_JOIN 0x802C
++
++#define HostCmd_RET_802_11_KEY_MATERIAL 0x805e
++
++#define HostCmd_ACT_SET 0x0001
++#define HostCmd_ACT_GET 0x0000
++
++#define HostCmd_RET_802_11_AD_HOC_STOP 0x8040
++
++#define HostCmd_RET_802_11_HOST_SLEEP_CFG 0x8043
++#define HostCmd_RET_802_11_WAKEUP_CONFIRM 0x8044
++#define HostCmd_RET_802_11_HOST_SLEEP_ACTIVATE 0x8045
++
++#define HostCmd_RET_802_11_MAC_ADDRESS 0x804D
++#define HostCmd_RET_802_11_EEPROM_ACCESS 0x8059
++
++#define HostCmd_RET_802_11_BAND_CONFIG 0x8058
++
++#define HostCmd_RET_802_11_SLEEP_PARAMS 0x8066
++
++#define HostCmd_RET_802_11_INACTIVITY_TIMEOUT 0x8067
++
++#define HostCmd_RET_802_11_SLEEP_PERIOD 0x8068
++#define HostCmd_RET_802_11_BCA_CONFIG_TIMESHARE 0x8069
++
++#define HostCmd_RET_802_11D_DOMAIN_INFO 0x805B
++
++#define HostCmd_RET_802_11_BG_SCAN_CONFIG 0x806b
++#define HostCmd_RET_802_11_BG_SCAN_QUERY 0x806c
++
++#define HostCmd_RET_802_11_CAL_DATA_EXT 0x806d
++
++#define HostCmd_RET_WMM_ADDTS_REQ 0x806E
++#define HostCmd_RET_WMM_DELTS_REQ 0x806F
++#define HostCmd_RET_WMM_QUEUE_CONFIG 0x8070
++#define HostCmd_RET_WMM_GET_STATUS 0x8071
++
++#define HostCmd_RET_802_11_TPC_CFG 0x8072
++
++#define HostCmd_RET_802_11_LED_CONTROL 0x804e
++
++#define HostCmd_RET_802_11_FW_WAKE_METHOD 0x8074
++
++#define HostCmd_RET_802_11_SUBSCRIBE_EVENT 0x8075
++
++#define HostCmd_RET_802_11_RATE_ADAPT_RATESET 0x8076
++
++#define HostCmd_RTE_802_11_TX_RATE_QUERY 0x807f
++
++#define HostCmd_RET_GET_TSF 0x8080
++
++#define HostCmd_RET_WMM_QUEUE_STATS 0x8081
++
++#define HostCmd_RET_802_11_POWER_ADAPT_CFG_EXT 0x807e
++
++#define HostCmd_RET_802_11_AUTO_TX 0x8082
++
++#define HostCmd_RET_802_11_IBSS_COALESCING_STATUS 0x8083
++
++#define HostCmd_RET_MEM_ACCESS 0x8086
++
++#define HostCmd_RET_SDIO_GPIO_INT_CONFIG (0x8088)
++
++#define HostCmd_RET_TX_PKT_STATS 0x808d
++
++#define HostCmd_RET_SDIO_PULL_CTRL 0x8093
++
++#define HostCmd_RET_802_11_LDO_CONFIG 0x8096
++
++#define HostCmd_RET_VERSION_EXT 0x8097
++
++/** General Result Code*/
++/* OK */
++#define HostCmd_RESULT_OK 0x0000
++/* Genenral error */
++#define HostCmd_RESULT_ERROR 0x0001
++/* Command is not valid */
++#define HostCmd_RESULT_NOT_SUPPORT 0x0002
++/* Command is pending */
++#define HostCmd_RESULT_PENDING 0x0003
++/* System is busy (command ignored) */
++#define HostCmd_RESULT_BUSY 0x0004
++/* Data buffer is not big enough */
++#define HostCmd_RESULT_PARTIAL_DATA 0x0005
++
++/* Definition of action or option for each command */
++
++/* Define general purpose action */
++#define HostCmd_ACT_GEN_READ 0x0000
++#define HostCmd_ACT_GEN_WRITE 0x0001
++#define HostCmd_ACT_GEN_GET 0x0000
++#define HostCmd_ACT_GEN_SET 0x0001
++#define HostCmd_ACT_GEN_REMOVE 0x0002
++#define HostCmd_ACT_GEN_OFF 0x0000
++#define HostCmd_ACT_GEN_ON 0x0001
++
++/* Define action or option for HostCmd_CMD_802_11_SET_WEP */
++#define HostCmd_ACT_ADD 0x0002
++#define HostCmd_ACT_REMOVE 0x0004
++
++#define HostCmd_TYPE_WEP_40_BIT 0x0001
++#define HostCmd_TYPE_WEP_104_BIT 0x0002
++
++#define HostCmd_WEP_KEY_INDEX_MASK 0x3fff
++
++/* Define action or option for HostCmd_CMD_802_11_SCAN */
++#define HostCmd_BSS_TYPE_BSS 0x0001
++#define HostCmd_BSS_TYPE_IBSS 0x0002
++#define HostCmd_BSS_TYPE_ANY 0x0003
++
++/* Define action or option for HostCmd_CMD_802_11_SCAN */
++#define HostCmd_SCAN_TYPE_ACTIVE 0x0000
++#define HostCmd_SCAN_TYPE_PASSIVE 0x0001
++
++/* Radio type definitions for the channel TLV */
++#define HostCmd_SCAN_RADIO_TYPE_BG 0
++#define HostCmd_SCAN_RADIO_TYPE_A 1
++
++/* Define action or option for HostCmd_CMD_MAC_CONTROL */
++#define HostCmd_ACT_MAC_RX_ON 0x0001
++#define HostCmd_ACT_MAC_TX_ON 0x0002
++#define HostCmd_ACT_MAC_LOOPBACK_ON 0x0004
++#define HostCmd_ACT_MAC_WEP_ENABLE 0x0008
++#define HostCmd_ACT_MAC_ETHERNETII_ENABLE 0x0010
++#define HostCmd_ACT_MAC_PROMISCUOUS_ENABLE 0x0080
++#define HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE 0x0100
++#define HostCmd_ACT_MAC_RTS_CTS_ENABLE 0x0200
++#define HostCmd_ACT_MAC_STRICT_PROTECTION_ENABLE 0x0400
++#define HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON 0x2000
++
++/* Define action or option or constant for HostCmd_CMD_MAC_MULTICAST_ADR */
++#define HostCmd_SIZE_MAC_ADR 6
++#define HostCmd_MAX_MCAST_ADRS 32
++
++#define RADIO_ON 0x01
++#define RADIO_OFF 0x00
++
++/* Define action or option for CMD_802_11_RF_CHANNEL */
++#define HostCmd_OPT_802_11_RF_CHANNEL_GET 0x00
++#define HostCmd_OPT_802_11_RF_CHANNEL_SET 0x01
++
++#define HostCmd_ACT_SET_RX 0x0001
++#define HostCmd_ACT_SET_TX 0x0002
++#define HostCmd_ACT_SET_BOTH 0x0003
++#define HostCmd_ACT_GET_RX 0x0004
++#define HostCmd_ACT_GET_TX 0x0008
++#define HostCmd_ACT_GET_BOTH 0x000c
++
++/** Card Event definition */
++#define MACREG_INT_CODE_DUMMY_HOST_WAKEUP_SIGNAL 0x00000001
++#define MACREG_INT_CODE_LINK_LOST_WITH_SCAN 0x00000002
++#define MACREG_INT_CODE_LINK_LOST 0x00000003
++#define MACREG_INT_CODE_LINK_SENSED 0x00000004
++#define MACREG_INT_CODE_MIB_CHANGED 0x00000006
++#define MACREG_INT_CODE_INIT_DONE 0x00000007
++#define MACREG_INT_CODE_DEAUTHENTICATED 0x00000008
++#define MACREG_INT_CODE_DISASSOCIATED 0x00000009
++#define MACREG_INT_CODE_PS_AWAKE 0x0000000a
++#define MACREG_INT_CODE_PS_SLEEP 0x0000000b
++#define MACREG_INT_CODE_MIC_ERR_MULTICAST 0x0000000d
++#define MACREG_INT_CODE_MIC_ERR_UNICAST 0x0000000e
++#define MACREG_INT_CODE_WM_AWAKE 0x0000000f
++#define MACREG_INT_CODE_DEEP_SLEEP_AWAKE 0x00000010
++#define MACREG_INT_CODE_ADHOC_BCN_LOST 0x00000011
++#define MACREG_INT_CODE_HOST_SLEEP_AWAKE 0x00000012
++#define MACREG_INT_CODE_WMM_STATUS_CHANGE 0x00000017
++#define MACREG_INT_CODE_BG_SCAN_REPORT 0x00000018
++#define MACREG_INT_CODE_RSSI_LOW 0x00000019
++#define MACREG_INT_CODE_SNR_LOW 0x0000001a
++#define MACREG_INT_CODE_MAX_FAIL 0x0000001b
++#define MACREG_INT_CODE_RSSI_HIGH 0x0000001c
++#define MACREG_INT_CODE_SNR_HIGH 0x0000001d
++#define MACREG_INT_CODE_IBSS_COALESCED 0x0000001e
++#define MACREG_INT_CODE_PRE_BEACON_LOST 0x00000031
++
++/* Define bitmap conditions for HOST_SLEEP_CFG */
++#define HOST_SLEEP_CFG_CANCEL 0xffffffff
++#define HOST_SLEEP_CFG_WAKEUP_THRU_INTERFACE 0xff
++#define HOST_SLEEP_CFG_GAP_FF 0xff
++
++#endif /* _HOST_H_ */
+diff --git a/drivers/net/wireless/marvell8686/hostcmd.h b/drivers/net/wireless/marvell8686/hostcmd.h
+new file mode 100644
+index 0000000..9f189bb
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/hostcmd.h
+@@ -0,0 +1,1052 @@
++/** @file hostcmd.h
++ *
++ * @brief This file contains the function prototypes, data structure
++ * and defines for all the host/station commands
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 10/11/05: Add Doxygen format comments
++ 01/11/06: Update association struct to reflect IEEE passthrough response
++ Conditionalize new scan/join structures
++ 04/10/06: Add hostcmd generic API and power_adapt_cfg_ext command
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 05/03/06: Add auto_tx hostcmd
++ 05/04/06: Add IBSS coalescing related new hostcmd
++ 08/28/06: Add LED_CTRL hostcmd
++ 08/29/06: Add ledgpio private command
++********************************************************/
++
++#ifndef __HOSTCMD__H
++#define __HOSTCMD__H
++
++/* 802.11-related definitions */
++
++/** TxPD descriptor */
++typedef struct _TxPD
++{
++ /** Current Tx packet status */
++ u32 TxStatus;
++ /** Tx Control */
++ u32 TxControl;
++ u32 TxPacketLocation;
++ /** Tx packet length */
++ u16 TxPacketLength;
++ /**Destination MAC address */
++ u8 TxDestAddr[MRVDRV_ETH_ADDR_LEN];
++ /** Pkt Priority */
++ u8 Priority;
++ /** Trasnit Pkt Flags*/
++ u8 Flags;
++ /** Amount of time the packet has been queued in the driver (units = 2ms)*/
++ u8 PktDelay_2ms;
++ /** Reserved */
++ u8 Reserved1;
++
++} __ATTRIB_PACK__ TxPD, *PTxPD;
++
++/** RxPD Descriptor */
++typedef struct _RxPD
++{
++ /** Current Rx packet status */
++ u16 RxStatus;
++
++ /** SNR */
++ u8 SNR;
++
++ /** Tx Control */
++ u8 RxControl;
++
++ /** Pkt Length */
++ u16 PktLen;
++
++ /** Noise Floor */
++ u8 NF;
++
++ /** Rx Packet Rate */
++ u8 RxRate;
++
++ /** Pkt offset */
++ u32 PktOffset;
++ u8 RxPacketType;
++ u8 Reserved_1[3];
++ /** Pkt Priority */
++ u8 Priority;
++ u8 Reserved[3];
++
++} __ATTRIB_PACK__ RxPD, *PRxPD;
++
++#if defined(__KERNEL__)
++
++/** CmdCtrlNode */
++typedef struct _CmdCtrlNode
++{
++ /* CMD link list */
++ struct list_head list;
++
++ u32 Status;
++
++ /* CMD ID */
++ WLAN_OID cmd_oid;
++
++ /*CMD wait option: wait for finish or no wait */
++ u16 wait_option;
++
++ /* command parameter */
++ void *pdata_buf;
++
++ /*command data */
++ u8 *BufVirtualAddr;
++
++ u16 CmdFlags;
++
++ /* wait queue */
++ u16 CmdWaitQWoken;
++ wait_queue_head_t cmdwait_q __ATTRIB_ALIGN__;
++} __ATTRIB_PACK__ CmdCtrlNode, *PCmdCtrlNode;
++
++#endif
++
++/** MRVL_WEP_KEY */
++typedef struct _MRVL_WEP_KEY
++{
++ u32 Length;
++ u32 KeyIndex;
++ u32 KeyLength;
++ u8 KeyMaterial[MRVL_KEY_BUFFER_SIZE_IN_BYTE];
++} __ATTRIB_PACK__ MRVL_WEP_KEY, *PMRVL_WEP_KEY;
++
++typedef ULONGLONG WLAN_802_11_KEY_RSC;
++
++/** WLAN_802_11_KEY */
++typedef struct _WLAN_802_11_KEY
++{
++ u32 Length;
++ u32 KeyIndex;
++ u32 KeyLength;
++ WLAN_802_11_MAC_ADDRESS BSSID;
++ WLAN_802_11_KEY_RSC KeyRSC;
++ u8 KeyMaterial[MRVL_MAX_KEY_WPA_KEY_LENGTH];
++} __ATTRIB_PACK__ WLAN_802_11_KEY;
++
++/** MRVL_WPA_KEY */
++typedef struct _MRVL_WPA_KEY
++{
++ u32 KeyIndex;
++ u32 KeyLength;
++ u32 KeyRSC;
++ u8 KeyMaterial[MRVL_MAX_KEY_WPA_KEY_LENGTH];
++} MRVL_WPA_KEY, *PMRVL_WPA_KEY;
++
++/** MRVL_WLAN_WPA_KEY */
++typedef struct _MRVL_WLAN_WPA_KEY
++{
++ u8 EncryptionKey[16];
++ u8 MICKey1[8];
++ u8 MICKey2[8];
++} MRVL_WLAN_WPA_KEY, *PMRVL_WLAN_WPA_KEY;
++
++/* Received Signal Strength Indication in dBm*/
++typedef LONG WLAN_802_11_RSSI;
++
++/** WLAN_802_11_WEP */
++typedef struct _WLAN_802_11_WEP
++{
++ /* Length of this structure */
++ u32 Length;
++
++ /* 0 is the per-client key, 1-N are the global keys */
++ u32 KeyIndex;
++
++ /* length of key in bytes */
++ u32 KeyLength;
++
++ /* variable length depending on above field */
++ u8 KeyMaterial[1];
++} __ATTRIB_PACK__ WLAN_802_11_WEP;
++
++/** WLAN_802_11_SSID */
++typedef struct _WLAN_802_11_SSID
++{
++ /* SSID Length */
++ u32 SsidLength;
++
++ /* SSID information field */
++ u8 Ssid[WLAN_MAX_SSID_LENGTH];
++} __ATTRIB_PACK__ WLAN_802_11_SSID;
++
++typedef u32 WLAN_802_11_FRAGMENTATION_THRESHOLD;
++typedef u32 WLAN_802_11_RTS_THRESHOLD;
++typedef u32 WLAN_802_11_ANTENNA;
++
++/** wlan_offset_value */
++typedef struct _wlan_offset_value
++{
++ u32 offset;
++ u32 value;
++} wlan_offset_value;
++
++/** WLAN_802_11_FIXED_IEs */
++typedef struct _WLAN_802_11_FIXED_IEs
++{
++ u8 Timestamp[8];
++ u16 BeaconInterval;
++ u16 Capabilities;
++} WLAN_802_11_FIXED_IEs;
++
++/** WLAN_802_11_VARIABLE_IEs */
++typedef struct _WLAN_802_11_VARIABLE_IEs
++{
++ u8 ElementID;
++ u8 Length;
++ u8 data[1];
++} WLAN_802_11_VARIABLE_IEs;
++
++/** WLAN_802_11_AI_RESFI */
++typedef struct _WLAN_802_11_AI_RESFI
++{
++ u16 Capabilities;
++ u16 StatusCode;
++ u16 AssociationId;
++} WLAN_802_11_AI_RESFI;
++
++/** WLAN_802_11_AI_REQFI */
++typedef struct _WLAN_802_11_AI_REQFI
++{
++ u16 Capabilities;
++ u16 ListenInterval;
++ WLAN_802_11_MAC_ADDRESS CurrentAPAddress;
++} WLAN_802_11_AI_REQFI;
++
++/* Define general data structure */
++/** HostCmd_DS_GEN */
++typedef struct _HostCmd_DS_GEN
++{
++ u16 Command;
++ u16 Size;
++ u16 SeqNum;
++ u16 Result;
++} __ATTRIB_PACK__ HostCmd_DS_GEN, HostCmd_DS_802_11_DEEP_SLEEP;
++
++#define S_DS_GEN sizeof(HostCmd_DS_GEN)
++/*
++ * Define data structure for HostCmd_CMD_GET_HW_SPEC
++ * This structure defines the response for the GET_HW_SPEC command
++ */
++/** HostCmd_DS_GET_HW_SPEC */
++typedef struct _HostCmd_DS_GET_HW_SPEC
++{
++ /* HW Interface version number */
++ u16 HWIfVersion;
++
++ /* HW version number */
++ u16 Version;
++
++ /* Max number of TxPD FW can handle */
++ u16 NumOfTxPD;
++
++ /* Max no of Multicast address */
++ u16 NumOfMCastAdr;
++
++ /* MAC address */
++ u8 PermanentAddr[6];
++
++ /* Region Code */
++ u16 RegionCode;
++
++ /* Number of antenna used */
++ u16 NumberOfAntenna;
++
++ /* FW release number, example 0x1234=1.2.3.4 */
++ u32 FWReleaseNumber;
++
++ u32 Reserved_1;
++
++ u32 Reserved_2;
++
++ u32 Reserved_3;
++
++ /*FW/HW Capability */
++ u32 fwCapInfo;
++} __ATTRIB_PACK__ HostCmd_DS_GET_HW_SPEC;
++
++typedef struct _HostCmd_DS_802_11_SUBSCRIBE_EVENT
++{
++ u16 Action;
++ u16 Events;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_SUBSCRIBE_EVENT;
++
++/*
++ * This scan handle Country Information IE(802.11d compliant)
++ * Define data structure for HostCmd_CMD_802_11_SCAN
++ */
++/** HostCmd_DS_802_11_SCAN */
++typedef struct _HostCmd_DS_802_11_SCAN
++{
++ u8 BSSType;
++ u8 BSSID[ETH_ALEN];
++ u8 TlvBuffer[1];
++ /* MrvlIEtypes_SsIdParamSet_t SsIdParamSet;
++ * MrvlIEtypes_ChanListParamSet_t ChanListParamSet;
++ * MrvlIEtypes_RatesParamSet_t OpRateSet;
++ * */
++} __ATTRIB_PACK__ HostCmd_DS_802_11_SCAN;
++
++typedef struct _HostCmd_DS_802_11_SCAN_RSP
++{
++ u16 BSSDescriptSize;
++ u8 NumberOfSets;
++ u8 BssDescAndTlvBuffer[1];
++
++} __ATTRIB_PACK__ HostCmd_DS_802_11_SCAN_RSP;
++
++/** HostCmd_CMD_802_11_GET_LOG */
++typedef struct _HostCmd_DS_802_11_GET_LOG
++{
++ u32 mcasttxframe;
++ u32 failed;
++ u32 retry;
++ u32 multiretry;
++ u32 framedup;
++ u32 rtssuccess;
++ u32 rtsfailure;
++ u32 ackfailure;
++ u32 rxfrag;
++ u32 mcastrxframe;
++ u32 fcserror;
++ u32 txframe;
++ u32 reserved;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_GET_LOG;
++
++/** HostCmd_CMD_MAC_CONTROL */
++typedef struct _HostCmd_DS_MAC_CONTROL
++{
++ u16 Action;
++ u16 Reserved;
++} __ATTRIB_PACK__ HostCmd_DS_MAC_CONTROL;
++
++/** HostCmd_CMD_MAC_MULTICAST_ADR */
++typedef struct _HostCmd_DS_MAC_MULTICAST_ADR
++{
++ u16 Action;
++ u16 NumOfAdrs;
++ u8 MACList[MRVDRV_ETH_ADDR_LEN * MRVDRV_MAX_MULTICAST_LIST_SIZE];
++} __ATTRIB_PACK__ HostCmd_DS_MAC_MULTICAST_ADR;
++
++/** HostCmd_CMD_802_11_DEAUTHENTICATE */
++typedef struct _HostCmd_DS_802_11_DEAUTHENTICATE
++{
++ u8 MacAddr[6];
++ u16 ReasonCode;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_DEAUTHENTICATE;
++
++/** HostCmd_DS_802_11_ASSOCIATE */
++typedef struct _HostCmd_DS_802_11_ASSOCIATE
++{
++ u8 PeerStaAddr[6];
++ IEEEtypes_CapInfo_t CapInfo;
++ u16 ListenInterval;
++ u8 Reserved1[3];
++
++ /*
++ * MrvlIEtypes_SsIdParamSet_t SsIdParamSet;
++ * MrvlIEtypes_PhyParamSet_t PhyParamSet;
++ * MrvlIEtypes_SsParamSet_t SsParamSet;
++ * MrvlIEtypes_RatesParamSet_t RatesParamSet;
++ */
++} __ATTRIB_PACK__ HostCmd_DS_802_11_ASSOCIATE;
++
++/** HostCmd_RET_802_11_ASSOCIATE */
++typedef struct
++{
++ IEEEtypes_AssocRsp_t assocRsp;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_ASSOCIATE_RSP;
++
++/** HostCmd_RET_802_11_AD_HOC_JOIN */
++typedef struct _HostCmd_DS_802_11_AD_HOC_RESULT
++{
++ u8 PAD[3];
++ u8 BSSID[MRVDRV_ETH_ADDR_LEN];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_AD_HOC_RESULT;
++
++/** HostCmd_CMD_802_11_SET_WEP */
++typedef struct _HostCmd_DS_802_11_SET_WEP
++{
++ /* ACT_ADD, ACT_REMOVE or ACT_ENABLE */
++ u16 Action;
++
++ /* Key Index selected for Tx */
++ u16 KeyIndex;
++
++ /* 40, 128bit or TXWEP */
++ u8 WEPTypeForKey1;
++
++ u8 WEPTypeForKey2;
++ u8 WEPTypeForKey3;
++ u8 WEPTypeForKey4;
++ u8 WEP1[16];
++ u8 WEP2[16];
++ u8 WEP3[16];
++ u8 WEP4[16];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_SET_WEP;
++
++/** HostCmd_DS_802_11_AD_HOC_STOP */
++typedef struct _HostCmd_DS_802_11_AD_HOC_STOP
++{
++
++} __ATTRIB_PACK__ HostCmd_DS_802_11_AD_HOC_STOP;
++
++/** HostCmd_CMD_802_11_SNMP_MIB */
++typedef struct _HostCmd_DS_802_11_SNMP_MIB
++{
++ u16 QueryType;
++ u16 OID;
++ u16 BufSize;
++ u8 Value[128];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_SNMP_MIB;
++
++/** HostCmd_CMD_MAC_REG_ACCESS */
++typedef struct _HostCmd_DS_MAC_REG_ACCESS
++{
++ u16 Action;
++ u16 Offset;
++ u32 Value;
++} __ATTRIB_PACK__ HostCmd_DS_MAC_REG_ACCESS;
++
++/** HostCmd_CMD_BBP_REG_ACCESS */
++typedef struct _HostCmd_DS_BBP_REG_ACCESS
++{
++ u16 Action;
++ u16 Offset;
++ u8 Value;
++ u8 Reserved[3];
++} __ATTRIB_PACK__ HostCmd_DS_BBP_REG_ACCESS;
++
++/** HostCmd_CMD_RF_REG_ACCESS */
++typedef struct _HostCmd_DS_RF_REG_ACCESS
++{
++ u16 Action;
++ u16 Offset;
++ u8 Value;
++ u8 Reserved[3];
++} __ATTRIB_PACK__ HostCmd_DS_RF_REG_ACCESS;
++
++/** HostCmd_CMD_802_11_RADIO_CONTROL */
++typedef struct _HostCmd_DS_802_11_RADIO_CONTROL
++{
++ u16 Action;
++ u16 Control;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_RADIO_CONTROL;
++
++/* HostCmd_DS_802_11_SLEEP_PARAMS */
++typedef struct _HostCmd_DS_802_11_SLEEP_PARAMS
++{
++ /* ACT_GET/ACT_SET */
++ u16 Action;
++
++ /* Sleep clock error in ppm */
++ u16 Error;
++
++ /* Wakeup offset in usec */
++ u16 Offset;
++
++ /* Clock stabilization time in usec */
++ u16 StableTime;
++
++ /* Control periodic calibration */
++ u8 CalControl;
++
++ /* Control the use of external sleep clock */
++ u8 ExternalSleepClk;
++
++ /* Reserved field, should be set to zero */
++ u16 Reserved;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_SLEEP_PARAMS;
++
++/* HostCmd_DS_802_11_SLEEP_PERIOD */
++typedef struct _HostCmd_DS_802_11_SLEEP_PERIOD
++{
++ /* ACT_GET/ACT_SET */
++ u16 Action;
++
++ /* Sleep Period in msec */
++ u16 Period;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_SLEEP_PERIOD;
++
++/* HostCmd_DS_802_11_BCA_TIMESHARE */
++typedef struct _HostCmd_DS_802_11_BCA_TIMESHARE
++{
++ /* ACT_GET/ACT_SET */
++ u16 Action;
++
++ /* Type: WLAN, BT */
++ u16 TrafficType;
++
++ /* 20msec - 60000msec */
++ u32 TimeShareInterval;
++
++ /* PTA arbiter time in msec */
++ u32 BTTime;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_BCA_TIMESHARE;
++
++/* HostCmd_DS_802_11_INACTIVITY_TIMEOUT */
++typedef struct _HostCmd_DS_802_11_INACTIVITY_TIMEOUT
++{
++ /* ACT_GET/ACT_SET */
++ u16 Action;
++
++ /* Inactivity timeout in msec */
++ u16 Timeout;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_INACTIVITY_TIMEOUT;
++
++/** HostCmd_CMD_802_11_RF_CHANNEL */
++typedef struct _HostCmd_DS_802_11_RF_CHANNEL
++{
++ u16 Action;
++ u16 CurrentChannel;
++ u16 RFType;
++ u16 Reserved;
++ u8 ChannelList[32];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_RF_CHANNEL;
++
++/** HostCmd_CMD_802_11_RSSI */
++typedef struct _HostCmd_DS_802_11_RSSI
++{
++ /* weighting factor */
++ u16 N;
++
++ u16 Reserved_0;
++ u16 Reserved_1;
++ u16 Reserved_2;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_RSSI;
++
++/** HostCmd_DS_802_11_RSSI_RSP */
++typedef struct _HostCmd_DS_802_11_RSSI_RSP
++{
++ u16 SNR;
++ u16 NoiseFloor;
++ u16 AvgSNR;
++ u16 AvgNoiseFloor;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_RSSI_RSP;
++
++/** HostCmd_DS_802_11_MAC_ADDRESS */
++typedef struct _HostCmd_DS_802_11_MAC_ADDRESS
++{
++ u16 Action;
++ u8 MacAdd[ETH_ALEN];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_MAC_ADDRESS;
++
++/** HostCmd_CMD_802_11_RF_TX_POWER */
++typedef struct _HostCmd_DS_802_11_RF_TX_POWER
++{
++ u16 Action;
++ u16 CurrentLevel;
++ u8 MaxPower;
++ u8 MinPower;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_RF_TX_POWER;
++
++/** HostCmd_CMD_802_11_RF_ANTENNA */
++typedef struct _HostCmd_DS_802_11_RF_ANTENNA
++{
++ u16 Action;
++
++ /* Number of antennas or 0xffff(diversity) */
++ u16 AntennaMode;
++
++} __ATTRIB_PACK__ HostCmd_DS_802_11_RF_ANTENNA;
++
++/** HostCmd_CMD_802_11_PS_MODE */
++typedef struct _HostCmd_DS_802_11_PS_MODE
++{
++ u16 Action;
++ u16 NullPktInterval;
++ u16 MultipleDtim;
++ u16 BCNMissTimeOut;
++ u16 LocalListenInterval;
++ u16 AdhocAwakePeriod;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_PS_MODE;
++
++/** PS_CMD_ConfirmSleep */
++typedef struct _PS_CMD_ConfirmSleep
++{
++ u16 Command;
++ u16 Size;
++ u16 SeqNum;
++ u16 Result;
++
++ u16 Action;
++ u16 Reserved1;
++ u16 MultipleDtim;
++ u16 Reserved;
++ u16 LocalListenInterval;
++} __ATTRIB_PACK__ PS_CMD_ConfirmSleep, *PPS_CMD_ConfirmSleep;
++
++/** HostCmd_CMD_802_11_FW_WAKE_METHOD */
++typedef struct _HostCmd_DS_802_11_FW_WAKEUP_METHOD
++{
++ u16 Action;
++ u16 Method;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_FW_WAKEUP_METHOD;
++
++/** HostCmd_DS_802_11_RATE_ADAPT_RATESET */
++typedef struct _HostCmd_DS_802_11_RATE_ADAPT_RATESET
++{
++ u16 Action;
++ u16 HWRateDropMode;
++ u16 Bitmap;
++ u16 Threshold;
++ u16 FinalRate;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_RATE_ADAPT_RATESET;
++
++/** HostCmd_DS_802_11_AD_HOC_START*/
++typedef struct _HostCmd_DS_802_11_AD_HOC_START
++{
++ u8 SSID[MRVDRV_MAX_SSID_LENGTH];
++ u8 BSSType;
++ u16 BeaconPeriod;
++ u8 DTIMPeriod;
++ IEEEtypes_SsParamSet_t SsParamSet;
++ IEEEtypes_PhyParamSet_t PhyParamSet;
++ u16 Reserved1;
++ IEEEtypes_CapInfo_t Cap;
++ u8 DataRate[HOSTCMD_SUPPORTED_RATES];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_AD_HOC_START;
++
++/** AdHoc_BssDesc_t */
++typedef struct _AdHoc_BssDesc_t
++{
++ u8 BSSID[6];
++ u8 SSID[32];
++ u8 BSSType;
++ u16 BeaconPeriod;
++ u8 DTIMPeriod;
++ u8 TimeStamp[8];
++ u8 LocalTime[8];
++ IEEEtypes_PhyParamSet_t PhyParamSet;
++ IEEEtypes_SsParamSet_t SsParamSet;
++ IEEEtypes_CapInfo_t Cap;
++ u8 DataRates[HOSTCMD_SUPPORTED_RATES];
++
++ /* DO NOT ADD ANY FIELDS TO THIS STRUCTURE. It is used below in the
++ * Adhoc join command and will cause a binary layout mismatch with
++ * the firmware
++ */
++} __ATTRIB_PACK__ AdHoc_BssDesc_t;
++
++/** HostCmd_DS_802_11_AD_HOC_JOIN */
++typedef struct _HostCmd_DS_802_11_AD_HOC_JOIN
++{
++ AdHoc_BssDesc_t BssDescriptor;
++ u16 Reserved1;
++ u16 Reserved2;
++
++} __ATTRIB_PACK__ HostCmd_DS_802_11_AD_HOC_JOIN;
++
++typedef union _KeyInfo_WEP_t
++{
++ u8 Reserved;
++
++ /* bits 1-4: Specifies the index of key */
++ u8 WepKeyIndex;
++
++ /* bit 0: Specifies that this key is
++ * to be used as the default for TX data packets
++ * */
++ u8 isWepDefaultKey;
++} __ATTRIB_PACK__ KeyInfo_WEP_t;
++
++typedef union _KeyInfo_TKIP_t
++{
++ u8 Reserved;
++
++ /* bit 2: Specifies that this key is
++ * enabled and valid to use */
++ u8 isKeyEnabled;
++
++ /* bit 1: Specifies that this key is
++ * to be used as the unicast key */
++ u8 isUnicastKey;
++
++ /* bit 0: Specifies that this key is
++ * to be used as the multicast key */
++ u8 isMulticastKey;
++} __ATTRIB_PACK__ KeyInfo_TKIP_t;
++
++typedef union _KeyInfo_AES_t
++{
++ u8 Reserved;
++
++ /* bit 2: Specifies that this key is
++ * enabled and valid to use */
++ u8 isKeyEnabled;
++
++ /* bit 1: Specifies that this key is
++ * to be used as the unicast key */
++ u8 isUnicastKey;
++
++ /* bit 0: Specifies that this key is
++ * to be used as the multicast key */
++ u8 isMulticastKey;
++} __ATTRIB_PACK__ KeyInfo_AES_t;
++
++/** KeyMaterial_TKIP_t */
++typedef struct _KeyMaterial_TKIP_t
++{
++ /* TKIP encryption/decryption key */
++ u8 TkipKey[16];
++
++ /* TKIP TX MIC Key */
++ u8 TkipTxMicKey[16];
++
++ /* TKIP RX MIC Key */
++ u8 TkipRxMicKey[16];
++} __ATTRIB_PACK__ KeyMaterial_TKIP_t, *PKeyMaterial_TKIP_t;
++
++/** KeyMaterial_AES_t */
++typedef struct _KeyMaterial_AES_t
++{
++ /* AES encryption/decryption key */
++ u8 AesKey[16];
++} __ATTRIB_PACK__ KeyMaterial_AES_t, *PKeyMaterial_AES_t;
++
++/** MrvlIEtype_KeyParamSet_t */
++typedef struct _MrvlIEtype_KeyParamSet_t
++{
++ /* Type ID */
++ u16 Type;
++
++ /* Length of Payload */
++ u16 Length;
++
++ /* Type of Key: WEP=0, TKIP=1, AES=2 */
++ u16 KeyTypeId;
++
++ /* Key Control Info specific to a KeyTypeId */
++ u16 KeyInfo;
++
++ /* Length of key */
++ u16 KeyLen;
++
++ /* Key material of size KeyLen */
++ u8 Key[32];
++} __ATTRIB_PACK__ MrvlIEtype_KeyParamSet_t, *PMrvlIEtype_KeyParamSet_t;
++
++/** HostCmd_DS_802_11_KEY_MATERIAL */
++typedef struct _HostCmd_DS_802_11_KEY_MATERIAL
++{
++ u16 Action;
++
++ MrvlIEtype_KeyParamSet_t KeyParamSet;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_KEY_MATERIAL;
++
++/** HostCmd_DS_802_11_HOST_SLEEP_CFG */
++typedef struct _HostCmd_DS_HOST_802_11_HOST_SLEEP_CFG
++{
++ /* bit0=1: non-unicast data
++ * bit1=1: unicast data
++ * bit2=1: mac events
++ * bit3=1: magic packet
++ */
++ u32 conditions;
++
++ u8 gpio;
++
++ /* in milliseconds */
++ u8 gap;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_HOST_SLEEP_CFG;
++
++#define CAL_DATA_HEADER_LEN 6 /* sizeof(HostCmd_DS_802_11_CAL_DATA_EXT)-sizeof(CalData) */
++
++/** HostCmd_DS_802_11_CAL_DATA_EXT */
++typedef struct _HostCmd_DS_802_11_CAL_DATA_EXT
++{
++ u16 Action;
++ u16 Revision;
++ u16 CalDataLen;
++ u8 CalData[1];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_CAL_DATA_EXT;
++
++/** HostCmd_DS_802_11_EEPROM_ACCESS */
++typedef struct _HostCmd_DS_802_11_EEPROM_ACCESS
++{
++ u16 Action;
++
++ /* multiple 4 */
++ u16 Offset;
++ u16 ByteCount;
++ u8 Value;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_EEPROM_ACCESS;
++
++/** HostCmd_DS_802_11_BG_SCAN_CONFIG */
++typedef struct _HostCmd_DS_802_11_BG_SCAN_CONFIG
++{
++ /** Action */
++ u16 Action;
++
++ /**
++ * Enable/Disable
++ * 0 - Disable
++ * 1 - Enable
++ */
++ u8 Enable;
++
++ /**
++ * bssType
++ * 1 - Infrastructure
++ * 2 - IBSS
++ * 3 - any
++ */
++ u8 BssType;
++
++ /**
++ * ChannelsPerScan
++ * Number of channels to scan during a single scanning opportunity
++ */
++ u8 ChannelsPerScan;
++
++ u8 Reserved1[3];
++
++ /** ScanInterval */
++ u32 ScanInterval;
++
++ /**
++ * StoreCondition
++ * - SSID Match
++ * - SSID Match & Exceed SNR Threshold
++ */
++ u32 StoreCondition;
++
++ /**
++ * ReportConditions
++ * - SSID Match
++ * - SSID Match & Exceed SNR Threshold
++ */
++ u32 ReportConditions;
++
++ u16 Reserved2;
++
++ /* Attach TLV based parameters as needed:
++ *
++ * MrvlIEtypes_SsIdParamSet_t Set specific SSID filter
++ * MrvlIEtypes_ChanListParamSet_t Set the channels & channel params
++ * MrvlIEtypes_NumProbes_t Number of probes per SSID/broadcast
++ * MrvlIEtypes_WildCardSsIdParamSet_t Wildcard SSID matching patterns
++ * MrvlIEtypes_SnrThreshold_t SNR Threshold for match/report
++ */
++
++} __ATTRIB_PACK__ HostCmd_DS_802_11_BG_SCAN_CONFIG;
++
++/** HostCmd_DS_802_11_BG_SCAN_QUERY */
++typedef struct _HostCmd_DS_802_11_BG_SCAN_QUERY
++{
++ u8 Flush;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_BG_SCAN_QUERY;
++
++/** HostCmd_DS_802_11_BG_SCAN_QUERY_RSP */
++typedef struct _HostCmd_DS_802_11_BG_SCAN_QUERY_RSP
++{
++ u32 ReportCondition;
++ HostCmd_DS_802_11_SCAN_RSP scanresp;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_BG_SCAN_QUERY_RSP;
++
++/** HostCmd_DS_802_11_TPC_CFG */
++typedef struct _HostCmd_DS_802_11_TPC_CFG
++{
++ u16 Action;
++ u8 Enable;
++ s8 P0;
++ s8 P1;
++ s8 P2;
++ u8 UseSNR;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_TPC_CFG;
++
++/** HostCmd_DS_802_11_LED_CTRL */
++typedef struct _HostCmd_DS_802_11_LED_CTRL
++{
++ u16 Action; /* 0 = ACT_GET; 1 = ACT_SET; */
++ u16 LedNums; /* Numbers of LEDs supported */
++ MrvlIEtypes_LedGpio_t LedGpio;
++ MrvlIEtypes_LedBehavior_t LedBehavior[1];
++} __ATTRIB_PACK__ HostCmd_DS_802_11_LED_CTRL;
++
++/** HostCmd_DS_802_11_POWER_ADAPT_CFG_EXT */
++typedef struct _HostCmd_DS_802_11_POWER_ADAPT_CFG_EXT
++{
++ /** Action */
++ u16 Action; /* 0 = ACT_GET; 1 = ACT_SET; */
++ u16 EnablePA; /* 0 = disable; 1 = enable; */
++ MrvlIEtypes_PowerAdapt_Group_t PowerAdaptGroup;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_POWER_ADAPT_CFG_EXT;
++
++typedef struct _HostCmd_DS_SDIO_INT_CONFIG
++{
++ u16 Action; /* 0: get; 1: set */
++ u16 Gpio_pin;
++ u16 Gpio_int_edge; /*1: failing edge; 0: rasing edge */
++ u16 Gpio_pulse_width; /* in usec units */
++} __ATTRIB_PACK__ HostCmd_DS_SDIO_INT_CONFIG;
++
++typedef struct _HostCmd_DS_SDIO_PULL_CTRL
++{
++ u16 Action; /* 0: get; 1: set */
++ u16 PullUp; /* the delay of pulling up in us */
++ u16 PullDown; /* the delay of pulling down in us */
++} __ATTRIB_PACK__ HostCmd_DS_SDIO_PULL_CTRL;
++typedef struct _HostCmd_DS_802_11_IBSS_Status
++{
++ u16 Action;
++ u16 Enable;
++ u8 BSSID[ETH_ALEN];
++ u16 BeaconInterval;
++ u16 ATIMWindow;
++ u16 UseGRateProtection;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_IBSS_Status;
++
++typedef struct _HostCmd_TX_RATE_QUERY
++{
++ u16 TxRate;
++} __ATTRIB_PACK__ HostCmd_TX_RATE_QUERY;
++
++/** HostCmd_DS_802_11_AUTO_TX */
++typedef struct _HostCmd_DS_802_11_AUTO_TX
++{
++ /** Action */
++ u16 Action; /* 0 = ACT_GET; 1 = ACT_SET; */
++ MrvlIEtypes_AutoTx_t AutoTx;
++} __ATTRIB_PACK__ HostCmd_DS_802_11_AUTO_TX;
++
++/** HostCmd_MEM_ACCESS */
++typedef struct _HostCmd_DS_MEM_ACCESS
++{
++ /** Action */
++ u16 Action; /* 0 = ACT_GET; 1 = ACT_SET; */
++ u16 Reserved;
++ u32 Addr;
++ u32 Value;
++} __ATTRIB_PACK__ HostCmd_DS_MEM_ACCESS;
++
++typedef struct
++{
++ u64 TsfValue;
++} __ATTRIB_PACK__ HostCmd_DS_GET_TSF;
++
++#define LDO_INTERNAL 0
++#define LDO_EXTERNAL 1
++
++typedef struct _HostCmd_DS_802_11_LDO_CONFIG
++{
++ u16 Action; /* 0 = ACT_GET; 1 = ACT_SET; */
++ u16 PMSource; /* 0 = LDO_INTERNAL; 1 = LDO_EXTERNAL */
++} __ATTRIB_PACK__ HostCmd_DS_802_11_LDO_CONFIG;
++
++typedef struct _HostCmd_DS_VERSION_EXT
++{
++ u8 versionStrSel;
++ char versionStr[128];
++} __ATTRIB_PACK__ HostCmd_DS_VERSION_EXT;
++
++/** Define data structure for HostCmd_CMD_802_11D_DOMAIN_INFO */
++typedef struct _HostCmd_DS_802_11D_DOMAIN_INFO
++{
++ u16 Action;
++ MrvlIEtypes_DomainParamSet_t Domain;
++} __ATTRIB_PACK__ HostCmd_DS_802_11D_DOMAIN_INFO;
++
++/** Define data structure for HostCmd_RET_802_11D_DOMAIN_INFO */
++typedef struct _HostCmd_DS_802_11D_DOMAIN_INFO_RSP
++{
++ u16 Action;
++ MrvlIEtypes_DomainParamSet_t Domain;
++} __ATTRIB_PACK__ HostCmd_DS_802_11D_DOMAIN_INFO_RSP;
++
++typedef struct
++{
++ u32 PktInitCnt;
++ u32 PktSuccessCnt;
++ u32 TxAttempts;
++ u32 RetryFailure;
++ u32 ExpiryFailure;
++} __ATTRIB_PACK__ HostCmd_DS_TX_PKT_STAT_Entry;
++
++typedef struct
++{
++ HostCmd_DS_TX_PKT_STAT_Entry StatEntry[HOSTCMD_SUPPORTED_RATES];
++} __ATTRIB_PACK__ HostCmd_DS_TX_PKT_STATS;
++
++/** _HostCmd_DS_COMMAND*/
++struct _HostCmd_DS_COMMAND
++{
++
++ /** Command Header */
++ u16 Command;
++ u16 Size;
++ u16 SeqNum;
++ u16 Result;
++
++ /** Command Body */
++ union
++ {
++ HostCmd_DS_GET_HW_SPEC hwspec;
++ HostCmd_DS_802_11_PS_MODE psmode;
++ HostCmd_DS_802_11_SCAN scan;
++ HostCmd_DS_802_11_SCAN_RSP scanresp;
++ HostCmd_DS_MAC_CONTROL macctrl;
++ HostCmd_DS_802_11_ASSOCIATE associate;
++ HostCmd_DS_802_11_ASSOCIATE_RSP associatersp;
++ HostCmd_DS_802_11_DEAUTHENTICATE deauth;
++ HostCmd_DS_802_11_SET_WEP wep;
++ HostCmd_DS_802_11_AD_HOC_START ads;
++ HostCmd_DS_802_11_AD_HOC_RESULT result;
++ HostCmd_DS_802_11_GET_LOG glog;
++ HostCmd_DS_802_11_SNMP_MIB smib;
++ HostCmd_DS_802_11_RF_TX_POWER txp;
++ HostCmd_DS_802_11_RF_ANTENNA rant;
++ HostCmd_DS_802_11_RATE_ADAPT_RATESET rateset;
++ HostCmd_DS_MAC_MULTICAST_ADR madr;
++ HostCmd_DS_802_11_AD_HOC_JOIN adj;
++ HostCmd_DS_802_11_RADIO_CONTROL radio;
++ HostCmd_DS_802_11_RF_CHANNEL rfchannel;
++ HostCmd_DS_802_11_RSSI rssi;
++ HostCmd_DS_802_11_RSSI_RSP rssirsp;
++ HostCmd_DS_802_11_AD_HOC_STOP adhoc_stop;
++ HostCmd_DS_802_11_MAC_ADDRESS macadd;
++ HostCmd_DS_802_11_KEY_MATERIAL keymaterial;
++ HostCmd_DS_MAC_REG_ACCESS macreg;
++ HostCmd_DS_BBP_REG_ACCESS bbpreg;
++ HostCmd_DS_RF_REG_ACCESS rfreg;
++ HostCmd_DS_802_11_CAL_DATA_EXT caldataext;
++ HostCmd_DS_802_11_HOST_SLEEP_CFG hostsleepcfg;
++ HostCmd_DS_802_11_EEPROM_ACCESS rdeeprom;
++
++ HostCmd_DS_802_11D_DOMAIN_INFO domaininfo;
++ HostCmd_DS_802_11D_DOMAIN_INFO_RSP domaininforesp;
++ HostCmd_DS_802_11_BG_SCAN_CONFIG bgscancfg;
++ HostCmd_DS_802_11_BG_SCAN_QUERY bgscanquery;
++ HostCmd_DS_802_11_BG_SCAN_QUERY_RSP bgscanqueryresp;
++ HostCmd_DS_WMM_GET_STATUS getWmmStatus;
++ HostCmd_DS_WMM_ADDTS_REQ addTsReq;
++ HostCmd_DS_WMM_DELTS_REQ delTsReq;
++ HostCmd_DS_WMM_QUEUE_CONFIG queueConfig;
++ HostCmd_DS_WMM_QUEUE_STATS queueStats;
++ HostCmd_DS_TX_PKT_STATS txPktStats;
++ HostCmd_DS_802_11_SLEEP_PARAMS sleep_params;
++ HostCmd_DS_802_11_BCA_TIMESHARE bca_timeshare;
++ HostCmd_DS_802_11_INACTIVITY_TIMEOUT inactivity_timeout;
++ HostCmd_DS_802_11_SLEEP_PERIOD ps_sleeppd;
++ HostCmd_DS_802_11_TPC_CFG tpccfg;
++ HostCmd_DS_802_11_LED_CTRL ledgpio;
++ HostCmd_DS_802_11_FW_WAKEUP_METHOD fwwakeupmethod;
++
++ HostCmd_TX_RATE_QUERY txrate;
++ HostCmd_DS_GET_TSF gettsf;
++ HostCmd_DS_802_11_IBSS_Status ibssCoalescing;
++ HostCmd_DS_SDIO_INT_CONFIG sdio_int;
++ HostCmd_DS_SDIO_PULL_CTRL sdiopullctl;
++ HostCmd_DS_802_11_LDO_CONFIG ldocfg;
++ HostCmd_DS_VERSION_EXT verext;
++ } params;
++} __ATTRIB_PACK__;
++
++#endif
+diff --git a/drivers/net/wireless/marvell8686/if_sdio.c b/drivers/net/wireless/marvell8686/if_sdio.c
+new file mode 100644
+index 0000000..2384e05
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/if_sdio.c
+@@ -0,0 +1,1379 @@
++/** @file if_sdio.c
++ * @brief This file contains SDIO IF (interface) module
++ * related functions.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/****************************************************
++Change log:
++ 10/14/05: add Doxygen format comments
++ 01/05/06: add kernel 2.6.x support
++ 01/23/06: add fw downlaod
++ 06/06/06: add macro SD_BLOCK_SIZE_FW_DL for firmware download
++ add macro ALLOC_BUF_SIZE for cmd resp/Rx data skb buffer allocation
++****************************************************/
++#include <linux/mmc/card.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
++
++#include "if_sdio.h"
++
++//#undef PRINTM
++//#define PRINTM(INFO, msg...) printk(msg)
++
++/* define SD block size for firmware download */
++#define SD_BLOCK_SIZE_FW_DL 32
++
++/* define SD block size for data Tx/Rx */
++#define SD_BLOCK_SIZE 320 /* To minimize the overhead of ethernet frame
++ with 1514 bytes, 320 bytes block size is used */
++
++#define ALLOC_BUF_SIZE (((MAX(MRVDRV_ETH_RX_PACKET_BUFFER_SIZE, \
++ MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
++ + SD_BLOCK_SIZE - 1) / SD_BLOCK_SIZE) * SD_BLOCK_SIZE)
++
++/* Max retry number of CMD53 write */
++#define MAX_WRITE_IOMEM_RETRY 2
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++struct if_sdio_card {
++ struct sdio_func *func;
++ wlan_private *priv;
++ int model;
++
++ u8 int_cause;
++
++ u8 chiprev;
++ u8 async_int_mode;
++ u8 block_size_512;
++ card_capability info;
++};
++
++extern wlan_private *wlanpriv;
++const char *helper_name;
++const char *fw_name;
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function adds the card
++ *
++ * @param card A pointer to the card
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++sbi_add_card(void *card)
++{
++ struct if_sdio_card *sdio_card = (struct if_sdio_card*)card;
++ sdio_card->priv = wlan_add_card(card);
++ if (sdio_card->priv)
++ return WLAN_STATUS_SUCCESS;
++ else
++ return WLAN_STATUS_FAILURE;
++}
++
++/**
++ * @brief This function removes the card
++ *
++ * @param card A pointer to the card
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++sbi_remove_card(void *card)
++{
++ return wlan_remove_card(card);
++}
++
++/**
++ * @brief This function reads scratch registers
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param dat A pointer to keep returned data
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++mv_sdio_read_scratch(wlan_private * priv, u16 * dat)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 scr0;
++ u8 scr1;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ scr0 = sdio_readb(card->func, CARD_OCR_0_REG, &ret);
++ if (ret)
++ return WLAN_STATUS_FAILURE;
++
++ scr1 = sdio_readb(card->func, CARD_OCR_1_REG, &ret);
++ PRINTM(INFO, "CARD_OCR_0_REG = 0x%x, CARD_OCR_1_REG = 0x%x\n", scr0,
++ scr1);
++ if (ret)
++ return WLAN_STATUS_FAILURE;
++
++ *dat = (((u16) scr1) << 8) | scr0;
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function polls the card status register.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param bits the bit mask
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++mv_sdio_poll_card_status(wlan_private * priv, u8 bits)
++{
++ int tries;
++ int rval;
++ u8 cs;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
++ cs = sdio_readb(card->func, CARD_STATUS_REG, &rval);
++ if (rval == 0 && (cs & bits) == bits) {
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ mdelay(1);
++ }
++
++ PRINTM(WARN, "mv_sdio_poll_card_status: FAILED!:%d\n", rval);
++ return WLAN_STATUS_FAILURE;
++}
++
++/**
++ * @brief This function programs the firmware image.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param firmware A pointer to the buffer of firmware image
++ * @param firmwarelen the length of firmware image
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++sbi_prog_firmware_image(wlan_private * priv,
++ const u8 * firmware, int firmwarelen)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u16 firmwarestat;
++ u8 *fwbuf = priv->adapter->TmpTxBuf;
++ int fwblknow;
++ u32 tx_len;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++#ifdef FW_DOWNLOAD_SPEED
++ u32 tv1, tv2;
++#endif
++
++ ENTER();
++
++ sdio_claim_host(card->func);
++ ret = sdio_set_block_size(card->func, SD_BLOCK_SIZE_FW_DL);
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ if ((ret = mv_sdio_read_scratch(priv, &firmwarestat)) < 0) {
++ PRINTM(INFO, "read scratch returned <0\n");
++ goto done;
++ }
++
++ if (firmwarestat == FIRMWARE_READY) {
++ PRINTM(INFO, "FW already downloaded!\n");
++ ret = WLAN_STATUS_SUCCESS;
++ goto done;
++ }
++
++ PRINTM(INFO, "Downloading helper image (%d bytes), block size %d bytes\n",
++ firmwarelen, SD_BLOCK_SIZE_FW_DL);
++
++#ifdef FW_DOWNLOAD_SPEED
++ tv1 = get_utimeofday();
++#endif
++ /* Perform firmware data transfer */
++ tx_len =
++ (FIRMWARE_TRANSFER_NBLOCK * SD_BLOCK_SIZE_FW_DL) - SDIO_HEADER_LEN;
++ for (fwblknow = 0; fwblknow < firmwarelen; fwblknow += tx_len) {
++
++ /* The host polls for the DN_LD_CARD_RDY and CARD_IO_READY bits */
++ ret = mv_sdio_poll_card_status(priv, CARD_IO_READY | DN_LD_CARD_RDY);
++ if (ret < 0) {
++ PRINTM(FATAL, "FW download died @ %d\n", fwblknow);
++ goto done;
++ }
++
++ /* Set blocksize to transfer - checking for last block */
++ if (firmwarelen - fwblknow < tx_len)
++ tx_len = firmwarelen - fwblknow;
++
++ fwbuf[0] = ((tx_len & 0x000000ff) >> 0); /* Little-endian */
++ fwbuf[1] = ((tx_len & 0x0000ff00) >> 8);
++ fwbuf[2] = ((tx_len & 0x00ff0000) >> 16);
++ fwbuf[3] = ((tx_len & 0xff000000) >> 24);
++
++ /* Copy payload to buffer */
++ memcpy(&fwbuf[SDIO_HEADER_LEN], &firmware[fwblknow], tx_len);
++
++ PRINTM(INFO, ".");
++
++ /* Send data */
++ ret = sdio_writesb(card->func, priv->wlan_dev.ioport,
++ fwbuf, FIRMWARE_TRANSFER_NBLOCK * SD_BLOCK_SIZE_FW_DL);
++
++ if (ret) {
++ PRINTM(FATAL, "IO error: transferring block @ %d\n", fwblknow);
++ goto done;
++ }
++ }
++
++#ifdef FW_DOWNLOAD_SPEED
++ tv2 = get_utimeofday();
++ PRINTM(INFO, "helper: %ld.%03ld.%03ld ", tv1 / 1000000,
++ (tv1 % 1000000) / 1000, tv1 % 1000);
++ PRINTM(INFO, " -> %ld.%03ld.%03ld ", tv2 / 1000000,
++ (tv2 % 1000000) / 1000, tv2 % 1000);
++ tv2 -= tv1;
++ PRINTM(INFO, " == %ld.%03ld.%03ld\n", tv2 / 1000000,
++ (tv2 % 1000000) / 1000, tv2 % 1000);
++#endif
++
++ /* Write last EOF data */
++ PRINTM(INFO, "\nTransferring EOF block\n");
++ memset(fwbuf, 0x0, SD_BLOCK_SIZE_FW_DL);
++ ret = sdio_writesb(card->func, priv->wlan_dev.ioport, fwbuf, SD_BLOCK_SIZE_FW_DL);
++
++ if (ret) {
++ PRINTM(FATAL, "IO error in writing EOF FW block\n");
++ goto done;
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++
++done:
++ sdio_set_block_size(card->func, 0);
++ sdio_release_host(card->func);
++ return ret;
++}
++
++/**
++ * @brief This function downloads firmware image to the card.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param firmware A pointer to firmware image buffer
++ * @param firmwarelen the length of firmware image
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++sbi_download_wlan_fw_image(wlan_private * priv,
++ const u8 * firmware, int firmwarelen)
++{
++ u8 base0;
++ u8 base1;
++ int ret = WLAN_STATUS_SUCCESS;
++ int offset;
++ u8 *fwbuf = priv->adapter->TmpTxBuf;
++ int timeout = 5000;
++ u16 len;
++ int txlen = 0;
++ int tx_blocks = 0;
++ int i = 0;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++#ifdef FW_DOWNLOAD_SPEED
++ u32 tv1, tv2;
++#endif
++
++ ENTER();
++
++ PRINTM(INFO, "Downloading FW image (%d bytes)\n", firmwarelen);
++
++#ifdef FW_DOWNLOAD_SPEED
++ tv1 = get_utimeofday();
++#endif
++ sdio_claim_host(card->func);
++
++ ret = sdio_set_block_size(card->func, SD_BLOCK_SIZE_FW_DL);
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Wait initially for the first non-zero value */
++ do {
++ base0 = sdio_readb(card->func, HOST_F1_RD_BASE_0, &ret);
++ if (ret) {
++ PRINTM(WARN, "Dev BASE0 register read failed:"
++ " base0=0x%04X(%d)\n", base0, base0);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ base1 = sdio_readb(card->func, HOST_F1_RD_BASE_1, &ret);
++ if (ret) {
++ PRINTM(WARN, "Dev BASE1 register read failed:"
++ " base1=0x%04X(%d)\n", base1, base1);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ len = (((u16) base1) << 8) | base0;
++ mdelay(1);
++ } while (!len && --timeout);
++
++ if (!timeout) {
++ PRINTM(MSG, "Helper downloading finished.\n");
++ PRINTM(MSG, "Timeout for FW downloading!\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* The host polls for the DN_LD_CARD_RDY and CARD_IO_READY bits */
++ ret = mv_sdio_poll_card_status(priv, CARD_IO_READY | DN_LD_CARD_RDY);
++ if (ret < 0) {
++ PRINTM(FATAL, "FW download died, helper not ready\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ len &= ~B_BIT_0;
++
++ /* Perform firmware data transfer */
++ for (offset = 0; offset < firmwarelen; offset += txlen) {
++ txlen = len;
++
++ /* Set blocksize to transfer - checking for last block */
++ if (firmwarelen - offset < txlen) {
++ txlen = firmwarelen - offset;
++ }
++ /* PRINTM(INFO, "fw: offset=%d, txlen = 0x%04X(%d)\n",
++ offset,txlen,txlen); */
++ PRINTM(INFO, ".");
++
++ tx_blocks = (txlen + SD_BLOCK_SIZE_FW_DL - 1) / SD_BLOCK_SIZE_FW_DL;
++
++ /* Copy payload to buffer */
++ memcpy(fwbuf, &firmware[offset], txlen);
++
++ /* Send data */
++ ret = sdio_writesb(card->func, priv->wlan_dev.ioport,
++ fwbuf, tx_blocks * SD_BLOCK_SIZE_FW_DL);
++
++ if (ret) {
++ PRINTM(ERROR, "FW download, write iomem (%d) failed: %d\n", i,
++ ret);
++ sdio_writeb(card->func, 0x04, CONFIGURATION_REG, &ret);
++ if (ret) {
++ PRINTM(ERROR, "write ioreg failed (FN1 CFG)\n");
++ }
++ }
++
++ /* The host polls for the DN_LD_CARD_RDY and CARD_IO_READY bits */
++ ret = mv_sdio_poll_card_status(priv, CARD_IO_READY | DN_LD_CARD_RDY);
++ if (ret < 0) {
++ PRINTM(FATAL, "FW download with helper died @ %d\n", offset);
++ goto done;
++ }
++
++ base0 = sdio_readb(card->func, HOST_F1_RD_BASE_0, &ret);
++ if (ret) {
++ PRINTM(WARN, "Dev BASE0 register read failed:"
++ " base0=0x%04X(%d)\n", base0, base0);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ base1 = sdio_readb(card->func, HOST_F1_RD_BASE_1, &ret);
++ if (ret) {
++ PRINTM(WARN, "Dev BASE1 register read failed:"
++ " base1=0x%04X(%d)\n", base1, base1);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ len = (((u16) base1) << 8) | base0;
++
++ if (!len) {
++ break;
++ }
++
++ if (len & B_BIT_0) {
++ i++;
++ if (i > MAX_WRITE_IOMEM_RETRY) {
++ PRINTM(FATAL, "FW download failure, over max retry count\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ PRINTM(ERROR, "CRC error indicated by the helper:"
++ " len = 0x%04X, txlen = %d\n", len, txlen);
++ len &= ~B_BIT_0;
++ /* Setting this to 0 to resend from same offset */
++ txlen = 0;
++ }
++ else
++ i = 0;
++ }
++ PRINTM(INFO, "\nFW download over, size %d bytes\n", firmwarelen);
++
++ ret = WLAN_STATUS_SUCCESS;
++done:
++ sdio_set_block_size(card->func, 0);
++ sdio_release_host(card->func);
++#ifdef FW_DOWNLOAD_SPEED
++ tv2 = get_utimeofday();
++ PRINTM(INFO, "FW: %ld.%03ld.%03ld ", tv1 / 1000000,
++ (tv1 % 1000000) / 1000, tv1 % 1000);
++ PRINTM(INFO, " -> %ld.%03ld.%03ld ", tv2 / 1000000,
++ (tv2 % 1000000) / 1000, tv2 % 1000);
++ tv2 -= tv1;
++ PRINTM(INFO, " == %ld.%03ld.%03ld\n", tv2 / 1000000,
++ (tv2 % 1000000) / 1000, tv2 % 1000);
++#endif
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function reads data from the card.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param type A pointer to keep type as data or command
++ * @param nb A pointer to keep the data/cmd length retured in buffer
++ * @param payload A pointer to the data/cmd buffer
++ * @param nb the length of data/cmd buffer
++ * @param npayload the length of data/cmd buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++mv_sdio_card_to_host(wlan_private * priv,
++ u32 * type, int *nb, u8 * payload, int npayload)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u16 buf_len = 0;
++ int buf_block_len;
++ int blksz;
++ u32 *pevent;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ ENTER();
++
++ if (!payload) {
++ PRINTM(WARN, "payload NULL pointer received!\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto exit;
++ }
++
++ /* Read the length of data to be transferred */
++ ret = mv_sdio_read_scratch(priv, &buf_len);
++ if (ret < 0) {
++ PRINTM(ERROR, "card_to_host, read RX length failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto exit;
++ }
++
++ if (buf_len <= SDIO_HEADER_LEN || buf_len > npayload) {
++ PRINTM(ERROR, "card_to_host, invalid packet length: %d\n", buf_len);
++ ret = WLAN_STATUS_FAILURE;
++ goto exit;
++ }
++
++ ret = mv_sdio_poll_card_status(priv, CARD_IO_READY);
++ if (ret < 0) {
++ PRINTM(FATAL, "MV card status fail\n");
++ goto exit;
++ }
++
++ /* Allocate buffer */
++ blksz = SD_BLOCK_SIZE;
++ buf_block_len = (buf_len + blksz - 1) / blksz;
++
++ ret = sdio_set_block_size(card->func, blksz);
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto exit;
++ }
++
++ ret = sdio_readsb(card->func, payload, priv->wlan_dev.ioport, buf_block_len * blksz);
++
++ if (ret) {
++ PRINTM(ERROR, "card_to_host, read iomem failed: %d\n", ret);
++ ret = WLAN_STATUS_FAILURE;
++ goto exit;
++ }
++ *nb = buf_len;
++
++ DBG_HEXDUMP(IF_D, "SDIO Blk Rd", payload, blksz * buf_block_len);
++
++ *type = (payload[2] | (payload[3] << 8));
++ if (*type == MVSD_EVENT) {
++ pevent = (u32 *) & payload[4];
++ priv->adapter->EventCause = MVSD_EVENT | (((u16) (*pevent)) << 3);
++ }
++
++exit:
++ sdio_set_block_size(card->func, 0);
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function enables the host interrupts mask
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param mask the interrupt mask
++ * @return WLAN_STATUS_SUCCESS
++ */
++static int
++enable_host_int_mask(wlan_private * priv, u8 mask)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ sdio_claim_host(card->func);
++ /* Simply write the mask to the register */
++ sdio_writeb(card->func, mask, HOST_INT_MASK_REG, &ret);
++ sdio_release_host(card->func);
++
++ if (ret) {
++ PRINTM(WARN, "ret = %d\n", ret);
++ ret = WLAN_STATUS_FAILURE;
++ }
++
++ priv->adapter->HisRegCpy = 1;
++
++ return ret;
++}
++
++/** @brief This function disables the host interrupts mask.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param mask the interrupt mask
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++disable_host_int_mask(wlan_private * priv, u8 mask)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 host_int_mask;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ sdio_claim_host(card->func);
++ /* Read back the host_int_mask register */
++ host_int_mask = sdio_readb(card->func, HOST_INT_MASK_REG, &ret);
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Update with the mask and write back to the register */
++ host_int_mask &= ~mask;
++ sdio_writeb(card->func, host_int_mask, HOST_INT_MASK_REG, &ret);
++ if (ret) {
++ PRINTM(WARN, "Unable to diable the host interrupt!\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++done:
++ sdio_release_host(card->func);
++ return ret;
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief This function handles the interrupt.
++ *
++ * @param irq The irq of device.
++ * @param dev_id A pointer to net_device structure
++ * @param fp A pointer to pt_regs structure
++ * @return n/a
++ */
++static void sbi_interrupt(struct sdio_func *func)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 sdio_ireg = 0;
++ u8 *cmdBuf;
++ wlan_private *priv;
++ wlan_dev_t *wlan_dev;
++ struct sk_buff *skb;
++ struct if_sdio_card* card = NULL;
++ ENTER();
++
++ priv = wlanpriv;
++ wlan_dev = &priv->wlan_dev;
++ card = (struct if_sdio_card*)wlan_dev->card;
++
++ sdio_ireg = sdio_readb(func, HOST_INTSTATUS_REG, &ret);
++ if (ret) {
++ PRINTM(WARN, "sdio_read_ioreg: read int status register failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ sdio_writeb(func, (~sdio_ireg) & (DN_LD_HOST_INT_STATUS | UP_LD_HOST_INT_STATUS),
++ HOST_INTSTATUS_REG, &ret);
++ if (ret) {
++ PRINTM(WARN, "sdio_write_ioreg: clear int status register failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ if (sdio_ireg & DN_LD_HOST_INT_STATUS) { /* tx_done INT */
++ if (!priv->wlan_dev.dnld_sent) { /* tx_done already received */
++ PRINTM(INFO, "warning: tx_done already received:"
++ " dnld_sent=0x%x int status=0x%x\n",
++ priv->wlan_dev.dnld_sent, sdio_ireg);
++ }
++ else {
++ wmm_process_fw_iface_tx_xfer_end(priv);
++ priv->wlan_dev.dnld_sent = DNLD_RES_RECEIVED;
++ }
++ OS_INT_DISABLE;
++ card->int_cause |= HIS_TxDnLdRdy;
++ wlan_interrupt(wlan_dev->netdev);
++ OS_INT_RESTORE;
++ }
++
++ if (sdio_ireg & UP_LD_HOST_INT_STATUS) {
++
++ /*
++ * DMA read data is by block alignment,so we need alloc extra block
++ * to avoid wrong memory access.
++ */
++ if (!(skb = dev_alloc_skb(ALLOC_BUF_SIZE))) {
++ PRINTM(WARN, "No free skb\n");
++ priv->stats.rx_dropped++;
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /*
++ * Transfer data from card
++ * skb->tail is passed as we are calling skb_put after we
++ * are reading the data
++ */
++ if (mv_sdio_card_to_host(priv, &wlan_dev->upld_typ,
++ (int *) &wlan_dev->upld_len, skb->tail,
++ ALLOC_BUF_SIZE) < 0) {
++ u8 cr = 0;
++
++ PRINTM(ERROR, "Card to host failed: int status=0x%x\n",
++ sdio_ireg);
++ cr = sdio_readb(func, CONFIGURATION_REG, &ret);
++ if (ret)
++ PRINTM(ERROR, "read ioreg failed (FN1 CFG)\n");
++
++ PRINTM(INFO, "Config Reg val = %d\n", cr);
++ sdio_writeb(func, cr | 0x04, CONFIGURATION_REG, &ret);
++ if (ret)
++ PRINTM(ERROR, "write ioreg failed (FN1 CFG)\n");
++
++ PRINTM(INFO, "write success\n");
++ cr = sdio_readb(func, CONFIGURATION_REG, &ret);
++ if (ret)
++ PRINTM(ERROR, "read ioreg failed (FN1 CFG)\n");
++
++ PRINTM(INFO, "Config reg val =%x\n", cr);
++ ret = WLAN_STATUS_FAILURE;
++ kfree_skb(skb);
++ goto done;
++ }
++
++ OS_INT_DISABLE;
++ switch (wlan_dev->upld_typ) {
++ case MVSD_DAT:
++ PRINTM(DATA, "Data <= FW\n");
++ card->int_cause |= HIS_RxUpLdRdy;
++ skb_put(skb, priv->wlan_dev.upld_len);
++ skb_pull(skb, SDIO_HEADER_LEN);
++ list_add_tail((struct list_head *) skb,
++ (struct list_head *) &priv->adapter->RxSkbQ);
++ /* skb will be freed by kernel later */
++ break;
++
++ case MVSD_CMD:
++ PRINTM(DATA, "CMD\n");
++
++ /* take care of CurCmd = NULL case */
++ if (!priv->adapter->CurCmd) {
++ cmdBuf = priv->wlan_dev.upld_buf;
++ }
++ else {
++ cmdBuf = priv->adapter->CurCmd->BufVirtualAddr;
++ }
++
++ priv->wlan_dev.upld_len -= SDIO_HEADER_LEN;
++ memcpy(cmdBuf, skb->data + SDIO_HEADER_LEN,
++ MIN(MRVDRV_SIZE_OF_CMD_BUFFER, priv->wlan_dev.upld_len));
++ kfree_skb(skb);
++ card->int_cause |= HIS_CmdUpLdRdy;
++ break;
++
++ case MVSD_EVENT:
++ /* event cause has been saved to priv->adapter->EventCause */
++ kfree_skb(skb);
++ card->int_cause |= HIS_CardEvent;
++ break;
++
++ default:
++ PRINTM(ERROR, "SDIO unknown upld type = 0x%x\n",
++ wlan_dev->upld_typ);
++ kfree_skb(skb);
++ break;
++ }
++ wlan_interrupt(wlan_dev->netdev);
++ OS_INT_RESTORE;
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++done:
++ LEAVE();
++ return;
++}
++
++/**
++ * @brief This function reads the IO register.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param func funcion number
++ * @param reg register to be read
++ * @param dat A pointer to variable that keeps returned value
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_read_ioreg(wlan_private * priv, u8 func, u32 reg, u8 * dat)
++{
++ int ret;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++ sdio_claim_host(card->func);
++ if (func == 0)
++ *dat = sdio_f0_readb(card->func, reg, &ret);
++ else
++ *dat = sdio_readb(card->func, reg, &ret);
++ sdio_release_host(card->func);
++ return ret;
++}
++
++/**
++ * @brief This function writes the IO register.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param func funcion number
++ * @param reg register to be written
++ * @param dat the value to be written
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_write_ioreg(wlan_private * priv, u8 func, u32 reg, u8 dat)
++{
++ int ret;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++ sdio_claim_host(card->func);
++ if (func == 0)
++ sdio_f0_writeb(card->func, dat, reg, &ret);
++ else
++ sdio_writeb(card->func, dat, reg, &ret);
++ sdio_release_host(card->func);
++ return ret;
++}
++
++/**
++ * @brief This function checks the interrupt status and handle it accordingly.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param ireg A pointer to variable that keeps returned value
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_get_int_status(wlan_private * priv, u8 * ireg)
++{
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++ OS_INT_DISABLE;
++ *ireg = card->int_cause;
++ card->int_cause = 0;
++ OS_INT_RESTORE;
++ return WLAN_STATUS_SUCCESS;
++
++}
++
++/**
++ * @brief This function is a dummy function.
++ *
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++sbi_card_to_host(wlan_private * priv, u32 type,
++ u32 * nb, u8 * payload, u16 npayload)
++{
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++sbi_read_event_cause(wlan_private * priv)
++{
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function disables the host interrupts.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_disable_host_int(wlan_private * priv)
++{
++ return disable_host_int_mask(priv, HIM_DISABLE);
++}
++
++/**
++ * @brief This function enables the host interrupts.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++sbi_enable_host_int(wlan_private * priv)
++{
++ return enable_host_int_mask(priv, HIM_ENABLE);
++}
++
++/**
++ * @brief This function de-registers the device.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++sbi_unregister_dev(wlan_private * priv)
++{
++ ENTER();
++
++ if (priv->wlan_dev.card != NULL) {
++ /* Release the SDIO IRQ */
++ PRINTM(WARN, "Making the sdio dev card as NULL\n");
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function registers the device.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_register_dev(wlan_private * priv)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 reg;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ ENTER();
++
++ /* Initialize the private structure */
++ strncpy(priv->wlan_dev.name, "sdio0", sizeof(priv->wlan_dev.name));
++ priv->wlan_dev.ioport = 0;
++ priv->wlan_dev.upld_rcv = 0;
++ priv->wlan_dev.upld_typ = 0;
++ priv->wlan_dev.upld_len = 0;
++
++ sdio_claim_host(card->func);
++ /* Read the IO port */
++ reg = sdio_readb(card->func, IO_PORT_0_REG, &ret);
++ if (ret)
++ goto failed;
++ else
++ priv->wlan_dev.ioport |= reg;
++
++ reg = sdio_readb(card->func, IO_PORT_1_REG, &ret);
++ if (ret)
++ goto failed;
++ else
++ priv->wlan_dev.ioport |= (reg << 8);
++
++ reg = sdio_readb(card->func, IO_PORT_2_REG, &ret);
++ if (ret)
++ goto failed;
++ else
++ priv->wlan_dev.ioport |= (reg << 16);
++ sdio_release_host(card->func);
++
++ PRINTM(INFO, "SDIO FUNC1 IO port: 0x%x\n", priv->wlan_dev.ioport);
++
++ /* Disable host interrupt first. */
++ if ((ret = disable_host_int_mask(priv, 0xff)) < 0) {
++ PRINTM(WARN, "Warning: unable to disable host interrupt!\n");
++ }
++
++ priv->adapter->chip_rev = card->chiprev;
++ priv->adapter->sdiomode = 4;
++
++ return WLAN_STATUS_SUCCESS;
++
++failed:
++ sdio_release_host(card->func);
++ priv->wlan_dev.card = NULL;
++
++ return WLAN_STATUS_FAILURE;
++}
++
++/**
++ * @brief This function sends data to the card.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param type data or command
++ * @param payload A pointer to the data/cmd buffer
++ * @param nb the length of data/cmd
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_host_to_card(wlan_private * priv, u8 type, u8 * payload, u16 nb)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ int buf_block_len;
++ int blksz;
++ int i = 0;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ ENTER();
++
++ sdio_claim_host(card->func);
++ priv->adapter->HisRegCpy = 0;
++
++ /* Allocate buffer and copy payload */
++ blksz = SD_BLOCK_SIZE;
++ buf_block_len = (nb + SDIO_HEADER_LEN + blksz - 1) / blksz;
++
++ /* This is SDIO specific header
++ * length: byte[1][0],
++ * type: byte[3][2] (MVSD_DAT = 0, MVSD_CMD = 1, MVSD_EVENT = 3)
++ */
++ priv->adapter->TmpTxBuf[0] = (nb + SDIO_HEADER_LEN) & 0xff;
++ priv->adapter->TmpTxBuf[1] = ((nb + SDIO_HEADER_LEN) >> 8) & 0xff;
++ priv->adapter->TmpTxBuf[2] = type;
++ priv->adapter->TmpTxBuf[3] = 0x0;
++
++ if (payload != NULL &&
++ (nb > 0 &&
++ nb <= (sizeof(priv->adapter->TmpTxBuf) - SDIO_HEADER_LEN))) {
++ if (type == MVMS_CMD)
++ memcpy(&priv->adapter->TmpTxBuf[SDIO_HEADER_LEN], payload, nb);
++ }
++ else {
++ PRINTM(WARN, "sbi_host_to_card(): Error: payload=%p, nb=%d\n",
++ payload, nb);
++ }
++
++ if (type == MVSD_DAT)
++ priv->wlan_dev.dnld_sent = DNLD_DATA_SENT;
++ else
++ priv->wlan_dev.dnld_sent = DNLD_CMD_SENT;
++
++ ret = sdio_set_block_size(card->func, blksz);
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto exit;
++ }
++
++ do {
++ /* Transfer data to card */
++ ret = sdio_writesb(card->func, priv->wlan_dev.ioport,
++ priv->adapter->TmpTxBuf, blksz * buf_block_len);
++ if (ret) {
++ i++;
++
++ PRINTM(ERROR, "host_to_card, write iomem (%d) failed: %d\n", i,
++ ret);
++ sdio_writeb(card->func, 0x04, CONFIGURATION_REG, &ret);
++ if (ret) {
++ PRINTM(ERROR, "write ioreg failed (FN1 CFG)\n");
++ }
++ ret = WLAN_STATUS_FAILURE;
++ if (i > MAX_WRITE_IOMEM_RETRY) {
++ priv->wlan_dev.dnld_sent = DNLD_RES_RECEIVED;
++ goto exit;
++ }
++ }
++ else {
++ DBG_HEXDUMP(IF_D, "SDIO Blk Wr", priv->adapter->TmpTxBuf,
++ blksz * buf_block_len);
++ }
++ } while (ret == WLAN_STATUS_FAILURE);
++
++exit:
++ sdio_set_block_size(card->func, 0);
++ sdio_release_host(card->func);
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function reads CIS informaion.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_get_cis_info(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ u8 tupledata[255];
++ ENTER();
++
++ /* TODO using sdio tuple data */
++
++ /* Copy the CIS Table to Adapter */
++ memset(Adapter->CisInfoBuf, 0x0, sizeof(Adapter->CisInfoBuf));
++ memcpy(Adapter->CisInfoBuf, tupledata, sizeof(tupledata));
++ Adapter->CisInfoLen = sizeof(tupledata);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function probes the card.
++ *
++ * @param card_p A pointer to the card
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_probe_card(void *card_p)
++{
++ struct if_sdio_card* card = (struct if_sdio_card*)card_p;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ if (!card) {
++ ret = -ENODEV; //WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Check for MANFID */
++ PRINTM(INFO, "Marvell SDIO card detected!\n");
++
++ sdio_claim_host(card->func);
++ /* read Revision Register to get the hw revision number */
++ card->chiprev = sdio_readb(card->func, CARD_REVISION_REG, &ret);
++ if (ret) {
++ PRINTM(FATAL, "cannot read CARD_REVISION_REG\n");
++ }
++ else {
++ PRINTM(INFO, "revision=0x%x\n", card->chiprev);
++ switch (card->chiprev) {
++ default:
++ card->block_size_512 = TRUE;
++ card->async_int_mode = TRUE;
++ break;
++ }
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++done:
++ sdio_release_host(card->func);
++ return ret;
++}
++
++/**
++ * @brief This function calls sbi_download_wlan_fw_image to download
++ * firmware image to the card.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_prog_firmware_w_helper(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ if (Adapter->fmimage != NULL) {
++ return sbi_download_wlan_fw_image(priv,
++ Adapter->fmimage,
++ Adapter->fmimage_len);
++ }
++ else {
++ PRINTM(MSG, "No external FW image\n");
++ return WLAN_STATUS_FAILURE;
++ }
++}
++
++/**
++ * @brief This function programs helper image.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_prog_helper(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ if (Adapter->helper != NULL) {
++ return sbi_prog_firmware_image(priv,
++ Adapter->helper, Adapter->helper_len);
++ }
++ else {
++ PRINTM(MSG, "No external helper image\n");
++ return WLAN_STATUS_FAILURE;
++ }
++}
++
++/**
++ * @brief This function checks if the firmware is ready to accept
++ * command or not.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_verify_fw_download(wlan_private * priv)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u16 firmwarestat;
++ int tries;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ sdio_claim_host(card->func);
++ /* Wait for firmware initialization event */
++ for (tries = 0; tries < MAX_FIRMWARE_POLL_TRIES; tries++) {
++ if ((ret = mv_sdio_read_scratch(priv, &firmwarestat)) < 0)
++ continue;
++
++ if (firmwarestat == FIRMWARE_READY) {
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ }
++ else {
++ mdelay(10);
++ ret = WLAN_STATUS_FAILURE;
++ }
++ }
++
++ if (ret < 0) {
++ PRINTM(MSG, "Timeout waiting for FW to become active\n");
++ goto done;
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++done:
++ sdio_release_host(card->func);
++ return ret;
++}
++
++/**
++ * @brief This function set bus clock on/off
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param option TRUE--on , FALSE--off
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++sbi_set_bus_clock(wlan_private * priv, u8 option)
++{
++/* if (option == TRUE)
++ start_bus_clock(((mmc_card_t) ((priv->wlan_dev).card))->ctrlr);
++ else
++ stop_bus_clock_2(((mmc_card_t) ((priv->wlan_dev).card))->ctrlr); */
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function makes firmware exiting from deep sleep.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_exit_deep_sleep(wlan_private * priv)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ sbi_set_bus_clock(priv, TRUE);
++
++ sdio_claim_host(card->func);
++ sdio_writeb(card->func, HOST_POWER_UP, CONFIGURATION_REG, &ret);
++ sdio_release_host(card->func);
++
++ return ret;
++}
++
++/**
++ * @brief This function resets the setting of deep sleep.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sbi_reset_deepsleep_wakeup(wlan_private * priv)
++{
++
++ int ret = WLAN_STATUS_SUCCESS;
++ struct if_sdio_card* card = (struct if_sdio_card*)priv->wlan_dev.card;
++
++ ENTER();
++
++ sdio_claim_host(card->func);
++ sdio_writeb(card->func, 0, CONFIGURATION_REG, &ret);
++ sdio_release_host(card->func);
++
++ LEAVE();
++
++ return ret;
++}
++
++static const struct sdio_device_id if_sdio_ids[] = {
++ { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_LIBERTAS)},
++ { /* end: all zeroes */},
++};
++
++MODULE_DEVICE_TABLE(sdio, if_sdio_ids);
++struct if_sdio_model
++{
++ int model;
++ const char *helper;
++ const char *firmware;
++};
++
++static struct if_sdio_model if_sdio_models[] = {
++ {
++ /* 8686 */
++ .model = 0x0B,
++ .helper = "/lib/firmware/sd8686_helper.bin",
++ .firmware = "/lib/firmware/sd8686.bin",
++ },
++};
++
++static int if_sdio_probe(struct sdio_func *func,
++ const struct sdio_device_id *id)
++{
++ struct if_sdio_card *card;
++ int ret, i;
++ unsigned int model;
++
++ card = kzalloc(sizeof(struct if_sdio_card), GFP_KERNEL);
++
++ for (i = 0;i < func->card->num_info;i++) {
++ if (sscanf(func->card->info[i],
++ "802.11 SDIO ID: %x", &model) == 1)
++ break;
++ if (sscanf(func->card->info[i],
++ "ID: %x", &model) == 1)
++ break;
++ if (!strcmp(func->card->info[i], "IBIS Wireless SDIO Card")) {
++ model = 4;
++ break;
++ }
++ }
++
++ if (i == func->card->num_info) {
++ printk("unable to identify card model\n");
++ return -ENODEV;
++ }
++
++ card->func = func;
++ card->model = model;
++
++ for (i = 0;i < ARRAY_SIZE(if_sdio_models);i++) {
++ if (card->model == if_sdio_models[i].model)
++ break;
++ }
++
++ if (i == ARRAY_SIZE(if_sdio_models)) {
++ printk("unknown card model 0x%x\n", card->model);
++ ret = -ENODEV;
++ goto free;
++ }
++
++ helper_name = if_sdio_models[i].helper;
++ fw_name = if_sdio_models[i].firmware;
++
++ sdio_claim_host(func);
++
++ ret = sdio_enable_func(func);
++ if (ret)
++ goto release;
++
++ sdio_writeb(func, 0x00, HOST_INT_MASK_REG, &ret);
++ if (ret) {
++ PRINTM(WARN, "Unable to diable the host interrupt!\n");
++ goto reclaim;
++ }
++
++ ret = sdio_claim_irq(func, sbi_interrupt);
++ if (ret)
++ goto disable;
++
++ sdio_release_host(func);
++
++ sdio_set_drvdata(func, card);
++
++ ret = sbi_add_card(card);
++ if (ret)
++ goto reclaim;
++
++out:
++ return ret;
++
++reclaim:
++ sdio_claim_host(func);
++ sdio_release_irq(func);
++disable:
++ sdio_disable_func(func);
++release:
++ sdio_release_host(func);
++free:
++ kfree(card);
++ goto out;
++}
++
++static void if_sdio_remove(struct sdio_func *func)
++{
++ struct if_sdio_card *card = sdio_get_drvdata(func);
++ sbi_remove_card(card);
++ sdio_claim_host(func);
++ sdio_release_irq(func);
++ sdio_disable_func(func);
++ sdio_release_host(func);
++ kfree(card);
++ return;
++}
++
++static struct sdio_driver if_sdio_driver = {
++ .name = "sd8686_sdio",
++ .id_table = if_sdio_ids,
++ .probe = if_sdio_probe,
++ .remove = if_sdio_remove,
++};
++
++static int if_sdio_init_module(void)
++{
++ int ret = 0;
++
++ printk(KERN_INFO "8686 sdio: sd 8686 driver\n");
++ printk(KERN_INFO "8686 sdio: Copyright HHCN 2009\n");
++
++ ret = sdio_register_driver(&if_sdio_driver);
++
++ return ret;
++}
++
++static void if_sdio_exit_module(void)
++{
++ sdio_unregister_driver(&if_sdio_driver);
++}
++
++module_init(if_sdio_init_module);
++module_exit(if_sdio_exit_module);
++
++MODULE_DESCRIPTION("Marvell SD8686 SDIO WLAN Driver");
++MODULE_AUTHOR("You Sheng");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/net/wireless/marvell8686/if_sdio.h b/drivers/net/wireless/marvell8686/if_sdio.h
+new file mode 100644
+index 0000000..d059ccf
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/if_sdio.h
+@@ -0,0 +1,97 @@
++/** @file if_sdio.h
++ * @brief This file contains SDIO IF (interface) module
++ * related macros, enum, and structure.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/****************************************************
++Change log:
++ 10/12/05: add Doxygen format comments
++****************************************************/
++
++#ifndef _IF_SDIO_H_
++#define _IF_SDIO_H_
++
++#include "include.h"
++#include "sdio.h"
++
++#define SD_BUS_WIDTH_1 0x00
++#define SD_BUS_WIDTH_4 0x02
++#define SD_BUS_WIDTH_MASK 0x03
++#define ASYNC_INT_MODE 0x20
++
++/* Host Control Registers */
++#define IO_PORT_0_REG 0x00
++#define IO_PORT_1_REG 0x01
++#define IO_PORT_2_REG 0x02
++#define CONFIGURATION_REG 0x03
++#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
++#define HOST_POWER_UP (0x1U << 1)
++#define HOST_POWER_DOWN (0x1U << 0)
++#define HOST_INT_MASK_REG 0x04
++#define UP_LD_HOST_INT_MASK (0x1U)
++#define DN_LD_HOST_INT_MASK (0x2U)
++#define HOST_INTSTATUS_REG 0x05
++#define UP_LD_HOST_INT_STATUS (0x1U)
++#define DN_LD_HOST_INT_STATUS (0x2U)
++#define HOST_INT_RSR_REG 0x06
++#define UP_LD_HOST_INT_RSR (0x1U)
++#define HOST_INT_STATUS_REG 0x07
++#define UP_LD_CRC_ERR (0x1U << 2)
++#define UP_LD_RESTART (0x1U << 1)
++#define DN_LD_RESTART (0x1U << 0)
++
++/* Card Control Registers */
++#define SQ_READ_BASE_ADDRESS_A0_REG 0x10
++#define SQ_READ_BASE_ADDRESS_A1_REG 0x11
++#define SQ_READ_BASE_ADDRESS_A2_REG 0x12
++#define SQ_READ_BASE_ADDRESS_A3_REG 0x13
++#define SQ_READ_BASE_ADDRESS_B0_REG 0x14
++#define SQ_READ_BASE_ADDRESS_B1_REG 0x15
++#define SQ_READ_BASE_ADDRESS_B2_REG 0x16
++#define SQ_READ_BASE_ADDRESS_B3_REG 0x17
++#define CARD_STATUS_REG 0x20
++#define CARD_IO_READY (0x1U << 3)
++#define CIS_CARD_RDY (0x1U << 2)
++#define UP_LD_CARD_RDY (0x1U << 1)
++#define DN_LD_CARD_RDY (0x1U << 0)
++#define HOST_INTERRUPT_MASK_REG 0x24
++#define HOST_POWER_INT_MASK (0x1U << 3)
++#define ABORT_CARD_INT_MASK (0x1U << 2)
++#define UP_LD_CARD_INT_MASK (0x1U << 1)
++#define DN_LD_CARD_INT_MASK (0x1U << 0)
++#define CARD_INTERRUPT_STATUS_REG 0x28
++#define POWER_UP_INT (0x1U << 4)
++#define POWER_DOWN_INT (0x1U << 3)
++#define CARD_INTERRUPT_RSR_REG 0x2c
++#define POWER_UP_RSR (0x1U << 4)
++#define POWER_DOWN_RSR (0x1U << 3)
++#define DEBUG_0_REG 0x30
++#define SD_TESTBUS0 (0x1U)
++#define DEBUG_1_REG 0x31
++#define SD_TESTBUS1 (0x1U)
++#define DEBUG_2_REG 0x32
++#define SD_TESTBUS2 (0x1U)
++#define DEBUG_3_REG 0x33
++#define SD_TESTBUS3 (0x1U)
++#define CARD_OCR_0_REG 0x34
++#define CARD_OCR_1_REG 0x35
++#define CARD_OCR_3_REG 0x36
++#define CARD_CONFIG_REG 0x38
++#define CARD_REVISION_REG 0x3c
++#define CMD53_FINISH_GBUS (0x1U << 1)
++#define SD_NEG_EDGE (0x1U << 0)
++
++/* Special registers in function 0 of the SDxx card */
++#define SCRATCH_0_REG 0x80fe
++#define SCRATCH_1_REG 0x80ff
++
++#define HOST_F1_RD_BASE_0 0x0010
++#define HOST_F1_RD_BASE_1 0x0011
++#define HOST_F1_CARD_RDY 0x0020
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++#endif /* _IF_SDIO_H */
+diff --git a/drivers/net/wireless/marvell8686/include.h b/drivers/net/wireless/marvell8686/include.h
+new file mode 100644
+index 0000000..6bf9abe
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/include.h
+@@ -0,0 +1,42 @@
++/** @file include.h
++ *
++ * @brief This file contains all the necessary include file.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 10/11/05: Add Doxygen format comments
++ 01/11/06: Conditional include file removal/addition
++ 01/30/06: Add kernel 2.6 support
++
++********************************************************/
++
++#ifndef _INCLUDE_H_
++#define _INCLUDE_H_
++
++#include "os_headers.h"
++#include "wlan_types.h"
++#include "wlan_defs.h"
++#include "wlan_thread.h"
++
++#include "wlan_wmm.h"
++#include "wlan_11d.h"
++
++#include "os_timers.h"
++
++#include "host.h"
++#include "hostcmd.h"
++
++#include "wlan_scan.h"
++#include "wlan_join.h"
++
++#include "wlan_dev.h"
++#include "os_macros.h"
++#include "sbi.h"
++
++#include "sdio.h"
++
++#include "wlan_wext.h"
++#include "wlan_decl.h"
++#endif /* _INCLUDE_H_ */
+diff --git a/drivers/net/wireless/marvell8686/os_defs.h b/drivers/net/wireless/marvell8686/os_defs.h
+new file mode 100644
+index 0000000..0529bdd
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/os_defs.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++
++#ifndef _OS_HEADER1_
++#define _OS_HEADER1_
++
++typedef char CHAR;
++typedef char *PCHAR;
++typedef u8 *PUCHAR;
++typedef u16 *PUSHORT;
++typedef long *PLONG;
++typedef PLONG LONG_PTR;
++typedef u32 *ULONG_PTR;
++typedef u32 *Pu32;
++typedef unsigned int UINT;
++typedef UINT *PUINT;
++typedef void VOID;
++typedef VOID *PVOID;
++typedef int WLAN_STATUS;
++typedef u8 BOOLEAN;
++typedef BOOLEAN *PBOOLEAN;
++typedef PVOID PDRIVER_OBJECT;
++typedef PUCHAR PUNICODE_STRING;
++typedef long long LONGLONG;
++typedef LONGLONG *PLONGLONG;
++typedef unsigned long long *PULONGLONG;
++typedef PUCHAR ANSI_STRING;
++typedef ANSI_STRING *PANSI_STRING;
++typedef unsigned short WCHAR;
++typedef WCHAR *PWCHAR;
++typedef WCHAR *LPWCH, *PWCH;
++typedef WCHAR *NWPSTR;
++typedef WCHAR *LPWSTR, *PWSTR;
++typedef struct semaphore SEMAPHORE;
++
++#ifdef __KERNEL__
++typedef irqreturn_t IRQ_RET_TYPE;
++#define IRQ_RET return IRQ_HANDLED
++#endif /* __KERNEL__ */
++
++#endif /* _OS_HEADER1 */
+diff --git a/drivers/net/wireless/marvell8686/os_headers.h b/drivers/net/wireless/marvell8686/os_headers.h
+new file mode 100644
+index 0000000..d01c604
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/os_headers.h
+@@ -0,0 +1,69 @@
++/*
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++
++#ifndef _OS_HEADERS_H
++#define _OS_HEADERS_H
++
++#ifndef __ATTRIB_ALIGN__
++#define __ATTRIB_ALIGN__ __attribute__((aligned(4)))
++#endif
++
++#ifndef __ATTRIB_PACK__
++#define __ATTRIB_PACK__ __attribute__ ((packed))
++#endif
++
++/* Linux header files */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/version.h>
++#include <linux/param.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/mm.h>
++#include <linux/types.h>
++#include <linux/sched.h>
++#include <linux/timer.h>
++#include <linux/types.h>
++#include <linux/ioport.h>
++#include <linux/pci.h>
++#include <linux/ctype.h>
++#include <linux/proc_fs.h>
++#include <linux/ptrace.h>
++#include <linux/string.h>
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
++#include <linux/config.h>
++#endif
++
++#include <linux/ioport.h>
++
++/* New Code to synchronize between IEEE Power save and PM*/
++#ifdef ENABLE_PM
++#include <linux/pm.h>
++#endif
++
++/* ASM files */
++#include <asm/semaphore.h>
++#include <asm/byteorder.h>
++#include <asm/irq.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++#include <asm/system.h>
++
++/* Net header files */
++#include <linux/wireless.h>
++#include <linux/netdevice.h>
++#include <linux/net.h>
++#include <linux/ip.h>
++#include <linux/skbuff.h>
++#include <linux/if_arp.h>
++#include <linux/if_ether.h>
++#include <linux/etherdevice.h>
++#include <net/arp.h>
++#include <linux/rtnetlink.h>
++
++/* Wireless header */
++#include <net/iw_handler.h>
++#endif
+diff --git a/drivers/net/wireless/marvell8686/os_macros.h b/drivers/net/wireless/marvell8686/os_macros.h
+new file mode 100644
+index 0000000..945c609
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/os_macros.h
+@@ -0,0 +1,165 @@
++/*
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++#ifndef _OS_MACROS_H
++#define _OS_MACROS_H
++
++#define os_time_get() jiffies
++
++extern spinlock_t driver_lock;
++extern unsigned long driver_flags;
++#define OS_INT_DISABLE spin_lock_irqsave(&driver_lock, driver_flags)
++#define OS_INT_RESTORE spin_unlock_irqrestore(&driver_lock, driver_flags); \
++ driver_lock = SPIN_LOCK_UNLOCKED
++
++#define UpdateTransStart(dev) { \
++ dev->trans_start = jiffies; \
++}
++
++#define OS_SET_THREAD_STATE(x) set_current_state(x)
++
++#define MODULE_GET if(try_module_get(THIS_MODULE)==0) return WLAN_STATUS_FAILURE;
++#define MODULE_PUT module_put(THIS_MODULE)
++
++#define OS_INIT_SEMAPHORE(x) init_MUTEX(x)
++#define OS_ACQ_SEMAPHORE_BLOCK(x) down_interruptible(x)
++#define OS_ACQ_SEMAPHORE_NOBLOCK(x) down_trylock(x)
++#define OS_REL_SEMAPHORE(x) up(x)
++
++/* Definitions below are needed for other OS like threadx */
++#define TX_DISABLE
++#define TX_RESTORE
++#define ConfigureThreadPriority()
++#define OS_INTERRUPT_SAVE_AREA
++#define OS_FREE_LOCK(x)
++#define TX_EVENT_FLAGS_SET(x, y, z)
++
++#define os_wait_interruptible_timeout(waitq, cond, timeout) \
++ wait_event_interruptible_timeout(waitq, cond, timeout)
++
++static inline void
++os_sched_timeout(u32 millisec)
++{
++ set_current_state(TASK_INTERRUPTIBLE);
++
++ schedule_timeout((millisec * HZ) / 1000);
++}
++
++static inline void
++os_schedule(u32 millisec)
++{
++ schedule_timeout((millisec * HZ) / 1000);
++}
++
++static inline int
++CopyMulticastAddrs(wlan_adapter * Adapter, struct net_device *dev)
++{
++ int i = 0;
++ struct dev_mc_list *mcptr = dev->mc_list;
++
++ for (i = 0; i < dev->mc_count; i++) {
++ memcpy(&Adapter->MulticastList[i], mcptr->dmi_addr, ETH_ALEN);
++ mcptr = mcptr->next;
++ }
++
++ return i;
++}
++
++static inline u32
++get_utimeofday(void)
++{
++ struct timeval t;
++ u32 ut;
++
++ do_gettimeofday(&t);
++ ut = (u32) t.tv_sec * 1000000 + ((u32) t.tv_usec);
++ return ut;
++}
++
++static inline int
++os_upload_rx_packet(wlan_private * priv, struct sk_buff *skb)
++{
++
++#define IPFIELD_ALIGN_OFFSET 2
++
++ skb->dev = priv->wlan_dev.netdev;
++ skb->protocol = eth_type_trans(skb, priv->wlan_dev.netdev);
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++
++ netif_rx(skb);
++
++ return 0;
++}
++
++static inline void
++os_free_tx_packet(wlan_private * priv)
++{
++ ulong flags;
++
++ if (priv->adapter->CurrentTxSkb) {
++ kfree_skb(priv->adapter->CurrentTxSkb);
++ spin_lock_irqsave(&priv->adapter->CurrentTxLock, flags);
++ priv->adapter->CurrentTxSkb = NULL;
++ spin_unlock_irqrestore(&priv->adapter->CurrentTxLock, flags);
++ }
++}
++
++/*
++ * netif carrier_on/off and start(wake)/stop_queue handling
++ *
++ * carrier_on carrier_off start_queue stop_queue
++ * open x(connect) x(disconnect) x
++ * close x x
++ * assoc x x
++ * deauth x x
++ * adhoc-start
++ * adhoc-join
++ * adhoc-link x x
++ * adhoc-bcnlost x x
++ * scan-begin x x
++ * scan-end x x
++ * ds-enter x x
++ * ds-exit x x
++ * xmit x
++ * xmit-done x
++ * tx-timeout
++ */
++static inline void
++os_carrier_on(wlan_private * priv)
++{
++ if (!netif_carrier_ok(priv->wlan_dev.netdev) &&
++ (priv->adapter->MediaConnectStatus == WlanMediaStateConnected) &&
++ ((priv->adapter->InfrastructureMode != Wlan802_11IBSS) ||
++ (priv->adapter->AdhocLinkSensed))) {
++ netif_carrier_on(priv->wlan_dev.netdev);
++ }
++}
++
++static inline void
++os_carrier_off(wlan_private * priv)
++{
++ if (netif_carrier_ok(priv->wlan_dev.netdev)) {
++ netif_carrier_off(priv->wlan_dev.netdev);
++ }
++}
++
++static inline void
++os_start_queue(wlan_private * priv)
++{
++ if (netif_queue_stopped(priv->wlan_dev.netdev) &&
++ (priv->adapter->MediaConnectStatus == WlanMediaStateConnected) &&
++ ((priv->adapter->InfrastructureMode != Wlan802_11IBSS) ||
++ (priv->adapter->AdhocLinkSensed))) {
++ netif_wake_queue(priv->wlan_dev.netdev);
++ }
++}
++
++static inline void
++os_stop_queue(wlan_private * priv)
++{
++ if (!netif_queue_stopped(priv->wlan_dev.netdev)) {
++ netif_stop_queue(priv->wlan_dev.netdev);
++ }
++}
++
++#endif /* _OS_MACROS_H */
+diff --git a/drivers/net/wireless/marvell8686/os_timers.h b/drivers/net/wireless/marvell8686/os_timers.h
+new file mode 100644
+index 0000000..b31387f
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/os_timers.h
+@@ -0,0 +1,83 @@
++/*
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++
++#ifndef _OS_TIMERS_H
++#define _OS_TIMERS_H
++
++typedef struct __WLAN_DRV_TIMER
++{
++ struct timer_list tl;
++ void (*timer_function) (void *context);
++ void *function_context;
++ UINT time_period;
++ BOOLEAN timer_is_periodic;
++ BOOLEAN timer_is_canceled;
++} __ATTRIB_PACK__ WLAN_DRV_TIMER, *PWLAN_DRV_TIMER;
++
++static inline void
++TimerHandler(unsigned long fcontext)
++{
++ PWLAN_DRV_TIMER timer = (PWLAN_DRV_TIMER) fcontext;
++
++ timer->timer_function(timer->function_context);
++
++ if (timer->timer_is_periodic == TRUE) {
++ mod_timer(&timer->tl, jiffies + ((timer->time_period * HZ) / 1000));
++ }
++}
++
++static inline void
++InitializeTimer(PWLAN_DRV_TIMER timer,
++ void (*TimerFunction) (void *context), void *FunctionContext)
++{
++ // first, setup the timer to trigger the WlanTimerHandler proxy
++ init_timer(&timer->tl);
++ timer->tl.function = TimerHandler;
++ timer->tl.data = (u32) timer;
++
++ // then tell the proxy which function to call and what to pass it
++ timer->timer_function = TimerFunction;
++ timer->function_context = FunctionContext;
++ timer->timer_is_canceled = FALSE;
++}
++
++static inline void
++SetTimer(PWLAN_DRV_TIMER timer, UINT MillisecondPeriod)
++{
++ timer->time_period = MillisecondPeriod;
++ timer->timer_is_periodic = FALSE;
++ timer->tl.expires = jiffies + (MillisecondPeriod * HZ) / 1000;
++ add_timer(&timer->tl);
++ timer->timer_is_canceled = FALSE;
++}
++
++static inline void
++ModTimer(PWLAN_DRV_TIMER timer, UINT MillisecondPeriod)
++{
++ timer->time_period = MillisecondPeriod;
++ timer->timer_is_periodic = FALSE;
++ mod_timer(&timer->tl, jiffies + (MillisecondPeriod * HZ) / 1000);
++ timer->timer_is_canceled = FALSE;
++}
++
++static inline void
++SetPeriodicTimer(PWLAN_DRV_TIMER timer, UINT MillisecondPeriod)
++{
++ timer->time_period = MillisecondPeriod;
++ timer->timer_is_periodic = TRUE;
++ timer->tl.expires = jiffies + (MillisecondPeriod * HZ) / 1000;
++ add_timer(&timer->tl);
++ timer->timer_is_canceled = FALSE;
++}
++
++#define FreeTimer(x) do {} while (0)
++
++static inline void
++CancelTimer(WLAN_DRV_TIMER * timer)
++{
++ del_timer(&timer->tl);
++ timer->timer_is_canceled = TRUE;
++}
++
++#endif /* _OS_TIMERS_H */
+diff --git a/drivers/net/wireless/marvell8686/release_version.h b/drivers/net/wireless/marvell8686/release_version.h
+new file mode 100644
+index 0000000..161da80
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/release_version.h
+@@ -0,0 +1,5 @@
++/**
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++
++#define DRIVER_RELEASE_VERSION "26409.p60"
+diff --git a/drivers/net/wireless/marvell8686/sbi.h b/drivers/net/wireless/marvell8686/sbi.h
+new file mode 100644
+index 0000000..65cf3f8
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/sbi.h
+@@ -0,0 +1,111 @@
++/** @file sbi.h
++ *
++ * @brief This file contains IF layer definitions.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 10/11/05: Add Doxygen format comments
++ 01/05/06: Add kernel 2.6.x support
++
++********************************************************/
++
++#ifndef _SBI_H_
++#define _SBI_H_
++
++/**Bit Definition*/
++#define B_BIT_0 0x01
++#define B_BIT_1 0x02
++#define B_BIT_2 0x04
++#define B_BIT_3 0x08
++#define B_BIT_4 0x10
++#define B_BIT_5 0x20
++#define B_BIT_6 0x40
++#define B_BIT_7 0x80
++#define B_BIT_8 0x100
++#define B_BIT_9 0X200
++#define B_BIT_10 0x400
++
++/** INT Status Bit Definition*/
++#define HIS_RxUpLdRdy B_BIT_0
++#define HIS_TxDnLdRdy B_BIT_1
++#define HIS_CmdDnLdRdy B_BIT_2
++#define HIS_CardEvent B_BIT_3
++#define HIS_CmdUpLdRdy B_BIT_4
++#define HIS_WrFifoOvrflow B_BIT_5
++#define HIS_RdFifoUndrflow B_BIT_6
++#define HIS_WlanReady B_BIT_7
++
++#define HIM_DISABLE 0xff
++#define HIM_ENABLE 0x03
++
++#define FIRMWARE_READY 0xfedc
++#ifndef DEV_NAME_LEN
++#define DEV_NAME_LEN 32
++#endif
++#define MAXKEYLEN 13
++
++/* The number of times to try when polling for status bits */
++#define MAX_POLL_TRIES 1000
++
++/* The number of times to try when waiting for downloaded firmware to
++ become active. (polling the scratch register). */
++
++#define MAX_FIRMWARE_POLL_TRIES 1000
++
++#define FIRMWARE_TRANSFER_NBLOCK 1
++#define SBI_EVENT_CAUSE_SHIFT 3
++
++typedef enum _mv_sd_type
++{
++ MVSD_DAT = 0,
++ MVSD_CMD = 1,
++ MVSD_EVENT = 3
++} mv_sd_type;
++
++/** Function Prototype Declaration */
++typedef wlan_private *(*wlan_notifier_fn_add) (void *dev_id);
++typedef int (*wlan_notifier_fn_remove) (void *dev_id);
++
++typedef IRQ_RET_TYPE(*isr_notifier_fn_t) (s32 irq, void *dev_id,
++ struct pt_regs * reg);
++typedef IRQ_RET_TYPE(*handler_fn_t) (s32 irq, void *dev_id, struct pt_regs *);
++
++/* Probe and Check if the card is present*/
++int sbi_probe_card(void *card);
++int *sbi_register(wlan_notifier_fn_add, wlan_notifier_fn_remove, void *);
++int sbi_register_dev(wlan_private * priv);
++int sbi_unregister_dev(wlan_private *);
++int sbi_disable_host_int(wlan_private * priv);
++int sbi_get_int_status(wlan_private * priv, u8 *);
++void sbi_unregister(void);
++int sbi_prog_firmware(wlan_private *);
++int sbi_verify_fw_download(wlan_private *);
++
++int sbi_prog_helper(wlan_private *);
++int sbi_prog_firmware_w_helper(wlan_private *);
++
++int sbi_read_event_cause(wlan_private *);
++int sbi_host_to_card(wlan_private * priv, u8 type, u8 * payload, u16 nb);
++int sbi_card_to_host(wlan_private * priv, u32 type, u32 * nb, u8 * payload,
++ u16 npayload);
++int sbi_enable_host_int(wlan_private *);
++
++int sbi_exit_deep_sleep(wlan_private *);
++int sbi_reset_deepsleep_wakeup(wlan_private *);
++#ifdef ENABLE_PM
++int sbi_suspend(wlan_private *);
++int sbi_resume(wlan_private *);
++#endif
++
++int sbi_read_ioreg(wlan_private * priv, u8 func, u32 reg, u8 * dat);
++int sbi_write_ioreg(wlan_private * priv, u8 func, u32 reg, u8 dat);
++int sbi_set_bus_clock(wlan_private * priv, u8 option);
++
++int sbi_get_cis_info(wlan_private * priv);
++
++int wlan_remove_card(void *card);
++wlan_private* wlan_add_card(void *card);
++
++#endif /* _SBI_H */
+diff --git a/drivers/net/wireless/marvell8686/sdio.h b/drivers/net/wireless/marvell8686/sdio.h
+new file mode 100644
+index 0000000..3e2e60d
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/sdio.h
+@@ -0,0 +1,112 @@
++/*File sdio.h
++ * This file contains the structure definations for the low level driver
++ * And the error response related code
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++
++#ifndef __SDIO_H__
++#define __SDIO_H__
++
++#include <linux/spinlock.h> /* For read write semaphores */
++#include <asm/semaphore.h>
++#include <linux/completion.h>
++#include <asm/dma.h>
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++ #include <linux/proc_fs.h>
++#endif
++
++#include "os_defs.h"
++
++#ifdef DEBUG_SDIO_LEVEL2
++#ifndef DEBUG_LEVEL1
++#define DEBUG_LEVEL1
++#endif
++#define _ENTER() printk(KERN_DEBUG "Enter: %s, %s linux %i\n", __FUNCTION__, \
++ __FILE__, __LINE__)
++#define _LEAVE() printk(KERN_DEBUG "Leave: %s, %s linux %i\n", __FUNCTION__, \
++ __FILE__, __LINE__)
++#else
++#define _ENTER()
++#define _LEAVE()
++#endif
++
++#ifdef DEBUG_SDIO_LEVEL1
++#define _DBGMSG(x...) printk(KERN_DEBUG x)
++#define _WARNING(x...) printk(KERN_DEBUG x)
++#else
++#define _DBGMSG(x...)
++#define _WARNING(x...)
++#endif
++
++#ifdef DEBUG_SDIO_LEVEL0
++#define _PRINTK(x...) printk(x)
++#define _ERROR(x...) printk(KERN_ERR x)
++#else
++#define _PRINTK(x...)
++#define _ERROR(x...)
++#endif
++
++typedef struct _card_capability
++{
++ u8 num_of_io_funcs; /* Number of i/o functions */
++ u8 memory_yes; /* Memory present ? */
++ u16 rca; /* Relative Card Address */
++ u32 ocr; /* Operation Condition register */
++ u16 fnblksz[8];
++ u32 cisptr[8];
++} card_capability;
++
++typedef struct _dummy_tmpl
++{
++ int irq_line;
++} dummy_tmpl;
++
++typedef struct _sdio_host *mmc_controller_t;
++
++typedef enum _sdio_fsm
++{
++ SDIO_FSM_IDLE = 1,
++ SDIO_FSM_CLK_OFF,
++ SDIO_FSM_END_CMD,
++ SDIO_FSM_BUFFER_IN_TRANSIT,
++ SDIO_FSM_END_BUFFER,
++ SDIO_FSM_END_IO,
++ SDIO_FSM_END_PRG,
++ SDIO_FSM_ERROR
++} sdio_fsm_state;
++
++typedef struct _sdio_host
++{
++ char name[16];
++ int bus_width;
++} __attribute__ ((aligned)) sdio_ctrller;
++
++typedef struct _sdio_operations
++{
++ char name[16];
++} sdio_operations;
++
++typedef struct _iorw_extended_t
++{
++ u8 rw_flag; /** If 0 command is READ; else if 1 command is WRITE */
++ u8 func_num;
++ u8 blkmode;
++ u8 op_code;
++ u32 reg_addr;
++ u32 byte_cnt;
++ u32 blk_size;
++ u8 *buf;
++} iorw_extended_t;
++
++#define BUS_INTERFACE_CONTROL_REG 0x07
++#define CARD_CAPABILITY_REG 0x08
++#define COMMON_CIS_POINTER_0_REG 0x09
++#define COMMON_CIS_POINTER_1_REG 0x0a
++#define COMMON_CIS_POINTER_2_REG 0x0b
++#define BUS_SUSPEND_REG 0x0c
++#define FUNCTION_SELECT_REG 0x0d
++#define EXEC_FLAGS_REG 0x0e
++#define READY_FLAGS_REG 0x0f
++
++#endif /* __SDIO__H */
+diff --git a/drivers/net/wireless/marvell8686/wlan_11d.c b/drivers/net/wireless/marvell8686/wlan_11d.c
+new file mode 100644
+index 0000000..0dbcf49
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_11d.c
+@@ -0,0 +1,893 @@
++/** @file wlan_11d.c
++ * @brief This file contains functions for 802.11D.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 10/04/05: Add Doxygen format comments
++
++********************************************************/
++#include "include.h"
++
++/********************************************************
++ Local Variables
++********************************************************/
++#define TX_PWR_DEFAULT 10
++
++static region_code_mapping_t region_code_mapping[] = {
++ {"US ", 0x10}, /* US FCC */
++ {"CA ", 0x20}, /* IC Canada */
++ {"SG ", 0x10}, /* Singapore */
++ {"EU ", 0x30}, /* ETSI */
++ {"AU ", 0x30}, /* Australia */
++ {"KR ", 0x30}, /* Republic Of Korea */
++ {"FR ", 0x32}, /* France */
++ {"JP ", 0x40}, /* Japan */
++ {"JP ", 0x41}, /* Japan */
++};
++
++/********************************************************
++ Global Variables
++********************************************************/
++/* Following 2 structure defines the supported channels */
++CHANNEL_FREQ_POWER channel_freq_power_UN_BG[] = {
++ {1, 2412, TX_PWR_DEFAULT},
++ {2, 2417, TX_PWR_DEFAULT},
++ {3, 2422, TX_PWR_DEFAULT},
++ {4, 2427, TX_PWR_DEFAULT},
++ {5, 2432, TX_PWR_DEFAULT},
++ {6, 2437, TX_PWR_DEFAULT},
++ {7, 2442, TX_PWR_DEFAULT},
++ {8, 2447, TX_PWR_DEFAULT},
++ {9, 2452, TX_PWR_DEFAULT},
++ {10, 2457, TX_PWR_DEFAULT},
++ {11, 2462, TX_PWR_DEFAULT},
++ {12, 2467, TX_PWR_DEFAULT},
++ {13, 2472, TX_PWR_DEFAULT},
++ {14, 2484, TX_PWR_DEFAULT}
++};
++
++CHANNEL_FREQ_POWER channel_freq_power_UN_AJ[] = {
++ {8, 5040, TX_PWR_DEFAULT},
++ {12, 5060, TX_PWR_DEFAULT},
++ {16, 5080, TX_PWR_DEFAULT},
++ {34, 5170, TX_PWR_DEFAULT},
++ {38, 5190, TX_PWR_DEFAULT},
++ {42, 5210, TX_PWR_DEFAULT},
++ {46, 5230, TX_PWR_DEFAULT},
++ {36, 5180, TX_PWR_DEFAULT},
++ {40, 5200, TX_PWR_DEFAULT},
++ {44, 5220, TX_PWR_DEFAULT},
++ {48, 5240, TX_PWR_DEFAULT},
++ {52, 5260, TX_PWR_DEFAULT},
++ {56, 5280, TX_PWR_DEFAULT},
++ {60, 5300, TX_PWR_DEFAULT},
++ {64, 5320, TX_PWR_DEFAULT},
++ {100, 5500, TX_PWR_DEFAULT},
++ {104, 5520, TX_PWR_DEFAULT},
++ {108, 5540, TX_PWR_DEFAULT},
++ {112, 5560, TX_PWR_DEFAULT},
++ {116, 5580, TX_PWR_DEFAULT},
++ {120, 5600, TX_PWR_DEFAULT},
++ {124, 5620, TX_PWR_DEFAULT},
++ {128, 5640, TX_PWR_DEFAULT},
++ {132, 5660, TX_PWR_DEFAULT},
++ {136, 5680, TX_PWR_DEFAULT},
++ {140, 5700, TX_PWR_DEFAULT},
++ {149, 5745, TX_PWR_DEFAULT},
++ {153, 5765, TX_PWR_DEFAULT},
++ {157, 5785, TX_PWR_DEFAULT},
++ {161, 5805, TX_PWR_DEFAULT},
++ {165, 5825, TX_PWR_DEFAULT},
++/* {240, 4920, TX_PWR_DEFAULT},
++ {244, 4940, TX_PWR_DEFAULT},
++ {248, 4960, TX_PWR_DEFAULT},
++ {252, 4980, TX_PWR_DEFAULT},
++channels for 11J JP 10M channel gap */
++};
++
++extern CHANNEL_FREQ_POWER *wlan_get_region_cfp_table(u8 region,
++ u8 band, int *cfp_no);
++
++/********************************************************
++ Local Functions
++********************************************************/
++/**
++ * @brief This function convert Region string to code integer
++ * @param region region string
++ * @return region id
++*/
++static u8
++wlan_region_2_code(s8 * region)
++{
++ u8 i;
++ u8 size = sizeof(region_code_mapping) / sizeof(region_code_mapping_t);
++
++ for (i = 0; i < COUNTRY_CODE_LEN && region[i]; i++)
++ region[i] = toupper(region[i]);
++
++ for (i = 0; i < size; i++) {
++ if (!memcmp(region, region_code_mapping[i].region, COUNTRY_CODE_LEN))
++ return (region_code_mapping[i].code);
++ }
++
++ /* default is US */
++ return (region_code_mapping[0].code);
++}
++
++/**
++ * @brief This function converts interger code to region string
++ * @param code region code
++ * @return region string
++*/
++static u8 *
++wlan_code_2_region(u8 code)
++{
++ u8 i;
++ u8 size = sizeof(region_code_mapping) / sizeof(region_code_mapping_t);
++ for (i = 0; i < size; i++) {
++ if (region_code_mapping[i].code == code)
++ return (region_code_mapping[i].region);
++ }
++ /* default is US */
++ return (region_code_mapping[0].region);
++}
++
++/**
++ * @brief This function finds the NoOfChan-th chan after the firstChan
++ * @param band band
++ * @param firstChan first channel number
++ * @param NoOfChan number of channels
++ * @return the NoOfChan-th chan number
++*/
++static BOOLEAN
++wlan_get_chan_11d(u8 band, u8 firstChan, u8 NoOfChan, u8 * chan)
++/*find the NoOfChan-th chan after the firstChan*/
++{
++ u8 i;
++ CHANNEL_FREQ_POWER *cfp;
++ u8 cfp_no;
++
++ ENTER();
++
++ {
++ cfp = channel_freq_power_UN_BG;
++ cfp_no = sizeof(channel_freq_power_UN_BG) /
++ sizeof(CHANNEL_FREQ_POWER);
++ }
++
++ for (i = 0; i < cfp_no; i++) {
++ if ((cfp + i)->Channel == firstChan) {
++ PRINTM(INFO, "firstChan found\n");
++ break;
++ }
++ }
++
++ if (i < cfp_no) {
++ /*if beyond the boundary */
++ if (i + NoOfChan < cfp_no) {
++ *chan = (cfp + i + NoOfChan)->Channel;
++ return TRUE;
++ }
++ }
++
++ LEAVE();
++ return FALSE;
++}
++
++/**
++ * @brief This function Checks if chan txpwr is learned from AP/IBSS
++ * @param chan chan number
++ * @param parsed_region_chan pointer to parsed_region_chan_11d_t
++ * @return TRUE; FALSE
++*/
++BOOLEAN
++wlan_channel_known_11d(u8 chan, parsed_region_chan_11d_t * parsed_region_chan)
++{
++ chan_power_11d_t *chanPwr = parsed_region_chan->chanPwr;
++ u8 NoOfChan = parsed_region_chan->NoOfChan;
++ u8 i = 0;
++
++ ENTER();
++ HEXDUMP("11D:parsed_region_chan:", (char *) chanPwr,
++ sizeof(chan_power_11d_t) * NoOfChan);
++
++ for (i = 0; i < NoOfChan; i++) {
++ if (chan == chanPwr[i].chan) {
++ PRINTM(INFO, "11D: Found Chan:%d\n", chan);
++ LEAVE();
++ return TRUE;
++ }
++ }
++
++ PRINTM(INFO, "11D: Not Find Chan:%d\n", chan);
++ LEAVE();
++ return FALSE;
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief This function Converts chan to frequency
++ * @param chan channel number
++ * @param band band
++ * @return channel frequency
++*/
++u32
++chan_2_freq(u8 chan, u8 band)
++{
++ CHANNEL_FREQ_POWER *cf;
++ u16 cnt;
++ u16 i;
++ u32 freq = 0;
++
++ ENTER();
++
++ {
++ cf = channel_freq_power_UN_BG;
++ cnt = sizeof(channel_freq_power_UN_BG) / sizeof(CHANNEL_FREQ_POWER);
++ }
++
++ for (i = 0; i < cnt; i++) {
++ if (chan == cf[i].Channel)
++ freq = cf[i].Freq;
++ }
++
++ LEAVE();
++ return freq;
++}
++
++/**
++ * @brief This function generates domaininfo from parsed_region_chan
++ * @param parsed_region_chan pointer to parsed_region_chan_11d_t
++ * @param domaininfo pointer to wlan_802_11d_domain_reg_t
++ * @return WLAN_STATUS_SUCCESS
++*/
++int
++wlan_generate_domain_info_11d(parsed_region_chan_11d_t * parsed_region_chan,
++ wlan_802_11d_domain_reg_t * domaininfo)
++{
++ u8 NoOfSubband = 0;
++
++ u8 NoOfChan = parsed_region_chan->NoOfChan;
++ u8 NoOfParsedChan = 0;
++
++ u8 firstChan = 0, nextChan = 0, maxPwr = 0;
++
++ u8 i, flag = 0;
++
++ ENTER();
++
++ memcpy(domaininfo->CountryCode, parsed_region_chan->CountryCode,
++ COUNTRY_CODE_LEN);
++
++ PRINTM(INFO, "11D:NoOfChan=%d\n", NoOfChan);
++ HEXDUMP("11D:parsed_region_chan:", (char *) parsed_region_chan,
++ sizeof(parsed_region_chan_11d_t));
++
++ for (i = 0; i < NoOfChan; i++) {
++ if (!flag) {
++ flag = 1;
++ nextChan = firstChan = parsed_region_chan->chanPwr[i].chan;
++ maxPwr = parsed_region_chan->chanPwr[i].pwr;
++ NoOfParsedChan = 1;
++ continue;
++ }
++
++ if (parsed_region_chan->chanPwr[i].chan == nextChan + 1 &&
++ parsed_region_chan->chanPwr[i].pwr == maxPwr) {
++ nextChan++;
++ NoOfParsedChan++;
++ } else {
++ domaininfo->Subband[NoOfSubband].FirstChan = firstChan;
++ domaininfo->Subband[NoOfSubband].NoOfChan = NoOfParsedChan;
++ domaininfo->Subband[NoOfSubband].MaxTxPwr = maxPwr;
++ NoOfSubband++;
++ NoOfParsedChan = 1;
++ nextChan = firstChan = parsed_region_chan->chanPwr[i].chan;
++ maxPwr = parsed_region_chan->chanPwr[i].pwr;
++ }
++ }
++
++ if (flag) {
++ domaininfo->Subband[NoOfSubband].FirstChan = firstChan;
++ domaininfo->Subband[NoOfSubband].NoOfChan = NoOfParsedChan;
++ domaininfo->Subband[NoOfSubband].MaxTxPwr = maxPwr;
++ NoOfSubband++;
++ }
++ domaininfo->NoOfSubband = NoOfSubband;
++
++ PRINTM(INFO, "NoOfSubband=%x\n", domaininfo->NoOfSubband);
++ HEXDUMP("11D:domaininfo:", (char *) domaininfo,
++ COUNTRY_CODE_LEN + 1 +
++ sizeof(IEEEtypes_SubbandSet_t) * NoOfSubband);
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function generates parsed_region_chan from Domain Info learned from AP/IBSS
++ * @param region_chan pointer to REGION_CHANNEL
++ * @param *parsed_region_chan pointer to parsed_region_chan_11d_t
++ * @return N/A
++*/
++void
++wlan_generate_parsed_region_chan_11d(REGION_CHANNEL * region_chan,
++ parsed_region_chan_11d_t *
++ parsed_region_chan)
++{
++ u8 i;
++ CHANNEL_FREQ_POWER *cfp;
++
++ ENTER();
++
++ if (region_chan == NULL) {
++ PRINTM(INFO, "11D: region_chan is NULL\n");
++ return;
++ }
++
++ cfp = region_chan->CFP;
++ if (cfp == NULL) {
++ PRINTM(INFO, "11D: cfp equal NULL \n");
++ return;
++ }
++
++ parsed_region_chan->band = region_chan->Band;
++ parsed_region_chan->region = region_chan->Region;
++ memcpy(parsed_region_chan->CountryCode,
++ wlan_code_2_region(region_chan->Region), COUNTRY_CODE_LEN);
++
++ PRINTM(INFO, "11D: region[0x%x] band[%d]\n", parsed_region_chan->region,
++ parsed_region_chan->band);
++
++ for (i = 0; i < region_chan->NrCFP; i++, cfp++) {
++ parsed_region_chan->chanPwr[i].chan = cfp->Channel;
++ parsed_region_chan->chanPwr[i].pwr = cfp->MaxTxPower;
++ PRINTM(INFO, "11D: Chan[%d] Pwr[%d]\n",
++ parsed_region_chan->chanPwr[i].chan,
++ parsed_region_chan->chanPwr[i].pwr);
++ }
++ parsed_region_chan->NoOfChan = region_chan->NrCFP;
++
++ PRINTM(INFO, "11D: NoOfChan[%d]\n", parsed_region_chan->NoOfChan);
++
++ LEAVE();
++ return;
++}
++
++/**
++ * @brief generate parsed_region_chan from Domain Info learned from AP/IBSS
++ * @param region region ID
++ * @param band band
++ * @param chan chan
++ * @return TRUE;FALSE
++*/
++BOOLEAN
++wlan_region_chan_supported_11d(u8 region, u8 band, u8 chan)
++{
++ CHANNEL_FREQ_POWER *cfp;
++ int cfp_no;
++ u8 idx;
++
++ ENTER();
++
++ if ((cfp = wlan_get_region_cfp_table(region, band, &cfp_no)) == NULL) {
++ return FALSE;
++ }
++
++ for (idx = 0; idx < cfp_no; idx++) {
++ if (chan == (cfp + idx)->Channel) {
++ /* If Mrvl Chip Supported? */
++ if ((cfp + idx)->Unsupported) {
++ return FALSE;
++ } else {
++ return TRUE;
++ }
++ }
++ }
++
++ /*chan is not in the region table */
++ LEAVE();
++ return FALSE;
++}
++
++/**
++ * @brief This function checks if chan txpwr is learned from AP/IBSS
++ * @param chan chan number
++ * @param parsed_region_chan pointer to parsed_region_chan_11d_t
++ * @return WLAN_STATUS_SUCCESS
++*/
++int
++wlan_parse_domain_info_11d(IEEEtypes_CountryInfoFullSet_t * CountryInfo,
++ u8 band,
++ parsed_region_chan_11d_t * parsed_region_chan)
++{
++ u8 NoOfSubband, NoOfChan;
++ u8 lastChan, firstChan, curChan;
++ u8 region;
++
++ u8 idx = 0; /*chan index in parsed_region_chan */
++
++ u8 j, i;
++
++ ENTER();
++
++ /*Validation Rules:
++ 1. Valid Region Code
++ 2. First Chan increment
++ 3. Channel range no overlap
++ 4. Channel is valid?
++ 5. Channel is supported by Region?
++ 6. Others
++ */
++
++ HEXDUMP("CountryInfo:", (s8 *) CountryInfo, 30);
++
++ if ((*(CountryInfo->CountryCode)) == 0 ||
++ (CountryInfo->Len <= COUNTRY_CODE_LEN)) {
++ /* No region Info or Wrong region info: treat as No 11D info */
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ /*Step1: check region_code */
++ parsed_region_chan->region = region =
++ wlan_region_2_code((s8 *) CountryInfo->CountryCode);
++
++ PRINTM(INFO, "regioncode=%x\n", (u8) parsed_region_chan->region);
++ HEXDUMP("CountryCode:", (char *) CountryInfo->CountryCode,
++ COUNTRY_CODE_LEN);
++
++ parsed_region_chan->band = band;
++
++ memcpy(parsed_region_chan->CountryCode, CountryInfo->CountryCode,
++ COUNTRY_CODE_LEN);
++
++ NoOfSubband = (CountryInfo->Len - COUNTRY_CODE_LEN) /
++ sizeof(IEEEtypes_SubbandSet_t);
++
++ for (j = 0, lastChan = 0; j < NoOfSubband; j++) {
++
++ if (CountryInfo->Subband[j].FirstChan <= lastChan) {
++ /*Step2&3. Check First Chan Num increment and no overlap */
++ PRINTM(INFO, "11D: Chan[%d>%d] Overlap\n",
++ CountryInfo->Subband[j].FirstChan, lastChan);
++ continue;
++ }
++
++ firstChan = CountryInfo->Subband[j].FirstChan;
++ NoOfChan = CountryInfo->Subband[j].NoOfChan;
++
++ for (i = 0; idx < MAX_NO_OF_CHAN && i < NoOfChan; i++) {
++ /*step4: channel is supported? */
++
++ if (wlan_get_chan_11d(band, firstChan, i, &curChan)
++ == FALSE) {
++ /* Chan is not found in UN table */
++ PRINTM(INFO, "chan is not supported: %d \n", i);
++ break;
++ }
++
++ lastChan = curChan;
++
++ /*step5: We don't need to Check if curChan is supported by mrvl in region */
++ parsed_region_chan->chanPwr[idx].chan = curChan;
++ parsed_region_chan->chanPwr[idx].pwr =
++ CountryInfo->Subband[j].MaxTxPwr;
++ idx++;
++ }
++
++ /*Step6: Add other checking if any */
++
++ }
++
++ parsed_region_chan->NoOfChan = idx;
++
++ PRINTM(INFO, "NoOfChan=%x\n", parsed_region_chan->NoOfChan);
++ HEXDUMP("11D:parsed_region_chan:", (s8 *) parsed_region_chan,
++ 2 + COUNTRY_CODE_LEN + sizeof(parsed_region_chan_11d_t) * idx);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function calculates the scan type for channels
++ * @param chan chan number
++ * @param parsed_region_chan pointer to parsed_region_chan_11d_t
++ * @return PASSIVE if chan is unknown; ACTIVE if chan is known
++*/
++u8
++wlan_get_scan_type_11d(u8 chan, parsed_region_chan_11d_t * parsed_region_chan)
++{
++ u8 scan_type = HostCmd_SCAN_TYPE_PASSIVE;
++
++ ENTER();
++
++ if (wlan_channel_known_11d(chan, parsed_region_chan)) {
++ PRINTM(INFO, "11D: Found and do Active Scan\n");
++ scan_type = HostCmd_SCAN_TYPE_ACTIVE;
++ } else {
++ PRINTM(INFO, "11D: Not Find and do Passive Scan\n");
++ }
++
++ LEAVE();
++ return scan_type;
++
++}
++
++/**
++ * @brief This function gets if 11D is enabled
++ * @param priv pointer to wlan_private
++ * @return ENABLE_11D;DISABLE_11D
++*/
++state_11d_t
++wlan_get_state_11d(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_802_11d_state_t *state = &Adapter->State11D;
++ return (state->Enable11D);
++}
++
++/**
++ * @brief initialize internal variable for 11D
++ * @param priv pointer to wlan_private
++ * @return N/A
++*/
++void
++wlan_init_11d(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_802_11d_state_t *state = &Adapter->State11D;
++
++ state->Enable11D = DISABLE_11D;
++
++ memset(&(priv->adapter->parsed_region_chan), 0,
++ sizeof(parsed_region_chan_11d_t));
++
++ return;
++}
++
++/**
++ * @brief This function enable/disable 11D
++ * @param priv pointer to wlan_private
++ * @param flag enable/disable flag
++ * @return WLAN_STATUS_SUCCESS; WLAN_STATUS_FAILURE
++*/
++int
++wlan_enable_11d(wlan_private * priv, state_11d_t flag)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_802_11d_state_t *state = &Adapter->State11D;
++ int ret;
++ state_11d_t enable = flag;
++
++ ENTER();
++
++ state->Enable11D = flag;
++
++ /* send cmd to FW to enable/disable 11D fucntion in FW */
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SNMP_MIB,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP,
++ OID_802_11D_ENABLE, &enable);
++ if (ret) {
++ PRINTM(INFO, "11D: Fail to enable 11D \n");
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function sets DOMAIN INFO to FW
++ * @param priv pointer to wlan_private
++ * @return WLAN_STATUS_SUCCESS; WLAN_STATUS_FAILURE
++*/
++int
++wlan_set_domain_info_11d(wlan_private * priv)
++{
++ int ret;
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11D_DOMAIN_INFO,
++ HostCmd_ACT_GEN_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++ if (ret) {
++ PRINTM(INFO, "11D: Fail to dnld domain Info\n");
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function setups scan channels
++ * @param priv pointer to wlan_private
++ * @param band band
++ * @return WLAN_STATUS_SUCCESS
++*/
++int
++wlan_set_universaltable(wlan_private * priv, u8 band)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ u16 size = sizeof(CHANNEL_FREQ_POWER);
++ u16 i = 0;
++
++ ENTER();
++
++ memset(Adapter->universal_channel, 0, sizeof(Adapter->universal_channel));
++
++ {
++ Adapter->universal_channel[i].NrCFP =
++ sizeof(channel_freq_power_UN_BG) / size;
++ PRINTM(INFO, "11D: BG-band NrCFP=%d\n",
++ Adapter->universal_channel[i].NrCFP);
++
++ Adapter->universal_channel[i].CFP = channel_freq_power_UN_BG;
++ Adapter->universal_channel[i].Valid = TRUE;
++ Adapter->universal_channel[i].Region = UNIVERSAL_REGION_CODE;
++ Adapter->universal_channel[i].Band = band;
++ i++;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function implements command CMD_802_11D_DOMAIN_INFO
++ * @param priv pointer to wlan_private
++ * @param cmd pointer to cmd buffer
++ * @param cmdno cmd ID
++ * @param CmdOption cmd action
++ * @return WLAN_STATUS_SUCCESS
++*/
++int
++wlan_cmd_802_11d_domain_info(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u16 cmdno,
++ u16 CmdOption)
++{
++ HostCmd_DS_802_11D_DOMAIN_INFO *pDomainInfo = &cmd->params.domaininfo;
++ MrvlIEtypes_DomainParamSet_t *domain = &pDomainInfo->Domain;
++ wlan_adapter *Adapter = priv->adapter;
++ u8 NoOfSubband = Adapter->DomainReg.NoOfSubband;
++
++ ENTER();
++
++ PRINTM(INFO, "NoOfSubband=%x\n", NoOfSubband);
++
++ cmd->Command = wlan_cpu_to_le16(cmdno);
++ pDomainInfo->Action = wlan_cpu_to_le16(CmdOption);
++ if (CmdOption == HostCmd_ACT_GET) {
++ cmd->Size = wlan_cpu_to_le16(sizeof(pDomainInfo->Action) + S_DS_GEN);
++ HEXDUMP("11D: 802_11D_DOMAIN_INFO:", (u8 *) cmd, (int) (cmd->Size));
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ domain->Header.Type = wlan_cpu_to_le16(TLV_TYPE_DOMAIN);
++ memcpy(domain->CountryCode, Adapter->DomainReg.CountryCode,
++ sizeof(domain->CountryCode));
++
++ domain->Header.Len =
++ wlan_cpu_to_le16(NoOfSubband * sizeof(IEEEtypes_SubbandSet_t) +
++ sizeof(domain->CountryCode));
++
++ if (NoOfSubband) {
++ memcpy(domain->Subband, Adapter->DomainReg.Subband,
++ NoOfSubband * sizeof(IEEEtypes_SubbandSet_t));
++
++ cmd->Size = wlan_cpu_to_le16(sizeof(pDomainInfo->Action) +
++ domain->Header.Len +
++ sizeof(MrvlIEtypesHeader_t) + S_DS_GEN);
++ } else {
++ cmd->Size = wlan_cpu_to_le16(sizeof(pDomainInfo->Action) + S_DS_GEN);
++ }
++
++ HEXDUMP("11D:802_11D_DOMAIN_INFO:", (u8 *) cmd, (int) (cmd->Size));
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function implements private cmd: enable/disable 11D
++ * @param priv pointer to wlan_private
++ * @param wrq pointer to user data
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_enable_11d(wlan_private * priv, struct iwreq *wrq)
++{
++ int data = 0;
++ int *val;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++
++ PRINTM(INFO, "Enable 11D: %s\n",
++ (data == CMD_ENABLED) ? "Enable" : "Disable");
++ switch (data) {
++ case CMD_ENABLED:
++ wlan_enable_11d(priv, ENABLE_11D);
++ break;
++ case CMD_DISABLED:
++ wlan_enable_11d(priv, DISABLE_11D);
++ break;
++ default:
++ break;
++ }
++
++ data =
++ (Adapter->State11D.Enable11D ==
++ ENABLE_11D) ? CMD_ENABLED : CMD_DISABLED;
++ val = (int *) wrq->u.name;
++ *val = data;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function parses countryinfo from AP and download country info to FW
++ * @param priv pointer to wlan_private
++ * @param resp pointer to command response buffer
++ * @return WLAN_STATUS_SUCCESS; WLAN_STATUS_FAILURE
++ */
++int
++wlan_ret_802_11d_domain_info(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11D_DOMAIN_INFO_RSP
++ * domaininfo = &resp->params.domaininforesp;
++ MrvlIEtypes_DomainParamSet_t * domain = &domaininfo->Domain;
++ u16 Action = wlan_le16_to_cpu(domaininfo->Action);
++ s16 ret = WLAN_STATUS_SUCCESS;
++ u8 NoOfSubband = 0;
++
++ ENTER();
++
++ HEXDUMP("11D DOMAIN Info Rsp Data:", (u8 *) resp, resp->Size);
++
++ NoOfSubband =
++ (wlan_le16_to_cpu(domain->Header.Len) -
++ 3) / sizeof(IEEEtypes_SubbandSet_t);
++ /* countrycode 3 bytes */
++
++ PRINTM(INFO, "11D Domain Info Resp: NoOfSubband=%d\n", NoOfSubband);
++
++ if (NoOfSubband > MRVDRV_MAX_SUBBAND_802_11D) {
++ PRINTM(INFO, "Invalid Numrer of Subband returned!!\n");
++ return WLAN_STATUS_FAILURE;
++ }
++
++ switch (Action) {
++ case HostCmd_ACT_SET: /*Proc Set Action */
++ break;
++
++ case HostCmd_ACT_GET:
++ break;
++ default:
++ PRINTM(INFO, "Invalid Action:%d\n", domaininfo->Action);
++ ret = WLAN_STATUS_FAILURE;
++ break;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function parses countryinfo from AP and download country info to FW
++ * @param priv pointer to wlan_private
++ * @return WLAN_STATUS_SUCCESS; WLAN_STATUS_FAILURE
++ */
++int
++wlan_parse_dnld_countryinfo_11d(wlan_private * priv)
++{
++ int ret;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ /* Skip new 11d download when roaming */
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ if (wlan_get_state_11d(priv) == ENABLE_11D) {
++
++ memset(&Adapter->parsed_region_chan, 0,
++ sizeof(parsed_region_chan_11d_t));
++
++ ret =
++ wlan_parse_domain_info_11d(&Adapter->pAttemptedBSSDesc->
++ CountryInfo, 0,
++ &Adapter->parsed_region_chan);
++
++ if (ret == WLAN_STATUS_FAILURE) {
++ PRINTM(INFO, "11D: No region info in the AP BssDesc..\n");
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ memset(&Adapter->DomainReg, 0, sizeof(wlan_802_11d_domain_reg_t));
++ wlan_generate_domain_info_11d(&Adapter->parsed_region_chan,
++ &Adapter->DomainReg);
++
++ ret = wlan_set_domain_info_11d(priv);
++
++ if (ret) {
++ PRINTM(INFO, "11D: Err set domainInfo to FW\n");
++ LEAVE();
++ return ret;
++ }
++ }
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function generates 11D info from user specified regioncode and download to FW
++ * @param priv pointer to wlan_private
++ * @return WLAN_STATUS_SUCCESS; WLAN_STATUS_FAILURE
++ */
++int
++wlan_create_dnld_countryinfo_11d(wlan_private * priv, u8 band)
++{
++ int ret;
++ wlan_adapter *Adapter = priv->adapter;
++ REGION_CHANNEL *region_chan;
++ u8 j;
++
++ ENTER();
++ PRINTM(INFO, "11D:Band[%d]\n", band);
++
++ /* update parsed_region_chan_11; dnld domaininf to FW */
++
++ for (j = 0; j < sizeof(Adapter->region_channel) /
++ sizeof(Adapter->region_channel[0]); j++) {
++ region_chan = &Adapter->region_channel[j];
++
++ PRINTM(INFO, "11D:[%d] region_chan->Band[%d]\n", j,
++ region_chan->Band);
++
++ if (!region_chan || !region_chan->Valid || !region_chan->CFP)
++ continue;
++ if (region_chan->Band != band)
++ continue;
++ break;
++ }
++
++ if (j >= sizeof(Adapter->region_channel) /
++ sizeof(Adapter->region_channel[0])) {
++ PRINTM(INFO, "11D:region_chan not found. Band[%d]\n", band);
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ memset(&Adapter->parsed_region_chan, 0, sizeof(parsed_region_chan_11d_t));
++ wlan_generate_parsed_region_chan_11d(region_chan,
++ &Adapter->parsed_region_chan);
++
++ memset(&Adapter->DomainReg, 0, sizeof(wlan_802_11d_domain_reg_t));
++ wlan_generate_domain_info_11d(&Adapter->parsed_region_chan,
++ &Adapter->DomainReg);
++
++ ret = wlan_set_domain_info_11d(priv);
++
++ if (ret) {
++ PRINTM(INFO, "11D: Err set domainInfo to FW\n");
++ LEAVE();
++ return ret;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_11d.h b/drivers/net/wireless/marvell8686/wlan_11d.h
+new file mode 100644
+index 0000000..208f64b
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_11d.h
+@@ -0,0 +1,110 @@
++/** @file wlan_11d.h
++ * @brief This header file contains data structures and
++ * function declarations of 802.11d
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/*************************************************************
++Change log:
++ 09/26/05: add Doxygen format comments
++ ************************************************************/
++
++#ifndef _WLAN_11D_
++#define _WLAN_11D_
++
++#define MAX_CHAN_NUM 255
++
++#define UNIVERSAL_REGION_CODE 0xff
++
++/** (Beaconsize(256)-5(IEId,len,contrystr(3))/3(FirstChan,NoOfChan,MaxPwr)
++ */
++#define MAX_NO_OF_CHAN 40
++
++typedef struct _REGION_CHANNEL *PREGION_CHANNEL;
++
++typedef enum
++{
++ DISABLE_11D = 0,
++ ENABLE_11D = 1,
++} state_11d_t;
++
++/** domain regulatory information */
++typedef struct _wlan_802_11d_domain_reg
++{
++ /** country Code*/
++ u8 CountryCode[COUNTRY_CODE_LEN];
++ /** No. of subband*/
++ u8 NoOfSubband;
++ IEEEtypes_SubbandSet_t Subband[MRVDRV_MAX_SUBBAND_802_11D];
++} wlan_802_11d_domain_reg_t;
++
++typedef struct _chan_power_11d
++{
++ u8 chan;
++ u8 pwr;
++} __ATTRIB_PACK__ chan_power_11d_t;
++
++typedef struct _parsed_region_chan_11d
++{
++ u8 band;
++ u8 region;
++ s8 CountryCode[COUNTRY_CODE_LEN];
++ chan_power_11d_t chanPwr[MAX_NO_OF_CHAN];
++ u8 NoOfChan;
++} __ATTRIB_PACK__ parsed_region_chan_11d_t;
++
++/** Data for state machine */
++typedef struct _wlan_802_11d_state
++{
++ /** True for Enabling 11D*/
++ BOOLEAN Enable11D;
++} wlan_802_11d_state_t;
++
++typedef struct _region_code_mapping
++{
++ s8 region[COUNTRY_CODE_LEN];
++ u8 code;
++} region_code_mapping_t;
++
++/* function prototypes*/
++int wlan_generate_domain_info_11d(parsed_region_chan_11d_t *
++ parsed_region_chan,
++ wlan_802_11d_domain_reg_t * domaininfo);
++
++int wlan_parse_domain_info_11d(IEEEtypes_CountryInfoFullSet_t * CountryInfo,
++ u8 band,
++ parsed_region_chan_11d_t * parsed_region_chan);
++
++u8 wlan_get_scan_type_11d(u8 chan,
++ parsed_region_chan_11d_t * parsed_region_chan);
++
++u32 chan_2_freq(u8 chan, u8 band);
++
++int wlan_set_domain_info_11d(wlan_private * priv);
++
++state_11d_t wlan_get_state_11d(wlan_private * priv);
++
++void wlan_init_11d(wlan_private * priv);
++
++int wlan_enable_11d(wlan_private * priv, state_11d_t flag);
++
++int wlan_set_universaltable(wlan_private * priv, u8 band);
++
++void wlan_generate_parsed_region_chan_11d(PREGION_CHANNEL region_chan,
++ parsed_region_chan_11d_t *
++ parsed_region_chan);
++
++int wlan_cmd_802_11d_domain_info(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u16 cmdno,
++ u16 CmdOption);
++
++int wlan_cmd_enable_11d(wlan_private * priv, struct iwreq *wrq);
++
++int wlan_ret_802_11d_domain_info(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp);
++
++int wlan_parse_dnld_countryinfo_11d(wlan_private * priv);
++
++int wlan_create_dnld_countryinfo_11d(wlan_private * priv, u8 band);
++
++#endif /* _WLAN_11D_ */
+diff --git a/drivers/net/wireless/marvell8686/wlan_cmd.c b/drivers/net/wireless/marvell8686/wlan_cmd.c
+new file mode 100644
+index 0000000..2d5bf55
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_cmd.c
+@@ -0,0 +1,2501 @@
++/** @file wlan_cmd.c
++ *
++ * @brief This file contains the handling of command.
++ * it prepares command and sends it to firmware when
++ * it is ready.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ *
++ */
++/********************************************************
++Change log:
++ 10/04/05: Add Doxygen format comments
++ 01/05/06: Add kernel 2.6.x support
++ 01/11/06: Conditionalize new scan/join structures
++ 01/31/06: Add support to selectively enabe the FW Scan channel filter
++ 02/16/06: Clear scan in progress flag when scan command failed and dropped
++ 04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 05/04/06: Add IBSS coalescing related new hostcmd handling
++ 08/29/06: Add ledgpio private command
++********************************************************/
++
++#include "include.h"
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++static u16 Commands_Allowed_In_PS[] = {
++ HostCmd_CMD_802_11_RSSI,
++ HostCmd_CMD_802_11_HOST_SLEEP_CFG,
++ HostCmd_CMD_802_11_WAKEUP_CONFIRM,
++};
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function checks if the commans is allowed
++ * in PS mode not.
++ *
++ * @param Command the command ID
++ * @return TRUE or FALSE
++ */
++static BOOLEAN
++Is_Command_Allowed_In_PS(u16 Command)
++{
++ int count = sizeof(Commands_Allowed_In_PS)
++ / sizeof(Commands_Allowed_In_PS[0]);
++ int i;
++
++ for (i = 0; i < count; i++) {
++ if (Command == wlan_cpu_to_le16(Commands_Allowed_In_PS[i]))
++ return TRUE;
++ }
++
++ return FALSE;
++}
++
++/**
++ * @brief This function prepares command of get_hw_spec.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_hw_spec(wlan_private * priv, HostCmd_DS_COMMAND * cmd)
++{
++ HostCmd_DS_GET_HW_SPEC *hwspec = &cmd->params.hwspec;
++
++ ENTER();
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_GET_HW_SPEC);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_GET_HW_SPEC) + S_DS_GEN);
++ memcpy(hwspec->PermanentAddr, priv->adapter->CurrentAddr, ETH_ALEN);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of ps_mode.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_ps_mode(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u16 cmd_action)
++{
++ HostCmd_DS_802_11_PS_MODE *psm = &cmd->params.psmode;
++ u16 Action = cmd_action;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_PS_MODE);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_PS_MODE) + S_DS_GEN);
++ psm->Action = wlan_cpu_to_le16(cmd_action);
++ psm->MultipleDtim = 0;
++ switch (Action) {
++ case HostCmd_SubCmd_Enter_PS:
++ PRINTM(INFO, "PS Command:" "SubCode- Enter PS\n");
++ PRINTM(INFO, "LocalListenInterval = %d\n",
++ Adapter->LocalListenInterval);
++
++ psm->LocalListenInterval =
++ wlan_cpu_to_le16(Adapter->LocalListenInterval);
++ psm->NullPktInterval = wlan_cpu_to_le16(Adapter->NullPktInterval);
++ psm->MultipleDtim = wlan_cpu_to_le16(priv->adapter->MultipleDtim);
++ psm->BCNMissTimeOut = wlan_cpu_to_le16(priv->adapter->BCNMissTimeOut);
++ if (priv->adapter->InfrastructureMode == Wlan802_11IBSS)
++ psm->AdhocAwakePeriod =
++ wlan_cpu_to_le16(priv->adapter->AdhocAwakePeriod);
++ break;
++
++ case HostCmd_SubCmd_Exit_PS:
++ PRINTM(INFO, "PS Command:" "SubCode- Exit PS\n");
++ break;
++
++ case HostCmd_SubCmd_Sleep_Confirmed:
++ PRINTM(INFO, "PS Command: SubCode- sleep confirm\n");
++ break;
++
++ default:
++ break;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of fw_wakeup_method.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_fw_wakeup_method(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ int cmd_action, void *pdata_buf)
++{
++ HostCmd_DS_802_11_FW_WAKEUP_METHOD *fwwm = &cmd->params.fwwakeupmethod;
++ u16 action = (u16) cmd_action;
++ u16 method = *((u16 *) pdata_buf);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_FW_WAKE_METHOD);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_FW_WAKEUP_METHOD) +
++ S_DS_GEN);
++ fwwm->Action = wlan_cpu_to_le16(action);
++ switch (action) {
++ case HostCmd_ACT_SET:
++ fwwm->Method = wlan_cpu_to_le16(method);
++ break;
++ case HostCmd_ACT_GET:
++ default:
++ fwwm->Method = 0;
++ break;
++ }
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function sends the HS_Activated event to the application
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_host_sleep_activated_event(wlan_private * priv)
++{
++ ENTER();
++
++ priv->adapter->HS_Activated = TRUE;
++ os_carrier_off(priv);
++ os_stop_queue(priv);
++ wmm_stop_queue(priv);
++
++#if WIRELESS_EXT > 14
++ send_iwevcustom_event(priv, CUS_EVT_HS_ACTIVATED);
++#endif /* WIRELESS_EXT */
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function sends the HS_DeActivated event to the application
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_host_sleep_deactivated_event(wlan_private * priv)
++{
++ ENTER();
++
++ priv->adapter->HS_Activated = FALSE;
++
++#if WIRELESS_EXT > 14
++ send_iwevcustom_event(priv, CUS_EVT_HS_DEACTIVATED);
++#endif /* WIRELESS_EXT */
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function sends the HS_GPIO_INT event to the application
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_host_sleep_gpio_int_event(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (Adapter->bHostSleepConfigured) {
++#if WIRELESS_EXT > 14
++ send_iwevcustom_event(priv, CUS_EVT_HS_GPIO_INT);
++#endif /* WIRELESS_EXT */
++ } else {
++ PRINTM(INFO, "hs_gpio_int: HS not configured !!!\n");
++ }
++
++ LEAVE();
++
++ return ret;
++}
++
++/**
++ * @brief This function prepares command of host_sleep_cfg.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param pdata_buf A pointer to HostCmd_DS_802_11_HOST_SLEEP_CFG structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_host_sleep_cfg(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ HostCmd_DS_802_11_HOST_SLEEP_CFG * pdata_buf)
++{
++ HostCmd_DS_802_11_HOST_SLEEP_CFG *phwuc = &cmd->params.hostsleepcfg;
++
++ ENTER();
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_HOST_SLEEP_CFG);
++ if ((pdata_buf->conditions != HOST_SLEEP_CFG_CANCEL)
++ && ((priv->adapter->ArpFilterSize > 0)
++ && (priv->adapter->ArpFilterSize <= ARP_FILTER_MAX_BUF_SIZE))) {
++ PRINTM(INFO, "Attach %d bytes ArpFilter to HSCfg cmd\n",
++ priv->adapter->ArpFilterSize);
++ memcpy(((u8 *) phwuc) + sizeof(HostCmd_DS_802_11_HOST_SLEEP_CFG),
++ priv->adapter->ArpFilter, priv->adapter->ArpFilterSize);
++ cmd->Size =
++ wlan_cpu_to_le16(priv->adapter->ArpFilterSize +
++ sizeof(HostCmd_DS_802_11_HOST_SLEEP_CFG) +
++ S_DS_GEN);
++ } else
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_HOST_SLEEP_CFG) +
++ S_DS_GEN);
++ phwuc->conditions = wlan_cpu_to_le32(pdata_buf->conditions);
++ phwuc->gpio = pdata_buf->gpio;
++ phwuc->gap = pdata_buf->gap;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of inactivity_timeout.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action Action: GET SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_inactivity_timeout(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ u16 cmd_action, void *pdata_buf)
++{
++ u16 *timeout = (u16 *) pdata_buf;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_INACTIVITY_TIMEOUT);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_INACTIVITY_TIMEOUT) +
++ S_DS_GEN);
++
++ cmd->params.inactivity_timeout.Action = wlan_cpu_to_le16(cmd_action);
++
++ if (cmd_action)
++ cmd->params.inactivity_timeout.Timeout = wlan_cpu_to_le16(*timeout);
++ else
++ cmd->params.inactivity_timeout.Timeout = 0;
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of sleep_period.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_sleep_period(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ u16 cmd_action, void *pdata_buf)
++{
++ HostCmd_DS_802_11_SLEEP_PERIOD *pSleepPeriod = &cmd->params.ps_sleeppd;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SLEEP_PERIOD);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_SLEEP_PERIOD) +
++ S_DS_GEN);
++ memmove(pSleepPeriod, pdata_buf, sizeof(HostCmd_DS_802_11_SLEEP_PERIOD));
++ pSleepPeriod->Action = wlan_cpu_to_le16(pSleepPeriod->Action);
++ pSleepPeriod->Period = wlan_cpu_to_le16(pSleepPeriod->Period);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of sleep_params.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_sleep_params(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u16 cmd_action)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_SLEEP_PARAMS *sp = &cmd->params.sleep_params;
++
++ ENTER();
++
++ cmd->Size = wlan_cpu_to_le16((sizeof(HostCmd_DS_802_11_SLEEP_PARAMS)) +
++ S_DS_GEN);
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SLEEP_PARAMS);
++
++ if (cmd_action == HostCmd_ACT_GEN_GET) {
++ memset(&Adapter->sp, 0, sizeof(SleepParams));
++ memset(sp, 0, sizeof(HostCmd_DS_802_11_SLEEP_PARAMS));
++ sp->Action = wlan_cpu_to_le16(cmd_action);
++ } else if (cmd_action == HostCmd_ACT_GEN_SET) {
++ sp->Action = wlan_cpu_to_le16(cmd_action);
++ sp->Error = wlan_cpu_to_le16(Adapter->sp.sp_error);
++ sp->Offset = wlan_cpu_to_le16(Adapter->sp.sp_offset);
++ sp->StableTime = wlan_cpu_to_le16(Adapter->sp.sp_stabletime);
++ sp->CalControl = (u8) Adapter->sp.sp_calcontrol;
++ sp->ExternalSleepClk = (u8) Adapter->sp.sp_extsleepclk;
++ sp->Reserved = wlan_cpu_to_le16(Adapter->sp.sp_reserved);
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++#define WEP_40_BIT_LEN 5
++#define WEP_104_BIT_LEN 13
++
++/**
++ * @brief This function prepares command of set_wep.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_oid OID: ADD_WEP KEY or REMOVE_WEP KEY
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_set_wep(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u32 cmd_oid)
++{
++ HostCmd_DS_802_11_SET_WEP *wep = &cmd->params.wep;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (cmd_oid == OID_802_11_ADD_WEP) {
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SET_WEP);
++ cmd->Size =
++ wlan_cpu_to_le16((sizeof(HostCmd_DS_802_11_SET_WEP)) + S_DS_GEN);
++ wep->Action = wlan_cpu_to_le16(HostCmd_ACT_ADD);
++
++ /* default tx key index */
++ wep->KeyIndex = wlan_cpu_to_le16(Adapter->CurrentWepKeyIndex &
++ HostCmd_WEP_KEY_INDEX_MASK);
++
++ PRINTM(INFO, "Tx Key Index: %u\n", wep->KeyIndex);
++
++ switch (Adapter->WepKey[0].KeyLength) {
++ case WEP_40_BIT_LEN:
++ wep->WEPTypeForKey1 = HostCmd_TYPE_WEP_40_BIT;
++ memmove(wep->WEP1, Adapter->WepKey[0].KeyMaterial,
++ Adapter->WepKey[0].KeyLength);
++ break;
++ case WEP_104_BIT_LEN:
++ wep->WEPTypeForKey1 = HostCmd_TYPE_WEP_104_BIT;
++ memmove(wep->WEP1, Adapter->WepKey[0].KeyMaterial,
++ Adapter->WepKey[0].KeyLength);
++ break;
++ case 0:
++ break;
++ default:
++ PRINTM(INFO, "Key1 Length = %d is incorrect\n",
++ Adapter->WepKey[0].KeyLength);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ switch (Adapter->WepKey[1].KeyLength) {
++ case WEP_40_BIT_LEN:
++ wep->WEPTypeForKey2 = HostCmd_TYPE_WEP_40_BIT;
++ memmove(wep->WEP2, Adapter->WepKey[1].KeyMaterial,
++ Adapter->WepKey[1].KeyLength);
++ break;
++ case WEP_104_BIT_LEN:
++ wep->WEPTypeForKey2 = HostCmd_TYPE_WEP_104_BIT;
++ memmove(wep->WEP2, Adapter->WepKey[1].KeyMaterial,
++ Adapter->WepKey[1].KeyLength);
++ break;
++ case 0:
++ break;
++ default:
++ PRINTM(INFO, "Key2 Length = %d is incorrect\n",
++ Adapter->WepKey[1].KeyLength);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ switch (Adapter->WepKey[2].KeyLength) {
++ case WEP_40_BIT_LEN:
++ wep->WEPTypeForKey3 = HostCmd_TYPE_WEP_40_BIT;
++ memmove(wep->WEP3, Adapter->WepKey[2].KeyMaterial,
++ Adapter->WepKey[2].KeyLength);
++ break;
++ case WEP_104_BIT_LEN:
++ wep->WEPTypeForKey3 = HostCmd_TYPE_WEP_104_BIT;
++ memmove(wep->WEP3, Adapter->WepKey[2].KeyMaterial,
++ Adapter->WepKey[2].KeyLength);
++ break;
++ case 0:
++ break;
++ default:
++ PRINTM(INFO, "Key3 Length = %d is incorrect\n",
++ Adapter->WepKey[2].KeyLength);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ switch (Adapter->WepKey[3].KeyLength) {
++ case WEP_40_BIT_LEN:
++ wep->WEPTypeForKey4 = HostCmd_TYPE_WEP_40_BIT;
++ memmove(wep->WEP4, Adapter->WepKey[3].KeyMaterial,
++ Adapter->WepKey[3].KeyLength);
++ break;
++ case WEP_104_BIT_LEN:
++ wep->WEPTypeForKey4 = HostCmd_TYPE_WEP_104_BIT;
++ memmove(wep->WEP4, Adapter->WepKey[3].KeyMaterial,
++ Adapter->WepKey[3].KeyLength);
++ break;
++ case 0:
++ break;
++ default:
++ PRINTM(INFO, "Key4 Length = %d is incorrect\n",
++ Adapter->WepKey[3].KeyLength);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ } else if (cmd_oid == OID_802_11_REMOVE_WEP) {
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SET_WEP);
++ cmd->Size =
++ wlan_cpu_to_le16((sizeof(HostCmd_DS_802_11_SET_WEP)) + S_DS_GEN);
++ wep->Action = wlan_cpu_to_le16(HostCmd_ACT_REMOVE);
++
++ /* default tx key index */
++ wep->KeyIndex = wlan_cpu_to_le16((u16) (Adapter->CurrentWepKeyIndex &
++ (u32)
++ HostCmd_WEP_KEY_INDEX_MASK));
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function prepares command of key_material.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param cmd_oid OID: ENABLE or DISABLE
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_key_material(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ u16 cmd_action,
++ WLAN_OID cmd_oid, void *pdata_buf)
++{
++ HostCmd_DS_802_11_KEY_MATERIAL *pKeyMaterial = &cmd->params.keymaterial;
++ WLAN_802_11_KEY *pKey = (WLAN_802_11_KEY *) pdata_buf;
++ u16 KeyParamSet_len;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_KEY_MATERIAL);
++ pKeyMaterial->Action = wlan_cpu_to_le16(cmd_action);
++
++ if (cmd_action == HostCmd_ACT_GET) {
++ cmd->Size = wlan_cpu_to_le16(2 + S_DS_GEN);
++ ret = WLAN_STATUS_SUCCESS;
++ goto done;
++ }
++
++ memset(&pKeyMaterial->KeyParamSet, 0, sizeof(MrvlIEtype_KeyParamSet_t));
++
++ if (pKey->KeyLength == WPA_AES_KEY_LEN) {
++ PRINTM(INFO, "WPA_AES\n");
++ pKeyMaterial->KeyParamSet.KeyTypeId =
++ wlan_cpu_to_le16(KEY_TYPE_ID_AES);
++
++ if (cmd_oid == (WLAN_OID) KEY_INFO_ENABLED)
++ pKeyMaterial->KeyParamSet.KeyInfo =
++ wlan_cpu_to_le16(KEY_INFO_AES_ENABLED);
++ else
++ pKeyMaterial->KeyParamSet.KeyInfo =
++ !(wlan_cpu_to_le16(KEY_INFO_AES_ENABLED));
++
++ if (pKey->KeyIndex & 0x40000000) //AES pairwise key: unicast
++ pKeyMaterial->KeyParamSet.KeyInfo |=
++ wlan_cpu_to_le16(KEY_INFO_AES_UNICAST);
++ else //AES group key: multicast
++ pKeyMaterial->KeyParamSet.KeyInfo |=
++ wlan_cpu_to_le16(KEY_INFO_AES_MCAST);
++ } else if (pKey->KeyLength == WPA_TKIP_KEY_LEN) {
++ PRINTM(INFO, "WPA_TKIP\n");
++ pKeyMaterial->KeyParamSet.KeyTypeId =
++ wlan_cpu_to_le16(KEY_TYPE_ID_TKIP);
++ pKeyMaterial->KeyParamSet.KeyInfo =
++ wlan_cpu_to_le16(KEY_INFO_TKIP_ENABLED);
++
++ if (pKey->KeyIndex & 0x40000000) //TKIP pairwise key: unicast
++ pKeyMaterial->KeyParamSet.KeyInfo |=
++ wlan_cpu_to_le16(KEY_INFO_TKIP_UNICAST);
++ else //TKIP group key: multicast
++ pKeyMaterial->KeyParamSet.KeyInfo |=
++ wlan_cpu_to_le16(KEY_INFO_TKIP_MCAST);
++ }
++
++ if (pKeyMaterial->KeyParamSet.KeyTypeId) {
++ pKeyMaterial->KeyParamSet.Type =
++ wlan_cpu_to_le16(TLV_TYPE_KEY_MATERIAL);
++ pKeyMaterial->KeyParamSet.KeyLen = wlan_cpu_to_le16(pKey->KeyLength);
++ memcpy(pKeyMaterial->KeyParamSet.Key,
++ pKey->KeyMaterial, pKey->KeyLength);
++ pKeyMaterial->KeyParamSet.Length =
++ wlan_cpu_to_le16(pKey->KeyLength + 6);
++
++#define TYPE_LEN_FIELDS_LEN 4
++ KeyParamSet_len = (pKey->KeyLength + 6) + TYPE_LEN_FIELDS_LEN;
++#define ACTION_FIELD_LEN 2
++ cmd->Size =
++ wlan_cpu_to_le16(KeyParamSet_len + ACTION_FIELD_LEN + S_DS_GEN);
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function prepares command of get_log.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_get_log(wlan_private * priv, HostCmd_DS_COMMAND * cmd)
++{
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_GET_LOG);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_GET_LOG) + S_DS_GEN);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of snmp_mib.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param cmd_oid the OID of SNMP MIB
++ * @param pdata_buf the pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_snmp_mib(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ int cmd_action, int cmd_oid, void *pdata_buf)
++{
++ HostCmd_DS_802_11_SNMP_MIB *pSNMPMIB = &cmd->params.smib;
++ wlan_adapter *Adapter = priv->adapter;
++ u8 ucTemp;
++
++ ENTER();
++
++ PRINTM(INFO, "SNMP_CMD: cmd_oid = 0x%x\n", cmd_oid);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SNMP_MIB);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_SNMP_MIB) + S_DS_GEN);
++
++ switch (cmd_oid) {
++ case OID_802_11_INFRASTRUCTURE_MODE:
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
++ pSNMPMIB->OID = wlan_cpu_to_le16((u16) DesiredBssType_i);
++ pSNMPMIB->BufSize = wlan_cpu_to_le16(sizeof(u8));
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure)
++ ucTemp = SNMP_MIB_VALUE_INFRA;
++ else
++ ucTemp = SNMP_MIB_VALUE_ADHOC;
++
++ memmove(pSNMPMIB->Value, &ucTemp, sizeof(u8));
++
++ break;
++
++ case OID_802_11D_ENABLE:
++ {
++ u32 ulTemp;
++
++ pSNMPMIB->OID = wlan_cpu_to_le16((u16) Dot11D_i);
++
++ if (cmd_action == HostCmd_ACT_SET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
++ pSNMPMIB->BufSize = wlan_cpu_to_le16(sizeof(u16));
++ ulTemp = *(u32 *) pdata_buf;
++ *((PUSHORT) (pSNMPMIB->Value)) =
++ wlan_cpu_to_le16((u16) ulTemp);
++ }
++ break;
++ }
++
++ case OID_802_11_FRAGMENTATION_THRESHOLD:
++ {
++ WLAN_802_11_FRAGMENTATION_THRESHOLD ulTemp;
++
++ pSNMPMIB->OID = wlan_cpu_to_le16((u16) FragThresh_i);
++
++ if (cmd_action == HostCmd_ACT_GET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
++ } else if (cmd_action == HostCmd_ACT_SET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
++ pSNMPMIB->BufSize = wlan_cpu_to_le16(sizeof(u16));
++ ulTemp = *((WLAN_802_11_FRAGMENTATION_THRESHOLD *)
++ pdata_buf);
++ *((PUSHORT) (pSNMPMIB->Value)) =
++ wlan_cpu_to_le16((u16) ulTemp);
++
++ }
++
++ break;
++ }
++
++ case OID_802_11_RTS_THRESHOLD:
++ {
++
++ WLAN_802_11_RTS_THRESHOLD ulTemp;
++ pSNMPMIB->OID = wlan_cpu_to_le16((u16) RtsThresh_i);
++
++ if (cmd_action == HostCmd_ACT_GET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
++ } else if (cmd_action == HostCmd_ACT_SET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
++ pSNMPMIB->BufSize = wlan_cpu_to_le16(sizeof(u16));
++ ulTemp = *((WLAN_802_11_RTS_THRESHOLD *)
++ pdata_buf);
++ *(PUSHORT) (pSNMPMIB->Value) = wlan_cpu_to_le16((u16) ulTemp);
++ }
++ break;
++ }
++ case OID_802_11_TX_RETRYCOUNT:
++ pSNMPMIB->OID = wlan_cpu_to_le16((u16) ShortRetryLim_i);
++
++ if (cmd_action == HostCmd_ACT_GET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
++ } else if (cmd_action == HostCmd_ACT_SET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
++ pSNMPMIB->BufSize = wlan_cpu_to_le16(sizeof(u16));
++ *((PUSHORT) (pSNMPMIB->Value)) =
++ wlan_cpu_to_le16((u16) Adapter->TxRetryCount);
++ }
++ break;
++
++ case OID_802_11_DTIM:
++ pSNMPMIB->OID = wlan_cpu_to_le16((u16) DtimPeriod_i);
++
++ if (cmd_action == HostCmd_ACT_GET) {
++ pSNMPMIB->QueryType = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ PRINTM(INFO,
++ "SNMP_CMD: Command=0x%x, Size=0x%x, SeqNum=0x%x, Result=0x%x\n",
++ cmd->Command, cmd->Size, cmd->SeqNum, cmd->Result);
++
++ PRINTM(INFO,
++ "SNMP_CMD: Action=0x%x, OID=0x%x, OIDSize=0x%x, Value=0x%x\n",
++ pSNMPMIB->QueryType, pSNMPMIB->OID, pSNMPMIB->BufSize,
++ *(u16 *) pSNMPMIB->Value);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of radio_control.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_radio_control(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, int cmd_action)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_RADIO_CONTROL *pRadioControl = &cmd->params.radio;
++
++ ENTER();
++
++ cmd->Size = wlan_cpu_to_le16((sizeof(HostCmd_DS_802_11_RADIO_CONTROL))
++ + S_DS_GEN);
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RADIO_CONTROL);
++
++ pRadioControl->Action = wlan_cpu_to_le16(cmd_action);
++ pRadioControl->Control = wlan_cpu_to_le16(Adapter->RadioOn);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of bca_timeshare.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param user_bca_ts A pointer to HostCmd_DS_802_11_BCA_TIMESHARE structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_bca_timeshare(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ u16 cmd_action,
++ HostCmd_DS_802_11_BCA_TIMESHARE * user_bca_ts)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_BCA_TIMESHARE *bca_ts = &cmd->params.bca_timeshare;
++
++ ENTER();
++
++ cmd->Size = wlan_cpu_to_le16((sizeof(HostCmd_DS_802_11_BCA_TIMESHARE)) +
++ S_DS_GEN);
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_BCA_CONFIG_TIMESHARE);
++
++ if (cmd_action == HostCmd_ACT_GEN_GET) {
++ memset(&Adapter->bca_ts, 0, sizeof(bca_ts));
++ memset(bca_ts, 0, sizeof(HostCmd_DS_802_11_BCA_TIMESHARE));
++ bca_ts->Action = wlan_cpu_to_le16(cmd_action);
++ bca_ts->TrafficType = wlan_cpu_to_le16(user_bca_ts->TrafficType);
++ } else if (cmd_action == HostCmd_ACT_GEN_SET) {
++ bca_ts->Action = wlan_cpu_to_le16(cmd_action);
++ bca_ts->TrafficType = wlan_cpu_to_le16(user_bca_ts->TrafficType);
++ bca_ts->TimeShareInterval =
++ wlan_cpu_to_le32(user_bca_ts->TimeShareInterval);
++ bca_ts->BTTime = wlan_cpu_to_le32(user_bca_ts->BTTime);
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of rf_tx_power.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_rf_tx_power(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ u16 cmd_action, void *pdata_buf)
++{
++
++ HostCmd_DS_802_11_RF_TX_POWER *pRTP = &cmd->params.txp;
++
++ ENTER();
++
++ cmd->Size =
++ wlan_cpu_to_le16((sizeof(HostCmd_DS_802_11_RF_TX_POWER)) + S_DS_GEN);
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RF_TX_POWER);
++ pRTP->Action = cmd_action;
++
++ PRINTM(INFO, "RF_TX_POWER_CMD: Size:%d Cmd:0x%x Act:%d\n", cmd->Size,
++ cmd->Command, pRTP->Action);
++
++ switch (cmd_action) {
++ case HostCmd_ACT_GEN_GET:
++ pRTP->Action = wlan_cpu_to_le16(HostCmd_ACT_GEN_GET);
++ pRTP->CurrentLevel = 0;
++ break;
++
++ case HostCmd_ACT_GEN_SET:
++ pRTP->Action = wlan_cpu_to_le16(HostCmd_ACT_GEN_SET);
++ pRTP->CurrentLevel = wlan_cpu_to_le16(*((u16 *) pdata_buf));
++ break;
++ }
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of rf_antenna.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_rf_antenna(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ u16 cmd_action, void *pdata_buf)
++{
++ HostCmd_DS_802_11_RF_ANTENNA *rant = &cmd->params.rant;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RF_ANTENNA);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_RF_ANTENNA) + S_DS_GEN);
++
++ rant->Action = wlan_cpu_to_le16(cmd_action);
++ if ((cmd_action == HostCmd_ACT_SET_RX) ||
++ (cmd_action == HostCmd_ACT_SET_TX)) {
++ rant->AntennaMode =
++ wlan_cpu_to_le16((u16) (*(WLAN_802_11_ANTENNA *) pdata_buf));
++ }
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of rate_adapt_rateset.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_rate_adapt_rateset(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u16 cmd_action)
++{
++ HostCmd_DS_802_11_RATE_ADAPT_RATESET * rateadapt = &cmd->params.rateset;
++ wlan_adapter *Adapter = priv->adapter;
++
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_RATE_ADAPT_RATESET) +
++ S_DS_GEN);
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RATE_ADAPT_RATESET);
++
++ ENTER();
++
++ rateadapt->Action = wlan_cpu_to_le16(cmd_action);
++ rateadapt->HWRateDropMode = wlan_cpu_to_le16(Adapter->HWRateDropMode);
++ rateadapt->Threshold = wlan_cpu_to_le16(Adapter->Threshold);
++ rateadapt->FinalRate = wlan_cpu_to_le16(Adapter->FinalRate);
++ rateadapt->Bitmap = wlan_cpu_to_le16(Adapter->RateBitmap);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of mac_multicast_adr.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_mac_multicast_adr(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u16 cmd_action)
++{
++ HostCmd_DS_MAC_MULTICAST_ADR *pMCastAdr = &cmd->params.madr;
++ wlan_adapter *Adapter = priv->adapter;
++
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_MAC_MULTICAST_ADR) + S_DS_GEN);
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_MAC_MULTICAST_ADR);
++
++ pMCastAdr->Action = wlan_cpu_to_le16(cmd_action);
++ pMCastAdr->NumOfAdrs =
++ wlan_cpu_to_le16((u16) Adapter->NumOfMulticastMACAddr);
++ memcpy(pMCastAdr->MACList, Adapter->MulticastList,
++ Adapter->NumOfMulticastMACAddr * ETH_ALEN);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of rf_channel.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_rf_channel(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ int option, void *pdata_buf)
++{
++ HostCmd_DS_802_11_RF_CHANNEL *rfchan = &cmd->params.rfchannel;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RF_CHANNEL);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_RF_CHANNEL)
++ + S_DS_GEN);
++
++ if (option == HostCmd_OPT_802_11_RF_CHANNEL_SET) {
++ rfchan->CurrentChannel = wlan_cpu_to_le16(*((u16 *) pdata_buf));
++ }
++
++ rfchan->Action = wlan_cpu_to_le16(option);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of rssi.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_rssi(wlan_private * priv, HostCmd_DS_COMMAND * cmd)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_RSSI);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_RSSI) + S_DS_GEN);
++ cmd->params.rssi.N = wlan_cpu_to_le16(Adapter->bcn_avg_factor);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of reg_access.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_reg_access(wlan_private * priv,
++ HostCmd_DS_COMMAND * CmdPtr,
++ u8 cmd_action, void *pdata_buf)
++{
++ wlan_offset_value *offval;
++
++ ENTER();
++
++ offval = (wlan_offset_value *) pdata_buf;
++
++ switch (CmdPtr->Command) {
++ case HostCmd_CMD_MAC_REG_ACCESS:
++ {
++ HostCmd_DS_MAC_REG_ACCESS *macreg;
++
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_MAC_REG_ACCESS) +
++ S_DS_GEN);
++ macreg = (HostCmd_DS_MAC_REG_ACCESS *) & CmdPtr->params.macreg;
++
++ macreg->Action = wlan_cpu_to_le16(cmd_action);
++ macreg->Offset = wlan_cpu_to_le16((u16) offval->offset);
++ macreg->Value = wlan_cpu_to_le32(offval->value);
++
++ break;
++ }
++
++ case HostCmd_CMD_BBP_REG_ACCESS:
++ {
++ HostCmd_DS_BBP_REG_ACCESS *bbpreg;
++
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_BBP_REG_ACCESS) +
++ S_DS_GEN);
++ bbpreg = (HostCmd_DS_BBP_REG_ACCESS *) & CmdPtr->params.bbpreg;
++
++ bbpreg->Action = wlan_cpu_to_le16(cmd_action);
++ bbpreg->Offset = wlan_cpu_to_le16((u16) offval->offset);
++ bbpreg->Value = (u8) offval->value;
++
++ break;
++ }
++
++ case HostCmd_CMD_RF_REG_ACCESS:
++ {
++ HostCmd_DS_RF_REG_ACCESS *rfreg;
++
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_RF_REG_ACCESS) + S_DS_GEN);
++ rfreg = (HostCmd_DS_RF_REG_ACCESS *) & CmdPtr->params.rfreg;
++
++ rfreg->Action = wlan_cpu_to_le16(cmd_action);
++ rfreg->Offset = wlan_cpu_to_le16((u16) offval->offset);
++ rfreg->Value = (u8) offval->value;
++
++ break;
++ }
++
++ default:
++ break;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of mac_address.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_mac_address(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, u16 cmd_action)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_MAC_ADDRESS);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_MAC_ADDRESS) +
++ S_DS_GEN);
++ cmd->Result = 0;
++
++ cmd->params.macadd.Action = wlan_cpu_to_le16(cmd_action);
++
++ if (cmd_action == HostCmd_ACT_SET) {
++ memcpy(cmd->params.macadd.MacAdd, Adapter->CurrentAddr, ETH_ALEN);
++ HEXDUMP("SET_CMD: MAC ADDRESS-", Adapter->CurrentAddr, 6);
++ }
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of cal_data_ext.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_cal_data_ext(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *pdata_buf)
++{
++ HostCmd_DS_802_11_CAL_DATA_EXT *PCalDataext = pdata_buf;
++
++ HostCmd_DS_802_11_CAL_DATA_EXT *pCmdCalData =
++ (HostCmd_DS_802_11_CAL_DATA_EXT *) & cmd->params.caldataext;
++
++ ENTER();
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_CAL_DATA_EXT);
++
++ PRINTM(INFO, "CalDataLen = %d(d)\n", PCalDataext->CalDataLen);
++
++ if (PCalDataext->CalDataLen >
++ MAX_SETGET_CONF_CMD_LEN - CAL_DATA_HEADER_LEN) {
++ PRINTM(MSG, "CAL_DATA_EXT: Cal data lenght too large!\n");
++ return WLAN_STATUS_FAILURE;
++ }
++
++ memcpy(pCmdCalData, PCalDataext,
++ PCalDataext->CalDataLen + CAL_DATA_HEADER_LEN);
++
++ pCmdCalData->Action = wlan_cpu_to_le16(pCmdCalData->Action);
++ pCmdCalData->Revision = wlan_cpu_to_le16(pCmdCalData->Revision);
++ pCmdCalData->CalDataLen = wlan_cpu_to_le16(pCmdCalData->CalDataLen);
++
++ cmd->Size = wlan_cpu_to_le16(PCalDataext->CalDataLen +
++ CAL_DATA_HEADER_LEN + S_DS_GEN);
++
++ PRINTM(INFO, "CAL_DATA_EXT: cmd->Size = %d(d)\n", cmd->Size);
++
++ cmd->Result = 0;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of eeprom_access.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_802_11_eeprom_access(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ int cmd_action, void *pdata_buf)
++{
++ wlan_ioctl_regrdwr *ea = pdata_buf;
++
++ ENTER();
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_EEPROM_ACCESS);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_EEPROM_ACCESS) + S_DS_GEN);
++ cmd->Result = 0;
++
++ cmd->params.rdeeprom.Action = wlan_cpu_to_le16(ea->Action);
++ cmd->params.rdeeprom.Offset = wlan_cpu_to_le16(ea->Offset);
++ cmd->params.rdeeprom.ByteCount = wlan_cpu_to_le16(ea->NOB);
++ cmd->params.rdeeprom.Value = 0;
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++static int
++wlan_cmd_802_11_IBSS_Coalesced_Status(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ int cmd_action, void *pdata_buf)
++{
++ HostCmd_DS_802_11_IBSS_Status *pIBSSReq = &(cmd->params.ibssCoalescing);
++ u16 *enable = pdata_buf;
++
++ PRINTM(INFO, "HostCmd_CMD_802_11_BSSID_QUERY request");
++
++ cmd->Command =
++ wlan_cpu_to_le16(HostCmd_CMD_802_11_IBSS_COALESCING_STATUS);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_IBSS_Status) + S_DS_GEN);
++ cmd->Result = 0;
++ pIBSSReq->Action = wlan_cpu_to_le16(cmd_action);
++
++ switch (cmd_action) {
++ case HostCmd_ACT_SET:
++ pIBSSReq->Enable = wlan_cpu_to_le16(*enable);
++ break;
++
++ /* In other case.. Noting to do */
++ case HostCmd_ACT_GET:
++ default:
++ break;
++ }
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function queues the command to cmd list.
++ *
++ * @param Adapter A pointer to wlan_adapter structure
++ * @param CmdNode A pointer to CmdCtrlNode structure
++ * @param addtail specify if the cmd needs to be queued in the header or tail
++ * @return n/a
++ */
++void
++QueueCmd(wlan_adapter * Adapter, CmdCtrlNode * CmdNode, BOOLEAN addtail)
++{
++ ulong flags;
++ HostCmd_DS_COMMAND *CmdPtr;
++ u16 command;
++
++ ENTER();
++
++ if (!CmdNode) {
++ PRINTM(WARN, "QUEUE_CMD: CmdNode is NULL\n");
++ goto done;
++ }
++
++ CmdPtr = (HostCmd_DS_COMMAND *) CmdNode->BufVirtualAddr;
++ if (!CmdPtr) {
++ PRINTM(WARN, "QUEUE_CMD: CmdPtr is NULL\n");
++ goto done;
++ }
++
++ command = wlan_le16_to_cpu(CmdPtr->Command);
++
++ /* Exit_PS command needs to be queued in the header always. */
++ if (command == HostCmd_CMD_802_11_PS_MODE) {
++ HostCmd_DS_802_11_PS_MODE *psm = &CmdPtr->params.psmode;
++ if (wlan_le16_to_cpu(psm->Action) == HostCmd_SubCmd_Exit_PS) {
++ if (Adapter->PSState != PS_STATE_FULL_POWER)
++ addtail = FALSE;
++ }
++ }
++
++ if ((command == HostCmd_CMD_802_11_WAKEUP_CONFIRM)
++ || (command == HostCmd_CMD_802_11_HOST_SLEEP_ACTIVATE)
++ || (command == HostCmd_CMD_802_11_HOST_SLEEP_CFG)
++ ) {
++ addtail = FALSE;
++ }
++
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++
++ if (addtail)
++ list_add_tail((struct list_head *) CmdNode, &Adapter->CmdPendingQ);
++ else
++ list_add((struct list_head *) CmdNode, &Adapter->CmdPendingQ);
++
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ PRINTM(INFO, "QUEUE_CMD: cmd=0x%x is queued\n", command);
++
++ done:
++ LEAVE();
++ return;
++}
++
++#ifdef MFG_CMD_SUPPORT
++/**
++ * @brief This function sends general command to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param pdata_buf A pointer to data buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_mfg_cmd(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *pdata_buf)
++{
++ HostCmd_DS_GEN *pCmdPtr;
++
++ ENTER();
++
++ pCmdPtr = (HostCmd_DS_GEN *) pdata_buf;
++
++ /* copy the MFG command to command buffer */
++ memcpy((void *) cmd, pdata_buf, pCmdPtr->Size);
++
++ PRINTM(INFO, "MFG command size = %d\n", pCmdPtr->Size);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_MFG_COMMAND);
++ cmd->Size = wlan_cpu_to_le16(cmd->Size);
++ cmd->Result = 0;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++#endif
++
++/**
++ * @brief This function downloads the command to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param CmdNode A pointer to CmdCtrlNode structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++DownloadCommandToStation(wlan_private * priv, CmdCtrlNode * CmdNode)
++{
++ ulong flags;
++ HostCmd_DS_COMMAND *CmdPtr;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ u16 CmdSize;
++ u16 Command;
++
++ OS_INTERRUPT_SAVE_AREA;
++
++ ENTER();
++
++ if (!Adapter || !CmdNode) {
++ PRINTM(ERROR, "DNLD_CMD: Adapter = %#x, CmdNode = %#x\n",
++ (int) Adapter, (int) CmdNode);
++ if (CmdNode)
++ CleanupAndInsertCmd(priv, CmdNode);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ CmdPtr = (HostCmd_DS_COMMAND *) CmdNode->BufVirtualAddr;
++
++ if (!CmdPtr || !CmdPtr->Size) {
++ PRINTM(ERROR, "DNLD_CMD: CmdPtr is Null or Cmd Size is Zero, "
++ "Not sending\n");
++ CleanupAndInsertCmd(priv, CmdNode);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Set command sequence number */
++ Adapter->SeqNum++;
++ CmdPtr->SeqNum = wlan_cpu_to_le16(Adapter->SeqNum);
++
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ Adapter->CurCmd = CmdNode;
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ Command = wlan_le16_to_cpu(CmdPtr->Command);
++ CmdSize = wlan_le16_to_cpu(CmdPtr->Size);
++
++ CmdNode->CmdWaitQWoken = FALSE;
++
++ ret = sbi_host_to_card(priv, MVMS_CMD, (u8 *) CmdPtr, CmdSize);
++
++ /* clear TxDone interrupt bit */
++ OS_INT_DISABLE;
++ Adapter->HisRegCpy &= ~HIS_TxDnLdRdy;
++ OS_INT_RESTORE;
++
++ if (ret != 0) {
++ PRINTM(ERROR, "DNLD_CMD: Host to Card Failed\n");
++ /* set error code that will be transferred back to PrepareAndSendCommand() */
++ Adapter->CurCmdRetCode = WLAN_STATUS_FAILURE;
++ CleanupAndInsertCmd(priv, Adapter->CurCmd);
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ Adapter->CurCmd = NULL;
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++ Adapter->dbg.num_cmd_host_to_card_failure++;
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Save the last command id and action to debug log */
++ Adapter->dbg.LastCmdIndex = (Adapter->dbg.LastCmdIndex + 1) % DBG_CMD_NUM;
++ Adapter->dbg.LastCmdId[Adapter->dbg.LastCmdIndex] = Command;
++ Adapter->dbg.LastCmdAct[Adapter->dbg.LastCmdIndex] =
++ wlan_le16_to_cpu(*(u16 *) ((u8 *) CmdPtr + S_DS_GEN));
++
++ PRINTM(CMND, "DNLD_CMD: 0x%x, act 0x%x, len %d, seqno %d @ %lu\n",
++ Command, wlan_le16_to_cpu(*(u16 *) ((u8 *) CmdPtr + S_DS_GEN)),
++ CmdSize, wlan_le16_to_cpu(CmdPtr->SeqNum), os_time_get());
++ DBG_HEXDUMP(CMD_D, "DNLD_CMD", CmdNode->BufVirtualAddr, CmdSize);
++
++ /* Setup the timer after transmit command */
++ if (Command == HostCmd_CMD_802_11_SCAN
++ || Command == HostCmd_CMD_802_11_DEAUTHENTICATE
++ || Command == HostCmd_CMD_802_11_ASSOCIATE
++ || Command == HostCmd_CMD_WMM_ADDTS_REQ) {
++ ModTimer(&Adapter->MrvDrvCommandTimer, MRVDRV_TIMER_10S);
++ } else {
++ ModTimer(&Adapter->MrvDrvCommandTimer, MRVDRV_TIMER_5S);
++ }
++
++ Adapter->CommandTimerIsSet = TRUE;
++
++ if (Command == HostCmd_CMD_802_11_DEEP_SLEEP) {
++ if (Adapter->IntCounter || Adapter->CurrentTxSkb)
++ PRINTM(INFO, "DNLD_CMD: DS- IntCnt=%d CurTxSkb=%s\n",
++ Adapter->IntCounter, (Adapter->CurrentTxSkb) ? "Y" : "N");
++
++ if (Adapter->IntCounter) {
++ OS_INT_DISABLE;
++ Adapter->IntCounterSaved = Adapter->IntCounter;
++ Adapter->IntCounter = 0;
++ OS_INT_RESTORE;
++ }
++ if (Adapter->CurrentTxSkb) {
++ kfree_skb(Adapter->CurrentTxSkb);
++ OS_INT_DISABLE;
++ Adapter->CurrentTxSkb = NULL;
++ OS_INT_RESTORE;
++ priv->stats.tx_dropped++;
++ }
++ /* 1. change the PS state to DEEP_SLEEP
++ * 2. since there is no response for this command, so
++ * delete the command timer and free the Node. */
++
++ Adapter->IsDeepSleep = TRUE;
++
++ CleanupAndInsertCmd(priv, CmdNode);
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ Adapter->CurCmd = NULL;
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ if (Adapter->CommandTimerIsSet) {
++ CancelTimer(&Adapter->MrvDrvCommandTimer);
++ Adapter->CommandTimerIsSet = FALSE;
++ }
++
++ if (!Adapter->IsAutoDeepSleepEnabled
++ || (Adapter->bHostSleepConfigured &&
++ (Adapter->HSCfg.gpio != HOST_SLEEP_CFG_WAKEUP_THRU_INTERFACE))
++ )
++ /* stop clock to save more power */
++ sbi_set_bus_clock(priv, FALSE);
++
++ if (Adapter->IsAutoDeepSleepEnabled) {
++ Adapter->bWakeupDevRequired = TRUE;
++ /* For auto deep sleep mode, after entering deep sleep state,
++ * dnld_sent flag should be cleared so that the commands in
++ * pending queue can be handled by main thread. */
++ priv->wlan_dev.dnld_sent = DNLD_RES_RECEIVED;
++ }
++
++ if (Adapter->bHostSleepConfigured) {
++ Adapter->bWakeupDevRequired = TRUE;
++ wlan_host_sleep_activated_event(priv);
++ }
++
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function prepares command of mac_control.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_cmd_mac_control(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf)
++{
++ HostCmd_DS_MAC_CONTROL *mac = &cmd->params.macctrl;
++ u16 Action = *((u16 *) InfoBuf);
++
++ ENTER();
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_MAC_CONTROL);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_MAC_CONTROL) + S_DS_GEN);
++ mac->Action = wlan_cpu_to_le16(Action);
++
++ PRINTM(INFO, "wlan_cmd_mac_control(): Action=0x%X Size=%d\n",
++ mac->Action, cmd->Size);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief This function inserts command node to CmdFreeQ
++ * after cleans it.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pTempCmd A pointer to CmdCtrlNode structure
++ * @return n/a
++ */
++void
++CleanupAndInsertCmd(wlan_private * priv, CmdCtrlNode * pTempCmd)
++{
++ ulong flags;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!pTempCmd)
++ goto done;
++
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ CleanUpCmdCtrlNode(pTempCmd);
++ list_add_tail((struct list_head *) pTempCmd, &Adapter->CmdFreeQ);
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ done:
++ LEAVE();
++}
++
++/**
++ * @brief This function prepare the command before send to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd_no command number
++ * @param cmd_action command action: GET or SET
++ * @param wait_option wait option: wait response or not
++ * @param cmd_oid cmd oid: treated as sub command
++ * @param pdata_buf A pointer to informaion buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++PrepareAndSendCommand(wlan_private * priv,
++ u16 cmd_no,
++ u16 cmd_action,
++ u16 wait_option, WLAN_OID cmd_oid, void *pdata_buf)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++ CmdCtrlNode *CmdNode;
++ HostCmd_DS_COMMAND *CmdPtr;
++
++ ENTER();
++
++ if (!Adapter) {
++ PRINTM(ERROR, "PREP_CMD: Adapter is Null\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ if (Adapter->SurpriseRemoved) {
++ PRINTM(ERROR, "PREP_CMD: Card is Removed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ CmdNode = GetFreeCmdCtrlNode(priv);
++
++ if (CmdNode == NULL) {
++ PRINTM(MSG, "PREP_CMD: No free CmdNode\n");
++
++ /* Wake up main thread to execute next command */
++ wake_up_interruptible(&priv->MainThread.waitQ);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ SetCmdCtrlNode(priv, CmdNode, cmd_oid, wait_option, pdata_buf);
++
++ CmdPtr = (HostCmd_DS_COMMAND *) CmdNode->BufVirtualAddr;
++
++ if (!CmdPtr) {
++ PRINTM(MSG, "PREP_CMD: BufVirtualAddr of CmdNode is NULL\n");
++ CleanupAndInsertCmd(priv, CmdNode);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ CmdPtr->Command = cmd_no;
++ CmdPtr->Result = 0;
++
++ TX_EVENT_FLAGS_SET(&CmdNode->cmdwait_q, 0, TX_AND);
++ switch (cmd_no) {
++ case HostCmd_CMD_GET_HW_SPEC:
++ ret = wlan_cmd_hw_spec(priv, CmdPtr);
++ break;
++ case HostCmd_CMD_802_11_PS_MODE:
++ ret = wlan_cmd_802_11_ps_mode(priv, CmdPtr, cmd_action);
++ break;
++
++ case HostCmd_CMD_802_11_SCAN:
++ ret = wlan_cmd_802_11_scan(priv, CmdPtr, pdata_buf);
++ break;
++
++ case HostCmd_CMD_MAC_CONTROL:
++ ret = wlan_cmd_mac_control(priv, CmdPtr, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_ASSOCIATE:
++ ret = wlan_cmd_802_11_associate(priv, CmdPtr, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_DEAUTHENTICATE:
++ ret = wlan_cmd_802_11_deauthenticate(priv, CmdPtr);
++ break;
++
++ case HostCmd_CMD_802_11_SET_WEP:
++ ret = wlan_cmd_802_11_set_wep(priv, CmdPtr, cmd_oid);
++ break;
++
++ case HostCmd_CMD_802_11_AD_HOC_START:
++ ret = wlan_cmd_802_11_ad_hoc_start(priv, CmdPtr, pdata_buf);
++ break;
++ case HostCmd_CMD_802_11_RESET:
++ CmdPtr->Command = wlan_cpu_to_le16(cmd_no);
++ CmdPtr->Size = wlan_cpu_to_le16(S_DS_GEN);
++ break;
++
++ case HostCmd_CMD_802_11_GET_LOG:
++ ret = wlan_cmd_802_11_get_log(priv, CmdPtr);
++ break;
++
++ case HostCmd_CMD_802_11_SNMP_MIB:
++ ret = wlan_cmd_802_11_snmp_mib(priv, CmdPtr,
++ cmd_action, cmd_oid, pdata_buf);
++ break;
++
++ case HostCmd_CMD_MAC_REG_ACCESS:
++ case HostCmd_CMD_BBP_REG_ACCESS:
++ case HostCmd_CMD_RF_REG_ACCESS:
++ ret = wlan_cmd_reg_access(priv, CmdPtr, cmd_action, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_RF_CHANNEL:
++ ret = wlan_cmd_802_11_rf_channel(priv, CmdPtr, cmd_action, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_RF_TX_POWER:
++ ret = wlan_cmd_802_11_rf_tx_power(priv, CmdPtr,
++ cmd_action, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_RADIO_CONTROL:
++ ret = wlan_cmd_802_11_radio_control(priv, CmdPtr, cmd_action);
++ break;
++
++ case HostCmd_CMD_802_11_RF_ANTENNA:
++ ret = wlan_cmd_802_11_rf_antenna(priv, CmdPtr, cmd_action, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_RATE_ADAPT_RATESET:
++ ret = wlan_cmd_802_11_rate_adapt_rateset(priv, CmdPtr, cmd_action);
++ break;
++
++ case HostCmd_CMD_MAC_MULTICAST_ADR:
++ ret = wlan_cmd_mac_multicast_adr(priv, CmdPtr, cmd_action);
++ break;
++
++ case HostCmd_CMD_802_11_AD_HOC_JOIN:
++ ret = wlan_cmd_802_11_ad_hoc_join(priv, CmdPtr, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_RSSI:
++ ret = wlan_cmd_802_11_rssi(priv, CmdPtr);
++ break;
++
++ case HostCmd_CMD_802_11_AD_HOC_STOP:
++ ret = wlan_cmd_802_11_ad_hoc_stop(priv, CmdPtr);
++ break;
++ case HostCmd_CMD_802_11_KEY_MATERIAL:
++ ret = wlan_cmd_802_11_key_material(priv, CmdPtr,
++ cmd_action, cmd_oid, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_MAC_ADDRESS:
++ ret = wlan_cmd_802_11_mac_address(priv, CmdPtr, cmd_action);
++ break;
++ case HostCmd_CMD_802_11_CAL_DATA_EXT:
++ ret = wlan_cmd_802_11_cal_data_ext(priv, CmdPtr, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_DEEP_SLEEP:
++ CmdPtr->Command = wlan_cpu_to_le16(cmd_no);
++ CmdPtr->Size = wlan_cpu_to_le16((u16)
++ (sizeof
++ (HostCmd_DS_802_11_DEEP_SLEEP)));
++ break;
++
++ case HostCmd_CMD_802_11_HOST_SLEEP_CFG:
++ ret = wlan_cmd_802_11_host_sleep_cfg(priv, CmdPtr, pdata_buf);
++ break;
++ case HostCmd_CMD_802_11_WAKEUP_CONFIRM:
++ case HostCmd_CMD_802_11_HOST_SLEEP_ACTIVATE:
++ CmdPtr->Command = wlan_cpu_to_le16(cmd_no);
++ CmdPtr->Size = wlan_cpu_to_le16(S_DS_GEN);
++ break;
++
++ case HostCmd_CMD_802_11_EEPROM_ACCESS:
++ ret = wlan_cmd_802_11_eeprom_access(priv, CmdPtr,
++ cmd_action, pdata_buf);
++ break;
++
++#ifdef MFG_CMD_SUPPORT
++ case HostCmd_CMD_MFG_COMMAND:
++ ret = wlan_cmd_mfg_cmd(priv, CmdPtr, pdata_buf);
++ break;
++#endif
++
++ case HostCmd_CMD_802_11D_DOMAIN_INFO:
++ ret = wlan_cmd_802_11d_domain_info(priv, CmdPtr, cmd_no, cmd_action);
++ break;
++
++ case HostCmd_CMD_802_11_SLEEP_PARAMS:
++ ret = wlan_cmd_802_11_sleep_params(priv, CmdPtr, cmd_action);
++ break;
++ case HostCmd_CMD_802_11_BCA_CONFIG_TIMESHARE:
++ ret = wlan_cmd_802_11_bca_timeshare(priv, CmdPtr,
++ cmd_action, pdata_buf);
++ break;
++ case HostCmd_CMD_802_11_INACTIVITY_TIMEOUT:
++ ret = wlan_cmd_802_11_inactivity_timeout(priv, CmdPtr,
++ cmd_action, pdata_buf);
++ break;
++ case HostCmd_CMD_802_11_BG_SCAN_CONFIG:
++ ret = wlan_cmd_802_11_bg_scan_config(priv, CmdPtr,
++ cmd_action, pdata_buf);
++ break;
++
++ case HostCmd_CMD_802_11_BG_SCAN_QUERY:
++ ret = wlan_cmd_802_11_bg_scan_query(priv, CmdPtr);
++ break;
++
++ case HostCmd_CMD_802_11_FW_WAKE_METHOD:
++ ret = wlan_cmd_802_11_fw_wakeup_method(priv, CmdPtr,
++ cmd_action, pdata_buf);
++ break;
++
++ case HostCmd_CMD_WMM_GET_STATUS:
++ ret = wlan_cmd_wmm_get_status(priv, CmdPtr, pdata_buf);
++ break;
++
++ case HostCmd_CMD_WMM_ADDTS_REQ:
++ ret = wlan_cmd_wmm_addts_req(priv, CmdPtr, pdata_buf);
++ break;
++ case HostCmd_CMD_WMM_DELTS_REQ:
++ ret = wlan_cmd_wmm_delts_req(priv, CmdPtr, pdata_buf);
++ break;
++ case HostCmd_CMD_WMM_QUEUE_CONFIG:
++ ret = wlan_cmd_wmm_queue_config(priv, CmdPtr, pdata_buf);
++ break;
++ case HostCmd_CMD_WMM_QUEUE_STATS:
++ ret = wlan_cmd_wmm_queue_stats(priv, CmdPtr, pdata_buf);
++ break;
++ case HostCmd_CMD_TX_PKT_STATS:
++ CmdPtr->Command = wlan_cpu_to_le16(HostCmd_CMD_TX_PKT_STATS);
++ CmdPtr->Size = wlan_cpu_to_le16(S_DS_GEN);
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ case HostCmd_CMD_802_11_TPC_CFG:
++ CmdPtr->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_TPC_CFG);
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_TPC_CFG) + S_DS_GEN);
++
++ memmove(&CmdPtr->params.tpccfg,
++ pdata_buf, sizeof(HostCmd_DS_802_11_TPC_CFG));
++ CmdPtr->params.tpccfg.Action =
++ wlan_cpu_to_le16(CmdPtr->params.tpccfg.Action);
++
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ case HostCmd_CMD_802_11_LED_CONTROL:
++ {
++ HostCmd_DS_802_11_LED_CTRL *pLedCtrl = &CmdPtr->params.ledgpio;
++ MrvlIEtypes_LedGpio_t *gpio = &pLedCtrl->LedGpio;
++ MrvlIEtypes_LedBehavior_t *pLedBehavior = pLedCtrl->LedBehavior;
++
++ memmove(&CmdPtr->params.ledgpio,
++ pdata_buf, sizeof(HostCmd_DS_802_11_LED_CTRL));
++
++ CmdPtr->Command =
++ wlan_cpu_to_le16(HostCmd_CMD_802_11_LED_CONTROL);
++
++#define ACTION_NUMLED_TLVTYPE_LEN_FIELDS_LEN 8
++ CmdPtr->Size = wlan_cpu_to_le16(gpio->Header.Len + S_DS_GEN
++ +
++ ACTION_NUMLED_TLVTYPE_LEN_FIELDS_LEN);
++
++ pLedCtrl->Action = wlan_cpu_to_le16(pLedCtrl->Action);
++ pLedCtrl->LedNums = wlan_cpu_to_le16(pLedCtrl->LedNums);
++
++ gpio->Header.Type = wlan_cpu_to_le16(gpio->Header.Type);
++ gpio->Header.Len = wlan_cpu_to_le16(gpio->Header.Len);
++
++ pLedBehavior->Header.Type =
++ wlan_cpu_to_le16(pLedBehavior->Header.Type);
++ pLedBehavior->Header.Len =
++ wlan_cpu_to_le16(pLedBehavior->Header.Len);
++
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ }
++ case HostCmd_CMD_802_11_SLEEP_PERIOD:
++ ret = wlan_cmd_802_11_sleep_period(priv, CmdPtr,
++ cmd_action, pdata_buf);
++ break;
++ case HostCmd_CMD_GET_TSF:
++ CmdPtr->Command = wlan_cpu_to_le16(HostCmd_CMD_GET_TSF);
++ CmdPtr->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_GET_TSF)
++ + S_DS_GEN);
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ case HostCmd_CMD_802_11_TX_RATE_QUERY:
++ CmdPtr->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_TX_RATE_QUERY);
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_TX_RATE_QUERY) + S_DS_GEN);
++ Adapter->TxRate = 0;
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ case HostCmd_CMD_802_11_IBSS_COALESCING_STATUS:
++ ret =
++ wlan_cmd_802_11_IBSS_Coalesced_Status(priv, CmdPtr, cmd_action,
++ pdata_buf);
++ break;
++
++ case HostCmd_CMD_SDIO_GPIO_INT_CONFIG:
++ {
++ HostCmd_DS_SDIO_INT_CONFIG *pSdioIntConf =
++ &CmdPtr->params.sdio_int;
++
++ CmdPtr->Command =
++ wlan_cpu_to_le16(HostCmd_CMD_SDIO_GPIO_INT_CONFIG);
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_SDIO_INT_CONFIG) +
++ S_DS_GEN);
++
++ memcpy(pSdioIntConf, pdata_buf,
++ sizeof(HostCmd_DS_SDIO_INT_CONFIG));
++ pSdioIntConf->Action = wlan_cpu_to_le16(pSdioIntConf->Action);
++ pSdioIntConf->Gpio_pin = wlan_cpu_to_le16(pSdioIntConf->Gpio_pin);
++ pSdioIntConf->Gpio_int_edge =
++ wlan_cpu_to_le16(pSdioIntConf->Gpio_int_edge);
++ pSdioIntConf->Gpio_pulse_width =
++ wlan_cpu_to_le16(pSdioIntConf->Gpio_pulse_width);
++
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ }
++
++ case HostCmd_CMD_SDIO_PULL_CTRL:
++ {
++ HostCmd_DS_SDIO_PULL_CTRL *pSdiopullctl =
++ &CmdPtr->params.sdiopullctl;
++
++ CmdPtr->Command = wlan_cpu_to_le16(HostCmd_CMD_SDIO_PULL_CTRL);
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_SDIO_PULL_CTRL) +
++ S_DS_GEN);
++
++ memcpy(pSdiopullctl, pdata_buf,
++ sizeof(HostCmd_DS_SDIO_PULL_CTRL));
++ pSdiopullctl->Action = wlan_cpu_to_le16(pSdiopullctl->Action);
++ pSdiopullctl->PullUp = wlan_cpu_to_le16(pSdiopullctl->PullUp);
++ pSdiopullctl->PullDown = wlan_cpu_to_le16(pSdiopullctl->PullDown);
++
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ }
++
++ case HostCmd_CMD_802_11_LDO_CONFIG:
++ CmdPtr->Command = wlan_cpu_to_le16(cmd_no);
++ CmdPtr->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_LDO_CONFIG) + S_DS_GEN);
++ memcpy(&CmdPtr->params.ldocfg, pdata_buf,
++ sizeof(HostCmd_DS_802_11_LDO_CONFIG));
++ CmdPtr->params.ldocfg.Action =
++ wlan_cpu_to_le16(CmdPtr->params.ldocfg.Action);
++ CmdPtr->params.ldocfg.PMSource =
++ wlan_cpu_to_le16(CmdPtr->params.ldocfg.PMSource);
++ break;
++
++ case HostCmd_CMD_VERSION_EXT:
++ CmdPtr->Command = wlan_cpu_to_le16(cmd_no);
++ memcpy(&CmdPtr->params, pdata_buf, sizeof(HostCmd_DS_VERSION_EXT));
++ CmdPtr->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_VERSION_EXT)
++ + S_DS_GEN);
++ break;
++
++ default:
++ PRINTM(INFO, "PREP_CMD: unknown command- %#x\n", cmd_no);
++ ret = WLAN_STATUS_FAILURE;
++ break;
++ }
++
++ /* return error, since the command preparation failed */
++ if (ret != WLAN_STATUS_SUCCESS) {
++ PRINTM(ERROR, "PREP_CMD: Command 0x%x preparation failed\n", cmd_no);
++ CleanupAndInsertCmd(priv, CmdNode);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ PRINTM(CMND, "PREP_CMD: 0x%x\n", cmd_no);
++
++ CmdNode->CmdWaitQWoken = FALSE;
++ QueueCmd(Adapter, CmdNode, TRUE);
++ wake_up_interruptible(&priv->MainThread.waitQ);
++
++ if (wait_option & HostCmd_OPTION_WAITFORRSP) {
++ PRINTM(INFO, "PREP_CMD: Wait for CMD response...\n");
++ wait_event_interruptible(CmdNode->cmdwait_q, CmdNode->CmdWaitQWoken);
++ if (Adapter->CurCmdRetCode) {
++ PRINTM(INFO, "PREP_CMD: Command failed with return code=%d\n",
++ Adapter->CurCmdRetCode);
++ Adapter->CurCmdRetCode = 0;
++ ret = WLAN_STATUS_FAILURE;
++ }
++ }
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function allocates the command buffer and link
++ * it to command free queue.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++AllocateCmdBuffer(wlan_private * priv)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ u32 ulBufSize;
++ u32 i;
++ CmdCtrlNode *TempCmdArray;
++ u8 *pTempVirtualAddr;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ /* Allocate and initialize CmdCtrlNode */
++ ulBufSize = sizeof(CmdCtrlNode) * MRVDRV_NUM_OF_CMD_BUFFER;
++
++ if (!(TempCmdArray = kmalloc(ulBufSize, GFP_KERNEL))) {
++ PRINTM(INFO, "ALLOC_CMD_BUF: Failed to allocate TempCmdArray\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ Adapter->CmdArray = TempCmdArray;
++ memset(Adapter->CmdArray, 0, ulBufSize);
++
++ /* Allocate and initialize command buffers */
++ ulBufSize = MRVDRV_SIZE_OF_CMD_BUFFER;
++ for (i = 0; i < MRVDRV_NUM_OF_CMD_BUFFER; i++) {
++ if (!(pTempVirtualAddr = kmalloc(ulBufSize, GFP_KERNEL))) {
++ PRINTM(INFO, "ALLOC_CMD_BUF: pTempVirtualAddr: out of memory\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ memset(pTempVirtualAddr, 0, ulBufSize);
++
++ /* Update command buffer virtual */
++ TempCmdArray[i].BufVirtualAddr = pTempVirtualAddr;
++ }
++
++ for (i = 0; i < MRVDRV_NUM_OF_CMD_BUFFER; i++) {
++ init_waitqueue_head(&TempCmdArray[i].cmdwait_q);
++ CleanupAndInsertCmd(priv, &TempCmdArray[i]);
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function frees the command buffer.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++FreeCmdBuffer(wlan_private * priv)
++{
++ u32 ulBufSize;
++ UINT i;
++ CmdCtrlNode *TempCmdArray;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ /* need to check if cmd array is allocated or not */
++ if (Adapter->CmdArray == NULL) {
++ PRINTM(INFO, "FREE_CMD_BUF: CmdArray is Null\n");
++ goto done;
++ }
++
++ TempCmdArray = Adapter->CmdArray;
++
++ /* Release shared memory buffers */
++ ulBufSize = MRVDRV_SIZE_OF_CMD_BUFFER;
++ for (i = 0; i < MRVDRV_NUM_OF_CMD_BUFFER; i++) {
++ if (TempCmdArray[i].BufVirtualAddr) {
++ PRINTM(INFO, "Free all the array\n");
++ kfree(TempCmdArray[i].BufVirtualAddr);
++ TempCmdArray[i].BufVirtualAddr = NULL;
++ }
++ }
++
++ /* Release CmdCtrlNode */
++ if (Adapter->CmdArray) {
++ PRINTM(INFO, "Free CmdArray\n");
++ kfree(Adapter->CmdArray);
++ Adapter->CmdArray = NULL;
++ }
++
++ done:
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function gets a free command node if available in
++ * command free queue.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return CmdCtrlNode A pointer to CmdCtrlNode structure or NULL
++ */
++CmdCtrlNode *
++GetFreeCmdCtrlNode(wlan_private * priv)
++{
++ CmdCtrlNode *TempNode;
++ wlan_adapter *Adapter = priv->adapter;
++ ulong flags;
++
++ ENTER();
++
++ if (!Adapter)
++ return NULL;
++
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++
++ if (!list_empty(&Adapter->CmdFreeQ)) {
++ TempNode = (CmdCtrlNode *) Adapter->CmdFreeQ.next;
++ list_del((struct list_head *) TempNode);
++ } else {
++ PRINTM(WARN, "GET_CMD_NODE: CmdCtrlNode is not available\n");
++ TempNode = NULL;
++ }
++
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ if (TempNode) {
++ CleanUpCmdCtrlNode(TempNode);
++ }
++
++ LEAVE();
++ return TempNode;
++}
++
++/**
++ * @brief This function cleans command node.
++ *
++ * @param pTempNode A pointer to CmdCtrlNode structure
++ * @return n/a
++ */
++void
++CleanUpCmdCtrlNode(CmdCtrlNode * pTempNode)
++{
++ ENTER();
++
++ if (!pTempNode)
++ return;
++ pTempNode->CmdWaitQWoken = TRUE;
++
++ if (pTempNode->wait_option & HostCmd_OPTION_WAITFORRSP) {
++ wake_up_interruptible(&pTempNode->cmdwait_q);
++ }
++ pTempNode->Status = 0;
++ pTempNode->cmd_oid = (WLAN_OID) 0;
++ pTempNode->wait_option = 0;
++ pTempNode->CmdFlags = 0;
++ pTempNode->pdata_buf = NULL;
++
++ if (pTempNode->BufVirtualAddr != NULL)
++ memset(pTempNode->BufVirtualAddr, 0, MRVDRV_SIZE_OF_CMD_BUFFER);
++
++ LEAVE();
++ return;
++}
++
++/**
++ * @brief This function initializes the command node.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pTempNode A pointer to CmdCtrlNode structure
++ * @param cmd_oid cmd oid: treated as sub command
++ * @param wait_option wait option: wait response or not
++ * @param pdata_buf A pointer to informaion buffer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++void
++SetCmdCtrlNode(wlan_private * priv,
++ CmdCtrlNode * pTempNode,
++ WLAN_OID cmd_oid, u16 wait_option, void *pdata_buf)
++{
++ ENTER();
++
++ if (!pTempNode)
++ return;
++
++ pTempNode->cmd_oid = cmd_oid;
++ pTempNode->wait_option = wait_option;
++ pTempNode->pdata_buf = pdata_buf;
++
++ LEAVE();
++}
++
++/**
++ * @brief This function executes next command in command
++ * pending queue. It will put fimware back to PS mode
++ * if applicable.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++ExecuteNextCommand(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ CmdCtrlNode *CmdNode = NULL;
++ HostCmd_DS_COMMAND *CmdPtr;
++ ulong flags;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (!Adapter) {
++ PRINTM(MSG, "EXEC_NEXT_CMD: Adapter is NULL\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++
++ if (Adapter->CurCmd) {
++ PRINTM(MSG, "EXEC_NEXT_CMD: there is command in processing!\n");
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ if (!list_empty(&Adapter->CmdPendingQ)) {
++ CmdNode = (CmdCtrlNode *)
++ Adapter->CmdPendingQ.next;
++ }
++
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ if (CmdNode) {
++ CmdPtr = (HostCmd_DS_COMMAND *) CmdNode->BufVirtualAddr;
++
++ if (Is_Command_Allowed_In_PS(CmdPtr->Command)) {
++ if ((Adapter->PSState == PS_STATE_SLEEP)
++ || (Adapter->PSState == PS_STATE_PRE_SLEEP)
++ ) {
++ PRINTM(INFO,
++ "EXEC_NEXT_CMD: Cannot send cmd 0x%x in PSState %d\n",
++ CmdPtr->Command, Adapter->PSState);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ PRINTM(INFO, "EXEC_NEXT_CMD: OK to send command "
++ "0x%x in PSState %d\n", CmdPtr->Command, Adapter->PSState);
++ } else if (Adapter->PSState != PS_STATE_FULL_POWER) {
++ /*
++ * 1. Non-PS command:
++ * Queue it. set NeedToWakeup to TRUE if current state
++ * is SLEEP, otherwise call PSWakeup to send Exit_PS.
++ * 2. PS command but not Exit_PS:
++ * Ignore it.
++ * 3. PS command Exit_PS:
++ * Set NeedToWakeup to TRUE if current state is SLEEP,
++ * otherwise send this command down to firmware
++ * immediately.
++ */
++ if (CmdPtr->Command !=
++ wlan_cpu_to_le16(HostCmd_CMD_802_11_PS_MODE)) {
++ /* Prepare to send Exit PS,
++ * this non PS command will be sent later */
++ if ((Adapter->PSState == PS_STATE_SLEEP)
++ || (Adapter->PSState == PS_STATE_PRE_SLEEP)
++ ) {
++ /* w/ new scheme, it will not reach here.
++ since it is blocked in main_thread. */
++ Adapter->NeedToWakeup = TRUE;
++ } else
++ PSWakeup(priv, 0);
++
++ ret = WLAN_STATUS_SUCCESS;
++ goto done;
++ } else {
++ /*
++ * PS command. Ignore it if it is not Exit_PS.
++ * otherwise send it down immediately.
++ */
++ HostCmd_DS_802_11_PS_MODE *psm = &CmdPtr->params.psmode;
++
++ PRINTM(INFO, "EXEC_NEXT_CMD: PS cmd- Action=0x%x\n",
++ psm->Action);
++ if (psm->Action != wlan_cpu_to_le16(HostCmd_SubCmd_Exit_PS)) {
++ PRINTM(INFO, "EXEC_NEXT_CMD: Ignore Enter PS cmd\n");
++ list_del((struct list_head *) CmdNode);
++ CleanupAndInsertCmd(priv, CmdNode);
++
++ ret = WLAN_STATUS_SUCCESS;
++ goto done;
++ }
++
++ if ((Adapter->PSState == PS_STATE_SLEEP)
++ || (Adapter->PSState == PS_STATE_PRE_SLEEP)
++ ) {
++ PRINTM(INFO,
++ "EXEC_NEXT_CMD: Ignore ExitPS cmd in sleep\n");
++ list_del((struct list_head *) CmdNode);
++ CleanupAndInsertCmd(priv, CmdNode);
++ Adapter->NeedToWakeup = TRUE;
++
++ ret = WLAN_STATUS_SUCCESS;
++ goto done;
++ }
++
++ PRINTM(INFO, "EXEC_NEXT_CMD: Sending Exit_PS down...\n");
++ }
++ }
++ list_del((struct list_head *) CmdNode);
++ DownloadCommandToStation(priv, CmdNode);
++ } else {
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ /*
++ * check if in power save mode, if yes, put the device back
++ * to PS mode
++ */
++ if ((Adapter->PSMode != Wlan802_11PowerModeCAM) &&
++ (Adapter->PSState == PS_STATE_FULL_POWER)) {
++ if (Adapter->SecInfo.WPAEnabled
++ || Adapter->SecInfo.WPA2Enabled) {
++ if (Adapter->IsGTK_SET) {
++ PRINTM(INFO, "EXEC_NEXT_CMD: WPA enabled and GTK_SET"
++ " go back to PS_SLEEP");
++ PSSleep(priv, 0);
++ }
++ } else {
++ if ((Adapter->InfrastructureMode != Wlan802_11IBSS)
++ || Adapter->CurBssParams.BSSDescriptor.ATIMWindow) {
++ PRINTM(INFO, "EXEC_NEXT_CMD: Command PendQ is empty,"
++ " go back to PS_SLEEP");
++ PSSleep(priv, 0);
++ }
++ }
++ }
++ } else {
++ /*
++ * check if in auto deep sleep mode, if yes, put the device back
++ * to DS mode
++ */
++ if (Adapter->IsAutoDeepSleepEnabled && !Adapter->IntCounter) {
++ PRINTM(INFO, "Entering Auto Deep Sleep mode...\n");
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_DEEP_SLEEP, 0,
++ 0, 0, NULL);
++ }
++ }
++ /* The hs_activate command is sent when Host Sleep is configured
++ and de-activated in full power mode. */
++ if (Adapter->bHostSleepConfigured && !Adapter->HS_Activated
++ && ((Adapter->MediaConnectStatus == WlanMediaStateConnected)
++ || (!Adapter->IsAutoDeepSleepEnabled))
++ && (((Adapter->PSMode == Wlan802_11PowerModeCAM)
++ && (Adapter->PSState == PS_STATE_FULL_POWER))
++ || ((Adapter->InfrastructureMode == Wlan802_11IBSS)
++ && !Adapter->CurBssParams.BSSDescriptor.ATIMWindow)
++ )) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_HOST_SLEEP_ACTIVATE,
++ 0, 0, 0, NULL);
++ }
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function handles the timeout of command sending.
++ * It will re-send the same command again.
++ *
++ * @param FunctionContext A pointer to FunctionContext
++ * @return n/a
++ */
++void
++MrvDrvCommandTimerFunction(void *FunctionContext)
++{
++ wlan_private *priv = (wlan_private *) FunctionContext;
++ wlan_adapter *Adapter = priv->adapter;
++ CmdCtrlNode *pTempNode;
++ HostCmd_DS_COMMAND *CmdPtr;
++
++ ENTER();
++
++ PRINTM(CMND, "Command timeout.\n");
++
++ Adapter->CommandTimerIsSet = FALSE;
++
++ if (!Adapter->num_cmd_timeout)
++ Adapter->dbg.num_cmd_timeout++;
++
++ pTempNode = Adapter->CurCmd;
++
++ if (pTempNode == NULL) {
++ PRINTM(INFO, "CurCmd Empty\n");
++ goto exit;
++ }
++
++ CmdPtr = (HostCmd_DS_COMMAND *) pTempNode->BufVirtualAddr;
++ if (CmdPtr == NULL) {
++ goto exit;
++ }
++
++ if (CmdPtr->Size) {
++ Adapter->dbg.TimeoutCmdId = wlan_cpu_to_le16(CmdPtr->Command);
++ Adapter->dbg.TimeoutCmdAct =
++ wlan_cpu_to_le16(*(u16 *) ((u8 *) CmdPtr + S_DS_GEN));
++ PRINTM(CMND, "Timeout cmd = 0x%x, act = 0x%x\n",
++ Adapter->dbg.TimeoutCmdId, Adapter->dbg.TimeoutCmdAct);
++ }
++#define MAX_CMD_TIMEOUT_COUNT 3
++ Adapter->num_cmd_timeout++;
++ if (Adapter->num_cmd_timeout > MAX_CMD_TIMEOUT_COUNT) {
++ PRINTM(FATAL, "num_cmd_timeout=%d\n", Adapter->num_cmd_timeout);
++ goto exit;
++ }
++
++ /* Restart the timer to trace command response again */
++ ModTimer(&Adapter->MrvDrvCommandTimer, MRVDRV_TIMER_1S);
++ Adapter->CommandTimerIsSet = TRUE;
++
++ /* Wake up main thread to read int status register */
++ Adapter->IntCounter++;
++ wake_up_interruptible(&priv->MainThread.waitQ);
++
++ exit:
++ LEAVE();
++ return;
++}
++
++/**
++ * @brief This function sends sleep confirm command to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmdptr A pointer to the command
++ * @param size the size of command
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++SendConfirmSleep(wlan_private * priv, u8 * CmdPtr, u16 size)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ static u32 i = 0;
++
++ ENTER();
++
++ HEXDUMP("SLEEP_CFM", CmdPtr, size);
++
++ ret = sbi_host_to_card(priv, MVMS_CMD, CmdPtr, size);
++ priv->wlan_dev.dnld_sent = DNLD_RES_RECEIVED;
++
++ if (ret) {
++ PRINTM(MSG, "SLEEP_CFM: sbi_host_to_card() failed\n");
++ Adapter->dbg.num_cmd_sleep_cfm_host_to_card_failure++;
++ } else {
++ Adapter->PSState = PS_STATE_SLEEP;
++
++ if (Adapter->bHostSleepConfigured &&
++ (Adapter->sleep_period.period == 0)) {
++ Adapter->bWakeupDevRequired = TRUE;
++
++ wlan_host_sleep_activated_event(priv);
++ }
++#define NUM_SC_PER_LINE 16
++ if (++i % NUM_SC_PER_LINE == 0) {
++ PRINTM(EVENT, "+\n");
++ } else {
++ PRINTM(EVENT, "+");
++ }
++
++ /* check if interrupt is received after sleep confirm */
++ if (Adapter->IntCounter) {
++ PRINTM(INFO, "SLEEP_CFM: After sent, IntCnt=%d\n",
++ Adapter->IntCounter);
++ Adapter->PSState = PS_STATE_AWAKE;
++
++ }
++
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function sends Enter_PS command to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wait_option wait response or not
++ * @return n/a
++ */
++void
++PSSleep(wlan_private * priv, int wait_option)
++{
++
++ ENTER();
++
++ PrepareAndSendCommand(priv, HostCmd_CMD_802_11_PS_MODE,
++ HostCmd_SubCmd_Enter_PS, wait_option, 0, NULL);
++
++ LEAVE();
++ return;
++}
++
++/**
++ * @brief This function sends Eixt_PS command to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wait_option wait response or not
++ * @return n/a
++ */
++void
++PSWakeup(wlan_private * priv, int wait_option)
++{
++ WLAN_802_11_POWER_MODE LocalPSMode;
++
++ ENTER();
++
++ LocalPSMode = Wlan802_11PowerModeCAM;
++
++ PrepareAndSendCommand(priv, HostCmd_CMD_802_11_PS_MODE,
++ HostCmd_SubCmd_Exit_PS,
++ wait_option, 0, &LocalPSMode);
++
++ LEAVE();
++ return;
++}
++
++/**
++ * @brief This function checks condition and prepares to
++ * send sleep confirm command to firmware if ok.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param PSMode Power Saving mode
++ * @return n/a
++ */
++void
++PSConfirmSleep(wlan_private * priv, u16 PSMode)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!priv->wlan_dev.dnld_sent && !Adapter->CurCmd && !Adapter->IntCounter) {
++ SendConfirmSleep(priv, (u8 *) & Adapter->PSConfirmSleep,
++ sizeof(PS_CMD_ConfirmSleep));
++
++ os_start_queue(priv);
++ } else {
++ PRINTM(INFO, "Delay Sleep Confirm (%s%s%s)\n",
++ (priv->wlan_dev.dnld_sent) ? "D" : "",
++ (Adapter->CurCmd) ? "C" : "",
++ (Adapter->IntCounter) ? "I" : "");
++ }
++
++ LEAVE();
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_cmdresp.c b/drivers/net/wireless/marvell8686/wlan_cmdresp.c
+new file mode 100644
+index 0000000..780c997
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_cmdresp.c
+@@ -0,0 +1,1595 @@
++/** @file wlan_cmdresp.c
++ * @brief This file contains the handling of command
++ * responses as well as events generated by firmware.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 10/10/05: Add Doxygen format comments
++ 11/11/05: Add support for WMM Status change event
++ 12/13/05: Add Proprietary periodic sleep support
++ 12/23/05: Fix bug in adhoc start where the current index was
++ not properly being assigned before it was used.
++ 01/05/06: Add kernel 2.6.x support
++ 01/11/06: Conditionalize new scan/join structures.
++ Update assoc response handling; entire IEEE response returned
++ 04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
++ 04/10/06: Add hostcmd generic API
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 05/04/06: Add IBSS coalescing related new hostcmd response handling
++ 05/08/06: Remove PermanentAddr from Adapter
++ 06/08/06: Remove function HandleMICFailureEvent()
++ 08/29/06: Add ledgpio private command
++********************************************************/
++
++#include "include.h"
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function handles disconnect event. it
++ * reports disconnect to upper layer, clean tx/rx packets,
++ * reset link state etc.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++void
++MacEventDisconnected(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ union iwreq_data wrqu;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus != WlanMediaStateConnected)
++ return;
++
++ PRINTM(INFO, "Handles disconnect event.\n");
++
++ /* Free Tx and Rx packets, report disconnect to upper layer */
++ wlan_clean_txrx(priv);
++
++ memset(wrqu.ap_addr.sa_data, 0x00, ETH_ALEN);
++ wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWAP, &wrqu, NULL);
++
++ /* reset SNR/NF/RSSI values */
++ memset(Adapter->SNR, 0x00, sizeof(Adapter->SNR));
++ memset(Adapter->NF, 0x00, sizeof(Adapter->NF));
++ memset(Adapter->RSSI, 0x00, sizeof(Adapter->RSSI));
++ memset(Adapter->rawSNR, 0x00, sizeof(Adapter->rawSNR));
++ memset(Adapter->rawNF, 0x00, sizeof(Adapter->rawNF));
++ Adapter->nextSNRNF = 0;
++ Adapter->numSNRNF = 0;
++ Adapter->RxPDRate = 0;
++ PRINTM(INFO, "Current SSID=%s, Ssid Length=%u\n",
++ Adapter->CurBssParams.BSSDescriptor.Ssid.Ssid,
++ Adapter->CurBssParams.BSSDescriptor.Ssid.SsidLength);
++ PRINTM(INFO, "Previous SSID=%s, Ssid Length=%u\n",
++ Adapter->PreviousSSID.Ssid, Adapter->PreviousSSID.SsidLength);
++
++ Adapter->SecInfo.WPAEnabled = FALSE;
++ Adapter->SecInfo.WPA2Enabled = FALSE;
++ Adapter->Wpa_ie_len = 0;
++ Adapter->SecInfo.EncryptionMode = CIPHER_NONE;
++
++ Adapter->MediaConnectStatus = WlanMediaStateDisconnected;
++
++ Adapter->AdhocLinkSensed = FALSE;
++
++ /*
++ * memorize the previous SSID and BSSID
++ * it could be used for re-assoc
++ */
++ memcpy(&Adapter->PreviousSSID,
++ &Adapter->CurBssParams.BSSDescriptor.Ssid,
++ sizeof(WLAN_802_11_SSID));
++ memcpy(Adapter->PreviousBSSID,
++ Adapter->CurBssParams.BSSDescriptor.MacAddress, ETH_ALEN);
++
++ /* need to erase the current SSID and BSSID info */
++ memset(&Adapter->CurBssParams, 0x00, sizeof(Adapter->CurBssParams));
++
++ if (Adapter->PSState != PS_STATE_FULL_POWER) {
++ /* make firmware to exit PS mode */
++ PRINTM(INFO, "Disconnected, so exit PS mode.\n");
++ PSWakeup(priv, 0);
++ }
++
++ LEAVE();
++}
++
++/**
++ * @brief This function handles link lost, deauth and
++ * disassoc events.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++static void
++HandleDisconnectEvent(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ MacEventDisconnected(priv);
++#ifdef REASSOCIATION
++ if (Adapter->Reassoc_on == TRUE) {
++ PRINTM(INFO, "RE-ASSOC: trigger the timer\n");
++ Adapter->ReassocTimerIsSet = TRUE;
++ ModTimer(&Adapter->MrvDrvTimer, 0);
++ }
++#endif /* REASSOCIATION */
++ }
++}
++
++/**
++ * @brief This function handles the command response of reg_access
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param type the type of reg access (MAC, BBP or RF)
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_reg_access(wlan_private * priv, u16 type, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_offset_value *pOffsetValue =
++ (wlan_offset_value *) Adapter->CurCmd->pdata_buf;
++
++ ENTER();
++
++ switch (type) {
++ case HostCmd_RET_MAC_REG_ACCESS:
++ {
++ HostCmd_DS_MAC_REG_ACCESS *reg;
++
++ reg = (HostCmd_DS_MAC_REG_ACCESS *) & resp->params.macreg;
++
++ pOffsetValue->offset = wlan_le16_to_cpu(reg->Offset);
++ pOffsetValue->value = wlan_le32_to_cpu(reg->Value);
++ break;
++ }
++
++ case HostCmd_RET_BBP_REG_ACCESS:
++ {
++ HostCmd_DS_BBP_REG_ACCESS *reg;
++ reg = (HostCmd_DS_BBP_REG_ACCESS *) & resp->params.bbpreg;
++
++ pOffsetValue->offset = wlan_le16_to_cpu(reg->Offset);
++ pOffsetValue->value = (u8) reg->Value;
++ break;
++ }
++
++ case HostCmd_RET_RF_REG_ACCESS:
++ {
++ HostCmd_DS_RF_REG_ACCESS *reg;
++ reg = (HostCmd_DS_RF_REG_ACCESS *) & resp->params.rfreg;
++
++ pOffsetValue->offset = wlan_le16_to_cpu(reg->Offset);
++ pOffsetValue->value = (u8) reg->Value;
++ break;
++ }
++
++ default:
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of get_hw_spec
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_get_hw_spec(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ u32 i;
++ HostCmd_DS_GET_HW_SPEC *hwspec = &resp->params.hwspec;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ Adapter->fwCapInfo = wlan_le32_to_cpu(hwspec->fwCapInfo);
++
++ Adapter->FWReleaseNumber = wlan_le32_to_cpu(hwspec->FWReleaseNumber);
++
++ PRINTM(INFO, "GET_HW_SPEC: FWReleaseVersion- 0x%X\n",
++ Adapter->FWReleaseNumber);
++ PRINTM(INFO, "GET_HW_SPEC: Permanent addr- %2x:%2x:%2x:%2x:%2x:%2x\n",
++ hwspec->PermanentAddr[0], hwspec->PermanentAddr[1],
++ hwspec->PermanentAddr[2], hwspec->PermanentAddr[3],
++ hwspec->PermanentAddr[4], hwspec->PermanentAddr[5]);
++ PRINTM(INFO, "GET_HW_SPEC: HWIfVersion=0x%X Version=0x%X\n",
++ wlan_le16_to_cpu(hwspec->HWIfVersion),
++ wlan_le16_to_cpu(hwspec->Version));
++
++ Adapter->RegionCode = wlan_le16_to_cpu(hwspec->RegionCode);
++
++ for (i = 0; i < MRVDRV_MAX_REGION_CODE; i++) {
++ /* use the region code to search for the index */
++ if (Adapter->RegionCode == RegionCodeToIndex[i]) {
++ break;
++ }
++ }
++
++ /* if it's unidentified region code, use the default (USA) */
++ if (i >= MRVDRV_MAX_REGION_CODE) {
++ Adapter->RegionCode = 0x10;
++ PRINTM(WARN, "unidentified region code, use the default (USA)\n");
++ }
++
++ /* HACK IT MAKE RegionCode always equals 0x30 */
++ Adapter->RegionCode = 0x30;
++
++ if (Adapter->CurrentAddr[0] == 0xff) {
++ memmove(Adapter->CurrentAddr, hwspec->PermanentAddr, ETH_ALEN);
++ }
++ /* HACK PermanentAddr[0] Equals 0xFF */
++ if (Adapter->CurrentAddr[0] == 0xff) {
++ Adapter->CurrentAddr[0] = 0x00;
++ Adapter->CurrentAddr[1] = 0x1a;
++ Adapter->CurrentAddr[2] = 0x6b;
++ }
++ memcpy(priv->wlan_dev.netdev->dev_addr, Adapter->CurrentAddr, ETH_ALEN);
++
++ if (wlan_set_regiontable(priv, Adapter->RegionCode, 0)) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ if (wlan_set_universaltable(priv, 0)) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function handles the command response of host_sleep_cfg
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_host_sleep_cfg(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_HOST_SLEEP_CFG *hscfg = &resp->params.hostsleepcfg;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (hscfg->conditions != HOST_SLEEP_CFG_CANCEL) {
++ Adapter->bHostSleepConfigured = TRUE;
++ } else {
++ Adapter->bHostSleepConfigured = FALSE;
++ if (Adapter->PSState == PS_STATE_FULL_POWER && Adapter->HS_Activated) {
++ wlan_host_sleep_deactivated_event(priv);
++ }
++ os_start_queue(priv);
++ os_carrier_on(priv);
++ wmm_start_queue(priv);
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function handles the command response of fw_wakeup_method
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_fw_wakeup_method(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_FW_WAKEUP_METHOD *fwwm = &resp->params.fwwakeupmethod;
++ u16 action;
++
++ ENTER();
++
++ action = wlan_le16_to_cpu(fwwm->Action);
++
++ switch (action) {
++ case HostCmd_ACT_GET:
++ case HostCmd_ACT_SET:
++ Adapter->fwWakeupMethod = wlan_le16_to_cpu(fwwm->Method);
++ break;
++ default:
++ break;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of sleep_params
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_sleep_params(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_SLEEP_PARAMS *sp = &resp->params.sleep_params;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ PRINTM(INFO, "error=%x offset=%x stabletime=%x calcontrol=%x\n"
++ " extsleepclk=%x\n", sp->Error, sp->Offset,
++ sp->StableTime, sp->CalControl, sp->ExternalSleepClk);
++ Adapter->sp.sp_error = wlan_le16_to_cpu(sp->Error);
++ Adapter->sp.sp_offset = wlan_le16_to_cpu(sp->Offset);
++ Adapter->sp.sp_stabletime = wlan_le16_to_cpu(sp->StableTime);
++ Adapter->sp.sp_calcontrol = wlan_le16_to_cpu(sp->CalControl);
++ Adapter->sp.sp_extsleepclk = wlan_le16_to_cpu(sp->ExternalSleepClk);
++ Adapter->sp.sp_reserved = wlan_le16_to_cpu(sp->Reserved);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of sleep_params
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_sleep_period(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_SLEEP_PERIOD *sp_period = &resp->params.ps_sleeppd;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ Adapter->sleep_period.period = wlan_le16_to_cpu(sp_period->Period);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of bca_timeshare
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_bca_timeshare(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_BCA_TIMESHARE *bca_ts = &resp->params.bca_timeshare;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ PRINTM(MSG, "TrafficType=%x TimeShareInterva=%x BTTime=%x\n",
++ bca_ts->TrafficType, bca_ts->TimeShareInterval, bca_ts->BTTime);
++
++ Adapter->bca_ts.TrafficType = wlan_le16_to_cpu(bca_ts->TrafficType);
++ Adapter->bca_ts.TimeShareInterval =
++ wlan_le32_to_cpu(bca_ts->TimeShareInterval);
++ Adapter->bca_ts.BTTime = wlan_le32_to_cpu(bca_ts->BTTime);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of mac_control
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_mac_control(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of set_wep
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_set_wep(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of reset
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_reset(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ ENTER();
++ PRINTM(INFO, "HWAC - Reset command successful\n");
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of snmp_mib
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_snmp_mib(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_SNMP_MIB *smib = &resp->params.smib;
++ u16 OID = wlan_le16_to_cpu(smib->OID);
++ u16 QueryType = wlan_le16_to_cpu(smib->QueryType);
++
++ ENTER();
++
++ PRINTM(INFO, "SNMP_RESP: value of the OID = %x, QueryType=%x\n", OID,
++ QueryType);
++ PRINTM(INFO, "SNMP_RESP: Buf size = %x\n",
++ wlan_le16_to_cpu(smib->BufSize));
++
++ if (QueryType == HostCmd_ACT_GEN_GET) {
++ switch (OID) {
++ case FragThresh_i:
++ priv->adapter->FragThsd =
++ wlan_le16_to_cpu(*((PUSHORT) (smib->Value)));
++ PRINTM(INFO, "SNMP_RESP: FragThsd =%u\n",
++ priv->adapter->FragThsd);
++ break;
++ case RtsThresh_i:
++ priv->adapter->RTSThsd =
++ wlan_le16_to_cpu(*((PUSHORT) (smib->Value)));
++ PRINTM(INFO, "SNMP_RESP: RTSThsd =%u\n", priv->adapter->RTSThsd);
++ break;
++ case ShortRetryLim_i:
++ priv->adapter->TxRetryCount =
++ wlan_le16_to_cpu(*((PUSHORT) (smib->Value)));
++ PRINTM(INFO, "SNMP_RESP: TxRetryCount =%u\n",
++ priv->adapter->RTSThsd);
++ break;
++ case DtimPeriod_i:
++ priv->adapter->Dtim =
++ wlan_le16_to_cpu(*((PUSHORT) (smib->Value)));
++ PRINTM(INFO, "SNMP_RESP: DtimPeriod =%u\n", priv->adapter->Dtim);
++ break;
++ default:
++ break;
++ }
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of radio_control
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_radio_control(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ ENTER();
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of key_material
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_key_material(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_KEY_MATERIAL *pKey = &resp->params.keymaterial;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wlan_le16_to_cpu(pKey->Action) == HostCmd_ACT_SET) {
++ if ((wlan_le16_to_cpu(pKey->KeyParamSet.KeyInfo) &
++ KEY_INFO_TKIP_MCAST)
++ || (wlan_le16_to_cpu(pKey->KeyParamSet.KeyInfo) &
++ KEY_INFO_AES_MCAST)) {
++ PRINTM(INFO, "Key: GTK is set\n");
++ Adapter->IsGTK_SET = TRUE;
++ }
++ }
++
++ memcpy(Adapter->aeskey.KeyParamSet.Key, pKey->KeyParamSet.Key,
++ sizeof(pKey->KeyParamSet.Key));
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of mac_address
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_mac_address(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_MAC_ADDRESS *MacAdd = &resp->params.macadd;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ memcpy(Adapter->CurrentAddr, MacAdd->MacAdd, ETH_ALEN);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of rf_tx_power
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_rf_tx_power(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_RF_TX_POWER *rtp = &resp->params.txp;
++ wlan_adapter *Adapter = priv->adapter;
++ u16 Action = wlan_le16_to_cpu(rtp->Action);
++
++ ENTER();
++
++ Adapter->TxPowerLevel = wlan_le16_to_cpu(rtp->CurrentLevel);
++
++ if (Action == HostCmd_ACT_GET) {
++ Adapter->MaxTxPowerLevel = rtp->MaxPower;
++ Adapter->MinTxPowerLevel = rtp->MinPower;
++ }
++
++ PRINTM(INFO, "Current TxPower Level = %d,Max Power=%d, Min Power=%d\n",
++ Adapter->TxPowerLevel, Adapter->MaxTxPowerLevel,
++ Adapter->MinTxPowerLevel);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of rf_antenna
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_rf_antenna(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_RF_ANTENNA *pAntenna = &resp->params.rant;
++ wlan_adapter *Adapter = priv->adapter;
++ u16 Action = wlan_le16_to_cpu(pAntenna->Action);
++
++ if (Action == HostCmd_ACT_GET_RX)
++ Adapter->RxAntennaMode = wlan_le16_to_cpu(pAntenna->AntennaMode);
++
++ if (Action == HostCmd_ACT_GET_TX)
++ Adapter->TxAntennaMode = wlan_le16_to_cpu(pAntenna->AntennaMode);
++
++ PRINTM(INFO, "RF_ANT_RESP: Action = 0x%x, Mode = 0x%04x\n",
++ Action, wlan_le16_to_cpu(pAntenna->AntennaMode));
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of multicast_address
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_mac_multicast_adr(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of rate_adapt_rateset
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_rate_adapt_rateset(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_RATE_ADAPT_RATESET *rates = &resp->params.rateset;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wlan_le16_to_cpu(rates->Action) == HostCmd_ACT_GET) {
++ Adapter->HWRateDropMode = wlan_le16_to_cpu(rates->HWRateDropMode);
++ Adapter->Threshold = wlan_le16_to_cpu(rates->Threshold);
++ Adapter->FinalRate = wlan_le16_to_cpu(rates->FinalRate);
++ Adapter->RateBitmap = wlan_le16_to_cpu(rates->Bitmap);
++ }
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of rf_channel
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_rf_channel(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_RF_CHANNEL *rfchannel = &resp->params.rfchannel;
++ wlan_adapter *Adapter = priv->adapter;
++ u16 Action = wlan_le16_to_cpu(rfchannel->Action);
++ u16 newChannel = wlan_le16_to_cpu(rfchannel->CurrentChannel);
++
++ ENTER();
++
++ if (Action == HostCmd_OPT_802_11_RF_CHANNEL_GET
++ && Adapter->CurBssParams.BSSDescriptor.Channel != newChannel) {
++ PRINTM(INFO, "Channel Switch: %d to %d\n",
++ Adapter->CurBssParams.BSSDescriptor.Channel, newChannel);
++
++ /* Update the channel again */
++ Adapter->CurBssParams.BSSDescriptor.Channel = newChannel;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of rssi
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_rssi(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_RSSI_RSP *rssirsp = &resp->params.rssirsp;
++ wlan_adapter *Adapter = priv->adapter;
++
++ /* store the non average value */
++ Adapter->SNR[TYPE_BEACON][TYPE_NOAVG] = wlan_le16_to_cpu(rssirsp->SNR);
++ Adapter->NF[TYPE_BEACON][TYPE_NOAVG] =
++ wlan_le16_to_cpu(rssirsp->NoiseFloor);
++
++ Adapter->SNR[TYPE_BEACON][TYPE_AVG] = wlan_le16_to_cpu(rssirsp->AvgSNR);
++ Adapter->NF[TYPE_BEACON][TYPE_AVG] =
++ wlan_le16_to_cpu(rssirsp->AvgNoiseFloor);
++
++ Adapter->RSSI[TYPE_BEACON][TYPE_NOAVG] =
++ CAL_RSSI(Adapter->SNR[TYPE_BEACON][TYPE_NOAVG],
++ Adapter->NF[TYPE_BEACON][TYPE_NOAVG]);
++
++ Adapter->RSSI[TYPE_BEACON][TYPE_AVG] =
++ CAL_RSSI(Adapter->SNR[TYPE_BEACON][TYPE_AVG] / AVG_SCALE,
++ Adapter->NF[TYPE_BEACON][TYPE_AVG] / AVG_SCALE);
++
++ PRINTM(INFO, "Beacon RSSI value = 0x%x\n",
++ Adapter->RSSI[TYPE_BEACON][TYPE_AVG]);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++#ifdef MFG_CMD_SUPPORT
++/**
++ * @brief This function handles the command response of mfg_cmd
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_mfg_cmd(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ PRINTM(INFO, "MFG command response size = %d\n", resp->Size);
++
++ resp->Size = MIN(resp->Size, MRVDRV_SIZE_OF_CMD_BUFFER);
++ memcpy(Adapter->CurCmd->pdata_buf, (void *) resp, resp->Size);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++#endif /* MFG_CMD_SUPPORT */
++
++/**
++ * @brief This function handles the command response of cal_data_ext.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_802_11_cal_data_ext(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_CAL_DATA_EXT *pCalDataExt = &resp->params.caldataext;
++
++ ENTER();
++
++ if (wlan_le16_to_cpu(pCalDataExt->Action) == HostCmd_ACT_GEN_GET) {
++ pCalDataExt->Action = wlan_le16_to_cpu(pCalDataExt->Action);
++ pCalDataExt->Revision = wlan_le16_to_cpu(pCalDataExt->Revision);
++ pCalDataExt->CalDataLen = wlan_le16_to_cpu(pCalDataExt->CalDataLen);
++
++ memmove(Adapter->CurCmd->pdata_buf,
++ pCalDataExt, pCalDataExt->CalDataLen + CAL_DATA_HEADER_LEN);
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of eeprom_access
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_ret_802_11_eeprom_access(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_ioctl_regrdwr *pBuf =
++ (wlan_ioctl_regrdwr *) Adapter->CurCmd->pdata_buf;
++
++ PRINTM(INFO, "eeprom read len=%x\n",
++ wlan_le16_to_cpu(resp->params.rdeeprom.ByteCount));
++ if (pBuf->NOB < wlan_le16_to_cpu(resp->params.rdeeprom.ByteCount)) {
++ pBuf->NOB = 0;
++ PRINTM(INFO, "eeprom read return length is too big\n");
++ return WLAN_STATUS_FAILURE;
++ }
++ pBuf->NOB = wlan_le16_to_cpu(resp->params.rdeeprom.ByteCount);
++ if (pBuf->NOB > 0) {
++ memcpy(&pBuf->Value, (u8 *) & resp->params.rdeeprom.Value, pBuf->NOB);
++ HEXDUMP("EEPROM", (char *) &pBuf->Value, pBuf->NOB);
++ }
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of get_log
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_ret_get_log(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_GET_LOG *LogMessage =
++ (HostCmd_DS_802_11_GET_LOG *) & resp->params.glog;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ /* TODO Convert it to Big Endian before copy */
++ memcpy(&Adapter->LogMsg, LogMessage, sizeof(HostCmd_DS_802_11_GET_LOG));
++ endian_convert_GET_LOG(Adapter->LogMsg);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++static void
++wlan_ret_802_11_IBSS_Coalesced_Status(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_802_11_IBSS_Status *IBSSStatusRsp;
++ wlan_adapter *Adapter;
++ union iwreq_data wrqu;
++ u8 nullMac[6] = { 0, 0, 0, 0, 0, 0 };
++
++ Adapter = priv->adapter;
++ IBSSStatusRsp = &(resp->params.ibssCoalescing);
++
++ if (Adapter->CurCmd->pdata_buf)
++ *(int *) Adapter->CurCmd->pdata_buf = IBSSStatusRsp->Enable;
++
++ if (wlan_le16_to_cpu(IBSSStatusRsp->Action) == HostCmd_ACT_SET) {
++ return;
++ }
++
++ PRINTM(INFO, "New BSSID %x:%x:%x:%x:%x:%x\n",
++ IBSSStatusRsp->BSSID[0],
++ IBSSStatusRsp->BSSID[1],
++ IBSSStatusRsp->BSSID[2],
++ IBSSStatusRsp->BSSID[3],
++ IBSSStatusRsp->BSSID[4], IBSSStatusRsp->BSSID[5]);
++
++ /* if rsp has NULL BSSID, Just return.. No Action */
++ if (!memcmp(IBSSStatusRsp->BSSID, nullMac, MRVDRV_ETH_ADDR_LEN)) {
++ PRINTM(MSG, "New BSSID is NULL\n");
++ return;
++ }
++
++ /* if BSSID is diff, Send evnet to Linux */
++ if (memcmp(Adapter->CurBssParams.BSSDescriptor.MacAddress,
++ IBSSStatusRsp->BSSID, ETH_ALEN)) {
++ memcpy((void *) Adapter->CurBssParams.BSSDescriptor.MacAddress,
++ (void *) IBSSStatusRsp->BSSID, MRVDRV_ETH_ADDR_LEN);
++
++ /* Beacon Interval and ATIM window */
++ Adapter->CurBssParams.BSSDescriptor.BeaconPeriod
++ = IBSSStatusRsp->BeaconInterval;
++ Adapter->CurBssParams.BSSDescriptor.ATIMWindow
++ = IBSSStatusRsp->ATIMWindow;
++ //ERP Information
++ Adapter->CurBssParams.BSSDescriptor.ERPFlags =
++ (u8) IBSSStatusRsp->UseGRateProtection;
++
++ memset(&wrqu, 0, sizeof(wrqu));
++ memcpy(wrqu.ap_addr.sa_data,
++ Adapter->CurBssParams.BSSDescriptor.MacAddress, ETH_ALEN);
++ wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWAP, &wrqu, NULL);
++
++ }
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief This function stop tx/rx queue and free skb
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++void
++wlan_clean_txrx(wlan_private * priv)
++{
++ os_stop_queue(priv);
++ os_carrier_off(priv);
++
++ wmm_stop_queue(priv);
++ wmm_cleanup_queues(priv);
++
++ /* Free Tx and Rx packets */
++ os_free_tx_packet(priv);
++ wlan_send_rxskbQ(priv);
++}
++
++/**
++ * @brief This function handles the command response
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_process_rx_command(wlan_private * priv)
++{
++ u16 RespCmd;
++ HostCmd_DS_COMMAND *resp;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ ulong flags;
++ u16 Result;
++
++ ENTER();
++
++ /* Now we got response from FW, cancel the command timer */
++ if (Adapter->CommandTimerIsSet) {
++ CancelTimer(&Adapter->MrvDrvCommandTimer);
++ Adapter->CommandTimerIsSet = FALSE;
++ }
++
++ if (!Adapter->CurCmd) {
++ resp = (HostCmd_DS_COMMAND *) priv->wlan_dev.upld_buf;
++ resp->Command = wlan_le16_to_cpu(resp->Command);
++ PRINTM(ERROR, "CMD_RESP: NULL CurCmd, 0x%x\n", resp->Command);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ Adapter->num_cmd_timeout = 0;
++
++ DBG_HEXDUMP(CMD_D, "CMD_RESP", Adapter->CurCmd->BufVirtualAddr,
++ priv->wlan_dev.upld_len);
++
++ resp = (HostCmd_DS_COMMAND *) (Adapter->CurCmd->BufVirtualAddr);
++
++ resp->Command = wlan_le16_to_cpu(resp->Command);
++ resp->Size = wlan_le16_to_cpu(resp->Size);
++ resp->SeqNum = wlan_le16_to_cpu(resp->SeqNum);
++ resp->Result = wlan_le16_to_cpu(resp->Result);
++
++ RespCmd = resp->Command;
++ Result = resp->Result;
++
++ /* Save the last command response to debug log */
++ Adapter->dbg.LastCmdRespIndex =
++ (Adapter->dbg.LastCmdRespIndex + 1) % DBG_CMD_NUM;
++ Adapter->dbg.LastCmdRespId[Adapter->dbg.LastCmdRespIndex] = RespCmd;
++
++ PRINTM(CMND, "CMD_RESP: 0x%x, result %d, len %d, seqno %d @ %lu\n",
++ RespCmd, Result, resp->Size, resp->SeqNum, os_time_get());
++
++ if (!(RespCmd & 0x8000)) {
++ PRINTM(ERROR, "CMD_RESP: Invalid response to command!");
++ Adapter->CurCmdRetCode = WLAN_STATUS_FAILURE;
++ CleanupAndInsertCmd(priv, Adapter->CurCmd);
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ Adapter->CurCmd = NULL;
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Store the response code to CurCmdRetCode. */
++ Adapter->CurCmdRetCode = resp->Result;
++
++ if (RespCmd == HostCmd_RET_802_11_PS_MODE) {
++ HostCmd_DS_802_11_PS_MODE *psmode;
++
++ psmode = &resp->params.psmode;
++ PRINTM(INFO, "CMD_RESP: PS_MODE cmd reply result=%#x action=0x%X\n",
++ resp->Result, psmode->Action);
++ psmode->Action = wlan_cpu_to_le16(psmode->Action);
++
++ if (Result) {
++ PRINTM(ERROR, "CMD_RESP: PS command failed- %#x \n",
++ resp->Result);
++ if (Adapter->InfrastructureMode == Wlan802_11IBSS) {
++ /*
++ * We should not re-try enter-ps command in
++ * ad-hoc mode. It takes place in
++ * ExecuteNextCommand().
++ */
++ if (psmode->Action == HostCmd_SubCmd_Enter_PS)
++ Adapter->PSMode = Wlan802_11PowerModeCAM;
++ }
++ } else if (psmode->Action == HostCmd_SubCmd_Enter_PS) {
++ Adapter->NeedToWakeup = FALSE;
++ Adapter->PSState = PS_STATE_AWAKE;
++
++ if (Adapter->MediaConnectStatus != WlanMediaStateConnected) {
++ /*
++ * When Deauth Event received before Enter_PS command
++ * response, We need to wake up the firmware.
++ */
++ PRINTM(INFO,
++ "CMD_RESP: Disconnected, Going to invoke PSWakeup\n");
++ PSWakeup(priv, 0);
++ }
++ } else if (psmode->Action == HostCmd_SubCmd_Exit_PS) {
++ Adapter->NeedToWakeup = FALSE;
++ Adapter->PSState = PS_STATE_FULL_POWER;
++
++ } else {
++ PRINTM(INFO, "CMD_RESP: PS- Action=0x%X\n", psmode->Action);
++ }
++
++ CleanupAndInsertCmd(priv, Adapter->CurCmd);
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ Adapter->CurCmd = NULL;
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ ret = WLAN_STATUS_SUCCESS;
++ goto done;
++ }
++
++ if (Adapter->CurCmd->CmdFlags & CMD_F_HOSTCMD) {
++ /* Copy the response back to response buffer */
++ memcpy(Adapter->CurCmd->pdata_buf, resp, resp->Size);
++
++ Adapter->CurCmd->CmdFlags &= ~CMD_F_HOSTCMD;
++
++ if ((Result == HostCmd_RESULT_OK)
++ && (RespCmd == HostCmd_RET_802_11_HOST_SLEEP_CFG)) {
++ ret = wlan_ret_host_sleep_cfg(priv, resp);
++ }
++ } else {
++ /* If the command is not successful, cleanup and return failure */
++ if ((Result != HostCmd_RESULT_OK || !(RespCmd & 0x8000))) {
++ PRINTM(ERROR, "CMD_RESP: cmd %#x error, result=%#x\n",
++ resp->Command, resp->Result);
++ /*
++ * Handling errors here
++ */
++ switch (RespCmd) {
++ case HostCmd_RET_HW_SPEC_INFO:
++ PRINTM(INFO, "CMD_RESP: HW spec command Failed\n");
++ break;
++
++ }
++
++ CleanupAndInsertCmd(priv, Adapter->CurCmd);
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ Adapter->CurCmd = NULL;
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ return WLAN_STATUS_FAILURE;
++ }
++
++ switch (RespCmd) {
++ case HostCmd_RET_MAC_REG_ACCESS:
++ case HostCmd_RET_BBP_REG_ACCESS:
++ case HostCmd_RET_RF_REG_ACCESS:
++ ret = wlan_ret_reg_access(priv, RespCmd, resp);
++
++ break;
++
++ case HostCmd_RET_HW_SPEC_INFO:
++ ret = wlan_ret_get_hw_spec(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_BG_SCAN_QUERY:
++ {
++ union iwreq_data wrqu;
++
++ ret = wlan_ret_802_11_scan(priv, resp);
++ memset(&wrqu, 0, sizeof(union iwreq_data));
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWSCAN, &wrqu,
++ NULL);
++ PRINTM(INFO, "CMD_RESP: BG_SCAN result is ready!\n");
++ break;
++ }
++ case HostCmd_RET_802_11_SCAN:
++ ret = wlan_ret_802_11_scan(priv, resp);
++ break;
++
++ case HostCmd_RET_MAC_CONTROL:
++ ret = wlan_ret_mac_control(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_GET_LOG:
++ ret = wlan_ret_get_log(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_ASSOCIATE:
++ ret = wlan_ret_802_11_associate(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_DEAUTHENTICATE:
++ ret = wlan_ret_802_11_disassociate(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_SET_WEP:
++ ret = wlan_ret_802_11_set_wep(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_AD_HOC_START:
++ case HostCmd_RET_802_11_AD_HOC_JOIN:
++ ret = wlan_ret_802_11_ad_hoc(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_RESET:
++ ret = wlan_ret_802_11_reset(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_SNMP_MIB:
++ ret = wlan_ret_802_11_snmp_mib(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_RF_TX_POWER:
++ ret = wlan_ret_802_11_rf_tx_power(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_RADIO_CONTROL:
++ ret = wlan_ret_802_11_radio_control(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_HOST_SLEEP_CFG:
++ ret = wlan_ret_host_sleep_cfg(priv, resp);
++ break;
++ case HostCmd_RET_802_11_WAKEUP_CONFIRM:
++ wlan_host_sleep_deactivated_event(priv);
++ break;
++ case HostCmd_RET_802_11_HOST_SLEEP_ACTIVATE:
++ if (Adapter->bHostSleepConfigured
++ && Adapter->HSCfg.gap == HOST_SLEEP_CFG_GAP_FF)
++ Adapter->bWakeupDevRequired = TRUE;
++ wlan_host_sleep_activated_event(priv);
++ break;
++
++ case HostCmd_RET_802_11_RF_ANTENNA:
++ ret = wlan_ret_802_11_rf_antenna(priv, resp);
++ break;
++
++ case HostCmd_RET_MAC_MULTICAST_ADR:
++ ret = wlan_ret_mac_multicast_adr(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_RATE_ADAPT_RATESET:
++ ret = wlan_ret_802_11_rate_adapt_rateset(priv, resp);
++ break;
++ case HostCmd_RET_802_11_RF_CHANNEL:
++ ret = wlan_ret_802_11_rf_channel(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_RSSI:
++ ret = wlan_ret_802_11_rssi(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_MAC_ADDRESS:
++ ret = wlan_ret_802_11_mac_address(priv, resp);
++ break;
++
++#ifdef MFG_CMD_SUPPORT
++ case HostCmd_RET_MFG_COMMAND:
++ ret = wlan_ret_mfg_cmd(priv, resp);
++ break;
++#endif
++ case HostCmd_RET_802_11_AD_HOC_STOP:
++ ret = wlan_ret_802_11_ad_hoc_stop(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_CAL_DATA_EXT:
++ ret = wlan_ret_802_11_cal_data_ext(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_KEY_MATERIAL:
++ ret = wlan_ret_802_11_key_material(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_EEPROM_ACCESS:
++ ret = wlan_ret_802_11_eeprom_access(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11D_DOMAIN_INFO:
++ ret = wlan_ret_802_11d_domain_info(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_SLEEP_PARAMS:
++ ret = wlan_ret_802_11_sleep_params(priv, resp);
++ break;
++ case HostCmd_RET_802_11_BCA_CONFIG_TIMESHARE:
++ ret = wlan_ret_802_11_bca_timeshare(priv, resp);
++ break;
++ case HostCmd_RET_802_11_INACTIVITY_TIMEOUT:
++ *((u16 *) Adapter->CurCmd->pdata_buf) =
++ wlan_le16_to_cpu(resp->params.inactivity_timeout.Timeout);
++ break;
++ case HostCmd_RET_802_11_BG_SCAN_CONFIG:
++ break;
++
++ case HostCmd_RET_802_11_FW_WAKE_METHOD:
++ ret = wlan_ret_fw_wakeup_method(priv, resp);
++ break;
++
++ case HostCmd_RET_802_11_SLEEP_PERIOD:
++ ret = wlan_ret_802_11_sleep_period(priv, resp);
++ break;
++ case HostCmd_RET_WMM_GET_STATUS:
++ ret = wlan_cmdresp_wmm_get_status(priv, resp);
++ break;
++ case HostCmd_RET_WMM_ADDTS_REQ:
++ ret = wlan_cmdresp_wmm_addts_req(priv, resp);
++ break;
++ case HostCmd_RET_WMM_DELTS_REQ:
++ ret = wlan_cmdresp_wmm_delts_req(priv, resp);
++ break;
++ case HostCmd_RET_WMM_QUEUE_CONFIG:
++ ret = wlan_cmdresp_wmm_queue_config(priv, resp);
++ break;
++ case HostCmd_RET_WMM_QUEUE_STATS:
++ ret = wlan_cmdresp_wmm_queue_stats(priv, resp);
++ break;
++ case HostCmd_RET_TX_PKT_STATS:
++ memcpy(Adapter->CurCmd->pdata_buf,
++ &resp->params.txPktStats, sizeof(HostCmd_DS_TX_PKT_STATS));
++ ret = WLAN_STATUS_SUCCESS;
++ break;
++ case HostCmd_RET_802_11_TPC_CFG:
++ memmove(Adapter->CurCmd->pdata_buf,
++ &resp->params.tpccfg, sizeof(HostCmd_DS_802_11_TPC_CFG));
++ break;
++ case HostCmd_RET_802_11_LED_CONTROL:
++ {
++ HostCmd_DS_802_11_LED_CTRL *pLedCtrl = &resp->params.ledgpio;
++ MrvlIEtypes_LedGpio_t *pGpio = &pLedCtrl->LedGpio;
++ MrvlIEtypes_LedBehavior_t *pBehavior = pLedCtrl->LedBehavior;
++
++ pLedCtrl->Action = wlan_le16_to_cpu(pLedCtrl->Action);
++ pLedCtrl->LedNums = wlan_le16_to_cpu(pLedCtrl->LedNums);
++ pGpio->Header.Type = wlan_le16_to_cpu(pGpio->Header.Type);
++ pGpio->Header.Len = wlan_le16_to_cpu(pGpio->Header.Len);
++ pBehavior->Header.Type =
++ wlan_le16_to_cpu(pBehavior->Header.Type);
++ pBehavior->Header.Len =
++ wlan_le16_to_cpu(pBehavior->Header.Len);
++ memmove(Adapter->CurCmd->pdata_buf, &resp->params.ledgpio,
++ sizeof(HostCmd_DS_802_11_LED_CTRL));
++ break;
++ }
++
++ case HostCmd_RET_GET_TSF:
++ resp->params.gettsf.TsfValue =
++ wlan_le64_to_cpu(resp->params.gettsf.TsfValue);
++ memcpy(priv->adapter->CurCmd->pdata_buf,
++ &resp->params.gettsf.TsfValue, sizeof(u64));
++ break;
++ case HostCmd_RTE_802_11_TX_RATE_QUERY:
++ priv->adapter->TxRate =
++ wlan_le16_to_cpu(resp->params.txrate.TxRate);
++ break;
++ case HostCmd_RET_802_11_IBSS_COALESCING_STATUS:
++ wlan_ret_802_11_IBSS_Coalesced_Status(priv, resp);
++ break;
++
++ case HostCmd_RET_SDIO_GPIO_INT_CONFIG:
++ memmove(Adapter->CurCmd->pdata_buf,
++ &resp->params.sdio_int,
++ sizeof(HostCmd_DS_SDIO_INT_CONFIG));
++ break;
++
++ case HostCmd_RET_SDIO_PULL_CTRL:
++ memmove(Adapter->CurCmd->pdata_buf,
++ &resp->params.sdiopullctl,
++ sizeof(HostCmd_DS_SDIO_PULL_CTRL));
++ break;
++
++ case HostCmd_RET_802_11_LDO_CONFIG:
++ resp->params.ldocfg.Action =
++ wlan_le16_to_cpu(resp->params.ldocfg.Action);
++ resp->params.ldocfg.PMSource =
++ wlan_le16_to_cpu(resp->params.ldocfg.PMSource);
++ memmove(Adapter->CurCmd->pdata_buf, &resp->params.ldocfg,
++ sizeof(HostCmd_DS_802_11_LDO_CONFIG));
++ break;
++
++ case HostCmd_RET_VERSION_EXT:
++ memcpy(Adapter->CurCmd->pdata_buf,
++ &resp->params.verext, sizeof(HostCmd_DS_VERSION_EXT));
++ break;
++
++ default:
++ PRINTM(INFO, "CMD_RESP: Unknown command response %#x\n",
++ resp->Command);
++ break;
++ }
++ }
++
++ if (Adapter->CurCmd) {
++ /* Clean up and Put current command back to CmdFreeQ */
++ CleanupAndInsertCmd(priv, Adapter->CurCmd);
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ Adapter->CurCmd = NULL;
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++ }
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++#if WIRELESS_EXT >= 18
++/**
++ * @brief This function sends mic error event to application.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @para event MIC ERROR EVENT.
++ * @return n/a
++ */
++void
++send_mic_error_event(wlan_private * priv, u32 event)
++{
++ union iwreq_data iwrq;
++ struct iw_michaelmicfailure mic;
++
++ ENTER();
++
++ memset(&iwrq, 0, sizeof(iwrq));
++ memset(&mic, 0, sizeof(mic));
++ if (event == MACREG_INT_CODE_MIC_ERR_UNICAST) {
++ mic.flags = IW_MICFAILURE_PAIRWISE;
++ } else {
++ mic.flags = IW_MICFAILURE_GROUP;
++ }
++
++ iwrq.data.pointer = &mic;
++ iwrq.data.length = sizeof(mic);
++
++ wireless_send_event(priv->wlan_dev.netdev, IWEVMICHAELMICFAILURE, &iwrq,
++ (u8 *) & mic);
++
++ LEAVE();
++ return;
++}
++#endif
++
++/**
++ * @brief This function handles events generated by firmware
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_process_event(wlan_private * priv)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++ u32 eventcause = Adapter->EventCause >> SBI_EVENT_CAUSE_SHIFT;
++
++ ENTER();
++
++ /* Save the last event to debug log */
++ Adapter->dbg.LastEventIndex =
++ (Adapter->dbg.LastEventIndex + 1) % DBG_CMD_NUM;
++ Adapter->dbg.LastEvent[Adapter->dbg.LastEventIndex] = eventcause;
++
++ if (eventcause != MACREG_INT_CODE_PS_SLEEP &&
++ eventcause != MACREG_INT_CODE_PS_AWAKE)
++ PRINTM(EVENT, "EVENT: 0x%x @ %lu\n", eventcause, os_time_get());
++
++ switch (eventcause) {
++ case MACREG_INT_CODE_DUMMY_HOST_WAKEUP_SIGNAL:
++ PRINTM(INFO, "EVENT: DUMMY_HOST_WAKEUP_SIGNAL\n");
++ if (!priv->adapter->HS_Activated) {
++ PRINTM(WARN, "DUMMY_HOST_WAKEUP_SIGNAL (HS_Deactivated)\n");
++ } else {
++ wlan_host_sleep_gpio_int_event(priv);
++ }
++ break;
++ case MACREG_INT_CODE_LINK_SENSED:
++ PRINTM(INFO, "EVENT: LINK_SENSED\n");
++ Adapter->AdhocLinkSensed = TRUE;
++ os_carrier_on(priv);
++ os_start_queue(priv);
++ wmm_start_queue(priv);
++ send_iwevcustom_event(priv, CUS_EVT_ADHOC_LINK_SENSED);
++ break;
++
++ case MACREG_INT_CODE_DEAUTHENTICATED:
++ PRINTM(INFO, "EVENT: Deauthenticated\n");
++ Adapter->dbg.num_event_deauth++;
++ HandleDisconnectEvent(priv);
++ break;
++
++ case MACREG_INT_CODE_DISASSOCIATED:
++ PRINTM(INFO, "EVENT: Disassociated\n");
++ Adapter->dbg.num_event_disassoc++;
++ HandleDisconnectEvent(priv);
++ break;
++
++ case MACREG_INT_CODE_LINK_LOST:
++ PRINTM(INFO, "EVENT: Link lost\n");
++ Adapter->dbg.num_event_link_lost++;
++ HandleDisconnectEvent(priv);
++ break;
++
++ case MACREG_INT_CODE_PS_SLEEP:
++ PRINTM(INFO, "EVENT: SLEEP\n");
++ PRINTM(EVENT, "_");
++
++ /* handle unexpected PS SLEEP event */
++ if (Adapter->PSState == PS_STATE_FULL_POWER) {
++ PRINTM(INFO, "EVENT: In FULL POWER mode - ignore PS SLEEP\n");
++ break;
++ }
++ Adapter->PSState = PS_STATE_PRE_SLEEP;
++ PSConfirmSleep(priv, (u16) Adapter->PSMode);
++ break;
++
++ case MACREG_INT_CODE_PS_AWAKE:
++ PRINTM(INFO, "EVENT: AWAKE \n");
++ PRINTM(EVENT, "|");
++
++ /* handle unexpected PS AWAKE event */
++ if (Adapter->PSState == PS_STATE_FULL_POWER) {
++ PRINTM(INFO, "EVENT: In FULL POWER mode - ignore PS AWAKE\n");
++ break;
++ }
++
++ Adapter->TxLockFlag = FALSE;
++ if (TRUE == CheckLastPacketIndication(priv)) {
++ if (!priv->wlan_dev.dnld_sent && Adapter->gen_null_pkg) {
++ SendNullPacket(priv, MRVDRV_TxPD_POWER_MGMT_NULL_PACKET |
++ MRVDRV_TxPD_POWER_MGMT_LAST_PACKET);
++ Adapter->TxLockFlag = TRUE;
++ }
++ }
++
++ Adapter->PSState = PS_STATE_AWAKE;
++
++ if (Adapter->NeedToWakeup == TRUE) {
++ /*
++ * wait for the command processing to finish
++ * before resuming sending
++ * Adapter->NeedToWakeup will be set to FALSE
++ * in PSWakup()
++ */
++ PRINTM(INFO, "Waking up...\n");
++ PSWakeup(priv, 0);
++ }
++ break;
++
++ case MACREG_INT_CODE_DEEP_SLEEP_AWAKE:
++ sbi_reset_deepsleep_wakeup(priv);
++ PRINTM(INFO, "EVENT: DS_AWAKE\n");
++ if (priv->adapter->IsDeepSleep == TRUE) {
++ Adapter->IsDeepSleep = FALSE;
++ Adapter->bWakeupDevRequired = FALSE;
++ Adapter->WakeupTries = 0;
++
++ /*
++ * For auto DS + BGS case, some delay is needed to
++ * avoid going back to DS before getting BGS result
++ */
++ if (Adapter->IsAutoDeepSleepEnabled &&
++ Adapter->bgScanConfig->Enable)
++ os_sched_timeout(10);
++ priv->wlan_dev.dnld_sent = DNLD_RES_RECEIVED;
++ priv->adapter->HisRegCpy |= HIS_TxDnLdRdy;
++ }
++ send_iwevcustom_event(priv, CUS_EVT_DEEP_SLEEP_AWAKE);
++ wake_up_interruptible(&Adapter->ds_awake_q);
++ break;
++
++ case MACREG_INT_CODE_HOST_SLEEP_AWAKE:
++ PRINTM(INFO, "EVENT: HS_AWAKE\n");
++ Adapter->bWakeupDevRequired = FALSE;
++
++ Adapter->WakeupTries = 0;
++
++ sbi_reset_deepsleep_wakeup(priv);
++
++ /*
++ * in BG SCAN mode w/ deep sleep, WAKE UP event
++ * will be sent first, Deep Sleep Awake will
++ * be sent later.
++ */
++ if (priv->adapter->IsDeepSleep == TRUE) {
++ priv->adapter->IsDeepSleep = FALSE;
++ priv->wlan_dev.dnld_sent = DNLD_RES_RECEIVED;
++ priv->adapter->HisRegCpy |= HIS_TxDnLdRdy;
++ }
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_WAKEUP_CONFIRM,
++ 0, 0, 0, NULL);
++ break;
++
++ case MACREG_INT_CODE_MIC_ERR_UNICAST:
++ PRINTM(INFO, "EVENT: UNICAST MIC ERROR\n");
++#if WIRELESS_EXT >= 18
++ send_mic_error_event(priv, MACREG_INT_CODE_MIC_ERR_UNICAST);
++#else
++ send_iwevcustom_event(priv, CUS_EVT_MLME_MIC_ERR_UNI);
++#endif
++ break;
++
++ case MACREG_INT_CODE_MIC_ERR_MULTICAST:
++ PRINTM(INFO, "EVENT: MULTICAST MIC ERROR\n");
++#if WIRELESS_EXT >= 18
++ send_mic_error_event(priv, MACREG_INT_CODE_MIC_ERR_MULTICAST);
++#else
++ send_iwevcustom_event(priv, CUS_EVT_MLME_MIC_ERR_MUL);
++#endif
++ break;
++ case MACREG_INT_CODE_MIB_CHANGED:
++ case MACREG_INT_CODE_INIT_DONE:
++ break;
++
++ case MACREG_INT_CODE_ADHOC_BCN_LOST:
++ PRINTM(INFO, "EVENT: ADHOC_BCN_LOST\n");
++ Adapter->AdhocLinkSensed = FALSE;
++ wlan_clean_txrx(priv);
++ send_iwevcustom_event(priv, CUS_EVT_ADHOC_BCN_LOST);
++ break;
++
++ case MACREG_INT_CODE_BG_SCAN_REPORT:
++ PRINTM(INFO, "EVENT: BGS_REPORT\n");
++ Adapter->bgScanConfig->Enable = FALSE;
++ ret = sendBgScanQueryCmd(priv);
++ break;
++ case MACREG_INT_CODE_WMM_STATUS_CHANGE:
++ PRINTM(INFO, "EVENT: WMM status changed\n");
++ ret = sendWMMStatusChangeCmd(priv);
++ break;
++
++ case MACREG_INT_CODE_RSSI_LOW:
++ PRINTM(INFO, "EVENT: RSSI_LOW\n");
++ send_iwevcustom_event(priv, CUS_EVT_BEACON_RSSI_LOW);
++ break;
++ case MACREG_INT_CODE_SNR_LOW:
++ PRINTM(INFO, "EVENT: SNR_LOW\n");
++ send_iwevcustom_event(priv, CUS_EVT_BEACON_SNR_LOW);
++ break;
++ case MACREG_INT_CODE_MAX_FAIL:
++ PRINTM(INFO, "EVENT: MAX_FAIL\n");
++ send_iwevcustom_event(priv, CUS_EVT_MAX_FAIL);
++ break;
++ case MACREG_INT_CODE_RSSI_HIGH:
++ PRINTM(INFO, "EVENT: RSSI_HIGH\n");
++ send_iwevcustom_event(priv, CUS_EVT_BEACON_RSSI_HIGH);
++ break;
++ case MACREG_INT_CODE_SNR_HIGH:
++ PRINTM(INFO, "EVENT: SNR_HIGH\n");
++ send_iwevcustom_event(priv, CUS_EVT_BEACON_SNR_HIGH);
++ break;
++ case MACREG_INT_CODE_PRE_BEACON_LOST:
++ PRINTM(INFO, "EVENT: Pre-Beacon Lost\n");
++ send_iwevcustom_event(priv, CUS_EVT_PRE_BEACON_LOST);
++ break;
++ case MACREG_INT_CODE_IBSS_COALESCED:
++ PRINTM(INFO, "EVENT: IBSS_COALESCED\n");
++ ret = sendADHOCBSSIDQuery(priv);
++ break;
++ default:
++ PRINTM(INFO, "EVENT: unknown event id: %#x\n", eventcause);
++ break;
++ }
++
++ Adapter->EventCause = 0;
++ LEAVE();
++ return ret;
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_debug.c b/drivers/net/wireless/marvell8686/wlan_debug.c
+new file mode 100644
+index 0000000..8a980aa
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_debug.c
+@@ -0,0 +1,281 @@
++/** @file wlan_debug.c
++ * @brief This file contains functions for debug proc file.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 10/04/05: Add Doxygen format comments
++ 01/05/06: Add kernel 2.6.x support
++
++********************************************************/
++
++#include "include.h"
++
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++/********************************************************
++ Local Variables
++********************************************************/
++
++#define item_size(n) (sizeof ((wlan_adapter *)0)->n)
++#define item_addr(n) ((u32) &((wlan_adapter *)0)->n)
++
++#define item_dbg_size(n) (sizeof (((wlan_adapter *)0)->dbg.n))
++#define item_dbg_addr(n) ((u32) &(((wlan_adapter *)0)->dbg.n))
++
++#define item1_size(n) (sizeof ((wlan_dev_t *)0)->n)
++#define item1_addr(n) ((u32) &((wlan_dev_t *)0)->n)
++
++struct debug_data
++{
++ char name[32];
++ u32 size;
++ u32 addr;
++ u32 offset;
++};
++
++/* To debug any member of wlan_adapter or wlan_dev_t, simply add one line here.
++ */
++#define ITEMS_FROM_WLAN_DEV 1
++
++static struct debug_data items[] = {
++ {"IntCounter", item_size(IntCounter), 0, item_addr(IntCounter)},
++ {"ConnectStatus", item_size(MediaConnectStatus), 0,
++ item_addr(MediaConnectStatus)},
++ {"wmmQStp", item_size(wmm.queueStopped), 0, item_addr(wmm.queueStopped)},
++ {"wmmPkts", item_size(wmm.packetsQueued), 0,
++ item_addr(wmm.packetsQueued)},
++ {"wmmAcVo", item_size(wmm.packetsOut[WMM_AC_VO]), 0,
++ item_addr(wmm.packetsOut[WMM_AC_VO])},
++ {"wmmAcVi", item_size(wmm.packetsOut[WMM_AC_VI]), 0,
++ item_addr(wmm.packetsOut[WMM_AC_VI])},
++ {"wmmAcBE", item_size(wmm.packetsOut[WMM_AC_BE]), 0,
++ item_addr(wmm.packetsOut[WMM_AC_BE])},
++ {"wmmAcBK", item_size(wmm.packetsOut[WMM_AC_BK]), 0,
++ item_addr(wmm.packetsOut[WMM_AC_BK])},
++ {"PSMode", item_size(PSMode), 0, item_addr(PSMode)},
++ {"PSState", item_size(PSState), 0, item_addr(PSState)},
++ {"IsDeepSleep", item_size(IsDeepSleep), 0, item_addr(IsDeepSleep)},
++ {"IsAutoDeepSleepEnabled", item_size(IsAutoDeepSleepEnabled), 0,
++ item_addr(IsAutoDeepSleepEnabled)},
++ {"WakeupDevReq", item_size(bWakeupDevRequired), 0,
++ item_addr(bWakeupDevRequired)},
++ {"WakeupTries", item_size(WakeupTries), 0, item_addr(WakeupTries)},
++ {"HS_Configured", item_size(bHostSleepConfigured), 0,
++ item_addr(bHostSleepConfigured)},
++ {"HS_Activated", item_size(HS_Activated), 0, item_addr(HS_Activated)},
++ {"num_tx_timeout", item_dbg_size(num_tx_timeout), 0,
++ item_dbg_addr(num_tx_timeout)},
++ {"num_cmd_timeout", item_dbg_size(num_cmd_timeout), 0,
++ item_dbg_addr(num_cmd_timeout)},
++ {"TimeoutCmdId", item_dbg_size(TimeoutCmdId), 0,
++ item_dbg_addr(TimeoutCmdId)},
++ {"TimeoutCmdAct", item_dbg_size(TimeoutCmdAct), 0,
++ item_dbg_addr(TimeoutCmdAct)},
++ {"LastCmdId", item_dbg_size(LastCmdId), 0, item_dbg_addr(LastCmdId)},
++ {"LastCmdAct", item_dbg_size(LastCmdAct), 0, item_dbg_addr(LastCmdAct)},
++ {"LastCmdIndex", item_dbg_size(LastCmdIndex), 0,
++ item_dbg_addr(LastCmdIndex)},
++ {"LastCmdRespId", item_dbg_size(LastCmdRespId), 0,
++ item_dbg_addr(LastCmdRespId)},
++ {"LastCmdRespIndex", item_dbg_size(LastCmdRespIndex), 0,
++ item_dbg_addr(LastCmdRespIndex)},
++ {"LastEvent", item_dbg_size(LastEvent), 0, item_dbg_addr(LastEvent)},
++ {"LastEventIndex", item_dbg_size(LastEventIndex), 0,
++ item_dbg_addr(LastEventIndex)},
++ {"num_cmd_h2c_fail", item_dbg_size(num_cmd_host_to_card_failure), 0,
++ item_dbg_addr(num_cmd_host_to_card_failure)},
++ {"num_cmd_sleep_cfm_fail",
++ item_dbg_size(num_cmd_sleep_cfm_host_to_card_failure), 0,
++ item_dbg_addr(num_cmd_sleep_cfm_host_to_card_failure)},
++ {"num_tx_h2c_fail", item_dbg_size(num_tx_host_to_card_failure), 0,
++ item_dbg_addr(num_tx_host_to_card_failure)},
++ {"num_evt_deauth", item_dbg_size(num_event_deauth), 0,
++ item_dbg_addr(num_event_deauth)},
++ {"num_evt_disassoc", item_dbg_size(num_event_disassoc), 0,
++ item_dbg_addr(num_event_disassoc)},
++ {"num_evt_link_lost", item_dbg_size(num_event_link_lost), 0,
++ item_dbg_addr(num_event_link_lost)},
++ {"num_cmd_deauth", item_dbg_size(num_cmd_deauth), 0,
++ item_dbg_addr(num_cmd_deauth)},
++ {"num_cmd_assoc_ok", item_dbg_size(num_cmd_assoc_success), 0,
++ item_dbg_addr(num_cmd_assoc_success)},
++ {"num_cmd_assoc_fail", item_dbg_size(num_cmd_assoc_failure), 0,
++ item_dbg_addr(num_cmd_assoc_failure)},
++
++ {"dnld_sent", item1_size(dnld_sent), 0, item1_addr(dnld_sent)},
++};
++
++static int num_of_items = sizeof(items) / sizeof(items[0]);
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++/**
++ * @brief proc read function
++ *
++ * @param page pointer to buffer
++ * @param s read data starting position
++ * @param off offset
++ * @param cnt counter
++ * @param eof end of file flag
++ * @param data data to output
++ * @return number of output data
++ */
++static int
++wlan_debug_read(char *page, char **s, off_t off, int cnt, int *eof,
++ void *data)
++{
++ int val = 0;
++ char *p = page;
++ int i;
++
++ struct debug_data *d = (struct debug_data *) data;
++
++ MODULE_GET;
++
++ for (i = 0; i < num_of_items; i++) {
++ if (d[i].size == 1)
++ val = *((u8 *) d[i].addr);
++ else if (d[i].size == 2)
++ val = *((u16 *) d[i].addr);
++ else if (d[i].size == 4)
++ val = *((u32 *) d[i].addr);
++ else {
++ int j;
++ p += sprintf(p, "%s=", d[i].name);
++ for (j = 0; j < d[i].size; j += 2) {
++ val = *(u16 *) (d[i].addr + j);
++ p += sprintf(p, "0x%x ", val);
++ }
++ p += sprintf(p, "\n");
++ continue;
++ }
++
++ if (strstr(d[i].name, "Id"))
++ p += sprintf(p, "%s=0x%x\n", d[i].name, val);
++ else
++ p += sprintf(p, "%s=%d\n", d[i].name, val);
++ }
++ MODULE_PUT;
++ return p - page;
++}
++
++/**
++ * @brief proc write function
++ *
++ * @param f file pointer
++ * @param buf pointer to data buffer
++ * @param cnt data number to write
++ * @param data data to write
++ * @return number of data
++ */
++static int
++wlan_debug_write(struct file *f, const char *buf, unsigned long cnt,
++ void *data)
++{
++ int r, i;
++ char *pdata;
++ char *p;
++ char *p0;
++ char *p1;
++ char *p2;
++ struct debug_data *d = (struct debug_data *) data;
++
++ MODULE_GET;
++
++ pdata = (char *) kmalloc(cnt, GFP_KERNEL);
++ if (pdata == NULL) {
++ MODULE_PUT;
++ return 0;
++ }
++
++ if (copy_from_user(pdata, buf, cnt)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ kfree(pdata);
++ MODULE_PUT;
++ return 0;
++ }
++
++ p0 = pdata;
++ for (i = 0; i < num_of_items; i++) {
++ do {
++ p = strstr(p0, d[i].name);
++ if (p == NULL)
++ break;
++ p1 = strchr(p, '\n');
++ if (p1 == NULL)
++ break;
++ p0 = p1++;
++ p2 = strchr(p, '=');
++ if (!p2)
++ break;
++ p2++;
++ r = string_to_number(p2);
++ if (d[i].size == 1)
++ *((u8 *) d[i].addr) = (u8) r;
++ else if (d[i].size == 2)
++ *((u16 *) d[i].addr) = (u16) r;
++ else if (d[i].size == 4)
++ *((u32 *) d[i].addr) = (u32) r;
++ break;
++ } while (TRUE);
++ }
++ kfree(pdata);
++ MODULE_PUT;
++ return cnt;
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++/**
++ * @brief create debug proc file
++ *
++ * @param priv pointer wlan_private
++ * @param dev pointer net_device
++ * @return N/A
++ */
++void
++wlan_debug_entry(wlan_private * priv, struct net_device *dev)
++{
++ int i;
++ struct proc_dir_entry *r;
++
++ if (priv->proc_entry == NULL)
++ return;
++
++ for (i = 0; i < (num_of_items - ITEMS_FROM_WLAN_DEV); i++) {
++ items[i].addr = items[i].offset + (u32) priv->adapter;
++ }
++ for (i = num_of_items - ITEMS_FROM_WLAN_DEV; i < num_of_items; i++) {
++ items[i].addr = items[i].offset + (u32) & priv->wlan_dev;
++ }
++ r = create_proc_entry("debug", 0644, priv->proc_entry);
++ if (r == NULL)
++ return;
++
++ r->data = &items[0];
++ r->read_proc = wlan_debug_read;
++ r->write_proc = wlan_debug_write;
++ r->owner = THIS_MODULE;
++
++}
++
++/**
++ * @brief remove proc file
++ *
++ * @param priv pointer wlan_private
++ * @return N/A
++ */
++void
++wlan_debug_remove(wlan_private * priv)
++{
++ remove_proc_entry("debug", priv->proc_entry);
++}
++
++#endif
+diff --git a/drivers/net/wireless/marvell8686/wlan_decl.h b/drivers/net/wireless/marvell8686/wlan_decl.h
+new file mode 100644
+index 0000000..73aaad4
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_decl.h
+@@ -0,0 +1,109 @@
++/** @file wlan_decl.h
++ * @brief This file contains declaration referring to
++ * functions defined in other source files
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/******************************************************
++Change log:
++ 09/29/05: add Doxygen format comments
++ 01/05/06: Add kernel 2.6.x support
++ 01/11/06: Conditionalize new scan/join structures.
++ Move wlan_wext statics to their source file.
++******************************************************/
++
++#ifndef _WLAN_DECL_H_
++#define _WLAN_DECL_H_
++
++/** Function Prototype Declaration */
++int wlan_init_fw(wlan_private * priv);
++int wlan_tx_packet(wlan_private * priv, struct sk_buff *skb);
++void wlan_free_adapter(wlan_private * priv);
++
++int SendNullPacket(wlan_private * priv, u8 flags);
++BOOLEAN CheckLastPacketIndication(wlan_private * priv);
++
++void Wep_encrypt(wlan_private * priv, u8 * Buf, u32 Len);
++int FreeCmdBuffer(wlan_private * priv);
++void CleanUpCmdCtrlNode(CmdCtrlNode * pTempNode);
++CmdCtrlNode *GetFreeCmdCtrlNode(wlan_private * priv);
++
++void SetCmdCtrlNode(wlan_private * priv,
++ CmdCtrlNode * pTempNode,
++ WLAN_OID cmd_oid, u16 wait_option, void *pdata_buf);
++
++BOOLEAN Is_Command_Allowed(wlan_private * priv);
++
++int PrepareAndSendCommand(wlan_private * priv,
++ u16 cmd_no,
++ u16 cmd_action,
++ u16 wait_option, WLAN_OID cmd_oid, void *pdata_buf);
++
++void QueueCmd(wlan_adapter * Adapter, CmdCtrlNode * CmdNode, BOOLEAN addtail);
++
++int SetDeepSleep(wlan_private * priv, BOOLEAN bDeepSleep);
++int AllocateCmdBuffer(wlan_private * priv);
++int ExecuteNextCommand(wlan_private * priv);
++int wlan_process_event(wlan_private * priv);
++void wlan_interrupt(struct net_device *);
++u32 index_to_data_rate(u8 index);
++u8 data_rate_to_index(u32 rate);
++void HexDump(char *prompt, u8 * data, int len);
++void get_version(wlan_adapter * adapter, char *version, int maxlen);
++void wlan_read_write_rfreg(wlan_private * priv);
++
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++/** The proc fs interface */
++void wlan_proc_entry(wlan_private * priv, struct net_device *dev);
++void wlan_proc_remove(wlan_private * priv);
++int string_to_number(char *s);
++#ifdef CONFIG_MARVELL_8686_DEBUG
++void wlan_debug_entry(wlan_private * priv, struct net_device *dev);
++void wlan_debug_remove(wlan_private * priv);
++#endif
++#endif
++int wlan_process_rx_command(wlan_private * priv);
++void wlan_process_tx(wlan_private * priv);
++void CleanupAndInsertCmd(wlan_private * priv, CmdCtrlNode * pTempCmd);
++void MrvDrvCommandTimerFunction(void *FunctionContext);
++
++#ifdef REASSOCIATION
++void MrvDrvReassocTimerFunction(void *FunctionContext);
++#endif /* REASSOCIATION */
++
++int wlan_set_essid(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra);
++int wlan_set_regiontable(wlan_private * priv, u8 region, u8 band);
++
++void wlan_clean_txrx(wlan_private * priv);
++
++int wlan_host_sleep_activated_event(wlan_private * priv);
++int wlan_host_sleep_deactivated_event(wlan_private * priv);
++int wlan_host_sleep_gpio_int_event(wlan_private * priv);
++int wlan_deep_sleep_ioctl(wlan_private * priv, struct ifreq *rq);
++
++int ProcessRxedPacket(wlan_private * priv, struct sk_buff *);
++
++void PSSleep(wlan_private * priv, int wait_option);
++void PSConfirmSleep(wlan_private * priv, u16 PSMode);
++void PSWakeup(wlan_private * priv, int wait_option);
++
++void wlan_send_rxskbQ(wlan_private * priv);
++
++extern CHANNEL_FREQ_POWER *find_cfp_by_band_and_channel(wlan_adapter *
++ adapter, u8 band,
++ u16 channel);
++extern CHANNEL_FREQ_POWER *get_cfp_by_band_and_channel(u8 band, u16 channel,
++ REGION_CHANNEL *
++ region_channnel);
++
++extern void MacEventDisconnected(wlan_private * priv);
++
++#if WIRELESS_EXT > 14
++void send_iwevcustom_event(wlan_private * priv, s8 * str);
++#endif
++
++int fw_read(const char *name, u8 ** addr, u32 * len);
++void fw_buffer_free(u8 * addr);
++
++#endif /* _WLAN_DECL_H_ */
+diff --git a/drivers/net/wireless/marvell8686/wlan_defs.h b/drivers/net/wireless/marvell8686/wlan_defs.h
+new file mode 100644
+index 0000000..0f6202b
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_defs.h
+@@ -0,0 +1,623 @@
++/** @file wlan_defs.h
++ * @brief This header file contains global constant/enum definitions,
++ * global variable declaration.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/*************************************************************
++Change log:
++ 10/11/05: add Doxygen format comments
++ 01/11/06: Add NELEMENTS, BAND_XX defines
++ 04/10/06: Add hostcmd generic API and power_adapt_cfg_ext command
++************************************************************/
++
++#ifndef _WLAN_DEFS_H_
++#define _WLAN_DEFS_H_
++
++#include "os_defs.h"
++
++/** Double-Word(32Bit) Bit definition */
++#define DW_BIT_0 0x00000001
++#define DW_BIT_1 0x00000002
++#define DW_BIT_2 0x00000004
++#define DW_BIT_3 0x00000008
++#define DW_BIT_4 0x00000010
++#define DW_BIT_5 0x00000020
++#define DW_BIT_6 0x00000040
++#define DW_BIT_7 0x00000080
++#define DW_BIT_8 0x00000100
++#define DW_BIT_9 0x00000200
++#define DW_BIT_10 0x00000400
++#define DW_BIT_11 0x00000800
++#define DW_BIT_12 0x00001000
++#define DW_BIT_13 0x00002000
++#define DW_BIT_14 0x00004000
++#define DW_BIT_15 0x00008000
++#define DW_BIT_16 0x00010000
++#define DW_BIT_17 0x00020000
++#define DW_BIT_18 0x00040000
++#define DW_BIT_19 0x00080000
++#define DW_BIT_20 0x00100000
++#define DW_BIT_21 0x00200000
++#define DW_BIT_22 0x00400000
++#define DW_BIT_23 0x00800000
++#define DW_BIT_24 0x01000000
++#define DW_BIT_25 0x02000000
++#define DW_BIT_26 0x04000000
++#define DW_BIT_27 0x08000000
++#define DW_BIT_28 0x10000000
++#define DW_BIT_29 0x20000000
++#define DW_BIT_30 0x40000000
++#define DW_BIT_31 0x80000000
++
++/** Word (16bit) Bit Definition*/
++#define W_BIT_0 0x0001
++#define W_BIT_1 0x0002
++#define W_BIT_2 0x0004
++#define W_BIT_3 0x0008
++#define W_BIT_4 0x0010
++#define W_BIT_5 0x0020
++#define W_BIT_6 0x0040
++#define W_BIT_7 0x0080
++#define W_BIT_8 0x0100
++#define W_BIT_9 0x0200
++#define W_BIT_10 0x0400
++#define W_BIT_11 0x0800
++#define W_BIT_12 0x1000
++#define W_BIT_13 0x2000
++#define W_BIT_14 0x4000
++#define W_BIT_15 0x8000
++
++/** Byte (8Bit) Bit definition*/
++#define B_BIT_0 0x01
++#define B_BIT_1 0x02
++#define B_BIT_2 0x04
++#define B_BIT_3 0x08
++#define B_BIT_4 0x10
++#define B_BIT_5 0x20
++#define B_BIT_6 0x40
++#define B_BIT_7 0x80
++
++/** Debug Macro definition*/
++#ifdef DEBUG_LEVEL1
++
++extern u32 drvdbg;
++extern u32 ifdbg;
++
++/* Debug message control bit definition for drvdbg */
++#define DBG_MSG DW_BIT_0
++#define DBG_FATAL DW_BIT_1
++#define DBG_ERROR DW_BIT_2
++#define DBG_DATA DW_BIT_3
++#define DBG_CMND DW_BIT_4
++#define DBG_EVENT DW_BIT_5
++#define DBG_INTR DW_BIT_6
++
++#define DBG_DAT_D DW_BIT_16
++#define DBG_CMD_D DW_BIT_17
++#define DBG_FW_D DW_BIT_18
++
++#define DBG_ENTRY DW_BIT_28
++#define DBG_WARN DW_BIT_29
++#define DBG_INFO DW_BIT_30
++
++/* Debug message control bit definition for ifdbg */
++#define DBG_IF_D DW_BIT_0
++
++#ifdef DEBUG_LEVEL2
++#define PRINTM_INFO(msg...) {if (drvdbg & DBG_INFO) printk(KERN_DEBUG msg);}
++#define PRINTM_WARN(msg...) {if (drvdbg & DBG_WARN) printk(KERN_DEBUG msg);}
++#define PRINTM_ENTRY(msg...) {if (drvdbg & DBG_ENTRY) printk(KERN_DEBUG msg);}
++#else
++#define PRINTM_INFO(msg...) do {} while (0)
++#define PRINTM_WARN(msg...) do {} while (0)
++#define PRINTM_ENTRY(msg...) do {} while (0)
++#endif /* DEBUG_LEVEL2 */
++
++#define PRINTM_FW_D(msg...) {if (drvdbg & DBG_FW_D) printk(KERN_DEBUG msg);}
++#define PRINTM_CMD_D(msg...) {if (drvdbg & DBG_CMD_D) printk(KERN_DEBUG msg);}
++#define PRINTM_DAT_D(msg...) {if (drvdbg & DBG_DAT_D) printk(KERN_DEBUG msg);}
++
++#define PRINTM_INTR(msg...) {if (drvdbg & DBG_INTR) printk(KERN_DEBUG msg);}
++#define PRINTM_EVENT(msg...) {if (drvdbg & DBG_EVENT) printk(msg);}
++#define PRINTM_CMND(msg...) {if (drvdbg & DBG_CMND) printk(KERN_DEBUG msg);}
++#define PRINTM_DATA(msg...) {if (drvdbg & DBG_DATA) printk(KERN_DEBUG msg);}
++#define PRINTM_ERROR(msg...) {if (drvdbg & DBG_ERROR) printk(KERN_DEBUG msg);}
++#define PRINTM_FATAL(msg...) {if (drvdbg & DBG_FATAL) printk(KERN_DEBUG msg);}
++#define PRINTM_MSG(msg...) {if (drvdbg & DBG_MSG) printk(KERN_ALERT msg);}
++
++#define PRINTM_IF_D(msg...) {if (ifdbg & DBG_IF_D) printk(KERN_DEBUG msg);}
++
++#define PRINTM(level,msg...) PRINTM_##level(msg)
++
++#else
++
++#define PRINTM(level,msg...) do {} while (0)
++
++#endif /* DEBUG_LEVEL1 */
++
++#define ASSERT(cond) \
++do { \
++ if (!(cond)) \
++ PRINTM(INFO, "ASSERT: %s, %s:%i\n", \
++ __FUNCTION__, __FILE__, __LINE__); \
++} while(0)
++
++#define ENTER() PRINTM(ENTRY, "Enter: %s, %s:%i\n", __FUNCTION__, \
++ __FILE__, __LINE__)
++#define LEAVE() PRINTM(ENTRY, "Leave: %s, %s:%i\n", __FUNCTION__, \
++ __FILE__, __LINE__)
++
++#if defined(DEBUG_LEVEL1) && defined(__KERNEL__)
++#define DBG_DUMP_BUF_LEN 64
++#define MAX_DUMP_PER_LINE 16
++#define MAX_DATA_DUMP_LEN 48
++
++static inline void
++hexdump(char *prompt, u8 * buf, int len)
++{
++ int i;
++ char dbgdumpbuf[DBG_DUMP_BUF_LEN];
++ char *ptr = dbgdumpbuf;
++
++ printk(KERN_DEBUG "%s:\n", prompt);
++ for (i = 1; i <= len; i++) {
++ ptr += sprintf(ptr, "%02x ", *buf);
++ buf++;
++ if (i % MAX_DUMP_PER_LINE == 0) {
++ *ptr = 0;
++ printk(KERN_DEBUG "%s\n", dbgdumpbuf);
++ ptr = dbgdumpbuf;
++ }
++ }
++ if (len % MAX_DUMP_PER_LINE) {
++ *ptr = 0;
++ printk(KERN_DEBUG "%s\n", dbgdumpbuf);
++ }
++}
++
++#define DBG_HEXDUMP_CMD_D(x,y,z) {if (drvdbg & DBG_CMD_D) hexdump(x,y,z);}
++#define DBG_HEXDUMP_DAT_D(x,y,z) {if (drvdbg & DBG_DAT_D) hexdump(x,y,z);}
++#define DBG_HEXDUMP_IF_D(x,y,z) {if (ifdbg & DBG_IF_D) hexdump(x,y,z);}
++#define DBG_HEXDUMP_FW_D(x,y,z) {if (drvdbg & DBG_FW_D) hexdump(x,y,z);}
++
++#define DBG_HEXDUMP(level,x,y,z) DBG_HEXDUMP_##level(x,y,z)
++
++#else
++#define DBG_HEXDUMP(level,x,y,z) do {} while (0)
++#endif
++
++#if defined(DEBUG_LEVEL2) && defined(__KERNEL__)
++#define HEXDUMP(x,y,z) {if (drvdbg & DBG_INFO) hexdump(x,y,z);}
++#else
++#define HEXDUMP(x,y,z) do {} while (0)
++#endif
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++#ifndef FALSE
++#define FALSE 0
++#endif
++
++#ifndef MIN
++#define MIN(a,b) ((a) < (b) ? (a) : (b))
++#endif
++
++#ifndef MAX
++#define MAX(a,b) ((a) > (b) ? (a) : (b))
++#endif
++
++#ifndef NELEMENTS
++#define NELEMENTS(x) (sizeof(x)/sizeof(x[0]))
++#endif
++
++/** Buffer Constants */
++
++/* The size of SQ memory PPA, DPA are 8 DWORDs, that keep the physical
++* addresses of TxPD buffers. Station has only 8 TxPD available, Whereas
++* driver has more local TxPDs. Each TxPD on the host memory is associated
++* with a Tx control node. The driver maintains 8 RxPD descriptors for
++* station firmware to store Rx packet information.
++*
++* Current version of MAC has a 32x6 multicast address buffer.
++*
++* 802.11b can have up to 14 channels, the driver keeps the
++* BSSID(MAC address) of each APs or Ad hoc stations it has sensed.
++*/
++
++#define MRVDRV_SIZE_OF_PPA 0x00000008
++#define MRVDRV_SIZE_OF_DPA 0x00000008
++#define MRVDRV_NUM_OF_TxPD 0x00000020
++#define MRVDRV_NUM_OF_CMD_BUFFER 10
++#define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
++#define MRVDRV_MAX_BSSID_LIST 64
++#define MRVDRV_TIMER_10S 10000
++#define MRVDRV_TIMER_5S 5000
++#define MRVDRV_TIMER_1S 1000
++#define MRVDRV_SNAP_HEADER_LEN 8
++#define MRVDRV_ETH_HEADER_SIZE 14
++
++#define ARP_FILTER_MAX_BUF_SIZE 68
++
++#define WLAN_UPLD_SIZE 2312
++#define DEV_NAME_LEN 32
++
++#ifndef ETH_ALEN
++#define ETH_ALEN 6
++#endif
++
++/** Misc constants */
++/* This section defines 802.11 specific contants */
++#define SDIO_HEADER_LEN 4
++
++#define MRVDRV_MAX_REGION_CODE 6
++#define MRVDRV_IGNORE_MULTIPLE_DTIM 0xfffe
++#define MRVDRV_MIN_MULTIPLE_DTIM 1
++#define MRVDRV_MAX_MULTIPLE_DTIM 5
++#define MRVDRV_DEFAULT_MULTIPLE_DTIM 1
++
++#define MRVDRV_DEFAULT_LISTEN_INTERVAL 10
++#define MRVDRV_DEFAULT_LOCAL_LISTEN_INTERVAL 0
++
++#define MRVDRV_CHANNELS_PER_ACTIVE_SCAN 14
++#define MRVDRV_MIN_BEACON_INTERVAL 20
++#define MRVDRV_MAX_BEACON_INTERVAL 1000
++#define MRVDRV_BEACON_INTERVAL 100
++
++#define MRVDRV_DEFAULT_WATCHDOG_TIMEOUT (5 * HZ)
++#define MRVDRV_SCAN_WATCHDOG_TIMEOUT (10 * HZ)
++#define MRVDRV_DEEP_SLEEP_EXIT_TIMEOUT (10 * HZ)
++
++/** TxPD Status */
++
++/* Station firmware use TxPD status field to report final Tx transmit
++* result, Bit masks are used to present combined situations.
++*/
++
++#define MRVDRV_TxPD_POWER_MGMT_NULL_PACKET 0x01
++#define MRVDRV_TxPD_POWER_MGMT_LAST_PACKET 0x08
++
++/** Tx control node status */
++
++#define MRVDRV_TX_CTRL_NODE_STATUS_IDLE 0x0000
++
++/* Link spped */
++#define MRVDRV_LINK_SPEED_1mbps 10000 /* in unit of 100bps */
++#define MRVDRV_LINK_SPEED_11mbps 110000
++
++/** RSSI-related defines */
++/* RSSI constants are used to implement 802.11 RSSI threshold
++* indication. if the Rx packet signal got too weak for 5 consecutive
++* times, miniport driver (driver) will report this event to wrapper
++*/
++
++#define MRVDRV_NF_DEFAULT_SCAN_VALUE (-96)
++
++/** RTS/FRAG related defines */
++#define MRVDRV_RTS_MIN_VALUE 0
++#define MRVDRV_RTS_MAX_VALUE 2347
++#define MRVDRV_FRAG_MIN_VALUE 256
++#define MRVDRV_FRAG_MAX_VALUE 2346
++
++/* Fixed IE size is 8 bytes time stamp + 2 bytes beacon interval +
++ * 2 bytes cap */
++#define MRVL_FIXED_IE_SIZE 12
++
++/* This is for firmware specific length */
++#define EXTRA_LEN 36
++#define MRVDRV_MAXIMUM_ETH_PACKET_SIZE 1514
++
++#define MRVDRV_ETH_TX_PACKET_BUFFER_SIZE \
++ (MRVDRV_MAXIMUM_ETH_PACKET_SIZE + sizeof(TxPD) + EXTRA_LEN)
++
++#define MRVDRV_ETH_RX_PACKET_BUFFER_SIZE \
++ (MRVDRV_MAXIMUM_ETH_PACKET_SIZE + sizeof(RxPD) \
++ + MRVDRV_SNAP_HEADER_LEN + EXTRA_LEN)
++
++#define CMD_F_HOSTCMD (1 << 0)
++
++/* to resolve CISCO AP extension */
++#define MRVDRV_SCAN_LIST_VAR_IE_SPACE 256
++#define FW_IS_WPA_ENABLED(_adapter) \
++ (_adapter->fwCapInfo & FW_CAPINFO_WPA)
++
++#define FW_CAPINFO_WPA (1 << 0)
++#define WLAN_802_11_AI_REQFI_CAPABILITIES 1
++#define WLAN_802_11_AI_REQFI_LISTENINTERVAL 2
++#define WLAN_802_11_AI_REQFI_CURRENTAPADDRESS 4
++
++#define WLAN_802_11_AI_RESFI_CAPABILITIES 1
++#define WLAN_802_11_AI_RESFI_STATUSCODE 2
++#define WLAN_802_11_AI_RESFI_ASSOCIATIONID 4
++
++#define MRVL_NUM_WEP_KEY 4
++
++/** WPA Key LENGTH*/
++/* Support 4 keys per key set */
++#define MRVL_NUM_WPA_KEY_PER_SET 4
++#define MRVL_MAX_WPA_KEY_LENGTH 32
++
++#define WPA_AES_KEY_LEN 16
++#define WPA_TKIP_KEY_LEN 32
++
++/* A few details needed for WEP (Wireless Equivalent Privacy) */
++/* 104 bits */
++#define MAX_WEP_KEY_SIZE 13
++/*40 bits RC4 - WEP*/
++#define MIN_WEP_KEY_SIZE 5
++
++#define RF_ANTENNA_1 0x1
++#define RF_ANTENNA_2 0x2
++#define RF_ANTENNA_AUTO 0xFFFF
++
++#define KEY_INFO_ENABLED 0x01
++
++#define SNR_BEACON 0
++#define SNR_RXPD 1
++#define NF_BEACON 2
++#define NF_RXPD 3
++
++/** MACRO DEFINITIONS */
++#define CAL_NF(NF) ((s32)(-(s32)(NF)))
++#define CAL_RSSI(SNR, NF) ((s32)((s32)(SNR) + CAL_NF(NF)))
++#define SCAN_RSSI(RSSI) (0x100 - ((u8)(RSSI)))
++
++#define DEFAULT_BCN_AVG_FACTOR 8
++#define DEFAULT_DATA_AVG_FACTOR 8
++#define MIN_BCN_AVG_FACTOR 1
++#define MAX_BCN_AVG_FACTOR 8
++#define MIN_DATA_AVG_FACTOR 1
++#define MAX_DATA_AVG_FACTOR 8
++#define AVG_SCALE 100
++#define CAL_AVG_SNR_NF(AVG, SNRNF, N) \
++ (((AVG) == 0) ? ((u16)(SNRNF) * AVG_SCALE) : \
++ ((((int)(AVG) * (N -1)) + ((u16)(SNRNF) * \
++ AVG_SCALE)) / N))
++
++#define WLAN_STATUS_SUCCESS (0)
++#define WLAN_STATUS_FAILURE (-1)
++#define WLAN_STATUS_NOT_ACCEPTED (-2)
++
++#define MAX_LEDS 3
++#define LED_DISABLED 16
++#define LED_BLINKING 2
++
++/* S_SWAP : To swap 2 u8 */
++#define S_SWAP(a,b) do { \
++ u8 t = SArr[a]; \
++ SArr[a] = SArr[b]; SArr[b] = t; \
++ } while(0)
++
++/* SWAP: swap u8 */
++#define SWAP_U8(a,b) {u8 t; t=a; a=b; b=t;}
++
++/* SWAP: swap u8 */
++#define SWAP_U16(a,b) {u16 t; t=a; a=b; b=t;}
++
++#define wlan_le16_to_cpu(x) x
++#define wlan_le32_to_cpu(x) x
++#define wlan_le64_to_cpu(x) x
++#define wlan_cpu_to_le16(x) x
++#define wlan_cpu_to_le32(x) x
++#define wlan_cpu_to_le64(x) x
++
++#define endian_convert_TxPD(x)
++#define endian_convert_RxPD(x)
++#define endian_convert_GET_LOG(x)
++
++/** Global Varibale Declaration */
++typedef struct _wlan_private wlan_private;
++typedef struct _wlan_adapter wlan_adapter;
++typedef struct _HostCmd_DS_COMMAND HostCmd_DS_COMMAND;
++
++extern u32 DSFreqList[15];
++extern const char driver_version[];
++extern u32 DSFreqList[];
++extern u16 RegionCodeToIndex[MRVDRV_MAX_REGION_CODE];
++
++extern u8 WlanDataRates[WLAN_SUPPORTED_RATES];
++
++extern u8 SupportedRates[G_SUPPORTED_RATES];
++
++extern u8 AdhocRates_G[G_SUPPORTED_RATES];
++
++extern u8 AdhocRates_B[4];
++extern wlan_private *wlanpriv;
++
++#ifdef MFG_CMD_SUPPORT
++#define SIOCCFMFG SIOCDEVPRIVATE
++#endif /* MFG_CMD_SUPPORT */
++
++#define INTMODE_SDIO 0
++#define INTMODE_GPIO 1
++extern int intmode;
++extern int gpiopin;
++
++/** ENUM definition*/
++/** SNRNF_TYPE */
++typedef enum _SNRNF_TYPE
++{
++ TYPE_BEACON = 0,
++ TYPE_RXPD,
++ MAX_TYPE_B
++} SNRNF_TYPE;
++
++/** SNRNF_DATA*/
++typedef enum _SNRNF_DATA
++{
++ TYPE_NOAVG = 0,
++ TYPE_AVG,
++ MAX_TYPE_AVG
++} SNRNF_DATA;
++
++/** WLAN_802_11_AUTH_ALG*/
++typedef enum _WLAN_802_11_AUTH_ALG
++{
++ AUTH_ALG_OPEN_SYSTEM = 1,
++ AUTH_ALG_SHARED_KEY = 2,
++ AUTH_ALG_NETWORK_EAP = 8,
++} WLAN_802_11_AUTH_ALG;
++
++/** WLAN_802_11_ENCRYPTION_MODE */
++typedef enum _WLAN_802_11_ENCRYPTION_MODE
++{
++ CIPHER_NONE,
++ CIPHER_WEP40,
++ CIPHER_TKIP,
++ CIPHER_CCMP,
++ CIPHER_WEP104,
++} WLAN_802_11_ENCRYPTION_MODE;
++
++/** WLAN_802_11_POWER_MODE */
++typedef enum _WLAN_802_11_POWER_MODE
++{
++ Wlan802_11PowerModeCAM,
++ Wlan802_11PowerModeMAX_PSP,
++ Wlan802_11PowerModeFast_PSP,
++
++ /*not a real mode, defined as an upper bound */
++ Wlan802_11PowerModeMax
++} WLAN_802_11_POWER_MODE;
++
++/** PS_STATE */
++typedef enum _PS_STATE
++{
++ PS_STATE_FULL_POWER,
++ PS_STATE_AWAKE,
++ PS_STATE_PRE_SLEEP,
++ PS_STATE_SLEEP
++} PS_STATE;
++
++/** DNLD_STATE */
++typedef enum _DNLD_STATE
++{
++ DNLD_RES_RECEIVED,
++ DNLD_DATA_SENT,
++ DNLD_CMD_SENT
++} DNLD_STATE;
++
++/** WLAN_MEDIA_STATE */
++typedef enum _WLAN_MEDIA_STATE
++{
++ WlanMediaStateDisconnected,
++ WlanMediaStateConnected
++} WLAN_MEDIA_STATE;
++
++/** WLAN_802_11_PRIVACY_FILTER */
++typedef enum _WLAN_802_11_PRIVACY_FILTER
++{
++ Wlan802_11PrivFilterAcceptAll,
++ Wlan802_11PrivFilter8021xWEP
++} WLAN_802_11_PRIVACY_FILTER;
++
++/** mv_ms_type */
++typedef enum _mv_ms_type
++{
++ MVMS_DAT = 0,
++ MVMS_CMD = 1,
++ /* 2: reserved */
++ MVMS_EVENT = 3
++} mv_ms_type;
++
++/* Hardware status codes */
++typedef enum _WLAN_HARDWARE_STATUS
++{
++ WlanHardwareStatusReady,
++ WlanHardwareStatusInitializing,
++ WlanHardwareStatusReset,
++ WlanHardwareStatusClosing,
++ WlanHardwareStatusNotReady
++} WLAN_HARDWARE_STATUS;
++
++/** WLAN_802_11_AUTHENTICATION_MODE */
++typedef enum _WLAN_802_11_AUTHENTICATION_MODE
++{
++ Wlan802_11AuthModeOpen = 0x00,
++ Wlan802_11AuthModeShared = 0x01,
++ Wlan802_11AuthModeNetworkEAP = 0x80,
++} WLAN_802_11_AUTHENTICATION_MODE;
++
++/** WLAN_802_11_WEP_STATUS */
++typedef enum _WLAN_802_11_WEP_STATUS
++{
++ Wlan802_11WEPEnabled,
++ Wlan802_11WEPDisabled,
++ Wlan802_11WEPKeyAbsent,
++ Wlan802_11WEPNotSupported
++} WLAN_802_11_WEP_STATUS;
++
++/** SNMP_MIB_INDEX_e */
++typedef enum _SNMP_MIB_INDEX_e
++{
++ DesiredBssType_i = 0,
++ OpRateSet_i,
++ BcnPeriod_i,
++ DtimPeriod_i,
++ AssocRspTimeOut_i,
++ RtsThresh_i,
++ ShortRetryLim_i,
++ LongRetryLim_i,
++ FragThresh_i,
++ Dot11D_i,
++ Dot11H_i,
++ ManufId_i,
++ ProdId_i,
++ ManufOui_i,
++ ManufName_i,
++ ManufProdName_i,
++ ManufProdVer_i
++} SNMP_MIB_INDEX_e;
++
++/** KEY_TYPE_ID */
++typedef enum _KEY_TYPE_ID
++{
++ KEY_TYPE_ID_WEP = 0,
++ KEY_TYPE_ID_TKIP,
++ KEY_TYPE_ID_AES
++} KEY_TYPE_ID;
++
++/** KEY_INFO_WEP*/
++typedef enum _KEY_INFO_WEP
++{
++ KEY_INFO_WEP_DEFAULT_KEY = 0x01
++} KEY_INFO_WEP;
++
++/** KEY_INFO_TKIP */
++typedef enum _KEY_INFO_TKIP
++{
++ KEY_INFO_TKIP_MCAST = 0x01,
++ KEY_INFO_TKIP_UNICAST = 0x02,
++ KEY_INFO_TKIP_ENABLED = 0x04
++} KEY_INFO_TKIP;
++
++/** KEY_INFO_AES*/
++typedef enum _KEY_INFO_AES
++{
++ KEY_INFO_AES_MCAST = 0x01,
++ KEY_INFO_AES_UNICAST = 0x02,
++ KEY_INFO_AES_ENABLED = 0x04
++} KEY_INFO_AES;
++
++/** SNMP_MIB_VALUE_e */
++typedef enum _SNMP_MIB_VALUE_e
++{
++ SNMP_MIB_VALUE_INFRA = 1,
++ SNMP_MIB_VALUE_ADHOC
++} SNMP_MIB_VALUE_e;
++
++/** HWRateDropMode */
++typedef enum _HWRateDropMode
++{
++ NO_HW_RATE_DROP,
++ HW_TABLE_RATE_DROP,
++ HW_SINGLE_RATE_DROP
++} HWRateDropMode;
++
++#ifdef __KERNEL__
++extern struct iw_handler_def wlan_handler_def;
++struct iw_statistics *wlan_get_wireless_stats(struct net_device *dev);
++int wlan_do_ioctl(struct net_device *dev, struct ifreq *req, int i);
++#endif
++
++#endif /* _WLAN_DEFS_H_ */
+diff --git a/drivers/net/wireless/marvell8686/wlan_dev.h b/drivers/net/wireless/marvell8686/wlan_dev.h
+new file mode 100644
+index 0000000..c818b0c
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_dev.h
+@@ -0,0 +1,468 @@
++/** @file wlan_dev.h
++ * @brief This file contains definitions and data structures specific
++ * to Marvell 802.11 NIC. It contains the Device Information
++ * structure wlan_adapter.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/*************************************************************
++Change log:
++ 09/26/05: add Doxygen format comments
++ 01/11/06: Conditionalize new scan/join structures.
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 05/08/06: Remove PermanentAddr from Adapter
++
++ ************************************************************/
++
++#ifndef _WLAN_DEV_H_
++#define _WLAN_DEV_H_
++
++#define MAX_BSSID_PER_CHANNEL 16
++
++/* For the extended Scan */
++#define MAX_EXTENDED_SCAN_BSSID_LIST MAX_BSSID_PER_CHANNEL * \
++ MRVDRV_MAX_CHANNEL_SIZE + 1
++
++typedef struct _PER_CHANNEL_BSSID_LIST_DATA
++{
++ u8 ucStart;
++ u8 ucNumEntry;
++} PER_CHANNEL_BSSID_LIST_DATA, *PPER_CHANNEL_BSSID_LIST_DATA;
++
++typedef struct _MRV_BSSID_IE_LIST
++{
++ WLAN_802_11_FIXED_IEs FixedIE;
++ u8 VariableIE[MRVDRV_SCAN_LIST_VAR_IE_SPACE];
++} MRV_BSSID_IE_LIST, *PMRV_BSSID_IE_LIST;
++
++#define MAX_REGION_CHANNEL_NUM 2
++
++/** Chan-Freq-TxPower mapping table*/
++typedef struct _CHANNEL_FREQ_POWER
++{
++ /** Channel Number */
++ u16 Channel;
++ /** Frequency of this Channel */
++ u32 Freq;
++ /** Max allowed Tx power level */
++ u16 MaxTxPower;
++ /** TRUE:channel unsupported; FLASE:supported*/
++ BOOLEAN Unsupported;
++} CHANNEL_FREQ_POWER;
++
++/** region-band mapping table*/
++typedef struct _REGION_CHANNEL
++{
++ /** TRUE if this entry is valid */
++ BOOLEAN Valid;
++ /** Region code for US, Japan ... */
++ u8 Region;
++ /** Band B/G/A, used for BAND_CONFIG cmd */
++ u8 Band;
++ /** Actual No. of elements in the array below */
++ u8 NrCFP;
++ /** chan-freq-txpower mapping table*/
++ CHANNEL_FREQ_POWER *CFP;
++} REGION_CHANNEL;
++
++typedef struct _wlan_802_11_security_t
++{
++ BOOLEAN WPAEnabled;
++ BOOLEAN WPA2Enabled;
++ WLAN_802_11_WEP_STATUS WEPStatus;
++ WLAN_802_11_AUTHENTICATION_MODE AuthenticationMode;
++ WLAN_802_11_ENCRYPTION_MODE EncryptionMode;
++} wlan_802_11_security_t;
++
++/** Current Basic Service Set State Structure */
++typedef struct
++{
++ BSSDescriptor_t BSSDescriptor;
++
++ /** band */
++ u8 band;
++
++ /** number of rates supported */
++ int NumOfRates;
++
++ /** supported rates*/
++ u8 DataRates[WLAN_SUPPORTED_RATES];
++
++ /** wmm enable? */
++ u8 wmm_enabled;
++
++ /** uapsd enable?*/
++ u8 wmm_uapsd_enabled;
++} CurrentBSSParams_t;
++
++/** sleep_params */
++typedef struct SleepParams
++{
++ u16 sp_error;
++ u16 sp_offset;
++ u16 sp_stabletime;
++ u8 sp_calcontrol;
++ u8 sp_extsleepclk;
++ u16 sp_reserved;
++} SleepParams;
++
++/** sleep_period */
++typedef struct SleepPeriod
++{
++ u16 period;
++ u16 reserved;
++} SleepPeriod;
++
++#define DBG_CMD_NUM 5
++
++/** info for debug purpose */
++typedef struct _wlan_dbg
++{
++ u32 num_cmd_host_to_card_failure;
++ u32 num_cmd_sleep_cfm_host_to_card_failure;
++ u32 num_tx_host_to_card_failure;
++ u32 num_event_deauth;
++ u32 num_event_disassoc;
++ u32 num_event_link_lost;
++ u32 num_cmd_deauth;
++ u32 num_cmd_assoc_success;
++ u32 num_cmd_assoc_failure;
++ u32 num_tx_timeout;
++ u32 num_cmd_timeout;
++ u16 TimeoutCmdId;
++ u16 TimeoutCmdAct;
++ u16 LastCmdId[DBG_CMD_NUM];
++ u16 LastCmdAct[DBG_CMD_NUM];
++ u16 LastCmdIndex;
++ u16 LastCmdRespId[DBG_CMD_NUM];
++ u16 LastCmdRespIndex;
++ u16 LastEvent[DBG_CMD_NUM];
++ u16 LastEventIndex;
++} wlan_dbg;
++
++/** Data structure for the Marvell WLAN device */
++typedef struct _wlan_dev
++{
++ /** device name */
++ char name[DEV_NAME_LEN];
++ /** card pointer */
++ void *card;
++ /** IO port */
++ u32 ioport;
++ /** Upload received */
++ u32 upld_rcv;
++ /** Upload type */
++ u32 upld_typ;
++ /** Upload length */
++ u32 upld_len;
++ /** netdev pointer */
++ struct net_device *netdev;
++ /* Upload buffer */
++ u8 upld_buf[WLAN_UPLD_SIZE];
++ /* Download sent:
++ bit0 1/0=data_sent/data_tx_done,
++ bit1 1/0=cmd_sent/cmd_tx_done,
++ all other bits reserved 0 */
++ u8 dnld_sent;
++} wlan_dev_t, *pwlan_dev_t;
++
++/* Data structure for WPS information */
++typedef struct
++{
++ IEEEtypes_VendorSpecific_t wpsIe;
++ BOOLEAN SessionEnable;
++} wps_t;
++
++/** Private structure for the MV device */
++struct _wlan_private
++{
++ int open;
++
++ wlan_adapter *adapter;
++ wlan_dev_t wlan_dev;
++
++ struct net_device_stats stats;
++
++ struct iw_statistics wstats;
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++ struct proc_dir_entry *proc_entry;
++ struct proc_dir_entry *proc_dev;
++#endif
++
++ /** thread to service interrupts */
++ wlan_thread MainThread;
++
++#ifdef REASSOCIATION
++ /** thread to service mac events */
++ wlan_thread ReassocThread;
++#endif /* REASSOCIATION */
++};
++
++/** Wlan Adapter data structure*/
++struct _wlan_adapter
++{
++ u8 TmpTxBuf[WLAN_UPLD_SIZE] __ATTRIB_ALIGN__;
++ /** STATUS variables */
++ WLAN_HARDWARE_STATUS HardwareStatus;
++ u32 FWReleaseNumber;
++ u32 fwCapInfo;
++ u8 chip_rev;
++
++ /** Command-related variables */
++ u16 SeqNum;
++ CmdCtrlNode *CmdArray;
++ /** Current Command */
++ CmdCtrlNode *CurCmd;
++ int CurCmdRetCode;
++
++ /** Command Queues */
++ /** Free command buffers */
++ struct list_head CmdFreeQ;
++ /** Pending command buffers */
++ struct list_head CmdPendingQ;
++
++ /** Variables brought in from private structure */
++ int irq;
++
++ /** Async and Sync Event variables */
++ u32 IntCounter;
++ u32 IntCounterSaved; /* save int for DS/PS */
++ u32 EventCause;
++ u8 nodeName[16]; /* nickname */
++
++ /** spin locks */
++ spinlock_t QueueSpinLock __ATTRIB_ALIGN__;
++
++ /** Timers */
++ WLAN_DRV_TIMER MrvDrvCommandTimer __ATTRIB_ALIGN__;
++ BOOLEAN CommandTimerIsSet;
++
++#ifdef REASSOCIATION
++ /**Reassociation timer*/
++ BOOLEAN ReassocTimerIsSet;
++ WLAN_DRV_TIMER MrvDrvTimer __ATTRIB_ALIGN__;
++#endif /* REASSOCIATION */
++
++ /** Event Queues */
++ wait_queue_head_t ds_awake_q __ATTRIB_ALIGN__;
++
++ u8 HisRegCpy;
++
++ /** bg scan related variable */
++ HostCmd_DS_802_11_BG_SCAN_CONFIG *bgScanConfig;
++ u32 bgScanConfigSize;
++
++ /** WMM related variable*/
++ WMM_DESC wmm;
++
++ /** current ssid/bssid related parameters*/
++ CurrentBSSParams_t CurBssParams;
++
++ WLAN_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
++
++ BSSDescriptor_t *pAttemptedBSSDesc;
++
++ WLAN_802_11_SSID AttemptedSSIDBeforeScan;
++ WLAN_802_11_SSID PreviousSSID;
++ u8 PreviousBSSID[MRVDRV_ETH_ADDR_LEN];
++
++ BSSDescriptor_t *ScanTable;
++ u32 NumInScanTable;
++
++ u8 ScanType;
++ u32 ScanMode;
++ u16 SpecificScanTime;
++ u16 ActiveScanTime;
++ u16 PassiveScanTime;
++
++ u16 BeaconPeriod;
++ u8 AdhocCreate;
++ BOOLEAN AdhocLinkSensed;
++
++#ifdef REASSOCIATION
++ /** Reassociation on and off */
++ BOOLEAN Reassoc_on;
++ SEMAPHORE ReassocSem;
++#endif /* REASSOCIATION */
++
++ BOOLEAN ATIMEnabled;
++
++ /** MAC address information */
++ u8 CurrentAddr[MRVDRV_ETH_ADDR_LEN];
++ u8 MulticastList[MRVDRV_MAX_MULTICAST_LIST_SIZE]
++ [MRVDRV_ETH_ADDR_LEN];
++ u32 NumOfMulticastMACAddr;
++
++ u16 HWRateDropMode;
++ u16 RateBitmap;
++ u16 Threshold;
++ u16 FinalRate;
++ /** control G Rates */
++ BOOLEAN adhoc_grate_enabled;
++
++ WLAN_802_11_ANTENNA TxAntenna;
++ WLAN_802_11_ANTENNA RxAntenna;
++
++ u8 AdhocChannel;
++ WLAN_802_11_FRAGMENTATION_THRESHOLD FragThsd;
++ WLAN_802_11_RTS_THRESHOLD RTSThsd;
++
++ u32 DataRate;
++ BOOLEAN Is_DataRate_Auto;
++
++ /** number of association attempts for the current SSID cmd */
++ u16 ListenInterval;
++ u16 TxRetryCount;
++
++ u16 Dtim;
++
++ /** Tx-related variables (for single packet tx) */
++ struct sk_buff *CurrentTxSkb;
++ struct sk_buff RxSkbQ;
++ BOOLEAN TxLockFlag;
++ u16 gen_null_pkg;
++ spinlock_t CurrentTxLock __ATTRIB_ALIGN__;
++
++ /** NIC Operation characteristics */
++ u16 CurrentPacketFilter;
++ u32 MediaConnectStatus;
++ u16 RegionCode;
++ u16 TxPowerLevel;
++ u8 MaxTxPowerLevel;
++ u8 MinTxPowerLevel;
++
++ /** POWER MANAGEMENT AND PnP SUPPORT */
++ BOOLEAN SurpriseRemoved;
++ u16 AtimWindow;
++
++ u16 PSMode; /* Wlan802_11PowerModeCAM=disable
++ Wlan802_11PowerModeMAX_PSP=enable */
++ u16 MultipleDtim;
++ u16 BCNMissTimeOut;
++ u32 PSState;
++ BOOLEAN NeedToWakeup;
++
++ PS_CMD_ConfirmSleep PSConfirmSleep;
++ u16 LocalListenInterval;
++ u16 NullPktInterval;
++ u16 AdhocAwakePeriod;
++ u16 fwWakeupMethod;
++ BOOLEAN IsDeepSleep;
++ BOOLEAN IsAutoDeepSleepEnabled;
++ BOOLEAN bWakeupDevRequired;
++ u32 WakeupTries;
++ BOOLEAN bHostSleepConfigured;
++ HostCmd_DS_802_11_HOST_SLEEP_CFG HSCfg;
++ /** ARP filter related variable */
++ u8 ArpFilter[ARP_FILTER_MAX_BUF_SIZE];
++ u32 ArpFilterSize;
++ BOOLEAN HS_Activated;
++
++ /** Encryption parameter */
++ wlan_802_11_security_t SecInfo;
++
++ MRVL_WEP_KEY WepKey[MRVL_NUM_WEP_KEY];
++ u16 CurrentWepKeyIndex;
++
++ /** Buffer for TLVs passed from the application to be inserted into the
++ * association request to firmware
++ */
++ u8 mrvlAssocTlvBuffer[MRVDRV_ASSOC_TLV_BUF_SIZE];
++
++ /** Length of the data stored in mrvlAssocTlvBuffer*/
++ u8 mrvlAssocTlvBufferLen;
++
++ /** Buffer to store the association response for application retrieval */
++ u8 assocRspBuffer[MRVDRV_ASSOC_RSP_BUF_SIZE];
++
++ /** Length of the data stored in assocRspBuffer */
++ int assocRspSize;
++
++ /** Generice IEEE IEs passed from the application to be inserted into the
++ * association request to firmware
++ */
++ u8 genIeBuffer[MRVDRV_GENIE_BUF_SIZE];
++
++ /** Length of the data stored in genIeBuffer */
++ u8 genIeBufferLen;
++
++ BOOLEAN IsGTK_SET;
++
++ /** Encryption Key*/
++ u8 Wpa_ie[256];
++ u8 Wpa_ie_len;
++
++ HostCmd_DS_802_11_KEY_MATERIAL aeskey;
++
++ /* Advanced Encryption Standard */
++ BOOLEAN AdhocAESEnabled;
++ wait_queue_head_t cmd_EncKey __ATTRIB_ALIGN__;
++
++ u16 RxAntennaMode;
++ u16 TxAntennaMode;
++
++ /** Requested Signal Strength*/
++ u16 bcn_avg_factor;
++ u16 data_avg_factor;
++ u16 SNR[MAX_TYPE_B][MAX_TYPE_AVG];
++ u16 NF[MAX_TYPE_B][MAX_TYPE_AVG];
++ u8 RSSI[MAX_TYPE_B][MAX_TYPE_AVG];
++ u8 rawSNR[DEFAULT_DATA_AVG_FACTOR];
++ u8 rawNF[DEFAULT_DATA_AVG_FACTOR];
++ u16 nextSNRNF;
++ u16 numSNRNF;
++ u32 RxPDAge;
++ u16 RxPDRate;
++
++ BOOLEAN RadioOn;
++
++ /** Blue Tooth Co-existence Arbitration */
++ HostCmd_DS_802_11_BCA_TIMESHARE bca_ts;
++
++ /** sleep_params */
++ SleepParams sp;
++
++ /** sleep_period (Enhanced Power Save) */
++ SleepPeriod sleep_period;
++
++#define MAX_REGION_CHANNEL_NUM 2
++ /** Region Channel data */
++ REGION_CHANNEL region_channel[MAX_REGION_CHANNEL_NUM];
++
++ REGION_CHANNEL universal_channel[MAX_REGION_CHANNEL_NUM];
++
++ /** 11D and Domain Regulatory Data */
++ wlan_802_11d_domain_reg_t DomainReg;
++ parsed_region_chan_11d_t parsed_region_chan;
++
++ /** FSM variable for 11d support */
++ wlan_802_11d_state_t State11D;
++ u8 beaconBuffer[MAX_SCAN_BEACON_BUFFER];
++ u8 *pBeaconBufEnd;
++
++ /** MISCELLANEOUS */
++ /* Card Information Structure */
++ u8 CisInfoBuf[512];
++ u16 CisInfoLen;
++
++ HostCmd_DS_802_11_GET_LOG LogMsg;
++ u16 ScanProbes;
++
++ u32 PktTxCtrl;
++
++ u8 *helper;
++ u32 helper_len;
++ u8 *fmimage;
++ u32 fmimage_len;
++ u16 TxRate;
++
++ wps_t wps;
++
++ wlan_dbg dbg;
++ wlan_subscribe_event subevent;
++ u8 sdiomode;
++ u32 num_cmd_timeout;
++};
++
++#endif /* _WLAN_DEV_H_ */
+diff --git a/drivers/net/wireless/marvell8686/wlan_fops.c b/drivers/net/wireless/marvell8686/wlan_fops.c
+new file mode 100644
+index 0000000..1e27d6f
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_fops.c
+@@ -0,0 +1,217 @@
++/** @file wlan_fops.c
++ * @brief This file contains the file read functions
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 01/06/06: Add Doxygen format comments
++
++********************************************************/
++
++#include "include.h"
++
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <asm/fcntl.h>
++#include <linux/vmalloc.h>
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function opens/create a file in kernel mode.
++ *
++ * @param filename Name of the file to be opened
++ * @param flags File flags
++ * @param mode File permissions
++ * @return file pointer if successful or NULL if failed.
++ */
++static struct file *
++wlan_fopen(const char *filename, unsigned int flags, int mode)
++{
++ int orgfsuid, orgfsgid;
++ struct file *file_ret;
++
++ /* Save uid and gid used for filesystem access. */
++
++ orgfsuid = current->fsuid;
++ orgfsgid = current->fsgid;
++
++ /* Set user and group to 0 (root) */
++ current->fsuid = 0;
++ current->fsgid = 0;
++
++ /* Open the file in kernel mode */
++ file_ret = filp_open(filename, flags, mode);
++
++ /* Restore the uid and gid */
++ current->fsuid = orgfsuid;
++ current->fsgid = orgfsgid;
++
++ /* Check if the file was opened successfully
++ and return the file pointer of it was. */
++ return ((IS_ERR(file_ret)) ? NULL : file_ret);
++}
++
++/**
++ * @brief This function closes a file in kernel mode.
++ *
++ * @param file_ptr File pointer
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_fclose(struct file *file_ptr)
++{
++ int orgfsuid, orgfsgid;
++ int file_ret;
++
++ if ((NULL == file_ptr) || (IS_ERR(file_ptr)))
++ return -ENOENT;
++
++ /* Save uid and gid used for filesystem access. */
++ orgfsuid = current->fsuid;
++ orgfsgid = current->fsgid;
++
++ /* Set user and group to 0 (root) */
++ current->fsuid = 0;
++ current->fsgid = 0;
++
++ /* Close the file in kernel mode (user_id = 0) */
++ file_ret = filp_close(file_ptr, 0);
++
++ /* Restore the uid and gid */
++ current->fsuid = orgfsuid;
++ current->fsgid = orgfsgid;
++
++ return (file_ret);
++}
++
++/**
++ * @brief This function reads data from files in kernel mode.
++ *
++ * @param file_ptr File pointer
++ * @param buf Buffers to read data into
++ * @param len Length of buffer
++ * @return number of characters read
++ */
++static int
++wlan_fread(struct file *file_ptr, char *buf, int len)
++{
++ int orgfsuid, orgfsgid;
++ int file_ret;
++ mm_segment_t orgfs;
++
++ /* Check if the file pointer is valid */
++ if ((NULL == file_ptr) || (IS_ERR(file_ptr)))
++ return -ENOENT;
++
++ /* Check for a valid file read function */
++ if (file_ptr->f_op->read == NULL)
++ return -ENOSYS;
++
++ /* Check for access permissions */
++ if (((file_ptr->f_flags & O_ACCMODE) & (O_RDONLY | O_RDWR)) == 0)
++ return -EACCES;
++
++ /* Check if there is a valid length */
++ if (0 >= len)
++ return -EINVAL;
++
++ /* Save uid and gid used for filesystem access. */
++ orgfsuid = current->fsuid;
++ orgfsgid = current->fsgid;
++
++ /* Set user and group to 0 (root) */
++ current->fsuid = 0;
++ current->fsgid = 0;
++
++ /* Save FS register and set FS register to kernel
++ space, needed for read and write to accept
++ buffer in kernel space. */
++ orgfs = get_fs();
++
++ /* Set the FS register to KERNEL mode. */
++ set_fs(KERNEL_DS);
++
++ /* Read the actual data from the file */
++ file_ret = file_ptr->f_op->read(file_ptr, buf, len, &file_ptr->f_pos);
++
++ /* Restore the FS register */
++ set_fs(orgfs);
++
++ /* Restore the uid and gid */
++ current->fsuid = orgfsuid;
++ current->fsgid = orgfsgid;
++
++ return (file_ret);
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief This function free FW/Helper buffer.
++ *
++ * @param addr Pointer to buffer storing FW/Helper
++ * @return None
++ */
++void
++fw_buffer_free(u8 * addr)
++{
++ vfree(addr);
++}
++
++/**
++ * @brief This function reads FW/Helper.
++ *
++ * @param name File name
++ * @param addr Pointer to buffer storing FW/Helper
++ * @param len Pointer to length of FW/Helper
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++fw_read(const char *name, u8 ** addr, u32 * len)
++{
++ struct file *fp;
++ int ret;
++ u8 *ptr;
++
++ fp = wlan_fopen(name, O_RDWR, 0);
++
++ if (fp == NULL) {
++ PRINTM(MSG, "Could not open file:%s\n", name);
++ return WLAN_STATUS_FAILURE;
++ }
++
++ /*calculate file length */
++ *len = fp->f_dentry->d_inode->i_size - fp->f_pos;
++
++ ptr = (u8 *) vmalloc(*len + 1023);
++ if (ptr == NULL) {
++ PRINTM(MSG, "vmalloc failure\n");
++ return WLAN_STATUS_FAILURE;
++ }
++ if (wlan_fread(fp, ptr, *len) > 0) {
++ *addr = ptr;
++ ret = WLAN_STATUS_SUCCESS;
++ } else {
++ fw_buffer_free(ptr);
++ *addr = NULL;
++ PRINTM(MSG, "fail to read the file %s \n", name);
++ ret = WLAN_STATUS_FAILURE;
++ }
++
++ wlan_fclose(fp);
++ return ret;
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_fw.c b/drivers/net/wireless/marvell8686/wlan_fw.c
+new file mode 100644
+index 0000000..0fc258d
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_fw.c
+@@ -0,0 +1,532 @@
++/** @file wlan_fw.c
++ * @brief This file contains the initialization for FW
++ * and HW
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 09/28/05: Add Doxygen format comments
++ 01/05/06: Add kernel 2.6.x support
++ 01/11/06: Conditionalize new scan/join functions.
++ Cleanup association response handler initialization.
++ 01/06/05: Add FW file read
++ 05/08/06: Remove the 2nd GET_HW_SPEC command and TempAddr/PermanentAddr
++ 06/30/06: replaced MODULE_PARM(name, type) with module_param(name, type, perm)
++
++********************************************************/
++
++#include "include.h"
++#include <linux/vmalloc.h>
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++extern const char *helper_name;
++extern const char *fw_name;
++
++#if 0
++module_param(helper_name, charp, 0);
++module_param(fw_name, charp, 0);
++#endif
++
++#ifdef MFG_CMD_SUPPORT
++int mfgmode = 0;
++module_param(mfgmode, int, 0);
++#endif
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function downloads firmware image, gets
++ * HW spec from firmware and set basic parameters to
++ * firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_setup_station_hw(wlan_private * priv)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *adapter = priv->adapter;
++ u8 *ptr = NULL;
++ u32 len = 0;
++
++ //HostCmd_DS_SDIO_INT_CONFIG sdio_int_cfg;
++
++ ENTER();
++
++ sbi_disable_host_int(priv);
++
++#if 0
++ if ((intmode == INTMODE_GPIO) && (gpiopin == 0)) {
++ PRINTM(MSG, "Invalid gpio pin#\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++#endif
++
++ adapter->fmimage = NULL;
++ adapter->fmimage_len = 0;
++ adapter->helper = NULL;
++ adapter->helper_len = 0;
++
++ if (helper_name != NULL) {
++ if (fw_read(helper_name, &ptr, &len) != WLAN_STATUS_FAILURE) {
++ adapter->helper = ptr;
++ adapter->helper_len = len;
++ PRINTM(INFO, "helper read success, len=%x\n", len);
++ } else {
++ PRINTM(MSG, "helper %s read fail.\n", helper_name);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ }
++
++ if (fw_name != NULL) {
++ if (fw_read(fw_name, &ptr, &len) != WLAN_STATUS_FAILURE) {
++ adapter->fmimage = ptr;
++ adapter->fmimage_len = len;
++ PRINTM(INFO, "fw read success, len=%x\n", len);
++ } else {
++ PRINTM(MSG, "fw %s read fail.\n", fw_name);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ }
++
++ /* Download the helper */
++ ret = sbi_prog_helper(priv);
++
++ if (ret) {
++ PRINTM(INFO, "Bootloader in invalid state!\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ /* Download the main firmware via the helper firmware */
++ if (sbi_prog_firmware_w_helper(priv)) {
++ PRINTM(INFO, "Wlan FW download failed!\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* check if the fimware is downloaded successfully or not */
++ if (sbi_verify_fw_download(priv)) {
++ PRINTM(INFO, "FW failed to be active in time!\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++#define RF_REG_OFFSET 0x07
++#define RF_REG_VALUE 0xc8
++
++ sbi_enable_host_int(priv);
++
++#define INT_RASING_EDGE 0
++#define INT_FALLING_EDGE 1
++
++#define DELAY_1_US 1
++#if 0
++ if (intmode == INTMODE_GPIO) {
++ /* This command should be issued first */
++ sdio_int_cfg.Action = HostCmd_ACT_GEN_SET;
++ sdio_int_cfg.Gpio_pin = gpiopin;
++ sdio_int_cfg.Gpio_int_edge = INT_FALLING_EDGE;
++ sdio_int_cfg.Gpio_pulse_width = DELAY_1_US;
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_SDIO_GPIO_INT_CONFIG,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, &sdio_int_cfg);
++ }
++#endif
++#ifdef MFG_CMD_SUPPORT
++ if (mfgmode == 0) {
++#endif
++
++ /*
++ * Read MAC address from HW
++ */
++ memset(adapter->CurrentAddr, 0xff, MRVDRV_ETH_ADDR_LEN);
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_GET_HW_SPEC,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_MAC_CONTROL,
++ 0, HostCmd_OPTION_WAITFORRSP, 0,
++ &adapter->CurrentPacketFilter);
++
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_FW_WAKE_METHOD,
++ HostCmd_ACT_GET,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ &priv->adapter->fwWakeupMethod);
++
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++#ifdef MFG_CMD_SUPPORT
++ }
++#endif
++
++#ifdef MFG_CMD_SUPPORT
++ if (mfgmode == 0) {
++#endif
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RATE_ADAPT_RATESET,
++ HostCmd_ACT_GEN_GET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ priv->adapter->DataRate = 0;
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RF_TX_POWER,
++ HostCmd_ACT_GEN_GET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++#ifdef MFG_CMD_SUPPORT
++ }
++#endif
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ if (adapter->helper != NULL) {
++ fw_buffer_free(adapter->helper);
++ }
++ if (adapter->fmimage != NULL) {
++ fw_buffer_free(adapter->fmimage);
++ }
++
++ LEAVE();
++
++ return (ret);
++}
++
++/**
++ * @brief This function initializes timers.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++static void
++init_sync_objects(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ InitializeTimer(&Adapter->MrvDrvCommandTimer,
++ MrvDrvCommandTimerFunction, priv);
++ Adapter->CommandTimerIsSet = FALSE;
++
++#ifdef REASSOCIATION
++ /* Initialize the timer for the reassociation */
++ InitializeTimer(&Adapter->MrvDrvTimer, MrvDrvReassocTimerFunction, priv);
++ Adapter->ReassocTimerIsSet = FALSE;
++#endif /* REASSOCIATION */
++
++ return;
++}
++
++/**
++ * @brief This function allocates buffer for the member of adapter
++ * structure like command buffer and BSSID list.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_allocate_adapter(wlan_private * priv)
++{
++ u32 ulBufSize;
++ wlan_adapter *Adapter = priv->adapter;
++
++ BSSDescriptor_t *pTempScanTable;
++
++ /* Allocate buffer to store the BSSID list */
++ ulBufSize = sizeof(BSSDescriptor_t) * MRVDRV_MAX_BSSID_LIST;
++ if (!(pTempScanTable = kmalloc(ulBufSize, GFP_KERNEL))) {
++ return WLAN_STATUS_FAILURE;
++ }
++
++ Adapter->ScanTable = pTempScanTable;
++ memset(Adapter->ScanTable, 0, ulBufSize);
++
++ if (!(Adapter->bgScanConfig =
++ kmalloc(sizeof(HostCmd_DS_802_11_BG_SCAN_CONFIG), GFP_KERNEL))) {
++ return WLAN_STATUS_FAILURE;
++ }
++ Adapter->bgScanConfigSize = sizeof(HostCmd_DS_802_11_BG_SCAN_CONFIG);
++ memset(Adapter->bgScanConfig, 0, Adapter->bgScanConfigSize);
++
++ spin_lock_init(&Adapter->QueueSpinLock);
++
++ /* Allocate the command buffers */
++ if (AllocateCmdBuffer(priv) != WLAN_STATUS_SUCCESS) {
++ return WLAN_STATUS_FAILURE;
++ }
++
++ memset(&Adapter->PSConfirmSleep, 0, sizeof(PS_CMD_ConfirmSleep));
++ Adapter->PSConfirmSleep.SeqNum = wlan_cpu_to_le16(++Adapter->SeqNum);
++ Adapter->PSConfirmSleep.Command =
++ wlan_cpu_to_le16(HostCmd_CMD_802_11_PS_MODE);
++ Adapter->PSConfirmSleep.Size =
++ wlan_cpu_to_le16(sizeof(PS_CMD_ConfirmSleep));
++ Adapter->PSConfirmSleep.Result = 0;
++ Adapter->PSConfirmSleep.Action =
++ wlan_cpu_to_le16(HostCmd_SubCmd_Sleep_Confirmed);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function initializes the adapter structure
++ * and set default value to the member of adapter.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++static void
++wlan_init_adapter(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int i;
++
++ Adapter->ScanProbes = 0;
++
++ Adapter->bcn_avg_factor = DEFAULT_BCN_AVG_FACTOR;
++ Adapter->data_avg_factor = DEFAULT_DATA_AVG_FACTOR;
++
++ /* ATIM params */
++ Adapter->AtimWindow = 0;
++ Adapter->ATIMEnabled = FALSE;
++
++ Adapter->MediaConnectStatus = WlanMediaStateDisconnected;
++
++ memset(Adapter->CurrentAddr, 0xff, MRVDRV_ETH_ADDR_LEN);
++
++ /* Status variables */
++ Adapter->HardwareStatus = WlanHardwareStatusInitializing;
++
++ /* scan type */
++ Adapter->ScanType = HostCmd_SCAN_TYPE_ACTIVE;
++
++ /* scan mode */
++ Adapter->ScanMode = HostCmd_BSS_TYPE_ANY;
++
++ /* scan time */
++ Adapter->SpecificScanTime = MRVDRV_SPECIFIC_SCAN_CHAN_TIME;
++ Adapter->ActiveScanTime = MRVDRV_ACTIVE_SCAN_CHAN_TIME;
++ Adapter->PassiveScanTime = MRVDRV_PASSIVE_SCAN_CHAN_TIME;
++
++ /* 802.11 specific */
++ Adapter->SecInfo.WEPStatus = Wlan802_11WEPDisabled;
++ for (i = 0; i < sizeof(Adapter->WepKey) / sizeof(Adapter->WepKey[0]); i++)
++ memset(&Adapter->WepKey[i], 0, sizeof(MRVL_WEP_KEY));
++ Adapter->CurrentWepKeyIndex = 0;
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeOpen;
++ Adapter->SecInfo.EncryptionMode = CIPHER_NONE;
++ Adapter->AdhocAESEnabled = FALSE;
++ Adapter->InfrastructureMode = Wlan802_11Infrastructure;
++
++ Adapter->NumInScanTable = 0;
++ Adapter->pAttemptedBSSDesc = NULL;
++#ifdef REASSOCIATION
++ OS_INIT_SEMAPHORE(&Adapter->ReassocSem);
++#endif
++ Adapter->pBeaconBufEnd = Adapter->beaconBuffer;
++
++ Adapter->HisRegCpy |= HIS_TxDnLdRdy;
++
++ memset(&Adapter->CurBssParams, 0, sizeof(Adapter->CurBssParams));
++
++ /* PnP and power profile */
++ Adapter->SurpriseRemoved = FALSE;
++
++ Adapter->CurrentPacketFilter =
++ HostCmd_ACT_MAC_RTS_CTS_ENABLE |
++ HostCmd_ACT_MAC_RX_ON | HostCmd_ACT_MAC_TX_ON;
++
++ Adapter->RadioOn = RADIO_ON;
++#ifdef REASSOCIATION
++#if (WIRELESS_EXT >= 18)
++ Adapter->Reassoc_on = FALSE;
++#else
++ Adapter->Reassoc_on = TRUE;
++#endif
++#endif /* REASSOCIATION */
++ Adapter->TxAntenna = RF_ANTENNA_2;
++ Adapter->RxAntenna = RF_ANTENNA_AUTO;
++
++ Adapter->HWRateDropMode = HW_TABLE_RATE_DROP;
++ Adapter->Is_DataRate_Auto = TRUE;
++ Adapter->BeaconPeriod = MRVDRV_BEACON_INTERVAL;
++
++ Adapter->AdhocChannel = DEFAULT_AD_HOC_CHANNEL;
++
++ Adapter->PSMode = Wlan802_11PowerModeCAM;
++ Adapter->MultipleDtim = MRVDRV_DEFAULT_MULTIPLE_DTIM;
++
++ Adapter->ListenInterval = MRVDRV_DEFAULT_LISTEN_INTERVAL;
++
++ Adapter->PSState = PS_STATE_FULL_POWER;
++
++ Adapter->NeedToWakeup = FALSE;
++ Adapter->LocalListenInterval = 0; /* default value in firmware will be used */
++ Adapter->fwWakeupMethod = WAKEUP_FW_UNCHANGED;
++
++ Adapter->IsDeepSleep = FALSE;
++ Adapter->IsAutoDeepSleepEnabled = FALSE;
++
++ Adapter->bWakeupDevRequired = FALSE;
++
++ Adapter->WakeupTries = 0;
++ Adapter->bHostSleepConfigured = FALSE;
++
++ Adapter->HSCfg.conditions = HOST_SLEEP_CFG_CANCEL;
++ Adapter->HSCfg.gpio = 0;
++ Adapter->HSCfg.gap = 0;
++
++ Adapter->DataRate = 0; // Initially indicate the rate as auto
++
++ Adapter->adhoc_grate_enabled = FALSE;
++
++ Adapter->IntCounter = Adapter->IntCounterSaved = 0;
++
++ INIT_LIST_HEAD((struct list_head *) &Adapter->RxSkbQ);
++
++ Adapter->gen_null_pkg = TRUE; /*Enable NULL Pkg generation */
++
++ init_waitqueue_head(&Adapter->cmd_EncKey);
++
++ spin_lock_init(&Adapter->CurrentTxLock);
++
++ Adapter->CurrentTxSkb = NULL;
++ Adapter->PktTxCtrl = 0;
++
++ return;
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief This function initializes firmware
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_init_fw(wlan_private * priv)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ /* Allocate adapter structure */
++ if ((ret = wlan_allocate_adapter(priv)) != WLAN_STATUS_SUCCESS) {
++ goto done;
++ }
++
++ /* init adapter structure */
++ wlan_init_adapter(priv);
++
++ /* init timer etc. */
++ init_sync_objects(priv);
++
++ /* download fimrware etc. */
++ if ((ret = wlan_setup_station_hw(priv)) != WLAN_STATUS_SUCCESS) {
++ Adapter->HardwareStatus = WlanHardwareStatusNotReady;
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ /* init 802.11d */
++ wlan_init_11d(priv);
++
++ Adapter->HardwareStatus = WlanHardwareStatusReady;
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function frees the structure of adapter
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++void
++wlan_free_adapter(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!Adapter) {
++ PRINTM(INFO, "Why double free adapter?:)\n");
++ return;
++ }
++
++ PRINTM(INFO, "Free Command buffer\n");
++ FreeCmdBuffer(priv);
++
++ PRINTM(INFO, "Free CommandTimer\n");
++ if (Adapter->CommandTimerIsSet) {
++ CancelTimer(&Adapter->MrvDrvCommandTimer);
++ Adapter->CommandTimerIsSet = FALSE;
++ }
++ FreeTimer(&Adapter->MrvDrvCommandTimer);
++#ifdef REASSOCIATION
++ PRINTM(INFO, "Free MrvDrvTimer\n");
++ if (Adapter->ReassocTimerIsSet) {
++ CancelTimer(&Adapter->MrvDrvTimer);
++ Adapter->ReassocTimerIsSet = FALSE;
++ }
++ FreeTimer(&Adapter->MrvDrvTimer);
++#endif /* REASSOCIATION */
++
++ if (Adapter->bgScanConfig) {
++ kfree(Adapter->bgScanConfig);
++ Adapter->bgScanConfig = NULL;
++ }
++
++ OS_FREE_LOCK(&Adapter->CurrentTxLock);
++ OS_FREE_LOCK(&Adapter->QueueSpinLock);
++
++ PRINTM(INFO, "Free ScanTable\n");
++ if (Adapter->ScanTable) {
++ kfree(Adapter->ScanTable);
++ Adapter->ScanTable = NULL;
++ }
++
++ PRINTM(INFO, "Free Adapter\n");
++
++ /* Free the adapter object itself */
++ kfree(Adapter);
++ priv->adapter = NULL;
++ LEAVE();
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_join.c b/drivers/net/wireless/marvell8686/wlan_join.c
+new file mode 100644
+index 0000000..46d5961
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_join.c
+@@ -0,0 +1,2031 @@
++/** @file wlan_join.c
++ *
++ * @brief Functions implementing wlan infrastructure and adhoc join routines
++ *
++ * IOCTL handlers as well as command preperation and response routines
++ * for sending adhoc start, adhoc join, and association commands
++ * to the firmware.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ *
++ * @sa wlan_join.h
++ */
++/*************************************************************
++Change Log:
++ 01/11/06: Initial revision. Match new scan code, relocate related functions
++ 01/19/06: Fix failure to save adhoc ssid as current after adhoc start
++ 03/16/06: Add a semaphore to protect reassociation thread
++
++************************************************************/
++
++#include "include.h"
++
++/**
++ * @brief This function finds out the common rates between rate1 and rate2.
++ *
++ * It will fill common rates in rate1 as output if found.
++ *
++ * NOTE: Setting the MSB of the basic rates need to be taken
++ * care, either before or after calling this function
++ *
++ * @param Adapter A pointer to wlan_adapter structure
++ * @param rate1 the buffer which keeps input and output
++ * @param rate1_size the size of rate1 buffer
++ * @param rate2 the buffer which keeps rate2
++ * @param rate2_size the size of rate2 buffer.
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++get_common_rates(wlan_adapter * Adapter, u8 * rate1,
++ int rate1_size, u8 * rate2, int rate2_size)
++{
++ u8 *ptr = rate1;
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 *tmp = NULL;
++ int i, j;
++
++ if (!(tmp = kmalloc(rate1_size, GFP_KERNEL))) {
++ PRINTM(WARN, "Allocate buffer for common rates failed\n");
++ return -ENOMEM;
++ }
++
++ memcpy(tmp, rate1, rate1_size);
++ memset(rate1, 0, rate1_size);
++
++ for (i = 0; rate2[i] && i < rate2_size; i++) {
++ for (j = 0; tmp[j] && j < rate1_size; j++) {
++ /* Check common rate, excluding the bit for basic rate */
++ if ((rate2[i] & 0x7F) == (tmp[j] & 0x7F)) {
++ *rate1++ = tmp[j];
++ break;
++ }
++ }
++ }
++
++ HEXDUMP("rate1 (AP) Rates", tmp, rate1_size);
++ HEXDUMP("rate2 (Card) Rates", rate2, rate2_size);
++ HEXDUMP("Common Rates", ptr, rate1 - ptr);
++ PRINTM(INFO, "Tx DataRate is set to 0x%X\n", Adapter->DataRate);
++
++ if (!Adapter->Is_DataRate_Auto) {
++ while (*ptr) {
++ if ((*ptr & 0x7f) == Adapter->DataRate) {
++ ret = WLAN_STATUS_SUCCESS;
++ goto done;
++ }
++ ptr++;
++ }
++ PRINTM(MSG, "Previously set fixed data rate %#x isn't "
++ "compatible with the network.\n", Adapter->DataRate);
++
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ kfree(tmp);
++ return ret;
++}
++
++/**
++ * @brief Create the intersection of the rates supported by a target BSS and
++ * our Adapter settings for use in an assoc/join command.
++ *
++ * @param Adapter A pointer to wlan_adapter structure
++ * @param pBSSDesc BSS Descriptor whose rates are used in the setup
++ * @param pOutRates Output: Octet array of rates common between the BSS
++ * and the Adapter supported rates settings
++ * @param pOutRatesSize Output: Number of rates/octets set in pOutRates
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ *
++ */
++static int
++setup_rates_from_bssdesc(wlan_adapter * Adapter,
++ BSSDescriptor_t * pBSSDesc,
++ u8 * pOutRates, int *pOutRatesSize)
++{
++ u8 *card_rates;
++ int card_rates_size;
++
++ ENTER();
++
++ memcpy(pOutRates, pBSSDesc->SupportedRates, WLAN_SUPPORTED_RATES);
++
++ card_rates = SupportedRates;
++ card_rates_size = sizeof(SupportedRates);
++
++ if (get_common_rates(Adapter, pOutRates, WLAN_SUPPORTED_RATES,
++ card_rates, card_rates_size)) {
++ *pOutRatesSize = 0;
++ PRINTM(INFO, "get_common_rates failed\n");
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ *pOutRatesSize = MIN(strlen(pOutRates), WLAN_SUPPORTED_RATES);
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Retrieve the association response
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_get_assoc_rsp_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int copySize;
++
++ /*
++ * Set the amount to copy back to the application as the minimum of the
++ * available assoc resp data or the buffer provided by the application
++ */
++ copySize = MIN(Adapter->assocRspSize, wrq->u.data.length);
++
++ /* Copy the (re)association response back to the application */
++ if (copy_to_user(wrq->u.data.pointer, Adapter->assocRspBuffer, copySize)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ /* Returned copy length */
++ wrq->u.data.length = copySize;
++
++ /* Reset assoc buffer */
++ Adapter->assocRspSize = 0;
++
++ /* No error on return */
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set an opaque block of Marvell TLVs for insertion into the
++ * association command
++ *
++ * Pass an opaque block of data, expected to be Marvell TLVs, to the driver
++ * for eventual passthrough to the firmware in an associate/join
++ * (and potentially start) command.
++ *
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_set_mrvl_tlv_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ /* If the passed length is zero, reset the buffer */
++ if (wrq->u.data.length == 0) {
++ Adapter->mrvlAssocTlvBufferLen = 0;
++ } else {
++ /*
++ * Verify that the passed length is not larger than the available
++ * space remaining in the buffer
++ */
++ if (wrq->u.data.length < (sizeof(Adapter->mrvlAssocTlvBuffer)
++ - Adapter->mrvlAssocTlvBufferLen)) {
++ /* Append the passed data to the end of the mrvlAssocTlvBuffer */
++ if (copy_from_user(Adapter->mrvlAssocTlvBuffer
++ + Adapter->mrvlAssocTlvBufferLen,
++ wrq->u.data.pointer, wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ /* Increment the stored buffer length by the size passed */
++ Adapter->mrvlAssocTlvBufferLen += wrq->u.data.length;
++ } else {
++ /* Passed data does not fit in the remaining buffer space */
++ ret = WLAN_STATUS_FAILURE;
++ }
++ }
++
++ /* Return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE */
++ return ret;
++}
++
++/**
++ * @brief Stop Adhoc Network
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_do_adhocstop_ioctl(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (Adapter->InfrastructureMode == Wlan802_11IBSS &&
++ Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++
++ ret = StopAdhocNetwork(priv);
++
++ } else {
++ LEAVE();
++ return -ENOTSUPP;
++ }
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set essid
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param dwrq A pointer to iw_point structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS--success, otherwise--fail
++ */
++int
++wlan_set_essid(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ WLAN_802_11_SSID reqSSID;
++ int i;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ /* Clear any past association response stored for application retrieval */
++ Adapter->assocRspSize = 0;
++
++#ifdef REASSOCIATION
++ // cancel re-association timer if there's one
++ if (Adapter->ReassocTimerIsSet == TRUE) {
++ CancelTimer(&Adapter->MrvDrvTimer);
++ Adapter->ReassocTimerIsSet = FALSE;
++ }
++
++ if (OS_ACQ_SEMAPHORE_BLOCK(&Adapter->ReassocSem)) {
++ PRINTM(ERROR, "Acquire semaphore error, wlan_set_essid\n");
++ return -EBUSY;
++ }
++#endif /* REASSOCIATION */
++
++ /* Check the size of the string */
++ if (dwrq->length > IW_ESSID_MAX_SIZE + 1) {
++ ret = -E2BIG;
++ goto setessid_ret;
++ }
++
++ memset(&reqSSID, 0, sizeof(WLAN_802_11_SSID));
++
++ /*
++ * Check if we asked for `any' or 'particular'
++ */
++ if (!dwrq->flags) {
++ if (FindBestNetworkSsid(priv, &reqSSID)) {
++ PRINTM(INFO, "Could not find best network\n");
++ ret = WLAN_STATUS_SUCCESS;
++ goto setessid_ret;
++ }
++ } else {
++ /* Set the SSID */
++#if WIRELESS_EXT > 20
++ reqSSID.SsidLength = dwrq->length;
++#else
++ reqSSID.SsidLength = dwrq->length - 1;
++#endif
++ memcpy(reqSSID.Ssid, extra,
++ MIN(reqSSID.SsidLength, reqSSID.SsidLength));
++
++ }
++
++ PRINTM(INFO, "Requested new SSID = %s\n",
++ (reqSSID.SsidLength > 0) ? (char *) reqSSID.Ssid : "NULL");
++ if (!reqSSID.SsidLength || reqSSID.Ssid[0] < 0x20) {
++ PRINTM(INFO, "Invalid SSID - aborting set_essid\n");
++ ret = -EINVAL;
++ goto setessid_ret;
++ }
++
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure) {
++ /* infrastructure mode */
++ PRINTM(INFO, "SSID requested = %s\n", reqSSID.Ssid);
++
++ if ((dwrq->flags & IW_ENCODE_INDEX) > 1) {
++ i = (dwrq->flags & IW_ENCODE_INDEX) - 1; /* convert to 0 based */
++
++ PRINTM(INFO, "Request SSID by index = %d\n", i);
++
++ if (i > Adapter->NumInScanTable) {
++ /* Failed to find in table since index is > current max. */
++ i = -EINVAL;
++ }
++ } else {
++ SendSpecificSSIDScan(priv, &reqSSID);
++ i = FindSSIDInList(Adapter,
++ &reqSSID, NULL, Wlan802_11Infrastructure);
++ }
++
++ if (i >= 0) {
++ PRINTM(INFO, "SSID found in scan list ... associating...\n");
++
++ ret = wlan_associate(priv, &Adapter->ScanTable[i]);
++
++ if (ret) {
++ goto setessid_ret;
++ }
++ } else { /* i >= 0 */
++ ret = i; /* return -ENETUNREACH, passed from FindSSIDInList */
++ goto setessid_ret;
++ }
++ } else {
++ /* ad hoc mode */
++ /* If the requested SSID matches current SSID return */
++ if (!SSIDcmp(&Adapter->CurBssParams.BSSDescriptor.Ssid, &reqSSID)) {
++ ret = WLAN_STATUS_SUCCESS;
++ goto setessid_ret;
++ }
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ /*
++ * Exit Adhoc mode
++ */
++ PRINTM(INFO, "Sending Adhoc Stop\n");
++ ret = StopAdhocNetwork(priv);
++
++ if (ret) {
++ goto setessid_ret;
++ }
++ }
++ Adapter->AdhocLinkSensed = FALSE;
++
++ if ((dwrq->flags & IW_ENCODE_INDEX) > 1) {
++ i = (dwrq->flags & IW_ENCODE_INDEX) - 1; /* 0 based */
++ if (i > Adapter->NumInScanTable) {
++ /* Failed to find in table since index is > current max. */
++ i = -EINVAL;
++ }
++ } else {
++ /* Scan for the network */
++ SendSpecificSSIDScan(priv, &reqSSID);
++
++ /* Search for the requested SSID in the scan table */
++ i = FindSSIDInList(Adapter, &reqSSID, NULL, Wlan802_11IBSS);
++ }
++
++ if (i >= 0) {
++ PRINTM(INFO, "SSID found at %d in List, so join\n", i);
++ JoinAdhocNetwork(priv, &Adapter->ScanTable[i]);
++ } else {
++ /* else send START command */
++ PRINTM(INFO, "SSID not found in list, "
++ "so creating adhoc with ssid = %s\n", reqSSID.Ssid);
++
++ StartAdhocNetwork(priv, &reqSSID);
++ } /* end of else (START command) */
++ } /* end of else (Ad hoc mode) */
++
++ /*
++ * The MediaConnectStatus change can be removed later when
++ * the ret code is being properly returned.
++ */
++ /* Check to see if we successfully connected */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ ret = WLAN_STATUS_SUCCESS;
++ } else {
++ ret = -ENETDOWN;
++ }
++
++ setessid_ret:
++#ifdef REASSOCIATION
++ OS_REL_SEMAPHORE(&Adapter->ReassocSem);
++#endif
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Connect to the AP or Ad-hoc Network with specific bssid
++ *
++ * NOTE: Scan should be issued by application before this function is called
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param awrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_set_wap(struct net_device *dev, struct iw_request_info *info,
++ struct sockaddr *awrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ const u8 bcast[ETH_ALEN] = { 255, 255, 255, 255, 255, 255 };
++ u8 reqBSSID[ETH_ALEN];
++ int i;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ /* Clear any past association response stored for application retrieval */
++ Adapter->assocRspSize = 0;
++
++ if (awrq->sa_family != ARPHRD_ETHER)
++ return -EINVAL;
++
++ PRINTM(INFO, "ASSOC: WAP: sa_data: %02x:%02x:%02x:%02x:%02x:%02x\n",
++ (u8) awrq->sa_data[0], (u8) awrq->sa_data[1],
++ (u8) awrq->sa_data[2], (u8) awrq->sa_data[3],
++ (u8) awrq->sa_data[4], (u8) awrq->sa_data[5]);
++#ifdef REASSOCIATION
++ // cancel re-association timer if there's one
++ if (Adapter->ReassocTimerIsSet == TRUE) {
++ CancelTimer(&Adapter->MrvDrvTimer);
++ Adapter->ReassocTimerIsSet = FALSE;
++ }
++#endif /* REASSOCIATION */
++
++ if (!memcmp(bcast, awrq->sa_data, ETH_ALEN)) {
++ i = FindBestSSIDInList(Adapter);
++ } else {
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ if (memcmp
++ (awrq->sa_data,
++ Adapter->CurBssParams.BSSDescriptor.MacAddress,
++ ETH_ALEN) == 0)
++ return WLAN_STATUS_SUCCESS;
++ }
++ memcpy(reqBSSID, awrq->sa_data, ETH_ALEN);
++
++ PRINTM(INFO, "ASSOC: WAP: Bssid = %02x:%02x:%02x:%02x:%02x:%02x\n",
++ reqBSSID[0], reqBSSID[1], reqBSSID[2],
++ reqBSSID[3], reqBSSID[4], reqBSSID[5]);
++
++ /* Search for index position in list for requested MAC */
++ i = FindBSSIDInList(Adapter, reqBSSID, Adapter->InfrastructureMode);
++ }
++
++ if (i < 0) {
++ PRINTM(INFO, "ASSOC: WAP: MAC address not found in BSSID List\n");
++ return -ENETUNREACH;
++ }
++
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure) {
++
++ ret = wlan_associate(priv, &Adapter->ScanTable[i]);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ } else {
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ /* Exit Adhoc mode */
++ ret = StopAdhocNetwork(priv);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ }
++ Adapter->AdhocLinkSensed = FALSE;
++
++ JoinAdhocNetwork(priv, &Adapter->ScanTable[i]);
++ }
++
++ /* Check to see if we successfully connected */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ ret = WLAN_STATUS_SUCCESS;
++ } else {
++ ret = -ENETDOWN;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Associated to a specific BSS discovered in a scan
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pBSSDesc Pointer to the BSS descriptor to associate with.
++ *
++ * @return WLAN_STATUS_SUCCESS-success, otherwise fail
++ */
++int
++wlan_associate(wlan_private * priv, BSSDescriptor_t * pBSSDesc)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int enableData = TRUE;
++ union iwreq_data wrqu;
++ int ret;
++ IEEEtypes_AssocRsp_t *pAssocRsp;
++ u8 currentBSSID[MRVDRV_ETH_ADDR_LEN];
++ int reassocAttempt = FALSE;
++
++ ENTER();
++
++ /* Return error if the Adapter or table entry is not marked as infra */
++ if ((Adapter->InfrastructureMode != Wlan802_11Infrastructure)
++ || (pBSSDesc->InfrastructureMode != Wlan802_11Infrastructure)) {
++ LEAVE();
++ return -EINVAL;
++ }
++
++ memcpy(&currentBSSID,
++ &Adapter->CurBssParams.BSSDescriptor.MacAddress,
++ sizeof(currentBSSID));
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ reassocAttempt = TRUE;
++ PRINTM(INFO, "Attempting reassociation, stopping wmm queues\n");
++ wmm_stop_queue(priv);
++ }
++
++ /* Clear any past association response stored for application retrieval */
++ Adapter->assocRspSize = 0;
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_ASSOCIATE,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, pBSSDesc);
++
++ if (Adapter->wmm.enabled) {
++ /* Don't re-enable carrier until we get the WMM_GET_STATUS event */
++ enableData = FALSE;
++ } else {
++ /* Since WMM is not enabled, setup the queues with the defaults */
++ wmm_setup_queues(priv);
++ }
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++
++ if (reassocAttempt
++ && (memcmp(&currentBSSID,
++ &Adapter->CurBssParams.BSSDescriptor.MacAddress,
++ sizeof(currentBSSID)) == 0)) {
++
++ /* Reassociation attempt failed, still associated to old AP,
++ ** no need to wait for WMM notification to restart data
++ */
++ enableData = TRUE;
++ }
++ if (enableData) {
++ PRINTM(INFO, "Post association, re-enabling data flow\n");
++ wmm_start_queue(priv);
++ os_carrier_on(priv);
++ os_start_queue(priv);
++ }
++ } else {
++ PRINTM(INFO, "Post association, stopping data flow\n");
++ os_carrier_off(priv);
++ os_stop_queue(priv);
++ }
++
++ memcpy(wrqu.ap_addr.sa_data,
++ &Adapter->CurBssParams.BSSDescriptor.MacAddress, ETH_ALEN);
++ wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWAP, &wrqu, NULL);
++
++ pAssocRsp = (IEEEtypes_AssocRsp_t *) Adapter->assocRspBuffer;
++
++ if (ret || pAssocRsp->StatusCode) {
++ ret = -ENETUNREACH;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Associated to a specific indexed entry in the ScanTable
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param tableIdx Index into the ScanTable to associate to, index parameter
++ * base value is 1. No scanning is done before the
++ * association attempt.
++ *
++ * @return WLAN_STATUS_SUCCESS-success, otherwise fail
++ */
++int
++wlan_associate_to_table_idx(wlan_private * priv, int tableIdx)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret;
++
++ ENTER();
++
++#ifdef REASSOCIATION
++ if (OS_ACQ_SEMAPHORE_BLOCK(&Adapter->ReassocSem)) {
++ PRINTM(ERROR, "Acquire semaphore error\n");
++ return -EBUSY;
++ }
++#endif
++
++ PRINTM(INFO, "ASSOC: iwpriv: Index = %d, NumInScanTable = %d\n",
++ tableIdx, Adapter->NumInScanTable);
++
++ /* Check index in table, subtract 1 if within range and call association
++ * sub-function. ScanTable[] is 0 based, parameter is 1 based to
++ * conform with IW_ENCODE_INDEX flag parameter passing in iwconfig/iwlist
++ */
++ if (tableIdx && (tableIdx <= Adapter->NumInScanTable)) {
++ ret = wlan_associate(priv, &Adapter->ScanTable[tableIdx - 1]);
++ } else {
++ ret = -EINVAL;
++ }
++
++#ifdef REASSOCIATION
++ OS_REL_SEMAPHORE(&Adapter->ReassocSem);
++#endif
++ LEAVE();
++
++ return ret;
++}
++
++/**
++ * @brief Start an Adhoc Network
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param AdhocSSID The ssid of the Adhoc Network
++ * @return WLAN_STATUS_SUCCESS--success, WLAN_STATUS_FAILURE--fail
++ */
++int
++StartAdhocNetwork(wlan_private * priv, WLAN_802_11_SSID * AdhocSSID)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ Adapter->AdhocCreate = TRUE;
++
++ PRINTM(INFO, "Adhoc Channel = %d\n", Adapter->AdhocChannel);
++ PRINTM(INFO, "CurBssParams.channel = %d\n",
++ Adapter->CurBssParams.BSSDescriptor.Channel);
++ PRINTM(INFO, "CurBssParams.band = %d\n", Adapter->CurBssParams.band);
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_AD_HOC_START,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, AdhocSSID);
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Join an adhoc network found in a previous scan
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pBSSDesc Pointer to a BSS descriptor found in a previous scan
++ * to attempt to join
++ *
++ * @return WLAN_STATUS_SUCCESS--success, WLAN_STATUS_FAILURE--fail
++ */
++int
++JoinAdhocNetwork(wlan_private * priv, BSSDescriptor_t * pBSSDesc)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ PRINTM(INFO, "JoinAdhocNetwork: CurBss.ssid =%s\n",
++ Adapter->CurBssParams.BSSDescriptor.Ssid.Ssid);
++ PRINTM(INFO, "JoinAdhocNetwork: CurBss.ssid_len =%u\n",
++ Adapter->CurBssParams.BSSDescriptor.Ssid.SsidLength);
++ PRINTM(INFO, "JoinAdhocNetwork: ssid =%s\n", pBSSDesc->Ssid.Ssid);
++ PRINTM(INFO, "JoinAdhocNetwork: ssid len =%u\n",
++ pBSSDesc->Ssid.SsidLength);
++
++ /* check if the requested SSID is already joined */
++ if (Adapter->CurBssParams.BSSDescriptor.Ssid.SsidLength
++ && !SSIDcmp(&pBSSDesc->Ssid,
++ &Adapter->CurBssParams.BSSDescriptor.Ssid)
++ && (Adapter->CurBssParams.BSSDescriptor.InfrastructureMode ==
++ Wlan802_11IBSS)) {
++
++ PRINTM(INFO,
++ "ADHOC_J_CMD: New ad-hoc SSID is the same as current, "
++ "not attempting to re-join");
++
++ return WLAN_STATUS_FAILURE;
++ }
++
++ PRINTM(INFO, "CurBssParams.channel = %d\n",
++ Adapter->CurBssParams.BSSDescriptor.Channel);
++ PRINTM(INFO, "CurBssParams.band = %c\n", Adapter->CurBssParams.band);
++
++ Adapter->AdhocCreate = FALSE;
++
++ // store the SSID info temporarily
++ memset(&Adapter->AttemptedSSIDBeforeScan, 0, sizeof(WLAN_802_11_SSID));
++ memcpy(&Adapter->AttemptedSSIDBeforeScan,
++ &pBSSDesc->Ssid, sizeof(WLAN_802_11_SSID));
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_AD_HOC_JOIN,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, pBSSDesc);
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Stop the Adhoc Network
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS--success, WLAN_STATUS_FAILURE--fail
++ */
++int
++StopAdhocNetwork(wlan_private * priv)
++{
++ return PrepareAndSendCommand(priv, HostCmd_CMD_802_11_AD_HOC_STOP,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, NULL);
++}
++
++/**
++ * @brief Send Deauthentication Request
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS--success, WLAN_STATUS_FAILURE--fail
++ */
++int
++SendDeauthentication(wlan_private * priv)
++{
++ return PrepareAndSendCommand(priv, HostCmd_CMD_802_11_DEAUTHENTICATE,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, NULL);
++}
++
++/**
++ * @brief Set Idle Off
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlanidle_off(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ const u8 zeroMac[] = { 0, 0, 0, 0, 0, 0 };
++ int i;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateDisconnected) {
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure) {
++ if (memcmp(Adapter->PreviousBSSID, zeroMac, sizeof(zeroMac)) != 0) {
++
++ PRINTM(INFO, "Previous SSID = %s\n",
++ Adapter->PreviousSSID.Ssid);
++ PRINTM(INFO, "Previous BSSID = "
++ "%02x:%02x:%02x:%02x:%02x:%02x:\n",
++ Adapter->PreviousBSSID[0], Adapter->PreviousBSSID[1],
++ Adapter->PreviousBSSID[2], Adapter->PreviousBSSID[3],
++ Adapter->PreviousBSSID[4], Adapter->PreviousBSSID[5]);
++
++ i = FindSSIDInList(Adapter,
++ &Adapter->PreviousSSID,
++ Adapter->PreviousBSSID,
++ Adapter->InfrastructureMode);
++
++ if (i < 0) {
++ SendSpecificBSSIDScan(priv, Adapter->PreviousBSSID);
++ i = FindSSIDInList(Adapter,
++ &Adapter->PreviousSSID,
++ Adapter->PreviousBSSID,
++ Adapter->InfrastructureMode);
++ }
++
++ if (i < 0) {
++ /* If the BSSID could not be found, try just the SSID */
++ i = FindSSIDInList(Adapter,
++ &Adapter->PreviousSSID,
++ NULL, Adapter->InfrastructureMode);
++ }
++
++ if (i < 0) {
++ SendSpecificSSIDScan(priv, &Adapter->PreviousSSID);
++ i = FindSSIDInList(Adapter,
++ &Adapter->PreviousSSID,
++ NULL, Adapter->InfrastructureMode);
++ }
++
++ if (i >= 0) {
++ ret = wlan_associate(priv, &Adapter->ScanTable[i]);
++ }
++ }
++ } else if (Adapter->InfrastructureMode == Wlan802_11IBSS) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_AD_HOC_START,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, &Adapter->PreviousSSID);
++ }
++ }
++ /* else it is connected */
++
++ PRINTM(INFO, "\nwlanidle is off");
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set Idle On
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlanidle_on(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure) {
++ PRINTM(INFO, "Previous SSID = %s\n", Adapter->PreviousSSID.Ssid);
++ memcpy(&Adapter->PreviousSSID,
++ &Adapter->CurBssParams.BSSDescriptor.Ssid,
++ sizeof(WLAN_802_11_SSID));
++ SendDeauthentication(priv);
++
++ } else if (Adapter->InfrastructureMode == Wlan802_11IBSS) {
++ ret = StopAdhocNetwork(priv);
++ }
++
++ }
++#ifdef REASSOCIATION
++ if (Adapter->ReassocTimerIsSet == TRUE) {
++ CancelTimer(&Adapter->MrvDrvTimer);
++ Adapter->ReassocTimerIsSet = FALSE;
++ }
++#endif /* REASSOCIATION */
++
++ PRINTM(INFO, "\nwlanidle is on");
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Append a generic IE as a passthrough TLV to a TLV buffer.
++ *
++ * This function is called from the network join command prep. routine.
++ * If the IE buffer has been setup by the application, this routine appends
++ * the buffer as a passthrough TLV type to the request.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param ppBuffer pointer to command buffer pointer
++ *
++ * @return bytes added to the buffer
++ */
++static int
++wlan_cmd_append_generic_ie(wlan_private * priv, u8 ** ppBuffer)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int retLen = 0;
++ MrvlIEtypesHeader_t ieHeader;
++
++ /* Null Checks */
++ if (ppBuffer == 0)
++ return 0;
++ if (*ppBuffer == 0)
++ return 0;
++
++ /*
++ * If there is a generic ie buffer setup, append it to the return
++ * parameter buffer pointer.
++ */
++ if (Adapter->genIeBufferLen) {
++ PRINTM(INFO, "append generic %d to %p\n", Adapter->genIeBufferLen,
++ *ppBuffer);
++
++ /* Wrap the generic IE buffer with a passthrough TLV type */
++ ieHeader.Type = wlan_cpu_to_le16(TLV_TYPE_PASSTHROUGH);
++ ieHeader.Len = wlan_cpu_to_le16(Adapter->genIeBufferLen);
++ memcpy(*ppBuffer, &ieHeader, sizeof(ieHeader));
++
++ /* Increment the return size and the return buffer pointer param */
++ *ppBuffer += sizeof(ieHeader);
++ retLen += sizeof(ieHeader);
++
++ /* Copy the generic IE buffer to the output buffer, advance pointer */
++ memcpy(*ppBuffer, Adapter->genIeBuffer, Adapter->genIeBufferLen);
++
++ /* Increment the return size and the return buffer pointer param */
++ *ppBuffer += Adapter->genIeBufferLen;
++ retLen += Adapter->genIeBufferLen;
++
++ /* Reset the generic IE buffer */
++ Adapter->genIeBufferLen = 0;
++ }
++
++ /* return the length appended to the buffer */
++ return retLen;
++}
++
++/**
++ * @brief Append any application provided Marvell TLVs to a TLV buffer.
++ *
++ * This function is called from the network join command prep. routine.
++ * If the Marvell TLV buffer has been setup by the application, this routine
++ * appends the buffer to the request.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param ppBuffer pointer to command buffer pointer
++ *
++ * @return bytes added to the buffer
++ */
++static int
++wlan_cmd_append_marvell_tlv(wlan_private * priv, u8 ** ppBuffer)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int retLen = 0;
++
++ /* Null Checks */
++ if (ppBuffer == 0)
++ return 0;
++ if (*ppBuffer == 0)
++ return 0;
++
++ /*
++ * If there is a Marvell TLV buffer setup, append it to the return
++ * parameter buffer pointer.
++ */
++ if (Adapter->mrvlAssocTlvBufferLen) {
++ PRINTM(INFO, "append tlv %d to %p\n",
++ Adapter->mrvlAssocTlvBufferLen, *ppBuffer);
++
++ /* Copy the TLV buffer to the output buffer, advance pointer */
++ memcpy(*ppBuffer,
++ Adapter->mrvlAssocTlvBuffer, Adapter->mrvlAssocTlvBufferLen);
++
++ /* Increment the return size and the return buffer pointer param */
++ *ppBuffer += Adapter->mrvlAssocTlvBufferLen;
++ retLen += Adapter->mrvlAssocTlvBufferLen;
++
++ /* Reset the Marvell TLV buffer */
++ Adapter->mrvlAssocTlvBufferLen = 0;
++ }
++
++ /* return the length appended to the buffer */
++ return retLen;
++}
++
++/**
++ * @brief Append TSF tracking info from the scan table for the target AP
++ *
++ * This function is called from the network join command prep. routine.
++ * The TSF table TSF sent to the firmware contians two TSF values:
++ * - the TSF of the target AP from its previous beacon/probe response
++ * - the TSF timestamp of our local MAC at the time we observed the
++ * beacon/probe response.
++ *
++ * The firmware uses the timestamp values to set an initial TSF value
++ * in the MAC for the new association after a reassociation attempt.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param ppBuffer A pointer to command buffer pointer
++ * @param pBSSDesc A pointer to the BSS Descriptor from the scan table of
++ * the AP we are trying to join
++ *
++ * @return bytes added to the buffer
++ */
++static int
++wlan_cmd_append_tsf_tlv(wlan_private * priv, u8 ** ppBuffer,
++ BSSDescriptor_t * pBSSDesc)
++{
++ MrvlIEtypes_TsfTimestamp_t tsfTlv;
++ u64 tsfVal;
++
++ /* Null Checks */
++ if (ppBuffer == 0)
++ return 0;
++ if (*ppBuffer == 0)
++ return 0;
++
++ memset(&tsfTlv, 0x00, sizeof(MrvlIEtypes_TsfTimestamp_t));
++
++ tsfTlv.Header.Type = wlan_cpu_to_le16(TLV_TYPE_TSFTIMESTAMP);
++ tsfTlv.Header.Len = wlan_cpu_to_le16(2 * sizeof(tsfVal));
++
++ memcpy(*ppBuffer, &tsfTlv, sizeof(tsfTlv.Header));
++ *ppBuffer += sizeof(tsfTlv.Header);
++
++ /* TSF timestamp from the firmware TSF when the bcn/prb rsp was received */
++ tsfVal = wlan_cpu_to_le64(pBSSDesc->networkTSF);
++ memcpy(*ppBuffer, &tsfVal, sizeof(tsfVal));
++ *ppBuffer += sizeof(tsfVal);
++
++ memcpy(&tsfVal, pBSSDesc->TimeStamp, sizeof(tsfVal));
++
++ PRINTM(INFO, "ASSOC: TSF offset calc: %016llx - %016llx\n",
++ tsfVal, pBSSDesc->networkTSF);
++
++ tsfVal = wlan_cpu_to_le64(tsfVal);
++ memcpy(*ppBuffer, &tsfVal, sizeof(tsfVal));
++ *ppBuffer += sizeof(tsfVal);
++
++ return (sizeof(tsfTlv.Header) + (2 * sizeof(tsfVal)));
++}
++
++/**
++ * @brief This function prepares command of deauthenticate.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_802_11_deauthenticate(wlan_private * priv, HostCmd_DS_COMMAND * cmd)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_DEAUTHENTICATE *dauth = &cmd->params.deauth;
++
++ ENTER();
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_DEAUTHENTICATE);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_DEAUTHENTICATE) + S_DS_GEN);
++
++ /* set AP MAC address */
++ memcpy(dauth->MacAddr,
++ &Adapter->CurBssParams.BSSDescriptor.MacAddress, ETH_ALEN);
++
++ /* Reason code 3 = Station is leaving */
++#define REASON_CODE_STA_LEAVING 3
++ dauth->ReasonCode = wlan_cpu_to_le16(REASON_CODE_STA_LEAVING);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of association.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param pdata_buf Void cast of BSSDescriptor_t from the scan table to assoc
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_802_11_associate(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *pdata_buf)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_ASSOCIATE *pAsso = &cmd->params.associate;
++ int ret = WLAN_STATUS_SUCCESS;
++ BSSDescriptor_t *pBSSDesc;
++ WLAN_802_11_RATES rates;
++ int ratesSize;
++ u8 *pos;
++ u16 TmpCap;
++ MrvlIEtypes_SsIdParamSet_t *pSsidTlv;
++ MrvlIEtypes_PhyParamSet_t *pPhyTlv;
++ MrvlIEtypes_SsParamSet_t *pSsTlv;
++ MrvlIEtypes_RatesParamSet_t *pRatesTlv;
++ MrvlIEtypes_AuthType_t *pAuthTlv;
++ MrvlIEtypes_RsnParamSet_t *pRsnTlv;
++
++ ENTER();
++
++ pBSSDesc = (BSSDescriptor_t *) pdata_buf;
++ pos = (u8 *) pAsso;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_ASSOCIATE);
++
++ /* Save so we know which BSS Desc to use in the response handler */
++ Adapter->pAttemptedBSSDesc = pBSSDesc;
++
++ memcpy(pAsso->PeerStaAddr,
++ pBSSDesc->MacAddress, sizeof(pAsso->PeerStaAddr));
++ pos += sizeof(pAsso->PeerStaAddr);
++
++ /* set the listen interval */
++ pAsso->ListenInterval = wlan_cpu_to_le16(Adapter->ListenInterval);
++
++ pos += sizeof(pAsso->CapInfo);
++ pos += sizeof(pAsso->ListenInterval);
++ pos += sizeof(pAsso->Reserved1);
++
++ pSsidTlv = (MrvlIEtypes_SsIdParamSet_t *) pos;
++ pSsidTlv->Header.Type = wlan_cpu_to_le16(TLV_TYPE_SSID);
++ pSsidTlv->Header.Len = pBSSDesc->Ssid.SsidLength;
++ memcpy(pSsidTlv->SsId, pBSSDesc->Ssid.Ssid, pSsidTlv->Header.Len);
++ pos += sizeof(pSsidTlv->Header) + pSsidTlv->Header.Len;
++ pSsidTlv->Header.Len = wlan_cpu_to_le16(pSsidTlv->Header.Len);
++
++ pPhyTlv = (MrvlIEtypes_PhyParamSet_t *) pos;
++ pPhyTlv->Header.Type = wlan_cpu_to_le16(TLV_TYPE_PHY_DS);
++ pPhyTlv->Header.Len = sizeof(pPhyTlv->fh_ds.DsParamSet);
++ memcpy(&pPhyTlv->fh_ds.DsParamSet,
++ &pBSSDesc->PhyParamSet.DsParamSet.CurrentChan,
++ sizeof(pPhyTlv->fh_ds.DsParamSet));
++ pos += sizeof(pPhyTlv->Header) + pPhyTlv->Header.Len;
++ pPhyTlv->Header.Len = wlan_cpu_to_le16(pPhyTlv->Header.Len);
++
++ pSsTlv = (MrvlIEtypes_SsParamSet_t *) pos;
++ pSsTlv->Header.Type = wlan_cpu_to_le16(TLV_TYPE_CF);
++ pSsTlv->Header.Len = sizeof(pSsTlv->cf_ibss.CfParamSet);
++ pos += sizeof(pSsTlv->Header) + pSsTlv->Header.Len;
++ pSsTlv->Header.Len = wlan_cpu_to_le16(pSsTlv->Header.Len);
++
++ /* Get the common rates supported between the driver and the BSS Desc */
++ if (setup_rates_from_bssdesc(Adapter, pBSSDesc, rates, &ratesSize)) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Setup the Rates TLV in the association command */
++ pRatesTlv = (MrvlIEtypes_RatesParamSet_t *) pos;
++ pRatesTlv->Header.Type = wlan_cpu_to_le16(TLV_TYPE_RATES);
++ pRatesTlv->Header.Len = wlan_cpu_to_le16(ratesSize);
++ memcpy(pRatesTlv->Rates, rates, ratesSize);
++ pos += sizeof(pRatesTlv->Header) + ratesSize;
++ PRINTM(INFO, "ASSOC_CMD: Rates size = %d\n", ratesSize);
++
++ /* Add the Authentication type to be used for Auth frames if needed */
++ pAuthTlv = (MrvlIEtypes_AuthType_t *) pos;
++ pAuthTlv->Header.Type = wlan_cpu_to_le16(TLV_TYPE_AUTH_TYPE);
++ pAuthTlv->Header.Len = sizeof(pAuthTlv->AuthType);
++ pAuthTlv->AuthType = Adapter->SecInfo.AuthenticationMode;
++ pos += sizeof(pAuthTlv->Header) + pAuthTlv->Header.Len;
++ pAuthTlv->Header.Len = wlan_cpu_to_le16(pAuthTlv->Header.Len);
++
++ if (!Adapter->wps.SessionEnable) {
++ if (Adapter->SecInfo.WPAEnabled || Adapter->SecInfo.WPA2Enabled) {
++ pRsnTlv = (MrvlIEtypes_RsnParamSet_t *) pos;
++ pRsnTlv->Header.Type = (u16) Adapter->Wpa_ie[0]; /* WPA_IE or WPA2_IE */
++ pRsnTlv->Header.Type = pRsnTlv->Header.Type & 0x00FF;
++ pRsnTlv->Header.Type = wlan_cpu_to_le16(pRsnTlv->Header.Type);
++ pRsnTlv->Header.Len = (u16) Adapter->Wpa_ie[1];
++ pRsnTlv->Header.Len = pRsnTlv->Header.Len & 0x00FF;
++ if (pRsnTlv->Header.Len <= (sizeof(Adapter->Wpa_ie) - 2)) {
++ memcpy(pRsnTlv->RsnIE, &Adapter->Wpa_ie[2],
++ pRsnTlv->Header.Len);
++ } else {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ HEXDUMP("ASSOC_CMD: RSN IE", (u8 *) pRsnTlv,
++ sizeof(pRsnTlv->Header) + pRsnTlv->Header.Len);
++ pos += sizeof(pRsnTlv->Header) + pRsnTlv->Header.Len;
++ pRsnTlv->Header.Len = wlan_cpu_to_le16(pRsnTlv->Header.Len);
++ }
++ }
++
++ wlan_wmm_process_association_req(priv, &pos, &pBSSDesc->wmmIE);
++
++ wlan_cmd_append_generic_ie(priv, &pos);
++
++ wlan_cmd_append_marvell_tlv(priv, &pos);
++
++ wlan_cmd_append_tsf_tlv(priv, &pos, pBSSDesc);
++
++ if (wlan_create_dnld_countryinfo_11d(priv, 0)) {
++ PRINTM(INFO, "Dnld_countryinfo_11d failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ if (wlan_parse_dnld_countryinfo_11d(priv)) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ cmd->Size = wlan_cpu_to_le16((u16) (pos - (u8 *) pAsso) + S_DS_GEN);
++
++ /* set the Capability info at last */
++ memcpy(&TmpCap, &pBSSDesc->Cap, sizeof(pAsso->CapInfo));
++ TmpCap &= CAPINFO_MASK;
++ PRINTM(INFO, "ASSOC_CMD: TmpCap=%4X CAPINFO_MASK=%4X\n",
++ TmpCap, CAPINFO_MASK);
++ TmpCap = wlan_cpu_to_le16(TmpCap);
++ memcpy(&pAsso->CapInfo, &TmpCap, sizeof(pAsso->CapInfo));
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function prepares command of ad_hoc_start.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param pssid A pointer to WLAN_802_11_SSID structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_802_11_ad_hoc_start(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *pssid)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_AD_HOC_START *adhs = &cmd->params.ads;
++ int ret = WLAN_STATUS_SUCCESS;
++ int cmdAppendSize = 0;
++ int i;
++ u16 TmpCap;
++ BSSDescriptor_t *pBSSDesc;
++
++ ENTER();
++
++ if (!Adapter) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_AD_HOC_START);
++
++ pBSSDesc = &Adapter->CurBssParams.BSSDescriptor;
++ Adapter->pAttemptedBSSDesc = pBSSDesc;
++
++ /*
++ * Fill in the parameters for 2 data structures:
++ * 1. HostCmd_DS_802_11_AD_HOC_START Command
++ * 2. pBSSDesc
++ *
++ * Driver will fill up SSID, BSSType,IBSS param, Physical Param,
++ * probe delay, and Cap info.
++ *
++ * Firmware will fill up beacon period, Basic rates
++ * and operational rates.
++ */
++
++ memset(adhs->SSID, 0, MRVDRV_MAX_SSID_LENGTH);
++
++ memcpy(adhs->SSID, ((WLAN_802_11_SSID *) pssid)->Ssid,
++ ((WLAN_802_11_SSID *) pssid)->SsidLength);
++
++ PRINTM(INFO, "ADHOC_S_CMD: SSID = %s\n", adhs->SSID);
++
++ memset(pBSSDesc->Ssid.Ssid, 0, MRVDRV_MAX_SSID_LENGTH);
++ memcpy(pBSSDesc->Ssid.Ssid,
++ ((WLAN_802_11_SSID *) pssid)->Ssid,
++ ((WLAN_802_11_SSID *) pssid)->SsidLength);
++
++ pBSSDesc->Ssid.SsidLength = ((WLAN_802_11_SSID *) pssid)->SsidLength;
++
++ /* set the BSS type */
++ adhs->BSSType = HostCmd_BSS_TYPE_IBSS;
++ pBSSDesc->InfrastructureMode = Wlan802_11IBSS;
++ adhs->BeaconPeriod = wlan_cpu_to_le16(Adapter->BeaconPeriod);
++ pBSSDesc->BeaconPeriod = Adapter->BeaconPeriod;
++
++ /* set Physical param set */
++#define DS_PARA_IE_ID 3
++#define DS_PARA_IE_LEN 1
++
++ adhs->PhyParamSet.DsParamSet.ElementId = DS_PARA_IE_ID;
++ adhs->PhyParamSet.DsParamSet.Len = DS_PARA_IE_LEN;
++
++ if (!get_cfp_by_band_and_channel
++ (0, (u16) Adapter->AdhocChannel, Adapter->region_channel)) {
++ CHANNEL_FREQ_POWER *cfp;
++ cfp =
++ get_cfp_by_band_and_channel(0, FIRST_VALID_CHANNEL,
++ Adapter->region_channel);
++ if (cfp)
++ Adapter->AdhocChannel = cfp->Channel;
++ }
++
++ ASSERT(Adapter->AdhocChannel);
++
++ PRINTM(INFO, "ADHOC_S_CMD: Creating ADHOC on Channel %d\n",
++ Adapter->AdhocChannel);
++
++ Adapter->CurBssParams.BSSDescriptor.Channel = Adapter->AdhocChannel;
++
++ pBSSDesc->Channel = Adapter->AdhocChannel;
++ adhs->PhyParamSet.DsParamSet.CurrentChan = Adapter->AdhocChannel;
++
++ memcpy(&pBSSDesc->PhyParamSet,
++ &adhs->PhyParamSet, sizeof(IEEEtypes_PhyParamSet_t));
++
++ pBSSDesc->NetworkTypeInUse = Wlan802_11DS;
++
++ /* set IBSS param set */
++#define IBSS_PARA_IE_ID 6
++#define IBSS_PARA_IE_LEN 2
++
++ adhs->SsParamSet.IbssParamSet.ElementId = IBSS_PARA_IE_ID;
++ adhs->SsParamSet.IbssParamSet.Len = IBSS_PARA_IE_LEN;
++ adhs->SsParamSet.IbssParamSet.AtimWindow
++ = wlan_cpu_to_le16(Adapter->AtimWindow);
++ pBSSDesc->ATIMWindow = Adapter->AtimWindow;
++ memcpy(&pBSSDesc->SsParamSet,
++ &adhs->SsParamSet, sizeof(IEEEtypes_SsParamSet_t));
++
++ /* set Capability info */
++ adhs->Cap.Ess = 0;
++ adhs->Cap.Ibss = 1;
++ pBSSDesc->Cap.Ibss = 1;
++
++ /* set up privacy in pBSSDesc */
++ if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled
++ || Adapter->AdhocAESEnabled) {
++
++#define AD_HOC_CAP_PRIVACY_ON 1
++ PRINTM(INFO, "ADHOC_S_CMD: WEPStatus set, Privacy to WEP\n");
++ pBSSDesc->Privacy = Wlan802_11PrivFilter8021xWEP;
++ adhs->Cap.Privacy = AD_HOC_CAP_PRIVACY_ON;
++ } else {
++ PRINTM(INFO, "ADHOC_S_CMD: WEPStatus NOT set, Setting "
++ "Privacy to ACCEPT ALL\n");
++ pBSSDesc->Privacy = Wlan802_11PrivFilterAcceptAll;
++ }
++
++ memset(adhs->DataRate, 0, sizeof(adhs->DataRate));
++
++ if (Adapter->adhoc_grate_enabled == TRUE) {
++ memcpy(adhs->DataRate, AdhocRates_G,
++ MIN(sizeof(adhs->DataRate), sizeof(AdhocRates_G)));
++ if (Adapter->
++ CurrentPacketFilter & HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON) {
++ ret =
++ PrepareAndSendCommand(priv, HostCmd_CMD_MAC_CONTROL, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ &Adapter->CurrentPacketFilter);
++ if (ret) {
++ PRINTM(INFO, "ADHOC_S_CMD: G Protection config failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ }
++ } else {
++ memcpy(adhs->DataRate, AdhocRates_B,
++ MIN(sizeof(adhs->DataRate), sizeof(AdhocRates_B)));
++ }
++
++ /* Find the last non zero */
++ for (i = 0; i < sizeof(adhs->DataRate) && adhs->DataRate[i]; i++);
++
++ Adapter->CurBssParams.NumOfRates = i;
++
++ /* Copy the ad-hoc creating rates into Current BSS state structure */
++ memcpy(&Adapter->CurBssParams.DataRates,
++ &adhs->DataRate, Adapter->CurBssParams.NumOfRates);
++
++ PRINTM(INFO, "ADHOC_S_CMD: Rates=%02x %02x %02x %02x \n",
++ adhs->DataRate[0], adhs->DataRate[1],
++ adhs->DataRate[2], adhs->DataRate[3]);
++
++ PRINTM(INFO, "ADHOC_S_CMD: AD HOC Start command is ready\n");
++
++ if (wlan_create_dnld_countryinfo_11d(priv, Adapter->CurBssParams.band)) {
++ PRINTM(INFO, "ADHOC_S_CMD: dnld_countryinfo_11d failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_AD_HOC_START)
++ + S_DS_GEN + cmdAppendSize);
++
++ memcpy(&TmpCap, &adhs->Cap, sizeof(u16));
++ TmpCap = wlan_cpu_to_le16(TmpCap);
++ memcpy(&adhs->Cap, &TmpCap, sizeof(u16));
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function prepares command of ad_hoc_stop.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_802_11_ad_hoc_stop(wlan_private * priv, HostCmd_DS_COMMAND * cmd)
++{
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_AD_HOC_STOP);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_AD_HOC_STOP)
++ + S_DS_GEN);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of ad_hoc_join.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param pdata_buf Void cast of BSSDescriptor_t from the scan table to join
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_802_11_ad_hoc_join(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *pdata_buf)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_AD_HOC_JOIN *pAdHocJoin = &cmd->params.adj;
++ BSSDescriptor_t *pBSSDesc = (BSSDescriptor_t *) pdata_buf;
++ int cmdAppendSize = 0;
++ int ret = WLAN_STATUS_SUCCESS;
++ WLAN_802_11_RATES rates;
++ int ratesSize;
++ u16 TmpCap;
++ u16 CurrentPacketFilter;
++
++ ENTER();
++
++#define USE_G_PROTECTION 0x02
++ if (pBSSDesc->ERPFlags & USE_G_PROTECTION) {
++ CurrentPacketFilter =
++ Adapter->
++ CurrentPacketFilter | HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON;
++ ret =
++ PrepareAndSendCommand(priv, HostCmd_CMD_MAC_CONTROL, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ &CurrentPacketFilter);
++ if (ret) {
++ PRINTM(INFO, "ADHOC_S_CMD: G Protection config failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ }
++ Adapter->pAttemptedBSSDesc = pBSSDesc;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_AD_HOC_JOIN);
++
++ pAdHocJoin->BssDescriptor.BSSType = HostCmd_BSS_TYPE_IBSS;
++
++ pAdHocJoin->BssDescriptor.BeaconPeriod
++ = wlan_cpu_to_le16(pBSSDesc->BeaconPeriod);
++
++ memcpy(&pAdHocJoin->BssDescriptor.BSSID,
++ &pBSSDesc->MacAddress, MRVDRV_ETH_ADDR_LEN);
++
++ memcpy(&pAdHocJoin->BssDescriptor.SSID,
++ &pBSSDesc->Ssid.Ssid, pBSSDesc->Ssid.SsidLength);
++
++ memcpy(&pAdHocJoin->BssDescriptor.PhyParamSet,
++ &pBSSDesc->PhyParamSet, sizeof(IEEEtypes_PhyParamSet_t));
++
++ memcpy(&pAdHocJoin->BssDescriptor.SsParamSet,
++ &pBSSDesc->SsParamSet, sizeof(IEEEtypes_SsParamSet_t));
++
++ memcpy(&TmpCap, &pBSSDesc->Cap, sizeof(IEEEtypes_CapInfo_t));
++
++ TmpCap &= CAPINFO_MASK;
++
++ PRINTM(INFO, "ADHOC_J_CMD: TmpCap=%4X CAPINFO_MASK=%4X\n",
++ TmpCap, CAPINFO_MASK);
++ memcpy(&pAdHocJoin->BssDescriptor.Cap, &TmpCap,
++ sizeof(IEEEtypes_CapInfo_t));
++
++ /* information on BSSID descriptor passed to FW */
++ PRINTM(INFO,
++ "ADHOC_J_CMD: BSSID = %02x-%02x-%02x-%02x-%02x-%02x, SSID = %s\n",
++ pAdHocJoin->BssDescriptor.BSSID[0],
++ pAdHocJoin->BssDescriptor.BSSID[1],
++ pAdHocJoin->BssDescriptor.BSSID[2],
++ pAdHocJoin->BssDescriptor.BSSID[3],
++ pAdHocJoin->BssDescriptor.BSSID[4],
++ pAdHocJoin->BssDescriptor.BSSID[5],
++ pAdHocJoin->BssDescriptor.SSID);
++
++ /* Get the common rates supported between the driver and the BSS Desc */
++ if (setup_rates_from_bssdesc(Adapter, pBSSDesc, rates, &ratesSize)) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Copy Data Rates from the Rates recorded in scan response */
++ memset(pAdHocJoin->BssDescriptor.DataRates, 0,
++ sizeof(pAdHocJoin->BssDescriptor.DataRates));
++ memcpy(pAdHocJoin->BssDescriptor.DataRates, rates, ratesSize);
++
++ /* Copy the adhoc join rates into Current BSS state structure */
++ Adapter->CurBssParams.NumOfRates = ratesSize;
++ memcpy(&Adapter->CurBssParams.DataRates, rates, ratesSize);
++
++ /* Copy the channel information */
++ Adapter->CurBssParams.BSSDescriptor.Channel = pBSSDesc->Channel;
++
++ if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled
++ || Adapter->AdhocAESEnabled) {
++ pAdHocJoin->BssDescriptor.Cap.Privacy = AD_HOC_CAP_PRIVACY_ON;
++ }
++
++ if (Adapter->PSMode == Wlan802_11PowerModeMAX_PSP) {
++ /* wake up first */
++ WLAN_802_11_POWER_MODE LocalPSMode;
++
++ LocalPSMode = Wlan802_11PowerModeCAM;
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_PS_MODE,
++ HostCmd_ACT_GEN_SET, 0, 0, &LocalPSMode);
++
++ if (ret) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ }
++
++ if (wlan_create_dnld_countryinfo_11d(priv, 0)) {
++ PRINTM(INFO, "Dnld_countryinfo_11d failed\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ if (wlan_parse_dnld_countryinfo_11d(priv)) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_AD_HOC_JOIN)
++ + S_DS_GEN + cmdAppendSize);
++
++ memcpy(&TmpCap, &pAdHocJoin->BssDescriptor.Cap,
++ sizeof(IEEEtypes_CapInfo_t));
++ TmpCap = wlan_cpu_to_le16(TmpCap);
++
++ memcpy(&pAdHocJoin->BssDescriptor.Cap,
++ &TmpCap, sizeof(IEEEtypes_CapInfo_t));
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Association firmware command response handler
++ *
++ * The response buffer for the association command has the following
++ * memory layout.
++ *
++ * For cases where an association response was not received (indicated
++ * by the CapInfo and AId field):
++ *
++ * .------------------------------------------------------------.
++ * | Header(4 * sizeof(u16)): Standard command response hdr |
++ * .------------------------------------------------------------.
++ * | CapInfo/Error Return(u16): |
++ * | 0xFFFF(-1): Internal error |
++ * | 0xFFFE(-2): Authentication unhandled message |
++ * | 0xFFFD(-3): Authentication refused |
++ * | 0xFFFC(-4): Timeout waiting for AP response |
++ * .------------------------------------------------------------.
++ * | StatusCode(u16): |
++ * | If CapInfo is -1: |
++ * | An internal firmware failure prevented the |
++ * | command from being processed. The StatusCode |
++ * | will be set to 1. |
++ * | |
++ * | If CapInfo is -2: |
++ * | An authentication frame was received but was |
++ * | not handled by the firmware. IEEE Status |
++ * | code for the failure is returned. |
++ * | |
++ * | If CapInfo is -3: |
++ * | An authentication frame was received and the |
++ * | StatusCode is the IEEE Status reported in the |
++ * | response. |
++ * | |
++ * | If CapInfo is -4: |
++ * | (1) Association response timeout |
++ * | (2) Authentication response timeout |
++ * .------------------------------------------------------------.
++ * | AId(u16): 0xFFFF |
++ * .------------------------------------------------------------.
++ *
++ *
++ * For cases where an association response was received, the IEEE
++ * standard association response frame is returned:
++ *
++ * .------------------------------------------------------------.
++ * | Header(4 * sizeof(u16)): Standard command response hdr |
++ * .------------------------------------------------------------.
++ * | CapInfo(u16): IEEE Capability |
++ * .------------------------------------------------------------.
++ * | StatusCode(u16): IEEE Status Code |
++ * .------------------------------------------------------------.
++ * | AId(u16): IEEE Association ID |
++ * .------------------------------------------------------------.
++ * | IEEE IEs(variable): Any received IEs comprising the |
++ * | remaining portion of a received |
++ * | association response frame. |
++ * .------------------------------------------------------------.
++ *
++ * For simplistic handling, the StatusCode field can be used to determine
++ * an association success (0) or failure (non-zero).
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_ret_802_11_associate(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ IEEEtypes_AssocRsp_t *pAssocRsp;
++ BSSDescriptor_t *pBSSDesc;
++ WLAN_802_11_RATES rates;
++ int ratesSize;
++
++ ENTER();
++
++ pAssocRsp = (IEEEtypes_AssocRsp_t *) & resp->params;
++
++ HEXDUMP("ASSOC_RESP:", (void *) &resp->params,
++ wlan_le16_to_cpu(resp->Size) - S_DS_GEN);
++
++ Adapter->assocRspSize = MIN(wlan_le16_to_cpu(resp->Size) - S_DS_GEN,
++ sizeof(Adapter->assocRspBuffer));
++
++ memcpy(Adapter->assocRspBuffer, &resp->params, Adapter->assocRspSize);
++
++ if (pAssocRsp->StatusCode) {
++ priv->adapter->dbg.num_cmd_assoc_failure++;
++
++ PRINTM(CMND, "ASSOC_RESP: Association Failed, "
++ "status code = %d, error = %d\n",
++ pAssocRsp->StatusCode, *(short *) &pAssocRsp->Capability);
++ ret = WLAN_STATUS_FAILURE;
++
++ goto done;
++ }
++
++ /* Send a Media Connected event, according to the Spec */
++ Adapter->MediaConnectStatus = WlanMediaStateConnected;
++
++ /* Set the attempted BSSID Index to current */
++ pBSSDesc = Adapter->pAttemptedBSSDesc;
++
++ PRINTM(INFO, "ASSOC_RESP: %s\n", pBSSDesc->Ssid.Ssid);
++
++ /* Make a copy of current BSSID descriptor */
++ memcpy(&Adapter->CurBssParams.BSSDescriptor,
++ pBSSDesc, sizeof(BSSDescriptor_t));
++
++ /* update CurBssParams */
++ Adapter->CurBssParams.BSSDescriptor.Channel
++ = pBSSDesc->PhyParamSet.DsParamSet.CurrentChan;
++
++ if (setup_rates_from_bssdesc(Adapter, pBSSDesc, rates, &ratesSize)) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ /* Copy the infra. association rates into Current BSS state structure */
++ Adapter->CurBssParams.NumOfRates = ratesSize;
++ memcpy(&Adapter->CurBssParams.DataRates, rates, ratesSize);
++
++ /* Adjust the timestamps in the scan table to be relative to the newly
++ * associated AP's TSF
++ */
++ wlan_scan_update_tsf_timestamps(priv, pBSSDesc);
++
++ if (pBSSDesc->wmmIE.VendHdr.ElementId == WMM_IE) {
++ Adapter->CurBssParams.wmm_enabled = TRUE;
++ } else {
++ Adapter->CurBssParams.wmm_enabled = FALSE;
++ }
++
++ if (Adapter->wmm.required && Adapter->CurBssParams.wmm_enabled) {
++ Adapter->wmm.enabled = TRUE;
++ } else {
++ Adapter->wmm.enabled = FALSE;
++ }
++
++ Adapter->CurBssParams.wmm_uapsd_enabled = FALSE;
++
++ if (Adapter->wmm.enabled == TRUE) {
++ Adapter->CurBssParams.wmm_uapsd_enabled
++ = pBSSDesc->wmmIE.QoSInfo.QosUAPSD;
++ }
++
++ PRINTM(INFO, "ASSOC_RESP: CurrentPacketFilter is %x\n",
++ Adapter->CurrentPacketFilter);
++
++ if (Adapter->SecInfo.WPAEnabled || Adapter->SecInfo.WPA2Enabled)
++ Adapter->IsGTK_SET = FALSE;
++
++ Adapter->SNR[TYPE_RXPD][TYPE_AVG] = 0;
++ Adapter->NF[TYPE_RXPD][TYPE_AVG] = 0;
++
++ memset(Adapter->rawSNR, 0x00, sizeof(Adapter->rawSNR));
++ memset(Adapter->rawNF, 0x00, sizeof(Adapter->rawNF));
++ Adapter->nextSNRNF = 0;
++ Adapter->numSNRNF = 0;
++
++ priv->adapter->dbg.num_cmd_assoc_success++;
++
++ PRINTM(INFO, "ASSOC_RESP: Associated \n");
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function handles the command response of disassociate
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_ret_802_11_disassociate(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ ENTER();
++
++ priv->adapter->dbg.num_cmd_deauth++;
++ MacEventDisconnected(priv);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the command response of ad_hoc_start and
++ * ad_hoc_join
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_ret_802_11_ad_hoc(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ u16 Command = resp->Command;
++ u16 Result = resp->Result;
++ HostCmd_DS_802_11_AD_HOC_RESULT *pAdHocResult;
++ union iwreq_data wrqu;
++ BSSDescriptor_t *pBSSDesc;
++
++ ENTER();
++
++ pAdHocResult = &resp->params.result;
++
++ pBSSDesc = Adapter->pAttemptedBSSDesc;
++
++ /*
++ * Join result code 0 --> SUCCESS
++ */
++ if (Result) {
++ PRINTM(INFO, "ADHOC_RESP Failed\n");
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ MacEventDisconnected(priv);
++ }
++
++ memset(&Adapter->CurBssParams.BSSDescriptor,
++ 0x00, sizeof(Adapter->CurBssParams.BSSDescriptor));
++
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ /* Send a Media Connected event, according to the Spec */
++ Adapter->MediaConnectStatus = WlanMediaStateConnected;
++
++ if (Command == HostCmd_RET_802_11_AD_HOC_START) {
++ PRINTM(INFO, "ADHOC_S_RESP %s\n", pBSSDesc->Ssid.Ssid);
++
++ /* Update the created network descriptor with the new BSSID */
++ memcpy(pBSSDesc->MacAddress,
++ pAdHocResult->BSSID, MRVDRV_ETH_ADDR_LEN);
++ } else {
++ /*
++ * Now the join cmd should be successful
++ * If BSSID has changed use SSID to compare instead of BSSID
++ */
++ PRINTM(INFO, "ADHOC_J_RESP %s\n", pBSSDesc->Ssid.Ssid);
++
++ /* Make a copy of current BSSID descriptor, only needed for join since
++ * the current descriptor is already being used for adhoc start
++ */
++ memcpy(&Adapter->CurBssParams.BSSDescriptor,
++ pBSSDesc, sizeof(BSSDescriptor_t));
++ }
++
++ memset(&wrqu, 0, sizeof(wrqu));
++ memcpy(wrqu.ap_addr.sa_data,
++ &Adapter->CurBssParams.BSSDescriptor.MacAddress, ETH_ALEN);
++ wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWAP, &wrqu, NULL);
++
++ PRINTM(INFO, "ADHOC_RESP: Channel = %d\n", Adapter->AdhocChannel);
++ PRINTM(INFO, "ADHOC_RESP: BSSID = %02x:%02x:%02x:%02x:%02x:%02x\n",
++ Adapter->CurBssParams.BSSDescriptor.MacAddress[0],
++ Adapter->CurBssParams.BSSDescriptor.MacAddress[1],
++ Adapter->CurBssParams.BSSDescriptor.MacAddress[2],
++ Adapter->CurBssParams.BSSDescriptor.MacAddress[3],
++ Adapter->CurBssParams.BSSDescriptor.MacAddress[4],
++ Adapter->CurBssParams.BSSDescriptor.MacAddress[5]);
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function handles the command response of ad_hoc_stop
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_ret_802_11_ad_hoc_stop(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ ENTER();
++
++ MacEventDisconnected(priv);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++#ifdef REASSOCIATION
++/**
++ * @brief This function handles re-association. it is triggered
++ * by re-assoc timer.
++ *
++ * @param data A pointer to wlan_thread structure
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++wlan_reassociation_thread(void *data)
++{
++ wlan_thread *thread = data;
++ wlan_private *priv = thread->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ wait_queue_t wait;
++ int i;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ OS_INTERRUPT_SAVE_AREA;
++
++ ENTER();
++
++ wlan_activate_thread(thread);
++ init_waitqueue_entry(&wait, current);
++
++ current->flags |= PF_NOFREEZE;
++
++ for (;;) {
++ add_wait_queue(&thread->waitQ, &wait);
++ OS_SET_THREAD_STATE(TASK_INTERRUPTIBLE);
++
++ PRINTM(INFO, "Reassoc: Thread sleeping...\n");
++
++ schedule();
++
++ OS_SET_THREAD_STATE(TASK_RUNNING);
++ remove_wait_queue(&thread->waitQ, &wait);
++
++ if (Adapter->SurpriseRemoved) {
++ break;
++ }
++
++ if (kthread_should_stop()) {
++ break;
++ }
++
++ PRINTM(INFO, "Reassoc: Thread waking up...\n");
++
++ if (Adapter->InfrastructureMode != Wlan802_11Infrastructure ||
++ Adapter->HardwareStatus != WlanHardwareStatusReady) {
++ PRINTM(MSG, "Reassoc: mode or hardware status is not correct\n");
++ continue;
++ }
++
++ /* The semaphore is used to avoid reassociation thread and
++ wlan_set_scan/wlan_set_essid interrupting each other.
++ Reassociation should be disabled completely by application if
++ wlan_set_user_scan_ioctl/wlan_set_wap is used.
++ */
++ if (OS_ACQ_SEMAPHORE_BLOCK(&Adapter->ReassocSem)) {
++ PRINTM(ERROR, "Acquire semaphore error, reassociation thread\n");
++ goto settimer;
++ }
++
++ if (Adapter->MediaConnectStatus != WlanMediaStateDisconnected) {
++ OS_REL_SEMAPHORE(&Adapter->ReassocSem);
++ PRINTM(MSG, "Reassoc: Adapter->MediaConnectStatus is wrong\n");
++ continue;
++ }
++
++ PRINTM(INFO, "Reassoc: Required ESSID: %s\n",
++ Adapter->PreviousSSID.Ssid);
++
++ PRINTM(INFO, "Reassoc: Performing Active Scan @ %lu\n",
++ os_time_get());
++ SendSpecificSSIDScan(priv, &Adapter->PreviousSSID);
++
++ i = FindSSIDInList(Adapter,
++ &Adapter->PreviousSSID,
++ Adapter->PreviousBSSID,
++ Adapter->InfrastructureMode);
++
++ if (i < 0) {
++ /* If the SSID could not be found, try just the SSID */
++ i = FindSSIDInList(Adapter,
++ &Adapter->PreviousSSID,
++ NULL, Adapter->InfrastructureMode);
++ }
++
++ if (i >= 0) {
++ if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SET_WEP,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_ADD_WEP, NULL);
++ if (ret)
++ PRINTM(INFO, "Ressoc: Fail to set WEP KEY\n");
++ }
++ wlan_associate(priv, &Adapter->ScanTable[i]);
++ }
++
++ OS_REL_SEMAPHORE(&Adapter->ReassocSem);
++
++ settimer:
++ if (Adapter->MediaConnectStatus == WlanMediaStateDisconnected) {
++ PRINTM(INFO, "Reassoc: No AP found or assoc failed."
++ "Restarting re-assoc Timer @ %lu\n", os_time_get());
++
++ Adapter->ReassocTimerIsSet = TRUE;
++ ModTimer(&Adapter->MrvDrvTimer, MRVDRV_TIMER_10S);
++ }
++ }
++
++ wlan_deactivate_thread(thread);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function triggers re-association by waking up
++ * re-assoc thread.
++ *
++ * @param FunctionContext A pointer to FunctionContext
++ * @return n/a
++ */
++void
++MrvDrvReassocTimerFunction(void *FunctionContext)
++{
++ wlan_private *priv = (wlan_private *) FunctionContext;
++ wlan_adapter *Adapter = priv->adapter;
++ OS_INTERRUPT_SAVE_AREA;
++
++ ENTER();
++
++ PRINTM(INFO, "MrvDrvReassocTimer fired.\n");
++ Adapter->ReassocTimerIsSet = FALSE;
++ if (Adapter->PSState != PS_STATE_FULL_POWER) {
++ /* wait until Exit_PS command returns */
++ Adapter->ReassocTimerIsSet = TRUE;
++ ModTimer(&Adapter->MrvDrvTimer, MRVDRV_TIMER_1S);
++ PRINTM(INFO, "MrvDrvTimerFunction(PSState=%d) waiting"
++ "for Exit_PS done\n", Adapter->PSState);
++ LEAVE();
++ return;
++ }
++
++ PRINTM(INFO, "Waking Up the Reassoc Thread\n");
++
++ wake_up_interruptible(&priv->ReassocThread.waitQ);
++
++ LEAVE();
++ return;
++}
++#endif /* REASSOCIATION */
++
++int
++sendADHOCBSSIDQuery(wlan_private * priv)
++{
++ return PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_IBSS_COALESCING_STATUS,
++ HostCmd_ACT_GET, 0, 0, NULL);
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_join.h b/drivers/net/wireless/marvell8686/wlan_join.h
+new file mode 100644
+index 0000000..ffb944e
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_join.h
+@@ -0,0 +1,84 @@
++/** @file wlan_join.h
++ *
++ * @brief Interface for the wlan infrastructure and adhoc join routines
++ *
++ * Driver interface functions and type declarations for the join module
++ * implemented in wlan_join.c. Process all start/join requests for
++ * both adhoc and infrastructure networks
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ *
++ * @sa wlan_join.c
++ */
++/*************************************************************
++Change Log:
++ 01/11/06: Initial revision. Match new scan code, relocate related functions
++
++************************************************************/
++
++#ifndef _WLAN_JOIN_H
++#define _WLAN_JOIN_H
++
++//! Size of buffer allocated to store the association response from firmware
++#define MRVDRV_ASSOC_RSP_BUF_SIZE 500
++
++//! Size of buffer allocated to store IEs passed to firmware in the assoc req
++#define MRVDRV_GENIE_BUF_SIZE 256
++
++//! Size of buffer allocated to store TLVs passed to firmware in the assoc req
++#define MRVDRV_ASSOC_TLV_BUF_SIZE 256
++
++extern int wlan_cmd_802_11_authenticate(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ void *pdata_buf);
++extern int wlan_cmd_802_11_ad_hoc_join(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ void *pdata_buf);
++extern int wlan_cmd_802_11_ad_hoc_stop(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd);
++extern int wlan_cmd_802_11_ad_hoc_start(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ void *pssid);
++extern int wlan_cmd_802_11_deauthenticate(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd);
++extern int wlan_cmd_802_11_associate(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ void *pdata_buf);
++extern int wlan_ret_802_11_authenticate(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp);
++extern int wlan_ret_802_11_ad_hoc(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp);
++extern int wlan_ret_802_11_ad_hoc_stop(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp);
++extern int wlan_ret_802_11_disassociate(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp);
++extern int wlan_ret_802_11_associate(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp);
++
++extern int wlan_associate(wlan_private * priv, BSSDescriptor_t * pBSSDesc);
++extern int wlan_associate_to_table_idx(wlan_private * priv, int tableIdx);
++
++extern int wlanidle_on(wlan_private * priv);
++extern int wlanidle_off(wlan_private * priv);
++
++extern int wlan_do_adhocstop_ioctl(wlan_private * priv);
++extern int wlan_reassociation_thread(void *data);
++
++extern int StartAdhocNetwork(wlan_private * priv,
++ WLAN_802_11_SSID * AdhocSSID);
++extern int JoinAdhocNetwork(wlan_private * priv, BSSDescriptor_t * pBSSDesc);
++extern int StopAdhocNetwork(wlan_private * priv);
++extern int SendDeauthentication(wlan_private * priv);
++
++extern int wlan_do_adhocstop_ioctl(wlan_private * priv);
++extern int wlan_get_assoc_rsp_ioctl(wlan_private * priv, struct iwreq *wrq);
++extern int wlan_set_mrvl_tlv_ioctl(wlan_private * priv, struct iwreq *wrq);
++
++#ifdef __KERNEL__
++extern int wlan_set_wap(struct net_device *dev, struct iw_request_info *info,
++ struct sockaddr *awrq, char *extra);
++#endif
++
++extern int sendADHOCBSSIDQuery(wlan_private * priv);
++
++#endif
+diff --git a/drivers/net/wireless/marvell8686/wlan_main.c b/drivers/net/wireless/marvell8686/wlan_main.c
+new file mode 100644
+index 0000000..c938cee
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_main.c
+@@ -0,0 +1,1359 @@
++/** @file wlan_main.c
++ *
++ * @brief This file contains the major functions in WLAN
++ * driver. It includes init, exit, open, close and main
++ * thread etc..
++ *
++ */
++/**
++ * @mainpage M-WLAN Linux Driver
++ *
++ * @section overview_sec Overview
++ *
++ * The M-WLAN is a Linux reference driver for Marvell
++ * 802.11 (a/b/g) WLAN chipset.
++ *
++ * @section copyright_sec Copyright
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ *
++ */
++/********************************************************
++Change log:
++ 09/30/05: Add Doxygen format comments
++ 12/09/05: Add TX_QUEUE support
++ 01/05/06: Add kernel 2.6.x support
++ 01/11/06: Conditionalize new scan/join functions.
++ 01/12/06: Add TxLockFlag for UAPSD power save mode
++ and Proprietary Periodic sleep support
++********************************************************/
++
++#include "include.h"
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++#ifdef ENABLE_PM
++#define WLAN_PM_DRV_NAME "wlan_pm_drv"
++
++static int wlan_pm_suspend(struct device *pmdev, u32 state, u32 level);
++static int wlan_pm_resume(struct device *pmdev, u32 level);
++static void wlan_pm_release(struct device *pmdev);
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct device_driver wlan_pm_driver = {
++ .name = WLAN_PM_DRV_NAME,
++ .bus = &platform_bus_type,
++ .suspend = wlan_pm_suspend,
++ .resume = wlan_pm_resume,
++};
++
++/*! Device Definition for WLAN */
++static struct platform_device wlan_pm_platform_device = {
++ .name = WLAN_PM_DRV_NAME,
++ .id = 0,
++ .dev.release = wlan_pm_release,
++};
++#endif
++
++spinlock_t driver_lock = SPIN_LOCK_UNLOCKED;
++ulong driver_flags;
++
++#define WLAN_TX_PWR_DEFAULT 20 /*100mW */
++#define WLAN_TX_PWR_US_DEFAULT 20 /*100mW */
++#define WLAN_TX_PWR_JP_DEFAULT 16 /*50mW */
++#define WLAN_TX_PWR_FR_100MW 20 /*100mW */
++#define WLAN_TX_PWR_FR_10MW 10 /*10mW */
++#define WLAN_TX_PWR_EMEA_DEFAULT 20 /*100mW */
++
++/* Format { Channel, Frequency (MHz), MaxTxPower } */
++/* Band: 'B/G', Region: USA FCC/Canada IC */
++static CHANNEL_FREQ_POWER channel_freq_power_US_BG[] = {
++ {1, 2412, WLAN_TX_PWR_US_DEFAULT},
++ {2, 2417, WLAN_TX_PWR_US_DEFAULT},
++ {3, 2422, WLAN_TX_PWR_US_DEFAULT},
++ {4, 2427, WLAN_TX_PWR_US_DEFAULT},
++ {5, 2432, WLAN_TX_PWR_US_DEFAULT},
++ {6, 2437, WLAN_TX_PWR_US_DEFAULT},
++ {7, 2442, WLAN_TX_PWR_US_DEFAULT},
++ {8, 2447, WLAN_TX_PWR_US_DEFAULT},
++ {9, 2452, WLAN_TX_PWR_US_DEFAULT},
++ {10, 2457, WLAN_TX_PWR_US_DEFAULT},
++ {11, 2462, WLAN_TX_PWR_US_DEFAULT}
++};
++
++/* Band: 'B/G', Region: Europe ETSI */
++static CHANNEL_FREQ_POWER channel_freq_power_EU_BG[] = {
++ {1, 2412, WLAN_TX_PWR_EMEA_DEFAULT},
++ {2, 2417, WLAN_TX_PWR_EMEA_DEFAULT},
++ {3, 2422, WLAN_TX_PWR_EMEA_DEFAULT},
++ {4, 2427, WLAN_TX_PWR_EMEA_DEFAULT},
++ {5, 2432, WLAN_TX_PWR_EMEA_DEFAULT},
++ {6, 2437, WLAN_TX_PWR_EMEA_DEFAULT},
++ {7, 2442, WLAN_TX_PWR_EMEA_DEFAULT},
++ {8, 2447, WLAN_TX_PWR_EMEA_DEFAULT},
++ {9, 2452, WLAN_TX_PWR_EMEA_DEFAULT},
++ {10, 2457, WLAN_TX_PWR_EMEA_DEFAULT},
++ {11, 2462, WLAN_TX_PWR_EMEA_DEFAULT},
++ {12, 2467, WLAN_TX_PWR_EMEA_DEFAULT},
++ {13, 2472, WLAN_TX_PWR_EMEA_DEFAULT}
++};
++
++/* Band: 'B/G', Region: France */
++static CHANNEL_FREQ_POWER channel_freq_power_FR_BG[] = {
++ {1, 2412, WLAN_TX_PWR_FR_100MW},
++ {2, 2417, WLAN_TX_PWR_FR_100MW},
++ {3, 2422, WLAN_TX_PWR_FR_100MW},
++ {4, 2427, WLAN_TX_PWR_FR_100MW},
++ {5, 2432, WLAN_TX_PWR_FR_100MW},
++ {6, 2437, WLAN_TX_PWR_FR_100MW},
++ {7, 2442, WLAN_TX_PWR_FR_100MW},
++ {8, 2447, WLAN_TX_PWR_FR_100MW},
++ {9, 2452, WLAN_TX_PWR_FR_100MW},
++ {10, 2457, WLAN_TX_PWR_FR_10MW},
++ {11, 2462, WLAN_TX_PWR_FR_10MW},
++ {12, 2467, WLAN_TX_PWR_FR_10MW},
++ {13, 2472, WLAN_TX_PWR_FR_10MW}
++};
++
++/* Band: 'B/G', Region: Japan */
++static CHANNEL_FREQ_POWER channel_freq_power_JPN41_BG[] = {
++ {1, 2412, WLAN_TX_PWR_JP_DEFAULT},
++ {2, 2417, WLAN_TX_PWR_JP_DEFAULT},
++ {3, 2422, WLAN_TX_PWR_JP_DEFAULT},
++ {4, 2427, WLAN_TX_PWR_JP_DEFAULT},
++ {5, 2432, WLAN_TX_PWR_JP_DEFAULT},
++ {6, 2437, WLAN_TX_PWR_JP_DEFAULT},
++ {7, 2442, WLAN_TX_PWR_JP_DEFAULT},
++ {8, 2447, WLAN_TX_PWR_JP_DEFAULT},
++ {9, 2452, WLAN_TX_PWR_JP_DEFAULT},
++ {10, 2457, WLAN_TX_PWR_JP_DEFAULT},
++ {11, 2462, WLAN_TX_PWR_JP_DEFAULT},
++ {12, 2467, WLAN_TX_PWR_JP_DEFAULT},
++ {13, 2472, WLAN_TX_PWR_JP_DEFAULT}
++};
++
++/* Band: 'B/G', Region: Japan */
++static CHANNEL_FREQ_POWER channel_freq_power_JPN40_BG[] = {
++ {14, 2484, WLAN_TX_PWR_JP_DEFAULT}
++};
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/**
++ * the structure for channel, frequency and power
++ */
++typedef struct _region_cfp_table
++{
++ u8 region;
++ CHANNEL_FREQ_POWER *cfp_BG;
++ int cfp_no_BG;
++} region_cfp_table_t;
++
++/**
++ * the structure for the mapping between region and CFP
++ */
++region_cfp_table_t region_cfp_table[] = {
++ {0x10, /*US FCC */
++ channel_freq_power_US_BG,
++ sizeof(channel_freq_power_US_BG) / sizeof(CHANNEL_FREQ_POWER),
++ }
++ ,
++ {0x20, /*CANADA IC */
++ channel_freq_power_US_BG,
++ sizeof(channel_freq_power_US_BG) / sizeof(CHANNEL_FREQ_POWER),
++ }
++ ,
++ {0x30, /*EU*/ channel_freq_power_EU_BG,
++ sizeof(channel_freq_power_EU_BG) / sizeof(CHANNEL_FREQ_POWER),
++ }
++ ,
++ {0x32, /*FRANCE*/ channel_freq_power_FR_BG,
++ sizeof(channel_freq_power_FR_BG) / sizeof(CHANNEL_FREQ_POWER),
++ }
++ ,
++ {0x40, /*JAPAN*/ channel_freq_power_JPN40_BG,
++ sizeof(channel_freq_power_JPN40_BG) / sizeof(CHANNEL_FREQ_POWER),
++ }
++ ,
++ {0x41, /*JAPAN*/ channel_freq_power_JPN41_BG,
++ sizeof(channel_freq_power_JPN41_BG) / sizeof(CHANNEL_FREQ_POWER),
++ }
++ ,
++/*Add new region here */
++};
++
++/**
++ * the rates supported by the card
++ */
++u8 WlanDataRates[WLAN_SUPPORTED_RATES] =
++ { 0x02, 0x04, 0x0B, 0x16, 0x00, 0x0C, 0x12,
++ 0x18, 0x24, 0x30, 0x48, 0x60, 0x6C, 0x00
++};
++
++/**
++ * the rates supported
++ */
++u8 SupportedRates[G_SUPPORTED_RATES] =
++ { 0x82, 0x84, 0x8b, 0x96, 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48,
++ 0x60, 0x6c, 0
++};
++
++/**
++ * the rates supported for ad-hoc G mode
++ */
++u8 AdhocRates_G[G_SUPPORTED_RATES] =
++ { 0x82, 0x84, 0x8b, 0x96, 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c,
++0 };
++
++/**
++ * the rates supported for ad-hoc B mode
++ */
++u8 AdhocRates_B[4] = { 0x82, 0x84, 0x8b, 0x96 };
++
++/**
++ * the global variable of a pointer to wlan_private
++ * structure variable
++ */
++wlan_private *wlanpriv = NULL;
++
++u32 DSFreqList[15] = {
++ 0, 2412000, 2417000, 2422000, 2427000, 2432000, 2437000, 2442000,
++ 2447000, 2452000, 2457000, 2462000, 2467000, 2472000, 2484000
++};
++
++/**
++ * the table to keep region code
++ */
++u16 RegionCodeToIndex[MRVDRV_MAX_REGION_CODE] =
++ { 0x10, 0x20, 0x30, 0x32, 0x40, 0x41 };
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function opens the network device
++ *
++ * @param dev A pointer to net_device structure
++ * @return WLAN_STATUS_SUCCESS
++ */
++static int
++wlan_open(struct net_device *dev)
++{
++ wlan_private *priv = (wlan_private *) dev->priv;
++ wlan_adapter *adapter = priv->adapter;
++
++ ENTER();
++
++ MODULE_GET;
++
++ priv->open = TRUE;
++
++ if ((adapter->MediaConnectStatus == WlanMediaStateConnected)
++ && (adapter->InfrastructureMode != Wlan802_11IBSS
++ || adapter->AdhocLinkSensed == TRUE))
++ os_carrier_on(priv);
++ else
++ os_carrier_off(priv);
++
++ os_start_queue(priv);
++ wmm_start_queue(priv);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function closes the network device
++ *
++ * @param dev A pointer to net_device structure
++ * @return WLAN_STATUS_SUCCESS
++ */
++static int
++wlan_close(struct net_device *dev)
++{
++ wlan_private *priv = dev->priv;
++
++ ENTER();
++
++ if (priv->adapter)
++ wlan_clean_txrx(priv);
++
++ MODULE_PUT;
++
++ priv->open = FALSE;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++#ifdef ENABLE_PM
++/**
++ * @brief
++ * This function is called to put the SDHC in a low power state. Refer to the
++ * document driver-model/driver.txt in the kernel source tree for more
++ * information.
++ *
++ * @param dev the device structure used to give information on which SDHC
++ * to suspend
++ * @param state the power state the device is entering
++ * @param level the stage in device suspension process that we want the
++ * device to be put in
++ *
++ * @return 0 : go to sleep mode
++ * -1 : do not accept to go to sleep mode.
++ */
++static int
++wlan_pm_suspend(struct device *pmdev, u32 state, u32 level)
++{
++ wlan_private *priv = wlanpriv;
++ wlan_adapter *Adapter = priv->adapter;
++ struct net_device *dev = priv->wlan_dev.netdev;
++
++ switch (level) {
++
++ case SUSPEND_DISABLE:
++ PRINTM(INFO, "WIFI_PM_SUSPEND_CALLBACK: enter SUSPEND_DISABLE.\n");
++
++ /* in associated mode : check that chipset is in IEEE PS and well configured to wake up the host if needed */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ if ((Adapter->PSState != PS_STATE_SLEEP)
++ || (!Adapter->bWakeupDevRequired)
++ || (Adapter->WakeupTries != 0)) {
++ PRINTM(INFO, "WIFI_PM_SUSPEND_CALLBACK: can't enter sleep mode because \
++ PSstate=%d, bWakeupDevRequired=%d, wakeupTries=%d\n",
++ Adapter->PSState, Adapter->bWakeupDevRequired, Adapter->WakeupTries);
++ return WLAN_STATUS_FAILURE;
++ }
++
++ else {
++
++ /*
++ * Detach the network interface
++ * if the network is running
++ */
++ if (netif_running(dev)) {
++ netif_device_detach(dev);
++ PRINTM(INFO, "netif_device_detach().\n");
++ }
++ /* Stop bus clock */
++ sbi_set_bus_clock(priv, FALSE);
++ }
++ }
++
++ /* in non associated mode : check that chipset is in Deepsleep mode */
++ else {
++ if (Adapter->IsDeepSleep == FALSE) {
++ PRINTM(INFO,
++ "WIFI_PM_SUSPEND_CALLBACK: No allowed to enter sleep while in FW in full power.\n");
++ return WLAN_STATUS_FAILURE;
++ }
++ /*
++ * Detach the network interface
++ * if the network is running
++ */
++ if (netif_running(dev)) {
++ netif_device_detach(dev);
++ }
++ }
++ break;
++
++ case SUSPEND_SAVE_STATE:
++
++ PRINTM(INFO, "WIFI_PM_SUSPEND_CALLBACK: enter SUSPEND_SAVE_STATE.\n");
++ /* Save bus state to restore it when waking up */
++ sbi_suspend(priv);
++
++ break;
++
++ case SUSPEND_POWER_DOWN:
++
++ PRINTM(INFO, "WIFI_PM_SUSPEND_CALLBACK: enter SUSPEND_POWER_DOWN.\n");
++ /* nothing to do */
++ break;
++
++ default:
++
++ break;
++
++ }
++
++ return WLAN_STATUS_SUCCESS;
++
++}
++
++/**
++ * @brief
++ * This function is called to bring the SDHC back from a low power state. Refer
++ * to the document driver-model/driver.txt in the kernel source tree for more
++ * information.
++ *
++ * @param dev the device structure used to give information on which SDHC
++ * to resume
++ * @param level the stage in device resumption process that we want the
++ * device to be put in
++ *
++ * @return The function always returns 0.
++ */
++static int
++wlan_pm_resume(struct device *pmdev, u32 level)
++{
++ wlan_private *priv = wlanpriv;
++ wlan_adapter *Adapter = priv->adapter;
++ struct net_device *dev = priv->wlan_dev.netdev;
++
++ switch (level) {
++
++ case RESUME_POWER_ON:
++
++ PRINTM(INFO, "WIFI_PM_RESUME_CALLBACK: enter RESUME_POWER_ON.\n");
++ /* nothing to do */
++ break;
++
++ case RESUME_RESTORE_STATE:
++
++ PRINTM(INFO,
++ "WIFI_PM_RESUME_CALLBACK: enter RESUME_RESTORE_STATE.\n");
++ /* Restore bus state */
++ sbi_resume(priv);
++ break;
++
++ case RESUME_ENABLE:
++
++ PRINTM(INFO, "WIFI_PM_RESUME_CALLBACK: enter RESUME_ENABLE.\n");
++
++ /* in associated mode */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++
++ if (Adapter->bWakeupDevRequired == FALSE) {
++ /* could never happen */
++ PRINTM(MSG, "WIFI_PM_RESUME_CALLBACK: serious error.\n");
++ } else {
++ /*
++ * Start bus clock
++ */
++ sbi_set_bus_clock(priv, TRUE);
++ /*
++ * Attach the network interface
++ * if the network is running
++ */
++ if (netif_running(dev)) {
++ netif_device_attach(dev);
++ PRINTM(INFO, "WIFI_PM : after netif_device_attach().\n");
++ }
++ PRINTM(INFO,
++ "WIFI_PM : After netif attach, in associated mode.\n");
++ }
++ }
++
++ /* in non associated mode */
++ else {
++ if (netif_running(dev)) {
++ netif_device_attach(dev);
++ }
++
++ PRINTM(INFO,
++ "WIFI_PM : after netif attach, in NON associated mode.\n");
++ }
++ break;
++
++ default:
++ break;
++
++ }
++ return WLAN_STATUS_SUCCESS;
++
++}
++
++/**
++ * @brief
++ * Dummy function to be compliant with Linux Power Management framework.
++ *
++ * @param pmdev the device structure used to give information on which SDHC
++ * to use
++ *
++ * @return None.
++ */
++static void
++wlan_pm_release(struct device *pmdev)
++{
++ PRINTM(INFO, "WIFI_PM_DRIVER : Into pm_device release function\n");
++ return;
++}
++
++#endif /* ENABLE_PM */
++
++/**
++ * @brief This function handles packet transmission
++ *
++ * @param skb A pointer to sk_buff structure
++ * @param dev A pointer to net_device structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ int ret;
++ wlan_private *priv = dev->priv;
++
++ ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ PRINTM(DATA, "Data <= kernel\n");
++
++ if (wlan_tx_packet(priv, skb)) {
++ /* Transmit failed */
++ ret = WLAN_STATUS_FAILURE;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function handles the timeout of packet
++ * transmission
++ *
++ * @param dev A pointer to net_device structure
++ * @return n/a
++ */
++static void
++wlan_tx_timeout(struct net_device *dev)
++{
++ wlan_private *priv = (wlan_private *) dev->priv;
++
++ ENTER();
++
++ PRINTM(DATA, "Tx timeout\n");
++ UpdateTransStart(dev);
++
++ priv->adapter->dbg.num_tx_timeout++;
++
++ priv->adapter->IntCounter++;
++ wake_up_interruptible(&priv->MainThread.waitQ);
++
++ LEAVE();
++}
++
++/**
++ * @brief This function returns the network statistics
++ *
++ * @param dev A pointer to wlan_private structure
++ * @return A pointer to net_device_stats structure
++ */
++static struct net_device_stats *
++wlan_get_stats(struct net_device *dev)
++{
++ wlan_private *priv = (wlan_private *) dev->priv;
++
++ return &priv->stats;
++}
++
++/**
++ * @brief This function sets the MAC address to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pRxPD A pointer to RxPD structure of received packet
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++wlan_set_mac_address(struct net_device *dev, void *addr)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = (wlan_private *) dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ struct sockaddr *pHwAddr = (struct sockaddr *) addr;
++
++ ENTER();
++
++ memset(Adapter->CurrentAddr, 0, MRVDRV_ETH_ADDR_LEN);
++
++ /* dev->dev_addr is 8 bytes */
++ HEXDUMP("dev->dev_addr:", dev->dev_addr, ETH_ALEN);
++
++ HEXDUMP("addr:", pHwAddr->sa_data, ETH_ALEN);
++ memcpy(Adapter->CurrentAddr, pHwAddr->sa_data, ETH_ALEN);
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_MAC_ADDRESS,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ if (ret) {
++ PRINTM(INFO, "set mac address failed.\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ HEXDUMP("Adapter->MacAddr:", Adapter->CurrentAddr, ETH_ALEN);
++ memcpy(dev->dev_addr, Adapter->CurrentAddr, ETH_ALEN);
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function sets multicast addresses to firmware
++ *
++ * @param dev A pointer to net_device structure
++ * @return n/a
++ */
++static void
++wlan_set_multicast_list(struct net_device *dev)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int OldPacketFilter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ OldPacketFilter = Adapter->CurrentPacketFilter;
++
++ if (dev->flags & IFF_PROMISC) {
++ PRINTM(INFO, "Enable Promiscuous mode\n");
++ Adapter->CurrentPacketFilter |= HostCmd_ACT_MAC_PROMISCUOUS_ENABLE;
++ Adapter->CurrentPacketFilter &= ~HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE;
++ } else {
++ /* Multicast */
++ Adapter->CurrentPacketFilter &= ~HostCmd_ACT_MAC_PROMISCUOUS_ENABLE;
++
++ if (dev->flags & IFF_ALLMULTI || dev->mc_count >
++ MRVDRV_MAX_MULTICAST_LIST_SIZE) {
++ PRINTM(INFO, "Enabling All Multicast!\n");
++ Adapter->CurrentPacketFilter |=
++ HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE;
++ } else {
++ Adapter->CurrentPacketFilter &=
++ ~HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE;
++
++ if (!dev->mc_count) {
++ PRINTM(INFO, "No multicast addresses - "
++ "disabling multicast!\n");
++
++ } else {
++ int i;
++
++ Adapter->NumOfMulticastMACAddr =
++ CopyMulticastAddrs(Adapter, dev);
++
++ PRINTM(INFO, "Multicast addresses: %d\n", dev->mc_count);
++
++ for (i = 0; i < dev->mc_count; i++) {
++ PRINTM(INFO, "Multicast address %d:"
++ "%x %x %x %x %x %x\n", i,
++ Adapter->MulticastList[i][0],
++ Adapter->MulticastList[i][1],
++ Adapter->MulticastList[i][2],
++ Adapter->MulticastList[i][3],
++ Adapter->MulticastList[i][4],
++ Adapter->MulticastList[i][5]);
++ }
++ /* set multicast addresses to firmware */
++ ret =
++ PrepareAndSendCommand(priv, HostCmd_CMD_MAC_MULTICAST_ADR,
++ HostCmd_ACT_GEN_SET, 0, 0, NULL);
++ }
++ }
++ }
++
++ if (Adapter->CurrentPacketFilter != OldPacketFilter) {
++ if (ret == WLAN_STATUS_SUCCESS)
++ PrepareAndSendCommand(priv,
++ HostCmd_CMD_MAC_CONTROL,
++ 0, 0, 0, &Adapter->CurrentPacketFilter);
++ }
++
++ LEAVE();
++}
++
++/**
++ * @brief This function pops rx_skb from the rx queue.
++ *
++ * @param RxSkbQ A pointer to rx_skb queue
++ * @return A pointer to skb
++ */
++static struct sk_buff *
++wlan_pop_rx_skb(struct sk_buff *RxSkbQ)
++{
++ struct sk_buff *skb_data = NULL;
++
++ if (!list_empty((struct list_head *) RxSkbQ)) {
++ skb_data = RxSkbQ->next;
++ list_del((struct list_head *) RxSkbQ->next);
++ }
++
++ return skb_data;
++}
++
++/**
++ * @brief This function hanldes the major job in WLAN driver.
++ * it handles the event generated by firmware, rx data received
++ * from firmware and tx data sent from kernel.
++ *
++ * @param data A pointer to wlan_thread structure
++ * @return WLAN_STATUS_SUCCESS
++ */
++static int
++wlan_service_main_thread(void *data)
++{
++ wlan_thread *thread = data;
++ wlan_private *priv = thread->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ wait_queue_t wait;
++ u8 ireg = 0;
++ u8 runCmd = 1;
++
++ OS_INTERRUPT_SAVE_AREA;
++
++ ENTER();
++
++ wlan_activate_thread(thread);
++
++ init_waitqueue_entry(&wait, current);
++
++ current->flags |= PF_NOFREEZE;
++
++ wmm_init(priv);
++
++ for (;;) {
++ add_wait_queue(&thread->waitQ, &wait);
++ OS_SET_THREAD_STATE(TASK_INTERRUPTIBLE);
++
++ runCmd = 1;
++ TX_DISABLE;
++
++ if ((Adapter->WakeupTries) ||
++ (Adapter->PSState == PS_STATE_SLEEP
++ && !Adapter->bWakeupDevRequired) ||
++ (!Adapter->IntCounter &&
++ Adapter->PSState == PS_STATE_PRE_SLEEP) ||
++ (!Adapter->IntCounter
++ && (priv->wlan_dev.dnld_sent || Adapter->TxLockFlag
++ || wmm_lists_empty(priv) || wmm_is_queue_stopped(priv))
++ && (priv->wlan_dev.dnld_sent || !Adapter->CurrentTxSkb)
++ && (priv->wlan_dev.dnld_sent || Adapter->CurCmd ||
++ list_empty(&Adapter->CmdPendingQ))
++ )
++ ) {
++ PRINTM(INFO, "main-thread sleeping... "
++ "HS_Act=%s WakeupReq=%s Conn=%s PS_Mode=%d PS_State=%d\n",
++ (Adapter->HS_Activated) ? "Y" : "N",
++ (Adapter->bWakeupDevRequired) ? "Y" : "N",
++ (Adapter->MediaConnectStatus) ? "Y" : "N",
++ Adapter->PSMode, Adapter->PSState);
++
++#ifdef _MAINSTONE
++ MST_LEDDAT1 = get_utimeofday();
++#endif
++ TX_RESTORE;
++ schedule();
++ PRINTM(INFO, "main-thread waking up: IntCnt=%d "
++ "CurCmd=%s CmdPending=%s\n"
++ " Connect=%s "
++ "CurTxSkb=%s dnld_sent=%d\n",
++ Adapter->IntCounter,
++ (Adapter->CurCmd) ? "Y" : "N",
++ list_empty(&Adapter->CmdPendingQ) ? "N" : "Y",
++ (Adapter->MediaConnectStatus) ? "Y" : "N",
++ (Adapter->CurrentTxSkb) ? "Y" : "N",
++ priv->wlan_dev.dnld_sent);
++ } else {
++ TX_RESTORE;
++ }
++
++ OS_SET_THREAD_STATE(TASK_RUNNING);
++ remove_wait_queue(&thread->waitQ, &wait);
++
++ if (kthread_should_stop() || Adapter->SurpriseRemoved) {
++ PRINTM(INFO, "main-thread: break from main thread: "
++ "SurpriseRemoved=0x%x\n", Adapter->SurpriseRemoved);
++ break;
++ }
++
++ if (Adapter->IntCounter) {
++ OS_INT_DISABLE;
++ Adapter->IntCounter = 0;
++ OS_INT_RESTORE;
++
++ if (sbi_get_int_status(priv, &ireg)) {
++ PRINTM(ERROR,
++ "main-thread: reading HOST_INT_STATUS_REG failed\n");
++ continue;
++ }
++ OS_INT_DISABLE;
++ Adapter->HisRegCpy |= ireg;
++ OS_INT_RESTORE;
++ PRINTM(INTR, "INT: status = 0x%x\n", Adapter->HisRegCpy);
++ } else if (Adapter->bWakeupDevRequired
++ && (Adapter->HS_Activated || (Adapter->IsDeepSleep)
++ )
++ ) {
++ Adapter->WakeupTries++;
++ PRINTM(CMND,
++ "Wakeup device... WakeupReq=%s Conn=%s PS_Mode=%d PS_State=%d\n",
++ (Adapter->bWakeupDevRequired) ? "Y" : "N",
++ (priv->adapter->MediaConnectStatus) ? "Y" : "N",
++ priv->adapter->PSMode, priv->adapter->PSState);
++
++ /* Wake up device */
++ if (sbi_exit_deep_sleep(priv))
++ PRINTM(MSG, "main-thread: wakeup dev failed\n");
++ continue;
++ }
++
++ /* Command response? */
++ if (Adapter->HisRegCpy & HIS_CmdUpLdRdy) {
++ OS_INT_DISABLE;
++ Adapter->HisRegCpy &= ~HIS_CmdUpLdRdy;
++ OS_INT_RESTORE;
++
++ wlan_process_rx_command(priv);
++ }
++
++ /* Any received data? */
++ if (Adapter->HisRegCpy & HIS_RxUpLdRdy) {
++ OS_INT_DISABLE;
++ Adapter->HisRegCpy &= ~HIS_RxUpLdRdy;
++ OS_INT_RESTORE;
++
++ wlan_send_rxskbQ(priv);
++ runCmd = 0;
++ }
++
++ /* Any Card Event */
++ if (Adapter->HisRegCpy & HIS_CardEvent) {
++ OS_INT_DISABLE;
++ Adapter->HisRegCpy &= ~HIS_CardEvent;
++ OS_INT_RESTORE;
++
++ if (sbi_read_event_cause(priv)) {
++ PRINTM(ERROR, "main-thread: sbi_read_event_cause failed.\n");
++ continue;
++ }
++ wlan_process_event(priv);
++ }
++
++ /* Check if we need to confirm Sleep Request received previously */
++ if (Adapter->PSState == PS_STATE_PRE_SLEEP) {
++ if (!priv->wlan_dev.dnld_sent && !Adapter->CurCmd) {
++ ASSERT(Adapter->MediaConnectStatus ==
++ WlanMediaStateConnected);
++ PSConfirmSleep(priv, (u16) Adapter->PSMode);
++ }
++ }
++
++ /* The PS state is changed during processing of
++ * Sleep Request event above
++ */
++ if ((Adapter->PSState == PS_STATE_SLEEP)
++ || (Adapter->PSState == PS_STATE_PRE_SLEEP)) {
++ continue;
++ }
++
++ if (Adapter->IsDeepSleep)
++ continue;
++
++ /* The HS_Activated flag is changed during processing of
++ HS_Activate command resp */
++ /* We cannot send command or data if HS_Activated and
++ WakeupDevRequired are TRUE */
++ if (Adapter->HS_Activated && Adapter->bWakeupDevRequired) {
++ PRINTM(INFO, "main-thread: cannot send command or data, "
++ "HS_Activated=%d\n", Adapter->HS_Activated);
++ continue;
++ }
++
++ /* Execute the next command */
++ if (!priv->wlan_dev.dnld_sent && !Adapter->CurCmd && runCmd == 1) {
++ ExecuteNextCommand(priv);
++ }
++
++ if (!priv->wlan_dev.dnld_sent
++ && !wmm_lists_empty(priv) && !wmm_is_queue_stopped(priv)) {
++ if ((Adapter->PSState == PS_STATE_FULL_POWER)
++ || (Adapter->sleep_period.period == 0)
++ || (Adapter->TxLockFlag == FALSE)) {
++ wmm_process_tx(priv);
++ }
++ }
++
++ }
++
++ wlan_deactivate_thread(thread);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function adds the card. it will probe the
++ * card, allocate the wlan_priv and initialize the device.
++ *
++ * @param card A pointer to card
++ * @return A pointer to wlan_private structure
++ */
++wlan_private *
++wlan_add_card(void *card)
++{
++ struct net_device *dev = NULL;
++ wlan_private *priv = NULL;
++
++ ENTER();
++
++ /* probe the card */
++ if (sbi_probe_card(card) < 0) {
++ PRINTM(MSG, "NO card found!\n");
++ return NULL;
++ }
++
++ /* Allocate an Ethernet device and register it */
++ if (!(dev = alloc_etherdev(sizeof(wlan_private)))) {
++ PRINTM(MSG, "Init ethernet device failed!\n");
++ return NULL;
++ }
++
++ priv = dev->priv;
++
++ /* allocate buffer for wlan_adapter */
++ if (!(priv->adapter = kmalloc(sizeof(wlan_adapter), GFP_KERNEL))) {
++ PRINTM(MSG, "Allocate buffer for wlan_adapter failed!\n");
++ goto err_kmalloc;
++ }
++
++ /* init wlan_adapter */
++ memset(priv->adapter, 0, sizeof(wlan_adapter));
++
++ priv->wlan_dev.netdev = dev;
++ priv->wlan_dev.card = card;
++ wlanpriv = priv;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
++ SET_MODULE_OWNER(dev);
++#endif
++
++ /* Setup the OS Interface to our functions */
++ dev->open = wlan_open;
++ dev->hard_start_xmit = wlan_hard_start_xmit;
++ dev->stop = wlan_close;
++ dev->do_ioctl = wlan_do_ioctl;
++ dev->set_mac_address = wlan_set_mac_address;
++
++ dev->tx_timeout = wlan_tx_timeout;
++ dev->get_stats = wlan_get_stats;
++ dev->watchdog_timeo = MRVDRV_DEFAULT_WATCHDOG_TIMEOUT;
++
++#ifdef WIRELESS_EXT
++#if WIRELESS_EXT > 17
++ wlan_handler_def.get_wireless_stats = wlan_get_wireless_stats;
++#else
++ dev->get_wireless_stats = wlan_get_wireless_stats;
++#endif
++ dev->wireless_handlers = (struct iw_handler_def *) &wlan_handler_def;
++#endif
++#define NETIF_F_DYNALLOC 16
++ dev->features |= NETIF_F_DYNALLOC;
++ dev->flags |= IFF_BROADCAST | IFF_MULTICAST;
++ dev->set_multicast_list = wlan_set_multicast_list;
++
++ init_waitqueue_head(&priv->adapter->ds_awake_q);
++
++#ifdef ENABLE_PM
++ /* register Driver to Linux Power Management system. */
++ if (!driver_register(&wlan_pm_driver)) {
++ /* Register one device to Linux Power Management system. */
++ if (platform_device_register(&wlan_pm_platform_device)) {
++ PRINTM(MSG,
++ "WiFi driver, wlan_main : error when registering device to Linux Power Managment.\n");
++ driver_unregister(&wlan_pm_driver);
++ } else {
++ PRINTM(INFO,
++ "WiFi device and driver registered to Linux Power Managment.\n");
++ }
++ } else {
++ PRINTM(MSG,
++ "WiFi driver, wlan_main : error when registering driver to Linux Power Managment.\n");
++ }
++
++#endif
++
++ INIT_LIST_HEAD(&priv->adapter->CmdFreeQ);
++ INIT_LIST_HEAD(&priv->adapter->CmdPendingQ);
++
++ PRINTM(INFO, "Starting kthread...\n");
++ priv->MainThread.priv = priv;
++ wlan_create_thread(wlan_service_main_thread,
++ &priv->MainThread, "wlan_main_service");
++
++ ConfigureThreadPriority();
++
++#ifdef REASSOCIATION
++ priv->ReassocThread.priv = priv;
++ wlan_create_thread(wlan_reassociation_thread,
++ &priv->ReassocThread, "wlan_reassoc_service");
++#endif /* REASSOCIATION */
++
++ /*
++ * Register the device. Fillup the private data structure with
++ * relevant information from the card and request for the required
++ * IRQ.
++ */
++
++ if (sbi_register_dev(priv) < 0) {
++ PRINTM(FATAL, "Failed to register wlan device!\n");
++ goto err_registerdev;
++ }
++
++ PRINTM(WARN, "%s: Marvell Wlan 802.11 Adapter "
++ "revision 0x%02X at IRQ %i\n", dev->name,
++ priv->adapter->chip_rev, dev->irq);
++
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++ wlan_proc_entry(priv, dev);
++#ifdef CONFIG_MARVELL_8686_DEBUG
++ wlan_debug_entry(priv, dev);
++#endif
++#endif
++
++ /* Get the CIS Table */
++ sbi_get_cis_info(priv);
++
++ /* init FW and HW */
++ if (wlan_init_fw(priv)) {
++ PRINTM(FATAL, "Firmware Init Failed\n");
++ goto err_init_fw;
++ }
++
++ if (register_netdev(dev)) {
++ printk(KERN_ERR "Cannot register network device!\n");
++ goto err_netdev;
++ }
++
++ LEAVE();
++ return priv;
++
++err_netdev:
++ unregister_netdev(dev);
++
++err_init_fw:
++ sbi_unregister_dev(priv);
++
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++#ifdef CONFIG_MARVELL_8686_DEBUG
++ wlan_debug_remove(priv);
++#endif
++ wlan_proc_remove(priv);
++#endif
++
++err_registerdev:
++ /* Stop the thread servicing the interrupts */
++ wake_up_interruptible(&priv->MainThread.waitQ);
++ wlan_terminate_thread(&priv->MainThread);
++
++#ifdef REASSOCIATION
++ wake_up_interruptible(&priv->ReassocThread.waitQ);
++ wlan_terminate_thread(&priv->ReassocThread);
++#endif /* REASSOCIATION */
++
++err_kmalloc:
++ free_netdev(dev);
++ wlan_free_adapter(priv);
++ wlanpriv = NULL;
++
++ LEAVE();
++ return NULL;
++}
++
++/**
++ * @brief This function removes the card.
++ *
++ * @param priv A pointer to card
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++wlan_remove_card(void *card)
++{
++ wlan_private *priv = wlanpriv;
++ wlan_adapter *Adapter;
++ struct net_device *dev;
++ union iwreq_data wrqu;
++
++ ENTER();
++
++ if (!priv) {
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ Adapter = priv->adapter;
++
++ if (!Adapter) {
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ dev = priv->wlan_dev.netdev;
++
++ wake_up_interruptible(&Adapter->ds_awake_q);
++
++ if (Adapter->CurCmd) {
++ PRINTM(INFO, "Wake up current cmdwait_q\n");
++ wake_up_interruptible(&Adapter->CurCmd->cmdwait_q);
++ }
++
++ Adapter->CurCmd = NULL;
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ wlan_clean_txrx(priv);
++ Adapter->MediaConnectStatus = WlanMediaStateDisconnected;
++ }
++ Adapter->IsAutoDeepSleepEnabled = FALSE;
++ if (Adapter->IsDeepSleep == TRUE) {
++ sbi_exit_deep_sleep(priv);
++ if (Adapter->IsDeepSleep == TRUE) {
++ if (os_wait_interruptible_timeout(Adapter->ds_awake_q,
++ !Adapter->IsDeepSleep,
++ MRVDRV_DEEP_SLEEP_EXIT_TIMEOUT)
++ == 0) {
++ PRINTM(MSG, "ds_awake_q: timer expired\n");
++ }
++ }
++ }
++
++ if (Adapter->PSMode == Wlan802_11PowerModeMAX_PSP) {
++ Adapter->PSMode = Wlan802_11PowerModeCAM;
++ PSWakeup(priv, HostCmd_OPTION_WAITFORRSP);
++ }
++
++ memset(wrqu.ap_addr.sa_data, 0xaa, ETH_ALEN);
++ wrqu.ap_addr.sa_family = ARPHRD_ETHER;
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWAP, &wrqu, NULL);
++
++ /* Disable interrupts on the card as we cannot handle them after RESET */
++ sbi_disable_host_int(priv);
++
++ PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RESET, 0, 0, 0, NULL);
++
++ os_sched_timeout(500);
++
++#ifdef ENABLE_PM
++ /* unregister driver and device from Linux Power Management system. */
++ platform_device_unregister(&wlan_pm_platform_device);
++ driver_unregister(&wlan_pm_driver);
++#endif
++
++ Adapter->SurpriseRemoved = TRUE;
++
++ /* Stop the thread servicing the interrupts */
++ wake_up_interruptible(&priv->MainThread.waitQ);
++
++#ifdef REASSOCIATION
++ wake_up_interruptible(&priv->ReassocThread.waitQ);
++#endif /* REASSOCIATION */
++
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++#ifdef CONFIG_MARVELL_8686_DEBUG
++ wlan_debug_remove(priv);
++#endif
++ wlan_proc_remove(priv);
++#endif
++
++ PRINTM(INFO, "unregester dev\n");
++ sbi_unregister_dev(priv);
++
++ /* Last reference is our one */
++ PRINTM(INFO, "refcnt = %d\n", atomic_read(&dev->refcnt));
++
++ PRINTM(INFO, "netdev_finish_unregister: %s%s.\n", dev->name,
++ (dev->features & NETIF_F_DYNALLOC) ? "" : ", old style");
++
++ unregister_netdev(dev);
++
++ PRINTM(INFO, "Unregister finish\n");
++
++ priv->wlan_dev.netdev = NULL;
++ PRINTM(INFO, "Free Adapter\n");
++ wlan_free_adapter(priv);
++ free_netdev(dev);
++ wlanpriv = NULL;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief This function sends the rx packets to the os from the skb queue
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++void
++wlan_send_rxskbQ(wlan_private * priv)
++{
++ struct sk_buff *skb;
++
++ ENTER();
++ if (priv->adapter) {
++ while ((skb = wlan_pop_rx_skb(&priv->adapter->RxSkbQ))) {
++ if (ProcessRxedPacket(priv, skb) == -ENOMEM)
++ break;
++ }
++ }
++ LEAVE();
++}
++
++/**
++ * @brief This function finds the CFP in
++ * region_cfp_table based on region and band parameter.
++ *
++ * @param region The region code
++ * @param band The band
++ * @param cfp_no A pointer to CFP number
++ * @return A pointer to CFP
++ */
++CHANNEL_FREQ_POWER *
++wlan_get_region_cfp_table(u8 region, u8 band, int *cfp_no)
++{
++ int i;
++
++ ENTER();
++
++ for (i = 0; i < sizeof(region_cfp_table) / sizeof(region_cfp_table_t);
++ i++) {
++ PRINTM(INFO, "region_cfp_table[i].region=%d\n",
++ region_cfp_table[i].region);
++ if (region_cfp_table[i].region == region) {
++ {
++ *cfp_no = region_cfp_table[i].cfp_no_BG;
++ LEAVE();
++ return region_cfp_table[i].cfp_BG;
++ }
++ }
++ }
++
++ LEAVE();
++ return NULL;
++}
++
++/**
++ * @brief This function sets region table.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param region The region code
++ * @param band The band
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_set_regiontable(wlan_private * priv, u8 region, u8 band)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int i = 0;
++
++ CHANNEL_FREQ_POWER *cfp;
++ int cfp_no;
++
++ ENTER();
++
++ memset(Adapter->region_channel, 0, sizeof(Adapter->region_channel));
++
++ {
++ cfp = wlan_get_region_cfp_table(region, band, &cfp_no);
++ if (cfp != NULL) {
++ Adapter->region_channel[i].NrCFP = cfp_no;
++ Adapter->region_channel[i].CFP = cfp;
++ } else {
++ PRINTM(INFO, "wrong region code %#x in Band B-G\n", region);
++ return WLAN_STATUS_FAILURE;
++ }
++ Adapter->region_channel[i].Valid = TRUE;
++ Adapter->region_channel[i].Region = region;
++ Adapter->region_channel[i].Band = band;
++ i++;
++ }
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function handles the interrupt. it will change PS
++ * state if applicable. it will wake up main_thread to handle
++ * the interrupt event as well.
++ *
++ * @param dev A pointer to net_device structure
++ * @return n/a
++ */
++void
++wlan_interrupt(struct net_device *dev)
++{
++ wlan_private *priv = dev->priv;
++
++ priv->adapter->IntCounter++;
++
++ PRINTM(INTR, "*\n");
++
++ priv->adapter->WakeupTries = 0;
++
++ if (priv->adapter->PSState == PS_STATE_SLEEP) {
++ priv->adapter->PSState = PS_STATE_AWAKE;
++ }
++
++ wake_up_interruptible(&priv->MainThread.waitQ);
++}
++
++#if 0
++/**
++ * @brief This function initializes module.
++ *
++ * @param n/a A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_init_module(void)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (sbi_register(wlan_add_card, wlan_remove_card, NULL) == NULL) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function cleans module
++ *
++ * @param priv n/a
++ * @return n/a
++ */
++void
++wlan_cleanup_module(void)
++{
++ ENTER();
++
++ sbi_unregister();
++
++ LEAVE();
++}
++
++module_init(wlan_init_module);
++module_exit(wlan_cleanup_module);
++#endif
++
++MODULE_DESCRIPTION("M-WLAN Driver");
++MODULE_AUTHOR("Marvell International Ltd.");
+diff --git a/drivers/net/wireless/marvell8686/wlan_proc.c b/drivers/net/wireless/marvell8686/wlan_proc.c
+new file mode 100644
+index 0000000..99604dd
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_proc.c
+@@ -0,0 +1,213 @@
++/** @file wlan_proc.c
++ * @brief This file contains functions for proc fin proc file.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 10/04/05: Add Doxygen format comments
++ 01/05/06: Add kernel 2.6.x support
++
++********************************************************/
++#include "include.h"
++
++#ifdef CONFIG_MARVELL_8686_PROC_FS
++/********************************************************
++ Local Variables
++********************************************************/
++
++static char *szModes[] = {
++ "Ad-hoc",
++ "Managed",
++ "Auto",
++ "Unknown"
++};
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief proc read function
++ *
++ * @param page pointer to buffer
++ * @param start read data starting position
++ * @param offset offset
++ * @param count counter
++ * @param eof end of file flag
++ * @param data data to output
++ * @return number of output data
++ */
++static int
++wlan_proc_read(char *page, char **start, off_t offset,
++ int count, int *eof, void *data)
++{
++ int i;
++ char *p = page;
++ struct net_device *netdev = data;
++ struct dev_mc_list *mcptr = netdev->mc_list;
++ char fmt[64];
++ wlan_private *priv = netdev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ ulong flags;
++
++ if (offset != 0) {
++ *eof = 1;
++ goto exit;
++ }
++
++ get_version(Adapter, fmt, sizeof(fmt) - 1);
++
++ p += sprintf(p, "driver_name = " "\"wlan\"\n");
++ p += sprintf(p, "driver_version = %s", fmt);
++ p += sprintf(p, "\nInterfaceName=\"%s\"\n", netdev->name);
++ p += sprintf(p, "Mode=\"%s\"\n", szModes[Adapter->InfrastructureMode]);
++ p += sprintf(p, "State=\"%s\"\n",
++ ((Adapter->MediaConnectStatus ==
++ WlanMediaStateDisconnected) ? "Disconnected" :
++ "Connected"));
++ p += sprintf(p, "MACAddress=\"%02x:%02x:%02x:%02x:%02x:%02x\"\n",
++ netdev->dev_addr[0], netdev->dev_addr[1],
++ netdev->dev_addr[2], netdev->dev_addr[3],
++ netdev->dev_addr[4], netdev->dev_addr[5]);
++
++ p += sprintf(p, "MCCount=\"%d\"\n", netdev->mc_count);
++ p += sprintf(p, "ESSID=\"%s\"\n",
++ (u8 *) Adapter->CurBssParams.BSSDescriptor.Ssid.Ssid);
++ p += sprintf(p, "Channel=\"%d\"\n",
++ Adapter->CurBssParams.BSSDescriptor.Channel);
++ p += sprintf(p, "region_code = \"%02x\"\n", (u32) Adapter->RegionCode);
++
++ /*
++ * Put out the multicast list
++ */
++ for (i = 0; i < netdev->mc_count; i++) {
++ p += sprintf(p,
++ "MCAddr[%d]=\"%02x:%02x:%02x:%02x:%02x:%02x\"\n",
++ i,
++ mcptr->dmi_addr[0], mcptr->dmi_addr[1],
++ mcptr->dmi_addr[2], mcptr->dmi_addr[3],
++ mcptr->dmi_addr[4], mcptr->dmi_addr[5]);
++
++ mcptr = mcptr->next;
++ }
++ p += sprintf(p, "num_tx_bytes = %lu\n", priv->stats.tx_bytes);
++ p += sprintf(p, "num_rx_bytes = %lu\n", priv->stats.rx_bytes);
++ p += sprintf(p, "num_tx_pkts = %lu\n", priv->stats.tx_packets);
++ p += sprintf(p, "num_rx_pkts = %lu\n", priv->stats.rx_packets);
++ p += sprintf(p, "num_tx_pkts_dropped = %lu\n", priv->stats.tx_dropped);
++ p += sprintf(p, "num_rx_pkts_dropped = %lu\n", priv->stats.rx_dropped);
++ p += sprintf(p, "num_tx_pkts_err = %lu\n", priv->stats.tx_errors);
++ p += sprintf(p, "num_rx_pkts_err = %lu\n", priv->stats.rx_errors);
++ p += sprintf(p, "carrier %s\n",
++ ((netif_carrier_ok(priv->wlan_dev.netdev)) ? "on" : "off"));
++ p += sprintf(p, "tx queue %s\n",
++ ((netif_queue_stopped(priv->wlan_dev.netdev)) ? "stopped" :
++ "started"));
++
++ spin_lock_irqsave(&Adapter->QueueSpinLock, flags);
++ if (Adapter->CurCmd) {
++ HostCmd_DS_COMMAND *CmdPtr =
++ (HostCmd_DS_COMMAND *) Adapter->CurCmd->BufVirtualAddr;
++ p += sprintf(p, "CurCmd ID = 0x%x, 0x%x\n",
++ wlan_cpu_to_le16(CmdPtr->Command),
++ wlan_cpu_to_le16(*(u16 *) ((u8 *) CmdPtr + S_DS_GEN)));
++ } else {
++ p += sprintf(p, "CurCmd NULL\n");
++ }
++ spin_unlock_irqrestore(&Adapter->QueueSpinLock, flags);
++
++ exit:
++ return (p - page);
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++
++/**
++ * @brief create wlan proc file
++ *
++ * @param priv pointer wlan_private
++ * @param dev pointer net_device
++ * @return N/A
++ */
++void
++wlan_proc_entry(wlan_private * priv, struct net_device *dev)
++{
++
++ PRINTM(INFO, "Creating Proc Interface\n");
++
++ if (!priv->proc_entry) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ priv->proc_entry = proc_mkdir("wlan", init_net.proc_net);
++#else
++ priv->proc_entry = proc_mkdir("wlan", proc_net);
++#endif
++
++
++ if (priv->proc_entry) {
++ priv->proc_dev = create_proc_read_entry
++ ("info", 0, priv->proc_entry, wlan_proc_read, dev);
++ }
++ }
++}
++
++/**
++ * @brief remove proc file
++ *
++ * @param priv pointer wlan_private
++ * @return N/A
++ */
++void
++wlan_proc_remove(wlan_private * priv)
++{
++
++ if (priv->proc_entry) {
++ remove_proc_entry("info", priv->proc_entry);
++ }
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ remove_proc_entry("wlan", init_net.proc_net);
++#else
++ remove_proc_entry("wlan", proc_net);
++#endif
++
++}
++
++/**
++ * @brief convert string to number
++ *
++ * @param s pointer to numbered string
++ * @return converted number from string s
++ */
++int
++string_to_number(char *s)
++{
++ int r = 0;
++ int base = 0;
++
++ if ((strncmp(s, "0x", 2) == 0) || (strncmp(s, "0X", 2) == 0))
++ base = 16;
++ else
++ base = 10;
++ if (base == 16)
++ s += 2;
++ for (s = s; *s != 0; s++) {
++ if ((*s >= 48) && (*s <= 57))
++ r = (r * base) + (*s - 48);
++ else if ((*s >= 65) && (*s <= 70))
++ r = (r * base) + (*s - 55);
++ else if ((*s >= 97) && (*s <= 102))
++ r = (r * base) + (*s - 87);
++ else
++ break;
++ }
++
++ return r;
++}
++
++#endif
+diff --git a/drivers/net/wireless/marvell8686/wlan_rx.c b/drivers/net/wireless/marvell8686/wlan_rx.c
+new file mode 100644
+index 0000000..9a55ca1
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_rx.c
+@@ -0,0 +1,367 @@
++/** @file wlan_rx.c
++ * @brief This file contains the handling of RX in wlan
++ * driver.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 09/28/05: Add Doxygen format comments
++ 12/09/05: ADD Sliding window SNR/NF Average Calculation support
++
++********************************************************/
++
++#include "include.h"
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++typedef struct
++{
++ u8 dest_addr[6];
++ u8 src_addr[6];
++ u16 h803_len;
++
++} __ATTRIB_PACK__ Eth803Hdr_t;
++
++typedef struct
++{
++ u8 llc_dsap;
++ u8 llc_ssap;
++ u8 llc_ctrl;
++ u8 snap_oui[3];
++ u16 snap_type;
++
++} __ATTRIB_PACK__ Rfc1042Hdr_t;
++
++typedef struct
++{
++ Eth803Hdr_t eth803_hdr;
++ Rfc1042Hdr_t rfc1042_hdr;
++
++} __ATTRIB_PACK__ RxPacketHdr_t;
++
++typedef struct
++{
++ u8 dest_addr[6];
++ u8 src_addr[6];
++ u16 ethertype;
++
++} __ATTRIB_PACK__ EthII_Hdr_t;
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function computes the AvgSNR .
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return AvgSNR
++ */
++static u8
++wlan_getAvgSNR(wlan_private * priv)
++{
++ u8 i;
++ u16 temp = 0;
++ wlan_adapter *Adapter = priv->adapter;
++ if (Adapter->numSNRNF == 0)
++ return 0;
++ for (i = 0; i < Adapter->numSNRNF; i++)
++ temp += Adapter->rawSNR[i];
++ return (u8) (temp / Adapter->numSNRNF);
++
++}
++
++/**
++ * @brief This function computes the AvgNF
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return AvgNF
++ */
++static u8
++wlan_getAvgNF(wlan_private * priv)
++{
++ u8 i;
++ u16 temp = 0;
++ wlan_adapter *Adapter = priv->adapter;
++ if (Adapter->numSNRNF == 0)
++ return 0;
++ for (i = 0; i < Adapter->numSNRNF; i++)
++ temp += Adapter->rawNF[i];
++ return (u8) (temp / Adapter->numSNRNF);
++
++}
++
++/**
++ * @brief This function save the raw SNR/NF to our internel buffer
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pRxPD A pointer to RxPD structure of received packet
++ * @return n/a
++ */
++static void
++wlan_save_rawSNRNF(wlan_private * priv, RxPD * pRxPD)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ if (Adapter->numSNRNF < Adapter->data_avg_factor)
++ Adapter->numSNRNF++;
++ Adapter->rawSNR[Adapter->nextSNRNF] = pRxPD->SNR;
++ Adapter->rawNF[Adapter->nextSNRNF] = pRxPD->NF;
++ Adapter->nextSNRNF++;
++ if (Adapter->nextSNRNF >= Adapter->data_avg_factor)
++ Adapter->nextSNRNF = 0;
++ return;
++}
++
++#define DATA_RSSI_LOW_BIT 0x01
++#define DATA_SNR_LOW_BIT 0x02
++#define DATA_RSSI_HIGH_BIT 0x04
++#define DATA_SNR_HIGH_BIT 0x08
++/**
++ * @brief This function computes the RSSI in received packet.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++static void
++wlan_check_subscribe_event(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int temp;
++ if (Adapter->subevent.EventsBitmap == 0)
++ return;
++ if ((Adapter->subevent.EventsBitmap & DATA_RSSI_LOW_BIT) ||
++ (Adapter->subevent.EventsBitmap & DATA_RSSI_HIGH_BIT)) {
++ temp =
++ -CAL_RSSI(Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE,
++ Adapter->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE);
++ if (Adapter->subevent.EventsBitmap & DATA_RSSI_LOW_BIT) {
++ if (temp > Adapter->subevent.Rssi_low.value) {
++ if (!Adapter->subevent.Rssi_low.Freq) {
++ Adapter->subevent.EventsBitmap &= ~DATA_RSSI_LOW_BIT;
++ send_iwevcustom_event(priv, CUS_EVT_DATA_RSSI_LOW);
++ } else {
++ Adapter->subevent.Rssi_low_count++;
++ if (Adapter->subevent.Rssi_low_count >=
++ Adapter->subevent.Rssi_low.Freq) {
++ Adapter->subevent.Rssi_low_count = 0;
++ send_iwevcustom_event(priv, CUS_EVT_DATA_RSSI_LOW);
++ }
++ }
++ } else
++ Adapter->subevent.Rssi_low_count = 0;
++ }
++ if (Adapter->subevent.EventsBitmap & DATA_RSSI_HIGH_BIT) {
++ if (temp < Adapter->subevent.Rssi_high.value) {
++ if (!Adapter->subevent.Rssi_high.Freq) {
++ Adapter->subevent.EventsBitmap &= ~DATA_RSSI_HIGH_BIT;
++ send_iwevcustom_event(priv, CUS_EVT_DATA_RSSI_HIGH);
++ } else {
++ Adapter->subevent.Rssi_high_count++;
++ if (Adapter->subevent.Rssi_high_count >=
++ Adapter->subevent.Rssi_high.Freq) {
++ Adapter->subevent.Rssi_high_count = 0;
++ send_iwevcustom_event(priv, CUS_EVT_DATA_RSSI_HIGH);
++ }
++ }
++ } else
++ Adapter->subevent.Rssi_high_count = 0;
++ }
++ }
++ if ((Adapter->subevent.EventsBitmap & DATA_SNR_LOW_BIT) ||
++ (Adapter->subevent.EventsBitmap & DATA_SNR_HIGH_BIT)) {
++ temp = Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE;
++ if (Adapter->subevent.EventsBitmap & DATA_SNR_LOW_BIT) {
++ if (temp < Adapter->subevent.Snr_low.value) {
++ if (!Adapter->subevent.Snr_low.Freq) {
++ send_iwevcustom_event(priv, CUS_EVT_DATA_SNR_LOW);
++ Adapter->subevent.EventsBitmap &= ~DATA_SNR_LOW_BIT;
++ } else {
++ Adapter->subevent.Snr_low_count++;
++ if (Adapter->subevent.Snr_low_count >=
++ Adapter->subevent.Snr_low.Freq) {
++ Adapter->subevent.Snr_low_count = 0;
++ send_iwevcustom_event(priv, CUS_EVT_DATA_SNR_LOW);
++ }
++ }
++ } else
++ Adapter->subevent.Snr_low_count = 0;
++ }
++ if (Adapter->subevent.EventsBitmap & DATA_SNR_HIGH_BIT) {
++ if (temp > Adapter->subevent.Snr_high.value) {
++ if (!Adapter->subevent.Snr_high.Freq) {
++ Adapter->subevent.EventsBitmap &= ~DATA_SNR_HIGH_BIT;
++ send_iwevcustom_event(priv, CUS_EVT_DATA_SNR_HIGH);
++ } else {
++ Adapter->subevent.Snr_high_count++;
++ if (Adapter->subevent.Snr_high_count >=
++ Adapter->subevent.Snr_high.Freq) {
++ Adapter->subevent.Snr_high_count = 0;
++ send_iwevcustom_event(priv, CUS_EVT_DATA_SNR_HIGH);
++ }
++ }
++
++ } else
++ Adapter->subevent.Snr_high_count = 0;
++ }
++ }
++ return;
++}
++
++/**
++ * @brief This function computes the RSSI in received packet.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pRxPD A pointer to RxPD structure of received packet
++ * @return n/a
++ */
++static void
++wlan_compute_rssi(wlan_private * priv, RxPD * pRxPD)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ PRINTM(INFO, "RxPD: SNR = %d, NF = %d\n", pRxPD->SNR, pRxPD->NF);
++
++ Adapter->SNR[TYPE_RXPD][TYPE_NOAVG] = pRxPD->SNR;
++ Adapter->NF[TYPE_RXPD][TYPE_NOAVG] = pRxPD->NF;
++ wlan_save_rawSNRNF(priv, pRxPD);
++
++ Adapter->RxPDAge = os_time_get();
++ Adapter->RxPDRate = pRxPD->RxRate;
++
++ Adapter->SNR[TYPE_RXPD][TYPE_AVG] = wlan_getAvgSNR(priv) * AVG_SCALE;
++ Adapter->NF[TYPE_RXPD][TYPE_AVG] = wlan_getAvgNF(priv) * AVG_SCALE;
++ PRINTM(INFO, "SNR-avg = %d, NF-avg = %d\n",
++ Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE,
++ Adapter->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE);
++
++ Adapter->RSSI[TYPE_RXPD][TYPE_NOAVG] =
++ CAL_RSSI(Adapter->SNR[TYPE_RXPD][TYPE_NOAVG],
++ Adapter->NF[TYPE_RXPD][TYPE_NOAVG]);
++
++ Adapter->RSSI[TYPE_RXPD][TYPE_AVG] =
++ CAL_RSSI(Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE,
++ Adapter->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE);
++ wlan_check_subscribe_event(priv);
++ LEAVE();
++}
++
++/********************************************************
++ Global functions
++********************************************************/
++
++/**
++ * @brief This function processes received packet and forwards it
++ * to kernel/upper layer
++ *
++ * @param priv A pointer to wlan_private
++ * @param skb A pointer to skb which includes the received packet
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++ProcessRxedPacket(wlan_private * priv, struct sk_buff *skb)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++
++ RxPacketHdr_t *pRxPkt;
++ RxPD *pRxPD;
++
++ int hdrChop;
++ EthII_Hdr_t *pEthHdr;
++ u32 u32SkbLen = skb->len;
++
++ const u8 rfc1042_eth_hdr[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
++
++ ENTER();
++
++ pRxPD = (RxPD *) skb->data;
++ pRxPkt = (RxPacketHdr_t *) ((u8 *) pRxPD + pRxPD->PktOffset);
++
++ DBG_HEXDUMP(DAT_D, "Rx", skb->data, MIN(skb->len, MAX_DATA_DUMP_LEN));
++
++ endian_convert_RxPD(pRxPD);
++
++ if (skb->len < (ETH_HLEN + 8 + pRxPD->PktOffset)) {
++ PRINTM(ERROR, "RX Error: FRAME RECEIVED WITH BAD LENGTH\n");
++ priv->stats.rx_length_errors++;
++ ret = WLAN_STATUS_SUCCESS;
++ kfree_skb(skb);
++ goto done;
++ }
++
++ PRINTM(INFO, "RX Data: skb->len - pRxPD->PktOffset = %d - %d = %d\n",
++ skb->len, pRxPD->PktOffset, skb->len - pRxPD->PktOffset);
++
++ HEXDUMP("RX Data: Dest", pRxPkt->eth803_hdr.dest_addr,
++ sizeof(pRxPkt->eth803_hdr.dest_addr));
++ HEXDUMP("RX Data: Src", pRxPkt->eth803_hdr.src_addr,
++ sizeof(pRxPkt->eth803_hdr.src_addr));
++
++ if (memcmp(&pRxPkt->rfc1042_hdr,
++ rfc1042_eth_hdr, sizeof(rfc1042_eth_hdr)) == 0) {
++ /*
++ * Replace the 803 header and rfc1042 header (llc/snap) with an
++ * EthernetII header, keep the src/dst and snap_type (ethertype)
++ *
++ * The firmware only passes up SNAP frames converting
++ * all RX Data from 802.11 to 802.2/LLC/SNAP frames.
++ *
++ * To create the Ethernet II, just move the src, dst address right
++ * before the snap_type.
++ */
++ pEthHdr = (EthII_Hdr_t *)
++ ((u8 *) & pRxPkt->eth803_hdr
++ + sizeof(pRxPkt->eth803_hdr) + sizeof(pRxPkt->rfc1042_hdr)
++ - sizeof(pRxPkt->eth803_hdr.dest_addr)
++ - sizeof(pRxPkt->eth803_hdr.src_addr)
++ - sizeof(pRxPkt->rfc1042_hdr.snap_type));
++
++ memcpy(pEthHdr->src_addr, pRxPkt->eth803_hdr.src_addr,
++ sizeof(pEthHdr->src_addr));
++ memcpy(pEthHdr->dest_addr, pRxPkt->eth803_hdr.dest_addr,
++ sizeof(pEthHdr->dest_addr));
++
++ /* Chop off the RxPD + the excess memory from the 802.2/llc/snap header
++ * that was removed
++ */
++ hdrChop = (u8 *) pEthHdr - (u8 *) pRxPD;
++ } else {
++ HEXDUMP("RX Data: LLC/SNAP",
++ (u8 *) & pRxPkt->rfc1042_hdr, sizeof(pRxPkt->rfc1042_hdr));
++
++ /* Chop off the RxPD */
++ hdrChop = (u8 *) & pRxPkt->eth803_hdr - (u8 *) pRxPD;
++ }
++
++ /* Chop off the leading header bytes so the skb points to the start of
++ * either the reconstructed EthII frame or the 802.2/llc/snap frame
++ */
++ skb_pull(skb, hdrChop);
++
++ u32SkbLen = skb->len;
++ wlan_compute_rssi(priv, pRxPD);
++
++ if (os_upload_rx_packet(priv, skb)) {
++ PRINTM(ERROR, "RX Error: os_upload_rx_packet" " returns failure\n");
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++ priv->stats.rx_bytes += u32SkbLen;
++ priv->stats.rx_packets++;
++
++ PRINTM(DATA, "Data => kernel\n");
++
++ ret = WLAN_STATUS_SUCCESS;
++ done:
++ LEAVE();
++
++ return (ret);
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_scan.c b/drivers/net/wireless/marvell8686/wlan_scan.c
+new file mode 100644
+index 0000000..5ce08d3
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_scan.c
+@@ -0,0 +1,3226 @@
++/** @file wlan_scan.c
++ *
++ * @brief Functions implementing wlan scan IOCTL and firmware command APIs
++ *
++ * IOCTL handlers as well as command preperation and response routines
++ * for sending scan commands to the firmware.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ *
++ * @sa wlan_scan.h
++ */
++/********************************************************
++Change Log:
++ 01/11/06: Initial revision. New scan code, relocate related functions
++ 01/19/06: Update specific scan routines to discard old results for adhoc
++ 01/31/06: Add support for selectively enabling the FW Scan channel filter
++
++************************************************************/
++
++#include "include.h"
++
++/********************************************************
++ Local Constants
++********************************************************/
++
++//! Approximate amount of data needed to pass a scan result back to iwlist
++#define MAX_SCAN_CELL_SIZE (IW_EV_ADDR_LEN \
++ + MRVDRV_MAX_SSID_LENGTH \
++ + IW_EV_UINT_LEN \
++ + IW_EV_FREQ_LEN \
++ + IW_EV_QUAL_LEN \
++ + MRVDRV_MAX_SSID_LENGTH \
++ + IW_EV_PARAM_LEN \
++ + 40) /* 40 for WPAIE */
++
++//! Memory needed to store a max sized Channel List TLV for a firmware scan
++#define CHAN_TLV_MAX_SIZE (sizeof(MrvlIEtypesHeader_t) \
++ + (MRVDRV_MAX_CHANNELS_PER_SCAN \
++ * sizeof(ChanScanParamSet_t)))
++
++//! Memory needed to store a max number/size SSID TLV for a firmware scan
++#define SSID_TLV_MAX_SIZE (1 * sizeof(MrvlIEtypes_SsIdParamSet_t))
++
++//! WPS TLV MAX size is MAX IE size plus 2 bytes for u16 MRVL TLV extension
++#define WPS_TLV_MAX_SIZE (sizeof(IEEEtypes_VendorSpecific_t) + 2)
++
++//! Maximum memory needed for a wlan_scan_cmd_config with all TLVs at max
++#define MAX_SCAN_CFG_ALLOC (sizeof(wlan_scan_cmd_config) \
++ + sizeof(MrvlIEtypes_NumProbes_t) \
++ + CHAN_TLV_MAX_SIZE \
++ + SSID_TLV_MAX_SIZE \
++ + WPS_TLV_MAX_SIZE)
++
++//! The maximum number of channels the firmware can scan per command
++#define MRVDRV_MAX_CHANNELS_PER_SCAN 14
++
++/**
++ * @brief Number of channels to scan per firmware scan command issuance.
++ *
++ * Number restricted to prevent hitting the limit on the amount of scan data
++ * returned in a single firmware scan command.
++ */
++#define MRVDRV_CHANNELS_PER_SCAN_CMD 4
++
++//! Macro to enable/disable SSID checking before storing a scan table
++#ifdef DISCARD_BAD_SSID
++#define CHECK_SSID_IS_VALID(x) ssid_valid(&bssidEntry.Ssid)
++#else
++#define CHECK_SSID_IS_VALID(x) TRUE
++#endif
++
++/********************************************************
++ Local Variables and Types
++********************************************************/
++
++/**
++ * @brief Interally used to send a configured scan cmd between driver routines
++ */
++typedef union
++{
++ wlan_scan_cmd_config config; //!< Scan configuration (variable length)
++ u8 configAllocBuf[MAX_SCAN_CFG_ALLOC]; //!< Max allocated block
++} wlan_scan_cmd_config_tlv;
++
++/**
++ * @brief Check if a scanned network compatible with the driver settings
++ *
++ * WEP WPA WPA2 ad-hoc encrypt Network
++ * enabled enabled enabled AES mode Privacy WPA WPA2 Compatible
++ * 0 0 0 0 NONE 0 0 0 yes No security
++ * 0 1 0 0 x 1x 1 x yes WPA
++ * 0 0 1 0 x 1x x 1 yes WPA2
++ * 0 0 0 1 NONE 1 0 0 yes Ad-hoc AES
++ *
++ * 1 0 0 0 NONE 1 0 0 yes Static WEP
++ * 0 0 0 0 !=NONE 1 0 0 yes Dynamic WEP
++ *
++ *
++ * @param Adapter A pointer to wlan_adapter
++ * @param index Index in ScanTable to check against current driver settings
++ * @param mode Network mode: Infrastructure or IBSS
++ *
++ * @return Index in ScanTable, or error code if negative
++ */
++static int
++IsNetworkCompatible(wlan_adapter * Adapter, int index, int mode)
++{
++ BSSDescriptor_t *pBSSDesc;
++
++ ENTER();
++
++ pBSSDesc = &Adapter->ScanTable[index];
++
++ /* Don't check for compatibility if roaming */
++ if ((Adapter->MediaConnectStatus == WlanMediaStateConnected)
++ && (Adapter->InfrastructureMode == Wlan802_11Infrastructure)
++ && (pBSSDesc->InfrastructureMode == Wlan802_11Infrastructure)) {
++ LEAVE();
++ return index;
++ }
++
++ if (Adapter->wps.SessionEnable == TRUE) {
++ PRINTM(INFO, "Return success directly in WPS period\n");
++ LEAVE();
++ return index;
++ }
++
++ if (pBSSDesc->InfrastructureMode == mode) {
++ if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPDisabled
++ && !Adapter->SecInfo.WPAEnabled
++ && !Adapter->SecInfo.WPA2Enabled
++ && pBSSDesc->wpaIE.VendHdr.ElementId != WPA_IE
++ && pBSSDesc->rsnIE.IeeeHdr.ElementId != RSN_IE
++ && !Adapter->AdhocAESEnabled
++ && Adapter->SecInfo.EncryptionMode == CIPHER_NONE
++ && !pBSSDesc->Privacy) {
++ /* no security */
++ LEAVE();
++ return index;
++ } else if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled
++ && !Adapter->SecInfo.WPAEnabled
++ && !Adapter->SecInfo.WPA2Enabled
++ && !Adapter->AdhocAESEnabled && pBSSDesc->Privacy) {
++ /* static WEP enabled */
++ LEAVE();
++ return index;
++ } else if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPDisabled
++ && Adapter->SecInfo.WPAEnabled
++ && !Adapter->SecInfo.WPA2Enabled
++ && (pBSSDesc->wpaIE.VendHdr.ElementId == WPA_IE)
++ && !Adapter->AdhocAESEnabled
++ /* Privacy bit may NOT be set in some APs like LinkSys WRT54G
++ && pBSSDesc->Privacy */
++ ) {
++ /* WPA enabled */
++ PRINTM(INFO, "IsNetworkCompatible() WPA: index=%d wpa_ie=%#x "
++ "wpa2_ie=%#x WEP=%s WPA=%s WPA2=%s EncMode=%#x "
++ "privacy=%#x\n",
++ index,
++ pBSSDesc->wpaIE.VendHdr.ElementId,
++ pBSSDesc->rsnIE.IeeeHdr.ElementId,
++ (Adapter->SecInfo.WEPStatus ==
++ Wlan802_11WEPEnabled) ? "e" : "d",
++ (Adapter->SecInfo.WPAEnabled) ? "e" : "d",
++ (Adapter->SecInfo.WPA2Enabled) ? "e" : "d",
++ Adapter->SecInfo.EncryptionMode, pBSSDesc->Privacy);
++ LEAVE();
++ return index;
++ } else if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPDisabled
++ && !Adapter->SecInfo.WPAEnabled
++ && Adapter->SecInfo.WPA2Enabled
++ && (pBSSDesc->rsnIE.IeeeHdr.ElementId == RSN_IE)
++ && !Adapter->AdhocAESEnabled
++ /* Privacy bit may NOT be set in some APs like LinkSys WRT54G
++ && pBSSDesc->Privacy */
++ ) {
++ /* WPA2 enabled */
++ PRINTM(INFO, "IsNetworkCompatible() WPA2: index=%d wpa_ie=%#x "
++ "wpa2_ie=%#x WEP=%s WPA=%s WPA2=%s EncMode=%#x "
++ "privacy=%#x\n",
++ index,
++ pBSSDesc->wpaIE.VendHdr.ElementId,
++ pBSSDesc->rsnIE.IeeeHdr.ElementId,
++ (Adapter->SecInfo.WEPStatus ==
++ Wlan802_11WEPEnabled) ? "e" : "d",
++ (Adapter->SecInfo.WPAEnabled) ? "e" : "d",
++ (Adapter->SecInfo.WPA2Enabled) ? "e" : "d",
++ Adapter->SecInfo.EncryptionMode, pBSSDesc->Privacy);
++ LEAVE();
++ return index;
++ } else if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPDisabled
++ && !Adapter->SecInfo.WPAEnabled
++ && !Adapter->SecInfo.WPA2Enabled
++ && (pBSSDesc->wpaIE.VendHdr.ElementId != WPA_IE)
++ && (pBSSDesc->rsnIE.IeeeHdr.ElementId != RSN_IE)
++ && Adapter->AdhocAESEnabled
++ && Adapter->SecInfo.EncryptionMode == CIPHER_NONE
++ && pBSSDesc->Privacy) {
++ /* Ad-hoc AES enabled */
++ LEAVE();
++ return index;
++ } else if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPDisabled
++ && !Adapter->SecInfo.WPAEnabled
++ && !Adapter->SecInfo.WPA2Enabled
++ && (pBSSDesc->wpaIE.VendHdr.ElementId != WPA_IE)
++ && (pBSSDesc->rsnIE.IeeeHdr.ElementId != RSN_IE)
++ && !Adapter->AdhocAESEnabled
++ && Adapter->SecInfo.EncryptionMode != CIPHER_NONE
++ && pBSSDesc->Privacy) {
++ /* dynamic WEP enabled */
++ PRINTM(INFO, "IsNetworkCompatible() dynamic WEP: index=%d "
++ "wpa_ie=%#x wpa2_ie=%#x EncMode=%#x privacy=%#x\n",
++ index,
++ pBSSDesc->wpaIE.VendHdr.ElementId,
++ pBSSDesc->rsnIE.IeeeHdr.ElementId,
++ Adapter->SecInfo.EncryptionMode, pBSSDesc->Privacy);
++ LEAVE();
++ return index;
++ }
++
++ /* security doesn't match */
++ PRINTM(INFO, "IsNetworkCompatible() FAILED: index=%d wpa_ie=%#x "
++ "wpa2_ie=%#x WEP=%s WPA=%s WPA2=%s EncMode=%#x privacy=%#x\n",
++ index,
++ pBSSDesc->wpaIE.VendHdr.ElementId,
++ pBSSDesc->rsnIE.IeeeHdr.ElementId,
++ (Adapter->SecInfo.WEPStatus ==
++ Wlan802_11WEPEnabled) ? "e" : "d",
++ (Adapter->SecInfo.WPAEnabled) ? "e" : "d",
++ (Adapter->SecInfo.WPA2Enabled) ? "e" : "d",
++ Adapter->SecInfo.EncryptionMode, pBSSDesc->Privacy);
++ LEAVE();
++ return -ECONNREFUSED;
++ }
++
++ /* mode doesn't match */
++ LEAVE();
++ return -ENETUNREACH;
++}
++
++/**
++ * @brief This function validates a SSID as being able to be printed
++ *
++ * @param pSsid SSID structure to validate
++ *
++ * @return TRUE or FALSE
++ */
++static BOOLEAN
++ssid_valid(WLAN_802_11_SSID * pSsid)
++{
++ int ssidIdx;
++
++ for (ssidIdx = 0; ssidIdx < pSsid->SsidLength; ssidIdx++) {
++ if (!isprint(pSsid->Ssid[ssidIdx])) {
++ return FALSE;
++ }
++ }
++
++ return TRUE;
++}
++
++/**
++ * @brief Post process the scan table after a new scan command has completed
++ *
++ * Inspect each entry of the scan table and try to find an entry that
++ * matches our current associated/joined network from the scan. If
++ * one is found, update the stored copy of the BSSDescriptor for our
++ * current network.
++ *
++ * Debug dump the current scan table contents if compiled accordingly.
++ *
++ * @param priv A pointer to wlan_private structure
++ *
++ * @return void
++ */
++static void
++wlan_scan_process_results(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int i;
++ int foundCurrent;
++
++ foundCurrent = FALSE;
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ Adapter->CurBssParams.BSSDescriptor.pBeaconBuf = NULL;
++ Adapter->CurBssParams.BSSDescriptor.beaconBufSize = 0;
++ Adapter->CurBssParams.BSSDescriptor.beaconBufSizeMax = 0;
++ i = FindSSIDInList(Adapter,
++ &Adapter->CurBssParams.BSSDescriptor.Ssid,
++ Adapter->CurBssParams.BSSDescriptor.MacAddress,
++ Adapter->InfrastructureMode);
++
++ if (i >= 0) {
++ PRINTM(INFO, "Found current ssid/bssid in list @ index #%d\n", i);
++ /* Make a copy of current BSSID descriptor */
++ memcpy(&Adapter->CurBssParams.BSSDescriptor,
++ &Adapter->ScanTable[i],
++ sizeof(Adapter->CurBssParams.BSSDescriptor));
++ }
++ }
++
++ for (i = 0; i < Adapter->NumInScanTable; i++) {
++ PRINTM(INFO, "Scan:(%02d) %02x:%02x:%02x:%02x:%02x:%02x, "
++ "RSSI[%03d], SSID[%s]\n",
++ i,
++ Adapter->ScanTable[i].MacAddress[0],
++ Adapter->ScanTable[i].MacAddress[1],
++ Adapter->ScanTable[i].MacAddress[2],
++ Adapter->ScanTable[i].MacAddress[3],
++ Adapter->ScanTable[i].MacAddress[4],
++ Adapter->ScanTable[i].MacAddress[5],
++ (s32) Adapter->ScanTable[i].Rssi,
++ Adapter->ScanTable[i].Ssid.Ssid);
++
++ }
++}
++
++/**
++ * @brief Create a channel list for the driver to scan based on region info
++ *
++ * Use the driver region/band information to construct a comprehensive list
++ * of channels to scan. This routine is used for any scan that is not
++ * provided a specific channel list to scan.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param scanChanList Output parameter: Resulting channel list to scan
++ * @param filteredScan Flag indicating whether or not a BSSID or SSID filter
++ * is being sent in the command to firmware. Used to
++ * increase the number of channels sent in a scan
++ * command and to disable the firmware channel scan
++ * filter.
++ *
++ * @return void
++ */
++static void
++wlan_scan_create_channel_list(wlan_private * priv,
++ ChanScanParamSet_t * scanChanList,
++ BOOLEAN filteredScan)
++{
++
++ wlan_adapter *Adapter = priv->adapter;
++ REGION_CHANNEL *scanRegion;
++ CHANNEL_FREQ_POWER *cfp;
++ int rgnIdx;
++ int chanIdx;
++ int nextChan;
++ u8 scanType;
++
++ chanIdx = 0;
++
++ /* Set the default scan type to the user specified type, will later
++ * be changed to passive on a per channel basis if restricted by
++ * regulatory requirements (11d or 11h)
++ */
++ scanType = Adapter->ScanType;
++
++ for (rgnIdx = 0; rgnIdx < NELEMENTS(Adapter->region_channel); rgnIdx++) {
++ if (wlan_get_state_11d(priv) == ENABLE_11D &&
++ Adapter->MediaConnectStatus != WlanMediaStateConnected) {
++ /* Scan all the supported chan for the first scan */
++ if (!Adapter->universal_channel[rgnIdx].Valid)
++ continue;
++ scanRegion = &Adapter->universal_channel[rgnIdx];
++
++ /* clear the parsed_region_chan for the first scan */
++ memset(&Adapter->parsed_region_chan, 0x00,
++ sizeof(Adapter->parsed_region_chan));
++ } else {
++ if (!Adapter->region_channel[rgnIdx].Valid)
++ continue;
++ scanRegion = &Adapter->region_channel[rgnIdx];
++ }
++
++ for (nextChan = 0;
++ nextChan < scanRegion->NrCFP; nextChan++, chanIdx++) {
++
++ cfp = scanRegion->CFP + nextChan;
++
++ if (wlan_get_state_11d(priv) == ENABLE_11D) {
++ scanType =
++ wlan_get_scan_type_11d(cfp->Channel,
++ &Adapter->parsed_region_chan);
++ }
++
++ switch (scanRegion->Band) {
++ case BAND_B:
++ case BAND_G:
++ default:
++ scanChanList[chanIdx].RadioType = HostCmd_SCAN_RADIO_TYPE_BG;
++ break;
++ }
++
++ if (scanType == HostCmd_SCAN_TYPE_PASSIVE) {
++ scanChanList[chanIdx].MaxScanTime =
++ wlan_cpu_to_le16(Adapter->PassiveScanTime);
++ scanChanList[chanIdx].ChanScanMode.PassiveScan = TRUE;
++ } else {
++ scanChanList[chanIdx].MaxScanTime =
++ wlan_cpu_to_le16(Adapter->ActiveScanTime);
++ scanChanList[chanIdx].ChanScanMode.PassiveScan = FALSE;
++ }
++
++ scanChanList[chanIdx].ChanNumber = cfp->Channel;
++
++ if (filteredScan) {
++ scanChanList[chanIdx].MaxScanTime =
++ wlan_cpu_to_le16(Adapter->SpecificScanTime);
++ scanChanList[chanIdx].ChanScanMode.DisableChanFilt = TRUE;
++ }
++ }
++ }
++}
++
++static void
++wlan_add_wps_probe_request_ie(wlan_private * priv, u8 ** ppTlvOut)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ MrvlIEtypesHeader_t *tlv;
++
++ if (Adapter->wps.wpsIe.VendHdr.Len) {
++ tlv = (MrvlIEtypesHeader_t *) * ppTlvOut;
++ tlv->Type = wlan_cpu_to_le16(TLV_TYPE_WPS_ENROLLEE_PROBE_REQ_TLV);
++ tlv->Len = wlan_cpu_to_le16(Adapter->wps.wpsIe.VendHdr.Len);
++ *ppTlvOut += sizeof(MrvlIEtypesHeader_t);
++ memcpy(*ppTlvOut,
++ Adapter->wps.wpsIe.VendHdr.Oui,
++ Adapter->wps.wpsIe.VendHdr.Len);
++ *ppTlvOut += (Adapter->wps.wpsIe.VendHdr.Len
++ + sizeof(MrvlIEtypesHeader_t));
++ }
++}
++
++/**
++ * @brief Construct a wlan_scan_cmd_config structure to use in issue scan cmds
++ *
++ * Application layer or other functions can invoke wlan_scan_networks
++ * with a scan configuration supplied in a wlan_ioctl_user_scan_cfg struct.
++ * This structure is used as the basis of one or many wlan_scan_cmd_config
++ * commands that are sent to the command processing module and sent to
++ * firmware.
++ *
++ * Create a wlan_scan_cmd_config based on the following user supplied
++ * parameters (if present):
++ * - SSID filter
++ * - BSSID filter
++ * - Number of Probes to be sent
++ * - Channel list
++ *
++ * If the SSID or BSSID filter is not present, disable/clear the filter.
++ * If the number of probes is not set, use the adapter default setting
++ * Qualify the channel
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pUserScanIn NULL or pointer to scan configuration parameters
++ * @param pScanCfgOut Output parameter: Resulting scan configuration
++ * @param ppChanTlvOut Output parameter: Pointer to the start of the
++ * channel TLV portion of the output scan config
++ * @param pScanChanList Output parameter: Pointer to the resulting channel
++ * list to scan
++ * @param pMaxChanPerScan Output parameter: Number of channels to scan for
++ * each issuance of the firmware scan command
++ * @param pFilteredScan Output parameter: Flag indicating whether or not
++ * a BSSID or SSID filter is being sent in the
++ * command to firmware. Used to increase the number
++ * of channels sent in a scan command and to
++ * disable the firmware channel scan filter.
++ * @param pScanCurrentOnly Output parameter: Flag indicating whether or not
++ * we are only scanning our current active channel
++ *
++ * @return void
++ */
++static void
++wlan_scan_setup_scan_config(wlan_private * priv,
++ const wlan_ioctl_user_scan_cfg * pUserScanIn,
++ wlan_scan_cmd_config * pScanCfgOut,
++ MrvlIEtypes_ChanListParamSet_t ** ppChanTlvOut,
++ ChanScanParamSet_t * pScanChanList,
++ int *pMaxChanPerScan,
++ BOOLEAN * pFilteredScan,
++ BOOLEAN * pScanCurrentOnly)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ const u8 zeroMac[ETH_ALEN] = { 0, 0, 0, 0, 0, 0 };
++ MrvlIEtypes_NumProbes_t *pNumProbesTlv;
++ u8 *pTlvPos;
++ u16 numProbes;
++ u16 ssidLen;
++ int chanIdx;
++ int scanType;
++ int scanDur;
++ int channel;
++ int radioType;
++ int ssidIdx;
++ BOOLEAN ssidFilter;
++
++ MrvlIEtypes_WildCardSsIdParamSet_t *pWildCardSsidTlv;
++
++ /* The tlvBufferLen is calculated for each scan command. The TLVs added
++ * in this routine will be preserved since the routine that sends
++ * the command will append channelTLVs at *ppChanTlvOut. The difference
++ * between the *ppChanTlvOut and the tlvBuffer start will be used
++ * to calculate the size of anything we add in this routine.
++ */
++ pScanCfgOut->tlvBufferLen = 0;
++
++ /* Running tlv pointer. Assigned to ppChanTlvOut at end of function
++ * so later routines know where channels can be added to the command buf
++ */
++ pTlvPos = pScanCfgOut->tlvBuffer;
++
++ /*
++ * Set the initial scan paramters for progressive scanning. If a specific
++ * BSSID or SSID is used, the number of channels in the scan command
++ * will be increased to the absolute maximum
++ */
++ *pMaxChanPerScan = MRVDRV_MAX_CHANNELS_PER_SCAN;
++
++ /* Initialize the scan as un-filtered; the flag is later set to
++ * TRUE below if a SSID or BSSID filter is sent in the command
++ */
++ *pFilteredScan = FALSE;
++
++ /* Initialize the scan as not being only on the current channel. If
++ * the channel list is customized, only contains one channel, and
++ * is the active channel, this is set true and data flow is not halted.
++ */
++ *pScanCurrentOnly = FALSE;
++
++ if (pUserScanIn) {
++
++ /* Default the ssidFilter flag to TRUE, set false under certain
++ * wildcard conditions and qualified by the existence of an SSID
++ * list before marking the scan as filtered
++ */
++ ssidFilter = TRUE;
++
++ /* Set the bss type scan filter, use Adapter setting if unset */
++ pScanCfgOut->bssType = (pUserScanIn->bssType ? pUserScanIn->bssType :
++ Adapter->ScanMode);
++
++ /* Set the number of probes to send, use Adapter setting if unset */
++ numProbes = (pUserScanIn->numProbes ? pUserScanIn->numProbes :
++ Adapter->ScanProbes);
++
++ /*
++ * Set the BSSID filter to the incoming configuration,
++ * if non-zero. If not set, it will remain disabled (all zeros).
++ */
++ memcpy(pScanCfgOut->specificBSSID,
++ pUserScanIn->specificBSSID,
++ sizeof(pScanCfgOut->specificBSSID));
++
++ for (ssidIdx = 0; ((ssidIdx < NELEMENTS(pUserScanIn->ssidList))
++ && (*pUserScanIn->ssidList[ssidIdx].ssid
++ || pUserScanIn->ssidList[ssidIdx].maxLen));
++ ssidIdx++) {
++
++ ssidLen = strlen(pUserScanIn->ssidList[ssidIdx].ssid) + 1;
++
++ pWildCardSsidTlv = (MrvlIEtypes_WildCardSsIdParamSet_t *) pTlvPos;
++ pWildCardSsidTlv->Header.Type
++ = wlan_cpu_to_le16(TLV_TYPE_WILDCARDSSID);
++ pWildCardSsidTlv->Header.Len
++ = ssidLen + sizeof(pWildCardSsidTlv->MaxSsidLength);
++ pWildCardSsidTlv->MaxSsidLength
++ = pUserScanIn->ssidList[ssidIdx].maxLen;
++
++ memcpy(pWildCardSsidTlv->SsId,
++ pUserScanIn->ssidList[ssidIdx].ssid, ssidLen);
++
++ pTlvPos += (sizeof(pWildCardSsidTlv->Header)
++ + pWildCardSsidTlv->Header.Len);
++
++ pWildCardSsidTlv->Header.Len
++ = wlan_cpu_to_le16(pWildCardSsidTlv->Header.Len);
++
++ PRINTM(INFO, "Scan: ssidList[%d]: %s, %d\n",
++ ssidIdx,
++ pWildCardSsidTlv->SsId, pWildCardSsidTlv->MaxSsidLength);
++
++ /* Empty wildcard ssid with a maxlen will match many or potentially
++ * all SSIDs (maxlen == 32), therefore do not treat the scan
++ * as filtered.
++ */
++ if ((ssidLen == 0) && pWildCardSsidTlv->MaxSsidLength) {
++ ssidFilter = FALSE;
++ }
++ }
++
++ /*
++ * The default number of channels sent in the command is low to
++ * ensure the response buffer from the firmware does not truncate
++ * scan results. That is not an issue with an SSID or BSSID
++ * filter applied to the scan results in the firmware.
++ */
++ if ((ssidIdx && ssidFilter)
++ || memcmp(pScanCfgOut->specificBSSID, &zeroMac, sizeof(zeroMac))) {
++ *pFilteredScan = TRUE;
++ }
++
++ } else {
++ pScanCfgOut->bssType = Adapter->ScanMode;
++ numProbes = Adapter->ScanProbes;
++ }
++
++ /* If the input config or adapter has the number of Probes set, add tlv */
++ if (numProbes) {
++
++ PRINTM(INFO, "Scan: numProbes = %d\n", numProbes);
++
++ pNumProbesTlv = (MrvlIEtypes_NumProbes_t *) pTlvPos;
++ pNumProbesTlv->Header.Type = wlan_cpu_to_le16(TLV_TYPE_NUMPROBES);
++ pNumProbesTlv->Header.Len = sizeof(pNumProbesTlv->NumProbes);
++ pNumProbesTlv->NumProbes = wlan_cpu_to_le16(numProbes);
++
++ pTlvPos += sizeof(pNumProbesTlv->Header) + pNumProbesTlv->Header.Len;
++
++ pNumProbesTlv->Header.Len =
++ wlan_cpu_to_le16(pNumProbesTlv->Header.Len);
++ }
++
++ wlan_add_wps_probe_request_ie(priv, &pTlvPos);
++
++ /*
++ * Set the output for the channel TLV to the address in the tlv buffer
++ * past any TLVs that were added in this fuction (SSID, numProbes).
++ * Channel TLVs will be added past this for each scan command, preserving
++ * the TLVs that were previously added.
++ */
++ *ppChanTlvOut = (MrvlIEtypes_ChanListParamSet_t *) pTlvPos;
++
++ if (pUserScanIn && pUserScanIn->chanList[0].chanNumber) {
++
++ PRINTM(INFO, "Scan: Using supplied channel list\n");
++
++ for (chanIdx = 0;
++ chanIdx < WLAN_IOCTL_USER_SCAN_CHAN_MAX
++ && pUserScanIn->chanList[chanIdx].chanNumber; chanIdx++) {
++
++ channel = pUserScanIn->chanList[chanIdx].chanNumber;
++ (pScanChanList + chanIdx)->ChanNumber = channel;
++
++ radioType = pUserScanIn->chanList[chanIdx].radioType;
++ (pScanChanList + chanIdx)->RadioType = radioType;
++
++ scanType = pUserScanIn->chanList[chanIdx].scanType;
++
++ if (scanType == HostCmd_SCAN_TYPE_PASSIVE) {
++ (pScanChanList + chanIdx)->ChanScanMode.PassiveScan = TRUE;
++ } else {
++ (pScanChanList + chanIdx)->ChanScanMode.PassiveScan = FALSE;
++ }
++
++ if (pUserScanIn->chanList[chanIdx].scanTime) {
++ scanDur = pUserScanIn->chanList[chanIdx].scanTime;
++ } else {
++ if (scanType == HostCmd_SCAN_TYPE_PASSIVE) {
++ scanDur = Adapter->PassiveScanTime;
++ } else if (*pFilteredScan) {
++ scanDur = Adapter->SpecificScanTime;
++ } else {
++ scanDur = Adapter->ActiveScanTime;
++ }
++ }
++
++ (pScanChanList + chanIdx)->MinScanTime =
++ wlan_cpu_to_le16(scanDur);
++ (pScanChanList + chanIdx)->MaxScanTime =
++ wlan_cpu_to_le16(scanDur);
++ }
++
++ /* Check if we are only scanning the current channel */
++ if ((chanIdx == 1)
++ && (pUserScanIn->chanList[0].chanNumber
++ == priv->adapter->CurBssParams.BSSDescriptor.Channel)) {
++ *pScanCurrentOnly = TRUE;
++ PRINTM(INFO, "Scan: Scanning current channel only");
++ }
++
++ } else {
++ PRINTM(INFO, "Scan: Creating full region channel list\n");
++ wlan_scan_create_channel_list(priv, pScanChanList, *pFilteredScan);
++ }
++}
++
++/**
++ * @brief Construct and send multiple scan config commands to the firmware
++ *
++ * Previous routines have created a wlan_scan_cmd_config with any requested
++ * TLVs. This function splits the channel TLV into maxChanPerScan lists
++ * and sends the portion of the channel TLV along with the other TLVs
++ * to the wlan_cmd routines for execution in the firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param maxChanPerScan Maximum number channels to be included in each
++ * scan command sent to firmware
++ * @param filteredScan Flag indicating whether or not a BSSID or SSID
++ * filter is being used for the firmware command
++ * scan command sent to firmware
++ * @param pScanCfgOut Scan configuration used for this scan.
++ * @param pChanTlvOut Pointer in the pScanCfgOut where the channel TLV
++ * should start. This is past any other TLVs that
++ * must be sent down in each firmware command.
++ * @param pScanChanList List of channels to scan in maxChanPerScan segments
++ *
++ * @return WLAN_STATUS_SUCCESS or error return otherwise
++ */
++static int
++wlan_scan_channel_list(wlan_private * priv,
++ int maxChanPerScan,
++ BOOLEAN filteredScan,
++ wlan_scan_cmd_config * pScanCfgOut,
++ MrvlIEtypes_ChanListParamSet_t * pChanTlvOut,
++ ChanScanParamSet_t * pScanChanList)
++{
++ ChanScanParamSet_t *pTmpChan;
++ ChanScanParamSet_t *pStartChan;
++ u8 scanBand;
++ int doneEarly;
++ int tlvIdx;
++ int totalscantime;
++ int ret;
++
++ ENTER();
++
++ if (pScanCfgOut == 0 || pChanTlvOut == 0 || pScanChanList == 0) {
++ PRINTM(INFO, "Scan: Null detect: %p, %p, %p\n",
++ pScanCfgOut, pChanTlvOut, pScanChanList);
++ return WLAN_STATUS_FAILURE;
++ }
++
++ ret = WLAN_STATUS_SUCCESS;
++
++ pChanTlvOut->Header.Type = wlan_cpu_to_le16(TLV_TYPE_CHANLIST);
++
++ /* Set the temp channel struct pointer to the start of the desired list */
++ pTmpChan = pScanChanList;
++
++ /* Loop through the desired channel list, sending a new firmware scan
++ * commands for each maxChanPerScan channels (or for 1,6,11 individually
++ * if configured accordingly)
++ */
++ while (pTmpChan->ChanNumber) {
++
++ tlvIdx = 0;
++ totalscantime = 0;
++ pChanTlvOut->Header.Len = 0;
++ scanBand = pTmpChan->RadioType;
++ pStartChan = pTmpChan;
++ doneEarly = FALSE;
++
++ /* Construct the Channel TLV for the scan command. Continue to
++ * insert channel TLVs until:
++ * - the tlvIdx hits the maximum configured per scan command
++ * - the next channel to insert is 0 (end of desired channel list)
++ * - doneEarly is set (controlling individual scanning of 1,6,11)
++ */
++ while (tlvIdx < maxChanPerScan && pTmpChan->ChanNumber && !doneEarly) {
++
++ PRINTM(INFO, "Scan: Chan(%3d), Radio(%d), Mode(%d,%d), Dur(%d)\n",
++ pTmpChan->ChanNumber,
++ pTmpChan->RadioType,
++ pTmpChan->ChanScanMode.PassiveScan,
++ pTmpChan->ChanScanMode.DisableChanFilt,
++ pTmpChan->MaxScanTime);
++
++ /* Copy the current channel TLV to the command being prepared */
++ memcpy(pChanTlvOut->ChanScanParam + tlvIdx,
++ pTmpChan, sizeof(pChanTlvOut->ChanScanParam));
++
++ /* Increment the TLV header length by the size appended */
++ pChanTlvOut->Header.Len += sizeof(pChanTlvOut->ChanScanParam);
++
++ /*
++ * The tlv buffer length is set to the number of bytes of the
++ * between the channel tlv pointer and the start of the
++ * tlv buffer. This compensates for any TLVs that were appended
++ * before the channel list.
++ */
++ pScanCfgOut->tlvBufferLen = ((u8 *) pChanTlvOut
++ - pScanCfgOut->tlvBuffer);
++
++ /* Add the size of the channel tlv header and the data length */
++ pScanCfgOut->tlvBufferLen += (sizeof(pChanTlvOut->Header)
++ + pChanTlvOut->Header.Len);
++
++ /* Increment the index to the channel tlv we are constructing */
++ tlvIdx++;
++
++ /* Count the total scan time per command */
++ totalscantime += pTmpChan->MaxScanTime;
++
++ doneEarly = FALSE;
++
++ /* Stop the loop if the *current* channel is in the 1,6,11 set
++ * and we are not filtering on a BSSID or SSID.
++ */
++ if (!filteredScan && (pTmpChan->ChanNumber == 1
++ || pTmpChan->ChanNumber == 6
++ || pTmpChan->ChanNumber == 11)) {
++ doneEarly = TRUE;
++ }
++
++ /* Increment the tmp pointer to the next channel to be scanned */
++ pTmpChan++;
++
++ /* Stop the loop if the *next* channel is in the 1,6,11 set.
++ * This will cause it to be the only channel scanned on the next
++ * interation
++ */
++ if (!filteredScan && (pTmpChan->ChanNumber == 1
++ || pTmpChan->ChanNumber == 6
++ || pTmpChan->ChanNumber == 11)) {
++ doneEarly = TRUE;
++ }
++ }
++
++ /* The total scan time should be less than scan command timeout value */
++ if (totalscantime > MRVDRV_MAX_TOTAL_SCAN_TIME) {
++ PRINTM(MSG,
++ "Total scan time %d ms is over limit (%d ms), scan skipped\n",
++ totalscantime, MRVDRV_MAX_TOTAL_SCAN_TIME);
++ ret = WLAN_STATUS_FAILURE;
++ break;
++ }
++
++ pChanTlvOut->Header.Len = wlan_cpu_to_le16(pChanTlvOut->Header.Len);
++
++ /* Send the scan command to the firmware with the specified cfg */
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SCAN, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ pScanCfgOut);
++ }
++
++ LEAVE();
++
++ if (ret) {
++ return WLAN_STATUS_FAILURE;
++ }
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Internal function used to start a scan based on an input config
++ *
++ * Use the input user scan configuration information when provided in
++ * order to send the appropriate scan commands to firmware to populate or
++ * update the internal driver scan table
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pUserScanIn Pointer to the input configuration for the requested
++ * scan.
++ *
++ * @return WLAN_STATUS_SUCCESS or < 0 if error
++ */
++static int
++wlan_scan_networks(wlan_private * priv,
++ const wlan_ioctl_user_scan_cfg * pUserScanIn)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ MrvlIEtypes_ChanListParamSet_t *pChanTlvOut;
++
++ ChanScanParamSet_t scanChanList[WLAN_IOCTL_USER_SCAN_CHAN_MAX];
++ wlan_scan_cmd_config_tlv scanCfgOut;
++ BOOLEAN keepPreviousScan;
++ BOOLEAN filteredScan;
++ BOOLEAN scanCurrentChanOnly;
++ int maxChanPerScan;
++ int ret;
++ BOOLEAN bBgScan;
++
++ ENTER();
++
++ memset(scanChanList, 0x00, sizeof(scanChanList));
++ memset(&scanCfgOut, 0x00, sizeof(scanCfgOut));
++
++ keepPreviousScan = FALSE;
++
++ wlan_scan_setup_scan_config(priv,
++ pUserScanIn,
++ &scanCfgOut.config,
++ &pChanTlvOut,
++ scanChanList,
++ &maxChanPerScan,
++ &filteredScan, &scanCurrentChanOnly);
++
++ if (pUserScanIn) {
++ keepPreviousScan = pUserScanIn->keepPreviousScan;
++ }
++
++ if (keepPreviousScan == FALSE) {
++ memset(Adapter->ScanTable, 0x00,
++ sizeof(BSSDescriptor_t) * MRVDRV_MAX_BSSID_LIST);
++ Adapter->NumInScanTable = 0;
++ Adapter->pBeaconBufEnd = Adapter->beaconBuffer;
++ }
++
++ /* Keep the data path active if we are only scanning our current channel */
++ if (!scanCurrentChanOnly) {
++ PRINTM(INFO, "Scan: WMM Queue stop\n");
++ priv->wlan_dev.netdev->watchdog_timeo = MRVDRV_SCAN_WATCHDOG_TIMEOUT;
++ /* If WMM queues are in use, only stop the internal data queues */
++ wmm_stop_queue(priv);
++ }
++
++ bBgScan = priv->adapter->bgScanConfig->Enable;
++ if (priv->adapter->bgScanConfig->Enable == TRUE) {
++ wlan_bg_scan_enable(priv, FALSE);
++ }
++
++ ret = wlan_scan_channel_list(priv,
++ maxChanPerScan,
++ filteredScan,
++ &scanCfgOut.config,
++ pChanTlvOut, scanChanList);
++
++ /* Process the resulting scan table:
++ * - Remove any bad ssids
++ * - Update our current BSS information from scan data
++ */
++ wlan_scan_process_results(priv);
++
++ if (bBgScan == TRUE) {
++ wlan_bg_scan_enable(priv, TRUE);
++ }
++
++ PRINTM(INFO, "Scan: WMM Queue start\n");
++
++ priv->wlan_dev.netdev->watchdog_timeo = MRVDRV_DEFAULT_WATCHDOG_TIMEOUT;
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ wmm_start_queue(priv);
++ }
++ os_carrier_on(priv);
++ os_start_queue(priv);
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Create a brief scan resp to relay basic BSS info to the app layer
++ *
++ * When the beacon/probe response has not been buffered, use the saved BSS
++ * information available to provide a minimum response for the application
++ * ioctl retrieval routines. Include:
++ * - Timestamp
++ * - Beacon Period
++ * - Capabilities (including WMM Element if available)
++ * - SSID
++ *
++ * @param ppBuffer Output parameter: Buffer used to create basic scan rsp
++ * @param pBSSDesc Pointer to a BSS entry in the scan table to create
++ * scan response from for delivery to the application layer
++ *
++ * @return void
++ */
++static void
++wlan_scan_create_brief_table_entry(u8 ** ppBuffer, BSSDescriptor_t * pBSSDesc)
++{
++ u8 *pTmpBuf = *ppBuffer;
++ u8 tmpSSIDHdr[2];
++ u8 ieLen;
++
++ if (copy_to_user(pTmpBuf, pBSSDesc->TimeStamp,
++ sizeof(pBSSDesc->TimeStamp))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++ pTmpBuf += sizeof(pBSSDesc->TimeStamp);
++
++ if (copy_to_user(pTmpBuf, &pBSSDesc->BeaconPeriod,
++ sizeof(pBSSDesc->BeaconPeriod))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++ pTmpBuf += sizeof(pBSSDesc->BeaconPeriod);
++
++ if (copy_to_user(pTmpBuf, &pBSSDesc->Cap, sizeof(pBSSDesc->Cap))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++ pTmpBuf += sizeof(pBSSDesc->Cap);
++
++ tmpSSIDHdr[0] = 0; /* Element ID for SSID is zero */
++ tmpSSIDHdr[1] = pBSSDesc->Ssid.SsidLength;
++ if (copy_to_user(pTmpBuf, tmpSSIDHdr, sizeof(tmpSSIDHdr))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++ pTmpBuf += sizeof(tmpSSIDHdr);
++
++ if (copy_to_user(pTmpBuf, pBSSDesc->Ssid.Ssid, pBSSDesc->Ssid.SsidLength)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++ pTmpBuf += pBSSDesc->Ssid.SsidLength;
++
++ if (pBSSDesc->wmmIE.VendHdr.ElementId == WMM_IE) {
++ ieLen = sizeof(IEEEtypes_Header_t) + pBSSDesc->wmmIE.VendHdr.Len;
++ if (copy_to_user(pTmpBuf, &pBSSDesc->wmmIE, ieLen)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++
++ pTmpBuf += ieLen;
++ }
++
++ if (pBSSDesc->wpaIE.VendHdr.ElementId == WPA_IE) {
++ ieLen = sizeof(IEEEtypes_Header_t) + pBSSDesc->wpaIE.VendHdr.Len;
++ if (copy_to_user(pTmpBuf, &pBSSDesc->wpaIE, ieLen)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++
++ pTmpBuf += ieLen;
++ }
++
++ if (pBSSDesc->rsnIE.IeeeHdr.ElementId == RSN_IE) {
++ ieLen = sizeof(IEEEtypes_Header_t) + pBSSDesc->rsnIE.IeeeHdr.Len;
++ if (copy_to_user(pTmpBuf, &pBSSDesc->rsnIE, ieLen)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return;
++ }
++
++ pTmpBuf += ieLen;
++ }
++
++ *ppBuffer = pTmpBuf;
++}
++
++/**
++ * @brief Inspect the scan response buffer for pointers to expected TLVs
++ *
++ * TLVs can be included at the end of the scan response BSS information.
++ * Parse the data in the buffer for pointers to TLVs that can potentially
++ * be passed back in the response
++ *
++ * @param pTlv Pointer to the start of the TLV buffer to parse
++ * @param tlvBufSize Size of the TLV buffer
++ * @param ppTsfTlv Output parameter: Pointer to the TSF TLV if found
++ *
++ * @return void
++ */
++static void
++wlan_ret_802_11_scan_get_tlv_ptrs(MrvlIEtypes_Data_t * pTlv,
++ int tlvBufSize,
++ MrvlIEtypes_TsfTimestamp_t ** ppTsfTlv)
++{
++ MrvlIEtypes_Data_t *pCurrentTlv;
++ int tlvBufLeft;
++ u16 tlvType;
++ u16 tlvLen;
++
++ pCurrentTlv = pTlv;
++ tlvBufLeft = tlvBufSize;
++ *ppTsfTlv = NULL;
++
++ PRINTM(INFO, "SCAN_RESP: tlvBufSize = %d\n", tlvBufSize);
++ HEXDUMP("SCAN_RESP: TLV Buf", (u8 *) pTlv, tlvBufSize);
++
++ while (tlvBufLeft >= sizeof(MrvlIEtypesHeader_t)) {
++ tlvType = wlan_le16_to_cpu(pCurrentTlv->Header.Type);
++ tlvLen = wlan_le16_to_cpu(pCurrentTlv->Header.Len);
++
++ switch (tlvType) {
++ case TLV_TYPE_TSFTIMESTAMP:
++ PRINTM(INFO, "SCAN_RESP: TSF Timestamp TLV, len = %d\n", tlvLen);
++ *ppTsfTlv = (MrvlIEtypes_TsfTimestamp_t *) pCurrentTlv;
++ break;
++
++ default:
++ PRINTM(INFO, "SCAN_RESP: Unhandled TLV = %d\n", tlvType);
++ /* Give up, this seems corrupted */
++ return;
++ } /* switch */
++
++ tlvBufLeft -= (sizeof(pTlv->Header) + tlvLen);
++ pCurrentTlv = (MrvlIEtypes_Data_t *) (pCurrentTlv->Data + tlvLen);
++ } /* while */
++}
++
++/**
++ * @brief Interpret a BSS scan response returned from the firmware
++ *
++ * Parse the various fixed fields and IEs passed back for a a BSS probe
++ * response or beacon from the scan command. Record information as needed
++ * in the scan table BSSDescriptor_t for that entry.
++ *
++ * @param pBSSIDEntry Output parameter: Pointer to the BSS Entry
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++InterpretBSSDescriptionWithIE(BSSDescriptor_t * pBSSEntry,
++ u8 ** pBeaconInfo, int *bytesLeft)
++{
++ IEEEtypes_ElementId_e elemID;
++ IEEEtypes_FhParamSet_t *pFH;
++ IEEEtypes_DsParamSet_t *pDS;
++ IEEEtypes_CfParamSet_t *pCF;
++ IEEEtypes_IbssParamSet_t *pIbss;
++ IEEEtypes_CapInfo_t *pCap;
++ WLAN_802_11_FIXED_IEs fixedIE;
++ u8 *pCurrentPtr;
++ u8 *pRate;
++ u8 elemLen;
++ u16 totalIeLen;
++ u8 bytesToCopy;
++ u8 rateSize;
++ u16 beaconSize;
++ BOOLEAN foundDataRateIE;
++ int bytesLeftForCurrentBeacon;
++ IEEEtypes_ERPInfo_t *pERPInfo;
++
++ IEEEtypes_VendorSpecific_t *pVendorIe;
++ const u8 wpa_oui[4] = { 0x00, 0x50, 0xf2, 0x01 };
++ const u8 wmm_oui[4] = { 0x00, 0x50, 0xf2, 0x02 };
++ const u8 wps_oui[4] = { 0x00, 0x50, 0xf2, 0x04 };
++
++ IEEEtypes_CountryInfoSet_t *pcountryinfo;
++
++ ENTER();
++
++ foundDataRateIE = FALSE;
++ rateSize = 0;
++ beaconSize = 0;
++
++ if (*bytesLeft >= sizeof(beaconSize)) {
++ /* Extract & convert beacon size from the command buffer */
++ memcpy(&beaconSize, *pBeaconInfo, sizeof(beaconSize));
++ beaconSize = wlan_le16_to_cpu(beaconSize);
++ *bytesLeft -= sizeof(beaconSize);
++ *pBeaconInfo += sizeof(beaconSize);
++ }
++
++ if (beaconSize == 0 || beaconSize > *bytesLeft) {
++
++ *pBeaconInfo += *bytesLeft;
++ *bytesLeft = 0;
++
++ return WLAN_STATUS_FAILURE;
++ }
++
++ /* Initialize the current working beacon pointer for this BSS iteration */
++ pCurrentPtr = *pBeaconInfo;
++
++ /* Advance the return beacon pointer past the current beacon */
++ *pBeaconInfo += beaconSize;
++ *bytesLeft -= beaconSize;
++
++ bytesLeftForCurrentBeacon = beaconSize;
++
++ memcpy(pBSSEntry->MacAddress, pCurrentPtr, MRVDRV_ETH_ADDR_LEN);
++ PRINTM(INFO, "InterpretIE: AP MAC Addr-%02x:%02x:%02x:%02x:%02x:%02x\n",
++ pBSSEntry->MacAddress[0], pBSSEntry->MacAddress[1],
++ pBSSEntry->MacAddress[2], pBSSEntry->MacAddress[3],
++ pBSSEntry->MacAddress[4], pBSSEntry->MacAddress[5]);
++
++ pCurrentPtr += MRVDRV_ETH_ADDR_LEN;
++ bytesLeftForCurrentBeacon -= MRVDRV_ETH_ADDR_LEN;
++
++ if (bytesLeftForCurrentBeacon < 12) {
++ PRINTM(INFO, "InterpretIE: Not enough bytes left\n");
++ return WLAN_STATUS_FAILURE;
++ }
++
++ /*
++ * next 4 fields are RSSI, time stamp, beacon interval,
++ * and capability information
++ */
++
++ /* RSSI is 1 byte long */
++ pBSSEntry->Rssi = wlan_le32_to_cpu((LONG) (*pCurrentPtr));
++ PRINTM(INFO, "InterpretIE: RSSI=%02X\n", *pCurrentPtr);
++ pCurrentPtr += 1;
++ bytesLeftForCurrentBeacon -= 1;
++
++ /*
++ * The RSSI is not part of the beacon/probe response. After we have
++ * advanced pCurrentPtr past the RSSI field, save the remaining
++ * data for use at the application layer
++ */
++ pBSSEntry->pBeaconBuf = pCurrentPtr;
++ pBSSEntry->beaconBufSize = bytesLeftForCurrentBeacon;
++
++ /* time stamp is 8 bytes long */
++ memcpy(fixedIE.Timestamp, pCurrentPtr, 8);
++ memcpy(pBSSEntry->TimeStamp, pCurrentPtr, 8);
++ pCurrentPtr += 8;
++ bytesLeftForCurrentBeacon -= 8;
++
++ /* beacon interval is 2 bytes long */
++ memcpy(&fixedIE.BeaconInterval, pCurrentPtr, 2);
++ pBSSEntry->BeaconPeriod = wlan_le16_to_cpu(fixedIE.BeaconInterval);
++ pCurrentPtr += 2;
++ bytesLeftForCurrentBeacon -= 2;
++
++ /* capability information is 2 bytes long */
++ memcpy(&fixedIE.Capabilities, pCurrentPtr, 2);
++ PRINTM(INFO, "InterpretIE: fixedIE.Capabilities=0x%X\n",
++ fixedIE.Capabilities);
++ fixedIE.Capabilities = wlan_le16_to_cpu(fixedIE.Capabilities);
++ pCap = (IEEEtypes_CapInfo_t *) & fixedIE.Capabilities;
++ memcpy(&pBSSEntry->Cap, pCap, sizeof(IEEEtypes_CapInfo_t));
++ pCurrentPtr += 2;
++ bytesLeftForCurrentBeacon -= 2;
++
++ /* rest of the current buffer are IE's */
++ PRINTM(INFO, "InterpretIE: IELength for this AP = %d\n",
++ bytesLeftForCurrentBeacon);
++
++ HEXDUMP("InterpretIE: IE info", (u8 *) pCurrentPtr,
++ bytesLeftForCurrentBeacon);
++
++ if (pCap->Privacy) {
++ PRINTM(INFO, "InterpretIE: AP WEP enabled\n");
++ pBSSEntry->Privacy = Wlan802_11PrivFilter8021xWEP;
++ } else {
++ pBSSEntry->Privacy = Wlan802_11PrivFilterAcceptAll;
++ }
++
++ if (pCap->Ibss == 1) {
++ pBSSEntry->InfrastructureMode = Wlan802_11IBSS;
++ } else {
++ pBSSEntry->InfrastructureMode = Wlan802_11Infrastructure;
++ }
++
++ /* process variable IE */
++ while (bytesLeftForCurrentBeacon >= 2) {
++ elemID = (IEEEtypes_ElementId_e) (*((u8 *) pCurrentPtr));
++ elemLen = *((u8 *) pCurrentPtr + 1);
++ totalIeLen = elemLen + sizeof(IEEEtypes_Header_t);
++
++ if (bytesLeftForCurrentBeacon < elemLen) {
++ PRINTM(INFO, "InterpretIE: Error in processing IE, "
++ "bytes left < IE length\n");
++ bytesLeftForCurrentBeacon = 0;
++ continue;
++ }
++
++ switch (elemID) {
++
++ case SSID:
++ pBSSEntry->Ssid.SsidLength = elemLen;
++ memcpy(pBSSEntry->Ssid.Ssid, (pCurrentPtr + 2), elemLen);
++ PRINTM(INFO, "InterpretIE: Ssid: %-32s\n", pBSSEntry->Ssid.Ssid);
++ break;
++
++ case SUPPORTED_RATES:
++ memcpy(pBSSEntry->DataRates, pCurrentPtr + 2, elemLen);
++ memcpy(pBSSEntry->SupportedRates, pCurrentPtr + 2, elemLen);
++ HEXDUMP("InterpretIE: SupportedRates:",
++ pBSSEntry->SupportedRates, elemLen);
++ rateSize = elemLen;
++ foundDataRateIE = TRUE;
++ break;
++
++ case EXTRA_IE:
++ PRINTM(INFO, "InterpretIE: EXTRA_IE Found!\n");
++ pBSSEntry->extra_ie = 1;
++ break;
++
++ case FH_PARAM_SET:
++ pFH = (IEEEtypes_FhParamSet_t *) pCurrentPtr;
++ pBSSEntry->NetworkTypeInUse = Wlan802_11FH;
++ memcpy(&pBSSEntry->PhyParamSet.FhParamSet, pFH,
++ sizeof(IEEEtypes_FhParamSet_t));
++ pBSSEntry->PhyParamSet.FhParamSet.DwellTime
++ =
++ wlan_le16_to_cpu(pBSSEntry->PhyParamSet.FhParamSet.DwellTime);
++ break;
++
++ case DS_PARAM_SET:
++ pDS = (IEEEtypes_DsParamSet_t *) pCurrentPtr;
++
++ pBSSEntry->NetworkTypeInUse = Wlan802_11DS;
++ pBSSEntry->Channel = pDS->CurrentChan;
++
++ memcpy(&pBSSEntry->PhyParamSet.DsParamSet, pDS,
++ sizeof(IEEEtypes_DsParamSet_t));
++ break;
++
++ case CF_PARAM_SET:
++ pCF = (IEEEtypes_CfParamSet_t *) pCurrentPtr;
++ memcpy(&pBSSEntry->SsParamSet.CfParamSet, pCF,
++ sizeof(IEEEtypes_CfParamSet_t));
++ break;
++
++ case IBSS_PARAM_SET:
++ pIbss = (IEEEtypes_IbssParamSet_t *) pCurrentPtr;
++ pBSSEntry->ATIMWindow = wlan_le32_to_cpu(pIbss->AtimWindow);
++ memcpy(&pBSSEntry->SsParamSet.IbssParamSet, pIbss,
++ sizeof(IEEEtypes_IbssParamSet_t));
++ break;
++
++ /* Handle Country Info IE */
++ case COUNTRY_INFO:
++ pcountryinfo = (IEEEtypes_CountryInfoSet_t *) pCurrentPtr;
++
++ if (pcountryinfo->Len < sizeof(pcountryinfo->CountryCode) ||
++ pcountryinfo->Len + 2 >
++ sizeof(IEEEtypes_CountryInfoFullSet_t)) {
++ PRINTM(INFO,
++ "InterpretIE: 11D- Err "
++ "CountryInfo len =%d min=%d max=%d\n",
++ pcountryinfo->Len, sizeof(pcountryinfo->CountryCode),
++ sizeof(IEEEtypes_CountryInfoFullSet_t));
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ memcpy(&pBSSEntry->CountryInfo,
++ pcountryinfo, pcountryinfo->Len + 2);
++ HEXDUMP("InterpretIE: 11D- CountryInfo:",
++ (u8 *) pcountryinfo, (u32) (pcountryinfo->Len + 2));
++ break;
++ case ERP_INFO:
++ pERPInfo = (IEEEtypes_ERPInfo_t *) pCurrentPtr;
++ pBSSEntry->ERPFlags = pERPInfo->ERPFlags;
++ break;
++ case EXTENDED_SUPPORTED_RATES:
++ /*
++ * only process extended supported rate
++ * if data rate is already found.
++ * data rate IE should come before
++ * extended supported rate IE
++ */
++ if (foundDataRateIE) {
++ if ((elemLen + rateSize) > WLAN_SUPPORTED_RATES) {
++ bytesToCopy = (WLAN_SUPPORTED_RATES - rateSize);
++ } else {
++ bytesToCopy = elemLen;
++ }
++
++ pRate = (u8 *) pBSSEntry->DataRates;
++ pRate += rateSize;
++ memcpy(pRate, pCurrentPtr + 2, bytesToCopy);
++
++ pRate = (u8 *) pBSSEntry->SupportedRates;
++ pRate += rateSize;
++ memcpy(pRate, pCurrentPtr + 2, bytesToCopy);
++ }
++ HEXDUMP("InterpretIE: ExtSupportedRates:",
++ pBSSEntry->SupportedRates, elemLen + rateSize);
++ break;
++
++ case VENDOR_SPECIFIC_221:
++ pVendorIe = (IEEEtypes_VendorSpecific_t *) pCurrentPtr;
++
++ if ((!memcmp
++ (pVendorIe->VendHdr.Oui, wpa_oui,
++ sizeof(pVendorIe->VendHdr.Oui)))
++ && (pVendorIe->VendHdr.OuiType == wpa_oui[3])) {
++ pBSSEntry->wpaIE.VendHdr.Len
++ = (MIN(totalIeLen, sizeof(pBSSEntry->wpaIE))
++ - sizeof(IEEEtypes_Header_t));
++
++ memcpy(&pBSSEntry->wpaIE,
++ pCurrentPtr,
++ (pBSSEntry->wpaIE.VendHdr.Len
++ + sizeof(IEEEtypes_Header_t)));
++
++ HEXDUMP("InterpretIE: Resp WPA_IE",
++ (u8 *) & pBSSEntry->wpaIE,
++ (pBSSEntry->wpaIE.VendHdr.Len
++ + sizeof(IEEEtypes_Header_t)));
++ } else
++ if ((!memcmp
++ (pVendorIe->VendHdr.Oui, wmm_oui,
++ sizeof(pVendorIe->VendHdr.Oui)))
++ && (pVendorIe->VendHdr.OuiType == wmm_oui[3])) {
++ if (totalIeLen == sizeof(IEEEtypes_WmmParameter_t)
++ || totalIeLen == sizeof(IEEEtypes_WmmInfo_t)) {
++
++ /* Only accept and copy the WMM IE if it matches
++ * the size expected for the WMM Info IE or the
++ * WMM Parameter IE.
++ */
++ memcpy((u8 *) & pBSSEntry->wmmIE, pCurrentPtr,
++ totalIeLen);
++ HEXDUMP("InterpretIE: Resp WMM_IE",
++ (u8 *) & pBSSEntry->wmmIE, totalIeLen);
++ }
++ } else
++ if ((!memcmp
++ (pVendorIe->VendHdr.Oui, wps_oui,
++ sizeof(pVendorIe->VendHdr.Oui)))
++ && (pVendorIe->VendHdr.OuiType == wps_oui[3])) {
++ memcpy((u8 *) & pBSSEntry->wpsIE, pCurrentPtr, totalIeLen);
++ HEXDUMP("InterpretIE: Resp WPS_IE",
++ (u8 *) & pBSSEntry->wpsIE, totalIeLen);
++ }
++ break;
++ case RSN_IE:
++ pBSSEntry->rsnIE.IeeeHdr.Len
++ = (MIN(totalIeLen, sizeof(pBSSEntry->rsnIE))
++ - sizeof(IEEEtypes_Header_t));
++
++ memcpy(&pBSSEntry->rsnIE,
++ pCurrentPtr,
++ pBSSEntry->rsnIE.IeeeHdr.Len + sizeof(IEEEtypes_Header_t));
++
++ HEXDUMP("InterpretIE: Resp RSN_IE",
++ (u8 *) & pBSSEntry->rsnIE,
++ pBSSEntry->rsnIE.IeeeHdr.Len +
++ sizeof(IEEEtypes_Header_t));
++ break;
++ }
++
++ pCurrentPtr += elemLen + 2;
++
++ /* need to account for IE ID and IE Len */
++ bytesLeftForCurrentBeacon -= (elemLen + 2);
++
++ } /* while (bytesLeftForCurrentBeacon > 2) */
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Compare two SSIDs
++ *
++ * @param ssid1 A pointer to ssid to compare
++ * @param ssid2 A pointer to ssid to compare
++ *
++ * @return 0--ssid is same, otherwise is different
++ */
++int
++SSIDcmp(WLAN_802_11_SSID * ssid1, WLAN_802_11_SSID * ssid2)
++{
++ if (!ssid1 || !ssid2)
++ return -1;
++
++ if (ssid1->SsidLength != ssid2->SsidLength)
++ return -1;
++
++ return memcmp(ssid1->Ssid, ssid2->Ssid, ssid1->SsidLength);
++}
++
++/**
++ * @brief This function finds a specific compatible BSSID in the scan list
++ *
++ * @param Adapter A pointer to wlan_adapter
++ * @param bssid BSSID to find in the scan list
++ * @param mode Network mode: Infrastructure or IBSS
++ *
++ * @return index in BSSID list, or error return code (< 0)
++ */
++int
++FindBSSIDInList(wlan_adapter * Adapter, u8 * bssid, int mode)
++{
++ int ret = -ENETUNREACH;
++ int i;
++
++ if (!bssid)
++ return -EFAULT;
++
++ PRINTM(INFO, "FindBSSID: Num of BSSIDs = %d\n", Adapter->NumInScanTable);
++
++ /* Look through the scan table for a compatible match. The ret return
++ * variable will be equal to the index in the scan table (greater
++ * than zero) if the network is compatible. The loop will continue
++ * past a matched bssid that is not compatible in case there is an
++ * AP with multiple SSIDs assigned to the same BSSID
++ */
++ for (i = 0; ret < 0 && i < Adapter->NumInScanTable; i++) {
++ if (!memcmp(Adapter->ScanTable[i].MacAddress, bssid, ETH_ALEN)) {
++ switch (mode) {
++ case Wlan802_11Infrastructure:
++ case Wlan802_11IBSS:
++ ret = IsNetworkCompatible(Adapter, i, mode);
++ break;
++ default:
++ ret = i;
++ break;
++ }
++ }
++ }
++
++ if (ret >= 0) {
++ if (find_cfp_by_band_and_channel
++ (Adapter, 0, Adapter->ScanTable[ret].Channel) == NULL) {
++ ret = -ENETUNREACH;
++ }
++ }
++ return ret;
++}
++
++/**
++ * @brief This function finds ssid in ssid list.
++ *
++ * @param Adapter A pointer to wlan_adapter
++ * @param ssid SSID to find in the list
++ * @param bssid BSSID to qualify the SSID selection (if provided)
++ * @param mode Network mode: Infrastructure or IBSS
++ *
++ * @return index in BSSID list
++ */
++int
++FindSSIDInList(wlan_adapter * Adapter, WLAN_802_11_SSID * ssid,
++ u8 * bssid, int mode)
++{
++ int net = -ENETUNREACH;
++ u8 bestrssi = 0;
++ int i, j;
++
++ PRINTM(INFO, "Num of Entries in Table = %d\n", Adapter->NumInScanTable);
++
++ /* Loop through the table until the maximum is reached or until a match
++ * is found based on the bssid field comparison
++ */
++ for (i = 0;
++ i < Adapter->NumInScanTable && (bssid == NULL || (bssid && net < 0));
++ i++) {
++
++ if (!SSIDcmp(&Adapter->ScanTable[i].Ssid, ssid) && ((bssid == NULL)
++ ||
++ !memcmp(Adapter->
++ ScanTable
++ [i].
++ MacAddress,
++ bssid,
++ ETH_ALEN)))
++ {
++ switch (mode) {
++ case Wlan802_11Infrastructure:
++ case Wlan802_11IBSS:
++ j = IsNetworkCompatible(Adapter, i, mode);
++
++ if (j >= 0) {
++ if (SCAN_RSSI(Adapter->ScanTable[i].Rssi) > bestrssi) {
++ bestrssi = SCAN_RSSI(Adapter->ScanTable[i].Rssi);
++ net = i;
++ }
++ } else {
++ if (net == -ENETUNREACH) {
++ net = j;
++ }
++ }
++ break;
++ case Wlan802_11AutoUnknown:
++ default:
++ /* Do not check compatibility if the mode requested is
++ * AutoUnknown. Allows generic find to work without
++ * verifying against the Adapter security settings
++ */
++ if (SCAN_RSSI(Adapter->ScanTable[i].Rssi) > bestrssi) {
++ bestrssi = SCAN_RSSI(Adapter->ScanTable[i].Rssi);
++ net = i;
++ }
++ break;
++ }
++ }
++ }
++ if (net >= 0) {
++ if (find_cfp_by_band_and_channel
++ (Adapter, 0, Adapter->ScanTable[net].Channel) == NULL) {
++ net = -ENETUNREACH;
++ }
++ }
++ return net;
++}
++
++/**
++ * @brief This function finds the best SSID in the Scan List
++ *
++ * Search the scan table for the best SSID that also matches the current
++ * adapter network preference (infrastructure or adhoc)
++ *
++ * @param Adapter A pointer to wlan_adapter
++ *
++ * @return index in BSSID list
++ */
++int
++FindBestSSIDInList(wlan_adapter * Adapter)
++{
++ int mode = Adapter->InfrastructureMode;
++ int bestnet = -ENETUNREACH;
++ u8 bestrssi = 0;
++ int i;
++
++ ENTER();
++
++ PRINTM(INFO, "Num of BSSIDs = %d\n", Adapter->NumInScanTable);
++
++ for (i = 0; i < Adapter->NumInScanTable; i++) {
++ switch (mode) {
++ case Wlan802_11Infrastructure:
++ case Wlan802_11IBSS:
++ if (IsNetworkCompatible(Adapter, i, mode) >= 0) {
++ if (SCAN_RSSI(Adapter->ScanTable[i].Rssi) > bestrssi) {
++ bestrssi = SCAN_RSSI(Adapter->ScanTable[i].Rssi);
++ bestnet = i;
++ }
++ }
++ break;
++ case Wlan802_11AutoUnknown:
++ default:
++ if (SCAN_RSSI(Adapter->ScanTable[i].Rssi) > bestrssi) {
++ bestrssi = SCAN_RSSI(Adapter->ScanTable[i].Rssi);
++ bestnet = i;
++ }
++ break;
++ }
++ }
++
++ LEAVE();
++ return bestnet;
++}
++
++/**
++ * @brief Find the AP with specific ssid in the scan list
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pSSID A pointer to AP's ssid
++ *
++ * @return WLAN_STATUS_SUCCESS--success, otherwise--fail
++ */
++int
++FindBestNetworkSsid(wlan_private * priv, WLAN_802_11_SSID * pSSID)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ BSSDescriptor_t *pReqBSSID;
++ int i;
++
++ ENTER();
++
++ memset(pSSID, 0, sizeof(WLAN_802_11_SSID));
++
++ wlan_scan_networks(priv, NULL);
++
++ i = FindBestSSIDInList(Adapter);
++
++ if (i >= 0) {
++
++ pReqBSSID = &Adapter->ScanTable[i];
++ memcpy(pSSID, &pReqBSSID->Ssid, sizeof(WLAN_802_11_SSID));
++
++ /* Make sure we are in the right mode */
++ if (Adapter->InfrastructureMode == Wlan802_11AutoUnknown) {
++ Adapter->InfrastructureMode = pReqBSSID->InfrastructureMode;
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SNMP_MIB,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_INFRASTRUCTURE_MODE, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ }
++ }
++
++ if (!pSSID->SsidLength) {
++ ret = WLAN_STATUS_FAILURE;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Delete a specific indexed entry from the scan table.
++ *
++ * Delete the scan table entry indexed by tableIdx. Compact the remaining
++ * entries and adjust any buffering of beacon/probe response data
++ * if needed.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param tableIdx Scan table entry index to delete from the table
++ *
++ * @return void
++ *
++ * @pre tableIdx must be an index to a valid entry
++ */
++static void
++wlan_scan_delete_table_entry(wlan_private * priv, int tableIdx)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int delIdx;
++ uint beaconBufAdj;
++ u8 *pBeaconBuf;
++
++ /* Shift the saved beacon buffer data for the scan table back over the
++ * entry being removed. Update the end of buffer pointer. Save the
++ * deleted buffer allocation size for pointer adjustments for entries
++ * compacted after the deleted index.
++ */
++ beaconBufAdj = Adapter->ScanTable[tableIdx].beaconBufSizeMax;
++
++ PRINTM(INFO, "Scan: Delete Entry %d, beacon buffer removal = %d bytes\n",
++ tableIdx, beaconBufAdj);
++
++ /* Check if the table entry had storage allocated for its beacon */
++ if (beaconBufAdj) {
++ pBeaconBuf = Adapter->ScanTable[tableIdx].pBeaconBuf;
++
++ /* Remove the entry's buffer space, decrement the table end pointer
++ * by the amount we are removing
++ */
++ Adapter->pBeaconBufEnd -= beaconBufAdj;
++
++ PRINTM(INFO,
++ "Scan: Delete Entry %d, compact data: %p <- %p (sz = %d)\n",
++ tableIdx,
++ pBeaconBuf,
++ pBeaconBuf + beaconBufAdj,
++ Adapter->pBeaconBufEnd - pBeaconBuf);
++
++ /* Compact data storage. Copy all data after the deleted entry's
++ * end address (pBeaconBuf + beaconBufAdj) back to the original
++ * start address (pBeaconBuf).
++ *
++ * Scan table entries affected by the move will have their entry
++ * pointer adjusted below.
++ *
++ * Use memmove since the dest/src memory regions overlap.
++ */
++ memmove(pBeaconBuf,
++ pBeaconBuf + beaconBufAdj,
++ Adapter->pBeaconBufEnd - pBeaconBuf);
++ }
++
++ PRINTM(INFO, "Scan: Delete Entry %d, NumInScanTable = %d\n",
++ tableIdx, Adapter->NumInScanTable);
++
++ /* Shift all of the entries after the tableIdx back by one, compacting
++ * the table and removing the requested entry
++ */
++ for (delIdx = tableIdx; (delIdx + 1) < Adapter->NumInScanTable; delIdx++) {
++ /* Copy the next entry over this one */
++ memcpy(Adapter->ScanTable + delIdx,
++ Adapter->ScanTable + delIdx + 1, sizeof(BSSDescriptor_t));
++
++ /* Adjust this entry's pointer to its beacon buffer based on the
++ * removed/compacted entry from the deleted index. Don't decrement
++ * if the buffer pointer is NULL (no data stored for this entry).
++ */
++ if (Adapter->ScanTable[delIdx].pBeaconBuf) {
++ Adapter->ScanTable[delIdx].pBeaconBuf -= beaconBufAdj;
++ }
++ }
++
++ /* The last entry is invalid now that it has been deleted or moved back */
++ memset(Adapter->ScanTable + Adapter->NumInScanTable - 1,
++ 0x00, sizeof(BSSDescriptor_t));
++
++ Adapter->NumInScanTable--;
++}
++
++/**
++ * @brief Delete all occurrences of a given SSID from the scan table
++ *
++ * Iterate through the scan table and delete all entries that match a given
++ * SSID. Compact the remaining scan table entries.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pDelSSID Pointer to an SSID struct to use in deleting all
++ * matching SSIDs from the scan table
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ *
++ */
++static int
++wlan_scan_delete_ssid_table_entry(wlan_private * priv,
++ WLAN_802_11_SSID * pDelSSID)
++{
++ int tableIdx;
++ int retval = WLAN_STATUS_FAILURE;
++
++ ENTER();
++
++ PRINTM(INFO, "Scan: Delete Ssid Entry: %-32s\n", pDelSSID->Ssid);
++
++ /* If the requested SSID is found in the table, delete it. Then keep
++ * searching the table for multiple entires for the SSID until no
++ * more are found
++ */
++ while ((tableIdx = FindSSIDInList(priv->adapter,
++ pDelSSID,
++ NULL, Wlan802_11AutoUnknown)) >= 0) {
++ PRINTM(INFO, "Scan: Delete Ssid Entry: Found Idx = %d\n", tableIdx);
++ retval = WLAN_STATUS_SUCCESS;
++ wlan_scan_delete_table_entry(priv, tableIdx);
++ }
++
++ LEAVE();
++
++ return retval;
++}
++
++/**
++ * @brief Scan Network
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_set_scan(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ union iwreq_data wrqu;
++#if WIRELESS_EXT >= 18
++ struct iw_scan_req *req;
++ struct iw_point *dwrq = (struct iw_point *) vwrq;
++ wlan_ioctl_user_scan_cfg scanCfg;
++#endif
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++#ifdef REASSOCIATION
++ if (OS_ACQ_SEMAPHORE_BLOCK(&Adapter->ReassocSem)) {
++ PRINTM(ERROR, "Acquire semaphore error, wlan_set_scan\n");
++ return -EBUSY;
++ }
++#endif
++#if WIRELESS_EXT >= 18
++ if ((dwrq->flags & IW_SCAN_THIS_ESSID) &&
++ (dwrq->length == sizeof(struct iw_scan_req))) {
++ req = (struct iw_scan_req *) extra;
++ if (req->essid_len <= WLAN_MAX_SSID_LENGTH) {
++ memset(&scanCfg, 0x00, sizeof(scanCfg));
++ memcpy(scanCfg.ssidList[0].ssid, (u8 *) req->essid,
++ req->essid_len);
++ if (!wlan_scan_networks(priv, &scanCfg)) {
++ memset(&wrqu, 0, sizeof(union iwreq_data));
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWSCAN, &wrqu,
++ NULL);
++
++ }
++ }
++ } else {
++#endif
++
++ if (!wlan_scan_networks(priv, NULL)) {
++ memset(&wrqu, 0, sizeof(union iwreq_data));
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWSCAN, &wrqu,
++ NULL);
++
++ }
++#if WIRELESS_EXT >= 18
++ }
++#endif
++
++#ifdef REASSOCIATION
++ OS_REL_SEMAPHORE(&Adapter->ReassocSem);
++#endif
++
++ if (Adapter->SurpriseRemoved)
++ return WLAN_STATUS_FAILURE;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Send a scan command for all available channels filtered on a spec
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pRequestedSSID A pointer to AP's ssid
++ *
++ * @return WLAN_STATUS_SUCCESS-success, otherwise fail
++ */
++int
++SendSpecificSSIDScan(wlan_private * priv, WLAN_802_11_SSID * pRequestedSSID)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_ioctl_user_scan_cfg scanCfg;
++
++ ENTER();
++
++ if (pRequestedSSID == NULL) {
++ return WLAN_STATUS_FAILURE;
++ }
++
++ wlan_scan_delete_ssid_table_entry(priv, pRequestedSSID);
++
++ memset(&scanCfg, 0x00, sizeof(scanCfg));
++
++ memcpy(scanCfg.ssidList[0].ssid,
++ pRequestedSSID->Ssid, pRequestedSSID->SsidLength);
++ scanCfg.keepPreviousScan = TRUE;
++
++ wlan_scan_networks(priv, &scanCfg);
++
++ if (Adapter->SurpriseRemoved)
++ return WLAN_STATUS_FAILURE;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief scan an AP with specific BSSID
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param bssid A pointer to AP's bssid
++ *
++ * @return WLAN_STATUS_SUCCESS-success, otherwise fail
++ */
++int
++SendSpecificBSSIDScan(wlan_private * priv, u8 * bssid)
++{
++ wlan_ioctl_user_scan_cfg scanCfg;
++
++ ENTER();
++
++ if (bssid == NULL) {
++ return WLAN_STATUS_FAILURE;
++ }
++
++ memset(&scanCfg, 0x00, sizeof(scanCfg));
++ memcpy(scanCfg.specificBSSID, bssid, sizeof(scanCfg.specificBSSID));
++ scanCfg.keepPreviousScan = TRUE;
++
++ wlan_scan_networks(priv, &scanCfg);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Retrieve the scan table entries via wireless tools IOCTL call
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param dwrq A pointer to iw_point structure
++ * @param extra A pointer to extra data buf
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_get_scan(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ char *current_ev = extra;
++ char *end_buf = extra + IW_SCAN_MAX_DATA;
++ CHANNEL_FREQ_POWER *cfp;
++ BSSDescriptor_t *pScanTable;
++ char *current_val; /* For rates */
++ struct iw_event iwe; /* Temporary buffer */
++ int i;
++ int j;
++ int rate;
++
++ u8 buf[16 + 256 * 2];
++ u8 *ptr;
++ u8 *pRawData;
++#define PERFECT_RSSI ((u8)50)
++#define WORST_RSSI ((u8)0)
++#define RSSI_DIFF ((u8)(PERFECT_RSSI - WORST_RSSI))
++ u8 rssi;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ PRINTM(INFO, "Current Ssid: %-32s\n",
++ Adapter->CurBssParams.BSSDescriptor.Ssid.Ssid);
++ }
++
++ PRINTM(INFO, "Scan: Get: NumInScanTable = %d\n", Adapter->NumInScanTable);
++
++#if WIRELESS_EXT > 13
++ /* The old API using SIOCGIWAPLIST had a hard limit of IW_MAX_AP.
++ * The new API using SIOCGIWSCAN is only limited by buffer size
++ * WE-14 -> WE-16 the buffer is limited to IW_SCAN_MAX_DATA bytes
++ * which is 4096.
++ */
++ for (i = 0; i < Adapter->NumInScanTable; i++) {
++ if ((current_ev + MAX_SCAN_CELL_SIZE) >= end_buf) {
++ PRINTM(INFO, "i=%d break out: current_ev=%p end_buf=%p "
++ "MAX_SCAN_CELL_SIZE=%d\n",
++ i, current_ev, end_buf, MAX_SCAN_CELL_SIZE);
++ break;
++ }
++
++ pScanTable = &Adapter->ScanTable[i];
++
++ PRINTM(INFO, "i=%d Ssid: %-32s\n", i, pScanTable->Ssid.Ssid);
++
++ cfp =
++ find_cfp_by_band_and_channel(Adapter, 0,
++ (u16) pScanTable->Channel);
++ if (!cfp) {
++ PRINTM(INFO, "Invalid channel number %d\n", pScanTable->Channel);
++ continue;
++ }
++
++ if (ssid_valid(&Adapter->ScanTable[i].Ssid) == FALSE) {
++ continue;
++ }
++
++ /* First entry *MUST* be the AP MAC address */
++ iwe.cmd = SIOCGIWAP;
++ iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
++ memcpy(iwe.u.ap_addr.sa_data,
++ &Adapter->ScanTable[i].MacAddress, ETH_ALEN);
++
++ iwe.len = IW_EV_ADDR_LEN;
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, iwe.len);
++
++ //Add the ESSID
++ iwe.u.data.length = Adapter->ScanTable[i].Ssid.SsidLength;
++
++ if (iwe.u.data.length > 32) {
++ iwe.u.data.length = 32;
++ }
++
++ iwe.cmd = SIOCGIWESSID;
++ iwe.u.essid.flags = (i + 1) & IW_ENCODE_INDEX;
++ iwe.len = IW_EV_POINT_LEN + iwe.u.data.length;
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe,
++ (s8 *) Adapter->ScanTable[i].Ssid.
++ Ssid);
++
++ //Add mode
++ iwe.cmd = SIOCGIWMODE;
++ iwe.u.mode = Adapter->ScanTable[i].InfrastructureMode + 1;
++ iwe.len = IW_EV_UINT_LEN;
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, iwe.len);
++
++ //frequency
++ iwe.cmd = SIOCGIWFREQ;
++ iwe.u.freq.m = (long) cfp->Freq * 100000;
++ iwe.u.freq.e = 1;
++ iwe.len = IW_EV_FREQ_LEN;
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, iwe.len);
++
++ /* Add quality statistics */
++ iwe.cmd = IWEVQUAL;
++ iwe.u.qual.updated = IW_QUAL_ALL_UPDATED;
++ iwe.u.qual.level = SCAN_RSSI(Adapter->ScanTable[i].Rssi);
++
++ rssi = iwe.u.qual.level - MRVDRV_NF_DEFAULT_SCAN_VALUE;
++ iwe.u.qual.qual =
++ (100 * RSSI_DIFF * RSSI_DIFF - (PERFECT_RSSI - rssi) *
++ (15 * (RSSI_DIFF) + 62 * (PERFECT_RSSI - rssi))) /
++ (RSSI_DIFF * RSSI_DIFF);
++ if (iwe.u.qual.qual > 100)
++ iwe.u.qual.qual = 100;
++
++ if (Adapter->NF[TYPE_BEACON][TYPE_NOAVG] == 0) {
++ iwe.u.qual.noise = MRVDRV_NF_DEFAULT_SCAN_VALUE;
++ } else {
++ iwe.u.qual.noise = CAL_NF(Adapter->NF[TYPE_BEACON][TYPE_NOAVG]);
++ }
++ if ((Adapter->InfrastructureMode == Wlan802_11IBSS) &&
++ !SSIDcmp(&Adapter->CurBssParams.BSSDescriptor.Ssid,
++ &Adapter->ScanTable[i].Ssid)
++ && Adapter->AdhocCreate) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RSSI,
++ 0, HostCmd_OPTION_WAITFORRSP, 0,
++ NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ iwe.u.qual.level =
++ CAL_RSSI(Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE,
++ Adapter->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE);
++ }
++
++ iwe.len = IW_EV_QUAL_LEN;
++ current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, iwe.len);
++
++ /* Add encryption capability */
++ iwe.cmd = SIOCGIWENCODE;
++ if (Adapter->ScanTable[i].Privacy) {
++ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
++ } else {
++ iwe.u.data.flags = IW_ENCODE_DISABLED;
++ }
++ iwe.u.data.length = 0;
++ iwe.len = IW_EV_POINT_LEN + iwe.u.data.length;
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, NULL);
++
++ current_val = current_ev + IW_EV_LCP_LEN;
++
++ iwe.cmd = SIOCGIWRATE;
++
++ iwe.u.bitrate.fixed = 0;
++ iwe.u.bitrate.disabled = 0;
++ iwe.u.bitrate.value = 0;
++
++ /* Bit rate given in 500 kb/s units (+ 0x80) */
++ for (j = 0; j < sizeof(Adapter->ScanTable[i].SupportedRates); j++) {
++ if (Adapter->ScanTable[i].SupportedRates[j] == 0) {
++ break;
++ }
++ rate = (Adapter->ScanTable[i].SupportedRates[j] & 0x7F) * 500000;
++ if (rate > iwe.u.bitrate.value) {
++ iwe.u.bitrate.value = rate;
++ }
++
++ iwe.u.bitrate.value = (Adapter->ScanTable[i].SupportedRates[j]
++ & 0x7f) * 500000;
++ iwe.len = IW_EV_PARAM_LEN;
++ current_ev =
++ iwe_stream_add_value(current_ev, current_val, end_buf, &iwe,
++ iwe.len);
++
++ }
++ if ((Adapter->ScanTable[i].InfrastructureMode == Wlan802_11IBSS) &&
++ !SSIDcmp(&Adapter->CurBssParams.BSSDescriptor.Ssid,
++ &Adapter->ScanTable[i].Ssid)
++ && Adapter->AdhocCreate) {
++ iwe.u.bitrate.value = 22 * 500000;
++ }
++ iwe.len = IW_EV_PARAM_LEN;
++ current_ev = iwe_stream_add_value(current_ev, current_val, end_buf,
++ &iwe, iwe.len);
++
++ /* Add new value to event */
++ current_val = current_ev + IW_EV_LCP_LEN;
++
++ if (Adapter->ScanTable[i].rsnIE.IeeeHdr.ElementId == RSN_IE) {
++ pRawData = (u8 *) & Adapter->ScanTable[i].rsnIE;
++ memset(&iwe, 0, sizeof(iwe));
++ memset(buf, 0, sizeof(buf));
++ ptr = buf;
++#if WIRELESS_EXT >= 18
++ memcpy(buf, pRawData,
++ Adapter->ScanTable[i].rsnIE.IeeeHdr.Len + 2);
++ iwe.cmd = IWEVGENIE;
++ iwe.u.data.length = Adapter->ScanTable[i].rsnIE.IeeeHdr.Len + 2;
++#else
++ ptr += sprintf(ptr, "rsn_ie=");
++
++ for (j = 0;
++ j < (Adapter->ScanTable[i].rsnIE.IeeeHdr.Len
++ + sizeof(IEEEtypes_Header_t)); j++) {
++ ptr += sprintf(ptr, "%02x", *(pRawData + j));
++ }
++ iwe.u.data.length = strlen(buf);
++
++ PRINTM(INFO, "iwe.u.data.length %d\n", iwe.u.data.length);
++ PRINTM(INFO, "WPA2 BUF: %s \n", buf);
++
++ iwe.cmd = IWEVCUSTOM;
++#endif
++ iwe.len = IW_EV_POINT_LEN + iwe.u.data.length;
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++ }
++ if (Adapter->ScanTable[i].wpaIE.VendHdr.ElementId == WPA_IE) {
++ pRawData = (u8 *) & Adapter->ScanTable[i].wpaIE;
++ memset(&iwe, 0, sizeof(iwe));
++ memset(buf, 0, sizeof(buf));
++ ptr = buf;
++#if WIRELESS_EXT >= 18
++ memcpy(buf, pRawData,
++ Adapter->ScanTable[i].wpaIE.VendHdr.Len + 2);
++ iwe.cmd = IWEVGENIE;
++ iwe.u.data.length = Adapter->ScanTable[i].wpaIE.VendHdr.Len + 2;
++#else
++ ptr += sprintf(ptr, "wpa_ie=");
++
++ for (j = 0;
++ j < (Adapter->ScanTable[i].wpaIE.VendHdr.Len
++ + sizeof(IEEEtypes_Header_t)); j++) {
++ ptr += sprintf(ptr, "%02x", *(pRawData + j));
++ }
++ iwe.u.data.length = strlen(buf);
++
++ PRINTM(INFO, "iwe.u.data.length %d\n", iwe.u.data.length);
++ PRINTM(INFO, "WPA BUF: %s \n", buf);
++
++ iwe.cmd = IWEVCUSTOM;
++#endif
++ iwe.len = IW_EV_POINT_LEN + iwe.u.data.length;
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++ }
++ if (Adapter->ScanTable[i].wpsIE.VendHdr.ElementId == WPS_IE) {
++ pRawData = (u8 *) & Adapter->ScanTable[i].wpsIE;
++ memset(&iwe, 0, sizeof(iwe));
++ memset(buf, 0, sizeof(buf));
++ ptr = buf;
++ ptr += sprintf(ptr, "wps_ie=");
++
++ for (j = 0;
++ j < (Adapter->ScanTable[i].wpsIE.VendHdr.Len
++ + sizeof(IEEEtypes_Header_t)); j++) {
++ ptr += sprintf(ptr, "%02x", *(pRawData + j));
++ }
++ iwe.u.data.length = strlen(buf);
++
++ PRINTM(INFO, "iwe.u.data.length %d\n", iwe.u.data.length);
++ PRINTM(INFO, "WPS BUF: %s \n", buf);
++
++ iwe.cmd = IWEVCUSTOM;
++ iwe.len = IW_EV_POINT_LEN + iwe.u.data.length;
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++ }
++
++#if WIRELESS_EXT > 14
++
++ if (Adapter->ScanTable[i].extra_ie != 0) {
++ memset(&iwe, 0, sizeof(iwe));
++ memset(buf, 0, sizeof(buf));
++ ptr = buf;
++ ptr += sprintf(ptr, "extra_ie");
++ iwe.u.data.length = strlen(buf);
++
++ PRINTM(INFO, "iwe.u.data.length %d\n", iwe.u.data.length);
++ PRINTM(INFO, "BUF: %s \n", buf);
++
++ iwe.cmd = IWEVCUSTOM;
++ iwe.len = IW_EV_POINT_LEN + iwe.u.data.length;
++ current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, buf);
++ }
++#endif
++
++ current_val = current_ev + IW_EV_LCP_LEN;
++
++ /*
++ * Check if we added any event
++ */
++ if ((current_val - current_ev) > IW_EV_LCP_LEN)
++ current_ev = current_val;
++ }
++
++ dwrq->length = (current_ev - extra);
++ dwrq->flags = 0;
++
++ LEAVE();
++#endif
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Create a wlan_ioctl_get_scan_table_entry for a given BSS
++ * Descriptor for inclusion in the ioctl response to the user space
++ * application.
++ *
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pBSSDesc Pointer to a BSS entry in the scan table to form
++ * scan response from for delivery to the application layer
++ * @param ppBuffer Output parameter: Buffer used to output scan return struct
++ * @param pSpaceLeft Output parameter: Number of bytes available in the
++ * response buffer.
++ *
++ * @return WLAN_STATUS_SUCCESS, or < 0 with IOCTL error code
++ */
++static int
++wlan_get_scan_table_ret_entry(wlan_private * priv,
++ BSSDescriptor_t * pBSSDesc,
++ u8 ** ppBuffer, int *pSpaceLeft)
++{
++ wlan_adapter *Adapter;
++ wlan_ioctl_get_scan_table_entry *pRspEntry;
++ wlan_ioctl_get_scan_table_entry tmpRspEntry;
++ int spaceNeeded;
++ u8 *pCurrent;
++ int variableSize;
++
++ const int fixedSize = (sizeof(tmpRspEntry.fixedFieldLength)
++ + sizeof(tmpRspEntry.fixedFields)
++ + sizeof(tmpRspEntry.bssInfoLength));
++
++ ENTER();
++
++ Adapter = priv->adapter;
++ pCurrent = *ppBuffer;
++
++ /* The variable size returned is the stored beacon size */
++ variableSize = pBSSDesc->beaconBufSize;
++
++ /* If we stored a beacon and its size was zero, set the variable
++ * size return value to the size of the brief scan response
++ * wlan_scan_create_brief_table_entry creates. Also used if
++ * we are not configured to store beacons in the first place
++ */
++ if (variableSize == 0) {
++ variableSize = pBSSDesc->Ssid.SsidLength + 2;
++ variableSize += (sizeof(pBSSDesc->BeaconPeriod)
++ + sizeof(pBSSDesc->TimeStamp)
++ + sizeof(pBSSDesc->Cap));
++ if (pBSSDesc->wmmIE.VendHdr.ElementId == WMM_IE) {
++ variableSize += (sizeof(IEEEtypes_Header_t)
++ + pBSSDesc->wmmIE.VendHdr.Len);
++ }
++
++ if (pBSSDesc->wpaIE.VendHdr.ElementId == WPA_IE) {
++ variableSize += (sizeof(IEEEtypes_Header_t)
++ + pBSSDesc->wpaIE.VendHdr.Len);
++ }
++
++ if (pBSSDesc->rsnIE.IeeeHdr.ElementId == RSN_IE) {
++ variableSize += (sizeof(IEEEtypes_Header_t)
++ + pBSSDesc->rsnIE.IeeeHdr.Len);
++ }
++ }
++
++ spaceNeeded = fixedSize + variableSize;
++
++ PRINTM(INFO, "GetScanTable: need(%d), left(%d)\n",
++ spaceNeeded, *pSpaceLeft);
++
++ if (spaceNeeded >= *pSpaceLeft) {
++ *pSpaceLeft = 0;
++ LEAVE();
++ return -E2BIG;
++ }
++
++ *pSpaceLeft -= spaceNeeded;
++
++ tmpRspEntry.fixedFieldLength = sizeof(pRspEntry->fixedFields);
++
++ memcpy(tmpRspEntry.fixedFields.bssid,
++ pBSSDesc->MacAddress, sizeof(pRspEntry->fixedFields.bssid));
++
++ tmpRspEntry.fixedFields.rssi = pBSSDesc->Rssi;
++ tmpRspEntry.fixedFields.channel = pBSSDesc->Channel;
++ tmpRspEntry.fixedFields.networkTSF = pBSSDesc->networkTSF;
++ tmpRspEntry.bssInfoLength = variableSize;
++
++ /*
++ * Copy fixed fields to user space
++ */
++ if (copy_to_user(pCurrent, &tmpRspEntry, fixedSize)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ LEAVE();
++ return -EFAULT;
++ }
++
++ pCurrent += fixedSize;
++
++ if (pBSSDesc->pBeaconBuf) {
++ /*
++ * Copy variable length elements to user space
++ */
++ if (copy_to_user(pCurrent, pBSSDesc->pBeaconBuf,
++ pBSSDesc->beaconBufSize)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ LEAVE();
++ return -EFAULT;
++ }
++
++ pCurrent += pBSSDesc->beaconBufSize;
++ } else {
++ wlan_scan_create_brief_table_entry(&pCurrent, pBSSDesc);
++ }
++
++ *ppBuffer = pCurrent;
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Retrieve the scan response/beacon table
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_get_scan_table_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter;
++ BSSDescriptor_t *pBSSDesc;
++ wlan_ioctl_get_scan_table_info *pRspInfo;
++ int retcode;
++ int retlen;
++ int spaceLeft;
++ u8 *pCurrent;
++ u8 *pBufferEnd;
++ u32 scanStart;
++ u32 numScansDone;
++
++ numScansDone = 0;
++ retcode = WLAN_STATUS_SUCCESS;
++ Adapter = priv->adapter;
++
++ if (copy_from_user(&scanStart,
++ wrq->u.data.pointer, sizeof(scanStart)) != 0) {
++ /* copy_from_user failed */
++ PRINTM(INFO, "GetScanTable: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ pRspInfo = (wlan_ioctl_get_scan_table_info *) wrq->u.data.pointer;
++ pCurrent = pRspInfo->scan_table_entry_buffer;
++ pBufferEnd = wrq->u.data.pointer + wrq->u.data.length - 1;
++ spaceLeft = pBufferEnd - pCurrent;
++ PRINTM(INFO, "GetScanTable: scanStart req = %d\n", scanStart);
++ PRINTM(INFO, "GetScanTable: length avail = %d\n", wrq->u.data.length);
++
++ if (scanStart == 0) {
++ PRINTM(INFO, "GetScanTable: get current BSS Descriptor\n");
++
++ /* Use to get current association saved descriptor */
++ pBSSDesc = &Adapter->CurBssParams.BSSDescriptor;
++
++ retcode = wlan_get_scan_table_ret_entry(priv,
++ pBSSDesc,
++ &pCurrent, &spaceLeft);
++
++ if (retcode == WLAN_STATUS_SUCCESS) {
++ numScansDone = 1;
++ }
++
++ } else {
++ scanStart--;
++
++ while (spaceLeft
++ && (scanStart + numScansDone < Adapter->NumInScanTable)
++ && (retcode == WLAN_STATUS_SUCCESS)) {
++
++ pBSSDesc = &Adapter->ScanTable[scanStart + numScansDone];
++
++ PRINTM(INFO, "GetScanTable: get current BSS Descriptor [%d]\n",
++ scanStart + numScansDone);
++
++ retcode = wlan_get_scan_table_ret_entry(priv,
++ pBSSDesc,
++ &pCurrent, &spaceLeft);
++
++ if (retcode == WLAN_STATUS_SUCCESS) {
++ numScansDone++;
++ }
++ }
++ }
++
++ pRspInfo->scanNumber = numScansDone;
++ retlen = pCurrent - (u8 *) wrq->u.data.pointer;
++
++ wrq->u.data.length = retlen;
++
++ /* Return retcode (EFAULT or E2BIG) in the case where no scan results were
++ * successfully encoded.
++ */
++
++ return (numScansDone ? WLAN_STATUS_SUCCESS : retcode);
++}
++
++/**
++ * @brief Update the scan entry TSF timestamps to reflect a new association
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param pNewBssDesc A pointer to the newly associated AP's scan table entry
++ *
++ * @return void
++ */
++void
++wlan_scan_update_tsf_timestamps(wlan_private * priv,
++ BSSDescriptor_t * pNewBssDesc)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int tableIdx;
++ u64 newTsfBase;
++ s64 tsfDelta;
++
++ memcpy(&newTsfBase, pNewBssDesc->TimeStamp, sizeof(newTsfBase));
++
++ tsfDelta = newTsfBase - pNewBssDesc->networkTSF;
++
++ PRINTM(INFO, "TSF: Update TSF timestamps, 0x%016llx -> 0x%016llx\n",
++ pNewBssDesc->networkTSF, newTsfBase);
++
++ for (tableIdx = 0; tableIdx < Adapter->NumInScanTable; tableIdx++) {
++ Adapter->ScanTable[tableIdx].networkTSF += tsfDelta;
++ }
++}
++
++/**
++ * @brief Private IOCTL entry to perform an app configured immediate scan
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure containing the
++ * wlan_ioctl_user_scan_cfg requesting this scan
++ *
++ * @return 0 if successful; IOCTL error code otherwise
++ */
++int
++wlan_set_user_scan_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_ioctl_user_scan_cfg scanReq;
++ int retcode;
++ union iwreq_data wrqu;
++
++#ifdef REASSOCIATION
++ if (OS_ACQ_SEMAPHORE_BLOCK(&priv->adapter->ReassocSem)) {
++ PRINTM(ERROR, "Acquire semaphore error, wlan_extscan_ioctl\n");
++ return -EBUSY;
++ }
++#endif
++
++ memset(&scanReq, 0x00, sizeof(scanReq));
++
++ if (copy_from_user(&scanReq,
++ wrq->u.data.pointer,
++ MIN(wrq->u.data.length, sizeof(scanReq))) != 0) {
++ /* copy_from_user failed */
++ PRINTM(INFO, "SetUserScan: copy from user failed\n");
++ retcode = -EFAULT;
++
++ } else {
++
++ retcode = wlan_scan_networks(priv, &scanReq);
++
++ memset(&wrqu, 0x00, sizeof(union iwreq_data));
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWSCAN, &wrqu, NULL);
++
++ }
++
++#ifdef REASSOCIATION
++ OS_REL_SEMAPHORE(&priv->adapter->ReassocSem);
++#endif
++
++ return retcode;
++}
++
++/**
++ * @brief Prepare a scan command to be sent to the firmware
++ *
++ * Use the wlan_scan_cmd_config sent to the command processing module in
++ * the PrepareAndSendCommand to configure a HostCmd_DS_802_11_SCAN command
++ * struct to send to firmware.
++ *
++ * The fixed fields specifying the BSS type and BSSID filters as well as a
++ * variable number/length of TLVs are sent in the command to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure to be sent to
++ * firmware with the HostCmd_DS_801_11_SCAN structure
++ * @param pdata_buf Void pointer cast of a wlan_scan_cmd_config struct used
++ * to set the fields/TLVs for the command sent to firmware
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ *
++ * @sa wlan_scan_create_channel_list
++ */
++int
++wlan_cmd_802_11_scan(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *pdata_buf)
++{
++ HostCmd_DS_802_11_SCAN *pScan = &cmd->params.scan;
++ wlan_scan_cmd_config *pScanCfg;
++
++ ENTER();
++
++ pScanCfg = (wlan_scan_cmd_config *) pdata_buf;
++
++ /* Set fixed field variables in scan command */
++ pScan->BSSType = pScanCfg->bssType;
++ memcpy(pScan->BSSID, pScanCfg->specificBSSID, sizeof(pScan->BSSID));
++ memcpy(pScan->TlvBuffer, pScanCfg->tlvBuffer, pScanCfg->tlvBufferLen);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_SCAN);
++
++ /* Size is equal to the sizeof(fixed portions) + the TLV len + header */
++ cmd->Size = wlan_cpu_to_le16(sizeof(pScan->BSSType)
++ + sizeof(pScan->BSSID)
++ + pScanCfg->tlvBufferLen + S_DS_GEN);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Store a beacon or probe response for a BSS returned in the scan
++ *
++ * Store a new scan response or an update for a previous scan response. New
++ * entries need to verify that they do not exceed the total amount of
++ * memory allocated for the table.
++
++ * Replacement entries need to take into consideration the amount of space
++ * currently allocated for the beacon/probe response and adjust the entry
++ * as needed.
++ *
++ * A small amount of extra pad (SCAN_BEACON_ENTRY_PAD) is generally reserved
++ * for an entry in case it is a beacon since a probe response for the
++ * network will by larger per the standard. This helps to reduce the
++ * amount of memory copying to fit a new probe response into an entry
++ * already occupied by a network's previously stored beacon.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param beaconIdx Index in the scan table to store this entry; may be
++ * replacing an older duplicate entry for this BSS
++ * @param numInTable Number of entries currently in the table
++ * @param pNewBeacon Pointer to the new beacon/probe response to save
++ *
++ * @return void
++ */
++void
++wlan_ret_802_11_scan_store_beacon(wlan_private * priv,
++ int beaconIdx,
++ int numInTable,
++ BSSDescriptor_t * pNewBeacon)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ u8 *pBcnStore;
++ int newBcnSize;
++ int oldBcnSize;
++ int bcnSpace;
++ int adjIdx;
++
++ if (Adapter->ScanTable[beaconIdx].pBeaconBuf != NULL) {
++
++ newBcnSize = pNewBeacon->beaconBufSize;
++ oldBcnSize = Adapter->ScanTable[beaconIdx].beaconBufSize;
++ bcnSpace = Adapter->ScanTable[beaconIdx].beaconBufSizeMax;
++ pBcnStore = Adapter->ScanTable[beaconIdx].pBeaconBuf;
++
++ /* Set the max to be the same as current entry unless changed below */
++ pNewBeacon->beaconBufSizeMax = bcnSpace;
++
++ if (newBcnSize == oldBcnSize) {
++ /*
++ * Beacon is the same size as the previous entry.
++ * Replace the previous contents with the scan result
++ */
++ memcpy(pBcnStore,
++ pNewBeacon->pBeaconBuf, pNewBeacon->beaconBufSize);
++
++ } else if (newBcnSize <= bcnSpace) {
++ /*
++ * New beacon size will fit in the amount of space
++ * we have previously allocated for it
++ */
++
++ /* Copy the new beacon buffer entry over the old one */
++ memcpy(pBcnStore, pNewBeacon->pBeaconBuf, newBcnSize);
++
++ /* If the old beacon size was less than the maximum
++ * we had alloted for the entry, and the new entry
++ * is even smaller, reset the max size to the old beacon
++ * entry and compress the storage space (leaving a new
++ * pad space of (oldBcnSize - newBcnSize).
++ */
++ if (oldBcnSize < bcnSpace && newBcnSize != bcnSpace) {
++ /*
++ * Old Beacon size is smaller than the alloted storage size.
++ * Shrink the alloted storage space.
++ */
++ PRINTM(INFO, "AppControl: Smaller Duplicate Beacon (%d), "
++ "old = %d, new = %d, space = %d, left = %d\n",
++ beaconIdx, oldBcnSize, newBcnSize, bcnSpace,
++ (sizeof(Adapter->beaconBuffer) -
++ (Adapter->pBeaconBufEnd - Adapter->beaconBuffer)));
++
++ /* memmove (since the memory overlaps) the data
++ * after the beacon we just stored to the end of
++ * the current beacon. This cleans up any unused
++ * space the old larger beacon was using in the buffer
++ */
++ memmove(pBcnStore + oldBcnSize,
++ pBcnStore + bcnSpace,
++ Adapter->pBeaconBufEnd - (pBcnStore + bcnSpace));
++
++ /* Decrement the end pointer by the difference between
++ * the old larger size and the new smaller size since
++ * we are using less space due to the new beacon being
++ * smaller
++ */
++ Adapter->pBeaconBufEnd -= (bcnSpace - oldBcnSize);
++
++ /* Set the maximum storage size to the old beacon size */
++ pNewBeacon->beaconBufSizeMax = oldBcnSize;
++
++ /* Adjust beacon buffer pointers that are past the current */
++ for (adjIdx = 0; adjIdx < numInTable; adjIdx++) {
++ if (Adapter->ScanTable[adjIdx].pBeaconBuf > pBcnStore) {
++ Adapter->ScanTable[adjIdx].pBeaconBuf
++ -= (bcnSpace - oldBcnSize);
++ }
++ }
++ }
++ } else if (Adapter->pBeaconBufEnd + (newBcnSize - bcnSpace)
++ < (Adapter->beaconBuffer + sizeof(Adapter->beaconBuffer))) {
++ /*
++ * Beacon is larger than space previously allocated (bcnSpace)
++ * and there is enough space left in the beaconBuffer to store
++ * the additional data
++ */
++ PRINTM(INFO, "AppControl: Larger Duplicate Beacon (%d), "
++ "old = %d, new = %d, space = %d, left = %d\n",
++ beaconIdx, oldBcnSize, newBcnSize, bcnSpace,
++ (sizeof(Adapter->beaconBuffer) -
++ (Adapter->pBeaconBufEnd - Adapter->beaconBuffer)));
++
++ /* memmove (since the memory overlaps) the data
++ * after the beacon we just stored to the end of
++ * the current beacon. This moves the data for
++ * the beacons after this further in memory to
++ * make space for the new larger beacon we are
++ * about to copy in.
++ */
++ memmove(pBcnStore + newBcnSize,
++ pBcnStore + bcnSpace,
++ Adapter->pBeaconBufEnd - (pBcnStore + bcnSpace));
++
++ /* Copy the new beacon buffer entry over the old one */
++ memcpy(pBcnStore, pNewBeacon->pBeaconBuf, newBcnSize);
++
++ /* Move the beacon end pointer by the amount of new
++ * beacon data we are adding
++ */
++ Adapter->pBeaconBufEnd += (newBcnSize - bcnSpace);
++
++ /* This entry is bigger than the alloted max space
++ * previously reserved. Increase the max space to
++ * be equal to the new beacon size
++ */
++ pNewBeacon->beaconBufSizeMax = newBcnSize;
++
++ /* Adjust beacon buffer pointers that are past the current */
++ for (adjIdx = 0; adjIdx < numInTable; adjIdx++) {
++ if (Adapter->ScanTable[adjIdx].pBeaconBuf > pBcnStore) {
++ Adapter->ScanTable[adjIdx].pBeaconBuf
++ += (newBcnSize - bcnSpace);
++ }
++ }
++ } else {
++ /*
++ * Beacon is larger than the previously allocated space, but
++ * there is not enough free space to store the additional data
++ */
++ PRINTM(INFO,
++ "AppControl: Failed: Larger Duplicate Beacon (%d),"
++ " old = %d, new = %d, space = %d, left = %d\n",
++ beaconIdx, oldBcnSize, newBcnSize, bcnSpace,
++ (sizeof(Adapter->beaconBuffer) -
++ (Adapter->pBeaconBufEnd - Adapter->beaconBuffer)));
++
++ /* Storage failure, keep old beacon intact */
++ pNewBeacon->beaconBufSize = oldBcnSize;
++ }
++
++ /* Point the new entry to its permanent storage space */
++ pNewBeacon->pBeaconBuf = pBcnStore;
++
++ } else {
++ /* No existing beacon data exists for this entry, check to see
++ * if we can fit it in the remaining space
++ */
++ if (Adapter->pBeaconBufEnd + pNewBeacon->beaconBufSize +
++ SCAN_BEACON_ENTRY_PAD < (Adapter->beaconBuffer +
++ sizeof(Adapter->beaconBuffer))) {
++
++ /* Copy the beacon buffer data from the local entry to the
++ * adapter dev struct buffer space used to store the raw
++ * beacon data for each entry in the scan table
++ */
++ memcpy(Adapter->pBeaconBufEnd, pNewBeacon->pBeaconBuf,
++ pNewBeacon->beaconBufSize);
++
++ /* Update the beacon ptr to point to the table save area */
++ pNewBeacon->pBeaconBuf = Adapter->pBeaconBufEnd;
++ pNewBeacon->beaconBufSizeMax = (pNewBeacon->beaconBufSize
++ + SCAN_BEACON_ENTRY_PAD);
++
++ /* Increment the end pointer by the size reserved */
++ Adapter->pBeaconBufEnd += pNewBeacon->beaconBufSizeMax;
++
++ PRINTM(INFO, "AppControl: Beacon[%02d] sz=%03d,"
++ " used = %04d, left = %04d\n",
++ beaconIdx,
++ pNewBeacon->beaconBufSize,
++ (Adapter->pBeaconBufEnd - Adapter->beaconBuffer),
++ (sizeof(Adapter->beaconBuffer) -
++ (Adapter->pBeaconBufEnd - Adapter->beaconBuffer)));
++ } else {
++ /*
++ * No space for new beacon
++ */
++ PRINTM(INFO, "AppControl: No space beacon (%d): "
++ "%02x:%02x:%02x:%02x:%02x:%02x; sz=%03d, left=%03d\n",
++ beaconIdx,
++ pNewBeacon->MacAddress[0], pNewBeacon->MacAddress[1],
++ pNewBeacon->MacAddress[2], pNewBeacon->MacAddress[3],
++ pNewBeacon->MacAddress[4], pNewBeacon->MacAddress[5],
++ pNewBeacon->beaconBufSize,
++ (sizeof(Adapter->beaconBuffer) -
++ (Adapter->pBeaconBufEnd - Adapter->beaconBuffer)));
++
++ /* Storage failure; clear storage records for this bcn */
++ pNewBeacon->pBeaconBuf = NULL;
++ pNewBeacon->beaconBufSize = 0;
++ pNewBeacon->beaconBufSizeMax = 0;
++ }
++ }
++}
++
++/**
++ * @brief This function handles the command response of scan
++ *
++ * The response buffer for the scan command has the following
++ * memory layout:
++ *
++ * .-----------------------------------------------------------.
++ * | Header (4 * sizeof(u16)): Standard command response hdr |
++ * .-----------------------------------------------------------.
++ * | BufSize (u16) : sizeof the BSS Description data |
++ * .-----------------------------------------------------------.
++ * | NumOfSet (u8) : Number of BSS Descs returned |
++ * .-----------------------------------------------------------.
++ * | BSSDescription data (variable, size given in BufSize) |
++ * .-----------------------------------------------------------.
++ * | TLV data (variable, size calculated using Header->Size, |
++ * | BufSize and sizeof the fixed fields above) |
++ * .-----------------------------------------------------------.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param resp A pointer to HostCmd_DS_COMMAND
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_ret_802_11_scan(wlan_private * priv, HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_SCAN_RSP *pScan;
++ BSSDescriptor_t newBssEntry;
++ MrvlIEtypes_Data_t *pTlv;
++ MrvlIEtypes_TsfTimestamp_t *pTsfTlv;
++ u8 *pBssInfo;
++ u16 scanRespSize;
++ int bytesLeft;
++ int numInTable;
++ int bssIdx;
++ int idx;
++ int tlvBufSize;
++ u64 tsfVal;
++ BOOLEAN bgScanResp;
++
++ ENTER();
++
++ bgScanResp = (resp->Command == HostCmd_RET_802_11_BG_SCAN_QUERY);
++ if (bgScanResp) {
++ pScan = &resp->params.bgscanqueryresp.scanresp;
++ } else {
++ pScan = &resp->params.scanresp;
++ }
++
++ if (pScan->NumberOfSets > MRVDRV_MAX_BSSID_LIST) {
++ PRINTM(INFO, "SCAN_RESP: Invalid number of AP returned (%d)!!\n",
++ pScan->NumberOfSets);
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ bytesLeft = wlan_le16_to_cpu(pScan->BSSDescriptSize);
++ PRINTM(INFO, "SCAN_RESP: BSSDescriptSize %d\n", bytesLeft);
++
++ scanRespSize = resp->Size;
++
++ PRINTM(CMND, "SCAN_RESP: returned %d APs before parsing\n",
++ pScan->NumberOfSets);
++
++ numInTable = Adapter->NumInScanTable;
++ pBssInfo = pScan->BssDescAndTlvBuffer;
++
++ /* The size of the TLV buffer is equal to the entire command response
++ * size (scanRespSize) minus the fixed fields (sizeof()'s), the
++ * BSS Descriptions (BSSDescriptSize as bytesLef) and the command
++ * response header (S_DS_GEN)
++ */
++ tlvBufSize = scanRespSize - (bytesLeft + sizeof(pScan->BSSDescriptSize)
++ + sizeof(pScan->NumberOfSets)
++ + S_DS_GEN);
++
++ pTlv = (MrvlIEtypes_Data_t *) (pScan->BssDescAndTlvBuffer + bytesLeft);
++
++ /* Search the TLV buffer space in the scan response for any valid TLVs */
++ wlan_ret_802_11_scan_get_tlv_ptrs(pTlv, tlvBufSize, &pTsfTlv);
++
++ /*
++ * Process each scan response returned (pScan->NumberOfSets). Save
++ * the information in the newBssEntry and then insert into the
++ * driver scan table either as an update to an existing entry
++ * or as an addition at the end of the table
++ */
++ for (idx = 0; idx < pScan->NumberOfSets && bytesLeft; idx++) {
++ /* Zero out the newBssEntry we are about to store info in */
++ memset(&newBssEntry, 0x00, sizeof(newBssEntry));
++
++ /* Process the data fields and IEs returned for this BSS */
++ if ((InterpretBSSDescriptionWithIE(&newBssEntry,
++ &pBssInfo,
++ &bytesLeft) == WLAN_STATUS_SUCCESS)
++ && CHECK_SSID_IS_VALID(&newBssEntry.Ssid)) {
++
++ PRINTM(INFO, "SCAN_RESP: BSSID = %02x:%02x:%02x:%02x:%02x:%02x\n",
++ newBssEntry.MacAddress[0], newBssEntry.MacAddress[1],
++ newBssEntry.MacAddress[2], newBssEntry.MacAddress[3],
++ newBssEntry.MacAddress[4], newBssEntry.MacAddress[5]);
++
++ /*
++ * Search the scan table for the same bssid
++ */
++ for (bssIdx = 0; bssIdx < numInTable; bssIdx++) {
++ if (memcmp(newBssEntry.MacAddress,
++ Adapter->ScanTable[bssIdx].MacAddress,
++ sizeof(newBssEntry.MacAddress)) == 0) {
++ /*
++ * If the SSID matches as well, it is a duplicate of
++ * this entry. Keep the bssIdx set to this
++ * entry so we replace the old contents in the table
++ */
++ if ((newBssEntry.Ssid.SsidLength ==
++ Adapter->ScanTable[bssIdx].Ssid.SsidLength)
++ && (memcmp(newBssEntry.Ssid.Ssid,
++ Adapter->ScanTable[bssIdx].Ssid.Ssid,
++ newBssEntry.Ssid.SsidLength) == 0)) {
++ PRINTM(INFO, "SCAN_RESP: Duplicate of index: %d\n",
++ bssIdx);
++ break;
++ }
++ }
++ }
++ /*
++ * If the bssIdx is equal to the number of entries in the table,
++ * the new entry was not a duplicate; append it to the scan
++ * table
++ */
++ if (bssIdx == numInTable) {
++ /* Range check the bssIdx, keep it limited to the last entry */
++ if (bssIdx == MRVDRV_MAX_BSSID_LIST) {
++ bssIdx--;
++ } else {
++ numInTable++;
++ }
++ }
++
++ /*
++ * Save the beacon/probe response returned for later application
++ * retrieval. Duplicate beacon/probe responses are updated if
++ * possible
++ */
++ wlan_ret_802_11_scan_store_beacon(priv,
++ bssIdx,
++ numInTable, &newBssEntry);
++ /*
++ * If the TSF TLV was appended to the scan results, save
++ * this entry's TSF value in the networkTSF field. The
++ * networkTSF is the firmware's TSF value at the time the
++ * beacon or probe response was received.
++ */
++ if (pTsfTlv) {
++ memcpy(&tsfVal, &pTsfTlv->tsfTable[idx], sizeof(tsfVal));
++ tsfVal = wlan_le64_to_cpu(tsfVal);
++
++ memcpy(&newBssEntry.networkTSF,
++ &tsfVal, sizeof(newBssEntry.networkTSF));
++ }
++
++ /* Copy the locally created newBssEntry to the scan table */
++ memcpy(&Adapter->ScanTable[bssIdx],
++ &newBssEntry, sizeof(Adapter->ScanTable[bssIdx]));
++
++ } else {
++
++ /* Error parsing/interpreting the scan response, skipped */
++ PRINTM(INFO, "SCAN_RESP: "
++ "InterpretBSSDescriptionWithIE returned ERROR\n");
++ }
++ }
++
++ PRINTM(CMND, "SCAN_RESP: Scanned %2d APs, %d valid, %d total\n",
++ pScan->NumberOfSets, numInTable - Adapter->NumInScanTable,
++ numInTable);
++
++ /* Update the total number of BSSIDs in the scan table */
++ Adapter->NumInScanTable = numInTable;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief scan network with specific ssid
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_extscan_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ WLAN_802_11_SSID Ext_Scan_SSID;
++ wlan_ioctl_user_scan_cfg scanCfg;
++ union iwreq_data wrqu;
++
++ ENTER();
++
++ if (copy_from_user(&Ext_Scan_SSID, req->ifr_data, sizeof(Ext_Scan_SSID))) {
++ PRINTM(INFO, "copy of SSID for ext scan from user failed \n");
++ LEAVE();
++ return -EFAULT;
++ }
++#ifdef REASSOCIATION
++ if (OS_ACQ_SEMAPHORE_BLOCK(&Adapter->ReassocSem)) {
++ PRINTM(ERROR, "Acquire semaphore error, wlan_extscan_ioctl\n");
++ return -EBUSY;
++ }
++#endif
++
++ memset(&scanCfg, 0x00, sizeof(scanCfg));
++
++ memcpy(scanCfg.ssidList[0].ssid, Ext_Scan_SSID.Ssid,
++ Ext_Scan_SSID.SsidLength);
++
++ wlan_scan_networks(priv, &scanCfg);
++
++ memset(&wrqu, 0, sizeof(union iwreq_data));
++ wireless_send_event(priv->wlan_dev.netdev, SIOCGIWSCAN, &wrqu, NULL);
++
++#ifdef REASSOCIATION
++ OS_REL_SEMAPHORE(&Adapter->ReassocSem);
++#endif
++
++ if (Adapter->SurpriseRemoved)
++ return WLAN_STATUS_FAILURE;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function sends BG_SCAN query command to firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++sendBgScanQueryCmd(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ /* Clear the previous scan result */
++ memset(Adapter->ScanTable, 0x00,
++ sizeof(BSSDescriptor_t) * MRVDRV_MAX_BSSID_LIST);
++ Adapter->NumInScanTable = 0;
++ Adapter->pBeaconBufEnd = Adapter->beaconBuffer;
++
++ return PrepareAndSendCommand(priv, HostCmd_CMD_802_11_BG_SCAN_QUERY,
++ 0, 0, 0, NULL);
++}
++
++/**
++ * @brief Enable/Disable BG Scan
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param enable TRUE-enable, FALSE-disable
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_bg_scan_enable(wlan_private * priv, BOOLEAN enable)
++{
++ int ret;
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_BG_SCAN_CONFIG,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, &enable);
++ return ret;
++}
++
++/**
++ * @brief config BGSCAN parameter
++
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_do_bg_scan_config_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 action;
++ u8 *buf = NULL;
++ HostCmd_DS_802_11_BG_SCAN_CONFIG *tmp;
++
++ ENTER();
++
++ action = *((u8 *) req->ifr_data + SKIP_CMDNUM + SKIP_SIZE);
++ PRINTM(INFO, "Action = %d\n", action);
++
++ switch (action) {
++ case HostCmd_ACT_GEN_GET:
++ buf = kmalloc(Adapter->bgScanConfigSize + SKIP_TYPE_SIZE, GFP_KERNEL);
++ if (!buf) {
++ PRINTM(MSG, "kmalloc no memory !!\n");
++ return -ENOMEM;
++ }
++ memcpy(buf, &Adapter->bgScanConfigSize, SKIP_SIZE);
++ memcpy(buf + SKIP_TYPE_SIZE, Adapter->bgScanConfig,
++ Adapter->bgScanConfigSize);
++
++ if (copy_to_user(req->ifr_data, buf,
++ Adapter->bgScanConfigSize + SKIP_TYPE_SIZE)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ kfree(buf);
++ return -EFAULT;
++ }
++
++ kfree(buf);
++
++ break;
++
++ case HostCmd_ACT_GEN_SET:
++ Adapter->bgScanConfigSize = *(u16 *) (req->ifr_data + SKIP_CMDNUM);
++ PRINTM(INFO, "bgscanConfigSize = %d\n", Adapter->bgScanConfigSize);
++
++ if (!(tmp = kmalloc(Adapter->bgScanConfigSize, GFP_KERNEL))) {
++ PRINTM(MSG, "kmalloc no memory !!\n");
++ Adapter->bgScanConfigSize = 0;
++ return -ENOMEM;
++ }
++
++ HEXDUMP("treq", req->ifr_data + SKIP_CMDNUM + SKIP_SIZE,
++ Adapter->bgScanConfigSize);
++
++ if (copy_from_user(tmp, req->ifr_data + SKIP_CMDNUM + SKIP_SIZE,
++ Adapter->bgScanConfigSize)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ kfree(tmp);
++ return -EFAULT;
++ }
++
++ if (Adapter->bgScanConfig) {
++ tmp->Enable = Adapter->bgScanConfig->Enable;
++ buf = (u8 *) Adapter->bgScanConfig;
++ }
++ Adapter->bgScanConfig = tmp;
++ if (buf)
++ kfree(buf);
++
++ break;
++ }
++
++ LEAVE();
++
++ return ret;
++}
++
++/**
++ * @brief This function prepares command of bg_scan_config.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ * @param cmd_action the action: GET or SET
++ * @param pdata_buf A pointer to data buffer
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_802_11_bg_scan_config(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ int cmd_action, void *pdata_buf)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_BG_SCAN_CONFIG *bgcfg = &cmd->params.bgscancfg;
++ BOOLEAN enable = *((BOOLEAN *) pdata_buf);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_BG_SCAN_CONFIG);
++ cmd->Size =
++ wlan_cpu_to_le16((priv->adapter->bgScanConfigSize) + S_DS_GEN);
++
++ Adapter->bgScanConfig->Enable = enable;
++
++ memcpy(bgcfg, Adapter->bgScanConfig, Adapter->bgScanConfigSize);
++
++ bgcfg->Action = wlan_cpu_to_le16(bgcfg->Action);
++ bgcfg->ScanInterval = wlan_cpu_to_le32(bgcfg->ScanInterval);
++ bgcfg->StoreCondition = wlan_cpu_to_le32(bgcfg->StoreCondition);
++ bgcfg->ReportConditions = wlan_cpu_to_le32(bgcfg->ReportConditions);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief This function prepares command of bg_scan_query.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param cmd A pointer to HostCmd_DS_COMMAND structure
++ *
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_cmd_802_11_bg_scan_query(wlan_private * priv, HostCmd_DS_COMMAND * cmd)
++{
++ HostCmd_DS_802_11_BG_SCAN_QUERY *bgquery = &cmd->params.bgscanquery;
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_802_11_BG_SCAN_QUERY);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_802_11_BG_SCAN_QUERY) + S_DS_GEN);
++
++ bgquery->Flush = 1;
++
++ return WLAN_STATUS_SUCCESS;
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_scan.h b/drivers/net/wireless/marvell8686/wlan_scan.h
+new file mode 100644
+index 0000000..2274cd3
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_scan.h
+@@ -0,0 +1,284 @@
++/** @file wlan_scan.h
++ *
++ * @brief Interface for the wlan network scan routines
++ *
++ * Driver interface functions and type declarations for the scan module
++ * implemented in wlan_scan.c.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ *
++ * @sa wlan_scan.c
++ */
++/*************************************************************
++Change Log:
++ 01/11/06: Initial revision. New scan code, relocate related functions
++
++************************************************************/
++
++#ifndef _WLAN_SCAN_H
++#define _WLAN_SCAN_H
++
++//! Infrastructure BSS scan type in wlan_scan_cmd_config
++#define WLAN_SCAN_BSS_TYPE_BSS 1
++
++//! Adhoc BSS scan type in wlan_scan_cmd_config
++#define WLAN_SCAN_BSS_TYPE_IBSS 2
++
++//! Adhoc or Infrastructure BSS scan type in wlan_scan_cmd_config, no filter
++#define WLAN_SCAN_BSS_TYPE_ANY 3
++
++/** @brief Maximum buffer space for beacons retrieved from scan responses
++ * 4000 has successfully stored up to 40 beacons
++ * 6000 has successfully stored the max scan results (max 64)
++ */
++#define MAX_SCAN_BEACON_BUFFER 6000
++
++/**
++ * @brief Buffer pad space for newly allocated beacons/probe responses
++ *
++ * Beacons are typically 6 bytes longer than an equivalent probe response.
++ * For each scan response stored, allocate an extra byte pad at the end to
++ * allow easy expansion to store a beacon in the same memory a probe reponse
++ * previously contained
++ */
++#define SCAN_BEACON_ENTRY_PAD 6
++
++//! Scan time specified in the channel TLV for each channel for passive scans
++#define MRVDRV_PASSIVE_SCAN_CHAN_TIME 100
++
++//! Scan time specified in the channel TLV for each channel for active scans
++#define MRVDRV_ACTIVE_SCAN_CHAN_TIME 100
++
++//! Scan time specified in the channel TLV for each channel for specific scans
++#define MRVDRV_SPECIFIC_SCAN_CHAN_TIME 100
++
++//! Max passive scan time for each channel in milliseconds
++#define MRVDRV_MAX_PASSIVE_SCAN_CHAN_TIME 2000
++
++//! Max active scan time for each channel in milliseconds
++#define MRVDRV_MAX_ACTIVE_SCAN_CHAN_TIME 500
++
++/**
++ * Max total scan time in milliseconds
++ * The total scan time should be less than scan command timeout value (10s)
++ */
++#define MRVDRV_MAX_TOTAL_SCAN_TIME (MRVDRV_TIMER_10S - MRVDRV_TIMER_1S)
++
++/**
++ * @brief Structure used internally in the wlan driver to configure a scan.
++ *
++ * Sent to the command processing module to configure the firmware
++ * scan command prepared by wlan_cmd_802_11_scan.
++ *
++ * @sa wlan_scan_networks
++ *
++ */
++typedef struct
++{
++ /**
++ * @brief BSS Type to be sent in the firmware command
++ *
++ * Field can be used to restrict the types of networks returned in the
++ * scan. Valid settings are:
++ *
++ * - WLAN_SCAN_BSS_TYPE_BSS (infrastructure)
++ * - WLAN_SCAN_BSS_TYPE_IBSS (adhoc)
++ * - WLAN_SCAN_BSS_TYPE_ANY (unrestricted, adhoc and infrastructure)
++ */
++ u8 bssType;
++
++ /**
++ * @brief Specific BSSID used to filter scan results in the firmware
++ */
++ u8 specificBSSID[MRVDRV_ETH_ADDR_LEN];
++
++ /**
++ * @brief Length of TLVs sent in command starting at tlvBuffer
++ */
++ int tlvBufferLen;
++
++ /**
++ * @brief SSID TLV(s) and ChanList TLVs to be sent in the firmware command
++ *
++ * @sa TLV_TYPE_CHANLIST, MrvlIEtypes_ChanListParamSet_t
++ * @sa TLV_TYPE_SSID, MrvlIEtypes_SsIdParamSet_t
++ */
++ u8 tlvBuffer[1]; //!< SSID TLV(s) and ChanList TLVs are stored here
++} wlan_scan_cmd_config;
++
++/**
++ * @brief Sub-structure passed in wlan_ioctl_get_scan_table_entry for each BSS
++ *
++ * Fixed field information returned for the scan response in the IOCTL
++ * response.
++ */
++typedef struct
++{
++ u8 bssid[6]; //!< BSSID of this network
++ u8 channel; //!< Channel this beacon/probe response was detected
++ u8 rssi; //!< RSSI for the received packet
++ u64 networkTSF; //!< TSF value from the firmware at packet reception
++} __ATTRIB_PACK__ wlan_ioctl_get_scan_table_fixed;
++
++/**
++ * @brief Structure passed in the wlan_ioctl_get_scan_table_info for each
++ * BSS returned in the WLAN_GET_SCAN_RESP IOCTL
++ *
++ * @sa wlan_get_scan_table_ioctl
++ */
++typedef struct
++{
++
++ /**
++ * @brief Fixed field length included in the response.
++ *
++ * Length value is included so future fixed fields can be added to the
++ * response without breaking backwards compatibility. Use the length
++ * to find the offset for the bssInfoLength field, not a sizeof() calc.
++ */
++ u32 fixedFieldLength;
++
++ /**
++ * @brief Always present, fixed length data fields for the BSS
++ */
++ wlan_ioctl_get_scan_table_fixed fixedFields;
++
++ /**
++ * @brief Length of the BSS Information (probe resp or beacon) that
++ * follows starting at bssInfoBuffer
++ */
++ u32 bssInfoLength;
++
++ /**
++ * @brief Probe response or beacon scanned for the BSS.
++ *
++ * Field layout:
++ * - TSF 8 octets
++ * - Beacon Interval 2 octets
++ * - Capability Info 2 octets
++ *
++ * - IEEE Infomation Elements; variable number & length per 802.11 spec
++ */
++ u8 bssInfoBuffer[1];
++} __ATTRIB_PACK__ wlan_ioctl_get_scan_table_entry;
++
++/**
++ * @brief WLAN_GET_SCAN_RESP private IOCTL struct to retrieve the scan table
++ *
++ * @sa wlan_get_scan_table_ioctl
++ */
++typedef struct
++{
++
++ /**
++ * - Zero based scan entry to start retrieval in command request
++ * - Number of scans entires returned in command response
++ */
++ u32 scanNumber;
++
++ /**
++ * Buffer marker for multiple wlan_ioctl_get_scan_table_entry structures.
++ * Each struct is padded to the nearest 32 bit boundary.
++ */
++ u8 scan_table_entry_buffer[1];
++
++} __ATTRIB_PACK__ wlan_ioctl_get_scan_table_info;
++
++/**
++ * @brief Structure used to store information for each beacon/probe response
++ */
++typedef struct
++{
++ WLAN_802_11_MAC_ADDRESS MacAddress;
++
++ WLAN_802_11_SSID Ssid;
++
++ /* WEP encryption requirement */
++ u32 Privacy;
++
++ /* receive signal strength in dBm */
++ WLAN_802_11_RSSI Rssi;
++
++ u32 Channel;
++
++ u16 BeaconPeriod;
++
++ u32 ATIMWindow;
++ u8 ERPFlags;
++
++ WLAN_802_11_NETWORK_TYPE NetworkTypeInUse;
++ WLAN_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
++ WLAN_802_11_RATES SupportedRates;
++ IEEEtypes_WmmParameter_t wmmIE;
++
++ int extra_ie;
++
++ u8 TimeStamp[8]; //!< TSF value included in the beacon/probe response
++
++ IEEEtypes_PhyParamSet_t PhyParamSet;
++ IEEEtypes_SsParamSet_t SsParamSet;
++ IEEEtypes_CapInfo_t Cap;
++
++ u8 DataRates[WLAN_SUPPORTED_RATES];
++
++ u64 networkTSF; //!< TSF timestamp from the current firmware TSF
++
++ IEEEtypes_CountryInfoFullSet_t CountryInfo;
++
++ IEEEtypes_VendorSpecific_t wpaIE;
++ IEEEtypes_Generic_t rsnIE;
++
++ IEEEtypes_VendorSpecific_t wpsIE;
++
++ u8 *pBeaconBuf; //!< Pointer to the returned scan response
++ uint beaconBufSize; //!< Length of the stored scan response
++ uint beaconBufSizeMax; //!< Max allocated size for updated scan response
++
++} BSSDescriptor_t;
++
++extern int SSIDcmp(WLAN_802_11_SSID * ssid1, WLAN_802_11_SSID * ssid2);
++extern int FindSSIDInList(wlan_adapter * Adapter, WLAN_802_11_SSID * ssid,
++ u8 * bssid, int mode);
++extern int FindBestSSIDInList(wlan_adapter * Adapter);
++extern int FindBSSIDInList(wlan_adapter * Adapter, u8 * bssid, int mode);
++
++extern int FindBestNetworkSsid(wlan_private * priv, WLAN_802_11_SSID * pSSID);
++
++extern int SendSpecificSSIDScan(wlan_private * priv,
++ WLAN_802_11_SSID * pRequestedSSID);
++extern int SendSpecificBSSIDScan(wlan_private * priv, u8 * bssid);
++
++extern int wlan_get_scan_table_ioctl(wlan_private * priv, struct iwreq *wrq);
++extern int wlan_set_user_scan_ioctl(wlan_private * priv, struct iwreq *wrq);
++
++extern int wlan_associate(wlan_private * priv, BSSDescriptor_t * pBSSDesc);
++
++extern int wlan_cmd_802_11_scan(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *pdata_buf);
++
++extern void wlan_scan_update_tsf_timestamps(wlan_private * priv,
++ BSSDescriptor_t * pNewBssDesc);
++
++extern int wlan_ret_802_11_scan(wlan_private * priv,
++ HostCmd_DS_COMMAND * resp);
++
++extern int wlan_extscan_ioctl(wlan_private * priv, struct ifreq *req);
++
++extern int sendBgScanQueryCmd(wlan_private * priv);
++extern int wlan_bg_scan_enable(wlan_private * priv, BOOLEAN enable);
++extern int wlan_do_bg_scan_config_ioctl(wlan_private * priv,
++ struct ifreq *req);
++extern int wlan_cmd_802_11_bg_scan_config(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd,
++ int cmd_action, void *pdata_buf);
++extern int wlan_cmd_802_11_bg_scan_query(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd);
++
++#ifdef __KERNEL__
++extern int wlan_get_scan(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra);
++extern int wlan_set_scan(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra);
++#endif
++
++#endif /* _WLAN_SCAN_H */
+diff --git a/drivers/net/wireless/marvell8686/wlan_thread.h b/drivers/net/wireless/marvell8686/wlan_thread.h
+new file mode 100644
+index 0000000..3d9c01c
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_thread.h
+@@ -0,0 +1,58 @@
++/*
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++
++#ifndef __WLAN_THREAD_H_
++#define __WLAN_THREAD_H_
++
++#include <linux/kthread.h>
++
++typedef struct
++{
++ struct task_struct *task;
++ wait_queue_head_t waitQ;
++ pid_t pid;
++ void *priv;
++} wlan_thread;
++
++static inline void
++wlan_activate_thread(wlan_thread * thr)
++{
++ /** Record the thread pid */
++ thr->pid = current->pid;
++
++ /** Initialize the wait queue */
++ init_waitqueue_head(&thr->waitQ);
++}
++
++static inline void
++wlan_deactivate_thread(wlan_thread * thr)
++{
++ ENTER();
++
++ LEAVE();
++}
++
++static inline void
++wlan_create_thread(int (*wlanfunc) (void *), wlan_thread * thr, char *name)
++{
++ thr->task = kthread_run(wlanfunc, thr, "%s", name);
++}
++
++static inline int
++wlan_terminate_thread(wlan_thread * thr)
++{
++ ENTER();
++
++ /* Check if the thread is active or not */
++ if (!thr->pid) {
++ PRINTM(INFO, "Thread does not exist\n");
++ return -1;
++ }
++ kthread_stop(thr->task);
++
++ LEAVE();
++ return 0;
++}
++
++#endif
+diff --git a/drivers/net/wireless/marvell8686/wlan_tx.c b/drivers/net/wireless/marvell8686/wlan_tx.c
+new file mode 100644
+index 0000000..f04f6e1
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_tx.c
+@@ -0,0 +1,286 @@
++/** @file wlan_tx.c
++ * @brief This file contains the handling of TX in wlan
++ * driver.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 09/28/05: Add Doxygen format comments
++ 12/13/05: Add Proprietary periodic sleep support
++ 01/05/06: Add kernel 2.6.x support
++ 04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
++********************************************************/
++
++#include "include.h"
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++/********************************************************
++ Global Variables
++********************************************************/
++
++/********************************************************
++ Local Functions
++********************************************************/
++
++/**
++ * @brief This function processes a single packet and sends
++ * to IF layer
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param skb A pointer to skb which includes TX packet
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++static int
++SendSinglePacket(wlan_private * priv, struct sk_buff *skb)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ TxPD LocalTxPD;
++ TxPD *pLocalTxPD = &LocalTxPD;
++ u8 *ptr = Adapter->TmpTxBuf;
++
++ ENTER();
++
++ if (!skb->len || (skb->len > MRVDRV_ETH_TX_PACKET_BUFFER_SIZE)) {
++ PRINTM(ERROR, "Tx Error: Bad skb length %d : %d\n",
++ skb->len, MRVDRV_ETH_TX_PACKET_BUFFER_SIZE);
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ memset(pLocalTxPD, 0, sizeof(TxPD));
++
++ pLocalTxPD->TxPacketLength = skb->len;
++
++ if (Adapter->wmm.enabled) {
++ /*
++ * original skb->priority has been overwritten
++ * by wmm_map_and_add_skb()
++ */
++ pLocalTxPD->Priority = (u8) skb->priority;
++
++ pLocalTxPD->PktDelay_2ms = wmm_compute_driver_packet_delay(skb);
++ }
++
++ if (pLocalTxPD->Priority < NELEMENTS(Adapter->wmm.userPriPktTxCtrl)) {
++ /*
++ * Set the priority specific TxControl field, setting of 0 will
++ * cause the default value to be used later in this function
++ */
++ pLocalTxPD->TxControl
++ = Adapter->wmm.userPriPktTxCtrl[pLocalTxPD->Priority];
++ }
++
++ if (Adapter->PSState != PS_STATE_FULL_POWER) {
++ if (TRUE == CheckLastPacketIndication(priv)) {
++ Adapter->TxLockFlag = TRUE;
++ pLocalTxPD->Flags = MRVDRV_TxPD_POWER_MGMT_LAST_PACKET;
++ }
++ }
++
++ /* offset of actual data */
++ pLocalTxPD->TxPacketLocation = sizeof(TxPD);
++
++ if (pLocalTxPD->TxControl == 0) {
++ /* TxCtrl set by user or default */
++ pLocalTxPD->TxControl = Adapter->PktTxCtrl;
++ }
++
++ endian_convert_TxPD(pLocalTxPD);
++
++ memcpy((u8 *) pLocalTxPD->TxDestAddr, skb->data, MRVDRV_ETH_ADDR_LEN);
++
++ ptr += SDIO_HEADER_LEN;
++ memcpy(ptr, pLocalTxPD, sizeof(TxPD));
++
++ ptr += sizeof(TxPD);
++
++ memcpy(ptr, skb->data, skb->len);
++
++ ret = sbi_host_to_card(priv, MVMS_DAT, Adapter->TmpTxBuf,
++ skb->len + sizeof(TxPD));
++ if (ret) {
++ PRINTM(ERROR,
++ "SendSinglePacket Error: sbi_host_to_card failed: 0x%X\n",
++ ret);
++ Adapter->dbg.num_tx_host_to_card_failure++;
++ goto done;
++ }
++
++ PRINTM(DATA, "Data => FW\n");
++ DBG_HEXDUMP(DAT_D, "Tx", ptr - sizeof(TxPD),
++ MIN(skb->len + sizeof(TxPD), MAX_DATA_DUMP_LEN));
++
++ wmm_process_fw_iface_tx_xfer_start(priv);
++
++ done:
++ if (!ret) {
++ priv->stats.tx_packets++;
++ priv->stats.tx_bytes += skb->len;
++ } else {
++ priv->stats.tx_dropped++;
++ priv->stats.tx_errors++;
++ }
++
++ /* need to be freed in all cases */
++ os_free_tx_packet(priv);
++
++ LEAVE();
++ return ret;
++}
++
++/********************************************************
++ Global functions
++********************************************************/
++
++/**
++ * @brief This function checks the conditions and sends packet to IF
++ * layer if everything is ok.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return n/a
++ */
++void
++wlan_process_tx(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ OS_INTERRUPT_SAVE_AREA;
++
++ if (priv->wlan_dev.dnld_sent) {
++ PRINTM(MSG, "TX Error: dnld_sent = %d, not sending\n",
++ priv->wlan_dev.dnld_sent);
++ goto done;
++ }
++
++ SendSinglePacket(priv, Adapter->CurrentTxSkb);
++ OS_INT_DISABLE;
++ priv->adapter->HisRegCpy &= ~HIS_TxDnLdRdy;
++ OS_INT_RESTORE;
++
++ done:
++ LEAVE();
++}
++
++/**
++ * @brief This function queues the packet received from
++ * kernel/upper layer and wake up the main thread to handle it.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param skb A pointer to skb which includes TX packet
++ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
++ */
++int
++wlan_tx_packet(wlan_private * priv, struct sk_buff *skb)
++{
++ ulong flags;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ HEXDUMP("TX Data", skb->data, MIN(skb->len, 100));
++
++ spin_lock_irqsave(&Adapter->CurrentTxLock, flags);
++
++ wmm_map_and_add_skb(priv, skb);
++ wake_up_interruptible(&priv->MainThread.waitQ);
++ spin_unlock_irqrestore(&Adapter->CurrentTxLock, flags);
++
++ LEAVE();
++
++ return ret;
++}
++
++/**
++ * @brief This function tells firmware to send a NULL data packet.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param flags Trasnit Pkt Flags
++ * @return n/a
++ */
++int
++SendNullPacket(wlan_private * priv, u8 flags)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ TxPD txpd = { 0 };
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 *ptr = Adapter->TmpTxBuf;
++
++ ENTER();
++
++ if (Adapter->SurpriseRemoved == TRUE) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateDisconnected) {
++ ret = WLAN_STATUS_FAILURE;
++ goto done;
++ }
++
++ memset(&txpd, 0, sizeof(TxPD));
++
++ txpd.TxControl = Adapter->PktTxCtrl;
++ txpd.Flags = flags;
++ txpd.Priority = WMM_HIGHEST_PRIORITY;
++ txpd.TxPacketLocation = sizeof(TxPD);
++
++ endian_convert_TxPD(&txpd);
++
++ ptr += SDIO_HEADER_LEN;
++ memcpy(ptr, &txpd, sizeof(TxPD));
++
++ ret = sbi_host_to_card(priv, MVMS_DAT, Adapter->TmpTxBuf, sizeof(TxPD));
++
++ if (ret != 0) {
++ PRINTM(ERROR, "TX Error: SendNullPacket failed!\n");
++ Adapter->dbg.num_tx_host_to_card_failure++;
++ goto done;
++ }
++ PRINTM(DATA, "Null data => FW\n");
++ DBG_HEXDUMP(DAT_D, "Tx", ptr, sizeof(TxPD));
++
++ done:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief This function check if we need send last packet indication.
++ *
++ * @param priv A pointer to wlan_private structure
++ *
++ * @return TRUE or FALSE
++ */
++BOOLEAN
++CheckLastPacketIndication(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ BOOLEAN ret = FALSE;
++ BOOLEAN prop_ps = TRUE;
++
++ ENTER();
++
++ if (Adapter->sleep_period.period == 0 || Adapter->gen_null_pkg == FALSE /* for UPSD certification tests */
++ ) {
++ LEAVE();
++ return ret;
++ }
++
++ if (wmm_lists_empty(priv)) {
++ if (((Adapter->CurBssParams.wmm_uapsd_enabled == TRUE)
++ && (Adapter->wmm.qosinfo != 0)) || prop_ps) {
++ ret = TRUE;
++ }
++ }
++
++ LEAVE();
++ return ret;
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_types.h b/drivers/net/wireless/marvell8686/wlan_types.h
+new file mode 100644
+index 0000000..76e4f25
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_types.h
+@@ -0,0 +1,1050 @@
++/** @file wlan_types.h
++ * @brief This header file contains definition for global types
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/*************************************************************
++Change log:
++ 10/11/05: add Doxygen format comments
++ 01/11/06: Add IEEE Association response type. Add TSF TLV information.
++ 01/31/06: Add support to selectively enabe the FW Scan channel filter
++ 04/10/06: Add power_adapt_cfg_ext command
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 05/03/06: Add auto_tx hostcmd
++ 08/28/06: Add LED_CTRL hostcmd
++************************************************************/
++
++#ifndef _WLAN_TYPES_
++#define _WLAN_TYPES_
++
++#ifndef __KERNEL__
++typedef char s8;
++typedef unsigned char u8;
++
++typedef signed short s16;
++typedef unsigned short u16;
++
++typedef signed long s32;
++typedef unsigned long u32;
++
++typedef signed long long s64;
++typedef unsigned long long u64;
++
++typedef u32 dma_addr_t;
++typedef u32 dma64_addr_t;
++/* Dma addresses are 32-bits wide. */
++#ifndef __ATTRIB_ALIGN__
++#define __ATTRIB_ALIGN__ __attribute__((aligned(4)))
++#endif
++
++#ifndef __ATTRIB_PACK__
++#define __ATTRIB_PACK__ __attribute__ ((packed))
++#endif
++#endif
++
++typedef long LONG;
++typedef unsigned long long ULONGLONG;
++typedef u32 WLAN_OID;
++
++#define MRVDRV_MAX_MULTICAST_LIST_SIZE 32
++#define MRVDRV_MAX_CHANNEL_SIZE 14
++#define MRVDRV_ETH_ADDR_LEN 6
++#define MRVDRV_MAX_SSID_LENGTH 32
++#define MRVDRV_MAX_BSS_DESCRIPTS 16
++/** WEP list macros & data structures */
++#define MRVL_KEY_BUFFER_SIZE_IN_BYTE 16
++#define MRVL_MAX_KEY_WPA_KEY_LENGTH 32
++
++#define HOSTCMD_SUPPORTED_RATES G_SUPPORTED_RATES
++
++#define BAND_B (0x01)
++#define BAND_G (0x02)
++#define ALL_802_11_BANDS (BAND_B | BAND_G)
++
++#define B_SUPPORTED_RATES 8
++#define G_SUPPORTED_RATES 14
++
++#define WLAN_SUPPORTED_RATES 14
++#define WLAN_MAX_SSID_LENGTH 32
++
++#define MAX_POWER_ADAPT_GROUP 5
++
++#define MRVDRV_MAX_SSID_LIST_LENGTH 10
++
++typedef u8 WLAN_802_11_RATES[WLAN_SUPPORTED_RATES];
++typedef u8 WLAN_802_11_MAC_ADDRESS[ETH_ALEN];
++
++/** WLAN_802_11_NETWORK_TYPE */
++typedef enum _WLAN_802_11_NETWORK_TYPE
++{
++ Wlan802_11FH,
++ Wlan802_11DS,
++ /*defined as upper bound */
++ Wlan802_11NetworkTypeMax
++} WLAN_802_11_NETWORK_TYPE, *PWLAN_802_11_NETWORK_TYPE;
++
++/** WLAN_802_11_NETWORK_INFRASTRUCTURE */
++typedef enum _WLAN_802_11_NETWORK_INFRASTRUCTURE
++{
++ Wlan802_11IBSS,
++ Wlan802_11Infrastructure,
++ Wlan802_11AutoUnknown,
++ /*defined as upper bound */
++ Wlan802_11InfrastructureMax
++} WLAN_802_11_NETWORK_INFRASTRUCTURE, *PWLAN_802_11_NETWORK_INFRASTRUCTURE;
++
++#define IEEE_MAX_IE_SIZE 256
++
++/** IEEE Type definitions */
++typedef enum _IEEEtypes_ElementId_e
++{
++ SSID = 0,
++ SUPPORTED_RATES = 1,
++ FH_PARAM_SET = 2,
++ DS_PARAM_SET = 3,
++ CF_PARAM_SET = 4,
++
++ IBSS_PARAM_SET = 6,
++
++ COUNTRY_INFO = 7,
++
++ ERP_INFO = 42,
++ EXTENDED_SUPPORTED_RATES = 50,
++
++ VENDOR_SPECIFIC_221 = 221,
++ WMM_IE = VENDOR_SPECIFIC_221,
++
++ WPS_IE = VENDOR_SPECIFIC_221,
++
++ WPA_IE = VENDOR_SPECIFIC_221,
++ RSN_IE = 48,
++
++ EXTRA_IE = 133,
++} __ATTRIB_PACK__ IEEEtypes_ElementId_e;
++
++#define CAPINFO_MASK (~( W_BIT_15 | W_BIT_14 | \
++ W_BIT_12 | W_BIT_11 | W_BIT_9) )
++
++typedef struct _IEEEtypes_CapInfo_t
++{
++ u8 Ess:1;
++ u8 Ibss:1;
++ u8 CfPollable:1;
++ u8 CfPollRqst:1;
++ u8 Privacy:1;
++ u8 ShortPreamble:1;
++ u8 Pbcc:1;
++ u8 ChanAgility:1;
++ u8 SpectrumMgmt:1;
++ u8 Rsrvd3:1;
++ u8 ShortSlotTime:1;
++ u8 Apsd:1;
++ u8 Rsvrd2:1;
++ u8 DSSSOFDM:1;
++ u8 Rsrvd1:2;
++} __ATTRIB_PACK__ IEEEtypes_CapInfo_t;
++
++typedef struct
++{
++ u8 ElementId;
++ u8 Len;
++} __ATTRIB_PACK__ IEEEtypes_Header_t;
++
++/** IEEEtypes_CfParamSet_t */
++typedef struct _IEEEtypes_CfParamSet_t
++{
++ u8 ElementId;
++ u8 Len;
++ u8 CfpCnt;
++ u8 CfpPeriod;
++ u16 CfpMaxDuration;
++ u16 CfpDurationRemaining;
++} __ATTRIB_PACK__ IEEEtypes_CfParamSet_t;
++
++typedef struct IEEEtypes_IbssParamSet_t
++{
++ u8 ElementId;
++ u8 Len;
++ u16 AtimWindow;
++} __ATTRIB_PACK__ IEEEtypes_IbssParamSet_t;
++
++/** IEEEtypes_SsParamSet_t */
++typedef union _IEEEtypes_SsParamSet_t
++{
++ IEEEtypes_CfParamSet_t CfParamSet;
++ IEEEtypes_IbssParamSet_t IbssParamSet;
++} __ATTRIB_PACK__ IEEEtypes_SsParamSet_t;
++
++/** IEEEtypes_FhParamSet_t */
++typedef struct _IEEEtypes_FhParamSet_t
++{
++ u8 ElementId;
++ u8 Len;
++ u16 DwellTime;
++ u8 HopSet;
++ u8 HopPattern;
++ u8 HopIndex;
++} __ATTRIB_PACK__ IEEEtypes_FhParamSet_t;
++
++typedef struct _IEEEtypes_DsParamSet_t
++{
++ u8 ElementId;
++ u8 Len;
++ u8 CurrentChan;
++} __ATTRIB_PACK__ IEEEtypes_DsParamSet_t;
++
++/** IEEEtypes_DsParamSet_t */
++typedef union IEEEtypes_PhyParamSet_t
++{
++ IEEEtypes_FhParamSet_t FhParamSet;
++ IEEEtypes_DsParamSet_t DsParamSet;
++} __ATTRIB_PACK__ IEEEtypes_PhyParamSet_t;
++
++typedef struct _IEEEtypes_ERPInfo_t
++{
++ u8 ElementId;
++ u8 Len;
++ u8 ERPFlags;
++} __ATTRIB_PACK__ IEEEtypes_ERPInfo_t;
++
++typedef u16 IEEEtypes_AId_t;
++typedef u16 IEEEtypes_StatusCode_t;
++
++typedef struct
++{
++ IEEEtypes_CapInfo_t Capability;
++ IEEEtypes_StatusCode_t StatusCode;
++ IEEEtypes_AId_t AId;
++ u8 IEBuffer[1];
++} __ATTRIB_PACK__ IEEEtypes_AssocRsp_t;
++
++typedef struct
++{
++ u8 ElementId;
++ u8 Len;
++ u8 Oui[3];
++ u8 OuiType;
++ u8 OuiSubtype;
++ u8 Version;
++} __ATTRIB_PACK__ IEEEtypes_VendorHeader_t;
++
++typedef struct
++{
++ IEEEtypes_VendorHeader_t VendHdr;
++
++ /* IE Max - size of previous fields */
++ u8 Data[IEEE_MAX_IE_SIZE - sizeof(IEEEtypes_VendorHeader_t)];
++
++}
++__ATTRIB_PACK__ IEEEtypes_VendorSpecific_t;
++
++typedef struct
++{
++ IEEEtypes_Header_t IeeeHdr;
++
++ /* IE Max - size of previous fields */
++ u8 Data[IEEE_MAX_IE_SIZE - sizeof(IEEEtypes_Header_t)];
++
++}
++__ATTRIB_PACK__ IEEEtypes_Generic_t;
++
++/** TLV type ID definition */
++#define PROPRIETARY_TLV_BASE_ID 0x0100
++
++/* Terminating TLV Type */
++#define MRVL_TERMINATE_TLV_ID 0xffff
++
++#define TLV_TYPE_SSID 0x0000
++#define TLV_TYPE_RATES 0x0001
++#define TLV_TYPE_PHY_FH 0x0002
++#define TLV_TYPE_PHY_DS 0x0003
++#define TLV_TYPE_CF 0x0004
++#define TLV_TYPE_IBSS 0x0006
++
++#define TLV_TYPE_DOMAIN 0x0007
++
++#define TLV_TYPE_POWER_CAPABILITY 0x0021
++
++#define TLV_TYPE_KEY_MATERIAL (PROPRIETARY_TLV_BASE_ID + 0)
++#define TLV_TYPE_CHANLIST (PROPRIETARY_TLV_BASE_ID + 1)
++#define TLV_TYPE_NUMPROBES (PROPRIETARY_TLV_BASE_ID + 2)
++#define TLV_TYPE_RSSI_LOW (PROPRIETARY_TLV_BASE_ID + 4)
++#define TLV_TYPE_SNR_LOW (PROPRIETARY_TLV_BASE_ID + 5)
++#define TLV_TYPE_FAILCOUNT (PROPRIETARY_TLV_BASE_ID + 6)
++#define TLV_TYPE_BCNMISS (PROPRIETARY_TLV_BASE_ID + 7)
++#define TLV_TYPE_LED_GPIO (PROPRIETARY_TLV_BASE_ID + 8)
++#define TLV_TYPE_LEDBEHAVIOR (PROPRIETARY_TLV_BASE_ID + 9)
++#define TLV_TYPE_PASSTHROUGH (PROPRIETARY_TLV_BASE_ID + 10)
++#define TLV_TYPE_POWER_TBL_2_4GHZ (PROPRIETARY_TLV_BASE_ID + 12)
++#define TLV_TYPE_POWER_TBL_5GHZ (PROPRIETARY_TLV_BASE_ID + 13)
++#define TLV_TYPE_WMMQSTATUS (PROPRIETARY_TLV_BASE_ID + 16)
++#define TLV_TYPE_WILDCARDSSID (PROPRIETARY_TLV_BASE_ID + 18)
++#define TLV_TYPE_TSFTIMESTAMP (PROPRIETARY_TLV_BASE_ID + 19)
++#define TLV_TYPE_POWERADAPTCFGEXT (PROPRIETARY_TLV_BASE_ID + 20)
++#define TLV_TYPE_RSSI_HIGH (PROPRIETARY_TLV_BASE_ID + 22)
++#define TLV_TYPE_SNR_HIGH (PROPRIETARY_TLV_BASE_ID + 23)
++#define TLV_TYPE_AUTO_TX (PROPRIETARY_TLV_BASE_ID + 24)
++#define TLV_TYPE_WPS_ENROLLEE_PROBE_REQ_TLV (PROPRIETARY_TLV_BASE_ID + 27)
++#define TLV_TYPE_STARTBGSCANLATER (PROPRIETARY_TLV_BASE_ID + 30)
++#define TLV_TYPE_AUTH_TYPE (PROPRIETARY_TLV_BASE_ID + 31)
++#define TLV_TYPE_PRE_BEACON_LOST (PROPRIETARY_TLV_BASE_ID + 73)
++
++/** TLV related data structures*/
++/** MrvlIEtypesHeader_t */
++typedef struct _MrvlIEtypesHeader
++{
++ u16 Type;
++ u16 Len;
++} __ATTRIB_PACK__ MrvlIEtypesHeader_t;
++
++/** MrvlIEtypes_Data_t */
++typedef struct _MrvlIEtypes_Data_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 Data[1];
++} __ATTRIB_PACK__ MrvlIEtypes_Data_t;
++
++/** MrvlIEtypes_RatesParamSet_t */
++typedef struct _MrvlIEtypes_RatesParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 Rates[1];
++} __ATTRIB_PACK__ MrvlIEtypes_RatesParamSet_t;
++
++/** MrvlIEtypes_SsIdParamSet_t */
++typedef struct _MrvlIEtypes_SsIdParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 SsId[1];
++} __ATTRIB_PACK__ MrvlIEtypes_SsIdParamSet_t;
++
++/** MrvlIEtypes_WildCardSsIdParamSet_t */
++typedef struct _MrvlIEtypes_WildCardSsIdParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 MaxSsidLength;
++ u8 SsId[1];
++} __ATTRIB_PACK__ MrvlIEtypes_WildCardSsIdParamSet_t;
++
++/** ChanScanMode_t */
++typedef struct
++{
++ u8 PassiveScan:1;
++ u8 DisableChanFilt:1;
++ u8 Reserved_2_7:6;
++} __ATTRIB_PACK__ ChanScanMode_t;
++
++/** ChanScanParamSet_t */
++typedef struct _ChanScanParamSet_t
++{
++ u8 RadioType;
++ u8 ChanNumber;
++ ChanScanMode_t ChanScanMode;
++ u16 MinScanTime;
++ u16 MaxScanTime;
++} __ATTRIB_PACK__ ChanScanParamSet_t;
++
++/** MrvlIEtypes_ChanListParamSet_t */
++typedef struct _MrvlIEtypes_ChanListParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ ChanScanParamSet_t ChanScanParam[1];
++} __ATTRIB_PACK__ MrvlIEtypes_ChanListParamSet_t;
++
++/** CfParamSet_t */
++typedef struct _CfParamSet_t
++{
++ u8 CfpCnt;
++ u8 CfpPeriod;
++ u16 CfpMaxDuration;
++ u16 CfpDurationRemaining;
++} __ATTRIB_PACK__ CfParamSet_t;
++
++/** IbssParamSet_t */
++typedef struct _IbssParamSet_t
++{
++ u16 AtimWindow;
++} __ATTRIB_PACK__ IbssParamSet_t;
++
++/** MrvlIEtypes_SsParamSet_t */
++typedef struct _MrvlIEtypes_SsParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ union
++ {
++ CfParamSet_t CfParamSet[1];
++ IbssParamSet_t IbssParamSet[1];
++ } cf_ibss;
++} __ATTRIB_PACK__ MrvlIEtypes_SsParamSet_t;
++
++/** FhParamSet_t */
++typedef struct _FhParamSet_t
++{
++ u16 DwellTime;
++ u8 HopSet;
++ u8 HopPattern;
++ u8 HopIndex;
++} __ATTRIB_PACK__ FhParamSet_t;
++
++/** DsParamSet_t */
++typedef struct _DsParamSet_t
++{
++ u8 CurrentChan;
++} __ATTRIB_PACK__ DsParamSet_t;
++
++/** MrvlIEtypes_PhyParamSet_t */
++typedef struct _MrvlIEtypes_PhyParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ union
++ {
++ FhParamSet_t FhParamSet[1];
++ DsParamSet_t DsParamSet[1];
++ } fh_ds;
++} __ATTRIB_PACK__ MrvlIEtypes_PhyParamSet_t;
++
++/** MrvlIEtypes_RsnParamSet_t */
++typedef struct _MrvlIEtypes_RsnParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 RsnIE[1];
++} __ATTRIB_PACK__ MrvlIEtypes_RsnParamSet_t;
++
++/** MrvlIEtypes_WmmParamSet_t */
++typedef struct _MrvlIEtypes_WmmParamSet_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 WmmIE[1];
++} __ATTRIB_PACK__ MrvlIEtypes_WmmParamSet_t;
++
++typedef struct
++{
++ MrvlIEtypesHeader_t Header;
++ u8 QueueIndex;
++ u8 Disabled;
++ u8 Reserved1;
++ u8 Reserved2;
++ u8 FlowRequired;
++ u8 FlowCreated;
++ u32 Reserved3;
++} __ATTRIB_PACK__ MrvlIEtypes_WmmQueueStatus_t;
++
++/** Table of TSF values returned in the scan result */
++typedef struct
++{
++ MrvlIEtypesHeader_t Header;
++ u64 tsfTable[1];
++} __ATTRIB_PACK__ MrvlIEtypes_TsfTimestamp_t;
++
++/** Local Power Capability */
++typedef struct _MrvlIEtypes_PowerCapability_t
++{
++ MrvlIEtypesHeader_t Header;
++ s8 MinPower;
++ s8 MaxPower;
++} __ATTRIB_PACK__ MrvlIEtypes_PowerCapability_t;
++
++/** MrvlIEtypes_RssiParamSet_t */
++typedef struct _MrvlIEtypes_RssiThreshold_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 RSSIValue;
++ u8 RSSIFreq;
++} __ATTRIB_PACK__ MrvlIEtypes_RssiThreshold_t;
++
++/** MrvlIEtypes_SnrThreshold_t */
++typedef struct _MrvlIEtypes_SnrThreshold_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 SNRValue;
++ u8 SNRFreq;
++} __ATTRIB_PACK__ MrvlIEtypes_SnrThreshold_t;
++
++/** MrvlIEtypes_PreBeaconLost_t */
++typedef struct _MrvlIEtypes_PreBeaconLost_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 PreBeaconLost;
++ u8 Reserved;
++} __ATTRIB_PACK__ MrvlIEtypes_PreBeaconLost_t;
++
++/** MrvlIEtypes_FailureCount_t */
++typedef struct _MrvlIEtypes_FailureCount_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 FailValue;
++ u8 FailFreq;
++} __ATTRIB_PACK__ MrvlIEtypes_FailureCount_t;
++
++/** MrvlIEtypes_BeaconsMissed_t */
++typedef struct _MrvlIEtypes_BeaconsMissed_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 BeaconMissed;
++ u8 Reserved;
++} __ATTRIB_PACK__ MrvlIEtypes_BeaconsMissed_t;
++
++/** MrvlIEtypes_NumProbes_t */
++typedef struct _MrvlIEtypes_NumProbes_t
++{
++ MrvlIEtypesHeader_t Header;
++ u16 NumProbes;
++} __ATTRIB_PACK__ MrvlIEtypes_NumProbes_t;
++
++/** MrvlIEtypes_StartBGScanLater_t */
++typedef struct _MrvlIEtypes_StartBGScanLater_t
++{
++ MrvlIEtypesHeader_t Header;
++ u16 StartLater;
++} __ATTRIB_PACK__ MrvlIEtypes_StartBGScanLater_t;
++
++typedef struct _LedGpio_t
++{
++ u8 LedNum; /* LED # mapped to GPIO pin # below */
++ u8 GpioNum; /* GPIO pin # used to control LED # above */
++} __ATTRIB_PACK__ LedGpio_t;
++
++/** MrvlIEtypes_LedGpio_t */
++typedef struct _MrvlIEtypes_LedGpio_t
++{
++ MrvlIEtypesHeader_t Header;
++ LedGpio_t LedGpio[1];
++} __ATTRIB_PACK__ MrvlIEtypes_LedGpio_t;
++
++/** MrvlIEtypes_LedBehavior_t */
++typedef struct _MrvlIEtypes_LedBehavior_t
++{
++ MrvlIEtypesHeader_t Header;
++ u8 FirmwareState; /* Firmware State */
++ u8 LedNum; /* LED # */
++ u8 LedState; /* LED State corresponding to Firmware State */
++ u8 LedArgs; /* Arguments for LED State */
++} __ATTRIB_PACK__ MrvlIEtypes_LedBehavior_t;
++
++typedef struct _PA_Group_t
++{
++ u16 PowerAdaptLevel;
++ u16 RateBitmap;
++ u32 Reserved;
++} __ATTRIB_PACK__ PA_Group_t;
++
++/** MrvlIEtypes_PA_Group_t */
++typedef struct _MrvlIEtypes_PowerAdapt_Group_t
++{
++ MrvlIEtypesHeader_t Header;
++ PA_Group_t PA_Group[MAX_POWER_ADAPT_GROUP];
++} __ATTRIB_PACK__ MrvlIEtypes_PowerAdapt_Group_t;
++
++typedef struct _AutoTx_MacFrame_t
++{
++ u16 Interval; /* in seconds */
++ u8 Priority; /* User Priority: 0~7, ignored if non-WMM */
++ u8 Reserved; /* set to 0 */
++ u16 FrameLen; /* Length of MAC frame payload */
++ u8 DestMacAddr[ETH_ALEN];
++ u8 SrcMacAddr[ETH_ALEN];
++ u8 Payload[];
++} __ATTRIB_PACK__ AutoTx_MacFrame_t;
++
++/** MrvlIEtypes_AutoTx_t */
++typedef struct _MrvlIEtypes_AutoTx_t
++{
++ MrvlIEtypesHeader_t Header;
++ AutoTx_MacFrame_t AutoTx_MacFrame;
++} __ATTRIB_PACK__ MrvlIEtypes_AutoTx_t;
++
++typedef struct
++{
++ u8 value;
++ u8 Freq;
++} Threshold;
++
++typedef struct
++{
++ u16 EventsBitmap; /* bit 0: RSSI low, bit 1: SNR low,
++ * bit 2: RSSI high, bit 3: SNR high
++ */
++ Threshold Rssi_low;
++ Threshold Snr_low;
++ Threshold Rssi_high;
++ Threshold Snr_high;
++ u8 Rssi_low_count;
++ u8 Snr_low_count;
++ u8 Rssi_high_count;
++ u8 Snr_high_count;
++} wlan_subscribe_event;
++
++/** Auth type to be used in the Authentication portion of an Assoc seq */
++typedef struct
++{
++ MrvlIEtypesHeader_t Header;
++ u16 AuthType;
++} __ATTRIB_PACK__ MrvlIEtypes_AuthType_t;
++
++#define MRVDRV_MAX_SUBBAND_802_11D 83
++#define COUNTRY_CODE_LEN 3
++
++/** Data structure for Country IE*/
++typedef struct _IEEEtypes_SubbandSet
++{
++ u8 FirstChan;
++ u8 NoOfChan;
++ u8 MaxTxPwr;
++} __ATTRIB_PACK__ IEEEtypes_SubbandSet_t;
++
++typedef struct _IEEEtypes_CountryInfoSet
++{
++ u8 ElementId;
++ u8 Len;
++ u8 CountryCode[COUNTRY_CODE_LEN];
++ IEEEtypes_SubbandSet_t Subband[1];
++} __ATTRIB_PACK__ IEEEtypes_CountryInfoSet_t;
++
++typedef struct _IEEEtypes_CountryInfoFullSet
++{
++ u8 ElementId;
++ u8 Len;
++ u8 CountryCode[COUNTRY_CODE_LEN];
++ IEEEtypes_SubbandSet_t Subband[MRVDRV_MAX_SUBBAND_802_11D];
++} __ATTRIB_PACK__ IEEEtypes_CountryInfoFullSet_t;
++
++typedef struct _MrvlIEtypes_DomainParamSet
++{
++ MrvlIEtypesHeader_t Header;
++ u8 CountryCode[COUNTRY_CODE_LEN];
++ IEEEtypes_SubbandSet_t Subband[1];
++} __ATTRIB_PACK__ MrvlIEtypes_DomainParamSet_t;
++
++/** Size of a TSPEC. Used to allocate necessary buffer space in commands */
++#define WMM_TSPEC_SIZE 63
++
++/** Extra IE bytes allocated in messages for appended IEs after a TSPEC */
++#define WMM_ADDTS_EXTRA_IE_BYTES 256
++
++/** Extra TLV bytes allocated in messages for configuring WMM Queues */
++#define WMM_QUEUE_CONFIG_EXTRA_TLV_BYTES 64
++/** Maximum number of AC QOS queues available in the driver/firmware */
++#define MAX_AC_QUEUES 4
++
++/** enum of WMM AC_QUEUES */
++typedef enum
++{
++ WMM_AC_BK,
++ WMM_AC_BE,
++ WMM_AC_VI,
++ WMM_AC_VO,
++} __ATTRIB_PACK__ wlan_wmm_ac_e;
++
++/** data structure of WMM QoS information */
++typedef struct
++{
++ u8 ParaSetCount:4;
++ u8 Reserved:3;
++ u8 QosUAPSD:1;
++} __ATTRIB_PACK__ IEEEtypes_WmmQosInfo_t;
++
++typedef struct
++{
++ u8 Aifsn:4;
++ u8 Acm:1;
++ u8 Aci:2;
++ u8 Reserved:1;
++} __ATTRIB_PACK__ IEEEtypes_WmmAciAifsn_t;
++
++/** data structure of WMM ECW */
++typedef struct
++{
++ u8 EcwMin:4;
++ u8 EcwMax:4;
++} __ATTRIB_PACK__ IEEEtypes_WmmEcw_t;
++
++/** data structure of WMM AC parameters */
++typedef struct
++{
++ IEEEtypes_WmmAciAifsn_t AciAifsn;
++ IEEEtypes_WmmEcw_t Ecw;
++ u16 TxopLimit;
++} __ATTRIB_PACK__ IEEEtypes_WmmAcParameters_t;
++
++/** data structure of WMM Info IE */
++typedef struct
++{
++
++ /**
++ * WMM Info IE - Vendor Specific Header:
++ * ElementId [221/0xdd]
++ * Len [7]
++ * Oui [00:50:f2]
++ * OuiType [2]
++ * OuiSubType [0]
++ * Version [1]
++ */
++ IEEEtypes_VendorHeader_t VendHdr;
++
++ IEEEtypes_WmmQosInfo_t QoSInfo;
++
++} __ATTRIB_PACK__ IEEEtypes_WmmInfo_t;
++
++/** data structure of WMM parameter IE */
++typedef struct
++{
++ /**
++ * WMM Parameter IE - Vendor Specific Header:
++ * ElementId [221/0xdd]
++ * Len [24]
++ * Oui [00:50:f2]
++ * OuiType [2]
++ * OuiSubType [1]
++ * Version [1]
++ */
++ IEEEtypes_VendorHeader_t VendHdr;
++
++ IEEEtypes_WmmQosInfo_t QoSInfo;
++ u8 Reserved;
++
++ /** AC Parameters Record WMM_AC_BE, WMM_AC_BK, WMM_AC_VI, WMM_AC_VO */
++ IEEEtypes_WmmAcParameters_t AcParams[MAX_AC_QUEUES];
++
++} __ATTRIB_PACK__ IEEEtypes_WmmParameter_t;
++
++/**
++ * @brief Firmware command structure to retrieve the firmware WMM status.
++ *
++ * Used to retrieve the status of each WMM AC Queue in TLV
++ * format (MrvlIEtypes_WmmQueueStatus_t) as well as the current WMM
++ * parameter IE advertised by the AP.
++ *
++ * Used in response to a MACREG_INT_CODE_WMM_STATUS_CHANGE event signalling
++ * a QOS change on one of the ACs or a change in the WMM Parameter in
++ * the Beacon.
++ *
++ * TLV based command, byte arrays used for max sizing purpose. There are no
++ * arguments sent in the command, the TLVs are returned by the firmware.
++ */
++typedef struct
++{
++ u8 queueStatusTlv[sizeof(MrvlIEtypes_WmmQueueStatus_t) * MAX_AC_QUEUES];
++ u8 wmmParamTlv[sizeof(IEEEtypes_WmmParameter_t) + 2];
++
++}
++__ATTRIB_PACK__ HostCmd_DS_WMM_GET_STATUS;
++
++/**
++ * @brief Enumeration for the command result from an ADDTS or DELTS command
++ */
++typedef enum
++{
++ TSPEC_RESULT_SUCCESS = 0,
++ TSPEC_RESULT_EXEC_FAILURE = 1,
++ TSPEC_RESULT_TIMEOUT = 2,
++ TSPEC_RESULT_DATA_INVALID = 3,
++
++} __ATTRIB_PACK__ wlan_wmm_tspec_result_e;
++
++/**
++ * @brief IOCTL structure to send an ADDTS request and retrieve the response.
++ *
++ * IOCTL structure from the application layer relayed to firmware to
++ * instigate an ADDTS management frame with an appropriate TSPEC IE as well
++ * as any additional IEs appended in the ADDTS Action frame.
++ *
++ * @sa wlan_wmm_addts_req_ioctl
++ */
++typedef struct
++{
++ wlan_wmm_tspec_result_e commandResult;
++ u32 timeout_ms;
++
++ u8 ieeeStatusCode;
++
++ u8 tspecData[WMM_TSPEC_SIZE];
++
++ u8 addtsExtraIEBuf[WMM_ADDTS_EXTRA_IE_BYTES];
++
++} __ATTRIB_PACK__ wlan_ioctl_wmm_addts_req_t;
++
++/**
++ * @brief IOCTL structure to send a DELTS request.
++ *
++ * IOCTL structure from the application layer relayed to firmware to
++ * instigate an DELTS management frame with an appropriate TSPEC IE.
++ *
++ * @sa wlan_wmm_delts_req_ioctl
++ */
++typedef struct
++{
++ wlan_wmm_tspec_result_e commandResult; //!< Firmware execution result
++
++ u8 ieeeReasonCode; //!< IEEE reason code sent, unused for WMM
++
++ u8 tspecData[WMM_TSPEC_SIZE]; //!< TSPEC to send in the DELTS
++
++} __ATTRIB_PACK__ wlan_ioctl_wmm_delts_req_t;
++
++/**
++ * @brief Internal command structure used in executing an ADDTS command.
++ *
++ * Relay information between the IOCTL layer and the firmware command and
++ * command response procedures.
++ *
++ * @sa wlan_wmm_addts_req_ioctl
++ * @sa wlan_cmd_wmm_addts_req
++ * @sa wlan_cmdresp_wmm_addts_req
++ */
++typedef struct
++{
++ wlan_wmm_tspec_result_e commandResult;
++ u32 timeout_ms;
++
++ u8 dialogToken;
++ u8 ieeeStatusCode;
++
++ int tspecDataLen;
++ u8 tspecData[WMM_TSPEC_SIZE];
++ u8 addtsExtraIEBuf[WMM_ADDTS_EXTRA_IE_BYTES];
++
++} wlan_cmd_wmm_addts_req_t;
++
++/**
++ * @brief Internal command structure used in executing an DELTS command.
++ *
++ * Relay information between the IOCTL layer and the firmware command and
++ * command response procedures.
++ *
++ * @sa wlan_wmm_delts_req_ioctl
++ * @sa wlan_cmd_wmm_delts_req
++ * @sa wlan_cmdresp_wmm_delts_req
++ */
++typedef struct
++{
++ wlan_wmm_tspec_result_e commandResult;
++
++ u8 dialogToken;
++
++ u8 ieeeReasonCode;
++
++ int tspecDataLen;
++ u8 tspecData[WMM_TSPEC_SIZE];
++
++} wlan_cmd_wmm_delts_req_t;
++
++/**
++ * @brief Command structure for the HostCmd_CMD_WMM_ADDTS_REQ firmware command
++ *
++ */
++typedef struct
++{
++ wlan_wmm_tspec_result_e commandResult;
++ u32 timeout_ms;
++
++ u8 dialogToken;
++ u8 ieeeStatusCode;
++ u8 tspecData[WMM_TSPEC_SIZE];
++ u8 addtsExtraIEBuf[WMM_ADDTS_EXTRA_IE_BYTES];
++
++} __ATTRIB_PACK__ HostCmd_DS_WMM_ADDTS_REQ;
++
++/**
++ * @brief Command structure for the HostCmd_CMD_WMM_DELTS_REQ firmware command
++ */
++typedef struct
++{
++ wlan_wmm_tspec_result_e commandResult;
++ u8 dialogToken;
++ u8 ieeeReasonCode;
++ u8 tspecData[WMM_TSPEC_SIZE];
++
++} __ATTRIB_PACK__ HostCmd_DS_WMM_DELTS_REQ;
++
++/**
++ * @brief Enumeration for the action field in the Queue configure command
++ */
++typedef enum
++{
++ WMM_QUEUE_CONFIG_ACTION_GET = 0,
++ WMM_QUEUE_CONFIG_ACTION_SET = 1,
++ WMM_QUEUE_CONFIG_ACTION_DEFAULT = 2,
++
++ WMM_QUEUE_CONFIG_ACTION_MAX
++} __ATTRIB_PACK__ wlan_wmm_queue_config_action_e;
++
++/**
++ * @brief Command structure for the HostCmd_CMD_WMM_QUEUE_CONFIG firmware cmd
++ *
++ * Set/Get/Default the Queue parameters for a specific AC in the firmware.
++ *
++ */
++typedef struct
++{
++ wlan_wmm_queue_config_action_e action; //!< Set, Get, or Default
++ wlan_wmm_ac_e accessCategory; //!< WMM_AC_BK(0) to WMM_AC_VO(3)
++
++ /** @brief MSDU lifetime expiry per 802.11e
++ *
++ * - Ignored if 0 on a set command
++ * - Set to the 802.11e specified 500 TUs when defaulted
++ */
++ u16 msduLifetimeExpiry;
++
++ u8 tlvBuffer[WMM_QUEUE_CONFIG_EXTRA_TLV_BYTES]; //!< Not supported yet
++
++} __ATTRIB_PACK__ HostCmd_DS_WMM_QUEUE_CONFIG;
++
++/**
++ * @brief Internal command structure used in executing a queue config command.
++ *
++ * Relay information between the IOCTL layer and the firmware command and
++ * command response procedures.
++ *
++ * @sa wlan_wmm_queue_config_ioctl
++ * @sa wlan_cmd_wmm_queue_config
++ * @sa wlan_cmdresp_wmm_queue_config
++ */
++typedef struct
++{
++ wlan_wmm_queue_config_action_e action; //!< Set, Get, or Default
++ wlan_wmm_ac_e accessCategory; //!< WMM_AC_BK(0) to WMM_AC_VO(3)
++ u16 msduLifetimeExpiry; //!< lifetime expiry in TUs
++
++ int tlvBufLen; //!< Not supported yet
++ u8 tlvBuffer[WMM_QUEUE_CONFIG_EXTRA_TLV_BYTES]; //!< Not supported yet
++
++} wlan_cmd_wmm_queue_config_t;
++
++/**
++ * @brief IOCTL structure to configure a specific AC Queue's parameters
++ *
++ * IOCTL structure from the application layer relayed to firmware to
++ * get, set, or default the WMM AC queue parameters.
++ *
++ * - msduLifetimeExpiry is ignored if set to 0 on a set command
++ *
++ * @sa wlan_wmm_queue_config_ioctl
++ */
++typedef struct
++{
++ wlan_wmm_queue_config_action_e action; //!< Set, Get, or Default
++ wlan_wmm_ac_e accessCategory; //!< WMM_AC_BK(0) to WMM_AC_VO(3)
++ u16 msduLifetimeExpiry; //!< lifetime expiry in TUs
++
++ u8 supportedRates[10]; //!< Not supported yet
++
++} __ATTRIB_PACK__ wlan_ioctl_wmm_queue_config_t;
++
++/**
++ * @brief Enumeration for the action field in the queue stats command
++ */
++typedef enum
++{
++ WMM_STATS_ACTION_START = 0,
++ WMM_STATS_ACTION_STOP = 1,
++ WMM_STATS_ACTION_GET_CLR = 2,
++ WMM_STATS_ACTION_SET_CFG = 3, /* Not currently used */
++ WMM_STATS_ACTION_GET_CFG = 4, /* Not currently used */
++
++ WMM_STATS_ACTION_MAX
++} __ATTRIB_PACK__ wlan_wmm_stats_action_e;
++
++/** Number of bins in the histogram for the HostCmd_DS_WMM_QUEUE_STATS */
++#define WMM_STATS_PKTS_HIST_BINS 7
++
++/**
++ * @brief Command structure for the HostCmd_CMD_WMM_QUEUE_STATS firmware cmd
++ *
++ * Turn statistical collection on/off for a given AC or retrieve the
++ * accumulated stats for an AC and clear them in the firmware.
++ */
++typedef struct
++{
++ wlan_wmm_stats_action_e action; //!< Start, Stop, or Get
++ wlan_wmm_ac_e accessCategory; //!< WMM_AC_BK(0) to WMM_AC_VO(3)
++
++ u16 pktCount; //!< Number of successful packets transmitted
++ u16 pktLoss; //!< Packets lost; not included in pktCount
++ u32 avgQueueDelay; //!< Average Queue delay in microseconds
++ u32 avgTxDelay; //!< Average Transmission delay in microseconds
++ u32 usedTime; //!< Calculated medium time - Not currently used
++
++ /** @brief Queue Delay Histogram; number of packets per queue delay range
++ *
++ * [0] - 0ms <= delay < 5ms
++ * [1] - 5ms <= delay < 10ms
++ * [2] - 10ms <= delay < 20ms
++ * [3] - 20ms <= delay < 30ms
++ * [4] - 30ms <= delay < 40ms
++ * [5] - 40ms <= delay < 50ms
++ * [6] - 50ms <= delay < msduLifetime (TUs)
++ */
++ u16 delayHistogram[WMM_STATS_PKTS_HIST_BINS];
++
++ u16 reserved_u16_1;
++
++} __ATTRIB_PACK__ HostCmd_DS_WMM_QUEUE_STATS;
++
++/**
++ * @brief IOCTL structure to start, stop, and get statistics for a WMM AC
++ *
++ * IOCTL structure from the application layer relayed to firmware to
++ * start or stop statistical collection for a given AC. Also used to
++ * retrieve and clear the collected stats on a given AC.
++ *
++ * @sa wlan_wmm_queue_stats_ioctl
++ */
++typedef struct
++{
++ wlan_wmm_stats_action_e action; //!< Start, Stop, or Get
++ wlan_wmm_ac_e accessCategory; //!< WMM_AC_BK(0) to WMM_AC_VO(3)
++ u16 pktCount; //!< Number of successful packets transmitted
++ u16 pktLoss; //!< Packets lost; not included in pktCount
++ u32 avgQueueDelay; //!< Average Queue delay in microseconds
++ u32 avgTxDelay; //!< Average Transmission delay in microseconds
++ u32 usedTime; //!< Calculated medium time
++
++ /** @brief Queue Delay Histogram; number of packets per queue delay range
++ *
++ * [0] - 0ms <= delay < 5ms
++ * [1] - 5ms <= delay < 10ms
++ * [2] - 10ms <= delay < 20ms
++ * [3] - 20ms <= delay < 30ms
++ * [4] - 30ms <= delay < 40ms
++ * [5] - 40ms <= delay < 50ms
++ * [6] - 50ms <= delay < msduLifetime (TUs)
++ */
++ u16 delayHistogram[WMM_STATS_PKTS_HIST_BINS];
++} __ATTRIB_PACK__ wlan_ioctl_wmm_queue_stats_t;
++
++/**
++ * @brief IOCTL sub structure for a specific WMM AC Status
++ */
++typedef struct
++{
++ u8 wmmAcm;
++ u8 flowRequired;
++ u8 flowCreated;
++ u8 disabled;
++} __ATTRIB_PACK__ wlan_ioctl_wmm_queue_status_ac_t;
++
++/**
++ * @brief IOCTL structure to retrieve the WMM AC Queue status
++ *
++ * IOCTL structure from the application layer to retrieve:
++ * - ACM bit setting for the AC
++ * - Firmware status (flow required, flow created, flow disabled)
++ *
++ * @sa wlan_wmm_queue_status_ioctl
++ */
++typedef struct
++{
++ wlan_ioctl_wmm_queue_status_ac_t acStatus[MAX_AC_QUEUES];
++} __ATTRIB_PACK__ wlan_ioctl_wmm_queue_status_t;
++
++/** Firmware status for a specific AC */
++typedef struct
++{
++ u8 Disabled;
++ u8 FlowRequired;
++ u8 FlowCreated;
++} WmmAcStatus_t;
++
++#endif /* _WLAN_TYPES_ */
+diff --git a/drivers/net/wireless/marvell8686/wlan_version.h b/drivers/net/wireless/marvell8686/wlan_version.h
+new file mode 100644
+index 0000000..bacedd5
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_version.h
+@@ -0,0 +1,18 @@
++/** @file wlan_version.h
++ * @brief This file contains wlan driver version number.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 10/04/05: Add Doxygen format comments
++
++********************************************************/
++#include "release_version.h"
++
++const char driver_version[] =
++ "sd8686-%s-" DRIVER_RELEASE_VERSION "-(" "FP" "4" ")"
++#ifdef DEBUG_LEVEL2
++ "-dbg"
++#endif
++ " ";
+diff --git a/drivers/net/wireless/marvell8686/wlan_wext.c b/drivers/net/wireless/marvell8686/wlan_wext.c
+new file mode 100644
+index 0000000..85ee593
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_wext.c
+@@ -0,0 +1,8045 @@
++/** @file wlan_wext.c
++ * @brief This file contains ioctl functions
++ *
++ * Copyright ?Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 10/10/05: Add Doxygen format comments
++ 12/23/05: Modify FindBSSIDInList to search entire table for
++ duplicate BSSIDs when earlier matches are not compatible
++ 12/26/05: Remove errant memcpy in wlanidle_off; overwriting stack space
++ 01/05/06: Add kernel 2.6.x support
++ 01/11/06: Conditionalize new scan/join functions.
++ Update statics/externs. Move forward decl. from wlan_decl.h
++ 04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
++ 04/10/06: Add hostcmd generic API
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 05/04/06: Add IBSS coalescing related new iwpriv command
++ 08/29/06: Add ledgpio private command
++ 10/23/06: Validate setbcnavg/setdataavg command parameters and
++ return error if out of range
++********************************************************/
++
++#include "include.h"
++
++#include "wlan_version.h"
++
++#define GETLOG_BUFSIZE 512
++
++#define MAX_SCAN_CELL_SIZE (IW_EV_ADDR_LEN + \
++ MRVDRV_MAX_SSID_LENGTH + \
++ IW_EV_UINT_LEN + IW_EV_FREQ_LEN + \
++ IW_EV_QUAL_LEN + MRVDRV_MAX_SSID_LENGTH + \
++ IW_EV_PARAM_LEN + 40) /* 40 for WPAIE */
++
++typedef struct _ioctl_cmd
++{
++ int cmd;
++ int subcmd;
++ BOOLEAN fixsize;
++} ioctl_cmd;
++
++static ioctl_cmd Commands_Allowed_In_DeepSleep[] = {
++ {.cmd = WLANDEEPSLEEP,.subcmd = 0,.fixsize = FALSE},
++ {.cmd = WLAN_SETONEINT_GETWORDCHAR,.subcmd = WLANVERSION,.fixsize =
++ FALSE},
++ {.cmd = WLAN_SETINT_GETINT,.subcmd = WLANSDIOCLOCK,.fixsize = TRUE},
++ {.cmd = WLAN_SET_GET_2K,.subcmd = WLAN_GET_CFP_TABLE,.fixsize = FALSE},
++#ifdef DEBUG_LEVEL1
++ {.cmd = WLAN_SET_GET_SIXTEEN_INT,.subcmd = WLAN_DRV_DBG,.fixsize = FALSE},
++#endif
++};
++
++static ioctl_cmd Commands_Allowed_In_HostSleep[] = {
++ {.cmd = WLAN_SETONEINT_GETWORDCHAR,.subcmd = WLANVERSION,.fixsize =
++ FALSE},
++ {.cmd = WLANDEEPSLEEP,.subcmd = 1,.fixsize = FALSE},
++ {.cmd = WLANDEEPSLEEP,.subcmd = 0,.fixsize = FALSE},
++ {.cmd = WLAN_SETINT_GETINT,.subcmd = WLANSDIOCLOCK,.fixsize = TRUE},
++ {.cmd = WLAN_SET_GET_2K,.subcmd = WLAN_GET_CFP_TABLE,.fixsize = FALSE},
++#ifdef DEBUG_LEVEL1
++ {.cmd = WLAN_SET_GET_SIXTEEN_INT,.subcmd = WLAN_DRV_DBG,.fixsize = FALSE},
++#endif
++};
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++/********************************************************
++ Global Variables
++********************************************************/
++#ifdef DEBUG_LEVEL1
++#ifdef DEBUG_LEVEL2
++#define DEFAULT_DEBUG_MASK (0xffffffff & ~DBG_EVENT)
++#else
++#define DEFAULT_DEBUG_MASK (DBG_MSG | DBG_FATAL | DBG_ERROR)
++#endif
++u32 drvdbg = DEFAULT_DEBUG_MASK;
++u32 ifdbg = 0;
++#endif
++
++/********************************************************
++ Local Functions
++********************************************************/
++static int wlan_set_rate(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra);
++static int wlan_get_rate(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra);
++
++static int wlan_get_essid(struct net_device *dev,
++ struct iw_request_info *info, struct iw_point *dwrq,
++ char *extra);
++
++static int wlan_set_freq(struct net_device *dev, struct iw_request_info *info,
++ struct iw_freq *fwrq, char *extra);
++static int wlan_get_freq(struct net_device *dev, struct iw_request_info *info,
++ struct iw_freq *fwrq, char *extra);
++
++static int wlan_set_mode(struct net_device *dev, struct iw_request_info *info,
++ u32 * uwrq, char *extra);
++static int wlan_get_mode(struct net_device *dev, struct iw_request_info *info,
++ u32 * uwrq, char *extra);
++
++static int wlan_set_encode(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra);
++static int wlan_get_encode(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, u8 * extra);
++
++static int wlan_set_txpow(struct net_device *dev,
++ struct iw_request_info *info, struct iw_param *vwrq,
++ char *extra);
++static int wlan_get_txpow(struct net_device *dev,
++ struct iw_request_info *info, struct iw_param *vwrq,
++ char *extra);
++
++static int wlan_set_coalescing_ioctl(wlan_private * priv, struct iwreq *wrq);
++
++extern CHANNEL_FREQ_POWER *wlan_get_region_cfp_table(u8 region, u8 band,
++ int *cfp_no);
++
++/**
++ * @brief This function checks if the commans is allowed
++ * in deepsleep/hostsleep mode or not.
++ *
++ * @param req A pointer to ifreq structure
++ * @param cmd the command ID
++ * @return TRUE or FALSE
++ */
++static BOOLEAN
++Is_Command_Allowed_In_Sleep(struct ifreq *req, int cmd,
++ ioctl_cmd * allowed_cmds, int count)
++{
++ int subcmd = 0;
++ struct iwreq *wrq = (struct iwreq *) req;
++ int i;
++
++ for (i = 0; i < count; i++) {
++ if (cmd == allowed_cmds[i].cmd) {
++ if (allowed_cmds[i].subcmd == 0)
++ return TRUE;
++ if (allowed_cmds[i].fixsize == TRUE)
++ subcmd = (int) req->ifr_data;
++ else
++ subcmd = wrq->u.data.flags;
++ if (allowed_cmds[i].subcmd == subcmd)
++ return TRUE;
++ }
++ }
++ return FALSE;
++}
++
++/**
++ * @brief This function checks if the command is allowed.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return TRUE or FALSE
++ */
++BOOLEAN
++Is_Command_Allowed(wlan_private * priv)
++{
++ BOOLEAN ret = TRUE;
++
++ if (priv->adapter->bHostSleepConfigured) {
++ PRINTM(INFO, "IOCTLS called when WLAN access is blocked\n");
++ ret = FALSE;
++ }
++ if (!priv->adapter->IsAutoDeepSleepEnabled) {
++ if ((priv->adapter->IsDeepSleep == TRUE)) {
++ PRINTM(INFO, "IOCTLS called when station is in DeepSleep\n");
++ ret = FALSE;
++ }
++ }
++
++ return ret;
++}
++
++/**
++ * @brief Find a character in a string.
++ *
++ * @param s A pointer to string
++ * @param c Character to be located
++ * @param dlen the length of string
++ * @return A pointer to the first occurrence of c in string, or NULL if c is not found.
++ */
++static void *
++wlan_memchr(void *s, int c, int n)
++{
++ const u8 *p = s;
++
++ while (n-- != 0) {
++ if ((u8) c == *p++) {
++ return (void *) (p - 1);
++ }
++ }
++ return NULL;
++}
++
++#if WIRELESS_EXT > 14
++/**
++ * @brief Convert mw value to dbm value
++ *
++ * @param mw the value of mw
++ * @return the value of dbm
++ */
++static int
++mw_to_dbm(int mw)
++{
++ if (mw < 2)
++ return 0;
++ else if (mw < 3)
++ return 3;
++ else if (mw < 4)
++ return 5;
++ else if (mw < 6)
++ return 7;
++ else if (mw < 7)
++ return 8;
++ else if (mw < 8)
++ return 9;
++ else if (mw < 10)
++ return 10;
++ else if (mw < 13)
++ return 11;
++ else if (mw < 16)
++ return 12;
++ else if (mw < 20)
++ return 13;
++ else if (mw < 25)
++ return 14;
++ else if (mw < 32)
++ return 15;
++ else if (mw < 40)
++ return 16;
++ else if (mw < 50)
++ return 17;
++ else if (mw < 63)
++ return 18;
++ else if (mw < 79)
++ return 19;
++ else if (mw < 100)
++ return 20;
++ else
++ return 21;
++}
++
++/**
++ * @brief This function sends customized event to application.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @para str A pointer to event string
++ * @return n/a
++ */
++void
++send_iwevcustom_event(wlan_private * priv, s8 * str)
++{
++ union iwreq_data iwrq;
++ u8 buf[50];
++
++ ENTER();
++
++ memset(&iwrq, 0, sizeof(union iwreq_data));
++ memset(buf, 0, sizeof(buf));
++
++ snprintf(buf, sizeof(buf) - 1, "%s", str);
++
++ iwrq.data.pointer = buf;
++ iwrq.data.length = strlen(buf) + 1 + IW_EV_LCP_LEN;
++
++ /* Send Event to upper layer */
++ wireless_send_event(priv->wlan_dev.netdev, IWEVCUSTOM, &iwrq, buf);
++ PRINTM(INFO, "Wireless event %s is sent to app\n", str);
++
++ LEAVE();
++ return;
++}
++#endif
++
++/**
++ * @brief Find the channel frequency power info with specific channel
++ *
++ * @param adapter A pointer to wlan_adapter structure
++ * @param band it can be BAND_A, BAND_G or BAND_B
++ * @param channel the channel for looking
++ * @return A pointer to CHANNEL_FREQ_POWER structure or NULL if not find.
++ */
++CHANNEL_FREQ_POWER *
++find_cfp_by_band_and_channel(wlan_adapter * adapter, u8 band, u16 channel)
++{
++ CHANNEL_FREQ_POWER *cfp = NULL;
++
++ ENTER();
++
++ if (adapter->State11D.Enable11D == ENABLE_11D)
++ cfp =
++ get_cfp_by_band_and_channel(band, channel,
++ adapter->universal_channel);
++ else
++ cfp =
++ get_cfp_by_band_and_channel(band, channel,
++ adapter->region_channel);
++
++ return cfp;
++}
++
++/**
++ * @brief Find the channel frequency power info with specific frequency
++ *
++ * @param adapter A pointer to wlan_adapter structure
++ * @param band it can be BAND_A, BAND_G or BAND_B
++ * @param freq the frequency for looking
++ * @return Pointer to CHANNEL_FREQ_POWER structure; NULL if not found
++ */
++static CHANNEL_FREQ_POWER *
++find_cfp_by_band_and_freq(wlan_adapter * adapter, u8 band, u32 freq)
++{
++ CHANNEL_FREQ_POWER *cfp = NULL;
++ REGION_CHANNEL *rc;
++ int count = sizeof(adapter->region_channel) /
++ sizeof(adapter->region_channel[0]);
++ int i, j;
++
++ for (j = 0; !cfp && (j < count); j++) {
++ rc = &adapter->region_channel[j];
++
++ if (adapter->State11D.Enable11D == ENABLE_11D) {
++ rc = &adapter->universal_channel[j];
++ }
++
++ if (!rc->Valid || !rc->CFP)
++ continue;
++ if (rc->Band != band)
++ continue;
++ for (i = 0; i < rc->NrCFP; i++) {
++ if (rc->CFP[i].Freq == freq) {
++ cfp = &rc->CFP[i];
++ break;
++ }
++ }
++ }
++
++ if (!cfp && freq)
++ PRINTM(INFO, "find_cfp_by_band_and_freql(): cannot find cfp by "
++ "band %d & freq %d\n", band, freq);
++
++ return cfp;
++}
++
++#ifdef MFG_CMD_SUPPORT
++/**
++ * @brief Manufacturing command ioctl function
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS--success, otherwise--fail
++ */
++static int
++wlan_mfg_command(wlan_private * priv, struct iwreq *wrq)
++{
++ HostCmd_DS_GEN *pCmdPtr;
++ u8 *mfg_cmd;
++ u16 mfg_cmd_len;
++ int ret;
++
++ ENTER();
++
++ /* allocate MFG command buffer */
++ if (!(mfg_cmd = kmalloc(MRVDRV_SIZE_OF_CMD_BUFFER, GFP_KERNEL))) {
++ PRINTM(INFO, "allocate MFG command buffer failed!\n");
++ return -ENOMEM;
++ }
++
++ /* get MFG command header */
++ if (copy_from_user(mfg_cmd, wrq->u.data.pointer, sizeof(HostCmd_DS_GEN))) {
++ PRINTM(INFO, "copy from user failed: MFG command header\n");
++ ret = -EFAULT;
++ goto mfg_exit;
++ }
++
++ /* get the command size */
++ pCmdPtr = (HostCmd_DS_GEN *) mfg_cmd;
++ mfg_cmd_len = pCmdPtr->Size;
++ PRINTM(INFO, "MFG command len = %d\n", mfg_cmd_len);
++
++ if (mfg_cmd_len > MRVDRV_SIZE_OF_CMD_BUFFER) {
++ ret = -EINVAL;
++ goto mfg_exit;
++ }
++
++ /* get the whole command from user */
++ if (copy_from_user(mfg_cmd, wrq->u.data.pointer, mfg_cmd_len)) {
++ PRINTM(INFO, "copy from user failed: MFG command\n");
++ ret = -EFAULT;
++ goto mfg_exit;
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_MFG_COMMAND,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, mfg_cmd);
++
++ /* copy the response back to user */
++ if (!ret && pCmdPtr->Size) {
++ mfg_cmd_len = MIN(pCmdPtr->Size, mfg_cmd_len);
++ if (copy_to_user(wrq->u.data.pointer, mfg_cmd, mfg_cmd_len)) {
++ PRINTM(INFO, "copy to user failed: MFG command\n");
++ ret = -EFAULT;
++ }
++ wrq->u.data.length = mfg_cmd_len;
++ }
++
++ mfg_exit:
++ kfree(mfg_cmd);
++ LEAVE();
++ return ret;
++}
++#endif
++
++/**
++ * @brief Check if Rate Auto
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return TRUE/FALSE
++ */
++BOOLEAN
++Is_Rate_Auto(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int i;
++ int ratenum = 0;
++ int bitsize = 0;
++ bitsize = sizeof(Adapter->RateBitmap) * 8;
++ for (i = 0; i < bitsize; i++) {
++ if (Adapter->RateBitmap & (1 << i))
++ ratenum++;
++ if (ratenum > 1)
++ break;
++ }
++ if (ratenum > 1)
++ return TRUE;
++ else
++ return FALSE;
++}
++
++/**
++ * @brief Covert Rate Bitmap to Rate index
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return TRUE/FALSE
++ */
++int
++GetRateIndex(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int bitsize = sizeof(Adapter->RateBitmap) * 8;
++ int i;
++ for (i = 0; i < bitsize; i++) {
++ if (Adapter->RateBitmap & (1 << i))
++ return i;
++ }
++ return 0;
++}
++
++/**
++ * @brief Update Current Channel
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS--success, WLAN_STATUS_FAILURE--fail
++ */
++static int
++UpdateCurrentChannel(wlan_private * priv)
++{
++ int ret;
++
++ /*
++ ** the channel in f/w could be out of sync, get the current channel
++ */
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RF_CHANNEL,
++ HostCmd_OPT_802_11_RF_CHANNEL_GET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ PRINTM(INFO, "Current Channel = %d\n",
++ priv->adapter->CurBssParams.BSSDescriptor.Channel);
++
++ return ret;
++}
++
++/**
++ * @brief Set Current Channel
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param channel The channel to be set.
++ * @return WLAN_STATUS_SUCCESS--success, WLAN_STATUS_FAILURE--fail
++ */
++static int
++SetCurrentChannel(wlan_private * priv, int channel)
++{
++ PRINTM(INFO, "Set Channel = %d\n", channel);
++
++ /*
++ ** Current channel is not set to AdhocChannel requested, set channel
++ */
++ return (PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RF_CHANNEL,
++ HostCmd_OPT_802_11_RF_CHANNEL_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, &channel));
++}
++
++/**
++ * @brief Change Adhoc Channel
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param channel The channel to be set.
++ * @return WLAN_STATUS_SUCCESS--success, WLAN_STATUS_FAILURE--fail
++ */
++static int
++ChangeAdhocChannel(wlan_private * priv, int channel)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++
++ Adapter->AdhocChannel = channel;
++
++ UpdateCurrentChannel(priv);
++
++ if (Adapter->CurBssParams.BSSDescriptor.Channel == Adapter->AdhocChannel) {
++ /* AdhocChannel is set to the current Channel already */
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ PRINTM(INFO, "Updating Channel from %d to %d\n",
++ Adapter->CurBssParams.BSSDescriptor.Channel,
++ Adapter->AdhocChannel);
++
++ SetCurrentChannel(priv, Adapter->AdhocChannel);
++
++ UpdateCurrentChannel(priv);
++
++ if (Adapter->CurBssParams.BSSDescriptor.Channel != Adapter->AdhocChannel) {
++ PRINTM(INFO, "Failed to updated Channel to %d, channel = %d\n",
++ Adapter->AdhocChannel,
++ Adapter->CurBssParams.BSSDescriptor.Channel);
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ int i;
++ WLAN_802_11_SSID curAdhocSsid;
++
++ PRINTM(INFO, "Channel Changed while in an IBSS\n");
++
++ /* Copy the current ssid */
++ memcpy(&curAdhocSsid,
++ &Adapter->CurBssParams.BSSDescriptor.Ssid,
++ sizeof(WLAN_802_11_SSID));
++
++ /* Exit Adhoc mode */
++ PRINTM(INFO, "In ChangeAdhocChannel(): Sending Adhoc Stop\n");
++ ret = StopAdhocNetwork(priv);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ /* Scan for the network */
++ SendSpecificSSIDScan(priv, &curAdhocSsid);
++
++ // find out the BSSID that matches the current SSID
++ i = FindSSIDInList(Adapter, &curAdhocSsid, NULL, Wlan802_11IBSS);
++
++ if (i >= 0) {
++ PRINTM(INFO, "SSID found at %d in List," "so join\n", i);
++ JoinAdhocNetwork(priv, &Adapter->ScanTable[i]);
++ } else {
++ // else send START command
++ PRINTM(INFO, "SSID not found in list, "
++ "so creating adhoc with ssid = %s\n", curAdhocSsid.Ssid);
++ StartAdhocNetwork(priv, &curAdhocSsid);
++ } // end of else (START command)
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set/Get WPA IE
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param ie_data_ptr A pointer to IE
++ * @param ie_len Length of the IE
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_wpa_ie_helper(wlan_private * priv, u8 * ie_data_ptr, u16 ie_len)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (ie_len) {
++ if (ie_len > sizeof(Adapter->Wpa_ie)) {
++ PRINTM(INFO, "failed to copy WPA IE, too big \n");
++ return -EFAULT;
++ }
++ if (copy_from_user(Adapter->Wpa_ie, ie_data_ptr, ie_len)) {
++ PRINTM(INFO, "failed to copy WPA IE \n");
++ return -EFAULT;
++ }
++ Adapter->Wpa_ie_len = ie_len;
++ PRINTM(INFO, "Set Wpa_ie_len=%d IE=%#x\n",
++ Adapter->Wpa_ie_len, Adapter->Wpa_ie[0]);
++ HEXDUMP("Wpa_ie", Adapter->Wpa_ie, Adapter->Wpa_ie_len);
++
++ if (Adapter->Wpa_ie[0] == WPA_IE) {
++ Adapter->SecInfo.WPAEnabled = TRUE;
++ } else if (Adapter->Wpa_ie[0] == RSN_IE) {
++ Adapter->SecInfo.WPA2Enabled = TRUE;
++ } else {
++ Adapter->SecInfo.WPAEnabled = FALSE;
++ Adapter->SecInfo.WPA2Enabled = FALSE;
++ }
++ } else {
++ memset(Adapter->Wpa_ie, 0, sizeof(Adapter->Wpa_ie));
++ Adapter->Wpa_ie_len = ie_len;
++ PRINTM(INFO, "Reset Wpa_ie_len=%d IE=%#x\n",
++ Adapter->Wpa_ie_len, Adapter->Wpa_ie[0]);
++ Adapter->SecInfo.WPAEnabled = FALSE;
++ Adapter->SecInfo.WPA2Enabled = FALSE;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set/Get WPA IE
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_wpa_ie_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ return wlan_set_wpa_ie_helper(priv,
++ wrq->u.data.pointer, wrq->u.data.length);
++}
++
++/**
++ * @brief Set WPA key
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_encode_wpa(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ WLAN_802_11_KEY *pKey;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ pKey = (WLAN_802_11_KEY *) extra;
++
++ HEXDUMP("Key buffer: ", extra, dwrq->length);
++
++ // current driver only supports key length of up to 32 bytes
++ if (pKey->KeyLength > MRVL_MAX_WPA_KEY_LENGTH) {
++ PRINTM(INFO, " Error in key length \n");
++ return WLAN_STATUS_FAILURE;
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_KEY_MATERIAL,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP,
++ KEY_INFO_ENABLED, pKey);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/*
++ * iwconfig ethX key on: WEPEnabled;
++ * iwconfig ethX key off: WEPDisabled;
++ * iwconfig ethX key [x]: CurrentWepKeyIndex = x; WEPEnabled;
++ * iwconfig ethX key [x] kstr: WepKey[x] = kstr;
++ * iwconfig ethX key kstr: WepKey[CurrentWepKeyIndex] = kstr;
++ *
++ * all: Send command SET_WEP;
++ SetMacPacketFilter;
++ */
++
++/**
++ * @brief Set WEP key
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_encode_nonwpa(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ MRVL_WEP_KEY *pWep;
++ int index, PrevAuthMode;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ if (Adapter->CurrentWepKeyIndex >= MRVL_NUM_WEP_KEY)
++ Adapter->CurrentWepKeyIndex = 0;
++ pWep = &Adapter->WepKey[Adapter->CurrentWepKeyIndex];
++ PrevAuthMode = Adapter->SecInfo.AuthenticationMode;
++
++ index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
++
++ if (index >= 4) {
++ PRINTM(INFO, "Key index #%d out of range.\n", index + 1);
++ return -EINVAL;
++ }
++
++ PRINTM(INFO, "Flags=0x%x, Length=%d Index=%d CurrentWepKeyIndex=%d\n",
++ dwrq->flags, dwrq->length, index, Adapter->CurrentWepKeyIndex);
++
++ if (dwrq->length > 0) {
++ /* iwconfig ethX key [n] xxxxxxxxxxx
++ * Key has been provided by the user
++ */
++
++ /*
++ * Check the size of the key
++ */
++
++ if (dwrq->length > MAX_WEP_KEY_SIZE) {
++ return -EINVAL;
++ }
++
++ /*
++ * Check the index (none -> use current)
++ */
++
++ if (index < 0 || index > 3) //invalid index or no index
++ index = Adapter->CurrentWepKeyIndex;
++ else //index is given & valid
++ pWep = &Adapter->WepKey[index];
++
++ /*
++ * Check if the key is not marked as invalid
++ */
++ if (!(dwrq->flags & IW_ENCODE_NOKEY)) {
++ /* Cleanup */
++ memset(pWep, 0, sizeof(MRVL_WEP_KEY));
++
++ /* Copy the key in the driver */
++ memcpy(pWep->KeyMaterial, extra, dwrq->length);
++
++ /* Set the length */
++ if (dwrq->length > MIN_WEP_KEY_SIZE) {
++ pWep->KeyLength = MAX_WEP_KEY_SIZE;
++ } else {
++ if (dwrq->length > 0) {
++ pWep->KeyLength = MIN_WEP_KEY_SIZE;
++ } else {
++ /* Disable the key */
++ pWep->KeyLength = 0;
++ }
++ }
++ pWep->KeyIndex = index;
++
++ if (Adapter->SecInfo.WEPStatus != Wlan802_11WEPEnabled) {
++ /*
++ * The status is set as Key Absent
++ * so as to make sure we display the
++ * keys when iwlist ethX key is used
++ */
++ Adapter->SecInfo.WEPStatus = Wlan802_11WEPKeyAbsent;
++ }
++
++ PRINTM(INFO, "KeyIndex=%u KeyLength=%u\n",
++ pWep->KeyIndex, pWep->KeyLength);
++ HEXDUMP("WepKey", (u8 *) pWep->KeyMaterial, pWep->KeyLength);
++ }
++ } else {
++ /*
++ * No key provided so it is either enable key,
++ * on or off */
++ if (dwrq->flags & IW_ENCODE_DISABLED) {
++ PRINTM(INFO, "*** iwconfig ethX key off ***\n");
++
++ Adapter->SecInfo.WEPStatus = Wlan802_11WEPDisabled;
++ if (Adapter->SecInfo.AuthenticationMode ==
++ Wlan802_11AuthModeShared)
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeOpen;
++ } else {
++ /* iwconfig ethX key [n]
++ * iwconfig ethX key on
++ * Do we want to just set the transmit key index ?
++ */
++
++ if (index < 0 || index > 3) {
++ PRINTM(INFO, "*** iwconfig ethX key on ***\n");
++ index = Adapter->CurrentWepKeyIndex;
++ } else {
++ PRINTM(INFO, "*** iwconfig ethX key [x=%d] ***\n", index);
++ Adapter->CurrentWepKeyIndex = index;
++ }
++
++ /* Copy the required key as the current key */
++ pWep = &Adapter->WepKey[index];
++
++ if (!pWep->KeyLength) {
++ PRINTM(INFO, "Key not set,so cannot enable it\n");
++ return -EPERM;
++ }
++
++ Adapter->SecInfo.WEPStatus = Wlan802_11WEPEnabled;
++
++ HEXDUMP("KeyMaterial", (u8 *) pWep->KeyMaterial, pWep->KeyLength);
++ }
++ }
++
++ if (pWep->KeyLength) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SET_WEP,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_ADD_WEP, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ }
++
++ if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled) {
++ Adapter->CurrentPacketFilter |= HostCmd_ACT_MAC_WEP_ENABLE;
++ } else {
++ Adapter->CurrentPacketFilter &= ~HostCmd_ACT_MAC_WEP_ENABLE;
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_MAC_CONTROL,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, &Adapter->CurrentPacketFilter);
++
++ if (dwrq->flags & IW_ENCODE_RESTRICTED) {
++ /* iwconfig ethX restricted key [1] */
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeShared;
++ PRINTM(INFO, "Auth mode restricted!\n");
++ } else if (dwrq->flags & IW_ENCODE_OPEN) {
++ /* iwconfig ethX key [2] open */
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeOpen;
++ PRINTM(INFO, "Auth mode open!\n");
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set RX Antenna
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param Mode RF antenna mode
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++SetRxAntenna(wlan_private * priv, int Mode)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++
++ if (Mode != RF_ANTENNA_1 && Mode != RF_ANTENNA_2
++ && Mode != RF_ANTENNA_AUTO) {
++ return -EINVAL;
++ }
++
++ Adapter->RxAntennaMode = Mode;
++
++ PRINTM(INFO, "SET RX Antenna Mode to 0x%04x\n", Adapter->RxAntennaMode);
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RF_ANTENNA,
++ HostCmd_ACT_SET_RX, HostCmd_OPTION_WAITFORRSP,
++ 0, &Adapter->RxAntennaMode);
++ return ret;
++}
++
++/**
++ * @brief Set TX Antenna
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param Mode RF antenna mode
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++SetTxAntenna(wlan_private * priv, int Mode)
++{
++ int ret = 0;
++ wlan_adapter *Adapter = priv->adapter;
++
++ if ((Mode != RF_ANTENNA_1) && (Mode != RF_ANTENNA_2)
++ && (Mode != RF_ANTENNA_AUTO)) {
++ return -EINVAL;
++ }
++
++ Adapter->TxAntennaMode = Mode;
++
++ PRINTM(INFO, "SET TX Antenna Mode to 0x%04x\n", Adapter->TxAntennaMode);
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RF_ANTENNA,
++ HostCmd_ACT_SET_TX, HostCmd_OPTION_WAITFORRSP,
++ 0, &Adapter->TxAntennaMode);
++
++ return ret;
++}
++
++/**
++ * @brief Get RX Antenna
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param buf A pointer to recieve antenna mode
++ * @return length of buf
++ */
++static int
++GetRxAntenna(wlan_private * priv, char *buf)
++{
++ int ret = 0;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ // clear it, so we will know if the value
++ // returned below is correct or not.
++ Adapter->RxAntennaMode = 0;
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RF_ANTENNA,
++ HostCmd_ACT_GET_RX, HostCmd_OPTION_WAITFORRSP,
++ 0, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ PRINTM(INFO, "Get Rx Antenna Mode:0x%04x\n", Adapter->RxAntennaMode);
++
++ LEAVE();
++
++ return sprintf(buf, "0x%04x", Adapter->RxAntennaMode) + 1;
++}
++
++/**
++ * @brief Get TX Antenna
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param buf A pointer to recieve antenna mode
++ * @return length of buf
++ */
++static int
++GetTxAntenna(wlan_private * priv, char *buf)
++{
++ int ret = 0;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ // clear it, so we will know if the value
++ // returned below is correct or not.
++ Adapter->TxAntennaMode = 0;
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RF_ANTENNA,
++ HostCmd_ACT_GET_TX, HostCmd_OPTION_WAITFORRSP,
++ 0, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ PRINTM(INFO, "Get Tx Antenna Mode:0x%04x\n", Adapter->TxAntennaMode);
++
++ LEAVE();
++
++ return sprintf(buf, "0x%04x", Adapter->TxAntennaMode) + 1;
++}
++
++/**
++ * @brief Set Radio On/OFF
++ *
++ * @param priv A pointer to wlan_private structure
++ * @option Radio Option
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_radio_ioctl(wlan_private * priv, u8 option)
++{
++ int ret = 0;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (Adapter->RadioOn != option) {
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ PRINTM(MSG, "Cannot turn radio off in connected state.\n");
++ LEAVE();
++ return -EINVAL;
++ }
++
++ PRINTM(INFO, "Switching %s the Radio\n", option ? "On" : "Off");
++ Adapter->RadioOn = option;
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RADIO_CONTROL,
++ HostCmd_ACT_GEN_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++ }
++
++ LEAVE();
++ return ret;
++}
++
++#ifdef REASSOCIATION
++/**
++ * @brief Set Auto Reassociation On
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++reassociation_on(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ Adapter->Reassoc_on = TRUE;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set Auto Reassociation Off
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++reassociation_off(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (Adapter->ReassocTimerIsSet == TRUE) {
++ CancelTimer(&Adapter->MrvDrvTimer);
++ Adapter->ReassocTimerIsSet = FALSE;
++ }
++
++ Adapter->Reassoc_on = FALSE;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++#endif /* REASSOCIATION */
++
++/**
++ * @brief Set Region
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param region_code region code
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_region(wlan_private * priv, u16 region_code)
++{
++ int i;
++
++ ENTER();
++
++ for (i = 0; i < MRVDRV_MAX_REGION_CODE; i++) {
++ // use the region code to search for the index
++ if (region_code == RegionCodeToIndex[i]) {
++ priv->adapter->RegionCode = region_code;
++ break;
++ }
++ }
++
++ // if it's unidentified region code
++ if (i >= MRVDRV_MAX_REGION_CODE) {
++ PRINTM(INFO, "Region Code not identified\n");
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++ }
++
++ if (wlan_set_regiontable(priv, priv->adapter->RegionCode, 0)) {
++ LEAVE();
++ return -EINVAL;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Copy Rates
++ *
++ * @param dest A pointer to Dest Buf
++ * @param src A pointer to Src Buf
++ * @param len The len of Src Buf
++ * @return Number of Rates copyed
++ */
++static inline int
++CopyRates(u8 * dest, int pos, u8 * src, int len)
++{
++ int i;
++
++ for (i = 0; i < len && src[i]; i++, pos++) {
++ if (pos >= sizeof(WLAN_802_11_RATES))
++ break;
++ dest[pos] = src[i];
++ }
++
++ return pos;
++}
++
++/**
++ * @brief Get active data rates
++ *
++ * @param Adapter A pointer to wlan_adapter structure
++ * @param rate The buf to return the active rates
++ * @return The number of Rates
++ */
++static int
++get_active_data_rates(wlan_adapter * Adapter, WLAN_802_11_RATES rates)
++{
++ int k = 0;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus != WlanMediaStateConnected) {
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure) {
++ //Infra. mode
++ PRINTM(INFO, "Infra\n");
++ k = CopyRates(rates, k, SupportedRates, sizeof(SupportedRates));
++ } else {
++ //ad-hoc mode
++ PRINTM(INFO, "Adhoc G\n");
++ k = CopyRates(rates, k, AdhocRates_G, sizeof(AdhocRates_G));
++ }
++ } else {
++ k = CopyRates(rates, 0, Adapter->CurBssParams.DataRates,
++ Adapter->CurBssParams.NumOfRates);
++ }
++
++ LEAVE();
++
++ return k;
++}
++
++/**
++ * @brief Get/Set Per packet TX Control flags
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_txcontrol(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data[3];
++ int ret;
++
++ ENTER();
++
++ ret = WLAN_STATUS_SUCCESS;
++
++ switch (wrq->u.data.length) {
++ case 0:
++ /*
++ * Get the Global setting for TxCtrl
++ */
++ if (copy_to_user(wrq->u.data.pointer,
++ &Adapter->PktTxCtrl, sizeof(u32))) {
++ PRINTM(INFO, "copy_to_user failed!\n");
++ ret = -EFAULT;
++ } else {
++ wrq->u.data.length = 1;
++ }
++ break;
++
++ case 1:
++ /*
++ * Set the Global setting for TxCtrl
++ */
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ ret = -EFAULT;
++ } else {
++ Adapter->PktTxCtrl = data[0];
++ PRINTM(INFO, "PktTxCtrl set: 0x%08x\n", Adapter->PktTxCtrl);
++ }
++ break;
++
++ case 2:
++ /*
++ * Get the per User Priority setting for TxCtrl for the given UP
++ */
++ if (copy_from_user(data, wrq->u.data.pointer, sizeof(int) * 2)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ ret = -EFAULT;
++
++ } else if (data[1] >= NELEMENTS(Adapter->wmm.userPriPktTxCtrl)) {
++ /* Range check the UP input from user space */
++ PRINTM(INFO, "User priority out of range\n");
++ ret = -EINVAL;
++
++ } else if (Adapter->wmm.userPriPktTxCtrl[data[1]]) {
++ data[2] = Adapter->wmm.userPriPktTxCtrl[data[1]];
++
++ /* User priority setting is valid, return it */
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int) * 3)) {
++ PRINTM(INFO, "copy_to_user failed!\n");
++ ret = -EFAULT;
++ } else {
++ wrq->u.data.length = 3;
++ }
++
++ } else {
++ /* Return the global setting since the UP set is zero */
++ data[2] = Adapter->PktTxCtrl;
++
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int) * 3)) {
++ PRINTM(INFO, "copy_to_user failed!\n");
++ ret = -EFAULT;
++ } else {
++ wrq->u.data.length = 3;
++ }
++ }
++ break;
++
++ case 3:
++ /*
++ * Set the per User Priority setting for TxCtrl for the given UP
++ */
++
++ if (copy_from_user(data, wrq->u.data.pointer, sizeof(int) * 3)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ ret = -EFAULT;
++ } else if (data[1] >= NELEMENTS(Adapter->wmm.userPriPktTxCtrl)) {
++ PRINTM(INFO, "User priority out of range\n");
++ ret = -EINVAL;
++ } else {
++ Adapter->wmm.userPriPktTxCtrl[data[1]] = data[2];
++
++ if (Adapter->wmm.userPriPktTxCtrl[data[1]] == 0) {
++ /* Return the global setting since the UP set is zero */
++ data[2] = Adapter->PktTxCtrl;
++ }
++
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int) * 3)) {
++ PRINTM(INFO, "copy_to_user failed!\n");
++ ret = -EFAULT;
++ } else {
++ wrq->u.data.length = 3;
++ }
++ }
++ break;
++
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Enable/Disable atim uapsd null package generation
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_null_pkg_gen(wlan_private * priv, struct iwreq *wrq)
++{
++ int data;
++ wlan_adapter *Adapter = priv->adapter;
++ int *val;
++
++ ENTER();
++
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ PRINTM(INFO, "Enable UAPSD NULL PKG: %s\n",
++ (data == CMD_ENABLED) ? "Enable" : "Disable");
++ switch (data) {
++ case CMD_ENABLED:
++ Adapter->gen_null_pkg = TRUE;
++ break;
++ case CMD_DISABLED:
++ Adapter->gen_null_pkg = FALSE;
++ break;
++ default:
++ break;
++ }
++
++ data = (Adapter->gen_null_pkg == TRUE) ? CMD_ENABLED : CMD_DISABLED;
++ val = (int *) wrq->u.name;
++ *val = data;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set NULL Package generation interval
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_null_pkt_interval(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data;
++ ENTER();
++
++ if ((int) wrq->u.data.length == 0) {
++ data = Adapter->NullPktInterval;
++
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(MSG, "copy_to_user failed!\n");
++ return -EFAULT;
++ }
++ } else {
++ if ((int) wrq->u.data.length > 1) {
++ PRINTM(MSG, "ioctl too many args!\n");
++ return -EFAULT;
++ }
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ Adapter->NullPktInterval = data;
++ }
++
++ wrq->u.data.length = 1;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set Adhoc awake period
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_adhoc_awake_period(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data;
++ ENTER();
++
++ if ((int) wrq->u.data.length == 0) {
++ data = Adapter->AdhocAwakePeriod;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(MSG, "copy_to_user failed!\n");
++ return -EFAULT;
++ }
++ } else {
++ if ((int) wrq->u.data.length > 1) {
++ PRINTM(MSG, "ioctl too many args!\n");
++ return -EFAULT;
++ }
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++#define AWAKE_PERIOD_MIN 1
++#define AWAKE_PERIOD_MAX 31
++#define DISABLE_AWAKE_PERIOD 0xff
++ if ((((data & 0xff) >= AWAKE_PERIOD_MIN) &&
++ ((data & 0xff) <= AWAKE_PERIOD_MAX)) ||
++ ((data & 0xff) == DISABLE_AWAKE_PERIOD))
++ Adapter->AdhocAwakePeriod = (u16) data;
++ else {
++ PRINTM(INFO,
++ "Invalid parameter, AdhocAwakePeriod not changed.\n");
++ return -EINVAL;
++
++ }
++ }
++ wrq->u.data.length = 1;
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set bcn missing timeout
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_bcn_miss_timeout(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data;
++ ENTER();
++
++ if ((int) wrq->u.data.length == 0) {
++ data = Adapter->BCNMissTimeOut;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(MSG, "copy_to_user failed!\n");
++ return -EFAULT;
++ }
++ } else {
++ if ((int) wrq->u.data.length > 1) {
++ PRINTM(MSG, "ioctl too many args!\n");
++ return -EFAULT;
++ }
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ if (((data >= 0) && (data <= 50)) || (data == 0xffff))
++ Adapter->BCNMissTimeOut = (u16) data;
++ else {
++ PRINTM(INFO,
++ "Invalid parameter, BCN Missing timeout not changed.\n");
++ return -EINVAL;
++
++ }
++ }
++
++ wrq->u.data.length = 1;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set adhoc g proctection
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_adhoc_g_protection(wlan_private * priv, struct iwreq *wrq)
++{
++ int data;
++ int *val;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++#define ADHOC_G_PROTECTION_ON 1
++#define ADHOC_G_PROTECTION_OFF 0
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++
++ switch (data) {
++ case CMD_DISABLED:
++ Adapter->CurrentPacketFilter &=
++ ~HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON;
++ break;
++ case CMD_ENABLED:
++ Adapter->CurrentPacketFilter |= HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON;
++ break;
++
++ case CMD_GET:
++ if (Adapter->
++ CurrentPacketFilter & HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON)
++ data = ADHOC_G_PROTECTION_ON;
++ else
++ data = ADHOC_G_PROTECTION_OFF;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ val = (int *) wrq->u.name;
++ *val = data;
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++#define USE_RTS_CTS 1
++#define USE_CTS_TO_SELF 0
++/**
++ * @brief GetSet RTS/CTS or CTS to self.
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_rts_cts_ctrl(wlan_private * priv, struct iwreq *wrq)
++{
++ int data;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = 0;
++ ENTER();
++
++ if ((int) wrq->u.data.length == 0) {
++ if (Adapter->CurrentPacketFilter & HostCmd_ACT_MAC_RTS_CTS_ENABLE)
++ data = USE_RTS_CTS;
++ else
++ data = USE_CTS_TO_SELF;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(MSG, "copy_to_user failed!\n");
++ return -EFAULT;
++ }
++ } else {
++ if ((int) wrq->u.data.length > 1) {
++ PRINTM(MSG, "ioctl too many args!\n");
++ return -EFAULT;
++ }
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ if (data == USE_RTS_CTS) {
++ Adapter->CurrentPacketFilter |= HostCmd_ACT_MAC_RTS_CTS_ENABLE;
++ } else {
++ Adapter->CurrentPacketFilter &= ~HostCmd_ACT_MAC_RTS_CTS_ENABLE;
++ }
++ PRINTM(INFO, "Adapter->CurrentPacketFilter=0x%x\n",
++ Adapter->CurrentPacketFilter);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_MAC_CONTROL,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, &Adapter->CurrentPacketFilter);
++ }
++ wrq->u.data.length = 1;
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set sdio mode
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_sdio_mode(wlan_private * priv, struct iwreq *wrq)
++{
++ int data;
++ int bus_width;
++ wlan_adapter *Adapter = priv->adapter;
++ ENTER();
++
++ if ((int) wrq->u.data.length == 0) {
++ data = 4;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(MSG, "copy_to_user failed!\n");
++ return -EFAULT;
++ }
++ } else {
++ if ((int) wrq->u.data.length > 1) {
++ PRINTM(MSG, "ioctl too many args!\n");
++ return -EFAULT;
++ }
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ if ((data != 1) && (data != 4))
++ return -EFAULT;
++ bus_width = 4;
++ if (bus_width != data)
++ Adapter->sdiomode = (u8) data;
++ }
++ wrq->u.data.length = 1;
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set LDO config
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to wrq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_ldo_config(wlan_private * priv, struct iwreq *wrq)
++{
++ HostCmd_DS_802_11_LDO_CONFIG ldocfg;
++ int data = 0;
++ u16 action;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (wrq->u.data.length == 0) {
++ action = HostCmd_ACT_GEN_GET;
++ } else if (wrq->u.data.length > 1) {
++ PRINTM(MSG, "ioctl too many args!\n");
++ ret = -EFAULT;
++ goto ldoexit;
++ } else {
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ ret = -EFAULT;
++ goto ldoexit;
++ }
++ if (data != LDO_INTERNAL && data != LDO_EXTERNAL) {
++ PRINTM(MSG, "Invalid parameter, LDO config not changed.\n");
++ ret = -EFAULT;
++ goto ldoexit;
++ }
++ action = HostCmd_ACT_GEN_SET;
++ }
++ ldocfg.Action = action;
++ ldocfg.PMSource = (u16) data;
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_LDO_CONFIG,
++ action, HostCmd_OPTION_WAITFORRSP,
++ 0, (void *) &ldocfg);
++
++ if (!ret && action == HostCmd_ACT_GEN_GET) {
++ data = (int) ldocfg.PMSource;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ ret = -EFAULT;
++ goto ldoexit;
++ }
++ wrq->u.data.length = 1;
++ }
++
++ ldoexit:
++ LEAVE();
++ return ret;
++}
++
++#ifdef DEBUG_LEVEL1
++/**
++ * @brief Get/Set the bit mask of driver debug message control
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to wrq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_drv_dbg(wlan_private * priv, struct iwreq *wrq)
++{
++ int data[4];
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (wrq->u.data.length == 0) {
++ data[0] = drvdbg;
++ data[1] = ifdbg;
++ /* Return the current driver debug bit masks */
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int) * 2)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ ret = -EFAULT;
++ goto drvdbgexit;
++ }
++ wrq->u.data.length = 2;
++ } else if (wrq->u.data.length < 3) {
++ /* Get the driver debug bit masks */
++ if (copy_from_user
++ (data, wrq->u.data.pointer, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ ret = -EFAULT;
++ goto drvdbgexit;
++ }
++ drvdbg = data[0];
++ if (wrq->u.data.length == 2)
++ ifdbg = data[1];
++ } else {
++ PRINTM(INFO, "Invalid parameter number\n");
++ goto drvdbgexit;
++ }
++
++ printk(KERN_ALERT "drvdbg = 0x%x\n", drvdbg);
++#ifdef DEBUG_LEVEL2
++ printk(KERN_ALERT "INFO (%08x) %s\n", DBG_INFO,
++ (drvdbg & DBG_INFO) ? "X" : "");
++ printk(KERN_ALERT "WARN (%08x) %s\n", DBG_WARN,
++ (drvdbg & DBG_WARN) ? "X" : "");
++ printk(KERN_ALERT "ENTRY (%08x) %s\n", DBG_ENTRY,
++ (drvdbg & DBG_ENTRY) ? "X" : "");
++#endif
++ printk(KERN_ALERT "FW_D (%08x) %s\n", DBG_FW_D,
++ (drvdbg & DBG_FW_D) ? "X" : "");
++ printk(KERN_ALERT "CMD_D (%08x) %s\n", DBG_CMD_D,
++ (drvdbg & DBG_CMD_D) ? "X" : "");
++ printk(KERN_ALERT "DAT_D (%08x) %s\n", DBG_DAT_D,
++ (drvdbg & DBG_DAT_D) ? "X" : "");
++
++ printk(KERN_ALERT "INTR (%08x) %s\n", DBG_INTR,
++ (drvdbg & DBG_INTR) ? "X" : "");
++ printk(KERN_ALERT "EVENT (%08x) %s\n", DBG_EVENT,
++ (drvdbg & DBG_EVENT) ? "X" : "");
++ printk(KERN_ALERT "CMND (%08x) %s\n", DBG_CMND,
++ (drvdbg & DBG_CMND) ? "X" : "");
++ printk(KERN_ALERT "DATA (%08x) %s\n", DBG_DATA,
++ (drvdbg & DBG_DATA) ? "X" : "");
++ printk(KERN_ALERT "ERROR (%08x) %s\n", DBG_ERROR,
++ (drvdbg & DBG_ERROR) ? "X" : "");
++ printk(KERN_ALERT "FATAL (%08x) %s\n", DBG_FATAL,
++ (drvdbg & DBG_FATAL) ? "X" : "");
++ printk(KERN_ALERT "MSG (%08x) %s\n", DBG_MSG,
++ (drvdbg & DBG_MSG) ? "X" : "");
++ printk(KERN_ALERT "ifdbg = 0x%x\n", ifdbg);
++ printk(KERN_ALERT "IF_D (%08x) %s\n", DBG_IF_D,
++ (ifdbg & DBG_IF_D) ? "X" : "");
++
++ drvdbgexit:
++ LEAVE();
++ return ret;
++}
++#endif
++
++/**
++ * @brief Commit handler: called after a bunch of SET operations
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_config_commit(struct net_device *dev,
++ struct iw_request_info *info, char *cwrq, char *extra)
++{
++ ENTER();
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get protocol name
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_name(struct net_device *dev, struct iw_request_info *info,
++ char *cwrq, char *extra)
++{
++ const char *cp;
++ char comm[6] = { "COMM-" };
++ char mrvl[6] = { "MRVL-" };
++ int cnt;
++
++ ENTER();
++
++ strcpy(cwrq, mrvl);
++
++ cp = strstr(driver_version, comm);
++ if (cp == driver_version) //skip leading "COMM-"
++ cp = driver_version + strlen(comm);
++ else
++ cp = driver_version;
++
++ cnt = strlen(mrvl);
++ cwrq += cnt;
++ while (cnt < 16 && (*cp != '-')) {
++ *cwrq++ = toupper(*cp++);
++ cnt++;
++ }
++ *cwrq = '\0';
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get frequency
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param fwrq A pointer to iw_freq structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_freq(struct net_device *dev, struct iw_request_info *info,
++ struct iw_freq *fwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ CHANNEL_FREQ_POWER *cfp;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ cfp = find_cfp_by_band_and_channel(Adapter, 0,
++ (u16) Adapter->CurBssParams.
++ BSSDescriptor.Channel);
++
++ if (!cfp) {
++ if (Adapter->CurBssParams.BSSDescriptor.Channel) {
++ PRINTM(INFO, "Invalid channel=%d\n",
++ Adapter->CurBssParams.BSSDescriptor.Channel);
++ }
++ return -EINVAL;
++ }
++
++ fwrq->m = (long) cfp->Freq * 100000;
++ fwrq->e = 1;
++
++ PRINTM(INFO, "freq=%u\n", fwrq->m);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get current BSSID
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param awrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_wap(struct net_device *dev, struct iw_request_info *info,
++ struct sockaddr *awrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ memcpy(awrq->sa_data,
++ Adapter->CurBssParams.BSSDescriptor.MacAddress, ETH_ALEN);
++ } else {
++ memset(awrq->sa_data, 0, ETH_ALEN);
++ }
++ awrq->sa_family = ARPHRD_ETHER;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set Adapter Node Name
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_nick(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ /*
++ * Check the size of the string
++ */
++
++ if (dwrq->length > 16) {
++ return -E2BIG;
++ }
++
++ memset(Adapter->nodeName, 0, sizeof(Adapter->nodeName));
++ memcpy(Adapter->nodeName, extra, dwrq->length);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get Adapter Node Name
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_nick(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ /*
++ * Get the Nick Name saved
++ */
++
++ strncpy(extra, Adapter->nodeName, 16);
++
++ extra[16] = '\0';
++
++ /*
++ * If none, we may want to get the one that was set
++ */
++
++ /*
++ * Push it out !
++ */
++#if WIRELESS_EXT > 20
++ dwrq->length = strlen(extra);
++#else
++ dwrq->length = strlen(extra) + 1;
++#endif
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set RTS threshold
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_rts(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int rthr = vwrq->value;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ if (vwrq->disabled) {
++ Adapter->RTSThsd = rthr = MRVDRV_RTS_MAX_VALUE;
++ } else {
++ if (rthr < MRVDRV_RTS_MIN_VALUE || rthr > MRVDRV_RTS_MAX_VALUE)
++ return -EINVAL;
++ Adapter->RTSThsd = rthr;
++ }
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SNMP_MIB,
++ HostCmd_ACT_SET, HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_RTS_THRESHOLD, &rthr);
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get RTS threshold
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_rts(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ Adapter->RTSThsd = 0;
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SNMP_MIB,
++ HostCmd_ACT_GET, HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_RTS_THRESHOLD, NULL);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ vwrq->value = Adapter->RTSThsd;
++ vwrq->disabled = ((vwrq->value < MRVDRV_RTS_MIN_VALUE)
++ || (vwrq->value > MRVDRV_RTS_MAX_VALUE));
++ vwrq->fixed = 1;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set Fragment threshold
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_frag(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ int fthr = vwrq->value;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ if (vwrq->disabled) {
++ Adapter->FragThsd = fthr = MRVDRV_FRAG_MAX_VALUE;
++ } else {
++ if (fthr < MRVDRV_FRAG_MIN_VALUE || fthr > MRVDRV_FRAG_MAX_VALUE)
++ return -EINVAL;
++ Adapter->FragThsd = fthr;
++ }
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SNMP_MIB,
++ HostCmd_ACT_SET, HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_FRAGMENTATION_THRESHOLD, &fthr);
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get Fragment threshold
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_frag(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ Adapter->FragThsd = 0;
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SNMP_MIB, HostCmd_ACT_GET,
++ HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_FRAGMENTATION_THRESHOLD, NULL);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ vwrq->value = Adapter->FragThsd;
++ vwrq->disabled = ((vwrq->value < MRVDRV_FRAG_MIN_VALUE)
++ || (vwrq->value > MRVDRV_FRAG_MAX_VALUE));
++ vwrq->fixed = 1;
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get Wlan Mode
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_mode(struct net_device *dev,
++ struct iw_request_info *info, u32 * uwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *adapter = priv->adapter;
++
++ ENTER();
++
++ switch (adapter->InfrastructureMode) {
++ case Wlan802_11IBSS:
++ *uwrq = IW_MODE_ADHOC;
++ break;
++
++ case Wlan802_11Infrastructure:
++ *uwrq = IW_MODE_INFRA;
++ break;
++
++ default:
++ case Wlan802_11AutoUnknown:
++ *uwrq = IW_MODE_AUTO;
++ break;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get Encryption key
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_encode(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, u8 * extra)
++{
++
++ wlan_private *priv = dev->priv;
++ wlan_adapter *adapter = priv->adapter;
++ int index = (dwrq->flags & IW_ENCODE_INDEX);
++
++ ENTER();
++
++ PRINTM(INFO, "flags=0x%x index=%d length=%d CurrentWepKeyIndex=%d\n",
++ dwrq->flags, index, dwrq->length, adapter->CurrentWepKeyIndex);
++ if (index < 0 || index > 4) {
++ PRINTM(INFO, "Key index #%d out of range.\n", index);
++ LEAVE();
++ return -EINVAL;
++ }
++ if (adapter->CurrentWepKeyIndex >= MRVL_NUM_WEP_KEY)
++ adapter->CurrentWepKeyIndex = 0;
++ dwrq->flags = 0;
++
++ /*
++ * Check encryption mode
++ */
++
++ switch (adapter->SecInfo.AuthenticationMode) {
++ case Wlan802_11AuthModeOpen:
++ dwrq->flags = IW_ENCODE_OPEN;
++ break;
++
++ case Wlan802_11AuthModeShared:
++ case Wlan802_11AuthModeNetworkEAP:
++ dwrq->flags = IW_ENCODE_RESTRICTED;
++ break;
++ default:
++ dwrq->flags = IW_ENCODE_DISABLED | IW_ENCODE_OPEN;
++ break;
++ }
++
++ if ((adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled)
++ || (adapter->SecInfo.WEPStatus == Wlan802_11WEPKeyAbsent)
++ || adapter->SecInfo.WPAEnabled || adapter->SecInfo.WPA2Enabled) {
++ dwrq->flags &= ~IW_ENCODE_DISABLED;
++ } else {
++ dwrq->flags |= IW_ENCODE_DISABLED;
++ }
++
++ memset(extra, 0, 16);
++
++ if (!index) {
++ /* Handle current key request */
++ if ((adapter->WepKey[adapter->CurrentWepKeyIndex].KeyLength) &&
++ (adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled)) {
++ index = adapter->WepKey[adapter->CurrentWepKeyIndex].KeyIndex;
++ memcpy(extra, adapter->WepKey[index].KeyMaterial,
++ adapter->WepKey[index].KeyLength);
++ dwrq->length = adapter->WepKey[index].KeyLength;
++ /* return current key */
++ dwrq->flags |= (index + 1);
++ /* return WEP enabled */
++ dwrq->flags &= ~IW_ENCODE_DISABLED;
++ } else if ((adapter->SecInfo.WPAEnabled)
++ || (adapter->SecInfo.WPA2Enabled)
++ ) {
++ /* return WPA enabled */
++ dwrq->flags &= ~IW_ENCODE_DISABLED;
++ } else {
++ dwrq->flags |= IW_ENCODE_DISABLED;
++ }
++ } else {
++ /* Handle specific key requests */
++ index--;
++ if (adapter->WepKey[index].KeyLength) {
++ memcpy(extra, adapter->WepKey[index].KeyMaterial,
++ adapter->WepKey[index].KeyLength);
++ dwrq->length = adapter->WepKey[index].KeyLength;
++ /* return current key */
++ dwrq->flags |= (index + 1);
++ /* return WEP enabled */
++ dwrq->flags &= ~IW_ENCODE_DISABLED;
++ } else if ((adapter->SecInfo.WPAEnabled)
++ || (adapter->SecInfo.WPA2Enabled)
++ ) {
++ /* return WPA enabled */
++ dwrq->flags &= ~IW_ENCODE_DISABLED;
++ } else {
++ dwrq->flags |= IW_ENCODE_DISABLED;
++ }
++ }
++
++ dwrq->flags |= IW_ENCODE_NOKEY;
++
++ PRINTM(INFO, "Key:%02x:%02x:%02x:%02x:%02x:%02x KeyLen=%d\n",
++ extra[0], extra[1], extra[2],
++ extra[3], extra[4], extra[5], dwrq->length);
++
++ PRINTM(INFO, "Return flags=0x%x\n", dwrq->flags);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get TX Power
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_txpow(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RF_TX_POWER,
++ HostCmd_ACT_GEN_GET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ PRINTM(INFO, "TXPOWER GET %d dbm.\n", Adapter->TxPowerLevel);
++ vwrq->value = Adapter->TxPowerLevel;
++ vwrq->fixed = 1;
++ if (Adapter->RadioOn) {
++ vwrq->disabled = 0;
++ vwrq->flags = IW_TXPOW_DBM;
++ } else {
++ vwrq->disabled = 1;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set TX Retry Count
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_retry(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *adapter = priv->adapter;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ if (vwrq->flags == IW_RETRY_LIMIT) {
++ /* The MAC has a 4-bit Total_Tx_Count register
++ Total_Tx_Count = 1 + Tx_Retry_Count */
++#define TX_RETRY_MIN 0
++#define TX_RETRY_MAX 14
++ if (vwrq->value < TX_RETRY_MIN || vwrq->value > TX_RETRY_MAX)
++ return -EINVAL;
++
++ /* Set Tx retry count */
++ adapter->TxRetryCount = vwrq->value + 1;
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SNMP_MIB,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_TX_RETRYCOUNT, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ } else {
++ return -EOPNOTSUPP;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get TX Retry Count
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_retry(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ Adapter->TxRetryCount = 0;
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SNMP_MIB, HostCmd_ACT_GET,
++ HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_TX_RETRYCOUNT, NULL);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ vwrq->disabled = 0;
++ if (!vwrq->flags) {
++ vwrq->flags = IW_RETRY_LIMIT;
++ /* Get Tx retry count */
++ vwrq->value = Adapter->TxRetryCount - 1;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Sort Channels
++ *
++ * @param freq A pointer to iw_freq structure
++ * @param num number of Channels
++ * @return NA
++ */
++static inline void
++sort_channels(struct iw_freq *freq, int num)
++{
++ int i, j;
++ struct iw_freq temp;
++
++ for (i = 0; i < num; i++)
++ for (j = i + 1; j < num; j++)
++ if (freq[i].i > freq[j].i) {
++ temp.i = freq[i].i;
++ temp.m = freq[i].m;
++
++ freq[i].i = freq[j].i;
++ freq[i].m = freq[j].m;
++
++ freq[j].i = temp.i;
++ freq[j].m = temp.m;
++ }
++}
++
++/* data rate listing
++ MULTI_BANDS:
++ abg a b b/g
++ Infra G(12) A(8) B(4) G(12)
++ Adhoc A+B(12) A(8) B(4) B(4)
++
++ non-MULTI_BANDS:
++ b b/g
++ Infra B(4) G(12)
++ Adhoc B(4) B(4)
++ */
++/**
++ * @brief Get Range Info
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_range(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ int i, j;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ struct iw_range *range = (struct iw_range *) extra;
++ CHANNEL_FREQ_POWER *cfp;
++ WLAN_802_11_RATES rates;
++
++ ENTER();
++
++ dwrq->length = sizeof(struct iw_range);
++ memset(range, 0, sizeof(struct iw_range));
++
++ range->min_nwid = 0;
++ range->max_nwid = 0;
++
++ memset(rates, 0, sizeof(rates));
++ range->num_bitrates = get_active_data_rates(Adapter, rates);
++ if (range->num_bitrates > sizeof(rates))
++ range->num_bitrates = sizeof(rates);
++
++ for (i = 0; i < MIN(range->num_bitrates, IW_MAX_BITRATES) && rates[i];
++ i++) {
++ range->bitrate[i] = (rates[i] & 0x7f) * 500000;
++ }
++ range->num_bitrates = i;
++ PRINTM(INFO, "IW_MAX_BITRATES=%d num_bitrates=%d\n", IW_MAX_BITRATES,
++ range->num_bitrates);
++
++ range->num_frequency = 0;
++ if (wlan_get_state_11d(priv) == ENABLE_11D &&
++ Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ u8 chan_no;
++ u8 band;
++
++ parsed_region_chan_11d_t *parsed_region_chan =
++ &Adapter->parsed_region_chan;
++
++ band = parsed_region_chan->band;
++ PRINTM(INFO, "band=%d NoOfChan=%d\n", band,
++ parsed_region_chan->NoOfChan);
++
++ for (i = 0; (range->num_frequency < IW_MAX_FREQUENCIES)
++ && (i < parsed_region_chan->NoOfChan); i++) {
++ chan_no = parsed_region_chan->chanPwr[i].chan;
++ PRINTM(INFO, "chan_no=%d\n", chan_no);
++ range->freq[range->num_frequency].i = (long) chan_no;
++ range->freq[range->num_frequency].m =
++ (long) chan_2_freq(chan_no, band) * 100000;
++ range->freq[range->num_frequency].e = 1;
++ range->num_frequency++;
++ }
++ } else {
++ for (j = 0; (range->num_frequency < IW_MAX_FREQUENCIES)
++ && (j < sizeof(Adapter->region_channel)
++ / sizeof(Adapter->region_channel[0])); j++) {
++ cfp = Adapter->region_channel[j].CFP;
++ for (i = 0; (range->num_frequency < IW_MAX_FREQUENCIES)
++ && Adapter->region_channel[j].Valid
++ && cfp && (i < Adapter->region_channel[j].NrCFP); i++) {
++ range->freq[range->num_frequency].i = (long) cfp->Channel;
++ range->freq[range->num_frequency].m =
++ (long) cfp->Freq * 100000;
++ range->freq[range->num_frequency].e = 1;
++ cfp++;
++ range->num_frequency++;
++ }
++ }
++ }
++
++ PRINTM(INFO, "IW_MAX_FREQUENCIES=%d num_frequency=%d\n",
++ IW_MAX_FREQUENCIES, range->num_frequency);
++
++ range->num_channels = range->num_frequency;
++
++ sort_channels(&range->freq[0], range->num_frequency);
++
++ /*
++ * Set an indication of the max TCP throughput in bit/s that we can
++ * expect using this interface
++ */
++ if (i > 2)
++ range->throughput = 5000 * 1000;
++ else
++ range->throughput = 1500 * 1000;
++
++ range->min_rts = MRVDRV_RTS_MIN_VALUE;
++ range->max_rts = MRVDRV_RTS_MAX_VALUE;
++ range->min_frag = MRVDRV_FRAG_MIN_VALUE;
++ range->max_frag = MRVDRV_FRAG_MAX_VALUE;
++
++ range->encoding_size[0] = 5;
++ range->encoding_size[1] = 13;
++ range->num_encoding_sizes = 2;
++ range->max_encoding_tokens = 4;
++
++#define IW_POWER_PERIOD_MIN 1000000 /* 1 sec */
++#define IW_POWER_PERIOD_MAX 120000000 /* 2 min */
++#define IW_POWER_TIMEOUT_MIN 1000 /* 1 ms */
++#define IW_POWER_TIMEOUT_MAX 1000000 /* 1 sec */
++
++ /* Power Management duration & timeout */
++ range->min_pmp = IW_POWER_PERIOD_MIN;
++ range->max_pmp = IW_POWER_PERIOD_MAX;
++ range->min_pmt = IW_POWER_TIMEOUT_MIN;
++ range->max_pmt = IW_POWER_TIMEOUT_MAX;
++ range->pmp_flags = IW_POWER_PERIOD;
++ range->pmt_flags = IW_POWER_TIMEOUT;
++ range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_ALL_R;
++
++ /*
++ * Minimum version we recommend
++ */
++ range->we_version_source = 15;
++
++ /*
++ * Version we are compiled with
++ */
++ range->we_version_compiled = WIRELESS_EXT;
++
++ range->retry_capa = IW_RETRY_LIMIT;
++ range->retry_flags = IW_RETRY_LIMIT | IW_RETRY_MAX;
++
++ range->min_retry = TX_RETRY_MIN;
++ range->max_retry = TX_RETRY_MAX;
++
++ /*
++ * Set the qual, level and noise range values
++ */
++ /*
++ * need to put the right values here
++ */
++#define IW_MAX_QUAL_PERCENT 100
++#define IW_AVG_QUAL_PERCENT 70
++ range->max_qual.qual = IW_MAX_QUAL_PERCENT;
++ range->max_qual.level = 0;
++ range->max_qual.noise = 0;
++
++ range->avg_qual.qual = IW_AVG_QUAL_PERCENT;
++ range->avg_qual.level = 0;
++ range->avg_qual.noise = 0;
++
++ range->sensitivity = 0;
++ /*
++ * Setup the supported power level ranges
++ */
++ memset(range->txpower, 0, sizeof(range->txpower));
++ range->txpower[0] = Adapter->MinTxPowerLevel;
++ range->txpower[1] = Adapter->MaxTxPowerLevel;
++ range->num_txpower = 2;
++ range->txpower_capa = IW_TXPOW_DBM | IW_TXPOW_RANGE;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set power management
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_set_power(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ /* PS is currently supported only in Infrastructure Mode
++ * Remove this check if it is to be supported in IBSS mode also
++ */
++
++ if (vwrq->disabled) {
++ Adapter->PSMode = Wlan802_11PowerModeCAM;
++ if (Adapter->PSState != PS_STATE_FULL_POWER) {
++ PSWakeup(priv, HostCmd_OPTION_WAITFORRSP);
++ }
++
++ return 0;
++ }
++
++ if ((vwrq->flags & IW_POWER_TYPE) == IW_POWER_TIMEOUT) {
++ PRINTM(INFO, "Setting power timeout command is not supported\n");
++ return -EINVAL;
++ } else if ((vwrq->flags & IW_POWER_TYPE) == IW_POWER_PERIOD) {
++ PRINTM(INFO, "Setting power period command is not supported\n");
++ return -EINVAL;
++ }
++
++ if (Adapter->PSMode != Wlan802_11PowerModeCAM) {
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ Adapter->PSMode = Wlan802_11PowerModeMAX_PSP;
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ PSSleep(priv, HostCmd_OPTION_WAITFORRSP);
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get power management
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_power(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int mode;
++
++ ENTER();
++
++ mode = Adapter->PSMode;
++
++ if ((vwrq->disabled = (mode == Wlan802_11PowerModeCAM))
++ || Adapter->MediaConnectStatus == WlanMediaStateDisconnected) {
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ vwrq->value = 0;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set sensitivity threshold
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_sens(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ ENTER();
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get sensitivity threshold
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_FAILURE
++ */
++static int
++wlan_get_sens(struct net_device *dev,
++ struct iw_request_info *info, struct iw_param *vwrq,
++ char *extra)
++{
++ ENTER();
++ LEAVE();
++ return WLAN_STATUS_FAILURE;
++}
++
++/**
++ * @brief Append/Reset IE buffer.
++ *
++ * Pass an opaque block of data, expected to be IEEE IEs, to the driver
++ * for eventual passthrough to the firmware in an associate/join
++ * (and potentially start) command. This function is the main body
++ * for both wlan_set_gen_ie_ioctl and wlan_set_gen_ie
++ *
++ * Data is appended to an existing buffer and then wrapped in a passthrough
++ * TLV in the command API to the firmware. The firmware treats the data
++ * as a transparent passthrough to the transmitted management frame.
++ *
++ * @param Adapter A pointer to wlan_private structure
++ * @param ie_data_ptr A pointer to iwreq structure
++ * @param ie_len Length of the IE or IE block passed in ie_data_ptr
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_gen_ie_helper(wlan_private * priv, u8 * ie_data_ptr, u16 ie_len)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++ IEEEtypes_VendorHeader_t *pVendorIe;
++ const u8 wpa_oui[] = { 0x00, 0x50, 0xf2, 0x01 };
++ const u8 wps_oui[] = { 0x00, 0x50, 0xf2, 0x04 };
++ /* If the passed length is zero, reset the buffer */
++ if (ie_len == 0) {
++ Adapter->genIeBufferLen = 0;
++
++ } else if (ie_data_ptr == NULL) {
++ /* NULL check */
++ ret = -EINVAL;
++ } else {
++
++ pVendorIe = (IEEEtypes_VendorHeader_t *) ie_data_ptr;
++
++ /* Test to see if it is a WPA IE, if not, then it is a gen IE */
++ if ((pVendorIe->ElementId == RSN_IE)
++ || ((pVendorIe->ElementId == WPA_IE)
++ && (pVendorIe->OuiType == wpa_oui[3])
++ && (memcmp(pVendorIe->Oui, wpa_oui, sizeof(pVendorIe->Oui)) ==
++ 0))) {
++
++ /* IE is a WPA/WPA2 IE so call set_wpa function */
++ ret = wlan_set_wpa_ie_helper(priv, ie_data_ptr, ie_len);
++ } else if ((pVendorIe->ElementId == WPS_IE)
++ && (memcmp(pVendorIe->Oui, wps_oui, sizeof(pVendorIe->Oui))
++ == 0)
++ && (pVendorIe->OuiType == wps_oui[3])) {
++ /*
++ * Discard first two byte (Element ID and Length)
++ * because they are not needed in the case of setting WPS_IE
++ */
++ if (pVendorIe->Len > 4) {
++ memcpy((u8 *) & Adapter->wps.wpsIe, ie_data_ptr, ie_len);
++ HEXDUMP("wpsIe",
++ (u8 *) & Adapter->wps.wpsIe,
++ Adapter->wps.wpsIe.VendHdr.Len + 2);
++
++ } else {
++ /* Only wps oui exist, reset driver wps buffer */
++ memset((u8 *) & Adapter->wps.wpsIe,
++ 0x00, sizeof(Adapter->wps.wpsIe));
++ PRINTM(INFO, "wpsIe cleared\n");
++ }
++ } else {
++ /*
++ * Verify that the passed length is not larger than the available
++ * space remaining in the buffer
++ */
++ if (ie_len < (sizeof(Adapter->genIeBuffer)
++ - Adapter->genIeBufferLen)) {
++
++ /* Append the passed data to the end of the genIeBuffer */
++ if (copy_from_user((Adapter->genIeBuffer
++ + Adapter->genIeBufferLen),
++ ie_data_ptr, ie_len)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ ret = -EFAULT;
++
++ } else {
++ /* Increment the stored buffer length by the size passed */
++ Adapter->genIeBufferLen += ie_len;
++ }
++
++ } else {
++ /* Passed data does not fit in the remaining buffer space */
++ ret = WLAN_STATUS_FAILURE;
++ }
++ }
++ }
++
++ /* Return WLAN_STATUS_SUCCESS, or < 0 for error case */
++ return ret;
++}
++
++/**
++ * @brief Get IE buffer from driver
++ *
++ * Used to pass an opaque block of data, expected to be IEEE IEs,
++ * back to the application. Currently the data block passed
++ * back to the application is the saved association response retrieved
++ * from the firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param ie_data_ptr A pointer to the IE or IE block
++ * @param ie_len_ptr In/Out parameter pointer for the buffer length passed
++ * in ie_data_ptr and the resulting data length copied
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_gen_ie_helper(wlan_private * priv,
++ u8 * ie_data_ptr, u16 * ie_len_ptr)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ IEEEtypes_AssocRsp_t *pAssocRsp;
++ int copySize;
++
++ pAssocRsp = (IEEEtypes_AssocRsp_t *) Adapter->assocRspBuffer;
++
++ /*
++ * Set the amount to copy back to the application as the minimum of the
++ * available IE data or the buffer provided by the application
++ */
++ copySize = (Adapter->assocRspSize - sizeof(pAssocRsp->Capability) -
++ -sizeof(pAssocRsp->StatusCode) - sizeof(pAssocRsp->AId));
++ copySize = MIN(copySize, *ie_len_ptr);
++
++ /* Copy the IEEE TLVs in the assoc response back to the application */
++ if (copy_to_user(ie_data_ptr, (u8 *) pAssocRsp->IEBuffer, copySize)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ /* Returned copy length */
++ *ie_len_ptr = copySize;
++
++ /* No error on return */
++ return WLAN_STATUS_SUCCESS;
++}
++
++#if (WIRELESS_EXT >= 18)
++/**
++ * @brief Set IE
++ *
++ * Calls main function set_gen_ie_fuct that adds the inputted IE
++ * to the genie buffer
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param dwrq A pointer to iw_point structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_gen_ie(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ return wlan_set_gen_ie_helper(dev->priv, dwrq->pointer, dwrq->length);
++}
++
++/**
++ * @brief Get IE
++ *
++ * Calls main function get_gen_ie_fuct that retrieves expected IEEE IEs
++ * and places then in the iw_point structure
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param dwrq A pointer to iw_point structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_gen_ie(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ return wlan_get_gen_ie_helper(dev->priv, dwrq->pointer, &dwrq->length);
++}
++
++/**
++ * @brief Set authentication mode
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_setauthalg(wlan_private * priv, int alg)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ PRINTM(INFO, "auth alg is %#x\n", alg);
++
++ switch (alg) {
++ case IW_AUTH_ALG_SHARED_KEY:
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeShared;
++ break;
++ case IW_AUTH_ALG_LEAP:
++ //clear WPA IE
++ wlan_set_wpa_ie_helper(priv, NULL, 0);
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeNetworkEAP;
++ break;
++ case IW_AUTH_ALG_OPEN_SYSTEM:
++ default:
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeOpen;
++ break;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief set authentication mode params
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_auth(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++ switch (vwrq->flags & IW_AUTH_INDEX) {
++ case IW_AUTH_CIPHER_PAIRWISE:
++ case IW_AUTH_CIPHER_GROUP:
++ if (vwrq->value & IW_AUTH_CIPHER_NONE)
++ priv->adapter->SecInfo.EncryptionMode = CIPHER_NONE;
++ else if (vwrq->value & IW_AUTH_CIPHER_WEP40)
++ priv->adapter->SecInfo.EncryptionMode = CIPHER_WEP40;
++ else if (vwrq->value & IW_AUTH_CIPHER_TKIP)
++ priv->adapter->SecInfo.EncryptionMode = CIPHER_TKIP;
++ else if (vwrq->value & IW_AUTH_CIPHER_CCMP)
++ priv->adapter->SecInfo.EncryptionMode = CIPHER_CCMP;
++ else if (vwrq->value & IW_AUTH_CIPHER_WEP104)
++ priv->adapter->SecInfo.EncryptionMode = CIPHER_WEP104;
++ break;
++ case IW_AUTH_80211_AUTH_ALG:
++ wlan_setauthalg(priv, vwrq->value);
++ break;
++ case IW_AUTH_WPA_ENABLED:
++ if (vwrq->value == FALSE)
++ wlan_set_wpa_ie_helper(priv, NULL, 0);
++ break;
++ case IW_AUTH_WPA_VERSION:
++ case IW_AUTH_KEY_MGMT:
++ case IW_AUTH_TKIP_COUNTERMEASURES:
++ case IW_AUTH_DROP_UNENCRYPTED:
++ case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++ case IW_AUTH_ROAMING_CONTROL:
++ case IW_AUTH_PRIVACY_INVOKED:
++ default:
++ break;
++ }
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief get authentication mode params
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_auth(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ ENTER();
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++ switch (vwrq->flags & IW_AUTH_INDEX) {
++ case IW_AUTH_CIPHER_PAIRWISE:
++ case IW_AUTH_CIPHER_GROUP:
++ if (priv->adapter->SecInfo.EncryptionMode == CIPHER_NONE)
++ vwrq->value = IW_AUTH_CIPHER_NONE;
++ else if (priv->adapter->SecInfo.EncryptionMode == CIPHER_WEP40)
++ vwrq->value = IW_AUTH_CIPHER_WEP40;
++ else if (priv->adapter->SecInfo.EncryptionMode == CIPHER_TKIP)
++ vwrq->value = IW_AUTH_CIPHER_TKIP;
++ else if (priv->adapter->SecInfo.EncryptionMode == CIPHER_CCMP)
++ vwrq->value = IW_AUTH_CIPHER_CCMP;
++ else if (priv->adapter->SecInfo.EncryptionMode == CIPHER_WEP104)
++ vwrq->value = IW_AUTH_CIPHER_WEP104;
++ break;
++ case IW_AUTH_80211_AUTH_ALG:
++ if (Adapter->SecInfo.AuthenticationMode == Wlan802_11AuthModeShared)
++ vwrq->value = IW_AUTH_ALG_SHARED_KEY;
++ else if (Adapter->SecInfo.AuthenticationMode ==
++ Wlan802_11AuthModeNetworkEAP)
++ vwrq->value = IW_AUTH_ALG_LEAP;
++ else
++ vwrq->value = IW_AUTH_ALG_OPEN_SYSTEM;
++ break;
++ case IW_AUTH_WPA_ENABLED:
++ if (Adapter->Wpa_ie_len > 0)
++ vwrq->value = TRUE;
++ else
++ vwrq->value = FALSE;
++ break;
++ case IW_AUTH_WPA_VERSION:
++ case IW_AUTH_KEY_MGMT:
++ case IW_AUTH_TKIP_COUNTERMEASURES:
++ case IW_AUTH_DROP_UNENCRYPTED:
++ case IW_AUTH_RX_UNENCRYPTED_EAPOL:
++ case IW_AUTH_ROAMING_CONTROL:
++ case IW_AUTH_PRIVACY_INVOKED:
++ default:
++ ret = -EOPNOTSUPP;
++ break;
++ }
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Request MLME operation
++ *
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param dwrq A pointer to iw_point structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_mlme(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ struct iw_mlme *mlme = (struct iw_mlme *) extra;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++ if ((mlme->cmd == IW_MLME_DEAUTH) || (mlme->cmd == IW_MLME_DISASSOC)) {
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure &&
++ Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ SendDeauthentication(priv);
++ } else if (Adapter->InfrastructureMode == Wlan802_11IBSS &&
++ Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ StopAdhocNetwork(priv);
++ }
++ }
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Extended version of encoding configuration
++ *
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param dwrq A pointer to iw_point structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_encode_ext(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ struct iw_encode_ext *ext = (struct iw_encode_ext *) extra;
++ wlan_private *priv = dev->priv;
++ WLAN_802_11_KEY *pkey;
++ int keyindex;
++ u8 *pKeyMaterial = NULL;
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++ keyindex = dwrq->flags & IW_ENCODE_INDEX;
++ if (keyindex > 4)
++ return -EINVAL;
++ if (ext->key_len > (dwrq->length - sizeof(struct iw_encode_ext)))
++ return -EINVAL;
++ pKeyMaterial = (u8 *) (ext + 1);
++ //Disable Key
++ if ((dwrq->flags & IW_ENCODE_DISABLED) && (ext->key_len == 0)) {
++ dwrq->length = 0;
++ wlan_set_encode_nonwpa(dev, info, dwrq, extra);
++ return WLAN_STATUS_SUCCESS;
++ }
++ //Set WEP key
++ if (ext->key_len <= MAX_WEP_KEY_SIZE) {
++ dwrq->length = ext->key_len;
++ wlan_set_encode_nonwpa(dev, info, dwrq, pKeyMaterial);
++ if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
++ dwrq->length = 0;
++ wlan_set_encode_nonwpa(dev, info, dwrq, extra);
++ }
++ } else {
++ pkey = kmalloc(sizeof(WLAN_802_11_KEY) + ext->key_len, GFP_KERNEL);
++ if (!pkey) {
++ PRINTM(INFO, "allocate key buffer failed!\n");
++ return -ENOMEM;
++ }
++ memset(pkey, 0, sizeof(WLAN_802_11_KEY) + ext->key_len);
++ memcpy((u8 *) pkey->BSSID, (u8 *) ext->addr.sa_data, ETH_ALEN);
++ pkey->KeyLength = ext->key_len;
++ memcpy(pkey->KeyMaterial, pKeyMaterial, ext->key_len);
++ pkey->KeyIndex = keyindex - 1;
++ if (pkey->KeyIndex == 0)
++ pkey->KeyIndex = 0x40000000;
++ if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID)
++ memcpy((u8 *) & pkey->KeyRSC, ext->rx_seq,
++ IW_ENCODE_SEQ_MAX_SIZE);
++ pkey->Length = sizeof(WLAN_802_11_KEY) + ext->key_len;
++ wlan_set_encode_wpa(dev, info, dwrq, (u8 *) pkey);
++ kfree(pkey);
++ }
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Extended version of encoding configuration
++ *
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param dwrq A pointer to iw_point structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_encode_ext(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ return -EOPNOTSUPP;
++}
++#endif /* #if (WIRELESS_EXT >= 18) */
++
++/**
++ * @brief Append/Reset IE buffer.
++ *
++ * Pass an opaque block of data, expected to be IEEE IEs, to the driver
++ * for eventual passthrough to the firmware in an associate/join
++ * (and potentially start) command.
++ *
++ * Data is appended to an existing buffer and then wrapped in a passthrough
++ * TLV in the command API to the firmware. The firmware treats the data
++ * as a transparent passthrough to the transmitted management frame.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_gen_ie_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ return wlan_set_gen_ie_helper(priv,
++ wrq->u.data.pointer, wrq->u.data.length);
++}
++
++/**
++ * @brief Get IE buffer from driver
++ *
++ * Used to pass an opaque block of data, expected to be IEEE IEs,
++ * back to the application. Currently the data block passed
++ * back to the application is the saved association response retrieved
++ * from the firmware.
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_gen_ie_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ return wlan_get_gen_ie_helper(priv,
++ wrq->u.data.pointer, &wrq->u.data.length);
++}
++
++/*
++ * iwconfig settable callbacks
++ */
++static const iw_handler wlan_handler[] = {
++ (iw_handler) wlan_config_commit, /* SIOCSIWCOMMIT */
++ (iw_handler) wlan_get_name, /* SIOCGIWNAME */
++ (iw_handler) NULL, /* SIOCSIWNWID */
++ (iw_handler) NULL, /* SIOCGIWNWID */
++ (iw_handler) wlan_set_freq, /* SIOCSIWFREQ */
++ (iw_handler) wlan_get_freq, /* SIOCGIWFREQ */
++ (iw_handler) wlan_set_mode, /* SIOCSIWMODE */
++ (iw_handler) wlan_get_mode, /* SIOCGIWMODE */
++ (iw_handler) wlan_set_sens, /* SIOCSIWSENS */
++ (iw_handler) wlan_get_sens, /* SIOCGIWSENS */
++ (iw_handler) NULL, /* SIOCSIWRANGE */
++ (iw_handler) wlan_get_range, /* SIOCGIWRANGE */
++ (iw_handler) NULL, /* SIOCSIWPRIV */
++ (iw_handler) NULL, /* SIOCGIWPRIV */
++ (iw_handler) NULL, /* SIOCSIWSTATS */
++ (iw_handler) NULL, /* SIOCGIWSTATS */
++#if WIRELESS_EXT > 15
++ iw_handler_set_spy, /* SIOCSIWSPY */
++ iw_handler_get_spy, /* SIOCGIWSPY */
++ iw_handler_set_thrspy, /* SIOCSIWTHRSPY */
++ iw_handler_get_thrspy, /* SIOCGIWTHRSPY */
++#else /* WIRELESS_EXT > 15 */
++#ifdef WIRELESS_SPY
++ (iw_handler) wlan_set_spy, /* SIOCSIWSPY */
++ (iw_handler) wlan_get_spy, /* SIOCGIWSPY */
++#else /* WIRELESS_SPY */
++ (iw_handler) NULL, /* SIOCSIWSPY */
++ (iw_handler) NULL, /* SIOCGIWSPY */
++#endif /* WIRELESS_SPY */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) NULL, /* -- hole -- */
++#endif /* WIRELESS_EXT > 15 */
++ (iw_handler) wlan_set_wap, /* SIOCSIWAP */
++ (iw_handler) wlan_get_wap, /* SIOCGIWAP */
++#if WIRELESS_EXT >= 18
++ (iw_handler) wlan_set_mlme, /* SIOCSIWMLME */
++#else
++ (iw_handler) NULL, /* -- hole -- */
++#endif
++ //(iw_handler) wlan_get_aplist, /* SIOCGIWAPLIST */
++ NULL, /* SIOCGIWAPLIST */
++#if WIRELESS_EXT > 13
++ (iw_handler) wlan_set_scan, /* SIOCSIWSCAN */
++ (iw_handler) wlan_get_scan, /* SIOCGIWSCAN */
++#else /* WIRELESS_EXT > 13 */
++ (iw_handler) NULL, /* SIOCSIWSCAN */
++ (iw_handler) NULL, /* SIOCGIWSCAN */
++#endif /* WIRELESS_EXT > 13 */
++ (iw_handler) wlan_set_essid, /* SIOCSIWESSID */
++ (iw_handler) wlan_get_essid, /* SIOCGIWESSID */
++ (iw_handler) wlan_set_nick, /* SIOCSIWNICKN */
++ (iw_handler) wlan_get_nick, /* SIOCGIWNICKN */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) wlan_set_rate, /* SIOCSIWRATE */
++ (iw_handler) wlan_get_rate, /* SIOCGIWRATE */
++ (iw_handler) wlan_set_rts, /* SIOCSIWRTS */
++ (iw_handler) wlan_get_rts, /* SIOCGIWRTS */
++ (iw_handler) wlan_set_frag, /* SIOCSIWFRAG */
++ (iw_handler) wlan_get_frag, /* SIOCGIWFRAG */
++ (iw_handler) wlan_set_txpow, /* SIOCSIWTXPOW */
++ (iw_handler) wlan_get_txpow, /* SIOCGIWTXPOW */
++ (iw_handler) wlan_set_retry, /* SIOCSIWRETRY */
++ (iw_handler) wlan_get_retry, /* SIOCGIWRETRY */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) wlan_get_encode, /* SIOCGIWENCODE */
++ (iw_handler) wlan_set_power, /* SIOCSIWPOWER */
++ (iw_handler) wlan_get_power, /* SIOCGIWPOWER */
++#if (WIRELESS_EXT >= 18)
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) NULL, /* -- hole -- */
++ (iw_handler) wlan_set_gen_ie, /* SIOCSIWGENIE */
++ (iw_handler) wlan_get_gen_ie, /* SIOCGIWGENIE */
++ (iw_handler) wlan_set_auth, /* SIOCSIWAUTH */
++ (iw_handler) wlan_get_auth, /* SIOCGIWAUTH */
++ (iw_handler) wlan_set_encode_ext, /* SIOCSIWENCODEEXT */
++ (iw_handler) wlan_get_encode_ext, /* SIOCGIWENCODEEXT */
++#endif /* WIRELESSS_EXT >= 18 */
++};
++
++/*
++ * iwpriv settable callbacks
++ */
++
++static const iw_handler wlan_private_handler[] = {
++ NULL, /* SIOCIWFIRSTPRIV */
++};
++
++static const struct iw_priv_args wlan_private_args[] = {
++ /*
++ * { cmd, set_args, get_args, name }
++ */
++ {
++ WLANEXTSCAN,
++ IW_PRIV_TYPE_INT,
++ IW_PRIV_TYPE_CHAR | 2,
++ "extscan"},
++ {
++ WLANHOSTCMD,
++ IW_PRIV_TYPE_BYTE | 2047,
++ IW_PRIV_TYPE_BYTE | 2047,
++ "hostcmd"},
++ {
++ WLANARPFILTER,
++ IW_PRIV_TYPE_BYTE | 2047,
++ IW_PRIV_TYPE_BYTE | 2047,
++ "arpfilter"},
++ {
++ WLANREGRDWR,
++ IW_PRIV_TYPE_CHAR | 256,
++ IW_PRIV_TYPE_CHAR | 256,
++ "regrdwr"},
++ {
++ WLANCMD52RDWR,
++ IW_PRIV_TYPE_BYTE | 7,
++ IW_PRIV_TYPE_BYTE | 7,
++ "sdcmd52rw"},
++ {
++ WLANCMD53RDWR,
++ IW_PRIV_TYPE_CHAR | 32,
++ IW_PRIV_TYPE_CHAR | 32,
++ "sdcmd53rw"},
++ {
++ WLAN_SETCONF_GETCONF,
++ IW_PRIV_TYPE_BYTE | MAX_SETGET_CONF_SIZE,
++ IW_PRIV_TYPE_BYTE | MAX_SETGET_CONF_SIZE,
++ "setgetconf"},
++ {
++ WLANCISDUMP,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_BYTE | 512,
++ "getcis"},
++ {
++ WLANSCAN_TYPE,
++ IW_PRIV_TYPE_CHAR | 8,
++ IW_PRIV_TYPE_CHAR | 8,
++ "scantype"},
++ {
++ WLAN_SETINT_GETINT,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ ""},
++ {
++ WLANNF,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getNF"},
++ {
++ WLANRSSI,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getRSSI"},
++ {
++ WLANBGSCAN,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "bgscan"},
++ {
++ WLANENABLE11D,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "enable11d"},
++ {
++ WLANADHOCGRATE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "adhocgrate"},
++ {
++ WLANSDIOCLOCK,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "sdioclock"},
++ {
++ WLANWMM_ENABLE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "wmm"},
++ {
++ WLANNULLGEN,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "uapsdnullgen"},
++ {
++ WLANADHOCCSET,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "setcoalescing"},
++ {
++ WLAN_ADHOC_G_PROT,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "adhocgprot"},
++
++ {
++ WLAN_SETONEINT_GETONEINT,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ ""},
++ {
++ WLAN_WMM_QOSINFO,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "wmm_qosinfo"},
++ {
++ WLAN_LISTENINTRVL,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "lolisteninter"},
++ {
++ WLAN_FW_WAKEUP_METHOD,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "fwwakeupmethod"},
++ {
++ WLAN_NULLPKTINTERVAL,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "psnullinterval"},
++ {
++ WLAN_BCN_MISS_TIMEOUT,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "bcnmisto"},
++ {
++ WLAN_ADHOC_AWAKE_PERIOD,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "adhocawakepd"},
++ {
++ WLAN_LDO,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "ldocfg"},
++ {
++ WLAN_SDIO_MODE,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "sdiomode"},
++ {
++ WLAN_RTS_CTS_CTRL,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "rtsctsctrl"},
++ {
++ WLAN_AUTODEEPSLEEP,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "autodeepsleep"},
++ {
++ WLAN_WAKEUP_MT,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_INT | 1,
++ "wakeupmt"},
++ /* Using iwpriv sub-command feature */
++ {
++ WLAN_SETONEINT_GETNONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ ""},
++ {
++ WLAN_SUBCMD_SETRXANTENNA,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "setrxant"},
++ {
++ WLAN_SUBCMD_SETTXANTENNA,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "settxant"},
++ {
++ WLANSETAUTHALG,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "authalgs",
++ },
++ {
++ WLANSETENCRYPTIONMODE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "encryptionmode",
++ },
++ {
++ WLANSETREGION,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "setregioncode"},
++ {
++ WLAN_SET_LISTEN_INTERVAL,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "setlisteninter"},
++ {
++ WLAN_SET_MULTIPLE_DTIM,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "setmultipledtim"},
++ {
++ WLANSETBCNAVG,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "setbcnavg"},
++ {
++ WLANSETDATAAVG,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "setdataavg"},
++ {
++ WLANASSOCIATE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ IW_PRIV_TYPE_NONE,
++ "associate"},
++ {
++ WLAN_SETNONE_GETONEINT,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ ""},
++ {
++ WLANGETREGION,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getregioncode"},
++ {
++ WLAN_GET_LISTEN_INTERVAL,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getlisteninter"},
++ {
++ WLAN_GET_MULTIPLE_DTIM,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getmultipledtim"},
++ {
++ WLAN_GET_TX_RATE,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "gettxrate"},
++ {
++ WLANGETBCNAVG,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getbcnavg"},
++ {
++ WLANGETDATAAVG,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getdataavg"},
++ {
++ WLANGETDTIM,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
++ "getdtim"},
++ {
++ WLAN_SETNONE_GETTWELVE_CHAR,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_CHAR | 12,
++ ""},
++ {
++ WLAN_SUBCMD_GETRXANTENNA,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_CHAR | 12,
++ "getrxant"},
++ {
++ WLAN_SUBCMD_GETTXANTENNA,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_CHAR | 12,
++ "gettxant"},
++ {
++ WLAN_GET_TSF,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_CHAR | 12,
++ "gettsf"},
++ {
++ WLAN_WPS_SESSION,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_CHAR | 12,
++ "wpssession"},
++ {
++ WLANDEEPSLEEP,
++ IW_PRIV_TYPE_CHAR | 1,
++ IW_PRIV_TYPE_CHAR | 6,
++ "deepsleep"},
++ {
++ WLANHOSTSLEEPCFG,
++ IW_PRIV_TYPE_CHAR | 31,
++ IW_PRIV_TYPE_NONE,
++ "hostsleepcfg"},
++ {
++ WLAN_SETNONE_GETNONE,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ ""},
++ {
++ WLANDEAUTH,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "deauth"},
++ {
++ WLANADHOCSTOP,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "adhocstop"},
++ {
++ WLANRADIOON,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "radioon"},
++ {
++ WLANRADIOOFF,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "radiooff"},
++ {
++ WLANREMOVEADHOCAES,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "rmaeskey"},
++#ifdef REASSOCIATION
++ {
++ WLANREASSOCIATIONAUTO,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "reasso-on"},
++ {
++ WLANREASSOCIATIONUSER,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "reasso-off"},
++#endif /* REASSOCIATION */
++ {
++ WLANWLANIDLEON,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "wlanidle-on"},
++ {
++ WLANWLANIDLEOFF,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_NONE,
++ "wlanidle-off"},
++ {
++ WLAN_SET64CHAR_GET64CHAR,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ ""},
++ {
++ WLANSLEEPPARAMS,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ "sleepparams"},
++
++ {
++ WLAN_BCA_TIMESHARE,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ "bca-ts"},
++ {
++ WLANSCAN_MODE,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ "scanmode"},
++ {
++ WLAN_GET_ADHOC_STATUS,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ "getadhocstatus"},
++ {
++ WLAN_SET_GEN_IE,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ "setgenie"},
++ {
++ WLAN_GET_GEN_IE,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ "getgenie"},
++ {
++ WLAN_WMM_QUEUE_STATUS,
++ IW_PRIV_TYPE_CHAR | 64,
++ IW_PRIV_TYPE_CHAR | 64,
++ "qstatus"},
++ {
++ WLAN_SETWORDCHAR_GETNONE,
++ IW_PRIV_TYPE_CHAR | 32,
++ IW_PRIV_TYPE_NONE,
++ ""},
++ {
++ WLANSETADHOCAES,
++ IW_PRIV_TYPE_CHAR | 32,
++ IW_PRIV_TYPE_NONE,
++ "setaeskey"},
++ {
++ WLAN_SETONEINT_GETWORDCHAR,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_CHAR | 128,
++ ""},
++ {
++ WLANGETADHOCAES,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_CHAR | 128,
++ "getaeskey"},
++ {
++ WLANVERSION,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_CHAR | 128,
++ "version"},
++ {
++ WLANVEREXT,
++ IW_PRIV_TYPE_INT | 1,
++ IW_PRIV_TYPE_CHAR | 128,
++ "verext"},
++ {
++ WLANSETWPAIE,
++ IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | 24,
++ IW_PRIV_TYPE_NONE,
++ "setwpaie"},
++ {
++ WLANGETLOG,
++ IW_PRIV_TYPE_NONE,
++ IW_PRIV_TYPE_CHAR | GETLOG_BUFSIZE,
++ "getlog"},
++ {
++ WLAN_SET_GET_SIXTEEN_INT,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ ""},
++ {
++ WLAN_TPCCFG,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "tpccfg"},
++ {
++ WLAN_SCANPROBES,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "scanprobes"},
++ {
++ WLAN_LED_GPIO_CTRL,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "ledgpio"},
++ {
++ WLAN_SLEEP_PERIOD,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "sleeppd"},
++ {
++ WLAN_ADAPT_RATESET,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "rateadapt"},
++
++ {
++ WLAN_INACTIVITY_TIMEOUT,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "inactivityto"},
++ {
++ WLANSNR,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "getSNR"},
++ {
++ WLAN_GET_RATE,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "getrate"},
++ {
++ WLAN_GET_RXINFO,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "getrxinfo"},
++ {
++ WLAN_SET_ATIM_WINDOW,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "atimwindow"},
++ {
++ WLAN_BEACON_INTERVAL,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "bcninterval"},
++ {
++ WLAN_SDIO_PULL_CTRL,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "sdiopullctrl"},
++ {
++ WLAN_SCAN_TIME,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "scantime"},
++ {
++ WLAN_DATA_SUBSCRIBE_EVENT,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "dataevtcfg"},
++ {
++ WLAN_TXCONTROL,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "txcontrol"},
++ {
++ WLANHSCFG,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "hscfg"},
++ {
++ WLANHSSETPARA,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "hssetpara"},
++#ifdef DEBUG_LEVEL1
++ {
++ WLAN_DRV_DBG,
++ IW_PRIV_TYPE_INT | 16,
++ IW_PRIV_TYPE_INT | 16,
++ "drvdbg"},
++#endif
++ {
++ WLAN_SET_GET_2K,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ ""},
++ {
++ WLAN_SET_USER_SCAN,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "setuserscan"},
++ {
++ WLAN_GET_SCAN_TABLE,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "getscantable"},
++ {
++ WLAN_SET_MRVL_TLV,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "setmrvltlv"},
++ {
++ WLAN_GET_ASSOC_RSP,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "getassocrsp"},
++ {
++ WLAN_ADDTS_REQ,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "addts"},
++ {
++ WLAN_DELTS_REQ,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "delts"},
++ {
++ WLAN_QUEUE_CONFIG,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "qconfig"},
++ {
++ WLAN_QUEUE_STATS,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "qstats"},
++ {
++ WLAN_TX_PKT_STATS,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "txpktstats"},
++ {
++ WLAN_GET_CFP_TABLE,
++ IW_PRIV_TYPE_BYTE | 2000,
++ IW_PRIV_TYPE_BYTE | 2000,
++ "getcfptable"},
++};
++
++struct iw_handler_def wlan_handler_def = {
++ num_standard:sizeof(wlan_handler) / sizeof(iw_handler),
++ num_private:sizeof(wlan_private_handler) / sizeof(iw_handler),
++ num_private_args:sizeof(wlan_private_args) /
++ sizeof(struct iw_priv_args),
++ standard:(iw_handler *) wlan_handler,
++ private:(iw_handler *) wlan_private_handler,
++ private_args:(struct iw_priv_args *) wlan_private_args,
++};
++
++/**
++ * @brief get the channel frequency power info with specific channel
++ *
++ * @param band it can be BAND_A, BAND_G or BAND_B
++ * @param channel the channel for looking
++ * @param region_channel A pointer to REGION_CHANNEL structure
++ * @return A pointer to CHANNEL_FREQ_POWER structure or NULL if not find.
++ */
++
++CHANNEL_FREQ_POWER *
++get_cfp_by_band_and_channel(u8 band, u16 channel,
++ REGION_CHANNEL * region_channnel)
++{
++ REGION_CHANNEL *rc;
++ CHANNEL_FREQ_POWER *cfp = NULL;
++ int i, j;
++
++ for (j = 0; !cfp && (j < MAX_REGION_CHANNEL_NUM); j++) {
++ rc = &region_channnel[j];
++
++ if (!rc->Valid || !rc->CFP)
++ continue;
++ if (rc->Band != band)
++ continue;
++ if (channel == FIRST_VALID_CHANNEL)
++ cfp = &rc->CFP[0];
++ else {
++ for (i = 0; i < rc->NrCFP; i++) {
++ if (rc->CFP[i].Channel == channel) {
++ cfp = &rc->CFP[i];
++ break;
++ }
++ }
++ }
++ }
++
++ if (!cfp && channel)
++ PRINTM(INFO, "get_cfp_by_band_and_channel(): cannot find "
++ "cfp by band %d & channel %d\n", band, channel);
++
++ LEAVE();
++ return cfp;
++}
++
++/**
++ * @brief wlan hostcmd ioctl handler
++ *
++ * @param dev A pointer to net_device structure
++ * @param req A pointer to ifreq structure
++ * @param cmd command
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_hostcmd_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
++{
++ u8 *tempResponseBuffer;
++ CmdCtrlNode *pCmdNode;
++ HostCmd_DS_GEN *pCmdPtr;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ u16 wait_option = 0;
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ ENTER();
++
++ if ((wrq->u.data.pointer == NULL) || (wrq->u.data.length < S_DS_GEN)) {
++ PRINTM(INFO,
++ "wlan_hostcmd_ioctl() corrupt data: pointer=%p, length=%d\n",
++ wrq->u.data.pointer, wrq->u.data.length);
++ return -EFAULT;
++ }
++
++ /*
++ * Get a free command control node
++ */
++ if (!(pCmdNode = GetFreeCmdCtrlNode(priv))) {
++ PRINTM(INFO, "Failed GetFreeCmdCtrlNode\n");
++ return -ENOMEM;
++ }
++
++ if (!
++ (tempResponseBuffer =
++ kmalloc(MRVDRV_SIZE_OF_CMD_BUFFER, GFP_KERNEL))) {
++ PRINTM(INFO, "ERROR: Failed to allocate response buffer!\n");
++ CleanupAndInsertCmd(priv, pCmdNode);
++ return -ENOMEM;
++ }
++
++ wait_option |= HostCmd_OPTION_WAITFORRSP;
++
++ SetCmdCtrlNode(priv, pCmdNode, 0, wait_option, NULL);
++ init_waitqueue_head(&pCmdNode->cmdwait_q);
++
++ pCmdPtr = (HostCmd_DS_GEN *) pCmdNode->BufVirtualAddr;
++
++ /*
++ * Copy the whole command into the command buffer
++ */
++ if (copy_from_user(pCmdPtr, wrq->u.data.pointer, wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ kfree(tempResponseBuffer);
++ CleanupAndInsertCmd(priv, pCmdNode);
++ return -EFAULT;
++ }
++
++ if (pCmdPtr->Size < S_DS_GEN) {
++ PRINTM(INFO, "wlan_hostcmd_ioctl() invalid cmd size: Size=%d\n",
++ pCmdPtr->Size);
++ kfree(tempResponseBuffer);
++ CleanupAndInsertCmd(priv, pCmdNode);
++ return -EFAULT;
++ }
++
++ pCmdNode->pdata_buf = tempResponseBuffer;
++ pCmdNode->CmdFlags |= CMD_F_HOSTCMD;
++
++ pCmdPtr->Result = 0;
++
++ PRINTM(INFO, "HOSTCMD Command: 0x%04x Size: %d\n",
++ pCmdPtr->Command, pCmdPtr->Size);
++ HEXDUMP("Command Data", (u8 *) (pCmdPtr), MIN(32, pCmdPtr->Size));
++ PRINTM(INFO, "Copying data from : (user)0x%p -> 0x%p(driver)\n",
++ req->ifr_data, pCmdPtr);
++
++ pCmdNode->CmdWaitQWoken = FALSE;
++ pCmdPtr->Command = wlan_cpu_to_le16(pCmdPtr->Command);
++ pCmdPtr->Size = wlan_cpu_to_le16(pCmdPtr->Size);
++ QueueCmd(Adapter, pCmdNode, TRUE);
++ wake_up_interruptible(&priv->MainThread.waitQ);
++
++ if (wait_option & HostCmd_OPTION_WAITFORRSP) {
++ /* Sleep until response is generated by FW */
++ wait_event_interruptible(pCmdNode->cmdwait_q,
++ pCmdNode->CmdWaitQWoken);
++ }
++
++ /* Copy the response back to user space */
++ pCmdPtr = (HostCmd_DS_GEN *) tempResponseBuffer;
++
++ if (copy_to_user(wrq->u.data.pointer, tempResponseBuffer, pCmdPtr->Size))
++ PRINTM(INFO, "ERROR: copy_to_user failed!\n");
++ wrq->u.data.length = pCmdPtr->Size;
++ kfree(tempResponseBuffer);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief wlan arpfilter ioctl handler
++ *
++ * @param dev A pointer to net_device structure
++ * @param req A pointer to ifreq structure
++ * @param cmd command
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_arpfilter_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
++{
++ wlan_private *priv = dev->priv;
++ struct iwreq *wrq = (struct iwreq *) req;
++ wlan_adapter *Adapter = priv->adapter;
++ MrvlIEtypesHeader_t hdr;
++
++ ENTER();
++
++ if ((wrq->u.data.pointer == NULL)
++ || (wrq->u.data.length < sizeof(MrvlIEtypesHeader_t))
++ || (wrq->u.data.length > sizeof(Adapter->ArpFilter))) {
++ PRINTM(INFO,
++ "wlan_arpfilter_ioctl() corrupt data: pointer=%p, length=%d\n",
++ wrq->u.data.pointer, wrq->u.data.length);
++ return -EFAULT;
++ }
++
++ if (copy_from_user(&hdr, wrq->u.data.pointer, sizeof(hdr))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ if (hdr.Len == 0) {
++ Adapter->ArpFilterSize = 0;
++ memset(Adapter->ArpFilter, 0, sizeof(Adapter->ArpFilter));
++ } else {
++ Adapter->ArpFilterSize = wrq->u.data.length;
++
++ PRINTM(INFO, "Copying data from : (user)0x%p -> 0x%p(driver)\n",
++ wrq->u.data.pointer, Adapter->ArpFilter);
++ if (copy_from_user(Adapter->ArpFilter, wrq->u.data.pointer,
++ Adapter->ArpFilterSize)) {
++ Adapter->ArpFilterSize = 0;
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ HEXDUMP("ArpFilter", Adapter->ArpFilter, Adapter->ArpFilterSize);
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get Rx Info
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success
++ */
++static int
++wlan_get_rxinfo(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data[2];
++ ENTER();
++ data[0] = Adapter->SNR[TYPE_RXPD][TYPE_NOAVG];
++ data[1] = Adapter->RxPDRate;
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int) * 2)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 2;
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get SNR
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_snr(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++ int data[4];
++
++ ENTER();
++
++ memset(data, 0, sizeof(data));
++ if (wrq->u.data.length) {
++ if (copy_from_user
++ (data, wrq->u.data.pointer,
++ MIN(wrq->u.data.length, 4) * sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ }
++ if ((wrq->u.data.length == 0) || (data[0] == 0) || (data[0] == 1)) {
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RSSI,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ }
++ }
++
++ if (wrq->u.data.length == 0) {
++ data[0] = Adapter->SNR[TYPE_BEACON][TYPE_NOAVG];
++ data[1] = Adapter->SNR[TYPE_BEACON][TYPE_AVG];
++ if ((jiffies - Adapter->RxPDAge) > HZ) //data expired after 1 second
++ data[2] = 0;
++ else
++ data[2] = Adapter->SNR[TYPE_RXPD][TYPE_NOAVG];
++ data[3] = Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE;
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int) * 4)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 4;
++ } else if (data[0] == 0) {
++ data[0] = Adapter->SNR[TYPE_BEACON][TYPE_NOAVG];
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++ } else if (data[0] == 1) {
++ data[0] = Adapter->SNR[TYPE_BEACON][TYPE_AVG];
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++ } else if (data[0] == 2) {
++ if ((jiffies - Adapter->RxPDAge) > HZ) //data expired after 1 second
++ data[0] = 0;
++ else
++ data[0] = Adapter->SNR[TYPE_RXPD][TYPE_NOAVG];
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++ } else if (data[0] == 3) {
++ data[0] = Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE;
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++ } else {
++ return -ENOTSUPP;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set SDIO PULL CTRL
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_sdio_pull_ctrl(wlan_private * priv, struct iwreq *wrq)
++{
++ int data[2];
++ HostCmd_DS_SDIO_PULL_CTRL sdio_pull_ctrl;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++ memset(&sdio_pull_ctrl, 0, sizeof(sdio_pull_ctrl));
++ if (wrq->u.data.length > 0) {
++ if (copy_from_user(data, wrq->u.data.pointer, sizeof(data))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ PRINTM(INFO, "WLAN SET SDIO PULL CTRL: %d %d\n", data[0], data[1]);
++ sdio_pull_ctrl.Action = HostCmd_ACT_GEN_SET;
++ sdio_pull_ctrl.PullUp = data[0];
++ sdio_pull_ctrl.PullDown = data[1];
++ } else {
++ sdio_pull_ctrl.Action = HostCmd_ACT_GEN_GET;
++ }
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_SDIO_PULL_CTRL,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, (void *) &sdio_pull_ctrl);
++ data[0] = sdio_pull_ctrl.PullUp;
++ data[1] = sdio_pull_ctrl.PullDown;
++ wrq->u.data.length = 2;
++ if (copy_to_user
++ (wrq->u.data.pointer, data, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set scan time
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_scan_time(wlan_private * priv, struct iwreq *wrq)
++{
++ int data[3] = { 0, 0, 0 };
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wrq->u.data.length > 0 && wrq->u.data.length <= 3) {
++ if (copy_from_user
++ (data, wrq->u.data.pointer, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ PRINTM(INFO,
++ "WLAN SET Scan Time: Specific %d, Active %d, Passive %d\n",
++ data[0], data[1], data[2]);
++ if (data[0]) {
++ if (data[0] > MRVDRV_MAX_ACTIVE_SCAN_CHAN_TIME) {
++ PRINTM(MSG,
++ "Invalid parameter, max specific scan time is %d ms\n",
++ MRVDRV_MAX_ACTIVE_SCAN_CHAN_TIME);
++ return -EINVAL;
++ }
++ Adapter->SpecificScanTime = data[0];
++ }
++ if (data[1]) {
++ if (data[1] > MRVDRV_MAX_ACTIVE_SCAN_CHAN_TIME) {
++ PRINTM(MSG,
++ "Invalid parameter, max active scan time is %d ms\n",
++ MRVDRV_MAX_ACTIVE_SCAN_CHAN_TIME);
++ return -EINVAL;
++ }
++ Adapter->ActiveScanTime = data[1];
++ }
++ if (data[2]) {
++ if (data[2] > MRVDRV_MAX_PASSIVE_SCAN_CHAN_TIME) {
++ PRINTM(MSG,
++ "Invalid parameter, max passive scan time is %d ms\n",
++ MRVDRV_MAX_PASSIVE_SCAN_CHAN_TIME);
++ return -EINVAL;
++ }
++ Adapter->PassiveScanTime = data[2];
++ }
++ }
++
++ data[0] = Adapter->SpecificScanTime;
++ data[1] = Adapter->ActiveScanTime;
++ data[2] = Adapter->PassiveScanTime;
++ wrq->u.data.length = 3;
++ if (copy_to_user
++ (wrq->u.data.pointer, data, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set Adhoc beacon Interval
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_beacon_interval(wlan_private * priv, struct iwreq *wrq)
++{
++ int data[2];
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wrq->u.data.length > 0) {
++ if (copy_from_user(data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ PRINTM(INFO, "WLAN SET BEACON INTERVAL: %d\n", data[0]);
++ if ((data[0] > MRVDRV_MAX_BEACON_INTERVAL) ||
++ (data[0] < MRVDRV_MIN_BEACON_INTERVAL))
++ return -ENOTSUPP;
++ Adapter->BeaconPeriod = data[0];
++ }
++ data[0] = Adapter->BeaconPeriod;
++ wrq->u.data.length = 1;
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ data[1] = Adapter->CurBssParams.BSSDescriptor.BeaconPeriod;
++ wrq->u.data.length = 2;
++ }
++ if (copy_to_user
++ (wrq->u.data.pointer, data, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set Adhoc ATIM Window
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_ATIM_Window(wlan_private * priv, struct iwreq *wrq)
++{
++ int data[2];
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wrq->u.data.length > 0) {
++ if (copy_from_user(data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ PRINTM(INFO, "WLAN SET ATIM WINDOW: %d\n", data[0]);
++ Adapter->AtimWindow = data[0];
++ Adapter->AtimWindow = MIN(Adapter->AtimWindow, 50);
++ }
++ data[0] = Adapter->AtimWindow;
++ wrq->u.data.length = 1;
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ data[1] = Adapter->CurBssParams.BSSDescriptor.ATIMWindow;
++ wrq->u.data.length = 2;
++ }
++ if (copy_to_user
++ (wrq->u.data.pointer, data, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set data subscribe event
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_data_subscribe_event(wlan_private * priv, struct iwreq *wrq)
++{
++ int data[9];
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ memset(data, 0, sizeof(data));
++ if (wrq->u.data.length > 9)
++ return -EFAULT;
++ if (wrq->u.data.length > 0) {
++ if (copy_from_user
++ (data, wrq->u.data.pointer, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ memset(&Adapter->subevent, 0, sizeof(Adapter->subevent));
++ Adapter->subevent.EventsBitmap = (u16) data[0];
++ Adapter->subevent.Rssi_low.value = (u8) data[1];
++ Adapter->subevent.Rssi_low.Freq = (u8) data[2];
++ Adapter->subevent.Snr_low.value = (u8) data[3];
++ Adapter->subevent.Snr_low.Freq = (u8) data[4];
++ Adapter->subevent.Rssi_high.value = (u8) data[5];
++ Adapter->subevent.Rssi_high.Freq = (u8) data[6];
++ Adapter->subevent.Snr_high.value = (u8) data[7];
++ Adapter->subevent.Snr_high.Freq = (u8) data[8];
++ } else {
++ data[0] = (int) Adapter->subevent.EventsBitmap;
++ data[1] = (int) Adapter->subevent.Rssi_low.value;
++ data[2] = (int) Adapter->subevent.Rssi_low.Freq;
++ data[3] = (int) Adapter->subevent.Snr_low.value;
++ data[4] = (int) Adapter->subevent.Snr_low.Freq;
++ data[5] = (int) Adapter->subevent.Rssi_high.value;
++ data[6] = (int) Adapter->subevent.Rssi_high.Freq;
++ data[7] = (int) Adapter->subevent.Snr_high.value;
++ data[8] = (int) Adapter->subevent.Snr_high.Freq;
++ }
++ wrq->u.data.length = 9;
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(data))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get RSSI
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_rssi(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++ int temp;
++ int data = 0;
++ int *val;
++
++ ENTER();
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ if ((data == 0) || (data == 1)) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RSSI,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, NULL);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ }
++
++ switch (data) {
++ case 0:
++
++ temp = CAL_RSSI(Adapter->SNR[TYPE_BEACON][TYPE_NOAVG],
++ Adapter->NF[TYPE_BEACON][TYPE_NOAVG]);
++ break;
++ case 1:
++ temp = CAL_RSSI(Adapter->SNR[TYPE_BEACON][TYPE_AVG],
++ Adapter->NF[TYPE_BEACON][TYPE_AVG]);
++ break;
++ case 2:
++ if ((jiffies - Adapter->RxPDAge) > HZ) //data expired after 1 second
++ temp = 0;
++ else
++ temp = CAL_RSSI(Adapter->SNR[TYPE_RXPD][TYPE_NOAVG],
++ Adapter->NF[TYPE_RXPD][TYPE_NOAVG]);
++ break;
++ case 3:
++ temp = CAL_RSSI(Adapter->SNR[TYPE_RXPD][TYPE_AVG] / AVG_SCALE,
++ Adapter->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE);
++ break;
++ default:
++ return -ENOTSUPP;
++ }
++ val = (int *) wrq->u.name;
++ *val = temp;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get NF
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_nf(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++ int temp;
++ int data = 0;
++ int *val;
++
++ ENTER();
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ if ((data == 0) || (data == 1)) {
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RSSI,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ }
++
++ switch (data) {
++ case 0:
++ temp = Adapter->NF[TYPE_BEACON][TYPE_NOAVG];
++ break;
++ case 1:
++ temp = Adapter->NF[TYPE_BEACON][TYPE_AVG];
++ break;
++ case 2:
++ if ((jiffies - Adapter->RxPDAge) > HZ) //data expired after 1 second
++ temp = 0;
++ else
++ temp = Adapter->NF[TYPE_RXPD][TYPE_NOAVG];
++ break;
++ case 3:
++ temp = Adapter->NF[TYPE_RXPD][TYPE_AVG] / AVG_SCALE;
++ break;
++ default:
++ return -ENOTSUPP;
++ }
++
++ temp = CAL_NF(temp);
++
++ PRINTM(INFO, "***temp = %d\n", temp);
++ val = (int *) wrq->u.name;
++ *val = temp;
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Remove AES key
++ *
++ * @param priv A pointer to wlan_private structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_remove_aes(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ WLAN_802_11_KEY key;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (Adapter->InfrastructureMode != Wlan802_11IBSS ||
++ Adapter->MediaConnectStatus == WlanMediaStateConnected)
++ return -EOPNOTSUPP;
++
++ Adapter->AdhocAESEnabled = FALSE;
++
++ memset(&key, 0, sizeof(WLAN_802_11_KEY));
++ PRINTM(INFO, "WPA2: DISABLE AES_KEY\n");
++ key.KeyLength = WPA_AES_KEY_LEN;
++ key.KeyIndex = 0x40000000;
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_KEY_MATERIAL,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP,
++ !(KEY_INFO_ENABLED), &key);
++
++ LEAVE();
++
++ return ret;
++}
++
++/**
++ * @brief Get Support Rates
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_getrate_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ WLAN_802_11_RATES rates;
++ int rate[sizeof(rates)];
++ int i;
++
++ ENTER();
++
++ memset(rates, 0, sizeof(rates));
++ memset(rate, 0, sizeof(rate));
++ wrq->u.data.length = get_active_data_rates(Adapter, rates);
++ if (wrq->u.data.length > sizeof(rates))
++ wrq->u.data.length = sizeof(rates);
++
++ for (i = 0; i < wrq->u.data.length; i++) {
++ rates[i] &= ~0x80;
++ rate[i] = rates[i];
++ }
++
++ if (copy_to_user
++ (wrq->u.data.pointer, rate, wrq->u.data.length * sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get TxRate
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_txrate_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int *pdata;
++ struct iwreq *wrq = (struct iwreq *) req;
++ int ret = WLAN_STATUS_SUCCESS;
++ ENTER();
++ Adapter->TxRate = 0;
++ PRINTM(INFO, "wlan_get_txrate_ioctl\n");
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_TX_RATE_QUERY,
++ HostCmd_ACT_GET, HostCmd_OPTION_WAITFORRSP,
++ 0, NULL);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ pdata = (int *) wrq->u.name;
++ *pdata = (int) Adapter->TxRate;
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get DTIM
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_dtim_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ struct iwreq *wrq = (struct iwreq *) req;
++ int *pdata;
++ int ret = WLAN_STATUS_FAILURE;
++
++ ENTER();
++
++ /* The DTIM value is valid only in connected state */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ Adapter->Dtim = 0;
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SNMP_MIB,
++ HostCmd_ACT_GET,
++ HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_DTIM, NULL);
++ if (!ret) {
++ pdata = (int *) wrq->u.name;
++ *pdata = (int) Adapter->Dtim;
++ }
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get Adhoc Status
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_get_adhoc_status_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ char status[64];
++ wlan_adapter *Adapter = priv->adapter;
++
++ memset(status, 0, sizeof(status));
++
++ switch (Adapter->InfrastructureMode) {
++ case Wlan802_11IBSS:
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ if (Adapter->AdhocCreate == TRUE)
++ strcpy(status, "AdhocStarted");
++ else
++ strcpy(status, "AdhocJoined");
++ } else {
++ strcpy(status, "AdhocIdle");
++ }
++ break;
++ case Wlan802_11Infrastructure:
++ strcpy(status, "InfraMode");
++ break;
++ default:
++ strcpy(status, "AutoUnknownMode");
++ break;
++ }
++
++ PRINTM(INFO, "Status = %s\n", status);
++ wrq->u.data.length = strlen(status) + 1;
++
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, &status, wrq->u.data.length))
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get Driver Version
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_version_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int len;
++ char buf[128];
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ ENTER();
++
++ get_version(priv->adapter, buf, sizeof(buf) - 1);
++
++ len = strlen(buf);
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, buf, len)) {
++ PRINTM(INFO, "CopyToUser failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = len;
++ }
++
++ PRINTM(INFO, "wlan version: %s\n", buf);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get Driver and FW version
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_verext_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ HostCmd_DS_VERSION_EXT versionExtCmd;
++ int len;
++
++ ENTER();
++
++ memset(&versionExtCmd, 0x00, sizeof(versionExtCmd));
++
++ if (wrq->u.data.flags == 0) {
++ //from iwpriv subcmd
++ versionExtCmd.versionStrSel =
++ *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ } else {
++ if (copy_from_user(&versionExtCmd.versionStrSel,
++ wrq->u.data.pointer,
++ sizeof(versionExtCmd.versionStrSel))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ }
++
++ PrepareAndSendCommand(priv,
++ HostCmd_CMD_VERSION_EXT, 0,
++ HostCmd_OPTION_WAITFORRSP, 0, &versionExtCmd);
++
++ len = strlen(versionExtCmd.versionStr) + 1;
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, versionExtCmd.versionStr, len)) {
++ PRINTM(INFO, "CopyToUser failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = len;
++ }
++
++ PRINTM(INFO, "Version: %s\n", versionExtCmd.versionStr);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Read/Write adapter registers
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_regrdwr_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ wlan_ioctl_regrdwr regrdwr;
++ wlan_offset_value offval;
++ u8 *pRdeeprom;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (copy_from_user(&regrdwr, req->ifr_data, sizeof(regrdwr))) {
++ PRINTM(INFO,
++ "copy of regrdwr for wlan_regrdwr_ioctl from user failed \n");
++ LEAVE();
++ return -EFAULT;
++ }
++
++ if (regrdwr.WhichReg == REG_EEPROM) {
++ PRINTM(INFO, "Inside RDEEPROM\n");
++ pRdeeprom =
++ (char *) kmalloc((regrdwr.NOB + sizeof(regrdwr)), GFP_KERNEL);
++ if (!pRdeeprom) {
++ PRINTM(INFO, "allocate memory for EEPROM read failed\n");
++ return -ENOMEM;
++ }
++ memcpy(pRdeeprom, &regrdwr, sizeof(regrdwr));
++ PRINTM(INFO, "Action: %d, Offset: %x, NOB: %02x\n",
++ regrdwr.Action, regrdwr.Offset, regrdwr.NOB);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_EEPROM_ACCESS,
++ regrdwr.Action, HostCmd_OPTION_WAITFORRSP,
++ 0, pRdeeprom);
++
++ /*
++ * Return the result back to the user
++ */
++ if (!ret && regrdwr.Action == HostCmd_ACT_GEN_READ) {
++ if (copy_to_user
++ (req->ifr_data, pRdeeprom, sizeof(regrdwr) + regrdwr.NOB)) {
++ PRINTM(INFO,
++ "copy of regrdwr for wlan_regrdwr_ioctl to user failed \n");
++ ret = -EFAULT;
++ }
++ }
++
++ kfree(pRdeeprom);
++
++ LEAVE();
++ return ret;
++ }
++
++ offval.offset = regrdwr.Offset;
++ offval.value = (regrdwr.Action) ? regrdwr.Value : 0x00;
++
++ PRINTM(INFO, "RegAccess: %02x Action:%d "
++ "Offset: %04x Value: %04x\n",
++ regrdwr.WhichReg, regrdwr.Action, offval.offset, offval.value);
++
++ /*
++ * regrdwr.WhichReg should contain the command that
++ * corresponds to which register access is to be
++ * performed HostCmd_CMD_MAC_REG_ACCESS 0x0019
++ * HostCmd_CMD_BBP_REG_ACCESS 0x001a
++ * HostCmd_CMD_RF_REG_ACCESS 0x001b
++ */
++ if (regrdwr.WhichReg == REG_MAC ||
++ regrdwr.WhichReg == REG_BBP || regrdwr.WhichReg == REG_RF) {
++ ret = PrepareAndSendCommand(priv, regrdwr.WhichReg,
++ regrdwr.Action, HostCmd_OPTION_WAITFORRSP,
++ 0, &offval);
++ } else
++ ret = -EINVAL;
++
++ /*
++ * Return the result back to the user
++ */
++ if (!ret && regrdwr.Action == HostCmd_ACT_GEN_READ) {
++ regrdwr.Value = offval.value;
++ if (copy_to_user(req->ifr_data, &regrdwr, sizeof(regrdwr))) {
++ PRINTM(INFO,
++ "copy of regrdwr for wlan_regrdwr_ioctl to user failed \n");
++ ret = -EFAULT;
++ }
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Cmd52 read/write register
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_cmd52rdwr_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ u8 buf[7];
++ u8 rw, func, dat = 0xff;
++ u32 reg;
++
++ ENTER();
++
++ if (copy_from_user(buf, req->ifr_data, sizeof(buf))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ rw = buf[0];
++ func = buf[1];
++ reg = buf[5];
++ reg = (reg << 8) + buf[4];
++ reg = (reg << 8) + buf[3];
++ reg = (reg << 8) + buf[2];
++
++ if (rw != 0)
++ dat = buf[6];
++
++ PRINTM(INFO, "rw=%d func=%d reg=0x%08X dat=0x%02X\n", rw, func, reg, dat);
++
++ if (rw == 0) {
++ if (sbi_read_ioreg(priv, func, reg, &dat) < 0) {
++ PRINTM(INFO, "sdio_read_ioreg: reading register 0x%X failed\n",
++ reg);
++ dat = 0xff;
++ }
++ } else {
++ if (sbi_write_ioreg(priv, func, reg, dat) < 0) {
++ PRINTM(INFO, "sdio_read_ioreg: writing register 0x%X failed\n",
++ reg);
++ dat = 0xff;
++ }
++ }
++ if (copy_to_user(req->ifr_data, &dat, sizeof(dat))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Cmd53 read/write register
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_cmd53rdwr_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ return -EINVAL;
++}
++
++/**
++ * @brief Convert ascii string to Hex integer
++ *
++ * @param d A pointer to integer buf
++ * @param s A pointer to ascii string
++ * @param dlen the length o fascii string
++ * @return number of integer
++ */
++static int
++ascii2hex(u8 * d, char *s, u32 dlen)
++{
++ int i;
++ u8 n;
++
++ memset(d, 0x00, dlen);
++
++ for (i = 0; i < dlen * 2; i++) {
++ if ((s[i] >= 48) && (s[i] <= 57))
++ n = s[i] - 48;
++ else if ((s[i] >= 65) && (s[i] <= 70))
++ n = s[i] - 55;
++ else if ((s[i] >= 97) && (s[i] <= 102))
++ n = s[i] - 87;
++ else
++ break;
++ if ((i % 2) == 0)
++ n = n * 16;
++ d[i / 2] += n;
++ }
++
++ return i;
++}
++
++/**
++ * @brief Set adhoc aes key
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_setadhocaes_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ u8 key_ascii[32];
++ u8 key_hex[16];
++ int ret = 0;
++ struct iwreq *wrq = (struct iwreq *) req;
++ wlan_adapter *Adapter = priv->adapter;
++
++ WLAN_802_11_KEY key;
++
++ ENTER();
++
++ if (Adapter->InfrastructureMode != Wlan802_11IBSS)
++ return -EOPNOTSUPP;
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected)
++ return -EOPNOTSUPP;
++
++ if (copy_from_user(key_ascii, wrq->u.data.pointer, sizeof(key_ascii))) {
++ PRINTM(INFO, "wlan_setadhocaes_ioctl copy from user failed \n");
++ LEAVE();
++ return -EFAULT;
++ }
++
++ Adapter->AdhocAESEnabled = TRUE;
++ ascii2hex(key_hex, key_ascii, sizeof(key_hex));
++
++ HEXDUMP("wlan_setadhocaes_ioctl", key_hex, sizeof(key_hex));
++
++ PRINTM(INFO, "WPA2: ENABLE AES_KEY\n");
++ key.KeyLength = WPA_AES_KEY_LEN;
++ key.KeyIndex = 0x40000000;
++ memcpy(key.KeyMaterial, key_hex, key.KeyLength);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_KEY_MATERIAL,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP,
++ KEY_INFO_ENABLED, &key);
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get adhoc aes key
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_getadhocaes_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ u8 *tmp;
++ u8 key_ascii[33];
++ u8 key_hex[16];
++ int i, ret = 0;
++ struct iwreq *wrq = (struct iwreq *) req;
++ wlan_adapter *Adapter = priv->adapter;
++ WLAN_802_11_KEY key;
++
++ ENTER();
++
++ memset(key_hex, 0x00, sizeof(key_hex));
++
++ PRINTM(INFO, "WPA2: ENABLE AES_KEY\n");
++ key.KeyLength = WPA_AES_KEY_LEN;
++ key.KeyIndex = 0x40000000;
++ memcpy(key.KeyMaterial, key_hex, key.KeyLength);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_KEY_MATERIAL,
++ HostCmd_ACT_GET,
++ HostCmd_OPTION_WAITFORRSP,
++ KEY_INFO_ENABLED, &key);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ memcpy(key_hex, Adapter->aeskey.KeyParamSet.Key, sizeof(key_hex));
++
++ HEXDUMP("wlan_getadhocaes_ioctl", key_hex, sizeof(key_hex));
++
++ wrq->u.data.length = sizeof(key_ascii) + 1;
++
++ memset(key_ascii, 0x00, sizeof(key_ascii));
++ tmp = key_ascii;
++
++ for (i = 0; i < sizeof(key_hex); i++)
++ tmp += sprintf(tmp, "%02x", key_hex[i]);
++
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, &key_ascii, sizeof(key_ascii))) {
++ PRINTM(INFO, "copy_to_user failed\n");
++ return -EFAULT;
++ }
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set multiple dtim
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_multiple_dtim_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ struct iwreq *wrq = (struct iwreq *) req;
++ u32 mdtim;
++ int idata;
++ int ret = -EINVAL;
++
++ ENTER();
++
++ idata = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ mdtim = (u32) idata;
++ if (((mdtim >= MRVDRV_MIN_MULTIPLE_DTIM) &&
++ (mdtim <= MRVDRV_MAX_MULTIPLE_DTIM))
++ || (mdtim == MRVDRV_IGNORE_MULTIPLE_DTIM)) {
++ priv->adapter->MultipleDtim = mdtim;
++ ret = WLAN_STATUS_SUCCESS;
++ }
++ if (ret)
++ PRINTM(INFO, "Invalid parameter, MultipleDtim not changed.\n");
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set authentication mode
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_setauthalg_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int alg;
++ struct iwreq *wrq = (struct iwreq *) req;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wrq->u.data.flags == 0) {
++ //from iwpriv subcmd
++ alg = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ } else {
++ //from wpa_supplicant subcmd
++ if (copy_from_user(&alg, wrq->u.data.pointer, sizeof(alg))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ }
++
++ PRINTM(INFO, "auth alg is %#x\n", alg);
++
++ switch (alg) {
++ case AUTH_ALG_SHARED_KEY:
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeShared;
++ break;
++ case AUTH_ALG_NETWORK_EAP:
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeNetworkEAP;
++ break;
++ case AUTH_ALG_OPEN_SYSTEM:
++ default:
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeOpen;
++ break;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set Encryption mode
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_setencryptionmode_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int mode;
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ ENTER();
++
++ if (wrq->u.data.flags == 0) {
++ //from iwpriv subcmd
++ mode = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ } else {
++ //from wpa_supplicant subcmd
++ if (copy_from_user(&mode, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ }
++ PRINTM(INFO, "encryption mode is %#x\n", mode);
++ priv->adapter->SecInfo.EncryptionMode = mode;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get Rx antenna
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_subcmd_getrxantenna_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int len;
++ char buf[8];
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ ENTER();
++
++ PRINTM(INFO, "WLAN_SUBCMD_GETRXANTENNA\n");
++ len = GetRxAntenna(priv, buf);
++
++ wrq->u.data.length = len;
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, &buf, len)) {
++ PRINTM(INFO, "CopyToUser failed\n");
++ return -EFAULT;
++ }
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get Tx antenna
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_subcmd_gettxantenna_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int len;
++ char buf[8];
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ ENTER();
++
++ PRINTM(INFO, "WLAN_SUBCMD_GETTXANTENNA\n");
++ len = GetTxAntenna(priv, buf);
++
++ wrq->u.data.length = len;
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, &buf, len)) {
++ PRINTM(INFO, "CopyToUser failed\n");
++ return -EFAULT;
++ }
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get the MAC TSF value from the firmware
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure containing buffer
++ * space to store a TSF value retrieved from the firmware
++ *
++ * @return 0 if successful; IOCTL error code otherwise
++ */
++static int
++wlan_get_tsf_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ u64 tsfVal = 0;
++ int ret;
++
++ ENTER();
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_GET_TSF,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, &tsfVal);
++
++ PRINTM(INFO, "IOCTL: Get TSF = 0x%016llx\n", tsfVal);
++
++ if (ret != WLAN_STATUS_SUCCESS) {
++ PRINTM(INFO, "IOCTL: Get TSF; Command exec failed\n");
++ ret = -EFAULT;
++ } else {
++ if (copy_to_user(wrq->u.data.pointer,
++ &tsfVal,
++ MIN(wrq->u.data.length, sizeof(tsfVal))) != 0) {
++
++ PRINTM(INFO, "IOCTL: Get TSF; Copy to user failed\n");
++ ret = -EFAULT;
++ } else {
++ ret = 0;
++ }
++ }
++
++ LEAVE();
++
++ return ret;
++}
++
++/**
++ * @brief Control WPS Session Enable/Disable
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_do_wps_session_ioctl(wlan_private * priv, struct iwreq *req)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ char buf[8];
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ ENTER();
++
++ PRINTM(INFO, "WLAN_WPS_SESSION\n");
++
++ memset(buf, 0, sizeof(buf));
++ if (copy_from_user(buf, wrq->u.data.pointer,
++ MIN(sizeof(buf) - 1, wrq->u.data.length))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ if (buf[0] == 1)
++ Adapter->wps.SessionEnable = TRUE;
++ else
++ Adapter->wps.SessionEnable = FALSE;
++
++ PRINTM(INFO, "Adapter->wps.SessionEnable = %d\n",
++ Adapter->wps.SessionEnable);
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set DeepSleep mode
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_deepsleep_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ char status[128];
++ struct iwreq *wrq = (struct iwreq *) req;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ PRINTM(MSG, "Cannot enter Deep Sleep mode in connected state.\n");
++ return -EINVAL;
++ }
++
++ if (*(char *) req->ifr_data == '0') {
++ PRINTM(INFO, "Exit Deep Sleep Mode.\n");
++ sprintf(status, "setting to off ");
++ SetDeepSleep(priv, FALSE);
++ } else if (*(char *) req->ifr_data == '1') {
++ PRINTM(INFO, "Enter Deep Sleep Mode.\n");
++ sprintf(status, "setting to on ");
++ SetDeepSleep(priv, TRUE);
++ } else if (*(char *) req->ifr_data == '2') {
++ PRINTM(INFO, "Get Deep Sleep Mode.\n");
++ if (Adapter->IsDeepSleep == TRUE) {
++ sprintf(status, "on ");
++ } else {
++ sprintf(status, "off ");
++ }
++ } else {
++ PRINTM(INFO, "unknown option = %d\n", *(u8 *) req->ifr_data);
++ return -EINVAL;
++ }
++
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, &status, strlen(status)))
++ return -EFAULT;
++ wrq->u.data.length = strlen(status);
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Config hostsleep parameter
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_do_hostsleepcfg_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ char buf[32];
++ int ret = WLAN_STATUS_SUCCESS;
++ int gpio, gap;
++
++ memset(buf, 0, sizeof(buf));
++ if (copy_from_user(buf, wrq->u.data.pointer,
++ MIN(sizeof(buf) - 1, wrq->u.data.length))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ buf[sizeof(buf) - 1] = 0;
++
++ if (sscanf(buf, "%x %x %x", &Adapter->HSCfg.conditions, &gpio, &gap) != 3) {
++ PRINTM(MSG, "Invalid parameters\n");
++ return -EINVAL;
++ }
++
++ if (Adapter->HSCfg.conditions != HOST_SLEEP_CFG_CANCEL) {
++ Adapter->HSCfg.gpio = (u8) gpio;
++ Adapter->HSCfg.gap = (u8) gap;
++ }
++
++ PRINTM(INFO,
++ "hostsleepcfg: cond=%#x gpio=%#x gap=%#x PSState=%d HS_Activated=%d\n",
++ Adapter->HSCfg.conditions, Adapter->HSCfg.gpio, Adapter->HSCfg.gap,
++ Adapter->PSState, Adapter->HS_Activated);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_HOST_SLEEP_CFG,
++ 0, HostCmd_OPTION_WAITFORRSP, 0,
++ &Adapter->HSCfg);
++
++ return ret;
++}
++
++/**
++ * @brief Config Host Sleep parameters
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_hscfg_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data[3] = { -1, 0xff, 0xff };
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (wrq->u.data.length >= 1 && wrq->u.data.length <= 3) {
++ if (copy_from_user
++ (data, wrq->u.data.pointer, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ PRINTM(INFO,
++ "wlan_hscfg_ioctl: data[0]=%#08x, data[1]=%#02x, data[2]=%#02x\n",
++ data[0], data[1], data[2]);
++ } else {
++ PRINTM(MSG, "Invalid Argument\n");
++ return -EINVAL;
++ }
++
++ Adapter->HSCfg.conditions = data[0];
++ if (Adapter->HSCfg.conditions != HOST_SLEEP_CFG_CANCEL) {
++ if (wrq->u.data.length == 2) {
++ Adapter->HSCfg.gpio = (u8) data[1];
++ } else if (wrq->u.data.length == 3) {
++ Adapter->HSCfg.gpio = (u8) data[1];
++ Adapter->HSCfg.gap = (u8) data[2];
++ }
++ }
++
++ PRINTM(INFO,
++ "hscfg: cond=%#x gpio=%#x gap=%#x PSState=%d HS_Activated=%d\n",
++ Adapter->HSCfg.conditions, Adapter->HSCfg.gpio, Adapter->HSCfg.gap,
++ Adapter->PSState, Adapter->HS_Activated);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_HOST_SLEEP_CFG,
++ 0, HostCmd_OPTION_WAITFORRSP, 0,
++ &Adapter->HSCfg);
++
++ data[0] = Adapter->HSCfg.conditions;
++ data[1] = Adapter->HSCfg.gpio;
++ data[2] = Adapter->HSCfg.gap;
++ wrq->u.data.length = 3;
++ if (copy_to_user
++ (wrq->u.data.pointer, data, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set Host Sleep parameters
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wreq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_hssetpara_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data[3] = { -1, 0xff, 0xff };
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (wrq->u.data.length >= 1 && wrq->u.data.length <= 3) {
++ if (copy_from_user
++ (data, wrq->u.data.pointer, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ PRINTM(INFO,
++ "wlan_hssetpara_ioctl: data[0]=%#08x, data[1]=%#02x, data[2]=%#02x\n",
++ data[0], data[1], data[2]);
++ }
++
++ Adapter->HSCfg.conditions = data[0];
++ if (Adapter->HSCfg.conditions != HOST_SLEEP_CFG_CANCEL) {
++ if (wrq->u.data.length == 2) {
++ Adapter->HSCfg.gpio = (u8) data[1];
++ } else if (wrq->u.data.length == 3) {
++ Adapter->HSCfg.gpio = (u8) data[1];
++ Adapter->HSCfg.gap = (u8) data[2];
++ }
++ }
++
++ PRINTM(INFO,
++ "hssetpara: cond=%#x gpio=%#x gap=%#x PSState=%d HS_Activated=%d\n",
++ Adapter->HSCfg.conditions, Adapter->HSCfg.gpio, Adapter->HSCfg.gap,
++ Adapter->PSState, Adapter->HS_Activated);
++
++ data[0] = Adapter->HSCfg.conditions;
++ data[1] = Adapter->HSCfg.gpio;
++ data[2] = Adapter->HSCfg.gap;
++ wrq->u.data.length = 3;
++ if (copy_to_user
++ (wrq->u.data.pointer, data, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set Cal data ext
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_do_caldata_ext_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ HostCmd_DS_802_11_CAL_DATA_EXT *pCalData = NULL;
++ int ret = WLAN_STATUS_SUCCESS;
++ u16 action;
++
++ ENTER();
++
++ if (!(pCalData = kmalloc(MAX_SETGET_CONF_CMD_LEN, GFP_KERNEL))) {
++ PRINTM(INFO, "Allocate memory failed\n");
++ ret = -ENOMEM;
++ goto calexit;
++ }
++ memset(pCalData, 0, MAX_SETGET_CONF_CMD_LEN);
++
++ if (copy_from_user(pCalData, req->ifr_data + SKIP_CMDNUM,
++ MAX_SETGET_CONF_CMD_LEN)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ kfree(pCalData);
++ ret = -EFAULT;
++ goto calexit;
++ }
++
++ action = (pCalData->Action == HostCmd_ACT_GEN_SET) ?
++ HostCmd_ACT_GEN_SET : HostCmd_ACT_GEN_GET;
++
++ HEXDUMP("Cal data ext", (u8 *) pCalData, MAX_SETGET_CONF_CMD_LEN);
++
++ PRINTM(INFO, "CalData Action = 0x%0X\n", action);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_CAL_DATA_EXT,
++ action,
++ HostCmd_OPTION_WAITFORRSP, 0, pCalData);
++
++ if (!ret && action == HostCmd_ACT_GEN_GET) {
++ if (copy_to_user(req->ifr_data + SKIP_CMDNUM, pCalData,
++ MAX_SETGET_CONF_CMD_LEN)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ ret = -EFAULT;
++ }
++ }
++
++ kfree(pCalData);
++ calexit:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set sleep period
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_sleep_period(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret;
++ int data;
++ wlan_adapter *Adapter = priv->adapter;
++ HostCmd_DS_802_11_SLEEP_PERIOD sleeppd;
++
++ ENTER();
++
++ if (wrq->u.data.length > 1)
++ return -ENOTSUPP;
++
++ memset(&sleeppd, 0, sizeof(sleeppd));
++ memset(&Adapter->sleep_period, 0, sizeof(SleepPeriod));
++
++ if (wrq->u.data.length == 0) {
++ sleeppd.Action = HostCmd_ACT_GEN_GET;
++ } else {
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ /* sleep period is 0 or 10~60 in milliseconds */
++#define MIN_SLEEP_PERIOD 10
++#define MAX_SLEEP_PERIOD 60
++#define SLEEP_PERIOD_RESERVED_FF 0xFF
++ if ((data <= MAX_SLEEP_PERIOD && data >= MIN_SLEEP_PERIOD) ||
++ (data == 0)
++ || (data == SLEEP_PERIOD_RESERVED_FF) /* for UPSD certification tests */
++ ) {
++ sleeppd.Action = HostCmd_ACT_GEN_SET;
++ sleeppd.Period = data;
++ } else
++ return -EINVAL;
++ }
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SLEEP_PERIOD,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, (void *) &sleeppd);
++
++ data = (int) Adapter->sleep_period.period;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set adapt rate
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_adapt_rateset(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret;
++ wlan_adapter *Adapter = priv->adapter;
++ int data[4];
++ int rateindex;
++
++ ENTER();
++ memset(data, 0, sizeof(data));
++ if (!wrq->u.data.length) {
++ PRINTM(INFO, "Get ADAPT RATE SET\n");
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RATE_ADAPT_RATESET,
++ HostCmd_ACT_GEN_GET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++ data[0] = Adapter->HWRateDropMode;
++ data[2] = Adapter->Threshold;
++ data[3] = Adapter->FinalRate;
++ wrq->u.data.length = 4;
++ data[1] = Adapter->RateBitmap;
++ if (copy_to_user
++ (wrq->u.data.pointer, data, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ } else {
++ PRINTM(INFO, "Set ADAPT RATE SET\n");
++ if (wrq->u.data.length > 4)
++ return -EINVAL;
++ if (copy_from_user
++ (data, wrq->u.data.pointer, sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ if (data[0] > HW_SINGLE_RATE_DROP)
++ return -EINVAL;
++ Adapter->HWRateDropMode = data[0];
++ Adapter->Threshold = data[2];
++ Adapter->FinalRate = data[3];
++ Adapter->RateBitmap = data[1];
++ Adapter->Is_DataRate_Auto = Is_Rate_Auto(priv);
++ if (Adapter->Is_DataRate_Auto)
++ Adapter->DataRate = 0;
++ else {
++ rateindex = GetRateIndex(priv);
++ Adapter->DataRate = index_to_data_rate(rateindex);
++ }
++ PRINTM(INFO, "RateBitmap=%x,IsRateAuto=%d,DataRate=%d\n",
++ Adapter->RateBitmap, Adapter->Is_DataRate_Auto,
++ Adapter->DataRate);
++ ret =
++ PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RATE_ADAPT_RATESET,
++ HostCmd_ACT_GEN_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set inactivity timeout
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_inactivity_timeout(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret;
++ int data = 0;
++ u16 timeout = 0;
++
++ ENTER();
++ if (wrq->u.data.length > 1)
++ return -ENOTSUPP;
++
++ if (wrq->u.data.length == 0) {
++ /* Get */
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_INACTIVITY_TIMEOUT,
++ HostCmd_ACT_GET,
++ HostCmd_OPTION_WAITFORRSP, 0, &timeout);
++ data = timeout;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ } else {
++ /* Set */
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ timeout = data;
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_INACTIVITY_TIMEOUT,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, &timeout);
++ }
++
++ wrq->u.data.length = 1;
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get LOG
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_do_getlog_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret;
++ char *buf = NULL;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ PRINTM(INFO, " GET STATS\n");
++
++ if (!(buf = kmalloc(GETLOG_BUFSIZE, GFP_KERNEL))) {
++ PRINTM(INFO, "kmalloc failed!\n");
++ return -ENOMEM;
++ }
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_GET_LOG,
++ 0, HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ if (!ret && wrq->u.data.pointer) {
++ sprintf(buf, "\n"
++ "mcasttxframe %u\n"
++ "failed %u\n"
++ "retry %u\n"
++ "multiretry %u\n"
++ "framedup %u\n"
++ "rtssuccess %u\n"
++ "rtsfailure %u\n"
++ "ackfailure %u\n"
++ "rxfrag %u\n"
++ "mcastrxframe %u\n"
++ "fcserror %u\n"
++ "txframe %u\n",
++ Adapter->LogMsg.mcasttxframe,
++ Adapter->LogMsg.failed,
++ Adapter->LogMsg.retry,
++ Adapter->LogMsg.multiretry,
++ Adapter->LogMsg.framedup,
++ Adapter->LogMsg.rtssuccess,
++ Adapter->LogMsg.rtsfailure,
++ Adapter->LogMsg.ackfailure,
++ Adapter->LogMsg.rxfrag,
++ Adapter->LogMsg.mcastrxframe,
++ Adapter->LogMsg.fcserror, Adapter->LogMsg.txframe);
++
++ wrq->u.data.length = strlen(buf) + 1;
++ if (copy_to_user(wrq->u.data.pointer, buf, wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ ret = -EFAULT;
++ }
++ }
++
++ kfree(buf);
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief config sleep parameters
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_sleep_params_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret;
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_ioctl_sleep_params_config sp;
++
++ ENTER();
++
++ memset(&sp, 0, sizeof(sp));
++
++ if (!wrq->u.data.pointer)
++ return -EFAULT;
++ if (copy_from_user(&sp, wrq->u.data.pointer,
++ MIN(sizeof(sp), wrq->u.data.length))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ memcpy(&Adapter->sp, &sp.Error, sizeof(SleepParams));
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_SLEEP_PARAMS,
++ sp.Action, HostCmd_OPTION_WAITFORRSP,
++ 0, NULL);
++
++ if (!ret && !sp.Action) {
++ memcpy(&sp.Error, &Adapter->sp, sizeof(SleepParams));
++ if (copy_to_user(wrq->u.data.pointer, &sp, sizeof(sp))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = sizeof(sp);
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Read the CIS Table
++ * @param priv A pointer to wlan_private structure
++ * @param req A pointer to ifreq structure
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_do_getcis_ioctl(wlan_private * priv, struct ifreq *req)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ struct iwreq *wrq = (struct iwreq *) req;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wrq->u.data.pointer) {
++ if (copy_to_user(wrq->u.data.pointer, Adapter->CisInfoBuf,
++ Adapter->CisInfoLen)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = Adapter->CisInfoLen;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set BCA timeshare
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_bca_timeshare_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ int ret;
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_ioctl_bca_timeshare_config bca_ts;
++
++ ENTER();
++
++ memset(&bca_ts, 0, sizeof(HostCmd_DS_802_11_BCA_TIMESHARE));
++
++ if (!wrq->u.data.pointer)
++ return -EFAULT;
++ if (copy_from_user(&bca_ts, wrq->u.data.pointer,
++ MIN(sizeof(bca_ts), wrq->u.data.length))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ PRINTM(INFO, "TrafficType=%x TimeShareInterva=%x BTTime=%x\n",
++ bca_ts.TrafficType, bca_ts.TimeShareInterval, bca_ts.BTTime);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_BCA_CONFIG_TIMESHARE,
++ bca_ts.Action, HostCmd_OPTION_WAITFORRSP,
++ 0, &bca_ts);
++
++ if (!ret && !bca_ts.Action) {
++ if (copy_to_user(wrq->u.data.pointer, &Adapter->bca_ts,
++ sizeof(bca_ts))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = sizeof(HostCmd_DS_802_11_BCA_TIMESHARE);
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set scan type
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_scan_type_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ u8 buf[12];
++ u8 *option[] = { "active", "passive", "get", };
++ int i, max_options = (sizeof(option) / sizeof(option[0]));
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (wlan_get_state_11d(priv) == ENABLE_11D) {
++ PRINTM(INFO, "11D: Cannot set scantype when 11D enabled\n");
++ return -EFAULT;
++ }
++
++ memset(buf, 0, sizeof(buf));
++
++ if (copy_from_user(buf, wrq->u.data.pointer, MIN(sizeof(buf),
++ wrq->u.data.length))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ PRINTM(INFO, "Scan Type Option = %s\n", buf);
++
++ buf[sizeof(buf) - 1] = '\0';
++
++ for (i = 0; i < max_options; i++) {
++ if (!strcmp(buf, option[i]))
++ break;
++ }
++
++ switch (i) {
++ case 0:
++ Adapter->ScanType = HostCmd_SCAN_TYPE_ACTIVE;
++
++ break;
++ case 1:
++ Adapter->ScanType = HostCmd_SCAN_TYPE_PASSIVE;
++ break;
++ case 2:
++ wrq->u.data.length = strlen(option[Adapter->ScanType]) + 1;
++
++ if (copy_to_user(wrq->u.data.pointer,
++ option[Adapter->ScanType], wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ ret = -EFAULT;
++ }
++
++ break;
++ default:
++ PRINTM(INFO, "Invalid Scan Type Ioctl Option\n");
++ ret = -EINVAL;
++ break;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Set scan mode
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_scan_mode_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ u8 buf[12];
++ u8 *option[] = { "bss", "ibss", "any", "get" };
++ int i, max_options = (sizeof(option) / sizeof(option[0]));
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ memset(buf, 0, sizeof(buf));
++
++ if (copy_from_user(buf, wrq->u.data.pointer, MIN(sizeof(buf),
++ wrq->u.data.length))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ PRINTM(INFO, "Scan Mode Option = %s\n", buf);
++
++ buf[sizeof(buf) - 1] = '\0';
++
++ for (i = 0; i < max_options; i++) {
++ if (!strcmp(buf, option[i]))
++ break;
++ }
++
++ switch (i) {
++
++ case 0:
++ Adapter->ScanMode = HostCmd_BSS_TYPE_BSS;
++ break;
++ case 1:
++ Adapter->ScanMode = HostCmd_BSS_TYPE_IBSS;
++ break;
++ case 2:
++ Adapter->ScanMode = HostCmd_BSS_TYPE_ANY;
++ break;
++ case 3:
++
++ wrq->u.data.length = strlen(option[Adapter->ScanMode - 1]) + 1;
++
++ PRINTM(INFO, "Get Scan Mode Option = %s\n",
++ option[Adapter->ScanMode - 1]);
++
++ PRINTM(INFO, "Scan Mode Length %d\n", wrq->u.data.length);
++
++ if (copy_to_user(wrq->u.data.pointer,
++ option[Adapter->ScanMode - 1], wrq->u.data.length)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ ret = -EFAULT;
++ }
++ PRINTM(INFO, "GET Scan Type Option after copy = %s\n",
++ (char *) wrq->u.data.pointer);
++
++ break;
++
++ default:
++ PRINTM(INFO, "Invalid Scan Mode Ioctl Option\n");
++ ret = -EINVAL;
++ break;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set Adhoc G Rate
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_do_set_grate_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data, data1;
++ int *val;
++
++ ENTER();
++
++ data1 = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ switch (data1) {
++ case 0:
++ Adapter->adhoc_grate_enabled = FALSE;
++ break;
++ case 1:
++ Adapter->adhoc_grate_enabled = TRUE;
++ break;
++ case 2:
++ break;
++ default:
++ return -EINVAL;
++ }
++ data = Adapter->adhoc_grate_enabled;
++ val = (int *) wrq->u.name;
++ *val = data;
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get/Set Firmware wakeup method
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_cmd_fw_wakeup_method(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ u16 action;
++ u16 method;
++ int ret;
++ int data;
++
++ ENTER();
++
++ if (wrq->u.data.length == 0 || !wrq->u.data.pointer) {
++ action = HostCmd_ACT_GET;
++ method = Adapter->fwWakeupMethod;
++ } else {
++ action = HostCmd_ACT_SET;
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ switch (data) {
++ case 0:
++ method = WAKEUP_FW_UNCHANGED;
++ break;
++ case 1:
++ method = WAKEUP_FW_THRU_INTERFACE;
++ break;
++ case 2:
++ method = WAKEUP_FW_THRU_GPIO;
++ break;
++ default:
++ return -EINVAL;
++ }
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_FW_WAKE_METHOD, action,
++ HostCmd_OPTION_WAITFORRSP, 0, &method);
++
++ if (action == HostCmd_ACT_GET) {
++ method = Adapter->fwWakeupMethod;
++ if (copy_to_user(wrq->u.data.pointer, &method, sizeof(method))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++ }
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get/Set Auto Deep Sleep mode
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to user data
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++static int
++wlan_auto_deep_sleep(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int data;
++
++ ENTER();
++
++ if (wrq->u.data.length > 0 && wrq->u.data.pointer) {
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ switch (data) {
++ case 0:
++ if (Adapter->IsAutoDeepSleepEnabled) {
++ Adapter->IsAutoDeepSleepEnabled = FALSE;
++ /* Try to exit DS if auto DS disabled */
++ SetDeepSleep(priv, FALSE);
++ }
++ break;
++ case 1:
++ if (!Adapter->IsAutoDeepSleepEnabled) {
++ Adapter->IsAutoDeepSleepEnabled = TRUE;
++ /* Wakeup main thread to enter DS if auto DS enabled */
++ wake_up_interruptible(&priv->MainThread.waitQ);
++ }
++ break;
++ default:
++ return -EINVAL;
++ }
++ }
++
++ data = Adapter->IsAutoDeepSleepEnabled;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(data))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get the CFP table based on the region code
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_get_cfp_table_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ pwlan_ioctl_cfp_table ioctl_cfp;
++ CHANNEL_FREQ_POWER *cfp;
++ int cfp_no;
++ int regioncode;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (wrq->u.data.length == 0 || !wrq->u.data.pointer) {
++ ret = -EINVAL;
++ goto cfpexit;
++ }
++
++ ioctl_cfp = (pwlan_ioctl_cfp_table) wrq->u.data.pointer;
++
++ if (copy_from_user(&regioncode, &ioctl_cfp->region, sizeof(int))) {
++ PRINTM(INFO, "Get CFP table: copy from user failed\n");
++ ret = -EFAULT;
++ goto cfpexit;
++ }
++
++ if (!regioncode)
++ regioncode = Adapter->RegionCode;
++
++ cfp =
++ wlan_get_region_cfp_table((u8) regioncode, BAND_G | BAND_B, &cfp_no);
++
++ if (cfp == NULL) {
++ PRINTM(MSG, "No related CFP table found, region code = 0x%x\n",
++ regioncode);
++ ret = -EFAULT;
++ goto cfpexit;
++ }
++
++ if (copy_to_user(&ioctl_cfp->cfp_no, &cfp_no, sizeof(int))) {
++ PRINTM(INFO, "Get CFP table: copy to user failed\n");
++ ret = -EFAULT;
++ goto cfpexit;
++ }
++
++ if (copy_to_user
++ (ioctl_cfp->cfp, cfp, sizeof(CHANNEL_FREQ_POWER) * cfp_no)) {
++ PRINTM(INFO, "Get CFP table: copy to user failed\n");
++ ret = -EFAULT;
++ goto cfpexit;
++ }
++
++ wrq->u.data.length =
++ sizeof(int) * 2 + sizeof(CHANNEL_FREQ_POWER) * cfp_no;
++
++ cfpexit:
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Retrieve transmit packet statistics from the firmware
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param wrq A pointer to iwreq structure
++ *
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_tx_pkt_stats_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ HostCmd_DS_TX_PKT_STATS txPktStats;
++ int ret;
++
++ ENTER();
++
++ if (wrq->u.data.length == 0 || !wrq->u.data.pointer) {
++ LEAVE();
++ return -EINVAL;
++ }
++
++ if (wrq->u.data.length < sizeof(txPktStats)) {
++ LEAVE();
++ return -E2BIG;
++ }
++
++ memset(&txPktStats, 0x00, sizeof(txPktStats));
++
++ if ((ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_TX_PKT_STATS, 0,
++ HostCmd_OPTION_WAITFORRSP,
++ 0, &txPktStats))) {
++ LEAVE();
++ return ret;
++ }
++
++ if (copy_to_user(wrq->u.data.pointer,
++ (u8 *) & txPktStats, sizeof(txPktStats))) {
++ PRINTM(INFO, "TxPktStats: copy to user failed\n");
++ return -EFAULT;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/********************************************************
++ Global Functions
++********************************************************/
++/**
++ * @brief ioctl function - entry point
++ *
++ * @param dev A pointer to net_device structure
++ * @param req A pointer to ifreq structure
++ * @param cmd command
++ * @return WLAN_STATUS_SUCCESS--success, otherwise fail
++ */
++int
++wlan_do_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
++{
++ int subcmd = 0;
++ int idata = 0;
++ int *pdata;
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ struct iwreq *wrq = (struct iwreq *) req;
++
++ ENTER();
++
++ if (Adapter->bHostSleepConfigured) {
++ BOOLEAN cmd_allowed = FALSE;
++ int count = sizeof(Commands_Allowed_In_HostSleep)
++ / sizeof(Commands_Allowed_In_HostSleep[0]);
++
++ if (cmd == WLANHOSTSLEEPCFG) {
++ char buf[32];
++ u32 cond;
++
++ memset(buf, 0, sizeof(buf));
++ if (copy_from_user(buf, wrq->u.data.pointer,
++ MIN(sizeof(buf) - 1, wrq->u.data.length))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ buf[sizeof(buf) - 1] = 0;
++ sscanf(buf, "%x ", &cond);
++ if (cond == HOST_SLEEP_CFG_CANCEL) {
++ cmd_allowed = TRUE;
++ if (Adapter->IsDeepSleep) {
++ SetDeepSleep(priv, FALSE);
++ }
++ }
++ } else if (cmd == WLAN_SET_GET_SIXTEEN_INT &&
++ ((int) wrq->u.data.flags == WLANHSCFG)) {
++ u32 cond;
++ if (copy_from_user(&cond, wrq->u.data.pointer, sizeof(cond))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ if (cond == HOST_SLEEP_CFG_CANCEL) {
++ cmd_allowed = TRUE;
++ if (Adapter->IsDeepSleep) {
++ SetDeepSleep(priv, FALSE);
++ }
++ }
++ } else
++ if (Is_Command_Allowed_In_Sleep
++ (req, cmd, Commands_Allowed_In_HostSleep, count)) {
++ cmd_allowed = TRUE;
++ }
++ if (!cmd_allowed) {
++ PRINTM(MSG, "%s IOCTLS called when WLAN access is blocked\n",
++ __FUNCTION__);
++ return -EBUSY;
++ }
++ }
++
++ if (!Adapter->IsAutoDeepSleepEnabled) {
++ if (Adapter->IsDeepSleep) {
++ int count = sizeof(Commands_Allowed_In_DeepSleep)
++ / sizeof(Commands_Allowed_In_DeepSleep[0]);
++
++ if (!Is_Command_Allowed_In_Sleep
++ (req, cmd, Commands_Allowed_In_DeepSleep, count)) {
++ PRINTM(MSG,
++ "():%s IOCTLS called when station is"
++ " in DeepSleep\n", __FUNCTION__);
++ return -EBUSY;
++ }
++ }
++ } else if (cmd == WLANDEEPSLEEP) {
++ PRINTM(MSG,
++ "DeepSleep command is not allowed in AutoDeepSleep mode\n");
++ return -EBUSY;
++ }
++
++ PRINTM(INFO, "wlan_do_ioctl: ioctl cmd = 0x%x\n", cmd);
++ switch (cmd) {
++ case WLANEXTSCAN:
++ ret = wlan_extscan_ioctl(priv, req);
++ break;
++ case WLANHOSTCMD:
++ ret = wlan_hostcmd_ioctl(dev, req, cmd);
++ break;
++ case WLANARPFILTER:
++ ret = wlan_arpfilter_ioctl(dev, req, cmd);
++ break;
++
++ case WLANCISDUMP: /* Read CIS Table */
++ ret = wlan_do_getcis_ioctl(priv, req);
++ break;
++
++ case WLANSCAN_TYPE:
++ PRINTM(INFO, "Scan Type Ioctl\n");
++ ret = wlan_scan_type_ioctl(priv, wrq);
++ break;
++
++#ifdef MFG_CMD_SUPPORT
++ case WLANMANFCMD:
++ PRINTM(INFO, "Entering the Manufacturing ioctl SIOCCFMFG\n");
++ ret = wlan_mfg_command(priv, wrq);
++
++ PRINTM(INFO, "Manufacturing Ioctl %s\n",
++ (ret) ? "failed" : "success");
++ break;
++#endif
++
++ case WLANREGRDWR: /* Register read write command */
++ ret = wlan_regrdwr_ioctl(priv, req);
++ break;
++
++ case WLANCMD52RDWR: /* CMD52 read/write command */
++ ret = wlan_cmd52rdwr_ioctl(priv, req);
++ break;
++
++ case WLANCMD53RDWR: /* CMD53 read/write command */
++ ret = wlan_cmd53rdwr_ioctl(priv, req);
++ break;
++
++ case SIOCSIWENCODE: /* set encoding token & mode for WPA */
++ ret = wlan_set_encode(dev, NULL, &(wrq->u.data), wrq->u.data.pointer);
++ break;
++ case WLAN_SETNONE_GETNONE: /* set WPA mode on/off ioctl #20 */
++ switch (wrq->u.data.flags) {
++ case WLANDEAUTH:
++ PRINTM(INFO, "Deauth\n");
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure &&
++ Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ SendDeauthentication(priv);
++ } else if (Adapter->InfrastructureMode == Wlan802_11IBSS &&
++ Adapter->MediaConnectStatus ==
++ WlanMediaStateConnected) {
++ StopAdhocNetwork(priv);
++ }
++ break;
++
++ case WLANADHOCSTOP:
++ PRINTM(INFO, "Adhoc stop\n");
++ ret = wlan_do_adhocstop_ioctl(priv);
++ break;
++
++ case WLANRADIOON:
++ wlan_radio_ioctl(priv, RADIO_ON);
++ break;
++
++ case WLANRADIOOFF:
++ ret = wlan_radio_ioctl(priv, RADIO_OFF);
++ break;
++ case WLANREMOVEADHOCAES:
++ ret = wlan_remove_aes(priv);
++ break;
++#ifdef REASSOCIATION
++ case WLANREASSOCIATIONAUTO:
++ reassociation_on(priv);
++ break;
++ case WLANREASSOCIATIONUSER:
++ reassociation_off(priv);
++ break;
++#endif /* REASSOCIATION */
++ case WLANWLANIDLEON:
++ wlanidle_on(priv);
++ break;
++ case WLANWLANIDLEOFF:
++ wlanidle_off(priv);
++ break;
++ } /* End of switch */
++ break;
++
++ case WLAN_SETWORDCHAR_GETNONE:
++ switch (wrq->u.data.flags) {
++ case WLANSETADHOCAES:
++ ret = wlan_setadhocaes_ioctl(priv, req);
++ break;
++ }
++ break;
++
++ case WLAN_SETONEINT_GETWORDCHAR:
++ switch (wrq->u.data.flags) {
++ case WLANGETADHOCAES:
++ ret = wlan_getadhocaes_ioctl(priv, req);
++ break;
++ case WLANVERSION: /* Get driver version */
++ ret = wlan_version_ioctl(priv, req);
++ break;
++ case WLANVEREXT:
++ ret = wlan_verext_ioctl(priv, wrq);
++ break;
++ }
++ break;
++
++ case WLANSETWPAIE:
++ ret = wlan_set_wpa_ie_ioctl(priv, req);
++ break;
++ case WLAN_SETINT_GETINT:
++ /* The first 4 bytes of req->ifr_data is sub-ioctl number
++ * after 4 bytes sits the payload.
++ */
++ subcmd = (int) req->ifr_data; //from iwpriv subcmd
++ switch (subcmd) {
++ case WLANNF:
++ ret = wlan_get_nf(priv, wrq);
++ break;
++ case WLANRSSI:
++ ret = wlan_get_rssi(priv, wrq);
++ break;
++ case WLANBGSCAN:
++ {
++ int data, data1;
++ int *val;
++ data1 = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ switch (data1) {
++ case CMD_DISABLED:
++ PRINTM(INFO, "Background scan is set to disable\n");
++ ret = wlan_bg_scan_enable(priv, FALSE);
++ val = (int *) wrq->u.name;
++ *val = data1;
++ break;
++ case CMD_ENABLED:
++ PRINTM(INFO, "Background scan is set to enable\n");
++ ret = wlan_bg_scan_enable(priv, TRUE);
++ val = (int *) wrq->u.name;
++ *val = data1;
++ break;
++ case CMD_GET:
++ data = (Adapter->bgScanConfig->Enable == TRUE) ?
++ CMD_ENABLED : CMD_DISABLED;
++ val = (int *) wrq->u.name;
++ *val = data;
++ break;
++ default:
++ ret = -EINVAL;
++ PRINTM(INFO, "Background scan: wrong parameter\n");
++ break;
++ }
++ }
++ break;
++ case WLANENABLE11D:
++ ret = wlan_cmd_enable_11d(priv, wrq);
++ break;
++ case WLANADHOCGRATE:
++ ret = wlan_do_set_grate_ioctl(priv, wrq);
++ break;
++ case WLANSDIOCLOCK:
++ {
++ int data;
++ int *val;
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ switch (data) {
++ case CMD_DISABLED:
++ PRINTM(INFO, "SDIO clock is turned off\n");
++ ret = sbi_set_bus_clock(priv, FALSE);
++ break;
++ case CMD_ENABLED:
++ PRINTM(INFO, "SDIO clock is turned on\n");
++ ret = sbi_set_bus_clock(priv, TRUE);
++ break;
++ case CMD_GET: /* need an API in sdio.c to get STRPCL */
++ default:
++ ret = -EINVAL;
++ PRINTM(INFO, "sdioclock: wrong parameter\n");
++ break;
++ }
++ val = (int *) wrq->u.name;
++ *val = data;
++ }
++ break;
++ case WLANWMM_ENABLE:
++ ret = wlan_wmm_enable_ioctl(priv, wrq);
++ break;
++ case WLANNULLGEN:
++ ret = wlan_null_pkg_gen(priv, wrq);
++ /* enable/disable null pkg generation */
++ break;
++ case WLANADHOCCSET:
++ ret = wlan_set_coalescing_ioctl(priv, wrq);
++ break;
++ case WLAN_ADHOC_G_PROT:
++ ret = wlan_adhoc_g_protection(priv, wrq);
++ break;
++
++ }
++ break;
++
++ case WLAN_SETONEINT_GETONEINT:
++ switch (wrq->u.data.flags) {
++
++ case WLAN_WMM_QOSINFO:
++ {
++ int data;
++ if (wrq->u.data.length == 1) {
++ if (copy_from_user
++ (&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++ Adapter->wmm.qosinfo = (u8) data;
++ } else {
++ data = (int) Adapter->wmm.qosinfo;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ wrq->u.data.length = 1;
++ }
++ }
++ break;
++ case WLAN_LISTENINTRVL:
++ if (!wrq->u.data.length) {
++ int data;
++ PRINTM(INFO, "Get LocalListenInterval Value\n");
++#define GET_ONE_INT 1
++ data = Adapter->LocalListenInterval;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ wrq->u.data.length = GET_ONE_INT;
++ } else {
++ int data;
++ if (copy_from_user(&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ PRINTM(INFO, "Set LocalListenInterval = %d\n", data);
++#define MAX_U16_VAL 65535
++ if (data > MAX_U16_VAL) {
++ PRINTM(INFO, "Exceeds U16 value\n");
++ return -EINVAL;
++ }
++ Adapter->LocalListenInterval = data;
++ }
++ break;
++ case WLAN_FW_WAKEUP_METHOD:
++ ret = wlan_cmd_fw_wakeup_method(priv, wrq);
++ break;
++ case WLAN_NULLPKTINTERVAL:
++ ret = wlan_null_pkt_interval(priv, wrq);
++ break;
++ case WLAN_BCN_MISS_TIMEOUT:
++ ret = wlan_bcn_miss_timeout(priv, wrq);
++ break;
++ case WLAN_ADHOC_AWAKE_PERIOD:
++ ret = wlan_adhoc_awake_period(priv, wrq);
++ break;
++ case WLAN_LDO:
++ ret = wlan_ldo_config(priv, wrq);
++ break;
++ case WLAN_SDIO_MODE:
++ ret = wlan_sdio_mode(priv, wrq);
++ break;
++ case WLAN_RTS_CTS_CTRL:
++ ret = wlan_rts_cts_ctrl(priv, wrq);
++ break;
++ case WLAN_AUTODEEPSLEEP:
++ ret = wlan_auto_deep_sleep(priv, wrq);
++ break;
++ case WLAN_WAKEUP_MT:
++ if (wrq->u.data.length > 0)
++ Adapter->IntCounter++;
++ wake_up_interruptible(&priv->MainThread.waitQ);
++ break;
++ default:
++ ret = -EOPNOTSUPP;
++ break;
++ }
++ break;
++
++ case WLAN_SETONEINT_GETNONE:
++ /* The first 4 bytes of req->ifr_data is sub-ioctl number
++ * after 4 bytes sits the payload.
++ */
++ subcmd = wrq->u.data.flags; //from wpa_supplicant subcmd
++
++ if (!subcmd)
++ subcmd = (int) req->ifr_data; //from iwpriv subcmd
++
++ idata = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++
++ switch (subcmd) {
++ case WLAN_SUBCMD_SETRXANTENNA: /* SETRXANTENNA */
++ ret = SetRxAntenna(priv, idata);
++ break;
++ case WLAN_SUBCMD_SETTXANTENNA: /* SETTXANTENNA */
++ ret = SetTxAntenna(priv, idata);
++ break;
++
++ case WLANSETBCNAVG:
++ if (idata == 0)
++ Adapter->bcn_avg_factor = DEFAULT_BCN_AVG_FACTOR;
++ else if (idata > MAX_BCN_AVG_FACTOR || idata < MIN_BCN_AVG_FACTOR) {
++ PRINTM(MSG, "The value '%u' is out of the range (0-%u).\n",
++ idata, MAX_BCN_AVG_FACTOR);
++ return -EINVAL;
++ } else
++ Adapter->bcn_avg_factor = idata;
++ break;
++ case WLANSETDATAAVG:
++ if (idata == 0)
++ Adapter->data_avg_factor = DEFAULT_DATA_AVG_FACTOR;
++ else if (idata > MAX_DATA_AVG_FACTOR
++ || idata < MIN_DATA_AVG_FACTOR) {
++ PRINTM(MSG, "The value '%u' is out of the range (0-%u).\n",
++ idata, MAX_DATA_AVG_FACTOR);
++ return -EINVAL;
++ } else
++ Adapter->data_avg_factor = idata;
++ memset(Adapter->rawSNR, 0x00, sizeof(Adapter->rawSNR));
++ memset(Adapter->rawNF, 0x00, sizeof(Adapter->rawNF));
++ Adapter->nextSNRNF = 0;
++ Adapter->numSNRNF = 0;
++ break;
++ case WLANASSOCIATE:
++ ret = wlan_associate_to_table_idx(priv, idata);
++ break;
++
++ case WLANSETREGION:
++ ret = wlan_set_region(priv, (u16) idata);
++ break;
++
++ case WLAN_SET_LISTEN_INTERVAL:
++ Adapter->ListenInterval = (u16) idata;
++ break;
++
++ case WLAN_SET_MULTIPLE_DTIM:
++ ret = wlan_set_multiple_dtim_ioctl(priv, req);
++ break;
++
++ case WLANSETAUTHALG:
++ ret = wlan_setauthalg_ioctl(priv, req);
++ break;
++
++ case WLANSETENCRYPTIONMODE:
++ ret = wlan_setencryptionmode_ioctl(priv, req);
++ break;
++
++ default:
++ ret = -EOPNOTSUPP;
++ break;
++ }
++
++ break;
++
++ case WLAN_SETNONE_GETTWELVE_CHAR: /* Get Antenna settings */
++ /*
++ * We've not used IW_PRIV_TYPE_FIXED so sub-ioctl number is
++ * in flags of iwreq structure, otherwise it will be in
++ * mode member of iwreq structure.
++ */
++ switch ((int) wrq->u.data.flags) {
++ case WLAN_SUBCMD_GETRXANTENNA: /* Get Rx Antenna */
++ ret = wlan_subcmd_getrxantenna_ioctl(priv, req);
++ break;
++
++ case WLAN_SUBCMD_GETTXANTENNA: /* Get Tx Antenna */
++ ret = wlan_subcmd_gettxantenna_ioctl(priv, req);
++ break;
++
++ case WLAN_GET_TSF:
++ ret = wlan_get_tsf_ioctl(priv, wrq);
++ break;
++
++ case WLAN_WPS_SESSION:
++ ret = wlan_do_wps_session_ioctl(priv, wrq);
++ break;
++ }
++ break;
++
++ case WLANDEEPSLEEP:
++ ret = wlan_deepsleep_ioctl(priv, req);
++ break;
++
++ case WLANHOSTSLEEPCFG:
++ ret = wlan_do_hostsleepcfg_ioctl(priv, wrq);
++ break;
++
++ case WLAN_SET64CHAR_GET64CHAR:
++ switch ((int) wrq->u.data.flags) {
++
++ case WLANSLEEPPARAMS:
++ ret = wlan_sleep_params_ioctl(priv, wrq);
++ break;
++
++ case WLAN_BCA_TIMESHARE:
++ ret = wlan_bca_timeshare_ioctl(priv, wrq);
++ break;
++ case WLANSCAN_MODE:
++ PRINTM(INFO, "Scan Mode Ioctl\n");
++ ret = wlan_scan_mode_ioctl(priv, wrq);
++ break;
++
++ case WLAN_GET_ADHOC_STATUS:
++ ret = wlan_get_adhoc_status_ioctl(priv, wrq);
++ break;
++ case WLAN_SET_GEN_IE:
++ ret = wlan_set_gen_ie_ioctl(priv, wrq);
++ break;
++ case WLAN_GET_GEN_IE:
++ ret = wlan_get_gen_ie_ioctl(priv, wrq);
++ break;
++ case WLAN_WMM_QUEUE_STATUS:
++ ret = wlan_wmm_queue_status_ioctl(priv, wrq);
++ break;
++ }
++ break;
++
++ case WLAN_SETCONF_GETCONF:
++ PRINTM(INFO, "The WLAN_SETCONF_GETCONF=0x%x is %d\n",
++ WLAN_SETCONF_GETCONF, *(u8 *) req->ifr_data);
++ switch (*(u8 *) req->ifr_data) {
++ case CAL_DATA_EXT_CONFIG:
++ ret = wlan_do_caldata_ext_ioctl(priv, req);
++ break;
++ case BG_SCAN_CONFIG:
++ ret = wlan_do_bg_scan_config_ioctl(priv, req);
++ break;
++ }
++ break;
++
++ case WLAN_SETNONE_GETONEINT:
++ switch ((int) req->ifr_data) {
++ case WLANGETBCNAVG:
++ pdata = (int *) wrq->u.name;
++ *pdata = (int) Adapter->bcn_avg_factor;
++ break;
++
++ case WLANGETDATAAVG:
++ pdata = (int *) wrq->u.name;
++ *pdata = (int) Adapter->data_avg_factor;
++ break;
++
++ case WLANGETREGION:
++ pdata = (int *) wrq->u.name;
++ *pdata = (int) Adapter->RegionCode;
++ break;
++
++ case WLAN_GET_LISTEN_INTERVAL:
++ pdata = (int *) wrq->u.name;
++ *pdata = (int) Adapter->ListenInterval;
++ break;
++
++ case WLAN_GET_MULTIPLE_DTIM:
++ pdata = (int *) wrq->u.name;
++ *pdata = (int) Adapter->MultipleDtim;
++ break;
++ case WLAN_GET_TX_RATE:
++ ret = wlan_get_txrate_ioctl(priv, req);
++ break;
++ case WLANGETDTIM:
++ ret = wlan_get_dtim_ioctl(priv, req);
++ break;
++ default:
++ ret = -EOPNOTSUPP;
++
++ }
++
++ break;
++
++ case WLANGETLOG:
++ ret = wlan_do_getlog_ioctl(priv, wrq);
++ break;
++
++ case WLAN_SET_GET_SIXTEEN_INT:
++ switch ((int) wrq->u.data.flags) {
++ case WLAN_TPCCFG:
++ {
++ int data[5];
++ HostCmd_DS_802_11_TPC_CFG cfg;
++ memset(&cfg, 0, sizeof(cfg));
++ if ((wrq->u.data.length > 1) && (wrq->u.data.length != 5))
++ return WLAN_STATUS_FAILURE;
++
++ if (wrq->u.data.length == 0) {
++ cfg.Action = HostCmd_ACT_GEN_GET;
++ } else {
++ if (copy_from_user(data,
++ wrq->u.data.pointer,
++ sizeof(int) * 5)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ cfg.Action = HostCmd_ACT_GEN_SET;
++ cfg.Enable = data[0];
++ cfg.UseSNR = data[1];
++#define TPC_DATA_NO_CHANG 0x7f
++ if (wrq->u.data.length == 1) {
++ cfg.P0 = TPC_DATA_NO_CHANG;
++ cfg.P1 = TPC_DATA_NO_CHANG;
++ cfg.P2 = TPC_DATA_NO_CHANG;
++ } else {
++ cfg.P0 = data[2];
++ cfg.P1 = data[3];
++ cfg.P2 = data[4];
++ }
++ }
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_TPC_CFG, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ (void *) &cfg);
++
++ data[0] = cfg.Enable;
++ data[1] = cfg.UseSNR;
++ data[2] = cfg.P0;
++ data[3] = cfg.P1;
++ data[4] = cfg.P2;
++ if (copy_to_user(wrq->u.data.pointer, data, sizeof(int) * 5)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ wrq->u.data.length = 5;
++ }
++ break;
++
++ case WLAN_SCANPROBES:
++ {
++ int data;
++ if (wrq->u.data.length > 0) {
++ if (copy_from_user
++ (&data, wrq->u.data.pointer, sizeof(int))) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ Adapter->ScanProbes = data;
++ } else {
++ data = Adapter->ScanProbes;
++ if (copy_to_user(wrq->u.data.pointer, &data, sizeof(int))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++ }
++ wrq->u.data.length = 1;
++ }
++ break;
++ case WLAN_LED_GPIO_CTRL:
++ {
++ int i;
++ int data[MAX_LEDS * 2];
++ HostCmd_DS_802_11_LED_CTRL ctrl;
++ MrvlIEtypes_LedGpio_t *gpio;
++
++ gpio = (MrvlIEtypes_LedGpio_t *) & ctrl.LedGpio;
++
++ if ((wrq->u.data.length > MAX_LEDS * 2) ||
++ (wrq->u.data.length % 2) != 0) {
++ PRINTM(MSG, "invalid ledgpio parameters\n");
++ return -EINVAL;
++ }
++
++ memset(&ctrl, 0, sizeof(ctrl));
++ if (wrq->u.data.length == 0) {
++ ctrl.Action = HostCmd_ACT_GEN_GET;
++ } else {
++ if (copy_from_user(data, wrq->u.data.pointer,
++ sizeof(int) * wrq->u.data.length)) {
++ PRINTM(INFO, "Copy from user failed\n");
++ return -EFAULT;
++ }
++
++ ctrl.Action = HostCmd_ACT_GEN_SET;
++ ctrl.LedNums = 0;
++ gpio->Header.Type = TLV_TYPE_LED_GPIO;
++ gpio->Header.Len = wrq->u.data.length;
++ for (i = 0; i < wrq->u.data.length; i += 2) {
++ gpio->LedGpio[i / 2].LedNum = data[i];
++ gpio->LedGpio[i / 2].GpioNum = data[i + 1];
++ }
++ }
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_LED_CONTROL, 0,
++ HostCmd_OPTION_WAITFORRSP,
++ 0, (void *) &ctrl);
++
++ for (i = 0; i < gpio->Header.Len; i += 2) {
++ data[i] = gpio->LedGpio[i / 2].LedNum;
++ data[i + 1] = gpio->LedGpio[i / 2].GpioNum;
++ }
++ if (copy_to_user(wrq->u.data.pointer, data,
++ sizeof(int) * gpio->Header.Len)) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ wrq->u.data.length = gpio->Header.Len;
++ }
++ break;
++ case WLAN_SLEEP_PERIOD:
++ ret = wlan_sleep_period(priv, wrq);
++ break;
++ case WLAN_ADAPT_RATESET:
++ ret = wlan_adapt_rateset(priv, wrq);
++ break;
++ case WLAN_INACTIVITY_TIMEOUT:
++ ret = wlan_inactivity_timeout(priv, wrq);
++ break;
++ case WLANSNR:
++ ret = wlan_get_snr(priv, wrq);
++ break;
++ case WLAN_GET_RATE:
++ ret = wlan_getrate_ioctl(priv, wrq);
++ break;
++ case WLAN_GET_RXINFO:
++ ret = wlan_get_rxinfo(priv, wrq);
++ break;
++ case WLAN_SET_ATIM_WINDOW:
++ ret = wlan_ATIM_Window(priv, wrq);
++ break;
++ case WLAN_BEACON_INTERVAL:
++ ret = wlan_beacon_interval(priv, wrq);
++ break;
++ case WLAN_SDIO_PULL_CTRL:
++ ret = wlan_sdio_pull_ctrl(priv, wrq);
++ break;
++ case WLAN_SCAN_TIME:
++ ret = wlan_scan_time(priv, wrq);
++ break;
++ case WLAN_DATA_SUBSCRIBE_EVENT:
++ ret = wlan_data_subscribe_event(priv, wrq);
++ break;
++ case WLAN_TXCONTROL:
++ ret = wlan_txcontrol(priv, wrq);
++ break;
++ case WLANHSCFG:
++ ret = wlan_hscfg_ioctl(priv, wrq);
++ break;
++ case WLANHSSETPARA:
++ ret = wlan_hssetpara_ioctl(priv, wrq);
++ break;
++#ifdef DEBUG_LEVEL1
++ case WLAN_DRV_DBG:
++ ret = wlan_drv_dbg(priv, wrq);
++ break;
++#endif
++ }
++ break;
++
++ case WLAN_SET_GET_2K:
++ switch ((int) wrq->u.data.flags) {
++ case WLAN_SET_USER_SCAN:
++ ret = wlan_set_user_scan_ioctl(priv, wrq);
++ break;
++ case WLAN_GET_SCAN_TABLE:
++ ret = wlan_get_scan_table_ioctl(priv, wrq);
++ break;
++ case WLAN_SET_MRVL_TLV:
++ ret = wlan_set_mrvl_tlv_ioctl(priv, wrq);
++ break;
++ case WLAN_GET_ASSOC_RSP:
++ ret = wlan_get_assoc_rsp_ioctl(priv, wrq);
++ break;
++ case WLAN_ADDTS_REQ:
++ ret = wlan_wmm_addts_req_ioctl(priv, wrq);
++ break;
++ case WLAN_DELTS_REQ:
++ ret = wlan_wmm_delts_req_ioctl(priv, wrq);
++ break;
++ case WLAN_QUEUE_CONFIG:
++ ret = wlan_wmm_queue_config_ioctl(priv, wrq);
++ break;
++ case WLAN_QUEUE_STATS:
++ ret = wlan_wmm_queue_stats_ioctl(priv, wrq);
++ break;
++ case WLAN_TX_PKT_STATS:
++ ret = wlan_tx_pkt_stats_ioctl(priv, wrq);
++ break;
++ case WLAN_GET_CFP_TABLE:
++ ret = wlan_get_cfp_table_ioctl(priv, wrq);
++ break;
++ default:
++ ret = -EOPNOTSUPP;
++ }
++ break;
++
++ default:
++ ret = -EINVAL;
++ break;
++ }
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get wireless statistics
++ *
++ * NOTE: If PrepareAndSendCommand() with wait option is issued
++ * in this function, a kernel dump (scheduling while atomic)
++ * issue may happen on some versions of kernels.
++ *
++ * @param dev A pointer to net_device structure
++ * @return A pointer to iw_statistics buf
++ */
++struct iw_statistics *
++wlan_get_wireless_stats(struct net_device *dev)
++{
++ enum {
++ POOR = 30,
++ FAIR = 60,
++ GOOD = 80,
++ VERY_GOOD = 90,
++ EXCELLENT = 95,
++ PERFECT = 100
++ };
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++ u8 rssi;
++ u32 rssi_qual;
++ u32 tx_qual;
++ u32 quality = 0;
++ u32 tx_retries;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return NULL;
++ }
++
++ priv->wstats.status = Adapter->InfrastructureMode;
++ priv->wstats.discard.retries = priv->stats.tx_errors;
++
++ priv->wstats.qual.level =
++ CAL_RSSI(Adapter->SNR[TYPE_BEACON][TYPE_NOAVG],
++ Adapter->NF[TYPE_BEACON][TYPE_NOAVG]);
++ priv->wstats.qual.noise = CAL_NF(Adapter->NF[TYPE_BEACON][TYPE_NOAVG]);
++ if (Adapter->NF[TYPE_BEACON][TYPE_NOAVG] == 0
++ && Adapter->MediaConnectStatus == WlanMediaStateConnected)
++ priv->wstats.qual.noise = MRVDRV_NF_DEFAULT_SCAN_VALUE;
++ else
++ priv->wstats.qual.noise =
++ CAL_NF(Adapter->NF[TYPE_BEACON][TYPE_NOAVG]);
++
++ rssi = priv->wstats.qual.level - priv->wstats.qual.noise;
++ if (rssi < 15)
++ rssi_qual = rssi * POOR / 10;
++ else if (rssi < 20)
++ rssi_qual = (rssi - 15) * (FAIR - POOR) / 5 + POOR;
++ else if (rssi < 30)
++ rssi_qual = (rssi - 20) * (GOOD - FAIR) / 5 + FAIR;
++ else if (rssi < 40)
++ rssi_qual = (rssi - 30) * (VERY_GOOD - GOOD) / 10 + GOOD;
++ else
++ rssi_qual = (rssi - 40) * (PERFECT - VERY_GOOD) / 10 + VERY_GOOD;
++ quality = rssi_qual;
++
++ tx_retries = Adapter->LogMsg.retry;
++
++ if (tx_retries > 75)
++ tx_qual = (90 - tx_retries) * POOR / 15;
++ else if (tx_retries > 70)
++ tx_qual = (75 - tx_retries) * (FAIR - POOR) / 5 + POOR;
++ else if (tx_retries > 65)
++ tx_qual = (70 - tx_retries) * (GOOD - FAIR) / 5 + FAIR;
++ else if (tx_retries > 50)
++ tx_qual = (65 - tx_retries) * (VERY_GOOD - GOOD) / 15 + GOOD;
++ else
++ tx_qual = (50 - tx_retries) * (PERFECT - VERY_GOOD) / 50 + VERY_GOOD;
++ quality = min(quality, tx_qual);
++
++ priv->wstats.qual.qual = min_t(u8, quality, 100);
++ priv->wstats.qual.updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM;
++
++ PRINTM(INFO, "Signal Level = %#x\n", priv->wstats.qual.level);
++ PRINTM(INFO, "Noise = %#x\n", priv->wstats.qual.noise);
++
++ /* send RSSI command to get beacon RSSI/NF, valid only if associated */
++ PrepareAndSendCommand(priv, HostCmd_CMD_802_11_RSSI, 0, 0, 0, NULL);
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_GET_LOG, 0,
++ 0, 0, NULL);
++
++ if (!ret) {
++ priv->wstats.discard.code = 0;
++ priv->wstats.discard.fragment = Adapter->LogMsg.fcserror;
++ priv->wstats.discard.retries = Adapter->LogMsg.retry;
++ priv->wstats.discard.misc = Adapter->LogMsg.ackfailure;
++ }
++
++ return &priv->wstats;
++}
++
++static int
++wlan_set_coalescing_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ int data;
++ int *val;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++
++ switch (data) {
++ case CMD_DISABLED:
++ case CMD_ENABLED:
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_IBSS_COALESCING_STATUS,
++ HostCmd_ACT_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, &data);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ break;
++
++ case CMD_GET:
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_IBSS_COALESCING_STATUS,
++ HostCmd_ACT_GET,
++ HostCmd_OPTION_WAITFORRSP, 0, &data);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ val = (int *) wrq->u.name;
++ *val = data;
++
++ LEAVE();
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set frequency
++ *
++ * @param priv A pointer to wlan_private structure
++ * @param info A pointer to iw_request_info structure
++ * @param fwrq A pointer to iw_freq structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS--success, otherwise--fail
++ */
++int
++wlan_set_freq(struct net_device *dev, struct iw_request_info *info,
++ struct iw_freq *fwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int rc = -EINPROGRESS; /* Call commit handler */
++ CHANNEL_FREQ_POWER *cfp;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++ if (Adapter->InfrastructureMode != Wlan802_11IBSS)
++ return -EOPNOTSUPP;
++
++ /*
++ * If setting by frequency, convert to a channel
++ */
++ if (fwrq->e == 1) {
++
++ long f = fwrq->m / 100000;
++ int c = 0;
++
++ cfp = find_cfp_by_band_and_freq(Adapter, 0, f);
++ if (!cfp) {
++ PRINTM(INFO, "Invalid freq=%ld\n", f);
++ return -EINVAL;
++ }
++
++ c = (int) cfp->Channel;
++
++ if (c < 0)
++ return -EINVAL;
++
++ fwrq->e = 0;
++ fwrq->m = c;
++ }
++
++ /*
++ * Setting by channel number
++ */
++ if (fwrq->m > 1000 || fwrq->e > 0) {
++ rc = -EOPNOTSUPP;
++ } else {
++ int channel = fwrq->m;
++
++ cfp = find_cfp_by_band_and_channel(Adapter, 0, (u16) channel);
++ if (!cfp) {
++ rc = -EINVAL;
++ } else {
++ rc = ChangeAdhocChannel(priv, channel);
++ /* If station is WEP enabled, send the
++ * command to set WEP in firmware
++ */
++ if (Adapter->SecInfo.WEPStatus == Wlan802_11WEPEnabled) {
++ PRINTM(INFO, "set_freq: WEP Enabled\n");
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SET_WEP,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_ADD_WEP, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ Adapter->CurrentPacketFilter |= HostCmd_ACT_MAC_WEP_ENABLE;
++
++ PrepareAndSendCommand(priv,
++ HostCmd_CMD_MAC_CONTROL,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ 0, &Adapter->CurrentPacketFilter);
++ }
++ }
++ }
++
++ LEAVE();
++ return rc;
++}
++
++/**
++ * @brief Set Deep Sleep
++ *
++ * @param adapter A pointer to wlan_private structure
++ * @param bDeepSleep TRUE--enalbe deepsleep, FALSE--disable deepsleep
++ * @return WLAN_STATUS_SUCCESS-success, otherwise fail
++ */
++
++int
++SetDeepSleep(wlan_private * priv, BOOLEAN bDeepSleep)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_adapter *Adapter = priv->adapter;
++
++ ENTER();
++
++ if (bDeepSleep == TRUE) {
++ if (Adapter->IsDeepSleep != TRUE) {
++ PRINTM(INFO, "Deep Sleep: sleep\n");
++
++ // note: the command could be queued and executed later
++ // if there is command in prigressing.
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_DEEP_SLEEP, 0,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ wmm_stop_queue(priv);
++ os_stop_queue(priv);
++ os_carrier_off(priv);
++ }
++ } else {
++ if (Adapter->IsDeepSleep == TRUE) {
++ PRINTM(CMND, "Deep Sleep: wakeup\n");
++
++ if (Adapter->IntCounterSaved) {
++ Adapter->IntCounter = Adapter->IntCounterSaved;
++ Adapter->IntCounterSaved = 0;
++ }
++
++ if (sbi_exit_deep_sleep(priv))
++ PRINTM(ERROR, "Deep Sleep : wakeup failed\n");
++
++ if (Adapter->IsDeepSleep == TRUE) {
++
++ if (os_wait_interruptible_timeout(Adapter->ds_awake_q,
++ !Adapter->IsDeepSleep,
++ MRVDRV_DEEP_SLEEP_EXIT_TIMEOUT)
++ == 0) {
++ PRINTM(MSG, "ds_awake_q: timer expired\n");
++ }
++ }
++
++ if (Adapter->IntCounter)
++ wake_up_interruptible(&priv->MainThread.waitQ);
++ }
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief use index to get the data rate
++ *
++ * @param index The index of data rate
++ * @return data rate or 0
++ */
++u32
++index_to_data_rate(u8 index)
++{
++ if (index >= sizeof(WlanDataRates))
++ index = 0;
++
++ return WlanDataRates[index];
++}
++
++/**
++ * @brief use rate to get the index
++ *
++ * @param rate data rate
++ * @return index or 0
++ */
++u8
++data_rate_to_index(u32 rate)
++{
++ u8 *ptr;
++
++ if (rate)
++ if ((ptr = wlan_memchr(WlanDataRates, (u8) rate,
++ sizeof(WlanDataRates))))
++ return (ptr - WlanDataRates);
++
++ return 0;
++}
++
++/**
++ * @brief set data rate
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++
++int
++wlan_set_rate(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ u32 data_rate;
++ int ret = WLAN_STATUS_SUCCESS;
++ WLAN_802_11_RATES rates;
++ u8 *rate;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ PRINTM(INFO, "Vwrq->value = %d\n", vwrq->value);
++
++ if (vwrq->value == -1) {
++ Adapter->DataRate = 0;
++ Adapter->RateBitmap = 0;
++ memset(rates, 0, sizeof(rates));
++ get_active_data_rates(Adapter, rates);
++ rate = rates;
++ while (*rate) {
++ Adapter->RateBitmap |= 1 << (data_rate_to_index(*rate & 0x7f));
++ rate++;
++ }
++ Adapter->Is_DataRate_Auto = TRUE;
++ } else {
++ if ((vwrq->value % 500000)) {
++ return -EINVAL;
++ }
++
++ data_rate = vwrq->value / 500000;
++
++ memset(rates, 0, sizeof(rates));
++ get_active_data_rates(Adapter, rates);
++ rate = rates;
++ while (*rate) {
++ PRINTM(INFO, "Rate=0x%X Wanted=0x%X\n", *rate, data_rate);
++ if ((*rate & 0x7f) == (data_rate & 0x7f))
++ break;
++ rate++;
++ }
++ if (!*rate) {
++ PRINTM(MSG, "The fixed data rate 0x%X is out "
++ "of range.\n", data_rate);
++ return -EINVAL;
++ }
++
++ Adapter->DataRate = data_rate;
++ Adapter->RateBitmap = 1 << (data_rate_to_index(Adapter->DataRate));
++ Adapter->Is_DataRate_Auto = FALSE;
++ }
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RATE_ADAPT_RATESET,
++ HostCmd_ACT_GEN_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, NULL);
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief get data rate
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_get_rate(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ if (Adapter->Is_DataRate_Auto)
++ vwrq->fixed = 0;
++ else
++ vwrq->fixed = 1;
++
++ Adapter->TxRate = 0;
++
++ ret = PrepareAndSendCommand(priv, HostCmd_CMD_802_11_TX_RATE_QUERY,
++ HostCmd_ACT_GET, HostCmd_OPTION_WAITFORRSP,
++ 0, NULL);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ vwrq->value = index_to_data_rate(Adapter->TxRate) * 500000;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief set wireless mode
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_set_mode(struct net_device *dev,
++ struct iw_request_info *info, u32 * uwrq, char *extra)
++{
++ int ret = WLAN_STATUS_SUCCESS;
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++
++ WLAN_802_11_NETWORK_INFRASTRUCTURE WantedMode;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ switch (*uwrq) {
++ case IW_MODE_ADHOC:
++ PRINTM(INFO, "Wanted Mode is ad-hoc: current DataRate=%#x\n",
++ Adapter->DataRate);
++ WantedMode = Wlan802_11IBSS;
++ break;
++
++ case IW_MODE_INFRA:
++ PRINTM(INFO, "Wanted Mode is Infrastructure\n");
++ WantedMode = Wlan802_11Infrastructure;
++ break;
++
++ case IW_MODE_AUTO:
++ PRINTM(INFO, "Wanted Mode is Auto\n");
++ WantedMode = Wlan802_11AutoUnknown;
++ break;
++
++ default:
++ PRINTM(INFO, "Wanted Mode is Unknown: 0x%x\n", *uwrq);
++ return -EINVAL;
++ }
++
++ if (Adapter->InfrastructureMode == WantedMode ||
++ WantedMode == Wlan802_11AutoUnknown) {
++ PRINTM(INFO, "Already set to required mode! No change!\n");
++
++ Adapter->InfrastructureMode = WantedMode;
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure) {
++ if (Adapter->PSState != PS_STATE_FULL_POWER) {
++ PSWakeup(priv, HostCmd_OPTION_WAITFORRSP);
++ }
++ Adapter->PSMode = Wlan802_11PowerModeCAM;
++ }
++
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ if (Adapter->InfrastructureMode == Wlan802_11Infrastructure) {
++ ret = SendDeauthentication(priv);
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ } else if (Adapter->InfrastructureMode == Wlan802_11IBSS) {
++ /* If current mode is Adhoc, clean stale information */
++ ret = StopAdhocNetwork(priv);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++ }
++ }
++
++ Adapter->SecInfo.AuthenticationMode = Wlan802_11AuthModeOpen;
++
++ Adapter->InfrastructureMode = WantedMode;
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_SNMP_MIB,
++ 0, HostCmd_OPTION_WAITFORRSP,
++ OID_802_11_INFRASTRUCTURE_MODE, NULL);
++
++ if (ret) {
++ LEAVE();
++ return ret;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Set Encryption key
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++static int
++wlan_set_encode(struct net_device *dev,
++ struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++
++ WLAN_802_11_KEY *pKey = NULL;
++ int retval = -EINVAL;
++
++ ENTER();
++
++ if (dwrq->length > MAX_WEP_KEY_SIZE) {
++ pKey = (WLAN_802_11_KEY *) extra;
++ if (pKey->KeyLength <= MAX_WEP_KEY_SIZE) {
++ //dynamic WEP
++ dwrq->length = pKey->KeyLength;
++ dwrq->flags = pKey->KeyIndex + 1;
++ retval = wlan_set_encode_nonwpa(dev, info, dwrq,
++ pKey->KeyMaterial);
++ } else {
++ //WPA
++ retval = wlan_set_encode_wpa(dev, info, dwrq, extra);
++ }
++ } else {
++ //static WEP
++ PRINTM(INFO, "Setting WEP\n");
++ retval = wlan_set_encode_nonwpa(dev, info, dwrq, extra);
++ }
++
++ return retval;
++}
++
++/**
++ * @brief set tx power
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_set_txpow(struct net_device *dev, struct iw_request_info *info,
++ struct iw_param *vwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int ret = WLAN_STATUS_SUCCESS;
++
++ u16 dbm;
++
++ ENTER();
++
++ if (!Is_Command_Allowed(priv)) {
++ PRINTM(MSG, "%s: not allowed\n", __FUNCTION__);
++ return -EBUSY;
++ }
++
++ if (vwrq->disabled) {
++ wlan_radio_ioctl(priv, RADIO_OFF);
++ return WLAN_STATUS_SUCCESS;
++ }
++
++ wlan_radio_ioctl(priv, RADIO_ON);
++
++#if WIRELESS_EXT > 14
++ if ((vwrq->flags & IW_TXPOW_TYPE) == IW_TXPOW_MWATT) {
++ dbm = (u16) mw_to_dbm(vwrq->value);
++ } else
++#endif
++ dbm = (u16) vwrq->value;
++
++ if ((dbm < Adapter->MinTxPowerLevel) || (dbm > Adapter->MaxTxPowerLevel)) {
++ PRINTM(MSG,
++ "The set txpower value %d dBm is out of range (%d dBm-%d dBm)!\n",
++ dbm, Adapter->MinTxPowerLevel, Adapter->MaxTxPowerLevel);
++ LEAVE();
++ return -EINVAL;
++ }
++
++ /* auto tx power control */
++
++ if (vwrq->fixed == 0)
++ dbm = 0xffff;
++
++ PRINTM(INFO, "<1>TXPOWER SET %d dbm.\n", dbm);
++
++ ret = PrepareAndSendCommand(priv,
++ HostCmd_CMD_802_11_RF_TX_POWER,
++ HostCmd_ACT_GEN_SET,
++ HostCmd_OPTION_WAITFORRSP, 0, (void *) &dbm);
++
++ LEAVE();
++ return ret;
++}
++
++/**
++ * @brief Get current essid
++ *
++ * @param dev A pointer to net_device structure
++ * @param info A pointer to iw_request_info structure
++ * @param vwrq A pointer to iw_param structure
++ * @param extra A pointer to extra data buf
++ * @return WLAN_STATUS_SUCCESS --success, otherwise fail
++ */
++int
++wlan_get_essid(struct net_device *dev, struct iw_request_info *info,
++ struct iw_point *dwrq, char *extra)
++{
++ wlan_private *priv = dev->priv;
++ wlan_adapter *Adapter = priv->adapter;
++ int tblIdx = -1;
++ BSSDescriptor_t *pBSSDesc;
++
++ ENTER();
++
++ pBSSDesc = &Adapter->CurBssParams.BSSDescriptor;
++
++ /*
++ * Get the current SSID
++ */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++
++ tblIdx = FindSSIDInList(Adapter,
++ &pBSSDesc->Ssid,
++ pBSSDesc->MacAddress,
++ Adapter->InfrastructureMode);
++
++ memcpy(extra, &pBSSDesc->Ssid.Ssid, pBSSDesc->Ssid.SsidLength);
++ extra[pBSSDesc->Ssid.SsidLength] = '\0';
++
++ } else {
++ memset(extra, 0, 32);
++ extra[pBSSDesc->Ssid.SsidLength] = '\0';
++ }
++
++ /* To make the driver backward compatible with WPA supplicant v0.2.4 */
++ if (dwrq->length == 32) {
++ dwrq->length = MIN(pBSSDesc->Ssid.SsidLength, IW_ESSID_MAX_SIZE);
++ } else {
++#if WIRELESS_EXT > 20
++ dwrq->length = pBSSDesc->Ssid.SsidLength;
++#else
++ dwrq->length = pBSSDesc->Ssid.SsidLength + 1;
++#endif
++ }
++
++ /* If the current network is in the table, return the table index */
++ if (tblIdx >= 0) {
++ dwrq->flags = (tblIdx + 1) & IW_ENCODE_INDEX;
++ } else {
++ dwrq->flags = 1;
++ }
++
++ LEAVE();
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Get version
++ *
++ * @param adapter A pointer to wlan_adapter structure
++ * @param version A pointer to version buffer
++ * @param maxlen max length of version buffer
++ * @return NA
++ */
++void
++get_version(wlan_adapter * adapter, char *version, int maxlen)
++{
++ union
++ {
++ u32 l;
++ u8 c[4];
++ } ver;
++ char fwver[32];
++
++ ver.l = adapter->FWReleaseNumber;
++ if (ver.c[3] == 0)
++ sprintf(fwver, "%u.%u.%u", ver.c[2], ver.c[1], ver.c[0]);
++ else
++ sprintf(fwver, "%u.%u.%u.p%u",
++ ver.c[2], ver.c[1], ver.c[0], ver.c[3]);
++
++ snprintf(version, maxlen, driver_version, fwver);
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_wext.h b/drivers/net/wireless/marvell8686/wlan_wext.h
+new file mode 100644
+index 0000000..d1d40d1
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_wext.h
+@@ -0,0 +1,406 @@
++/** @file wlan_wext.h
++ * @brief This file contains definition for IOCTL call.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
++ */
++/********************************************************
++Change log:
++ 10/11/05: Add Doxygen format comments
++ 12/19/05: Correct a typo in structure _wlan_ioctl_wmm_tspec
++ 01/11/06: Conditionalize new scan/join ioctls
++ 04/10/06: Add hostcmd generic API
++ 04/18/06: Remove old Subscrive Event and add new Subscribe Event
++ implementation through generic hostcmd API
++ 06/08/06: Add definitions of custom events
++ 08/29/06: Add ledgpio private command
++********************************************************/
++
++#ifndef _WLAN_WEXT_H_
++#define _WLAN_WEXT_H_
++
++#include "wlan_types.h"
++
++#define SUBCMD_OFFSET 4
++/** PRIVATE CMD ID */
++#define WLANIOCTL 0x8BE0
++
++#define WLANSETWPAIE (WLANIOCTL + 0)
++#define WLANCISDUMP (WLANIOCTL + 1)
++#ifdef MFG_CMD_SUPPORT
++#define WLANMANFCMD (WLANIOCTL + 2)
++#endif
++#define WLANREGRDWR (WLANIOCTL + 3)
++#define MAX_EEPROM_DATA 256
++#define WLANHOSTCMD (WLANIOCTL + 4)
++
++#define WLANHOSTSLEEPCFG (WLANIOCTL + 5)
++#define WLANARPFILTER (WLANIOCTL + 6)
++
++#define WLAN_SETINT_GETINT (WLANIOCTL + 7)
++#define WLANNF 1
++#define WLANRSSI 2
++#define WLANBGSCAN 4
++#define WLANENABLE11D 5
++#define WLANADHOCGRATE 6
++#define WLANSDIOCLOCK 7
++#define WLANWMM_ENABLE 8
++#define WLANNULLGEN 10
++#define WLANADHOCCSET 11
++#define WLAN_ADHOC_G_PROT 12
++
++#define WLAN_SETNONE_GETNONE (WLANIOCTL + 8)
++#define WLANDEAUTH 1
++#define WLANRADIOON 2
++#define WLANRADIOOFF 3
++#define WLANREMOVEADHOCAES 4
++#define WLANADHOCSTOP 5
++#ifdef REASSOCIATION
++#define WLANREASSOCIATIONAUTO 8
++#define WLANREASSOCIATIONUSER 9
++#endif /* REASSOCIATION */
++#define WLANWLANIDLEON 10
++#define WLANWLANIDLEOFF 11
++
++#define WLANGETLOG (WLANIOCTL + 9)
++#define WLAN_SETCONF_GETCONF (WLANIOCTL + 10)
++
++#define BG_SCAN_CONFIG 1
++#define CAL_DATA_EXT_CONFIG 2
++
++#define WLANSCAN_TYPE (WLANIOCTL + 11)
++
++#define WLAN_SET_GET_2K (WLANIOCTL + 13)
++#define WLAN_SET_USER_SCAN 1
++#define WLAN_GET_SCAN_TABLE 2
++#define WLAN_SET_MRVL_TLV 3
++#define WLAN_GET_ASSOC_RSP 4
++#define WLAN_ADDTS_REQ 5
++#define WLAN_DELTS_REQ 6
++#define WLAN_QUEUE_CONFIG 7
++#define WLAN_QUEUE_STATS 8
++#define WLAN_GET_CFP_TABLE 9
++#define WLAN_TX_PKT_STATS 12
++
++#define WLAN_SETNONE_GETONEINT (WLANIOCTL + 15)
++#define WLANGETREGION 1
++#define WLAN_GET_LISTEN_INTERVAL 2
++#define WLAN_GET_MULTIPLE_DTIM 3
++#define WLAN_GET_TX_RATE 4
++#define WLANGETBCNAVG 5
++#define WLANGETDATAAVG 6
++#define WLANGETDTIM 7
++
++#define WLAN_SETNONE_GETTWELVE_CHAR (WLANIOCTL + 19)
++#define WLAN_SUBCMD_GETRXANTENNA 1
++#define WLAN_SUBCMD_GETTXANTENNA 2
++#define WLAN_GET_TSF 3
++#define WLAN_WPS_SESSION 4
++
++#define WLAN_SETWORDCHAR_GETNONE (WLANIOCTL + 20)
++#define WLANSETADHOCAES 1
++
++#define WLAN_SETONEINT_GETWORDCHAR (WLANIOCTL + 21)
++#define WLANGETADHOCAES 1
++#define WLANVERSION 2
++#define WLANVEREXT 3
++
++#define WLAN_SETONEINT_GETONEINT (WLANIOCTL + 23)
++#define WLAN_WMM_QOSINFO 2
++#define WLAN_LISTENINTRVL 3
++#define WLAN_FW_WAKEUP_METHOD 4
++#define WAKEUP_FW_UNCHANGED 0
++#define WAKEUP_FW_THRU_INTERFACE 1
++#define WAKEUP_FW_THRU_GPIO 2
++
++#define WLAN_NULLPKTINTERVAL 5
++#define WLAN_BCN_MISS_TIMEOUT 6
++#define WLAN_ADHOC_AWAKE_PERIOD 7
++#define WLAN_LDO 8
++#define WLAN_SDIO_MODE 9
++#define WLAN_AUTODEEPSLEEP 12
++#define WLAN_WAKEUP_MT 13
++
++#define WLAN_RTS_CTS_CTRL 14
++
++#define WLAN_SETONEINT_GETNONE (WLANIOCTL + 24)
++#define WLAN_SUBCMD_SETRXANTENNA 1
++#define WLAN_SUBCMD_SETTXANTENNA 2
++#define WLANSETAUTHALG 4
++#define WLANSETENCRYPTIONMODE 5
++#define WLANSETREGION 6
++#define WLAN_SET_LISTEN_INTERVAL 7
++
++#define WLAN_SET_MULTIPLE_DTIM 8
++
++#define WLANSETBCNAVG 9
++#define WLANSETDATAAVG 10
++#define WLANASSOCIATE 11
++
++#define WLAN_SET64CHAR_GET64CHAR (WLANIOCTL + 25)
++#define WLANSLEEPPARAMS 2
++#define WLAN_BCA_TIMESHARE 3
++#define WLANSCAN_MODE 6
++
++#define WLAN_GET_ADHOC_STATUS 9
++
++#define WLAN_SET_GEN_IE 10
++#define WLAN_GET_GEN_IE 11
++
++#define WLAN_WMM_QUEUE_STATUS 13
++
++#define WLANEXTSCAN (WLANIOCTL + 26)
++#define WLANDEEPSLEEP (WLANIOCTL + 27)
++#define DEEP_SLEEP_ENABLE 1
++#define DEEP_SLEEP_DISABLE 0
++
++#define WLAN_SET_GET_SIXTEEN_INT (WLANIOCTL + 29)
++#define WLAN_TPCCFG 1
++#define WLAN_LED_GPIO_CTRL 5
++#define WLAN_SCANPROBES 6
++#define WLAN_SLEEP_PERIOD 7
++#define WLAN_ADAPT_RATESET 8
++#define WLAN_INACTIVITY_TIMEOUT 9
++#define WLANSNR 10
++#define WLAN_GET_RATE 11
++#define WLAN_GET_RXINFO 12
++#define WLAN_SET_ATIM_WINDOW 13
++#define WLAN_BEACON_INTERVAL 14
++#define WLAN_SDIO_PULL_CTRL 15
++#define WLAN_SCAN_TIME 16
++#define WLAN_DATA_SUBSCRIBE_EVENT 18
++#define WLAN_TXCONTROL 19
++#define WLANHSCFG 21
++#define WLANHSSETPARA 22
++#ifdef DEBUG_LEVEL1
++#define WLAN_DRV_DBG 25
++#endif
++
++#define WLANCMD52RDWR (WLANIOCTL + 30)
++#define WLANCMD53RDWR (WLANIOCTL + 31)
++#define CMD53BUFLEN 32
++
++#define REG_MAC 0x19
++#define REG_BBP 0x1a
++#define REG_RF 0x1b
++#define REG_EEPROM 0x59
++
++#define CMD_DISABLED 0
++#define CMD_ENABLED 1
++#define CMD_GET 2
++#define SKIP_CMDNUM 4
++#define SKIP_TYPE 1
++#define SKIP_SIZE 2
++#define SKIP_ACTION 2
++#define SKIP_TYPE_SIZE (SKIP_TYPE + SKIP_SIZE)
++#define SKIP_TYPE_ACTION (SKIP_TYPE + SKIP_ACTION)
++
++#define MAX_SETGET_CONF_SIZE 2000 /* less than MRVDRV_SIZE_OF_CMD_BUFFER */
++#define MAX_SETGET_CONF_CMD_LEN (MAX_SETGET_CONF_SIZE - SKIP_CMDNUM)
++
++/* define custom events */
++#define CUS_EVT_HS_ACTIVATED "HS_ACTIVATED "
++#define CUS_EVT_HS_DEACTIVATED "HS_DEACTIVATED "
++#define CUS_EVT_HS_GPIO_INT "HS_GPIO_INT "
++#define CUS_EVT_BEACON_RSSI_LOW "EVENT=BEACON_RSSI_LOW"
++#define CUS_EVT_BEACON_SNR_LOW "EVENT=BEACON_SNR_LOW"
++#define CUS_EVT_BEACON_RSSI_HIGH "EVENT=BEACON_RSSI_HIGH"
++#define CUS_EVT_BEACON_SNR_HIGH "EVENT=BEACON_SNR_HIGH"
++#define CUS_EVT_MAX_FAIL "EVENT=MAX_FAIL"
++#define CUS_EVT_MLME_MIC_ERR_UNI "MLME-MICHAELMICFAILURE.indication unicast "
++#define CUS_EVT_MLME_MIC_ERR_MUL "MLME-MICHAELMICFAILURE.indication multicast "
++
++#define CUS_EVT_DATA_RSSI_LOW "EVENT=DATA_RSSI_LOW"
++#define CUS_EVT_DATA_SNR_LOW "EVENT=DATA_SNR_LOW"
++#define CUS_EVT_DATA_RSSI_HIGH "EVENT=DATA_RSSI_HIGH"
++#define CUS_EVT_DATA_SNR_HIGH "EVENT=DATA_SNR_HIGH"
++#define CUS_EVT_PRE_BEACON_LOST "EVENT=PRE_BEACON_LOST"
++
++#define CUS_EVT_DEEP_SLEEP_AWAKE "EVENT=DS_AWAKE"
++
++#define CUS_EVT_ADHOC_LINK_SENSED "EVENT=ADHOC_LINK_SENSED"
++#define CUS_EVT_ADHOC_BCN_LOST "EVENT=ADHOC_BCN_LOST"
++
++/**
++ * @brief Maximum number of channels that can be sent in a setuserscan ioctl
++ *
++ * @sa wlan_ioctl_user_scan_cfg
++ */
++#define WLAN_IOCTL_USER_SCAN_CHAN_MAX 50
++
++/** wlan_ioctl */
++typedef struct _wlan_ioctl
++{
++ /** Command ID */
++ u16 command;
++ /** data length */
++ u16 len;
++ /** data pointer */
++ u8 *data;
++} wlan_ioctl;
++
++/** wlan_ioctl_rfantenna */
++typedef struct _wlan_ioctl_rfantenna
++{
++ u16 Action;
++ u16 AntennaMode;
++} wlan_ioctl_rfantenna;
++
++/** wlan_ioctl_regrdwr */
++typedef struct _wlan_ioctl_regrdwr
++{
++ /** Which register to access */
++ u16 WhichReg;
++ /** Read or Write */
++ u16 Action;
++ u32 Offset;
++ u16 NOB;
++ u32 Value;
++} wlan_ioctl_regrdwr;
++
++/** wlan_ioctl_cfregrdwr */
++typedef struct _wlan_ioctl_cfregrdwr
++{
++ /** Read or Write */
++ u8 Action;
++ /** register address */
++ u16 Offset;
++ /** register value */
++ u16 Value;
++} wlan_ioctl_cfregrdwr;
++
++/** wlan_ioctl_adhoc_key_info */
++typedef struct _wlan_ioctl_adhoc_key_info
++{
++ u16 action;
++ u8 key[16];
++ u8 tkiptxmickey[16];
++ u8 tkiprxmickey[16];
++} wlan_ioctl_adhoc_key_info;
++
++/** sleep_params */
++typedef struct _wlan_ioctl_sleep_params_config
++{
++ u16 Action;
++ u16 Error;
++ u16 Offset;
++ u16 StableTime;
++ u8 CalControl;
++ u8 ExtSleepClk;
++ u16 Reserved;
++} __ATTRIB_PACK__ wlan_ioctl_sleep_params_config,
++ *pwlan_ioctl_sleep_params_config;
++
++/** BCA TIME SHARE */
++typedef struct _wlan_ioctl_bca_timeshare_config
++{
++ /** ACT_GET/ACT_SET */
++ u16 Action;
++ /** Type: WLAN, BT */
++ u16 TrafficType;
++ /** Interval: 20msec - 60000msec */
++ u32 TimeShareInterval;
++ /** PTA arbiter time in msec */
++ u32 BTTime;
++} __ATTRIB_PACK__ wlan_ioctl_bca_timeshare_config,
++ *pwlan_ioctl_bca_timeshare_config;
++
++#define MAX_CFP_LIST_NUM 64
++
++/** wlan_ioctl_cfp_table */
++typedef struct _wlan_ioctl_cfp_table
++{
++ u32 region;
++ u32 cfp_no;
++ struct
++ {
++ u16 Channel;
++ u32 Freq;
++ u16 MaxTxPower;
++ u8 Unsupported;
++ } cfp[MAX_CFP_LIST_NUM];
++} __ATTRIB_PACK__ wlan_ioctl_cfp_table, *pwlan_ioctl_cfp_table;
++
++/**
++ * @brief IOCTL channel sub-structure sent in wlan_ioctl_user_scan_cfg
++ *
++ * Multiple instances of this structure are included in the IOCTL command
++ * to configure a instance of a scan on the specific channel.
++ */
++typedef struct
++{
++ u8 chanNumber; //!< Channel Number to scan
++ u8 radioType; //!< Radio type: 'B/G' Band = 0, 'A' Band = 1
++ u8 scanType; //!< Scan type: Active = 0, Passive = 1
++ u8 reserved;
++ u16 scanTime; //!< Scan duration in milliseconds; if 0 default used
++} __ATTRIB_PACK__ wlan_ioctl_user_scan_chan;
++/**
++ * @brief IOCTL SSID List sub-structure sent in wlan_ioctl_user_scan_cfg
++ *
++ * Used to specify SSID specific filters as well as SSID pattern matching
++ * filters for scan result processing in firmware.
++ */
++typedef struct
++{
++ char ssid[MRVDRV_MAX_SSID_LENGTH + 1];
++ u8 maxLen;
++} __ATTRIB_PACK__ wlan_ioctl_user_scan_ssid;
++
++/**
++ * @brief IOCTL input structure to configure an immediate scan cmd to firmware
++ *
++ * Used in the setuserscan (WLAN_SET_USER_SCAN) private ioctl. Specifies
++ * a number of parameters to be used in general for the scan as well
++ * as a channel list (wlan_ioctl_user_scan_chan) for each scan period
++ * desired.
++ *
++ * @sa wlan_set_user_scan_ioctl
++ */
++typedef struct
++{
++
++ /**
++ * @brief Flag set to keep the previous scan table intact
++ *
++ * If set, the scan results will accumulate, replacing any previous
++ * matched entries for a BSS with the new scan data
++ */
++ u8 keepPreviousScan; //!< Do not erase the existing scan results
++
++ /**
++ * @brief BSS Type to be sent in the firmware command
++ *
++ * Field can be used to restrict the types of networks returned in the
++ * scan. Valid settings are:
++ *
++ * - WLAN_SCAN_BSS_TYPE_BSS (infrastructure)
++ * - WLAN_SCAN_BSS_TYPE_IBSS (adhoc)
++ * - WLAN_SCAN_BSS_TYPE_ANY (unrestricted, adhoc and infrastructure)
++ */
++ u8 bssType;
++
++ /**
++ * @brief Configure the number of probe requests for active chan scans
++ */
++ u8 numProbes;
++
++ u8 reserved;
++
++ /**
++ * @brief BSSID filter sent in the firmware command to limit the results
++ */
++ u8 specificBSSID[MRVDRV_ETH_ADDR_LEN];
++
++ /**
++ * @brief SSID filter list used in the to limit the scan results
++ */
++ wlan_ioctl_user_scan_ssid ssidList[MRVDRV_MAX_SSID_LIST_LENGTH];
++
++ /**
++ * @brief Variable number (fixed maximum) of channels to scan up
++ */
++ wlan_ioctl_user_scan_chan chanList[WLAN_IOCTL_USER_SCAN_CHAN_MAX];
++
++} __ATTRIB_PACK__ wlan_ioctl_user_scan_cfg;
++
++#endif /* _WLAN_WEXT_H_ */
+diff --git a/drivers/net/wireless/marvell8686/wlan_wmm.c b/drivers/net/wireless/marvell8686/wlan_wmm.c
+new file mode 100644
+index 0000000..789ad2e
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_wmm.c
+@@ -0,0 +1,1666 @@
++/** @file wlan_wmm.c
++ * @brief This file contains functions for WMM.
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/********************************************************
++Change log:
++ 10/04/05: Add Doxygen format comments
++ 11/11/05: Add support for WMM Status change event
++ 01/05/06: Add kernel 2.6.x support
++ 01/11/06: Conditionalize new scan/join code modifications.
++ 04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
++********************************************************/
++#include "include.h"
++
++/********************************************************
++ Local Variables
++********************************************************/
++
++/** Maximum value FW can accept for driver delay in packet transmission */
++#define DRV_PKT_DELAY_TO_FW_MAX 512
++
++/** Set limit of driver packet delay for use in MSDU lifetime expiry and
++ * traffic stream metrics.
++ *
++ * - Set to 0 to disable driver delay in firmware
++ * - Set to DRV_PKT_DELAY_TO_FW_MAX to enable all possible values
++ */
++#define DRV_PKT_DELAY_TO_FW_LIMIT 0
++
++/** Upper and Lower threshold for packet queuing in the driver
++ *
++ * - When the number of packets queued reaches the upper limit,
++ * the driver will stop the net queue in the app/kernel space.
++ *
++ * - When the number of packets drops beneath the lower limit after
++ * having reached the upper limit, the driver will restart the net
++ * queue.
++ */
++#define WMM_QUEUED_PACKET_LOWER_LIMIT 40
++#define WMM_QUEUED_PACKET_UPPER_LIMIT 50
++
++#define IPTOS_OFFSET 5
++
++static const u8 wmm_info_ie[] = { WMM_IE, 0x07,
++ 0x00, 0x50, 0xf2, 0x02,
++ 0x00, 0x01, 0x00
++};
++
++/********************************************************
++ Local Functions
++********************************************************/
++#ifdef DEBUG_LEVEL2
++/**
++ * @brief Debug print function to display the priority parameters for a WMM AC
++ *
++ * @param acStr String pointer giving the AC enumeration (BK, BE, VI, VO)
++ * @param pACParam Pointer to the AC paramters to display
++ *
++ * @return void
++ */
++static void
++wmm_debugPrintAC(wlan_wmm_ac_e acVal,
++ const IEEEtypes_WmmAcParameters_t * pACParam)
++{
++ const char *acStr[] = { "BK", "BE", "VI", "VO" };
++
++ PRINTM(INFO, "WMM AC_%s: ACI=%d, ACM=%d, Aifsn=%d, "
++ "EcwMin=%d, EcwMax=%d, TxopLimit=%d\n",
++ acStr[acVal], pACParam->AciAifsn.Aci, pACParam->AciAifsn.Acm,
++ pACParam->AciAifsn.Aifsn, pACParam->Ecw.EcwMin,
++ pACParam->Ecw.EcwMax, wlan_le16_to_cpu(pACParam->TxopLimit));
++}
++
++#define PRINTM_AC(acStr, pACParam) wmm_debugPrintAC(acStr, pACParam)
++#else
++#define PRINTM_AC(acStr, pACParam)
++#endif
++
++/**
++ * @brief Compute the difference between two timestamps.
++ *
++ * @param pTv1 Pointer to timestamp1
++ * @param pTv2 Pointer to timestamp2
++ *
++ * @return Time difference in ms between pTv1 and pTv2 (pTv1 - pTv2)
++ */
++static int
++timeval_diff_in_ms(const struct timeval *pTv1, const struct timeval *pTv2)
++{
++ int diff_ms;
++
++ diff_ms = (pTv1->tv_sec - pTv2->tv_sec) * 1000;
++ diff_ms += (pTv1->tv_usec - pTv2->tv_usec) / 1000;
++
++ return diff_ms;
++}
++
++/**
++ * @brief Set the WMM queue priorities to their default values
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++static void
++wmm_default_queue_priorities(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ /* default queue priorities: VO->VI->BE->BK */
++ Adapter->wmm.queuePriority[0] = WMM_AC_VO;
++ Adapter->wmm.queuePriority[1] = WMM_AC_VI;
++ Adapter->wmm.queuePriority[2] = WMM_AC_BE;
++ Adapter->wmm.queuePriority[3] = WMM_AC_BK;
++}
++
++/**
++ * @brief Initialize WMM priority queues
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++static void
++wmm_setup_queue_priorities(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ IEEEtypes_WmmParameter_t *pWmmIe;
++ wlan_wmm_ac_e acOrder[4] = { WMM_AC_BE, WMM_AC_BK,
++ WMM_AC_VI, WMM_AC_VO
++ };
++
++ u16 cwmax, cwmin, avg_back_off, tmp[4];
++ int i, j, numAc;
++
++ if (Adapter->wmm.enabled == FALSE) {
++ /* WMM is not enabled, just set the defaults and return */
++ wmm_default_queue_priorities(priv);
++ return;
++ }
++
++ pWmmIe = &Adapter->CurBssParams.BSSDescriptor.wmmIE;
++
++ HEXDUMP("WMM: setup_queue_priorities: param IE",
++ (u8 *) pWmmIe, sizeof(IEEEtypes_WmmParameter_t));
++
++ PRINTM(INFO, "WMM Parameter IE: version=%d, "
++ "QoSInfo Parameter Set Count=%d, Reserved=%#x\n",
++ pWmmIe->VendHdr.Version, pWmmIe->QoSInfo.ParaSetCount,
++ pWmmIe->Reserved);
++
++ for (numAc = 0; numAc < NELEMENTS(acOrder); numAc++) {
++ cwmax = (1 << pWmmIe->AcParams[numAc].Ecw.EcwMax) - 1;
++ cwmin = (1 << pWmmIe->AcParams[numAc].Ecw.EcwMin) - 1;
++ avg_back_off = (cwmin >> 1) + pWmmIe->AcParams[numAc].AciAifsn.Aifsn;
++ Adapter->wmm.queuePriority[numAc] = acOrder[numAc];
++ tmp[numAc] = avg_back_off;
++
++ PRINTM(INFO, "WMM: CWmax=%d CWmin=%d Avg Back-off=%d\n",
++ cwmax, cwmin, avg_back_off);
++ PRINTM_AC(acOrder[numAc], &pWmmIe->AcParams[numAc]);
++ }
++
++ HEXDUMP("WMM: avg_back_off", (u8 *) tmp, sizeof(tmp));
++ HEXDUMP("WMM: queuePriority", Adapter->wmm.queuePriority,
++ sizeof(Adapter->wmm.queuePriority));
++
++ /* bubble sort */
++ for (i = 0; i < numAc; i++) {
++ for (j = 1; j < numAc - i; j++) {
++ if (tmp[j - 1] > tmp[j]) {
++ SWAP_U16(tmp[j - 1], tmp[j]);
++ SWAP_U8(Adapter->wmm.queuePriority[j - 1],
++ Adapter->wmm.queuePriority[j]);
++ } else if (tmp[j - 1] == tmp[j]) {
++ if (Adapter->wmm.queuePriority[j - 1]
++ < Adapter->wmm.queuePriority[j]) {
++ SWAP_U8(Adapter->wmm.queuePriority[j - 1],
++ Adapter->wmm.queuePriority[j]);
++ }
++ }
++ }
++ }
++
++ HEXDUMP("WMM: avg_back_off, sort", (u8 *) tmp, sizeof(tmp));
++ HEXDUMP("WMM: queuePriority, sort", Adapter->wmm.queuePriority,
++ sizeof(Adapter->wmm.queuePriority));
++}
++
++/**
++ * @brief pop up the highest skb from wmm queue
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++static void
++wmm_pop_highest_prio_skb(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int i;
++ u8 ac;
++
++ ENTER();
++
++ for (i = 0; i < MAX_AC_QUEUES; i++) {
++ ac = Adapter->wmm.queuePriority[i];
++ if (!list_empty((struct list_head *) &Adapter->wmm.txSkbQ[ac])) {
++ PRINTM(DATA, "WMM: Highest prio pkt in AC Queue %d\n", i);
++ Adapter->CurrentTxSkb = Adapter->wmm.txSkbQ[ac].next;
++ Adapter->wmm.packetsOut[ac]++;
++ list_del((struct list_head *) Adapter->wmm.txSkbQ[ac].next);
++ break;
++ }
++ }
++
++ LEAVE();
++}
++
++/**
++ * @brief Evaluate whether or not an AC is to be downgraded
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param evalAC AC to evaluate for downgrading
++ *
++ * @return WMM AC the evalAC traffic is to be sent on.
++ */
++static wlan_wmm_ac_e
++wmm_eval_downgrade_ac(wlan_private * priv, wlan_wmm_ac_e evalAC)
++{
++ wlan_wmm_ac_e downAC;
++ wlan_wmm_ac_e retAC;
++ WmmAcStatus_t *pACStatus;
++
++ pACStatus = &priv->adapter->wmm.acStatus[evalAC];
++
++ if (pACStatus->Disabled == FALSE) {
++ /* Okay to use this AC, its enabled */
++ return evalAC;
++ }
++
++ /* Setup a default return value of the lowest priority */
++ retAC = WMM_AC_BK;
++
++ /*
++ * Find the highest AC that is enabled and does not require admission
++ * control. The spec disallows downgarding to an AC which is enabled
++ * due to a completed admission control. Unadmitted traffic is not
++ * to be sent on an AC with admitted traffic.
++ */
++ for (downAC = WMM_AC_BK; downAC < evalAC; downAC++) {
++ pACStatus = &priv->adapter->wmm.acStatus[downAC];
++
++ if ((pACStatus->Disabled == FALSE)
++ && (pACStatus->FlowRequired == FALSE)) {
++ /* AC is enabled and does not require admission control */
++ retAC = downAC;
++ }
++ }
++
++ return retAC;
++}
++
++/**
++ * @brief Downgrade WMM priority queue
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++static void
++wmm_setup_ac_downgrade(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_wmm_ac_e acVal;
++
++ PRINTM(INFO, "WMM: AC Priorities: BK(0), BE(1), VI(2), VO(3)\n");
++
++ if (Adapter->wmm.enabled == FALSE) {
++ /* WMM is not enabled, default priorities */
++ for (acVal = WMM_AC_BK; acVal <= WMM_AC_VO; acVal++) {
++ for (acVal = WMM_AC_BK; acVal <= WMM_AC_VO; acVal++) {
++ Adapter->wmm.acDowngradedVals[acVal] = acVal;
++ }
++ }
++ } else {
++ for (acVal = WMM_AC_BK; acVal <= WMM_AC_VO; acVal++) {
++ Adapter->wmm.acDowngradedVals[acVal]
++ = wmm_eval_downgrade_ac(priv, acVal);
++ PRINTM(INFO, "WMM: AC PRIO %d maps to %d\n",
++ acVal, Adapter->wmm.acDowngradedVals[acVal]);
++ }
++ }
++}
++
++/**
++ * @brief Convert the IP TOS field to an WMM AC Queue assignment
++ *
++ * @param tos IP TOS field
++ *
++ * @return WMM AC Queue mapping of the IP TOS field
++ */
++wlan_wmm_ac_e
++wmm_convert_tos_to_ac(int tos)
++{
++ u8 tosIdx;
++
++ /* Map of TOS UP values to WMM AC */
++ const wlan_wmm_ac_e tos_to_ac[] = { WMM_AC_BE,
++ WMM_AC_BK,
++ WMM_AC_BK,
++ WMM_AC_BE,
++ WMM_AC_VI,
++ WMM_AC_VI,
++ WMM_AC_VO,
++ WMM_AC_VO
++ };
++
++ tosIdx = tos >> IPTOS_OFFSET;
++
++ if (tosIdx >= NELEMENTS(tos_to_ac)) {
++ return WMM_AC_BE;
++ }
++
++ return tos_to_ac[tosIdx];
++}
++
++/**
++ * @brief Evaluate a given AC and downgrade it to a lower AC if the
++ * WMM Parameter IE received from the AP indicates that the AP
++ * is disabled (due to call admission control (ACM bit)
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param acVal AC to evaulate for downgrading
++ *
++ * @return Same AC as input if downgrading not required or
++ * the AC the traffic for the given AC should be downgraded to
++ */
++wlan_wmm_ac_e
++wmm_downgrade_ac(wlan_private * priv, wlan_wmm_ac_e acVal)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ return (Adapter->wmm.acDowngradedVals[acVal]);
++}
++
++/**
++ * @brief Map the IP TOS field to a user priority value
++ *
++ * @param tos IP TOS field
++ *
++ * @return User priority tos input parameter maps to
++ */
++static u8
++wmm_tos_to_priority(u8 tos)
++{
++ u8 tosIdx;
++ const u8 tos_to_priority[] = {
++ /* Priority DSCP_P2 DSCP_P1 DSCP_P0 WMM_AC */
++ 0x00, /* 0 0 0 AC_BE */
++ 0x01, /* 0 0 1 AC_BK */
++ 0x02, /* 0 1 0 AC_BK */
++ 0x03, /* 0 1 1 AC_BE */
++ 0x04, /* 1 0 0 AC_VI */
++ 0x05, /* 1 0 1 AC_VI */
++ 0x06, /* 1 1 0 AC_VO */
++ 0x07 /* 1 1 1 AC_VO */
++ };
++
++ tosIdx = tos >> IPTOS_OFFSET;
++
++ if (tosIdx >= NELEMENTS(tos_to_priority)) {
++ return WMM_AC_BE;
++ }
++
++ return tos_to_priority[tosIdx];
++}
++
++/**
++ * @brief Process a transfer of a data packet to the firmware from the
++ * driver queue in order to manipulate flow control in the driver.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_process_fw_iface_tx_xfer_start(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ if (--Adapter->wmm.packetsQueued < WMM_QUEUED_PACKET_LOWER_LIMIT) {
++ PRINTM(DATA, "WMM: FW OS+: %d\n", Adapter->wmm.packetsQueued);
++ os_start_queue(priv);
++ }
++}
++
++/**
++ * @brief Process the completion of a data packet transfer to the firmware
++ * from the driver queue in order to manipulate flow control in the
++ * driver.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ *
++ */
++void
++wmm_process_fw_iface_tx_xfer_end(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ if (Adapter->wmm.packetsQueued) {
++ PRINTM(DATA, "WMM: FW OS-: %d\n", Adapter->wmm.packetsQueued);
++ os_stop_queue(priv);
++ }
++}
++
++/**
++ * @brief Process a transfer of a data packet from the OS to the driver
++ * queue in order to manipulate flow control in the driver.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_process_app_iface_tx(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ Adapter->wmm.packetsQueued++;
++
++ if ((!priv->wlan_dev.dnld_sent && (Adapter->PSState != PS_STATE_SLEEP))
++ || (Adapter->wmm.packetsQueued >= WMM_QUEUED_PACKET_UPPER_LIMIT)) {
++ PRINTM(DATA, "WMM: APP OS-: %d\n", Adapter->wmm.packetsQueued);
++ os_stop_queue(priv);
++ }
++}
++
++/**
++ * @brief Stop the WMM data queues. Traffic is still accepted from the
++ * OS until the buffer limits are reached.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_stop_queue(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ PRINTM(DATA, "WMM: Q-: %d\n", Adapter->wmm.packetsQueued);
++ Adapter->wmm.queueStopped = TRUE;
++}
++
++/**
++ * @brief Start/re-start the WMM data queues and indicate to the OS layer
++ * that data is being accepted again.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_start_queue(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++
++ PRINTM(DATA, "WMM: Q+: %d\n", Adapter->wmm.packetsQueued);
++ Adapter->wmm.queueStopped = FALSE;
++ if (Adapter->wmm.packetsQueued) {
++ wake_up_interruptible(&priv->MainThread.waitQ);
++ }
++ os_carrier_on(priv);
++ os_start_queue(priv);
++}
++
++/**
++ * @brief Query the status of the WMM queues. Determine if the driver data
++ * path is active or not.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return TRUE if WMM queues have been stopped, FALSE if still active
++ */
++int
++wmm_is_queue_stopped(wlan_private * priv)
++{
++ return (priv->adapter->wmm.queueStopped == TRUE);
++}
++
++/**
++ * @brief Initialize the WMM state information and the WMM data path queues.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_init(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ int i;
++ memset(&Adapter->wmm, 0x00, sizeof(Adapter->wmm));
++
++ for (i = 0; i < MAX_AC_QUEUES; i++) {
++ INIT_LIST_HEAD((struct list_head *) &Adapter->wmm.txSkbQ[i]);
++ }
++
++ Adapter->wmm.required = FALSE;
++
++ Adapter->gen_null_pkg = TRUE; /*Enable NULL Pkg generation */
++}
++
++/**
++ * @brief Setup the queue priorities and downgrade any queues as required
++ * by the WMM info. Setups default values if WMM is not active
++ * for this association.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_setup_queues(wlan_private * priv)
++{
++ wmm_setup_queue_priorities(priv);
++ wmm_setup_ac_downgrade(priv);
++}
++
++/**
++ * @brief implement WMM enable command
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param wrq Pointer to user data
++ *
++ * @return WLAN_STATUS_SUCCESS if success; otherwise <0
++ */
++int
++wlan_wmm_enable_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ ulong flags;
++ int data, data1;
++ int *val;
++
++ ENTER();
++
++ data = *((int *) (wrq->u.name + SUBCMD_OFFSET));
++ switch (data) {
++ case CMD_DISABLED: /* disable */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ return -EPERM;
++ }
++
++ spin_lock_irqsave(&Adapter->CurrentTxLock, flags);
++ Adapter->wmm.required = FALSE;
++ if (!Adapter->wmm.enabled) {
++ spin_unlock_irqrestore(&Adapter->CurrentTxLock, flags);
++ data1 = Adapter->wmm.required;
++ val = (int *) wrq->u.name;
++ *val = data;
++ return WLAN_STATUS_SUCCESS;
++ } else {
++ Adapter->wmm.enabled = 0;
++ }
++
++ if (Adapter->CurrentTxSkb) {
++ kfree_skb(Adapter->CurrentTxSkb);
++ OS_INT_DISABLE;
++ Adapter->CurrentTxSkb = NULL;
++ OS_INT_RESTORE;
++ priv->stats.tx_dropped++;
++ }
++
++ spin_unlock_irqrestore(&Adapter->CurrentTxLock, flags);
++ break;
++
++ case CMD_ENABLED: /* enable */
++ if (Adapter->MediaConnectStatus == WlanMediaStateConnected) {
++ return -EPERM;
++ }
++ spin_lock_irqsave(&Adapter->CurrentTxLock, flags);
++ Adapter->wmm.required = TRUE;
++ spin_unlock_irqrestore(&Adapter->CurrentTxLock, flags);
++ break;
++
++ case CMD_GET:
++ break;
++ default:
++ PRINTM(INFO, "Invalid option\n");
++ return -EINVAL;
++ }
++
++ data = Adapter->wmm.required;
++ val = (int *) wrq->u.name;
++ *val = data;
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Implement cmd HostCmd_CMD_WMM_GET_STATUS
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param cmd Pointer to CMD buffer
++ * @param InfoBuf Pointer to cmd data
++ *
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++wlan_cmd_wmm_get_status(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf)
++{
++ PRINTM(INFO, "WMM: WMM_GET_STATUS cmd sent\n");
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_WMM_GET_STATUS);
++ cmd->Size =
++ wlan_cpu_to_le16(sizeof(HostCmd_DS_WMM_GET_STATUS) + S_DS_GEN);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Send a command to firmware to retrieve the current WMM status
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return WLAN_STATUS_SUCCESS; WLAN_STATUS_FAILURE
++ */
++int
++sendWMMStatusChangeCmd(wlan_private * priv)
++{
++ return PrepareAndSendCommand(priv, HostCmd_CMD_WMM_GET_STATUS,
++ 0, 0, 0, NULL);
++}
++
++/**
++ * @brief Check if wmm TX queue is empty
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return FALSE if not empty; TRUE if empty
++ */
++int
++wmm_lists_empty(wlan_private * priv)
++{
++ int i;
++
++ for (i = 0; i < MAX_AC_QUEUES; i++) {
++ if (!list_empty((struct list_head *) &priv->adapter->wmm.txSkbQ[i])) {
++ return FALSE;
++ }
++ }
++ return TRUE;
++}
++
++/**
++ * @brief Cleanup wmm TX queue
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_cleanup_queues(wlan_private * priv)
++{
++ int i;
++ struct sk_buff *delNode, *Q;
++
++ ENTER();
++
++ for (i = 0; i < MAX_AC_QUEUES; i++) {
++ Q = &priv->adapter->wmm.txSkbQ[i];
++
++ while (!list_empty((struct list_head *) Q)) {
++ delNode = Q->next;
++ list_del((struct list_head *) delNode);
++ kfree_skb(delNode);
++ }
++ }
++
++ priv->adapter->wmm.packetsQueued = 0;
++
++ LEAVE();
++}
++
++/**
++ * @brief Add skb to WMM queue
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param skb Pointer to sk_buff
++ *
++ * @return void
++ */
++void
++wmm_map_and_add_skb(wlan_private * priv, struct sk_buff *skb)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ struct ethhdr *eth;
++ struct timeval tstamp;
++ u8 tos;
++ wlan_wmm_ac_e ac;
++ wlan_wmm_ac_e ac_down;
++
++ eth = (struct ethhdr *) skb->data;
++
++ switch (eth->h_proto) {
++ case __constant_htons(ETH_P_IP):
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
++ PRINTM(INFO, "packet type ETH_P_IP: %04x, tos=%#x prio=%#x\n",
++ eth->h_proto, ip_hdr(skb)->tos, skb->priority);
++ tos = IPTOS_PREC(ip_hdr(skb)->tos) >> IPTOS_OFFSET;
++#else
++ PRINTM(DATA, "packet type ETH_P_IP: %04x, tos=%#x prio=%#x\n",
++ eth->h_proto, skb->nh.iph->tos, skb->priority);
++ tos = IPTOS_PREC(skb->nh.iph->tos);
++#endif
++ break;
++ case __constant_htons(ETH_P_ARP):
++ PRINTM(DATA, "ARP packet %04x\n", eth->h_proto);
++ default:
++ tos = 0;
++ break;
++ }
++
++ ac = wmm_convert_tos_to_ac(tos);
++ ac_down = wmm_downgrade_ac(priv, ac);
++
++ skb->priority = wmm_tos_to_priority(tos);
++ PRINTM(DATA, "wmm_map: tos=%#x, ac=%#x ac_down=%#x, priority=%#x\n",
++ tos, ac, ac_down, skb->priority);
++
++ list_add_tail((struct list_head *) skb,
++ (struct list_head *) &Adapter->wmm.txSkbQ[ac_down]);
++
++ wmm_process_app_iface_tx(priv);
++
++ /* Record the current time the packet was queued; used to determine
++ * the amount of time the packet was queued in the driver before it
++ * was sent to the firmware. The delay is then sent along with the
++ * packet to the firmware for aggregate delay calculation for stats
++ * and MSDU lifetime expiry.
++ */
++ do_gettimeofday(&tstamp);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
++ skb->tstamp = timeval_to_ktime(tstamp);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)
++ skb_set_timestamp(skb, &tstamp);
++#else
++ memcpy(&skb->stamp, &tstamp, sizeof(skb->stamp));
++#endif
++}
++
++/**
++ * @brief Process the GET_WMM_STATUS command response from firmware
++ *
++ * The GET_WMM_STATUS command returns multiple TLVs for:
++ * - Each AC Queue status
++ * - Current WMM Parameter IE
++ *
++ * This function parses the TLVs and then calls further functions
++ * to process any changes in the queue prioritization or state.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param resp Pointer to the command response buffer including TLVs
++ * TLVs for each queue and the WMM Parameter IE.
++ *
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++wlan_cmdresp_wmm_get_status(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ u8 *pCurrent = (u8 *) & resp->params.getWmmStatus;
++ u32 respLen = resp->Size;
++ int valid = TRUE;
++ int enableData = TRUE;
++
++ MrvlIEtypes_Data_t *pTlvHdr;
++ MrvlIEtypes_WmmQueueStatus_t *pTlvWmmQStatus;
++ IEEEtypes_WmmParameter_t *pWmmParamIe;
++ WmmAcStatus_t *pACStatus;
++
++ PRINTM(INFO, "WMM: WMM_GET_STATUS cmdresp received: %d\n", respLen);
++ HEXDUMP("CMD_RESP: WMM_GET_STATUS", pCurrent, respLen);
++
++ while ((respLen >= sizeof(pTlvHdr->Header)) && valid) {
++ pTlvHdr = (MrvlIEtypes_Data_t *) pCurrent;
++ pTlvHdr->Header.Len = wlan_le16_to_cpu(pTlvHdr->Header.Len);
++
++ switch (wlan_le16_to_cpu(pTlvHdr->Header.Type)) {
++ case TLV_TYPE_WMMQSTATUS:
++ pTlvWmmQStatus = (MrvlIEtypes_WmmQueueStatus_t *) pTlvHdr;
++ PRINTM(INFO,
++ "CMD_RESP: WMM_GET_STATUS: QSTATUS TLV: %d, %d, %d\n",
++ pTlvWmmQStatus->QueueIndex, pTlvWmmQStatus->FlowRequired,
++ pTlvWmmQStatus->Disabled);
++
++ pACStatus = &Adapter->wmm.acStatus[pTlvWmmQStatus->QueueIndex];
++ pACStatus->Disabled = pTlvWmmQStatus->Disabled;
++ pACStatus->FlowRequired = pTlvWmmQStatus->FlowRequired;
++ pACStatus->FlowCreated = pTlvWmmQStatus->FlowCreated;
++ break;
++
++ case WMM_IE:
++ /*
++ * Point the regular IEEE IE 2 bytes into the Marvell IE
++ * and setup the IEEE IE type and length byte fields
++ */
++
++ HEXDUMP("WMM: WMM TLV:", (u8 *) pTlvHdr, pTlvHdr->Header.Len + 4);
++
++ pWmmParamIe = (IEEEtypes_WmmParameter_t *) (pCurrent + 2);
++ pWmmParamIe->VendHdr.Len = pTlvHdr->Header.Len;
++ pWmmParamIe->VendHdr.ElementId = WMM_IE;
++
++ PRINTM(INFO, "CMD_RESP: WMM_GET_STATUS: WMM Parameter Set: %d\n",
++ pWmmParamIe->QoSInfo.ParaSetCount);
++
++ memcpy((u8 *) & Adapter->CurBssParams.BSSDescriptor.wmmIE,
++ pWmmParamIe, pWmmParamIe->VendHdr.Len + 2);
++
++ break;
++
++ default:
++ valid = FALSE;
++ break;
++ }
++
++ pCurrent += (pTlvHdr->Header.Len + sizeof(pTlvHdr->Header));
++ respLen -= (pTlvHdr->Header.Len + sizeof(pTlvHdr->Header));
++ }
++
++ wmm_setup_queue_priorities(priv);
++ wmm_setup_ac_downgrade(priv);
++
++ if (enableData) {
++ wmm_start_queue(priv);
++ os_carrier_on(priv);
++ os_start_queue(priv);
++ }
++
++ send_iwevcustom_event(priv, WMM_CONFIG_CHANGE_INDICATION);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Call back from the command module to allow insertion of a WMM TLV
++ *
++ * If the BSS we are associating to supports WMM, add the required WMM
++ * Information IE to the association request command buffer in the form
++ * of a Marvell extended IEEE IE.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param ppAssocBuf Output parameter: Pointer to the TLV output buffer,
++ * modified on return to point after the appended WMM TLV
++ * @param pWmmIE Pointer to the WMM IE for the BSS we are joining
++ *
++ * @return Length of data appended to the association tlv buffer
++ */
++u32
++wlan_wmm_process_association_req(wlan_private * priv,
++ u8 ** ppAssocBuf,
++ IEEEtypes_WmmParameter_t * pWmmIE)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ MrvlIEtypes_WmmParamSet_t *pWmmTlv;
++ u32 retLen = 0;
++
++ /* Null checks */
++ if (ppAssocBuf == 0)
++ return 0;
++ if (*ppAssocBuf == 0)
++ return 0;
++ if (pWmmIE == 0)
++ return 0;
++
++ PRINTM(INFO, "WMM: process assoc req: bss->wmmIe=%x\n",
++ pWmmIE->VendHdr.ElementId);
++
++ if (Adapter->wmm.required && pWmmIE->VendHdr.ElementId == WMM_IE) {
++ pWmmTlv = (MrvlIEtypes_WmmParamSet_t *) * ppAssocBuf;
++ pWmmTlv->Header.Type = (u16) wmm_info_ie[0];
++ pWmmTlv->Header.Type = wlan_cpu_to_le16(pWmmTlv->Header.Type);
++ pWmmTlv->Header.Len = (u16) wmm_info_ie[1];
++ pWmmTlv->Header.Len = wlan_cpu_to_le16(pWmmTlv->Header.Len);
++
++ memcpy(pWmmTlv->WmmIE, &wmm_info_ie[2], pWmmTlv->Header.Len);
++#define QOS_INFO_PARA_MASK 0x0f
++ if (pWmmIE->QoSInfo.QosUAPSD
++ && ((Adapter->wmm.qosinfo & QOS_INFO_PARA_MASK) != 0)) {
++ memcpy((u8 *) (pWmmTlv->WmmIE + pWmmTlv->Header.Len
++ - sizeof(Adapter->wmm.qosinfo)),
++ &Adapter->wmm.qosinfo, sizeof(Adapter->wmm.qosinfo));
++ }
++ retLen = sizeof(pWmmTlv->Header) + pWmmTlv->Header.Len;
++
++ HEXDUMP("ASSOC_CMD: WMM IE", (u8 *) pWmmTlv, retLen);
++ *ppAssocBuf += retLen;
++ }
++
++ return retLen;
++}
++
++/**
++ * @brief Compute the time delay in the driver queues for a given skb.
++ *
++ * When the skb is received at the OS/Driver interface, the current
++ * time is set in the skb structure. The difference between the present
++ * time and that received time is computed in this function and limited
++ * based on pre-compiled limits in the driver.
++ *
++ * @param skb Pointer to a sk_buff which has been previously timestamped
++ *
++ * @return Time delay of the packet in 2ms units after having limit applied
++ */
++u8
++wmm_compute_driver_packet_delay(const struct sk_buff * skb)
++{
++ u8 retVal;
++ struct timeval in_tv;
++ struct timeval out_tv;
++ int queue_delay;
++
++ retVal = 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)
++ skb_get_timestamp(skb, &in_tv);
++#else
++ memcpy(&in_tv, &skb->stamp, sizeof(in_tv));
++#endif
++ do_gettimeofday(&out_tv);
++
++ queue_delay = timeval_diff_in_ms(&out_tv, &in_tv);
++
++ /* Queue delay is passed as a uint8 in units of 2ms (ms shifted
++ * by 1). Min value (other than 0) is therefore 2ms, max is 510ms.
++ *
++ * Pass max value if queue_delay is beyond the uint8 range
++ */
++ retVal = MIN(queue_delay, DRV_PKT_DELAY_TO_FW_LIMIT) >> 1;
++
++ PRINTM(DATA, "WMM: Pkt Delay: %d ms, %d ms sent to FW\n",
++ queue_delay, retVal);
++
++ return retVal;
++}
++
++/**
++ * @brief Transmit the highest priority packet awaiting in the WMM Queues
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ *
++ * @return void
++ */
++void
++wmm_process_tx(wlan_private * priv)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ ulong flags;
++
++ OS_INTERRUPT_SAVE_AREA;
++
++ ENTER();
++
++ if ((Adapter->PSState == PS_STATE_SLEEP)
++ || (Adapter->PSState == PS_STATE_PRE_SLEEP)) {
++ PRINTM(INFO, "In PS State %d"
++ " - Not sending the packet\n", Adapter->PSState);
++ LEAVE();
++
++ return;
++ }
++
++ spin_lock_irqsave(&Adapter->CurrentTxLock, flags);
++
++ if (priv->wlan_dev.dnld_sent) {
++ spin_unlock_irqrestore(&Adapter->CurrentTxLock, flags);
++
++ LEAVE();
++
++ return;
++ }
++
++ UpdateTransStart(priv->wlan_dev.netdev);
++ wmm_pop_highest_prio_skb(priv);
++
++ spin_unlock_irqrestore(&Adapter->CurrentTxLock, flags);
++
++ if (Adapter->CurrentTxSkb) {
++ wlan_process_tx(priv);
++ }
++
++ LEAVE();
++}
++
++/**
++ * @brief Private IOCTL entry to get the status of the WMM queues
++ *
++ * Return the following information for each WMM AC:
++ * - WMM IE Acm Required
++ * - Firmware Flow Required
++ * - Firmware Flow Established
++ * - Firmware Queue Enabled
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param wrq A pointer to iwreq structure containing the
++ * wlan_ioctl_wmm_queue_status_t struct for request
++ *
++ * @return 0 if successful; IOCTL error code otherwise
++ */
++int
++wlan_wmm_queue_status_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_adapter *Adapter = priv->adapter;
++ wlan_ioctl_wmm_queue_status_t qstatus;
++ wlan_wmm_ac_e acVal;
++ WmmAcStatus_t *pACStatus;
++ IEEEtypes_WmmAcParameters_t *pWmmIeAC;
++
++ for (acVal = WMM_AC_BK; acVal <= WMM_AC_VO; acVal++) {
++ pACStatus = &Adapter->wmm.acStatus[acVal];
++ pWmmIeAC = &Adapter->CurBssParams.BSSDescriptor.wmmIE.AcParams[acVal];
++
++ /* Acm bit */
++ qstatus.acStatus[acVal].wmmAcm = pWmmIeAC->AciAifsn.Acm;
++
++ /* Firmware status */
++ qstatus.acStatus[acVal].flowRequired = pACStatus->FlowRequired;
++ qstatus.acStatus[acVal].flowCreated = pACStatus->FlowCreated;
++ qstatus.acStatus[acVal].disabled = pACStatus->Disabled;
++ }
++
++ if (copy_to_user(wrq->u.data.pointer, &qstatus, sizeof(qstatus))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Private IOCTL entry to send an ADDTS TSPEC
++ *
++ * Receive a ADDTS command from the application. The command structure
++ * contains a TSPEC and timeout in milliseconds. The timeout is performed
++ * in the firmware after the ADDTS command frame is sent.
++ *
++ * The TSPEC is received in the API as an opaque block whose length is
++ * calculated from the IOCTL data length. The firmware will send the
++ * entire data block, including the bytes after the TSPEC. This is done
++ * to allow extra IEs to be packaged with the TSPEC in the ADDTS action
++ * frame.
++ *
++ * The IOCTL structure contains two return fields:
++ * - The firmware command result which indicates failure and timeouts
++ * - The IEEE Status code which contains the corresponding value from
++ * any ADDTS response frame received.
++ *
++ * In addition, the opaque TSPEC data block passed in is replaced with the
++ * TSPEC recieved in the ADDTS response frame. In case of failure, the
++ * AP may modify the TSPEC on return and in the case of success, the
++ * medium time is returned as calculated by the AP. Along with the TSPEC,
++ * any IEs that are sent in the ADDTS response are also returned and can be
++ * parsed using the IOCTL length as an indicator of extra elements.
++ *
++ * The return value to the application layer indicates a driver execution
++ * success or failure. A successful return could still indicate a firmware
++ * failure or AP negotiation failure via the commandResult field copied
++ * back to the application.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param wrq A pointer to iwreq structure containing the
++ * wlan_ioctl_wmm_addts_req_t struct for this ADDTS request
++ *
++ * @return 0 if successful; IOCTL error code otherwise
++ */
++int
++wlan_wmm_addts_req_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ static u8 dialogTok = 0;
++ wlan_ioctl_wmm_addts_req_t addtsIoctl;
++ wlan_cmd_wmm_addts_req_t addtsCmd;
++ int retcode;
++
++ if (copy_from_user(&addtsIoctl,
++ wrq->u.data.pointer,
++ MIN(wrq->u.data.length, sizeof(addtsIoctl))) != 0) {
++ /* copy_from_user failed */
++ PRINTM(INFO, "TSPEC: ADDTS copy from user failed\n");
++ retcode = -EFAULT;
++
++ } else {
++ memset(&addtsCmd, 0x00, sizeof(addtsCmd));
++ if ((++dialogTok) == 0)
++ dialogTok = 1;
++
++ addtsCmd.dialogToken = dialogTok;
++ addtsCmd.timeout_ms = addtsIoctl.timeout_ms;
++ addtsCmd.tspecDataLen = (wrq->u.data.length
++ - sizeof(addtsCmd.timeout_ms)
++ - sizeof(addtsCmd.commandResult)
++ - sizeof(addtsCmd.ieeeStatusCode));
++ memcpy(addtsCmd.tspecData,
++ addtsIoctl.tspecData, addtsCmd.tspecDataLen);
++
++ retcode = PrepareAndSendCommand(priv,
++ HostCmd_CMD_WMM_ADDTS_REQ, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ &addtsCmd);
++
++ wrq->u.data.length = (sizeof(addtsIoctl.timeout_ms)
++ + sizeof(addtsIoctl.commandResult)
++ + sizeof(addtsIoctl.ieeeStatusCode)
++ + addtsCmd.tspecDataLen);
++
++ addtsIoctl.commandResult = addtsCmd.commandResult;
++ addtsIoctl.ieeeStatusCode = addtsCmd.ieeeStatusCode;
++ memcpy(addtsIoctl.tspecData,
++ addtsCmd.tspecData, addtsCmd.tspecDataLen);
++
++ if (copy_to_user(wrq->u.data.pointer,
++ &addtsIoctl, sizeof(addtsIoctl))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ if (retcode) {
++ return -EFAULT;
++ }
++ }
++
++ return retcode;
++}
++
++/**
++ * @brief Private IOCTL entry to send a DELTS TSPEC
++ *
++ * Receive a DELTS command from the application. The command structure
++ * contains a TSPEC and reason code along with space for a command result
++ * to be returned. The information is packaged is sent to the wlan_cmd.c
++ * firmware command prep and send routines for execution in the firmware.
++ *
++ * The reason code is not used for WMM implementations but is indicated in
++ * the 802.11e specification.
++ *
++ * The return value to the application layer indicates a driver execution
++ * success or failure. A successful return could still indicate a firmware
++ * failure via the commandResult field copied back to the application.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param wrq A pointer to iwreq structure containing the
++ * wlan_ioctl_wmm_delts_req_t struct for this DELTS request
++ *
++ * @return 0 if successful; IOCTL error code otherwise
++ */
++int
++wlan_wmm_delts_req_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_ioctl_wmm_delts_req_t deltsIoctl;
++ wlan_cmd_wmm_delts_req_t deltsCmd;
++ int retcode;
++
++ if (copy_from_user(&deltsIoctl,
++ wrq->u.data.pointer,
++ MIN(wrq->u.data.length, sizeof(deltsIoctl))) != 0) {
++ /* copy_from_user failed */
++ PRINTM(INFO, "TSPEC: DELTS copy from user failed\n");
++ retcode = -EFAULT;
++
++ } else {
++ memset(&deltsCmd, 0x00, sizeof(deltsCmd));
++
++ /* Dialog token unused for WMM implementations */
++ deltsCmd.dialogToken = 0;
++
++ deltsCmd.ieeeReasonCode = deltsIoctl.ieeeReasonCode;
++
++ /* Calculate the length of the TSPEC and any other IEs */
++ deltsCmd.tspecDataLen = (wrq->u.data.length
++ - sizeof(deltsCmd.commandResult)
++ - sizeof(deltsCmd.ieeeReasonCode));
++ memcpy(deltsCmd.tspecData,
++ deltsIoctl.tspecData, deltsCmd.tspecDataLen);
++
++ /* Send the DELTS request to firmware, wait for a response */
++ retcode = PrepareAndSendCommand(priv,
++ HostCmd_CMD_WMM_DELTS_REQ, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ &deltsCmd);
++
++ /* Return the firmware command result back to the application layer */
++ deltsIoctl.commandResult = deltsCmd.commandResult;
++
++ if (copy_to_user(wrq->u.data.pointer,
++ &deltsCmd,
++ MIN(wrq->u.data.length, sizeof(deltsIoctl)))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ return -EFAULT;
++ }
++
++ if (retcode) {
++ retcode = -EFAULT;
++ }
++ }
++
++ return retcode;
++}
++
++/**
++ * @brief Process the ADDTS_REQ command response from firmware
++ *
++ * Return the ADDTS firmware response to the calling thread that sent
++ * the command. The result is then relayed back the app layer.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param resp Pointer to the command response buffer including the
++ * command result and any returned ADDTS response TSPEC
++ * elements
++ *
++ * @return WLAN_STATUS_SUCCESS
++ *
++ * @sa wlan_wmm_addts_req_ioctl
++ */
++int
++wlan_cmdresp_wmm_addts_req(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp)
++{
++ wlan_cmd_wmm_addts_req_t *pAddTsCmd;
++ const HostCmd_DS_WMM_ADDTS_REQ *pCmdResp;
++
++ /* Cast the NULL pointer of the buffer the IOCTL sent in the command req */
++ pAddTsCmd = (wlan_cmd_wmm_addts_req_t *) priv->adapter->CurCmd->pdata_buf;
++
++ /* Convenience variable for the ADDTS response from the firmware */
++ pCmdResp = &resp->params.addTsReq;
++
++ /* Assign return data */
++ pAddTsCmd->commandResult = pCmdResp->commandResult;
++
++ if (pCmdResp->commandResult == TSPEC_RESULT_SUCCESS) {
++ pAddTsCmd->dialogToken = pCmdResp->dialogToken;
++ pAddTsCmd->ieeeStatusCode = pCmdResp->ieeeStatusCode;
++
++ /* The tspecData field is potentially variable in size due to extra IEs
++ * that may have been in the ADDTS response action frame. Calculate
++ * the data length from the firmware command response.
++ */
++ pAddTsCmd->tspecDataLen = (resp->Size
++ - sizeof(pCmdResp->commandResult)
++ - sizeof(pCmdResp->timeout_ms)
++ - sizeof(pCmdResp->dialogToken)
++ - sizeof(pCmdResp->ieeeStatusCode)
++ - S_DS_GEN);
++
++ /* Copy the TSPEC data include any extra IEs after the TSPEC */
++ memcpy(pAddTsCmd->tspecData,
++ pCmdResp->tspecData,
++ MIN(pAddTsCmd->tspecDataLen, sizeof(pAddTsCmd->tspecData)
++ + sizeof(pAddTsCmd->addtsExtraIEBuf)));
++ } else {
++ pAddTsCmd->dialogToken = 0;
++ pAddTsCmd->ieeeStatusCode = 0;
++ pAddTsCmd->tspecDataLen = 0;
++ }
++
++ PRINTM(INFO, "TSPEC: ADDTS ret = %d,%d sz=%d\n",
++ pAddTsCmd->commandResult, pAddTsCmd->ieeeStatusCode,
++ pAddTsCmd->tspecDataLen);
++
++ HEXDUMP("TSPEC: ADDTS data",
++ pAddTsCmd->tspecData, pAddTsCmd->tspecDataLen);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Process the DELTS_REQ command response from firmware
++ *
++ * Return the DELTS firmware response to the calling thread that sent
++ * the command. The result is then relayed back the app layer.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param resp Pointer to the command response buffer with the command
++ * result. No other response information is passed back
++ * to the driver.
++ *
++ * @return WLAN_STATUS_SUCCESS
++ *
++ * @sa wlan_wmm_delts_req_ioctl
++ */
++int
++wlan_cmdresp_wmm_delts_req(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp)
++{
++ wlan_cmd_wmm_delts_req_t *pDelTsCmd;
++
++ /* Cast the NULL pointer of the buffer the IOCTL sent in the command req */
++ pDelTsCmd = (wlan_cmd_wmm_delts_req_t *) priv->adapter->CurCmd->pdata_buf;
++
++ pDelTsCmd->commandResult =
++ wlan_le16_to_cpu(resp->params.delTsReq.commandResult);
++
++ PRINTM(INFO, "TSPEC: DELTS result = %d\n", pDelTsCmd->commandResult);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Implement cmd HostCmd_DS_WMM_ADDTS_REQ
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param cmd Pointer to CMD buffer
++ * @param InfoBuf Pointer to cmd data
++ *
++ * @return WLAN_STATUS_SUCCESS
++ *
++ * @sa wlan_wmm_addts_req_ioctl
++ */
++int
++wlan_cmd_wmm_addts_req(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf)
++{
++ wlan_cmd_wmm_addts_req_t *pAddTsCmd;
++ int tspecCopySize;
++
++ pAddTsCmd = (wlan_cmd_wmm_addts_req_t *) InfoBuf;
++
++ cmd->params.addTsReq.timeout_ms = pAddTsCmd->timeout_ms;
++ cmd->params.addTsReq.dialogToken = pAddTsCmd->dialogToken;
++
++ tspecCopySize = MIN(pAddTsCmd->tspecDataLen,
++ sizeof(cmd->params.addTsReq.tspecData));
++ memcpy(&cmd->params.addTsReq.tspecData,
++ pAddTsCmd->tspecData, tspecCopySize);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_WMM_ADDTS_REQ);
++ cmd->Size = wlan_cpu_to_le16(sizeof(cmd->params.addTsReq.dialogToken)
++ + sizeof(cmd->params.addTsReq.timeout_ms)
++ + sizeof(cmd->params.addTsReq.commandResult)
++ + sizeof(cmd->params.addTsReq.ieeeStatusCode)
++ + tspecCopySize + S_DS_GEN);
++
++ cmd->params.addTsReq.timeout_ms
++ = wlan_cpu_to_le32(cmd->params.addTsReq.timeout_ms);
++
++ PRINTM(INFO, "WMM: ADDTS Cmd: Data Len = %d\n", pAddTsCmd->tspecDataLen);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Implement cmd HostCmd_DS_WMM_DELTS_REQ
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param cmd Pointer to CMD buffer
++ * @param InfoBuf Void pointer cast of a wlan_cmd_wmm_delts_req_t struct
++ *
++ * @return WLAN_STATUS_SUCCESS
++ *
++ * @sa wlan_wmm_delts_req_ioctl
++ */
++int
++wlan_cmd_wmm_delts_req(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf)
++{
++ wlan_cmd_wmm_delts_req_t *pDelTsCmd;
++ int tspecCopySize;
++
++ pDelTsCmd = (wlan_cmd_wmm_delts_req_t *) InfoBuf;
++
++ cmd->params.delTsReq.dialogToken = pDelTsCmd->dialogToken;
++ cmd->params.delTsReq.ieeeReasonCode = pDelTsCmd->ieeeReasonCode;
++
++ tspecCopySize = MIN(pDelTsCmd->tspecDataLen,
++ sizeof(cmd->params.delTsReq.tspecData));
++ memcpy(&cmd->params.delTsReq.tspecData,
++ pDelTsCmd->tspecData, tspecCopySize);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_WMM_DELTS_REQ);
++ cmd->Size = wlan_cpu_to_le16(sizeof(cmd->params.delTsReq.dialogToken)
++ + sizeof(cmd->params.delTsReq.commandResult)
++ + sizeof(cmd->params.delTsReq.ieeeReasonCode)
++ + tspecCopySize + S_DS_GEN);
++
++ PRINTM(INFO, "WMM: DELTS Cmd prepared\n");
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Prepare the firmware command buffer for the WMM_QUEUE_CONFIG command
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param cmd Pointer to CMD buffer
++ * @param InfoBuf Void pointer cast of a wlan_cmd_wmm_queue_config_t struct
++ *
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++wlan_cmd_wmm_queue_config(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf)
++{
++ wlan_cmd_wmm_queue_config_t *pQConfigCmd;
++ int tlvCopySize;
++
++ pQConfigCmd = (wlan_cmd_wmm_queue_config_t *) InfoBuf;
++
++ cmd->params.queueConfig.action = pQConfigCmd->action;
++ cmd->params.queueConfig.accessCategory = pQConfigCmd->accessCategory;
++ cmd->params.queueConfig.msduLifetimeExpiry
++ = wlan_cpu_to_le16(pQConfigCmd->msduLifetimeExpiry);
++
++ tlvCopySize = MIN(pQConfigCmd->tlvBufLen,
++ sizeof(cmd->params.queueConfig.tlvBuffer));
++ memcpy(&cmd->params.queueConfig.tlvBuffer,
++ pQConfigCmd->tlvBuffer, tlvCopySize);
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_WMM_QUEUE_CONFIG);
++ cmd->Size = wlan_cpu_to_le16(sizeof(cmd->params.queueConfig.action)
++ +
++ sizeof(cmd->params.queueConfig.
++ accessCategory)
++ +
++ sizeof(cmd->params.queueConfig.
++ msduLifetimeExpiry)
++ + tlvCopySize + S_DS_GEN);
++
++ PRINTM(INFO, "WMM: QUEUE CONFIG Cmd prepared\n");
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Process the WMM_QUEUE_CONFIG command response from firmware
++ *
++ * Return the firmware command response to the blocked IOCTL caller function.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param resp Pointer to the command response buffer with:
++ * - action code
++ * - access category
++ * - collected statistics if requested
++ *
++ * @return WLAN_STATUS_SUCCESS
++ *
++ * @sa wlan_wmm_queue_config_ioctl
++ */
++int
++wlan_cmdresp_wmm_queue_config(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp)
++{
++ wlan_cmd_wmm_queue_config_t *pQConfigCmd;
++ const HostCmd_DS_WMM_QUEUE_CONFIG *pCmdResp;
++
++ pQConfigCmd =
++ (wlan_cmd_wmm_queue_config_t *) (priv->adapter->CurCmd->pdata_buf);
++ pCmdResp = &resp->params.queueConfig;
++
++ pQConfigCmd->action = pCmdResp->action;
++ pQConfigCmd->accessCategory = pCmdResp->accessCategory;
++ pQConfigCmd->msduLifetimeExpiry
++ = wlan_le16_to_cpu(pCmdResp->msduLifetimeExpiry);
++
++ pQConfigCmd->tlvBufLen = (resp->Size - sizeof(pCmdResp->action)
++ - sizeof(pCmdResp->accessCategory)
++ - sizeof(pCmdResp->msduLifetimeExpiry)
++ - S_DS_GEN);
++
++ memcpy(pQConfigCmd->tlvBuffer,
++ pCmdResp->tlvBuffer, pQConfigCmd->tlvBufLen);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Private IOCTL entry to get/set a specified AC Queue's parameters
++ *
++ * Receive a AC Queue configuration command which is used to get, set, or
++ * default the parameters associated with a specific WMM AC Queue.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param wrq A pointer to iwreq structure containing the
++ * wlan_ioctl_wmm_queue_config_t struct
++ *
++ * @return 0 if successful; IOCTL error code otherwise
++ */
++int
++wlan_wmm_queue_config_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_ioctl_wmm_queue_config_t queueConfigIoctl;
++ wlan_cmd_wmm_queue_config_t queueConfigCmd;
++ int retcode;
++
++ PRINTM(INFO, "WMM: Queue Config IOCTL Enter\n");
++
++ if (copy_from_user(&queueConfigIoctl,
++ wrq->u.data.pointer,
++ MIN(wrq->u.data.length,
++ sizeof(queueConfigIoctl))) != 0) {
++ /* copy_from_user failed */
++ PRINTM(INFO, "WMM: Queue Config: copy from user failed\n");
++ retcode = -EFAULT;
++
++ } else {
++ memset(&queueConfigCmd, 0x00, sizeof(queueConfigCmd));
++
++ queueConfigCmd.action = queueConfigIoctl.action;
++ queueConfigCmd.accessCategory = queueConfigIoctl.accessCategory;
++ queueConfigCmd.msduLifetimeExpiry
++ = queueConfigIoctl.msduLifetimeExpiry;
++
++ /* Create a rates TLV from the supportedRates[] ioctl field */
++ queueConfigCmd.tlvBufLen = 0;
++
++ retcode = PrepareAndSendCommand(priv,
++ HostCmd_CMD_WMM_QUEUE_CONFIG, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ &queueConfigCmd);
++ if (retcode) {
++ retcode = -EFAULT;
++ } else {
++ memset(&queueConfigIoctl, 0x00, sizeof(queueConfigIoctl));
++
++ queueConfigIoctl.action = queueConfigCmd.action;
++ queueConfigIoctl.accessCategory = queueConfigCmd.accessCategory;
++ queueConfigIoctl.msduLifetimeExpiry
++ = queueConfigCmd.msduLifetimeExpiry;
++
++ wrq->u.data.length = sizeof(queueConfigIoctl);
++
++ if (copy_to_user(wrq->u.data.pointer,
++ &queueConfigIoctl, sizeof(queueConfigIoctl))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ retcode = -EFAULT;
++ }
++ }
++ }
++
++ return retcode;
++}
++
++/**
++ * @brief Prepare the firmware command buffer for the WMM_QUEUE_STATS command
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param cmd pointer to CMD buffer
++ * @param InfoBuf void pointer cast of a HostCmd_CMD_WMM_QUEUE_STATS struct
++ *
++ * @return WLAN_STATUS_SUCCESS
++ */
++int
++wlan_cmd_wmm_queue_stats(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf)
++{
++ memcpy(&cmd->params.queueStats, InfoBuf, sizeof(cmd->params.queueStats));
++
++ cmd->Command = wlan_cpu_to_le16(HostCmd_CMD_WMM_QUEUE_STATS);
++ cmd->Size = wlan_cpu_to_le16(sizeof(HostCmd_DS_WMM_QUEUE_STATS)
++ + S_DS_GEN);
++
++ PRINTM(INFO, "WMM: QUEUE STATS Cmd prepared\n");
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Process the WMM_QUEUE_STATS command response from firmware
++ *
++ * Return the firmware command response to the blocked IOCTL caller function.
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param resp Pointer to the command response buffer with:
++ * - action code
++ * - access category
++ * - collected statistics if requested
++ *
++ * @return WLAN_STATUS_SUCCESS
++ *
++ * @sa wlan_wmm_queue_stats_ioctl
++ */
++int
++wlan_cmdresp_wmm_queue_stats(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp)
++{
++ HostCmd_DS_WMM_QUEUE_STATS *pQueueStats =
++ (HostCmd_DS_WMM_QUEUE_STATS *) priv->adapter->CurCmd->pdata_buf;
++
++ memcpy(pQueueStats, &resp->params.queueStats, (resp->Size - S_DS_GEN));
++
++ pQueueStats->pktCount = wlan_le16_to_cpu(pQueueStats->pktCount);
++ pQueueStats->pktLoss = wlan_le16_to_cpu(pQueueStats->pktLoss);
++ pQueueStats->avgQueueDelay = wlan_le32_to_cpu(pQueueStats->avgQueueDelay);
++ pQueueStats->avgTxDelay = wlan_le32_to_cpu(pQueueStats->avgTxDelay);
++ pQueueStats->usedTime = wlan_le32_to_cpu(pQueueStats->usedTime);
++
++ PRINTM(INFO, "WMM: Queue Stats response: %d\n", resp->Size - S_DS_GEN);
++
++ return WLAN_STATUS_SUCCESS;
++}
++
++/**
++ * @brief Private IOCTL entry to get and start/stop queue stats on a WMM AC
++ *
++ * Receive a AC Queue statistics command from the application for a specific
++ * WMM AC. The command can:
++ * - Turn stats on
++ * - Turn stats off
++ * - Collect and clear the stats
++ *
++ * @param priv Pointer to the wlan_private driver data struct
++ * @param wrq A pointer to iwreq structure containing the
++ * wlan_ioctl_wmm_queue_stats_t struct
++ *
++ * @return 0 if successful; IOCTL error code otherwise
++ */
++int
++wlan_wmm_queue_stats_ioctl(wlan_private * priv, struct iwreq *wrq)
++{
++ wlan_ioctl_wmm_queue_stats_t queueStatsIoctl;
++ HostCmd_DS_WMM_QUEUE_STATS queueStatsCmd;
++ int retcode;
++
++ if (copy_from_user(&queueStatsIoctl,
++ wrq->u.data.pointer,
++ MIN(wrq->u.data.length,
++ sizeof(queueStatsIoctl))) != 0) {
++ /* copy_from_user failed */
++ PRINTM(INFO, "WMM: Queue Stats: copy from user failed\n");
++ retcode = -EFAULT;
++
++ } else {
++ memcpy(&queueStatsCmd, &queueStatsIoctl, sizeof(queueStatsIoctl));
++
++ PRINTM(INFO, "WMM: QUEUE STATS Ioctl: %d, %d\n",
++ queueStatsCmd.action, queueStatsCmd.accessCategory);
++
++ retcode = PrepareAndSendCommand(priv,
++ HostCmd_CMD_WMM_QUEUE_STATS, 0,
++ HostCmd_OPTION_WAITFORRSP, 0,
++ &queueStatsCmd);
++ if (retcode) {
++ retcode = -EFAULT;
++ } else {
++ if (copy_to_user(wrq->u.data.pointer,
++ &queueStatsCmd,
++ MIN(wrq->u.data.length,
++ sizeof(queueStatsCmd)))) {
++ PRINTM(INFO, "Copy to user failed\n");
++ retcode = -EFAULT;
++ }
++ }
++ }
++
++ if (retcode != WLAN_STATUS_SUCCESS) {
++ PRINTM(INFO, "WMM: QUEUE STATS Ioctl FAILED: %d, %d\n",
++ queueStatsIoctl.action, queueStatsIoctl.accessCategory);
++ }
++
++ return retcode;
++}
+diff --git a/drivers/net/wireless/marvell8686/wlan_wmm.h b/drivers/net/wireless/marvell8686/wlan_wmm.h
+new file mode 100644
+index 0000000..97c24db
+--- /dev/null
++++ b/drivers/net/wireless/marvell8686/wlan_wmm.h
+@@ -0,0 +1,111 @@
++/** @file wlan_wmm.h
++ * @brief This file contains related macros, enum, and struct
++ * of wmm functionalities
++ *
++ * Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
++ */
++/****************************************************
++Change log:
++ 09/26/05: add Doxygen format comments
++ 04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
++****************************************************/
++
++#ifndef __WLAN_WMM_H
++#define __WLAN_WMM_H
++
++/** Custom indiciation message sent to the application layer for WMM changes */
++#define WMM_CONFIG_CHANGE_INDICATION "WMM_CONFIG_CHANGE.indication"
++
++/** Highest priority setting for a packet (uses voice AC) */
++#define WMM_HIGHEST_PRIORITY 7
++
++#ifdef __KERNEL__
++
++/** struct of WMM DESC */
++typedef struct
++{
++ u8 required;
++ u8 enabled;
++ u8 packetsQueued;
++ u8 queueStopped;
++ u32 packetsOut[MAX_AC_QUEUES];
++ u32 userPriPktTxCtrl[WMM_HIGHEST_PRIORITY + 1]; /* UP: 0 to 7 */
++
++ struct sk_buff txSkbQ[MAX_AC_QUEUES];
++ WmmAcStatus_t acStatus[MAX_AC_QUEUES];
++ wlan_wmm_ac_e acDowngradedVals[MAX_AC_QUEUES];
++
++ /** wmm queue priority table*/
++ u8 queuePriority[MAX_AC_QUEUES];
++
++ u8 qosinfo;
++} __ATTRIB_PACK__ WMM_DESC;
++
++extern void wmm_map_and_add_skb(wlan_private * priv, struct sk_buff *);
++extern u8 wmm_compute_driver_packet_delay(const struct sk_buff *skb);
++#endif
++
++extern int sendWMMStatusChangeCmd(wlan_private * priv);
++extern int wmm_lists_empty(wlan_private * priv);
++extern void wmm_cleanup_queues(wlan_private * priv);
++extern void wmm_process_tx(wlan_private * priv);
++
++extern void wmm_init(wlan_private * priv);
++extern void wmm_setup_queues(wlan_private * priv);
++extern void wmm_start_queue(wlan_private * priv);
++extern void wmm_stop_queue(wlan_private * priv);
++extern int wmm_is_queue_stopped(wlan_private * priv);
++
++extern void wmm_process_fw_iface_tx_xfer_start(wlan_private * priv);
++extern void wmm_process_fw_iface_tx_xfer_end(wlan_private * priv);
++extern void wmm_process_app_iface_tx(wlan_private * priv);
++extern wlan_wmm_ac_e wmm_convert_tos_to_ac(int tos);
++extern wlan_wmm_ac_e wmm_downgrade_ac(wlan_private * priv,
++ wlan_wmm_ac_e acVal);
++
++extern u32 wlan_wmm_process_association_req(wlan_private * priv,
++ u8 ** ppAssocBuf,
++ IEEEtypes_WmmParameter_t *
++ pWmmIE);
++
++/*
++ * Functions used in the cmd handling routine
++ */
++extern int wlan_cmd_wmm_get_status(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf);
++extern int wlan_cmd_wmm_addts_req(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf);
++extern int wlan_cmd_wmm_delts_req(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf);
++extern int wlan_cmd_wmm_queue_config(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf);
++extern int wlan_cmd_wmm_queue_stats(wlan_private * priv,
++ HostCmd_DS_COMMAND * cmd, void *InfoBuf);
++
++/*
++ * Functions used in the cmdresp handling routine
++ */
++extern int wlan_cmdresp_wmm_get_status(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp);
++extern int wlan_cmdresp_wmm_addts_req(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp);
++extern int wlan_cmdresp_wmm_delts_req(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp);
++extern int wlan_cmdresp_wmm_queue_config(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp);
++extern int wlan_cmdresp_wmm_queue_stats(wlan_private * priv,
++ const HostCmd_DS_COMMAND * resp);
++
++/*
++ * IOCTLs
++ */
++extern int wlan_wmm_enable_ioctl(wlan_private * priv, struct iwreq *wrq);
++extern int wlan_wmm_queue_status_ioctl(wlan_private * priv,
++ struct iwreq *wrq);
++
++extern int wlan_wmm_addts_req_ioctl(wlan_private * priv, struct iwreq *wrq);
++extern int wlan_wmm_delts_req_ioctl(wlan_private * priv, struct iwreq *wrq);
++extern int wlan_wmm_queue_config_ioctl(wlan_private * priv,
++ struct iwreq *wrq);
++extern int wlan_wmm_queue_stats_ioctl(wlan_private * priv, struct iwreq *wrq);
++#endif /* __WLAN_WMM_H */
+diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
+index de5dbcd..41001fa 100644
+--- a/drivers/rtc/rtc-s3c.c
++++ b/drivers/rtc/rtc-s3c.c
+@@ -36,7 +36,8 @@
+
+ static struct resource *s3c_rtc_mem;
+
+-static void __iomem *s3c_rtc_base;
++void __iomem *s3c_rtc_base;
++EXPORT_SYMBOL(s3c_rtc_base);
+ static int s3c_rtc_alarmno = NO_IRQ;
+ static int s3c_rtc_tickno = NO_IRQ;
+ static int s3c_rtc_freq = 1;
+@@ -77,7 +78,7 @@ static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
+ }
+
+ /* Update control registers */
+-static void s3c_rtc_setaie(int to)
++void s3c_rtc_setaie(int to)
+ {
+ unsigned int tmp;
+
+@@ -97,6 +98,7 @@ static void s3c_rtc_setaie(int to)
+ disable_irq_wake(s3c_rtc_alarmno);
+
+ }
++EXPORT_SYMBOL(s3c_rtc_setaie);
+
+ static void s3c_rtc_setpie(int to)
+ {
+@@ -120,7 +122,7 @@ static void s3c_rtc_setfreq(int freq)
+
+ /* Time read/write */
+
+-static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
++int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
+ {
+ unsigned int have_retried = 0;
+ void __iomem *base = s3c_rtc_base;
+@@ -159,6 +161,7 @@ static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
+
+ return 0;
+ }
++EXPORT_SYMBOL(s3c_rtc_gettime);
+
+ static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
+ {
+@@ -172,10 +175,8 @@ static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
+
+ /* we get around y2k by simply not supporting it */
+
+- if (year < 0 || year >= 100) {
+- dev_err(dev, "rtc only supports 100 years\n");
+- return -EINVAL;
+- }
++ if(year < 0) year = 0;
++ if(year >= 100) year = 99;
+
+ writeb(BIN2BCD(tm->tm_sec), base + S3C2410_RTCSEC);
+ writeb(BIN2BCD(tm->tm_min), base + S3C2410_RTCMIN);
+@@ -247,7 +248,7 @@ static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
+ return 0;
+ }
+
+-static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
++int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+ struct rtc_time *tm = &alrm->time;
+ void __iomem *base = s3c_rtc_base;
+@@ -290,6 +291,7 @@ static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+
+ return 0;
+ }
++EXPORT_SYMBOL(s3c_rtc_setalarm);
+
+ static int s3c_rtc_ioctl(struct device *dev,
+ unsigned int cmd, unsigned long arg)
+diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c
+index 89e15c7..2238df2 100644
+--- a/drivers/serial/s3c6400.c
++++ b/drivers/serial/s3c6400.c
+@@ -797,10 +797,11 @@ static int s3c_serial_calcbaud(struct baud_calc *calc,
+ calc->quot = tempdiv/1000;
+ calc->calc = (rate / (calc->quot * 16));
+ calc->slot = nSlotTable[nslot];
++
++return 1;
+ printk(KERN_DEBUG "FOUND quot %d, calc %d, slot 0x%x, nslot %ld\n",
+ calc->quot, calc->calc ,
+ calc->slot, nslot);
+- return 1;
+ }
+
+ static unsigned int s3c_serial_getclk(struct uart_port *port,
+@@ -882,15 +883,14 @@ static unsigned int s3c_serial_getclk(struct uart_port *port,
+ printk(KERN_DEBUG "The best clksrc among candidate clksrc: %p(%s) (deviation: %d bps)\n", best, best->clksrc->name, deviation);
+ }
+
+- printk(KERN_DEBUG "Selected clock is %p (%s) quot %d, calc %d\n",
+- best->clksrc, best->clksrc->name, best->quot, best->calc);
+-
+ /* store results to pass back */
+ *clksrc = best->clksrc;
+ *clk = best->src;
+ *slot = best->slot;
+
+- return best->quot;
++return best->quot;
++ printk(KERN_DEBUG "Selected clock is %p (%s) quot %d, calc %d\n",
++ best->clksrc, best->clksrc->name, best->quot, best->calc);
+ }
+
+ static void s3c_serial_set_termios(struct uart_port *port,
+diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c
+index b469718..64d182d 100644
+--- a/drivers/usb/core/driver.c
++++ b/drivers/usb/core/driver.c
+@@ -26,9 +26,13 @@
+ #include <linux/usb.h>
+ #include <linux/usb/quirks.h>
+ #include <linux/workqueue.h>
++#include <linux/module.h>
+ #include "hcd.h"
+ #include "usb.h"
+
++struct usb_device *sr_udev;
++EXPORT_SYMBOL(sr_udev);
++
+
+ #ifdef CONFIG_HOTPLUG
+
+@@ -1224,13 +1228,13 @@ static int usb_autopm_do_device(struct usb_device *udev, int inc_usage_cnt)
+ usb_pm_unlock(udev);
+ return status;
+ }
+-
++EXPORT_SYMBOL(usb_autopm_do_device);
+ /* usb_autosuspend_work - callback routine to autosuspend a USB device */
+ void usb_autosuspend_work(struct work_struct *work)
+ {
+ struct usb_device *udev =
+ container_of(work, struct usb_device, autosuspend.work);
+-
++ sr_udev = udev;
+ usb_autopm_do_device(udev, 0);
+ }
+
+@@ -1282,7 +1286,7 @@ void usb_try_autosuspend_device(struct usb_device *udev)
+ dev_vdbg(&udev->dev, "%s: cnt %d\n",
+ __FUNCTION__, udev->pm_usage_cnt);
+ }
+-
++EXPORT_SYMBOL(usb_try_autosuspend_device);
+ /**
+ * usb_autoresume_device - immediately autoresume a USB device and its interfaces
+ * @udev: the usb_device to autoresume
+@@ -1511,6 +1515,7 @@ int usb_external_resume_device(struct usb_device *udev)
+ usb_try_autosuspend_device(udev);
+ return status;
+ }
++EXPORT_SYMBOL(usb_external_resume_device);
+
+ static int usb_suspend(struct device *dev, pm_message_t message)
+ {
+diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
+index 10e2993..f71d038 100644
+--- a/drivers/usb/gadget/Kconfig
++++ b/drivers/usb/gadget/Kconfig
+@@ -297,7 +297,7 @@ config USB_GADGET_S3C_HS
+
+ config USB_GADGET_S3C_OTGD_HS
+ boolean "S3C USB OTG controller"
+- depends on PLAT_S3C64XX && !(USB_S3C_OTG_HOST)
++ depends on PLAT_S3C64XX #&& !(USB_S3C_OTG_HOST) # XXX: mhfan
+ select USB_GADGET_SELECTED
+ select USB_GADGET_DUALSPEED
+ help
+@@ -307,7 +307,7 @@ config USB_GADGET_S3C_OTGD_HS
+
+ config USB_S3C
+ tristate
+- depends on USB_GADGET_S3C_FS && USB_GADGET_S3C_HS && USB_GADGET_S3C_OTGD_HS
++ depends on USB_GADGET_S3C_FS || USB_GADGET_S3C_HS || USB_GADGET_S3C_OTGD_HS
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
+@@ -401,7 +401,7 @@ comment "NOTE: S3C OTG device role enables the controller driver below"
+
+ config USB_S3C_OTGD_HS
+ tristate "S3C high speed(2.0, dual-speed) USB OTG device"
+- depends on USB_GADGET && USB_GADGET_S3C_OTGD_HS && !(USB_S3C_OTG_HOST)
++ depends on USB_GADGET && USB_GADGET_S3C_OTGD_HS
+ default y
+ help
+ Say "y" to link the driver statically, or "m" to build a
+diff --git a/drivers/usb/gadget/s3c-udc-otg-hs.c b/drivers/usb/gadget/s3c-udc-otg-hs.c
+index 7b95e2c..6408c21 100644
+--- a/drivers/usb/gadget/s3c-udc-otg-hs.c
++++ b/drivers/usb/gadget/s3c-udc-otg-hs.c
+@@ -128,7 +128,7 @@ static u32 ep_fifo_size2 = 1024;
+ static int reset_available = 1;
+
+ /* extern declarations in arch/arm/mach-s3c64xx*/
+-#define OTGD_PHY_CLK_VALUE (0x20) /* UTMI Interface, Oscillator */
++#define OTGD_PHY_CLK_VALUE (0x02) /* UTMI Interface, Oscillator */
+ extern void otg_phy_init(u32 otg_phy_clk);
+ extern void otg_phy_off(void);
+ extern struct usb_ctrlrequest usb_ctrl;
+diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
+index c214ef5..c3401db 100644
+--- a/drivers/usb/host/ohci-s3c2410.c
++++ b/drivers/usb/host/ohci-s3c2410.c
+@@ -35,8 +35,11 @@
+ static struct clk *clk;
+ static struct clk *usb_clk;
+
+-#undef USB_HOST_PORT2_EN
+-//#define USB_HOST_PORT2_EN
++#if defined (CONFIG_LCD_7)
++#undef USB_HOST_PORT2_EN
++#else
++#define USB_HOST_PORT2_EN
++#endif
+
+ #if defined(CONFIG_PLAT_S3C64XX)
+ #define S3C_USB_CLKSRC_EPLL 0
+@@ -45,9 +48,9 @@ extern void usb_host_clk_en(int usb_host_clksrc, u32 otg_phy_clk);
+
+ #ifdef USB_HOST_PORT2_EN
+ static struct clk *otg_clk;
+-#define OTGH_PHY_CLK_VALUE (0x60) /* Serial Interface, Oscillator */
++#define OTGH_PHY_CLK_VALUE (0x42) /* Serial Interface, Oscillator */
+ #else
+-#define OTGH_PHY_CLK_VALUE (0x20) /* UTMI Interface, Oscillator */
++#define OTGH_PHY_CLK_VALUE (0x02) /* UTMI Interface, Oscillator */
+ #endif
+ #endif
+
+@@ -580,12 +583,58 @@ static int ohci_hcd_s3c2410_drv_remove(struct platform_device *pdev)
+ return 0;
+ }
+
++#ifdef CONFIG_PM
++static int ohci_hcd_s3c2410_drv_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct usb_hcd *hcd = platform_get_drvdata(pdev);
++ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
++
++ if (time_before(jiffies, ohci->next_statechange))
++ msleep(5);
++ ohci->next_statechange = jiffies;
++
++ s3c2410_stop_hc(pdev);
++ hcd->state = HC_STATE_SUSPENDED;
++ pdev->dev.power.power_state = PMSG_SUSPEND;
++
++ return 0;
++}
++
++static int ohci_hcd_s3c2410_drv_resume(struct platform_device *pdev)
++{
++ struct usb_hcd *hcd = platform_get_drvdata(pdev);
++ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
++
++ if (time_before(jiffies, ohci->next_statechange))
++ msleep(5);
++ ohci->next_statechange = jiffies;
++
++#if defined(CONFIG_PLAT_S3C64XX)
++ usb_host_clk_en(S3C_USB_CLKSRC_48M, OTGH_PHY_CLK_VALUE);
++#endif
++
++ s3c2410_usb_set_power(pdev->dev.platform_data, 1, 1);
++ s3c2410_usb_set_power(pdev->dev.platform_data, 2, 1);
++
++ s3c2410_start_hc(pdev, hcd);
++
++ ohci_hcd_init(hcd_to_ohci(hcd));
++
++ pdev->dev.power.power_state = PMSG_ON;
++ usb_hcd_resume_root_hub(hcd);
++
++ return 0;
++}
++#endif
++
+ static struct platform_driver ohci_hcd_s3c2410_driver = {
+ .probe = ohci_hcd_s3c2410_drv_probe,
+ .remove = ohci_hcd_s3c2410_drv_remove,
+ .shutdown = usb_hcd_platform_shutdown,
+- /*.suspend = ohci_hcd_s3c2410_drv_suspend, */
+- /*.resume = ohci_hcd_s3c2410_drv_resume, */
++#ifdef CONFIG_PM
++ .suspend = ohci_hcd_s3c2410_drv_suspend,
++ .resume = ohci_hcd_s3c2410_drv_resume,
++#endif
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "s3c2410-ohci",
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c
+index cfb8590..efca605 100644
+--- a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c
+@@ -29,9 +29,43 @@
+ ****************************************************************************/
+
+ #include "s3c-otg-hcdi-hcd.h"
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include <linux/module.h>
+
+ static SPINLOCK_t otg_hcd_spin_lock = SPIN_LOCK_INIT;
+
++struct work_struct port_work;
++struct work_struct disconnect_work;
++int suspend_yet;
++extern struct usb_device *sr_udev;
++extern void usb_try_autosuspend_device(struct usb_device *udev);
++extern int usb_external_resume_device(struct usb_device *udev);
++extern int usb_autopm_do_device(struct usb_device *udev, int inc_usage_cnt);
++
++void do_port_work(struct work_struct* work)
++{
++ if(suspend_yet == 0)
++ return;
++ else
++ usb_external_resume_device(sr_udev);
++ return;
++}
++
++void do_disconnect_work(struct work_struct* work)
++{
++ if(suspend_yet == 1)
++ return;
++ else
++ usb_try_autosuspend_device(sr_udev);
++ return;
++}
++
++EXPORT_SYMBOL(suspend_yet);
++EXPORT_SYMBOL(do_port_work);
++EXPORT_SYMBOL(do_disconnect_work);
++EXPORT_SYMBOL(port_work);
++EXPORT_SYMBOL(disconnect_work);
+ /**
+ * otg_hcd_init_modules()
+ *
+@@ -44,6 +78,8 @@ int otg_hcd_init_modules(void)
+ {
+ u32 spin_lock_flag = 0;
+
++ INIT_WORK(&port_work, do_port_work);
++ INIT_WORK(&disconnect_work, do_disconnect_work);
+ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "OTGHCD_InitModuless \n");
+ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
+
+@@ -60,7 +96,7 @@ int otg_hcd_init_modules(void)
+ * void otg_hcd_deinit_modules(void)
+ *
+ * @brief call other modules' de-init functions
+- *
++ * i
+ * @return PASS : If success \n
+ * FAIL : If fail \n
+ */
+@@ -165,6 +201,10 @@ void s3c6410_otghcd_stop(struct usb_hcd *hcd)
+ }
+ //-------------------------------------------------------------------------------
+
++void s3c6410_otghcd_resume(struct usb_hcd *usb_hcd_p)
++{
++}
++
+ /**
+ * void s3c6410_otghcd_shutdown(struct usb_hcd *hcd)
+ *
+@@ -174,8 +214,7 @@ void s3c6410_otghcd_stop(struct usb_hcd *hcd)
+ *
+ */
+ void s3c6410_otghcd_shutdown(struct usb_hcd *usb_hcd_p)
+-{
+-
++{
+ u32 spin_lock_flag = 0;
+
+ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_shutdown \n");
+@@ -583,7 +622,6 @@ s3c6410_otghcd_hub_control
+ int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd)
+ {
+ u32 spin_lock_flag = 0;
+-
+ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_bus_suspend \n");
+ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
+ bus_suspend();
+@@ -603,9 +641,8 @@ int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd)
+ * @return USB_ERR_SUCCESS \n
+ */
+ int s3c6410_otghcd_bus_resume(struct usb_hcd *hcd)
+-{
++{
+ u32 spin_lock_flag = 0;
+-
+ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_bus_resume \n");
+ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag);
+ if(bus_resume() != USB_ERR_SUCCESS)
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h
+index 031ebf6..f670990 100644
+--- a/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h
++++ b/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h
+@@ -132,7 +132,7 @@ static const struct hc_driver s3c6410_otg_hc_driver = {
+ .hub_status_data = s3c6410_otghcd_hub_status_data,
+ .hub_control = s3c6410_otghcd_hub_control,
+ //.hub_irq_enable =
+- .bus_suspend = s3c6410_otghcd_bus_suspend,
++ //.bus_suspend = s3c6410_otghcd_bus_suspend,
+ .bus_resume = s3c6410_otghcd_bus_resume,
+ .start_port_reset = s3c6410_otghcd_start_port_reset,
+ };
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-isr.c b/drivers/usb/host/s3c-otg/s3c-otg-isr.c
+index b2946a5..ba2c359 100644
+--- a/drivers/usb/host/s3c-otg/s3c-otg-isr.c
++++ b/drivers/usb/host/s3c-otg/s3c-otg-isr.c
+@@ -28,6 +28,9 @@
+ ****************************************************************************/
+
+ #include "s3c-otg-isr.h"
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include <linux/module.h>
+
+ /**
+ * void otg_handle_interrupt(void)
+@@ -44,6 +47,9 @@
+
+ extern port_flags_t port_flag;
+ extern bool ch_halt;
++extern int suspend_yet;
++extern struct work_struct port_work;
++extern struct work_struct disconnect_work;
+
+ __inline__ void otg_handle_interrupt(void)
+ {
+@@ -64,6 +70,8 @@ __inline__ void otg_handle_interrupt(void)
+ port_flag.b.port_connect_status_change = 1;
+ port_flag.b.port_connect_status = 0;
+ clearIntr.b.disconnect = 1;
++ if(suspend_yet == 0)
++ schedule_work(&disconnect_work);
+ }
+
+ if (gintsts.b.conidstschng)
+@@ -89,6 +97,8 @@ __inline__ void otg_handle_interrupt(void)
+ // Read Only
+ //otg_dbg(OTG_DBG_ISR, "Port Interrupt\n");
+ process_port_intr();
++ if(suspend_yet == 1)
++ schedule_work(&port_work);
+ }
+
+
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-oci.c b/drivers/usb/host/s3c-otg/s3c-otg-oci.c
+index 5e927c0..d054660 100644
+--- a/drivers/usb/host/s3c-otg/s3c-otg-oci.c
++++ b/drivers/usb/host/s3c-otg/s3c-otg-oci.c
+@@ -609,7 +609,7 @@ int oci_sys_init(void)
+ syscon_reg->HCLK_GATE |= (0x1<<20);
+ syscon_reg->OTHERS |= (0x1<<16);
+ otgphy_reg->OPHYPWR = 0x0;
+- otgphy_reg->OPHYCLK = 0x20;
++ otgphy_reg->OPHYCLK = 0x02;
+
+ otgphy_reg->ORSTCON = 0x1;
+ mdelay(80);
+diff --git a/drivers/usb/host/s3c-otg/s3c-otg-roothub.c b/drivers/usb/host/s3c-otg/s3c-otg-roothub.c
+index c38d115..e2fbf0f 100644
+--- a/drivers/usb/host/s3c-otg/s3c-otg-roothub.c
++++ b/drivers/usb/host/s3c-otg/s3c-otg-roothub.c
+@@ -30,7 +30,7 @@
+ #include "s3c-otg-roothub.h"
+
+ port_flags_t port_flag;
+-
++extern int suspend_yet;
+ /**
+ * int get_otg_port_status(const u8 port, char* status)
+ *
+@@ -393,6 +393,7 @@ __inline__ int root_hub_feature(const u8 port,
+ */
+ void bus_suspend(void)
+ {
++ suspend_yet = 1;
+ hprt_t hprt;
+ pcgcctl_t pcgcctl;
+
+@@ -402,14 +403,6 @@ void bus_suspend(void)
+ hprt.b.prtsusp = 1;
+ update_reg_32(HPRT, hprt.d32);
+
+- pcgcctl.b.pwrclmp = 1;
+- update_reg_32(PCGCCTL,pcgcctl.d32);
+- udelay(1);
+-
+- pcgcctl.b.rstpdwnmodule = 1;
+- update_reg_32(PCGCCTL,pcgcctl.d32);
+- udelay(1);
+-
+ pcgcctl.b.stoppclk = 1;
+ update_reg_32(PCGCCTL,pcgcctl.d32);
+ udelay(1);
+@@ -430,6 +423,7 @@ void bus_suspend(void)
+ */
+ int bus_resume(void)
+ {
++ suspend_yet = 0;
+ /*
+ hprt_t hprt;
+ pcgcctl_t pcgcctl;
+diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig
+index 9c7eb61..055c299 100644
+--- a/drivers/usb/misc/Kconfig
++++ b/drivers/usb/misc/Kconfig
+@@ -4,6 +4,15 @@
+ comment "USB Miscellaneous drivers"
+ depends on USB
+
++config USB_JZ4755
++ tristate "JZ4755 USB Boot interface support"
++ depends on USB
++ ---help---
++ This driver loads firmware to JZ4755.
++
++ After firmware load the JZ4755 can run Mplayer.
++
++
+ config USB_EMI62
+ tristate "EMI 6|2m USB Audio interface support"
+ depends on USB
+diff --git a/drivers/usb/misc/Makefile b/drivers/usb/misc/Makefile
+index b68e6b7..85f3131 100644
+--- a/drivers/usb/misc/Makefile
++++ b/drivers/usb/misc/Makefile
+@@ -26,6 +26,7 @@ obj-$(CONFIG_USB_RIO500) += rio500.o
+ obj-$(CONFIG_USB_TEST) += usbtest.o
+ obj-$(CONFIG_USB_TRANCEVIBRATOR) += trancevibrator.o
+ obj-$(CONFIG_USB_USS720) += uss720.o
++obj-$(CONFIG_USB_JZ4755) += jz4755.o
+
+ obj-$(CONFIG_USB_SISUSBVGA) += sisusbvga/
+
+diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
+index bbbe1b9..73b969a 100644
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -83,43 +83,236 @@ static int option_send_setup(struct usb_serial_port *port);
+ #define OPTION_PRODUCT_VIPER 0x6600
+ #define OPTION_PRODUCT_VIPER_BUS 0x6601
+ #define OPTION_PRODUCT_GT_MAX_READY 0x6701
+-#define OPTION_PRODUCT_GT_MAX 0x6711
+ #define OPTION_PRODUCT_FUJI_MODEM_LIGHT 0x6721
+ #define OPTION_PRODUCT_FUJI_MODEM_GT 0x6741
+ #define OPTION_PRODUCT_FUJI_MODEM_EX 0x6761
+-#define OPTION_PRODUCT_FUJI_NETWORK_LIGHT 0x6731
+-#define OPTION_PRODUCT_FUJI_NETWORK_GT 0x6751
+-#define OPTION_PRODUCT_FUJI_NETWORK_EX 0x6771
+ #define OPTION_PRODUCT_KOI_MODEM 0x6800
+-#define OPTION_PRODUCT_KOI_NETWORK 0x6811
+ #define OPTION_PRODUCT_SCORPION_MODEM 0x6901
+-#define OPTION_PRODUCT_SCORPION_NETWORK 0x6911
+ #define OPTION_PRODUCT_ETNA_MODEM 0x7001
+-#define OPTION_PRODUCT_ETNA_NETWORK 0x7011
+ #define OPTION_PRODUCT_ETNA_MODEM_LITE 0x7021
+ #define OPTION_PRODUCT_ETNA_MODEM_GT 0x7041
+ #define OPTION_PRODUCT_ETNA_MODEM_EX 0x7061
+-#define OPTION_PRODUCT_ETNA_NETWORK_LITE 0x7031
+-#define OPTION_PRODUCT_ETNA_NETWORK_GT 0x7051
+-#define OPTION_PRODUCT_ETNA_NETWORK_EX 0x7071
+ #define OPTION_PRODUCT_ETNA_KOI_MODEM 0x7100
+-#define OPTION_PRODUCT_ETNA_KOI_NETWORK 0x7111
++#define OPTION_PRODUCT_GTM380_MODEM 0x7201
+
+ #define HUAWEI_VENDOR_ID 0x12D1
+ #define HUAWEI_PRODUCT_E600 0x1001
+ #define HUAWEI_PRODUCT_E220 0x1003
+ #define HUAWEI_PRODUCT_E220BIS 0x1004
++#define HUAWEI_PRODUCT_E1401 0x1401
++#define HUAWEI_PRODUCT_E1402 0x1402
++#define HUAWEI_PRODUCT_E1403 0x1403
++#define HUAWEI_PRODUCT_E1404 0x1404
++#define HUAWEI_PRODUCT_E1405 0x1405
++#define HUAWEI_PRODUCT_E1406 0x1406
++#define HUAWEI_PRODUCT_E1407 0x1407
++#define HUAWEI_PRODUCT_E1408 0x1408
++#define HUAWEI_PRODUCT_E1409 0x1409
++#define HUAWEI_PRODUCT_E140A 0x140A
++#define HUAWEI_PRODUCT_E140B 0x140B
++#define HUAWEI_PRODUCT_E140C 0x140C
++#define HUAWEI_PRODUCT_E140D 0x140D
++#define HUAWEI_PRODUCT_E140E 0x140E
++#define HUAWEI_PRODUCT_E140F 0x140F
++#define HUAWEI_PRODUCT_E1410 0x1410
++#define HUAWEI_PRODUCT_E1411 0x1411
++#define HUAWEI_PRODUCT_E1412 0x1412
++#define HUAWEI_PRODUCT_E1413 0x1413
++#define HUAWEI_PRODUCT_E1414 0x1414
++#define HUAWEI_PRODUCT_E1415 0x1415
++#define HUAWEI_PRODUCT_E1416 0x1416
++#define HUAWEI_PRODUCT_E1417 0x1417
++#define HUAWEI_PRODUCT_E1418 0x1418
++#define HUAWEI_PRODUCT_E1419 0x1419
++#define HUAWEI_PRODUCT_E141A 0x141A
++#define HUAWEI_PRODUCT_E141B 0x141B
++#define HUAWEI_PRODUCT_E141C 0x141C
++#define HUAWEI_PRODUCT_E141D 0x141D
++#define HUAWEI_PRODUCT_E141E 0x141E
++#define HUAWEI_PRODUCT_E141F 0x141F
++#define HUAWEI_PRODUCT_E1420 0x1420
++#define HUAWEI_PRODUCT_E1421 0x1421
++#define HUAWEI_PRODUCT_E1422 0x1422
++#define HUAWEI_PRODUCT_E1423 0x1423
++#define HUAWEI_PRODUCT_E1424 0x1424
++#define HUAWEI_PRODUCT_E1425 0x1425
++#define HUAWEI_PRODUCT_E1426 0x1426
++#define HUAWEI_PRODUCT_E1427 0x1427
++#define HUAWEI_PRODUCT_E1428 0x1428
++#define HUAWEI_PRODUCT_E1429 0x1429
++#define HUAWEI_PRODUCT_E142A 0x142A
++#define HUAWEI_PRODUCT_E142B 0x142B
++#define HUAWEI_PRODUCT_E142C 0x142C
++#define HUAWEI_PRODUCT_E142D 0x142D
++#define HUAWEI_PRODUCT_E142E 0x142E
++#define HUAWEI_PRODUCT_E142F 0x142F
++#define HUAWEI_PRODUCT_E1430 0x1430
++#define HUAWEI_PRODUCT_E1431 0x1431
++#define HUAWEI_PRODUCT_E1432 0x1432
++#define HUAWEI_PRODUCT_E1433 0x1433
++#define HUAWEI_PRODUCT_E1434 0x1434
++#define HUAWEI_PRODUCT_E1435 0x1435
++#define HUAWEI_PRODUCT_E1436 0x1436
++#define HUAWEI_PRODUCT_E1437 0x1437
++#define HUAWEI_PRODUCT_E1438 0x1438
++#define HUAWEI_PRODUCT_E1439 0x1439
++#define HUAWEI_PRODUCT_E143A 0x143A
++#define HUAWEI_PRODUCT_E143B 0x143B
++#define HUAWEI_PRODUCT_E143C 0x143C
++#define HUAWEI_PRODUCT_E143D 0x143D
++#define HUAWEI_PRODUCT_E143E 0x143E
++#define HUAWEI_PRODUCT_E143F 0x143F
++
++#define QUANTA_VENDOR_ID 0x0408
++#define QUANTA_PRODUCT_Q101 0xEA02
++#define QUANTA_PRODUCT_Q111 0xEA03
++#define QUANTA_PRODUCT_GLX 0xEA04
++#define QUANTA_PRODUCT_GKE 0xEA05
++#define QUANTA_PRODUCT_GLE 0xEA06
+
+ #define NOVATELWIRELESS_VENDOR_ID 0x1410
++
++/* YISO PRODUCTS */
++
++#define YISO_VENDOR_ID 0x0EAB
++#define YISO_PRODUCT_U893 0xC893
++
++/* MERLIN EVDO PRODUCTS */
++#define NOVATELWIRELESS_PRODUCT_V640 0x1100
++#define NOVATELWIRELESS_PRODUCT_V620 0x1110
++#define NOVATELWIRELESS_PRODUCT_V740 0x1120
++#define NOVATELWIRELESS_PRODUCT_V720 0x1130
++
++/* MERLIN HSDPA/HSPA PRODUCTS */
++#define NOVATELWIRELESS_PRODUCT_U730 0x1400
++#define NOVATELWIRELESS_PRODUCT_U740 0x1410
++#define NOVATELWIRELESS_PRODUCT_U870 0x1420
++#define NOVATELWIRELESS_PRODUCT_XU870 0x1430
++#define NOVATELWIRELESS_PRODUCT_X950D 0x1450
++
++/* EXPEDITE PRODUCTS */
++#define NOVATELWIRELESS_PRODUCT_EV620 0x2100
++#define NOVATELWIRELESS_PRODUCT_ES720 0x2110
++#define NOVATELWIRELESS_PRODUCT_E725 0x2120
++#define NOVATELWIRELESS_PRODUCT_ES620 0x2130
++#define NOVATELWIRELESS_PRODUCT_EU730 0x2400
++#define NOVATELWIRELESS_PRODUCT_EU740 0x2410
++#define NOVATELWIRELESS_PRODUCT_EU870D 0x2420
++
++/* OVATION PRODUCTS */
++#define NOVATELWIRELESS_PRODUCT_MC727 0x4100
++#define NOVATELWIRELESS_PRODUCT_MC950D 0x4400
++#define NOVATELWIRELESS_PRODUCT_U727 0x5010
++#define NOVATELWIRELESS_PRODUCT_MC760 0x6000
++
++/* FUTURE NOVATEL PRODUCTS */
++#define NOVATELWIRELESS_PRODUCT_EVDO_HIGHSPEED 0X6001
++#define NOVATELWIRELESS_PRODUCT_HSPA_FULLSPEED 0X7000
++#define NOVATELWIRELESS_PRODUCT_HSPA_HIGHSPEED 0X7001
++#define NOVATELWIRELESS_PRODUCT_EVDO_EMBEDDED_FULLSPEED 0X8000
++#define NOVATELWIRELESS_PRODUCT_EVDO_EMBEDDED_HIGHSPEED 0X8001
++#define NOVATELWIRELESS_PRODUCT_HSPA_EMBEDDED_FULLSPEED 0X9000
++#define NOVATELWIRELESS_PRODUCT_HSPA_EMBEDDED_HIGHSPEED 0X9001
++#define NOVATELWIRELESS_PRODUCT_GLOBAL 0XA001
++
++/* AMOI PRODUCTS */
++#define AMOI_VENDOR_ID 0x1614
++#define AMOI_PRODUCT_H01 0x0800
++#define AMOI_PRODUCT_H01A 0x7002
++#define AMOI_PRODUCT_H02 0x0802
++
+ #define DELL_VENDOR_ID 0x413C
+
++/* Dell modems */
++#define DELL_PRODUCT_5700_MINICARD 0x8114
++#define DELL_PRODUCT_5500_MINICARD 0x8115
++#define DELL_PRODUCT_5505_MINICARD 0x8116
++#define DELL_PRODUCT_5700_EXPRESSCARD 0x8117
++#define DELL_PRODUCT_5510_EXPRESSCARD 0x8118
++
++#define DELL_PRODUCT_5700_MINICARD_SPRINT 0x8128
++#define DELL_PRODUCT_5700_MINICARD_TELUS 0x8129
++
++#define DELL_PRODUCT_5720_MINICARD_VZW 0x8133
++#define DELL_PRODUCT_5720_MINICARD_SPRINT 0x8134
++#define DELL_PRODUCT_5720_MINICARD_TELUS 0x8135
++#define DELL_PRODUCT_5520_MINICARD_CINGULAR 0x8136
++#define DELL_PRODUCT_5520_MINICARD_GENERIC_L 0x8137
++#define DELL_PRODUCT_5520_MINICARD_GENERIC_I 0x8138
++
++#define DELL_PRODUCT_5730_MINICARD_SPRINT 0x8180
++#define DELL_PRODUCT_5730_MINICARD_TELUS 0x8181
++#define DELL_PRODUCT_5730_MINICARD_VZW 0x8182
++
++#define KYOCERA_VENDOR_ID 0x0c88
++#define KYOCERA_PRODUCT_KPC650 0x17da
++#define KYOCERA_PRODUCT_KPC680 0x180a
++
+ #define ANYDATA_VENDOR_ID 0x16d5
++#define ANYDATA_PRODUCT_ADU_620UW 0x6202
+ #define ANYDATA_PRODUCT_ADU_E100A 0x6501
+ #define ANYDATA_PRODUCT_ADU_500A 0x6502
+
++#define AXESSTEL_VENDOR_ID 0x1726
++#define AXESSTEL_PRODUCT_MV110H 0x1000
++
++#define ONDA_VENDOR_ID 0x19d2
++#define ONDA_PRODUCT_MSA501HS 0x0001
++#define ONDA_PRODUCT_ET502HS 0x0002
++#define ONDA_PRODUCT_MT503HS 0x2000
++
+ #define BANDRICH_VENDOR_ID 0x1A8D
+ #define BANDRICH_PRODUCT_C100_1 0x1002
+ #define BANDRICH_PRODUCT_C100_2 0x1003
++#define BANDRICH_PRODUCT_1004 0x1004
++#define BANDRICH_PRODUCT_1005 0x1005
++#define BANDRICH_PRODUCT_1006 0x1006
++#define BANDRICH_PRODUCT_1007 0x1007
++#define BANDRICH_PRODUCT_1008 0x1008
++#define BANDRICH_PRODUCT_1009 0x1009
++#define BANDRICH_PRODUCT_100A 0x100a
++
++#define BANDRICH_PRODUCT_100B 0x100b
++#define BANDRICH_PRODUCT_100C 0x100c
++#define BANDRICH_PRODUCT_100D 0x100d
++#define BANDRICH_PRODUCT_100E 0x100e
++
++#define BANDRICH_PRODUCT_100F 0x100f
++#define BANDRICH_PRODUCT_1010 0x1010
++#define BANDRICH_PRODUCT_1011 0x1011
++#define BANDRICH_PRODUCT_1012 0x1012
++
++#define AMOI_VENDOR_ID 0x1614
++#define AMOI_PRODUCT_9508 0x0800
++
++#define QUALCOMM_VENDOR_ID 0x05C6
++
++#define MAXON_VENDOR_ID 0x16d8
++
++#define TELIT_VENDOR_ID 0x1bc7
++#define TELIT_PRODUCT_UC864E 0x1003
++
++/* ZTE PRODUCTS */
++#define ZTE_VENDOR_ID 0x19d2
++#define ZTE_PRODUCT_MF622 0x0001
++#define ZTE_PRODUCT_MU350 0x0003
++#define ZTE_PRODUCT_MF628 0x0015
++#define ZTE_PRODUCT_MF626 0x0031
++#define ZTE_PRODUCT_AC560 0x0073
++#define ZTE_PRODUCT_CDMA_TECH 0xfffe
++
++#define BENQ_VENDOR_ID 0x04a5
++#define BENQ_PRODUCT_H10 0x4068
++
++#define DLINK_VENDOR_ID 0x1186
++#define DLINK_PRODUCT_DWM_652 0x3e04
++
++#define DTT_VENDOR_ID 0x1ab7
++#define DTT_PRODUCT_AIRCARD_901 0x2000
++
++/* TOSHIBA PRODUCTS */
++#define TOSHIBA_VENDOR_ID 0x0930
++#define TOSHIBA_PRODUCT_HSDPA_MINICARD 0x1302
+
+ static struct usb_device_id option_ids[] = {
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },
+@@ -136,56 +329,213 @@ static struct usb_device_id option_ids[] = {
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_VIPER) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_VIPER_BUS) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_GT_MAX_READY) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_GT_MAX) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_FUJI_MODEM_LIGHT) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_FUJI_MODEM_GT) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_FUJI_MODEM_EX) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_FUJI_NETWORK_LIGHT) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_FUJI_NETWORK_GT) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_FUJI_NETWORK_EX) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_KOI_MODEM) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_KOI_NETWORK) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_SCORPION_MODEM) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_SCORPION_NETWORK) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_NETWORK) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM_LITE) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM_GT) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM_EX) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_NETWORK_LITE) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_NETWORK_GT) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_NETWORK_EX) },
+ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_KOI_MODEM) },
+- { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_KOI_NETWORK) },
+- { USB_DEVICE(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E600) },
++ { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_GTM380_MODEM) },
++ { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_Q101) },
++ { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_Q111) },
++ { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_GLX) },
++ { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_GKE) },
++ { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_GLE) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E600, 0xff, 0xff, 0xff) },
+ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E220, 0xff, 0xff, 0xff) },
+ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E220BIS, 0xff, 0xff, 0xff) },
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1100) }, /* Novatel Merlin XS620/S640 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1110) }, /* Novatel Merlin S620 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1120) }, /* Novatel Merlin EX720 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1130) }, /* Novatel Merlin S720 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1400) }, /* Novatel U730 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1410) }, /* Novatel U740 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1420) }, /* Novatel EU870 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x1430) }, /* Novatel Merlin XU870 HSDPA/3G */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x2100) }, /* Novatel EV620 CDMA/EV-DO */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x2110) }, /* Novatel Merlin ES620 / Merlin ES720 / Ovation U720 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x2130) }, /* Novatel Merlin ES620 SM Bus */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x2410) }, /* Novatel EU740 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x4100) }, /* Novatel U727 */
+- { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, 0x4400) }, /* Novatel MC950 */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8114) }, /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO Mini-Card == Novatel Expedite EV620 CDMA/EV-DO */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8115) }, /* Dell Wireless 5500 Mobile Broadband HSDPA Mini-Card == Novatel Expedite EU740 HSDPA/3G */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8116) }, /* Dell Wireless 5505 Mobile Broadband HSDPA Mini-Card == Novatel Expedite EU740 HSDPA/3G */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8117) }, /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO ExpressCard == Novatel Merlin XV620 CDMA/EV-DO */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8118) }, /* Dell Wireless 5510 Mobile Broadband HSDPA ExpressCard == Novatel Merlin XU870 HSDPA/3G */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8128) }, /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO Mini-Card == Novatel Expedite E720 CDMA/EV-DO */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8136) }, /* Dell Wireless HSDPA 5520 == Novatel Expedite EU860D */
+- { USB_DEVICE(DELL_VENDOR_ID, 0x8137) }, /* Dell Wireless HSDPA 5520 */
+- { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_E100A) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1401, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1402, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1403, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1404, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1405, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1406, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1407, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1408, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1409, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E140A, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E140B, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E140C, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E140D, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E140E, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E140F, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1410, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1411, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1412, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1413, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1414, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1415, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1416, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1417, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1418, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1419, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E141A, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E141B, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E141C, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E141D, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E141E, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E141F, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1420, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1421, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1422, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1423, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1424, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1425, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1426, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1427, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1428, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1429, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E142A, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E142B, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E142C, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E142D, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E142E, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E142F, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1430, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1431, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1432, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1433, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1434, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1435, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1436, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1437, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1438, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E1439, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143A, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143B, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143C, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143D, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143E, 0xff, 0xff, 0xff) },
++ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E143F, 0xff, 0xff, 0xff) },
++ { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_9508) },
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V640) }, /* Novatel Merlin V640/XV620 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V620) }, /* Novatel Merlin V620/S620 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V740) }, /* Novatel Merlin EX720/V740/X720 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V720) }, /* Novatel Merlin V720/S720/PC720 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_U730) }, /* Novatel U730/U740 (VF version) */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_U740) }, /* Novatel U740 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_U870) }, /* Novatel U870 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_XU870) }, /* Novatel Merlin XU870 HSDPA/3G */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_X950D) }, /* Novatel X950D */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EV620) }, /* Novatel EV620/ES620 CDMA/EV-DO */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_ES720) }, /* Novatel ES620/ES720/U720/USB720 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_E725) }, /* Novatel E725/E726 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_ES620) }, /* Novatel Merlin ES620 SM Bus */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EU730) }, /* Novatel EU730 and Vodafone EU740 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EU740) }, /* Novatel non-Vodafone EU740 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EU870D) }, /* Novatel EU850D/EU860D/EU870D */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC950D) }, /* Novatel MC930D/MC950D */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC727) }, /* Novatel MC727/U727/USB727 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_U727) }, /* Novatel MC727/U727/USB727 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC760) }, /* Novatel MC760/U760/USB760 */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_FULLSPEED) }, /* Novatel HSPA product */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_EMBEDDED_FULLSPEED) }, /* Novatel EVDO Embedded product */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_EMBEDDED_FULLSPEED) }, /* Novatel HSPA Embedded product */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_HIGHSPEED) }, /* Novatel EVDO product */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_HIGHSPEED) }, /* Novatel HSPA product */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_EMBEDDED_HIGHSPEED) }, /* Novatel EVDO Embedded product */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_EMBEDDED_HIGHSPEED) }, /* Novatel HSPA Embedded product */
++ { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_GLOBAL) }, /* Novatel Global product */
++
++ { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_H01) },
++ { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_H01A) },
++ { USB_DEVICE(AMOI_VENDOR_ID, AMOI_PRODUCT_H02) },
++
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5700_MINICARD) }, /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO Mini-Card == Novatel Expedite EV620 CDMA/EV-DO */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5500_MINICARD) }, /* Dell Wireless 5500 Mobile Broadband HSDPA Mini-Card == Novatel Expedite EU740 HSDPA/3G */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5505_MINICARD) }, /* Dell Wireless 5505 Mobile Broadband HSDPA Mini-Card == Novatel Expedite EU740 HSDPA/3G */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5700_EXPRESSCARD) }, /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO ExpressCard == Novatel Merlin XV620 CDMA/EV-DO */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5510_EXPRESSCARD) }, /* Dell Wireless 5510 Mobile Broadband HSDPA ExpressCard == Novatel Merlin XU870 HSDPA/3G */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5700_MINICARD_SPRINT) }, /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO Mini-Card == Novatel Expedite E720 CDMA/EV-DO */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5700_MINICARD_TELUS) }, /* Dell Wireless 5700 Mobile Broadband CDMA/EVDO Mini-Card == Novatel Expedite ET620 CDMA/EV-DO */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5720_MINICARD_VZW) }, /* Dell Wireless 5720 == Novatel EV620 CDMA/EV-DO */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5720_MINICARD_SPRINT) }, /* Dell Wireless 5720 == Novatel EV620 CDMA/EV-DO */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5720_MINICARD_TELUS) }, /* Dell Wireless 5720 == Novatel EV620 CDMA/EV-DO */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_CINGULAR) }, /* Dell Wireless HSDPA 5520 == Novatel Expedite EU860D */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_GENERIC_L) }, /* Dell Wireless HSDPA 5520 */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_GENERIC_I) }, /* Dell Wireless 5520 Voda I Mobile Broadband (3G HSDPA) Minicard */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_SPRINT) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_TELUS) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */
++ { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_VZW) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */
++ { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_E100A) }, /* ADU-E100, ADU-310 */
+ { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_500A) },
++ { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_620UW) },
++ { USB_DEVICE(AXESSTEL_VENDOR_ID, AXESSTEL_PRODUCT_MV110H) },
++ /*{ USB_DEVICE(ONDA_VENDOR_ID, ONDA_PRODUCT_MSA501HS) },
++ { USB_DEVICE(ONDA_VENDOR_ID, ONDA_PRODUCT_ET502HS) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0003) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0004) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0005) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0006) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0007) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0008) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0009) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x000a) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x000b) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x000c) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x000d) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x000e) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x000f) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0010) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0011) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0012) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0013) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0014) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0015) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0016) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0017) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0018) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0019) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0020) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0021) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0022) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0023) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0024) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0025) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0026) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0027) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0028) },
++ { USB_DEVICE(ONDA_VENDOR_ID, 0x0029) },
++ { USB_DEVICE(ONDA_VENDOR_ID, ONDA_PRODUCT_MT503HS) }, */
++ { USB_DEVICE(YISO_VENDOR_ID, YISO_PRODUCT_U893) },
+ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_C100_1) },
+ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_C100_2) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1004) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1005) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1006) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1007) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1008) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1009) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_100A) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_100B) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_100C) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_100D) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_100E) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_100F) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1010) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1011) },
++ { USB_DEVICE(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1012) },
++ { USB_DEVICE(KYOCERA_VENDOR_ID, KYOCERA_PRODUCT_KPC650) },
++ { USB_DEVICE(KYOCERA_VENDOR_ID, KYOCERA_PRODUCT_KPC680) },
++ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6000)}, /* ZTE AC8700 */
++ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6613)}, /* Onda H600/ZTE MF330 */
++ { USB_DEVICE(MAXON_VENDOR_ID, 0x6280) }, /* BP3-USB & BP3-EXT HSDPA */
++ { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864E) },
++ { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF622) },
++ { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MU350) },
++ { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF626) },
++ { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_AC560) },
++ { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF628) },
++ { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_CDMA_TECH) },
++ { USB_DEVICE(BENQ_VENDOR_ID, BENQ_PRODUCT_H10) },
++ { USB_DEVICE(DLINK_VENDOR_ID, DLINK_PRODUCT_DWM_652) },
++ { USB_DEVICE(DTT_VENDOR_ID, DTT_PRODUCT_AIRCARD_901) },
++ { USB_DEVICE(0x1da5, 0x4515) }, /* BenQ H20 */
++ { USB_DEVICE(TOSHIBA_VENDOR_ID, TOSHIBA_PRODUCT_HSDPA_MINICARD ) }, /* Toshiba 3G HSDPA == Novatel Expedite EU870D MiniCard */
+ { } /* Terminating entry */
+ };
+ MODULE_DEVICE_TABLE(usb, option_ids);
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index 4212cd0..ae66ace 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -231,6 +231,16 @@ config FB_S3C_LTS222QV
+ ---help---
+ TBA
+
++config FB_S3C_A070VW04
++ bool "A070VW04"
++ ---help---
++ TBA
++
++config FB_S3C_TD043MTEX
++ bool "TD043MTEX"
++ ---help---
++ TBA
++
+ endchoice
+
+ config FB_S3C_BPP
+diff --git a/drivers/video/s3c/Makefile b/drivers/video/s3c/Makefile
+index 3f52d72..cb6c218 100644
+--- a/drivers/video/s3c/Makefile
++++ b/drivers/video/s3c/Makefile
+@@ -9,4 +9,6 @@ obj-$(CONFIG_PLAT_S5PC1XX) += s5pfb_fimd5x.o
+ obj-$(CONFIG_FB_S3C_LTS222QV) += s3cfb_lts222qv.o
+ obj-$(CONFIG_FB_S3C_LTV350QV) += s3cfb_ltv350qv.o
+ obj-$(CONFIG_FB_S3C_LTE480WV) += s3cfb_lte480wv.o
++obj-$(CONFIG_FB_S3C_A070VW04) += s3cfb_a070vw04.o
++obj-$(CONFIG_FB_S3C_TD043MTEX) += s3cfb_td043mtex.o
+
+diff --git a/drivers/video/s3c/colorbar.c b/drivers/video/s3c/colorbar.c
+new file mode 100644
+index 0000000..69e7400
+--- /dev/null
++++ b/drivers/video/s3c/colorbar.c
+@@ -0,0 +1,423 @@
++/****************************************************************
++ * $ID: colorbar.c Sun, 23 Dec 2007 21:01:11 +0800 mhfan $ *
++ * *
++ * Description: *
++ * *
++ * Maintainer: ·¶ÃÀ»Ô(MeiHui FAN) <mhfan@hhcn.com> *
++ * *
++ * Copyright (C) 2007~2008 HHTech *
++ * www.hhcn.com, www.hhcn.org *
++ * All rights reserved. *
++ * *
++ * This file is free software; *
++ * you are free to modify and/or redistribute it *
++ * under the terms of the GNU General Public Licence (GPL). *
++ ****************************************************************/
++
++
++static inline void memset32(uint32_t* ptr, uint32_t val, int32_t siz)
++{
++ for (siz >>= 4; 0 < siz--; ptr += 4) {
++ ptr[0] = val; ptr[1] = val; ptr[2] = val; ptr[3] = val;
++ }
++}
++
++
++#define UYVY_WHITE (0xEB80EB80)
++#define UYVY_YELLOW (0xD292D210)
++#define UYVY_CYAN (0xAA10AAA6)
++#define UYVY_GREEN (0x91229136)
++#define UYVY_MAGENTA (0x6ADE6ACA)
++#define UYVY_RED (0x51F0515A)
++#define UYVY_BLUE (0x296E29F0)
++#define UYVY_BLACK (0x10801080)
++
++
++#ifdef CONFIG_ITU656_OUTPUT
++#ifdef NTSC
++#define FIELD1_VBL_START (1)
++#define FIELD1_VBL_FINISH (20)
++#define FIELD2_VBL_START (264)
++#define FIELD2_VBL_FINISH (283)
++#define FIELD1_START_LINE (4)
++#define FIELD2_START_LINE (266)
++
++#define LINES_PER_VBL (20) // XXX: 19.5
++#define LINES_PER_FIELD (243)
++#define LINES_PER_FRAME (525)
++
++#define LINE_BLANK_BYTES (268)
++#define FRAMES_PER_SECOND (30)
++
++#elif defined(PAL)
++
++#define FIELD1_VBL_START (624)
++#define FIELD1_VBL_FINISH (23)
++#define FIELD2_VBL_START (311)
++#define FIELD2_VBL_FINISH (336)
++#define FIELD1_START_LINE (1)
++#define FIELD2_START_LINE (313)
++
++#define LINES_PER_VBL (24) // XXX: 24.5
++#define LINES_PER_FIELD (288)
++#define LINES_PER_FRAME (625)
++
++#define LINE_BLANK_BYTES (280)
++#define FRAMES_PER_SECOND (25)
++
++#else
++#error "Please define `NTSC' or `PAL'!"
++#endif//NTSC
++
++#ifdef ACTIVE_VIDEO_ONLY
++#undef LINES_PER_FRAME
++#undef FIELD1_VBL_START
++#undef FIELD2_VBL_START
++#undef FIELD1_VBL_FINISH
++#undef FIELD2_VBL_FINISH
++#undef FIELD1_START_LINE
++#undef FIELD2_START_LINE
++#undef LINE_BLANK_BYTES
++#undef LINES_PER_VBL
++
++#define FIELD1_VBL_START (0)
++#define FIELD2_VBL_START (0)
++#define FIELD1_VBL_FINISH (0)
++#define FIELD2_VBL_FINISH (0)
++#define FIELD1_START_LINE (1)
++#define FIELD2_START_LINE (289)
++#define LINE_BLANK_BYTES (0)
++#define LINES_PER_VBL (0)
++
++#define LINES_PER_FRAME (FRAME_ACTIVE_LINES)
++#define SAV_BYTES (0)
++#define EAV_BYTES (0)
++
++#else// XXX:
++#define SAV_BYTES (4)
++#define EAV_BYTES (4)
++#endif//ACTIVE_VIDEO_ONLY
++
++#define BITS_PER_PIXEL (16)
++#define PIXELS_PER_LINE (720)
++
++#define FRAME_ACTIVE_LINES (LINES_PER_FIELD << 1)
++#define LINE_ACTIVE_BYTES (PIXELS_PER_LINE << 1)
++#define BYTES_PER_PIXEL ((BITS_PER_PIXEL + 7) >> 3)
++#define LINE_CONTROL_BYTES (SAV_BYTES + LINE_BLANK_BYTES + EAV_BYTES)
++#define BYTES_PER_LINE (LINE_CONTROL_BYTES + (PIXELS_PER_LINE << 1))
++#define BYTES_PER_FIELD (BYTES_PER_LINE * LINES_PER_FIELD)
++#define BYTES_PER_FRAME (BYTES_PER_LINE * LINES_PER_FRAME)
++
++static inline unsigned* itu656_line(unsigned* ptr, int init)
++{
++/*
++ * Offsets for ITU656/CCIR601 frame line definition:
++ *
++ * |<--EAV-->|<----BLANKING---->|<--SAV-->|<--------ACTIVE FIELD-------->|
++ * 4 268/280 4 1440
++ */
++ short i;
++#ifdef ACTIVE_VIDEO_ONLY
++ short V = 0;
++#else
++ static short L = 0, V = 1, F = 1;
++
++ switch (++L) {
++ // F-digital field identification:
++ case FIELD1_START_LINE : F = 0; break;
++ case FIELD2_START_LINE : F = 1; break;
++ // V-digital field blanking:
++ case FIELD1_VBL_START : V = 1; break;
++ case FIELD1_VBL_FINISH : V = 0; break;
++ case FIELD2_VBL_START : V = 1; break;
++ case FIELD2_VBL_FINISH : V = 0; break;
++ // finished a frame:
++ case LINES_PER_FRAME : L = 0; break;
++ }
++
++ // End Active Video (EAV):
++ *ptr++ = F ? (V ? 0xF10000FF : 0xDA0000FF) :
++ (V ? 0xB60000FF : 0x9D0000FF);
++
++ // Blanking Code:
++ if (init) for (i = (LINE_BLANK_BYTES >> 2) + 1; --i; )
++ *ptr++ = UYVY_BLACK;
++ else ptr += (LINE_BLANK_BYTES >> 2);
++
++ // Start Active Video (SAV):
++ *ptr++ = F ? (V ? 0xEC0000FF : 0xC70000FF) :
++ (V ? 0xAB0000FF : 0x800000FF);
++#endif//ACTIVE_VIDEO_ONLY
++
++ if (init) {
++ if (V) { // Video Blanking Line:
++ for (i = (LINE_ACTIVE_BYTES >> 2) + 1; --i; )
++ *ptr++ = UYVY_BLACK;
++ } else { // Active Video Line Code:
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_WHITE;
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_YELLOW;
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_CYAN;
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_GREEN;
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_MAGENTA;
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_RED;
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_BLUE;
++ for (i = ((LINE_ACTIVE_BYTES >> 2) >> 3) + 1; --i; )
++ *ptr++ = UYVY_BLACK;
++ }
++ } else ptr += (LINE_ACTIVE_BYTES >> 2);
++
++ return ptr;
++}
++#endif//CONFIG_ITU656_OUTPUT
++
++#ifdef CONFIG_FB_COLORBAR
++void __init draw_colorbar(struct fb_info* fbi)
++{
++ u16 s, r, w, h;
++ u32* pixels = (u32*)fbi->screen_base;
++ struct fb_var_screeninfo* var = &fbi->var;
++
++#define HORIZON_LINES (2)
++#define CURSOR_PIXELS (32)
++
++ printk("var->nonstd:%d, var->bits_per_pixel:%d\n", var->nonstd, var->bits_per_pixel);
++ if(var->bits_per_pixel == 24) var->bits_per_pixel = 32;
++ if (var->nonstd/* == FB_PIXEL_YUV*/) {
++ for (s = (var->xres >> 1) + 1, h = HORIZON_LINES + 1; --h; )
++ for (w = s; --w; ) *pixels++ = UYVY_BLUE; // margin
++
++ s = (var->xres >> 4) + 1, r = ((var->xres - ((s - 1) << 4)) >> 1);
++ for (h = var->yres - (HORIZON_LINES << 1) + 1; --h; ) {
++ for (w = s; --w; ) *pixels++ = UYVY_RED;
++ for (w = s; --w; ) *pixels++ = UYVY_GREEN;
++ for (w = s; --w; ) *pixels++ = UYVY_BLUE;
++ for (w = s; --w; ) *pixels++ = UYVY_BLACK;
++ for (w = s; --w; ) *pixels++ = UYVY_WHITE;
++ for (w = s; --w; ) *pixels++ = UYVY_YELLOW;
++ for (w = s; --w; ) *pixels++ = UYVY_MAGENTA;
++ for (w = s; --w; ) *pixels++ = UYVY_CYAN;
++ pixels += r;
++ }
++
++ for (s = (var->xres >> 1) + 1, h = HORIZON_LINES + 1; --h; )
++ for (w = s; --w; ) *pixels++ = UYVY_YELLOW;// margin
++ } else
++
++ if (var->bits_per_pixel < 9) /*dtrace*/; else
++ if (var->bits_per_pixel < 17) {
++ for (s = (var->xres >> 1) + 1, h = HORIZON_LINES + 1; --h; )
++ for (w = s; --w; ) *pixels++ = 0x001f001f; // Blue margin
++
++ s = (var->xres >> 4) + 1, r = ((var->xres - ((s - 1) << 4)) >> 1);
++ for (h = var->yres - (HORIZON_LINES << 1) + 1; --h; ) {
++ for (w = s; --w; ) *pixels++ = 0xf800f800; // Red
++ for (w = s; --w; ) *pixels++ = 0x07e007e0; // Green
++ for (w = s; --w; ) *pixels++ = 0x001f001f; // Blue
++ for (w = s; --w; ) *pixels++ = 0x00000000; // Black
++ for (w = s; --w; ) *pixels++ = 0xffffffff; // White
++ for (w = s; --w; ) *pixels++ = 0xffe0ffe0; // R + G
++ for (w = s; --w; ) *pixels++ = 0x07ff07ff; // G + B
++ for (w = s; --w; ) *pixels++ = 0xf81ff81f; // B + R
++ pixels += r;
++ }
++
++ for (s = (var->xres >> 1) + 1, h = HORIZON_LINES + 1; --h; )
++ for (w = s; --w; ) *pixels++ = 0xffe0ffe0; // Yellow
++ } else
++
++ if (var->bits_per_pixel < 25) {
++ for (s = (var->xres >> 2) + 1, h = HORIZON_LINES + 1; --h; ) {
++ for (w = s; --w; ) *pixels++ = 0x00ff0000, // Blue margin
++ *pixels++ = 0x0000ff00, *pixels++ = 0xff0000ff;
++#ifndef CONFIG_DELTA_LCD
++continue;
++#endif
++ --h; // even line:
++ for (w = s; --w; ) *pixels++ = 0x0000ff00, // Green
++ *pixels++ = 0xff0000ff, *pixels++ = 0x00ff0000;
++ }
++
++ s = (var->xres >> 5) + 1;
++ r = (((var->xres - ((s - 1) << 5)) * 3) >> 2);
++ for (h = var->yres - (HORIZON_LINES << 1) + 1; --h; ) {
++#if 0
++ unsigned t = 0xff - h;
++ for (w = s; --w; ) *pixels++ = 0x01000001 * t,
++ *pixels++ = 0x00010000 * t, *pixels++ = 0x00000100 * t;
++ for (w = s; --w; ) *pixels++ = 0x00000100 * t,
++ *pixels++ = 0x01000001 * t, *pixels++ = 0x00010000 * t;
++ for (w = s; --w; ) *pixels++ = 0x00010000 * t,
++ *pixels++ = 0x00000100 * t, *pixels++ = 0x01000001 * t;
++ for (w = s; --w; ) *pixels++ = 0x00000000 * t,
++ *pixels++ = 0x00000000 * t, *pixels++ = 0x00000000 * t;
++ for (w = s; --w; ) *pixels++ = 0x01010101 * t,
++ *pixels++ = 0x01010101 * t, *pixels++ = 0x01010101 * t;
++ for (w = s; --w; ) *pixels++ = 0x01000101 * t,
++ *pixels++ = 0x01010001 * t, *pixels++ = 0x00010100 * t;
++ for (w = s; --w; ) *pixels++ = 0x00010100 * t,
++ *pixels++ = 0x01000101 * t, *pixels++ = 0x01010001 * t;
++ for (w = s; --w; ) *pixels++ = 0x01010001 * t,
++ *pixels++ = 0x00010100 * t, *pixels++ = 0x01000101 * t;
++#else
++ for (w = s; --w; ) *pixels++ = 0xff0000ff, // Red
++ *pixels++ = 0x00ff0000, *pixels++ = 0x0000ff00;
++ for (w = s; --w; ) *pixels++ = 0x0000ff00, // Green
++ *pixels++ = 0xff0000ff, *pixels++ = 0x00ff0000;
++ for (w = s; --w; ) *pixels++ = 0x00ff0000, // Blue
++ *pixels++ = 0x0000ff00, *pixels++ = 0xff0000ff;
++ for (w = s; --w; ) *pixels++ = 0x00000000, // Black
++ *pixels++ = 0x00000000, *pixels++ = 0x00000000;
++ for (w = s; --w; ) *pixels++ = 0xffffffff, // White
++ *pixels++ = 0xffffffff, *pixels++ = 0xffffffff;
++ for (w = s; --w; ) *pixels++ = 0xff00ffff, // R + G
++ *pixels++ = 0xffff00ff, *pixels++ = 0x00ffff00;
++ for (w = s; --w; ) *pixels++ = 0x00ffff00, // G + B
++ *pixels++ = 0xff00ffff, *pixels++ = 0xffff00ff;
++ for (w = s; --w; ) *pixels++ = 0xffff00ff, // B + R
++ *pixels++ = 0x00ffff00, *pixels++ = 0xff00ffff;
++#endif
++ pixels += r;
++#ifndef CONFIG_DELTA_LCD
++continue; // The colorbar sequence is according the first line.
++#endif
++ --h; // even line:
++
++#if 0
++ t = 0xff - h;
++ for (w = s; --w; ) *pixels++ = 0x00010000 * t,
++ *pixels++ = 0x00000100 * t, *pixels++ = 0x01000001 * t;
++ for (w = s; --w; ) *pixels++ = 0x01000001 * t,
++ *pixels++ = 0x00010000 * t, *pixels++ = 0x00000100 * t;
++ for (w = s; --w; ) *pixels++ = 0x00000100 * t,
++ *pixels++ = 0x01000001 * t, *pixels++ = 0x00010000 * t;
++ for (w = s; --w; ) *pixels++ = 0x00000000 * t,
++ *pixels++ = 0x00000000 * t, *pixels++ = 0x00000000 * t;
++ for (w = s; --w; ) *pixels++ = 0x01010101 * t,
++ *pixels++ = 0x01010101 * t, *pixels++ = 0x01010101 * t;
++ for (w = s; --w; ) *pixels++ = 0x01010001 * t,
++ *pixels++ = 0x00010100 * t, *pixels++ = 0x01000101 * t;
++ for (w = s; --w; ) *pixels++ = 0x01000101 * t,
++ *pixels++ = 0x01010001 * t, *pixels++ = 0x00010100 * t;
++ for (w = s; --w; ) *pixels++ = 0x00010100 * t,
++ *pixels++ = 0x01000101 * t, *pixels++ = 0x01010001 * t;
++#else
++ for (w = s; --w; ) *pixels++ = 0x00ff0000, // Blue
++ *pixels++ = 0x0000ff00, *pixels++ = 0xff0000ff;
++ for (w = s; --w; ) *pixels++ = 0xff0000ff, // Red
++ *pixels++ = 0x00ff0000, *pixels++ = 0x0000ff00;
++ for (w = s; --w; ) *pixels++ = 0x0000ff00, // Green
++ *pixels++ = 0xff0000ff, *pixels++ = 0x00ff0000;
++ for (w = s; --w; ) *pixels++ = 0x00000000, // Black
++ *pixels++ = 0x00000000, *pixels++ = 0x00000000;
++ for (w = s; --w; ) *pixels++ = 0xffffffff, // White
++ *pixels++ = 0xffffffff, *pixels++ = 0xffffffff;
++ for (w = s; --w; ) *pixels++ = 0xffff00ff, // B + R
++ *pixels++ = 0x00ffff00, *pixels++ = 0xff00ffff;
++ for (w = s; --w; ) *pixels++ = 0xff00ffff, // R + G
++ *pixels++ = 0xffff00ff, *pixels++ = 0x00ffff00;
++ for (w = s; --w; ) *pixels++ = 0x00ffff00, // G + B
++ *pixels++ = 0xff00ffff, *pixels++ = 0xffff00ff;
++#endif
++ pixels += r;
++ }
++
++ for (s = (var->xres >> 2) + 1, h = HORIZON_LINES + 1; --h; ) {
++ for (w = s; --w; ) *pixels++ = 0xff00ffff, // Yellow
++ *pixels++ = 0xffff00ff, *pixels++ = 0x00ffff00;
++#ifndef CONFIG_DELTA_LCD
++continue;
++#endif
++ --h; // even line:
++ for (w = s; --w; ) *pixels++ = 0xffff00ff, // B + R
++ *pixels++ = 0x00ffff00, *pixels++ = 0xff00ffff;
++ }
++
++#ifdef CONFIG_DELTA_LCD
++ /*
++ * For Delta LCD(e.g.: A025DL01), the RGB sequence is:
++ * R-G-B for odd line, and G-B-R for even line.
++ *
++ * For best visual effect, the recommented RGB sequence is:
++ * G-B-R for odd line, and B-R-G for even line.
++ */
++ pixels = (u32*)fbi->screen_base;
++ for (s = (var->xres * 3) >> 2, h = var->yres + 1; --h; ) { u32 lva;
++#if 0
++ for (w = s, lva = *pixels; --w; ) {
++ u32 nva = pixels[1]; // shift the line data left:
++ *pixels++ = (lva >> 8) | (nva << 24); lva = nva;
++ } *pixels++ = lva >> 8;
++#else
++ for (w = s + 1, lva = 0; --w; ) {
++ u32 nva =*pixels; // shift the line data right:
++ *pixels++ = (nva << 8) | (lva >> 24); lva = nva;
++ }
++#endif
++ }
++#endif//CONFIG_DELTA_LCD
++
++#if 0
++{ unsigned char* ptr = (unsigned char*)fbi->screen_base +
++ ((var->xres >> 1) + 10) * 3;
++ for (h = var->yres + 1; --h; ) {
++ if (h % 2) ptr[2] = 0xff, ptr[1] = 0x00, ptr[3] = 0x00;
++ else ptr[2] = 0x00, ptr[1] = 0x00, ptr[3] = 0xff;
++ ptr[37] = ptr[38] = ptr[39] = 0x00;
++ ptr += var->xres * 3;
++ }
++}
++#endif
++ } else if (var->bits_per_pixel < 33) {
++ for (s = (var->xres >> 0) + 1, h = HORIZON_LINES + 1; --h; )
++ for (w = s; --w; ) *pixels++ = 0x000000ff; // Blue margin
++
++ s = (var->xres >> 3) + 1, r = ((var->xres - ((s - 1) << 3)) >> 0);
++ for (h = var->yres - (HORIZON_LINES << 1) + 1; --h; ) {
++ for (w = s; --w; ) *pixels++ = 0x00ff0000; // Red
++ for (w = s; --w; ) *pixels++ = 0x0000ff00; // Green
++ for (w = s; --w; ) *pixels++ = 0x000000ff; // Blue
++ for (w = s; --w; ) *pixels++ = 0x00000000; // Black
++ for (w = s; --w; ) *pixels++ = 0xffffffff; // White
++ for (w = s; --w; ) *pixels++ = 0x00ffff00; // G + R
++ for (w = s; --w; ) *pixels++ = 0x0000ffff; // B + G
++ for (w = s; --w; ) *pixels++ = 0x00ff00ff; // R + B
++ pixels += r;
++ }
++
++ for (s = (var->xres >> 0) + 1, h = HORIZON_LINES + 1; --h; )
++ for (w = s; --w; ) *pixels++ = 0x00ffff00; // Yellow
++ } else {
++ unsigned size = fbi->var.yres * fbi->fix.line_length / 2;
++
++ memset32(pixels, 0x00000000, size); // Black/
++ pixels = (void*)((unsigned char*)pixels + size);
++
++ memset32(pixels, 0xffffffff, size); // White/
++ pixels = (void*)((unsigned char*)pixels + size);
++
++ //dtrace;
++ }
++
++ BUG_ON((char*)pixels != fbi->screen_base +
++ fbi->var.yres * fbi->fix.line_length);
++
++ // draw a white cursor on top-left corner
++ pixels = (u32*)fbi->screen_base;
++ for (s = CURSOR_PIXELS; --s; ) {
++ memset32(pixels, 0xffffffff, CURSOR_PIXELS);
++ pixels = (u32*)((unsigned char*)pixels + fbi->fix.line_length);
++ }
++}
++#else
++#define draw_colorbar(...)
++#endif//CONFIG_FB_COLORBAR
++
++// vim:sts=4:ts=8:
+diff --git a/drivers/video/s3c/s3cfb.c b/drivers/video/s3c/s3cfb.c
+index d9b8196..19ab25f 100644
+--- a/drivers/video/s3c/s3cfb.c
++++ b/drivers/video/s3c/s3cfb.c
+@@ -40,6 +40,9 @@
+
+ #include "s3cfb.h"
+
++//#define CONFIG_FB_COLORBAR 1
++#include "colorbar.c"
++
+ /*
+ * Globals
+ */
+@@ -50,7 +53,7 @@ s3c_vsync_info_t s3c_vsync_info;
+ s3c_vs_info_t s3c_vs_info;
+ #endif
+
+-static int backlight_level = S3C_FB_DEFAULT_BACKLIGHT_LEVEL;
++static int backlight_level = S3C_FB_MIN_BACKLIGHT_LEVEL;
+ static int backlight_power = 1;
+ static int lcd_power = 1;
+ static int s3c_palette_win;
+@@ -63,13 +66,14 @@ static void s3cfb_set_lcd_power(int to)
+ (s3c_fimd.set_lcd_power)(to);
+ }
+
+-static void s3cfb_set_backlight_power(int to)
++void s3cfb_set_backlight_power(int to)
+ {
+ backlight_power = to;
+
+ if (s3c_fimd.set_backlight_power)
+ (s3c_fimd.set_backlight_power)(to);
+ }
++EXPORT_SYMBOL(s3cfb_set_backlight_power);
+
+ static void s3cfb_set_backlight_level(int to)
+ {
+@@ -91,7 +95,7 @@ static int __init s3cfb_map_video_memory(s3c_fb_info_t *fbi)
+ /* prevent initial garbage on screen */
+ printk("Window[%d] - FB1: map_video_memory: clear %p:%08x\n",
+ fbi->win_id, fbi->map_cpu_f1, fbi->map_size_f1);
+- memset(fbi->map_cpu_f1, 0xf0, fbi->map_size_f1);
++ memset(fbi->map_cpu_f1, 0xff, fbi->map_size_f1);
+
+ fbi->screen_dma_f1 = fbi->map_dma_f1;
+ fbi->fb.screen_base = fbi->map_cpu_f1;
+@@ -198,7 +202,8 @@ static int s3cfb_set_par(struct fb_info *info)
+ struct fb_var_screeninfo *var = &info->var;
+ s3c_fb_info_t *fbi = (s3c_fb_info_t *) info;
+
+- if (var->bits_per_pixel == 16 || var->bits_per_pixel == 24)
++ if (var->bits_per_pixel == 16 || var->bits_per_pixel == 24
++ || var->bits_per_pixel == 32)
+ fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
+ else
+ fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
+@@ -264,16 +269,16 @@ static int s3cfb_blank(int blank_mode, struct fb_info *info)
+
+ switch (blank_mode) {
+ case VESA_NO_BLANKING: /* lcd on, backlight on */
+- s3cfb_set_lcd_power(1);
+- s3cfb_set_backlight_power(1);
++ if(!backlight_power)
++ s3cfb_set_backlight_power(1);
+ break;
+
+ case VESA_VSYNC_SUSPEND: /* lcd on, backlight off */
+ case VESA_HSYNC_SUSPEND:
+- s3cfb_set_lcd_power(1);
+ s3cfb_set_backlight_power(0);
+ break;
+
++ case VESA_POWERDOWN + 1: // XXX: compatible with X
+ case VESA_POWERDOWN: /* lcd and backlight off */
+ s3cfb_set_lcd_power(0);
+ s3cfb_set_backlight_power(0);
+@@ -472,6 +477,17 @@ static int s3cfb_set_bpp(s3c_fb_info_t *fbi, int bpp)
+ return 0;
+ }
+
++void s3cfb_clear_lcd(int flag)
++{
++ if(flag) // clear the LCD screen to black
++ memset((s3c_fb_info[0].fb).screen_base, 0x0,
++ (s3c_fb_info[0].fb).var.bits_per_pixel / 8 * (s3c_fb_info[0].fb).var.xres * (s3c_fb_info[0].fb).var.yres);
++ else // clear the LCD screen to white
++ memset((s3c_fb_info[0].fb).screen_base, 0xff,
++ (s3c_fb_info[0].fb).var.bits_per_pixel / 8 * (s3c_fb_info[0].fb).var.xres * (s3c_fb_info[0].fb).var.yres);
++}
++EXPORT_SYMBOL(s3cfb_clear_lcd);
++
+ void s3cfb_stop_lcd(void)
+ {
+ unsigned long flags;
+@@ -494,8 +510,11 @@ void s3cfb_start_lcd(void)
+
+ local_irq_save(flags);
+
++ do {
+ tmp = readl(S3C_VIDCON0);
+ writel(tmp | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
++ tmp = readl(S3C_VIDCON0) & (S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE);
++ } while(tmp != (S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE));
+
+ local_irq_restore(flags);
+ }
+@@ -664,15 +683,15 @@ static int s3cfb_sysfs_store_backlight_level(struct device *dev, struct device_a
+ return len;
+ }
+
+-static DEVICE_ATTR(lcd_power, 0644,
++static DEVICE_ATTR(lcd_power, 0666,
+ s3cfb_sysfs_show_lcd_power,
+ s3cfb_sysfs_store_lcd_power);
+
+-static DEVICE_ATTR(backlight_power, 0644,
++static DEVICE_ATTR(backlight_power, 0666,
+ s3cfb_sysfs_show_backlight_power,
+ s3cfb_sysfs_store_backlight_power);
+
+-static DEVICE_ATTR(backlight_level, 0644,
++static DEVICE_ATTR(backlight_level, 0666,
+ s3cfb_sysfs_show_backlight_level,
+ s3cfb_sysfs_store_backlight_level);
+
+@@ -686,7 +705,7 @@ struct fb_ops s3cfb_ops = {
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+- .fb_cursor = soft_cursor,
++ //.fb_cursor = soft_cursor,
+ .fb_ioctl = s3cfb_ioctl,
+ };
+
+@@ -772,7 +791,6 @@ static int __init s3cfb_probe(struct platform_device *pdev)
+ struct resource *res;
+ struct fb_info *fbinfo;
+ s3c_fb_info_t *info;
+-
+ char driver_name[] = "s3cfb";
+ int index = 0, ret, size;
+
+@@ -812,9 +830,6 @@ static int __init s3cfb_probe(struct platform_device *pdev)
+ }
+
+ s3cfb_pre_init();
+- s3cfb_set_backlight_power(1);
+- s3cfb_set_lcd_power(1);
+- s3cfb_set_backlight_level(S3C_FB_DEFAULT_BACKLIGHT_LEVEL);
+
+ #if defined(CONFIG_PLAT_S5PC1XX)
+ info->clk = clk_get(NULL, "hclkd1");
+@@ -906,6 +921,10 @@ static int __init s3cfb_probe(struct platform_device *pdev)
+ if (ret < 0)
+ printk(KERN_WARNING "s3cfb: failed to add entries\n");
+
++ s3cfb_set_par(&(s3c_fb_info[0].fb));
++ mdelay(10);
++ //draw_colorbar(&(s3c_fb_info[0].fb));
++
+ return 0;
+
+ free_video_memory:
+diff --git a/drivers/video/s3c/s3cfb.h b/drivers/video/s3c/s3cfb.h
+index cf66ec4..fbff811 100644
+--- a/drivers/video/s3c/s3cfb.h
++++ b/drivers/video/s3c/s3cfb.h
+@@ -65,7 +65,9 @@ extern int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, uns
+ #define S3C_FB_PALETTE_BUFF_CLEAR (0x80000000) /* entry is clear/invalid */
+ #define S3C_FB_COLOR_KEY_DIR_BG 0
+ #define S3C_FB_COLOR_KEY_DIR_FG 1
+-#define S3C_FB_DEFAULT_BACKLIGHT_LEVEL 2
++#define S3C_FB_MIN_BACKLIGHT_LEVEL 0
++#define S3C_FB_MAX_BACKLIGHT_LEVEL 100
++#define S3C_FB_DEFAULT_BACKLIGHT_LEVEL 50
+ #define S3C_FB_MAX_DISPLAY_OFFSET 200
+ #define S3C_FB_DEFAULT_DISPLAY_OFFSET 100
+ #define S3C_FB_MAX_ALPHA_LEVEL 0xf
+@@ -476,6 +478,7 @@ extern int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg
+ extern void s3cfb_activate_var(s3c_fb_info_t *fbi, struct fb_var_screeninfo *var);
+ extern void s3cfb_set_fb_addr(s3c_fb_info_t *fbi);
+ extern void s3cfb_init_hw(void);
++extern void lcd_init_hw(void);
+ extern irqreturn_t s3cfb_irq(int irqno, void *param);
+ extern int s3cfb_init_registers(s3c_fb_info_t *fbi);
+ extern int s3cfb_set_win_position(s3c_fb_info_t *fbi, int left_x, int top_y, int width, int height);
+diff --git a/drivers/video/s3c/s3cfb_a070vw04.c b/drivers/video/s3c/s3cfb_a070vw04.c
+new file mode 100644
+index 0000000..58d2af1
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_a070vw04.c
+@@ -0,0 +1,263 @@
++/*
++ * drivers/video/s3c/s3cfb_a070vw04.c
++ *
++ * $Id: s3cfb_lte480wv.c,v 1.12 2008/06/05 02:13:24 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/wait.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-lcd.h>
++
++#include "s3cfb.h"
++#include <asm-arm/arch-s3c2410/gpio.h>
++
++#define S3C_FB_HFP 3 /* front porch */
++#define S3C_FB_HSW 10 /* Hsync width */
++#define S3C_FB_HBP 5 /* Back porch */
++
++#define S3C_FB_VFP 1 /* front porch */
++#define S3C_FB_VSW 3 /* Vsync width */
++#define S3C_FB_VBP 20 /* Back porch */
++
++#define S3C_FB_HRES 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES 480 /* line cnt y resolution */
++
++#define S3C_FB_HRES_VIRTUAL 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES_VIRTUAL 480 /* line cnt y resolution */
++
++#define S3C_FB_HRES_OSD 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES_OSD 480 /* line cnt y resolution */
++
++#define S3C_FB_VFRAME_FREQ 60 /* frame rate freq */
++
++#define S3C_FB_PIXEL_CLOCK (S3C_FB_VFRAME_FREQ * (S3C_FB_HFP + S3C_FB_HSW + S3C_FB_HBP + S3C_FB_HRES) * (S3C_FB_VFP + S3C_FB_VSW + S3C_FB_VBP + S3C_FB_VRES))
++
++#define LCD_SCEN S3C_GPM0
++#define LCD_SCL S3C_GPM1
++#define LCD_SDA S3C_GPM2
++
++static void set_lcd_power(int val)
++{
++ if(val > 0) {
++ /* Display On */
++ s3cfb_init_hw();
++ s3cfb_start_lcd();
++ } else {
++ /* Direct Off */
++ s3cfb_stop_lcd();
++ }
++}
++
++#define WAITTIME (10 * HZ / 1000) // 10ms
++static int old_display_brightness = S3C_FB_MIN_BACKLIGHT_LEVEL;
++
++static void __set_brightness(int val)
++{
++ int channel = 1; // must use channel-1
++ int usec = 0; // don't care value
++ unsigned long tcnt=1000;
++ unsigned long tcmp=0;
++
++ if(val == S3C_FB_MAX_BACKLIGHT_LEVEL)
++ gpio_direction_output(S3C_GPF15, 1);
++ else if(val == S3C_FB_MIN_BACKLIGHT_LEVEL)
++ gpio_direction_output(S3C_GPF15, 0);
++ else {
++ tcmp = val * 10;
++#if defined(CONFIG_S3C6410_PWM) && defined(CONFIG_PWM)
++ s3c6410_timer_setup (channel, usec, tcnt, tcmp);
++#endif
++ }
++}
++
++static void set_brightness(int val)
++{
++ int old_val = old_display_brightness;
++
++ if(val < 0) val = 0;
++ if(val > S3C_FB_MAX_BACKLIGHT_LEVEL) val = S3C_FB_MAX_BACKLIGHT_LEVEL;
++
++ if(val > old_val) {
++ while((++old_val) < val) {
++ __set_brightness(old_val);
++ set_current_state(TASK_INTERRUPTIBLE);
++ schedule_timeout(WAITTIME);
++ }
++ } else {
++ while((--old_val) > val) {
++ __set_brightness(old_val);
++ set_current_state(TASK_INTERRUPTIBLE);
++ schedule_timeout(WAITTIME);
++ }
++ }
++
++ __set_brightness(val);
++ old_display_brightness = val;
++}
++
++static void set_backlight_power(int val)
++{
++ if(val > 0)
++ __set_brightness(old_display_brightness);
++ else
++ __set_brightness(S3C_FB_MIN_BACKLIGHT_LEVEL);
++}
++
++static void s3cfb_set_fimd_info(void)
++{
++ s3c_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL | S3C_VIDCON1_IVCLK_RISE_EDGE;
++ s3c_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3C_FB_VBP - 1) | S3C_VIDTCON0_VFPD(S3C_FB_VFP - 1) | S3C_VIDTCON0_VSPW(S3C_FB_VSW - 1);
++ s3c_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3C_FB_HBP - 1) | S3C_VIDTCON1_HFPD(S3C_FB_HFP - 1) | S3C_VIDTCON1_HSPW(S3C_FB_HSW - 1);
++ s3c_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3C_FB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3C_FB_HRES - 1);
++
++ s3c_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES - 1);
++
++ s3c_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES_OSD - 1);
++
++ s3c_fimd.width = S3C_FB_HRES;
++ s3c_fimd.height = S3C_FB_VRES;
++ s3c_fimd.xres = S3C_FB_HRES;
++ s3c_fimd.yres = S3C_FB_VRES;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_fimd.xres_virtual = S3C_FB_HRES_VIRTUAL;
++ s3c_fimd.yres_virtual = S3C_FB_VRES_VIRTUAL;
++#else
++ s3c_fimd.xres_virtual = S3C_FB_HRES;
++ s3c_fimd.yres_virtual = S3C_FB_VRES;
++#endif
++
++ s3c_fimd.osd_width = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_height = S3C_FB_VRES_OSD;
++ s3c_fimd.osd_xres = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres = S3C_FB_VRES_OSD;
++
++ s3c_fimd.osd_xres_virtual = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres_virtual = S3C_FB_VRES_OSD;
++
++ s3c_fimd.pixclock = S3C_FB_PIXEL_CLOCK;
++
++ s3c_fimd.hsync_len = S3C_FB_HSW;
++ s3c_fimd.vsync_len = S3C_FB_VSW;
++ s3c_fimd.left_margin = S3C_FB_HFP;
++ s3c_fimd.upper_margin = S3C_FB_VFP;
++ s3c_fimd.right_margin = S3C_FB_HBP;
++ s3c_fimd.lower_margin = S3C_FB_VBP;
++
++ s3c_fimd.set_lcd_power = set_lcd_power;
++ s3c_fimd.set_backlight_power = set_backlight_power;
++ s3c_fimd.set_brightness = set_brightness;
++ s3c_fimd.backlight_min = S3C_FB_MIN_BACKLIGHT_LEVEL;
++ s3c_fimd.backlight_max = S3C_FB_MAX_BACKLIGHT_LEVEL;
++}
++
++void s3cfb_init_hw(void)
++{
++ printk(KERN_INFO "LCD TYPE :: A070VW04 will be initialized\n");
++
++ s3cfb_set_fimd_info();
++ s3cfb_set_gpio();
++ lcd_init_hw();
++ set_brightness(old_display_brightness);
++}
++
++static void us_delay(unsigned int dly)
++{
++ udelay(dly);
++}
++
++static void write_bit(unsigned char val)
++{
++ gpio_set_value(S3C_GPM1, 0); // SCL = 0
++ gpio_set_value(S3C_GPM2, val); // SDA = val
++ us_delay(1000);
++ gpio_set_value(S3C_GPM1, 1); // SCL = 1
++ us_delay(1000);
++}
++
++static unsigned int read_bit()
++{
++ gpio_set_value(S3C_GPM1, 0); // SCL = 0
++ unsigned int data = s3c2410_gpio_getpin(S3C_GPM2); // SDA
++ us_delay(1000);
++ gpio_set_value(S3C_GPM1, 1); // SCL = 1
++ us_delay(1000);
++ return data;
++}
++
++static void write_reg(unsigned char addr, unsigned short data)
++{
++ unsigned char i;
++ gpio_set_value(LCD_SCEN, 0); // CSB pin of LCD = 0
++ /* transfer the register address bits (4 bit) */
++ for(i=0; i<4; i++) {
++ if(addr & 0x8)
++ write_bit(1);
++ else
++ write_bit(0);
++ addr <<= 1;
++ }
++ /* transfer the write mode bit (1 bit) */
++ write_bit(0);
++ /* transfer the data bits (11 bits) */
++ write_bit(0);
++ for(i=0; i<10; i++) {
++ if(data & 0x200)
++ write_bit(1);
++ else
++ write_bit(0);
++ data <<= 1;
++ }
++ gpio_set_value(LCD_SCEN, 1); // CSB pin of LCD = 1
++}
++
++static unsigned int read_reg(unsigned char addr)
++{
++ unsigned char i;
++ unsigned int data = 0x0;
++ gpio_set_value(LCD_SCEN, 0); // CSB pin of LCD = 0
++ /* transfer the register address bits (4 bit) */
++ for(i=0; i<4; i++) {
++ if(addr & 0x8)
++ write_bit(1);
++ else
++ write_bit(0);
++ addr <<= 1;
++ }
++ /* transfer the read or read mode (1 bit) */
++ write_bit(1);
++ /* transfer the data (11 bits) */
++ write_bit(0);
++ for(i=0; i<10; i++) {
++ data |= (read_bit() << i);
++ }
++ gpio_set_value(LCD_SCEN, 1); // CSB pin of LCD = 1
++
++ return data;
++}
++
++void lcd_init_hw(void)
++{
++ gpio_direction_output(LCD_SCEN, 1); // GPM0 <---> CSB pin of LCD
++ gpio_direction_output(S3C_GPM1, 1); // GPM1 <---> SCL pin of LCD
++ gpio_direction_output(S3C_GPM2, 1); // GPM2 <---> SDA pin of LCD
++ write_reg(0x0, 0x2d3);
++ //write_reg(0x1, 0x181);
++ write_reg(0x4, 0x19f);
++}
++
+diff --git a/drivers/video/s3c/s3cfb_fimd4x.c b/drivers/video/s3c/s3cfb_fimd4x.c
+index c2ff1e8..79d857b 100644
+--- a/drivers/video/s3c/s3cfb_fimd4x.c
++++ b/drivers/video/s3c/s3cfb_fimd4x.c
+@@ -126,7 +126,6 @@ s3c_fimd_info_t s3c_fimd = {
+ .cmap_static = 1,
+ };
+
+-#if defined(CONFIG_S3C6410_PWM)
+ void s3cfb_set_brightness(int val)
+ {
+ int channel = 1; /* must use channel-1 */
+@@ -143,9 +142,11 @@ void s3cfb_set_brightness(int val)
+ s3c_display_brightness = val;
+ tcmp = val * 5;
+
++#if defined(CONFIG_S3C6410_PWM) && defined(CONFIG_PWM)
+ s3c6410_timer_setup (channel, usec, tcnt, tcmp);
+-}
+ #endif
++}
++EXPORT_SYMBOL(s3cfb_set_brightness);
+
+ #if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
+
+@@ -554,6 +555,9 @@ void s3cfb_activate_var(s3c_fb_info_t *fbi, struct fb_var_screeninfo *var)
+ break;
+ }
+
++ s3c_fimd.vidtcon1 &= ~S3C_VIDTCON1_HBPD(0xff);
++ s3c_fimd.vidtcon1 |= S3C_VIDTCON1_HBPD(var->right_margin);
++
+ /* write new registers */
+ writel(s3c_fimd.wincon0, S3C_WINCON0);
+ writel(s3c_fimd.wincon1, S3C_WINCON1);
+@@ -561,6 +565,7 @@ void s3cfb_activate_var(s3c_fb_info_t *fbi, struct fb_var_screeninfo *var)
+ writel(s3c_fimd.wincon3, S3C_WINCON3);
+ writel(s3c_fimd.wincon4, S3C_WINCON4);
+ writel(s3c_fimd.wpalcon, S3C_WPALCON);
++ writel(s3c_fimd.vidtcon1, S3C_VIDTCON1);
+ writel(s3c_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
+ writel(s3c_fimd.vidcon0 | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
+ }
+@@ -779,9 +784,7 @@ int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
+ struct fb_var_screeninfo *var= &fbi->fb.var;
+ unsigned int crt, alpha_level, alpha_mode;
+
+-#if defined(CONFIG_S3C6410_PWM)
+ int brightness;
+-#endif
+
+ #if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING)
+ unsigned int f_num_val;
+@@ -971,14 +974,12 @@ int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
+ return -EFAULT;
+ break;
+
+-#if defined(CONFIG_S3C6410_PWM)
+ case S3C_FB_SET_BRIGHTNESS:
+ if (copy_from_user(&brightness, (int *) arg, sizeof(int)))
+ return -EFAULT;
+
+ s3cfb_set_brightness(brightness);
+ break;
+-#endif
+
+ #if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
+ case S3C_FB_VS_START:
+@@ -1053,6 +1054,9 @@ void s3cfb_pre_init(void)
+ s3c_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
+
+ writel(s3c_fimd.vidintcon0, S3C_VIDINTCON0);
++
++ /* open the power of LCD */
++ gpio_direction_output(S3C_GPM3, 1);
+ }
+
+ void s3cfb_set_gpio(void)
+@@ -1103,9 +1107,6 @@ void s3cfb_set_gpio(void)
+ gpio_set_pin(S3C_GPJ10, S3C_GPJ10_LCD_VDEN);
+ gpio_set_pin(S3C_GPJ11, S3C_GPJ11_LCD_VCLK);
+
+- /* backlight ON */
+- gpio_direction_output(S3C_GPF15, 1);
+-
+ /* module reset */
+ gpio_direction_output(S3C_GPN5, 1);
+ mdelay(100);
+@@ -1240,6 +1241,8 @@ static struct sleep_save s3c_lcd_save[] = {
+ SAVE_ITEM(S3C_W4PDATA23),
+ };
+
++extern void s3cfb_set_backlight_power(int to);
++extern void s3cfb_clear_lcd(int flag);
+ /*
+ * Suspend
+ */
+@@ -1248,6 +1251,8 @@ int s3cfb_suspend(struct platform_device *dev, pm_message_t state)
+ struct fb_info *fbinfo = platform_get_drvdata(dev);
+ s3c_fb_info_t *info = fbinfo->par;
+
++ s3cfb_set_backlight_power(0); // close the backlight of LCD
++ s3cfb_clear_lcd(0); // clear the LCD screen to white
+ s3cfb_stop_lcd();
+ s3c2410_pm_do_save(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
+
+@@ -1272,9 +1277,13 @@ int s3cfb_resume(struct platform_device *dev)
+ clk_enable(info->clk);
+ msleep(1);
+ s3c2410_pm_do_restore(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save));
++ mdelay(1);
+
+ s3cfb_init_hw();
++ mdelay(10);
++ s3cfb_clear_lcd(1); // clear the LCD screen to black
+ s3cfb_start_lcd();
++ mdelay(10);
+
+ return 0;
+ }
+diff --git a/drivers/video/s3c/s3cfb_td043mtex.c b/drivers/video/s3c/s3cfb_td043mtex.c
+new file mode 100644
+index 0000000..86aab2f
+--- /dev/null
++++ b/drivers/video/s3c/s3cfb_td043mtex.c
+@@ -0,0 +1,279 @@
++/*
++ * drivers/video/s3c/s3cfb_a070vw04.c
++ *
++ * $Id: s3cfb_lte480wv.c,v 1.12 2008/06/05 02:13:24 jsgood Exp $
++ *
++ * Copyright (C) 2008 Jinsung Yang <jsgood.yang@samsung.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C Frame Buffer Driver
++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
++ */
++
++#include <linux/wait.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/arch/regs-lcd.h>
++
++#include "s3cfb.h"
++#include <asm-arm/arch-s3c2410/gpio.h>
++
++#define S3C_FB_HFP 40 /* front porch */
++#define S3C_FB_HSW 1 /* Hsync width */
++#define S3C_FB_HBP 216 /* Back porch */
++
++#define S3C_FB_VFP 10 /* front porch */
++#define S3C_FB_VSW 1 /* Vsync width */
++#define S3C_FB_VBP 35 /* Back porch */
++
++#define S3C_FB_HRES 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES 480 /* line cnt y resolution */
++
++#define S3C_FB_HRES_VIRTUAL 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES_VIRTUAL 960 /* line cnt y resolution */
++
++#define S3C_FB_HRES_OSD 800 /* horizon pixel x resolition */
++#define S3C_FB_VRES_OSD 480 /* line cnt y resolution */
++
++#define S3C_FB_VFRAME_FREQ 60 /* frame rate freq */
++
++#define S3C_FB_PIXEL_CLOCK (S3C_FB_VFRAME_FREQ * (S3C_FB_HFP + S3C_FB_HSW + S3C_FB_HBP + S3C_FB_HRES) * (S3C_FB_VFP + S3C_FB_VSW + S3C_FB_VBP + S3C_FB_VRES))
++
++static void set_lcd_power(int val)
++{
++ if(val > 0) {
++ /* Display On */
++ s3cfb_start_lcd();
++ } else {
++ /* Direct Off */
++ s3cfb_stop_lcd();
++ }
++}
++
++#define WAITTIME (10 * HZ / 1000) // 10ms
++static int old_display_brightness = S3C_FB_MIN_BACKLIGHT_LEVEL;
++
++static void __set_brightness(int val)
++{
++ int channel = 1; // must use channel-1
++ int usec = 0; // don't care value
++ unsigned long tcnt=1000;
++ unsigned long tcmp=0;
++
++ if(val == S3C_FB_MAX_BACKLIGHT_LEVEL)
++ gpio_direction_output(S3C_GPF15, 1);
++ else if(val == S3C_FB_MIN_BACKLIGHT_LEVEL)
++ gpio_direction_output(S3C_GPF15, 0);
++ else {
++ tcmp = val * 10;
++#if defined(CONFIG_S3C6410_PWM) && defined(CONFIG_PWM)
++ s3c6410_timer_setup (channel, usec, tcnt, tcmp);
++#endif
++ }
++}
++
++static void set_brightness(int val)
++{
++ int old_val = old_display_brightness;
++
++ if(val < 0) val = 0;
++ if(val > S3C_FB_MAX_BACKLIGHT_LEVEL) val = S3C_FB_MAX_BACKLIGHT_LEVEL;
++
++ if(val > old_val) {
++ while((++old_val) < val) {
++ __set_brightness(old_val);
++ set_current_state(TASK_INTERRUPTIBLE);
++ schedule_timeout(WAITTIME);
++ }
++ } else {
++ while((--old_val) > val) {
++ __set_brightness(old_val);
++ set_current_state(TASK_INTERRUPTIBLE);
++ schedule_timeout(WAITTIME);
++ }
++ }
++
++ __set_brightness(val);
++ old_display_brightness = val;
++}
++
++static void set_backlight_power(int val)
++{
++ if(val > 0)
++ __set_brightness(old_display_brightness);
++ else
++ __set_brightness(S3C_FB_MIN_BACKLIGHT_LEVEL);
++}
++
++static void s3cfb_set_fimd_info(void)
++{
++ s3c_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT |S3C_VIDCON1_IVDEN_INVERT;
++ s3c_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3C_FB_VBP - 1) | S3C_VIDTCON0_VFPD(S3C_FB_VFP - 1) | S3C_VIDTCON0_VSPW(S3C_FB_VSW - 1);
++ s3c_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3C_FB_HBP - 1) | S3C_VIDTCON1_HFPD(S3C_FB_HFP - 1) | S3C_VIDTCON1_HSPW(S3C_FB_HSW - 1);
++ s3c_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3C_FB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3C_FB_HRES - 1);
++
++ s3c_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES - 1);
++
++ s3c_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0);
++ s3c_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3C_FB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3C_FB_VRES_OSD - 1);
++
++ s3c_fimd.width = S3C_FB_HRES;
++ s3c_fimd.height = S3C_FB_VRES;
++ s3c_fimd.xres = S3C_FB_HRES;
++ s3c_fimd.yres = S3C_FB_VRES;
++
++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN)
++ s3c_fimd.xres_virtual = S3C_FB_HRES_VIRTUAL;
++ s3c_fimd.yres_virtual = S3C_FB_VRES_VIRTUAL;
++#else
++ s3c_fimd.xres_virtual = S3C_FB_HRES;
++ s3c_fimd.yres_virtual = S3C_FB_VRES;
++#endif
++
++ s3c_fimd.osd_width = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_height = S3C_FB_VRES_OSD;
++ s3c_fimd.osd_xres = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres = S3C_FB_VRES_OSD;
++
++ s3c_fimd.osd_xres_virtual = S3C_FB_HRES_OSD;
++ s3c_fimd.osd_yres_virtual = S3C_FB_VRES_OSD;
++
++ s3c_fimd.pixclock = S3C_FB_PIXEL_CLOCK;
++
++ s3c_fimd.hsync_len = S3C_FB_HSW;
++ s3c_fimd.vsync_len = S3C_FB_VSW;
++ s3c_fimd.left_margin = S3C_FB_HFP;
++ s3c_fimd.upper_margin = S3C_FB_VFP;
++ s3c_fimd.right_margin = S3C_FB_HBP;
++ s3c_fimd.lower_margin = S3C_FB_VBP;
++
++ s3c_fimd.set_lcd_power = set_lcd_power;
++ s3c_fimd.set_backlight_power = set_backlight_power;
++ s3c_fimd.set_brightness = set_brightness;
++ s3c_fimd.backlight_min = S3C_FB_MIN_BACKLIGHT_LEVEL;
++ s3c_fimd.backlight_max = S3C_FB_MAX_BACKLIGHT_LEVEL;
++}
++
++#define LCD_SCEN S3C_GPM0
++#define LCD_SCL S3C_GPM1
++#define LCD_SDA S3C_GPM2
++#define S3C_GPIO_OUTP 1
++#define S3C_GPIO_INP 0
++
++static int lcd_write(unsigned char,unsigned char);
++static void lcd_spi_stop(void);
++static void lcd_spi_start(void);
++static void lcd_spi_start(void)
++{
++ //set scen output 0
++ s3c_gpio_cfgpin(LCD_SCEN,S3C_GPIO_OUTP);
++ s3c_gpio_setpin(LCD_SCEN,0);
++}
++
++static void lcd_spi_stop(void)
++{
++ //set scen output 1
++ s3c_gpio_cfgpin(LCD_SCEN,S3C_GPIO_OUTP);
++ s3c_gpio_setpin(LCD_SCEN,1);
++ s3c_gpio_setpin(LCD_SCL,0);
++ s3c_gpio_setpin(LCD_SDA,0);
++ s3c_gpio_cfgpin(LCD_SCL,S3C_GPIO_INP);
++ s3c_gpio_cfgpin(LCD_SDA,S3C_GPIO_INP);
++}
++static int lcd_write(unsigned char addr,unsigned char data)
++{
++ unsigned char myaddr,mydata,i;
++ myaddr = (addr&0x3f)<<1 ;
++ myaddr <<= 1;
++ myaddr |= 0x1;
++ lcd_spi_start();
++
++ s3c_gpio_cfgpin(LCD_SCL,S3C_GPIO_OUTP);
++ s3c_gpio_setpin(LCD_SCL,0);
++ s3c_gpio_cfgpin(LCD_SDA,S3C_GPIO_OUTP);
++ for(i=0;i<8;i++){
++ s3c_gpio_setpin(LCD_SCL,0);
++ udelay(1);
++ s3c_gpio_setpin(LCD_SDA,(myaddr&0x80)>>7);
++ myaddr <<= 1 ;
++ udelay(1);
++ s3c_gpio_setpin(LCD_SCL,1);
++ udelay(1);
++ } //8nd is null turn
++ mydata = data;
++ for(i=0;i<8;i++){
++ s3c_gpio_setpin(LCD_SCL,0);
++ udelay(1);
++ s3c_gpio_setpin(LCD_SDA,(mydata&0x80)>>7);
++ mydata <<= 1;
++ udelay(1);
++ s3c_gpio_setpin(LCD_SCL,1);
++ udelay(1);
++ }
++
++ lcd_spi_stop();
++
++ return 0;
++}
++
++void s3cfb_init_hw(void)
++{
++ printk(KERN_INFO "LCD TYPE :: TD043MTEX will be initialized\n");
++
++ s3cfb_set_fimd_info();
++ s3cfb_set_gpio();
++ lcd_init_hw();
++}
++
++void lcd_init_hw(void)
++{
++#if 1
++ lcd_spi_stop();
++
++ lcd_write(0x02,0x07);
++ lcd_write(0x03,0x5f);
++ lcd_write(0x04,0x17);
++
++ lcd_write(0x05,0x20);
++ lcd_write(0x06,0x08);
++
++ lcd_write(0x07,0x20);
++ lcd_write(0x08,0x20);
++ lcd_write(0x09,0x20);
++ lcd_write(0x0a,0x20);
++
++ lcd_write(0x0b,0x20);
++ lcd_write(0x0c,0x20);
++ lcd_write(0x0d,0x22);
++
++ lcd_write(0x0e,0x10);
++ lcd_write(0x0f,0x10);
++ lcd_write(0x10,0x10);
++
++ lcd_write(0x11,0x15);
++ lcd_write(0x12,0xaa);
++ lcd_write(0x13,0xff);
++ lcd_write(0x14,0x86);
++ lcd_write(0x15,0x89);
++ lcd_write(0x16,0xc6);
++ lcd_write(0x17,0xea);
++ lcd_write(0x18,0x0c);
++ lcd_write(0x19,0x33);
++ lcd_write(0x1a,0x5e);
++ lcd_write(0x1b,0xd0);
++ lcd_write(0x1c,0x33);
++ lcd_write(0x1d,0x7e);
++ lcd_write(0x1e,0xb3);
++ lcd_write(0x1f,0xff);
++ lcd_write(0x20,0xf0);
++ lcd_write(0x21,0xf0);
++ lcd_write(0x22,0x08);
++#endif
++}
+diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
+index 5d1c15f..abd77f7 100644
+--- a/drivers/watchdog/s3c2410_wdt.c
++++ b/drivers/watchdog/s3c2410_wdt.c
+@@ -153,6 +153,21 @@ static int s3c2410wdt_start(void)
+ return 0;
+ }
+
++int s3c2410wdt_reboot(void)
++{
++ writel(0, wdt_base + S3C2410_WTCON); /* disable watchdog, to be safe */
++
++ /* put initial values into count and data */
++ writel(0x100, wdt_base + S3C2410_WTCNT);
++ writel(0x100, wdt_base + S3C2410_WTDAT);
++
++ /* set the watchdog to go and reset... */
++ writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
++ S3C2410_WTCON_PRESCALE(0x20), wdt_base + S3C2410_WTCON);
++ return 0;
++}
++EXPORT_SYMBOL(s3c2410wdt_reboot);
++
+ static int s3c2410wdt_set_heartbeat(int timeout)
+ {
+ unsigned int freq = clk_get_rate(wdt_clock);
+diff --git a/fs/Kconfig b/fs/Kconfig
+index 781b47d..7049712 100644
+--- a/fs/Kconfig
++++ b/fs/Kconfig
+@@ -1196,6 +1196,13 @@ config EFS_FS
+ To compile the EFS file system support as a module, choose M here: the
+ module will be called efs.
+
++
++# Patched by YAFFS
++source "fs/yaffs2/Kconfig"
++
++# Patched by AUFS
++source "fs/aufs/Kconfig"
++
+ config JFFS2_FS
+ tristate "Journalling Flash File System v2 (JFFS2) support"
+ select CRC32
+diff --git a/fs/Makefile b/fs/Makefile
+index 500cf15..0dc75db 100644
+--- a/fs/Makefile
++++ b/fs/Makefile
+@@ -118,3 +118,9 @@ obj-$(CONFIG_HPPFS) += hppfs/
+ obj-$(CONFIG_DEBUG_FS) += debugfs/
+ obj-$(CONFIG_OCFS2_FS) += ocfs2/
+ obj-$(CONFIG_GFS2_FS) += gfs2/
++
++# Patched by YAFFS
++obj-$(CONFIG_YAFFS_FS) += yaffs2/
++
++# Patched by AUFS
++obj-$(CONFIG_AUFS) += aufs/
+diff --git a/fs/aufs/Kconfig b/fs/aufs/Kconfig
+new file mode 100644
+index 0000000..f609923
+--- /dev/null
++++ b/fs/aufs/Kconfig
+@@ -0,0 +1,283 @@
++config AUFS
++ tristate "Another unionfs"
++ help
++ Aufs is a stackable unification filesystem such as Unionfs,
++ which unifies several directories and provides a merged single
++ directory.
++ In the early days, aufs was entirely re-designed and
++ re-implemented Unionfs Version 1.x series. After many original
++ ideas, approaches and improvements, it becomes totally
++ different from Unionfs while keeping the basic features.
++ See Unionfs for the basic features.
++if AUFS
++comment "These options are for 2.6.24.7"
++choice
++ prompt "Maximum number of branches"
++ default AUFS_BRANCH_MAX_127
++ help
++ Specifies the maximum number of branches (or member directories) in a single aufs. The larger value consumes more system resources and has an impact to performance.
++config AUFS_BRANCH_MAX_127
++ bool "127"
++ help
++ Specifies the maximum number of branches (or member directories) in a single aufs. The larger value consumes more system resources and has an impact to performance.
++config AUFS_BRANCH_MAX_511
++ bool "511"
++ help
++ Specifies the maximum number of branches (or member directories) in a single aufs. The larger value consumes more system resources and has an impact to performance.
++config AUFS_BRANCH_MAX_1023
++ bool "1023"
++ help
++ Specifies the maximum number of branches (or member directories) in a single aufs. The larger value consumes more system resources and has an impact to performance.
++config AUFS_BRANCH_MAX_32767
++ bool "32767"
++ help
++ Specifies the maximum number of branches (or member directories) in a single aufs. The larger value consumes more system resources and has an impact to performance.
++endchoice
++config AUFS_SYSAUFS
++ bool "Use <sysfs>/fs/aufs"
++ depends on SYSFS
++ default y
++ help
++ Aufs creates some files under sysfs for various purposes.
++ If the number of your branches is large or their path is long
++ and you meet the limitation of mount(8) or /etc/mtab, you need
++ to enable this option and set aufs module parameter brs=1.
++ See detail in aufs.5.
++comment "SYSFS and AUFS_SYSAUFS are disabled"
++ depends on SYSFS = n
++config AUFS_HINOTIFY
++ bool "Use inotify to detect actions on a branch"
++ depends on INOTIFY
++ help
++ If you want to modify files on branches directly, eg. bypassing aufs,
++ and want aufs to detect the changes of them fully, then enable this
++ option and use 'udba=inotify' mount option.
++ It will have a negative impact to the performance.
++ See detail in aufs.5.
++comment "INOTIFY and AUFS_HINOTIFY are disabled"
++ depends on INOTIFY = n
++config AUFS_EXPORT
++ bool "NFS-exportable aufs"
++ depends on (AUFS = y && EXPORTFS = y) || (AUFS = m && EXPORTFS)
++ help
++ If you want to export your mounted aufs, then enable this
++ option. There are several requirements for this configuration.
++ See detail in aufs.5.
++comment "EXPORTFS and AUFS_EXPORT are disabled"
++ depends on EXPORTFS = n
++comment "AUFS_EXPORT is disabled since EXPORTFS is a module but AUFS"
++ depends on EXPORTFS = m && AUFS = y
++config AUFS_INO_T_64
++ bool
++ depends on 64BIT && !(ALPHA || S390)
++ default y
++config AUFS_ROBR
++ bool "Aufs as an readonly branch of another aufs mount"
++ help
++ If you want make your aufs to be a part of another aufs, then
++ enable this option. In other words, you can specify your aufs
++ path in 'br:' mount option for another aufs, but cannot
++ specify 'rw' as the branch permission.
++ It will have a negative impact to the performance.
++ See detail in aufs.5.
++config AUFS_DLGT
++ bool "Delegate the internal branch access the kernel thread"
++ help
++ If you want aufs to delegate
++ the internal access to the branches which is made by aufs, to
++ the kernel thread, in order to hide the access issued by your
++ application from your LSM or something or make your
++ application to be traced strictly by the task I/O accounting,
++ then enable this option and use 'dlgt' mount option.
++ It will have a negative impact to the performance.
++ See detail in aufs.5.
++config AUFS_HIN_OR_DLGT
++ bool
++ depends on AUFS_HINOTIFY || AUFS_DLGT
++ default y
++ help
++ Automatic configuration for internal use.
++config AUFS_SHWH
++ bool "Show whiteouts"
++ help
++ If you want to make the whiteouts in aufs visible, then enable
++ this option and specify 'shwh' mount option. Although it may
++ sounds like philosophy or something, but in technically it
++ simply shows the name of whiteout with keeping its behaviour.
++config AUFS_RR_SQUASHFS
++ bool "Make squashfs branch RR (real readonly) by default"
++ default y
++ help
++ If you use squashfs or LZMA patched squashfs as an aufs branch
++ and want to set '=rr' to it by default, then enable this
++ configuration.
++ 'rr' stands for real readonly and it optimizes some aspects of
++ 'ro.'
++ See detail in aufs.5.
++config AUFS_SEC_PERM_PATCH
++ bool "sec_perm-2.6.24.patch was applied or not"
++ depends on AUFS = m
++ depends on SECURITY
++ help
++ If you build aufs as a module and enabled CONFIG_SECURITY,
++ then you need to apply the patch
++ 'CVS_TREE/aufs/patch/sec_perm-2.6.24.patch' to your kernel
++ source, and enable this configuration.
++ The sec_perm-2.6.24.patch exports a kernel function
++ security_inode_permission() to modules.
++comment "SECURITY and AUFS_SEC_PERM_PATCH are disabled"
++ depends on SECURITY = n
++config AUFS_SPLICE_PATCH
++ bool "splice.patch for sendfile(2) and splice(2)"
++ help
++ If you use 'loopback mount' on a fs-image file, or use
++ splice(2) or sendfile(2) systemcall in aufs, then you need to
++ apply the patch 'CVS_TREE/aufs/patch/splice.patch' to your
++ kernel source, and enable this configuration.
++ The splice.patch makes the kernel function do_splice_to/from()
++ global and exports them to modules.
++config AUFS_LHASH_PATCH
++ bool "lhash.patch for NFS branch"
++ depends on NFS_FS
++ help
++ If you use mounted NFS as an aufs branch filesystem, then you
++ need to apply the patch 'CVS_TREE/aufs/patch/lhash.patch' (or
++ lhash-2.6.22.patch for linux-2.6.22 and later) to your kernel
++ source, and enable this configuration.
++ The patch file makes the kernel function __lookup_hash() global
++ and exports it to modules.
++comment "NFS_FS and AUFS_LHASH_PATCH are disabled"
++ depends on NFS_FS = n
++config AUFS_PUT_FILP_PATCH
++ bool "put_filp.patch for 'atomic open'"
++ depends on AUFS = m && NFS_V4
++ help
++ If you build aufs as a module and use a filesystem which
++ operates 'atomic open' (for instance NFSv4) as an aufs branch
++ filesystem, then you need to apply the patch
++ 'CVS_TREE/aufs/patch/put_filp.patch' to your kernel source,
++ and enable this configuration.
++ The put_filp.patch exports a kernel function put_filp() to
++ modules.
++comment "NFS_V4 and AUFS_PUT_FILP_PATCH are disabled"
++ depends on NFS_V4 = n
++config AUFS_BR_NFS
++ bool
++ depends on NFS_FS
++ depends on AUFS_LHASH_PATCH
++ default y
++ help
++ Automatic configuration for internal use.
++ When aufs supports NFS branch, enabled automatically.
++config AUFS_BR_NFS_V4
++ bool
++ depends on NFS_V4 && AUFS_BR_NFS
++ depends on AUFS = y || (AUFS = m && AUFS_PUT_FILP_PATCH)
++ default y
++ help
++ Automatic configuration for internal use.
++ When aufs supports a branch filesystem which operates
++ 'atomic_open', for instance NFSv4, this configuration is enabled
++ automatically.
++config AUFS_BR_XFS
++ bool
++ depends on XFS_FS
++ default y
++ help
++ Automatic configuration for internal use.
++ When aufs supports XFS branch, enabled automatically.
++config AUFS_FSYNC_SUPER_PATCH
++ bool "fsync_super-2.6.xx.patch was applied or not"
++ depends on AUFS = m
++ help
++ If you build aufs as a module and want to flush everything for
++ branch filesystems which are not marked as 'rr' nor 'rr+wh' at
++ umount or remount time, then you need to apply the patch
++ 'CVS_TREE/aufs/patch/fsync_super-2.6.16.patch' or
++ '...-2.6.19.patch' to your kernel source, and enable this
++ configuration.
++ It may be helpful at shutdown time in case of your aufs is a
++ root filesystem. But this behaviour will not guarantee the
++ consistency of branch filesystems. To guarantee it, try the
++ approach described in the aufs manual, and do not forget
++ installing auplink script.
++ The fsync_super-2.6.xx.patch does nothing but exports a kernel
++ function fsync_super() to modules.
++config AUFS_DENY_WRITE_ACCESS_PATCH
++ bool "deny_write_access.patch was applied or not"
++ depends on AUFS = m
++ help
++ A security enhancement to deny writing to a running executable
++ which exists on an aufs branch filesystem and executed through
++ aufs. If you applied
++ 'CVS_TREE/aufs/patch/deny_write_access.patch' to your kernel
++ and you are compiling aufs as a module, then enable this
++ option.
++ The write_deny_access.patch does nothing but export the
++ function.
++config AUFS_WORKAROUND_FUSE
++ bool "Special handling for FUSE-based filesystem"
++ depends on FUSE_FS
++ help
++ A FUSE-based filesystem may not initialize its inode
++ attributes and the FUSE developer thinks the inode attributes
++ in a positive dentry which is returned by VFS lookup operation
++ are not reliable.
++ If you use a FUSE-based filesystem as an aufs branch, and it
++ customizes the inode attribute on it without overriding
++ fuse_lowlevel_ops.lookup, probably you need to enable this
++ configuration.
++ If you enable this configuration, aufs calls getattr operation
++ in every lookup and revalidate operation for the FUSE-based
++ filesystem branch.
++ It will have a negative impact to the performance even if you do
++ not use a FUSE-based filesystem branch.
++config AUFS_GETATTR
++ bool
++ depends on AUFS_HINOTIFY || AUFS_WORKAROUND_FUSE || AUFS_BR_NFS
++ default y
++ help
++ Automatic configuration for internal use.
++config AUFS_DEBUG
++ bool "Debug aufs"
++ default y
++ help
++ Enable this to compile aufs internal debug code.
++ It will have a negative impact to the performance.
++config AUFS_MAGIC_SYSRQ
++ bool
++ depends on AUFS_DEBUG && MAGIC_SYSRQ
++ depends on AUFS_SYSAUFS
++ default y
++ help
++ Automatic configuration for internal use.
++ When aufs supports Magic SysRq, enabled automatically.
++config AUFS_DEBUG_LOCK
++ bool "Show lock status in Magic SysRq"
++ depends on AUFS_MAGIC_SYSRQ
++ help
++ For developers only. Sometimes it is useful when a deadlock
++ occurs in aufs. Trace every aufs lock acquire and release, and
++ print them when Magic SysRq-<AUFS> key is pressed.
++ It will have a huge negative impact to the performance.
++config AUFS_COMPAT
++ bool "Compatibility with Unionfs (obsolete)"
++ help
++ This makes aufs compatible with unionfs-style mount options and some
++ behaviours.
++ The dirs= mount option and =nfsro branch permission flag are always
++ interpreted as br: mount option and =ro flag respectively. The
++ 'debug', 'delete' and 'imap' mount options are ignored.
++ If you disable this option, you will get,
++ - aufs issues a warning about the ignored mount options
++ - the default branch permission flag is set. RW for the first branch,
++ and RO for the rests.
++ - the name of a internal file which represents the directory is
++ 'opaque', becomes '.wh..wh..opq'
++ - the 'diropq=w' mount option is set by default
++config AUFS_UNIONFS23_PATCH
++ bool "Unionfs-2.3 or later patch is applied or not (obsolete)"
++ select AUFS_SPLICE_PATCH
++ help
++ Unionfs version 2.3 (and later) patch introduces some changes in VFS layer which has an impact to aufs. If you have applied such patch to your kernel, you need to enable this configuration even if you disabled CONFIG_UNIONFS.
++endif
+diff --git a/fs/aufs/Makefile b/fs/aufs/Makefile
+new file mode 100644
+index 0000000..f529b6f
+--- /dev/null
++++ b/fs/aufs/Makefile
+@@ -0,0 +1,70 @@
++# AUFS Makefile for the Linux 2.6.16 - 2.6.24
++# $Id: Makefile,v 1.49 2008/09/29 03:43:19 sfjro Exp $
++
++# the environment variables are not inherited since 2.6.23
++ifdef AUFS_EXTRA_CFLAGS
++ccflags-y += ${AUFS_EXTRA_CFLAGS}
++endif
++
++########################################
++
++ifdef CONFIG_AUFS_RR_SQUASHFS
++# cf. squashfs3.2-r2 and sqlzma patch.
++ccflags-y += -DSQUASHFS_MAGIC=0x73717368
++ccflags-y += -DSQUASHFS_MAGIC_SWAP=0x68737173
++ccflags-y += -DSQUASHFS_MAGIC_LZMA=0x71736873
++ccflags-y += -DSQUASHFS_MAGIC_LZMA_SWAP=0x73687371
++endif
++
++# defined in ${srctree}/fs/fuse/inode.c
++ccflags-$(CONFIG_AUFS_WORKAROUND_FUSE) += -DFUSE_SUPER_MAGIC=0x65735546
++
++# defined in ${srctree}/fs/xfs/xfs_sb.h
++# tristate
++ifdef CONFIG_XFS_FS
++ccflags-y += -DXFS_SB_MAGIC=0x58465342
++endif
++
++# defined in ${srctree}/mm/shmem.c
++# tristate
++ifdef CONFIG_TMPFS
++ccflags-y += -DTMPFS_MAGIC=0x01021994
++endif
++
++# defined in ${srctree}fs/sysfs/mount.c
++# bool
++ccflags-$(CONFIG_SYSFS) += -DSYSFS_MAGIC=0x62656572
++
++-include $(dir $(lastword ${MAKEFILE_LIST}))priv.mk
++EXTRA_CFLAGS += ${ccflags-y}
++#$(warning ${EXTRA_CFLAGS})
++
++########################################
++
++obj-$(CONFIG_AUFS) += aufs.o
++aufs-y := module.o super.o sbinfo.o branch.o xino.o opts.o \
++ wkq.o vfsub.o dcsub.o \
++ cpup.o whout.o plink.o wbr_policy.o \
++ dentry.o dinfo.o \
++ file.o f_op.o finfo.o \
++ dir.o vdir.o \
++ inode.o i_op.o i_op_add.o i_op_del.o i_op_ren.o iinfo.o \
++ misc.o
++
++aufs-$(CONFIG_AUFS_SYSAUFS) += sysaufs.o
++ifeq ($(strip $(shell test ${SUBLEVEL} -ge 19 && echo t)),t)
++aufs-$(CONFIG_AUFS_BR_NFS) += br_nfs.o
++endif
++aufs-$(CONFIG_AUFS_BR_XFS) += br_xfs.o
++aufs-$(CONFIG_AUFS_WORKAROUND_FUSE) += br_fuse.o
++aufs-$(CONFIG_AUFS_DLGT) += dlgt.o
++aufs-$(CONFIG_AUFS_HINOTIFY) += hinotify.o
++aufs-$(CONFIG_AUFS_HIN_OR_DLGT) += hin_or_dlgt.o
++aufs-$(CONFIG_AUFS_GETATTR) += getattr.o
++aufs-$(CONFIG_AUFS_EXPORT) += export.o
++aufs-$(CONFIG_AUFS_ROBR) += robr.o
++# reserved for future use
++#aufs-$(CONFIG_AUFS_XATTR) += xattr.o
++#aufs-$(CONFIG_DEBUGFS) += dbgfs.o
++aufs-$(CONFIG_AUFS_DEBUG) += debug.o
++aufs-$(CONFIG_AUFS_MAGIC_SYSRQ) += sysrq.o
+diff --git a/fs/aufs/aufs.h b/fs/aufs/aufs.h
+new file mode 100644
+index 0000000..ab271b0
+--- /dev/null
++++ b/fs/aufs/aufs.h
+@@ -0,0 +1,118 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * main header files
++ *
++ * $Id: aufs.h,v 1.51 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_H__
++#define __AUFS_H__
++
++#ifdef __KERNEL__
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++#include <linux/uaccess.h>
++#else
++#include <asm/uaccess.h>
++#endif
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24)
++#error you got wrong version
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++/* limited support before 2.6.16, curretly 2.6.15 only. */
++#include <linux/time.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 16)
++#define timespec_to_ns(ts) ({ (long long)(ts)->tv_sec; })
++#define D_CHILD d_child
++#else
++#define D_CHILD d_u.d_child
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17)
++#include <linux/types.h>
++typedef unsigned long blkcnt_t;
++#endif
++
++/* introduced linux-2.6.17 */
++#include <linux/fs.h>
++#ifndef FMODE_EXEC
++#define FMODE_EXEC 0
++#endif
++
++/* introduced in linux-2.6.21 */
++#include <linux/compiler.h>
++#ifndef __packed
++#define __packed __attribute__((packed))
++#endif
++#ifndef __aligned
++#define __aligned(x) __attribute__((aligned(x)))
++#endif
++
++/* introduced in linux-2.6.25 */
++#ifndef noinline_for_stack
++#define noinline_for_stack /* */
++#endif
++
++/* introduced in linux-2.6.27 */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)
++#define WARN_ONCE(cond, fmt ...) WARN_ON(cond)
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++#include "debug.h"
++
++#include "branch.h"
++#include "cpup.h"
++#include "dcsub.h"
++#include "dentry.h"
++#include "dir.h"
++#include "file.h"
++#include "hinode.h"
++#include "inode.h"
++#include "misc.h"
++#include "module.h"
++#include "opts.h"
++#include "super.h"
++#include "sysaufs.h"
++#include "vfsub.h"
++#include "whout.h"
++#include "wkq.h"
++/* reserved for future use */
++/* #include "xattr.h" */
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_MODULE
++
++/* call ksize() or not */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22) \
++ && !defined(CONFIG_AUFS_KSIZE_PATCH)
++#define ksize(p) (0U)
++#endif
++
++#endif /* CONFIG_AUFS_MODULE */
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_H__ */
+diff --git a/fs/aufs/br_fuse.c b/fs/aufs/br_fuse.c
+new file mode 100644
+index 0000000..9b614b6
+--- /dev/null
++++ b/fs/aufs/br_fuse.c
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * special handling for inode attributes on FUSE branch
++ *
++ * $Id: br_fuse.c,v 1.7 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/* h_mnt can be NULL, is it safe? */
++int au_update_fuse_h_inode(struct vfsmount *h_mnt, struct dentry *h_dentry)
++{
++ int err;
++ struct kstat st;
++
++ LKTRTrace("%.*s\n", AuDLNPair(h_dentry));
++
++ err = 0;
++ if (h_dentry->d_inode
++ /* && atomic_read(&h_dentry->d_inode->i_count) */
++ && au_test_fuse(h_dentry->d_sb)) {
++ err = vfsub_getattr(h_mnt, h_dentry, &st, /*dlgt*/0);
++ if (unlikely(err)) {
++ AuDbg("err %d\n", err);
++ au_debug_on();
++ AuDbgDentry(h_dentry);
++ au_debug_off();
++ WARN_ON(err);
++ }
++ }
++ return err;
++}
++
++#if 0 /* temp */
++/*
++ * This function was born after a discussion with the FUSE developer.
++ * The inode attributes on a filesystem who defines i_op->getattr()
++ * is unreliable since such fs may not maintain the attributes at lookup.
++ * This function doesn't want the result of stat, instead wants the side-effect
++ * which refreshes the attributes.
++ * Hmm, there seems to be no such filesystem except fuse.
++ */
++int vfsub_i_attr(struct vfsmount *mnt, struct dentry *dentry, int dlgt)
++{
++ int err;
++ struct inode *inode;
++ struct inode_operations *op;
++ struct kstat st;
++
++ inode = dentry->d_inode;
++ AuDebugOn(!inode);
++
++ err = 0;
++ op = inode->i_op;
++ if (op && op->getattr && !au_test_aufs(dentry->d_sb)) {
++ err = security_inode_getattr(mnt, dentry);
++ if (!err)
++ err = op->getattr(mnt, dentry, &st);
++ }
++ AuTraceErr(err);
++ return err;
++}
++#endif
+diff --git a/fs/aufs/br_nfs.c b/fs/aufs/br_nfs.c
+new file mode 100644
+index 0000000..74e34f2
+--- /dev/null
++++ b/fs/aufs/br_nfs.c
+@@ -0,0 +1,390 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * lookup functions for NFS branch in linux-2.6.19 and later
++ *
++ * $Id: br_nfs.c,v 1.8 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) \
++ || !defined(CONFIG_AUFS_BR_NFS)
++#error mis-configuraion or Makefile
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++static struct file *au_find_h_intent(struct au_hdentry *hd, struct file *file)
++{
++ struct file *h_file, *hf;
++ struct au_hdintent *hdi, *tmp, *do_free;
++
++ LKTRTrace("%.*s\n", AuDLNPair(hd->hd_dentry));
++
++ h_file = NULL;
++ do_free = NULL;
++ spin_lock(&hd->hd_lock);
++ list_for_each_entry_safe(hdi, tmp, hd->hd_intent_list, hdi_list) {
++ hf = hdi->hdi_file[AuIntent_BRANCH];
++ if (hdi->hdi_file[AuIntent_AUFS] == file
++ && hf->f_dentry == hd->hd_dentry) {
++ h_file = hf;
++ do_free = hdi;
++ list_del(&hdi->hdi_list);
++ break;
++ }
++ }
++ spin_unlock(&hd->hd_lock);
++ kfree(do_free);
++
++ return h_file;
++}
++
++struct file *au_h_intent(struct dentry *dentry, aufs_bindex_t bindex,
++ struct file *file)
++{
++ struct file *h_file;
++ struct au_hdentry *hd = au_di(dentry)->di_hdentry + bindex;
++
++ LKTRTrace("%.*s, b%d, f %p\n", AuDLNPair(dentry), bindex, file);
++ DiMustAnyLock(dentry);
++ AuDebugOn(bindex < au_di(dentry)->di_bstart
++ || bindex > au_di(dentry)->di_bend);
++
++ h_file = NULL;
++ if (!hd->hd_intent_list || !file)
++ return h_file; /* success */
++
++ /* AuDebugOn(au_test_wkq(current)); */
++ h_file = au_find_h_intent(hd, file);
++ return h_file;
++}
++
++static int au_set_h_intent(struct dentry *dentry, aufs_bindex_t bindex,
++ struct file *file, struct file *h_file)
++{
++ int err;
++ struct au_hdentry *hd = au_di(dentry)->di_hdentry + bindex;
++ struct au_hdintent *hdi;
++ struct file *hf;
++
++ LKTRTrace("%.*s, b%d, f %p\n", AuDLNPair(dentry), bindex, file);
++ /* d_revalidate() holds read_lock */
++ /* DiMustWriteLock(dentry); */
++ AuDebugOn(bindex < au_di(dentry)->di_bstart
++ || bindex > au_di(dentry)->di_bend
++ || !file
++ || !h_file
++ /* || au_test_wkq(current) */);
++
++ err = -ENOMEM;
++ if (hd->hd_intent_list) {
++ while (1) {
++ hf = au_find_h_intent(hd, file);
++ if (!hf)
++ break;
++ fput(hf);
++ AuWarn("freed hfile %.*s b%d left\n",
++ AuDLNPair(dentry), bindex);
++ }
++ } else {
++ spin_lock(&hd->hd_lock);
++ if (!hd->hd_intent_list) {
++ hd->hd_intent_list
++ = kmalloc(sizeof(*hd->hd_intent_list),
++ GFP_ATOMIC);
++ if (unlikely(!hd->hd_intent_list)) {
++ spin_unlock(&hd->hd_lock);
++ goto out;
++ }
++ INIT_LIST_HEAD(hd->hd_intent_list);
++ }
++ spin_unlock(&hd->hd_lock);
++ }
++
++ hdi = kmalloc(sizeof(*hdi), GFP_NOFS);
++ if (unlikely(!hdi))
++ goto out;
++
++ err = 0;
++ /* hdi->hdi_pid = current->pid; */
++ hdi->hdi_file[AuIntent_AUFS] = file;
++ hdi->hdi_file[AuIntent_BRANCH] = h_file;
++ spin_lock(&hd->hd_lock);
++ list_add(&hdi->hdi_list, hd->hd_intent_list);
++ spin_unlock(&hd->hd_lock);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_br_nfs_h_intent(struct file *nd_file, struct dentry *dentry,
++ aufs_bindex_t bindex, struct nameidata *nd)
++{
++ int err;
++
++ AuTraceEnter();
++
++ err = 0;
++ if (!nd_file)
++ goto out;
++
++ AuDebugOn(!nd);
++ err = au_set_h_intent(dentry, bindex, nd->intent.open.file, nd_file);
++ if (unlikely(err)) {
++ fput(nd_file);
++ au_set_h_dptr(dentry, bindex, NULL);
++ /* todo: update bstart and bend? */
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_hintent_put(struct au_hdentry *hd, int do_free)
++{
++ struct au_hdintent *hdi, *tmp;
++ struct file *hf;
++
++ if (hd->hd_intent_list) {
++ /* no spin lock */
++ list_for_each_entry_safe(hdi, tmp, hd->hd_intent_list,
++ hdi_list) {
++ LKTRTrace("hdi %p\n", hdi);
++ hf = hdi->hdi_file[AuIntent_BRANCH];
++ if (hf)
++ fput(hf);
++ /* list_del(&hdi->hdi_list); */
++ kfree(hdi);
++ }
++ if (do_free)
++ kfree(hd->hd_intent_list);
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++#if 0
++/* subset of nameidata */
++struct au_ndsub {
++ struct dentry *dentry;
++ struct vfsmount *mnt;
++ unsigned int flags;
++
++ union {
++ struct open_intent open;
++ } intent;
++};
++
++static void au_ndsub_restore(struct nameidata *nd, struct au_ndsub *save)
++{
++ nd->dentry = save->dentry;
++ nd->mnt = save->mnt;
++ nd->flags = save->flags;
++ nd->intent = save->intent;
++}
++#endif
++
++int au_fake_intent(/* struct au_ndsub *save, */struct nameidata *nd,
++ struct au_branch *br)
++{
++ int err;
++
++ LKTRTrace("perm %d\n", br->br_perm);
++
++ err = 0;
++#if 0
++ save->dentry = nd->dentry;
++ save->mnt = nd->mnt;
++ save->flags = nd->flags;
++ save->intent = nd->intent;
++#endif
++
++ nd->intent.open.file = NULL;
++ if (nd->flags & LOOKUP_OPEN) {
++ if (au_test_fs_intent(br->br_mnt->mnt_sb)) {
++ err = -ENFILE;
++ nd->intent.open.file = get_empty_filp();
++ if (unlikely(!nd->intent.open.file))
++ goto out;
++ err = 0;
++ }
++ if (!au_br_writable(br->br_perm)) {
++ nd->intent.open.flags = FMODE_READ
++ | au_file_roflags(nd->intent.open.flags);
++ nd->flags &= ~LOOKUP_CREATE;
++ }
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static void au_put_filp(struct file *file)
++{
++#if !defined(CONFIG_AUFS_MODULE) || defined(CONFIG_AUFS_PUT_FILP_PATCH)
++ if (unlikely(file))
++ put_filp(file);
++#else
++ WARN_ONCE(file, "unexpected put_fillp() call");
++#endif
++}
++
++int au_hin_after_reval(struct nameidata *nd, struct dentry *dentry,
++ aufs_bindex_t bindex, struct file *file)
++{
++ int err;
++
++ LKTRTrace("nd %p, %.*s, b%d, f %d\n",
++ nd, AuDLNPair(dentry), bindex, !!file);
++
++ err = 0;
++ if ((nd->flags & LOOKUP_OPEN)
++ && nd->intent.open.file
++ && !IS_ERR(nd->intent.open.file)) {
++ if (nd->intent.open.file->f_dentry) {
++ err = au_set_h_intent(dentry, bindex, file,
++ nd->intent.open.file);
++ if (!err)
++ nd->intent.open.file = NULL;
++ }
++ au_put_filp(nd->intent.open.file);
++ }
++
++ return err;
++}
++
++#ifdef CONFIG_AUFS_DLGT
++struct au_lookup_hash_args {
++ struct dentry **errp;
++ struct qstr *name;
++ struct dentry *base;
++ struct nameidata *nd;
++};
++
++static void au_call_lookup_hash(void *args)
++{
++ struct au_lookup_hash_args *a = args;
++ *a->errp = vfsub__lookup_hash(a->name, a->base, a->nd);
++}
++
++static struct dentry *
++au_lkup_hash_dlgt(struct qstr *this, struct dentry *parent,
++ struct nameidata *nd, unsigned int flags)
++{
++ struct dentry *dentry;
++ int dirperm1;
++
++ dirperm1 = au_ftest_ndx(flags, DIRPERM1);
++ if (!dirperm1 && !au_ftest_ndx(flags, DLGT))
++ dentry = vfsub__lookup_hash(this, parent, nd);
++ else {
++ int wkq_err;
++ struct au_lookup_hash_args args = {
++ .errp = &dentry,
++ .name = this,
++ .base = parent,
++ .nd = nd
++ };
++ wkq_err = au_wkq_wait(au_call_lookup_hash, &args,
++ /*dlgt*/!dirperm1);
++ if (unlikely(wkq_err))
++ dentry = ERR_PTR(wkq_err);
++ }
++
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++#else
++static struct dentry *
++au_lkup_hash_dlgt(struct qstr *this, struct dentry *parent,
++ struct nameidata *nd, unsigned int flags)
++{
++ return vfsub__lookup_hash(this, parent, nd);
++}
++#endif /* CONFIG_AUFS_DLGT */
++
++struct dentry *au_lkup_hash(const char *name, struct dentry *parent,
++ int len, struct au_ndx *ndx)
++{
++ struct dentry *dentry;
++ char *p;
++ unsigned long hash;
++ struct qstr this;
++ unsigned int c;
++ struct nameidata tmp_nd, *ndo;
++ int err;
++
++ LKTRTrace("%.*s/%.*s\n", AuDLNPair(parent), len, name);
++
++ /* todo: export and call __lookup_one_len() in fs/namei.c? */
++ dentry = ERR_PTR(-EACCES);
++ this.name = name;
++ this.len = len;
++ if (unlikely(!len))
++ goto out;
++
++ p = (void *)name;
++ hash = init_name_hash();
++ while (len--) {
++ c = *p++;
++ if (unlikely(c == '/' || c == '\0'))
++ goto out;
++ hash = partial_name_hash(c, hash);
++ }
++ this.hash = end_name_hash(hash);
++
++ ndo = ndx->nd;
++ if (ndo) {
++ tmp_nd = *ndo;
++ err = au_fake_intent(&tmp_nd, ndx->br);
++ dentry = ERR_PTR(err);
++ if (unlikely(err))
++ goto out_intent;
++ } else
++ memset(&tmp_nd, 0, sizeof(tmp_nd));
++
++ tmp_nd.dentry = dget(parent);
++ tmp_nd.mnt = mntget(ndx->nfsmnt);
++ dentry = au_lkup_hash_dlgt(&this, parent, &tmp_nd, ndx->flags);
++ if (!IS_ERR(dentry)) {
++ /* why negative dentry for a new dir was unhashed? */
++ if (unlikely(d_unhashed(dentry)))
++ d_rehash(dentry);
++ if (tmp_nd.intent.open.file
++ && tmp_nd.intent.open.file->f_dentry) {
++ ndx->nd_file = tmp_nd.intent.open.file;
++ tmp_nd.intent.open.file = NULL;
++ /* au_br_get(ndx->br); */
++ }
++ }
++ path_release(&tmp_nd);
++
++ out_intent:
++ au_put_filp(tmp_nd.intent.open.file);
++ out:
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
+diff --git a/fs/aufs/br_xfs.c b/fs/aufs/br_xfs.c
+new file mode 100644
+index 0000000..b4f7421
+--- /dev/null
++++ b/fs/aufs/br_xfs.c
+@@ -0,0 +1,74 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * special handling inode attributes on XFS branch in linux-2.6.24 and later
++ *
++ * $Id: br_xfs.c,v 1.4 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24) \
++ || (!defined(CONFIG_XFS_FS) && !defined(CONFIG_XFS_FS_MODULE))
++#error mis-configuraion or Makefile
++#endif
++
++/* h_mnt can be NULL, is it safe? */
++dev_t au_h_rdev(struct inode *h_inode, struct vfsmount *h_mnt,
++ struct dentry *h_dentry)
++{
++ dev_t rdev;
++ int err;
++ struct kstat st;
++
++ LKTRTrace("hi%lu\n", h_inode->i_ino);
++ if (h_dentry)
++ LKTRTrace("%.*s\n", AuDLNPair(h_dentry));
++
++ rdev = h_inode->i_rdev;
++ if (!rdev || !au_test_xfs(h_inode->i_sb))
++ goto out;
++
++ rdev = 0;
++ if (!h_dentry) {
++ err = 0;
++ h_dentry = d_find_alias(h_inode);
++ if (unlikely(!h_dentry))
++ goto failure;
++ err = PTR_ERR(h_dentry);
++ if (IS_ERR(h_dentry)) {
++ h_dentry = NULL;
++ goto failure;
++ }
++ LKTRTrace("%.*s\n", AuDLNPair(h_dentry));
++ } else
++ dget(h_dentry);
++
++ err = vfsub_getattr(h_mnt, h_dentry, &st, /*dlgt*/0);
++ dput(h_dentry);
++ if (!err) {
++ rdev = st.rdev;
++ goto out; /* success */
++ }
++
++ failure:
++ AuIOErr("failed rdev for XFS inode, hi%lu, %d\n", h_inode->i_ino, err);
++ out:
++ return rdev;
++}
+diff --git a/fs/aufs/branch.c b/fs/aufs/branch.c
+new file mode 100644
+index 0000000..bcf1a3d
+--- /dev/null
++++ b/fs/aufs/branch.c
+@@ -0,0 +1,1036 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * branch management
++ *
++ * $Id: branch.c,v 1.90 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/iso_fs.h>
++#include <linux/loop.h>
++#include <linux/romfs_fs.h>
++#include <linux/smp_lock.h>
++#include "aufs.h"
++
++static void au_br_do_free(struct au_branch *br)
++{
++ int i;
++ struct au_wbr *wbr;
++
++ AuTraceEnter();
++
++ if (br->br_xino.xi_file)
++ fput(br->br_xino.xi_file);
++ mutex_destroy(&br->br_xino.xi_nondir_mtx);
++ wbr = br->br_wbr;
++ if (wbr)
++ for (i = 0; i < AuBrWh_Last; i++)
++ dput(wbr->wbr_wh[i]);
++ /* do not call au_br_nfs_lockdep_off() here */
++ if (br->br_mnt && !au_test_nfs(br->br_mnt->mnt_sb))
++ mntput(br->br_mnt);
++ else {
++ lockdep_off();
++ mntput(br->br_mnt);
++ lockdep_on();
++ }
++ AuDebugOn(au_br_count(br));
++ if (wbr) {
++ AuDebugOn(atomic_read(&wbr->wbr_wh_running));
++ au_rwsem_destroy(&wbr->wbr_wh_rwsem);
++ }
++ sysaufs_br_put(br);
++ kfree(wbr);
++ kfree(br);
++}
++
++/*
++ * frees all branches
++ */
++void au_br_free(struct au_sbinfo *sbinfo)
++{
++ aufs_bindex_t bmax;
++ struct au_branch **br;
++
++ AuTraceEnter();
++ bmax = sbinfo->si_bend + 1;
++ br = sbinfo->si_branch;
++ while (bmax--)
++ au_br_do_free(*br++);
++}
++
++/*
++ * find the index of a branch which is specified by @br_id.
++ */
++int au_br_index(struct super_block *sb, aufs_bindex_t br_id)
++{
++ aufs_bindex_t bindex, bend;
++
++ AuTraceEnter();
++
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++)
++ if (au_sbr_id(sb, bindex) == br_id)
++ return bindex;
++ return -1;
++}
++
++/*
++ * test if the @h_sb is real-readonly.
++ */
++int au_test_def_rr(struct super_block *h_sb)
++{
++ switch (h_sb->s_magic) {
++#ifdef CONFIG_AUFS_RR_SQUASHFS
++ case SQUASHFS_MAGIC_LZMA:
++ case SQUASHFS_MAGIC:
++ case SQUASHFS_MAGIC_LZMA_SWAP:
++ case SQUASHFS_MAGIC_SWAP:
++ return 1; /* real readonly */
++#endif
++
++#if defined(CONFIG_ISO9660_FS) || defined(CONFIG_ISO9660_FS_MODULE)
++ case ISOFS_SUPER_MAGIC:
++ return 1;
++#endif
++
++#if defined(CONFIG_CRAMFS) || defined(CONFIG_CRAMFS_MODULE)
++ case CRAMFS_MAGIC:
++ return 1;
++#endif
++
++#if defined(CONFIG_ROMFS_FS) || defined(CONFIG_ROMFS_FS_MODULE)
++ case ROMFS_MAGIC:
++ return 1;
++#endif
++
++ default:
++ return 0;
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * test if two hidden_dentries have overlapping branches.
++ */
++static int do_test_overlap(struct super_block *sb, struct dentry *h_d1,
++ struct dentry *h_d2)
++{
++ struct dentry *d;
++
++ LKTRTrace("%.*s, %.*s\n", AuDLNPair(h_d1), AuDLNPair(h_d2));
++
++ d = au_test_subdir(h_d1, h_d2);
++ if (unlikely(d)) {
++ AuDbgDentry(h_d1);
++ AuDbgDentry(h_d2);
++ }
++ return !!d;
++}
++
++static int test_overlap_loopback(struct super_block *sb, struct dentry *h_d1,
++ struct dentry *h_d2)
++{
++#if defined(CONFIG_BLK_DEV_LOOP) || defined(CONFIG_BLK_DEV_LOOP_MODULE)
++ struct inode *h_inode;
++ struct loop_device *l;
++
++ LKTRTrace("%.*s, %.*s\n", AuDLNPair(h_d1), AuDLNPair(h_d2));
++ AuDbgDentry(h_d1);
++ AuDbgDentry(h_d2);
++ AuDbgSb(h_d1->d_sb);
++ AuDbgSb(h_d2->d_sb);
++
++ h_inode = h_d1->d_inode;
++ if (MAJOR(h_inode->i_sb->s_dev) != LOOP_MAJOR)
++ return 0;
++
++ l = h_inode->i_sb->s_bdev->bd_disk->private_data;
++ h_d1 = l->lo_backing_file->f_dentry;
++ /* h_d1 can be local NFS. in this case aufs cannot detect the loop */
++ AuDbgDentry(h_d1);
++ AuDbgDentry(h_d2);
++ AuDbgSb(h_d1->d_sb);
++ AuDbgSb(h_d2->d_sb);
++ if (unlikely(h_d1->d_sb == sb))
++ return 1;
++ return do_test_overlap(sb, h_d1, h_d2);
++#else
++ return 0;
++#endif
++}
++
++static int test_overlap(struct super_block *sb, struct dentry *h_d1,
++ struct dentry *h_d2)
++{
++ LKTRTrace("d1 %.*s, d2 %.*s\n", AuDLNPair(h_d1), AuDLNPair(h_d2));
++
++ if (unlikely(h_d1 == h_d2)) {
++ AuDbgDentry(h_d1);
++ AuDbgDentry(h_d2);
++ return 1;
++ }
++ return do_test_overlap(sb, h_d1, h_d2)
++ || do_test_overlap(sb, h_d2, h_d1)
++ || test_overlap_loopback(sb, h_d1, h_d2)
++ || test_overlap_loopback(sb, h_d2, h_d1);
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int au_br_init_wh(struct super_block *sb, aufs_bindex_t bindex,
++ struct au_branch *br, int new_perm,
++ struct dentry *h_root, struct vfsmount *h_mnt)
++{
++ int err, old_perm;
++ struct inode *h_dir;
++ struct au_wbr *wbr;
++
++ LKTRTrace("b%d, new_perm %d\n", bindex, new_perm);
++ SiMustWriteLock(sb);
++
++ wbr = br->br_wbr;
++ h_dir = h_root->d_inode;
++ old_perm = br->br_perm;
++ vfsub_i_lock_nested(h_dir, AuLsc_I_PARENT);
++ if (wbr)
++ wbr_wh_write_lock(wbr);
++ br->br_perm = new_perm;
++ err = au_wh_init(h_root, br, h_mnt, sb, bindex);
++ br->br_perm = old_perm;
++ if (wbr)
++ wbr_wh_write_unlock(wbr);
++ vfsub_i_unlock(h_dir);
++ if (!err && wbr && !au_br_writable(new_perm)) {
++ AuDebugOn(wbr->wbr_whbase);
++ AuDebugOn(wbr->wbr_plink);
++ AuDebugOn(wbr->wbr_tmp);
++ kfree(wbr);
++ br->br_wbr = NULL;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * returns a newly allocated branch. @new_nbranch is a number of branches
++ * after adding a branch.
++ */
++static struct au_branch *alloc_addbr(struct super_block *sb, int new_nbranch,
++ int perm)
++{
++ struct au_branch **branchp, *add_branch;
++ int sz;
++ void *p;
++ struct dentry *root;
++ struct inode *inode;
++ struct au_hinode *hinodep;
++ struct au_hdentry *hdentryp;
++
++ LKTRTrace("new_nbranch %d\n", new_nbranch);
++ SiMustWriteLock(sb);
++ root = sb->s_root;
++ DiMustWriteLock(root);
++ inode = root->d_inode;
++ IiMustWriteLock(inode);
++
++ add_branch = kmalloc(sizeof(*add_branch), GFP_NOFS);
++ if (unlikely(!add_branch))
++ goto out;
++ add_branch->br_sabr = sysaufs_br_alloc();
++ if (unlikely(!add_branch->br_sabr))
++ goto out;
++ add_branch->br_wbr = NULL;
++ if (au_br_writable(perm)) {
++ add_branch->br_wbr = kmalloc(sizeof(*add_branch->br_wbr),
++ GFP_NOFS);
++ if (unlikely(!add_branch->br_wbr))
++ goto out_sabr;
++ }
++
++ sz = sizeof(*branchp) * (new_nbranch - 1);
++ if (unlikely(!sz))
++ sz = sizeof(*branchp);
++ p = au_sbi(sb)->si_branch;
++ branchp = au_kzrealloc(p, sz, sizeof(*branchp) * new_nbranch, GFP_NOFS);
++ if (unlikely(!branchp))
++ goto out_wbr;
++ au_sbi(sb)->si_branch = branchp;
++
++ sz = sizeof(*hdentryp) * (new_nbranch - 1);
++ if (unlikely(!sz))
++ sz = sizeof(*hdentryp);
++ p = au_di(root)->di_hdentry;
++ hdentryp = au_kzrealloc(p, sz, sizeof(*hdentryp) * new_nbranch,
++ GFP_NOFS);
++ if (unlikely(!hdentryp))
++ goto out_wbr;
++ au_di(root)->di_hdentry = hdentryp;
++
++ sz = sizeof(*hinodep) * (new_nbranch - 1);
++ if (unlikely(!sz))
++ sz = sizeof(*hinodep);
++ p = au_ii(inode)->ii_hinode;
++ hinodep = au_kzrealloc(p, sz, sizeof(*hinodep) * new_nbranch, GFP_NOFS);
++ if (unlikely(!hinodep))
++ goto out_wbr;
++ au_ii(inode)->ii_hinode = hinodep;
++ return add_branch; /* success */
++
++ out_wbr:
++ kfree(add_branch->br_wbr);
++ out_sabr:
++ sysaufs_br_put(add_branch);
++ out:
++ kfree(add_branch);
++ AuTraceErr(-ENOMEM);
++ return ERR_PTR(-ENOMEM);
++}
++
++/*
++ * test if the branch permission is legal or not.
++ */
++static int test_br(struct super_block *sb, struct inode *inode, int brperm,
++ char *path)
++{
++ int err;
++
++ err = 0;
++ if (unlikely(au_br_writable(brperm) && IS_RDONLY(inode))) {
++ AuErr("write permission for readonly fs or inode, %s\n", path);
++ err = -EINVAL;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_unsupported_fs(struct super_block *sb)
++{
++ return sb->s_magic == PROC_SUPER_MAGIC
++#ifdef SYSFS_MAGIC
++ || sb->s_magic == SYSFS_MAGIC
++#endif
++ || !strcmp(au_sbtype(sb), "unionfs");
++}
++
++/*
++ * returns:
++ * 0: success, the caller will add it
++ * plus: success, it is already unified, the caller should ignore it
++ * minus: error
++ */
++static int test_add(struct super_block *sb, struct au_opt_add *add, int remount)
++{
++ int err;
++ struct dentry *root;
++ struct inode *inode, *h_inode;
++ aufs_bindex_t bend, bindex;
++
++ LKTRTrace("%s, remo%d\n", add->path, remount);
++
++ root = sb->s_root;
++ bend = au_sbend(sb);
++ if (unlikely(bend >= 0 && au_find_dbindex(root, add->nd.dentry) >= 0)) {
++ err = 1;
++ if (!remount) {
++ err = -EINVAL;
++ AuErr("%s duplicated\n", add->path);
++ }
++ goto out;
++ }
++
++ err = -ENOSPC; /* -E2BIG; */
++ if (unlikely(AUFS_BRANCH_MAX <= add->bindex
++ || AUFS_BRANCH_MAX - 1 <= bend)) {
++ AuErr("number of branches exceeded %s\n", add->path);
++ goto out;
++ }
++
++ err = -EDOM;
++ if (unlikely(add->bindex < 0 || bend + 1 < add->bindex)) {
++ AuErr("bad index %d\n", add->bindex);
++ goto out;
++ }
++
++ inode = add->nd.dentry->d_inode;
++ AuDebugOn(!inode || !S_ISDIR(inode->i_mode));
++ err = -ENOENT;
++ if (unlikely(!inode->i_nlink)) {
++ AuErr("no existence %s\n", add->path);
++ goto out;
++ }
++
++ err = -EINVAL;
++ if (unlikely(inode->i_sb == sb)) {
++ AuErr("%s must be outside\n", add->path);
++ goto out;
++ }
++
++ if (unlikely(au_test_nested(inode->i_sb))) {
++ AuErr("nested " AUFS_NAME " %s\n", add->path);
++ goto out;
++ }
++
++ if (unlikely(au_unsupported_fs(inode->i_sb))) {
++ AuErr("unsupported filesystem, %s\n", add->path);
++ goto out;
++ }
++
++ if (unlikely(au_test_unsupported_nfs(inode->i_sb))) {
++ AuErr(AuNoNfsBranchMsg " %s\n", add->path);
++ goto out;
++ }
++
++ if (unlikely(au_test_unsupported_nfs4(inode->i_sb))) {
++ AuErr(AuNoNfsv4BranchMsg " %s\n", add->path);
++ goto out;
++ }
++
++ err = test_br(sb, add->nd.dentry->d_inode, add->perm, add->path);
++ if (unlikely(err))
++ goto out;
++
++ if (bend < 0)
++ return 0; /* success */
++
++ err = -EINVAL;
++ for (bindex = 0; bindex <= bend; bindex++)
++ if (unlikely(test_overlap(sb, add->nd.dentry,
++ au_h_dptr(root, bindex)))) {
++ AuErr("%s is overlapped\n", add->path);
++ goto out;
++ }
++
++ err = 0;
++ h_inode = au_h_dptr(root, 0)->d_inode;
++ if (unlikely(au_opt_test(au_mntflags(sb), WARN_PERM)
++ && ((h_inode->i_mode & S_IALLUGO)
++ != (inode->i_mode & S_IALLUGO)
++ || h_inode->i_uid != inode->i_uid
++ || h_inode->i_gid != inode->i_gid)))
++ AuWarn("uid/gid/perm %s %u/%u/0%o, %u/%u/0%o\n",
++ add->path,
++ inode->i_uid, inode->i_gid, (inode->i_mode & S_IALLUGO),
++ h_inode->i_uid, h_inode->i_gid,
++ (h_inode->i_mode & S_IALLUGO));
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_wbr_init(struct au_branch *br, struct super_block *sb,
++ int perm, struct dentry *dentry, struct vfsmount *mnt)
++{
++ int err;
++ struct au_wbr *wbr;
++
++ AuTraceEnter();
++ wbr = br->br_wbr;
++ AuDebugOn(!wbr);
++
++ au_rw_init_nolock(&wbr->wbr_wh_rwsem);
++ memset(wbr->wbr_wh, 0, sizeof(wbr->wbr_wh));
++ atomic_set(&wbr->wbr_wh_running, 0);
++ wbr->wbr_bytes = 0;
++
++ err = au_br_init_wh(sb, /*bindex*/-1, br, perm, dentry, mnt);
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_br_init(struct au_branch *br, struct super_block *sb,
++ struct au_opt_add *add)
++{
++ int err;
++ unsigned int mnt_flags;
++
++ AuTraceEnter();
++
++ err = 0;
++ br->br_mnt = NULL;
++ br->br_xino.xi_file = NULL;
++ mutex_init(&br->br_xino.xi_nondir_mtx);
++ atomic_set(&br->br_xino_running, 0);
++ atomic_set(&br->br_count, 0);
++
++ if (au_br_writable(add->perm)) {
++ err = au_wbr_init(br, sb, add->perm, add->nd.dentry,
++ add->nd.mnt);
++ if (unlikely(err))
++ goto out;
++ }
++
++ br->br_mnt = mntget(add->nd.mnt);
++ mnt_flags = au_mntflags(sb);
++ if (au_opt_test(mnt_flags, XINO)) {
++ err = au_xino_br(sb, br, add->nd.dentry->d_inode->i_ino,
++ au_sbr(sb, 0)->br_xino.xi_file, /*do_test*/1);
++ if (unlikely(err)) {
++ AuDebugOn(br->br_xino.xi_file);
++ goto out;
++ }
++#if 0 /* reserved for future use */
++ } else if (au_opt_test(mnt_flags, XINODIR)) {
++ err = au_xinodir_br(sb, br, add->nd.dentry->d_inode->i_ino,
++ /*do_test*/1);
++ if (unlikely(err)) {
++ AuDebugOn(br->br_xino.xi_file);
++ goto out;
++ }
++#endif
++ }
++
++ br->br_id = au_new_br_id(sb);
++ br->br_perm = add->perm;
++ br->br_xino_upper = AUFS_XINO_TRUNC_INIT;
++ br->br_generation = au_sigen(sb);
++ /* smp_mb(); */ /* atomic_set */
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_br_add(struct super_block *sb, struct au_opt_add *add, int remount)
++{
++ int err, amount;
++ aufs_bindex_t bend, add_bindex;
++ struct dentry *root, *dentry;
++ struct au_iinfo *iinfo;
++ struct au_sbinfo *sbinfo;
++ struct au_dinfo *dinfo;
++ struct inode *root_inode;
++ unsigned long long maxb;
++ struct au_branch **branchp, *add_branch;
++ struct au_hdentry *hdentryp;
++ struct au_hinode *hinodep;
++
++ dentry = add->nd.dentry;
++ LKTRTrace("b%d, %s, 0x%x, %.*s\n",
++ add->bindex, add->path, add->perm, AuDLNPair(dentry));
++ SiMustWriteLock(sb);
++ root = sb->s_root;
++ DiMustWriteLock(root);
++ root_inode = root->d_inode;
++ IMustLock(root_inode);
++ IiMustWriteLock(root_inode);
++
++ err = test_add(sb, add, remount);
++ if (unlikely(err < 0))
++ goto out;
++ if (err) {
++ err = 0;
++ goto out; /* success */
++ }
++
++ bend = au_sbend(sb);
++ add_branch = alloc_addbr(sb, bend + 2, add->perm);
++ err = PTR_ERR(add_branch);
++ if (IS_ERR(add_branch))
++ goto out;
++ err = au_br_init(add_branch, sb, add);
++ if (unlikely(err)) {
++ au_br_do_free(add_branch);
++ goto out;
++ }
++
++ add_bindex = add->bindex;
++ if (remount)
++ sysaufs_brs_del(sb);
++
++ sbinfo = au_sbi(sb);
++ dinfo = au_di(root);
++ iinfo = au_ii(root_inode);
++
++ amount = bend + 1 - add_bindex;
++ branchp = sbinfo->si_branch + add_bindex;
++ memmove(branchp + 1, branchp, sizeof(*branchp) * amount);
++ *branchp = add_branch;
++ hdentryp = dinfo->di_hdentry + add_bindex;
++ memmove(hdentryp + 1, hdentryp, sizeof(*hdentryp) * amount);
++ au_h_dentry_init(hdentryp);
++ hinodep = iinfo->ii_hinode + add_bindex;
++ memmove(hinodep + 1, hinodep, sizeof(*hinodep) * amount);
++ hinodep->hi_inode = NULL;
++ au_hin_init(hinodep, NULL);
++
++ sbinfo->si_bend++;
++ dinfo->di_bend++;
++ iinfo->ii_bend++;
++ if (unlikely(bend < 0)) {
++ sbinfo->si_bend = 0;
++ dinfo->di_bstart = 0;
++ iinfo->ii_bstart = 0;
++ }
++ au_set_h_dptr(root, add_bindex, dget(dentry));
++ au_set_h_iptr(root_inode, add_bindex, au_igrab(dentry->d_inode), 0);
++ if (!add_bindex)
++ au_cpup_attr_all(root_inode, /*force*/1);
++ else
++ au_add_nlink(root_inode, dentry->d_inode);
++ maxb = dentry->d_sb->s_maxbytes;
++ if (sb->s_maxbytes < maxb)
++ sb->s_maxbytes = maxb;
++
++ if (remount)
++ sysaufs_brs_add(sb);
++
++ /* safe d_parent reference */
++ if (!au_xino_def_br(sbinfo)
++ && add_branch->br_xino.xi_file
++ && add_branch->br_xino.xi_file->f_dentry->d_parent == dentry)
++ au_xino_def_br_set(add_branch, sbinfo);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++#define AuVerbose(do_info, fmt, args...) do { \
++ if (!do_info) \
++ LKTRTrace(fmt, ##args); \
++ else \
++ AuInfo(fmt, ##args); \
++} while (0)
++
++/*
++ * test if the branch is deletable or not.
++ */
++static int test_dentry_busy(struct dentry *root, aufs_bindex_t bindex,
++ au_gen_t sigen)
++{
++ int err, i, j, ndentry;
++ struct au_dcsub_pages dpages;
++ struct au_dpage *dpage;
++ struct dentry *d;
++ aufs_bindex_t bstart, bend;
++ unsigned char verbose;
++ struct inode *inode;
++
++ LKTRTrace("b%d, gen%d\n", bindex, sigen);
++ SiMustWriteLock(root->d_sb);
++
++ err = au_dpages_init(&dpages, GFP_NOFS);
++ if (unlikely(err))
++ goto out;
++ err = au_dcsub_pages(&dpages, root, NULL, NULL);
++ if (unlikely(err))
++ goto out_dpages;
++
++ verbose = !!au_opt_test(au_mntflags(root->d_sb), VERBOSE);
++ for (i = 0; !err && i < dpages.ndpage; i++) {
++ dpage = dpages.dpages + i;
++ ndentry = dpage->ndentry;
++ for (j = 0; !err && j < ndentry; j++) {
++ d = dpage->dentries[j];
++ AuDebugOn(!atomic_read(&d->d_count));
++ inode = d->d_inode;
++ AuDebugOn(!inode);
++ if (au_digen(d) == sigen
++ && au_iigen(inode) == sigen)
++ di_read_lock_child(d, AuLock_IR);
++ else {
++ di_write_lock_child(d);
++ err = au_reval_dpath(d, sigen);
++ if (!err)
++ di_downgrade_lock(d, AuLock_IR);
++ else {
++ di_write_unlock(d);
++ break;
++ }
++ }
++
++ bstart = au_dbstart(d);
++ bend = au_dbend(d);
++ if (bstart <= bindex
++ && bindex <= bend
++ && au_h_dptr(d, bindex)
++ && (!S_ISDIR(d->d_inode->i_mode)
++ || bstart == bend)) {
++ err = -EBUSY;
++ AuVerbose(verbose, "busy %.*s\n", AuDLNPair(d));
++ }
++ di_read_unlock(d, AuLock_IR);
++ }
++ }
++
++ out_dpages:
++ au_dpages_free(&dpages);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int test_inode_busy(struct super_block *sb, aufs_bindex_t bindex,
++ au_gen_t sigen)
++{
++ int err;
++ struct inode *i;
++ aufs_bindex_t bstart, bend;
++ unsigned char verbose;
++
++ LKTRTrace("b%d, gen%d\n", bindex, sigen);
++ SiMustWriteLock(sb);
++
++ err = 0;
++ verbose = !!au_opt_test(au_mntflags(sb), VERBOSE);
++ list_for_each_entry(i, &sb->s_inodes, i_sb_list) {
++ AuDebugOn(!atomic_read(&i->i_count));
++ if (!list_empty(&i->i_dentry))
++ continue;
++
++ if (au_iigen(i) == sigen)
++ ii_read_lock_child(i);
++ else {
++ ii_write_lock_child(i);
++ err = au_refresh_hinode_self(i);
++ if (!err)
++ ii_downgrade_lock(i);
++ else {
++ ii_write_unlock(i);
++ break;
++ }
++ }
++
++ bstart = au_ibstart(i);
++ bend = au_ibend(i);
++ if (bstart <= bindex
++ && bindex <= bend
++ && au_h_iptr(i, bindex)
++ && (!S_ISDIR(i->i_mode) || bstart == bend)) {
++ err = -EBUSY;
++ AuVerbose(verbose, "busy i%lu\n", i->i_ino);
++ ii_read_unlock(i);
++ break;
++ }
++ ii_read_unlock(i);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int test_children_busy(struct dentry *root, aufs_bindex_t bindex)
++{
++ int err;
++ au_gen_t sigen;
++
++ LKTRTrace("b%d\n", bindex);
++ SiMustWriteLock(root->d_sb);
++ DiMustWriteLock(root);
++ /* dont trust BKL */
++ AuDebugOn(!kernel_locked());
++
++ sigen = au_sigen(root->d_sb);
++ DiMustNoWaiters(root);
++ IiMustNoWaiters(root->d_inode);
++ di_write_unlock(root);
++ err = test_dentry_busy(root, bindex, sigen);
++ if (!err)
++ err = test_inode_busy(root->d_sb, bindex, sigen);
++ di_write_lock_child(root); /* aufs_write_lock() calls ..._child() */
++
++ AuTraceErr(err);
++ return err;
++}
++
++int au_br_del(struct super_block *sb, struct au_opt_del *del, int remount)
++{
++ int err, rerr, i;
++ aufs_bindex_t bindex, bend, br_id;
++ unsigned char do_wh, verbose;
++ struct au_sbinfo *sbinfo;
++ struct au_dinfo *dinfo;
++ struct au_iinfo *iinfo;
++ struct au_branch *br, **brp;
++ struct au_wbr *wbr;
++ struct au_hdentry *hdp;
++ struct au_hinode *hip;
++
++ LKTRTrace("%s, %.*s\n", del->path, AuDLNPair(del->h_root));
++ SiMustWriteLock(sb);
++ DiMustWriteLock(sb->s_root);
++ IiMustWriteLock(sb->s_root->d_inode);
++
++ err = 0;
++ bindex = au_find_dbindex(sb->s_root, del->h_root);
++ if (bindex < 0) {
++ if (remount)
++ goto out; /* success */
++ err = -ENOENT;
++ AuErr("%s no such branch\n", del->path);
++ goto out;
++ }
++ LKTRTrace("bindex b%d\n", bindex);
++
++ err = -EBUSY;
++ verbose = !!au_opt_test(au_mntflags(sb), VERBOSE);
++ bend = au_sbend(sb);
++ if (unlikely(!bend)) {
++ AuVerbose(verbose, "no more branches left\n");
++ goto out;
++ }
++ br = au_sbr(sb, bindex);
++ if (unlikely(au_br_count(br))) {
++ AuVerbose(verbose, "%d file(s) opened\n", au_br_count(br));
++ goto out;
++ }
++
++ wbr = br->br_wbr;
++ do_wh = wbr && (wbr->wbr_whbase || wbr->wbr_plink || wbr->wbr_tmp);
++ if (do_wh) {
++#if 0 /* reserved for future use */
++ /* remove whiteout base */
++ err = au_br_init_wh(sb, bindex, br, AuBr_RO, del->h_root,
++ br->br_mnt);
++ if (unlikely(err))
++ goto out;
++#else
++ for (i = 0; i < AuBrWh_Last; i++) {
++ dput(wbr->wbr_wh[i]);
++ wbr->wbr_wh[i] = NULL;
++ }
++#endif
++ }
++
++ err = test_children_busy(sb->s_root, bindex);
++ if (unlikely(err)) {
++ if (do_wh)
++ goto out_wh;
++ goto out;
++ }
++
++ err = 0;
++ if (remount)
++ sysaufs_brs_del(sb);
++ sbinfo = au_sbi(sb);
++ dinfo = au_di(sb->s_root);
++ iinfo = au_ii(sb->s_root->d_inode);
++
++ dput(au_h_dptr(sb->s_root, bindex));
++ au_hiput(iinfo->ii_hinode + bindex);
++ br_id = br->br_id;
++ au_br_do_free(br);
++
++ /* todo: realloc and shrink memory? */
++ if (bindex < bend) {
++ const aufs_bindex_t n = bend - bindex;
++
++ brp = sbinfo->si_branch + bindex;
++ memmove(brp, brp + 1, sizeof(*brp) * n);
++ hdp = dinfo->di_hdentry + bindex;
++ memmove(hdp, hdp + 1, sizeof(*hdp) * n);
++ hip = iinfo->ii_hinode + bindex;
++ memmove(hip, hip + 1, sizeof(*hip) * n);
++ }
++ sbinfo->si_branch[0 + bend] = NULL;
++ dinfo->di_hdentry[0 + bend].hd_dentry = NULL;
++ iinfo->ii_hinode[0 + bend].hi_inode = NULL;
++ au_hin_init(iinfo->ii_hinode + bend, NULL);
++
++ sbinfo->si_bend--;
++ dinfo->di_bend--;
++ iinfo->ii_bend--;
++ if (!bindex)
++ au_cpup_attr_all(sb->s_root->d_inode, /*force*/1);
++ else
++ au_sub_nlink(sb->s_root->d_inode, del->h_root->d_inode);
++ if (au_opt_test(au_mntflags(sb), PLINK))
++ au_plink_half_refresh(sb, br_id);
++
++ if (sb->s_maxbytes == del->h_root->d_sb->s_maxbytes) {
++ bend--;
++ sb->s_maxbytes = 0;
++ for (bindex = 0; bindex <= bend; bindex++) {
++ unsigned long long maxb;
++ maxb = au_sbr_sb(sb, bindex)->s_maxbytes;
++ if (sb->s_maxbytes < maxb)
++ sb->s_maxbytes = maxb;
++ }
++ }
++ if (remount)
++ sysaufs_brs_add(sb);
++
++ if (au_xino_def_br(sbinfo) == br)
++ au_xino_def_br_set(NULL, sbinfo);
++ goto out; /* success */
++
++ out_wh:
++ /* revert */
++ rerr = au_br_init_wh(sb, bindex, br, br->br_perm, del->h_root,
++ br->br_mnt);
++ if (rerr)
++ AuWarn("failed re-creating base whiteout, %s. (%d)\n",
++ del->path, rerr);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int do_need_sigen_inc(int a, int b)
++{
++ return au_br_whable(a) && !au_br_whable(b);
++}
++
++static int need_sigen_inc(int old, int new)
++{
++ return do_need_sigen_inc(old, new)
++ || do_need_sigen_inc(new, old);
++}
++
++static int au_br_mod_files_ro(struct super_block *sb, aufs_bindex_t bindex)
++{
++ int err;
++ struct file *file, *hf;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ /* no need file_list_lock() since sbinfo is locked */
++ err = 0;
++ list_for_each_entry(file, &sb->s_files, f_u.fu_list) {
++ LKTRTrace("%.*s\n", AuDLNPair(file->f_dentry));
++ if (!au_test_aufs_file(file))
++ continue;
++
++ fi_read_lock(file);
++ if (!S_ISREG(file->f_dentry->d_inode->i_mode)
++ || !(file->f_mode & FMODE_WRITE)
++ || au_fbstart(file) != bindex) {
++ FiMustNoWaiters(file);
++ fi_read_unlock(file);
++ continue;
++ }
++
++ if (unlikely(au_test_mmapped(file))) {
++ err = -EBUSY;
++ FiMustNoWaiters(file);
++ fi_read_unlock(file);
++ break;
++ }
++
++ /* todo: already flushed? */
++ hf = au_h_fptr(file, au_fbstart(file));
++ hf->f_flags = au_file_roflags(hf->f_flags);
++ hf->f_mode &= ~FMODE_WRITE;
++ put_write_access(hf->f_dentry->d_inode);
++ FiMustNoWaiters(file);
++ fi_read_unlock(file);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++int au_br_mod(struct super_block *sb, struct au_opt_mod *mod, int remount,
++ int *do_update)
++{
++ int err;
++ struct dentry *root;
++ aufs_bindex_t bindex;
++ struct au_branch *br;
++ struct inode *hidden_dir;
++
++ LKTRTrace("%s, %.*s, 0x%x\n",
++ mod->path, AuDLNPair(mod->h_root), mod->perm);
++ SiMustWriteLock(sb);
++ root = sb->s_root;
++ DiMustWriteLock(root);
++ IiMustWriteLock(root->d_inode);
++
++ bindex = au_find_dbindex(root, mod->h_root);
++ if (bindex < 0) {
++ if (remount)
++ return 0; /* success */
++ err = -ENOENT;
++ AuErr("%s no such branch\n", mod->path);
++ goto out;
++ }
++ LKTRTrace("bindex b%d\n", bindex);
++
++ hidden_dir = mod->h_root->d_inode;
++ err = test_br(sb, hidden_dir, mod->perm, mod->path);
++ if (unlikely(err))
++ goto out;
++
++ br = au_sbr(sb, bindex);
++ if (br->br_perm == mod->perm)
++ return 0; /* success */
++
++ if (au_br_writable(br->br_perm)) {
++#if 1
++ /* remove whiteout base */
++ err = au_br_init_wh(sb, bindex, br, mod->perm, mod->h_root,
++ br->br_mnt);
++ if (unlikely(err))
++ goto out;
++#else /* reserved for future use */
++ struct au_wbr *wbr;
++ wbr = br->wbr;
++ if (wbr)
++ for (i = 0; i < AuBrWh_Last; i++) {
++ dput(wbr->wbr_wh[i]);
++ wbr->wbr_wh[i] = NULL;
++ }
++#endif
++
++ if (!au_br_writable(mod->perm)) {
++ /* rw --> ro, file might be mmapped */
++
++#if 1 /* todo: test more? */
++ DiMustNoWaiters(root);
++ IiMustNoWaiters(root->d_inode);
++ di_write_unlock(root);
++ err = au_br_mod_files_ro(sb, bindex);
++ /* aufs_write_lock() calls ..._child() */
++ di_write_lock_child(root);
++#endif
++ }
++ } else if (au_br_writable(mod->perm)) {
++ /* ro --> rw */
++ err = -ENOMEM;
++ br->br_wbr = kmalloc(sizeof(*br->br_wbr), GFP_NOFS);
++ if (br->br_wbr) {
++ err = au_wbr_init(br, sb, mod->perm, mod->h_root,
++ br->br_mnt);
++ if (unlikely(err)) {
++ kfree(br->br_wbr);
++ br->br_wbr = NULL;
++ }
++ }
++ }
++
++ if (!err) {
++ *do_update |= need_sigen_inc(br->br_perm, mod->perm);
++ br->br_perm = mod->perm;
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
+diff --git a/fs/aufs/branch.h b/fs/aufs/branch.h
+new file mode 100644
+index 0000000..ece9b51
+--- /dev/null
++++ b/fs/aufs/branch.h
+@@ -0,0 +1,443 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * branch filesystems and xino for them
++ *
++ * $Id: branch.h,v 1.64 2009/01/26 06:23:47 sfjro Exp $
++ */
++
++#ifndef __AUFS_BRANCH_H__
++#define __AUFS_BRANCH_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/mount.h>
++#include <linux/aufs_type.h>
++#include "misc.h"
++#include "super.h"
++
++/* ---------------------------------------------------------------------- */
++
++/* an entry in a xino file */
++struct au_xino_entry {
++ ino_t ino;
++ /* __u32 h_gen; */ /* reserved for future use */
++} __packed;
++
++/* reserved for future use */
++/* #define AuXino_INVALID_HGEN (-1) */
++
++/* a xino file */
++struct au_xino_file {
++ struct file *xi_file;
++ struct mutex xi_nondir_mtx;
++
++ /* reserved for future use */
++#if 0
++ struct file **xi_file;
++
++ /* array management */
++ unsigned long long xi_limit; /* Max xino file size */
++ unsigned long long xi_size; /* s_maxbytes */
++
++ /* truncation */
++ unsigned long long xi_upper; /* watermark in bytes */
++ unsigned long long xi_step; /* to next watermark in bytes */
++
++ /* truncation */
++ blkcnt_t xi_upper; /* watermark in blocks */
++ atomic_t xi_running;
++#endif
++};
++
++/* members for writable branch only */
++enum {AuBrWh_BASE, AuBrWh_PLINK, AuBrWh_TMP, AuBrWh_Last};
++struct au_wbr {
++ struct au_rwsem wbr_wh_rwsem;
++ struct dentry *wbr_wh[AuBrWh_Last];
++ atomic_t wbr_wh_running;
++#define wbr_whbase wbr_wh[AuBrWh_BASE] /* whiteout base */
++#define wbr_plink wbr_wh[AuBrWh_PLINK] /* pseudo-link dir */
++#define wbr_tmp wbr_wh[AuBrWh_TMP] /* temporary dir */
++
++ /* mfs mode */
++ unsigned long long wbr_bytes;
++};
++
++/* protected by superblock rwsem */
++struct sysaufs_br;
++struct au_branch {
++ struct au_xino_file br_xino;
++
++ aufs_bindex_t br_id;
++
++ int br_perm;
++ struct vfsmount *br_mnt;
++ atomic_t br_count;
++
++ struct au_wbr *br_wbr;
++
++#if 1 /* reserved for future use */
++ /* xino truncation */
++ blkcnt_t br_xino_upper; /* watermark in blocks */
++ atomic_t br_xino_running;
++#endif
++
++
++ au_gen_t br_generation;
++
++ /* an entry under sysfs per mount-point */
++ struct sysaufs_br *br_sabr;
++};
++
++/* ---------------------------------------------------------------------- */
++
++/* branch permission and attribute */
++enum {
++ AuBrPerm_RW, /* writable, linkable wh */
++ AuBrPerm_RO, /* readonly, no wh */
++ AuBrPerm_RR, /* natively readonly, no wh */
++
++ AuBrPerm_RWNoLinkWH, /* un-linkable whiteouts */
++
++ AuBrPerm_ROWH,
++ AuBrPerm_RRWH, /* whiteout-able */
++
++ AuBrPerm_Last
++};
++
++static inline int au_br_writable(int brperm)
++{
++ return brperm == AuBrPerm_RW || brperm == AuBrPerm_RWNoLinkWH;
++}
++
++static inline int au_br_whable(int brperm)
++{
++ return brperm == AuBrPerm_RW
++ || brperm == AuBrPerm_ROWH
++ || brperm == AuBrPerm_RRWH;
++}
++
++#if 0 /* reserved for future use */
++static inline int au_br_linkable_wh(int brperm)
++{
++ return brperm == AuBrPerm_RW;
++}
++#endif
++
++static inline int au_br_hinotifyable(int brperm)
++{
++#ifdef CONFIG_AUFS_HINOTIFY
++ return brperm != AuBrPerm_RR && brperm != AuBrPerm_RRWH;
++#else
++ return 0;
++#endif
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* branch.c */
++struct au_sbinfo;
++void au_br_free(struct au_sbinfo *sinfo);
++int au_test_def_rr(struct super_block *h_sb);
++int au_br_index(struct super_block *sb, aufs_bindex_t br_id);
++struct au_opt_add;
++int au_br_add(struct super_block *sb, struct au_opt_add *add, int remount);
++struct au_opt_del;
++int au_br_del(struct super_block *sb, struct au_opt_del *del, int remount);
++struct au_opt_mod;
++int au_br_mod(struct super_block *sb, struct au_opt_mod *mod, int remount,
++ int *do_update);
++
++/* xino.c */
++#ifndef LLONG_MAX /* before linux-2.6.18 */
++#define LLONG_MAX ((long long)(~0ULL >> 1))
++#endif
++#define Au_LOFF_MAX ((loff_t)LLONG_MAX)
++int au_xib_trunc(struct super_block *sb);
++ssize_t xino_fread(au_readf_t func, struct file *file, void *buf, size_t size,
++ loff_t *pos);
++ssize_t xino_fwrite(au_writef_t func, struct file *file, void *buf, size_t size,
++ loff_t *pos);
++struct file *au_xino_create(struct super_block *sb, char *fname, int silent);
++struct file *au_xino_create2(struct super_block *sb, struct file *base_file,
++ struct file *copy_src);
++ino_t au_xino_new_ino(struct super_block *sb);
++int au_xino_write0(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ ino_t ino);
++int au_xino_write(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ struct au_xino_entry *xinoe);
++int au_xino_read(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ struct au_xino_entry *xinoe);
++int au_xino_br(struct super_block *sb, struct au_branch *br, ino_t hino,
++ struct file *base_file, int do_test);
++int au_xino_trunc(struct super_block *sb, aufs_bindex_t bindex);
++
++struct au_opt_xino;
++int au_xino_set(struct super_block *sb, struct au_opt_xino *xino, int remount);
++void au_xino_clr(struct super_block *sb);
++struct file *au_xino_def(struct super_block *sb);
++
++struct au_opt_xinodir;
++#if 0 /* def CONFIG_AUFS_EXPORT */ /* reserved for future use */
++/* export.c */
++int au_xinodir_br(struct super_block *sb, struct au_branch *br, ino_t hino,
++ int do_test);
++int au_xinodir_set(struct super_block *sb, struct au_opt_xinodir *xinodir,
++ int remount);
++#else
++static inline
++int au_xinodir_br(struct super_block *sb, struct au_branch *br, ino_t hino,
++ int do_test)
++{
++ return 0;
++}
++
++static inline
++int au_xinodir_set(struct super_block *sb, struct au_opt_xinodir *xinodir,
++ int remount)
++{
++ return 0;
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++/* todo: memory barrier? */
++static inline int au_br_count(struct au_branch *br)
++{
++ return atomic_read(&br->br_count);
++}
++
++static inline int au_br_get(struct au_branch *br)
++{
++ return atomic_inc_return(&br->br_count);
++}
++
++static inline int au_br_put(struct au_branch *br)
++{
++ return atomic_dec_return(&br->br_count);
++}
++
++static inline au_gen_t au_br_gen(struct au_branch *br)
++{
++ return br->br_generation;
++}
++
++/*
++ * test if the @br is readonly or not.
++ */
++static inline int au_br_rdonly(struct au_branch *br)
++{
++ return ((br->br_mnt->mnt_sb->s_flags & MS_RDONLY)
++ || !au_br_writable(br->br_perm))
++ ? -EROFS : 0;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* Superblock to branch */
++static inline
++aufs_bindex_t au_sbr_id(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return au_sbr(sb, bindex)->br_id;
++}
++
++static inline
++struct vfsmount *au_sbr_mnt(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return au_sbr(sb, bindex)->br_mnt;
++}
++
++static inline
++struct super_block *au_sbr_sb(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return au_sbr_mnt(sb, bindex)->mnt_sb;
++}
++
++#if 0 /* reserved for future use */
++static inline int au_sbr_count(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return au_br_count(au_sbr(sb, bindex));
++}
++
++static inline void au_sbr_get(struct super_block *sb, aufs_bindex_t bindex)
++{
++ au_br_get(au_sbr(sb, bindex));
++}
++#endif
++
++static inline void au_sbr_put(struct super_block *sb, aufs_bindex_t bindex)
++{
++ au_br_put(au_sbr(sb, bindex));
++}
++
++static inline int au_sbr_perm(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return au_sbr(sb, bindex)->br_perm;
++}
++
++static inline int au_sbr_whable(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return au_br_whable(au_sbr_perm(sb, bindex));
++}
++
++static inline int au_br_want_write(struct au_branch *br)
++{
++ int err;
++
++ AuDebugOn(!au_br_writable(br->br_perm));
++ err = au_mnt_want_write(br->br_mnt);
++ AuTraceErr(err);
++ return err;
++}
++
++static inline void au_br_drop_write(struct au_branch *br)
++{
++ AuDebugOn(!au_br_writable(br->br_perm));
++ au_mnt_drop_write(br->br_mnt);
++}
++
++static inline int au_test_trunc_xino(struct super_block *sb)
++{
++ return au_test_tmpfs(sb);
++}
++
++/* temporary support for i#1 in cramfs */
++static inline int au_test_unique_ino(struct dentry *h_dentry, ino_t h_ino)
++{
++#if defined(CONFIG_CRAMFS) || defined(CONFIG_CRAMFS_MODULE)
++ if (unlikely(h_dentry->d_sb->s_magic == CRAMFS_MAGIC))
++ return h_ino != 1;
++#endif
++ return 1;
++}
++
++static inline struct vfsmount *au_do_nfsmnt(struct vfsmount *h_mnt)
++{
++ if (!au_test_nfs(h_mnt->mnt_sb)
++ && !au_test_ecryptfs(h_mnt->mnt_sb))
++ return NULL;
++ return h_mnt;
++}
++
++static inline void au_br_nfs_lockdep_off(struct super_block *sb)
++{
++ if (au_test_nfs(sb))
++ lockdep_off();
++}
++
++static inline void au_br_nfs_lockdep_on(struct super_block *sb)
++{
++ /* hoping this condition will be optimized... */
++ if (au_test_nfs(sb))
++ lockdep_on();
++}
++
++#ifdef CONFIG_AUFS_BR_NFS
++static inline int au_test_unsupported_nfs(struct super_block *h_sb)
++{
++ return 0;
++}
++
++/* it doesn't mntget() */
++static inline
++struct vfsmount *au_nfsmnt(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return au_do_nfsmnt(au_sbr_mnt(sb, bindex));
++}
++
++#define AuNoNfsBranchMsg "dummy"
++
++#else
++static inline int au_test_unsupported_nfs(struct super_block *h_sb)
++{
++ return h_sb->s_magic == NFS_SUPER_MAGIC;
++}
++
++/* it doesn't mntget() */
++static inline
++struct vfsmount *au_nfsmnt(struct super_block *sb, aufs_bindex_t bindex)
++{
++ return NULL;
++}
++
++#define _AuNoNfsBranchMsg "NFS branch is not supported"
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 16)
++#define AuNoNfsBranchMsg _AuNoNfsBranchMsg "."
++#else //if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++#define AuNoNfsBranchMsg _AuNoNfsBranchMsg \
++ ", try some configurations and patches included in aufs source CVS."
++#endif
++
++#endif /* CONFIG_AUFS_BR_NFS */
++
++#ifdef CONFIG_AUFS_BR_NFS_V4
++static inline int au_test_unsupported_nfs4(struct super_block *h_sb)
++{
++ return 0;
++}
++
++#define AuNoNfsv4BranchMsg "dummy"
++
++#else
++static inline int au_test_unsupported_nfs4(struct super_block *h_sb)
++{
++ return h_sb->s_magic == NFS_SUPER_MAGIC
++ && !strcmp(h_sb->s_type->name, "nfs4");
++}
++
++#define AuNoNfsv4BranchMsg "NFSv4 branch is not supported" \
++ ", try some configurations and patches included in aufs source CVS."
++
++#endif /* CONFIG_AUFS_BR_NFS_v4 */
++
++/* support atomic open */
++static inline int au_test_fs_intent(struct super_block *h_sb)
++{
++ return au_test_nfs4(h_sb) /*|| au_test_fuse(h_sb)*/;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * br_wh_read_lock, br_wh_write_lock
++ * br_wh_read_unlock, br_wh_write_unlock, br_wh_downgrade_lock
++ */
++AuSimpleRwsemFuncs(wbr_wh, struct au_wbr *wbr, wbr->wbr_wh_rwsem);
++
++/* to debug easier, do not make them inlined functions */
++#define WbrWhMustReadLock(wbr) do { \
++ /* SiMustAnyLock(sb); */ \
++ AuRwMustReadLock(&(wbr)->wbr_wh_rwsem); \
++} while (0)
++
++#define WbrWhMustWriteLock(wbr) do { \
++ /* SiMustAnyLock(sb); */ \
++ AuRwMustWriteLock(&(wbr)->wbr_wh_rwsem); \
++} while (0)
++
++#define WbrWhMustAnyLock(br) do { \
++ /* SiMustAnyLock(sb); */ \
++ AuRwMustAnyLock(&(wbr)->wbr_wh_rwsem); \
++} while (0)
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_BRANCH_H__ */
+diff --git a/fs/aufs/cpup.c b/fs/aufs/cpup.c
+new file mode 100644
+index 0000000..60e55e0
+--- /dev/null
++++ b/fs/aufs/cpup.c
+@@ -0,0 +1,1138 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * copy-up functions, see wbr_policy.c for copy-down
++ *
++ * $Id: cpup.c,v 1.79 2009/01/26 06:23:51 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/* todo? violent cpup_attr_*() functions don't care inode lock */
++
++void au_cpup_attr_timesizes(struct inode *inode)
++{
++ struct inode *h_inode;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++ /* todo? IMustLock(inode); */
++ h_inode = au_h_iptr(inode, au_ibstart(inode));
++ AuDebugOn(!h_inode);
++ /* todo? IMustLock(!h_inode); */
++
++ inode->i_atime = h_inode->i_atime;
++ inode->i_mtime = h_inode->i_mtime;
++ inode->i_ctime = h_inode->i_ctime;
++ spin_lock(&inode->i_lock);
++ i_size_write(inode, i_size_read(h_inode));
++ inode->i_blocks = h_inode->i_blocks;
++ spin_unlock(&inode->i_lock);
++}
++
++void au_cpup_attr_nlink(struct inode *inode, int force)
++{
++ struct inode *h_inode;
++ struct super_block *sb;
++ aufs_bindex_t bindex, bend;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++ /* todo? IMustLock(inode); */
++ AuDebugOn(!inode->i_mode);
++
++ sb = inode->i_sb;
++ bindex = au_ibstart(inode);
++ h_inode = au_h_iptr(inode, bindex);
++
++ if (!force
++ && !S_ISDIR(h_inode->i_mode)
++ && au_opt_test(au_mntflags(sb), PLINK)
++ && au_plink_test(sb, inode))
++ return;
++
++ inode->i_nlink = h_inode->i_nlink;
++
++ /*
++ * fewer nlink makes find(1) noisy, but larger nlink doesn't.
++ * it may includes whplink directory.
++ */
++ if (S_ISDIR(h_inode->i_mode)) {
++ bend = au_ibend(inode);
++ for (bindex++; bindex <= bend; bindex++) {
++ h_inode = au_h_iptr(inode, bindex);
++ if (h_inode)
++ au_add_nlink(inode, h_inode);
++ }
++ }
++}
++
++void au_cpup_attr_changeable(struct inode *inode)
++{
++ struct inode *h_inode;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++ /* todo? IMustLock(inode); */
++ h_inode = au_h_iptr(inode, au_ibstart(inode));
++ AuDebugOn(!h_inode);
++
++ inode->i_mode = h_inode->i_mode;
++ inode->i_uid = h_inode->i_uid;
++ inode->i_gid = h_inode->i_gid;
++ au_cpup_attr_timesizes(inode);
++ au_cpup_attr_flags(inode, h_inode);
++}
++
++void au_cpup_igen(struct inode *inode, struct inode *h_inode)
++{
++ struct au_iinfo *iinfo = au_ii(inode);
++ iinfo->ii_higen = h_inode->i_generation;
++ iinfo->ii_hsb1 = h_inode->i_sb;
++}
++
++void au_cpup_attr_all(struct inode *inode, int force)
++{
++ struct inode *h_inode;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++ /* todo? IMustLock(inode); */
++ h_inode = au_h_iptr(inode, au_ibstart(inode));
++ AuDebugOn(!h_inode);
++
++ au_cpup_attr_changeable(inode);
++ if (inode->i_nlink > 0)
++ au_cpup_attr_nlink(inode, force);
++
++ switch (inode->i_mode & S_IFMT) {
++ case S_IFBLK:
++ case S_IFCHR:
++ inode->i_rdev = au_h_rdev(h_inode, /*h_mnt*/NULL,
++ /*h_dentry*/NULL);
++ }
++ inode->i_blkbits = h_inode->i_blkbits;
++ au_cpup_attr_blksize(inode, h_inode);
++ au_cpup_igen(inode, h_inode);
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* Note: dt_dentry and dt_hidden_dentry are not dget/dput-ed */
++
++/* keep the timestamps of the parent dir when cpup */
++void au_dtime_store(struct au_dtime *dt, struct dentry *dentry,
++ struct dentry *h_dentry, struct au_hinode *hinode,
++ struct au_hinode *hdir)
++{
++ struct inode *h_inode;
++
++ LKTRTrace("%.*s, hdir %d\n", AuDLNPair(dentry), !!hdir);
++ AuDebugOn(!dentry || !h_dentry || !h_dentry->d_inode);
++
++ dt->dt_dentry = dentry;
++ dt->dt_h_dentry = h_dentry;
++ dt->dt_hinode = hinode;
++ dt->dt_hdir = hdir;
++ h_inode = h_dentry->d_inode;
++ dt->dt_atime = h_inode->i_atime;
++ dt->dt_mtime = h_inode->i_mtime;
++ /* smp_mb(); */
++}
++
++void au_dtime_revert(struct au_dtime *dt)
++{
++ struct iattr attr;
++ int err;
++ struct au_hin_ignore ign[2];
++ struct vfsub_args vargs;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dt->dt_dentry));
++
++ attr.ia_atime = dt->dt_atime;
++ attr.ia_mtime = dt->dt_mtime;
++ attr.ia_valid = ATTR_FORCE | ATTR_MTIME | ATTR_MTIME_SET
++ | ATTR_ATIME | ATTR_ATIME_SET;
++
++ vfsub_args_init(&vargs, ign,
++ au_test_dlgt(au_mntflags(dt->dt_dentry->d_sb)), 0);
++ /*
++ * IN_ATTRIB should be divided into
++ * IN_ATTRIB_ATIME, IN_ATTRIB_MTIME ...,
++ * and define all ORed new IN_ATTRIB macro.
++ */
++ vfsub_ign_hinode(&vargs, IN_ATTRIB, dt->dt_hinode);
++ vfsub_ign_hinode(&vargs, IN_ATTRIB, dt->dt_hdir);
++ err = vfsub_notify_change(dt->dt_h_dentry, &attr, &vargs);
++ if (unlikely(err))
++ AuWarn("restoring timestamps failed(%d). ignored\n", err);
++}
++
++/* ---------------------------------------------------------------------- */
++
++static noinline_for_stack
++int cpup_iattr(struct dentry *dst, aufs_bindex_t bindex, struct dentry *h_src,
++ struct au_hinode *hdir, struct vfsub_args *vargs)
++{
++ int err, sbits;
++ struct dentry *h_dst;
++ struct iattr ia;
++ struct inode *h_isrc, *h_idst;
++
++ h_dst = au_h_dptr(dst, bindex);
++ LKTRTrace("%.*s\n", AuDLNPair(h_dst));
++ h_idst = h_dst->d_inode;
++ /* todo? IMustLock(h_idst); */
++ h_isrc = h_src->d_inode;
++ /* todo? IMustLock(h_isrc); */
++
++ ia.ia_valid = ATTR_FORCE | ATTR_MODE | ATTR_UID | ATTR_GID
++ | ATTR_ATIME | ATTR_MTIME
++ | ATTR_ATIME_SET | ATTR_MTIME_SET;
++ ia.ia_mode = h_isrc->i_mode;
++ ia.ia_uid = h_isrc->i_uid;
++ ia.ia_gid = h_isrc->i_gid;
++ ia.ia_atime = h_isrc->i_atime;
++ ia.ia_mtime = h_isrc->i_mtime;
++ sbits = !!(ia.ia_mode & (S_ISUID | S_ISGID));
++ au_cpup_attr_flags(h_idst, h_isrc);
++
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_ATTRIB, hdir);
++ err = vfsub_notify_change(h_dst, &ia, vargs);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++ /* is this nfs only? */
++ if (!err && sbits && au_test_nfs(h_dst->d_sb)) {
++ ia.ia_valid = ATTR_FORCE | ATTR_MODE;
++ ia.ia_mode = h_isrc->i_mode;
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_ATTRIB, hdir);
++ err = vfsub_notify_change(h_dst, &ia, vargs);
++ }
++#endif
++
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * to support a sparse file which is opened with O_APPEND,
++ * we need to close the file.
++ */
++static noinline_for_stack
++int cpup_regular(struct dentry *dentry, aufs_bindex_t bdst, aufs_bindex_t bsrc,
++ loff_t len, struct au_hinode *hdir, struct vfsub_args *vargs)
++{
++ int err, i;
++ struct super_block *sb;
++ struct inode *h_inode;
++ enum { SRC, DST };
++ struct {
++ aufs_bindex_t bindex;
++ unsigned int flags;
++ struct dentry *dentry;
++ struct file *file;
++ void *label, *label_file;
++ } *h, hidden[] = {
++ {
++ .bindex = bsrc,
++ .flags = O_RDONLY | O_NOATIME | O_LARGEFILE,
++ .file = NULL,
++ .label = &&out,
++ .label_file = &&out_src_file
++ },
++ {
++ .bindex = bdst,
++ .flags = O_WRONLY | O_NOATIME | O_LARGEFILE,
++ .file = NULL,
++ .label = &&out_src_file,
++ .label_file = &&out_dst_file
++ }
++ };
++
++ LKTRTrace("dentry %.*s, bdst %d, bsrc %d, len %lld\n",
++ AuDLNPair(dentry), bdst, bsrc, len);
++ AuDebugOn(bsrc <= bdst);
++ AuDebugOn(!len);
++ sb = dentry->d_sb;
++ AuDebugOn(au_test_ro(sb, bdst, dentry->d_inode));
++ /* bsrc branch can be ro/rw. */
++
++ h = hidden;
++ for (i = 0; i < 2; i++, h++) {
++ h->dentry = au_h_dptr(dentry, h->bindex);
++ AuDebugOn(!h->dentry);
++ h_inode = h->dentry->d_inode;
++ AuDebugOn(!h_inode || !S_ISREG(h_inode->i_mode));
++ h->file = au_h_open(dentry, h->bindex, h->flags, /*file*/NULL);
++ err = PTR_ERR(h->file);
++ if (IS_ERR(h->file))
++ goto *h->label;
++ err = -EINVAL;
++ if (unlikely(!h->file->f_op))
++ goto *h->label_file;
++ }
++
++ /* stop updating while we copyup */
++ IMustLock(hidden[SRC].dentry->d_inode);
++ err = au_copy_file(hidden[DST].file, hidden[SRC].file, len, hdir, sb,
++ vargs);
++
++ out_dst_file:
++ fput(hidden[DST].file);
++ au_sbr_put(sb, hidden[DST].bindex);
++ out_src_file:
++ fput(hidden[SRC].file);
++ au_sbr_put(sb, hidden[SRC].bindex);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_do_cpup_regular(struct dentry *dentry, aufs_bindex_t bdst,
++ aufs_bindex_t bsrc, loff_t len,
++ struct au_hinode *hdir, struct dentry *h_dst,
++ struct vfsub_args *vargs)
++{
++ int err, rerr;
++ loff_t l;
++
++ AuTraceEnter();
++
++ err = 0;
++ l = i_size_read(au_h_iptr(dentry->d_inode, bsrc));
++ if (len == -1 || l < len)
++ len = l;
++ if (len)
++ err = cpup_regular(dentry, bdst, bsrc, len, hdir, vargs);
++ if (!err)
++ goto out; /* success */
++
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_DELETE, hdir);
++ rerr = vfsub_unlink(hdir->hi_inode, h_dst, vargs);
++ if (rerr) {
++ AuIOErr("failed unlinking cpup-ed %.*s(%d, %d)\n",
++ AuDLNPair(h_dst), err, rerr);
++ err = -EIO;
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_do_cpup_symlink(struct dentry *h_dst, struct dentry *h_src,
++ struct inode *h_dir, umode_t mode,
++ struct vfsub_args *vargs)
++{
++ int err, symlen;
++ char *sym;
++ mm_segment_t old_fs;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ sym = __getname();
++ if (unlikely(!sym))
++ goto out;
++
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ symlen = h_src->d_inode->i_op->readlink(h_src, (char __user *)sym,
++ PATH_MAX);
++ err = symlen;
++ set_fs(old_fs);
++
++ if (symlen > 0) {
++ sym[symlen] = 0;
++ err = vfsub_symlink(h_dir, h_dst, sym, mode, vargs);
++ }
++ __putname(sym);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* return with hidden dst inode is locked */
++static noinline_for_stack
++int cpup_entry(struct dentry *dentry, aufs_bindex_t bdst, aufs_bindex_t bsrc,
++ loff_t len, unsigned int flags, struct dentry *dst_parent,
++ struct vfsub_args *vargs)
++{
++ int err;
++ unsigned char isdir, hinotify;
++ struct dentry *h_src, *h_dst, *h_parent, *gparent;
++ struct inode *h_inode, *h_dir;
++ struct au_dtime dt;
++ umode_t mode;
++ struct super_block *sb;
++ struct au_hinode *hgdir, *hdir;
++ unsigned int mnt_flags;
++ const int do_dt = au_ftest_cpup(flags, DTIME);
++
++ LKTRTrace("%.*s, i%lu, bdst %d, bsrc %d, len %lld, dtime %u\n",
++ AuDLNPair(dentry), dentry->d_inode->i_ino, bdst, bsrc, len,
++ do_dt);
++ sb = dentry->d_sb;
++ AuDebugOn(bdst >= bsrc || au_test_ro(sb, bdst, NULL));
++ /* bsrc branch can be ro/rw. */
++
++ h_src = au_h_dptr(dentry, bsrc);
++ AuDebugOn(!h_src);
++ h_inode = h_src->d_inode;
++ AuDebugOn(!h_inode);
++ AuDebugOn(h_inode != au_h_iptr(dentry->d_inode, bsrc));
++
++ /* stop referencing while we are creating */
++ h_dst = au_h_dptr(dentry, bdst);
++ AuDebugOn(h_dst && h_dst->d_inode);
++ h_parent = h_dst->d_parent; /* dir inode is locked */
++ h_dir = h_parent->d_inode;
++ IMustLock(h_dir);
++ AuDebugOn(h_parent != h_dst->d_parent);
++
++ hdir = NULL;
++ mnt_flags = au_mntflags(sb);
++ hinotify = !!au_opt_test(mnt_flags, UDBA_INOTIFY);
++ if (hinotify) {
++ hdir = au_hi(dst_parent->d_inode, bdst);
++ AuDebugOn(hdir->hi_inode != h_dir);
++ }
++
++ if (do_dt) {
++ hgdir = NULL;
++ if (hinotify && !IS_ROOT(dst_parent)) {
++ gparent = dget_parent(dst_parent);
++ hgdir = au_hi(gparent->d_inode, bdst);
++ IMustLock(hgdir->hi_inode);
++ dput(gparent);
++ }
++ au_dtime_store(&dt, dst_parent, h_parent, hdir, hgdir);
++ }
++
++ isdir = 0;
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_CREATE, hdir);
++ mode = h_inode->i_mode;
++ switch (mode & S_IFMT) {
++ case S_IFREG:
++ /* stop updating while we are referencing */
++ IMustLock(h_inode);
++ err = au_h_create(h_dir, h_dst, mode | S_IWUSR, vargs, NULL,
++ au_nfsmnt(sb, bdst));
++ if (!err)
++ err = au_do_cpup_regular(dentry, bdst, bsrc, len,
++ hdir, h_dst, vargs);
++ break;
++ case S_IFDIR:
++ isdir = 1;
++ err = vfsub_mkdir(h_dir, h_dst, mode, vargs);
++ if (!err) {
++ /* setattr case: dir is not locked */
++ if (0 && au_ibstart(dst_parent->d_inode) == bdst)
++ au_cpup_attr_nlink(dst_parent->d_inode,
++ /*force*/1);
++ au_cpup_attr_nlink(dentry->d_inode, /*force*/1);
++ }
++ break;
++ case S_IFLNK:
++ err = au_do_cpup_symlink(h_dst, h_src, h_dir, mode, vargs);
++ break;
++ case S_IFCHR:
++ case S_IFBLK:
++ AuDebugOn(!capable(CAP_MKNOD));
++ /*FALLTHROUGH*/
++ case S_IFIFO:
++ case S_IFSOCK:
++ err = vfsub_mknod(h_dir, h_dst, mode,
++ au_h_rdev(h_inode, /*h_mnt*/NULL, h_src),
++ vargs);
++ break;
++ default:
++ AuIOErr("Unknown inode type 0%o\n", mode);
++ err = -EIO;
++ }
++
++ if (hinotify
++ && !isdir
++ && au_opt_test_xino(mnt_flags)
++ && h_inode->i_nlink == 1
++ /* todo: unnecessary? */
++ /* && dentry->d_inode->i_nlink == 1 */
++ && bdst < bsrc
++ && !au_ftest_cpup(flags, KEEPLINO))
++ au_xino_write0(sb, bsrc, h_inode->i_ino, /*ino*/0);
++ /* ignore this error */
++
++ if (do_dt)
++ au_dtime_revert(&dt);
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * copyup the @dentry from @bsrc to @bdst.
++ * the caller must set the both of hidden dentries.
++ * @len is for truncating when it is -1 copyup the entire file.
++ */
++static int au_cpup_single(struct dentry *dentry, aufs_bindex_t bdst,
++ aufs_bindex_t bsrc, loff_t len, unsigned int flags,
++ struct dentry *dst_parent, struct vfsub_args *vargs)
++{
++ int err, rerr;
++ unsigned int mnt_flags;
++ aufs_bindex_t old_ibstart;
++ unsigned char isdir, plink, hinotify;
++ struct au_dtime dt;
++ struct dentry *h_src, *h_dst, *h_parent, *gparent;
++ struct inode *dst_inode, *h_dir, *inode;
++ struct super_block *sb;
++ struct au_hinode *hgdir, *hdir;
++
++ LKTRTrace("%.*s, i%lu, bdst %d, bsrc %d, len %lld, flags 0x%x\n",
++ AuDLNPair(dentry), dentry->d_inode->i_ino, bdst, bsrc, len,
++ flags);
++ sb = dentry->d_sb;
++ AuDebugOn(bsrc <= bdst);
++ h_dst = au_h_dptr(dentry, bdst);
++ AuDebugOn(!h_dst || h_dst->d_inode);
++ h_parent = h_dst->d_parent; /* dir inode is locked */
++ h_dir = h_parent->d_inode;
++ IMustLock(h_dir);
++ h_src = au_h_dptr(dentry, bsrc);
++ AuDebugOn(!h_src || !h_src->d_inode);
++ inode = dentry->d_inode;
++ IiMustWriteLock(inode);
++ if (!dst_parent)
++ dst_parent = dget_parent(dentry);
++ else
++ dget(dst_parent);
++
++ mnt_flags = au_mntflags(sb);
++ plink = !!au_opt_test(mnt_flags, PLINK);
++ hinotify = !!au_opt_test(mnt_flags, UDBA_INOTIFY);
++ hdir = NULL;
++ if (hinotify)
++ hdir = au_hi(dst_parent->d_inode, bdst);
++ dst_inode = au_h_iptr(inode, bdst);
++ if (dst_inode) {
++ if (unlikely(!plink)) {
++ err = -EIO;
++ AuIOErr("i%lu exists on a upper branch "
++ "but plink is disabled\n", inode->i_ino);
++ goto out;
++ }
++
++ if (dst_inode->i_nlink) {
++ const int do_dt = au_ftest_cpup(flags, DTIME);
++
++ h_src = au_plink_lkup(sb, bdst, inode);
++ err = PTR_ERR(h_src);
++ if (IS_ERR(h_src))
++ goto out;
++ if (unlikely(!h_src->d_inode)) {
++ err = -EIO;
++ AuIOErr("i%lu exists on a upper branch "
++ "but plink is broken\n", inode->i_ino);
++ dput(h_src);
++ goto out;
++ }
++
++ if (do_dt) {
++ hgdir = NULL;
++ if (hinotify && !IS_ROOT(dst_parent)) {
++ gparent = dget_parent(dst_parent);
++ hgdir = au_hi(gparent->d_inode, bdst);
++ IMustLock(hgdir->hi_inode);
++ dput(gparent);
++ }
++ au_dtime_store(&dt, dst_parent, h_parent, hdir,
++ hgdir);
++ }
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_CREATE, hdir);
++ err = vfsub_link(h_src, h_dir, h_dst, vargs);
++ if (do_dt)
++ au_dtime_revert(&dt);
++ dput(h_src);
++ goto out;
++ } else
++ /* todo: cpup_wh_file? */
++ /* udba work */
++ au_update_brange(inode, 1);
++ }
++
++ old_ibstart = au_ibstart(inode);
++ err = cpup_entry(dentry, bdst, bsrc, len, flags, dst_parent, vargs);
++ if (unlikely(err))
++ goto out;
++ dst_inode = h_dst->d_inode;
++ vfsub_i_lock_nested(dst_inode, AuLsc_I_CHILD2);
++
++ /* todo: test dlgt? */
++ err = cpup_iattr(dentry, bdst, h_src, hdir, vargs);
++#if 0 /* reserved for future use */
++ if (0 && !err)
++ err = cpup_xattrs(h_src, h_dst);
++#endif
++ isdir = S_ISDIR(dst_inode->i_mode);
++ if (!err) {
++ if (bdst < old_ibstart)
++ au_set_ibstart(inode, bdst);
++ au_set_h_iptr(inode, bdst, au_igrab(dst_inode),
++ au_hi_flags(inode, isdir));
++ vfsub_i_unlock(dst_inode);
++ if (!isdir
++ && h_src->d_inode->i_nlink > 1
++ && plink)
++ au_plink_append(sb, inode, h_dst, bdst);
++ goto out; /* success */
++ }
++
++ /* revert */
++ vfsub_i_unlock(dst_inode);
++ hgdir = NULL;
++ if (au_opt_test(mnt_flags, UDBA_INOTIFY) && !IS_ROOT(dst_parent)) {
++ gparent = dget_parent(dst_parent);
++ hgdir = au_hi(gparent->d_inode, bdst);
++ dput(gparent);
++ }
++ au_dtime_store(&dt, dst_parent, h_parent, hdir, hgdir);
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_DELETE, hdir);
++ if (!isdir)
++ rerr = vfsub_unlink(h_dir, h_dst, vargs);
++ else
++ rerr = vfsub_rmdir(h_dir, h_dst, vargs);
++ au_dtime_revert(&dt);
++ if (rerr) {
++ AuIOErr("failed removing broken entry(%d, %d)\n", err, rerr);
++ err = -EIO;
++ }
++
++ out:
++ dput(dst_parent);
++ AuTraceErr(err);
++ return err;
++}
++
++struct au_cpup_single_args {
++ int *errp;
++ struct dentry *dentry;
++ aufs_bindex_t bdst, bsrc;
++ loff_t len;
++ unsigned int flags;
++ struct dentry *dst_parent;
++ struct vfsub_args *vargs;
++};
++
++static void au_call_cpup_single(void *args)
++{
++ struct au_cpup_single_args *a = args;
++ *a->errp = au_cpup_single(a->dentry, a->bdst, a->bsrc, a->len,
++ a->flags, a->dst_parent, a->vargs);
++}
++
++int au_sio_cpup_single(struct dentry *dentry, aufs_bindex_t bdst,
++ aufs_bindex_t bsrc, loff_t len, unsigned int flags,
++ struct dentry *dst_parent)
++{
++ int err, wkq_err;
++ struct dentry *h_dentry;
++ umode_t mode;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++
++ LKTRTrace("%.*s, i%lu, bdst %d, bsrc %d, len %lld, flags 0x%x\n",
++ AuDLNPair(dentry), dentry->d_inode->i_ino, bdst, bsrc, len,
++ flags);
++
++ vfsub_args_init(&vargs, &ign, au_test_dlgt(au_mntflags(dentry->d_sb)),
++ /*force_unlink*/0);
++ h_dentry = au_h_dptr(dentry, bsrc);
++ mode = h_dentry->d_inode->i_mode & S_IFMT;
++ if ((mode != S_IFCHR && mode != S_IFBLK)
++ || capable(CAP_MKNOD))
++ err = au_cpup_single(dentry, bdst, bsrc, len, flags,
++ dst_parent, &vargs);
++ else {
++ struct au_cpup_single_args args = {
++ .errp = &err,
++ .dentry = dentry,
++ .bdst = bdst,
++ .bsrc = bsrc,
++ .len = len,
++ .flags = flags,
++ .dst_parent = dst_parent,
++ .vargs = &vargs
++ };
++ vfsub_fclr(vargs.flags, DLGT);
++ wkq_err = au_wkq_wait(au_call_cpup_single, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * copyup the @dentry from the first active hidden branch to @bdst,
++ * using au_cpup_single().
++ */
++static int au_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len,
++ unsigned int flags, struct vfsub_args *vargs)
++{
++ int err;
++ struct inode *inode;
++ aufs_bindex_t bsrc, bend;
++
++ LKTRTrace("%.*s, bdst %d, len %lld, flags 0x%x\n",
++ AuDLNPair(dentry), bdst, len, flags);
++ inode = dentry->d_inode;
++ AuDebugOn(!S_ISDIR(inode->i_mode) && au_dbstart(dentry) < bdst);
++
++ bend = au_dbend(dentry);
++ for (bsrc = bdst + 1; bsrc <= bend; bsrc++)
++ if (au_h_dptr(dentry, bsrc))
++ break;
++ AuDebugOn(!au_h_dptr(dentry, bsrc));
++
++ err = au_lkup_neg(dentry, bdst);
++ if (!err) {
++ err = au_cpup_single(dentry, bdst, bsrc, len, flags, NULL,
++ vargs);
++ if (!err)
++ return 0; /* success */
++
++ /* revert */
++ au_set_h_dptr(dentry, bdst, NULL);
++ au_set_dbstart(dentry, bsrc);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++struct au_cpup_simple_args {
++ int *errp;
++ struct dentry *dentry;
++ aufs_bindex_t bdst;
++ loff_t len;
++ unsigned int flags;
++ struct vfsub_args *vargs;
++};
++
++static void au_call_cpup_simple(void *args)
++{
++ struct au_cpup_simple_args *a = args;
++ *a->errp = au_cpup_simple(a->dentry, a->bdst, a->len, a->flags,
++ a->vargs);
++}
++
++int au_sio_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len,
++ unsigned int flags)
++{
++ int err, wkq_err;
++ unsigned char do_sio, dlgt;
++ struct dentry *parent;
++ struct inode *h_dir, *dir;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++
++ LKTRTrace("%.*s, b%d, len %lld, flags 0x%x\n",
++ AuDLNPair(dentry), bdst, len, flags);
++
++ parent = dget_parent(dentry);
++ dir = parent->d_inode;
++ h_dir = au_h_iptr(dir, bdst);
++ dlgt = !!au_test_dlgt(au_mntflags(dir->i_sb));
++ do_sio = !!au_test_h_perm_sio(h_dir, MAY_EXEC | MAY_WRITE, dlgt);
++ if (!do_sio) {
++ /*
++ * testing CAP_MKNOD is for generic fs,
++ * but CAP_FSETID is for xfs only, currently.
++ */
++ umode_t mode = dentry->d_inode->i_mode;
++ do_sio = (((mode & (S_IFCHR | S_IFBLK))
++ && !capable(CAP_MKNOD))
++ || ((mode & (S_ISUID | S_ISGID))
++ && !capable(CAP_FSETID)));
++ }
++ vfsub_args_init(&vargs, &ign, dlgt, /*force_unlink*/0);
++ if (!do_sio)
++ err = au_cpup_simple(dentry, bdst, len, flags, &vargs);
++ else {
++ struct au_cpup_simple_args args = {
++ .errp = &err,
++ .dentry = dentry,
++ .bdst = bdst,
++ .len = len,
++ .flags = flags,
++ .vargs = &vargs
++ };
++ vfsub_fclr(vargs.flags, DLGT);
++ wkq_err = au_wkq_wait(au_call_cpup_simple, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int au_do_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst,
++ struct dentry *wh_dentry, struct file *file,
++ loff_t len, struct vfsub_args *vargs)
++{
++ int err;
++ struct au_dinfo *dinfo;
++ aufs_bindex_t bstart;
++ struct dentry *h_d_bdst, *h_d_bstart;
++
++ AuTraceEnter();
++
++ dinfo = au_di(dentry);
++ bstart = dinfo->di_bstart;
++ h_d_bdst = dinfo->di_hdentry[0 + bdst].hd_dentry;
++ dinfo->di_bstart = bdst;
++ dinfo->di_hdentry[0 + bdst].hd_dentry = wh_dentry;
++ h_d_bstart = dinfo->di_hdentry[0 + bstart].hd_dentry;
++ if (file)
++ dinfo->di_hdentry[0 + bstart].hd_dentry
++ = au_h_fptr(file, au_fbstart(file))->f_dentry;
++ err = au_cpup_single(dentry, bdst, bstart, len, !AuCpup_DTIME,
++ /*h_parent*/NULL, vargs);
++ if (!err && file) {
++ err = au_reopen_nondir(file);
++ dinfo->di_hdentry[0 + bstart].hd_dentry = h_d_bstart;
++ }
++ dinfo->di_hdentry[0 + bdst].hd_dentry = h_d_bdst;
++ dinfo->di_bstart = bstart;
++
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * copyup the deleted file for writing.
++ */
++static int au_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len,
++ struct file *file)
++{
++ int err;
++ unsigned char dlgt;
++ struct dentry *parent, *h_parent, *wh_dentry;
++ struct super_block *sb;
++ unsigned int mnt_flags;
++ struct au_dtime dt;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ struct au_hinode *hgdir, *hdir;
++ struct au_ndx ndx = {
++ .nd = NULL,
++ .flags = 0,
++ /* .br = NULL */
++ };
++
++ LKTRTrace("%.*s, bdst %d, len %llu\n", AuDLNPair(dentry), bdst, len);
++ AuDebugOn(S_ISDIR(dentry->d_inode->i_mode)
++ || (file && !(file->f_mode & FMODE_WRITE)));
++ DiMustWriteLock(dentry);
++
++ parent = dget_parent(dentry);
++ IiMustAnyLock(parent->d_inode);
++ h_parent = au_h_dptr(parent, bdst);
++ AuDebugOn(!h_parent);
++
++ sb = parent->d_sb;
++ mnt_flags = au_mntflags(sb);
++ dlgt = 0;
++ ndx.nfsmnt = au_nfsmnt(sb, bdst);
++ if (au_test_dlgt(mnt_flags)) {
++ dlgt = 1;
++ au_fset_ndx(ndx.flags, DLGT);
++ }
++ wh_dentry = au_whtmp_lkup(h_parent, &dentry->d_name, &ndx);
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out;
++
++ hdir = NULL;
++ hgdir = NULL;
++ if (au_opt_test(mnt_flags, UDBA_INOTIFY)) {
++ hdir = au_hi(parent->d_inode, bdst);
++ if (!IS_ROOT(parent)) {
++ struct dentry *gparent;
++ gparent = dget_parent(parent);
++ hgdir = au_hi(gparent->d_inode, bdst);
++ dput(gparent);
++ }
++ }
++ au_dtime_store(&dt, parent, h_parent, hdir, hgdir);
++ vfsub_args_init(&vargs, &ign, dlgt, /*force_unlink*/0);
++ err = au_do_cpup_wh(dentry, bdst, wh_dentry, file, len, &vargs);
++ if (unlikely(err))
++ goto out_wh;
++
++ AuDebugOn(!d_unhashed(dentry));
++ /* dget first to force sillyrename on nfs */
++ dget(wh_dentry);
++ vfsub_args_reinit(&vargs);
++ vfsub_ign_hinode(&vargs, IN_DELETE, hdir);
++ err = vfsub_unlink(h_parent->d_inode, wh_dentry, &vargs);
++ if (unlikely(err)) {
++ AuIOErr("failed remove copied-up tmp file %.*s(%d)\n",
++ AuDLNPair(wh_dentry), err);
++ err = -EIO;
++ }
++ au_dtime_revert(&dt);
++ au_set_hi_wh(dentry->d_inode, bdst, wh_dentry);
++
++ out_wh:
++ dput(wh_dentry);
++ out:
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++struct au_cpup_wh_args {
++ int *errp;
++ struct dentry *dentry;
++ aufs_bindex_t bdst;
++ loff_t len;
++ struct file *file;
++};
++
++static void au_call_cpup_wh(void *args)
++{
++ struct au_cpup_wh_args *a = args;
++ *a->errp = au_cpup_wh(a->dentry, a->bdst, a->len, a->file);
++}
++
++int au_sio_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len,
++ struct file *file)
++{
++ int err, wkq_err;
++ struct dentry *parent, *h_tmp, *h_parent, *h_dentry;
++ struct inode *dir, *h_dir, *h_tmpdir, *h_inode;
++ struct au_wbr *wbr;
++
++ AuTraceEnter();
++ parent = dget_parent(dentry);
++ dir = parent->d_inode;
++ IiMustAnyLock(dir);
++
++ h_tmp = NULL;
++ h_parent = NULL;
++ h_dir = au_igrab(au_h_iptr(dir, bdst));
++ h_tmpdir = h_dir;
++ if (!h_dir->i_nlink) {
++ DiMustWriteLock(parent);
++ wbr = au_sbr(dentry->d_sb, bdst)->br_wbr;
++ AuDebugOn(!wbr);
++ h_tmp = wbr->wbr_tmp;
++
++ h_parent = dget(au_h_dptr(parent, bdst));
++ au_set_h_dptr(parent, bdst, NULL);
++ au_set_h_dptr(parent, bdst, dget(h_tmp));
++ h_tmpdir = h_tmp->d_inode;
++ au_set_h_iptr(dir, bdst, NULL, 0);
++ au_set_h_iptr(dir, bdst, au_igrab(h_tmpdir), /*flags*/0);
++
++ /* this temporary unlock is safe */
++ if (file)
++ h_dentry = au_h_fptr(file, au_fbstart(file))->f_dentry;
++ else
++ h_dentry = au_h_dptr(dentry, au_dbstart(dentry));
++ h_inode = h_dentry->d_inode;
++ IMustLock(h_inode);
++ vfsub_i_unlock(h_inode);
++ vfsub_i_lock_nested(h_tmpdir, AuLsc_I_PARENT3);
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ }
++
++ if (!au_test_h_perm_sio
++ (h_tmpdir, MAY_EXEC | MAY_WRITE,
++ au_test_dlgt(au_mntflags(dentry->d_sb))))
++ err = au_cpup_wh(dentry, bdst, len, file);
++ else {
++ struct au_cpup_wh_args args = {
++ .errp = &err,
++ .dentry = dentry,
++ .bdst = bdst,
++ .len = len,
++ .file = file
++ };
++ wkq_err = au_wkq_wait(au_call_cpup_wh, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++
++ /* todo: is this restore safe? */
++ if (h_tmp) {
++ vfsub_i_unlock(h_tmpdir);
++ au_set_h_iptr(dir, bdst, NULL, 0);
++ au_set_h_iptr(dir, bdst, au_igrab(h_dir), /*flags*/0);
++ au_set_h_dptr(parent, bdst, NULL);
++ au_set_h_dptr(parent, bdst, h_parent);
++ }
++ iput(h_dir);
++ dput(parent);
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * generic routine for both of copy-up and copy-down.
++ * Although I've tried building a path by dcsub, I gave up this approach.
++ * Since the ancestor directory may be moved/renamed during copy.
++ */
++/* cf. revalidate function in file.c */
++int au_cp_dirs(struct dentry *dentry, aufs_bindex_t bdst,
++ int (*cp)(struct dentry *dentry, aufs_bindex_t bdst,
++ struct dentry *h_parent, void *arg),
++ void *arg)
++{
++ int err;
++ unsigned char pin_flags;
++ struct au_pin pin;
++ struct super_block *sb;
++ struct dentry *d, *parent, *h_parent, *real_parent;
++
++ LKTRTrace("%.*s, b%d, parent i%lu\n",
++ AuDLNPair(dentry), bdst, (unsigned long)parent_ino(dentry));
++ sb = dentry->d_sb;
++ AuDebugOn(au_test_ro(sb, bdst, NULL));
++ err = 0;
++ parent = dget_parent(dentry);
++ IiMustWriteLock(parent->d_inode);
++ if (IS_ROOT(parent))
++ goto out;
++
++ pin_flags = AuPin_MNT_WRITE;
++ if (au_opt_test(au_mntflags(sb), UDBA_INOTIFY))
++ au_fset_pin(pin_flags, DO_GPARENT);
++ au_pin_init(&pin, dentry, bdst, AuLsc_DI_PARENT3, AuLsc_I_PARENT2,
++ pin_flags);
++
++ /* do not use au_dpage */
++ real_parent = parent;
++ while (1) {
++ dput(parent);
++ parent = dget_parent(dentry);
++ h_parent = au_h_dptr(parent, bdst);
++ if (h_parent)
++ goto out; /* success */
++
++ /* find top dir which is needed to cpup */
++ do {
++ d = parent;
++ dput(parent);
++ parent = dget_parent(d);
++ di_read_lock_parent3(parent, !AuLock_IR);
++ h_parent = au_h_dptr(parent, bdst);
++ di_read_unlock(parent, !AuLock_IR);
++ } while (!h_parent);
++
++ if (d != real_parent)
++ di_write_lock_child3(d);
++
++ /* somebody else might create while we were sleeping */
++ if (!au_h_dptr(d, bdst) || !au_h_dptr(d, bdst)->d_inode) {
++ if (au_h_dptr(d, bdst))
++ au_update_dbstart(d);
++
++ au_pin_do_set_dentry(pin.pin + AuPin_PARENT, d);
++ err = au_do_pin(pin.pin + AuPin_PARENT,
++ au_pin_gp(&pin));
++ if (!err) {
++ err = cp(d, bdst, h_parent, arg);
++ au_unpin(&pin);
++ }
++ }
++
++ if (d != real_parent)
++ di_write_unlock(d);
++ if (unlikely(err))
++ break;
++ }
++
++ out:
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_cpup_dir(struct dentry *dentry, aufs_bindex_t bdst,
++ struct dentry *h_parent, void *arg)
++{
++ int err;
++
++ err = au_sio_cpup_simple(dentry, bdst, -1, AuCpup_DTIME);
++
++ AuTraceErr(err);
++ return err;
++}
++
++int au_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst)
++{
++ int err;
++
++ err = au_cp_dirs(dentry, bdst, au_cpup_dir, NULL);
++
++ AuTraceErr(err);
++ return err;
++}
++
++int au_test_and_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst)
++{
++ int err;
++ struct dentry *parent;
++ struct inode *dir;
++
++ parent = dget_parent(dentry);
++ dir = parent->d_inode;
++ LKTRTrace("%.*s, b%d, parent i%lu\n",
++ AuDLNPair(dentry), bdst, dir->i_ino);
++ DiMustReadLock(parent);
++ IiMustReadLock(dir);
++
++ err = 0;
++ if (au_h_iptr(dir, bdst))
++ goto out;
++
++ di_read_unlock(parent, AuLock_IR);
++ di_write_lock_parent(parent);
++ /* someone else might change our inode while we were sleeping */
++ if (!au_h_iptr(dir, bdst))
++ err = au_cpup_dirs(dentry, bdst);
++ di_downgrade_lock(parent, AuLock_IR);
++
++ out:
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
+diff --git a/fs/aufs/cpup.h b/fs/aufs/cpup.h
+new file mode 100644
+index 0000000..2ae810d
+--- /dev/null
++++ b/fs/aufs/cpup.h
+@@ -0,0 +1,95 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * copy-up/down functions
++ *
++ * $Id: cpup.h,v 1.36 2009/01/26 06:23:51 sfjro Exp $
++ */
++
++#ifndef __AUFS_CPUP_H__
++#define __AUFS_CPUP_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/version.h>
++#include <linux/aufs_type.h>
++
++static inline
++void au_cpup_attr_blksize(struct inode *inode, struct inode *h_inode)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)
++ inode->i_blksize = h_inode->i_blksize;
++#endif
++}
++
++void au_cpup_attr_timesizes(struct inode *inode);
++void au_cpup_attr_nlink(struct inode *inode, int force);
++void au_cpup_attr_changeable(struct inode *inode);
++void au_cpup_igen(struct inode *inode, struct inode *h_inode);
++void au_cpup_attr_all(struct inode *inode, int force);
++
++/* ---------------------------------------------------------------------- */
++
++/* cpup flags */
++#define AuCpup_DTIME 1 /* do dtime_store/revert */
++#define AuCpup_KEEPLINO (1 << 1) /* do not clear the lower xino,
++ for link(2) */
++#define au_ftest_cpup(flags, name) ((flags) & AuCpup_##name)
++#define au_fset_cpup(flags, name) { (flags) |= AuCpup_##name; }
++#define au_fclr_cpup(flags, name) { (flags) &= ~AuCpup_##name; }
++
++int au_sio_cpup_single(struct dentry *dentry, aufs_bindex_t bdst,
++ aufs_bindex_t bsrc, loff_t len, unsigned int flags,
++ struct dentry *dst_parent);
++int au_sio_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len,
++ unsigned int flags);
++int au_sio_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len,
++ struct file *file);
++
++int au_cp_dirs(struct dentry *dentry, aufs_bindex_t bdst,
++ int (*cp)(struct dentry *dentry, aufs_bindex_t bdst,
++ struct dentry *h_parent, void *arg),
++ void *arg);
++int au_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst);
++int au_test_and_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst);
++
++/* ---------------------------------------------------------------------- */
++
++/* keep timestamps when copyup */
++struct au_dtime {
++ struct dentry *dt_dentry, *dt_h_dentry;
++ struct au_hinode *dt_hinode, *dt_hdir;
++ struct timespec dt_atime, dt_mtime;
++};
++void au_dtime_store(struct au_dtime *dt, struct dentry *dentry,
++ struct dentry *h_dentry, struct au_hinode *hinode,
++ struct au_hinode *hdir);
++void au_dtime_revert(struct au_dtime *dt);
++
++/* ---------------------------------------------------------------------- */
++
++static inline void au_cpup_attr_flags(struct inode *inode,
++ struct inode *h_inode)
++{
++ inode->i_flags |= h_inode->i_flags & ~(S_DEAD | S_PRIVATE);
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_CPUP_H__ */
+diff --git a/fs/aufs/dcsub.c b/fs/aufs/dcsub.c
+new file mode 100644
+index 0000000..184eced
+--- /dev/null
++++ b/fs/aufs/dcsub.c
+@@ -0,0 +1,250 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * sub-routines for dentry cache
++ *
++ * $Id: dcsub.c,v 1.16 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++static void au_dpage_free(struct au_dpage *dpage)
++{
++ int i;
++
++ AuTraceEnter();
++ AuDebugOn(!dpage);
++
++ for (i = 0; i < dpage->ndentry; i++)
++ dput(dpage->dentries[i]);
++ free_page((unsigned long)dpage->dentries);
++}
++
++int au_dpages_init(struct au_dcsub_pages *dpages, gfp_t gfp)
++{
++ int err;
++ void *p;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ dpages->dpages = kmalloc(sizeof(*dpages->dpages), gfp);
++ if (unlikely(!dpages->dpages))
++ goto out;
++ p = (void *)__get_free_page(gfp);
++ if (unlikely(!p))
++ goto out_dpages;
++ dpages->dpages[0].ndentry = 0;
++ dpages->dpages[0].dentries = p;
++ dpages->ndpage = 1;
++ return 0; /* success */
++
++ out_dpages:
++ kfree(dpages->dpages);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++void au_dpages_free(struct au_dcsub_pages *dpages)
++{
++ int i;
++
++ AuTraceEnter();
++
++ for (i = 0; i < dpages->ndpage; i++)
++ au_dpage_free(dpages->dpages + i);
++ kfree(dpages->dpages);
++}
++
++static int au_dpages_append(struct au_dcsub_pages *dpages,
++ struct dentry *dentry, gfp_t gfp)
++{
++ int err, sz;
++ struct au_dpage *dpage;
++ void *p;
++
++ /* AuTraceEnter(); */
++
++ dpage = dpages->dpages + dpages->ndpage - 1;
++ AuDebugOn(!dpage);
++ sz = PAGE_SIZE / sizeof(dentry);
++ if (unlikely(dpage->ndentry >= sz)) {
++ LKTRLabel(new dpage);
++ err = -ENOMEM;
++ sz = dpages->ndpage * sizeof(*dpages->dpages);
++ p = au_kzrealloc(dpages->dpages, sz,
++ sz + sizeof(*dpages->dpages), gfp);
++ if (unlikely(!p))
++ goto out;
++ dpages->dpages = p;
++ dpage = dpages->dpages + dpages->ndpage;
++ p = (void *)__get_free_page(gfp);
++ if (unlikely(!p))
++ goto out;
++ dpage->ndentry = 0;
++ dpage->dentries = p;
++ dpages->ndpage++;
++ }
++
++ dpage->dentries[dpage->ndentry++] = dget(dentry);
++ return 0; /* success */
++
++ out:
++ /* AuTraceErr(err); */
++ return err;
++}
++
++int au_dcsub_pages(struct au_dcsub_pages *dpages, struct dentry *root,
++ au_dpages_test test, void *arg)
++{
++ int err;
++ struct dentry *this_parent = root;
++ struct list_head *next;
++ struct super_block *sb = root->d_sb;
++
++ AuTraceEnter();
++
++ err = 0;
++ spin_lock(&dcache_lock);
++ repeat:
++ next = this_parent->d_subdirs.next;
++ resume:
++ if (this_parent->d_sb == sb
++ && !IS_ROOT(this_parent)
++ && atomic_read(&this_parent->d_count)
++ && this_parent->d_inode
++ && (!test || test(this_parent, arg))) {
++ err = au_dpages_append(dpages, this_parent, GFP_ATOMIC);
++ if (unlikely(err))
++ goto out;
++ }
++
++ while (next != &this_parent->d_subdirs) {
++ struct list_head *tmp = next;
++ struct dentry *dentry = list_entry(tmp, struct dentry, D_CHILD);
++ next = tmp->next;
++ if (/*d_unhashed(dentry) || */!dentry->d_inode)
++ continue;
++ if (!list_empty(&dentry->d_subdirs)) {
++ this_parent = dentry;
++ goto repeat;
++ }
++ if (dentry->d_sb == sb
++ && atomic_read(&dentry->d_count)
++ && (!test || test(dentry, arg))) {
++ err = au_dpages_append(dpages, dentry, GFP_ATOMIC);
++ if (unlikely(err))
++ goto out;
++ }
++ }
++
++ if (this_parent != root) {
++ next = this_parent->D_CHILD.next;
++ this_parent = this_parent->d_parent; /* dcache_lock is locked */
++ goto resume;
++ }
++ out:
++ spin_unlock(&dcache_lock);
++#if 0 /* debug */
++ if (!err) {
++ int i, j;
++ j = 0;
++ for (i = 0; i < dpages->ndpage; i++) {
++ if ((dpages->dpages + i)->ndentry)
++ AuDbg("%d: %d\n",
++ i, (dpages->dpages + i)->ndentry);
++ j += (dpages->dpages + i)->ndentry;
++ }
++ if (j)
++ AuDbg("ndpage %d, %d\n", dpages->ndpage, j);
++ }
++#endif
++ AuTraceErr(err);
++ return err;
++}
++
++int au_dcsub_pages_rev(struct au_dcsub_pages *dpages, struct dentry *dentry,
++ int do_include, au_dpages_test test, void *arg)
++{
++ int err;
++
++ AuTraceEnter();
++
++ err = 0;
++ spin_lock(&dcache_lock);
++ if (do_include && (!test || test(dentry, arg))) {
++ err = au_dpages_append(dpages, dentry, GFP_ATOMIC);
++ if (unlikely(err))
++ goto out;
++ }
++ while (!IS_ROOT(dentry)) {
++ dentry = dentry->d_parent; /* dcache_lock is locked */
++ if (!test || test(dentry, arg)) {
++ err = au_dpages_append(dpages, dentry, GFP_ATOMIC);
++ if (unlikely(err))
++ break;
++ }
++ }
++
++ out:
++ spin_unlock(&dcache_lock);
++
++ AuTraceErr(err);
++ return err;
++}
++
++struct dentry *au_test_subdir(struct dentry *d1, struct dentry *d2)
++{
++ struct dentry *trap, **dentries;
++ int err, i, j;
++ struct au_dcsub_pages dpages;
++ struct au_dpage *dpage;
++
++ LKTRTrace("%.*s, %.*s\n", AuDLNPair(d1), AuDLNPair(d2));
++
++ trap = ERR_PTR(-ENOMEM);
++ err = au_dpages_init(&dpages, GFP_NOFS);
++ if (unlikely(err))
++ goto out;
++ err = au_dcsub_pages_rev(&dpages, d1, /*do_include*/1, NULL, NULL);
++ if (unlikely(err))
++ goto out_dpages;
++
++ trap = d1;
++ for (i = 0; !err && i < dpages.ndpage; i++) {
++ dpage = dpages.dpages + i;
++ dentries = dpage->dentries;
++ for (j = 0; !err && j < dpage->ndentry; j++) {
++ struct dentry *d;
++ d = dentries[j];
++ err = (d == d2);
++ if (!err)
++ trap = d;
++ }
++ }
++ if (!err)
++ trap = NULL;
++
++ out_dpages:
++ au_dpages_free(&dpages);
++ out:
++ AuTraceErrPtr(trap);
++ return trap;
++}
+diff --git a/fs/aufs/dcsub.h b/fs/aufs/dcsub.h
+new file mode 100644
+index 0000000..c437986
+--- /dev/null
++++ b/fs/aufs/dcsub.h
+@@ -0,0 +1,54 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * sub-routines for dentry cache
++ *
++ * $Id: dcsub.h,v 1.9 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_DCSUB_H__
++#define __AUFS_DCSUB_H__
++
++#ifdef __KERNEL__
++
++#include <linux/dcache.h>
++
++struct au_dpage {
++ int ndentry;
++ struct dentry **dentries;
++};
++
++struct au_dcsub_pages {
++ int ndpage;
++ struct au_dpage *dpages;
++};
++
++/* ---------------------------------------------------------------------- */
++
++int au_dpages_init(struct au_dcsub_pages *dpages, gfp_t gfp);
++void au_dpages_free(struct au_dcsub_pages *dpages);
++typedef int (*au_dpages_test)(struct dentry *dentry, void *arg);
++int au_dcsub_pages(struct au_dcsub_pages *dpages, struct dentry *root,
++ au_dpages_test test, void *arg);
++int au_dcsub_pages_rev(struct au_dcsub_pages *dpages, struct dentry *dentry,
++ int do_include, au_dpages_test test, void *arg);
++struct dentry *au_test_subdir(struct dentry *d1, struct dentry *d2);
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_DCSUB_H__ */
+diff --git a/fs/aufs/debug.c b/fs/aufs/debug.c
+new file mode 100644
+index 0000000..2591694
+--- /dev/null
++++ b/fs/aufs/debug.c
+@@ -0,0 +1,539 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * debug print functions
++ *
++ * $Id: debug.c,v 1.59 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/errno.h>
++#include "aufs.h"
++
++atomic_t au_cond = ATOMIC_INIT(0);
++
++char *au_plevel = KERN_DEBUG;
++#define dpri(fmt, arg...) do { \
++ if (LktrCond) \
++ printk("%s" fmt, au_plevel, ##arg); \
++} while (0)
++
++/* ---------------------------------------------------------------------- */
++
++void au_dpri_whlist(struct au_nhash *whlist)
++{
++ int i;
++ struct hlist_head *head;
++ struct au_vdir_wh *tpos;
++ struct hlist_node *pos;
++
++ for (i = 0; i < AuSize_NHASH; i++) {
++ head = whlist->heads + i;
++ hlist_for_each_entry(tpos, pos, head, wh_hash)
++ dpri("b%d, %.*s, %d\n",
++ tpos->wh_bindex,
++ tpos->wh_str.len, tpos->wh_str.name,
++ tpos->wh_str.len);
++ }
++}
++
++void au_dpri_vdir(struct au_vdir *vdir)
++{
++ int i;
++ union au_vdir_deblk_p p;
++ unsigned char *o;
++
++ if (!vdir || IS_ERR(vdir)) {
++ dpri("err %ld\n", PTR_ERR(vdir));
++ return;
++ }
++
++ dpri("nblk %d, deblk %p, last{%d, %p}, ver %lu\n",
++ vdir->vd_nblk, vdir->vd_deblk,
++ vdir->vd_last.i, vdir->vd_last.p.p, vdir->vd_version);
++ for (i = 0; i < vdir->vd_nblk; i++) {
++ p.deblk = vdir->vd_deblk[i];
++ o = p.p;
++ dpri("[%d]: %p\n", i, o);
++#if 0 // verbose
++ int j;
++ for (j = 0; j < 8; j++) {
++ dpri("%p(+%d) {%02x %02x %02x %02x %02x %02x %02x %02x "
++ "%02x %02x %02x %02x %02x %02x %02x %02x}\n",
++ p.p, p.p - o,
++ p.p[0], p.p[1], p.p[2], p.p[3],
++ p.p[4], p.p[5], p.p[6], p.p[7],
++ p.p[8], p.p[9], p.p[10], p.p[11],
++ p.p[12], p.p[13], p.p[14], p.p[15]);
++ p.p += 16;
++ }
++#endif
++ }
++}
++
++static int do_pri_inode(aufs_bindex_t bindex, struct inode *inode,
++ struct dentry *wh)
++{
++ char *n = NULL;
++ int l = 0, ntfy = 0;
++
++ if (!inode || IS_ERR(inode)) {
++ dpri("i%d: err %ld\n", bindex, PTR_ERR(inode));
++ return -1;
++ }
++
++ /* the type of i_blocks depends upon CONFIG_LSF */
++ BUILD_BUG_ON(sizeof(inode->i_blocks) != sizeof(unsigned long)
++ && sizeof(inode->i_blocks) != sizeof(u64));
++ if (wh) {
++ n = (void *)wh->d_name.name;
++ l = wh->d_name.len;
++ }
++
++ ntfy = au_test_inotify(inode);
++ dpri("i%d: i%lu, %s, cnt %d, nl %u, 0%o, ntfy %d, sz %llu, blk %llu,"
++ " ct %lld, np %lu, st 0x%lx, f 0x%x, g %x%s%.*s\n",
++ bindex,
++ inode->i_ino, inode->i_sb ? au_sbtype(inode->i_sb) : "??",
++ atomic_read(&inode->i_count), inode->i_nlink, inode->i_mode,
++ ntfy,
++ i_size_read(inode), (unsigned long long)inode->i_blocks,
++ (long long)timespec_to_ns(&inode->i_ctime) & 0x0ffff,
++ inode->i_mapping ? inode->i_mapping->nrpages : 0,
++ inode->i_state, inode->i_flags, inode->i_generation,
++ l ? ", wh " : "", l, n);
++ return 0;
++}
++
++void au_dpri_inode(struct inode *inode)
++{
++ struct au_iinfo *iinfo;
++ aufs_bindex_t bindex;
++ int err;
++
++ err = do_pri_inode(-1, inode, NULL);
++ if (err || !au_test_aufs(inode->i_sb))
++ return;
++
++ iinfo = au_ii(inode);
++ if (!iinfo)
++ return;
++ dpri("i-1: bstart %d, bend %d, gen %d\n",
++ iinfo->ii_bstart, iinfo->ii_bend, au_iigen(inode));
++ if (iinfo->ii_bstart < 0)
++ return;
++ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend; bindex++)
++ do_pri_inode(bindex, iinfo->ii_hinode[0 + bindex].hi_inode,
++ iinfo->ii_hinode[0 + bindex].hi_whdentry);
++}
++
++static int do_pri_dentry(aufs_bindex_t bindex, struct dentry *dentry,
++ struct list_head *intent)
++{
++ struct dentry *wh = NULL;
++
++ if (!dentry || IS_ERR(dentry)) {
++ dpri("d%d: err %ld\n", bindex, PTR_ERR(dentry));
++ return -1;
++ }
++ /* do not call dget_parent() here */
++ dpri("d%d: %.*s?/%.*s, %s, cnt %d, flags 0x%x, intent %d\n",
++ bindex,
++ AuDLNPair(dentry->d_parent), AuDLNPair(dentry),
++ dentry->d_sb ? au_sbtype(dentry->d_sb) : "??",
++ atomic_read(&dentry->d_count), dentry->d_flags, !!intent);
++ if (bindex >= 0 && dentry->d_inode && au_test_aufs(dentry->d_sb)) {
++ struct au_iinfo *iinfo = au_ii(dentry->d_inode);
++ if (iinfo)
++ wh = iinfo->ii_hinode[0 + bindex].hi_whdentry;
++ }
++ do_pri_inode(bindex, dentry->d_inode, wh);
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) \
++ && defined(CONFIG_AUFS_BR_NFS)
++static struct list_head *au_dbg_h_intent(struct au_dinfo *dinfo,
++ aufs_bindex_t bindex)
++{
++ return dinfo->di_hdentry[0 + bindex].hd_intent_list;
++}
++#else
++static struct list_head *au_dbg_h_intent(struct au_dinfo *dinfo,
++ aufs_bindex_t bindex)
++{
++ return NULL;
++}
++#endif
++
++void au_dpri_dentry(struct dentry *dentry)
++{
++ struct au_dinfo *dinfo;
++ aufs_bindex_t bindex;
++ int err;
++
++ err = do_pri_dentry(-1, dentry, NULL);
++ if (err || !au_test_aufs(dentry->d_sb))
++ return;
++
++ dinfo = au_di(dentry);
++ if (!dinfo)
++ return;
++ dpri("d-1: bstart %d, bend %d, bwh %d, bdiropq %d, gen %d\n",
++ dinfo->di_bstart, dinfo->di_bend,
++ dinfo->di_bwh, dinfo->di_bdiropq, au_digen(dentry));
++ if (dinfo->di_bstart < 0)
++ return;
++ for (bindex = dinfo->di_bstart; bindex <= dinfo->di_bend; bindex++)
++ do_pri_dentry(bindex, dinfo->di_hdentry[0 + bindex].hd_dentry,
++ au_dbg_h_intent(dinfo, bindex));
++}
++
++static int do_pri_file(aufs_bindex_t bindex, struct file *file)
++{
++ char a[32];
++
++ if (!file || IS_ERR(file)) {
++ dpri("f%d: err %ld\n", bindex, PTR_ERR(file));
++ return -1;
++ }
++ a[0] = 0;
++ if (bindex < 0
++ && file->f_dentry
++ && au_test_aufs(file->f_dentry->d_sb)
++ && au_fi(file))
++ snprintf(a, sizeof(a), ", mmapped %d", au_test_mmapped(file));
++ dpri("f%d: mode 0x%x, flags 0%o, cnt %ld, pos %llu%s\n",
++ bindex, file->f_mode, file->f_flags, (long)file_count(file),
++ file->f_pos, a);
++ if (file->f_dentry)
++ do_pri_dentry(bindex, file->f_dentry, NULL);
++ return 0;
++}
++
++void au_dpri_file(struct file *file)
++{
++ struct au_finfo *finfo;
++ aufs_bindex_t bindex;
++ int err;
++
++ err = do_pri_file(-1, file);
++ if (err || !file->f_dentry || !au_test_aufs(file->f_dentry->d_sb))
++ return;
++
++ finfo = au_fi(file);
++ if (!finfo)
++ return;
++ if (finfo->fi_bstart < 0)
++ return;
++ for (bindex = finfo->fi_bstart; bindex <= finfo->fi_bend; bindex++) {
++ struct au_hfile *hf;
++ hf = finfo->fi_hfile + bindex;
++ do_pri_file(bindex, hf ? hf->hf_file : NULL);
++ }
++}
++
++static int do_pri_br(aufs_bindex_t bindex, struct au_branch *br)
++{
++ struct vfsmount *mnt;
++ struct super_block *sb;
++
++ if (!br || IS_ERR(br)
++ || !(mnt = br->br_mnt) || IS_ERR(mnt)
++ || !(sb = mnt->mnt_sb) || IS_ERR(sb)) {
++ dpri("s%d: err %ld\n", bindex, PTR_ERR(br));
++ return -1;
++ }
++
++ dpri("s%d: {perm 0x%x, cnt %d, wbr %p}, "
++ "%s, dev 0x%02x%02x, flags 0x%lx, cnt(BIAS) %d, active %d, "
++ "xino %d\n",
++ bindex, br->br_perm, au_br_count(br), br->br_wbr,
++ au_sbtype(sb), MAJOR(sb->s_dev), MINOR(sb->s_dev),
++ sb->s_flags, sb->s_count - S_BIAS,
++ atomic_read(&sb->s_active), !!br->br_xino.xi_file);
++ return 0;
++}
++
++void au_dpri_sb(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++ aufs_bindex_t bindex;
++ int err;
++ /* to reuduce stack size */
++ struct {
++ struct vfsmount mnt;
++ struct au_branch fake;
++ } *a;
++
++ /* this function can be called from magic sysrq */
++ a = kzalloc(sizeof(*a), GFP_ATOMIC);
++ if (unlikely(!a)) {
++ dpri("no memory\n");
++ return;
++ }
++
++ a->mnt.mnt_sb = sb;
++ a->fake.br_perm = 0;
++ a->fake.br_mnt = &a->mnt;
++ a->fake.br_xino.xi_file = NULL;
++ atomic_set(&a->fake.br_count, 0);
++ smp_mb(); /* atomic_set */
++ err = do_pri_br(-1, &a->fake);
++ kfree(a);
++ dpri("dev 0x%x\n", sb->s_dev);
++ if (err || !au_test_aufs(sb))
++ return;
++
++ sbinfo = au_sbi(sb);
++ if (!sbinfo)
++ return;
++ dpri("nw %d, gen %u\n",
++ atomic_read(&sbinfo->si_nowait.nw_len), sbinfo->si_generation);
++ for (bindex = 0; bindex <= sbinfo->si_bend; bindex++)
++ do_pri_br(bindex, sbinfo->si_branch[0 + bindex]);
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_dbg_sleep(int sec)
++{
++ static DECLARE_WAIT_QUEUE_HEAD(wq);
++ wait_event_timeout(wq, 0, sec * HZ);
++}
++
++void au_dbg_sleep_jiffy(int jiffy)
++{
++ static DECLARE_WAIT_QUEUE_HEAD(wq);
++ wait_event_timeout(wq, 0, jiffy);
++}
++
++void au_dbg_iattr(struct iattr *ia)
++{
++#define AuBit(name) if (ia->ia_valid & ATTR_ ## name) \
++ dpri(#name "\n")
++ AuBit(MODE);
++ AuBit(UID);
++ AuBit(GID);
++ AuBit(SIZE);
++ AuBit(ATIME);
++ AuBit(MTIME);
++ AuBit(CTIME);
++ AuBit(ATIME_SET);
++ AuBit(MTIME_SET);
++ AuBit(FORCE);
++ AuBit(ATTR_FLAG);
++ AuBit(KILL_SUID);
++ AuBit(KILL_SGID);
++ AuBit(FILE);
++ AuBit(KILL_PRIV);
++ AuBit(OPEN);
++#undef AuBit
++ dpri("ia_file %p\n", ia->ia_file);
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_debug_sbinfo_init(struct au_sbinfo *sbinfo)
++{
++#ifdef ForceInotify
++ au_opt_set_udba(sbinfo->si_mntflags, UDBA_INOTIFY);
++#endif
++#ifdef ForceDlgt
++ au_opt_set(sbinfo->si_mntflags, DLGT);
++#endif
++#ifdef ForceNoPlink
++ au_opt_clr(sbinfo->si_mntflags, PLINK);
++#endif
++#ifdef ForceNoXino
++ au_opt_clr(sbinfo->si_mntflags, XINO);
++#endif
++#ifdef ForceNoRefrof
++ au_opt_clr(sbinfo->si_mntflags, REFROF);
++#endif
++#ifdef ForceShwh
++ au_opt_set(sbinfo->si_mntflags, SHWH);
++#endif
++
++#ifdef CONFIG_AUFS_DEBUG_LOCK
++ {
++ int i;
++ for (i = 0; i < AuDbgLock_Last; i++)
++ au_spl_init(sbinfo->si_dbg_lock + i);
++ }
++#endif
++}
++
++int __init au_debug_init(void)
++{
++ aufs_bindex_t bindex;
++ struct au_vdir_destr destr;
++
++ bindex = -1;
++ AuDebugOn(bindex >= 0);
++
++ destr.len = -1;
++ AuDebugOn(destr.len < NAME_MAX);
++
++#ifdef CONFIG_4KSTACKS
++ AuWarn("CONFIG_4KSTACKS is defined.\n");
++#endif
++
++#ifdef ForceBrs
++ sysaufs_brs = 1;
++#endif
++
++#if 0 /* verbose debug */
++ {
++ union {
++ struct au_branch *br;
++ struct au_dinfo *di;
++ struct au_finfo *fi;
++ struct au_iinfo *ii;
++ struct au_hinode *hi;
++ struct au_sbinfo *si;
++ struct au_vdir_destr *destr;
++ struct au_vdir_de *de;
++ struct au_vdir_wh *wh;
++ struct au_vdir *vd;
++ } u;
++
++ pr_info("br{"
++ "xino %d, "
++ "id %d, perm %d, mnt %d, count %d, "
++ "wbr %d, "
++ "xup %d, xrun %d, "
++ "gen %d, "
++ "sa %d} %d\n",
++ offsetof(typeof(*u.br), br_xino),
++ offsetof(typeof(*u.br), br_id),
++ offsetof(typeof(*u.br), br_perm),
++ offsetof(typeof(*u.br), br_mnt),
++ offsetof(typeof(*u.br), br_count),
++ offsetof(typeof(*u.br), wbr),
++ offsetof(typeof(*u.br), br_xino_upper),
++ offsetof(typeof(*u.br), br_xino_running),
++ offsetof(typeof(*u.br), br_generation),
++ offsetof(typeof(*u.br), br_sabr),
++ sizeof(*u.br));
++ pr_info("di{gen %d, rwsem %d, bstart %d, bend %d, bwh %d, "
++ "bdiropq %d, hdentry %d} %d\n",
++ offsetof(typeof(*u.di), di_generation),
++ offsetof(typeof(*u.di), di_rwsem),
++ offsetof(typeof(*u.di), di_bstart),
++ offsetof(typeof(*u.di), di_bend),
++ offsetof(typeof(*u.di), di_bwh),
++ offsetof(typeof(*u.di), di_bdiropq),
++ offsetof(typeof(*u.di), di_hdentry),
++ sizeof(*u.di));
++ pr_info("fi{gen %d, rwsem %d, hfile %d, bstart %d, bend %d, "
++ "h_vm_ops %d, vdir_cach %d} %d\n",
++ offsetof(typeof(*u.fi), fi_generation),
++ offsetof(typeof(*u.fi), fi_rwsem),
++ offsetof(typeof(*u.fi), fi_hfile),
++ offsetof(typeof(*u.fi), fi_bstart),
++ offsetof(typeof(*u.fi), fi_bend),
++ offsetof(typeof(*u.fi), fi_h_vm_ops),
++ offsetof(typeof(*u.fi), fi_vdir_cache),
++ sizeof(*u.fi));
++ pr_info("ii{gen %d, hsb %d, "
++ "rwsem %d, bstart %d, bend %d, hinode %d, vdir %d} "
++ "%d\n",
++ offsetof(typeof(*u.ii), ii_generation),
++ offsetof(typeof(*u.ii), ii_hsb1),
++ offsetof(typeof(*u.ii), ii_rwsem),
++ offsetof(typeof(*u.ii), ii_bstart),
++ offsetof(typeof(*u.ii), ii_bend),
++ offsetof(typeof(*u.ii), ii_hinode),
++ offsetof(typeof(*u.ii), ii_vdir),
++ sizeof(*u.ii));
++ pr_info("hi{inode %d, id %d, notify %d, wh %d} %d\n",
++ offsetof(typeof(*u.hi), hi_inode),
++ offsetof(typeof(*u.hi), hi_id),
++ offsetof(typeof(*u.hi), hi_notify),
++ offsetof(typeof(*u.hi), hi_whdentry),
++ sizeof(*u.hi));
++ pr_info("si{nwt %d, rwsem %d, gen %d, stat %d, "
++ "bend %d, last id %d, br %d, "
++ "cpup %d, creat %d, ops %d, ops %d, "
++ "rr %d, mfs %d, "
++ "mntflags %d, "
++ "xread %d, xwrite %d, xib %d, xmtx %d, buf %d, "
++ "xlast %d, xnext %d, "
++ "rdcache %d, "
++ "dirwh %d, "
++ "pl %d, "
++ "mnt %d, "
++ "sys %d, "
++ /* "lvma_l %d, lvma %d" */
++ "} %d\n",
++ offsetof(typeof(*u.si), si_nowait),
++ offsetof(typeof(*u.si), si_rwsem),
++ offsetof(typeof(*u.si), si_generation),
++ offsetof(typeof(*u.si), au_si_status),
++ offsetof(typeof(*u.si), si_bend),
++ offsetof(typeof(*u.si), si_last_br_id),
++ offsetof(typeof(*u.si), si_branch),
++ offsetof(typeof(*u.si), si_wbr_copyup),
++ offsetof(typeof(*u.si), si_wbr_create),
++ offsetof(typeof(*u.si), si_wbr_copyup_ops),
++ offsetof(typeof(*u.si), si_wbr_create_ops),
++ offsetof(typeof(*u.si), si_wbr_rr_next),
++ offsetof(typeof(*u.si), si_wbr_mfs),
++ offsetof(typeof(*u.si), si_mntflags),
++ offsetof(typeof(*u.si), si_xread),
++ offsetof(typeof(*u.si), si_xwrite),
++ offsetof(typeof(*u.si), si_xib),
++ offsetof(typeof(*u.si), si_xib_mtx),
++ offsetof(typeof(*u.si), si_xib_buf),
++ offsetof(typeof(*u.si), si_xib_last_pindex),
++ offsetof(typeof(*u.si), si_xib_next_bit),
++ offsetof(typeof(*u.si), si_rdcache),
++ offsetof(typeof(*u.si), si_dirwh),
++ offsetof(typeof(*u.si), si_plink),
++ offsetof(typeof(*u.si), si_mnt),
++ offsetof(typeof(*u.si), si_sa),
++ /*offsetof(typeof(*u.si), si_lvma_lock),
++ offsetof(typeof(*u.si), si_lvma),*/
++ sizeof(*u.si));
++ pr_info("destr{len %d, name %d} %d\n",
++ offsetof(typeof(*u.destr), len),
++ offsetof(typeof(*u.destr), name),
++ sizeof(*u.destr));
++ pr_info("de{ino %d, type %d, str %d} %d\n",
++ offsetof(typeof(*u.de), de_ino),
++ offsetof(typeof(*u.de), de_type),
++ offsetof(typeof(*u.de), de_str),
++ sizeof(*u.de));
++ pr_info("wh{hash %d, bindex %d, str %d} %d\n",
++ offsetof(typeof(*u.wh), wh_hash),
++ offsetof(typeof(*u.wh), wh_bindex),
++ offsetof(typeof(*u.wh), wh_str),
++ sizeof(*u.wh));
++ pr_info("vd{deblk %d, nblk %d, last %d, ver %d, jiffy %d} %d\n",
++ offsetof(typeof(*u.vd), vd_deblk),
++ offsetof(typeof(*u.vd), vd_nblk),
++ offsetof(typeof(*u.vd), vd_last),
++ offsetof(typeof(*u.vd), vd_version),
++ offsetof(typeof(*u.vd), vd_jiffy),
++ sizeof(*u.vd));
++ }
++#endif
++
++ return 0;
++}
+diff --git a/fs/aufs/debug.h b/fs/aufs/debug.h
+new file mode 100644
+index 0000000..a7bba3c
+--- /dev/null
++++ b/fs/aufs/debug.h
+@@ -0,0 +1,337 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * debug print functions
++ *
++ * $Id: debug.h,v 1.54 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_DEBUG_H__
++#define __AUFS_DEBUG_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/kd.h>
++#include <linux/vt_kern.h>
++#include <linux/sysrq.h>
++
++/* to debug easier, do not make it an inlined function */
++#define MtxMustLock(mtx) AuDebugOn(!mutex_is_locked(mtx))
++
++#ifdef CONFIG_AUFS_DEBUG
++/* sparse warns about pointer */
++#define AuDebugOn(a) BUG_ON(!!(a))
++extern atomic_t au_cond;
++#define au_debug_on() atomic_inc_return(&au_cond)
++#define au_debug_off() atomic_dec_return(&au_cond)
++static inline int au_debug_test(void)
++{
++ return atomic_read(&au_cond);
++}
++#else
++#define AuDebugOn(a) do {} while (0)
++#define au_debug_on() do {} while (0)
++#define au_debug_off() do {} while (0)
++static inline int au_debug_test(void)
++{
++ return 0;
++}
++#endif /* CONFIG_AUFS_DEBUG */
++
++/* ---------------------------------------------------------------------- */
++
++/* debug print */
++#if defined(CONFIG_LKTR) || defined(CONFIG_LKTR_MODULE)
++#include <linux/lktr.h>
++#ifdef CONFIG_AUFS_DEBUG
++#undef LktrCond
++#define LktrCond unlikely(au_debug_test() || (lktr_cond && lktr_cond()))
++#endif
++#else
++#define LktrCond au_debug_test()
++#define LKTRDumpVma(pre, vma, suf) do {} while (0)
++#define LKTRDumpStack() do {} while (0)
++#define LKTRTrace(fmt, args...) do { \
++ if (LktrCond) \
++ AuDbg(fmt, ##args); \
++} while (0)
++#define LKTRLabel(label) LKTRTrace("%s\n", #label)
++#endif /* CONFIG_LKTR */
++
++#define AuTraceErr(e) do { \
++ if (unlikely((e) < 0)) \
++ LKTRTrace("err %d\n", (int)(e)); \
++} while (0)
++
++#define AuTraceErrPtr(p) do { \
++ if (IS_ERR(p)) \
++ LKTRTrace("err %ld\n", PTR_ERR(p)); \
++} while (0)
++
++#define AuTraceEnter() LKTRLabel(enter)
++
++/* dirty macros for debug print, use with "%.*s" and caution */
++#define AuLNPair(qstr) (qstr)->len, (qstr)->name
++#define AuDLNPair(d) AuLNPair(&(d)->d_name)
++
++/* ---------------------------------------------------------------------- */
++
++#define AuDpri(lvl, fmt, arg...) \
++ printk(lvl AUFS_NAME " %s:%d:%s[%d]: " fmt, \
++ __func__, __LINE__, current->comm, current->pid, ##arg)
++#define AuDbg(fmt, arg...) AuDpri(KERN_DEBUG, fmt, ##arg)
++#define AuInfo(fmt, arg...) AuDpri(KERN_INFO, fmt, ##arg)
++#define AuWarn(fmt, arg...) AuDpri(KERN_WARNING, fmt, ##arg)
++#define AuErr(fmt, arg...) AuDpri(KERN_ERR, fmt, ##arg)
++#define AuIOErr(fmt, arg...) AuErr("I/O Error, " fmt, ##arg)
++#define AuIOErrWhck(fmt, arg...) AuErr("I/O Error, try whck. " fmt, ##arg)
++#define AuWarn1(fmt, arg...) do { \
++ static unsigned char _c; \
++ if (!_c++) \
++ AuWarn(fmt, ##arg); \
++} while (0)
++
++#define AuErr1(fmt, arg...) do { \
++ static unsigned char _c; \
++ if (!_c++) \
++ AuErr(fmt, ##arg); \
++} while (0)
++
++#define AuIOErr1(fmt, arg...) do { \
++ static unsigned char _c; \
++ if (!_c++) \
++ AuIOErr(fmt, ##arg); \
++} while (0)
++
++#define AuUnsupportMsg "This operation is not supported." \
++ " Please report this application to aufs-users ML."
++#define AuUnsupport(fmt, args...) do { \
++ AuErr(AuUnsupportMsg "\n" fmt, ##args); \
++ dump_stack(); \
++} while (0)
++
++/* ---------------------------------------------------------------------- */
++
++struct au_sbinfo;
++#ifdef CONFIG_AUFS_DEBUG
++extern char *au_plevel;
++struct au_nhash;
++void au_dpri_whlist(struct au_nhash *whlist);
++struct au_vdir;
++void au_dpri_vdir(struct au_vdir *vdir);
++void au_dpri_inode(struct inode *inode);
++void au_dpri_dentry(struct dentry *dentry);
++void au_dpri_file(struct file *filp);
++void au_dpri_sb(struct super_block *sb);
++void au_dbg_sleep(int sec);
++void au_dbg_sleep_jiffy(int jiffy);
++
++#ifndef ATTR_OPEN
++#define ATTR_OPEN 0
++#endif
++#ifndef ATTR_KILL_PRIV
++#define ATTR_KILL_PRIV 0
++#endif
++void au_dbg_iattr(struct iattr *ia);
++int __init au_debug_init(void);
++void au_debug_sbinfo_init(struct au_sbinfo *sbinfo);
++#define AuDbgWhlist(w) do { \
++ LKTRTrace(#w "\n"); \
++ au_dpri_whlist(w); \
++} while (0)
++
++#define AuDbgVdir(v) do { \
++ LKTRTrace(#v "\n"); \
++ au_dpri_vdir(v); \
++} while (0)
++
++#define AuDbgInode(i) do { \
++ LKTRTrace(#i "\n"); \
++ au_dpri_inode(i); \
++} while (0)
++
++#define AuDbgDentry(d) do { \
++ LKTRTrace(#d "\n"); \
++ au_dpri_dentry(d); \
++} while (0)
++
++#define AuDbgFile(f) do { \
++ LKTRTrace(#f "\n"); \
++ au_dpri_file(f); \
++} while (0)
++
++#define AuDbgSb(sb) do { \
++ LKTRTrace(#sb "\n"); \
++ au_dpri_sb(sb); \
++} while (0)
++
++#define AuDbgSleep(sec) do { \
++ AuDbg("sleep %d sec\n", sec); \
++ au_dbg_sleep(sec); \
++} while (0)
++
++#define AuDbgSleepJiffy(jiffy) do { \
++ AuDbg("sleep %d jiffies\n", jiffy); \
++ au_dbg_sleep_jiffy(jiffy); \
++} while (0)
++
++#define AuDbgIAttr(ia) do { \
++ AuDbg("ia_valid 0x%x\n", (ia)->ia_valid); \
++ au_dbg_iattr(ia); \
++} while (0)
++#else
++static inline int au_debug_init(void)
++{
++ return 0;
++}
++static inline void au_debug_sbinfo_init(struct au_sbinfo *sbinfo)
++{
++ /* empty */
++}
++#define AuDbgWhlist(w) do {} while (0)
++#define AuDbgVdir(v) do {} while (0)
++#define AuDbgInode(i) do {} while (0)
++#define AuDbgDentry(d) do {} while (0)
++#define AuDbgFile(f) do {} while (0)
++#define AuDbgSb(sb) do {} while (0)
++#define AuDbgSleep(sec) do {} while (0)
++#define AuDbgSleepJiffy(jiffy) do {} while (0)
++#define AuDbgIAttr(ia) do {} while (0)
++#endif /* CONFIG_AUFS_DEBUG */
++
++#ifdef DbgUdbaRace
++#define AuDbgSleep_UdbaRace() AuDbgSleep(DbgUdbaRace)
++#else
++#define AuDbgSleep_UdbaRace() do {} while (0)
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_MAGIC_SYSRQ
++int __init au_sysrq_init(void);
++void au_sysrq_fin(void);
++
++#if defined(CONFIG_HW_CONSOLE) \
++ && LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++#define au_dbg_blocked() do { \
++ WARN_ON(1); \
++ handle_sysrq('w', vc_cons[fg_console].d->vc_tty); \
++} while (0)
++#else
++#define au_dbg_blocked() do {} while (0)
++#endif
++
++#else
++static inline int au_sysrq_init(void)
++{
++ return 0;
++}
++#define au_sysrq_fin() do {} while (0)
++#define au_dbg_blocked() do {} while (0)
++#endif /* CONFIG_AUFS_MAGIC_SYSRQ */
++
++enum {
++ AuDbgLock_SI_LOCKING,
++ AuDbgLock_SI_LOCKED,
++ AuDbgLock_DI_LOCKING,
++ AuDbgLock_DI_LOCKED,
++ AuDbgLock_II_LOCKING,
++ AuDbgLock_II_LOCKED,
++ AuDbgLock_Last
++};
++#ifdef CONFIG_AUFS_DEBUG_LOCK
++void au_dbg_locking_si_reg(struct super_block *sb, int flags);
++void au_dbg_locking_si_unreg(struct super_block *sb, int flags);
++void au_dbg_locked_si_reg(struct super_block *sb, int flags);
++void au_dbg_locked_si_unreg(struct super_block *sb, int flags);
++void au_dbg_locking_di_reg(struct dentry *d, int flags, unsigned int lsc);
++void au_dbg_locking_di_unreg(struct dentry *d, int flags);
++void au_dbg_locked_di_reg(struct dentry *d, int flags, unsigned int lsc);
++void au_dbg_locked_di_unreg(struct dentry *d, int flags);
++void au_dbg_locking_ii_reg(struct inode *i, int flags, unsigned int lsc);
++void au_dbg_locking_ii_unreg(struct inode *i, int flags);
++void au_dbg_locked_ii_reg(struct inode *i, int flags, unsigned int lsc);
++void au_dbg_locked_ii_unreg(struct inode *i, int flags);
++#else
++static inline
++void au_dbg_locking_si_reg(struct super_block *sb, int flags)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locking_si_unreg(struct super_block *sb, int flags)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locked_si_reg(struct super_block *sb, int flags)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locked_si_unreg(struct super_block *sb, int flags)
++{
++ /* empty */
++}
++
++static inline
++void au_dbg_locking_di_reg(struct dentry *d, int flags, unsigned int lsc)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locking_di_unreg(struct dentry *d, int flags)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locked_di_reg(struct dentry *d, int flags, unsigned int lsc)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locked_di_unreg(struct dentry *d, int flags)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locking_ii_reg(struct inode *i, int flags, unsigned int lsc)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locking_ii_unreg(struct inode *i, int flags)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locked_ii_reg(struct inode *i, int flags, unsigned int lsc)
++{
++ /* empty */
++}
++static inline
++void au_dbg_locked_ii_unreg(struct inode *i, int flags)
++{
++ /* empty */
++}
++#endif /* CONFIG_AUFS_DEBUG_LOCK */
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_DEBUG_H__ */
+diff --git a/fs/aufs/dentry.c b/fs/aufs/dentry.c
+new file mode 100644
+index 0000000..e1d992e
+--- /dev/null
++++ b/fs/aufs/dentry.c
+@@ -0,0 +1,960 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * lookup and dentry operations
++ *
++ * $Id: dentry.c,v 1.86 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * au_lkup_one() is a generic abstract entry function which calls
++ * lookup_one_len() or __lookup_hash() finally. it is some condisions that makes
++ * lookup complicated, which are nfs branch, open-intent and dlgt mode.
++ */
++
++#if defined(CONFIG_AUFS_BR_NFS) || defined(CONFIG_AUFS_DLGT)
++/* cf. lookup_one_len() in linux/fs/namei.c */
++struct dentry *au_lkup_one(const char *name, struct dentry *parent, int len,
++ struct au_ndx *ndx)
++{
++ struct dentry *dentry;
++
++ LKTRTrace("%.*s/%.*s, ndx{%d, 0x%x}\n",
++ AuDLNPair(parent), len, name, !!ndx->nfsmnt, ndx->flags);
++
++ ndx->nd_file = NULL;
++ if (!ndx->nfsmnt)
++ dentry = au_lkup_one_dlgt(name, parent, len, ndx->flags);
++ else
++ dentry = au_lkup_hash(name, parent, len, ndx);
++
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++#endif /* CONFIG_AUFS_BR_NFS || CONFIG_AUFS_DLGT */
++
++struct au_lkup_one_args {
++ struct dentry **errp;
++ const char *name;
++ struct dentry *parent;
++ int len;
++ struct au_ndx *ndx;
++};
++
++static void au_call_lkup_one(void *args)
++{
++ struct au_lkup_one_args *a = args;
++ *a->errp = au_lkup_one(a->name, a->parent, a->len, a->ndx);
++}
++
++#define AuLkup_ALLOW_NEG 1
++#define AuLkup_DLGT (1 << 1)
++#define AuLkup_DIRPERM1 (1 << 2)
++#define au_ftest_lkup(flags, name) ((flags) & AuLkup_##name)
++#define au_fset_lkup(flags, name) { (flags) |= AuLkup_##name; }
++#define au_fclr_lkup(flags, name) { (flags) &= ~AuLkup_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef AuLkup_DLGT
++#define AuLkup_DLGT 0
++#undef AuLkup_DIRPERM1
++#define AuLkup_DIRPERM1 0
++#endif
++
++struct au_do_lookup_args {
++ unsigned int flags;
++ mode_t type;
++ struct nameidata *nd;
++};
++
++/*
++ * returns positive/negative dentry, NULL or an error.
++ * NULL means whiteout-ed or not-found.
++ */
++static /* noinline_for_stack */
++struct dentry *au_do_lookup(struct dentry *h_parent, struct dentry *dentry,
++ aufs_bindex_t bindex, struct qstr *wh_name,
++ struct au_do_lookup_args *args)
++{
++ struct dentry *h_dentry;
++ int err, wh_found, opq;
++ unsigned char wh_able;
++ struct inode *h_dir, *h_inode, *inode;
++ struct qstr *name;
++ struct super_block *sb;
++ unsigned int nd_flags;
++ struct au_ndx ndx = {
++ .flags = 0,
++ .nd = args->nd
++ };
++ const int allow_neg = au_ftest_lkup(args->flags, ALLOW_NEG);
++
++ LKTRTrace("%.*s/%.*s, b%d, {flags 0x%x, type 0%o, nd %d}\n",
++ AuDLNPair(h_parent), AuDLNPair(dentry), bindex,
++ args->flags, args->type, !!args->nd);
++ if (args->nd)
++ LKTRTrace("nd{0x%x}\n", args->nd->flags);
++ AuDebugOn(IS_ROOT(dentry));
++ h_dir = h_parent->d_inode;
++
++ nd_flags = 0;
++ wh_found = 0;
++ sb = dentry->d_sb;
++ ndx.nfsmnt = au_nfsmnt(sb, bindex);
++ if (au_ftest_lkup(args->flags, DLGT))
++ au_fset_ndx(ndx.flags, DLGT);
++ if (au_ftest_lkup(args->flags, DIRPERM1))
++ au_fset_ndx(ndx.flags, DIRPERM1);
++ LKTRTrace("nfsmnt %p\n", ndx.nfsmnt);
++ ndx.br = au_sbr(sb, bindex);
++ wh_able = !!au_br_whable(ndx.br->br_perm);
++ name = &dentry->d_name;
++ if (wh_able)
++ wh_found = au_test_robr_wh(name, h_parent, wh_name,
++ /*try_sio*/0, &ndx);
++ h_dentry = ERR_PTR(wh_found);
++ if (!wh_found)
++ goto real_lookup;
++ if (unlikely(wh_found < 0))
++ goto out;
++
++ /* We found a whiteout */
++ /* au_set_dbend(dentry, bindex); */
++ au_set_dbwh(dentry, bindex);
++ if (!allow_neg)
++ return NULL; /* success */
++ if (ndx.nd
++ && au_test_nfs(h_parent->d_sb)
++ && (ndx.nd->flags & LOOKUP_CREATE)) {
++ nd_flags = ndx.nd->flags;
++ ndx.nd->flags &= ~(LOOKUP_OPEN | LOOKUP_CREATE);
++ }
++
++ real_lookup:
++ /* do not superio. */
++ h_dentry = au_lkup_one(name->name, h_parent, name->len, &ndx);
++ if (IS_ERR(h_dentry))
++ goto out;
++ AuDebugOn(d_unhashed(h_dentry));
++ h_inode = h_dentry->d_inode;
++ if (!h_inode) {
++ if (!allow_neg)
++ goto out_neg;
++ } else if (wh_found
++ || (args->type && args->type != (h_inode->i_mode & S_IFMT)))
++ goto out_neg;
++
++ if (au_dbend(dentry) <= bindex)
++ au_set_dbend(dentry, bindex);
++ if (au_dbstart(dentry) < 0 || bindex < au_dbstart(dentry))
++ au_set_dbstart(dentry, bindex);
++ au_set_h_dptr(dentry, bindex, h_dentry);
++
++ err = au_br_nfs_h_intent(ndx.nd_file, dentry, bindex, args->nd);
++ if (unlikely(err)) {
++ h_dentry = ERR_PTR(err);
++ goto out;
++ }
++
++ inode = dentry->d_inode;
++ if (!h_inode || !S_ISDIR(h_inode->i_mode) || !wh_able
++ || (inode && !S_ISDIR(inode->i_mode)))
++ goto out; /* success */
++
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ opq = au_diropq_test(h_dentry, &ndx);
++ vfsub_i_unlock(h_inode);
++ if (opq > 0)
++ au_set_dbdiropq(dentry, bindex);
++ else if (unlikely(opq < 0)) {
++ au_set_h_dptr(dentry, bindex, NULL);
++ h_dentry = ERR_PTR(opq);
++ }
++ goto out;
++
++ out_neg:
++ dput(h_dentry);
++ h_dentry = NULL;
++ out:
++ if (nd_flags)
++ ndx.nd->flags |= (nd_flags & (LOOKUP_OPEN | LOOKUP_CREATE));
++ AuTraceErrPtr(h_dentry);
++ return h_dentry;
++}
++
++/*
++ * returns the number of hidden positive dentries,
++ * otherwise an error.
++ * can be called at unlinking with @type is zero.
++ */
++int au_lkup_dentry(struct dentry *dentry, aufs_bindex_t bstart, mode_t type,
++ struct nameidata *nd)
++{
++ int npositive, err;
++ unsigned int mnt_flags;
++ aufs_bindex_t bindex, btail, bdiropq;
++ unsigned char isdir;
++ struct qstr whname;
++ struct au_do_lookup_args args = {
++ .type = type,
++ .nd = nd
++ };
++ const struct qstr *name = &dentry->d_name;
++ struct dentry *parent;
++ struct super_block *sb;
++ struct inode *inode;
++
++ LKTRTrace("%.*s, b%d, type 0%o\n", AuLNPair(name), bstart, type);
++ AuDebugOn(bstart < 0 || IS_ROOT(dentry));
++
++ /* dir may not be locked */
++ parent = dget_parent(dentry);
++
++ err = au_test_robr_shwh(dentry->d_sb, name);
++ if (unlikely(err))
++ goto out;
++
++ err = au_wh_name_alloc(name->name, name->len, &whname);
++ if (unlikely(err))
++ goto out;
++
++ sb = dentry->d_sb;
++ mnt_flags = au_mntflags(sb);
++ inode = dentry->d_inode;
++ isdir = !!(inode && S_ISDIR(inode->i_mode));
++ args.flags = 0;
++ if (au_test_dlgt(mnt_flags))
++ au_fset_lkup(args.flags, DLGT);
++ if (au_test_dirperm1(mnt_flags))
++ au_fset_lkup(args.flags, DIRPERM1);
++ if (!type)
++ au_fset_lkup(args.flags, ALLOW_NEG);
++ npositive = 0;
++ btail = au_dbtaildir(parent);
++ for (bindex = bstart; bindex <= btail; bindex++) {
++ struct dentry *h_parent, *h_dentry;
++ struct inode *h_inode, *h_dir;
++
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (h_dentry) {
++ if (h_dentry->d_inode)
++ npositive++;
++ if (type != S_IFDIR)
++ break;
++ continue;
++ }
++ h_parent = au_h_dptr(parent, bindex);
++ if (!h_parent)
++ continue;
++ h_dir = h_parent->d_inode;
++ if (!h_dir || !S_ISDIR(h_dir->i_mode))
++ continue;
++
++ vfsub_i_lock_nested(h_dir, AuLsc_I_PARENT);
++ h_dentry = au_do_lookup(h_parent, dentry, bindex, &whname,
++ &args);
++ vfsub_i_unlock(h_dir);
++ err = PTR_ERR(h_dentry);
++ if (IS_ERR(h_dentry))
++ goto out_wh;
++ au_fclr_lkup(args.flags, ALLOW_NEG);
++
++ if (au_dbwh(dentry) >= 0)
++ break;
++ if (!h_dentry)
++ continue;
++ h_inode = h_dentry->d_inode;
++ if (!h_inode)
++ continue;
++ npositive++;
++ if (!args.type)
++ args.type = h_inode->i_mode & S_IFMT;
++ if (args.type != S_IFDIR)
++ break;
++ else if (isdir) {
++ /* the type of lowers may be different */
++ bdiropq = au_dbdiropq(dentry);
++ if (bdiropq >= 0 && bdiropq <= bindex)
++ break;
++ }
++ }
++
++ if (npositive) {
++ LKTRLabel(positive);
++ au_update_dbstart(dentry);
++ }
++ err = npositive;
++ if (!au_opt_test(mnt_flags, UDBA_NONE) && au_dbstart(dentry) < 0)
++ /* both of real entry and whiteout found */
++ err = -EIO;
++
++ out_wh:
++ au_wh_name_free(&whname);
++ out:
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++struct dentry *au_sio_lkup_one(const char *name, struct dentry *parent, int len,
++ struct au_ndx *ndx)
++{
++ struct dentry *dentry;
++ int wkq_err;
++
++ LKTRTrace("%.*s/%.*s\n", AuDLNPair(parent), len, name);
++
++ if (!au_test_h_perm_sio(parent->d_inode, MAY_EXEC,
++ au_ftest_ndx(ndx->flags, DLGT)))
++ dentry = au_lkup_one(name, parent, len, ndx);
++ else {
++ /* todo: ugly? */
++ unsigned int flags = ndx->flags;
++ struct au_lkup_one_args args = {
++ .errp = &dentry,
++ .name = name,
++ .parent = parent,
++ .len = len,
++ .ndx = ndx
++ };
++
++ au_fclr_ndx(ndx->flags, DLGT);
++ au_fclr_ndx(ndx->flags, DIRPERM1);
++ wkq_err = au_wkq_wait(au_call_lkup_one, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ dentry = ERR_PTR(wkq_err);
++ ndx->flags = flags;
++ }
++
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++
++/*
++ * lookup @dentry on @bindex which should be negative.
++ */
++int au_lkup_neg(struct dentry *dentry, aufs_bindex_t bindex)
++{
++ int err;
++ struct dentry *parent, *h_parent, *h_dentry;
++ struct inode *h_dir;
++ struct au_ndx ndx = {
++ .flags = 0,
++ .nd = NULL,
++ /* .br = NULL */
++ };
++ struct super_block *sb;
++ unsigned int mnt_flags;
++
++ LKTRTrace("%.*s, b%d\n", AuDLNPair(dentry), bindex);
++ /* dir may not be locked */
++ parent = dget_parent(dentry);
++ AuDebugOn(!parent || !parent->d_inode
++ || !S_ISDIR(parent->d_inode->i_mode));
++ h_parent = au_h_dptr(parent, bindex);
++ AuDebugOn(!h_parent);
++ h_dir = h_parent->d_inode;
++ AuDebugOn(!h_dir || !S_ISDIR(h_dir->i_mode));
++
++ sb = dentry->d_sb;
++ mnt_flags = au_mntflags(sb);
++ ndx.nfsmnt = au_nfsmnt(sb, bindex);
++ if (au_test_dlgt(mnt_flags))
++ au_fset_ndx(ndx.flags, DLGT);
++ if (au_test_dirperm1(mnt_flags))
++ au_fset_ndx(ndx.flags, DIRPERM1);
++ h_dentry = au_sio_lkup_one(dentry->d_name.name, h_parent,
++ dentry->d_name.len, &ndx);
++ err = PTR_ERR(h_dentry);
++ if (IS_ERR(h_dentry))
++ goto out;
++ if (unlikely(h_dentry->d_inode)) {
++ err = -EIO;
++ AuIOErr("b%d %.*s should be negative.\n",
++ bindex, AuDLNPair(h_dentry));
++ dput(h_dentry);
++ goto out;
++ }
++
++ if (bindex < au_dbstart(dentry))
++ au_set_dbstart(dentry, bindex);
++ if (au_dbend(dentry) < bindex)
++ au_set_dbend(dentry, bindex);
++ au_set_h_dptr(dentry, bindex, h_dentry);
++ err = 0;
++
++ out:
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * returns the number of found hidden positive dentries,
++ * otherwise an error.
++ */
++int au_refresh_hdentry(struct dentry *dentry, mode_t type)
++{
++ int npositive, new_sz;
++ struct au_dinfo *dinfo;
++ struct super_block *sb;
++ struct dentry *parent;
++ aufs_bindex_t bindex, parent_bend, parent_bstart, bwh, bdiropq, bend;
++ struct au_hdentry *p;
++ au_gen_t sgen;
++
++ LKTRTrace("%.*s, type 0%o\n", AuDLNPair(dentry), type);
++ DiMustWriteLock(dentry);
++ sb = dentry->d_sb;
++ AuDebugOn(IS_ROOT(dentry));
++ sgen = au_sigen(sb);
++ parent = dget_parent(dentry);
++ AuDebugOn(au_digen(parent) != sgen
++ || au_iigen(parent->d_inode) != sgen);
++
++ npositive = -ENOMEM;
++ new_sz = sizeof(*dinfo->di_hdentry) * (au_sbend(sb) + 1);
++ dinfo = au_di(dentry);
++ p = au_kzrealloc(dinfo->di_hdentry, sizeof(*p) * (dinfo->di_bend + 1),
++ new_sz, GFP_NOFS);
++ if (unlikely(!p))
++ goto out;
++ dinfo->di_hdentry = p;
++
++ bend = dinfo->di_bend;
++ bwh = dinfo->di_bwh;
++ bdiropq = dinfo->di_bdiropq;
++ p += dinfo->di_bstart;
++ for (bindex = dinfo->di_bstart; bindex <= bend; bindex++, p++) {
++ struct dentry *hd, *hdp;
++ struct au_hdentry tmp, *q;
++ aufs_bindex_t new_bindex;
++
++ hd = p->hd_dentry;
++ if (!hd)
++ continue;
++ hdp = dget_parent(hd);
++ if (hdp == au_h_dptr(parent, bindex)) {
++ dput(hdp);
++ continue;
++ }
++
++ new_bindex = au_find_dbindex(parent, hdp);
++ dput(hdp);
++ AuDebugOn(new_bindex == bindex);
++ if (dinfo->di_bwh == bindex)
++ bwh = new_bindex;
++ if (dinfo->di_bdiropq == bindex)
++ bdiropq = new_bindex;
++ /* todo: test more? */
++ if (new_bindex < 0) {
++ au_hdput(p, /*do_free*/0);
++ p->hd_dentry = NULL;
++ continue;
++ }
++ /* swap two hidden dentries, and loop again */
++ q = dinfo->di_hdentry + new_bindex;
++ tmp = *q;
++ *q = *p;
++ *p = tmp;
++ if (tmp.hd_dentry) {
++ bindex--;
++ p--;
++ }
++ }
++
++ /* todo: test more? */
++ dinfo->di_bwh = -1;
++ if (bwh >= 0 && bwh <= au_sbend(sb) && au_sbr_whable(sb, bwh))
++ dinfo->di_bwh = bwh;
++ dinfo->di_bdiropq = -1;
++ if (bdiropq >= 0
++ && bdiropq <= au_sbend(sb)
++ && au_sbr_whable(sb, bdiropq))
++ dinfo->di_bdiropq = bdiropq;
++ parent_bend = au_dbend(parent);
++ p = dinfo->di_hdentry;
++ for (bindex = 0; bindex <= parent_bend; bindex++, p++)
++ if (p->hd_dentry) {
++ dinfo->di_bstart = bindex;
++ break;
++ }
++ p = dinfo->di_hdentry + parent_bend;
++ for (bindex = parent_bend; bindex >= 0; bindex--, p--)
++ if (p->hd_dentry) {
++ dinfo->di_bend = bindex;
++ break;
++ }
++
++ npositive = 0;
++ parent_bstart = au_dbstart(parent);
++ if (type != S_IFDIR && dinfo->di_bstart == parent_bstart)
++ goto out_dgen; /* success */
++
++ npositive = au_lkup_dentry(dentry, parent_bstart, type, /*nd*/NULL);
++ if (npositive < 0)
++ goto out;
++ if (dinfo->di_bwh >= 0 && dinfo->di_bwh <= dinfo->di_bstart)
++ d_drop(dentry);
++
++ out_dgen:
++ au_update_digen(dentry);
++ out:
++ dput(parent);
++ AuTraceErr(npositive);
++ return npositive;
++}
++
++static int au_lock_nd(struct dentry *dentry, struct nameidata *nd)
++{
++ int locked = 0;
++ if (nd && dentry != nd->dentry) {
++ di_read_lock_parent(nd->dentry, 0);
++ locked = 1;
++ }
++ return locked;
++}
++
++static void au_unlock_nd(int locked, struct nameidata *nd)
++{
++ if (locked)
++ di_read_unlock(nd->dentry, 0);
++}
++
++/* #define TestingFuse */
++static noinline_for_stack
++int au_do_h_d_reval(struct dentry *dentry, aufs_bindex_t bindex,
++ struct nameidata *nd, struct dentry *h_dentry)
++{
++ int err, valid, e;
++ int (*reval)(struct dentry *, struct nameidata *);
++ struct super_block *sb;
++ struct nameidata fake_nd, *p;
++
++ LKTRTrace("%.*s, b%d, nd %d\n", AuDLNPair(dentry), bindex, !!nd);
++
++ err = 0;
++ reval = NULL;
++ if (h_dentry->d_op)
++ reval = h_dentry->d_op->d_revalidate;
++ if (!reval)
++ goto out;
++
++ sb = dentry->d_sb;
++ if (nd) {
++ memcpy(&fake_nd, nd, sizeof(*nd));
++ err = au_fake_intent(&fake_nd, au_sbr(sb, bindex));
++ if (unlikely(err)) {
++ err = -EINVAL;
++ goto out;
++ }
++ }
++ p = au_fake_dm(&fake_nd, nd, sb, bindex);
++ AuDebugOn(IS_ERR(p));
++ AuDebugOn(nd && p != &fake_nd);
++ LKTRTrace("b%d\n", bindex);
++
++ /* it may return tri-state */
++ valid = reval(h_dentry, p);
++ if (unlikely(valid < 0))
++ err = valid;
++ else if (!valid)
++ err = -EINVAL;
++ else
++ AuDebugOn(err);
++
++ if (p) {
++ AuDebugOn(!nd);
++ e = au_hin_after_reval(p, dentry, bindex, nd->intent.open.file);
++#ifndef TestingFuse
++ au_update_fuse_h_inode(p->mnt, h_dentry); /*ignore*/
++#endif
++ if (unlikely(e && !err))
++ err = e;
++ }
++#ifndef TestingFuse
++ else
++ au_update_fuse_h_inode(NULL, h_dentry); /*ignore*/
++#endif
++ au_fake_dm_release(p);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static noinline_for_stack
++int h_d_revalidate(struct dentry *dentry, struct inode *inode,
++ struct nameidata *nd, int do_udba)
++{
++ int err;
++ aufs_bindex_t bindex, btail, bstart, ibs, ibe;
++ unsigned char plus, locked, unhashed, is_root, h_plus;
++ struct super_block *sb;
++ struct inode *first, *h_inode, *h_cached_inode;
++ umode_t mode, h_mode;
++ struct dentry *h_dentry;
++ struct qstr *name;
++
++ LKTRTrace("%.*s, nd %d\n", AuDLNPair(dentry), !!nd);
++ AuDebugOn(inode && au_digen(dentry) != au_iigen(inode));
++
++ err = 0;
++ sb = dentry->d_sb;
++ plus = 0;
++ mode = 0;
++ first = NULL;
++ ibs = -1;
++ ibe = -1;
++ unhashed = !!d_unhashed(dentry);
++ is_root = !!IS_ROOT(dentry);
++ name = &dentry->d_name;
++
++ /*
++ * Theoretically, REVAL test should be unnecessary in case of INOTIFY.
++ * But inotify doesn't fire some necessary events,
++ * IN_ATTRIB for atime/nlink/pageio
++ * IN_DELETE for NFS dentry
++ * Let's do REVAL test too.
++ */
++ if (do_udba && inode) {
++ mode = (inode->i_mode & S_IFMT);
++ plus = (inode->i_nlink > 0);
++ first = au_h_iptr(inode, au_ibstart(inode));
++ ibs = au_ibstart(inode);
++ ibe = au_ibend(inode);
++ }
++
++ bstart = au_dbstart(dentry);
++ btail = bstart;
++ if (inode && S_ISDIR(inode->i_mode))
++ btail = au_dbtaildir(dentry);
++ locked = !!au_lock_nd(dentry, nd);
++ for (bindex = bstart; bindex <= btail; bindex++) {
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!h_dentry)
++ continue;
++
++ LKTRTrace("b%d, %.*s\n", bindex, AuDLNPair(h_dentry));
++#ifdef TestingFuse
++ /* force re-lookup for fuse, in order to update attributes */
++ if (au_test_fuse(h_dentry->d_sb))
++ goto err;
++#endif
++
++ if (unlikely(do_udba
++ && !is_root
++ && (unhashed != !!d_unhashed(h_dentry)
++ || name->len != h_dentry->d_name.len
++ || memcmp(name->name, h_dentry->d_name.name,
++ name->len)
++ ))) {
++ LKTRTrace("unhash 0x%x 0x%x, %.*s %.*s\n",
++ unhashed, d_unhashed(h_dentry),
++ AuDLNPair(dentry), AuDLNPair(h_dentry));
++ goto err;
++ }
++
++ err = au_do_h_d_reval(dentry, bindex, nd, h_dentry);
++ if (unlikely(err))
++ /* do not goto err, to keep the errno */
++ break;
++
++ /* todo: plink too? */
++ if (!do_udba)
++ continue;
++
++ /* UDBA tests */
++ h_inode = h_dentry->d_inode;
++ if (unlikely(!!inode != !!h_inode))
++ goto err;
++
++ h_plus = plus;
++ h_mode = mode;
++ h_cached_inode = h_inode;
++ if (h_inode) {
++ h_mode = (h_inode->i_mode & S_IFMT);
++ h_plus = (h_inode->i_nlink > 0);
++ }
++ if (inode && ibs <= bindex && bindex <= ibe)
++ h_cached_inode = au_h_iptr(inode, bindex);
++
++ LKTRTrace("{%d, 0%o, %p}, h{%d, 0%o, %p}\n",
++ plus, mode, h_cached_inode,
++ h_plus, h_mode, h_inode);
++ if (unlikely(plus != h_plus
++ || mode != h_mode
++ || h_cached_inode != h_inode))
++ goto err;
++ continue;
++
++ err:
++ err = -EINVAL;
++ break;
++ }
++ au_unlock_nd(locked, nd);
++
++ /*
++ * judging by timestamps is meaningless since some filesystem uses
++ * CURRENT_TIME_SEC instead of CURRENT_TIME.
++ */
++ /*
++ * NFS may stop IN_DELETE because of DCACHE_NFSFS_RENAMED.
++ */
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int simple_reval_dpath(struct dentry *dentry, au_gen_t sgen)
++{
++ int err;
++ mode_t type;
++ struct dentry *parent;
++ struct inode *inode;
++
++ LKTRTrace("%.*s, sgen %d\n", AuDLNPair(dentry), sgen);
++ SiMustAnyLock(dentry->d_sb);
++ DiMustWriteLock(dentry);
++ inode = dentry->d_inode;
++ AuDebugOn(!inode);
++
++ if (au_digen(dentry) == sgen && au_iigen(inode) == sgen)
++ return 0;
++
++ parent = dget_parent(dentry);
++ di_read_lock_parent(parent, AuLock_IR);
++ AuDebugOn(au_digen(parent) != sgen
++ || au_iigen(parent->d_inode) != sgen);
++#ifdef CONFIG_AUFS_DEBUG
++ {
++ int i, j;
++ struct au_dcsub_pages dpages;
++ struct au_dpage *dpage;
++ struct dentry **dentries;
++
++ err = au_dpages_init(&dpages, GFP_NOFS);
++ AuDebugOn(err);
++ err = au_dcsub_pages_rev(&dpages, parent, /*do_include*/1, NULL,
++ NULL);
++ AuDebugOn(err);
++ for (i = dpages.ndpage - 1; !err && i >= 0; i--) {
++ dpage = dpages.dpages + i;
++ dentries = dpage->dentries;
++ for (j = dpage->ndentry - 1; !err && j >= 0; j--)
++ AuDebugOn(au_digen(dentries[j]) != sgen);
++ }
++ au_dpages_free(&dpages);
++ }
++#endif
++ type = (inode->i_mode & S_IFMT);
++ /* returns a number of positive dentries */
++ err = au_refresh_hdentry(dentry, type);
++ if (err >= 0)
++ err = au_refresh_hinode(inode, dentry);
++ di_read_unlock(parent, AuLock_IR);
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++int au_reval_dpath(struct dentry *dentry, au_gen_t sgen)
++{
++ int err;
++ struct dentry *d, *parent;
++ struct inode *inode;
++
++ LKTRTrace("%.*s, sgen %d\n", AuDLNPair(dentry), sgen);
++ AuDebugOn(!dentry->d_inode);
++ DiMustWriteLock(dentry);
++
++ if (!au_ftest_si(au_sbi(dentry->d_sb), FAILED_REFRESH_DIRS))
++ return simple_reval_dpath(dentry, sgen);
++
++ /* slow loop, keep it simple and stupid */
++ /* cf: au_cpup_dirs() */
++ err = 0;
++ parent = NULL;
++ while (au_digen(dentry) != sgen || au_iigen(dentry->d_inode) != sgen) {
++ d = dentry;
++ while (1) {
++ dput(parent);
++ parent = dget_parent(d);
++ if (au_digen(parent) == sgen
++ && au_iigen(parent->d_inode) == sgen)
++ break;
++ d = parent;
++ }
++
++ inode = d->d_inode;
++ if (d != dentry)
++ di_write_lock_child(d);
++
++ /* someone might update our dentry while we were sleeping */
++ if (au_digen(d) != sgen || au_iigen(d->d_inode) != sgen) {
++ di_read_lock_parent(parent, AuLock_IR);
++ /* returns a number of positive dentries */
++ err = au_refresh_hdentry(d, inode->i_mode & S_IFMT);
++ if (err >= 0)
++ err = au_refresh_hinode(inode, d);
++ di_read_unlock(parent, AuLock_IR);
++ }
++
++ if (d != dentry)
++ di_write_unlock(d);
++ dput(parent);
++ if (unlikely(err))
++ break;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * THIS IS A BOOLEAN FUNCTION: returns 1 if valid, 0 otherwise.
++ * nfsd passes NULL as nameidata.
++ */
++static int aufs_d_revalidate(struct dentry *dentry, struct nameidata *nd)
++{
++ int valid, err;
++ au_gen_t sgen;
++ unsigned char do_udba;
++ struct nameidata tmp_nd, *ndp;
++ struct super_block *sb;
++ struct inode *inode;
++
++ LKTRTrace("dentry %.*s\n", AuDLNPair(dentry));
++ if (nd && nd->dentry)
++ LKTRTrace("nd{%.*s, 0x%x}\n",
++ AuDLNPair(nd->dentry), nd->flags);
++ /*
++ * dir case: AuDebugOn(dentry->d_parent != nd->dentry);
++ * remove failure case:AuDebugOn(!IS_ROOT(dentry)
++ * && d_unhashed(dentry));
++ */
++ AuDebugOn(!dentry->d_fsdata);
++
++ err = -EINVAL;
++ sb = dentry->d_sb;
++ aufs_read_lock(dentry, AuLock_FLUSH | AuLock_DW);
++ inode = dentry->d_inode;
++ sgen = au_sigen(sb);
++ if (au_digen(dentry) != sgen) {
++ AuDebugOn(IS_ROOT(dentry));
++#ifdef ForceInotify
++ AuDbg("UDBA or digen, %.*s\n", AuDLNPair(dentry));
++#endif
++ if (inode)
++ err = au_reval_dpath(dentry, sgen);
++ if (unlikely(err))
++ goto out_dgrade;
++ AuDebugOn(au_digen(dentry) != sgen);
++ }
++ if (inode && au_iigen(inode) != sgen) {
++ AuDebugOn(IS_ROOT(dentry));
++#ifdef ForceInotify
++ AuDbg("UDBA or survived, %.*s\n", AuDLNPair(dentry));
++#endif
++ err = au_refresh_hinode(inode, dentry);
++ if (unlikely(err))
++ goto out_dgrade;
++ AuDebugOn(au_iigen(inode) != sgen);
++ }
++ di_downgrade_lock(dentry, AuLock_IR);
++
++#if 0 /* todo: support it? */
++ /* parent dir i_nlink is not updated in the case of setattr */
++ if (S_ISDIR(inode->i_mode)) {
++ vfsub_i_lock(inode);
++ ii_write_lock(inode);
++ au_cpup_attr_nlink(inode);
++ ii_write_unlock(inode);
++ vfsub_i_unlock(inode);
++ }
++#endif
++
++ AuDebugOn(au_digen(dentry) != sgen);
++ AuDebugOn(inode && au_iigen(inode) != sgen);
++ err = -EINVAL;
++ do_udba = !au_opt_test(au_mntflags(sb), UDBA_NONE);
++ if (do_udba && inode) {
++ aufs_bindex_t bstart = au_ibstart(inode);
++ if (bstart >= 0
++ && au_test_higen(inode, au_h_iptr(inode, bstart)))
++ goto out;
++ }
++ ndp = au_dup_nd(au_sbi(sb), &tmp_nd, nd);
++ err = h_d_revalidate(dentry, inode, ndp, do_udba);
++ if (unlikely(!err && do_udba && au_dbstart(dentry) < 0))
++ /* both of real entry and whiteout found */
++ err = -EIO;
++ goto out;
++
++ out_dgrade:
++ di_downgrade_lock(dentry, AuLock_IR);
++ out:
++ au_store_fmode_exec(nd, inode);
++ aufs_read_unlock(dentry, AuLock_IR);
++ AuTraceErr(err);
++ valid = !err;
++ if (!valid)
++ LKTRTrace("%.*s invalid\n", AuDLNPair(dentry));
++ return valid;
++}
++
++static void aufs_d_release(struct dentry *dentry)
++{
++ struct au_dinfo *dinfo;
++ aufs_bindex_t bend, bindex;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ AuDebugOn(!d_unhashed(dentry));
++
++ dinfo = dentry->d_fsdata;
++ if (!dinfo)
++ return;
++
++ /* dentry may not be revalidated */
++ bindex = dinfo->di_bstart;
++ if (bindex >= 0) {
++ struct au_hdentry *p;
++ bend = dinfo->di_bend;
++ AuDebugOn(bend < bindex);
++ p = dinfo->di_hdentry + bindex;
++ while (bindex++ <= bend) {
++ if (p->hd_dentry)
++ au_hdput(p, /*do_free*/1);
++ p++;
++ }
++ }
++ kfree(dinfo->di_hdentry);
++ au_rwsem_destroy(&dinfo->di_rwsem);
++ au_cache_free_dinfo(dinfo);
++ au_hin_di_reinit(dentry);
++}
++
++struct dentry_operations aufs_dop = {
++ .d_revalidate = aufs_d_revalidate,
++ .d_release = aufs_d_release,
++ /* never use d_delete, especially in case of nfs server */
++};
+diff --git a/fs/aufs/dentry.h b/fs/aufs/dentry.h
+new file mode 100644
+index 0000000..3a8092f
+--- /dev/null
++++ b/fs/aufs/dentry.h
+@@ -0,0 +1,398 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * lookup and dentry operations
++ *
++ * $Id: dentry.h,v 1.49 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_DENTRY_H__
++#define __AUFS_DENTRY_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/namei.h>
++#include <linux/version.h>
++#include <linux/aufs_type.h>
++#include "misc.h"
++#include "vfsub.h"
++
++/* nameidata open_intent */
++enum {
++ AuIntent_AUFS,
++ AuIntent_BRANCH,
++ AuIntent_Last
++};
++
++struct au_hdintent {
++ struct list_head hdi_list;
++ struct file *hdi_file[AuIntent_Last];
++};
++
++struct au_hdentry {
++ struct dentry *hd_dentry;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) \
++ && defined(CONFIG_AUFS_BR_NFS)
++ spinlock_t hd_lock; /* intest_list */
++ struct list_head *hd_intent_list;
++#endif
++};
++
++struct au_dinfo {
++ atomic_t di_generation;
++
++ struct au_rwsem di_rwsem;
++ aufs_bindex_t di_bstart, di_bend, di_bwh, di_bdiropq;
++ struct au_hdentry *di_hdentry;
++};
++
++/* nameidata extension flags */
++#define AuNdx_DLGT 1
++#define AuNdx_DIRPERM1 (1 << 1)
++#define au_ftest_ndx(flags, name) ((flags) & AuNdx_##name)
++#define au_fset_ndx(flags, name) { (flags) |= AuNdx_##name; }
++#define au_fclr_ndx(flags, name) { (flags) &= ~AuNdx_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef AuNdx_DLGT
++#define AuNdx_DLGT 0
++#undef AuNdx_DIRPERM1
++#define AuNdx_DIRPERM1 0
++#endif
++
++struct au_ndx {
++ struct vfsmount *nfsmnt;
++ unsigned int flags;
++ struct nameidata *nd;
++ struct au_branch *br;
++ struct file *nd_file;
++};
++
++/* ---------------------------------------------------------------------- */
++
++static inline void au_do_h_dentry_init(struct au_hdentry *hdentry)
++{
++ hdentry->hd_dentry = NULL;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) \
++ && defined(CONFIG_AUFS_BR_NFS)
++static inline void au_h_dentry_init(struct au_hdentry *hdentry)
++{
++ au_do_h_dentry_init(hdentry);
++ spin_lock_init(&hdentry->hd_lock);
++}
++
++static inline void au_h_dentry_init_all(struct au_hdentry *hdentry, int n)
++{
++ while (n--)
++ spin_lock_init(&hdentry[n].hd_lock);
++}
++
++/* br_nfs.c */
++struct file *au_h_intent(struct dentry *dentry, aufs_bindex_t bindex,
++ struct file *file);
++int au_br_nfs_h_intent(struct file *nd_file, struct dentry *dentry,
++ aufs_bindex_t bindex, struct nameidata *nd);
++void au_hintent_put(struct au_hdentry *hd, int do_free);
++int au_fake_intent(struct nameidata *nd, struct au_branch *br);
++int au_hin_after_reval(struct nameidata *nd, struct dentry *dentry,
++ aufs_bindex_t bindex, struct file *file);
++struct dentry *au_lkup_hash(const char *name, struct dentry *parent, int len,
++ struct au_ndx *ndx);
++#else
++
++static inline void au_h_dentry_init(struct au_hdentry *hdentry)
++{
++ au_do_h_dentry_init(hdentry);
++}
++
++static inline void au_h_dentry_init_all(struct au_hdentry *hdentry, int n)
++{
++ /* nothing */
++}
++
++static inline
++struct file *au_h_intent(struct dentry *dentry, aufs_bindex_t bindex,
++ struct file *file)
++{
++ /* return ERR_PTR(-ENOSYS); */
++ return NULL;
++}
++
++static inline
++int au_br_nfs_h_intent(struct file *nd_file, struct dentry *dentry,
++ aufs_bindex_t bindex, struct nameidata *nd)
++{
++ return 0;
++}
++
++static inline void au_hintent_put(struct au_hdentry *hd, int do_free)
++{
++ /* empty */
++}
++
++static inline int au_fake_intent(struct nameidata *nd, struct au_branch *br)
++{
++ return 0;
++}
++
++static inline
++int au_hin_after_reval(struct nameidata *nd, struct dentry *dentry,
++ aufs_bindex_t bindex, struct file *file)
++{
++ return 0;
++}
++
++#if defined(CONFIG_AUFS_BR_NFS) || defined(CONFIG_AUFS_DLGT)
++static inline
++struct dentry *au_lkup_hash(const char *name, struct dentry *parent, int len,
++ struct au_ndx *ndx)
++{
++ /* return ERR_PTR(-ENOSYS); */
++ return vfsub_lookup_one_len(name, parent, len);
++}
++#endif
++#endif /* >= 2.6.19 && CONFIG_AUFS_BR_NFS */
++
++#ifdef CONFIG_AUFS_DLGT
++/* dlgt.c */
++struct dentry *au_lkup_one_dlgt(const char *name, struct dentry *parent,
++ int len, unsigned int flags);
++#elif defined(CONFIG_AUFS_BR_NFS)
++/* regardelss kernel version */
++static inline
++struct dentry *au_lkup_one_dlgt(const char *name, struct dentry *parent,
++ int len, unsigned int flags)
++{
++ return vfsub_lookup_one_len(name, parent, len);
++}
++#endif
++
++/* dentry.c */
++extern struct dentry_operations aufs_dop;
++#if defined(CONFIG_AUFS_BR_NFS) || defined(CONFIG_AUFS_DLGT)
++struct dentry *au_lkup_one(const char *name, struct dentry *parent, int len,
++ struct au_ndx *ndx);
++#else
++static inline
++struct dentry *au_lkup_one(const char *name, struct dentry *parent, int len,
++ struct au_ndx *ndx)
++{
++ /* todo? ndx->nd_file = NULL; */
++ return vfsub_lookup_one_len(name, parent, len);
++}
++#endif
++struct dentry *au_sio_lkup_one(const char *name, struct dentry *parent, int len,
++ struct au_ndx *ndx);
++int au_lkup_dentry(struct dentry *dentry, aufs_bindex_t bstart, mode_t type,
++ struct nameidata *nd);
++int au_lkup_neg(struct dentry *dentry, aufs_bindex_t bindex);
++int au_refresh_hdentry(struct dentry *dentry, mode_t type);
++int au_reval_dpath(struct dentry *dentry, au_gen_t sgen);
++
++/* dinfo.c */
++int au_alloc_dinfo(struct dentry *dentry);
++struct au_dinfo *au_di(struct dentry *dentry);
++
++void di_read_lock(struct dentry *d, int flags, unsigned int lsc);
++void di_read_unlock(struct dentry *d, int flags);
++void di_downgrade_lock(struct dentry *d, int flags);
++void di_write_lock(struct dentry *d, unsigned int lsc);
++void di_write_unlock(struct dentry *d);
++void di_write_lock2_child(struct dentry *d1, struct dentry *d2, int isdir);
++void di_write_lock2_parent(struct dentry *d1, struct dentry *d2, int isdir);
++void di_write_unlock2(struct dentry *d1, struct dentry *d2);
++
++struct dentry *au_h_dptr(struct dentry *dentry, aufs_bindex_t bindex);
++
++aufs_bindex_t au_dbtail(struct dentry *dentry);
++aufs_bindex_t au_dbtaildir(struct dentry *dentry);
++#if 0 /* reserved for future use */
++aufs_bindex_t au_dbtail_generic(struct dentry *dentry);
++#endif
++
++void au_set_dbdiropq(struct dentry *dentry, aufs_bindex_t bindex);
++void au_set_h_dptr(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_dentry);
++
++void au_update_dbrange(struct dentry *dentry, int do_put_zero);
++void au_update_dbstart(struct dentry *dentry);
++void au_update_dbend(struct dentry *dentry);
++int au_find_dbindex(struct dentry *dentry, struct dentry *h_dentry);
++
++/* ---------------------------------------------------------------------- */
++
++/* todo: memory barrier? */
++static inline au_gen_t au_digen(struct dentry *d)
++{
++ return atomic_read(&au_di(d)->di_generation);
++}
++
++#ifdef CONFIG_AUFS_HINOTIFY
++static inline au_gen_t au_digen_dec(struct dentry *d)
++{
++ return atomic_dec_return(&au_di(d)->di_generation);
++}
++
++static inline void au_hin_di_reinit(struct dentry *d)
++{
++ d->d_fsdata = NULL;
++}
++#else
++static inline void au_hin_di_reinit(struct dentry *d)
++{
++ /* empty */
++}
++#endif /* CONFIG_AUFS_HINOTIFY */
++
++/* ---------------------------------------------------------------------- */
++
++/* lock subclass for dinfo */
++enum {
++ AuLsc_DI_CHILD, /* child first */
++ AuLsc_DI_CHILD2, /* rename(2), link(2), and cpup at hinotify */
++ AuLsc_DI_CHILD3, /* copyup dirs */
++ AuLsc_DI_PARENT,
++ AuLsc_DI_PARENT2,
++ AuLsc_DI_PARENT3,
++ AuLsc_DI_PARENT4
++};
++
++/*
++ * di_read_lock_child, di_write_lock_child,
++ * di_read_lock_child2, di_write_lock_child2,
++ * di_read_lock_child3, di_write_lock_child3,
++ * di_read_lock_parent, di_write_lock_parent,
++ * di_read_lock_parent2, di_write_lock_parent2,
++ * di_read_lock_parent3, di_write_lock_parent3,
++ * di_read_lock_parent4, di_write_lock_parent4,
++ */
++#define AuReadLockFunc(name, lsc) \
++static inline void di_read_lock_##name(struct dentry *d, int flags) \
++{ di_read_lock(d, flags, AuLsc_DI_##lsc); }
++
++#define AuWriteLockFunc(name, lsc) \
++static inline void di_write_lock_##name(struct dentry *d) \
++{ di_write_lock(d, AuLsc_DI_##lsc); }
++
++#define AuRWLockFuncs(name, lsc) \
++ AuReadLockFunc(name, lsc) \
++ AuWriteLockFunc(name, lsc)
++
++AuRWLockFuncs(child, CHILD);
++AuRWLockFuncs(child2, CHILD2);
++AuRWLockFuncs(child3, CHILD3);
++AuRWLockFuncs(parent, PARENT);
++AuRWLockFuncs(parent2, PARENT2);
++AuRWLockFuncs(parent3, PARENT3);
++AuRWLockFuncs(parent4, PARENT4);
++
++#undef AuReadLockFunc
++#undef AuWriteLockFunc
++#undef AuRWLockFuncs
++
++/* to debug easier, do not make them inlined functions */
++#define DiMustReadLock(d) do { \
++ SiMustAnyLock((d)->d_sb); \
++ AuRwMustReadLock(&au_di(d)->di_rwsem); \
++} while (0)
++
++#define DiMustWriteLock(d) do { \
++ SiMustAnyLock((d)->d_sb); \
++ AuRwMustWriteLock(&au_di(d)->di_rwsem); \
++} while (0)
++
++#define DiMustAnyLock(d) do { \
++ SiMustAnyLock((d)->d_sb); \
++ AuRwMustAnyLock(&au_di(d)->di_rwsem); \
++} while (0)
++
++#define DiMustNoWaiters(d) AuRwMustNoWaiters(&au_di(d)->di_rwsem)
++
++/* ---------------------------------------------------------------------- */
++
++static inline aufs_bindex_t au_dbstart(struct dentry *dentry)
++{
++ DiMustAnyLock(dentry);
++ return au_di(dentry)->di_bstart;
++}
++
++static inline aufs_bindex_t au_dbend(struct dentry *dentry)
++{
++ DiMustAnyLock(dentry);
++ return au_di(dentry)->di_bend;
++}
++
++static inline aufs_bindex_t au_dbwh(struct dentry *dentry)
++{
++ DiMustAnyLock(dentry);
++ return au_di(dentry)->di_bwh;
++}
++
++static inline aufs_bindex_t au_dbdiropq(struct dentry *dentry)
++{
++ DiMustAnyLock(dentry);
++ AuDebugOn(dentry->d_inode
++ && dentry->d_inode->i_mode
++ && !S_ISDIR(dentry->d_inode->i_mode));
++ return au_di(dentry)->di_bdiropq;
++}
++
++/* todo: hard/soft set? */
++static inline void au_set_dbstart(struct dentry *dentry, aufs_bindex_t bindex)
++{
++ DiMustWriteLock(dentry);
++ AuDebugOn(au_sbend(dentry->d_sb) < bindex);
++ /* */
++ au_di(dentry)->di_bstart = bindex;
++}
++
++static inline void au_set_dbend(struct dentry *dentry, aufs_bindex_t bindex)
++{
++ DiMustWriteLock(dentry);
++ AuDebugOn(au_sbend(dentry->d_sb) < bindex
++ || bindex < au_dbstart(dentry));
++ au_di(dentry)->di_bend = bindex;
++}
++
++static inline void au_set_dbwh(struct dentry *dentry, aufs_bindex_t bindex)
++{
++ DiMustWriteLock(dentry);
++ AuDebugOn(au_sbend(dentry->d_sb) < bindex);
++ /* dbwh can be outside of bstart - bend range */
++ au_di(dentry)->di_bwh = bindex;
++}
++
++static inline void au_hdput(struct au_hdentry *hd, int do_free)
++{
++ au_hintent_put(hd, do_free);
++ dput(hd->hd_dentry);
++}
++
++static inline void au_update_digen(struct dentry *dentry)
++{
++ AuDebugOn(!dentry->d_sb);
++ atomic_set(&au_di(dentry)->di_generation, au_sigen(dentry->d_sb));
++ /* smp_mb(); */ /* atomic_set */
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_DENTRY_H__ */
+diff --git a/fs/aufs/dinfo.c b/fs/aufs/dinfo.c
+new file mode 100644
+index 0000000..909d1c5
+--- /dev/null
++++ b/fs/aufs/dinfo.c
+@@ -0,0 +1,436 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * dentry private data
++ *
++ * $Id: dinfo.c,v 1.47 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++int au_alloc_dinfo(struct dentry *dentry)
++{
++ struct au_dinfo *dinfo;
++ struct super_block *sb;
++ int nbr;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ AuDebugOn(dentry->d_fsdata);
++
++ dinfo = au_cache_alloc_dinfo();
++ if (dinfo) {
++ sb = dentry->d_sb;
++ nbr = au_sbend(sb) + 1;
++ if (nbr <= 0)
++ nbr = 1;
++ dinfo->di_hdentry = kcalloc(nbr, sizeof(*dinfo->di_hdentry),
++ GFP_NOFS);
++ if (dinfo->di_hdentry) {
++ au_h_dentry_init_all(dinfo->di_hdentry, nbr);
++ atomic_set(&dinfo->di_generation, au_sigen(sb));
++ /* smp_mb(); */ /* atomic_set */
++ au_rw_init_wlock_nested(&dinfo->di_rwsem,
++ AuLsc_DI_CHILD);
++ au_dbg_locked_di_reg(dentry, AuLock_DW, AuLsc_DI_CHILD);
++ dinfo->di_bstart = -1;
++ dinfo->di_bend = -1;
++ dinfo->di_bwh = -1;
++ dinfo->di_bdiropq = -1;
++
++ dentry->d_fsdata = dinfo;
++ dentry->d_op = &aufs_dop;
++ return 0; /* success */
++ }
++ au_cache_free_dinfo(dinfo);
++ }
++ AuTraceErr(-ENOMEM);
++ return -ENOMEM;
++}
++
++struct au_dinfo *au_di(struct dentry *dentry)
++{
++ struct au_dinfo *dinfo = dentry->d_fsdata;
++ AuDebugOn(!dinfo
++ || !dinfo->di_hdentry
++ /* || au_sbi(dentry->d_sb)->si_bend < dinfo->di_bend */
++ || dinfo->di_bend < dinfo->di_bstart
++ /* dbwh can be outside of this range */
++ || (0 <= dinfo->di_bdiropq
++ && (dinfo->di_bdiropq < dinfo->di_bstart
++ /* || dinfo->di_bend < dinfo->di_bdiropq */))
++ );
++ return dinfo;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static void do_ii_write_lock(struct inode *inode, unsigned int lsc)
++{
++ switch (lsc) {
++ case AuLsc_DI_CHILD:
++ ii_write_lock_child(inode);
++ break;
++ case AuLsc_DI_CHILD2:
++ ii_write_lock_child2(inode);
++ break;
++ case AuLsc_DI_CHILD3:
++ ii_write_lock_child3(inode);
++ break;
++ case AuLsc_DI_PARENT:
++ ii_write_lock_parent(inode);
++ break;
++ case AuLsc_DI_PARENT2:
++ ii_write_lock_parent2(inode);
++ break;
++ case AuLsc_DI_PARENT3:
++ ii_write_lock_parent3(inode);
++ break;
++ case AuLsc_DI_PARENT4:
++ ii_write_lock_parent4(inode);
++ break;
++ default:
++ BUG();
++ }
++}
++
++static void do_ii_read_lock(struct inode *inode, unsigned int lsc)
++{
++ switch (lsc) {
++ case AuLsc_DI_CHILD:
++ ii_read_lock_child(inode);
++ break;
++ case AuLsc_DI_CHILD2:
++ ii_read_lock_child2(inode);
++ break;
++ case AuLsc_DI_CHILD3:
++ ii_read_lock_child3(inode);
++ break;
++ case AuLsc_DI_PARENT:
++ ii_read_lock_parent(inode);
++ break;
++ case AuLsc_DI_PARENT2:
++ ii_read_lock_parent2(inode);
++ break;
++ case AuLsc_DI_PARENT3:
++ ii_read_lock_parent3(inode);
++ break;
++ case AuLsc_DI_PARENT4:
++ ii_read_lock_parent4(inode);
++ break;
++ default:
++ BUG();
++ }
++}
++
++void di_read_lock(struct dentry *d, int flags, unsigned int lsc)
++{
++ LKTRTrace("%.*s, %u\n", AuDLNPair(d), lsc);
++ SiMustAnyLock(d->d_sb);
++
++ /* todo: always nested? */
++ au_dbg_locking_di_reg(d, flags, lsc);
++ au_rw_read_lock_nested(&au_di(d)->di_rwsem, lsc);
++ au_dbg_locking_di_unreg(d, flags);
++ au_dbg_locked_di_reg(d, flags, lsc);
++ if (d->d_inode) {
++ if (au_ftest_lock(flags, IW))
++ do_ii_write_lock(d->d_inode, lsc);
++ else if (au_ftest_lock(flags, IR))
++ do_ii_read_lock(d->d_inode, lsc);
++ }
++}
++
++void di_read_unlock(struct dentry *d, int flags)
++{
++ LKTRTrace("%.*s\n", AuDLNPair(d));
++ SiMustAnyLock(d->d_sb);
++
++ if (d->d_inode) {
++ if (au_ftest_lock(flags, IW))
++ ii_write_unlock(d->d_inode);
++ else if (au_ftest_lock(flags, IR))
++ ii_read_unlock(d->d_inode);
++ }
++ au_rw_read_unlock(&au_di(d)->di_rwsem);
++ au_dbg_locked_di_unreg(d, flags);
++}
++
++void di_downgrade_lock(struct dentry *d, int flags)
++{
++ SiMustAnyLock(d->d_sb);
++
++ au_rw_dgrade_lock(&au_di(d)->di_rwsem);
++ if (d->d_inode && au_ftest_lock(flags, IR))
++ ii_downgrade_lock(d->d_inode);
++}
++
++void di_write_lock(struct dentry *d, unsigned int lsc)
++{
++ LKTRTrace("%.*s, %u\n", AuDLNPair(d), lsc);
++ SiMustAnyLock(d->d_sb);
++
++ /* todo: always nested? */
++ au_dbg_locking_di_reg(d, AuLock_IW, lsc);
++ au_rw_write_lock_nested(&au_di(d)->di_rwsem, lsc);
++ au_dbg_locking_di_unreg(d, AuLock_IW);
++ au_dbg_locked_di_reg(d, AuLock_IW, lsc);
++ if (d->d_inode)
++ do_ii_write_lock(d->d_inode, lsc);
++}
++
++void di_write_unlock(struct dentry *d)
++{
++ LKTRTrace("%.*s\n", AuDLNPair(d));
++ SiMustAnyLock(d->d_sb);
++
++ if (d->d_inode)
++ ii_write_unlock(d->d_inode);
++ au_rw_write_unlock(&au_di(d)->di_rwsem);
++ au_dbg_locked_di_unreg(d, AuLock_IW);
++}
++
++void di_write_lock2_child(struct dentry *d1, struct dentry *d2, int isdir)
++{
++ AuTraceEnter();
++ AuDebugOn(d1 == d2
++ || d1->d_inode == d2->d_inode
++ || d1->d_sb != d2->d_sb);
++
++ if (isdir && au_test_subdir(d1, d2)) {
++ di_write_lock_child(d1);
++ di_write_lock_child2(d2);
++ } else {
++ /* there should be no races */
++ di_write_lock_child(d2);
++ di_write_lock_child2(d1);
++ }
++}
++
++void di_write_lock2_parent(struct dentry *d1, struct dentry *d2, int isdir)
++{
++ AuTraceEnter();
++ AuDebugOn(d1 == d2
++ || d1->d_inode == d2->d_inode
++ || d1->d_sb != d2->d_sb);
++
++ if (isdir && au_test_subdir(d1, d2)) {
++ di_write_lock_parent(d1);
++ di_write_lock_parent2(d2);
++ } else {
++ /* there should be no races */
++ di_write_lock_parent(d2);
++ di_write_lock_parent2(d1);
++ }
++}
++
++void di_write_unlock2(struct dentry *d1, struct dentry *d2)
++{
++ di_write_unlock(d1);
++ if (d1->d_inode == d2->d_inode) {
++ au_rw_write_unlock(&au_di(d2)->di_rwsem);
++ au_dbg_locked_di_unreg(d2, AuLock_IW);
++ } else
++ di_write_unlock(d2);
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct dentry *au_h_dptr(struct dentry *dentry, aufs_bindex_t bindex)
++{
++ struct dentry *d;
++
++ DiMustAnyLock(dentry);
++ if (au_dbstart(dentry) < 0 || bindex < au_dbstart(dentry))
++ return NULL;
++ AuDebugOn(bindex < 0
++ /* || bindex > au_sbend(dentry->d_sb) */);
++ d = au_di(dentry)->di_hdentry[0 + bindex].hd_dentry;
++ AuDebugOn(d && (atomic_read(&d->d_count) <= 0));
++ return d;
++}
++
++aufs_bindex_t au_dbtail(struct dentry *dentry)
++{
++ aufs_bindex_t bend, bwh;
++
++ bend = au_dbend(dentry);
++ if (0 <= bend) {
++ bwh = au_dbwh(dentry);
++ if (!bwh)
++ return bwh;
++ if (0 < bwh && bwh < bend)
++ return bwh - 1;
++ }
++ return bend;
++}
++
++aufs_bindex_t au_dbtaildir(struct dentry *dentry)
++{
++ aufs_bindex_t bend, bopq;
++
++ AuDebugOn(dentry->d_inode
++ && dentry->d_inode->i_mode
++ && !S_ISDIR(dentry->d_inode->i_mode));
++
++ bend = au_dbtail(dentry);
++ if (0 <= bend) {
++ bopq = au_dbdiropq(dentry);
++ AuDebugOn(bend < bopq);
++ if (0 <= bopq && bopq < bend)
++ bend = bopq;
++ }
++ return bend;
++}
++
++#if 0 /* reserved for future use */
++aufs_bindex_t au_dbtail_generic(struct dentry *dentry)
++{
++ struct inode *inode;
++
++ inode = dentry->d_inode;
++ if (inode && S_ISDIR(inode->i_mode))
++ return au_dbtaildir(dentry);
++ else
++ return au_dbtail(dentry);
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++void au_set_dbdiropq(struct dentry *dentry, aufs_bindex_t bindex)
++{
++ DiMustWriteLock(dentry);
++ AuDebugOn(au_sbend(dentry->d_sb) < bindex);
++ AuDebugOn((bindex >= 0
++ && (bindex < au_dbstart(dentry)
++ || au_dbend(dentry) < bindex))
++ || (dentry->d_inode
++ && dentry->d_inode->i_mode
++ && !S_ISDIR(dentry->d_inode->i_mode)));
++ au_di(dentry)->di_bdiropq = bindex;
++}
++
++void au_set_h_dptr(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_dentry)
++{
++ struct au_hdentry *hd = au_di(dentry)->di_hdentry + bindex;
++ DiMustWriteLock(dentry);
++ AuDebugOn(bindex < au_di(dentry)->di_bstart
++ || bindex > au_di(dentry)->di_bend
++ || (h_dentry && atomic_read(&h_dentry->d_count) <= 0)
++ || (h_dentry && hd->hd_dentry)
++ );
++ if (hd->hd_dentry)
++ au_hdput(hd, /*do_free*/0);
++ hd->hd_dentry = h_dentry;
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_update_dbrange(struct dentry *dentry, int do_put_zero)
++{
++ struct au_dinfo *dinfo;
++ aufs_bindex_t bindex;
++ struct dentry *h_d;
++
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), do_put_zero);
++ DiMustWriteLock(dentry);
++
++ dinfo = au_di(dentry);
++ if (!dinfo || dinfo->di_bstart < 0)
++ return;
++
++ if (do_put_zero) {
++ for (bindex = dinfo->di_bstart; bindex <= dinfo->di_bend;
++ bindex++) {
++ h_d = dinfo->di_hdentry[0 + bindex].hd_dentry;
++ if (h_d && !h_d->d_inode)
++ au_set_h_dptr(dentry, bindex, NULL);
++ }
++ }
++
++ dinfo->di_bstart = -1;
++ while (++dinfo->di_bstart <= dinfo->di_bend)
++ if (dinfo->di_hdentry[0 + dinfo->di_bstart].hd_dentry)
++ break;
++ if (dinfo->di_bstart > dinfo->di_bend) {
++ dinfo->di_bstart = -1;
++ dinfo->di_bend = -1;
++ return;
++ }
++
++ dinfo->di_bend++;
++ while (0 <= --dinfo->di_bend)
++ if (dinfo->di_hdentry[0 + dinfo->di_bend].hd_dentry)
++ break;
++ AuDebugOn(dinfo->di_bstart > dinfo->di_bend || dinfo->di_bend < 0);
++}
++
++void au_update_dbstart(struct dentry *dentry)
++{
++ aufs_bindex_t bindex,
++ bstart = au_dbstart(dentry),
++ bend = au_dbend(dentry);
++ struct dentry *h_dentry;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ DiMustWriteLock(dentry);
++
++ for (bindex = bstart; bindex <= bend; bindex++) {
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!h_dentry)
++ continue;
++ if (h_dentry->d_inode) {
++ au_set_dbstart(dentry, bindex);
++ return;
++ }
++ au_set_h_dptr(dentry, bindex, NULL);
++ }
++}
++
++void au_update_dbend(struct dentry *dentry)
++{
++ aufs_bindex_t bindex,
++ bstart = au_dbstart(dentry),
++ bend = au_dbend(dentry);
++ struct dentry *h_dentry;
++
++ DiMustWriteLock(dentry);
++ for (bindex = bend; bindex <= bstart; bindex--) {
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!h_dentry)
++ continue;
++ if (h_dentry->d_inode) {
++ au_set_dbend(dentry, bindex);
++ return;
++ }
++ au_set_h_dptr(dentry, bindex, NULL);
++ }
++}
++
++int au_find_dbindex(struct dentry *dentry, struct dentry *h_dentry)
++{
++ aufs_bindex_t bindex, bend;
++
++ bend = au_dbend(dentry);
++ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++)
++ if (au_h_dptr(dentry, bindex) == h_dentry)
++ return bindex;
++ return -1;
++}
+diff --git a/fs/aufs/dir.c b/fs/aufs/dir.c
+new file mode 100644
+index 0000000..6dbe3ff
+--- /dev/null
++++ b/fs/aufs/dir.c
+@@ -0,0 +1,558 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * directory operations
++ *
++ * $Id: dir.c,v 1.69 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++static int reopen_dir(struct file *file)
++{
++ int err;
++ struct dentry *dentry, *h_dentry;
++ aufs_bindex_t bindex, btail, bstart;
++ struct file *h_file;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ AuDebugOn(!S_ISDIR(dentry->d_inode->i_mode));
++
++ /* open all hidden dirs */
++ bstart = au_dbstart(dentry);
++#if 1 /* todo: necessary? */
++ for (bindex = au_fbstart(file); bindex < bstart; bindex++)
++ au_set_h_fptr(file, bindex, NULL);
++#endif
++ au_set_fbstart(file, bstart);
++ btail = au_dbtaildir(dentry);
++#if 1 /* todo: necessary? */
++ for (bindex = au_fbend(file); btail < bindex; bindex--)
++ au_set_h_fptr(file, bindex, NULL);
++#endif
++ au_set_fbend(file, btail);
++ for (bindex = bstart; bindex <= btail; bindex++) {
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!h_dentry)
++ continue;
++ h_file = au_h_fptr(file, bindex);
++ if (h_file) {
++ AuDebugOn(h_file->f_dentry != h_dentry);
++ continue;
++ }
++
++ h_file = au_h_open(dentry, bindex, file->f_flags, file);
++ err = PTR_ERR(h_file);
++ if (IS_ERR(h_file))
++ goto out; /* close all? */
++ /* cpup_file_flags(h_file, file); */
++ au_set_h_fptr(file, bindex, h_file);
++ }
++ au_update_figen(file);
++ /* todo: necessary? */
++ /* file->f_ra = h_file->f_ra; */
++ err = 0;
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int do_open_dir(struct file *file, int flags)
++{
++ int err;
++ aufs_bindex_t bindex, btail;
++ struct dentry *dentry, *h_dentry;
++ struct file *h_file;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, 0x%x\n", AuDLNPair(dentry), flags);
++ AuDebugOn(!dentry->d_inode || !S_ISDIR(dentry->d_inode->i_mode));
++
++ err = 0;
++ au_set_fvdir_cache(file, NULL);
++ file->f_version = dentry->d_inode->i_version;
++ bindex = au_dbstart(dentry);
++ au_set_fbstart(file, bindex);
++ btail = au_dbtaildir(dentry);
++ au_set_fbend(file, btail);
++ for (; !err && bindex <= btail; bindex++) {
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!h_dentry)
++ continue;
++
++ h_file = au_h_open(dentry, bindex, flags, file);
++ if (IS_ERR(h_file)) {
++ err = PTR_ERR(h_file);
++ break;
++ }
++ au_set_h_fptr(file, bindex, h_file);
++ }
++ au_update_figen(file);
++ /* todo: necessary? */
++ /* file->f_ra = h_file->f_ra; */
++ if (!err)
++ return 0; /* success */
++
++ /* close all */
++ for (bindex = au_fbstart(file); bindex <= btail; bindex++)
++ au_set_h_fptr(file, bindex, NULL);
++ au_set_fbstart(file, -1);
++ au_set_fbend(file, -1);
++ return err;
++}
++
++static int aufs_open_dir(struct inode *inode, struct file *file)
++{
++ LKTRTrace("i%lu, %.*s\n", inode->i_ino, AuDLNPair(file->f_dentry));
++
++ return au_do_open(inode, file, do_open_dir);
++}
++
++static int aufs_release_dir(struct inode *inode, struct file *file)
++{
++ struct au_vdir *vdir_cache;
++ struct super_block *sb;
++
++ LKTRTrace("i%lu, %.*s\n", inode->i_ino, AuDLNPair(file->f_dentry));
++
++ sb = file->f_dentry->d_sb;
++ si_noflush_read_lock(sb);
++ fi_write_lock(file);
++ vdir_cache = au_fvdir_cache(file);
++ if (vdir_cache)
++ au_vdir_free(vdir_cache);
++ fi_write_unlock(file);
++ au_finfo_fin(file);
++ si_read_unlock(sb);
++ return 0;
++}
++
++static int fsync_dir(struct dentry *dentry, int datasync)
++{
++ int err;
++ struct inode *inode;
++ struct super_block *sb;
++ aufs_bindex_t bend, bindex;
++
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), datasync);
++ DiMustAnyLock(dentry);
++ sb = dentry->d_sb;
++ SiMustAnyLock(sb);
++ inode = dentry->d_inode;
++ IMustLock(inode);
++ IiMustAnyLock(inode);
++
++ err = 0;
++ bend = au_dbend(dentry);
++ for (bindex = au_dbstart(dentry); !err && bindex <= bend; bindex++) {
++ struct dentry *h_dentry;
++ struct inode *h_inode;
++ struct file_operations *fop;
++
++ if (au_test_ro(sb, bindex, inode))
++ continue;
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!h_dentry)
++ continue;
++ h_inode = h_dentry->d_inode;
++ if (!h_inode)
++ continue;
++
++ /* no mnt_want_write() */
++ /* cf. fs/nsfd/vfs.c and fs/nfsd/nfs4recover.c */
++ vfsub_i_lock(h_inode);
++ /* todo: inotiry fired? */
++ fop = (void *)h_inode->i_fop;
++ err = filemap_fdatawrite(h_inode->i_mapping);
++ if (!err && fop && fop->fsync)
++ err = fop->fsync(NULL, h_dentry, datasync);
++ if (!err)
++ err = filemap_fdatawrite(h_inode->i_mapping);
++ if (!err)
++ au_update_fuse_h_inode(NULL, h_dentry); /*ignore*/
++ vfsub_i_unlock(h_inode);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * @file may be NULL
++ */
++static int aufs_fsync_dir(struct file *file, struct dentry *dentry,
++ int datasync)
++{
++ int err;
++ struct inode *inode;
++ struct file *h_file;
++ struct super_block *sb;
++ aufs_bindex_t bend, bindex;
++
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), datasync);
++ inode = dentry->d_inode;
++ IMustLock(inode);
++
++ err = 0;
++ sb = dentry->d_sb;
++ si_noflush_read_lock(sb);
++ if (file) {
++ err = au_reval_and_lock_fdi(file, reopen_dir, /*wlock*/1,
++ /*locked*/1);
++ if (unlikely(err))
++ goto out;
++ } else
++ di_write_lock_child(dentry);
++
++ if (file) {
++ bend = au_fbend(file);
++ for (bindex = au_fbstart(file); !err && bindex <= bend;
++ bindex++) {
++ h_file = au_h_fptr(file, bindex);
++ if (!h_file || au_test_ro(sb, bindex, inode))
++ continue;
++
++ err = -EINVAL;
++ if (h_file->f_op && h_file->f_op->fsync) {
++ /* todo: try do_fsync() in fs/sync.c? */
++ vfsub_i_lock(h_file->f_mapping->host);
++ err = h_file->f_op->fsync
++ (h_file, h_file->f_dentry, datasync);
++ if (!err)
++ au_update_fuse_h_inode
++ (h_file->f_vfsmnt,
++ h_file->f_dentry);
++ /*ignore*/
++ vfsub_i_unlock(h_file->f_mapping->host);
++ }
++ }
++ } else
++ err = fsync_dir(dentry, datasync);
++ au_cpup_attr_timesizes(inode);
++ di_write_unlock(dentry);
++ if (file)
++ fi_write_unlock(file);
++
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int aufs_readdir(struct file *file, void *dirent, filldir_t filldir)
++{
++ int err;
++ struct dentry *dentry;
++ struct inode *inode;
++ struct super_block *sb;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, pos %lld\n", AuDLNPair(dentry), file->f_pos);
++ inode = dentry->d_inode;
++ IMustLock(inode);
++
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_reval_and_lock_fdi(file, reopen_dir, /*wlock*/1, /*locked*/1);
++ if (unlikely(err))
++ goto out;
++ err = au_vdir_init(file);
++ di_downgrade_lock(dentry, AuLock_IR);
++ if (unlikely(err))
++ goto out_unlock;
++
++ if (!au_test_nfsd(current)) {
++ err = au_vdir_fill_de(file, dirent, filldir);
++ } else {
++ /*
++ * nfsd filldir may call lookup_one_len(), vfs_getattr(),
++ * encode_fh() and others.
++ */
++ struct inode *h_inode = au_h_iptr(inode, au_ibstart(inode));
++
++ di_read_unlock(dentry, AuLock_IR);
++ si_read_unlock(sb);
++ lockdep_off();
++ err = au_vdir_fill_de(file, dirent, filldir);
++ lockdep_on();
++ inode->i_atime = h_inode->i_atime;
++ fi_write_unlock(file);
++
++ AuTraceErr(err);
++ return err;
++ }
++
++ inode->i_atime = au_h_iptr(inode, au_ibstart(inode))->i_atime;
++
++ out_unlock:
++ di_read_unlock(dentry, AuLock_IR);
++ fi_write_unlock(file);
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++#define AuTestEmpty_WHONLY 1
++#define AuTestEmpty_DLGT (1 << 1)
++#define AuTestEmpty_DIRPERM1 (1 << 2)
++#define AuTestEmpty_CALLED (1 << 3)
++#define AuTestEmpty_SHWH (1 << 4)
++#define au_ftest_testempty(flags, name) ((flags) & AuTestEmpty_##name)
++#define au_fset_testempty(flags, name) { (flags) |= AuTestEmpty_##name; }
++#define au_fclr_testempty(flags, name) { (flags) &= ~AuTestEmpty_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef AuTestEmpty_DLGT
++#define AuTestEmpty_DLGT 0
++#undef AuTestEmpty_DIRPERM1
++#define AuTestEmpty_DIRPERM1 0
++#endif
++#ifndef CONFIG_AUFS_SHWH
++#undef AuTestEmpty_SHWH
++#define AuTestEmpty_SHWH 0
++#endif
++
++struct test_empty_arg {
++ struct au_nhash *whlist;
++ unsigned int flags;
++ int err;
++ aufs_bindex_t bindex;
++};
++
++static int test_empty_cb(void *__arg, const char *__name, int namelen,
++ loff_t offset, au_filldir_ino_t ino,
++ unsigned int d_type)
++{
++ struct test_empty_arg *arg = __arg;
++ char *name = (void *)__name;
++
++ LKTRTrace("%.*s\n", namelen, name);
++
++ arg->err = 0;
++ au_fset_testempty(arg->flags, CALLED);
++ /* smp_mb(); */
++ if (name[0] == '.'
++ && (namelen == 1 || (name[1] == '.' && namelen == 2)))
++ return 0; /* success */
++
++ if (namelen <= AUFS_WH_PFX_LEN
++ || memcmp(name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) {
++ if (au_ftest_testempty(arg->flags, WHONLY)
++ && !au_nhash_test_known_wh(arg->whlist, name, namelen))
++ arg->err = -ENOTEMPTY;
++ goto out;
++ }
++
++ name += AUFS_WH_PFX_LEN;
++ namelen -= AUFS_WH_PFX_LEN;
++ if (!au_nhash_test_known_wh(arg->whlist, name, namelen))
++ arg->err = au_nhash_append_wh
++ (arg->whlist, name, namelen, ino, d_type, arg->bindex,
++ au_ftest_testempty(arg->flags, SHWH));
++
++ out:
++ /* smp_mb(); */
++ AuTraceErr(arg->err);
++ return arg->err;
++}
++
++static int do_test_empty(struct dentry *dentry, struct test_empty_arg *arg)
++{
++ int err, dlgt;
++ struct file *h_file;
++
++ LKTRTrace("%.*s, {%p, 0x%x, %d}\n",
++ AuDLNPair(dentry), arg->whlist, arg->flags, arg->bindex);
++
++ h_file = au_h_open(dentry, arg->bindex,
++ O_RDONLY | O_NONBLOCK | O_DIRECTORY | O_LARGEFILE,
++ /*file*/NULL);
++ err = PTR_ERR(h_file);
++ if (IS_ERR(h_file))
++ goto out;
++ err = 0;
++ if (au_opt_test(au_mntflags(dentry->d_sb), UDBA_INOTIFY)
++ && !h_file->f_dentry->d_inode->i_nlink)
++ goto out_put;
++
++ dlgt = au_ftest_testempty(arg->flags, DLGT);
++ do {
++ arg->err = 0;
++ au_fclr_testempty(arg->flags, CALLED);
++ /* smp_mb(); */
++ err = vfsub_readdir(h_file, test_empty_cb, arg, dlgt);
++ if (err >= 0)
++ err = arg->err;
++ } while (!err && au_ftest_testempty(arg->flags, CALLED));
++
++ out_put:
++ fput(h_file);
++ au_sbr_put(dentry->d_sb, arg->bindex);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++struct do_test_empty_args {
++ int *errp;
++ struct dentry *dentry;
++ struct test_empty_arg *arg;
++};
++
++static void call_do_test_empty(void *args)
++{
++ struct do_test_empty_args *a = args;
++ *a->errp = do_test_empty(a->dentry, a->arg);
++}
++
++static int sio_test_empty(struct dentry *dentry, struct test_empty_arg *arg)
++{
++ int err, wkq_err;
++ struct dentry *h_dentry;
++ struct inode *h_inode;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ h_dentry = au_h_dptr(dentry, arg->bindex);
++ AuDebugOn(!h_dentry);
++ h_inode = h_dentry->d_inode;
++ AuDebugOn(!h_inode);
++
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ err = au_test_h_perm_sio(h_inode, MAY_EXEC | MAY_READ,
++ au_test_dlgt(au_mntflags(dentry->d_sb)));
++ vfsub_i_unlock(h_inode);
++ if (!err)
++ err = do_test_empty(dentry, arg);
++ else {
++ struct do_test_empty_args args = {
++ .errp = &err,
++ .dentry = dentry,
++ .arg = arg
++ };
++ unsigned int flags = arg->flags;
++
++ au_fclr_testempty(arg->flags, DLGT);
++ au_fclr_testempty(arg->flags, DIRPERM1);
++ wkq_err = au_wkq_wait(call_do_test_empty, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ arg->flags = flags;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++int au_test_empty_lower(struct dentry *dentry)
++{
++ int err;
++ struct inode *inode;
++ struct test_empty_arg arg;
++ struct au_nhash *whlist;
++ aufs_bindex_t bindex, bstart, btail;
++ unsigned int mnt_flags;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ inode = dentry->d_inode;
++ AuDebugOn(!inode || !S_ISDIR(inode->i_mode));
++
++ whlist = au_nhash_new(GFP_NOFS);
++ err = PTR_ERR(whlist);
++ if (IS_ERR(whlist))
++ goto out;
++
++ bstart = au_dbstart(dentry);
++ mnt_flags = au_mntflags(dentry->d_sb);
++ arg.whlist = whlist;
++ arg.flags = 0;
++ if (au_test_dlgt(mnt_flags))
++ au_fset_testempty(arg.flags, DLGT);
++ if (au_opt_test(mnt_flags, SHWH))
++ au_fset_testempty(arg.flags, SHWH);
++ arg.bindex = bstart;
++ err = do_test_empty(dentry, &arg);
++ if (unlikely(err))
++ goto out_whlist;
++
++ au_fset_testempty(arg.flags, WHONLY);
++ if (au_test_dirperm1(mnt_flags))
++ au_fset_testempty(arg.flags, DIRPERM1);
++ btail = au_dbtaildir(dentry);
++ for (bindex = bstart + 1; !err && bindex <= btail; bindex++) {
++ struct dentry *h_dentry;
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (h_dentry && h_dentry->d_inode) {
++ arg.bindex = bindex;
++ err = do_test_empty(dentry, &arg);
++ }
++ }
++
++ out_whlist:
++ au_nhash_del(whlist);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_test_empty(struct dentry *dentry, struct au_nhash *whlist)
++{
++ int err;
++ struct inode *inode;
++ struct test_empty_arg arg;
++ aufs_bindex_t bindex, btail;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ inode = dentry->d_inode;
++ AuDebugOn(!inode || !S_ISDIR(inode->i_mode));
++
++ err = 0;
++ arg.whlist = whlist;
++ arg.flags = AuTestEmpty_WHONLY;
++ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH))
++ au_fset_testempty(arg.flags, SHWH);
++ btail = au_dbtaildir(dentry);
++ for (bindex = au_dbstart(dentry); !err && bindex <= btail; bindex++) {
++ struct dentry *h_dentry;
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (h_dentry && h_dentry->d_inode) {
++ arg.bindex = bindex;
++ err = sio_test_empty(dentry, &arg);
++ }
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct file_operations aufs_dir_fop = {
++ .read = generic_read_dir,
++ .readdir = aufs_readdir,
++ .open = aufs_open_dir,
++ .release = aufs_release_dir,
++ .flush = aufs_flush,
++ .fsync = aufs_fsync_dir,
++};
+diff --git a/fs/aufs/dir.h b/fs/aufs/dir.h
+new file mode 100644
+index 0000000..1870601
+--- /dev/null
++++ b/fs/aufs/dir.h
+@@ -0,0 +1,154 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * directory operations
++ *
++ * $Id: dir.h,v 1.33 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_DIR_H__
++#define __AUFS_DIR_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/version.h>
++#include <linux/aufs_type.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++typedef u64 au_filldir_ino_t;
++#else
++typedef ino_t au_filldir_ino_t;
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++/* need to be faster and smaller */
++
++/* todo: changeable? */
++#define AuSize_DEBLK 512
++#define AuSize_NHASH 32
++#if AuSize_DEBLK < NAME_MAX || PAGE_SIZE < AuSize_DEBLK
++#error invalid size AuSize_DEBLK
++#endif
++
++typedef char au_vdir_deblk_t[AuSize_DEBLK];
++
++struct au_nhash {
++ struct hlist_head heads[AuSize_NHASH];
++};
++
++struct au_vdir_destr {
++ unsigned char len;
++ char name[0];
++} __packed;
++
++struct au_vdir_dehstr {
++ struct hlist_node hash;
++ struct au_vdir_destr *str;
++};
++
++struct au_vdir_de {
++ ino_t de_ino;
++ unsigned char de_type;
++ /* caution: packed */
++ struct au_vdir_destr de_str;
++} __packed;
++
++struct au_vdir_wh {
++ struct hlist_node wh_hash;
++ aufs_bindex_t wh_bindex;
++#ifdef CONFIG_AUFS_SHWH
++ ino_t wh_ino;
++ unsigned char wh_type;
++ /* caution: packed */
++#endif
++ struct au_vdir_destr wh_str;
++} __packed;
++
++union au_vdir_deblk_p {
++ unsigned char *p;
++ au_vdir_deblk_t *deblk;
++ struct au_vdir_de *de;
++};
++
++struct au_vdir {
++ au_vdir_deblk_t **vd_deblk;
++ int vd_nblk;
++ struct {
++ int i;
++ union au_vdir_deblk_p p;
++ } vd_last;
++
++ unsigned long vd_version;
++ unsigned long vd_jiffy;
++};
++
++/* ---------------------------------------------------------------------- */
++
++/* dir.c */
++extern struct file_operations aufs_dir_fop;
++int au_test_empty_lower(struct dentry *dentry);
++int au_test_empty(struct dentry *dentry, struct au_nhash *whlist);
++
++/* vdir.c */
++struct au_nhash *au_nhash_new(gfp_t gfp);
++void au_nhash_del(struct au_nhash *nhash);
++void au_nhash_init(struct au_nhash *nhash);
++void au_nhash_move(struct au_nhash *dst, struct au_nhash *src);
++void au_nhash_fin(struct au_nhash *nhash);
++int au_nhash_test_longer_wh(struct au_nhash *whlist, aufs_bindex_t btgt,
++ int limit);
++int au_nhash_test_known_wh(struct au_nhash *whlist, char *name, int namelen);
++int au_nhash_append_wh(struct au_nhash *whlist, char *name, int namelen,
++ ino_t ino, unsigned int d_type, aufs_bindex_t bindex,
++ unsigned char shwh);
++void au_vdir_free(struct au_vdir *vdir);
++int au_vdir_init(struct file *file);
++int au_vdir_fill_de(struct file *file, void *dirent, filldir_t filldir);
++
++/* ---------------------------------------------------------------------- */
++
++static inline
++void au_shwh_init_wh(struct au_vdir_wh *wh, ino_t ino, unsigned char d_type)
++{
++#ifdef CONFIG_AUFS_SHWH
++ wh->wh_ino = ino;
++ wh->wh_type = d_type;
++#endif
++}
++
++static inline void au_add_nlink(struct inode *dir, struct inode *h_dir)
++{
++ AuDebugOn(!S_ISDIR(dir->i_mode) || !S_ISDIR(h_dir->i_mode));
++ dir->i_nlink += h_dir->i_nlink - 2;
++ if (h_dir->i_nlink < 2)
++ dir->i_nlink += 2;
++}
++
++static inline void au_sub_nlink(struct inode *dir, struct inode *h_dir)
++{
++ AuDebugOn(!S_ISDIR(dir->i_mode) || !S_ISDIR(h_dir->i_mode));
++ dir->i_nlink -= h_dir->i_nlink - 2;
++ if (h_dir->i_nlink < 2)
++ dir->i_nlink -= 2;
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_DIR_H__ */
+diff --git a/fs/aufs/dlgt.c b/fs/aufs/dlgt.c
+new file mode 100644
+index 0000000..6eea1b5
+--- /dev/null
++++ b/fs/aufs/dlgt.c
+@@ -0,0 +1,112 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * lookup functions in 'delegate' mode
++ *
++ * $Id: dlgt.c,v 1.4 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++struct au_lookup_one_len_args {
++ struct dentry **errp;
++ const char *name;
++ struct dentry *parent;
++ int len;
++};
++
++static void au_call_lookup_one_len(void *args)
++{
++ struct au_lookup_one_len_args *a = args;
++ *a->errp = vfsub_lookup_one_len(a->name, a->parent, a->len);
++}
++
++struct dentry *au_lkup_one_dlgt(const char *name, struct dentry *parent,
++ int len, unsigned int flags)
++{
++ struct dentry *dentry;
++ int dirperm1;
++
++ LKTRTrace("%.*s/%.*s, 0x%x\n", AuDLNPair(parent), len, name, flags);
++
++ dirperm1 = au_ftest_ndx(flags, DIRPERM1);
++ if (!dirperm1 && !au_ftest_ndx(flags, DLGT))
++ dentry = vfsub_lookup_one_len(name, parent, len);
++ else {
++ int wkq_err;
++ struct au_lookup_one_len_args args = {
++ .errp = &dentry,
++ .name = name,
++ .parent = parent,
++ .len = len
++ };
++ wkq_err = au_wkq_wait(au_call_lookup_one_len, &args,
++ /*dlgt*/!dirperm1);
++ if (unlikely(wkq_err))
++ dentry = ERR_PTR(wkq_err);
++ }
++
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct security_inode_permission_args {
++ int *errp;
++ struct inode *h_inode;
++ int mask;
++ struct nameidata *fake_nd;
++};
++
++static void call_security_inode_permission(void *args)
++{
++ struct security_inode_permission_args *a = args;
++ LKTRTrace("fsuid %d\n", current->fsuid);
++ *a->errp = security_inode_permission(a->h_inode, a->mask, a->fake_nd);
++}
++
++int au_security_inode_permission(struct inode *h_inode, int mask,
++ struct nameidata *fake_nd, int dlgt)
++{
++ int err;
++
++ AuTraceEnter();
++
++ if (!dlgt)
++ err = security_inode_permission(h_inode, mask, fake_nd);
++ else {
++ int wkq_err;
++ struct security_inode_permission_args args = {
++ .errp = &err,
++ .h_inode = h_inode,
++ .mask = mask,
++ .fake_nd = fake_nd
++ };
++ wkq_err = au_wkq_wait(call_security_inode_permission, &args,
++ /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
+diff --git a/fs/aufs/export.c b/fs/aufs/export.c
+new file mode 100644
+index 0000000..d2d474c
+--- /dev/null
++++ b/fs/aufs/export.c
+@@ -0,0 +1,809 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * export via nfs
++ *
++ * $Id: export.c,v 1.43 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++#include <linux/exportfs.h>
++#else
++#include <linux/fs.h>
++#endif
++#include <linux/random.h>
++#include "aufs.h"
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++static struct dentry *
++au_call_decode_fh(struct vfsmount *h_mnt, __u32 *fh, int fh_len, int fh_type,
++ int (*acceptable)(void *, struct dentry *), void *context)
++{
++ /* in linux-2.6.24, it takes struct fid * as file handle */
++ return exportfs_decode_fh(h_mnt, (void *)fh, fh_len, fh_type,
++ acceptable, context);
++}
++
++static int
++au_call_encode_fh(struct dentry *h_dentry, __u32 *fh, int *max_len,
++ int connectable)
++{
++ /* in linux-2.6.24, it takes struct fid * as file handle */
++ return exportfs_encode_fh(h_dentry, (void *)fh, max_len, connectable);
++}
++#else
++extern struct export_operations export_op_default;
++#define CALL(ops, func) \
++ (((ops)->func) ? ((ops)->func) : export_op_default.func)
++
++static struct dentry *
++au_call_decode_fh(struct vfsmount *h_mnt, __u32 *fh, int fh_len, int fh_type,
++ int (*acceptable)(void *, struct dentry *), void *context)
++{
++ return CALL(h_mnt->mnt_sb->s_export_op, decode_fh)
++ (h_mnt->mnt_sb, fh, fh_len, fh_type, acceptable, context);
++}
++
++static int
++au_call_encode_fh(struct dentry *h_dentry, __u32 *fh, int *max_len,
++ int connectable)
++{
++ return CALL(h_dentry->d_sb->s_export_op, encode_fh)
++ (h_dentry, fh, max_len, connectable);
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23) */
++
++/* ---------------------------------------------------------------------- */
++
++union conv {
++#ifdef CONFIG_AUFS_INO_T_64
++ __u32 a[2];
++#else
++ __u32 a[1];
++#endif
++ ino_t ino;
++};
++
++static ino_t decode_ino(__u32 *a)
++{
++ union conv u;
++
++ BUILD_BUG_ON(sizeof(u.ino) != sizeof(u.a));
++ u.a[0] = a[0];
++#ifdef CONFIG_AUFS_INO_T_64
++ u.a[1] = a[1];
++#endif
++ return u.ino;
++}
++
++static void encode_ino(__u32 *a, ino_t ino)
++{
++ union conv u;
++
++ u.ino = ino;
++ a[0] = u.a[0];
++#ifdef CONFIG_AUFS_INO_T_64
++ a[1] = u.a[1];
++#endif
++}
++
++/* NFS file handle */
++enum {
++ Fh_br_id,
++ Fh_sigen,
++#ifdef CONFIG_AUFS_INO_T_64
++ /* support 64bit inode number */
++ Fh_ino1,
++ Fh_ino2,
++ Fh_dir_ino1,
++ Fh_dir_ino2,
++#else
++ Fh_ino1,
++ Fh_dir_ino1,
++#endif
++ Fh_igen,
++ Fh_h_type,
++ Fh_tail,
++
++ Fh_ino = Fh_ino1,
++ Fh_dir_ino = Fh_dir_ino1
++};
++
++static int au_test_anon(struct dentry *dentry)
++{
++ return !!(dentry->d_flags & DCACHE_DISCONNECTED);
++}
++
++/* ---------------------------------------------------------------------- */
++/* inode generation external table */
++
++int au_xigen_inc(struct inode *inode)
++{
++ int err;
++ loff_t pos;
++ ssize_t sz;
++ __u32 igen;
++ struct super_block *sb;
++ struct au_sbinfo *sbinfo;
++
++ LKTRTrace("i%lu\n", (unsigned long)inode->i_ino);
++
++ err = 0;
++ sb = inode->i_sb;
++ if (unlikely(!au_opt_test_xino(au_mntflags(sb))))
++ goto out;
++
++ pos = inode->i_ino;
++ pos *= sizeof(igen);
++ igen = inode->i_generation + 1;
++ sbinfo = au_sbi(sb);
++ sz = xino_fwrite(sbinfo->si_xwrite, sbinfo->si_xigen, &igen,
++ sizeof(igen), &pos);
++ if (sz == sizeof(igen))
++ goto out; /* success */
++
++ err = sz;
++ if (unlikely(sz >= 0)) {
++ err = -EIO;
++ AuIOErr("xigen error (%zd)\n", sz);
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_xigen_new(struct inode *inode)
++{
++ int err;
++ loff_t pos;
++ ssize_t sz;
++ struct super_block *sb;
++ struct au_sbinfo *sbinfo;
++ struct file *file;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++
++ err = 0;
++ /* todo: dirty, at mount time */
++ if (inode->i_ino == AUFS_ROOT_INO)
++ goto out;
++ sb = inode->i_sb;
++ if (unlikely(!au_opt_test_xino(au_mntflags(sb))))
++ goto out;
++
++ err = -EFBIG;
++ pos = inode->i_ino;
++ if (unlikely(Au_LOFF_MAX / sizeof(inode->i_generation) - 1 < pos)) {
++ AuIOErr1("too large i%lld\n", pos);
++ goto out;
++ }
++ pos *= sizeof(inode->i_generation);
++
++ err = 0;
++ sbinfo = au_sbi(sb);
++ file = sbinfo->si_xigen;
++ BUG_ON(!file);
++
++ if (i_size_read(file->f_dentry->d_inode)
++ < pos + sizeof(inode->i_generation)) {
++ inode->i_generation = atomic_inc_return(&sbinfo->si_xigen_next);
++ sz = xino_fwrite(sbinfo->si_xwrite, file, &inode->i_generation,
++ sizeof(inode->i_generation), &pos);
++ } else
++ sz = xino_fread(sbinfo->si_xread, file, &inode->i_generation,
++ sizeof(inode->i_generation), &pos);
++ if (sz == sizeof(inode->i_generation))
++ goto out; /* success */
++
++ err = sz;
++ if (unlikely(sz >= 0)) {
++ err = -EIO;
++ AuIOErr("xigen error (%zd)\n", sz);
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_xigen_set(struct super_block *sb, struct file *base)
++{
++ int err;
++ struct au_sbinfo *sbinfo;
++ struct file *file;
++
++ LKTRTrace("%.*s\n", AuDLNPair(base->f_dentry));
++ SiMustWriteLock(sb);
++
++ sbinfo = au_sbi(sb);
++ file = au_xino_create2(sb, base, sbinfo->si_xigen);
++ err = PTR_ERR(file);
++ if (IS_ERR(file))
++ goto out;
++ err = 0;
++ if (sbinfo->si_xigen)
++ fput(sbinfo->si_xigen);
++ sbinfo->si_xigen = file;
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++void au_xigen_clr(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++
++ sbinfo = au_sbi(sb);
++ if (sbinfo->si_xigen) {
++ fput(sbinfo->si_xigen);
++ sbinfo->si_xigen = NULL;
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++static struct dentry *decode_by_ino(struct super_block *sb, ino_t ino,
++ ino_t dir_ino)
++{
++ struct dentry *dentry, *d;
++ struct inode *inode;
++ au_gen_t sigen;
++
++ LKTRTrace("i%lu, diri%lu\n",
++ (unsigned long)ino, (unsigned long)dir_ino);
++
++ dentry = NULL;
++ inode = ilookup(sb, ino);
++ if (!inode)
++ goto out;
++
++ dentry = ERR_PTR(-ESTALE);
++ sigen = au_sigen(sb);
++ if (unlikely(is_bad_inode(inode)
++ || IS_DEADDIR(inode)
++ || sigen != au_iigen(inode)))
++ goto out_iput;
++
++ dentry = NULL;
++ if (!dir_ino || S_ISDIR(inode->i_mode))
++ dentry = d_find_alias(inode);
++ else {
++ spin_lock(&dcache_lock);
++ list_for_each_entry(d, &inode->i_dentry, d_alias)
++ if (!au_test_anon(d)
++ && d->d_parent->d_inode->i_ino == dir_ino) {
++ dentry = dget_locked(d);
++ break;
++ }
++ spin_unlock(&dcache_lock);
++ }
++ if (unlikely(dentry && sigen != au_digen(dentry))) {
++ dput(dentry);
++ dentry = ERR_PTR(-ESTALE);
++ }
++
++ out_iput:
++ iput(inode);
++ out:
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct au_nfsd_si_lock {
++ const au_gen_t sigen;
++ const aufs_bindex_t br_id;
++ unsigned char force_lock;
++};
++
++static aufs_bindex_t si_nfsd_read_lock(struct super_block *sb,
++ struct au_nfsd_si_lock *nsi_lock)
++{
++ aufs_bindex_t bindex;
++
++ si_read_lock(sb, AuLock_FLUSH);
++
++ /* branch id may be wrapped around */
++ bindex = au_br_index(sb, nsi_lock->br_id);
++ LKTRTrace("b%d\n", bindex);
++ if (bindex >= 0 && nsi_lock->sigen + AUFS_BRANCH_MAX > au_sigen(sb))
++ goto out; /* success */
++
++ if (!nsi_lock->force_lock)
++ si_read_unlock(sb);
++ bindex = -1;
++
++ out:
++ return bindex;
++}
++
++struct find_name_by_ino {
++ int called, found;
++ ino_t ino;
++ char *name;
++ int namelen;
++};
++
++static int
++find_name_by_ino(void *arg, const char *name, int namelen, loff_t offset,
++ au_filldir_ino_t ino, unsigned int d_type)
++{
++ struct find_name_by_ino *a = arg;
++
++ a->called++;
++ if (a->ino != ino)
++ return 0;
++
++ memcpy(a->name, name, namelen);
++ a->namelen = namelen;
++ a->found = 1;
++ return 1;
++}
++
++static struct dentry *au_lkup_by_ino(struct path *path, ino_t ino,
++ struct au_nfsd_si_lock *nsi_lock)
++{
++ struct dentry *dentry, *parent;
++ struct file *file;
++ struct inode *dir;
++ struct find_name_by_ino arg;
++ int err;
++
++ parent = path->dentry;
++ LKTRTrace("%.*s, i%lu\n", AuDLNPair(parent), (unsigned long)ino);
++
++ if (nsi_lock)
++ si_read_unlock(parent->d_sb);
++ path_get(path);
++ file = dentry_open(parent, path->mnt, au_dir_roflags);
++ dentry = (void *)file;
++ if (IS_ERR(file))
++ goto out;
++
++ dentry = ERR_PTR(-ENOMEM);
++ arg.name = __getname();
++ if (unlikely(!arg.name))
++ goto out_file;
++ arg.ino = ino;
++ arg.found = 0;
++ do {
++ arg.called = 0;
++ /* smp_mb(); */
++ err = vfsub_readdir(file, find_name_by_ino, &arg, /*dlgt*/0);
++ } while (!err && !arg.found && arg.called);
++ dentry = ERR_PTR(err);
++ if (unlikely(err))
++ goto out_name;
++ dentry = ERR_PTR(-ENOENT);
++ if (!arg.found)
++ goto out_name;
++
++ /* do not call au_lkup_one(), nor dlgt */
++ dir = parent->d_inode;
++ vfsub_i_lock(dir);
++ dentry = vfsub_lookup_one_len(arg.name, parent, arg.namelen);
++ vfsub_i_unlock(dir);
++ AuTraceErrPtr(dentry);
++ if (IS_ERR(dentry))
++ goto out_name;
++ AuDebugOn(au_test_anon(dentry));
++ if (unlikely(!dentry->d_inode)) {
++ dput(dentry);
++ dentry = ERR_PTR(-ENOENT);
++ }
++
++ out_name:
++ __putname(arg.name);
++ out_file:
++ fput(file);
++ out:
++ if (unlikely(nsi_lock
++ && si_nfsd_read_lock(parent->d_sb, nsi_lock) < 0))
++ if (!IS_ERR(dentry)) {
++ dput(dentry);
++ dentry = ERR_PTR(-ESTALE);
++ }
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++
++static /* noinline_for_stack */
++struct dentry *decode_by_dir_ino(struct super_block *sb, ino_t ino,
++ ino_t dir_ino, struct au_nfsd_si_lock *nsi_lock)
++{
++ struct dentry *dentry, *parent;
++ struct path path;
++
++ LKTRTrace("i%lu, diri%lu\n",
++ (unsigned long)ino, (unsigned long)dir_ino);
++
++ parent = sb->s_root;
++ if (dir_ino != AUFS_ROOT_INO) {
++ parent = decode_by_ino(sb, dir_ino, 0);
++ dentry = parent;
++ if (!parent)
++ goto out;
++ if (IS_ERR(parent))
++ goto out;
++ AuDebugOn(au_test_anon(parent));
++ } else
++ dget(parent);
++
++ path.dentry = parent;
++ path.mnt = au_sbi(sb)->si_mnt;
++ dentry = au_lkup_by_ino(&path, ino, nsi_lock);
++ dput(parent);
++
++ out:
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int h_acceptable(void *expv, struct dentry *dentry)
++{
++ return 1;
++}
++
++static char *au_build_path(struct dentry *h_parent, struct path *h_rootpath,
++ char *buf, int len, struct super_block *sb)
++{
++ char *p;
++ int n;
++
++ AuTraceEnter();
++
++ p = d_path(h_rootpath->dentry, h_rootpath->mnt, buf, len);
++ if (IS_ERR(p))
++ goto out;
++ n = strlen(p);
++
++ p = d_path(h_parent, h_rootpath->mnt, buf, len);
++ if (IS_ERR(p))
++ goto out;
++ LKTRTrace("%s\n", p);
++ if (n != 1)
++ p += n;
++ LKTRTrace("%p, %s, %ld\n",
++ p, p, (long)(p - buf));
++
++ p = d_path(sb->s_root, au_sbi(sb)->si_mnt, buf, len - strlen(p));
++ if (IS_ERR(p))
++ goto out;
++ if (n != 1)
++ p[strlen(p)] = '/';
++ LKTRTrace("%s\n", p);
++
++ out:
++ AuTraceErrPtr(p);
++ return p;
++}
++
++static noinline_for_stack
++struct dentry *decode_by_path(struct super_block *sb, aufs_bindex_t bindex,
++ ino_t ino, __u32 *fh, int fh_len,
++ struct au_nfsd_si_lock *nsi_lock)
++{
++ struct dentry *dentry, *h_parent, *root;
++ struct super_block *h_sb;
++ char *pathname, *p;
++ struct vfsmount *h_mnt;
++ struct au_branch *br;
++ int err;
++ struct nameidata nd;
++ struct path path;
++
++ LKTRTrace("b%d\n", bindex);
++ SiMustAnyLock(sb);
++
++ br = au_sbr(sb, bindex);
++ /* au_br_get(br); */
++ h_mnt = br->br_mnt;
++ h_sb = h_mnt->mnt_sb;
++ LKTRTrace("%s, h_decode_fh\n", au_sbtype(h_sb));
++ h_parent = au_call_decode_fh(h_mnt, fh + Fh_tail, fh_len - Fh_tail,
++ fh[Fh_h_type], h_acceptable,
++ /*context*/NULL);
++ dentry = h_parent;
++ if (unlikely(!h_parent || IS_ERR(h_parent))) {
++ AuWarn1("%s decode_fh failed, %ld\n",
++ au_sbtype(h_sb), PTR_ERR(h_parent));
++ goto out;
++ }
++ dentry = NULL;
++ if (unlikely(au_test_anon(h_parent))) {
++ AuWarn1("%s decode_fh returned a disconnected dentry\n",
++ au_sbtype(h_sb));
++ goto out_h_parent;
++ }
++
++ dentry = ERR_PTR(-ENOMEM);
++ pathname = (void *)__get_free_page(GFP_NOFS);
++ if (unlikely(!pathname))
++ goto out_h_parent;
++
++ root = sb->s_root;
++ path.mnt = h_mnt;
++ di_read_lock_parent(root, !AuLock_IR);
++ path.dentry = au_h_dptr(root, bindex);
++ di_read_unlock(root, !AuLock_IR);
++ p = au_build_path(h_parent, &path, pathname, PAGE_SIZE, sb);
++ dentry = (void *)p;
++ if (IS_ERR(p))
++ goto out_pathname;
++
++ LKTRTrace("%s\n", p);
++ si_read_unlock(sb);
++ err = vfsub_path_lookup(p, LOOKUP_FOLLOW | LOOKUP_DIRECTORY, &nd);
++ dentry = ERR_PTR(err);
++ if (unlikely(err))
++ goto out_relock;
++
++ dentry = ERR_PTR(-ENOENT);
++ AuDebugOn(au_test_anon(nd.dentry));
++ if (unlikely(!nd.dentry->d_inode))
++ goto out_nd;
++
++ if (ino != nd.dentry->d_inode->i_ino) {
++ path.mnt = nd.mnt;
++ path.dentry = nd.dentry;
++ dentry = au_lkup_by_ino(&path, ino, /*nsi_lock*/NULL);
++ } else
++ dentry = dget(nd.dentry);
++
++ out_nd:
++ path_release(&nd);
++ out_relock:
++ if (unlikely(si_nfsd_read_lock(sb, nsi_lock) < 0))
++ if (!IS_ERR(dentry)) {
++ dput(dentry);
++ dentry = ERR_PTR(-ESTALE);
++ }
++ out_pathname:
++ free_page((unsigned long)pathname);
++ out_h_parent:
++ dput(h_parent);
++ out:
++ /* au_br_put(br); */
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static struct dentry *
++aufs_decode_fh(struct super_block *sb, __u32 *fh, int fh_len, int fh_type,
++ int (*acceptable)(void *context, struct dentry *de),
++ void *context)
++{
++ struct dentry *dentry;
++ ino_t ino, dir_ino;
++ aufs_bindex_t bindex;
++ struct au_nfsd_si_lock nsi_lock = {
++ .sigen = fh[Fh_sigen],
++ .br_id = fh[Fh_br_id],
++ .force_lock = 0
++ };
++
++ LKTRTrace("%d, fh{br_id %u, sigen %u, i%u, diri%u, g%u}\n",
++ fh_type, fh[Fh_br_id], fh[Fh_sigen], fh[Fh_ino],
++ fh[Fh_dir_ino], fh[Fh_igen]);
++ AuDebugOn(fh_len < Fh_tail);
++
++ dentry = ERR_PTR(-ESTALE);
++ /* branch id may be wrapped around */
++ bindex = si_nfsd_read_lock(sb, &nsi_lock);
++ if (unlikely(bindex < 0))
++ goto out;
++ nsi_lock.force_lock = 1;
++
++ /* is this inode still cached? */
++ ino = decode_ino(fh + Fh_ino);
++ AuDebugOn(ino == AUFS_ROOT_INO);
++ dir_ino = decode_ino(fh + Fh_dir_ino);
++ dentry = decode_by_ino(sb, ino, dir_ino);
++ if (IS_ERR(dentry))
++ goto out_unlock;
++ if (dentry)
++ goto accept;
++
++ /* is the parent dir cached? */
++ dentry = decode_by_dir_ino(sb, ino, dir_ino, &nsi_lock);
++ if (IS_ERR(dentry))
++ goto out_unlock;
++ if (dentry)
++ goto accept;
++
++ /* lookup path */
++ dentry = decode_by_path(sb, bindex, ino, fh, fh_len, &nsi_lock);
++ if (IS_ERR(dentry))
++ goto out_unlock;
++ if (unlikely(!dentry))
++ goto out_unlock;
++
++ accept:
++ LKTRLabel(accept);
++ if (dentry->d_inode->i_generation == fh[Fh_igen]
++ && acceptable(context, dentry))
++ goto out_unlock; /* success */
++
++ LKTRLabel(stale);
++ dput(dentry);
++ dentry = ERR_PTR(-ESTALE);
++ out_unlock:
++ LKTRLabel(out_unlock);
++ si_read_unlock(sb);
++ out:
++ LKTRLabel(out);
++ if (0 && IS_ERR(dentry))
++ dentry = ERR_PTR(-ESTALE);
++ AuTraceErrPtr(dentry);
++ return dentry;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static struct dentry *
++aufs_fh_to_dentry(struct super_block *sb, struct fid *fid, int fh_len,
++ int fh_type)
++{
++ return aufs_decode_fh(sb, fid->raw, fh_len, fh_type, h_acceptable,
++ /*context*/NULL);
++}
++#endif /* KERNEL_VERSION */
++
++/* ---------------------------------------------------------------------- */
++
++static int aufs_encode_fh(struct dentry *dentry, __u32 *fh, int *max_len,
++ int connectable)
++{
++ int err;
++ aufs_bindex_t bindex, bend;
++ struct super_block *sb, *h_sb;
++ struct inode *inode;
++ struct dentry *parent, *h_parent;
++ struct au_branch *br;
++
++ LKTRTrace("%.*s, max %d, conn %d\n",
++ AuDLNPair(dentry), *max_len, connectable);
++ AuDebugOn(au_test_anon(dentry));
++
++ parent = NULL;
++ err = -ENOSPC;
++ if (unlikely(*max_len <= Fh_tail)) {
++ AuWarn1("NFSv2 client (max_len %d)?\n", *max_len);
++ goto out;
++ }
++
++ err = 0; //FILEID_ROOT;
++ if (IS_ROOT(dentry)) {
++ AuDebugOn(dentry->d_inode->i_ino != AUFS_ROOT_INO);
++ goto out;
++ }
++
++ err = -EIO;
++ h_parent = NULL;
++ sb = dentry->d_sb;
++ aufs_read_lock(dentry, AuLock_FLUSH | AuLock_IR);
++ parent = dget_parent(dentry);
++ di_read_lock_parent(parent, !AuLock_IR);
++ inode = dentry->d_inode;
++ AuDebugOn(!inode);
++#ifdef CONFIG_AUFS_DEBUG
++ {
++ unsigned int mnt_flags = au_mntflags(sb);
++
++ if (unlikely(!au_opt_test_xino(mnt_flags)))
++ AuWarn1("NFS-exporting requires xino\n");
++ if (unlikely(0 && !au_opt_test(mnt_flags, UDBA_INOTIFY)))
++ AuWarn1("udba=inotify is recommended "
++ "for NFS-exporting\n");
++ }
++#endif
++
++ bend = au_dbtaildir(parent);
++ for (bindex = au_dbstart(parent); bindex <= bend; bindex++) {
++ h_parent = au_h_dptr(parent, bindex);
++ if (h_parent) {
++ dget(h_parent);
++ break;
++ }
++ }
++ if (unlikely(!h_parent))
++ goto out_unlock;
++ LKTRTrace("b%d\n", bindex);
++
++ err = -EPERM;
++ br = au_sbr(sb, bindex);
++ h_sb = br->br_mnt->mnt_sb;
++ if (unlikely(!h_sb->s_export_op)) {
++ AuErr1("%s branch is not exportable\n", au_sbtype(h_sb));
++ goto out_dput;
++ }
++
++ fh[Fh_br_id] = br->br_id;
++ fh[Fh_sigen] = au_sigen(sb);
++ encode_ino(fh + Fh_ino, inode->i_ino);
++ encode_ino(fh + Fh_dir_ino, parent->d_inode->i_ino);
++ fh[Fh_igen] = inode->i_generation;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
++ /* it should be set at exporting time */
++ if (unlikely(!h_sb->s_export_op->find_exported_dentry)) {
++ AuWarn("set default find_exported_dentry for %s\n",
++ au_sbtype(h_sb));
++ h_sb->s_export_op->find_exported_dentry = find_exported_dentry;
++ }
++#endif
++
++ *max_len -= Fh_tail;
++ fh[Fh_h_type] = au_call_encode_fh(h_parent, fh + Fh_tail, max_len,
++ /*connectable or subtreecheck*/0);
++ err = fh[Fh_h_type];
++ *max_len += Fh_tail;
++ /* todo: macros? */
++ if (err != 255)
++ err = 99;
++ else
++ AuWarn1("%s encode_fh failed\n", au_sbtype(h_sb));
++
++ out_dput:
++ dput(h_parent);
++ out_unlock:
++ di_read_unlock(parent, !AuLock_IR);
++ dput(parent);
++ aufs_read_unlock(dentry, AuLock_IR);
++ out:
++ AuTraceErr(err);
++ if (unlikely(err < 0))
++ err = 255;
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static struct export_operations aufs_export_op = {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++ .fh_to_dentry = aufs_fh_to_dentry,
++#else
++ .decode_fh = aufs_decode_fh,
++#endif
++ .encode_fh = aufs_encode_fh
++};
++
++void au_export_init(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++ __u32 u;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ sb->s_export_op = &aufs_export_op;
++ sbinfo = au_sbi(sb);
++ sbinfo->si_xigen = NULL;
++ get_random_bytes(&u, sizeof(u));
++ BUILD_BUG_ON(sizeof(u) != sizeof(int));
++ atomic_set(&sbinfo->si_xigen_next, u);
++ //memset(&sbinfo->si_xinodir, 0, sizeof(struct path));
++}
+diff --git a/fs/aufs/f_op.c b/fs/aufs/f_op.c
+new file mode 100644
+index 0000000..df38c61
+--- /dev/null
++++ b/fs/aufs/f_op.c
+@@ -0,0 +1,813 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * file and vm operations
++ *
++ * $Id: f_op.c,v 1.60 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/fsnotify.h>
++#include <linux/pagemap.h>
++#include <linux/poll.h>
++#include <linux/security.h>
++#include <linux/version.h>
++#include "aufs.h"
++
++/* common function to regular file and dir */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++#define FlushArgs h_file, id
++int aufs_flush(struct file *file, fl_owner_t id)
++#else
++#define FlushArgs h_file
++int aufs_flush(struct file *file)
++#endif
++{
++ int err;
++ struct dentry *dentry;
++ aufs_bindex_t bindex, bend;
++ struct file *h_file;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ si_noflush_read_lock(dentry->d_sb);
++ fi_read_lock(file);
++ di_read_lock_child(dentry, AuLock_IW);
++
++ err = 0;
++ bend = au_fbend(file);
++ for (bindex = au_fbstart(file); !err && bindex <= bend; bindex++) {
++ h_file = au_h_fptr(file, bindex);
++ if (h_file && h_file->f_op && h_file->f_op->flush) {
++ err = h_file->f_op->flush(FlushArgs);
++ if (!err)
++ au_update_fuse_h_inode
++ (h_file->f_vfsmnt, h_file->f_dentry);
++ /*ignore*/
++ }
++ }
++ au_cpup_attr_timesizes(dentry->d_inode);
++
++ di_read_unlock(dentry, AuLock_IW);
++ fi_read_unlock(file);
++ si_read_unlock(dentry->d_sb);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int do_open_nondir(struct file *file, int flags)
++{
++ int err;
++ aufs_bindex_t bindex;
++ struct super_block *sb;
++ struct file *h_file;
++ struct dentry *dentry;
++ struct inode *inode;
++ struct au_finfo *finfo;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, flags 0%o\n", AuDLNPair(dentry), flags);
++ FiMustWriteLock(file);
++ inode = dentry->d_inode;
++ AuDebugOn(!inode || S_ISDIR(inode->i_mode));
++
++ err = 0;
++ finfo = au_fi(file);
++ finfo->fi_h_vm_ops = NULL;
++ sb = dentry->d_sb;
++ bindex = au_dbstart(dentry);
++ AuDebugOn(!au_h_dptr(dentry, bindex)->d_inode);
++ /* O_TRUNC is processed already */
++ BUG_ON(au_test_ro(sb, bindex, inode) && (flags & O_TRUNC));
++
++ h_file = au_h_open(dentry, bindex, flags, file);
++ if (IS_ERR(h_file))
++ err = PTR_ERR(h_file);
++ else {
++ au_set_fbstart(file, bindex);
++ au_set_fbend(file, bindex);
++ au_set_h_fptr(file, bindex, h_file);
++ au_update_figen(file);
++ /* todo: necessary? */
++ /* file->f_ra = h_file->f_ra; */
++ err = 0;
++ }
++ AuTraceErr(err);
++ return err;
++}
++
++static int aufs_open_nondir(struct inode *inode, struct file *file)
++{
++ LKTRTrace("i%lu, %.*s\n", inode->i_ino, AuDLNPair(file->f_dentry));
++
++ return au_do_open(inode, file, do_open_nondir);
++}
++
++static int aufs_release_nondir(struct inode *inode, struct file *file)
++{
++ struct super_block *sb = file->f_dentry->d_sb;
++
++ LKTRTrace("i%lu, %.*s\n", inode->i_ino, AuDLNPair(file->f_dentry));
++
++ si_noflush_read_lock(sb);
++ au_finfo_fin(file);
++ si_read_unlock(sb);
++ return 0;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static ssize_t aufs_read(struct file *file, char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ ssize_t err;
++ struct dentry *dentry;
++ struct file *h_file;
++ struct super_block *sb;
++ struct inode *h_inode;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, cnt %zu, pos %lld\n", AuDLNPair(dentry), count, *ppos);
++
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0,
++ /*locked*/0);
++ if (unlikely(err))
++ goto out;
++
++ /* support LSM and notify */
++ h_file = au_h_fptr(file, au_fbstart(file));
++ h_inode = h_file->f_dentry->d_inode;
++ err = vfsub_read_u(h_file, buf, count, ppos,
++ au_test_dlgt(au_mntflags(sb)));
++ /* todo: necessary? */
++ /* file->f_ra = h_file->f_ra; */
++ dentry->d_inode->i_atime = h_file->f_dentry->d_inode->i_atime;
++
++ di_read_unlock(dentry, AuLock_IR);
++ fi_read_unlock(file);
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++
++static ssize_t aufs_write(struct file *file, const char __user *ubuf,
++ size_t count, loff_t *ppos)
++{
++ ssize_t err;
++ struct dentry *dentry;
++ struct inode *inode;
++ struct super_block *sb;
++ unsigned int mnt_flags;
++ struct file *h_file;
++ char __user *buf = (char __user *)ubuf;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ aufs_bindex_t bstart;
++ int hinotify;
++ struct au_pin pin;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, cnt %zu, pos %lld\n", AuDLNPair(dentry), count, *ppos);
++
++ inode = dentry->d_inode;
++ vfsub_i_lock(inode);
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ mnt_flags = au_mntflags(sb);
++ hinotify = !!au_opt_test(mnt_flags, UDBA_INOTIFY);
++ vfsub_args_init(&vargs, &ign, au_test_dlgt(mnt_flags), 0);
++
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1,
++ /*locked*/1);
++ if (unlikely(err))
++ goto out;
++ err = au_ready_to_write(file, -1, &pin);
++ di_downgrade_lock(dentry, AuLock_IR);
++ if (unlikely(err))
++ goto out_unlock;
++
++ bstart = au_fbstart(file);
++ h_file = au_h_fptr(file, bstart);
++ if (!hinotify) {
++ au_unpin(&pin);
++ err = vfsub_write_u(h_file, buf, count, ppos, &vargs);
++ } else {
++ vfsub_ign_hinode(&vargs, IN_MODIFY, au_pinned_hdir(&pin));
++ err = vfsub_write_u(h_file, buf, count, ppos, &vargs);
++ au_unpin(&pin);
++ }
++ au_cpup_attr_timesizes(inode);
++
++ out_unlock:
++ di_read_unlock(dentry, AuLock_IR);
++ fi_write_unlock(file);
++ out:
++ si_read_unlock(sb);
++ vfsub_i_unlock(inode);
++ AuTraceErr(err);
++ return err;
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23) \
++ || defined(CONFIG_AUFS_SPLICE_PATCH)
++static int au_test_loopback(void)
++{
++ const char c = current->comm[4];
++ /* true if a kernel thread named 'loop[0-9].*' accesses a file */
++ const int loopback = (current->mm == NULL
++ && '0' <= c && c <= '9'
++ && strncmp(current->comm, "loop", 4) == 0);
++ return loopback;
++}
++#endif
++
++#ifdef CONFIG_AUFS_SPLICE_PATCH
++static ssize_t aufs_splice_read(struct file *file, loff_t *ppos,
++ struct pipe_inode_info *pipe, size_t len,
++ unsigned int flags)
++{
++ ssize_t err;
++ struct file *h_file;
++ struct dentry *dentry;
++ struct super_block *sb;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, pos %lld, len %zu\n", AuDLNPair(dentry), *ppos, len);
++
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0,
++ /*locked*/0);
++ if (unlikely(err))
++ goto out;
++
++ err = -EINVAL;
++ /* support LSM and notify */
++ h_file = au_h_fptr(file, au_fbstart(file));
++ if (au_test_loopback()) {
++ file->f_mapping = h_file->f_mapping;
++ smp_mb(); /* unnecessary? */
++ }
++ err = vfsub_splice_to(h_file, ppos, pipe, len, flags,
++ au_test_dlgt(au_mntflags(sb)));
++ /* todo: necessasry? */
++ /* file->f_ra = h_file->f_ra; */
++ dentry->d_inode->i_atime = h_file->f_dentry->d_inode->i_atime;
++ di_read_unlock(dentry, AuLock_IR);
++ fi_read_unlock(file);
++
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++
++static ssize_t
++aufs_splice_write(struct pipe_inode_info *pipe, struct file *file, loff_t *ppos,
++ size_t len, unsigned int flags)
++{
++ ssize_t err;
++ struct dentry *dentry;
++ struct inode *inode, *h_inode;
++ struct super_block *sb;
++ struct file *h_file;
++ /* struct au_hin_ignore ign; */
++ struct vfsub_args vargs;
++ unsigned int mnt_flags;
++ struct au_pin pin;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, len %zu, pos %lld\n", AuDLNPair(dentry), len, *ppos);
++
++ inode = dentry->d_inode;
++ vfsub_i_lock(inode);
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ mnt_flags = au_mntflags(sb);
++ vfsub_args_init(&vargs, /*&ign*/NULL, au_test_dlgt(mnt_flags), 0);
++
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1,
++ /*locked*/1);
++ if (unlikely(err))
++ goto out;
++ err = au_ready_to_write(file, -1, &pin);
++ di_downgrade_lock(dentry, AuLock_IR);
++ if (unlikely(err))
++ goto out_unlock;
++
++ /* support LSM and notify */
++ /* current vfs_splice_from() doesn't fire up the inotify event */
++ h_file = au_h_fptr(file, au_fbstart(file));
++ h_inode = h_file->f_dentry->d_inode;
++ if (1 || !au_opt_test(mnt_flags, UDBA_INOTIFY)) {
++ au_unpin(&pin);
++ err = vfsub_splice_from(pipe, h_file, ppos, len, flags, &vargs);
++ }
++#if 0 /* reserved for future use */
++ else {
++ struct dentry *parent = dget_parent(dentry);
++ vfsub_ign_hinode(&vargs, IN_MODIFY, au_pinned_hdir(&pin));
++ err = vfsub_splice_from(pipe, h_file, ppos, len, flags, &vargs);
++ au_unpin(&pin);
++ }
++#endif
++ au_cpup_attr_timesizes(inode);
++
++ out_unlock:
++ di_read_unlock(dentry, AuLock_IR);
++ fi_write_unlock(file);
++ out:
++ si_read_unlock(sb);
++ vfsub_i_unlock(inode);
++ AuTraceErr(err);
++ return err;
++}
++#endif /* CONFIG_AUFS_SPLICE_PATCH */
++
++/* ---------------------------------------------------------------------- */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++static int aufs_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
++{
++ int err;
++ struct dentry *dentry;
++ struct file *file, *h_file;
++ struct inode *inode;
++ static DECLARE_WAIT_QUEUE_HEAD(wq);
++ struct au_finfo *finfo;
++
++ AuTraceEnter();
++ AuDebugOn(!vma || !vma->vm_file);
++ /* todo: non-robr mode, user vm_file as it is? */
++ wait_event(wq, (file = au_robr_safe_file(vma)));
++ AuDebugOn(!au_test_aufs(file->f_dentry->d_sb));
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ inode = dentry->d_inode;
++ AuDebugOn(!S_ISREG(inode->i_mode));
++
++ /* do not revalidate, no si lock */
++ finfo = au_fi(file);
++ h_file = finfo->fi_hfile[0 + finfo->fi_bstart].hf_file;
++ AuDebugOn(!h_file || !au_test_mmapped(file));
++ fi_write_lock(file);
++ vma->vm_file = h_file;
++ err = finfo->fi_h_vm_ops->fault(vma, vmf);
++ /* todo: necessary? */
++ /* file->f_ra = h_file->f_ra; */
++ au_robr_reset_file(vma, file);
++ fi_write_unlock(file);
++#if 0 /* def CONFIG_SMP */
++ /* wake_up_nr(&wq, online_cpu - 1); */
++ wake_up_all(&wq);
++#else
++ wake_up(&wq);
++#endif
++
++ if (!(err & VM_FAULT_ERROR)) {
++#if 0 /* debug */
++ struct page *page;
++ page = vmf->page;
++ AuDbg("%p, %d\n", page, page_mapcount(page));
++
++ page->mapping = file->f_mapping;
++ get_page(page);
++ file->f_mapping = h_file->f_mapping;
++ touch_atime(NULL, dentry);
++ inode->i_atime = h_file->f_dentry->d_inode->i_atime;
++#endif
++ }
++ AuTraceErr(err);
++ return err;
++}
++#else
++static struct page *aufs_nopage(struct vm_area_struct *vma, unsigned long addr,
++ int *type)
++{
++ struct page *page;
++ struct dentry *dentry;
++ struct file *file, *h_file;
++ struct inode *inode;
++ static DECLARE_WAIT_QUEUE_HEAD(wq);
++ struct au_finfo *finfo;
++
++ AuTraceEnter();
++ AuDebugOn(!vma || !vma->vm_file);
++ wait_event(wq, (file = au_robr_safe_file(vma)));
++ AuDebugOn(!au_test_aufs(file->f_dentry->d_sb));
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, addr %lx\n", AuDLNPair(dentry), addr);
++ inode = dentry->d_inode;
++ AuDebugOn(!S_ISREG(inode->i_mode));
++
++ /* do not revalidate, no si lock */
++ finfo = au_fi(file);
++ h_file = finfo->fi_hfile[0 + finfo->fi_bstart].hf_file;
++ AuDebugOn(!h_file || !au_test_mmapped(file));
++ fi_write_lock(file);
++ vma->vm_file = h_file;
++ page = finfo->fi_h_vm_ops->nopage(vma, addr, type);
++ //file->f_ra = h_file->f_ra; //??
++ au_robr_reset_file(vma, file);
++ fi_write_unlock(file);
++#if 0 //def CONFIG_SMP
++ //wake_up_nr(&wq, online_cpu - 1);
++ wake_up_all(&wq);
++#else
++ wake_up(&wq);
++#endif
++ if (page && !IS_ERR(page)) {
++ //AuDbg("%p, %d\n", page, page_mapcount(page));
++ //page->mapping = file->f_mapping;
++ //get_page(page);
++ //file->f_mapping = h_file->f_mapping;
++ //touch_atime(NULL, dentry);
++ //inode->i_atime = h_file->f_dentry->d_inode->i_atime;
++ }
++ AuTraceErrPtr(page);
++ return page;
++}
++
++static int aufs_populate(struct vm_area_struct *vma, unsigned long addr,
++ unsigned long len, pgprot_t prot, unsigned long pgoff,
++ int nonblock)
++{
++ AuUnsupport();
++ return au_fi(vma->vm_file)->fi_h_vm_ops->populate
++ (vma, addr, len, prot, pgoff, nonblock);
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23) */
++
++static struct vm_operations_struct aufs_vm_ops = {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++ .fault = aufs_fault,
++#else
++ .nopage = aufs_nopage,
++ .populate = aufs_populate,
++#endif
++#if 0 // rfu
++ unsigned long (*nopfn)(struct vm_area_struct *area,
++ unsigned long address);
++ page_mkwrite(struct vm_area_struct *vma, struct page *page)
++#endif
++};
++
++/* ---------------------------------------------------------------------- */
++
++static struct vm_operations_struct *au_vm_ops(struct file *h_file,
++ struct vm_area_struct *vma)
++{
++ struct vm_operations_struct *vm_ops;
++ int err;
++
++ AuTraceEnter();
++
++ if (!au_test_nfs(h_file->f_vfsmnt->mnt_sb))
++ err = h_file->f_op->mmap(h_file, vma);
++ else {
++ lockdep_off();
++ err = h_file->f_op->mmap(h_file, vma);
++ lockdep_on();
++ }
++ vm_ops = ERR_PTR(err);
++ if (unlikely(err))
++ goto out;
++ vm_ops = vma->vm_ops;
++ err = do_munmap(current->mm, vma->vm_start,
++ vma->vm_end - vma->vm_start);
++ if (unlikely(err)) {
++ AuIOErr("failed internal unmapping %.*s, %d\n",
++ AuDLNPair(h_file->f_dentry), err);
++ vm_ops = ERR_PTR(-EIO);
++ }
++
++ out:
++ AuTraceErrPtr(vm_ops);
++ return vm_ops;
++}
++
++static int aufs_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ int err;
++ unsigned char wlock, mmapped;
++ struct dentry *dentry;
++ struct super_block *sb;
++ struct file *h_file;
++ struct vm_operations_struct *vm_ops;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, %lx, len %lu\n",
++ AuDLNPair(dentry), vma->vm_start,
++ vma->vm_end - vma->vm_start);
++ AuDebugOn(!S_ISREG(dentry->d_inode->i_mode));
++ AuDebugOn(down_write_trylock(&vma->vm_mm->mmap_sem));
++
++ mmapped = au_test_mmapped(file); /* can be harmless race condition */
++ wlock = !!(file->f_mode & FMODE_WRITE);
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, wlock | !mmapped,
++ /*locked*/0);
++ if (unlikely(err))
++ goto out;
++
++ if (wlock) {
++ struct au_pin pin;
++
++ err = au_ready_to_write(file, -1, &pin);
++ di_downgrade_lock(dentry, AuLock_IR);
++ if (unlikely(err))
++ goto out_unlock;
++ au_unpin(&pin);
++ } else if (!mmapped)
++ di_downgrade_lock(dentry, AuLock_IR);
++
++ h_file = au_h_fptr(file, au_fbstart(file));
++ if (au_test_fuse(h_file->f_dentry->d_sb)) {
++ /*
++ * by this assignment, f_mapping will differs from aufs inode
++ * i_mapping.
++ * if someone else mixes the use of f_dentry->d_inode and
++ * f_mapping->host, then a problem may arise.
++ */
++ file->f_mapping = h_file->f_mapping;
++ }
++
++ if (0 && h_file->f_op->mmap == generic_file_mmap) {
++ err = generic_file_mmap(file, vma); /* instead of h_file */
++ if (unlikely(err))
++ goto out_unlock;
++ au_fi(file)->fi_h_vm_ops = vma->vm_ops;
++ } else {
++ vm_ops = NULL;
++ if (!mmapped) {
++ vm_ops = au_vm_ops(h_file, vma);
++ err = PTR_ERR(vm_ops);
++ if (IS_ERR(vm_ops))
++ goto out_unlock;
++ }
++
++ err = generic_file_mmap(file, vma);
++ if (unlikely(err))
++ goto out_unlock;
++ vma->vm_ops = &aufs_vm_ops;
++ /* test again */
++ if (!au_test_mmapped(file)) {
++ FiMustWriteLock(file);
++ au_fi(file)->fi_h_vm_ops = vm_ops;
++ }
++ }
++
++ file_accessed(h_file);
++ au_update_fuse_h_inode(h_file->f_vfsmnt, h_file->f_dentry); /*ignore*/
++ dentry->d_inode->i_atime = h_file->f_dentry->d_inode->i_atime;
++
++ out_unlock:
++ di_read_unlock(dentry, AuLock_IR);
++ if (!wlock && mmapped)
++ fi_read_unlock(file);
++ else
++ fi_write_unlock(file);
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++
++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 22)
++// todo: try do_sendfile() in fs/read_write.c
++static ssize_t aufs_sendfile(struct file *file, loff_t *ppos,
++ size_t count, read_actor_t actor, void *target)
++{
++ ssize_t err;
++ struct file *h_file;
++ struct dentry *dentry;
++ struct super_block *sb;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, pos %Ld, cnt %lu\n",
++ AuDLNPair(dentry), *ppos, (unsigned long)count);
++
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0,
++ /*locked*/0);
++ if (unlikely(err))
++ goto out;
++
++ err = -EINVAL;
++ h_file = au_h_fptr(file, au_fbstart(file));
++ if (h_file->f_op && h_file->f_op->sendfile) {
++ if (/* unlikely */(au_test_loopback())) {
++ file->f_mapping = h_file->f_mapping;
++ smp_mb(); /* unnecessary? */
++ }
++ if (!au_test_nfs(h_file->f_vfsmnt->mnt_sb))
++ err = h_file->f_op->sendfile(h_file, ppos, count, actor,
++ target);
++ else {
++ lockdep_off();
++ err = h_file->f_op->sendfile(h_file, ppos, count, actor,
++ target);
++ lockdep_on();
++ }
++ if (!err)
++ au_update_fuse_h_inode(h_file->f_vfsmnt,
++ h_file->f_dentry);
++ /*ignore*/
++ dentry->d_inode->i_atime = h_file->f_dentry->d_inode->i_atime;
++ }
++ di_read_unlock(dentry, AuLock_IR);
++ fi_read_unlock(file);
++
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++#endif /* LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 22) */
++
++/* ---------------------------------------------------------------------- */
++
++/* linux-2.6.22 and earlier */
++#ifndef DEFAULT_POLLMASK
++/* copied from linux/fs/select.h, must match */
++#define DEFAULT_POLLMASK (POLLIN | POLLOUT | POLLRDNORM | POLLWRNORM)
++#endif
++
++static unsigned int aufs_poll(struct file *file, poll_table *wait)
++{
++ unsigned int mask;
++ struct file *h_file;
++ int err;
++ struct dentry *dentry;
++ struct super_block *sb;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, wait %p\n", AuDLNPair(dentry), wait);
++ AuDebugOn(S_ISDIR(dentry->d_inode->i_mode));
++
++ /* We should pretend an error happened. */
++ mask = POLLERR /* | POLLIN | POLLOUT */;
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0,
++ /*locked*/0);
++ if (unlikely(err))
++ goto out;
++
++ /* it is not an error of hidden_file has no operation */
++ mask = DEFAULT_POLLMASK;
++ h_file = au_h_fptr(file, au_fbstart(file));
++ if (h_file->f_op && h_file->f_op->poll)
++ mask = h_file->f_op->poll(h_file, wait);
++ di_read_unlock(dentry, AuLock_IR);
++ fi_read_unlock(file);
++
++ out:
++ si_read_unlock(sb);
++ AuTraceErr((int)mask);
++ return mask;
++}
++
++static int aufs_fsync_nondir(struct file *file, struct dentry *dentry,
++ int datasync)
++{
++ int err, my_lock;
++ struct inode *inode;
++ struct file *h_file;
++ struct super_block *sb;
++ struct au_pin pin;
++
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), datasync);
++ inode = dentry->d_inode;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17)
++ IMustLock(file->f_mapping->host);
++ if (inode != file->f_mapping->host) {
++ vfsub_i_unlock(file->f_mapping->host);
++ vfsub_i_lock(inode);
++ }
++ IMustLock(inode);
++ my_lock = 0;
++#else
++ /* before 2.6.17,
++ * msync(2) calls me without locking i_sem/i_mutex, but fsync(2).
++ */
++ my_lock = vfsub_i_trylock(inode);
++#endif
++
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = 0; /* -EBADF; */ /* posix? */
++ if (unlikely(!(file->f_mode & FMODE_WRITE)))
++ goto out;
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1,
++ /*locked*/1);
++ if (unlikely(err))
++ goto out;
++ err = au_ready_to_write(file, -1, &pin);
++ di_downgrade_lock(dentry, AuLock_IR);
++ if (unlikely(err))
++ goto out_unlock;
++ au_unpin(&pin);
++
++ err = -EINVAL;
++ h_file = au_h_fptr(file, au_fbstart(file));
++ if (h_file->f_op && h_file->f_op->fsync) {
++ vfsub_i_lock_nested(h_file->f_dentry->d_inode, AuLsc_I_CHILD);
++ err = h_file->f_op->fsync(h_file, h_file->f_dentry, datasync);
++ if (!err)
++ au_update_fuse_h_inode(h_file->f_vfsmnt,
++ h_file->f_dentry);
++ au_cpup_attr_timesizes(inode);
++ vfsub_i_unlock(h_file->f_dentry->d_inode);
++ }
++
++ out_unlock:
++ di_read_unlock(dentry, AuLock_IR);
++ fi_write_unlock(file);
++ out:
++ si_read_unlock(sb);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17)
++ if (inode != file->f_mapping->host) {
++ vfsub_i_unlock(inode);
++ vfsub_i_lock(file->f_mapping->host);
++ }
++#else
++ if (my_lock)
++ vfsub_i_unlock(inode);
++#endif
++ AuTraceErr(err);
++ return err;
++}
++
++static int aufs_fasync(int fd, struct file *file, int flag)
++{
++ int err;
++ struct file *h_file;
++ struct dentry *dentry;
++ struct super_block *sb;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), flag);
++
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0,
++ /*locked*/0);
++ if (unlikely(err))
++ goto out;
++
++ h_file = au_h_fptr(file, au_fbstart(file));
++ if (h_file->f_op && h_file->f_op->fasync)
++ err = h_file->f_op->fasync(fd, h_file, flag);
++ di_read_unlock(dentry, AuLock_IR);
++ fi_read_unlock(file);
++
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct file_operations aufs_file_fop = {
++ .read = aufs_read,
++ .write = aufs_write,
++ .poll = aufs_poll,
++ .mmap = aufs_mmap,
++ .open = aufs_open_nondir,
++ .flush = aufs_flush,
++ .release = aufs_release_nondir,
++ .fsync = aufs_fsync_nondir,
++ .fasync = aufs_fasync,
++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 22)
++ .sendfile = aufs_sendfile,
++#endif
++#ifdef CONFIG_AUFS_SPLICE_PATCH
++ .splice_write = aufs_splice_write,
++ .splice_read = aufs_splice_read,
++#endif
++};
+diff --git a/fs/aufs/file.c b/fs/aufs/file.c
+new file mode 100644
+index 0000000..1ad2fd8
+--- /dev/null
++++ b/fs/aufs/file.c
+@@ -0,0 +1,806 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * handling file/dir, and address_space operation
++ *
++ * $Id: file.c,v 1.83 2009/01/26 06:23:56 sfjro Exp $
++ */
++
++//#include <linux/fsnotify.h>
++#include <linux/pagemap.h>
++//#include <linux/poll.h>
++//#include <linux/security.h>
++#include "aufs.h"
++
++/*
++ * a dirty trick for handling FMODE_EXEC and deny_write_access().
++ * because FMODE_EXEC flag is not passed to f_op->open(),
++ * set it to file->private_data temporary.
++ */
++#if !defined(CONFIG_AUFS_MODULE) || defined(CONFIG_AUFS_DENY_WRITE_ACCESS_PATCH)
++int au_store_fmode_exec(struct nameidata *nd, struct inode *inode)
++{
++ int err;
++ union {
++ void *p;
++ unsigned long ul;
++ } u;
++
++ err = 0;
++ if (nd
++ && (nd->flags & LOOKUP_OPEN)
++ && nd->intent.open.file
++ && (nd->intent.open.flags & FMODE_EXEC)
++ && inode
++ && S_ISREG(inode->i_mode)) {
++ u.ul = nd->intent.open.flags;
++ nd->intent.open.file->private_data = u.p;
++ /* smp_mb(); */
++ err = 1;
++ }
++
++ return err;
++}
++#endif
++
++/* drop flags for writing */
++unsigned int au_file_roflags(unsigned int flags)
++{
++ flags &= ~(O_WRONLY | O_RDWR | O_APPEND | O_CREAT | O_TRUNC);
++ flags |= O_RDONLY | O_NOATIME;
++ return flags;
++}
++
++/* common functions to regular file and dir */
++struct file *au_h_open(struct dentry *dentry, aufs_bindex_t bindex, int flags,
++ struct file *file)
++{
++ struct file *h_file;
++ struct dentry *h_dentry;
++ struct inode *h_inode;
++ struct super_block *sb;
++ struct au_branch *br;
++ int err;
++
++ LKTRTrace("%.*s, b%d, flags 0%o, f %d\n",
++ AuDLNPair(dentry), bindex, flags, !!file);
++ h_dentry = au_h_dptr(dentry, bindex);
++ AuDebugOn(!h_dentry);
++ h_inode = h_dentry->d_inode;
++
++ /* a race condition can happen between open and unlink/rmdir */
++ h_file = ERR_PTR(-ENOENT);
++ if (unlikely((!d_unhashed(dentry) && d_unhashed(h_dentry))
++ || !h_inode))
++ goto out;
++
++ sb = dentry->d_sb;
++ br = au_sbr(sb, bindex);
++ au_br_get(br);
++ /* drop flags for writing */
++ if (au_test_ro(sb, bindex, dentry->d_inode))
++ flags = au_file_roflags(flags);
++ flags &= ~O_CREAT;
++
++ h_file = NULL;
++ if (file && au_test_nfs(h_dentry->d_sb))
++ h_file = au_h_intent(dentry, bindex, file);
++ if (!h_file)
++ h_file = dentry_open(dget(h_dentry), mntget(br->br_mnt), flags);
++
++ /*
++ * a dirty trick for handling FMODE_EXEC and deny_write_access().
++ */
++ if (file && (file->f_mode & FMODE_EXEC)) {
++ h_file->f_mode |= FMODE_EXEC;
++ smp_mb(); /* flush f_mode */
++ err = au_deny_write_access(h_file);
++ if (unlikely(err)) {
++ fput(h_file);
++ h_file = ERR_PTR(err);
++ }
++ }
++ if (IS_ERR(h_file))
++ au_br_put(br);
++
++out:
++ AuTraceErrPtr(h_file);
++ return h_file;
++}
++
++static int do_coo(struct dentry *dentry, aufs_bindex_t bstart)
++{
++ int err;
++ aufs_bindex_t bcpup;
++ unsigned char pin_flags;
++ struct au_pin pin;
++ struct dentry *parent;
++ struct inode *h_inode;
++ struct super_block *sb;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ AuDebugOn(IS_ROOT(dentry));
++ DiMustWriteLock(dentry);
++
++ parent = dget_parent(dentry);
++ di_write_lock_parent(parent);
++ sb = dentry->d_sb;
++ err = AuWbrCopyup(au_sbi(sb), dentry);
++ bcpup = err;
++ if (err < 0) {
++ err = 0; /* stop copyup, it is not an error */
++ goto out_dgrade;
++ }
++ err = 0;
++
++ if (!au_h_dptr(parent, bcpup)) {
++ err = au_cpup_dirs(dentry, bcpup);
++ if (unlikely(err))
++ goto out_dgrade;
++ }
++
++ di_downgrade_lock(parent, AuLock_IR);
++ pin_flags = AuPin_DI_LOCKED | AuPin_MNT_WRITE;
++ if (au_opt_test(au_mntflags(sb), UDBA_INOTIFY))
++ au_fset_pin(pin_flags, DO_GPARENT);
++ err = au_pin(&pin, dentry, bcpup, pin_flags);
++ if (unlikely(err))
++ goto out;
++ h_inode = au_h_dptr(dentry, bstart)->d_inode;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ AuDebugOn(au_h_dptr(dentry, bcpup));
++ err = au_sio_cpup_simple(dentry, bcpup, -1, AuCpup_DTIME);
++ AuTraceErr(err);
++ vfsub_i_unlock(h_inode);
++ au_unpin(&pin);
++ goto out;
++
++ out_dgrade:
++ di_downgrade_lock(parent, AuLock_IR);
++ out:
++ di_read_unlock(parent, AuLock_IR);
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++int au_do_open(struct inode *inode, struct file *file,
++ int (*open)(struct file *file, int flags))
++{
++ int err;
++ struct dentry *dentry;
++ struct super_block *sb;
++ aufs_bindex_t bstart;
++ unsigned char coo;
++
++ dentry = file->f_dentry;
++ LKTRTrace("i%lu, %.*s\n", inode->i_ino, AuDLNPair(dentry));
++
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ coo = 0;
++ if (!(sb->s_flags & MS_RDONLY))
++ switch (au_mntflags(sb) & AuOptMask_COO) {
++ case AuOpt_COO_LEAF:
++ coo = !S_ISDIR(inode->i_mode);
++ break;
++ case AuOpt_COO_ALL:
++ coo = 1;
++ break;
++ }
++ err = au_finfo_init(file);
++ if (unlikely(err))
++ goto out;
++
++ if (!coo)
++ di_read_lock_child(dentry, AuLock_IR);
++ else {
++ di_write_lock_child(dentry);
++ bstart = au_dbstart(dentry);
++ if (au_test_ro(sb, bstart, dentry->d_inode)) {
++ err = do_coo(dentry, bstart);
++ if (err) {
++ di_write_unlock(dentry);
++ goto out_finfo;
++ }
++ }
++ di_downgrade_lock(dentry, AuLock_IR);
++ }
++
++ err = open(file, file->f_flags);
++ di_read_unlock(dentry, AuLock_IR);
++
++ out_finfo:
++ fi_write_unlock(file);
++ if (unlikely(err))
++ au_finfo_fin(file);
++ out:
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
++
++int au_reopen_nondir(struct file *file)
++{
++ int err;
++ aufs_bindex_t bstart, bindex, bend;
++ struct dentry *dentry;
++ struct file *h_file, *h_file_tmp;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ bstart = au_dbstart(dentry);
++ //bstart = au_ibstart(inode);
++ AuDebugOn(S_ISDIR(dentry->d_inode->i_mode)
++ || !au_h_dptr(dentry, bstart)->d_inode);
++
++ h_file_tmp = NULL;
++ if (au_fbstart(file) == bstart) {
++ h_file = au_h_fptr(file, bstart);
++ if (file->f_mode == h_file->f_mode)
++ return 0; /* success */
++ h_file_tmp = h_file;
++ get_file(h_file_tmp);
++ au_set_h_fptr(file, bstart, NULL);
++ }
++ AuDebugOn(au_fbstart(file) < bstart
++ || au_fi(file)->fi_hfile[0 + bstart].hf_file);
++
++ h_file = au_h_open(dentry, bstart, file->f_flags & ~O_TRUNC, file);
++ err = PTR_ERR(h_file);
++ if (IS_ERR(h_file))
++ goto out; /* todo: close all? */
++ err = 0;
++ /* cpup_file_flags(h_file, file); */
++ au_set_fbstart(file, bstart);
++ au_set_h_fptr(file, bstart, h_file);
++ au_update_figen(file);
++ /* todo: necessary? */
++ /* file->f_ra = h_file->f_ra; */
++
++ /* close lower files */
++ bend = au_fbend(file);
++ for (bindex = bstart + 1; bindex <= bend; bindex++)
++ au_set_h_fptr(file, bindex, NULL);
++ au_set_fbend(file, bstart);
++
++ out:
++ if (h_file_tmp)
++ fput(h_file_tmp);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int au_ready_to_write_wh(struct file *file, loff_t len,
++ aufs_bindex_t bcpup)
++{
++ int err;
++ aufs_bindex_t old_bstart;
++ struct inode *inode;
++ struct dentry *dentry, *hi_wh, *old_h_dentry;
++ struct au_dinfo *dinfo;
++ struct super_block *sb;
++
++ AuTraceEnter();
++
++ dentry = file->f_dentry;
++ inode = dentry->d_inode;
++ hi_wh = au_hi_wh(inode, bcpup);
++ if (!hi_wh)
++ err = au_sio_cpup_wh(dentry, bcpup, len, file);
++ else {
++ /* already copied-up after unlink */
++ dinfo = au_di(dentry);
++ old_bstart = dinfo->di_bstart;
++ dinfo->di_bstart = bcpup;
++ old_h_dentry = dinfo->di_hdentry[0 + bcpup].hd_dentry;
++ dinfo->di_hdentry[0 + bcpup].hd_dentry = hi_wh;
++ err = au_reopen_nondir(file);
++ dinfo->di_hdentry[0 + bcpup].hd_dentry = old_h_dentry;
++ dinfo->di_bstart = old_bstart;
++ }
++
++ sb = dentry->d_sb;
++ if (!err && inode->i_nlink > 1 && au_opt_test(au_mntflags(sb), PLINK))
++ au_plink_append(sb, inode, au_h_dptr(dentry, bcpup), bcpup);
++
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * prepare the @file for writing.
++ */
++int au_ready_to_write(struct file *file, loff_t len, struct au_pin *pin)
++{
++ int err;
++ unsigned char pin_flags;
++ aufs_bindex_t bstart, bcpup;
++ struct dentry *dentry, *parent, *h_dentry;
++ struct inode *h_inode, *inode;
++ struct super_block *sb;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, len %lld\n", AuDLNPair(dentry), len);
++ FiMustWriteLock(file);
++
++ sb = dentry->d_sb;
++ bstart = au_fbstart(file);
++ AuDebugOn(au_fbr(file, bstart) != au_sbr(sb, bstart));
++
++ inode = dentry->d_inode;
++ AuDebugOn(S_ISDIR(inode->i_mode));
++ LKTRTrace("rdonly %d, bstart %d\n",
++ au_test_ro(sb, bstart, inode), bstart);
++
++ err = au_test_ro(sb, bstart, inode);
++ if (!err && (au_h_fptr(file, bstart)->f_mode & FMODE_WRITE)) {
++ err = au_pin(pin, dentry, bstart, /*flags*/0);
++ goto out;
++ }
++
++ /* need to cpup */
++ parent = dget_parent(dentry);
++ di_write_lock_parent(parent);
++ err = AuWbrCopyup(au_sbi(sb), dentry);
++ bcpup = err;
++ if (unlikely(err < 0))
++ goto out_dgrade;
++ err = 0;
++
++ if (!au_h_dptr(parent, bcpup)) {
++ err = au_cpup_dirs(dentry, bcpup);
++ if (unlikely(err))
++ goto out_dgrade;
++ }
++
++ pin_flags = AuPin_DI_LOCKED | AuPin_MNT_WRITE;
++ if (au_opt_test(au_mntflags(sb), UDBA_INOTIFY))
++ au_fset_pin(pin_flags, DO_GPARENT);
++ err = au_pin(pin, dentry, bcpup, pin_flags);
++ if (unlikely(err))
++ goto out_dgrade;
++
++ AuDebugOn(au_fbstart(file) != bstart);
++ h_dentry = au_h_fptr(file, bstart)->f_dentry;
++ h_inode = h_dentry->d_inode;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ if (d_unhashed(dentry) /* || d_unhashed(h_dentry) */
++ /* || !h_inode->i_nlink */) {
++ err = au_ready_to_write_wh(file, len, bcpup);
++ di_downgrade_lock(parent, AuLock_IR);
++ } else {
++ di_downgrade_lock(parent, AuLock_IR);
++ if (!au_h_dptr(dentry, bcpup))
++ err = au_sio_cpup_simple(dentry, bcpup, len,
++ AuCpup_DTIME);
++ AuTraceErr(err);
++ if (!err)
++ err = au_reopen_nondir(file);
++ AuTraceErr(err);
++ }
++ vfsub_i_unlock(h_inode);
++
++ if (!err) {
++ au_unpin_gp(pin);
++ au_pin_set_parent_lflag(pin, /*lflag*/0);
++ goto out_dput; /* success */
++ }
++ au_unpin(pin);
++ goto out_unlock;
++
++ out_dgrade:
++ di_downgrade_lock(parent, AuLock_IR);
++ out_unlock:
++ di_read_unlock(parent, AuLock_IR);
++ out_dput:
++ dput(parent);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int au_file_refresh_by_inode(struct file *file, int *need_reopen)
++{
++ int err;
++ unsigned int mnt_flags;
++ unsigned char pin_flags;
++ aufs_bindex_t bstart, new_bstart, old_bstart;
++ struct au_pin pin;
++ struct au_finfo *finfo;
++ struct dentry *dentry, *parent, *old_h_dentry, *hi_wh;
++ struct inode *inode, *dir;
++ struct super_block *sb;
++ struct au_dinfo *dinfo;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ FiMustWriteLock(file);
++
++ err = 0;
++ finfo = au_fi(file);
++ inode = dentry->d_inode;
++ sb = dentry->d_sb;
++ mnt_flags = au_mntflags(sb);
++ pin_flags = AuPin_DI_LOCKED | AuPin_MNT_WRITE;
++ if (au_opt_test(mnt_flags, UDBA_INOTIFY))
++ au_fset_pin(pin_flags, DO_GPARENT);
++ again:
++ bstart = au_ibstart(inode);
++ if (bstart == finfo->fi_bstart)
++ goto out;
++
++ new_bstart = bstart;
++ parent = dget_parent(dentry);
++ dir = parent->d_inode;
++ if (au_test_ro(sb, bstart, inode)) {
++ di_read_lock_parent(parent, !AuLock_IR);
++ err = AuWbrCopyup(au_sbi(sb), dentry);
++ new_bstart = err;
++ di_read_unlock(parent, !AuLock_IR);
++ if (unlikely(err < 0))
++ goto out_dput;
++ err = 0;
++ }
++ /* someone else might change our inode while we were sleeping */
++ /* todo: test more? */
++ if (bstart != au_ibstart(inode)) {
++ err = 0;
++ dput(parent);
++ goto again;
++ }
++ di_read_lock_parent(parent, AuLock_IR);
++ bstart = new_bstart;
++
++ hi_wh = au_hi_wh(inode, bstart);
++ if (au_opt_test(mnt_flags, PLINK)
++ && au_plink_test(sb, inode)
++ && !d_unhashed(dentry)) {
++ err = au_test_and_cpup_dirs(dentry, bstart);
++ if (unlikely(err))
++ goto out_unlock;
++
++ /* always superio. */
++#if 1
++ err = au_pin(&pin, dentry, bstart, pin_flags);
++ if (!err)
++ err = au_sio_cpup_simple(dentry, bstart, -1,
++ AuCpup_DTIME);
++ au_unpin(&pin);
++#else /* reserved for future use */
++ if (!au_test_wkq(current)) {
++ int wkq_err;
++ struct cpup_pseudo_link_args args = {
++ .errp = &err,
++ .dentry = dentry,
++ .bdst = bstart,
++ .do_lock = 1
++ };
++ wkq_err = au_wkq_wait(call_cpup_pseudo_link, &args);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ } else
++ err = cpup_pseudo_link(dentry, bstart, /*do_lock*/1);
++#endif
++ } else if (hi_wh) {
++ /* already copied-up after unlink */
++ dinfo = au_di(dentry);
++ old_bstart = dinfo->di_bstart;
++ dinfo->di_bstart = bstart;
++ old_h_dentry = dinfo->di_hdentry[0 + bstart].hd_dentry;
++ dinfo->di_hdentry[0 + bstart].hd_dentry = hi_wh;
++ err = au_reopen_nondir(file);
++ dinfo->di_hdentry[0 + bstart].hd_dentry = old_h_dentry;
++ dinfo->di_bstart = old_bstart;
++ *need_reopen = 0;
++ }
++
++ out_unlock:
++ di_read_unlock(parent, AuLock_IR);
++ out_dput:
++ dput(parent);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * after branch manipulating, refresh the file.
++ */
++static int refresh_file(struct file *file, int (*reopen)(struct file *file))
++{
++ int err, new_sz, need_reopen;
++ struct dentry *dentry;
++ aufs_bindex_t bend, bindex, brid;
++ struct au_hfile *p;
++ struct au_finfo *finfo;
++ struct super_block *sb;
++ struct inode *inode;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ FiMustWriteLock(file);
++ DiMustAnyLock(dentry);
++ inode = dentry->d_inode;
++ IiMustAnyLock(inode);
++
++ err = -ENOMEM;
++ sb = dentry->d_sb;
++ finfo = au_fi(file);
++ new_sz = sizeof(*finfo->fi_hfile) * (au_sbend(sb) + 1);
++ p = au_kzrealloc(finfo->fi_hfile, sizeof(*p) * (finfo->fi_bend + 1),
++ new_sz, GFP_NOFS);
++ if (unlikely(!p))
++ goto out;
++ finfo->fi_hfile = p;
++
++ p += finfo->fi_bstart;
++ brid = p->hf_br->br_id;
++ bend = finfo->fi_bend;
++ for (bindex = finfo->fi_bstart; bindex <= bend; bindex++, p++) {
++ struct au_hfile tmp, *q;
++ aufs_bindex_t new_bindex;
++
++ if (!p->hf_file)
++ continue;
++ new_bindex = au_find_bindex(sb, p->hf_br);
++ if (new_bindex == bindex)
++ continue;
++ /* todo: test more? */
++ if (new_bindex < 0) {
++ au_set_h_fptr(file, bindex, NULL);
++ continue;
++ }
++
++ /* swap two hidden inode, and loop again */
++ q = finfo->fi_hfile + new_bindex;
++ tmp = *q;
++ *q = *p;
++ *p = tmp;
++ if (tmp.hf_file) {
++ bindex--;
++ p--;
++ }
++ }
++ {
++ aufs_bindex_t s = finfo->fi_bstart, e = finfo->fi_bend;
++ finfo->fi_bstart = 0;
++ finfo->fi_bend = au_sbend(sb);
++ finfo->fi_bstart = s;
++ finfo->fi_bend = e;
++ }
++
++ p = finfo->fi_hfile;
++ if (!au_test_mmapped(file) && !d_unhashed(dentry)) {
++ bend = au_sbend(sb);
++ for (finfo->fi_bstart = 0; finfo->fi_bstart <= bend;
++ finfo->fi_bstart++, p++)
++ if (p->hf_file) {
++ if (p->hf_file->f_dentry
++ && p->hf_file->f_dentry->d_inode)
++ break;
++ else
++ au_hfput(p);
++ }
++ } else {
++ bend = au_br_index(sb, brid);
++ for (finfo->fi_bstart = 0; finfo->fi_bstart < bend;
++ finfo->fi_bstart++, p++)
++ if (p->hf_file)
++ au_hfput(p);
++ bend = au_sbend(sb);
++ }
++
++ p = finfo->fi_hfile + bend;
++ for (finfo->fi_bend = bend; finfo->fi_bend >= finfo->fi_bstart;
++ finfo->fi_bend--, p--)
++ if (p->hf_file) {
++ if (p->hf_file->f_dentry
++ && p->hf_file->f_dentry->d_inode)
++ break;
++ else
++ au_hfput(p);
++ }
++ AuDebugOn(finfo->fi_bend < finfo->fi_bstart);
++
++ err = 0;
++ need_reopen = 1;
++ if (!au_test_mmapped(file))
++ err = au_file_refresh_by_inode(file, &need_reopen);
++ if (!err && need_reopen && !d_unhashed(dentry))
++ err = reopen(file);
++ if (!err) {
++ au_update_figen(file);
++ return 0; /* success */
++ }
++
++ /* error, close all hidden files */
++ bend = au_fbend(file);
++ for (bindex = au_fbstart(file); bindex <= bend; bindex++)
++ au_set_h_fptr(file, bindex, NULL);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* common function to regular file and dir */
++int au_reval_and_lock_fdi(struct file *file, int (*reopen)(struct file *file),
++ int wlock, int locked)
++{
++ int err;
++ struct dentry *dentry;
++ struct super_block *sb;
++ aufs_bindex_t bstart;
++ unsigned char pseudo_link;
++ au_gen_t sgen, fgen;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, w %d, l %d\n", AuDLNPair(dentry), wlock, locked);
++ sb = dentry->d_sb;
++ SiMustAnyLock(sb);
++
++ err = 0;
++ sgen = au_sigen(sb);
++ fi_write_lock(file);
++ fgen = au_figen(file);
++ di_write_lock_child(dentry);
++ bstart = au_dbstart(dentry);
++ pseudo_link = (bstart != au_ibstart(dentry->d_inode));
++ if (sgen == fgen && !pseudo_link && au_fbstart(file) == bstart) {
++ if (!wlock) {
++ di_downgrade_lock(dentry, AuLock_IR);
++ fi_downgrade_lock(file);
++ }
++ goto out; /* success */
++ }
++
++ LKTRTrace("sgen %d, fgen %d\n", sgen, fgen);
++ if (sgen != au_digen(dentry)
++ || sgen != au_iigen(dentry->d_inode)) {
++ /*
++ * d_path() and path_lookup() is a simple and good approach
++ * to revalidate. but si_rwsem in DEBUG_RWSEM will cause a
++ * deadlock. removed the code.
++ */
++ err = au_reval_dpath(dentry, sgen);
++ if (unlikely(err < 0))
++ goto out;
++ AuDebugOn(au_digen(dentry) != sgen
++ || au_iigen(dentry->d_inode) != sgen);
++ }
++
++ err = refresh_file(file, reopen
++ /* , au_opt_test(au_mnt_flags(sb), REFROF) */);
++ if (!err) {
++ if (!wlock) {
++ di_downgrade_lock(dentry, AuLock_IR);
++ fi_downgrade_lock(file);
++ }
++ } else {
++ di_write_unlock(dentry);
++ fi_write_unlock(file);
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* cf. aufs_nopage() */
++/* for madvise(2) */
++static int aufs_readpage(struct file *file, struct page *page)
++{
++ AuTraceEnter();
++ unlock_page(page);
++ return 0;
++}
++
++/* they will never be called. */
++#ifdef CONFIG_AUFS_DEBUG
++static int aufs_prepare_write(struct file *file, struct page *page,
++ unsigned from, unsigned to)
++{ AuUnsupport(); return 0; }
++static int aufs_commit_write(struct file *file, struct page *page,
++ unsigned from, unsigned to)
++{ AuUnsupport(); return 0; }
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static int aufs_write_begin(struct file *file, struct address_space *mapping,
++ loff_t pos, unsigned len, unsigned flags,
++ struct page **pagep, void **fsdata)
++{ AuUnsupport(); return 0; }
++static int aufs_write_end(struct file *file, struct address_space *mapping,
++ loff_t pos, unsigned len, unsigned copied,
++ struct page *page, void *fsdata)
++{ AuUnsupport(); return 0; }
++#endif
++static int aufs_writepage(struct page *page, struct writeback_control *wbc)
++{ AuUnsupport(); return 0; }
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17)
++static void aufs_sync_page(struct page *page)
++{ AuUnsupport(); }
++#else
++static int aufs_sync_page(struct page *page)
++{ AuUnsupport(); return 0; }
++#endif
++
++#if 0 // comment
++static int aufs_writepages(struct address_space *mapping,
++ struct writeback_control *wbc)
++{ AuUnsupport(); return 0; }
++static int aufs_readpages(struct file *filp, struct address_space *mapping,
++ struct list_head *pages, unsigned nr_pages)
++{ AuUnsupport(); return 0; }
++static sector_t aufs_bmap(struct address_space *mapping, sector_t block)
++{ AuUnsupport(); return 0; }
++#endif
++
++static int aufs_set_page_dirty(struct page *page)
++{ AuUnsupport(); return 0; }
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17)
++static void aufs_invalidatepage(struct page *page, unsigned long offset)
++{ AuUnsupport(); }
++#else
++static int aufs_invalidatepage(struct page *page, unsigned long offset)
++{ AuUnsupport(); return 0; }
++#endif
++static int aufs_releasepage(struct page *page, gfp_t gfp)
++{ AuUnsupport(); return 0; }
++static ssize_t aufs_direct_IO(int rw, struct kiocb *iocb,
++ const struct iovec *iov, loff_t offset,
++ unsigned long nr_segs)
++{ AuUnsupport(); return 0; }
++static struct page *aufs_get_xip_page(struct address_space *mapping,
++ sector_t offset, int create)
++{ AuUnsupport(); return NULL; }
++//static int aufs_migratepage (struct page *newpage, struct page *page)
++//{ AuUnsupport(); return 0; }
++#if 0 //LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
++int (*launder_page) (struct page *);
++#endif
++#endif /* CONFIG_AUFS_DEBUG */
++
++struct address_space_operations aufs_aop = {
++ .readpage = aufs_readpage,
++#ifdef CONFIG_AUFS_DEBUG
++ .writepage = aufs_writepage,
++ .sync_page = aufs_sync_page,
++ //.writepages = aufs_writepages,
++ .set_page_dirty = aufs_set_page_dirty,
++ //.readpages = aufs_readpages,
++ .prepare_write = aufs_prepare_write,
++ .commit_write = aufs_commit_write,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++ .write_begin = aufs_write_begin,
++ .write_end = aufs_write_end,
++#endif
++ //.bmap = aufs_bmap,
++ .invalidatepage = aufs_invalidatepage,
++ .releasepage = aufs_releasepage,
++ .direct_IO = aufs_direct_IO,
++ .get_xip_page = aufs_get_xip_page,
++ //.migratepage = aufs_migratepage
++#endif /* CONFIG_AUFS_DEBUG */
++};
+diff --git a/fs/aufs/file.h b/fs/aufs/file.h
+new file mode 100644
+index 0000000..a974284
+--- /dev/null
++++ b/fs/aufs/file.h
+@@ -0,0 +1,262 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * file operations
++ *
++ * $Id: file.h,v 1.40 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_FILE_H__
++#define __AUFS_FILE_H__
++
++#ifdef __KERNEL__
++
++#include <linux/file.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/version.h>
++#include <linux/aufs_type.h>
++#include "misc.h"
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++/* SEEK_xxx are defined in linux/fs.h */
++#else
++enum {
++ SEEK_SET, SEEK_CUR, SEEK_END
++};
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++struct au_branch;
++struct au_hfile {
++ struct file *hf_file;
++ struct au_branch *hf_br;
++};
++
++struct au_vdir;
++struct au_finfo {
++ atomic_t fi_generation;
++
++ struct au_rwsem fi_rwsem;
++ struct au_hfile *fi_hfile;
++ aufs_bindex_t fi_bstart, fi_bend;
++
++ union {
++ struct vm_operations_struct *fi_h_vm_ops;
++ struct au_vdir *fi_vdir_cache;
++ };
++};
++
++/* ---------------------------------------------------------------------- */
++
++/* file.c */
++extern struct address_space_operations aufs_aop;
++unsigned int au_file_roflags(unsigned int flags);
++struct file *au_h_open(struct dentry *dentry, aufs_bindex_t bindex, int flags,
++ struct file *file);
++int au_do_open(struct inode *inode, struct file *file,
++ int (*open)(struct file *file, int flags));
++int au_reopen_nondir(struct file *file);
++struct au_pin;
++int au_ready_to_write(struct file *file, loff_t len, struct au_pin *pin);
++int au_reval_and_lock_fdi(struct file *file, int (*reopen)(struct file *file),
++ int wlock, int locked);
++
++/* f_op.c */
++extern struct file_operations aufs_file_fop;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++int aufs_flush(struct file *file, fl_owner_t id);
++#else
++int aufs_flush(struct file *file);
++#endif
++
++/* finfo.c */
++struct au_finfo *au_fi(struct file *file);
++struct au_branch *au_fbr(struct file *file, aufs_bindex_t bindex);
++struct file *au_h_fptr(struct file *file, aufs_bindex_t bindex);
++
++void au_hfput(struct au_hfile *hf);
++void au_set_h_fptr(struct file *file, aufs_bindex_t bindex,
++ struct file *h_file);
++
++void au_finfo_fin(struct file *file);
++int au_finfo_init(struct file *file);
++
++#ifdef CONFIG_AUFS_ROBR
++/* robr.c */
++struct file *au_robr_safe_file(struct vm_area_struct *vma);
++void au_robr_reset_file(struct vm_area_struct *vma, struct file *file);
++#else
++static inline struct file *au_robr_safe_file(struct vm_area_struct *vma)
++{
++ struct file *file;
++
++ file = vma->vm_file;
++ if (file->private_data && au_test_aufs(file->f_dentry->d_sb))
++ return file;
++ return NULL;
++}
++
++static inline
++void au_robr_reset_file(struct vm_area_struct *vma, struct file *file)
++{
++ vma->vm_file = file;
++ /* smp_mb(); */ /* flush vm_file */
++}
++#endif /* CONFIG_AUFS_ROBR */
++
++/* ---------------------------------------------------------------------- */
++
++/* todo: memory barrier? */
++static inline au_gen_t au_figen(struct file *f)
++{
++ return atomic_read(&au_fi(f)->fi_generation);
++}
++
++static inline int au_test_mmapped(struct file *f)
++{
++ return !!(au_fi(f)->fi_h_vm_ops);
++}
++
++static inline int au_test_aufs_file(struct file *f)
++{
++ return !(f->f_dentry->d_inode->i_mode
++ & (S_IFCHR | S_IFBLK | S_IFIFO | S_IFSOCK));
++}
++
++/* ---------------------------------------------------------------------- */
++
++#if !defined(CONFIG_AUFS_MODULE) || defined(CONFIG_AUFS_DENY_WRITE_ACCESS_PATCH)
++int au_store_fmode_exec(struct nameidata *nd, struct inode *inode);
++
++static inline int au_deny_write_access(struct file *h_file)
++{
++ LKTRTrace("%.*s\n", AuDLNPair(h_file->f_dentry));
++ return deny_write_access(h_file);
++}
++
++static inline void au_allow_write_access(struct file *h_file)
++{
++ allow_write_access(h_file);
++}
++
++#else
++
++static inline int au_store_fmode_exec(struct nameidata *nd, struct inode *inode)
++{
++ /* nothing */
++ return 0;
++}
++
++static inline int au_deny_write_access(struct file *h_file)
++{
++ /* nothing */
++ return 0;
++}
++
++static inline void au_allow_write_access(struct file *h_file)
++{
++ /* nothing */
++}
++#endif /* CONFIG_AUFS_DENY_WRITE_ACCESS_PATCH */
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * fi_read_lock, fi_write_lock,
++ * fi_read_unlock, fi_write_unlock, fi_downgrade_lock
++ */
++AuSimpleRwsemFuncs(fi, struct file *f, au_fi(f)->fi_rwsem);
++
++/* to debug easier, do not make them inlined functions */
++#define FiMustReadLock(f) do { \
++ SiMustAnyLock((f)->f_dentry->d_sb); \
++ AuRwMustReadLock(&au_fi(f)->fi_rwsem); \
++} while (0)
++
++#define FiMustWriteLock(f) do { \
++ SiMustAnyLock((f)->f_dentry->d_sb); \
++ AuRwMustWriteLock(&au_fi(f)->fi_rwsem); \
++} while (0)
++
++#define FiMustAnyLock(f) do { \
++ SiMustAnyLock((f)->f_dentry->d_sb); \
++ AuRwMustAnyLock(&au_fi(f)->fi_rwsem); \
++} while (0)
++
++#define FiMustNoWaiters(f) AuRwMustNoWaiters(&au_fi(f)->fi_rwsem)
++
++/* ---------------------------------------------------------------------- */
++
++/* todo: hard/soft set? */
++static inline aufs_bindex_t au_fbstart(struct file *file)
++{
++ FiMustAnyLock(file);
++ return au_fi(file)->fi_bstart;
++}
++
++static inline aufs_bindex_t au_fbend(struct file *file)
++{
++ FiMustAnyLock(file);
++ return au_fi(file)->fi_bend;
++}
++
++static inline struct au_vdir *au_fvdir_cache(struct file *file)
++{
++#ifdef CONFIG_AUFS_EXPORT
++ AuRwMustAnyLock(&au_fi(file)->fi_rwsem);
++#else
++ FiMustAnyLock(file);
++#endif
++ return au_fi(file)->fi_vdir_cache;
++}
++
++static inline void au_set_fbstart(struct file *file, aufs_bindex_t bindex)
++{
++ FiMustWriteLock(file);
++ AuDebugOn(au_sbend(file->f_dentry->d_sb) < bindex);
++ au_fi(file)->fi_bstart = bindex;
++}
++
++static inline void au_set_fbend(struct file *file, aufs_bindex_t bindex)
++{
++ FiMustWriteLock(file);
++ AuDebugOn(au_sbend(file->f_dentry->d_sb) < bindex
++ || bindex < au_fbstart(file));
++ au_fi(file)->fi_bend = bindex;
++}
++
++static inline void au_set_fvdir_cache(struct file *file,
++ struct au_vdir *vdir_cache)
++{
++ FiMustWriteLock(file);
++ AuDebugOn(!S_ISDIR(file->f_dentry->d_inode->i_mode)
++ || (au_fi(file)->fi_vdir_cache && vdir_cache));
++ au_fi(file)->fi_vdir_cache = vdir_cache;
++}
++
++static inline void au_update_figen(struct file *file)
++{
++ atomic_set(&au_fi(file)->fi_generation, au_digen(file->f_dentry));
++ /* smp_mb(); */ /* atomic_set */
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_FILE_H__ */
+diff --git a/fs/aufs/finfo.c b/fs/aufs/finfo.c
+new file mode 100644
+index 0000000..928c0f4
+--- /dev/null
++++ b/fs/aufs/finfo.c
+@@ -0,0 +1,186 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * file private data
++ *
++ * $Id: finfo.c,v 1.37 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++struct au_finfo *au_fi(struct file *file)
++{
++ struct au_finfo *finfo = file->private_data;
++ AuDebugOn(!finfo
++ || !finfo->fi_hfile
++ || (0 < finfo->fi_bend
++ && (/* au_sbi(file->f_dentry->d_sb)->si_bend
++ < finfo->fi_bend
++ || */ finfo->fi_bend < finfo->fi_bstart)));
++ return finfo;
++}
++
++struct au_branch *au_fbr(struct file *file, aufs_bindex_t bindex)
++{
++ struct au_finfo *finfo = au_fi(file);
++ struct au_hfile *hf;
++
++ FiMustAnyLock(file);
++ AuDebugOn(!finfo
++ || finfo->fi_bstart < 0
++ || bindex < finfo->fi_bstart
++ || finfo->fi_bend < bindex);
++ hf = finfo->fi_hfile + bindex;
++ AuDebugOn(hf->hf_br && au_br_count(hf->hf_br) <= 0);
++ return hf->hf_br;
++}
++
++struct file *au_h_fptr(struct file *file, aufs_bindex_t bindex)
++{
++ struct au_finfo *finfo = au_fi(file);
++ struct au_hfile *hf;
++
++ FiMustAnyLock(file);
++ AuDebugOn(!finfo
++ || finfo->fi_bstart < 0
++ || bindex < finfo->fi_bstart
++ || finfo->fi_bend < bindex);
++ hf = finfo->fi_hfile + bindex;
++ AuDebugOn(hf->hf_file
++ && file_count(hf->hf_file) <= 0
++ && au_br_count(hf->hf_br) <= 0);
++ return hf->hf_file;
++}
++
++void au_hfput(struct au_hfile *hf)
++{
++ if (hf->hf_file->f_mode & FMODE_EXEC)
++ au_allow_write_access(hf->hf_file);
++ fput(hf->hf_file);
++ hf->hf_file = NULL;
++ AuDebugOn(!hf->hf_br);
++ au_br_put(hf->hf_br);
++ hf->hf_br = NULL;
++}
++
++void au_set_h_fptr(struct file *file, aufs_bindex_t bindex, struct file *val)
++{
++ struct au_finfo *finfo = au_fi(file);
++ struct au_hfile *hf;
++
++ FiMustWriteLock(file);
++ AuDebugOn(!finfo
++ || finfo->fi_bstart < 0
++ || bindex < finfo->fi_bstart
++ || finfo->fi_bend < bindex);
++ AuDebugOn(val && file_count(val) <= 0);
++ hf = finfo->fi_hfile + bindex;
++ AuDebugOn(val && hf->hf_file);
++ if (hf->hf_file)
++ au_hfput(hf);
++ if (val) {
++ hf->hf_file = val;
++ hf->hf_br = au_sbr(file->f_dentry->d_sb, bindex);
++ }
++}
++
++void au_finfo_fin(struct file *file)
++{
++ struct au_finfo *finfo;
++ struct dentry *dentry;
++ aufs_bindex_t bindex, bend;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ SiMustAnyLock(dentry->d_sb);
++
++ fi_write_lock(file);
++ bend = au_fbend(file);
++ bindex = au_fbstart(file);
++ if (bindex >= 0)
++ for (; bindex <= bend; bindex++)
++ au_set_h_fptr(file, bindex, NULL);
++
++ finfo = au_fi(file);
++#ifdef CONFIG_AUFS_DEBUG
++ if (finfo->fi_bstart >= 0) {
++ bend = au_fbend(file);
++ for (bindex = finfo->fi_bstart; bindex <= bend; bindex++) {
++ struct au_hfile *hf;
++ hf = finfo->fi_hfile + bindex;
++ AuDebugOn(hf->hf_file || hf->hf_br);
++ }
++ }
++#endif
++
++ kfree(finfo->fi_hfile);
++ fi_write_unlock(file);
++ au_rwsem_destroy(&finfo->fi_rwsem);
++ au_cache_free_finfo(finfo);
++}
++
++int au_finfo_init(struct file *file)
++{
++ struct au_finfo *finfo;
++ struct dentry *dentry;
++ union {
++ void *p;
++ unsigned long ul;
++ } u;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ AuDebugOn(!dentry->d_inode);
++
++ finfo = au_cache_alloc_finfo();
++ if (finfo) {
++ finfo->fi_hfile = kcalloc(au_sbend(dentry->d_sb) + 1,
++ sizeof(*finfo->fi_hfile), GFP_NOFS);
++ if (finfo->fi_hfile) {
++ au_rw_init_wlock(&finfo->fi_rwsem);
++ //au_dbg_lock_fi_reg(file);
++ finfo->fi_bstart = -1;
++ finfo->fi_bend = -1;
++ atomic_set(&finfo->fi_generation, au_digen(dentry));
++ /* smp_mb(); */ /* atomic_set */
++
++ /*
++ * a dirty trick for handling FMODE_EXEC and
++ * deny_write_access().
++ * because FMODE_EXEC flag is not passed to
++ * f_op->open(),
++ * aufs set it to file->private_data temporary in lookup
++ * or dentry revalidation operations.
++ * restore the flag to f_mode here.
++ */
++ u.p = file->private_data;
++ if (u.ul & FMODE_EXEC) {
++ file->f_mode |= FMODE_EXEC;
++ smp_mb(); /* flush f_mode */
++ }
++
++ file->private_data = finfo;
++ return 0; /* success */
++ }
++ au_cache_free_finfo(finfo);
++ }
++
++ AuTraceErr(-ENOMEM);
++ return -ENOMEM;
++}
+diff --git a/fs/aufs/getattr.c b/fs/aufs/getattr.c
+new file mode 100644
+index 0000000..d424a09
+--- /dev/null
++++ b/fs/aufs/getattr.c
+@@ -0,0 +1,133 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode attributes on NFS/FUSE branch or HINOTIFY
++ *
++ * $Id: getattr.c,v 1.5 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++static struct dentry *
++au_h_dget_any(struct dentry *dentry, aufs_bindex_t *bindex)
++{
++ struct dentry *h_dentry;
++ struct inode *inode, *h_inode;
++ struct super_block *sb;
++ aufs_bindex_t ib, db;
++
++ /* must be positive dentry */
++ inode = dentry->d_inode;
++ LKTRTrace("%.*s, i%lu\n", AuDLNPair(dentry), inode->i_ino);
++
++ sb = dentry->d_sb;
++ db = au_dbstart(dentry);
++ ib = au_ibstart(inode);
++ if (db == ib) {
++ *bindex = db;
++ h_dentry = dget(au_h_dptr(dentry, db));
++ if (h_dentry)
++ goto out; /* success */
++ }
++
++ *bindex = ib;
++ h_inode = au_h_iptr(inode, ib);
++ h_dentry = d_find_alias(h_inode);
++ if (h_dentry)
++ goto out; /* success */
++
++#if 0
++ if (au_opt_test(au_mntflags(sb), PLINK)
++ && au_plink_test(sb, inode)) {
++ h_dentry = au_plink_lkup(sb, ib, inode);
++ if (IS_ERR(h_dentry))
++ goto out;
++ AuDebugOn(!h_dentry->d_inode);
++ goto out; /* success */
++ }
++#endif
++
++ h_dentry = dget(au_hi_wh(inode, ib));
++
++ out:
++ AuTraceErrPtr(h_dentry);
++ return h_dentry;
++}
++
++int aufs_getattr(struct vfsmount *mnt, struct dentry *dentry, struct kstat *st)
++{
++ int err;
++ unsigned int mnt_flags;
++ aufs_bindex_t bindex;
++ unsigned char did_lock;
++ struct inode *inode;
++ struct dentry *h_dentry;
++ struct super_block *sb, *h_sb;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ err = 0;
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ mnt_flags = au_mntflags(sb);
++ if (dentry != sb->s_root) {
++ di_read_lock_parent(dentry, AuLock_IR);
++ inode = dentry->d_inode;
++ did_lock = 1;
++
++ /* todo: test bit inotify option too? */
++ bindex = au_ibstart(inode);
++ h_sb = au_sbr_sb(sb, bindex);
++ /* todo: fix this condition */
++ if ((au_opt_test(mnt_flags, PLINK) && au_plink_test(sb, inode))
++ /* au_iigen(inode) == au_sigen(sb) */
++ || (!au_test_fuse(h_sb) && !au_test_nfs(h_sb)))
++ goto fill;
++
++ h_dentry = au_h_dget_any(dentry, &bindex);
++ err = PTR_ERR(h_dentry);
++ if (IS_ERR(h_dentry))
++ goto out;
++ } else {
++ /* lock free root dinfo */
++ did_lock = 0;
++ bindex = 0;
++ inode = dentry->d_inode;
++ h_dentry = dget(au_di(dentry)->di_hdentry->hd_dentry);
++ }
++
++ err = -EIO;
++ if (h_dentry && h_dentry->d_inode)
++ err = vfsub_getattr(au_sbr_mnt(sb, bindex), h_dentry, st,
++ au_test_dlgt(mnt_flags));
++ dput(h_dentry);
++ if (!err) {
++ /* todo: I don't like this approach */
++ au_cpup_attr_all(inode, /*force*/0);
++ fill:
++ generic_fillattr(inode, st);
++ }
++
++ out:
++ if (did_lock)
++ di_read_unlock(dentry, AuLock_IR);
++ si_read_unlock(sb);
++ AuTraceErr(err);
++ return err;
++}
+diff --git a/fs/aufs/hin_or_dlgt.c b/fs/aufs/hin_or_dlgt.c
+new file mode 100644
+index 0000000..172fc34
+--- /dev/null
++++ b/fs/aufs/hin_or_dlgt.c
+@@ -0,0 +1,736 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * sub-routines for vfs in hinotify or dlgt mode
++ *
++ * $Id: hin_or_dlgt.c,v 1.7 2009/01/26 06:24:45 sfjro Exp $
++ */
++// I'm going to slightly mad
++
++#include "aufs.h"
++
++#if !defined(CONFIG_AUFS_HINOTIFY) && !defined(CONFIG_AUFS_DLGT)
++#error mis-configuraion or Makefile
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++struct permission_args {
++ int *errp;
++ struct inode *inode;
++ int mask;
++ struct nameidata *nd;
++};
++
++static void call_permission(void *args)
++{
++ struct permission_args *a = args;
++ *a->errp = do_vfsub_permission(a->inode, a->mask, a->nd);
++}
++
++int vfsub_permission(struct inode *inode, int mask, struct nameidata *nd,
++ int dlgt)
++{
++ if (!dlgt)
++ return do_vfsub_permission(inode, mask, nd);
++ else {
++ int err, wkq_err;
++ struct permission_args args = {
++ .errp = &err,
++ .inode = inode,
++ .mask = mask,
++ .nd = nd
++ };
++ wkq_err = au_wkq_wait(call_permission, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ return err;
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct create_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ int mode;
++ struct nameidata *nd;
++ struct vfsub_args *vargs;
++};
++
++static void call_create(void *args)
++{
++ struct create_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_create(a->dir, a->dentry, a->mode, a->nd);
++ if (unlikely(*a->errp))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++int vfsub_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *nd, struct vfsub_args *vargs)
++{
++ int err;
++ struct create_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .mode = mode,
++ .nd = nd,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_create(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_create, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++struct symlink_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ const char *symname;
++ int mode;
++ struct vfsub_args *vargs;
++};
++
++static void call_symlink(void *args)
++{
++ struct symlink_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_symlink(a->dir, a->dentry, a->symname, a->mode);
++ if (unlikely(*a->errp))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++int vfsub_symlink(struct inode *dir, struct dentry *dentry, const char *symname,
++ int mode, struct vfsub_args *vargs)
++{
++ int err;
++ struct symlink_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .symname = symname,
++ .mode = mode,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_symlink(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_symlink, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++struct mknod_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ int mode;
++ dev_t dev;
++ struct vfsub_args *vargs;
++};
++
++static void call_mknod(void *args)
++{
++ struct mknod_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_mknod(a->dir, a->dentry, a->mode, a->dev);
++ if (unlikely(*a->errp))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++int vfsub_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev,
++ struct vfsub_args *vargs)
++{
++ int err;
++ struct mknod_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .mode = mode,
++ .dev = dev,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_mknod(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_mknod, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++struct mkdir_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ int mode;
++ struct vfsub_args *vargs;
++};
++
++static void call_mkdir(void *args)
++{
++ struct mkdir_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_mkdir(a->dir, a->dentry, a->mode);
++ if (unlikely(*a->errp))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++int vfsub_mkdir(struct inode *dir, struct dentry *dentry, int mode,
++ struct vfsub_args *vargs)
++{
++ int err;
++ struct mkdir_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .mode = mode,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_mkdir(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_mkdir, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct link_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *src_dentry, *dentry;
++ struct vfsub_args *vargs;
++};
++
++static void call_link(void *args)
++{
++ struct link_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_link(a->src_dentry, a->dir, a->dentry);
++ if (unlikely(*a->errp))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++int vfsub_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry, struct vfsub_args *vargs)
++{
++ int err;
++ struct link_args args = {
++ .errp = &err,
++ .src_dentry = src_dentry,
++ .dir = dir,
++ .dentry = dentry,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_link(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_link, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++struct rename_args {
++ int *errp;
++ struct inode *src_dir, *dir;
++ struct dentry *src_dentry, *dentry;
++ struct vfsub_args *vargs;
++};
++
++static void call_rename(void *args)
++{
++ struct rename_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_rename(a->src_dir, a->src_dentry, a->dir,
++ a->dentry);
++ if (unlikely(*a->errp))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++int vfsub_rename(struct inode *src_dir, struct dentry *src_dentry,
++ struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs)
++{
++ int err;
++ struct rename_args args = {
++ .errp = &err,
++ .src_dir = src_dir,
++ .src_dentry = src_dentry,
++ .dir = dir,
++ .dentry = dentry,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_rename(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_rename, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++struct rmdir_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ struct vfsub_args *vargs;
++};
++
++static void call_rmdir(void *args)
++{
++ struct rmdir_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_rmdir(a->dir, a->dentry);
++ if (unlikely(*a->errp))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++int vfsub_rmdir(struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs)
++{
++ int err;
++ struct rmdir_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_rmdir(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_rmdir, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct read_args {
++ ssize_t *errp;
++ struct file *file;
++ union {
++ void *kbuf;
++ char __user *ubuf;
++ };
++ size_t count;
++ loff_t *ppos;
++};
++
++static void call_read_k(void *args)
++{
++ struct read_args *a = args;
++ LKTRTrace("%.*s, cnt %zu, pos %lld\n",
++ AuDLNPair(a->file->f_dentry), a->count, *a->ppos);
++ *a->errp = do_vfsub_read_k(a->file, a->kbuf, a->count, a->ppos);
++}
++
++ssize_t vfsub_read_u(struct file *file, char __user *ubuf, size_t count,
++ loff_t *ppos, int dlgt)
++{
++ if (!dlgt)
++ return do_vfsub_read_u(file, ubuf, count, ppos);
++ else {
++ int wkq_err;
++ ssize_t err, read;
++ struct read_args args = {
++ .errp = &err,
++ .file = file,
++ .count = count,
++ .ppos = ppos
++ };
++
++ if (!count)
++ return 0;
++
++ /*
++ * workaround an application bug.
++ * generally, read(2) or write(2) may return the value shorter
++ * than requested. But many applications don't support it,
++ * for example bash.
++ */
++ err = -ENOMEM;
++ if (args.count > PAGE_SIZE)
++ args.count = PAGE_SIZE;
++ args.kbuf = kmalloc(args.count, GFP_NOFS);
++ if (unlikely(!args.kbuf))
++ goto out;
++
++ read = 0;
++ do {
++ wkq_err = au_wkq_wait(call_read_k, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ if (unlikely(err > 0
++ && copy_to_user(ubuf, args.kbuf, err))) {
++ err = -EFAULT;
++ goto out_free;
++ } else if (!err)
++ break;
++ else if (unlikely(err < 0))
++ goto out_free;
++ count -= err;
++ /* do not read too much because of file i/o pointer */
++ if (count < args.count)
++ args.count = count;
++ ubuf += err;
++ read += err;
++ } while (count);
++ smp_mb(); /* flush ubuf */
++ err = read;
++
++ out_free:
++ kfree(args.kbuf);
++ out:
++ return err;
++ }
++}
++
++ssize_t vfsub_read_k(struct file *file, void *kbuf, size_t count, loff_t *ppos,
++ int dlgt)
++{
++ if (!dlgt)
++ return do_vfsub_read_k(file, kbuf, count, ppos);
++ else {
++ ssize_t err;
++ int wkq_err;
++ struct read_args args = {
++ .errp = &err,
++ .file = file,
++ .count = count,
++ .ppos = ppos
++ };
++ args.kbuf = kbuf;
++ wkq_err = au_wkq_wait(call_read_k, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ return err;
++ }
++}
++
++struct write_args {
++ ssize_t *errp;
++ struct file *file;
++ union {
++ void *kbuf;
++ const char __user *ubuf;
++ };
++ size_t count;
++ loff_t *ppos;
++ struct vfsub_args *vargs;
++};
++
++static void call_write_k(void *args)
++{
++ struct write_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_write_k(a->file, a->kbuf, a->count, a->ppos);
++ if (unlikely(*a->errp <= 0))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++ssize_t vfsub_write_u(struct file *file, const char __user *ubuf, size_t count,
++ loff_t *ppos, struct vfsub_args *vargs)
++{
++ ssize_t err;
++
++ if (!vfsub_ftest(vargs->flags, DLGT)) {
++ vfsub_ignore(vargs);
++ err = do_vfsub_write_u(file, ubuf, count, ppos);
++ if (unlikely(err <= 0))
++ vfsub_unignore(vargs);
++ au_dbg_hin_list(vargs);
++ } else {
++ ssize_t written;
++ int wkq_err;
++ struct write_args args = {
++ .errp = &err,
++ .file = file,
++ .count = count,
++ .ppos = ppos,
++ .vargs = vargs
++ };
++
++ if (!count)
++ return 0;
++
++ /*
++ * workaround an application bug.
++ * generally, read(2) or write(2) may return the value shorter
++ * than requested. But many applications don't support it,
++ * for example bash.
++ */
++ err = -ENOMEM;
++ if (args.count > PAGE_SIZE)
++ args.count = PAGE_SIZE;
++ args.kbuf = kmalloc(args.count, GFP_NOFS);
++ if (unlikely(!args.kbuf))
++ goto out;
++
++ written = 0;
++ do {
++ if (unlikely(copy_from_user(args.kbuf, ubuf,
++ args.count))) {
++ err = -EFAULT;
++ goto out_free;
++ }
++
++ wkq_err = au_wkq_wait(call_write_k, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ if (err > 0) {
++ count -= err;
++ if (count < args.count)
++ args.count = count;
++ ubuf += err;
++ written += err;
++ } else if (!err)
++ break;
++ else if (unlikely(err < 0))
++ goto out_free;
++ } while (count);
++ err = written;
++
++ out_free:
++ kfree(args.kbuf);
++ }
++ out:
++ return err;
++}
++
++ssize_t vfsub_write_k(struct file *file, void *kbuf, size_t count, loff_t *ppos,
++ struct vfsub_args *vargs)
++{
++ ssize_t err;
++ struct write_args args = {
++ .errp = &err,
++ .file = file,
++ .count = count,
++ .ppos = ppos,
++ .vargs = vargs
++ };
++
++ args.kbuf = kbuf;
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_write_k(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_write_k, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++struct readdir_args {
++ int *errp;
++ struct file *file;
++ filldir_t filldir;
++ void *arg;
++};
++
++static void call_readdir(void *args)
++{
++ struct readdir_args *a = args;
++ *a->errp = do_vfsub_readdir(a->file, a->filldir, a->arg);
++}
++
++int vfsub_readdir(struct file *file, filldir_t filldir, void *arg, int dlgt)
++{
++ if (!dlgt)
++ return do_vfsub_readdir(file, filldir, arg);
++ else {
++ int err, wkq_err;
++ struct readdir_args args = {
++ .errp = &err,
++ .file = file,
++ .filldir = filldir,
++ .arg = arg
++ };
++ wkq_err = au_wkq_wait(call_readdir, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ return err;
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct splice_to_args {
++ long *errp;
++ struct file *in;
++ loff_t *ppos;
++ struct pipe_inode_info *pipe;
++ size_t len;
++ unsigned int flags;
++};
++
++static void call_splice_to(void *args)
++{
++ struct splice_to_args *a = args;
++ *a->errp = do_vfsub_splice_to(a->in, a->ppos, a->pipe, a->len,
++ a->flags);
++}
++
++long vfsub_splice_to(struct file *in, loff_t *ppos,
++ struct pipe_inode_info *pipe, size_t len,
++ unsigned int flags, int dlgt)
++{
++ if (!dlgt)
++ return do_vfsub_splice_to(in, ppos, pipe, len, flags);
++ else {
++ long err;
++ int wkq_err;
++ struct splice_to_args args = {
++ .errp = &err,
++ .in = in,
++ .ppos = ppos,
++ .pipe = pipe,
++ .len = len,
++ .flags = flags
++ };
++ wkq_err = au_wkq_wait(call_splice_to, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ return err;
++ }
++}
++
++struct splice_from_args {
++ long *errp;
++ struct pipe_inode_info *pipe;
++ struct file *out;
++ loff_t *ppos;
++ size_t len;
++ unsigned int flags;
++ struct vfsub_args *vargs;
++};
++
++static void call_splice_from(void *args)
++{
++ struct splice_from_args *a = args;
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_splice_from(a->pipe, a->out, a->ppos, a->len,
++ a->flags);
++ if (unlikely(*a->errp < 0))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++}
++
++long vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out,
++ loff_t *ppos, size_t len, unsigned int flags,
++ struct vfsub_args *vargs)
++{
++ long err;
++ struct splice_from_args args = {
++ .errp = &err,
++ .pipe = pipe,
++ .out = out,
++ .ppos = ppos,
++ .len = len,
++ .flags = flags,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT))
++ call_splice_from(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_splice_from, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct getattr_args {
++ int *errp;
++ struct vfsmount *mnt;
++ struct dentry *dentry;
++ struct kstat *st;
++};
++
++static void call_getattr(void *args)
++{
++ struct getattr_args *a = args;
++ *a->errp = do_vfsub_getattr(a->mnt, a->dentry, a->st);
++}
++
++int vfsub_getattr(struct vfsmount *mnt, struct dentry *dentry, struct kstat *st,
++ int dlgt)
++{
++ if (!dlgt)
++ return do_vfsub_getattr(mnt, dentry, st);
++ else {
++ int err, wkq_err;
++ struct getattr_args args = {
++ .errp = &err,
++ .mnt = mnt,
++ .dentry = dentry,
++ .st = st
++ };
++ wkq_err = au_wkq_wait(call_getattr, &args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ return err;
++ }
++}
+diff --git a/fs/aufs/hinode.h b/fs/aufs/hinode.h
+new file mode 100644
+index 0000000..f14b664
+--- /dev/null
++++ b/fs/aufs/hinode.h
+@@ -0,0 +1,184 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * lower (branch filesystem) inode and setting inotify
++ *
++ * $Id: hinode.h,v 1.15 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_HINODE_H__
++#define __AUFS_HINODE_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/inotify.h>
++#include <linux/version.h>
++#include <linux/aufs_type.h>
++//#include "branch.h"
++//#include "inode.h"
++//#include "vfsub.h"
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++#else
++struct inotify_watch {
++ /* empty */
++};
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++struct au_hinotify {
++#ifdef CONFIG_AUFS_HINOTIFY
++ struct au_splhead hin_ignore;
++ struct inotify_watch hin_watch;
++ struct inode *hin_aufs_inode; /* no get/put */
++#endif
++};
++
++struct au_hinode {
++ struct inode *hi_inode;
++ aufs_bindex_t hi_id;
++#ifdef CONFIG_AUFS_HINOTIFY
++ struct au_hinotify *hi_notify;
++#endif
++
++ /* reference to the copied-up whiteout with get/put */
++ struct dentry *hi_whdentry;
++};
++
++struct au_hin_ignore {
++#ifdef CONFIG_AUFS_HINOTIFY
++ struct list_head ign_list;
++
++ pid_t ign_pid;
++ __u32 ign_events, ign_handled;
++ struct au_hinode *ign_hinode;
++#endif
++};
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_HINOTIFY
++/* inotify events */
++static const __u32 AuInMask = (IN_MOVE | IN_DELETE | IN_CREATE
++ /* | IN_ACCESS */
++ | IN_MODIFY | IN_ATTRIB
++ /* | IN_DELETE_SELF | IN_MOVE_SELF */
++ );
++
++static inline
++void au_hin_init(struct au_hinode *hinode, struct au_hinotify *val)
++{
++ hinode->hi_notify = val;
++}
++
++/* hinotify.c */
++int au_hin_alloc(struct au_hinode *hinode, struct inode *inode,
++ struct inode *h_inode);
++void au_hin_free(struct au_hinode *hinode);
++void au_hin_ctl(struct au_hinode *hinode, const __u32 mask);
++void au_reset_hinotify(struct inode *inode, unsigned int flags);
++
++int au_hin_verify_gen(struct dentry *dentry);
++
++int __init au_inotify_init(void);
++void au_inotify_fin(void);
++
++static inline void au_hin_suspend(struct au_hinode *hinode)
++{
++ au_hin_ctl(hinode, 0);
++}
++
++static inline void au_hin_resume(struct au_hinode *hinode)
++{
++ au_hin_ctl(hinode, AuInMask);
++}
++
++#else
++
++static inline
++void au_hin_init(struct au_hinode *hinode, struct au_hinotify *val)
++{
++ /* empty */
++}
++
++static inline
++int au_hin_alloc(struct au_hinode *hinode, struct inode *inode,
++ struct inode *h_inode)
++{
++ return -EOPNOTSUPP;
++}
++
++static inline void au_hin_free(struct au_hinode *hinode)
++{
++ /* nothing */
++}
++
++static inline void au_reset_hinotify(struct inode *inode, unsigned int flags)
++{
++ /* nothing */
++}
++
++static inline int au_hin_verify_gen(struct dentry *dentry)
++{
++ return 0;
++}
++
++static inline int au_inotify_init(void)
++{
++ return 0;
++}
++
++#define au_inotify_fin() do {} while (0)
++
++static inline void au_hin_suspend(struct au_hinode *hinode)
++{
++ /* empty */
++}
++
++static inline void au_hin_resume(struct au_hinode *hinode)
++{
++ /* empty */
++}
++#endif /* CONFIG_AUFS_HINOTIFY */
++
++#if defined(CONFIG_AUFS_HINOTIFY) && defined(CONFIG_AUFS_DEBUG)
++static inline void au_hin_list_del(struct list_head *e)
++{
++ list_del_init(e);
++}
++
++void au_dbg_hin_list(struct vfsub_args *vargs);
++#else
++static inline void au_hin_list_del(struct list_head *e)
++{
++ list_del(e);
++}
++
++static inline void au_dbg_hin_list(struct vfsub_args *vargs)
++{
++ /* empty */
++}
++#endif /* CONFIG_AUFS_DEBUG */
++
++/* ---------------------------------------------------------------------- */
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_HINODE_H__ */
+diff --git a/fs/aufs/hinotify.c b/fs/aufs/hinotify.c
+new file mode 100644
+index 0000000..036fd43
+--- /dev/null
++++ b/fs/aufs/hinotify.c
+@@ -0,0 +1,1146 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * internal/hidden inotify handler
++ *
++ * $Id: hinotify.c,v 1.62 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/*
++#ifdef DbgInotify
++#define AuDbgHin(args...) AuDbg(##args)
++#else
++#define AuDbgHin(args...) do {} while ()
++#endif
++*/
++
++static struct inotify_handle *in_handle;
++
++AuCacheFuncs(hinotify, AuCache_HINOTIFY);
++
++int au_hin_alloc(struct au_hinode *hinode, struct inode *inode,
++ struct inode *h_inode)
++{
++ int err;
++ struct au_hinotify *hin;
++ s32 wd;
++
++ LKTRTrace("i%lu, hi%lu\n", inode->i_ino, h_inode->i_ino);
++
++ err = -ENOMEM;
++ hin = au_cache_alloc_hinotify();
++ if (hin) {
++ AuDebugOn(hinode->hi_notify);
++ hinode->hi_notify = hin;
++ au_spl_init(&hin->hin_ignore);
++ hin->hin_aufs_inode = inode;
++
++ inotify_init_watch(&hin->hin_watch);
++ wd = inotify_add_watch(in_handle, &hin->hin_watch, h_inode,
++ AuInMask);
++ if (wd >= 0)
++ return 0; /* success */
++
++ err = wd;
++ put_inotify_watch(&hin->hin_watch);
++ au_cache_free_hinotify(hin);
++ hinode->hi_notify = NULL;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++void au_hin_free(struct au_hinode *hinode)
++{
++ int err;
++ struct au_hinotify *hin;
++
++ AuTraceEnter();
++
++ hin = hinode->hi_notify;
++ if (hin) {
++ err = 0;
++ if (atomic_read(&hin->hin_watch.count))
++ err = inotify_rm_watch(in_handle, &hin->hin_watch);
++ if (unlikely(err))
++ /* it means the watch is already removed */
++ LKTRTrace("failed inotify_rm_watch() %d\n", err);
++ au_cache_free_hinotify(hin);
++ hinode->hi_notify = NULL;
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_hin_ctl(struct au_hinode *hinode, const __u32 mask)
++{
++ struct inode *h_inode;
++ struct inotify_watch *watch;
++
++ h_inode = hinode->hi_inode;
++ LKTRTrace("hi%lu, sb %p, 0x%x\n", h_inode->i_ino, h_inode->i_sb, mask);
++ IMustLock(h_inode);
++ if (!hinode->hi_notify)
++ return;
++
++ watch = &hinode->hi_notify->hin_watch;
++#if 0 /* reserved for future use */
++ {
++ u32 wd;
++ wd = inotify_find_update_watch(in_handle, h_inode, mask);
++ AuTraceErr(wd);
++ /* ignore an err; */
++ }
++#else
++ /* struct inotify_handle is hidden */
++ mutex_lock(&h_inode->inotify_mutex);
++ /* mutex_lock(&watch->ih->mutex); */
++ watch->mask = mask;
++ /* mutex_unlock(&watch->ih->mutex); */
++ mutex_unlock(&h_inode->inotify_mutex);
++#endif
++ LKTRTrace("watch %p, mask %u\n", watch, watch->mask);
++}
++
++void au_reset_hinotify(struct inode *inode, unsigned int flags)
++{
++ aufs_bindex_t bindex, bend;
++ struct inode *hi;
++ struct dentry *iwhdentry;
++
++ LKTRTrace("i%lu, 0x%x\n", inode->i_ino, flags);
++
++ bend = au_ibend(inode);
++ for (bindex = au_ibstart(inode); bindex <= bend; bindex++) {
++ hi = au_h_iptr(inode, bindex);
++ if (hi) {
++ //vfsub_i_lock_nested(hi, AuLsc_I_CHILD);
++ iwhdentry = au_hi_wh(inode, bindex);
++ if (iwhdentry)
++ dget(iwhdentry);
++ au_igrab(hi);
++ au_set_h_iptr(inode, bindex, NULL, 0);
++ au_set_h_iptr(inode, bindex, au_igrab(hi),
++ flags & ~AuHi_XINO);
++ iput(hi);
++ dput(iwhdentry);
++ //vfsub_i_unlock(hi);
++ }
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_unpin_gp(struct au_pin *args)
++{
++ struct au_pin1 *gp;
++
++ gp = au_pin_gp(args);
++ AuDebugOn(!gp);
++ if (gp->dentry)
++ LKTRTrace("%.*s\n", AuDLNPair(gp->dentry));
++ else
++ AuTraceEnter();
++
++ au_do_unpin(gp, NULL);
++}
++
++int au_hin_verify_gen(struct dentry *dentry)
++{
++ struct super_block *sb = dentry->d_sb;
++ au_gen_t sigen;
++ struct inode *inode;
++
++ if (!au_opt_test(au_mntflags(sb), UDBA_INOTIFY))
++ return 0;
++
++ sigen = au_sigen(dentry->d_sb);
++ inode = dentry->d_inode;
++ return au_digen(dentry) != sigen
++ || (inode && au_iigen(inode) != sigen);
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* cf. fsnotify_change() */
++__u32 vfsub_events_notify_change(struct iattr *ia)
++{
++ __u32 events;
++ const unsigned int amtime = (ATTR_ATIME | ATTR_MTIME);
++
++ events = 0;
++ if ((ia->ia_valid & (ATTR_UID | ATTR_GID | ATTR_MODE))
++ || (ia->ia_valid & amtime) == amtime)
++ events |= IN_ATTRIB;
++ if ((ia->ia_valid & ATTR_SIZE)
++ || (ia->ia_valid & amtime) == ATTR_MTIME)
++ events |= IN_MODIFY;
++ return events;
++}
++
++void vfsub_ign_hinode(struct vfsub_args *vargs, __u32 events,
++ struct au_hinode *hinode)
++{
++ struct au_hinotify *hin;
++ struct super_block *sb;
++ struct au_hin_ignore *ign;
++
++ if (!hinode)
++ return;
++
++ hin = hinode->hi_notify;
++ if (!hin || !hin->hin_watch.mask)
++ return;
++
++ sb = hin->hin_aufs_inode->i_sb;
++ AuDebugOn(!au_opt_test(au_mntflags(sb), UDBA_INOTIFY));
++
++ ign = vargs->ignore + vargs->nignore++;
++ ign->ign_events = events;
++ ign->ign_handled = 0;
++ ign->ign_hinode = hinode;
++
++ {
++ struct inode *h_inode;
++ h_inode = hinode->hi_inode;
++ if (vfsub_i_trylock(h_inode))
++ au_dbg_blocked();
++ IMustLock(h_inode);
++ }
++}
++
++static void au_hin_ignore(struct au_hin_ignore *ign)
++{
++ struct au_hinode *hinode;
++ __u32 events;
++ struct au_hinotify *hin;
++ struct inode *h_inode;
++
++ hinode = ign->ign_hinode;
++ events = ign->ign_events;
++ LKTRTrace("0x%x\n", events);
++ AuDebugOn(!hinode || !events);
++
++ hin = hinode->hi_notify;
++ h_inode = hinode->hi_inode;
++ if (h_inode && hin) {
++ LKTRTrace("hi%lu\n", h_inode->i_ino);
++#ifdef DbgInotify
++ AuDbg("hi%lu, 0x%x\n", h_inode->i_ino, events);
++#endif
++
++ au_spl_add(&ign->ign_list, &hin->hin_ignore);
++ /* AuDbg("list_add %p, 0x%x\n", ign, events); */
++ }
++#if 1 /* todo: test dlgt */
++ else
++ /*
++ * it may happen by this scenario.
++ * - a file and its parent dir exist on two branches
++ * - a file on the upper branch is opened
++ * - the parent dir and the file are removed by udba
++ * - the parent is re-accessed, and new dentry/inode in
++ * aufs is generated for it, based upon the one on the lower
++ * branch
++ * - the opened file is re-accessed, re-validated, and it may be
++ * re-connected to the new parent dentry
++ * it means the file in aufs cannot get the actual removed
++ * parent dir on the branch.
++ */
++ INIT_LIST_HEAD(&ign->ign_list);
++#endif
++}
++
++static void au_hin_unignore(struct au_hin_ignore *ign)
++{
++ struct au_hinode *hinode;
++ __u32 events;
++ struct au_hinotify *hin;
++ struct inode *h_inode;
++
++ hinode = ign->ign_hinode;
++ events = ign->ign_events;
++ LKTRTrace("0x%x\n", events);
++ /* AuDbg("0x%x\n", events); */
++ AuDebugOn(!hinode || !events);
++
++ hin = hinode->hi_notify;
++ h_inode = hinode->hi_inode;
++ if (!h_inode || !hin)
++ return;
++ LKTRTrace("hi%lu\n", h_inode->i_ino);
++#ifdef DbgInotify
++ AuDbg("hi%lu, 0x%x\n", h_inode->i_ino, events);
++#endif
++
++ spin_lock(&hin->hin_ignore.spin);
++ au_hin_list_del(&ign->ign_list);
++ spin_unlock(&hin->hin_ignore.spin);
++ /* AuDbg("list_del %p, 0x%x\n", ign, events); */
++}
++
++static int au_hin_test_ignore(u32 mask, struct au_hinotify *hin)
++{
++ int do_ignore;
++ u32 events;
++ struct au_hin_ignore *ign, *tmp;
++ struct list_head *head;
++
++ do_ignore = 0;
++ head = &hin->hin_ignore.head;
++ spin_lock(&hin->hin_ignore.spin);
++ list_for_each_entry_safe(ign, tmp, head, ign_list) {
++ /* AuDbg("ign %p\n", ign); */
++ if (ign->ign_pid == current->pid) {
++ events = (mask & ign->ign_events);
++ if (events) {
++ do_ignore = 1;
++ ign->ign_handled |= events;
++ if (ign->ign_events == ign->ign_handled) {
++ list_del_init(&ign->ign_list);
++ /*
++ AuDbg("list_del %p, 0x%x\n",
++ ign, events);
++ */
++ }
++ break;
++ }
++ }
++ }
++ spin_unlock(&hin->hin_ignore.spin);
++
++ return do_ignore;
++}
++
++void vfsub_ignore(struct vfsub_args *vargs)
++{
++ int n;
++ struct au_hin_ignore *ign;
++ struct super_block *sb;
++ struct au_hinode *hinode;
++ struct inode *h_inode;
++
++ n = vargs->nignore;
++ if (!n)
++ return;
++
++ ign = vargs->ignore;
++ hinode = ign->ign_hinode;
++ sb = hinode->hi_notify->hin_aufs_inode->i_sb;
++ h_inode = hinode->hi_inode;
++ if (au_opt_test(au_mntflags(sb), UDBA_INOTIFY)) {
++ if (vfsub_i_trylock(h_inode))
++ au_dbg_blocked();
++ IMustLock(h_inode);
++ }
++ while (n-- > 0) {
++ ign->ign_pid = current->pid;
++ au_hin_ignore(ign++);
++ }
++}
++
++void vfsub_unignore(struct vfsub_args *vargs)
++{
++ int n;
++ struct au_hin_ignore *ign;
++
++ n = vargs->nignore;
++ if (!n)
++ return;
++
++ ign = vargs->ignore;
++ while (n-- > 0)
++ au_hin_unignore(ign++);
++}
++
++#ifdef CONFIG_AUFS_DEBUG
++void au_dbg_hin_list(struct vfsub_args *vargs)
++{
++ int n;
++ struct au_hin_ignore *ign;
++
++ n = vargs->nignore;
++ if (!n)
++ return;
++
++ ign = vargs->ignore;
++ while (n-- > 0) {
++ /* AuDebugOn(!list_empty(&ign++->ign_list)); */
++ if (list_empty(&ign++->ign_list))
++ continue;
++ ign--;
++ AuDbg("%d: pid %d, 0x%x\n",
++ n + 1, ign->ign_pid, ign->ign_events);
++ au_hin_unignore(ign);
++ ign++;
++ au_dbg_blocked();
++ }
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++static char *in_name(u32 mask)
++{
++#ifdef CONFIG_AUFS_DEBUG
++#define test_ret(flag) if (mask & flag) \
++ return #flag;
++ test_ret(IN_ACCESS);
++ test_ret(IN_MODIFY);
++ test_ret(IN_ATTRIB);
++ test_ret(IN_CLOSE_WRITE);
++ test_ret(IN_CLOSE_NOWRITE);
++ test_ret(IN_OPEN);
++ test_ret(IN_MOVED_FROM);
++ test_ret(IN_MOVED_TO);
++ test_ret(IN_CREATE);
++ test_ret(IN_DELETE);
++ test_ret(IN_DELETE_SELF);
++ test_ret(IN_MOVE_SELF);
++ test_ret(IN_UNMOUNT);
++ test_ret(IN_Q_OVERFLOW);
++ test_ret(IN_IGNORED);
++ return "";
++#undef test_ret
++#else
++ return "??";
++#endif
++}
++
++/* ---------------------------------------------------------------------- */
++
++static struct dentry *lookup_wlock_by_name(char *name, unsigned int nlen,
++ struct inode *dir)
++{
++ struct dentry *dentry, *d, *parent;
++ struct qstr *dname;
++
++ LKTRTrace("%.*s, dir%lu\n", nlen, name, dir->i_ino);
++
++ parent = d_find_alias(dir);
++ if (!parent)
++ return NULL;
++
++ dentry = NULL;
++ spin_lock(&dcache_lock);
++ list_for_each_entry(d, &parent->d_subdirs, d_u.d_child) {
++ LKTRTrace("%.*s\n", AuDLNPair(d));
++ dname = &d->d_name;
++ if (dname->len != nlen || memcmp(dname->name, name, nlen))
++ continue;
++ if (!atomic_read(&d->d_count) || !d->d_fsdata) {
++ spin_lock(&d->d_lock);
++ __d_drop(d);
++ spin_unlock(&d->d_lock);
++ continue;
++ }
++
++ dentry = dget(d);
++ break;
++ }
++ spin_unlock(&dcache_lock);
++ dput(parent);
++
++ if (dentry) {
++#if 0
++ lktr_set_pid(current->pid, LktrArrayPid);
++ AuDbgDentry(dentry);
++ lktr_clear_pid(current->pid, LktrArrayPid);
++#endif
++ di_write_lock_child(dentry);
++ }
++ return dentry;
++}
++
++static struct inode *lookup_wlock_by_ino(struct super_block *sb,
++ aufs_bindex_t bindex, ino_t h_ino)
++{
++ struct inode *inode;
++ struct au_xino_entry xinoe;
++ int err;
++
++ LKTRTrace("b%d, hi%lu\n", bindex, (unsigned long)h_ino);
++ AuDebugOn(!au_opt_test_xino(au_mntflags(sb)));
++
++ inode = NULL;
++ err = au_xino_read(sb, bindex, h_ino, &xinoe);
++ if (!err && xinoe.ino)
++ inode = ilookup(sb, xinoe.ino);
++ if (!inode)
++ goto out;
++ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) {
++ AuWarn("wrong root branch\n");
++ iput(inode);
++ inode = NULL;
++ goto out;
++ }
++
++ ii_write_lock_child(inode);
++
++ out:
++ return inode;
++}
++
++static int hin_xino(struct inode *inode, struct inode *h_inode)
++{
++ int err;
++ aufs_bindex_t bindex, bend, bfound, bstart;
++ struct inode *h_i;
++
++ LKTRTrace("i%lu, hi%lu\n", inode->i_ino, h_inode->i_ino);
++
++ err = 0;
++ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) {
++ AuWarn("branch root dir was changed\n");
++ goto out;
++ }
++
++ bfound = -1;
++ bend = au_ibend(inode);
++ bstart = au_ibstart(inode);
++#if 0 /* reserved for future use */
++ if (bindex == bend) {
++ /* keep this ino in rename case */
++ goto out;
++ }
++#endif
++ for (bindex = bstart; bindex <= bend; bindex++) {
++ if (au_h_iptr(inode, bindex) == h_inode) {
++ bfound = bindex;
++ break;
++ }
++ }
++ if (bfound < 0)
++ goto out;
++
++ for (bindex = bstart; bindex <= bend; bindex++) {
++ h_i = au_h_iptr(inode, bindex);
++ if (h_i)
++ err = au_xino_write0(inode->i_sb, bindex, h_i->i_ino,
++ 0);
++ /* ignore this error */
++ /* bad action? */
++ }
++
++ /* children inode number will be broken */
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int hin_gen_tree(struct dentry *dentry)
++{
++ int err, i, j, ndentry;
++ struct au_dcsub_pages dpages;
++ struct au_dpage *dpage;
++ struct dentry **dentries;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ err = au_dpages_init(&dpages, GFP_NOFS);
++ if (unlikely(err))
++ goto out;
++ err = au_dcsub_pages(&dpages, dentry, NULL, NULL);
++ if (unlikely(err))
++ goto out_dpages;
++
++ for (i = 0; i < dpages.ndpage; i++) {
++ dpage = dpages.dpages + i;
++ dentries = dpage->dentries;
++ ndentry = dpage->ndentry;
++ for (j = 0; j < ndentry; j++) {
++ struct dentry *d;
++ d = dentries[j];
++ LKTRTrace("%.*s\n", AuDLNPair(d));
++ if (IS_ROOT(d))
++ continue;
++
++ d_drop(d);
++ au_digen_dec(d);
++ if (d->d_inode)
++ /* todo: reset children xino?
++ cached children only? */
++ au_iigen_dec(d->d_inode);
++ }
++ }
++
++ out_dpages:
++ au_dpages_free(&dpages);
++
++ /* discard children */
++ dentry_unhash(dentry);
++ dput(dentry);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * return 0 if processed.
++ */
++static int hin_gen_by_inode(char *name, unsigned int nlen, struct inode *inode,
++ const unsigned int isdir)
++{
++ int err;
++ struct dentry *d;
++ struct qstr *dname;
++
++ LKTRTrace("%.*s, i%lu\n", nlen, name, inode->i_ino);
++
++ err = 1;
++ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) {
++ AuWarn("branch root dir was changed\n");
++ err = 0;
++ goto out;
++ }
++
++ if (!isdir) {
++ AuDebugOn(!name);
++ au_iigen_dec(inode);
++ spin_lock(&dcache_lock);
++ list_for_each_entry(d, &inode->i_dentry, d_alias) {
++ dname = &d->d_name;
++ if (dname->len != nlen
++ && memcmp(dname->name, name, nlen))
++ continue;
++ err = 0;
++ spin_lock(&d->d_lock);
++ __d_drop(d);
++ au_digen_dec(d);
++ spin_unlock(&d->d_lock);
++ break;
++ }
++ spin_unlock(&dcache_lock);
++ } else {
++ au_fset_si(au_sbi(inode->i_sb), FAILED_REFRESH_DIRS);
++ d = d_find_alias(inode);
++ if (!d) {
++ au_iigen_dec(inode);
++ goto out;
++ }
++
++ dname = &d->d_name;
++ if (dname->len == nlen && !memcmp(dname->name, name, nlen))
++ err = hin_gen_tree(d);
++ dput(d);
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int hin_gen_by_name(struct dentry *dentry, const unsigned int isdir)
++{
++ int err;
++ struct inode *inode;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ inode = dentry->d_inode;
++ if (IS_ROOT(dentry)
++ /* || (inode && inode->i_ino == AUFS_ROOT_INO) */
++ ) {
++ AuWarn("branch root dir was changed\n");
++ return 0;
++ }
++
++ err = 0;
++ if (!isdir) {
++ d_drop(dentry);
++ au_digen_dec(dentry);
++ if (inode)
++ au_iigen_dec(inode);
++ } else {
++ au_fset_si(au_sbi(dentry->d_sb), FAILED_REFRESH_DIRS);
++ if (inode)
++ err = hin_gen_tree(dentry);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static void hin_attr(struct inode *inode, struct inode *h_inode)
++{
++ struct dentry *h_dentry;
++
++ LKTRTrace("i%lu, hi%lu\n", inode->i_ino, h_inode->i_ino);
++
++ if (au_h_iptr(inode, au_ibstart(inode)) != h_inode)
++ return;
++
++ h_dentry = d_find_alias(h_inode);
++ if (h_dentry) {
++ au_update_fuse_h_inode(NULL, h_dentry);
++ /* ignore an error*/
++ dput(h_dentry);
++ }
++
++ au_cpup_attr_all(inode, /*force*/1);
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* hinotify job flags */
++#define AuHinJob_XINO0 1
++#define AuHinJob_GEN (1 << 1)
++#define AuHinJob_DIRENT (1 << 2)
++#define AuHinJob_ATTR (1 << 3)
++#define AuHinJob_ISDIR (1 << 4)
++#define AuHinJob_TRYXINO0 (1 << 5)
++#define AuHinJob_MNTPNT (1 << 6)
++#define au_ftest_hinjob(flags, name) ((flags) & AuHinJob_##name)
++#define au_fset_hinjob(flags, name) { (flags) |= AuHinJob_##name; }
++#define au_fclr_hinjob(flags, name) { (flags) &= ~AuHinJob_##name; }
++
++struct hin_job_args {
++ unsigned int flags;
++ struct inode *inode, *h_inode, *dir, *h_dir;
++ struct dentry *dentry;
++ char *h_name;
++ int h_nlen;
++};
++
++static int hin_job(struct hin_job_args *a)
++{
++ const unsigned int isdir = au_ftest_hinjob(a->flags, ISDIR);
++
++ /* reset xino */
++ if (au_ftest_hinjob(a->flags, XINO0) && a->inode)
++ hin_xino(a->inode, a->h_inode);
++ /* ignore this error */
++
++ if (au_ftest_hinjob(a->flags, TRYXINO0)
++ && a->inode
++ && a->h_inode) {
++ vfsub_i_lock_nested(a->h_inode, AuLsc_I_CHILD);
++ if (!a->h_inode->i_nlink)
++ hin_xino(a->inode, a->h_inode);
++ /* ignore this error */
++ vfsub_i_unlock(a->h_inode);
++ }
++
++ /* make the generation obsolete */
++ if (au_ftest_hinjob(a->flags, GEN)) {
++ int err = -1;
++ if (a->inode)
++ err = hin_gen_by_inode(a->h_name, a->h_nlen, a->inode,
++ isdir);
++ if (err && a->dentry)
++ hin_gen_by_name(a->dentry, isdir);
++ /* ignore this error */
++ }
++
++ /* make dir entries obsolete */
++ if (au_ftest_hinjob(a->flags, DIRENT) && a->inode) {
++ struct au_vdir *vdir;
++ IiMustWriteLock(a->inode);
++ vdir = au_ivdir(a->inode);
++ if (vdir)
++ vdir->vd_jiffy = 0;
++ /* IMustLock(a->inode); */
++ /* a->inode->i_version++; */
++ }
++
++ /* update the attr */
++ if (au_ftest_hinjob(a->flags, ATTR) && a->inode && a->h_inode) {
++ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD);
++ hin_attr(a->inode, a->h_inode);
++ mutex_unlock(&a->h_inode->i_mutex);
++ }
++
++ /* can do nothing but warn */
++ if (au_ftest_hinjob(a->flags, MNTPNT)
++ && a->dentry
++ && d_mountpoint(a->dentry))
++ AuWarn("mount-point %.*s is removed or renamed\n",
++ AuDLNPair(a->dentry));
++
++ return 0;
++}
++
++/* ---------------------------------------------------------------------- */
++
++enum { CHILD, PARENT };
++struct postproc_args {
++ struct inode *h_dir, *dir, *h_child_inode;
++ u32 mask;
++ unsigned int flags[2];
++ unsigned int h_child_nlen;
++ char h_child_name[];
++};
++
++static void postproc(void *_args)
++{
++ struct postproc_args *a = _args;
++ struct super_block *sb;
++ aufs_bindex_t bindex, bend, bfound;
++ unsigned char xino, try_iput;
++ int err;
++ struct inode *inode;
++ ino_t h_ino;
++ struct hin_job_args args;
++ struct dentry *dentry;
++ struct au_sbinfo *sbinfo;
++
++ AuDebugOn(!_args);
++ AuDebugOn(!a->h_dir);
++ AuDebugOn(!a->dir);
++ AuDebugOn(!a->mask);
++ LKTRTrace("mask 0x%x %s, i%lu, hi%lu, hci%lu\n",
++ a->mask, in_name(a->mask), a->dir->i_ino, a->h_dir->i_ino,
++ a->h_child_inode ? a->h_child_inode->i_ino : 0);
++
++ inode = NULL;
++ dentry = NULL;
++ /*
++ * do not lock a->dir->i_mutex here
++ * because of d_revalidate() may cause a deadlock.
++ */
++#if 0
++ /*
++ * just wait for the dir becoming non-busy.
++ * for instance, prevent NFSD lookup from "nlink == 0" message.
++ * but it is not guranteed.
++ */
++ mutex_lock(&a->dir->i_mutex);
++ mutex_unlock(&a->dir->i_mutex);
++#endif
++
++ sb = a->dir->i_sb;
++ AuDebugOn(!sb);
++ sbinfo = au_sbi(sb);
++ AuDebugOn(!sbinfo);
++ /* big aufs lock */
++ si_noflush_write_lock(sb);
++
++ ii_read_lock_parent(a->dir);
++ bfound = -1;
++ bend = au_ibend(a->dir);
++ for (bindex = au_ibstart(a->dir); bindex <= bend; bindex++)
++ if (au_h_iptr(a->dir, bindex) == a->h_dir) {
++ bfound = bindex;
++ break;
++ }
++ ii_read_unlock(a->dir);
++ if (unlikely(bfound < 0))
++ goto out;
++
++ xino = !!au_opt_test_xino(au_mntflags(sb));
++ h_ino = 0;
++ if (a->h_child_inode)
++ h_ino = a->h_child_inode->i_ino;
++
++ if (a->h_child_nlen
++ && (au_ftest_hinjob(a->flags[CHILD], GEN)
++ || au_ftest_hinjob(a->flags[CHILD], MNTPNT)))
++ dentry = lookup_wlock_by_name(a->h_child_name, a->h_child_nlen,
++ a->dir);
++ try_iput = 0;
++ if (dentry)
++ inode = dentry->d_inode;
++ if (xino && !inode && h_ino
++ && (au_ftest_hinjob(a->flags[CHILD], XINO0)
++ || au_ftest_hinjob(a->flags[CHILD], TRYXINO0)
++ || au_ftest_hinjob(a->flags[CHILD], GEN)
++ || au_ftest_hinjob(a->flags[CHILD], ATTR))) {
++ inode = lookup_wlock_by_ino(sb, bfound, h_ino);
++ try_iput = 1;
++ }
++
++ args.flags = a->flags[CHILD];
++ args.dentry = dentry;
++ args.inode = inode;
++ args.h_inode = a->h_child_inode;
++ args.dir = a->dir;
++ args.h_dir = a->h_dir;
++ args.h_name = a->h_child_name;
++ args.h_nlen = a->h_child_nlen;
++ err = hin_job(&args);
++ if (dentry) {
++ if (dentry->d_fsdata)
++ di_write_unlock(dentry);
++ dput(dentry);
++ }
++ if (inode && try_iput) {
++ ii_write_unlock(inode);
++ iput(inode);
++ }
++
++ ii_write_lock_parent(a->dir);
++ args.flags = a->flags[PARENT];
++ args.dentry = NULL;
++ args.inode = a->dir;
++ args.h_inode = a->h_dir;
++ args.dir = NULL;
++ args.h_dir = NULL;
++ args.h_name = NULL;
++ args.h_nlen = 0;
++ err = hin_job(&args);
++ ii_write_unlock(a->dir);
++
++ out:
++ au_nwt_done(&sbinfo->si_nowait);
++ si_write_unlock(sb);
++
++ iput(a->h_child_inode);
++ iput(a->h_dir);
++ iput(a->dir);
++ kfree(a);
++}
++
++static void aufs_inotify(struct inotify_watch *watch, u32 wd, u32 mask,
++ u32 cookie, const char *h_child_name,
++ struct inode *h_child_inode)
++{
++ struct au_hinotify *hinotify;
++ struct postproc_args *args;
++ int len, wkq_err;
++ unsigned char isdir, isroot, wh;
++ char *p;
++ struct inode *dir;
++ unsigned int flags[2];
++
++ LKTRTrace("i%lu, wd %d, mask 0x%x %s, cookie 0x%x, hcname %s, hi%lu\n",
++ watch->inode->i_ino, wd, mask, in_name(mask), cookie,
++ h_child_name ? h_child_name : "",
++ h_child_inode ? h_child_inode->i_ino : 0);
++
++ /* if IN_UNMOUNT happens, there must be another bug */
++ if (mask & (IN_IGNORED | IN_UNMOUNT)) {
++ put_inotify_watch(watch);
++ return;
++ }
++
++#ifdef DbgInotify
++ if (!h_child_name || strcmp(h_child_name, AUFS_XINO_FNAME))
++ AuDbg("i%lu, wd %d, mask 0x%x %s, cookie 0x%x, hcname %s,"
++ " hi%lu\n",
++ watch->inode->i_ino, wd, mask, in_name(mask), cookie,
++ h_child_name ? h_child_name : "",
++ h_child_inode ? h_child_inode->i_ino : 0);
++#endif
++
++ hinotify = container_of(watch, struct au_hinotify, hin_watch);
++ AuDebugOn(!hinotify || !hinotify->hin_aufs_inode);
++ if (au_hin_test_ignore(mask, hinotify)) {
++#ifdef DbgInotify
++ AuDbg("ignored\n");
++#endif
++ return;
++ }
++#if 0 /* tmp debug */
++ if (h_child_name && !strcmp(h_child_name, AUFS_XINO_FNAME)) {
++ AuDbg("i%lu, wd %d, mask 0x%x %s, cookie 0x%x, hcname %s, hi%lu\n",
++ watch->inode->i_ino, wd, mask, in_name(mask), cookie,
++ h_child_name ? h_child_name : "",
++ h_child_inode ? h_child_inode->i_ino : 0);
++ //au_dbg_blocked();
++ }
++#endif
++
++ dir = igrab(hinotify->hin_aufs_inode);
++ if (!dir)
++ return;
++ isroot = (dir->i_ino == AUFS_ROOT_INO);
++ len = 0;
++ wh = 0;
++ if (h_child_name) {
++ len = strlen(h_child_name);
++ if (!memcmp(h_child_name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) {
++ h_child_name += AUFS_WH_PFX_LEN;
++ len -= AUFS_WH_PFX_LEN;
++ wh = 1;
++ }
++ }
++
++ isdir = 0;
++ if (h_child_inode)
++ isdir = !!S_ISDIR(h_child_inode->i_mode);
++ flags[PARENT] = AuHinJob_ISDIR;
++ flags[CHILD] = 0;
++ if (isdir)
++ flags[CHILD] = AuHinJob_ISDIR;
++ switch (mask & IN_ALL_EVENTS) {
++ case IN_MODIFY:
++ /*FALLTHROUGH*/
++ case IN_ATTRIB:
++ if (h_child_inode) {
++ if (!wh)
++ au_fset_hinjob(flags[CHILD], ATTR);
++ } else
++ au_fset_hinjob(flags[PARENT], ATTR);
++ break;
++
++ /* IN_MOVED_FROM is the first event in rename(2) */
++ case IN_MOVED_FROM:
++ case IN_MOVED_TO:
++ AuDebugOn(!h_child_name || !h_child_inode);
++ au_fset_hinjob(flags[CHILD], GEN);
++ au_fset_hinjob(flags[CHILD], ATTR);
++ if (1 || isdir)
++ au_fset_hinjob(flags[CHILD], XINO0);
++ au_fset_hinjob(flags[CHILD], MNTPNT);
++
++ au_fset_hinjob(flags[PARENT], ATTR);
++ au_fset_hinjob(flags[PARENT], DIRENT);
++ break;
++
++ case IN_CREATE:
++ AuDebugOn(!h_child_name || !h_child_inode);
++ au_fset_hinjob(flags[PARENT], ATTR);
++ au_fset_hinjob(flags[PARENT], DIRENT);
++ au_fset_hinjob(flags[CHILD], GEN);
++ /* hard link */
++ if (!isdir && h_child_inode->i_nlink > 1)
++ au_fset_hinjob(flags[CHILD], ATTR);
++ break;
++
++ case IN_DELETE:
++ /*
++ * aufs never be able to get this child inode.
++ * revalidation should be in d_revalidate()
++ * by checking i_nlink, i_generation or d_unhashed().
++ */
++ AuDebugOn(!h_child_name);
++ au_fset_hinjob(flags[PARENT], ATTR);
++ au_fset_hinjob(flags[PARENT], DIRENT);
++ au_fset_hinjob(flags[CHILD], GEN);
++ au_fset_hinjob(flags[CHILD], TRYXINO0);
++ au_fset_hinjob(flags[CHILD], MNTPNT);
++ break;
++
++ case IN_DELETE_SELF:
++#if 0
++ if (!isroot)
++ au_fset_hinjob(flags[PARENT], GEN);
++ /*FALLTHROUGH*/
++#endif
++
++ case IN_MOVE_SELF:
++#if 0
++ /*
++ * when an inotify is set to an aufs inode,
++ * such inode can be isolated and this event can be fired
++ * solely.
++ */
++ AuDebugOn(h_child_name || h_child_inode);
++ if (unlikely(isroot)) {
++ AuWarn("root branch was moved\n");
++ iput(dir);
++ return;
++ }
++ au_fset_hinjob(flags[PARENT], XINO0);
++ au_fset_hinjob(flags[PARENT], GEN);
++ au_fset_hinjob(flags[PARENT], ATTR);
++ au_fset_hinjob(flags[PARENT], DIRENT);
++ /* au_fset_hinjob(flags[PARENT], MNTPNT); */
++ break;
++#endif
++
++ case IN_ACCESS:
++ default:
++ AuDebugOn(1);
++ }
++
++ if (wh)
++ h_child_inode = NULL;
++
++ /* iput() and kfree() will be called in postproc() */
++ /*
++ * inotify_mutex is already acquired and kmalloc/prune_icache may lock
++ * iprune_mutex. strange.
++ */
++ lockdep_off();
++ args = kmalloc(sizeof(*args) + len + 1, GFP_NOFS);
++ lockdep_on();
++ if (unlikely(!args)) {
++ AuErr1("no memory\n");
++ iput(dir);
++ return;
++ }
++ args->flags[PARENT] = flags[PARENT];
++ args->flags[CHILD] = flags[CHILD];
++ args->mask = mask;
++ args->dir = dir;
++ args->h_dir = igrab(watch->inode);
++ if (h_child_inode)
++ h_child_inode = igrab(h_child_inode); /* can be NULL */
++ args->h_child_inode = h_child_inode;
++ args->h_child_nlen = len;
++ if (len) {
++ p = (void *)args;
++ p += sizeof(*args);
++ memcpy(p, h_child_name, len + 1);
++ }
++
++ lockdep_off();
++ wkq_err = au_wkq_nowait(postproc, args, dir->i_sb, /*dlgt*/0);
++ lockdep_on();
++ if (unlikely(wkq_err))
++ AuErr("wkq %d\n", wkq_err);
++}
++
++static void aufs_inotify_destroy(struct inotify_watch *watch)
++{
++ return;
++}
++
++static struct inotify_operations aufs_inotify_ops = {
++ .handle_event = aufs_inotify,
++ .destroy_watch = aufs_inotify_destroy
++};
++
++/* ---------------------------------------------------------------------- */
++
++static void au_hin_destroy_cache(void)
++{
++ kmem_cache_destroy(au_cachep[AuCache_HINOTIFY]);
++ au_cachep[AuCache_HINOTIFY] = NULL;
++}
++
++int __init au_inotify_init(void)
++{
++ int err;
++
++ err = -ENOMEM;
++ au_cachep[AuCache_HINOTIFY] = AuCache(au_hinotify);
++ if (au_cachep[AuCache_HINOTIFY]) {
++ err = 0;
++ in_handle = inotify_init(&aufs_inotify_ops);
++ if (IS_ERR(in_handle)) {
++ err = PTR_ERR(in_handle);
++ au_hin_destroy_cache();
++ }
++ }
++ AuTraceErr(err);
++ return err;
++}
++
++void au_inotify_fin(void)
++{
++ inotify_destroy(in_handle);
++ if (au_cachep[AuCache_HINOTIFY])
++ au_hin_destroy_cache();
++}
+diff --git a/fs/aufs/i_op.c b/fs/aufs/i_op.c
+new file mode 100644
+index 0000000..3153263
+--- /dev/null
++++ b/fs/aufs/i_op.c
+@@ -0,0 +1,954 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode operations (except add/del/rename)
++ *
++ * $Id: i_op.c,v 1.79 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++//#include <linux/fs.h>
++//#include <linux/namei.h>
++#include <linux/mm.h>
++#include "aufs.h"
++
++static int silly_lock(struct inode *inode, struct nameidata *nd)
++{
++ int locked = 0;
++ struct super_block *sb = inode->i_sb;
++
++ LKTRTrace("i%lu, nd %p\n", inode->i_ino, nd);
++
++ if (!nd || !nd->dentry) {
++ si_read_lock(sb, AuLock_FLUSH);
++ ii_read_lock_child(inode);
++ } else if (nd->dentry->d_inode != inode) {
++ locked = 1;
++ /* lock child first, then parent */
++ si_read_lock(sb, AuLock_FLUSH);
++ ii_read_lock_child(inode);
++ di_read_lock_parent(nd->dentry, 0);
++ } else {
++ locked = 2;
++ aufs_read_lock(nd->dentry, AuLock_FLUSH | AuLock_IR);
++ }
++ return locked;
++}
++
++static void silly_unlock(int locked, struct inode *inode, struct nameidata *nd)
++{
++ struct super_block *sb = inode->i_sb;
++
++ LKTRTrace("locked %d, i%lu, nd %p\n", locked, inode->i_ino, nd);
++
++ switch (locked) {
++ case 0:
++ ii_read_unlock(inode);
++ si_read_unlock(sb);
++ break;
++ case 1:
++ di_read_unlock(nd->dentry, 0);
++ ii_read_unlock(inode);
++ si_read_unlock(sb);
++ break;
++ case 2:
++ aufs_read_unlock(nd->dentry, AuLock_FLUSH | AuLock_IR);
++ break;
++ default:
++ BUG();
++ }
++}
++
++static int h_permission(struct inode *h_inode, int mask,
++ struct nameidata *fake_nd, int brperm, int dlgt)
++{
++ int err, submask;
++ const int write_mask = (mask & (MAY_WRITE | MAY_APPEND));
++
++ LKTRTrace("ino %lu, mask 0x%x, brperm 0x%x\n",
++ h_inode->i_ino, mask, brperm);
++
++ err = -EACCES;
++ if ((write_mask && IS_IMMUTABLE(h_inode))
++ || ((mask & MAY_EXEC) && S_ISREG(h_inode->i_mode)
++ && fake_nd && fake_nd->mnt
++ && (fake_nd->mnt->mnt_flags & MNT_NOEXEC)))
++ goto out;
++
++ /*
++ * - skip hidden fs test in the case of write to ro branch.
++ * - nfs dir permission write check is optimized, but a policy for
++ * link/rename requires a real check.
++ */
++ submask = mask & ~MAY_APPEND;
++ if ((write_mask && !au_br_writable(brperm))
++ || (au_test_nfs(h_inode->i_sb) && S_ISDIR(h_inode->i_mode)
++ && write_mask && !(mask & MAY_READ))
++ || !h_inode->i_op
++ || !h_inode->i_op->permission) {
++ /* LKTRLabel(generic_permission); */
++ err = generic_permission(h_inode, submask, NULL);
++ } else {
++ /* LKTRLabel(h_inode->permission); */
++ err = h_inode->i_op->permission(h_inode, submask, fake_nd);
++ AuTraceErr(err);
++ }
++
++#if 1 /* todo: export? */
++ if (!err)
++ err = au_security_inode_permission(h_inode, mask, fake_nd,
++ dlgt);
++#endif
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int aufs_permission(struct inode *inode, int mask, struct nameidata *nd)
++{
++ int err;
++ aufs_bindex_t bindex, bend;
++ unsigned char locked, dlgt, do_nd;
++ const unsigned char isdir = S_ISDIR(inode->i_mode);
++ struct inode *h_inode;
++ struct super_block *sb;
++ unsigned int mnt_flags;
++ struct path path;
++ const int write_mask = (mask & (MAY_WRITE | MAY_APPEND));
++
++ LKTRTrace("ino %lu, mask 0x%x, isdir %d, write_mask %d, "
++ "nd %d{%d, %d}\n",
++ inode->i_ino, mask, isdir, write_mask,
++ !!nd, nd ? !!nd->dentry : 0, nd ? !!nd->mnt : 0);
++
++ sb = inode->i_sb;
++ locked = silly_lock(inode, nd);
++ do_nd = (nd && locked >= 1);
++ mnt_flags = au_mntflags(sb);
++ dlgt = !!au_test_dlgt(mnt_flags);
++
++ if (!isdir || write_mask || au_test_dirperm1(mnt_flags)) {
++ h_inode = au_h_iptr(inode, au_ibstart(inode));
++ AuDebugOn(!h_inode
++ || ((h_inode->i_mode & S_IFMT)
++ != (inode->i_mode & S_IFMT)));
++ err = 0;
++ bindex = au_ibstart(inode);
++ LKTRTrace("b%d\n", bindex);
++ if (do_nd) {
++ path.mnt = nd->mnt;
++ path.dentry = nd->dentry;
++ nd->mnt = mntget(au_sbr_mnt(sb, bindex));
++ nd->dentry = dget(au_h_dptr(nd->dentry, bindex));
++ err = h_permission(h_inode, mask, nd,
++ au_sbr_perm(sb, bindex), dlgt);
++ path_release(nd);
++ nd->mnt = path.mnt;
++ nd->dentry = path.dentry;
++ } else {
++ AuDebugOn(nd && nd->mnt);
++ err = h_permission(h_inode, mask, nd,
++ au_sbr_perm(sb, bindex), dlgt);
++ }
++
++ if (write_mask && !err) {
++ /* test whether the upper writable branch exists */
++ err = -EROFS;
++ for (; bindex >= 0; bindex--)
++ if (!au_br_rdonly(au_sbr(sb, bindex))) {
++ err = 0;
++ break;
++ }
++ }
++ goto out;
++ }
++
++ /* non-write to dir */
++ if (do_nd) {
++ path.mnt = nd->mnt;
++ path.dentry = nd->dentry;
++ } else {
++ path.mnt = NULL;
++ path.dentry = NULL;
++ }
++ err = 0;
++ bend = au_ibend(inode);
++ for (bindex = au_ibstart(inode); !err && bindex <= bend; bindex++) {
++ h_inode = au_h_iptr(inode, bindex);
++ if (!h_inode)
++ continue;
++ AuDebugOn(!S_ISDIR(h_inode->i_mode));
++
++ LKTRTrace("b%d\n", bindex);
++ if (do_nd) {
++ nd->mnt = mntget(au_sbr_mnt(sb, bindex));
++ nd->dentry = dget(au_h_dptr(path.dentry, bindex));
++ err = h_permission(h_inode, mask, nd,
++ au_sbr_perm(sb, bindex), dlgt);
++ path_release(nd);
++ } else {
++ AuDebugOn(nd && nd->mnt);
++ err = h_permission(h_inode, mask, nd,
++ au_sbr_perm(sb, bindex), dlgt);
++ }
++ }
++ if (do_nd) {
++ nd->mnt = path.mnt;
++ nd->dentry = path.dentry;
++ }
++
++ out:
++ silly_unlock(locked, inode, nd);
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static struct dentry *aufs_lookup(struct inode *dir, struct dentry *dentry,
++ struct nameidata *nd)
++{
++ struct dentry *ret, *parent;
++ int err, npositive;
++ struct inode *inode, *h_inode;
++ struct nameidata tmp_nd, *ndp;
++ aufs_bindex_t bstart;
++ struct mutex *mtx;
++ struct super_block *sb;
++
++ LKTRTrace("dir %lu, %.*s, nd{0x%x}\n",
++ dir->i_ino, AuDLNPair(dentry), nd ? nd->flags : 0);
++ AuDebugOn(IS_ROOT(dentry));
++ IMustLock(dir);
++
++ sb = dir->i_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ err = au_alloc_dinfo(dentry);
++ ret = ERR_PTR(err);
++ if (unlikely(err))
++ goto out;
++
++ /* nd can be NULL */
++ ndp = au_dup_nd(au_sbi(sb), &tmp_nd, nd);
++ parent = dentry->d_parent; /* dir inode is locked */
++ di_read_lock_parent(parent, AuLock_IR);
++ npositive = au_lkup_dentry(dentry, au_dbstart(parent), /*type*/0, ndp);
++ di_read_unlock(parent, AuLock_IR);
++ err = npositive;
++ ret = ERR_PTR(err);
++ if (unlikely(err < 0))
++ goto out_unlock;
++
++ inode = NULL;
++ if (npositive) {
++ bstart = au_dbstart(dentry);
++ h_inode = au_h_dptr(dentry, bstart)->d_inode;
++ AuDebugOn(!h_inode);
++ if (!S_ISDIR(h_inode->i_mode)) {
++ /*
++ * stop 'race'-ing between hardlinks under different
++ * parents.
++ */
++ mtx = &au_sbr(sb, bstart)->br_xino.xi_nondir_mtx;
++ mutex_lock(mtx);
++ inode = au_new_inode(dentry, /*must_new*/0);
++ mutex_unlock(mtx);
++ } else
++ inode = au_new_inode(dentry, /*must_new*/0);
++ ret = (void *)inode;
++ }
++ if (!IS_ERR(inode)) {
++ ret = d_splice_alias(inode, dentry);
++ if (unlikely(IS_ERR(ret) && inode))
++ ii_write_unlock(inode);
++ AuDebugOn(nd
++ && (nd->flags & LOOKUP_OPEN)
++ && nd->intent.open.file
++ && nd->intent.open.file->f_dentry);
++ au_store_fmode_exec(nd, inode);
++ }
++
++ out_unlock:
++ di_write_unlock(dentry);
++ out:
++ si_read_unlock(sb);
++ AuTraceErrPtr(ret);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return ret;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * decide the branch and the parent dir where we will create a new entry.
++ * returns new bindex or an error.
++ * copyup the parent dir if needed.
++ */
++int au_wr_dir(struct dentry *dentry, struct dentry *src_dentry,
++ struct au_wr_dir_args *args)
++{
++ int err;
++ aufs_bindex_t bcpup, bstart, src_bstart;
++ struct super_block *sb;
++ struct dentry *parent;
++ struct au_sbinfo *sbinfo;
++ const int add_entry = au_ftest_wrdir(args->flags, ADD_ENTRY);
++
++ LKTRTrace("%.*s, src %p, {%d, 0x%x}\n",
++ AuDLNPair(dentry), src_dentry, args->force_btgt, args->flags);
++
++ sb = dentry->d_sb;
++ sbinfo = au_sbi(sb);
++ parent = dget_parent(dentry);
++ bstart = au_dbstart(dentry);
++ bcpup = bstart;
++ if (args->force_btgt < 0) {
++ if (src_dentry) {
++ src_bstart = au_dbstart(src_dentry);
++ if (src_bstart < bstart)
++ bcpup = src_bstart;
++ } else if (add_entry) {
++ err = AuWbrCreate(sbinfo, dentry,
++ au_ftest_wrdir(args->flags, ISDIR));
++ bcpup = err;
++ }
++
++ if (bcpup < 0 || au_test_ro(sb, bcpup, dentry->d_inode)) {
++ if (add_entry)
++ err = AuWbrCopyup(sbinfo, dentry);
++ else {
++ if (!IS_ROOT(dentry)) {
++ di_read_lock_parent(parent, !AuLock_IR);
++ err = AuWbrCopyup(sbinfo, dentry);
++ di_read_unlock(parent, !AuLock_IR);
++ } else
++ err = AuWbrCopyup(sbinfo, dentry);
++ }
++ bcpup = err;
++ if (unlikely(err < 0))
++ goto out;
++ }
++ } else {
++ bcpup = args->force_btgt;
++ AuDebugOn(au_test_ro(sb, bcpup, dentry->d_inode));
++ }
++ LKTRTrace("bstart %d, bcpup %d\n", bstart, bcpup);
++ if (bstart < bcpup)
++ au_update_dbrange(dentry, /*do_put_zero*/1);
++
++ err = bcpup;
++ if (bcpup == bstart)
++ goto out; /* success */
++
++ /* copyup the new parent into the branch we process */
++ if (add_entry) {
++ au_update_dbstart(dentry);
++ IMustLock(parent->d_inode);
++ DiMustWriteLock(parent);
++ IiMustWriteLock(parent->d_inode);
++ } else
++ di_write_lock_parent(parent);
++
++ err = 0;
++ if (!au_h_dptr(parent, bcpup)) {
++ if (bstart < bcpup)
++ err = au_cpdown_dirs(dentry, bcpup);
++ else
++ err = au_cpup_dirs(dentry, bcpup);
++ }
++ if (!err && add_entry) {
++ struct dentry *h_parent;
++ struct inode *h_dir;
++
++ h_parent = au_h_dptr(parent, bcpup);
++ AuDebugOn(!h_parent);
++ h_dir = h_parent->d_inode;
++ AuDebugOn(!h_dir);
++ vfsub_i_lock_nested(h_parent->d_inode, AuLsc_I_PARENT);
++ err = au_lkup_neg(dentry, bcpup);
++ vfsub_i_unlock(h_parent->d_inode);
++ if (bstart < bcpup && au_dbstart(dentry) < 0) {
++ au_set_dbstart(dentry, 0);
++ au_update_dbrange(dentry, /*do_put_zero*/0);
++ }
++ }
++
++ if (!add_entry)
++ di_write_unlock(parent);
++ if (!err)
++ err = bcpup; /* success */
++ out:
++ dput(parent);
++ LKTRTrace("err %d\n", err);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct dentry *au_do_pinned_h_parent(struct au_pin1 *pin)
++{
++ if (pin && pin->parent)
++ return au_h_dptr(pin->parent, pin->bindex);
++ return NULL;
++}
++
++void au_do_unpin(struct au_pin1 *p, struct au_pin1 *gp)
++{
++ if (p->dentry)
++ LKTRTrace("%.*s\n", AuDLNPair(p->dentry));
++ LKTRTrace("p{%d, %d, %d, %d, 0x%x}, gp %p\n",
++ p->lsc_di, p->lsc_hi, !!p->parent, !!p->h_dir, p->flags, gp);
++
++ if (au_ftest_pin(p->flags, MNT_WRITE))
++ au_br_drop_write(au_sbr(p->dentry->d_sb, p->bindex));
++ if (au_ftest_pin(p->flags, VFS_RENAME))
++ vfsub_unlock_rename_mutex(au_sbr_sb(p->dentry->d_sb,
++ p->bindex));
++ if (!p->h_dir)
++ return;
++
++ vfsub_i_unlock(p->h_dir);
++ if (gp)
++ au_do_unpin(gp, NULL);
++ if (!au_ftest_pin(p->flags, DI_LOCKED))
++ di_read_unlock(p->parent, AuLock_IR);
++ iput(p->h_dir);
++ dput(p->parent);
++ p->parent = NULL;
++ p->h_dir = NULL;
++}
++
++int au_do_pin(struct au_pin1 *p, struct au_pin1 *gp)
++{
++ int err;
++ struct dentry *h_dentry;
++
++ LKTRTrace("%.*s, %d, b%d, 0x%x\n",
++ AuDLNPair(p->dentry), !!gp, p->bindex, p->flags);
++ AuDebugOn(au_ftest_pin(p->flags, DO_GPARENT) && !gp);
++ /* AuDebugOn(!do_gp && gp); */
++
++ err = 0;
++ if (IS_ROOT(p->dentry)) {
++ if (au_ftest_pin(p->flags, VFS_RENAME))
++ vfsub_lock_rename_mutex(au_sbr_sb(p->dentry->d_sb,
++ p->bindex));
++ if (au_ftest_pin(p->flags, MNT_WRITE)) {
++ err = au_br_want_write(au_sbr(p->dentry->d_sb,
++ p->bindex));
++ if (unlikely(err))
++ au_fclr_pin(p->flags, MNT_WRITE);
++ }
++ goto out;
++ }
++
++ h_dentry = NULL;
++ if (p->bindex <= au_dbend(p->dentry))
++ h_dentry = au_h_dptr(p->dentry, p->bindex);
++
++ p->parent = dget_parent(p->dentry);
++ if (!au_ftest_pin(p->flags, DI_LOCKED))
++ di_read_lock(p->parent, AuLock_IR, p->lsc_di);
++ else
++ DiMustAnyLock(p->parent);
++ AuDebugOn(!p->parent->d_inode);
++ p->h_dir = au_igrab(au_h_iptr(p->parent->d_inode, p->bindex));
++ /* udba case */
++ if (unlikely(au_ftest_pin(p->flags, VERIFY) && !p->h_dir)) {
++ err = -EIO;
++ if (!au_ftest_pin(p->flags, DI_LOCKED))
++ di_read_unlock(p->parent, AuLock_IR);
++ dput(p->parent);
++ p->parent = NULL;
++ goto out;
++ }
++
++ if (au_ftest_pin(p->flags, DO_GPARENT)) {
++ gp->dentry = p->parent;
++ err = au_do_pin(gp, NULL);
++ if (unlikely(err))
++ gp->dentry = NULL;
++ }
++ if (au_ftest_pin(p->flags, VFS_RENAME))
++ vfsub_lock_rename_mutex(p->h_dir->i_sb);
++ vfsub_i_lock_nested(p->h_dir, p->lsc_hi);
++ if (!err) {
++ /* todo: call d_revalidate() here? */
++#if 0
++ if (h_dentry && h_dentry->d_op && h_dentry->d_op->d_revalidate
++ && !h_dentry->d_op->d_revalidate(h_dentry, NULL))
++ err = -EIO;
++#endif
++ if (!h_dentry
++ || !au_ftest_pin(p->flags, VERIFY)
++ || !au_verify_parent(h_dentry, p->h_dir)) {
++ if (au_ftest_pin(p->flags, MNT_WRITE)) {
++ err = au_br_want_write(au_sbr(p->dentry->d_sb,
++ p->bindex));
++ if (unlikely(err))
++ au_fclr_pin(p->flags, MNT_WRITE);
++ }
++ if (!err)
++ goto out; /* success */
++ } else
++ err = -EIO;
++ }
++
++ AuDbgDentry(p->dentry);
++ AuDbgDentry(h_dentry);
++ AuDbgDentry(p->parent);
++ AuDbgInode(p->h_dir);
++ if (h_dentry)
++ AuDbgDentry(h_dentry->d_parent);
++
++ au_do_unpin(p, gp);
++ if (au_ftest_pin(p->flags, DO_GPARENT))
++ gp->dentry = NULL;
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++void au_pin_init(struct au_pin *args, struct dentry *dentry,
++ aufs_bindex_t bindex, int lsc_di, int lsc_hi,
++ unsigned char flags)
++{
++ struct au_pin1 *p;
++ unsigned char f;
++
++ AuTraceEnter();
++
++ memset(args, 0, sizeof(*args));
++ p = args->pin + AuPin_PARENT;
++ p->dentry = dentry;
++ p->lsc_di = lsc_di;
++ p->lsc_hi = lsc_hi;
++ p->flags = flags;
++ p->bindex = bindex;
++ if (!au_opt_test(au_mntflags(dentry->d_sb), UDBA_NONE))
++ au_fset_pin(p->flags, VERIFY);
++ if (!au_ftest_pin(flags, DO_GPARENT))
++ return;
++
++ f = p->flags;
++ p = au_pin_gp(args);
++ if (p) {
++ p->lsc_di = lsc_di + 1; /* child first */
++ p->lsc_hi = lsc_hi - 1; /* parent first */
++ p->bindex = bindex;
++ p->flags = f & ~(AuPin_MNT_WRITE
++ | AuPin_DO_GPARENT
++ | AuPin_DI_LOCKED);
++ }
++}
++
++int au_pin(struct au_pin *args, struct dentry *dentry, aufs_bindex_t bindex,
++ unsigned char flags)
++{
++ LKTRTrace("%.*s, b%d, 0x%x\n",
++ AuDLNPair(dentry), bindex, flags);
++
++ au_pin_init(args, dentry, bindex, AuLsc_DI_PARENT, AuLsc_I_PARENT2,
++ flags);
++ return au_do_pin(args->pin + AuPin_PARENT, au_pin_gp(args));
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct au_icpup_args {
++ unsigned char isdir, hinotify, did_cpup; /* flags */
++ unsigned char pin_flags;
++ aufs_bindex_t btgt;
++ struct au_pin pin;
++ struct au_hin_ignore ign[2];
++ struct vfsub_args vargs;
++ struct dentry *h_dentry;
++ struct inode *h_inode;
++};
++
++/* todo: refine it */
++static int au_lock_and_icpup(struct dentry *dentry, loff_t sz,
++ struct au_icpup_args *a)
++{
++ int err;
++ aufs_bindex_t bstart;
++ struct super_block *sb;
++ struct dentry *hi_wh, *parent;
++ struct inode *inode;
++ struct au_wr_dir_args wr_dir_args = {
++ .force_btgt = -1,
++ .flags = 0
++ };
++
++ LKTRTrace("%.*s, %lld\n", AuDLNPair(dentry), sz);
++
++ di_write_lock_child(dentry);
++ bstart = au_dbstart(dentry);
++ sb = dentry->d_sb;
++ inode = dentry->d_inode;
++ a->isdir = !!S_ISDIR(inode->i_mode);
++ if (a->isdir)
++ au_fset_wrdir(wr_dir_args.flags, ISDIR);
++ /* plink or hi_wh() */
++ if (bstart != au_ibstart(inode))
++ wr_dir_args.force_btgt = au_ibstart(inode);
++ err = au_wr_dir(dentry, /*src_dentry*/NULL, &wr_dir_args);
++ if (unlikely(err < 0))
++ goto out_dentry;
++ a->btgt = err;
++ a->did_cpup = (err != bstart);
++ err = 0;
++
++ /* crazy udba locks */
++ a->pin_flags = AuPin_MNT_WRITE;
++ a->hinotify = !!au_opt_test(au_mntflags(sb), UDBA_INOTIFY);
++ if (a->hinotify)
++ au_fset_pin(a->pin_flags, DO_GPARENT);
++ parent = NULL;
++ if (!IS_ROOT(dentry)) {
++ au_fset_pin(a->pin_flags, DI_LOCKED);
++ parent = dget_parent(dentry);
++ di_write_lock_parent(parent);
++ }
++ err = au_pin(&a->pin, dentry, a->btgt, a->pin_flags);
++ if (unlikely(err)) {
++ if (parent) {
++ di_write_unlock(parent);
++ dput(parent);
++ }
++ goto out_dentry;
++ }
++ a->h_dentry = au_h_dptr(dentry, bstart);
++ a->h_inode = a->h_dentry->d_inode;
++ AuDebugOn(!a->h_inode);
++ vfsub_i_lock_nested(a->h_inode, AuLsc_I_CHILD);
++ if (!a->did_cpup) {
++ au_unpin_gp(&a->pin);
++ if (parent) {
++ au_pin_set_parent_lflag(&a->pin, /*lflag*/0);
++ di_downgrade_lock(parent, AuLock_IR);
++ dput(parent);
++ }
++ goto out; /* success */
++ }
++
++ hi_wh = NULL;
++ if (!d_unhashed(dentry)) {
++ if (parent) {
++ au_pin_set_parent_lflag(&a->pin, /*lflag*/0);
++ di_downgrade_lock(parent, AuLock_IR);
++ dput(parent);
++ }
++ err = au_sio_cpup_simple(dentry, a->btgt, sz, AuCpup_DTIME);
++ if (!err)
++ a->h_dentry = au_h_dptr(dentry, a->btgt);
++ } else {
++ hi_wh = au_hi_wh(inode, a->btgt);
++ if (!hi_wh) {
++ err = au_sio_cpup_wh(dentry, a->btgt, sz,
++ /*file*/NULL);
++ if (!err)
++ hi_wh = au_hi_wh(inode, a->btgt);
++ /* todo: revalidate hi_wh? */
++ }
++ if (parent) {
++ au_pin_set_parent_lflag(&a->pin, /*lflag*/0);
++ di_downgrade_lock(parent, AuLock_IR);
++ dput(parent);
++ }
++ if (!hi_wh)
++ a->h_dentry = au_h_dptr(dentry, a->btgt);
++ else
++ a->h_dentry = hi_wh; /* do not dget here */
++ }
++
++ vfsub_i_unlock(a->h_inode);
++ a->h_inode = a->h_dentry->d_inode;
++ AuDebugOn(!a->h_inode);
++ if (!err) {
++ vfsub_i_lock_nested(a->h_inode, AuLsc_I_CHILD);
++ au_unpin_gp(&a->pin);
++ goto out; /* success */
++ }
++
++ au_unpin(&a->pin);
++
++ out_dentry:
++ di_write_unlock(dentry);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int aufs_setattr(struct dentry *dentry, struct iattr *ia)
++{
++ int err;
++ struct inode *inode;
++ struct super_block *sb;
++ __u32 events;
++ struct file *file;
++ loff_t sz;
++ struct au_icpup_args *a;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ inode = dentry->d_inode;
++ IMustLock(inode);
++
++ err = -ENOMEM;
++ a = kzalloc(sizeof(*a), GFP_NOFS);
++ if (unlikely(!a))
++ goto out;
++
++ file = NULL;
++ sb = dentry->d_sb;
++ si_read_lock(sb, AuLock_FLUSH);
++ vfsub_args_init(&a->vargs, a->ign, au_test_dlgt(au_mntflags(sb)), 0);
++
++ if (ia->ia_valid & ATTR_FILE) {
++ /* currently ftruncate(2) only */
++ file = ia->ia_file;
++ fi_write_lock(file);
++ ia->ia_file = au_h_fptr(file, au_fbstart(file));
++ }
++
++ sz = -1;
++ if ((ia->ia_valid & ATTR_SIZE)
++ && ia->ia_size < i_size_read(inode))
++ sz = ia->ia_size;
++ err = au_lock_and_icpup(dentry, sz, a);
++ if (unlikely(err < 0))
++ goto out_si;
++ if (a->did_cpup) {
++ ia->ia_file = NULL;
++ ia->ia_valid &= ~ATTR_FILE;
++ }
++
++ if ((ia->ia_valid & ATTR_SIZE)
++ && ia->ia_size < i_size_read(inode)) {
++ err = vmtruncate(inode, ia->ia_size);
++ if (unlikely(err))
++ goto out_unlock;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++ if (ia->ia_valid & (ATTR_KILL_SUID | ATTR_KILL_SGID))
++ ia->ia_valid &= ~ATTR_MODE;
++#endif
++
++ events = 0;
++ if (a->hinotify) {
++ events = vfsub_events_notify_change(ia);
++ if (events) {
++ if (a->isdir)
++ vfsub_ign_hinode(&a->vargs, events,
++ au_hi(inode, a->btgt));
++ vfsub_ign_hinode(&a->vargs, events,
++ au_pinned_hdir(&a->pin));
++ }
++ }
++ err = vfsub_notify_change(a->h_dentry, ia, &a->vargs);
++ if (!err)
++ au_cpup_attr_changeable(inode);
++
++ out_unlock:
++ vfsub_i_unlock(a->h_inode);
++ au_unpin(&a->pin);
++ di_write_unlock(dentry);
++ out_si:
++ if (file) {
++ fi_write_unlock(file);
++ ia->ia_file = file;
++ ia->ia_valid |= ATTR_FILE;
++ }
++ si_read_unlock(sb);
++ kfree(a);
++ out:
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int h_readlink(struct dentry *dentry, int bindex, char __user *buf,
++ int bufsiz)
++{
++ struct super_block *sb;
++ struct dentry *h_dentry;
++
++ LKTRTrace("%.*s, b%d, %d\n", AuDLNPair(dentry), bindex, bufsiz);
++
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (unlikely(/* !h_dentry
++ || !h_dentry->d_inode
++ || */
++ !h_dentry->d_inode->i_op
++ || !h_dentry->d_inode->i_op->readlink))
++ return -EINVAL;
++
++ sb = dentry->d_sb;
++ if (!au_test_ro(sb, bindex, dentry->d_inode)) {
++ touch_atime(au_sbr_mnt(sb, bindex), h_dentry);
++ au_update_fuse_h_inode(NULL, h_dentry); /*ignore*/
++ dentry->d_inode->i_atime = h_dentry->d_inode->i_atime;
++ }
++ return h_dentry->d_inode->i_op->readlink(h_dentry, buf, bufsiz);
++}
++
++static int aufs_readlink(struct dentry *dentry, char __user *buf, int bufsiz)
++{
++ int err;
++
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), bufsiz);
++
++ aufs_read_lock(dentry, AuLock_IR);
++ err = h_readlink(dentry, au_dbstart(dentry), buf, bufsiz);
++ aufs_read_unlock(dentry, AuLock_IR);
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
++
++static void *aufs_follow_link(struct dentry *dentry, struct nameidata *nd)
++{
++ int err;
++ char *buf;
++ mm_segment_t old_fs;
++
++ LKTRTrace("%.*s, nd %.*s\n",
++ AuDLNPair(dentry), AuDLNPair(nd->dentry));
++
++ err = -ENOMEM;
++ buf = __getname();
++ if (unlikely(!buf))
++ goto out;
++
++ aufs_read_lock(dentry, AuLock_IR);
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ err = h_readlink(dentry, au_dbstart(dentry), (char __user *)buf,
++ PATH_MAX);
++ set_fs(old_fs);
++ aufs_read_unlock(dentry, AuLock_IR);
++
++ if (err >= 0) {
++ buf[err] = 0;
++ /* will be freed by put_link */
++ nd_set_link(nd, buf);
++ return NULL; /* success */
++ }
++ __putname(buf);
++
++ out:
++ path_release(nd);
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return ERR_PTR(err);
++}
++
++static void aufs_put_link(struct dentry *dentry, struct nameidata *nd,
++ void *cookie)
++{
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ __putname(nd_get_link(nd));
++}
++
++/* ---------------------------------------------------------------------- */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++static void aufs_truncate_range(struct inode *inode, loff_t start, loff_t end)
++{
++ AuUnsupport();
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++struct inode_operations aufs_symlink_iop = {
++ .permission = aufs_permission,
++ .setattr = aufs_setattr,
++#ifdef CONFIG_AUFS_GETATTR
++ .getattr = aufs_getattr,
++#endif
++
++ .readlink = aufs_readlink,
++ .follow_link = aufs_follow_link,
++ .put_link = aufs_put_link
++};
++
++struct inode_operations aufs_dir_iop = {
++ .create = aufs_create,
++ .lookup = aufs_lookup,
++ .link = aufs_link,
++ .unlink = aufs_unlink,
++ .symlink = aufs_symlink,
++ .mkdir = aufs_mkdir,
++ .rmdir = aufs_rmdir,
++ .mknod = aufs_mknod,
++ .rename = aufs_rename,
++
++ .permission = aufs_permission,
++ .setattr = aufs_setattr,
++#ifdef CONFIG_AUFS_GETATTR
++ .getattr = aufs_getattr,
++#endif
++
++#if 0 /* reserved for future use */
++ .setxattr = aufs_setxattr,
++ .getxattr = aufs_getxattr,
++ .listxattr = aufs_listxattr,
++ .removexattr = aufs_removexattr,
++#endif
++
++#if 0 //LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++ .fallocate = aufs_fallocate
++#endif
++};
++
++struct inode_operations aufs_iop = {
++ .permission = aufs_permission,
++ .setattr = aufs_setattr,
++#ifdef CONFIG_AUFS_GETATTR
++ .getattr = aufs_getattr,
++#endif
++
++#if 0 /* reserved for future use */
++ .setxattr = aufs_setxattr,
++ .getxattr = aufs_getxattr,
++ .listxattr = aufs_listxattr,
++ .removexattr = aufs_removexattr,
++#endif
++
++ //void (*truncate) (struct inode *);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++ .truncate_range = aufs_truncate_range,
++#endif
++
++#if 0 //LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++ .fallocate = aufs_fallocate
++#endif
++};
+diff --git a/fs/aufs/i_op_add.c b/fs/aufs/i_op_add.c
+new file mode 100644
+index 0000000..cebc07f
+--- /dev/null
++++ b/fs/aufs/i_op_add.c
+@@ -0,0 +1,757 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode operations (add entry)
++ *
++ * $Id: i_op_add.c,v 1.74 2009/01/26 06:24:01 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/*
++ * final procedure of adding a new entry, except link(2).
++ * remove whiteout, instantiate, copyup the parent dir's times and size
++ * and update version.
++ * if it failed, re-create the removed whiteout.
++ */
++static int epilog(struct inode *dir, aufs_bindex_t bindex,
++ struct dentry *wh_dentry, struct dentry *dentry)
++{
++ int err, rerr;
++ aufs_bindex_t bwh;
++ struct inode *inode, *h_dir;
++ struct dentry *wh;
++ struct au_ndx ndx;
++ struct super_block *sb;
++
++ LKTRTrace("wh %p, %.*s\n", wh_dentry, AuDLNPair(dentry));
++
++ sb = dentry->d_sb;
++ bwh = -1;
++ if (wh_dentry) {
++ h_dir = wh_dentry->d_parent->d_inode; /* dir inode is locked */
++ IMustLock(h_dir);
++ AuDebugOn(au_h_iptr(dir, bindex) != h_dir);
++ bwh = au_dbwh(dentry);
++ err = au_wh_unlink_dentry(au_hi(dir, bindex), wh_dentry, dentry,
++ /*dlgt*/0);
++ if (unlikely(err))
++ goto out;
++ }
++
++ inode = au_new_inode(dentry, /*must_new*/1);
++ if (!IS_ERR(inode)) {
++ d_instantiate(dentry, inode);
++ dir = dentry->d_parent->d_inode; /* dir inode is locked */
++ IMustLock(dir);
++ /* or always cpup dir mtime? */
++ if (au_ibstart(dir) == au_dbstart(dentry))
++ au_cpup_attr_timesizes(dir);
++ dir->i_version++;
++ return 0; /* success */
++ }
++
++ err = PTR_ERR(inode);
++ if (!wh_dentry)
++ goto out;
++
++ /* revert */
++ ndx.flags = 0;
++ if (au_test_dlgt(au_mntflags(sb)))
++ au_fset_ndx(ndx.flags, DLGT);
++ ndx.nfsmnt = au_nfsmnt(sb, bwh);
++ ndx.nd = NULL;
++ /* ndx.br = NULL; */
++ /* dir inode is locked */
++ wh = au_wh_create(dentry, bwh, wh_dentry->d_parent, &ndx);
++ rerr = PTR_ERR(wh);
++ if (IS_ERR(wh)) {
++ AuIOErr("%.*s reverting whiteout failed(%d, %d)\n",
++ AuDLNPair(dentry), err, rerr);
++ err = -EIO;
++ } else
++ dput(wh);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * simple tests for the adding inode operations.
++ * following the checks in vfs, plus the parent-child relationship.
++ */
++int au_may_add(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_parent, int isdir, struct au_ndx *ndx)
++{
++ int err, exist;
++ struct dentry *h_dentry;
++ struct inode *h_inode;
++ umode_t h_mode;
++
++ LKTRTrace("%.*s/%.*s, b%d, dir %d\n",
++ AuDLNPair(h_parent), AuDLNPair(dentry), bindex, isdir);
++
++ exist = !!dentry->d_inode;
++ h_dentry = au_h_dptr(dentry, bindex);
++ h_inode = h_dentry->d_inode;
++ if (!exist) {
++ err = -EEXIST;
++ if (unlikely(h_inode))
++ goto out;
++ } else {
++ /* rename(2) case */
++ err = -EIO;
++ if (unlikely(!h_inode || !h_inode->i_nlink))
++ goto out;
++
++ h_mode = h_inode->i_mode;
++ if (!isdir) {
++ err = -EISDIR;
++ if (unlikely(S_ISDIR(h_mode)))
++ goto out;
++ } else if (unlikely(!S_ISDIR(h_mode))) {
++ err = -ENOTDIR;
++ goto out;
++ }
++ }
++
++ err = -EIO;
++ /* expected parent dir is locked */
++ if (unlikely(h_parent != h_dentry->d_parent))
++ goto out;
++ err = 0;
++
++ if (au_opt_test(au_mntflags(dentry->d_sb), UDBA_INOTIFY)) {
++ struct dentry *h_latest;
++ struct qstr *qstr = &dentry->d_name;
++
++ err = -EACCES;
++ if (unlikely(au_test_h_perm
++ (h_parent->d_inode, MAY_EXEC | MAY_WRITE,
++ au_ftest_ndx(ndx->flags, DLGT))))
++ goto out;
++
++ h_latest = au_sio_lkup_one(qstr->name, h_parent, qstr->len,
++ ndx);
++ err = PTR_ERR(h_latest);
++ if (IS_ERR(h_latest))
++ goto out;
++ err = -EIO;
++ dput(h_latest);
++ /* fuse d_revalidate always return 0 for negative dentries */
++ if (h_latest == h_dentry || au_test_fuse(h_dentry->d_sb))
++ err = 0;
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * initial procedure of adding a new entry.
++ * prepare writable branch and the parent dir, lock it,
++ * lookup whiteout for the new entry.
++ */
++static struct dentry*
++lock_hdir_lkup_wh(struct dentry *dentry, struct au_dtime *dt,
++ struct dentry *src_dentry, struct au_pin *pin,
++ struct au_wr_dir_args *wr_dir_args)
++{
++ struct dentry *wh_dentry, *h_parent;
++ struct super_block *sb;
++ int err;
++ unsigned int mnt_flags;
++ unsigned char pin_flags;
++ aufs_bindex_t bstart, bcpup;
++ struct au_ndx ndx;
++
++ LKTRTrace("%.*s, src %p\n", AuDLNPair(dentry), src_dentry);
++
++ bstart = au_dbstart(dentry);
++ err = au_wr_dir(dentry, src_dentry, wr_dir_args);
++ bcpup = err;
++ wh_dentry = ERR_PTR(err);
++ if (unlikely(err < 0))
++ goto out;
++
++ sb = dentry->d_sb;
++ mnt_flags = au_mntflags(sb);
++ pin_flags = AuPin_DI_LOCKED | AuPin_MNT_WRITE;
++ if (dt && au_opt_test(mnt_flags, UDBA_INOTIFY))
++ au_fset_pin(pin_flags, DO_GPARENT);
++ err = au_pin(pin, dentry, bcpup, pin_flags);
++ wh_dentry = ERR_PTR(err);
++ if (unlikely(err))
++ goto out;
++
++ ndx.nfsmnt = au_nfsmnt(sb, bcpup);
++ ndx.flags = 0;
++ if (au_test_dlgt(mnt_flags))
++ au_fset_ndx(ndx.flags, DLGT);
++ ndx.nd = NULL;
++ /* ndx.br = NULL; */
++ /* ndx.nd_file = NULL; */
++
++ h_parent = au_pinned_h_parent(pin);
++ if (!au_opt_test(mnt_flags, UDBA_NONE) && au_dbstart(dentry) == bcpup) {
++ struct nameidata nd;
++
++ if (ndx.nfsmnt) {
++ /* todo: dirty? */
++ ndx.nd = &nd;
++ ndx.br = au_sbr(sb, bcpup);
++ memset(&nd, 0, sizeof(nd));
++ nd.flags = LOOKUP_CREATE;
++ nd.intent.open.flags = O_EXCL;
++ }
++ err = au_may_add(dentry, bcpup, h_parent,
++ au_ftest_wrdir(wr_dir_args->flags, ISDIR),
++ &ndx);
++ wh_dentry = ERR_PTR(err);
++ if (unlikely(err))
++ goto out_unpin;
++ ndx.nd = NULL;
++ ndx.br = NULL;
++ }
++
++ if (dt)
++ au_dtime_store(dt, au_pinned_parent(pin), h_parent,
++ au_pinned_hdir(pin), au_pinned_hgdir(pin));
++
++ wh_dentry = NULL;
++ if (/* bcpup != bstart || */ bcpup != au_dbwh(dentry))
++ goto out; /* success */
++
++ wh_dentry = au_wh_lkup(h_parent, &dentry->d_name, &ndx);
++
++ out_unpin:
++ if (IS_ERR(wh_dentry))
++ au_unpin(pin);
++ out:
++ AuTraceErrPtr(wh_dentry);
++ return wh_dentry;
++}
++
++/* ---------------------------------------------------------------------- */
++
++enum { Mknod, Symlink, Creat };
++struct simple_arg {
++ int type;
++ union {
++ struct {
++ int mode;
++ struct nameidata *nd;
++ } c;
++ struct {
++ const char *symname;
++ } s;
++ struct {
++ int mode;
++ dev_t dev;
++ } m;
++ } u;
++};
++
++static int add_simple(struct inode *dir, struct dentry *dentry,
++ struct simple_arg *arg)
++{
++ int err;
++ struct dentry *h_dentry, *wh_dentry, *parent;
++ struct inode *h_dir;
++ struct au_dtime dt;
++ struct vfsub_args vargs;
++ struct super_block *sb;
++ aufs_bindex_t bstart;
++ unsigned char created;
++ struct au_hin_ignore ign;
++ struct au_pin pin;
++ struct au_wr_dir_args wr_dir_args = {
++ .force_btgt = -1,
++ .flags = AuWrDir_ADD_ENTRY
++ };
++
++ LKTRTrace("type %d, %.*s\n", arg->type, AuDLNPair(dentry));
++ IMustLock(dir);
++
++ sb = dir->i_sb;
++ parent = dentry->d_parent; /* dir inode is locked */
++ aufs_read_lock(dentry, AuLock_DW);
++ vfsub_args_init(&vargs, &ign, !!au_test_dlgt(au_mntflags(sb)), 0);
++ di_write_lock_parent(parent);
++ wh_dentry = lock_hdir_lkup_wh(dentry, &dt, /*src_dentry*/NULL, &pin,
++ &wr_dir_args);
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out;
++
++ bstart = au_dbstart(dentry);
++ h_dentry = au_h_dptr(dentry, bstart);
++ h_dir = au_pinned_h_dir(&pin);
++ vfsub_ign_hinode(&vargs, IN_CREATE, au_pinned_hdir(&pin));
++
++ switch (arg->type) {
++ case Creat:
++ AuDebugOn(au_test_nfs(h_dir->i_sb) && !arg->u.c.nd);
++ err = au_h_create(h_dir, h_dentry, arg->u.c.mode, &vargs,
++ arg->u.c.nd, au_nfsmnt(sb, bstart));
++ break;
++ case Symlink:
++ err = vfsub_symlink(h_dir, h_dentry, arg->u.s.symname,
++ S_IALLUGO, &vargs);
++ break;
++ case Mknod:
++ err = vfsub_mknod(h_dir, h_dentry, arg->u.m.mode, arg->u.m.dev,
++ &vargs);
++ break;
++ default:
++ BUG();
++ }
++ created = !err;
++ if (!err)
++ err = epilog(dir, bstart, wh_dentry, dentry);
++
++ /* revert */
++ if (unlikely(created && err && h_dentry->d_inode)) {
++ int rerr;
++ vfsub_args_reinit(&vargs);
++ vfsub_ign_hinode(&vargs, IN_DELETE, au_pinned_hdir(&pin));
++ rerr = vfsub_unlink(h_dir, h_dentry, &vargs);
++ if (rerr) {
++ AuIOErr("%.*s revert failure(%d, %d)\n",
++ AuDLNPair(dentry), err, rerr);
++ err = -EIO;
++ }
++ /* todo: inotify will be fired to the grand parent dir? */
++ au_dtime_revert(&dt);
++ d_drop(dentry);
++ }
++
++ au_unpin(&pin);
++ dput(wh_dentry);
++
++ out:
++ if (unlikely(err)) {
++ au_update_dbstart(dentry);
++ d_drop(dentry);
++ }
++ di_write_unlock(parent);
++ aufs_read_unlock(dentry, AuLock_DW);
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
++
++int aufs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev)
++{
++ struct simple_arg arg = {
++ .type = Mknod,
++ .u.m = {
++ .mode = mode,
++ .dev = dev
++ }
++ };
++ return add_simple(dir, dentry, &arg);
++}
++
++int aufs_symlink(struct inode *dir, struct dentry *dentry, const char *symname)
++{
++ struct simple_arg arg = {
++ .type = Symlink,
++ .u.s.symname = symname
++ };
++ return add_simple(dir, dentry, &arg);
++}
++
++int aufs_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *nd)
++{
++ struct simple_arg arg = {
++ .type = Creat,
++ .u.c = {
++ .mode = mode,
++ .nd = nd
++ }
++ };
++ return add_simple(dir, dentry, &arg);
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct au_link_args {
++ unsigned int mnt_flags;
++ unsigned char pin_flags;
++ aufs_bindex_t bdst, bsrc;
++ struct vfsub_args vargs;
++ struct au_pin pin;
++ struct au_hin_ignore ign;
++ struct dentry *h_dentry;
++ struct dentry *src_parent, *parent;
++};
++
++static int au_cpup_before_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry, struct au_link_args *a)
++{
++ int err;
++ struct inode *h_inode;
++ const int hinotify = au_opt_test(a->mnt_flags, UDBA_INOTIFY);
++
++ LKTRTrace("src %.*s, i%lu, dst %.*s\n",
++ AuDLNPair(src_dentry), dir->i_ino, AuDLNPair(dentry));
++
++ di_read_lock_parent(a->src_parent, AuLock_IR);
++ err = au_test_and_cpup_dirs(src_dentry, a->bdst);
++ if (unlikely(err))
++ goto out;
++
++ AuDebugOn(au_dbstart(src_dentry) != a->bsrc);
++ h_inode = au_h_dptr(src_dentry, a->bsrc)->d_inode;
++ a->pin_flags = AuPin_DI_LOCKED | AuPin_MNT_WRITE;
++ if (hinotify)
++ au_fset_pin(a->pin_flags, DO_GPARENT);
++ err = au_pin(&a->pin, src_dentry, a->bdst, a->pin_flags);
++ if (unlikely(err))
++ goto out;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ /* todo: no KEEPLINO because of noplink? */
++ err = au_sio_cpup_simple(src_dentry, a->bdst, -1,
++ AuCpup_DTIME /* | AuCpup_KEEPLINO */);
++ vfsub_i_unlock(h_inode);
++ au_unpin(&a->pin);
++
++ out:
++ di_read_unlock(a->src_parent, AuLock_IR);
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_cpup_or_link(struct dentry *src_dentry, struct au_link_args *a)
++{
++ int err;
++ struct inode *h_inode;
++ aufs_bindex_t bstart;
++ struct dentry *h_src_dentry;
++
++ AuTraceEnter();
++ AuDebugOn(au_dbstart(src_dentry) != a->bsrc);
++
++ bstart = au_ibstart(src_dentry->d_inode);
++ h_inode = NULL;
++ if (bstart <= a->bdst)
++ h_inode = au_h_iptr(src_dentry->d_inode, a->bdst);
++ if (!h_inode || !h_inode->i_nlink) {
++ /* copyup src_dentry as the name of dentry. */
++ au_set_dbstart(src_dentry, a->bdst);
++ au_set_h_dptr(src_dentry, a->bdst, dget(a->h_dentry));
++ h_inode = au_h_dptr(src_dentry, a->bsrc)->d_inode;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ err = au_sio_cpup_single(src_dentry, a->bdst, a->bsrc, -1,
++ AuCpup_KEEPLINO, a->parent);
++ vfsub_i_unlock(h_inode);
++ au_set_h_dptr(src_dentry, a->bdst, NULL);
++ au_set_dbstart(src_dentry, a->bsrc);
++ } else {
++ /* the inode of src_dentry already exists on a.bdst branch */
++ h_src_dentry = d_find_alias(h_inode);
++ if (h_src_dentry) {
++ /* vfsub_args_reinit(&a->vargs); */
++ vfsub_ign_hinode(&a->vargs, IN_CREATE,
++ au_pinned_hdir(&a->pin));
++ err = vfsub_link(h_src_dentry, au_pinned_h_dir(&a->pin),
++ a->h_dentry, &a->vargs);
++ dput(h_src_dentry);
++ } else {
++ AuIOErr("no dentry found for i%lu on b%d\n",
++ h_inode->i_ino, a->bdst);
++ err = -EIO;
++ }
++ }
++
++ if (!err)
++ au_plink_append(src_dentry->d_sb, src_dentry->d_inode,
++ a->h_dentry, a->bdst);
++
++ AuTraceErr(err);
++ return err;
++}
++
++int aufs_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry)
++{
++ int err, rerr;
++ struct au_dtime dt;
++ struct super_block *sb;
++ struct au_link_args *a;
++ struct au_wr_dir_args wr_dir_args = {
++ /* .force_btgt = -1, */
++ .flags = AuWrDir_ADD_ENTRY
++ };
++ struct dentry *wh_dentry, *h_src_dentry;
++ struct inode *inode;
++
++ LKTRTrace("src %.*s, i%lu, dst %.*s\n",
++ AuDLNPair(src_dentry), dir->i_ino, AuDLNPair(dentry));
++ IMustLock(dir);
++ inode = src_dentry->d_inode;
++ IMustLock(inode);
++ AuDebugOn(S_ISDIR(inode->i_mode));
++
++ err = -ENOMEM;
++ a = kzalloc(sizeof(*a), GFP_NOFS);
++ if (unlikely(!a))
++ goto out;
++
++ sb = dentry->d_sb;
++ a->parent = dentry->d_parent; /* dir inode is locked */
++ aufs_read_and_write_lock2(dentry, src_dentry, /*AuLock_FLUSH*/0);
++ a->src_parent = dget_parent(src_dentry);
++ wr_dir_args.force_btgt = au_dbstart(src_dentry);
++ a->mnt_flags = au_mntflags(sb);
++ vfsub_args_init(&a->vargs, &a->ign, au_test_dlgt(a->mnt_flags), 0);
++
++ di_write_lock_parent(a->parent);
++ wr_dir_args.force_btgt = au_wbr(dentry, wr_dir_args.force_btgt);
++ wh_dentry = lock_hdir_lkup_wh(dentry, &dt, src_dentry, &a->pin,
++ &wr_dir_args);
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out_unlock;
++ err = 0;
++
++ a->bdst = au_dbstart(dentry);
++ a->h_dentry = au_h_dptr(dentry, a->bdst);
++
++ /* todo: minor optimize,
++ their sb may be same while their bindex differs? */
++ a->bsrc = au_dbstart(src_dentry);
++ if (au_opt_test(a->mnt_flags, PLINK)) {
++ if (a->bdst < a->bsrc
++ /* && h_src_dentry->d_sb != a->h_dentry->d_sb */)
++ err = au_cpup_or_link(src_dentry, a);
++ else {
++ h_src_dentry = au_h_dptr(src_dentry, a->bdst);
++ AuDebugOn(!h_src_dentry);
++ AuDebugOn(!h_src_dentry->d_inode);
++ vfsub_ign_hinode(&a->vargs, IN_CREATE,
++ au_pinned_hdir(&a->pin));
++ err = vfsub_link(h_src_dentry, au_pinned_h_dir(&a->pin),
++ a->h_dentry, &a->vargs);
++ }
++ } else {
++ /*
++ * copyup src_dentry to the branch we process,
++ * and then link(2) to it.
++ */
++ if (a->bdst < a->bsrc
++ /* && h_src_dentry->d_sb != a->h_dentry->d_sb */) {
++ au_unpin(&a->pin);
++ di_write_unlock(a->parent);
++ err = au_cpup_before_link(src_dentry, dir, dentry, a);
++ if (!err) {
++ a->pin_flags
++ = AuPin_DI_LOCKED | AuPin_MNT_WRITE;
++ if (au_opt_test(a->mnt_flags, UDBA_INOTIFY))
++ au_fset_pin(a->pin_flags, DO_GPARENT);
++ di_write_lock_parent(a->parent);
++ err = au_pin(&a->pin, dentry, a->bdst,
++ a->pin_flags);
++ if (unlikely(err))
++ goto out_wh;
++ }
++ }
++ if (!err) {
++ /* vfsub_args_reinit(&a->vargs); */
++ vfsub_ign_hinode(&a->vargs, IN_CREATE,
++ au_pinned_hdir(&a->pin));
++ h_src_dentry = au_h_dptr(src_dentry, a->bdst);
++ err = vfsub_link(h_src_dentry, au_pinned_h_dir(&a->pin),
++ a->h_dentry, &a->vargs);
++ }
++ }
++ if (unlikely(err))
++ goto out_unpin;
++
++ if (wh_dentry) {
++ err = au_wh_unlink_dentry(au_pinned_hdir(&a->pin), wh_dentry,
++ dentry, /*dlgt*/0);
++ if (unlikely(err))
++ goto out_revert;
++ }
++
++#if 0 /* cannot support it */
++ /* fuse has different memory inode for the same inode number */
++ if (au_test_fuse(a->h_dentry->d_sb)) {
++ LKTRLabel(here);
++ d_drop(a->h_dentry);
++ /*d_drop(h_src_dentry);
++ d_drop(src_dentry);*/
++ a->inode->i_nlink++;
++ a->inode->i_ctime = dir->i_ctime;
++ }
++#endif
++
++ dir->i_version++;
++ if (au_ibstart(dir) == au_dbstart(dentry))
++ au_cpup_attr_timesizes(dir);
++ if (!d_unhashed(a->h_dentry)
++ /* || h_old_inode->i_nlink <= nlink */
++ /* || SB_NFS(h_src_dentry->d_sb) */) {
++ d_instantiate(dentry, au_igrab(inode));
++ inode->i_nlink++;
++ inode->i_ctime = dir->i_ctime;
++ } else
++ /* nfs case (< 2.6.15) */
++ d_drop(dentry);
++ goto out_unpin; /* success */
++
++ out_revert:
++ vfsub_args_reinit(&a->vargs);
++ vfsub_ign_hinode(&a->vargs, IN_DELETE, au_pinned_hdir(&a->pin));
++ rerr = vfsub_unlink(au_pinned_h_dir(&a->pin), a->h_dentry, &a->vargs);
++ if (!rerr)
++ goto out_dt;
++ AuIOErr("%.*s reverting failed(%d, %d)\n",
++ AuDLNPair(dentry), err, rerr);
++ err = -EIO;
++ out_dt:
++ d_drop(dentry);
++ au_dtime_revert(&dt);
++ out_unpin:
++ au_unpin(&a->pin);
++ out_wh:
++ dput(wh_dentry);
++ out_unlock:
++ if (unlikely(err)) {
++ au_update_dbstart(dentry);
++ d_drop(dentry);
++ }
++ di_write_unlock(a->parent);
++ dput(a->src_parent);
++ aufs_read_and_write_unlock2(dentry, src_dentry);
++ kfree(a);
++ out:
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
++
++int aufs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
++{
++ int err, rerr;
++ struct dentry *h_dentry, *wh_dentry, *parent, *opq_dentry;
++ struct inode *h_inode;
++ struct au_dtime dt;
++ aufs_bindex_t bindex;
++ unsigned char diropq, dlgt;
++ unsigned int mnt_flags;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ struct au_pin pin;
++ struct au_wr_dir_args wr_dir_args = {
++ .force_btgt = -1,
++ .flags = AuWrDir_ADD_ENTRY | AuWrDir_ISDIR
++ };
++
++ LKTRTrace("i%lu, %.*s, mode 0%o\n",
++ dir->i_ino, AuDLNPair(dentry), mode);
++ IMustLock(dir);
++
++ aufs_read_lock(dentry, AuLock_DW);
++ parent = dentry->d_parent; /* dir inode is locked */
++ mnt_flags = au_mntflags(dentry->d_sb);
++ dlgt = !!au_test_dlgt(mnt_flags);
++ vfsub_args_init(&vargs, &ign, dlgt, 0);
++
++ di_write_lock_parent(parent);
++ wh_dentry = lock_hdir_lkup_wh(dentry, &dt, /*src_dentry*/NULL, &pin,
++ &wr_dir_args);
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out;
++
++ bindex = au_dbstart(dentry);
++ h_dentry = au_h_dptr(dentry, bindex);
++ vfsub_ign_hinode(&vargs, IN_CREATE, au_pinned_hdir(&pin));
++ err = vfsub_mkdir(au_pinned_h_dir(&pin), h_dentry, mode, &vargs);
++ if (unlikely(err))
++ goto out_unlock;
++
++ /* make the dir opaque */
++ diropq = 0;
++ h_inode = h_dentry->d_inode;
++ if (wh_dentry || au_opt_test(mnt_flags, ALWAYS_DIROPQ)) {
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ opq_dentry = au_diropq_create(dentry, bindex, /*dlgt*/0);
++ vfsub_i_unlock(h_inode);
++ err = PTR_ERR(opq_dentry);
++ if (IS_ERR(opq_dentry))
++ goto out_dir;
++ dput(opq_dentry);
++ diropq = 1;
++ }
++
++ err = epilog(dir, bindex, wh_dentry, dentry);
++ if (!err) {
++ dir->i_nlink++;
++ goto out_unlock; /* success */
++ }
++
++ /* revert */
++ if (diropq) {
++ LKTRLabel(revert opq);
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ rerr = au_diropq_remove(dentry, bindex, dlgt);
++ vfsub_i_unlock(h_inode);
++ if (rerr) {
++ AuIOErr("%.*s reverting diropq failed(%d, %d)\n",
++ AuDLNPair(dentry), err, rerr);
++ err = -EIO;
++ }
++ }
++
++ out_dir:
++ LKTRLabel(revert dir);
++ vfsub_args_reinit(&vargs);
++ vfsub_ign_hinode(&vargs, IN_DELETE, au_pinned_hdir(&pin));
++ rerr = vfsub_rmdir(au_pinned_h_dir(&pin), h_dentry, &vargs);
++ if (rerr) {
++ AuIOErr("%.*s reverting dir failed(%d, %d)\n",
++ AuDLNPair(dentry), err, rerr);
++ err = -EIO;
++ }
++ d_drop(dentry);
++ au_dtime_revert(&dt);
++ out_unlock:
++ au_unpin(&pin);
++ dput(wh_dentry);
++ out:
++ if (unlikely(err)) {
++ au_update_dbstart(dentry);
++ d_drop(dentry);
++ }
++ di_write_unlock(parent);
++ aufs_read_unlock(dentry, AuLock_DW);
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
+diff --git a/fs/aufs/i_op_del.c b/fs/aufs/i_op_del.c
+new file mode 100644
+index 0000000..e2ce684
+--- /dev/null
++++ b/fs/aufs/i_op_del.c
+@@ -0,0 +1,566 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode operations (del entry)
++ *
++ * $Id: i_op_del.c,v 1.71 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/* returns,
++ * 0: wh is unnecessary
++ * plus: wh is necessary
++ * minus: error
++ */
++int au_wr_dir_need_wh(struct dentry *dentry, int isdir, aufs_bindex_t *bcpup)
++{
++ int need_wh, err;
++ aufs_bindex_t bstart;
++ struct dentry *h_dentry;
++ struct super_block *sb;
++
++ LKTRTrace("%.*s, isdir %d, *bcpup %d\n",
++ AuDLNPair(dentry), isdir, *bcpup);
++ sb = dentry->d_sb;
++
++ bstart = au_dbstart(dentry);
++ LKTRTrace("bcpup %d, bstart %d\n", *bcpup, bstart);
++ h_dentry = au_h_dptr(dentry, bstart);
++ if (*bcpup < 0) {
++ *bcpup = bstart;
++ if (au_test_ro(sb, bstart, dentry->d_inode)) {
++ err = AuWbrCopyup(au_sbi(sb), dentry);
++ *bcpup = err;
++ if (unlikely(err < 0))
++ goto out;
++ }
++ } else
++ AuDebugOn(bstart < *bcpup
++ || au_test_ro(sb, *bcpup, dentry->d_inode));
++ LKTRTrace("bcpup %d, bstart %d\n", *bcpup, bstart);
++
++ if (*bcpup != bstart) {
++ err = au_cpup_dirs(dentry, *bcpup);
++ if (unlikely(err))
++ goto out;
++ need_wh = 1;
++ } else {
++ aufs_bindex_t old_bend, new_bend, bdiropq = -1;
++ old_bend = au_dbend(dentry);
++ if (isdir) {
++ bdiropq = au_dbdiropq(dentry);
++ au_set_dbdiropq(dentry, -1);
++ }
++ need_wh = au_lkup_dentry(dentry, bstart + 1, /*type*/0,
++ /*nd*/NULL);
++ err = need_wh;
++ if (isdir)
++ au_set_dbdiropq(dentry, bdiropq);
++ if (unlikely(err < 0))
++ goto out;
++ new_bend = au_dbend(dentry);
++ if (!need_wh && old_bend != new_bend) {
++ au_set_h_dptr(dentry, new_bend, NULL);
++ au_set_dbend(dentry, old_bend);
++#if 0 /* todo: remove this? */
++ } else if (!au_h_dptr(dentry, new_bend)->d_inode) {
++ LKTRTrace("negative\n");
++ au_set_h_dptr(dentry, new_bend, NULL);
++ au_set_dbend(dentry, old_bend);
++ need_wh = 0;
++#endif
++ }
++ }
++ LKTRTrace("need_wh %d\n", need_wh);
++ err = need_wh;
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * simple tests for the removal inode operations.
++ * following the checks in vfs, plus the parent-child relationship.
++ */
++int au_may_del(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_parent, int isdir, struct au_ndx *ndx)
++{
++ int err, exist;
++ struct super_block *sb;
++ struct dentry *h_dentry;
++ struct inode *h_inode;
++ umode_t h_mode;
++
++ LKTRTrace("%.*s/%.*s, b%d, dir %d\n",
++ AuDLNPair(h_parent), AuDLNPair(dentry), bindex, isdir);
++
++ sb = dentry->d_sb;
++ exist = !!dentry->d_inode;
++ h_dentry = au_h_dptr(dentry, bindex);
++ h_inode = h_dentry->d_inode;
++ if (exist) {
++ err = -ENOENT;
++ if (unlikely(!h_inode || !h_inode->i_nlink))
++ goto out;
++
++ h_mode = h_inode->i_mode;
++ if (!isdir) {
++ err = -EISDIR;
++ if (unlikely(S_ISDIR(h_mode)))
++ goto out;
++ } else if (unlikely(!S_ISDIR(h_mode))) {
++ err = -ENOTDIR;
++ goto out;
++ }
++ } else {
++ /* rename(2) case */
++ err = -EIO;
++ if (unlikely(h_inode))
++ goto out;
++ }
++
++ err = -ENOENT;
++ /* expected parent dir is locked */
++ if (unlikely(h_parent != h_dentry->d_parent))
++ goto out;
++ err = 0;
++
++ /*
++ * some filesystem may unlink a dir and corrupt its consistency.
++ * so let's try heavy test.
++ */
++ if (1 /*au_opt_test(au_mntflags(sb), UDBA_INOTIFY)*/) {
++ struct dentry *h_latest;
++ struct qstr *qstr = &dentry->d_name;
++
++ err = -EACCES;
++ if (unlikely(au_test_h_perm(h_parent->d_inode,
++ MAY_EXEC | MAY_WRITE,
++ au_ftest_ndx(ndx->flags, DLGT))))
++ goto out;
++
++ h_latest = au_sio_lkup_one(qstr->name, h_parent, qstr->len,
++ ndx);
++ err = -EIO;
++ if (IS_ERR(h_latest))
++ goto out;
++ dput(h_latest);
++ if (h_latest == h_dentry)
++ err = 0;
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static struct dentry *
++lock_hdir_create_wh(struct dentry *dentry, int isdir, aufs_bindex_t *rbcpup,
++ struct au_dtime *dt, struct au_pin *pin)
++{
++ struct dentry *wh_dentry, *h_parent;
++ struct super_block *sb;
++ int err, need_wh;
++ unsigned int mnt_flags;
++ unsigned char pin_flags;
++ aufs_bindex_t bcpup;
++ struct au_ndx ndx;
++
++ LKTRTrace("%.*s, isdir %d\n", AuDLNPair(dentry), isdir);
++
++ need_wh = au_wr_dir_need_wh(dentry, isdir, rbcpup);
++ err = need_wh;
++ wh_dentry = ERR_PTR(err);
++ if (unlikely(err < 0))
++ goto out;
++
++ sb = dentry->d_sb;
++ mnt_flags = au_mntflags(sb);
++ bcpup = *rbcpup;
++ pin_flags = AuPin_DI_LOCKED | AuPin_MNT_WRITE;
++ if (au_opt_test(mnt_flags, UDBA_INOTIFY))
++ au_fset_pin(pin_flags, DO_GPARENT);
++ err = au_pin(pin, dentry, bcpup, pin_flags);
++ wh_dentry = ERR_PTR(err);
++ if (unlikely(err))
++ goto out;
++ h_parent = au_pinned_h_parent(pin);
++ if (!au_opt_test(mnt_flags, UDBA_NONE) && au_dbstart(dentry) == bcpup) {
++ ndx.nfsmnt = au_nfsmnt(sb, bcpup);
++ ndx.flags = 0;
++ if (au_test_dlgt(mnt_flags))
++ au_fset_ndx(ndx.flags, DLGT);
++ ndx.nd = NULL;
++ /* ndx.br = au_sbr(sb, bcpup); */
++ /* ndx.nd_file = NULL; */
++ err = au_may_del(dentry, bcpup, h_parent, isdir, &ndx);
++ wh_dentry = ERR_PTR(err);
++ if (unlikely(err))
++ goto out_unpin;
++ }
++
++ au_dtime_store(dt, au_pinned_parent(pin), h_parent, au_pinned_hdir(pin),
++ au_pinned_hgdir(pin));
++ wh_dentry = NULL;
++ if (!need_wh)
++ goto out; /* success, no need to create whiteout */
++
++ ndx.nfsmnt = au_nfsmnt(sb, bcpup);
++ ndx.flags = 0;
++ if (au_test_dlgt(mnt_flags))
++ au_fset_ndx(ndx.flags, DLGT);
++ ndx.nd = NULL;
++ /* ndx.br = NULL; */
++ wh_dentry = au_wh_create(dentry, bcpup, h_parent, &ndx);
++ if (!IS_ERR(wh_dentry))
++ goto out; /* success */
++ /* returns with the parent is locked and wh_dentry is DGETed */
++
++ out_unpin:
++ au_unpin(pin);
++ out:
++ AuTraceErrPtr(wh_dentry);
++ return wh_dentry;
++}
++
++static int renwh_and_rmdir(struct dentry *dentry, aufs_bindex_t bindex,
++ struct au_nhash *whlist, struct inode *dir)
++{
++ int rmdir_later, err;
++ struct dentry *h_dentry;
++ struct inode *inode, *h_inode;
++ struct super_block *sb;
++
++ LKTRTrace("%.*s, b%d\n", AuDLNPair(dentry), bindex);
++
++ inode = NULL;
++ h_inode = NULL;
++ sb = dentry->d_sb;
++ if (au_opt_test(au_mntflags(sb), UDBA_INOTIFY)) {
++ inode = dentry->d_inode;
++ h_inode = au_h_iptr(inode, bindex);
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ }
++ h_dentry = au_h_dptr(dentry, bindex);
++ err = au_whtmp_ren(dir, bindex, h_dentry);
++ if (inode) {
++ /* todo: bad approach? */
++ if (!err)
++ au_hin_suspend(au_hi(inode, bindex));
++ vfsub_i_unlock(h_inode);
++ }
++ if (unlikely(err))
++ goto out;
++
++ if (!au_test_nfs(h_dentry->d_sb)) {
++ const int dirwh = au_sbi(sb)->si_dirwh;
++ rmdir_later = (dirwh <= 1);
++ if (!rmdir_later)
++ rmdir_later = au_nhash_test_longer_wh(whlist, bindex,
++ dirwh);
++ if (rmdir_later)
++ return rmdir_later;
++ }
++
++ err = au_whtmp_rmdir(dir, bindex, h_dentry, whlist);
++ if (unlikely(err)) {
++ AuIOErr("rmdir %.*s, b%d failed, %d. ignored\n",
++ AuDLNPair(h_dentry), bindex, err);
++ /* we do not revert the inotify watch */
++ err = 0;
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static void epilog(struct inode *dir, struct dentry *dentry,
++ aufs_bindex_t bindex)
++{
++ /* todo: unnecessary? */
++ d_drop(dentry);
++ dentry->d_inode->i_ctime = dir->i_ctime;
++
++ if (atomic_read(&dentry->d_count) == 1) {
++ au_set_h_dptr(dentry, au_dbstart(dentry), NULL);
++ au_update_dbstart(dentry);
++ }
++ if (au_ibstart(dir) == bindex)
++ au_cpup_attr_timesizes(dir);
++ dir->i_version++;
++}
++
++/* revert flags */
++#define AuRev_DLGT 1
++#define au_ftest_rev(flags, name) ((flags) & AuRev_##name)
++#define au_fset_rev(flags, name) { (flags) |= AuRev_##name; }
++#define au_fclr_rev(flags, name) { (flags) &= ~AuRev_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef AuRev_DLGT
++#define AuRev_DLGT 0
++#endif
++
++static int do_revert(int err, struct inode *dir, aufs_bindex_t bwh,
++ struct dentry *wh_dentry, struct dentry *dentry,
++ struct au_dtime *dt, unsigned int flags)
++{
++ int rerr;
++
++ rerr = au_wh_unlink_dentry(au_hi(dir, bwh), wh_dentry, dentry,
++ au_ftest_rev(flags, DLGT));
++ if (!rerr) {
++ au_set_dbwh(dentry, bwh);
++ au_dtime_revert(dt);
++ return 0;
++ }
++
++ AuIOErr("%.*s reverting whiteout failed(%d, %d)\n",
++ AuDLNPair(dentry), err, rerr);
++ return -EIO;
++}
++
++/* ---------------------------------------------------------------------- */
++
++int aufs_unlink(struct inode *dir, struct dentry *dentry)
++{
++ int err;
++ struct inode *inode, *h_dir;
++ struct dentry *parent, *wh_dentry, *h_dentry;
++ struct au_dtime dt;
++ aufs_bindex_t bwh, bindex, bstart;
++ unsigned char dlgt;
++ struct super_block *sb;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ struct au_pin pin;
++
++ LKTRTrace("i%lu, %.*s\n", dir->i_ino, AuDLNPair(dentry));
++ IMustLock(dir);
++ inode = dentry->d_inode;
++ if (unlikely(!inode))
++ return -ENOENT; /* possible? */
++ IMustLock(inode);
++
++ aufs_read_lock(dentry, AuLock_DW);
++ parent = dentry->d_parent; /* dir inode is locked */
++ di_write_lock_parent(parent);
++
++ bstart = au_dbstart(dentry);
++ bwh = au_dbwh(dentry);
++ bindex = -1;
++ wh_dentry = lock_hdir_create_wh(dentry, /*isdir*/0, &bindex, &dt, &pin);
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out;
++
++ sb = dir->i_sb;
++ dlgt = !!au_test_dlgt(au_mntflags(sb));
++ AuDebugOn(au_dbstart(dentry) != bstart);
++ h_dentry = au_h_dptr(dentry, bstart);
++ dget(h_dentry);
++
++ if (bindex == bstart) {
++ vfsub_args_init(&vargs, &ign, dlgt, 0);
++ vfsub_ign_hinode(&vargs, IN_DELETE, au_pinned_hdir(&pin));
++ h_dir = au_pinned_h_dir(&pin);
++ err = vfsub_unlink(h_dir, h_dentry, &vargs);
++ } else {
++ /* dir inode is locked */
++ AuDebugOn(!wh_dentry
++ || wh_dentry->d_parent != au_h_dptr(parent, bindex));
++ h_dir = wh_dentry->d_parent->d_inode;
++ IMustLock(h_dir);
++ err = 0;
++ }
++
++ if (!err) {
++ inode->i_nlink--;
++#if 0 /* todo: update plink? */
++ if (!inode->i_nlink
++ && au_opt_test(p->a.mnt_flags, PLINK)
++ && au_plink_test(sb, inode)
++ /* && atomic_read(&inode->i_count) == 2) */) {
++ au_debug_on();
++ DbgInode(inode);
++ au_debug_off();
++ }
++#endif
++ /*
++ * although this is not a dir,
++ * set it here since we need to detect the dead inode.
++ */
++ if (!inode->i_nlink)
++ inode->i_flags |= S_DEAD;
++ epilog(dir, dentry, bindex);
++
++ /* update target timestamps */
++ if (bindex == bstart) {
++ au_update_fuse_h_inode(NULL, h_dentry); /*ignore*/
++ inode->i_ctime = h_dentry->d_inode->i_ctime;
++ } else
++ /* todo: this timestamp may be reverted later */
++ inode->i_ctime = h_dir->i_ctime;
++ goto out_unlock; /* success */
++ }
++
++ /* revert */
++ if (wh_dentry) {
++ int rerr;
++ unsigned int rev_flags;
++
++ rev_flags = 0;
++ if (dlgt)
++ au_fset_rev(rev_flags, DLGT);
++ rerr = do_revert(err, dir, bwh, wh_dentry, dentry, &dt,
++ rev_flags);
++ if (rerr)
++ err = rerr;
++ }
++
++ out_unlock:
++ au_unpin(&pin);
++ dput(wh_dentry);
++ dput(h_dentry);
++ out:
++ di_write_unlock(parent);
++ aufs_read_unlock(dentry, AuLock_DW);
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
++
++int aufs_rmdir(struct inode *dir, struct dentry *dentry)
++{
++ int err, rmdir_later;
++ struct inode *inode;
++ struct dentry *parent, *wh_dentry, *h_dentry;
++ struct au_dtime dt;
++ aufs_bindex_t bwh, bindex, bstart;
++ struct au_whtmp_rmdir_args *args;
++ struct au_nhash *whlist;
++ struct super_block *sb;
++ unsigned int mnt_flags;
++ struct au_pin pin;
++
++ LKTRTrace("i%lu, %.*s\n", dir->i_ino, AuDLNPair(dentry));
++ IMustLock(dir);
++ inode = dentry->d_inode;
++ err = -ENOENT; /* possible? */
++ if (unlikely(!inode))
++ goto out;
++ IMustLock(inode);
++
++ whlist = au_nhash_new(GFP_NOFS);
++ err = PTR_ERR(whlist);
++ if (IS_ERR(whlist))
++ goto out;
++
++ err = -ENOMEM;
++ args = kmalloc(sizeof(*args), GFP_NOFS);
++ if (unlikely(!args))
++ goto out_whlist;
++
++ aufs_read_lock(dentry, AuLock_DW);
++ parent = dentry->d_parent; /* dir inode is locked */
++ di_write_lock_parent(parent);
++ err = au_test_empty(dentry, whlist);
++ if (unlikely(err))
++ goto out_args;
++
++ bstart = au_dbstart(dentry);
++ bwh = au_dbwh(dentry);
++ bindex = -1;
++ wh_dentry = lock_hdir_create_wh(dentry, /*isdir*/1, &bindex, &dt, &pin);
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out_args;
++
++ AuDebugOn(au_dbstart(dentry) != bstart);
++ h_dentry = au_h_dptr(dentry, bstart);
++ dget(h_dentry);
++
++ rmdir_later = 0;
++ if (bindex == bstart) {
++ err = renwh_and_rmdir(dentry, bstart, whlist, dir);
++ if (err > 0) {
++ rmdir_later = err;
++ err = 0;
++ }
++ } else {
++ /* dir inode is locked */
++ AuDebugOn(!wh_dentry
++ || wh_dentry->d_parent != au_h_dptr(parent, bindex));
++ IMustLock(wh_dentry->d_parent->d_inode);
++ err = 0;
++ }
++
++ sb = dentry->d_sb;
++ mnt_flags = au_mntflags(sb);
++ if (!err) {
++ if (au_opt_test(mnt_flags, UDBA_INOTIFY) && rmdir_later)
++ au_reset_hinotify(inode, /*flags*/0);
++ inode->i_nlink = 0;
++ inode->i_flags |= S_DEAD;
++ au_set_dbdiropq(dentry, -1);
++ epilog(dir, dentry, bindex);
++
++ if (rmdir_later) {
++ au_whtmp_kick_rmdir(dir, bstart, h_dentry, whlist,
++ args);
++ args = NULL;
++ }
++
++ goto out_unlock; /* success */
++ }
++
++ /* revert */
++ LKTRLabel(revert);
++ if (wh_dentry) {
++ int rerr;
++ unsigned int rev_flags;
++
++ rev_flags = 0;
++ if (au_test_dlgt(mnt_flags))
++ au_fset_rev(rev_flags, DLGT);
++ rerr = do_revert(err, dir, bwh, wh_dentry, dentry, &dt,
++ rev_flags);
++ if (rerr)
++ err = rerr;
++ }
++
++ out_unlock:
++ au_unpin(&pin);
++ dput(wh_dentry);
++ dput(h_dentry);
++ out_args:
++ di_write_unlock(parent);
++ aufs_read_unlock(dentry, AuLock_DW);
++ kfree(args);
++ out_whlist:
++ au_nhash_del(whlist);
++ out:
++ AuTraceErr(err);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
+diff --git a/fs/aufs/i_op_ren.c b/fs/aufs/i_op_ren.c
+new file mode 100644
+index 0000000..89706ca
+--- /dev/null
++++ b/fs/aufs/i_op_ren.c
+@@ -0,0 +1,1261 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode operation (rename entry)
++ * todo: this is crazy monster
++ *
++ * $Id: i_op_ren.c,v 1.82 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++enum { SRC, DST };
++
++#define AuRen_ISDIR 1
++#define AuRen_ISSAMEDIR (1 << 1)
++#define AuRen_WHSRC (1 << 2)
++#define AuRen_WHDST (1 << 3)
++#define AuRen_DLGT (1 << 4)
++#define AuRen_VFSLOCK (1 << 5)
++#define AuRen_PINNED (1 << 6)
++#define AuRen_MNT_WRITE 0 //(1 << 7)
++#define au_ftest_ren(flags, name) ((flags) & AuRen_##name)
++#define au_fset_ren(flags, name) { (flags) |= AuRen_##name; }
++#define au_fclr_ren(flags, name) { (flags) &= ~AuRen_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef AuRen_DLGT
++#define AuRen_DLGT 0
++#endif
++
++struct au_ren_args {
++ /* original args */
++ struct dentry *src_dentry, *dentry;
++ struct inode *src_dir, *dir;
++
++ struct dentry *h_dentry[2], *h_parent[2], *h_trap, *h_locked[2];
++ /* todo: remove them */
++ struct dentry *parent[2], *gparent[2];
++ struct au_pin pin[2];
++ struct au_nhash whlist;
++ aufs_bindex_t btgt, bstart[2];
++ /* do_rename() only */
++ unsigned char need_diropq, bycpup;
++ struct super_block *sb;
++ unsigned int flags;
++ unsigned int mnt_flags;
++ struct au_ndx ndx;
++
++ /* do_rename() only */
++#ifdef CONFIG_AUFS_BR_NFS
++ struct au_hin_ignore ign[3];
++#else
++ struct au_hin_ignore ign[2];
++#endif
++ struct vfsub_args vargs;
++ struct au_whtmp_rmdir_args *thargs;
++ struct dentry *wh_dentry[2], *h_dst, *h_src;
++};
++
++/* ---------------------------------------------------------------------- */
++
++#define RevertFailure(fmt, args...) do { \
++ AuIOErrWhck("revert failure: " fmt " (%d, %d)\n", \
++ ##args, err, rerr); \
++ err = -EIO; \
++ } while (0)
++
++static noinline_for_stack
++void au_ren_rev_diropq(int err, struct au_ren_args *a)
++{
++ int rerr;
++ struct inode *h_inode;
++
++ /* lock inode simply since inotify is not set to h_inode. */
++ h_inode = au_h_dptr(a->src_dentry, a->btgt)->d_inode;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ rerr = au_diropq_remove(a->src_dentry, a->btgt,
++ au_ftest_ren(a->flags, DLGT));
++ vfsub_i_unlock(h_inode);
++ if (rerr)
++ RevertFailure("remove diropq %.*s", AuDLNPair(a->src_dentry));
++}
++
++static noinline_for_stack
++void au_ren_rev_rename(int err, struct au_ren_args *a)
++{
++ int rerr;
++ struct dentry *h_d;
++ struct qstr *name = &a->src_dentry->d_name;
++
++ h_d = au_lkup_one(name->name, a->h_parent[SRC], name->len, &a->ndx);
++ rerr = PTR_ERR(h_d);
++ if (IS_ERR(h_d)) {
++ RevertFailure("au_lkup_one %.*s", AuDLNPair(a->src_dentry));
++ return;
++ }
++
++ AuDebugOn(h_d->d_inode);
++ vfsub_args_reinit(&a->vargs);
++ vfsub_ign_hinode(&a->vargs, IN_MOVED_FROM,
++ au_pinned_hdir(a->pin + DST));
++ vfsub_ign_hinode(&a->vargs, IN_MOVED_TO, au_pinned_hdir(a->pin + SRC));
++ rerr = vfsub_rename(au_pinned_h_dir(a->pin + DST),
++ au_h_dptr(a->src_dentry, a->btgt),
++ au_pinned_h_dir(a->pin + SRC), h_d, &a->vargs);
++ d_drop(h_d);
++ dput(h_d);
++ /* au_set_h_dptr(a->src_dentry, a->btgt, NULL); */
++ if (rerr)
++ RevertFailure("rename %.*s", AuDLNPair(a->src_dentry));
++}
++
++static noinline_for_stack
++void au_ren_rev_cpup(int err, struct au_ren_args *a)
++{
++ int rerr;
++
++ vfsub_args_reinit(&a->vargs);
++ vfsub_ign_hinode(&a->vargs, IN_DELETE, au_pinned_hdir(a->pin + DST));
++ rerr = vfsub_unlink(au_pinned_h_dir(a->pin + DST), a->h_dentry[DST],
++ &a->vargs);
++ au_set_h_dptr(a->src_dentry, a->btgt, NULL);
++ au_set_dbstart(a->src_dentry, a->bstart[SRC]);
++ if (rerr)
++ RevertFailure("unlink %.*s", AuDLNPair(a->h_dentry[DST]));
++}
++
++static noinline_for_stack
++void au_ren_rev_whtmp(int err, struct au_ren_args *a)
++{
++ int rerr;
++ struct dentry *h_d;
++ struct inode *h_inode;
++ struct qstr *name = &a->dentry->d_name;
++
++ h_d = au_lkup_one(name->name, a->h_parent[DST], name->len, &a->ndx);
++ rerr = PTR_ERR(h_d);
++ if (IS_ERR(h_d)) {
++ RevertFailure("lookup %.*s", AuLNPair(name));
++ return;
++ }
++ if (h_d->d_inode) {
++ d_drop(h_d);
++ dput(h_d);
++ return;
++ }
++
++ h_inode = a->h_dst->d_inode;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ au_hin_resume(au_hi(a->src_dentry->d_inode, a->btgt));
++ vfsub_i_unlock(h_inode);
++ vfsub_args_reinit(&a->vargs);
++ vfsub_ign_hinode(&a->vargs, IN_MOVED_TO | IN_MOVED_FROM,
++ au_pinned_hdir(a->pin + DST));
++ rerr = vfsub_rename(au_pinned_h_dir(a->pin + DST), a->h_dst,
++ au_pinned_h_dir(a->pin + DST), h_d, &a->vargs);
++ d_drop(h_d);
++ dput(h_d);
++ if (!rerr) {
++ au_set_h_dptr(a->dentry, a->btgt, NULL);
++ au_set_h_dptr(a->dentry, a->btgt, dget(a->h_dst));
++ } else
++ RevertFailure("rename %.*s", AuDLNPair(a->h_dst));
++}
++
++static noinline_for_stack
++void au_ren_rev_whsrc(int err, struct au_ren_args *a)
++{
++ int rerr;
++
++ rerr = au_wh_unlink_dentry(au_pinned_hdir(a->pin + SRC),
++ a->wh_dentry[SRC], a->src_dentry, /*dlgt*/0);
++ if (rerr)
++ RevertFailure("unlink %.*s", AuDLNPair(a->wh_dentry[SRC]));
++}
++#undef RevertFailure
++
++/* ---------------------------------------------------------------------- */
++
++static /* noinline_for_stack */
++int au_ren_or_cpup(struct au_ren_args *a)
++{
++ int err;
++
++ AuTraceEnter();
++
++ if (au_dbstart(a->src_dentry) == a->btgt) {
++ if (a->need_diropq && au_dbdiropq(a->src_dentry) == a->btgt)
++ a->need_diropq = 0;
++ vfsub_ign_hinode(&a->vargs, IN_MOVED_FROM,
++ au_pinned_hdir(a->pin + SRC));
++ vfsub_ign_hinode(&a->vargs, IN_MOVED_TO,
++ au_pinned_hdir(a->pin + DST));
++ /* nfs_rename() calls d_delete() */
++ if (au_test_nfs(au_pinned_h_dir(a->pin + DST)->i_sb)
++ && a->h_dentry[DST]->d_inode
++ && (S_ISDIR(a->h_dentry[DST]->d_inode->i_mode)
++ || atomic_read(&a->h_dentry[DST]->d_count) <= 2))
++ vfsub_ign_hinode(&a->vargs, IN_DELETE,
++ au_pinned_hdir(a->pin + DST));
++ AuDebugOn(au_dbstart(a->src_dentry) != a->btgt);
++ err = vfsub_rename(au_pinned_h_dir(a->pin + SRC),
++ au_h_dptr(a->src_dentry, a->btgt),
++ au_pinned_h_dir(a->pin + DST),
++ a->h_dentry[DST], &a->vargs);
++ } else {
++ struct inode *h_inode = a->h_dentry[SRC]->d_inode;
++
++ a->bycpup = 1;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ au_set_dbstart(a->src_dentry, a->btgt);
++ au_set_h_dptr(a->src_dentry, a->btgt, dget(a->h_dentry[DST]));
++ err = au_sio_cpup_single(a->src_dentry, a->btgt, a->bstart[SRC],
++ -1, !AuCpup_DTIME, a->parent[DST]);
++ if (unlikely(err)) {
++ au_set_h_dptr(a->src_dentry, a->btgt, NULL);
++ au_set_dbstart(a->src_dentry, a->bstart[SRC]);
++ }
++ vfsub_i_unlock(h_inode);
++ }
++
++ return err;
++}
++
++static /* noinline_for_stack */
++int au_ren_del_whtmp(struct au_ren_args *a)
++{
++ int err;
++
++ AuTraceEnter();
++
++ if (au_test_nfs(a->h_dst->d_sb)
++ || !au_nhash_test_longer_wh(&a->whlist, a->btgt,
++ au_sbi(a->sb)->si_dirwh)) {
++ err = au_whtmp_rmdir(a->dir, a->btgt, a->h_dst, &a->whlist);
++ if (unlikely(err))
++ AuWarn("failed removing whtmp dir %.*s (%d), "
++ "ignored.\n", AuDLNPair(a->h_dst), err);
++ } else {
++ au_whtmp_kick_rmdir(a->dir, a->btgt, a->h_dst, &a->whlist,
++ a->thargs);
++ dput(a->h_dst);
++ a->thargs = NULL;
++ }
++
++ return 0;
++}
++
++static /* noinline_for_stack */
++int au_ren_diropq(struct au_ren_args *a)
++{
++ int err;
++ struct dentry *diropq;
++ struct inode *h_inode;
++
++ AuTraceEnter();
++
++ err = 0;
++ h_inode = au_h_dptr(a->src_dentry, a->btgt)->d_inode;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ diropq = au_diropq_create(a->src_dentry, a->btgt,
++ au_ftest_ren(a->flags, DLGT));
++ vfsub_i_unlock(h_inode);
++ if (IS_ERR(diropq))
++ err = PTR_ERR(diropq);
++ dput(diropq);
++
++ return err;
++}
++
++static /* noinline_for_stack */
++int do_rename(struct au_ren_args *a)
++{
++ int err;
++ aufs_bindex_t bindex, bend;
++ struct dentry *h_d;
++
++ LKTRTrace("%.*s/%.*s, %.*s/%.*s, "
++ "hd{%p, %p}, hp{%p, %p}, wh %p, btgt %d, bstart{%d, %d}, "
++ "flags 0x%x\n",
++ AuDLNPair(a->parent[SRC]), AuDLNPair(a->src_dentry),
++ AuDLNPair(a->parent[DST]), AuDLNPair(a->dentry),
++ a->h_dentry[SRC], a->h_dentry[DST],
++ a->h_parent[SRC], a->h_parent[DST],
++ &a->whlist, a->btgt,
++ a->bstart[SRC], a->bstart[DST],
++ a->flags);
++
++ /* prepare workqueue args */
++ if (au_ftest_ren(a->flags, ISDIR) && a->h_dentry[DST]->d_inode) {
++ err = -ENOMEM;
++ a->thargs = kmalloc(sizeof(*a->thargs), GFP_NOFS);
++ if (unlikely(!a->thargs))
++ goto out;
++ a->h_dst = dget(a->h_dentry[DST]);
++ }
++
++ a->ndx.nfsmnt = au_nfsmnt(a->sb, a->btgt);
++ if (au_ftest_ren(a->flags, DLGT))
++ au_fset_ndx(a->ndx.flags, DLGT);
++
++ /* create whiteout for src_dentry */
++ if (au_ftest_ren(a->flags, WHSRC)) {
++ a->wh_dentry[SRC] = au_wh_create(a->src_dentry, a->btgt,
++ a->h_parent[SRC], &a->ndx);
++ err = PTR_ERR(a->wh_dentry[SRC]);
++ if (IS_ERR(a->wh_dentry[SRC]))
++ goto out_thargs;
++ }
++
++ /* lookup whiteout for dentry */
++ if (au_ftest_ren(a->flags, WHDST)) {
++ h_d = au_wh_lkup(a->h_parent[DST], &a->dentry->d_name, &a->ndx);
++ err = PTR_ERR(h_d);
++ if (IS_ERR(h_d))
++ goto out_whsrc;
++ if (!h_d->d_inode)
++ dput(h_d);
++ else
++ a->wh_dentry[DST] = h_d;
++ }
++
++ /* rename dentry to tmpwh */
++ if (a->thargs) {
++ struct au_hinode *hinode;
++
++ AuDbgDentry(a->h_dentry[DST]);
++ err = au_whtmp_ren(a->dir, a->btgt, a->h_dentry[DST]);
++ if (unlikely(err))
++ goto out_whdst;
++ AuDbgDentry(a->h_dentry[DST]);
++ hinode = au_hi(a->dentry->d_inode, a->btgt);
++ /* todo: bad approach? */
++ vfsub_i_lock_nested(hinode->hi_inode, AuLsc_I_CHILD);
++ au_hin_suspend(hinode);
++ vfsub_i_unlock(hinode->hi_inode);
++ au_set_h_dptr(a->dentry, a->btgt, NULL);
++ AuDbgDentry(a->h_dentry[DST]);
++ err = au_lkup_neg(a->dentry, a->btgt);
++ if (unlikely(err))
++ goto out_whtmp;
++ a->h_dentry[DST] = au_h_dptr(a->dentry, a->btgt);
++ }
++
++ /* cpup src */
++ if (a->h_dentry[DST]->d_inode && a->bstart[SRC] != a->btgt) {
++ struct inode *h_inode = a->h_dentry[SRC]->d_inode;
++
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ err = au_sio_cpup_simple(a->src_dentry, a->btgt, -1,
++ !AuCpup_DTIME);
++ vfsub_i_unlock(h_inode);
++ if (unlikely(err))
++ goto out_whtmp;
++ }
++
++ /* rename by vfs_rename or cpup */
++ a->need_diropq = au_ftest_ren(a->flags, ISDIR)
++ && (a->wh_dentry[DST]
++ || au_dbdiropq(a->dentry) == a->btgt
++ /* hide the lower to keep xino */
++ || a->btgt < au_dbend(a->dentry)
++ || au_opt_test(a->mnt_flags, ALWAYS_DIROPQ));
++ a->bycpup = 0;
++ vfsub_args_init(&a->vargs, a->ign, au_ftest_ren(a->flags, DLGT), 0);
++ err = au_ren_or_cpup(a);
++ if (unlikely(err))
++ goto out_whtmp;
++
++ /* make dir opaque */
++ if (a->need_diropq) {
++ err = au_ren_diropq(a);
++ if (unlikely(err))
++ goto out_rename;
++ }
++
++ /* update target timestamps */
++ AuDebugOn(au_dbstart(a->src_dentry) != a->btgt);
++ a->h_src = au_h_dptr(a->src_dentry, a->btgt);
++ au_update_fuse_h_inode(NULL, a->h_src); /*ignore*/
++ /* src_dentry->d_inode->i_atime = h_src->d_inode->i_atime; */
++ a->src_dentry->d_inode->i_ctime = a->h_src->d_inode->i_ctime;
++
++ /* remove whiteout for dentry */
++ if (a->wh_dentry[DST]) {
++ err = au_wh_unlink_dentry(au_pinned_hdir(a->pin + DST),
++ a->wh_dentry[DST], a->dentry,
++ /*dlgt*/0);
++ if (unlikely(err))
++ goto out_diropq;
++ }
++
++ /* remove whtmp */
++ if (a->thargs)
++ /* ignore this error */
++ au_ren_del_whtmp(a);
++
++ err = 0;
++ goto out_success;
++
++ out_diropq:
++ if (a->need_diropq)
++ au_ren_rev_diropq(err, a);
++ out_rename:
++ if (!a->bycpup)
++ au_ren_rev_rename(err, a);
++ else
++ au_ren_rev_cpup(err, a);
++ out_whtmp:
++ if (a->thargs)
++ au_ren_rev_whtmp(err, a);
++ out_whdst:
++ dput(a->wh_dentry[DST]);
++ a->wh_dentry[DST] = NULL;
++ out_whsrc:
++ if (a->wh_dentry[SRC])
++ au_ren_rev_whsrc(err, a);
++ d_drop(a->src_dentry);
++ bend = au_dbend(a->src_dentry);
++ for (bindex = au_dbstart(a->src_dentry); bindex <= bend; bindex++) {
++ h_d = au_h_dptr(a->src_dentry, bindex);
++ if (h_d)
++ d_drop(h_d);
++ }
++ d_drop(a->dentry);
++ bend = au_dbend(a->dentry);
++ for (bindex = au_dbstart(a->dentry); bindex <= bend; bindex++) {
++ h_d = au_h_dptr(a->dentry, bindex);
++ if (h_d)
++ d_drop(h_d);
++ }
++ au_update_dbstart(a->dentry);
++ if (a->thargs)
++ d_drop(a->h_dst);
++ out_success:
++ dput(a->wh_dentry[SRC]);
++ dput(a->wh_dentry[DST]);
++ out_thargs:
++ if (a->thargs) {
++ dput(a->h_dst);
++ kfree(a->thargs);
++ }
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * test if @dentry dir can be rename destination or not.
++ * success means, it is a logically empty dir.
++ */
++static int may_rename_dstdir(struct dentry *dentry, aufs_bindex_t btgt,
++ struct au_nhash *whlist)
++{
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ return au_test_empty(dentry, whlist);
++}
++
++/*
++ * test if @dentry dir can be rename source or not.
++ * if it can, return 0 and @children is filled.
++ * success means,
++ * - or, it is a logically empty dir.
++ * - or, it exists on writable branch and has no children including whiteouts
++ * on the lower branch.
++ */
++static int may_rename_srcdir(struct dentry *dentry, aufs_bindex_t btgt)
++{
++ int err;
++ aufs_bindex_t bstart;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ bstart = au_dbstart(dentry);
++ if (bstart != btgt) {
++ struct au_nhash *whlist;
++
++ whlist = au_nhash_new(GFP_NOFS);
++ err = PTR_ERR(whlist);
++ if (IS_ERR(whlist))
++ goto out;
++ err = au_test_empty(dentry, whlist);
++ au_nhash_del(whlist);
++ goto out;
++ }
++
++ if (bstart == au_dbtaildir(dentry))
++ return 0; /* success */
++
++ err = au_test_empty_lower(dentry);
++
++ out:
++ if (/* unlikely */(err == -ENOTEMPTY)) {
++ AuWarn1("renaming dir who has child(ren) on multiple branches,"
++ " is not supported\n");
++ err = -EXDEV;
++ }
++ AuTraceErr(err);
++ return err;
++}
++
++/* mainly for link(2) and rename(2) */
++int au_wbr(struct dentry *dentry, aufs_bindex_t btgt)
++{
++ aufs_bindex_t bdiropq, bwh;
++ struct dentry *parent;
++
++ LKTRTrace("%.*s, b%d\n", AuDLNPair(dentry), btgt);
++ parent = dentry->d_parent;
++ IMustLock(parent->d_inode); /* dir is locked */
++
++ bdiropq = au_dbdiropq(parent);
++ bwh = au_dbwh(dentry);
++ if (au_br_rdonly(au_sbr(dentry->d_sb, btgt))
++ || (0 <= bdiropq && bdiropq < btgt)
++ || (0 <= bwh && bwh < btgt))
++ btgt = -1;
++
++ LKTRTrace("btgt %d\n", btgt);
++ return btgt;
++}
++
++/*
++ * simple tests for rename.
++ * following the checks in vfs, plus the parent-child relationship.
++ */
++static int au_may_ren(struct au_ren_args *a)
++{
++ int err;
++ struct inode *h_inode;
++
++ AuTraceEnter();
++
++ if (a->bstart[SRC] == a->btgt) {
++ err = au_may_del(a->src_dentry, a->btgt, a->h_parent[SRC],
++ au_ftest_ren(a->flags, ISDIR), &a->ndx);
++ if (unlikely(err))
++ goto out;
++ err = -EINVAL;
++ if (unlikely(a->h_dentry[SRC] == a->h_trap))
++ goto out;
++ }
++
++ err = 0;
++ if (a->bstart[DST] != a->btgt)
++ goto out;
++
++ err = -EIO;
++ h_inode = a->h_dentry[DST]->d_inode;
++ if (!a->dentry->d_inode) {
++ if (unlikely(h_inode))
++ goto out;
++ err = au_may_add(a->dentry, a->btgt, a->h_parent[DST],
++ au_ftest_ren(a->flags, ISDIR), &a->ndx);
++ } else {
++ if (unlikely(!h_inode || !h_inode->i_nlink))
++ goto out;
++ err = au_may_del(a->dentry, a->btgt, a->h_parent[DST],
++ au_ftest_ren(a->flags, ISDIR), &a->ndx);
++ if (unlikely(err))
++ goto out;
++ err = -ENOTEMPTY;
++ if (unlikely(a->h_dentry[DST] == a->h_trap))
++ goto out;
++ err = 0;
++ }
++
++ out:
++ if (unlikely(err == -ENOENT || err == -EEXIST))
++ err = -EIO;
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * locking order
++ * (VFS)
++ * - src_dir and dir by lock_rename()
++ * - inode if exitsts
++ * (aufs)
++ * - lock all
++ * + src_dentry and dentry by aufs_read_and_write_lock2() which calls,
++ * + si_read_lock
++ * + di_write_lock2_child()
++ * + di_write_lock_child()
++ * + ii_write_lock_child()
++ * + di_write_lock_child2()
++ * + ii_write_lock_child2()
++ * + src_parent and parent
++ * + di_write_lock_parent()
++ * + ii_write_lock_parent()
++ * + di_write_lock_parent2()
++ * + ii_write_lock_parent2()
++ * + if udab=inotify is specified, lock grand parents (crazy)
++ * + di_read_lock_gparent()
++ * + ii_read_lock_gparent()
++ * + di_read_lock_gparent2()
++ * + ii_read_lock_gparent2()
++ * + mutex_lock(s_vfs_rename_mutex)
++ * + mutex_lock_gparent()
++ * + mutex_lock_gparent2()
++ * + mutex_lock_parent()
++ * + mutex_lock_parent2()
++ * + else lower src_dir and dir by vfsub_lock_rename()
++ * + verify the every relations between child, parent and grand parent. if any
++ * of them failed, unlock all and return -EBUSY.
++ */
++static void au_ren_pin_init(struct au_pin *first, struct dentry *d1,
++ struct au_pin *next, struct dentry *d2,
++ aufs_bindex_t bindex)
++{
++ AuTraceEnter();
++
++ /* AuLsc_DI_PARENT3 is for higher gparent initially */
++ au_pin_init(first, d1, bindex, AuLsc_DI_PARENT2, AuLsc_I_PARENT2,
++ AuPin_DI_LOCKED | AuPin_DO_GPARENT);
++ /* AuLsc_DI_PARENT4 is for lower gparent initially */
++ au_pin_init(next, d2, bindex, AuLsc_DI_PARENT3, AuLsc_I_PARENT4,
++ AuPin_DI_LOCKED | AuPin_DO_GPARENT);
++}
++
++static void au_ren_fake_pin(struct au_ren_args *a)
++{
++ int i;
++ struct au_pin1 *p;
++ struct inode *h_i;
++
++ AuTraceEnter();
++
++ /* they increment the ref counter */
++ for (i = 0; i < 2; i++) {
++ p = a->pin[i].pin + AuPin_PARENT;
++ au_pin_set_parent(a->pin + i, a->parent[i]);
++ dput(a->parent[i]);
++ h_i = a->h_parent[i]->d_inode;
++ au_pin_set_h_dir(a->pin + i, h_i);
++ iput(h_i);
++
++ if (!a->gparent[i]) {
++ au_pin_set_gparent(a->pin + i, NULL);
++ au_pin_set_h_gdir(a->pin + i, NULL);
++ } else {
++ au_pin_set_gparent(a->pin + i, a->gparent[i]);
++ dput(a->gparent[i]);
++ h_i = au_h_iptr(a->gparent[i]->d_inode, a->btgt);
++ au_pin_set_h_gdir(a->pin + i, h_i);
++ iput(h_i);
++ }
++ }
++}
++
++/* crazy */
++/* cf. i_op.c: au_do_pin() */
++static int au_ren_pin4(int higher, int lower, struct au_ren_args *a)
++{
++ int err, i, lsc;
++ struct au_pin *p;
++ struct au_pin1 *p4[4];
++ struct inode *h_dir;
++
++#if 0
++ lktr_set_pid(current->pid, LktrArrayPid);
++ LKTRTrace("i%lu, %.*s, i%lu, %.*s\n",
++ a->src_dir->i_ino, AuDLNPair(a->src_dentry),
++ a->dir->i_ino, AuDLNPair(a->dentry));
++ lktr_clear_pid(current->pid, LktrArrayPid);
++#endif
++ LKTRTrace("%d, %d\n", higher, lower);
++
++ err = 0;
++ p = a->pin + higher;
++ p4[0] = au_pin_gp(p); /* highest */
++ p4[1] = p->pin + AuPin_PARENT;
++ p = a->pin + lower;
++ p4[2] = au_pin_gp(p);
++ p4[3] = p->pin + AuPin_PARENT;
++
++ if (a->gparent[higher]) {
++ au_pin_do_set_parent(p4[0], a->gparent[higher]);
++ au_pin_do_set_dentry(p4[0], a->parent[higher]);
++ }
++ au_pin_do_set_parent(p4[1], a->parent[higher]);
++ if (a->gparent[lower]) {
++ au_pin_do_set_parent(p4[2], a->gparent[lower]);
++ au_pin_do_set_dentry(p4[2], a->parent[lower]);
++ }
++ au_pin_do_set_parent(p4[3], a->parent[lower]);
++
++#if 0
++ lktr_set_pid(current->pid, LktrArrayPid);
++ for (i = 0; i < 4; i++)
++ AuDbgDentry(p4[i]->parent);
++#endif
++ DiMustWriteLock(p4[3]->parent);
++ di_write_unlock(p4[1]->parent);
++ if (p4[2]->parent)
++ di_read_lock_parent2(p4[2]->parent, AuLock_IR);
++ di_write_lock_parent3(p4[1]->parent);
++ if (p4[0]->parent)
++ di_read_lock_parent4(p4[0]->parent, AuLock_IR);
++ //lktr_clear_pid(current->pid, LktrArrayPid);
++
++ vfsub_lock_rename_mutex(au_sbr_sb(a->dentry->d_sb, a->btgt));
++ au_fset_ren(a->flags, VFSLOCK);
++
++ lsc = AuLsc_I_PARENT;
++ for (i = 0; i < 4; i++, lsc++) {
++ if (p4[i]->parent) {
++ h_dir = au_h_iptr(p4[i]->parent->d_inode, a->btgt);
++ au_pin_do_set_h_dir(p4[i], h_dir);
++ vfsub_i_lock_nested(p4[i]->h_dir, lsc);
++ }
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static struct dentry *au_ren_pin3(int higher, int lower, struct au_ren_args *a)
++{
++ struct dentry *h_trap;
++ struct au_pin *p;
++ int err;
++
++ LKTRTrace("%d, %d\n", higher, lower);
++
++ p = a->pin + higher;
++ AuDebugOn(!au_pin_gp(p));
++ au_fset_pin(au_pin_gp(p)->flags, VFS_RENAME);
++ err = au_do_pin(p->pin + AuPin_PARENT, au_pin_gp(p));
++ h_trap = ERR_PTR(err);
++ if (unlikely(err))
++ goto out;
++ p = a->pin + lower;
++ au_fclr_pin(p->pin[AuPin_PARENT].flags, DO_GPARENT);
++ err = au_do_pin(p->pin + AuPin_PARENT, NULL);
++ h_trap = ERR_PTR(err);
++ if (unlikely(err)) {
++ p = a->pin + higher;
++ au_do_unpin(p->pin + AuPin_PARENT, au_pin_gp(p));
++ goto out;
++ }
++ h_trap = au_pinned_h_parent(p);
++
++ out:
++ AuTraceErrPtr(h_trap);
++ return h_trap;
++}
++
++static struct dentry *au_ren_pin(struct au_ren_args *a)
++{
++ struct dentry *h_trap;
++ struct inode *h_gdir;
++ int err, i, same_gp;
++
++ //lktr_set_pid(current->pid, LktrArrayPid);
++ AuTraceEnter();
++ AuDebugOn(!au_opt_test(a->mnt_flags, UDBA_INOTIFY));
++
++ /* gdir is not locked */
++ same_gp = 0;
++ if (!IS_ROOT(a->parent[SRC]))
++ a->gparent[SRC] = dget_parent(a->parent[SRC]);
++ if (!IS_ROOT(a->parent[DST])) {
++ a->gparent[DST] = dget_parent(a->parent[DST]);
++ same_gp = (a->gparent[SRC] == a->gparent[DST]);
++ }
++
++ /*
++ * patterns
++ * - gparent[SRC] is parent[DST]
++ * - parent[SRC] is gparent[DST]
++ * - gparent[SRC] is gparent[DST]
++ * - gparent[SRC] is a descendant of parent[DST]
++ * - parent[SRC] is an ancestor of gparent[DST]
++ * - not within grand parent range
++ */
++ err = 0;
++ h_trap = ERR_PTR(-EBUSY);
++ if (a->gparent[SRC] == a->parent[DST]) {
++ //AuDbg("here\n");
++ LKTRLabel(here);
++ au_ren_pin_init(a->pin + DST, a->dentry, a->pin + SRC,
++ a->src_dentry, a->btgt);
++ h_trap = au_ren_pin3(DST, SRC, a);
++ if (!IS_ERR(h_trap)) {
++ h_gdir = au_pinned_h_dir(a->pin + DST);
++ err = au_verify_parent(a->h_parent[SRC], h_gdir);
++ if (unlikely(err))
++ h_trap = ERR_PTR(-EBUSY);
++ }
++ } else if (a->parent[SRC] == a->gparent[DST] || same_gp) {
++ //AuDbg("here\n");
++ LKTRLabel(here);
++ au_ren_pin_init(a->pin + SRC, a->src_dentry, a->pin + DST,
++ a->dentry, a->btgt);
++ h_trap = au_ren_pin3(SRC, DST, a);
++ if (!IS_ERR(h_trap)) {
++ if (!same_gp)
++ h_gdir = au_pinned_h_dir(a->pin + SRC);
++ else
++ h_gdir = au_pinned_h_gdir(a->pin + SRC);
++ err = au_verify_parent(a->h_parent[DST], h_gdir);
++ if (unlikely(err))
++ h_trap = ERR_PTR(-EBUSY);
++ }
++ } else if (a->gparent[SRC]
++ && (h_trap = au_test_subdir(a->gparent[SRC],
++ a->parent[DST]))) {
++ //AuDbg("here\n");
++ LKTRLabel(here);
++ au_ren_pin_init(a->pin + DST, a->dentry, a->pin + SRC,
++ a->src_dentry, a->btgt);
++ if (a->gparent[DST]) {
++ err = au_ren_pin4(DST, SRC, a);
++ if (unlikely(err))
++ h_trap = ERR_PTR(err);
++ } else {
++ struct dentry *t;
++ t = au_ren_pin3(DST, SRC, a);
++ AuDebugOn(t == h_trap);
++ }
++#if 1
++ } else if (a->gparent[DST]
++ && (h_trap = au_test_subdir(a->gparent[DST],
++ a->parent[SRC]))) {
++ /* todo: is this really necessary? */
++ //AuDbg("here\n");
++ LKTRLabel(here);
++ au_ren_pin_init(a->pin + SRC, a->src_dentry, a->pin + DST,
++ a->dentry, a->btgt);
++ if (a->gparent[SRC]) {
++ err = au_ren_pin4(SRC, DST, a);
++ if (unlikely(err))
++ h_trap = ERR_PTR(err);
++ } else {
++ struct dentry *t;
++ t = au_ren_pin3(SRC, DST, a);
++ AuDebugOn(t == h_trap);
++ }
++#endif
++ } else /* if (a->gparent[DST]
++ && (h_trap = au_test_subdir(a->gparent[DST],
++ a->parent[SRC]))) */ {
++ //AuDbg("here\n");
++ LKTRLabel(here);
++ h_trap = NULL;
++ if (a->gparent[DST])
++ h_trap = au_test_subdir(a->gparent[DST],
++ a->parent[SRC]);
++ au_ren_pin_init(a->pin + SRC, a->src_dentry, a->pin + DST,
++ a->dentry, a->btgt);
++ err = au_ren_pin4(SRC, DST, a);
++ if (unlikely(err))
++ h_trap = ERR_PTR(err);
++ }
++ au_fset_ren(a->flags, PINNED);
++
++ if (!IS_ERR(h_trap)) {
++ err = 0;
++ for (i = 0; !err && i < 2; i++) {
++ h_gdir = au_pinned_h_gdir(a->pin + i);
++ if (h_gdir)
++ err = au_verify_parent(a->h_parent[i], h_gdir);
++ }
++ if (unlikely(err)) {
++ h_trap = ERR_PTR(err);
++ //AuDbg("here\n");
++ }
++ }
++
++ dput(a->gparent[SRC]);
++ dput(a->gparent[DST]);
++ memset(a->gparent, 0, sizeof(a->gparent));
++ AuTraceErrPtr(h_trap);
++ //lktr_clear_pid(current->pid, LktrArrayPid);
++ return h_trap;
++}
++
++static void au_ren_unlock(struct au_ren_args *a)
++{
++ int i;
++
++ AuTraceEnter();
++
++ if (au_ftest_ren(a->flags, MNT_WRITE))
++ au_mnt_drop_write(au_sbr_mnt(a->dentry->d_sb, a->btgt));
++ if (a->h_locked[0])
++ vfsub_unlock_rename(a->h_locked[0], a->h_locked[1]);
++ if (au_ftest_ren(a->flags, PINNED)) {
++ au_unpin(a->pin + SRC);
++ au_unpin(a->pin + DST);
++ memset(a->gparent, 0, sizeof(a->gparent));
++ }
++ if (au_ftest_ren(a->flags, VFSLOCK))
++ vfsub_unlock_rename_mutex(au_sbr_sb(a->dentry->d_sb, a->btgt));
++ for (i = 0; i < 2; i++)
++ if (a->gparent[i]) {
++ di_read_unlock(a->gparent[i], AuLock_IR);
++ dput(a->gparent[i]);
++ }
++}
++
++static int au_ren_lock(struct au_ren_args *a)
++{
++ int err;
++ const int hinotify = au_opt_test(a->mnt_flags, UDBA_INOTIFY);
++
++ AuTraceEnter();
++
++ err = 0;
++ if (!hinotify
++ || (au_ftest_ren(a->flags, ISSAMEDIR) && IS_ROOT(a->parent[SRC]))) {
++ au_ren_pin_init(a->pin + SRC, a->src_dentry, a->pin + DST,
++ a->dentry, a->btgt);
++ LKTRLabel(here);
++ a->h_locked[0] = a->h_parent[SRC];
++ a->h_locked[1] = a->h_parent[DST];
++ a->h_trap = vfsub_lock_rename(a->h_locked[0], a->h_locked[1]);
++ au_ren_fake_pin(a);
++ } else if (au_ftest_ren(a->flags, ISSAMEDIR)
++ && !IS_ROOT(a->parent[SRC])) {
++ /* this and next block should not be compiled when
++ hinotify is disabled */
++ /* irregular/tricky rename lock */
++ LKTRLabel(here);
++ au_ren_pin_init(a->pin + SRC, a->src_dentry, a->pin + DST,
++ a->dentry, a->btgt);
++ a->gparent[SRC] = dget_parent(a->parent[SRC]);
++ di_read_lock_parent2(a->gparent[SRC], AuLock_IR);
++ a->h_locked[0] = a->h_parent[SRC];
++ a->h_locked[1] = dget_parent(a->h_parent[SRC]);
++ a->h_trap = vfsub_lock_rename(a->h_locked[0], a->h_locked[1]);
++ err = au_verify_parent(a->h_parent[SRC],
++ a->h_locked[1]->d_inode);
++ dput(a->h_locked[1]);
++ if (!err)
++ au_ren_fake_pin(a);
++ } else {
++ /* 3 or 4 dir locks. crazy */
++ LKTRLabel(here);
++ a->h_trap = au_ren_pin(a);
++ if (IS_ERR(a->h_trap))
++ err = PTR_ERR(a->h_trap);
++ }
++
++ if (!err && au_dbstart(a->src_dentry) == a->btgt)
++ err = au_verify_parent(a->h_dentry[SRC],
++ a->h_parent[SRC]->d_inode);
++ if (!err && au_dbstart(a->dentry) == a->btgt)
++ err = au_verify_parent(a->h_dentry[DST],
++ a->h_parent[DST]->d_inode);
++ if (!err) {
++ err = au_br_want_write(au_sbr(a->dentry->d_sb, a->btgt));
++ if (unlikely(err))
++ goto out_unlock;
++ au_fset_ren(a->flags, MNT_WRITE);
++ goto out; /* success */
++ }
++
++ err = -EBUSY;
++
++ out_unlock:
++ au_ren_unlock(a);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int aufs_rename(struct inode *src_dir, struct dentry *src_dentry,
++ struct inode *dir, struct dentry *dentry)
++{
++ int err;
++ aufs_bindex_t bend, bindex;
++ unsigned char do_dt_dstdir, hinotify;
++ struct inode *inode[2];
++ enum { PARENT, CHILD };
++ /* reduce stack space */
++ struct {
++ struct au_ren_args a;
++ struct au_dtime dt[2][2];
++ } *p;
++ struct au_wr_dir_args wr_dir_args = {
++ /* .force_btgt = -1, */
++ .flags = AuWrDir_ADD_ENTRY
++ };
++
++ LKTRTrace("i%lu, %.*s, i%lu, %.*s\n",
++ src_dir->i_ino, AuDLNPair(src_dentry),
++ dir->i_ino, AuDLNPair(dentry));
++ AuDebugOn(IS_ROOT(src_dentry) || IS_ROOT(dentry));
++ IMustLock(src_dir);
++ IMustLock(dir);
++ inode[DST] = dentry->d_inode;
++ if (inode[DST]) {
++ IMustLock(inode[DST]);
++ au_igrab(inode[DST]);
++ }
++
++ err = -ENOMEM;
++ BUILD_BUG_ON(sizeof(*p) > PAGE_SIZE);
++ p = kzalloc(sizeof(*p), GFP_NOFS);
++ if (unlikely(!p))
++ goto out;
++
++ err = -ENOTDIR;
++ p->a.src_dir = src_dir;
++ p->a.src_dentry = src_dentry;
++ p->a.dir = dir;
++ p->a.dentry = dentry;
++ p->a.sb = src_dentry->d_sb;
++ inode[SRC] = src_dentry->d_inode;
++ p->a.flags = 0;
++ if (S_ISDIR(inode[SRC]->i_mode)) {
++ au_fset_ren(p->a.flags, ISDIR);
++ if (unlikely(inode[DST] && !S_ISDIR(inode[DST]->i_mode)))
++ goto out_free;
++ aufs_read_and_write_lock2(dentry, src_dentry, AuLock_DIR);
++ } else
++ aufs_read_and_write_lock2(dentry, src_dentry, 0);
++
++ p->a.mnt_flags = au_mntflags(p->a.sb);
++ if (au_test_dlgt(p->a.mnt_flags))
++ au_fset_ren(p->a.flags, DLGT);
++ p->a.parent[SRC] = src_dentry->d_parent; /* dir inode is locked */
++ p->a.parent[DST] = dentry->d_parent; /* dir inode is locked */
++ au_fset_ren(p->a.flags, ISSAMEDIR); /* temporary */
++ di_write_lock_parent(p->a.parent[DST]);
++
++ /* which branch we process */
++ p->a.bstart[SRC] = au_dbstart(src_dentry);
++ p->a.bstart[DST] = au_dbstart(dentry);
++ if (au_ftest_ren(p->a.flags, ISDIR))
++ au_fset_wrdir(wr_dir_args.flags, ISDIR);
++ wr_dir_args.force_btgt = p->a.bstart[SRC];
++ if (dentry->d_inode && p->a.bstart[DST] < p->a.bstart[SRC])
++ wr_dir_args.force_btgt = p->a.bstart[DST];
++ wr_dir_args.force_btgt = au_wbr(dentry, wr_dir_args.force_btgt);
++ err = au_wr_dir(dentry, src_dentry, &wr_dir_args);
++ p->a.btgt = err;
++ if (unlikely(err < 0))
++ goto out_unlock;
++
++ /* are they available to be renamed */
++ err = 0;
++ au_nhash_init(&p->a.whlist);
++ if (au_ftest_ren(p->a.flags, ISDIR) && inode[DST]) {
++ au_set_dbstart(dentry, p->a.bstart[DST]);
++ err = may_rename_dstdir(dentry, p->a.btgt, &p->a.whlist);
++ au_set_dbstart(dentry, p->a.btgt);
++ }
++ p->a.h_dentry[DST] = au_h_dptr(dentry, au_dbstart(dentry));
++ if (unlikely(err))
++ goto out_unlock;
++ /* todo: minor optimize,
++ their sb may be same while their bindex differs? */
++ p->a.h_dentry[SRC] = au_h_dptr(src_dentry, au_dbstart(src_dentry));
++ if (au_ftest_ren(p->a.flags, ISDIR)) {
++ err = may_rename_srcdir(src_dentry, p->a.btgt);
++ if (unlikely(err))
++ goto out_children;
++ }
++
++ /* prepare the writable parent dir on the same branch */
++ if (p->a.bstart[DST] == p->a.btgt) {
++ au_fset_ren(p->a.flags, WHDST);
++ } else {
++ err = au_cpup_dirs(dentry, p->a.btgt);
++ if (unlikely(err))
++ goto out_children;
++ }
++
++ if (src_dir != dir) {
++ /*
++ * this temporary unlock is safe,
++ * because both dir->i_mutex are locked.
++ */
++ di_write_unlock(p->a.parent[DST]);
++ di_write_lock_parent(p->a.parent[SRC]);
++ err = au_wr_dir_need_wh
++ (src_dentry, au_ftest_ren(p->a.flags, ISDIR),
++ &p->a.btgt);
++ di_write_unlock(p->a.parent[SRC]);
++ di_write_lock2_parent(p->a.parent[SRC], p->a.parent[DST],
++ /*isdir*/1);
++ au_fclr_ren(p->a.flags, ISSAMEDIR);
++ } else
++ err = au_wr_dir_need_wh
++ (src_dentry, au_ftest_ren(p->a.flags, ISDIR),
++ &p->a.btgt);
++ if (unlikely(err < 0))
++ goto out_children;
++ if (err)
++ au_fset_ren(p->a.flags, WHSRC);
++
++ hinotify = au_opt_test(p->a.mnt_flags, UDBA_INOTIFY);
++ p->a.h_parent[SRC] = au_h_dptr(p->a.parent[SRC], p->a.btgt);
++ p->a.h_parent[DST] = au_h_dptr(p->a.parent[DST], p->a.btgt);
++ err = au_ren_lock(&p->a);
++ if (unlikely(err))
++ goto out_children;
++
++ if (!au_opt_test(p->a.mnt_flags, UDBA_NONE)) {
++ p->a.ndx.nfsmnt = au_nfsmnt(p->a.sb, p->a.btgt);
++ if (au_ftest_ren(p->a.flags, DLGT))
++ au_fset_ndx(p->a.ndx.flags, DLGT);
++ err = au_may_ren(&p->a);
++ if (unlikely(err))
++ goto out_hdir;
++ memset(&p->a.ndx, 0, sizeof(p->a.ndx));
++ }
++
++ /* store timestamps to be revertible */
++ au_dtime_store(p->dt[PARENT] + SRC, p->a.parent[SRC],
++ p->a.h_parent[SRC], au_pinned_hdir(p->a.pin + SRC),
++ au_pinned_hgdir(p->a.pin + SRC)
++ /* hgdir[SRC] */);
++ if (!au_ftest_ren(p->a.flags, ISSAMEDIR))
++ au_dtime_store(p->dt[PARENT] + DST, p->a.parent[DST],
++ p->a.h_parent[DST],
++ au_pinned_hdir(p->a.pin + DST),
++ au_pinned_hgdir(p->a.pin + DST)
++ /* hgdir[DST] */);
++ do_dt_dstdir = 0;
++ if (au_ftest_ren(p->a.flags, ISDIR)) {
++ au_dtime_store(p->dt[CHILD] + SRC, src_dentry,
++ p->a.h_dentry[SRC], au_hi(inode[SRC], p->a.btgt),
++ au_pinned_hdir(p->a.pin + SRC));
++ if (p->a.h_dentry[DST]->d_inode) {
++ do_dt_dstdir = 1;
++ au_dtime_store(p->dt[CHILD] + DST, dentry,
++ p->a.h_dentry[DST],
++ au_hi(inode[DST], p->a.btgt),
++ au_pinned_hdir(p->a.pin + DST));
++ }
++ }
++
++ err = do_rename(&p->a);
++ if (unlikely(err))
++ goto out_dt;
++
++ /* update dir attributes */
++ dir->i_version++;
++ if (au_ftest_ren(p->a.flags, ISDIR)) {
++ /* is this updating defined in POSIX? */
++ //vfsub_i_lock(inode[SRC]);
++ au_cpup_attr_timesizes(inode[SRC]);
++ //vfsub_i_unlock(inode[SRC]);
++
++ au_cpup_attr_nlink(dir, /*force*/1);
++ if (inode[DST]) {
++ inode[DST]->i_nlink = 0;
++ au_cpup_attr_timesizes(inode[DST]);
++ }
++ }
++ if (au_ibstart(dir) == p->a.btgt)
++ au_cpup_attr_timesizes(dir);
++
++ if (!au_ftest_ren(p->a.flags, ISSAMEDIR)) {
++ src_dir->i_version++;
++ if (au_ftest_ren(p->a.flags, ISDIR))
++ au_cpup_attr_nlink(src_dir, /*force*/1);
++ if (au_ibstart(src_dir) == p->a.btgt)
++ au_cpup_attr_timesizes(src_dir);
++ }
++
++ /* todo: simple d_drop(src_dentry) is not enough? */
++ /* dput/iput all lower dentries */
++ au_set_dbwh(src_dentry, -1);
++ bend = au_dbend(src_dentry);
++ for (bindex = p->a.btgt + 1; bindex <= bend; bindex++) {
++ struct dentry *hd;
++ hd = au_h_dptr(src_dentry, bindex);
++ if (hd)
++ au_set_h_dptr(src_dentry, bindex, NULL);
++ }
++ au_set_dbend(src_dentry, p->a.btgt);
++
++ if (au_opt_test(p->a.mnt_flags, PLINK)
++ && au_plink_test(src_dentry->d_sb, inode[SRC]))
++ goto out_hdir; /* success */
++ bend = au_ibend(inode[SRC]);
++ for (bindex = p->a.btgt + 1; bindex <= bend; bindex++) {
++ struct inode *hi;
++ hi = au_h_iptr(inode[SRC], bindex);
++ if (hi) {
++ au_xino_write0(p->a.sb, bindex, hi->i_ino, 0);
++ /* ignore this error */
++ au_set_h_iptr(inode[SRC], bindex, NULL, 0);
++ }
++ }
++ au_set_ibend(inode[SRC], p->a.btgt);
++ goto out_hdir; /* success */
++
++ out_dt:
++ au_dtime_revert(p->dt[PARENT] + SRC);
++ if (!au_ftest_ren(p->a.flags, ISSAMEDIR))
++ au_dtime_revert(p->dt[PARENT] + DST);
++ if (au_ftest_ren(p->a.flags, ISDIR) && err != -EIO) {
++ struct dentry *hd;
++
++ hd = p->dt[CHILD][SRC].dt_h_dentry;
++ vfsub_i_lock_nested(hd->d_inode, AuLsc_I_CHILD);
++ au_dtime_revert(p->dt[CHILD] + SRC);
++ vfsub_i_unlock(hd->d_inode);
++ if (do_dt_dstdir) {
++ hd = p->dt[CHILD][DST].dt_h_dentry;
++ vfsub_i_lock_nested(hd->d_inode, AuLsc_I_CHILD);
++ au_dtime_revert(p->dt[CHILD] + DST);
++ vfsub_i_unlock(hd->d_inode);
++ }
++ }
++ out_hdir:
++ au_ren_unlock(&p->a);
++ out_children:
++ au_nhash_fin(&p->a.whlist);
++ out_unlock:
++ if (unlikely(err && au_ftest_ren(p->a.flags, ISDIR))) {
++ au_update_dbstart(dentry);
++ d_drop(dentry);
++ }
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++ if (!err) {
++ d_move(src_dentry, dentry);
++ if (inode[DST]
++ && (inode[DST]->i_nlink == 1
++ || au_ftest_ren(p->a.flags, ISDIR)))
++ inode[DST]->i_flags |= S_DEAD;
++ }
++#endif
++ if (au_ftest_ren(p->a.flags, ISSAMEDIR))
++ di_write_unlock(p->a.parent[DST]);
++ else
++ di_write_unlock2(p->a.parent[SRC], p->a.parent[DST]);
++ aufs_read_and_write_unlock2(dentry, src_dentry);
++ out_free:
++ kfree(p);
++ out:
++ iput(inode[DST]);
++ AuTraceErr(err);
++ //lktr_clear_pid(current->pid, LktrArrayPid);
++ if (unlikely(err == -EBUSY && au_test_nfsd(current)))
++ err = -ESTALE;
++ return err;
++}
+diff --git a/fs/aufs/iinfo.c b/fs/aufs/iinfo.c
+new file mode 100644
+index 0000000..f6cf01c
+--- /dev/null
++++ b/fs/aufs/iinfo.c
+@@ -0,0 +1,284 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode private data
++ *
++ * $Id: iinfo.c,v 1.59 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++struct au_iinfo *au_ii(struct inode *inode)
++{
++ struct au_iinfo *iinfo;
++
++ iinfo = &(container_of(inode, struct aufs_icntnr, vfs_inode)->iinfo);
++ /* bad_inode case */
++ if (unlikely(!iinfo->ii_hinode))
++ return NULL;
++ AuDebugOn(!iinfo->ii_hinode
++ /* || au_sbi(inode->i_sb)->si_bend < iinfo->ii_bend */
++ || iinfo->ii_bend < iinfo->ii_bstart);
++ return iinfo;
++}
++
++struct inode *au_h_iptr(struct inode *inode, aufs_bindex_t bindex)
++{
++ struct inode *hidden_inode;
++
++ /* lock free root dinfo/inode */
++ if (inode->i_ino != AUFS_ROOT_INO) {
++ IiMustAnyLock(inode);
++ AuDebugOn(bindex < 0 || au_ibend(inode) < bindex);
++ } else {
++ SiMustAnyLock(inode->i_sb);
++ AuDebugOn(bindex < 0 || au_sbend(inode->i_sb) < bindex);
++ }
++ hidden_inode = au_ii(inode)->ii_hinode[0 + bindex].hi_inode;
++ AuDebugOn(hidden_inode && atomic_read(&hidden_inode->i_count) <= 0);
++ return hidden_inode;
++}
++
++aufs_bindex_t au_ii_br_id(struct inode *inode, aufs_bindex_t bindex)
++{
++ IiMustAnyLock(inode);
++ AuDebugOn(bindex < 0
++ || au_ibend(inode) < bindex
++ || !au_ii(inode)->ii_hinode[0 + bindex].hi_inode);
++ return au_ii(inode)->ii_hinode[0 + bindex].hi_id;
++}
++
++/* todo: hard/soft set? */
++void au_set_ibstart(struct inode *inode, aufs_bindex_t bindex)
++{
++ struct au_iinfo *iinfo = au_ii(inode);
++ struct inode *h_inode;
++
++ IiMustWriteLock(inode);
++ AuDebugOn(au_sbend(inode->i_sb) < bindex);
++ iinfo->ii_bstart = bindex;
++ h_inode = iinfo->ii_hinode[bindex + 0].hi_inode;
++ if (h_inode)
++ au_cpup_igen(inode, h_inode);
++}
++
++unsigned int au_hi_flags(struct inode *inode, int isdir)
++{
++ unsigned int flags;
++ const unsigned int mnt_flags = au_mntflags(inode->i_sb);
++
++ flags = 0;
++ if (au_opt_test_xino(mnt_flags))
++ au_fset_hi(flags, XINO);
++ if (isdir && au_opt_test(mnt_flags, UDBA_INOTIFY))
++ au_fset_hi(flags, NOTIFY);
++ return flags;
++}
++
++void au_set_h_iptr(struct inode *inode, aufs_bindex_t bindex,
++ struct inode *h_inode, unsigned int flags)
++{
++ struct au_hinode *hinode;
++ struct inode *hi;
++ struct au_iinfo *iinfo = au_ii(inode);
++
++ LKTRTrace("i%lu, b%d, hi%lu, flags 0x%x\n",
++ inode->i_ino, bindex, h_inode ? h_inode->i_ino : 0, flags);
++ IiMustWriteLock(inode);
++ hinode = iinfo->ii_hinode + bindex;
++ hi = hinode->hi_inode;
++ AuDebugOn(bindex < au_ibstart(inode) || au_ibend(inode) < bindex);
++ AuDebugOn(h_inode && atomic_read(&h_inode->i_count) <= 0);
++ AuDebugOn(h_inode && hi);
++
++ if (hi)
++ au_hiput(hinode);
++ hinode->hi_inode = h_inode;
++ if (h_inode) {
++ int err;
++ struct super_block *sb = inode->i_sb;
++
++ if (bindex == iinfo->ii_bstart)
++ au_cpup_igen(inode, h_inode);
++ hinode->hi_id = au_sbr_id(sb, bindex);
++ if (au_ftest_hi(flags, XINO)) {
++ struct au_xino_entry xinoe = {
++ .ino = inode->i_ino,
++ /* .h_gen = h_inode->i_generation */
++ };
++ err = au_xino_write(sb, bindex, h_inode->i_ino, &xinoe);
++ if (unlikely(err))
++ AuIOErr1("failed au_xino_write() %d\n", err);
++ }
++
++ if (au_ftest_hi(flags, NOTIFY)
++ && au_br_hinotifyable(au_sbr_perm(sb, bindex))) {
++ err = au_hin_alloc(hinode, inode, h_inode);
++ if (unlikely(err))
++ AuIOErr1("au_hin_alloc() %d\n", err);
++ }
++ }
++}
++
++void au_set_hi_wh(struct inode *inode, aufs_bindex_t bindex,
++ struct dentry *h_wh)
++{
++ struct au_hinode *hinode;
++
++ IiMustWriteLock(inode);
++ hinode = au_ii(inode)->ii_hinode + bindex;
++ AuDebugOn(hinode->hi_whdentry);
++ hinode->hi_whdentry = h_wh;
++}
++
++void au_update_iigen(struct inode *inode)
++{
++ AuDebugOn(!inode->i_sb);
++ atomic_set(&au_ii(inode)->ii_generation, au_sigen(inode->i_sb));
++ /* smp_mb(); */ /* atomic_set */
++}
++
++/* it may be called at remount time, too */
++void au_update_brange(struct inode *inode, int do_put_zero)
++{
++ struct au_iinfo *iinfo;
++
++ LKTRTrace("i%lu, %d\n", inode->i_ino, do_put_zero);
++ IiMustWriteLock(inode);
++
++ iinfo = au_ii(inode);
++ if (!iinfo || iinfo->ii_bstart < 0)
++ return;
++
++ if (do_put_zero) {
++ aufs_bindex_t bindex;
++ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend;
++ bindex++) {
++ struct inode *h_i;
++ h_i = iinfo->ii_hinode[0 + bindex].hi_inode;
++ if (h_i && !h_i->i_nlink)
++ au_set_h_iptr(inode, bindex, NULL, 0);
++ }
++ }
++
++ iinfo->ii_bstart = -1;
++ while (++iinfo->ii_bstart <= iinfo->ii_bend)
++ if (iinfo->ii_hinode[0 + iinfo->ii_bstart].hi_inode)
++ break;
++ if (iinfo->ii_bstart > iinfo->ii_bend) {
++ iinfo->ii_bstart = -1;
++ iinfo->ii_bend = -1;
++ return;
++ }
++
++ iinfo->ii_bend++;
++ while (0 <= --iinfo->ii_bend)
++ if (iinfo->ii_hinode[0 + iinfo->ii_bend].hi_inode)
++ break;
++ AuDebugOn(iinfo->ii_bstart > iinfo->ii_bend || iinfo->ii_bend < 0);
++}
++
++/* ---------------------------------------------------------------------- */
++
++int au_iinfo_init(struct inode *inode)
++{
++ struct au_iinfo *iinfo;
++ struct super_block *sb;
++ int nbr, i;
++
++ sb = inode->i_sb;
++ AuDebugOn(!sb);
++ iinfo = &(container_of(inode, struct aufs_icntnr, vfs_inode)->iinfo);
++ AuDebugOn(iinfo->ii_hinode);
++ nbr = au_sbend(sb) + 1;
++ if (nbr <= 0)
++ nbr = 1;
++ iinfo->ii_hinode = kcalloc(nbr, sizeof(*iinfo->ii_hinode), GFP_NOFS);
++ if (iinfo->ii_hinode) {
++ for (i = 0; i < nbr; i++)
++ iinfo->ii_hinode[i].hi_id = -1;
++ atomic_set(&iinfo->ii_generation, au_sigen(sb));
++ /* smp_mb(); */ /* atomic_set */
++ au_rw_init_nolock(&iinfo->ii_rwsem);
++ iinfo->ii_bstart = -1;
++ iinfo->ii_bend = -1;
++ iinfo->ii_vdir = NULL;
++ return 0;
++ }
++ return -ENOMEM;
++}
++
++static int au_iinfo_write0(struct super_block *sb, struct au_hinode *hinode,
++ ino_t ino)
++{
++ int err, locked;
++ aufs_bindex_t bindex;
++
++ err = 0;
++ locked = si_noflush_read_trylock(sb); /* crucio! */
++ bindex = au_br_index(sb, hinode->hi_id);
++ if (bindex >= 0)
++ err = au_xino_write0(sb, bindex, hinode->hi_inode->i_ino, ino);
++ /* error action? */
++ if (locked)
++ si_read_unlock(sb);
++ return err;
++}
++
++void au_iinfo_fin(struct inode *inode)
++{
++ struct au_iinfo *iinfo;
++ aufs_bindex_t bend;
++ unsigned char unlinked;
++ struct au_hinode *hi;
++ struct super_block *sb;
++ ino_t ino;
++
++ iinfo = au_ii(inode);
++ /* bad_inode case */
++ if (!iinfo)
++ return;
++
++ if (iinfo->ii_vdir)
++ au_vdir_free(iinfo->ii_vdir);
++
++ if (iinfo->ii_bstart >= 0) {
++ sb = inode->i_sb;
++ unlinked = !inode->i_nlink;
++ ino = 0;
++ if (unlinked)
++ ino = inode->i_ino;
++ hi = iinfo->ii_hinode + iinfo->ii_bstart;
++ bend = iinfo->ii_bend;
++ while (iinfo->ii_bstart++ <= bend) {
++ if (hi->hi_inode) {
++ if (unlinked || !hi->hi_inode->i_nlink) {
++ au_iinfo_write0(sb, hi, ino);
++ /* ignore this error */
++ ino = 0;
++ }
++ au_hiput(hi);
++ }
++ hi++;
++ }
++ }
++
++ kfree(iinfo->ii_hinode);
++ au_rwsem_destroy(&iinfo->ii_rwsem);
++}
+diff --git a/fs/aufs/inode.c b/fs/aufs/inode.c
+new file mode 100644
+index 0000000..023fb27
+--- /dev/null
++++ b/fs/aufs/inode.c
+@@ -0,0 +1,430 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode functions
++ *
++ * $Id: inode.c,v 1.55 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++int au_refresh_hinode_self(struct inode *inode)
++{
++ int err, new_sz, update;
++ struct inode *first;
++ struct au_hinode *p, *q, tmp;
++ struct super_block *sb;
++ struct au_iinfo *iinfo;
++ aufs_bindex_t bindex, bend, new_bindex;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++ IiMustWriteLock(inode);
++
++ err = -ENOMEM;
++ update = 0;
++ sb = inode->i_sb;
++ bend = au_sbend(sb);
++ new_sz = sizeof(*iinfo->ii_hinode) * (bend + 1);
++ iinfo = au_ii(inode);
++ p = au_kzrealloc(iinfo->ii_hinode, sizeof(*p) * (iinfo->ii_bend + 1),
++ new_sz, GFP_NOFS);
++ if (unlikely(!p))
++ goto out;
++
++ iinfo->ii_hinode = p;
++ p = iinfo->ii_hinode + iinfo->ii_bstart;
++ first = p->hi_inode;
++ err = 0;
++ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend;
++ bindex++, p++) {
++ if (!p->hi_inode)
++ continue;
++
++ new_bindex = au_br_index(sb, p->hi_id);
++ if (new_bindex == bindex)
++ continue;
++ if (new_bindex < 0) {
++ update++;
++ au_hiput(p);
++ p->hi_inode = NULL;
++ continue;
++ }
++
++ if (new_bindex < iinfo->ii_bstart)
++ iinfo->ii_bstart = new_bindex;
++ if (iinfo->ii_bend < new_bindex)
++ iinfo->ii_bend = new_bindex;
++ /* swap two hidden inode, and loop again */
++ q = iinfo->ii_hinode + new_bindex;
++ tmp = *q;
++ *q = *p;
++ *p = tmp;
++ if (tmp.hi_inode) {
++ bindex--;
++ p--;
++ }
++ }
++ au_update_brange(inode, /*do_put_zero*/0);
++
++ if (unlikely(err))
++ goto out;
++
++ if (1 || first != au_h_iptr(inode, iinfo->ii_bstart))
++ au_cpup_attr_all(inode, /*force*/0);
++ if (update && S_ISDIR(inode->i_mode))
++ inode->i_version++;
++ au_update_iigen(inode);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_refresh_hinode(struct inode *inode, struct dentry *dentry)
++{
++ int err, update;
++ struct inode *first;
++ struct au_hinode *p;
++ struct super_block *sb;
++ struct au_iinfo *iinfo;
++ aufs_bindex_t bindex, bend;
++ unsigned char isdir;
++ unsigned int flags;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ IiMustWriteLock(inode);
++
++ err = au_refresh_hinode_self(inode);
++ if (unlikely(err))
++ goto out;
++
++ sb = dentry->d_sb;
++ bend = au_sbend(sb);
++ iinfo = au_ii(inode);
++ update = 0;
++ p = iinfo->ii_hinode + iinfo->ii_bstart;
++ first = p->hi_inode;
++ isdir = S_ISDIR(inode->i_mode);
++ flags = au_hi_flags(inode, isdir);
++ bend = au_dbend(dentry);
++ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++) {
++ struct inode *hi;
++ struct dentry *hd;
++
++ hd = au_h_dptr(dentry, bindex);
++ if (!hd || !hd->d_inode)
++ continue;
++
++ if (iinfo->ii_bstart <= bindex && bindex <= iinfo->ii_bend) {
++ hi = au_h_iptr(inode, bindex);
++ if (hi) {
++ if (hi == hd->d_inode)
++ continue;
++ err = -ESTALE;
++ break;
++ }
++ }
++ if (bindex < iinfo->ii_bstart)
++ iinfo->ii_bstart = bindex;
++ if (iinfo->ii_bend < bindex)
++ iinfo->ii_bend = bindex;
++ au_set_h_iptr(inode, bindex, au_igrab(hd->d_inode), flags);
++ update++;
++ }
++ au_update_brange(inode, /*do_put_zero*/0);
++
++ if (unlikely(err))
++ goto out;
++
++ if (1 || first != au_h_iptr(inode, iinfo->ii_bstart))
++ au_cpup_attr_all(inode, /*force*/0);
++ if (update && isdir)
++ inode->i_version++;
++ au_update_iigen(inode);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int set_inode(struct inode *inode, struct dentry *dentry)
++{
++ int err;
++ struct dentry *h_dentry;
++ struct inode *h_inode;
++ umode_t mode;
++ aufs_bindex_t bindex, bstart, btail;
++ unsigned char isdir;
++ struct au_iinfo *iinfo;
++ unsigned int flags;
++
++ LKTRTrace("i%lu, %.*s\n", inode->i_ino, AuDLNPair(dentry));
++ AuDebugOn(!(inode->i_state & I_NEW));
++ IiMustWriteLock(inode);
++ bstart = au_dbstart(dentry);
++ h_dentry = au_h_dptr(dentry, bstart);
++ AuDebugOn(!h_dentry);
++ h_inode = h_dentry->d_inode;
++ AuDebugOn(!h_inode);
++
++ err = 0;
++ isdir = 0;
++ mode = h_inode->i_mode;
++ switch (mode & S_IFMT) {
++ case S_IFREG:
++ btail = au_dbtail(dentry);
++ inode->i_op = &aufs_iop;
++ inode->i_fop = &aufs_file_fop;
++ inode->i_mapping->a_ops = &aufs_aop;
++ break;
++ case S_IFDIR:
++ isdir = 1;
++ btail = au_dbtaildir(dentry);
++ inode->i_op = &aufs_dir_iop;
++ inode->i_fop = &aufs_dir_fop;
++ break;
++ case S_IFLNK:
++ btail = au_dbtail(dentry);
++ inode->i_op = &aufs_symlink_iop;
++ /* inode->i_fop = &aufs_file_fop; */
++ break;
++ case S_IFBLK:
++ case S_IFCHR:
++ case S_IFIFO:
++ case S_IFSOCK:
++ btail = au_dbtail(dentry);
++ inode->i_op = &aufs_iop;
++ init_special_inode(inode, mode,
++ au_h_rdev(h_inode, /*h_mnt*/NULL, h_dentry));
++ break;
++ default:
++ AuIOErr("Unknown file type 0%o\n", mode);
++ err = -EIO;
++ goto out;
++ }
++
++ /* do not set inotify for whiteouted dirs (SHWH mode) */
++ flags = au_hi_flags(inode, isdir);
++ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH)
++ && au_ftest_hi(flags, NOTIFY)
++ && dentry->d_name.len > AUFS_WH_PFX_LEN
++ && !memcmp(dentry->d_name.name, AUFS_WH_PFX, AUFS_WH_PFX_LEN))
++ au_fclr_hi(flags, NOTIFY);
++ iinfo = au_ii(inode);
++ iinfo->ii_bstart = bstart;
++ iinfo->ii_bend = btail;
++ for (bindex = bstart; bindex <= btail; bindex++) {
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!h_dentry)
++ continue;
++ AuDebugOn(!h_dentry->d_inode);
++ au_set_h_iptr(inode, bindex, au_igrab(h_dentry->d_inode),
++ flags);
++ }
++ au_cpup_attr_all(inode, /*force*/1);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* successful returns with iinfo write_locked */
++/* todo: return with unlocked? */
++static int reval_inode(struct inode *inode, struct dentry *dentry, int *matched)
++{
++ int err;
++ struct inode *h_inode, *h_dinode;
++ aufs_bindex_t bindex, bend;
++
++ LKTRTrace("i%lu, %.*s\n", inode->i_ino, AuDLNPair(dentry));
++
++ *matched = 0;
++
++ /*
++ * before this function, if aufs got any iinfo lock, it must be only
++ * one, the parent dir.
++ * it can happen by UDBA and the obsoleted inode number.
++ */
++ err = -EIO;
++ if (unlikely(inode->i_ino == parent_ino(dentry)))
++ goto out;
++
++ h_dinode = au_h_dptr(dentry, au_dbstart(dentry))->d_inode;
++ //vfsub_i_lock_nested(inode, AuLsc_I_CHILD);
++ ii_write_lock_new_child(inode);
++ /* it happend */
++ if (unlikely(IS_DEADDIR(inode)))
++ goto out_unlock;
++
++ err = 0;
++ bend = au_ibend(inode);
++ for (bindex = au_ibstart(inode); bindex <= bend; bindex++) {
++ h_inode = au_h_iptr(inode, bindex);
++ if (h_inode && h_inode == h_dinode) {
++ /* && (ibs != bstart
++ || !au_test_higen(inode, h_inode))); */
++ *matched = 1;
++ err = 0;
++ if (au_iigen(inode) != au_digen(dentry))
++ err = au_refresh_hinode(inode, dentry);
++ break;
++ }
++ }
++
++ out_unlock:
++ if (unlikely(err))
++ ii_write_unlock(inode);
++ //vfsub_i_unlock(inode);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* successful returns with iinfo write_locked */
++/* todo: return with unlocked? */
++struct inode *au_new_inode(struct dentry *dentry, int must_new)
++{
++ struct inode *inode, *h_inode;
++ struct dentry *h_dentry;
++ struct super_block *sb;
++ ino_t h_ino;
++ int err, match;
++ aufs_bindex_t bstart;
++ struct au_xino_entry xinoe;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ sb = dentry->d_sb;
++ bstart = au_dbstart(dentry);
++ h_dentry = au_h_dptr(dentry, bstart);
++ AuDebugOn(!h_dentry);
++ h_inode = h_dentry->d_inode;
++ AuDebugOn(!h_inode);
++
++ h_ino = h_inode->i_ino;
++ err = au_xino_read(sb, bstart, h_ino, &xinoe);
++ inode = ERR_PTR(err);
++ if (unlikely(err))
++ goto out;
++ new_ino:
++ if (!xinoe.ino) {
++ xinoe.ino = au_xino_new_ino(sb);
++ if (!xinoe.ino) {
++ inode = ERR_PTR(-EIO);
++ goto out;
++ }
++ }
++
++ LKTRTrace("i%lu\n", (unsigned long)xinoe.ino);
++ err = -ENOMEM;
++ inode = iget_locked(sb, xinoe.ino);
++ if (unlikely(!inode))
++ goto out;
++ err = PTR_ERR(inode);
++ if (IS_ERR(inode))
++ goto out;
++ err = -ENOMEM;
++ if (unlikely(is_bad_inode(inode)))
++ goto out_iput;
++
++ LKTRTrace("%lx, new %d\n", inode->i_state, !!(inode->i_state & I_NEW));
++ if (inode->i_state & I_NEW) {
++ sb->s_op->read_inode(inode);
++ if (!is_bad_inode(inode)) {
++ ii_write_lock_new_child(inode);
++ err = set_inode(inode, dentry);
++ //err = -1;
++ }
++ unlock_new_inode(inode);
++ if (!err)
++ goto out; /* success */
++ if (!is_bad_inode(inode))
++ ii_write_unlock(inode);
++ goto out_iput;
++ } else if (!must_new) {
++ err = reval_inode(inode, dentry, &match);
++ if (!err)
++ goto out; /* success */
++ else if (match)
++ goto out_iput;
++ }
++
++ if (unlikely(au_test_unique_ino(h_dentry, h_ino)))
++ AuWarn1("Un-notified UDBA or repeatedly renamed dir,"
++ " b%d, %s, %.*s, hi%lu, i%lu.\n",
++ bstart, au_sbtype(h_dentry->d_sb), AuDLNPair(dentry),
++ (unsigned long)h_ino, (unsigned long)xinoe.ino);
++ xinoe.ino = 0;
++ err = au_xino_write0(sb, bstart, h_ino, 0);
++ if (!err) {
++ iput(inode);
++ goto new_ino;
++ }
++ /* force noxino? */
++
++ out_iput:
++ iput(inode);
++ inode = ERR_PTR(err);
++ out:
++ AuTraceErrPtr(inode);
++ return inode;
++}
++
++/* ---------------------------------------------------------------------- */
++
++int au_test_ro(struct super_block *sb, aufs_bindex_t bindex,
++ struct inode *inode)
++{
++ int err;
++
++ err = au_br_rdonly(au_sbr(sb, bindex));
++
++ /* pseudo-link after flushed may out of bounds */
++ if (!err
++ && inode
++ && au_ibstart(inode) <= bindex
++ && bindex <= au_ibend(inode)) {
++ /*
++ * permission check is unnecessary since vfsub routine
++ * will be called later
++ */
++ struct inode *hi = au_h_iptr(inode, bindex);
++ if (hi)
++ err = IS_IMMUTABLE(hi) ? -EROFS : 0;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++int au_test_h_perm(struct inode *h_inode, int mask, int dlgt)
++{
++ if (!current->fsuid)
++ return 0;
++ /* todo: fake nameidata? */
++ return vfsub_permission(h_inode, mask, NULL, dlgt);
++}
++
++int au_test_h_perm_sio(struct inode *h_inode, int mask, int dlgt)
++{
++ if (au_test_nfs(h_inode->i_sb)
++ && (mask & MAY_WRITE)
++ && S_ISDIR(h_inode->i_mode))
++ mask |= MAY_READ; /* force permission check */
++ return au_test_h_perm(h_inode, mask, dlgt);
++}
+diff --git a/fs/aufs/inode.h b/fs/aufs/inode.h
+new file mode 100644
+index 0000000..7f7e9a3
+--- /dev/null
++++ b/fs/aufs/inode.h
+@@ -0,0 +1,593 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * inode operations
++ *
++ * $Id: inode.h,v 1.66 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_INODE_H__
++#define __AUFS_INODE_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/namei.h>
++#include <linux/security.h>
++#include <linux/aufs_type.h>
++#include "misc.h"
++
++struct au_hinode;
++struct au_vdir;
++struct au_iinfo {
++ atomic_t ii_generation;
++ struct super_block *ii_hsb1; /* no get/put */
++
++ struct au_rwsem ii_rwsem;
++ aufs_bindex_t ii_bstart, ii_bend;
++ __u32 ii_higen;
++ struct au_hinode *ii_hinode;
++ struct au_vdir *ii_vdir;
++};
++
++struct aufs_icntnr {
++ struct au_iinfo iinfo;
++ struct inode vfs_inode;
++};
++
++/* au_pin flags */
++#define AuPin_DI_LOCKED 1
++#define AuPin_DO_GPARENT (1 << 1)
++#define AuPin_MNT_WRITE 0 //(1 << 2)
++#define AuPin_VFS_RENAME (1 << 3)
++/* will be set automatically */
++#define AuPin_VERIFY (1 << 4)
++#define au_ftest_pin(flags, name) ((flags) & AuPin_##name)
++#define au_fset_pin(flags, name) { (flags) |= AuPin_##name; }
++#define au_fclr_pin(flags, name) { (flags) &= ~AuPin_##name; }
++
++struct au_pin1 {
++ /* input */
++ struct dentry *dentry;
++ unsigned char lsc_di, lsc_hi, flags;
++ aufs_bindex_t bindex;
++
++ /* output */
++ struct dentry *parent;
++ struct inode *h_dir;
++};
++
++enum {AuPin_PARENT, AuPin_GPARENT};
++struct au_pin {
++#ifdef CONFIG_AUFS_HINOTIFY
++ struct au_pin1 pin[2];
++#else
++ struct au_pin1 pin[1]; /* no grand parent */
++#endif
++};
++
++/* ---------------------------------------------------------------------- */
++
++/* inode.c */
++int au_refresh_hinode_self(struct inode *inode);
++int au_refresh_hinode(struct inode *inode, struct dentry *dentry);
++struct inode *au_new_inode(struct dentry *dentry, int must_new);
++int au_test_ro(struct super_block *sb, aufs_bindex_t bindex,
++ struct inode *inode);
++int au_test_h_perm(struct inode *h_inode, int mask, int dlgt);
++int au_test_h_perm_sio(struct inode *h_inode, int mask, int dlgt);
++
++/* i_op.c */
++extern struct inode_operations aufs_iop, aufs_symlink_iop, aufs_dir_iop;
++
++/* au_wr_dir flags */
++#define AuWrDir_ADD_ENTRY 1
++#define AuWrDir_ISDIR (1 << 1)
++#define au_ftest_wrdir(flags, name) ((flags) & AuWrDir_##name)
++#define au_fset_wrdir(flags, name) { (flags) |= AuWrDir_##name; }
++#define au_fclr_wrdir(flags, name) { (flags) &= ~AuWrDir_##name; }
++
++struct au_wr_dir_args {
++ aufs_bindex_t force_btgt;
++ unsigned char flags;
++};
++int au_wr_dir(struct dentry *dentry, struct dentry *src_dentry,
++ struct au_wr_dir_args *args);
++
++void au_pin_init(struct au_pin *args, struct dentry *dentry,
++ aufs_bindex_t bindex, int lsc_di, int lsc_hi,
++ unsigned char flags);
++int au_pin(struct au_pin *args, struct dentry *dentry, aufs_bindex_t bindex,
++ unsigned char flags) __must_check;
++int au_do_pin(struct au_pin1 *p, struct au_pin1 *gp) __must_check;
++void au_do_unpin(struct au_pin1 *p, struct au_pin1 *gp);
++
++/* i_op_add.c */
++struct au_ndx;
++int au_may_add(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_parent, int isdir, struct au_ndx *ndx);
++int aufs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev);
++int aufs_symlink(struct inode *dir, struct dentry *dentry, const char *symname);
++int aufs_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *nd);
++int aufs_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry);
++int aufs_mkdir(struct inode *dir, struct dentry *dentry, int mode);
++
++/* i_op_del.c */
++int au_wr_dir_need_wh(struct dentry *dentry, int isdir, aufs_bindex_t *bcpup);
++int au_may_del(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_parent, int isdir, struct au_ndx *ndx);
++int aufs_unlink(struct inode *dir, struct dentry *dentry);
++int aufs_rmdir(struct inode *dir, struct dentry *dentry);
++
++/* i_op_ren.c */
++int au_wbr(struct dentry *dentry, aufs_bindex_t btgt);
++int aufs_rename(struct inode *src_dir, struct dentry *src_dentry,
++ struct inode *dir, struct dentry *dentry);
++
++#ifdef CONFIG_AUFS_DLGT
++/* dlgt.c */
++int au_security_inode_permission(struct inode *h_inode, int mask,
++ struct nameidata *fake_nd, int dlgt);
++#else
++static inline
++int au_security_inode_permission(struct inode *h_inode, int mask,
++ struct nameidata *fake_nd, int dlgt)
++{
++ return security_inode_permission(h_inode, mask, fake_nd);
++}
++#endif /* CONFIG_AUFS_DLGT */
++
++#ifdef CONFIG_AUFS_GETATTR
++/* getattr.c */
++int aufs_getattr(struct vfsmount *mnt, struct dentry *dentry, struct kstat *st);
++#endif
++
++#if 0 /* reserved for future use */
++/* xattr.c */
++int aufs_setxattr(struct dentry *dentry, const char *name, const void *value,
++ size_t sz, int flags);
++ssize_t aufs_getxattr(struct dentry *dentry, const char *name, void *value,
++ size_t sz);
++ssize_t aufs_listxattr(struct dentry *dentry, char *list, size_t sz);
++int aufs_removexattr(struct dentry *dentry, const char *name);
++#endif
++
++/* iinfo.c */
++struct au_iinfo *au_ii(struct inode *inode);
++struct inode *au_h_iptr(struct inode *inode, aufs_bindex_t bindex);
++aufs_bindex_t au_ii_br_id(struct inode *inode, aufs_bindex_t bindex);
++
++void au_set_ibstart(struct inode *inode, aufs_bindex_t bindex);
++void au_set_hi_wh(struct inode *inode, aufs_bindex_t bindex,
++ struct dentry *h_wh);
++unsigned int au_hi_flags(struct inode *inode, int isdir);
++
++/* hinode flags */
++#define AuHi_XINO 1
++#define AuHi_NOTIFY (1 << 1)
++#define au_ftest_hi(flags, name) ((flags) & AuHi_##name)
++#define au_fset_hi(flags, name) { (flags) |= AuHi_##name; }
++#define au_fclr_hi(flags, name) { (flags) &= ~AuHi_##name; }
++#ifndef CONFIG_AUFS_HINOTIFY
++#undef AuHi_NOTIFY
++#define AuHi_NOTIFY 0
++#endif
++
++void au_set_h_iptr(struct inode *inode, aufs_bindex_t bindex,
++ struct inode *h_inode, unsigned int flags);
++
++void au_update_iigen(struct inode *inode);
++void au_update_brange(struct inode *inode, int do_put_zero);
++
++int au_iinfo_init(struct inode *inode);
++void au_iinfo_fin(struct inode *inode);
++
++/* plink.c */
++#ifdef CONFIG_AUFS_DEBUG
++void au_plink_list(struct super_block *sb);
++#else
++static inline void au_plink_list(struct super_block *sb)
++{
++ /* nothing */
++}
++#endif
++int au_plink_test(struct super_block *sb, struct inode *inode);
++struct dentry *au_plink_lkup(struct super_block *sb, aufs_bindex_t bindex,
++ struct inode *inode);
++void au_plink_append(struct super_block *sb, struct inode *inode,
++ struct dentry *h_dentry, aufs_bindex_t bindex);
++void au_plink_put(struct super_block *sb);
++void au_plink_half_refresh(struct super_block *sb, aufs_bindex_t br_id);
++
++/* ---------------------------------------------------------------------- */
++
++/* lock subclass for iinfo */
++enum {
++ AuLsc_II_CHILD, /* child first */
++ AuLsc_II_CHILD2, /* rename(2), link(2), and cpup at hinotify */
++ AuLsc_II_CHILD3, /* copyup dirs */
++ AuLsc_II_PARENT, /* see AuLsc_I_PARENT in vfsub.h */
++ AuLsc_II_PARENT2,
++ AuLsc_II_PARENT3,
++ AuLsc_II_PARENT4,
++ AuLsc_II_NEW_CHILD,
++};
++
++/*
++ * ii_read_lock_child, ii_write_lock_child,
++ * ii_read_lock_child2, ii_write_lock_child2,
++ * ii_read_lock_child3, ii_write_lock_child3,
++ * ii_read_lock_parent, ii_write_lock_parent,
++ * ii_read_lock_parent2, ii_write_lock_parent2,
++ * ii_read_lock_parent3, ii_write_lock_parent3,
++ * ii_read_lock_parent4, ii_write_lock_parent4,
++ * ii_read_lock_new_child, ii_write_lock_new_child,
++ */
++#define AuReadLockFunc(name, lsc) \
++static inline void ii_read_lock_##name(struct inode *i) \
++{ \
++ au_dbg_locking_ii_reg(i, 0, AuLsc_II_##lsc); \
++ au_rw_read_lock_nested(&au_ii(i)->ii_rwsem, AuLsc_II_##lsc); \
++ au_dbg_locking_ii_unreg(i, 0); \
++ au_dbg_locked_ii_reg(i, 0, AuLsc_II_##lsc); \
++}
++
++#define AuWriteLockFunc(name, lsc) \
++static inline void ii_write_lock_##name(struct inode *i) \
++{ \
++ au_dbg_locking_ii_reg(i, 1, AuLsc_II_##lsc); \
++ au_rw_write_lock_nested(&au_ii(i)->ii_rwsem, AuLsc_II_##lsc); \
++ au_dbg_locking_ii_unreg(i, 1); \
++ au_dbg_locked_ii_reg(i, 1, AuLsc_II_##lsc); \
++}
++
++#define AuRWLockFuncs(name, lsc) \
++ AuReadLockFunc(name, lsc) \
++ AuWriteLockFunc(name, lsc)
++
++AuRWLockFuncs(child, CHILD);
++AuRWLockFuncs(child2, CHILD2);
++AuRWLockFuncs(child3, CHILD3);
++AuRWLockFuncs(parent, PARENT);
++AuRWLockFuncs(parent2, PARENT2);
++AuRWLockFuncs(parent3, PARENT3);
++AuRWLockFuncs(parent4, PARENT4);
++AuRWLockFuncs(new_child, NEW_CHILD);
++
++#undef AuReadLockFunc
++#undef AuWriteLockFunc
++#undef AuRWLockFuncs
++
++/*
++ * ii_read_unlock, ii_write_unlock, ii_downgrade_lock
++ */
++AuSimpleUnlockRwsemFuncs(ii_do, struct inode *i, au_ii(i)->ii_rwsem);
++static inline void ii_read_unlock(struct inode *i)
++{
++ ii_do_read_unlock(i);
++ au_dbg_locked_ii_unreg(i, 0);
++}
++
++static inline void ii_write_unlock(struct inode *i)
++{
++ ii_do_write_unlock(i);
++ au_dbg_locked_ii_unreg(i, 0);
++}
++
++static inline void ii_downgrade_lock(struct inode *i)
++{
++ ii_do_downgrade_lock(i);
++}
++
++/* to debug easier, do not make them inlined functions */
++#define IiMustReadLock(i) do { \
++ SiMustAnyLock((i)->i_sb); \
++ AuRwMustReadLock(&au_ii(i)->ii_rwsem); \
++} while (0)
++
++#define IiMustWriteLock(i) do { \
++ SiMustAnyLock((i)->i_sb); \
++ AuRwMustWriteLock(&au_ii(i)->ii_rwsem); \
++} while (0)
++
++#define IiMustAnyLock(i) do { \
++ SiMustAnyLock((i)->i_sb); \
++ AuRwMustAnyLock(&au_ii(i)->ii_rwsem); \
++} while (0)
++
++#define IiMustNoWaiters(i) AuRwMustNoWaiters(&au_ii(i)->ii_rwsem)
++
++/* ---------------------------------------------------------------------- */
++
++static inline struct inode *au_igrab(struct inode *inode)
++{
++ if (inode) {
++ AuDebugOn(!atomic_read(&inode->i_count));
++ atomic_inc_return(&inode->i_count);
++ }
++ return inode;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static inline aufs_bindex_t au_ibstart(struct inode *inode)
++{
++ /* lock free root dinfo/inode */
++ if (inode->i_ino != AUFS_ROOT_INO)
++ IiMustAnyLock(inode);
++ else
++ SiMustAnyLock(inode->i_sb);
++ return au_ii(inode)->ii_bstart;
++}
++
++static inline aufs_bindex_t au_ibend(struct inode *inode)
++{
++ /* lock free root dinfo/inode */
++ if (inode->i_ino != AUFS_ROOT_INO)
++ IiMustAnyLock(inode);
++ else
++ SiMustAnyLock(inode->i_sb);
++ return au_ii(inode)->ii_bend;
++}
++
++static inline struct au_vdir *au_ivdir(struct inode *inode)
++{
++ IiMustAnyLock(inode);
++ AuDebugOn(!S_ISDIR(inode->i_mode));
++ return au_ii(inode)->ii_vdir;
++}
++
++static inline struct dentry *au_hi_wh(struct inode *inode, aufs_bindex_t bindex)
++{
++ struct au_hinode *hinode;
++ IiMustAnyLock(inode);
++ hinode = au_ii(inode)->ii_hinode + bindex;
++ return hinode->hi_whdentry;
++}
++
++static inline void au_set_ibend(struct inode *inode, aufs_bindex_t bindex)
++{
++ IiMustWriteLock(inode);
++ AuDebugOn(au_sbend(inode->i_sb) < bindex || bindex < au_ibstart(inode));
++ au_ii(inode)->ii_bend = bindex;
++}
++
++static inline void au_set_ivdir(struct inode *inode, struct au_vdir *vdir)
++{
++ IiMustWriteLock(inode);
++ AuDebugOn(!S_ISDIR(inode->i_mode) || (au_ii(inode)->ii_vdir && vdir));
++ au_ii(inode)->ii_vdir = vdir;
++}
++
++static inline void au_hiput(struct au_hinode *hinode)
++{
++ au_hin_free(hinode);
++ dput(hinode->hi_whdentry);
++ iput(hinode->hi_inode);
++}
++
++static inline struct au_hinode *au_hi(struct inode *inode, aufs_bindex_t bindex)
++{
++ /* todo: this lock check causes some unnecessary locks in callers. */
++ IiMustAnyLock(inode);
++ return au_ii(inode)->ii_hinode + bindex;
++}
++
++/* tiny test for inode number */
++/* tmpfs generation is too rough */
++static inline int au_test_higen(struct inode *inode, struct inode *h_inode)
++{
++ struct au_iinfo *iinfo;
++
++ IiMustAnyLock(inode);
++
++ iinfo = au_ii(inode);
++ return !(iinfo->ii_hsb1 == h_inode->i_sb
++ && iinfo->ii_higen == h_inode->i_generation);
++}
++
++static inline au_gen_t au_iigen(struct inode *inode)
++{
++ return atomic_read(&au_ii(inode)->ii_generation);
++}
++
++#ifdef CONFIG_AUFS_HINOTIFY
++static inline au_gen_t au_iigen_dec(struct inode *inode)
++{
++ /* AuDbg("i%lu\n", inode->i_ino); */
++ return atomic_dec_return(&au_ii(inode)->ii_generation);
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_HINOTIFY
++static inline struct au_pin1 *au_pin_gp(struct au_pin *args)
++{
++ return args->pin + AuPin_GPARENT;
++}
++
++/* hinotify.c */
++void au_unpin_gp(struct au_pin *args);
++
++#else
++
++static inline struct au_pin1 *au_pin_gp(struct au_pin *args)
++{
++ return NULL;
++}
++
++static inline void au_unpin_gp(struct au_pin *args)
++{
++ /* empty */
++}
++#endif /* HINOTIFY */
++
++static inline void au_unpin(struct au_pin *args)
++{
++ au_do_unpin(args->pin + AuPin_PARENT, au_pin_gp(args));
++}
++
++static inline
++struct au_hinode *au_do_pinned_hdir(struct au_pin1 *pin)
++{
++ if (pin && pin->parent)
++ return au_hi(pin->parent->d_inode, pin->bindex);
++ return NULL;
++}
++
++struct dentry *au_do_pinned_h_parent(struct au_pin1 *pin);
++
++static inline struct dentry *au_do_pinned_parent(struct au_pin1 *pin)
++{
++ if (pin)
++ return pin->parent;
++ return NULL;
++}
++
++static inline struct inode *au_do_pinned_h_dir(struct au_pin1 *pin)
++{
++ if (pin)
++ return pin->h_dir;
++ return NULL;
++}
++
++static inline
++void au_pin_do_set_dentry(struct au_pin1 *pin, struct dentry *dentry)
++{
++ if (pin)
++ pin->dentry = dentry;
++}
++
++static inline
++void au_pin_do_set_parent(struct au_pin1 *pin, struct dentry *parent)
++{
++ if (pin) {
++ dput(pin->parent);
++ pin->parent = dget(parent);
++ }
++}
++
++static inline void au_pin_do_set_h_dir(struct au_pin1 *pin, struct inode *h_dir)
++{
++ if (pin) {
++ iput(pin->h_dir);
++ pin->h_dir = au_igrab(h_dir);
++ }
++}
++
++static inline
++void au_pin_do_set_parent_lflag(struct au_pin1 *pin, unsigned char lflag)
++{
++ if (pin) {
++ /* dirty macros require brackets */
++ if (lflag) {
++ au_fset_pin(pin->flags, DI_LOCKED);
++ } else {
++ au_fclr_pin(pin->flags, DI_LOCKED);
++ }
++ }
++}
++
++static inline
++struct au_hinode *au_pinned_hdir(struct au_pin *args)
++{
++ return au_do_pinned_hdir(args->pin + AuPin_PARENT);
++}
++
++static inline
++struct au_hinode *au_pinned_hgdir(struct au_pin *args)
++{
++ return au_do_pinned_hdir(au_pin_gp(args));
++}
++
++static inline
++struct dentry *au_pinned_h_parent(struct au_pin *args)
++{
++ return au_do_pinned_h_parent(args->pin + AuPin_PARENT);
++}
++
++#if 0 /* reserved for future use */
++static inline
++struct dentry *au_pinned_h_gparent(struct au_pin *args)
++{
++ return au_do_pinned_h_parent(au_pin_gp(args));
++}
++#endif
++
++static inline
++struct dentry *au_pinned_parent(struct au_pin *args)
++{
++ return au_do_pinned_parent(args->pin + AuPin_PARENT);
++}
++
++static inline
++struct dentry *au_pinned_gparent(struct au_pin *args)
++{
++ return au_do_pinned_parent(au_pin_gp(args));
++}
++
++static inline
++struct inode *au_pinned_h_dir(struct au_pin *args)
++{
++ return au_do_pinned_h_dir(args->pin + AuPin_PARENT);
++}
++
++static inline
++struct inode *au_pinned_h_gdir(struct au_pin *args)
++{
++ return au_do_pinned_h_dir(au_pin_gp(args));
++}
++
++static inline void au_pin_set_parent(struct au_pin *args, struct dentry *d)
++{
++ au_pin_do_set_parent(args->pin + AuPin_PARENT, d);
++}
++
++static inline void au_pin_set_gparent(struct au_pin *args, struct dentry *d)
++{
++ au_pin_do_set_parent(au_pin_gp(args), d);
++}
++
++static inline void au_pin_set_h_dir(struct au_pin *args, struct inode *h_dir)
++{
++ au_pin_do_set_h_dir(args->pin + AuPin_PARENT, h_dir);
++}
++
++static inline void au_pin_set_h_gdir(struct au_pin *args, struct inode *h_dir)
++{
++ au_pin_do_set_h_dir(au_pin_gp(args), h_dir);
++}
++
++static inline
++void au_pin_set_parent_lflag(struct au_pin *args, unsigned char lflag)
++{
++ au_pin_do_set_parent_lflag(args->pin + AuPin_PARENT, lflag);
++}
++
++static inline
++void au_pin_set_gparent_lflag(struct au_pin *args, unsigned char lflag)
++{
++ au_pin_do_set_parent_lflag(au_pin_gp(args), lflag);
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_INODE_H__ */
+diff --git a/fs/aufs/misc.c b/fs/aufs/misc.c
+new file mode 100644
+index 0000000..7caf178
+--- /dev/null
++++ b/fs/aufs/misc.c
+@@ -0,0 +1,325 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * $Id: misc.c,v 1.65 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++void *au_kzrealloc(void *p, unsigned int nused, unsigned int new_sz, gfp_t gfp)
++{
++ void *q;
++
++ LKTRTrace("p %p, nused %d, sz %d\n", p, nused, new_sz);
++ AuDebugOn(new_sz <= 0);
++ if (new_sz <= nused)
++ return p;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++ q = krealloc(p, new_sz, gfp);
++ if (q)
++ memset(q + nused, 0, new_sz - nused);
++ return q;
++#else
++ LKTRTrace("ksize %d\n", ksize(p));
++ if (new_sz <= ksize(p)) {
++ memset(p + nused, 0, new_sz - nused);
++ return p;
++ }
++
++ q = kmalloc(new_sz, gfp);
++ //q = NULL;
++ if (unlikely(!q))
++ return NULL;
++ memcpy(q, p, nused);
++ memset(q + nused, 0, new_sz - nused);
++ //smp_mb();
++ kfree(p);
++ return q;
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) */
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct nameidata *au_dup_nd(struct au_sbinfo *sbinfo, struct nameidata *dst,
++ struct nameidata *src)
++{
++ LKTRTrace("src %p\n", src);
++
++ if (src) {
++ *dst = *src;
++ dst->flags &= ~LOOKUP_PARENT;
++ if (sbinfo->si_wbr_create == AuWbrCreate_TDP) {
++ if ((dst->flags & LOOKUP_CREATE)
++ && !(dst->intent.open.flags & O_CREAT))
++ dst->flags &= ~LOOKUP_CREATE;
++ } else {
++ dst->flags &= ~LOOKUP_CREATE;
++ dst->intent.open.flags &= ~O_CREAT;
++ }
++ } else
++ dst = NULL;
++
++ return dst;
++}
++
++struct nameidata *au_fake_dm(struct nameidata *fake_nd, struct nameidata *nd,
++ struct super_block *sb, aufs_bindex_t bindex)
++{
++ LKTRTrace("nd %p, b%d\n", nd, bindex);
++
++ if (!nd)
++ return NULL;
++
++ DiMustAnyLock(nd->dentry);
++
++ fake_nd->dentry = NULL;
++ fake_nd->mnt = NULL;
++
++ if (bindex <= au_dbend(nd->dentry))
++ fake_nd->dentry = au_h_dptr(nd->dentry, bindex);
++ if (fake_nd->dentry) {
++ dget(fake_nd->dentry);
++ fake_nd->mnt = au_sbr_mnt(sb, bindex);
++ AuDebugOn(!fake_nd->mnt);
++ mntget(fake_nd->mnt);
++ } else
++ fake_nd = ERR_PTR(-ENOENT);
++
++ AuTraceErrPtr(fake_nd);
++ return fake_nd;
++}
++
++void au_fake_dm_release(struct nameidata *fake_nd)
++{
++ if (fake_nd)
++ path_release(fake_nd);
++}
++
++int au_h_create(struct inode *h_dir, struct dentry *h_dentry, int mode,
++ struct vfsub_args *vargs, struct nameidata *nd,
++ struct vfsmount *nfsmnt)
++{
++ int err;
++
++ LKTRTrace("hi%lu, %.*s, 0%o, nd %d, nfsmnt %d\n",
++ h_dir->i_ino, AuDLNPair(h_dentry), mode, !!nd, !!nfsmnt);
++
++ err = -ENOSYS;
++ if (!nfsmnt)
++ err = vfsub_create(h_dir, h_dentry, mode, /*nd*/NULL, vargs);
++ else {
++ struct nameidata fake_nd;
++
++ if (nd)
++ fake_nd = *nd;
++ else
++ memset(&fake_nd, 0, sizeof(fake_nd));
++ fake_nd.dentry = dget(h_dentry);
++ fake_nd.mnt = mntget(nfsmnt);
++ fake_nd.flags = LOOKUP_CREATE;
++ fake_nd.intent.open.flags = O_CREAT | FMODE_READ;
++ fake_nd.intent.open.create_mode = mode;
++
++ err = vfsub_create(h_dir, h_dentry, mode, &fake_nd, vargs);
++ path_release(&fake_nd);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* empty_zero_page is not exported before 2.6.24 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static char *au_zp_alloc(void)
++{
++ return page_address(ZERO_PAGE(0));
++}
++
++static void au_zp_free(char *p)
++{
++ /* empty */
++}
++#else
++static char *au_zp_alloc(void)
++{
++ return (void *)get_zeroed_page(GFP_NOFS);
++}
++
++static void au_zp_free(char *p)
++{
++ if (p)
++ free_page((unsigned long)p);
++}
++#endif
++
++int au_copy_file(struct file *dst, struct file *src, loff_t len,
++ struct au_hinode *hdir, struct super_block *sb,
++ struct vfsub_args *vargs)
++{
++ int err, all_zero, do_kfree;
++ unsigned long blksize;
++ char *buf, *zp;
++ /* reduce stack usage */
++ struct iattr *ia;
++
++ LKTRTrace("%.*s, %.*s\n",
++ AuDLNPair(dst->f_dentry), AuDLNPair(src->f_dentry));
++ AuDebugOn(!(dst->f_mode & FMODE_WRITE));
++#ifdef CONFIG_AUFS_DEBUG
++ {
++ struct dentry *parent;
++ parent = dget_parent(dst->f_dentry);
++ IMustLock(parent->d_inode);
++ dput(parent);
++ }
++#endif
++
++ err = -ENOMEM;
++ zp = au_zp_alloc();
++ if (unlikely(!zp))
++ goto out;
++ blksize = dst->f_dentry->d_sb->s_blocksize;
++ if (!blksize || PAGE_SIZE < blksize)
++ blksize = PAGE_SIZE;
++ LKTRTrace("blksize %lu\n", blksize);
++ do_kfree = (blksize != PAGE_SIZE && blksize >= sizeof(*ia));
++ if (do_kfree)
++ buf = kmalloc(blksize, GFP_NOFS);
++ else
++ buf = (void *)__get_free_page(GFP_NOFS);
++ if (unlikely(!buf))
++ goto out;
++
++#ifdef CONFIG_AUFS_DEBUG
++ if (len > (1 << 22))
++ AuWarn("copying a large file %lld\n", (long long)len);
++#endif
++ err = 0;
++ all_zero = 0;
++ src->f_pos = 0;
++ dst->f_pos = 0;
++ while (len) {
++ size_t sz, rbytes, wbytes;
++ char *p;
++
++ LKTRTrace("len %lld\n", len);
++ sz = blksize;
++ if (len < blksize)
++ sz = len;
++
++ /* support LSM and notify */
++ rbytes = 0;
++ /* todo: signal_pending? */
++ while (!rbytes || err == -EAGAIN || err == -EINTR) {
++ rbytes = vfsub_read_k(src, buf, sz, &src->f_pos,
++ vfsub_ftest(vargs->flags, DLGT));
++ err = rbytes;
++ }
++ if (unlikely(err < 0))
++ break;
++
++ all_zero = 0;
++ if (len >= rbytes && rbytes == blksize) {
++#if 1
++ all_zero = !memcmp(buf, zp, rbytes);
++#else /* reserved for future use */
++ unsigned long long *ullp;
++ size_t n, i;
++
++ all_zero = 1;
++ ullp = (void *)buf;
++ n = rbytes / sizeof(*ullp);
++ i = n;
++ while (n-- > 0 && all_zero)
++ all_zero = !*ullp++;
++ p = (void *)ullp;
++ i *= sizeof(*ullp);
++ for (; all_zero && i < rbytes; i++)
++ all_zero = !*p++;
++#endif
++ }
++ if (!all_zero) {
++ wbytes = rbytes;
++ p = buf;
++ while (wbytes) {
++ size_t b;
++ /* support LSM and notify */
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_MODIFY, hdir);
++ b = vfsub_write_k(dst, p, wbytes, &dst->f_pos,
++ vargs);
++ err = b;
++ /* todo: signal_pending? */
++ if (unlikely(err == -EAGAIN || err == -EINTR))
++ continue;
++ if (unlikely(err < 0))
++ break;
++ wbytes -= b;
++ p += b;
++ }
++ } else {
++ loff_t res;
++ LKTRLabel(hole);
++ res = vfsub_llseek(dst, rbytes, SEEK_CUR);
++ err = res;
++ if (unlikely(res < 0))
++ break;
++ }
++ len -= rbytes;
++ err = 0;
++ }
++
++ /* the last block may be a hole */
++ if (!err && all_zero) {
++ struct dentry *h_d = dst->f_dentry;
++ struct inode *h_i = h_d->d_inode;
++
++ LKTRLabel(last hole);
++ do {
++ /* todo: signal_pending? */
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_MODIFY, hdir);
++ err = vfsub_write_k(dst, "\0", 1, &dst->f_pos, vargs);
++ } while (err == -EAGAIN || err == -EINTR);
++ if (err == 1) {
++ ia = (void *)buf;
++ ia->ia_size = dst->f_pos;
++ ia->ia_valid = ATTR_SIZE | ATTR_FILE;
++ ia->ia_file = dst;
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, vfsub_events_notify_change(ia),
++ hdir);
++ vfsub_i_lock_nested(h_i, AuLsc_I_CHILD2);
++ err = vfsub_notify_change(h_d, ia, vargs);
++ vfsub_i_unlock(h_i);
++ }
++ }
++ if (do_kfree)
++ kfree(buf);
++ else
++ free_page((unsigned long)buf);
++
++ out:
++ au_zp_free(zp);
++ AuTraceErr(err);
++ return err;
++}
+diff --git a/fs/aufs/misc.h b/fs/aufs/misc.h
+new file mode 100644
+index 0000000..d50bed1
+--- /dev/null
++++ b/fs/aufs/misc.h
+@@ -0,0 +1,244 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * $Id: misc.h,v 1.50 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_MISC_H__
++#define __AUFS_MISC_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/namei.h>
++#include <linux/version.h>
++#include <linux/aufs_type.h>
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#define I_MUTEX_QUOTA 0
++#define lockdep_off() do {} while (0)
++#define lockdep_on() do {} while (0)
++#define mutex_lock_nested(mtx, lsc) mutex_lock(mtx)
++#define down_write_nested(rw, lsc) down_write(rw)
++#define down_read_nested(rw, lsc) down_read(rw)
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++typedef unsigned int au_gen_t;
++/* see linux/include/linux/jiffies.h */
++#define AuGenYounger(a, b) ((int)(b) - (int)(a) < 0)
++#define AuGenOlder(a, b) AufsGenYounger(b, a)
++
++/* ---------------------------------------------------------------------- */
++
++struct au_splhead {
++ spinlock_t spin;
++ struct list_head head;
++};
++
++static inline void au_spl_init(struct au_splhead *spl)
++{
++ spin_lock_init(&spl->spin);
++ INIT_LIST_HEAD(&spl->head);
++}
++
++static inline void au_spl_add(struct list_head *list, struct au_splhead *spl)
++{
++ spin_lock(&spl->spin);
++ list_add(list, &spl->head);
++ spin_unlock(&spl->spin);
++}
++
++static inline void au_spl_del(struct list_head *list, struct au_splhead *spl)
++{
++ spin_lock(&spl->spin);
++ list_del(list);
++ spin_unlock(&spl->spin);
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct au_rwsem {
++ struct rw_semaphore rwsem;
++#ifdef CONFIG_AUFS_DEBUG
++ atomic_t rcnt;
++#endif
++};
++
++#ifdef CONFIG_AUFS_DEBUG
++#define AuDbgRcntInit(rw) do { \
++ atomic_set(&(rw)->rcnt, 0); \
++ smp_mb(); /* atomic set */ \
++} while (0)
++
++#define AuDbgRcntInc(rw) atomic_inc_return(&(rw)->rcnt)
++#define AuDbgRcntDec(rw) WARN_ON(atomic_dec_return(&(rw)->rcnt) < 0)
++#else
++#define AuDbgRcntInit(rw) do {} while (0)
++#define AuDbgRcntInc(rw) do {} while (0)
++#define AuDbgRcntDec(rw) do {} while (0)
++#endif /* CONFIG_AUFS_DEBUG */
++
++#define au_rwsem_destroy(rw) AuDebugOn(rwsem_is_locked(&(rw)->rwsem))
++
++static inline void au_rw_init_nolock(struct au_rwsem *rw)
++{
++ AuDbgRcntInit(rw);
++ init_rwsem(&rw->rwsem);
++}
++
++static inline void au_rw_init_wlock(struct au_rwsem *rw)
++{
++ au_rw_init_nolock(rw);
++ down_write(&rw->rwsem);
++}
++
++static inline void au_rw_init_wlock_nested(struct au_rwsem *rw,
++ unsigned int lsc)
++{
++ au_rw_init_nolock(rw);
++ down_write_nested(&rw->rwsem, lsc);
++}
++
++static inline void au_rw_read_lock(struct au_rwsem *rw)
++{
++ down_read(&rw->rwsem);
++ AuDbgRcntInc(rw);
++}
++
++static inline void au_rw_read_lock_nested(struct au_rwsem *rw, unsigned int lsc)
++{
++ down_read_nested(&rw->rwsem, lsc);
++ AuDbgRcntInc(rw);
++}
++
++static inline void au_rw_read_unlock(struct au_rwsem *rw)
++{
++ AuDbgRcntDec(rw);
++ up_read(&rw->rwsem);
++}
++
++static inline void au_rw_dgrade_lock(struct au_rwsem *rw)
++{
++ AuDbgRcntInc(rw);
++ downgrade_write(&rw->rwsem);
++}
++
++static inline void au_rw_write_lock(struct au_rwsem *rw)
++{
++ down_write(&rw->rwsem);
++}
++
++static inline void au_rw_write_lock_nested(struct au_rwsem *rw,
++ unsigned int lsc)
++{
++ down_write_nested(&rw->rwsem, lsc);
++}
++
++static inline void au_rw_write_unlock(struct au_rwsem *rw)
++{
++ up_write(&rw->rwsem);
++}
++
++/* why is not _nested version defined */
++static inline int au_rw_read_trylock(struct au_rwsem *rw)
++{
++ int ret = down_read_trylock(&rw->rwsem);
++ if (ret)
++ AuDbgRcntInc(rw);
++ return ret;
++}
++
++static inline int au_rw_write_trylock(struct au_rwsem *rw)
++{
++ return down_write_trylock(&rw->rwsem);
++}
++
++#undef AuDbgRcntInit
++#undef AuDbgRcntInc
++#undef AuDbgRcntDec
++
++/* to debug easier, do not make them inlined functions */
++#define AuRwMustNoWaiters(rw) AuDebugOn(!list_empty(&(rw)->rwsem.wait_list))
++#define AuRwMustAnyLock(rw) AuDebugOn(down_write_trylock(&(rw)->rwsem))
++#ifdef CONFIG_AUFS_DEBUG
++#define AuRwMustReadLock(rw) do { \
++ AuRwMustAnyLock(rw); \
++ AuDebugOn(!atomic_read(&(rw)->rcnt)); \
++} while (0)
++
++#define AuRwMustWriteLock(rw) do { \
++ AuRwMustAnyLock(rw); \
++ AuDebugOn(atomic_read(&(rw)->rcnt)); \
++} while (0)
++#else
++#define AuRwMustReadLock(rw) AuRwMustAnyLock(rw)
++#define AuRwMustWriteLock(rw) AuRwMustAnyLock(rw)
++#endif /* CONFIG_AUFS_DEBUG */
++
++#define AuSimpleLockRwsemFuncs(prefix, param, rwsem) \
++static inline void prefix##_read_lock(param) \
++{ au_rw_read_lock(&(rwsem)); } \
++static inline void prefix##_write_lock(param) \
++{ au_rw_write_lock(&(rwsem)); } \
++static inline int prefix##_read_trylock(param) \
++{ return au_rw_read_trylock(&(rwsem)); } \
++static inline int prefix##_write_trylock(param) \
++{ return au_rw_write_trylock(&(rwsem)); }
++/* static inline void prefix##_read_trylock_nested(param, lsc)
++{au_rw_read_trylock_nested(&(rwsem, lsc));}
++static inline void prefix##_write_trylock_nestd(param, lsc)
++{au_rw_write_trylock_nested(&(rwsem), nested);} */
++
++#define AuSimpleUnlockRwsemFuncs(prefix, param, rwsem) \
++static inline void prefix##_read_unlock(param) \
++{ au_rw_read_unlock(&(rwsem)); } \
++static inline void prefix##_write_unlock(param) \
++{ au_rw_write_unlock(&(rwsem)); } \
++static inline void prefix##_downgrade_lock(param) \
++{ au_rw_dgrade_lock(&(rwsem)); }
++
++#define AuSimpleRwsemFuncs(prefix, param, rwsem) \
++ AuSimpleLockRwsemFuncs(prefix, param, rwsem) \
++ AuSimpleUnlockRwsemFuncs(prefix, param, rwsem)
++
++/* ---------------------------------------------------------------------- */
++
++void *au_kzrealloc(void *p, unsigned int nused, unsigned int new_sz, gfp_t gfp);
++
++struct au_sbinfo;
++struct nameidata *au_dup_nd(struct au_sbinfo *sbinfo, struct nameidata *dst,
++ struct nameidata *src);
++
++struct nameidata *au_fake_dm(struct nameidata *fake_nd, struct nameidata *nd,
++ struct super_block *sb, aufs_bindex_t bindex);
++void au_fake_dm_release(struct nameidata *fake_nd);
++struct vfsub_args;
++int au_h_create(struct inode *h_dir, struct dentry *h_dentry, int mode,
++ struct vfsub_args *vargs, struct nameidata *nd,
++ struct vfsmount *nfsmnt);
++
++struct au_hinode;
++int au_copy_file(struct file *dst, struct file *src, loff_t len,
++ struct au_hinode *hdir, struct super_block *sb,
++ struct vfsub_args *vargs);
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_MISC_H__ */
+diff --git a/fs/aufs/module.c b/fs/aufs/module.c
+new file mode 100644
+index 0000000..030fa3b
+--- /dev/null
++++ b/fs/aufs/module.c
+@@ -0,0 +1,295 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * module global variables and operations
++ *
++ * $Id: module.c,v 1.38 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/module.h>
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * aufs caches
++ */
++struct kmem_cache *au_cachep[AuCache_Last];
++static int __init create_cache(void)
++{
++ au_cachep[AuCache_DINFO] = AuCache(au_dinfo);
++ if (au_cachep[AuCache_DINFO])
++ au_cachep[AuCache_ICNTNR] = AuCache(aufs_icntnr);
++ if (au_cachep[AuCache_ICNTNR])
++ au_cachep[AuCache_FINFO] = AuCache(au_finfo);
++ //au_cachep[AuCache_FINFO] = NULL;
++ if (au_cachep[AuCache_FINFO])
++ au_cachep[AuCache_VDIR] = AuCache(au_vdir);
++ if (au_cachep[AuCache_VDIR])
++ au_cachep[AuCache_DEHSTR] = AuCache(au_vdir_dehstr);
++ if (au_cachep[AuCache_DEHSTR])
++ return 0;
++
++ return -ENOMEM;
++}
++
++static void destroy_cache(void)
++{
++ int i;
++ for (i = 0; i < AuCache_Last; i++)
++ if (au_cachep[i]) {
++ kmem_cache_destroy(au_cachep[i]);
++ au_cachep[i] = NULL;
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++char au_esc_chars[0x20 + 3]; /* 0x01-0x20, backslash, del, and NULL */
++int au_dir_roflags;
++
++/*
++ * functions for module interface.
++ */
++MODULE_LICENSE("GPL");
++/* MODULE_LICENSE("GPL v2"); */
++MODULE_AUTHOR("Junjiro Okajima");
++MODULE_DESCRIPTION(AUFS_NAME " -- Another unionfs");
++MODULE_VERSION(AUFS_VERSION);
++
++/* it should be 'byte', but param_set_byte() prints it by "%c" */
++short aufs_nwkq = AUFS_NWKQ_DEF;
++MODULE_PARM_DESC(nwkq, "the number of workqueue thread, " AUFS_WKQ_NAME);
++module_param_named(nwkq, aufs_nwkq, short, S_IRUGO);
++
++int sysaufs_brs;
++MODULE_PARM_DESC(brs, "use <sysfs>/fs/aufs/sbi_*/brN");
++module_param_named(brs, sysaufs_brs, int, S_IRUGO);
++
++/* ---------------------------------------------------------------------- */
++
++static int __init aufs_init(void)
++{
++ int err, i;
++ char *p;
++
++ au_debug_init();
++#ifdef CONFIG_AUFS_INO_T_64
++ BUILD_BUG_ON(sizeof(ino_t) != sizeof(long long));
++#else
++ BUILD_BUG_ON(sizeof(ino_t) != sizeof(int));
++#endif
++
++ p = au_esc_chars;
++ for (i = 1; i <= ' '; i++)
++ *p++ = i;
++ *p++ = '\\';
++ *p++ = '\x7f';
++ *p = 0;
++
++ au_dir_roflags = au_file_roflags(O_DIRECTORY | O_LARGEFILE);
++
++ err = -EINVAL;
++ if (unlikely(aufs_nwkq <= 0))
++ goto out;
++
++ err = sysaufs_init();
++ if (unlikely(err))
++ goto out;
++ err = au_wkq_init();
++ if (unlikely(err))
++ goto out_sysaufs;
++ err = au_inotify_init();
++ if (unlikely(err))
++ goto out_wkq;
++ err = au_sysrq_init();
++ if (unlikely(err))
++ goto out_inotify;
++
++ err = create_cache();
++ if (unlikely(err))
++ goto out_sysrq;
++
++ err = register_filesystem(&aufs_fs_type);
++ if (unlikely(err))
++ goto out_cache;
++ pr_info(AUFS_NAME " " AUFS_VERSION "\n");
++ return 0; /* success */
++
++ out_cache:
++ destroy_cache();
++ out_sysrq:
++ au_sysrq_fin();
++ out_inotify:
++ au_inotify_fin();
++ out_wkq:
++ au_wkq_fin();
++ out_sysaufs:
++ sysaufs_fin();
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static void __exit aufs_exit(void)
++{
++ unregister_filesystem(&aufs_fs_type);
++ destroy_cache();
++
++ au_sysrq_fin();
++ au_inotify_fin();
++ au_wkq_fin();
++ sysaufs_fin();
++}
++
++module_init(aufs_init);
++module_exit(aufs_exit);
++
++/* ---------------------------------------------------------------------- */
++
++/* fake Kconfig */
++#if 1
++
++#if AUFS_BRANCH_MAX > 511 && PAGE_SIZE > 4096
++#warning pagesize is larger than 4kb, \
++ CONFIG_AUFS_BRANCH_MAX_511 or smaller is recommended.
++#endif
++
++#ifdef CONFIG_AUFS_SYSAUFS
++#ifndef CONFIG_SYSFS
++#error CONFIG_AUFS_SYSAUFS requires CONFIG_SYSFS.
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#error CONFIG_AUFS_SYSAUFS requires linux-2.6.18 and later.
++#endif
++#endif /* CONFIG_AUFS_SYSAUFS */
++
++#ifdef CONFIG_AUFS_HINOTIFY
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#error CONFIG_AUFS_HINOTIFY is supported in linux-2.6.18 and later.
++#endif
++#ifndef CONFIG_INOTIFY
++#error enable CONFIG_INOTIFY to use CONFIG_AUFS_HINOTIFY.
++#endif
++#endif /* CONFIG_AUFS_HINOTIFY */
++
++#ifdef CONFIG_AUFS_EXPORT
++#if !defined(CONFIG_EXPORTFS) && !defined(CONFIG_EXPORTFS_MODULE)
++#error CONFIG_AUFS_EXPORT requires CONFIG_EXPORTFS
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#error CONFIG_AUFS_EXPORT requires linux-2.6.18 and later.
++#endif
++#if defined(CONFIG_EXPORTFS_MODULE) && defined(CONFIG_AUFS)
++#error need CONFIG_EXPORTFS = y to link aufs statically with CONFIG_AUFS_EXPORT
++#endif
++#endif /* CONFIG_AUFS_EXPORT */
++
++#ifdef CONFIG_AUFS_SEC_PERM_PATCH
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
++#warning CONFIG_AUFS_SEC_PERM_PATCH does not support before linux-2.6.24.
++#endif
++#ifndef CONFIG_SECURITY
++#warning AUFS_SEC_PERM_PATCH is unnecessary since SECURITY is disabled.
++#endif
++#ifdef CONFIG_AUFS
++#warning AUFS_SEC_PERM_PATCH is unnecessary since AUFS is not a module.
++#endif
++#endif
++
++#if defined(CONFIG_AUFS_SPLICE_PATCH) \
++ && LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 23)
++#error CONFIG_AUFS_SPLICE_PATCH is supported linux-2.6.23 and later.
++#endif
++
++#ifdef CONFIG_AUFS_LHASH_PATCH
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)
++#error CONFIG_AUFS_LHASH_PATCH does not support before linux-2.6.19.
++#endif
++#if !defined(CONFIG_NFS_FS) && !defined(CONFIG_NFS_FS_MODULE)
++#warning CONFIG_AUFS_LHASH_PATCH is unnecessary since CONFIG_NFS_FS is disabled.
++#endif
++#endif
++
++#ifdef CONFIG_AUFS_PUT_FILP_PATCH
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)
++#warning CONFIG_AUFS_PUT_FILP_PATCH does not support before linux-2.6.19.
++#endif
++#ifndef CONFIG_NFS_V4
++#warning AUFS_PUT_FILP_PATCH is unnecessary since NFS_V4 is disabled.
++#endif
++#ifdef CONFIG_AUFS
++#warning AUFS_PUT_FILP_PATCH is unnecessary since AUFS is not a module.
++#endif
++#endif /* CONFIG_AUFS_PUT_FILP_PATCH */
++
++#ifdef CONFIG_AUFS_FSYNC_SUPER_PATCH
++#ifdef CONFIG_AUFS
++#warning AUFS_FSYNC_SUPER_PATCH is unnecessary since AUFS is not a module.
++#endif
++#endif
++
++#ifdef CONFIG_DENY_WRITE_ACCESS_PATCH
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17)
++#warning AUFS_DENY_WRITE_ACCESS_PATCH is supported in linux-2.6.17 and later.
++#endif
++#ifdef CONFIG_AUFS
++#warning AUFS_DENY_WRITE_ACCESS_PATCH is unnecessary since AUFS is not a module.
++#endif
++#endif
++
++#ifdef CONFIG_AUFS_KSIZE_PATCH
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++#warning CONFIG_AUFS_KSIZE_PATCH is unnecessary for linux-2.6.22 and later.
++#endif
++#ifdef CONFIG_AUFS
++#warning CONFIG_AUFS_KSIZE_PATCH is unnecessary since AUFS is not a module.
++#endif
++#endif
++
++#ifdef CONFIG_AUFS_WORKAROUND_FUSE
++#if !defined(CONFIG_FUSE_FS) && !defined(CONFIG_FUSE_FS_MODULE)
++#warning CONFIG_AUFS_WORKAROUND_FUSE is enabled while FUSE is disabled.
++#endif
++#endif
++
++#ifdef CONFIG_AUFS_DEBUG_LOCK
++#ifndef CONFIG_AUFS_MAGIC_SYSRQ
++#warning CONFIG_AUFS_DEBUG_LOCK is enabled but CONFIG_AUFS_MAGIC_SYSRQ.
++#endif
++#endif
++
++#ifdef CONFIG_AUFS_COMPAT
++#warning CONFIG_AUFS_COMPAT will be removed in the near future.
++#endif
++
++#ifdef CONFIG_AUFS_UNIONFS23_PATCH
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23) \
++ && !defined(CONFIG_AUFS_SPLICE_PATCH)
++#error mis-config. AUFS_UNIONFS23_PATCH is enabled but AUFS_SPLICE_PATCH.
++#endif
++#endif
++
++#ifdef CONFIG_DEBUG_PROVE_LOCKING
++#if MAX_LOCKDEP_SUBCLASSES < AuLsc_I_End
++#warning lockdep will not work since aufs uses deeper locks.
++#endif
++#endif
++
++#endif
+diff --git a/fs/aufs/module.h b/fs/aufs/module.h
+new file mode 100644
+index 0000000..6fc1a1a
+--- /dev/null
++++ b/fs/aufs/module.h
+@@ -0,0 +1,81 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * module initialization and module-global
++ *
++ * $Id: module.h,v 1.22 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_MODULE_H__
++#define __AUFS_MODULE_H__
++
++#ifdef __KERNEL__
++
++#include <linux/slab.h>
++
++/* ---------------------------------------------------------------------- */
++
++/* module parameters */
++extern short aufs_nwkq;
++extern int sysaufs_brs;
++
++/* ---------------------------------------------------------------------- */
++
++extern char au_esc_chars[];
++extern int au_dir_roflags;
++
++/* kmem cache */
++enum {
++ AuCache_DINFO,
++ AuCache_ICNTNR,
++ AuCache_FINFO,
++ AuCache_VDIR,
++ AuCache_DEHSTR,
++#ifdef CONFIG_AUFS_HINOTIFY
++ AuCache_HINOTIFY,
++#endif
++ AuCache_Last
++};
++
++extern struct kmem_cache *au_cachep[];
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++#define AuCacheArgs(type, sz) (type), (sz), 0, SLAB_RECLAIM_ACCOUNT, NULL
++#else
++#define AuCacheArgs(type, sz) (type), (sz), 0, SLAB_RECLAIM_ACCOUNT, NULL, NULL
++#endif
++#define AuCache(type) \
++ kmem_cache_create(AuCacheArgs(#type, sizeof(struct type)))
++
++/* ---------------------------------------------------------------------- */
++
++#define AuCacheFuncs(name, index) \
++static inline void *au_cache_alloc_##name(void) \
++{ return kmem_cache_alloc(au_cachep[index], GFP_NOFS); } \
++static inline void au_cache_free_##name(void *p) \
++{ kmem_cache_free(au_cachep[index], p); }
++
++AuCacheFuncs(dinfo, AuCache_DINFO);
++AuCacheFuncs(icntnr, AuCache_ICNTNR);
++AuCacheFuncs(finfo, AuCache_FINFO);
++AuCacheFuncs(vdir, AuCache_VDIR);
++AuCacheFuncs(dehstr, AuCache_DEHSTR);
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_MODULE_H__ */
+diff --git a/fs/aufs/opts.c b/fs/aufs/opts.c
+new file mode 100644
+index 0000000..c4e1412
+--- /dev/null
++++ b/fs/aufs/opts.c
+@@ -0,0 +1,1622 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * mount options/flags
++ *
++ * $Id: opts.c,v 1.72 2009/01/26 06:24:05 sfjro Exp $
++ */
++
++#include <linux/types.h> /* a distribution requires */
++#include <linux/parser.h>
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++enum {
++ Opt_br,
++ Opt_add, Opt_del, Opt_mod, Opt_reorder, Opt_append, Opt_prepend,
++ Opt_idel, Opt_imod, Opt_ireorder,
++ Opt_dirwh, Opt_rdcache, Opt_deblk, Opt_nhash, Opt_rendir,
++ Opt_xino, Opt_zxino, Opt_noxino,
++ Opt_trunc_xino, Opt_trunc_xino_v, Opt_notrunc_xino,
++ Opt_trunc_xino_path, Opt_itrunc_xino,
++ Opt_xinodir,
++ Opt_trunc_xib, Opt_notrunc_xib,
++ Opt_dirperm1, Opt_nodirperm1,
++ Opt_shwh, Opt_noshwh,
++ Opt_plink, Opt_noplink, Opt_list_plink, Opt_clean_plink,
++ Opt_udba,
++ /* Opt_lock, Opt_unlock, */
++ Opt_cmd, Opt_cmd_args,
++ Opt_diropq_a, Opt_diropq_w,
++ Opt_warn_perm, Opt_nowarn_perm,
++ Opt_wbr_copyup, Opt_wbr_create,
++ Opt_coo,
++ Opt_dlgt, Opt_nodlgt,
++ Opt_refrof, Opt_norefrof,
++ Opt_verbose, Opt_noverbose,
++ Opt_sum, Opt_nosum, Opt_wsum,
++ Opt_tail, Opt_ignore, Opt_ignore_silent, Opt_err
++};
++
++static match_table_t options = {
++ {Opt_br, "br=%s"},
++ {Opt_br, "br:%s"},
++
++ {Opt_add, "add=%d:%s"},
++ {Opt_add, "add:%d:%s"},
++ {Opt_add, "ins=%d:%s"},
++ {Opt_add, "ins:%d:%s"},
++ {Opt_append, "append=%s"},
++ {Opt_append, "append:%s"},
++ {Opt_prepend, "prepend=%s"},
++ {Opt_prepend, "prepend:%s"},
++
++ {Opt_del, "del=%s"},
++ {Opt_del, "del:%s"},
++ /* {Opt_idel, "idel:%d"}, */
++ {Opt_mod, "mod=%s"},
++ {Opt_mod, "mod:%s"},
++ {Opt_imod, "imod:%d:%s"},
++
++ {Opt_dirwh, "dirwh=%d"},
++ {Opt_dirwh, "dirwh:%d"},
++
++ {Opt_xino, "xino=%s"},
++ {Opt_xino, "xino:%s"},
++#if 0 /* def CONFIG_AUFS_EXPORT */ /* reserved for futur use */
++ {Opt_xinodir, "xinodir=%s"},
++ {Opt_xinodir, "xinodir:%s"},
++#endif
++ {Opt_noxino, "noxino"},
++ {Opt_trunc_xino, "trunc_xino"},
++ {Opt_trunc_xino_v, "trunc_xino_v=%d:%d"},
++ {Opt_notrunc_xino, "notrunc_xino"},
++ {Opt_trunc_xino_path, "trunc_xino=%s"},
++ {Opt_trunc_xino_path, "trunc_xino:%s"},
++ {Opt_itrunc_xino, "itrunc_xino=%d"},
++ {Opt_itrunc_xino, "itrunc_xino:%d"},
++ /* {Opt_zxino, "zxino=%s"}, */
++ {Opt_trunc_xib, "trunc_xib"},
++ {Opt_notrunc_xib, "notrunc_xib"},
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 16)
++ {Opt_plink, "plink"},
++ {Opt_noplink, "noplink"},
++#ifdef CONFIG_AUFS_DEBUG
++ {Opt_list_plink, "list_plink"},
++#endif
++ {Opt_clean_plink, "clean_plink"},
++#endif
++
++ {Opt_udba, "udba=%s"},
++
++ {Opt_diropq_a, "diropq=always"},
++ {Opt_diropq_a, "diropq=a"},
++ {Opt_diropq_w, "diropq=whiteouted"},
++ {Opt_diropq_w, "diropq=w"},
++
++ {Opt_warn_perm, "warn_perm"},
++ {Opt_nowarn_perm, "nowarn_perm"},
++
++#ifdef CONFIG_AUFS_DLGT
++ {Opt_dlgt, "dlgt"},
++ {Opt_dirperm1, "dirperm1"},
++#endif
++ {Opt_nodlgt, "nodlgt"},
++ {Opt_nodirperm1, "nodirperm1"},
++
++#ifdef CONFIG_AUFS_SHWH
++ {Opt_shwh, "shwh"},
++#endif
++ {Opt_noshwh, "noshwh"},
++
++ {Opt_rendir, "rendir=%d"},
++ {Opt_rendir, "rendir:%d"},
++
++ {Opt_refrof, "refrof"},
++ {Opt_norefrof, "norefrof"},
++
++ {Opt_verbose, "verbose"},
++ {Opt_verbose, "v"},
++ {Opt_noverbose, "noverbose"},
++ {Opt_noverbose, "quiet"},
++ {Opt_noverbose, "q"},
++ {Opt_noverbose, "silent"},
++
++ {Opt_sum, "sum"},
++ {Opt_nosum, "nosum"},
++ {Opt_wsum, "wsum"},
++
++ {Opt_rdcache, "rdcache=%d"},
++ {Opt_rdcache, "rdcache:%d"},
++
++ {Opt_coo, "coo=%s"},
++
++ {Opt_wbr_create, "create=%s"},
++ {Opt_wbr_create, "create:%s"},
++ {Opt_wbr_create, "create_policy=%s"},
++ {Opt_wbr_create, "create_policy:%s"},
++ {Opt_wbr_copyup, "cpup=%s"},
++ {Opt_wbr_copyup, "cpup:%s"},
++ {Opt_wbr_copyup, "copyup=%s"},
++ {Opt_wbr_copyup, "copyup:%s"},
++ {Opt_wbr_copyup, "copyup_policy=%s"},
++ {Opt_wbr_copyup, "copyup_policy:%s"},
++
++ /* internal use for the scripts */
++ {Opt_ignore_silent, "si=%s"},
++
++#if 0 /* reserved for future use */
++ {Opt_deblk, "deblk=%d"},
++ {Opt_deblk, "deblk:%d"},
++ {Opt_nhash, "nhash=%d"},
++ {Opt_nhash, "nhash:%d"},
++#endif
++
++ {Opt_br, "dirs=%s"},
++ {Opt_ignore, "debug=%d"},
++ {Opt_ignore, "delete=whiteout"},
++ {Opt_ignore, "delete=all"},
++ {Opt_ignore, "imap=%s"},
++
++ {Opt_err, NULL}
++};
++
++/* ---------------------------------------------------------------------- */
++
++static au_parser_pattern_t au_parser_pattern(int val, struct match_token *token)
++{
++ while (token->pattern) {
++ if (token->token == val)
++ return token->pattern;
++ token++;
++ }
++ BUG();
++ return "??";
++}
++
++/* ---------------------------------------------------------------------- */
++
++#define RW "rw"
++#define RO "ro"
++#define WH "wh"
++#define RR "rr"
++#define NoLinkWH "nolwh"
++
++static match_table_t brperms = {
++ {AuBrPerm_RR, RR},
++ {AuBrPerm_RO, RO},
++ {AuBrPerm_RW, RW},
++
++ {AuBrPerm_RRWH, RR "+" WH},
++ {AuBrPerm_ROWH, RO "+" WH},
++ {AuBrPerm_RWNoLinkWH, RW "+" NoLinkWH},
++
++ {AuBrPerm_ROWH, "nfsro"},
++ {AuBrPerm_RO, NULL}
++};
++
++static noinline_for_stack int br_perm_val(char *perm)
++{
++ int val;
++ substring_t args[MAX_OPT_ARGS];
++
++ AuDebugOn(!perm || !*perm);
++ LKTRTrace("perm %s\n", perm);
++ val = match_token(perm, brperms, args);
++ AuTraceErr(val);
++ return val;
++}
++
++au_parser_pattern_t au_optstr_br_perm(int brperm)
++{
++ return au_parser_pattern(brperm, brperms);
++}
++
++/* ---------------------------------------------------------------------- */
++
++static match_table_t udbalevel = {
++ {AuOpt_UDBA_REVAL, "reval"},
++#ifdef CONFIG_AUFS_HINOTIFY
++ {AuOpt_UDBA_INOTIFY, "inotify"},
++#endif
++ {AuOpt_UDBA_NONE, "none"},
++ {-1, NULL}
++};
++
++static noinline_for_stack int udba_val(char *str)
++{
++ substring_t args[MAX_OPT_ARGS];
++ return match_token(str, udbalevel, args);
++}
++
++au_parser_pattern_t au_optstr_udba(int udba)
++{
++ return au_parser_pattern(udba, udbalevel);
++}
++
++/* ---------------------------------------------------------------------- */
++
++static match_table_t coolevel = {
++ {AuOpt_COO_NONE, "none"},
++ {AuOpt_COO_LEAF, "leaf"},
++ {AuOpt_COO_ALL, "all"},
++ {-1, NULL}
++};
++
++static noinline_for_stack int coo_val(char *str)
++{
++ substring_t args[MAX_OPT_ARGS];
++ return match_token(str, coolevel, args);
++}
++
++au_parser_pattern_t au_optstr_coo(int coo)
++{
++ return au_parser_pattern(coo, coolevel);
++}
++
++/* ---------------------------------------------------------------------- */
++
++static match_table_t au_wbr_create_policy = {
++ {AuWbrCreate_TDP, "tdp"},
++ {AuWbrCreate_TDP, "top-down-parent"},
++ {AuWbrCreate_RR, "rr"},
++ {AuWbrCreate_RR, "round-robin"},
++ {AuWbrCreate_MFS, "mfs"},
++ {AuWbrCreate_MFS, "most-free-space"},
++ {AuWbrCreate_MFSV, "mfs:%d"},
++ {AuWbrCreate_MFSV, "most-free-space:%d"},
++
++ {AuWbrCreate_MFSRR, "mfsrr:%d"},
++ {AuWbrCreate_MFSRRV, "mfsrr:%d:%d"},
++ {AuWbrCreate_PMFS, "pmfs"},
++ {AuWbrCreate_PMFSV, "pmfs:%d"},
++
++ {-1, NULL}
++};
++
++/* cf. linux/lib/parser.c */
++static int au_match_ull(substring_t *s, unsigned long long *result)
++{
++ int err;
++ unsigned int len;
++ char a[32];
++ char *endp;
++
++ err = -ERANGE;
++ len = s->to - s->from;
++ if (len + 1 <= sizeof(a)) {
++ memcpy(a, s->from, len);
++ a[len] = '\0';
++#if 1
++ *result = simple_strtoull(a, &endp, 0);
++ err = 0;
++ if (endp == a)
++ err = -EINVAL;
++#else
++ char *next;
++ *result = memparse(a, &next);
++ err = *result;
++ if (!IS_ERR((void *)err))
++ err = 0;
++#endif
++ }
++ return err;
++}
++
++static int au_wbr_mfs_wmark(substring_t *arg, char *str,
++ struct au_opt_wbr_create *create)
++{
++ int err;
++ unsigned long long ull;
++
++ err = 0;
++ if (!au_match_ull(arg, &ull))
++ create->mfsrr_watermark = ull;
++ else {
++ AuErr("bad integer in %s\n", str);
++ err = -EINVAL;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_wbr_mfs_sec(substring_t *arg, char *str,
++ struct au_opt_wbr_create *create)
++{
++ int n, err;
++
++ err = 0;
++ if (!match_int(arg, &n) && 0 <= n)
++ create->mfs_second = n;
++ else {
++ AuErr("bad integer in %s\n", str);
++ err = -EINVAL;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static noinline_for_stack
++int au_wbr_create_val(char *str, struct au_opt_wbr_create *create)
++{
++ int err, e;
++ substring_t args[MAX_OPT_ARGS];
++
++ err = match_token(str, au_wbr_create_policy, args);
++ create->wbr_create = err;
++ switch (err) {
++ case AuWbrCreate_MFSRRV:
++ e = au_wbr_mfs_wmark(&args[0], str, create);
++ if (!e)
++ e = au_wbr_mfs_sec(&args[1], str, create);
++ if (unlikely(e))
++ err = e;
++ break;
++ case AuWbrCreate_MFSRR:
++ e = au_wbr_mfs_wmark(&args[0], str, create);
++ if (unlikely(e)) {
++ err = e;
++ break;
++ }
++ /*FALLTHROUGH*/
++ case AuWbrCreate_MFS:
++ case AuWbrCreate_PMFS:
++ create->mfs_second = AUFS_MFS_SECOND_DEF;
++ break;
++ case AuWbrCreate_MFSV:
++ case AuWbrCreate_PMFSV:
++ e = au_wbr_mfs_sec(&args[0], str, create);
++ if (unlikely(e))
++ err = e;
++ break;
++ }
++
++ return err;
++}
++
++au_parser_pattern_t au_optstr_wbr_create(int wbr_create)
++{
++ return au_parser_pattern(wbr_create, au_wbr_create_policy);
++}
++
++static match_table_t au_wbr_copyup_policy = {
++ {AuWbrCopyup_TDP, "tdp"},
++ {AuWbrCopyup_TDP, "top-down-parent"},
++ {AuWbrCopyup_BUP, "bup"},
++ {AuWbrCopyup_BUP, "bottom-up-parent"},
++ {AuWbrCopyup_BU, "bu"},
++ {AuWbrCopyup_BU, "bottom-up"},
++ {-1, NULL}
++};
++
++static noinline_for_stack int au_wbr_copyup_val(char *str)
++{
++ substring_t args[MAX_OPT_ARGS];
++ return match_token(str, au_wbr_copyup_policy, args);
++}
++
++au_parser_pattern_t au_optstr_wbr_copyup(int wbr_copyup)
++{
++ return au_parser_pattern(wbr_copyup, au_wbr_copyup_policy);
++}
++
++/* ---------------------------------------------------------------------- */
++
++static const int lkup_dirflags = LOOKUP_FOLLOW | LOOKUP_DIRECTORY;
++
++static void dump_opts(struct au_opts *opts)
++{
++#ifdef CONFIG_AUFS_DEBUG
++ /* reduce stack space */
++ union {
++ struct au_opt_add *add;
++ struct au_opt_del *del;
++ struct au_opt_mod *mod;
++ struct au_opt_xino *xino;
++ struct au_opt_xinodir *xinodir;
++ struct au_opt_xino_itrunc *xino_itrunc;
++ struct au_opt_wbr_create *create;
++ } u;
++ struct au_opt *opt;
++
++ AuTraceEnter();
++
++ opt = opts->opt;
++ while (/* opt < opts_tail && */ opt->type != Opt_tail) {
++ switch (opt->type) {
++ case Opt_add:
++ u.add = &opt->add;
++ LKTRTrace("add {b%d, %s, 0x%x, %p}\n",
++ u.add->bindex, u.add->path, u.add->perm,
++ u.add->nd.dentry);
++ break;
++ case Opt_del:
++ case Opt_idel:
++ u.del = &opt->del;
++ LKTRTrace("del {%s, %p}\n", u.del->path, u.del->h_root);
++ break;
++ case Opt_mod:
++ case Opt_imod:
++ u.mod = &opt->mod;
++ LKTRTrace("mod {%s, 0x%x, %p}\n",
++ u.mod->path, u.mod->perm, u.mod->h_root);
++ break;
++ case Opt_append:
++ u.add = &opt->add;
++ LKTRTrace("append {b%d, %s, 0x%x, %p}\n",
++ u.add->bindex, u.add->path, u.add->perm,
++ u.add->nd.dentry);
++ break;
++ case Opt_prepend:
++ u.add = &opt->add;
++ LKTRTrace("prepend {b%d, %s, 0x%x, %p}\n",
++ u.add->bindex, u.add->path, u.add->perm,
++ u.add->nd.dentry);
++ break;
++ case Opt_dirwh:
++ LKTRTrace("dirwh %d\n", opt->dirwh);
++ break;
++ case Opt_rdcache:
++ LKTRTrace("rdcache %d\n", opt->rdcache);
++ break;
++ case Opt_xino:
++ u.xino = &opt->xino;
++ LKTRTrace("xino {%s %.*s}\n",
++ u.xino->path,
++ AuDLNPair(u.xino->file->f_dentry));
++ break;
++#if 0 /* reserved for future use */
++ case Opt_xinodir:
++ u.xinodir = &opt->xinodir;
++ LKTRTrace("xinodir {%s %.*s}\n",
++ u.xinodir->name,
++ AuDLNPair(u.xinodir->path.dentry));
++ break;
++#endif
++ case Opt_trunc_xino:
++ LKTRLabel(trunc_xino);
++ break;
++ case Opt_notrunc_xino:
++ LKTRLabel(notrunc_xino);
++ break;
++ case Opt_trunc_xino_path:
++ case Opt_itrunc_xino:
++ u.xino_itrunc = &opt->xino_itrunc;
++ LKTRTrace("trunc_xino %d\n", u.xino_itrunc->bindex);
++ break;
++
++ case Opt_noxino:
++ LKTRLabel(noxino);
++ break;
++ case Opt_trunc_xib:
++ LKTRLabel(trunc_xib);
++ break;
++ case Opt_notrunc_xib:
++ LKTRLabel(notrunc_xib);
++ break;
++ case Opt_dirperm1:
++ LKTRLabel(dirperm1);
++ break;
++ case Opt_nodirperm1:
++ LKTRLabel(nodirperm1);
++ break;
++ case Opt_shwh:
++ LKTRLabel(shwh);
++ break;
++ case Opt_noshwh:
++ LKTRLabel(noshwh);
++ break;
++ case Opt_plink:
++ LKTRLabel(plink);
++ break;
++ case Opt_noplink:
++ LKTRLabel(noplink);
++ break;
++ case Opt_list_plink:
++ LKTRLabel(list_plink);
++ break;
++ case Opt_clean_plink:
++ LKTRLabel(clean_plink);
++ break;
++ case Opt_udba:
++ LKTRTrace("udba %d, %s\n",
++ opt->udba, au_optstr_udba(opt->udba));
++ break;
++ case Opt_diropq_a:
++ LKTRLabel(diropq_a);
++ break;
++ case Opt_diropq_w:
++ LKTRLabel(diropq_w);
++ break;
++ case Opt_warn_perm:
++ LKTRLabel(warn_perm);
++ break;
++ case Opt_nowarn_perm:
++ LKTRLabel(nowarn_perm);
++ break;
++ case Opt_dlgt:
++ LKTRLabel(dlgt);
++ break;
++ case Opt_nodlgt:
++ LKTRLabel(nodlgt);
++ break;
++ case Opt_refrof:
++ LKTRLabel(refrof);
++ break;
++ case Opt_norefrof:
++ LKTRLabel(norefrof);
++ break;
++ case Opt_verbose:
++ LKTRLabel(verbose);
++ break;
++ case Opt_noverbose:
++ LKTRLabel(noverbose);
++ break;
++ case Opt_sum:
++ LKTRLabel(sum);
++ break;
++ case Opt_nosum:
++ LKTRLabel(nosum);
++ break;
++ case Opt_wsum:
++ LKTRLabel(wsum);
++ break;
++ case Opt_coo:
++ LKTRTrace("coo %d, %s\n",
++ opt->coo, au_optstr_coo(opt->coo));
++ break;
++ case Opt_wbr_create:
++ u.create = &opt->wbr_create;
++ LKTRTrace("create %d, %s\n", u.create->wbr_create,
++ au_optstr_wbr_create(u.create->wbr_create));
++ switch (u.create->wbr_create) {
++ case AuWbrCreate_MFSV:
++ case AuWbrCreate_PMFSV:
++ LKTRTrace("%d sec\n", u.create->mfs_second);
++ break;
++ case AuWbrCreate_MFSRR:
++ LKTRTrace("%llu watermark\n",
++ u.create->mfsrr_watermark);
++ break;
++ case AuWbrCreate_MFSRRV:
++ LKTRTrace("%llu watermark, %d sec\n",
++ u.create->mfsrr_watermark,
++ u.create->mfs_second);
++ break;
++ }
++ break;
++ case Opt_wbr_copyup:
++ LKTRTrace("copyup %d, %s\n", opt->wbr_copyup,
++ au_optstr_wbr_copyup(opt->wbr_copyup));
++ break;
++ default:
++ BUG();
++ }
++ opt++;
++ }
++#endif
++}
++
++void au_opts_free(struct au_opts *opts)
++{
++ struct au_opt *opt;
++
++ AuTraceEnter();
++
++ opt = opts->opt;
++ while (opt->type != Opt_tail) {
++ switch (opt->type) {
++ case Opt_add:
++ case Opt_append:
++ case Opt_prepend:
++ path_release(&opt->add.nd);
++ break;
++ case Opt_del:
++ case Opt_idel:
++ dput(opt->del.h_root);
++ break;
++ case Opt_mod:
++ case Opt_imod:
++ dput(opt->mod.h_root);
++ break;
++ case Opt_xino:
++ fput(opt->xino.file);
++ break;
++#if 0 /* reserved for future use */
++ case Opt_xinodir:
++ path_put(&opt->xinodir.path);
++ break;
++#endif
++ }
++ opt++;
++ }
++}
++
++static int opt_add(struct au_opt *opt, char *opt_str, unsigned long sb_flags,
++ struct super_block *sb, aufs_bindex_t bindex)
++{
++ int err;
++ struct au_opt_add *add = &opt->add;
++ char *p;
++
++ LKTRTrace("%s, b%d\n", opt_str, bindex);
++
++ add->bindex = bindex;
++ add->perm = AuBrPerm_Last;
++ add->path = opt_str;
++ p = strchr(opt_str, '=');
++ if (p) {
++ *p++ = 0;
++ if (*p)
++ add->perm = br_perm_val(p);
++ }
++
++ /* LSM may detect it */
++ /* do not superio. */
++ err = vfsub_path_lookup(add->path, lkup_dirflags, &add->nd);
++ if (!err) {
++ if (!p /* && add->perm == AuBrPerm_Last */) {
++ add->perm = AuBrPerm_RO;
++ if (au_test_def_rr(add->nd.dentry->d_sb))
++ add->perm = AuBrPerm_RR;
++ if (!bindex && !(sb_flags & MS_RDONLY))
++ add->perm = AuBrPerm_RW;
++#ifdef CONFIG_AUFS_COMPAT
++ add->perm = AuBrPerm_RW;
++#endif
++ }
++ opt->type = Opt_add;
++ goto out;
++ }
++ AuErr("lookup failed %s (%d)\n", add->path, err);
++ err = -EINVAL;
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* called without aufs lock */
++int au_opts_parse(struct super_block *sb, char *str, struct au_opts *opts)
++{
++ int err, n, token;
++ struct dentry *root;
++ struct au_opt *opt, *opt_tail;
++ char *opt_str, *p;
++ aufs_bindex_t bindex, bend;
++ unsigned char skipped;
++ union {
++ struct au_opt_del *del;
++ struct au_opt_mod *mod;
++ struct au_opt_xino *xino;
++ struct au_opt_xinodir *xinodir;
++ struct au_opt_xino_itrunc *xino_itrunc;
++ struct au_opt_wbr_create *create;
++ } u;
++ struct file *file;
++ /* reduce the stack space */
++ struct {
++ substring_t args[MAX_OPT_ARGS];
++ struct nameidata nd;
++ } *a;
++
++ LKTRTrace("%s, nopts %d\n", str, opts->max_opt);
++
++ err = -ENOMEM;
++ a = kmalloc(sizeof(*a), GFP_NOFS);
++ if (unlikely(!a))
++ goto out;
++
++ root = sb->s_root;
++ err = 0;
++ bindex = 0;
++ opt = opts->opt;
++ opt_tail = opt + opts->max_opt - 1;
++ opt->type = Opt_tail;
++ while (!err && (opt_str = strsep(&str, ",")) && *opt_str) {
++ err = -EINVAL;
++ token = match_token(opt_str, options, a->args);
++ LKTRTrace("%s, token %d, a->args[0]{%p, %p}\n",
++ opt_str, token, a->args[0].from, a->args[0].to);
++
++ skipped = 0;
++ switch (token) {
++ case Opt_br:
++ err = 0;
++ while (!err && (opt_str = strsep(&a->args[0].from, ":"))
++ && *opt_str) {
++ err = opt_add(opt, opt_str, opts->sb_flags, sb,
++ bindex++);
++ if (unlikely(!err && ++opt > opt_tail)) {
++ err = -E2BIG;
++ break;
++ }
++ opt->type = Opt_tail;
++ skipped = 1;
++ }
++ break;
++ case Opt_add:
++ if (unlikely(match_int(&a->args[0], &n))) {
++ AuErr("bad integer in %s\n", opt_str);
++ break;
++ }
++ bindex = n;
++ err = opt_add(opt, a->args[1].from, opts->sb_flags, sb,
++ bindex);
++ break;
++ case Opt_append:
++ err = opt_add(opt, a->args[0].from, opts->sb_flags, sb,
++ /*dummy bindex*/1);
++ if (!err)
++ opt->type = token;
++ break;
++ case Opt_prepend:
++ err = opt_add(opt, a->args[0].from, opts->sb_flags, sb,
++ /*bindex*/0);
++ if (!err)
++ opt->type = token;
++ break;
++ case Opt_del:
++ u.del = &opt->del;
++ u.del->path = a->args[0].from;
++ LKTRTrace("del path %s\n", u.del->path);
++ /* LSM may detect it */
++ /* do not superio. */
++ err = vfsub_path_lookup(u.del->path, lkup_dirflags,
++ &a->nd);
++ if (unlikely(err)) {
++ AuErr("lookup failed %s (%d)\n",
++ u.del->path, err);
++ break;
++ }
++ u.del->h_root = dget(a->nd.dentry);
++ path_release(&a->nd);
++ opt->type = token;
++ break;
++#if 0 /* reserved for future use */
++ case Opt_idel:
++ u.del = &opt->del;
++ u.del->path = "(indexed)";
++ if (unlikely(match_int(&a->args[0], &n))) {
++ AuErr("bad integer in %s\n", opt_str);
++ break;
++ }
++ bindex = n;
++ aufs_read_lock(root, AuLock_FLUSH);
++ if (bindex < 0 || au_sbend(sb) < bindex) {
++ AuErr("out of bounds, %d\n", bindex);
++ aufs_read_unlock(root, !AuLock_IR);
++ break;
++ }
++ err = 0;
++ u.del->h_root = dget(au_h_dptr(root, bindex));
++ opt->type = token;
++ aufs_read_unlock(root, !AuLock_IR);
++ break;
++#endif
++ case Opt_mod:
++ u.mod = &opt->mod;
++ u.mod->path = a->args[0].from;
++ p = strchr(u.mod->path, '=');
++ if (unlikely(!p)) {
++ AuErr("no permssion %s\n", opt_str);
++ break;
++ }
++ *p++ = 0;
++ u.mod->perm = br_perm_val(p);
++ LKTRTrace("mod path %s, perm 0x%x, %s\n",
++ u.mod->path, u.mod->perm, p);
++ /* LSM may detect it */
++ /* do not superio. */
++ err = vfsub_path_lookup(u.mod->path, lkup_dirflags,
++ &a->nd);
++ if (unlikely(err)) {
++ AuErr("lookup failed %s (%d)\n",
++ u.mod->path, err);
++ break;
++ }
++ u.mod->h_root = dget(a->nd.dentry);
++ path_release(&a->nd);
++ opt->type = token;
++ break;
++#ifdef IMOD /* reserved for future use */
++ case Opt_imod:
++ u.mod = &opt->mod;
++ u.mod->path = "(indexed)";
++ if (unlikely(match_int(&a->args[0], &n))) {
++ AuErr("bad integer in %s\n", opt_str);
++ break;
++ }
++ bindex = n;
++ aufs_read_lock(root, AuLock_FLUSH);
++ if (bindex < 0 || au_sbend(sb) < bindex) {
++ AuErr("out of bounds, %d\n", bindex);
++ aufs_read_unlock(root, !AuLock_IR);
++ break;
++ }
++ u.mod->perm = br_perm_val(a->args[1].from);
++ LKTRTrace("mod path %s, perm 0x%x, %s\n",
++ u.mod->path, u.mod->perm, a->args[1].from);
++ err = 0;
++ u.mod->h_root = dget(au_h_dptr(root, bindex));
++ opt->type = token;
++ aufs_read_unlock(root, !AuLock_IR);
++ break;
++#endif
++ case Opt_xino:
++ u.xino = &opt->xino;
++ file = au_xino_create(sb, a->args[0].from, /*silent*/0);
++ err = PTR_ERR(file);
++ if (IS_ERR(file))
++ break;
++ err = -EINVAL;
++ if (unlikely(file->f_dentry->d_sb == sb)) {
++ fput(file);
++ AuErr("%s must be outside\n", a->args[0].from);
++ break;
++ }
++ err = 0;
++ u.xino->file = file;
++ u.xino->path = a->args[0].from;
++ opt->type = token;
++ break;
++
++#if 0 /* def CONFIG_AUFS_EXPORT */ /* reserved for futur use */
++ case Opt_xinodir:
++ u.xinodir = &opt->xinodir;
++ u.xinodir->name = a->args[0].from;
++ err = vfsub_path_lookup(u.xinodir->name, lkup_dirflags,
++ &a->nd);
++ if (unlikely(err)) {
++ AuErr("lookup failed %s (%d)\n",
++ u.xinodir->name, err);
++ break;
++ }
++ u.xinodir->path = a->nd.path;
++ /* do not path_put() */
++ opt->type = token;
++ break;
++#endif
++
++ case Opt_trunc_xino_path:
++ u.xino_itrunc = &opt->xino_itrunc;
++ p = a->args[0].from;
++ LKTRTrace("trunc_xino path %s\n", p);
++ /* LSM may detect it */
++ /* do not superio. */
++ err = vfsub_path_lookup(p, lkup_dirflags, &a->nd);
++ if (unlikely(err)) {
++ AuErr("lookup failed %s (%d)\n", p , err);
++ break;
++ }
++ u.xino_itrunc->bindex = -1;
++ aufs_read_lock(root, AuLock_FLUSH);
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++) {
++ if (au_h_dptr(root, bindex) == a->nd.dentry) {
++ u.xino_itrunc->bindex = bindex;
++ break;
++ }
++ }
++ aufs_read_unlock(root, !AuLock_IR);
++ path_release(&a->nd);
++ if (unlikely(u.xino_itrunc->bindex < 0)) {
++ AuErr("no such branch %s\n", p);
++ err = -EINVAL;
++ break;
++ }
++ opt->type = token;
++ break;
++
++ case Opt_itrunc_xino:
++ u.xino_itrunc = &opt->xino_itrunc;
++ if (unlikely(match_int(&a->args[0], &n))) {
++ AuErr("bad integer in %s\n", opt_str);
++ break;
++ }
++ u.xino_itrunc->bindex = n;
++ aufs_read_lock(root, AuLock_FLUSH);
++ if (n < 0 || au_sbend(sb) < n) {
++ AuErr("out of bounds, %d\n", n);
++ aufs_read_unlock(root, !AuLock_IR);
++ break;
++ }
++ aufs_read_unlock(root, !AuLock_IR);
++ err = 0;
++ opt->type = token;
++ break;
++
++ case Opt_dirwh:
++ if (unlikely(match_int(&a->args[0], &opt->dirwh)))
++ break;
++ err = 0;
++ opt->type = token;
++ break;
++
++ case Opt_rdcache:
++ if (unlikely(match_int(&a->args[0], &opt->rdcache)))
++ break;
++ err = 0;
++ opt->type = token;
++ break;
++
++ case Opt_shwh:
++ if (opts->sb_flags & MS_RDONLY) {
++ err = 0;
++ opt->type = token;
++ } else
++ AuErr("shwh requires ro\n");
++ break;
++
++ case Opt_trunc_xino:
++ case Opt_notrunc_xino:
++ case Opt_noxino:
++ case Opt_trunc_xib:
++ case Opt_notrunc_xib:
++ case Opt_dirperm1:
++ case Opt_nodirperm1:
++ case Opt_noshwh:
++ case Opt_plink:
++ case Opt_noplink:
++ case Opt_list_plink:
++ case Opt_clean_plink:
++ case Opt_diropq_a:
++ case Opt_diropq_w:
++ case Opt_warn_perm:
++ case Opt_nowarn_perm:
++ case Opt_dlgt:
++ case Opt_nodlgt:
++ case Opt_refrof:
++ case Opt_norefrof:
++ case Opt_verbose:
++ case Opt_noverbose:
++ case Opt_sum:
++ case Opt_nosum:
++ case Opt_wsum:
++ err = 0;
++ opt->type = token;
++ break;
++
++ case Opt_udba:
++ opt->udba = udba_val(a->args[0].from);
++ if (opt->udba >= 0) {
++ err = 0;
++ opt->type = token;
++ } else
++ AuErr("wrong value, %s\n", opt_str);
++ break;
++
++ case Opt_wbr_create:
++ u.create = &opt->wbr_create;
++ u.create->wbr_create
++ = au_wbr_create_val(a->args[0].from, u.create);
++ if (u.create->wbr_create >= 0) {
++ err = 0;
++ opt->type = token;
++ } else
++ AuErr("wrong value, %s\n", opt_str);
++ break;
++ case Opt_wbr_copyup:
++ opt->wbr_copyup = au_wbr_copyup_val(a->args[0].from);
++ if (opt->wbr_copyup >= 0) {
++ err = 0;
++ opt->type = token;
++ } else
++ AuErr("wrong value, %s\n", opt_str);
++ break;
++
++ case Opt_coo:
++ opt->coo = coo_val(a->args[0].from);
++ if (opt->coo >= 0) {
++ if (opt->coo == AuOpt_COO_NONE
++ || !(opts->sb_flags & MS_RDONLY)) {
++ err = 0;
++ opt->type = token;
++ } else
++ AuErr("bad %s for readonly mount\n",
++ opt_str);
++ } else
++ AuErr("wrong value, %s\n", opt_str);
++ break;
++
++ case Opt_ignore:
++#ifndef CONFIG_AUFS_COMPAT
++ AuWarn("ignored %s\n", opt_str);
++#endif
++ case Opt_ignore_silent:
++ skipped = 1;
++ err = 0;
++ break;
++ case Opt_err:
++ AuErr("unknown option %s\n", opt_str);
++ break;
++ }
++
++ if (!err && !skipped) {
++ if (unlikely(++opt > opt_tail)) {
++ err = -E2BIG;
++ opt--;
++ opt->type = Opt_tail;
++ break;
++ }
++ opt->type = Opt_tail;
++ }
++ }
++
++ kfree(a);
++ dump_opts(opts);
++ if (unlikely(err))
++ au_opts_free(opts);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * returns,
++ * plus: processed without an error
++ * zero: unprocessed
++ */
++static int au_opt_simple(struct super_block *sb, struct au_opt *opt,
++ struct au_opts *opts)
++{
++ int err;
++ struct au_sbinfo *sbinfo;
++ struct au_opt_wbr_create *create;
++
++ AuTraceEnter();
++
++ err = 1; /* handled */
++ sbinfo = au_sbi(sb);
++ switch (opt->type) {
++ case Opt_udba:
++ sbinfo->si_mntflags &= ~AuOptMask_UDBA;
++ sbinfo->si_mntflags |= opt->udba;
++ opts->given_udba |= opt->udba;
++ break;
++
++ case Opt_plink:
++ au_opt_set(sbinfo->si_mntflags, PLINK);
++ break;
++ case Opt_noplink:
++ if (au_opt_test(sbinfo->si_mntflags, PLINK))
++ au_plink_put(sb);
++ au_opt_clr(sbinfo->si_mntflags, PLINK);
++ break;
++ case Opt_list_plink:
++ if (au_opt_test(sbinfo->si_mntflags, PLINK))
++ au_plink_list(sb);
++ break;
++ case Opt_clean_plink:
++ if (au_opt_test(sbinfo->si_mntflags, PLINK))
++ au_plink_put(sb);
++ break;
++
++ case Opt_diropq_a:
++ au_opt_set(sbinfo->si_mntflags, ALWAYS_DIROPQ);
++ break;
++ case Opt_diropq_w:
++ au_opt_clr(sbinfo->si_mntflags, ALWAYS_DIROPQ);
++ break;
++
++ case Opt_dlgt:
++ au_opt_set(sbinfo->si_mntflags, DLGT);
++ break;
++ case Opt_nodlgt:
++ au_opt_clr(sbinfo->si_mntflags, DLGT);
++ break;
++
++ case Opt_warn_perm:
++ au_opt_set(sbinfo->si_mntflags, WARN_PERM);
++ break;
++ case Opt_nowarn_perm:
++ au_opt_clr(sbinfo->si_mntflags, WARN_PERM);
++ break;
++
++ case Opt_refrof:
++ au_opt_set(sbinfo->si_mntflags, REFROF);
++ break;
++ case Opt_norefrof:
++ /* au_opt_set(sbinfo->si_mntflags, COO_LEAF); */
++ au_opt_clr(sbinfo->si_mntflags, REFROF);
++ break;
++
++ case Opt_verbose:
++ au_opt_set(sbinfo->si_mntflags, VERBOSE);
++ break;
++ case Opt_noverbose:
++ au_opt_clr(sbinfo->si_mntflags, VERBOSE);
++ break;
++
++ case Opt_sum:
++ au_opt_set(sbinfo->si_mntflags, SUM);
++ break;
++ case Opt_wsum:
++ au_opt_clr(sbinfo->si_mntflags, SUM);
++ au_opt_set(sbinfo->si_mntflags, SUM_W);
++ case Opt_nosum:
++ au_opt_clr(sbinfo->si_mntflags, SUM);
++ au_opt_clr(sbinfo->si_mntflags, SUM_W);
++ break;
++
++ case Opt_wbr_create:
++ create = &opt->wbr_create;
++ if (sbinfo->si_wbr_create_ops->fin) {
++ err = sbinfo->si_wbr_create_ops->fin(sb);
++ if (!err)
++ err = 1;
++ }
++ sbinfo->si_wbr_create = create->wbr_create;
++ sbinfo->si_wbr_create_ops
++ = au_wbr_create_ops + create->wbr_create;
++ switch (create->wbr_create) {
++ case AuWbrCreate_MFSRRV:
++ case AuWbrCreate_MFSRR:
++ sbinfo->si_wbr_mfs.mfsrr_watermark
++ = create->mfsrr_watermark;
++ /*FALLTHROUGH*/
++ case AuWbrCreate_MFS:
++ case AuWbrCreate_MFSV:
++ case AuWbrCreate_PMFS:
++ case AuWbrCreate_PMFSV:
++ sbinfo->si_wbr_mfs.mfs_expire = create->mfs_second * HZ;
++ break;
++ }
++ if (sbinfo->si_wbr_create_ops->init)
++ sbinfo->si_wbr_create_ops->init(sb); /* ignore */
++ break;
++ case Opt_wbr_copyup:
++ sbinfo->si_wbr_copyup = opt->wbr_copyup;
++ sbinfo->si_wbr_copyup_ops = au_wbr_copyup_ops + opt->wbr_copyup;
++ break;
++
++ case Opt_coo:
++ sbinfo->si_mntflags &= ~AuOptMask_COO;
++ sbinfo->si_mntflags |= opt->coo;
++ break;
++
++ case Opt_dirwh:
++ sbinfo->si_dirwh = opt->dirwh;
++ break;
++
++ case Opt_rdcache:
++ sbinfo->si_rdcache = opt->rdcache * HZ;
++ break;
++
++ case Opt_trunc_xino:
++ au_opt_set(sbinfo->si_mntflags, TRUNC_XINO);
++ break;
++ case Opt_notrunc_xino:
++ au_opt_clr(sbinfo->si_mntflags, TRUNC_XINO);
++ break;
++
++ case Opt_dirperm1:
++ au_opt_set(sbinfo->si_mntflags, DIRPERM1);
++ break;
++ case Opt_nodirperm1:
++ au_opt_clr(sbinfo->si_mntflags, DIRPERM1);
++ break;
++
++ case Opt_shwh:
++ au_opt_set(sbinfo->si_mntflags, SHWH);
++ break;
++ case Opt_noshwh:
++ au_opt_clr(sbinfo->si_mntflags, SHWH);
++ break;
++
++ case Opt_trunc_xino_path:
++ case Opt_itrunc_xino:
++ err = au_xino_trunc(sb, opt->xino_itrunc.bindex);
++ if (!err)
++ err = 1;
++ break;
++
++ case Opt_trunc_xib:
++ au_fset_opts(opts->flags, TRUNC_XIB);
++ break;
++ case Opt_notrunc_xib:
++ au_fclr_opts(opts->flags, TRUNC_XIB);
++ break;
++
++ default:
++ err = 0;
++ break;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * returns tri-state.
++ * plus: processed without an error
++ * zero: unprocessed
++ * minus: error
++ */
++static int au_opt_br(struct super_block *sb, struct au_opt *opt,
++ struct au_opts *opts)
++{
++ int err, do_refresh;
++
++ AuTraceEnter();
++
++ err = 0;
++ switch (opt->type) {
++ case Opt_append:
++ opt->add.bindex = au_sbend(sb) + 1;
++ if (opt->add.bindex < 0)
++ opt->add.bindex = 0;
++ goto add;
++ case Opt_prepend:
++ opt->add.bindex = 0;
++ add:
++ case Opt_add:
++ err = au_br_add(sb, &opt->add,
++ au_ftest_opts(opts->flags, REMOUNT));
++ if (!err) {
++ err = 1;
++ au_fset_opts(opts->flags, REFRESH_DIR);
++ if (au_br_whable(opt->add.perm))
++ au_fset_opts(opts->flags, REFRESH_NONDIR);
++ }
++ break;
++
++ case Opt_del:
++ case Opt_idel:
++ err = au_br_del(sb, &opt->del,
++ au_ftest_opts(opts->flags, REMOUNT));
++ if (!err) {
++ err = 1;
++ au_fset_opts(opts->flags, TRUNC_XIB);
++ au_fset_opts(opts->flags, REFRESH_DIR);
++ au_fset_opts(opts->flags, REFRESH_NONDIR);
++ }
++ break;
++
++ case Opt_mod:
++ case Opt_imod:
++ err = au_br_mod(sb, &opt->mod,
++ au_ftest_opts(opts->flags, REMOUNT),
++ &do_refresh);
++ if (!err) {
++ err = 1;
++ if (do_refresh) {
++ au_fset_opts(opts->flags, REFRESH_DIR);
++ au_fset_opts(opts->flags, REFRESH_NONDIR);
++ }
++ }
++ break;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_opt_xino(struct super_block *sb, struct au_opt *opt,
++ struct au_opt_xino **opt_xino,
++ struct au_opt_xinodir **opt_xinodir,
++ struct au_opts *opts)
++{
++ int err;
++ const int remount = !!au_ftest_opts(opts->flags, REMOUNT);
++
++ AuTraceEnter();
++
++ err = 0;
++ switch (opt->type) {
++ case Opt_xino:
++ err = au_xino_set(sb, &opt->xino, remount);
++ if (!err)
++ *opt_xino = &opt->xino;
++ break;
++#if 0 /* def CONFIG_AUFS_EXPORT */ /* reserved for futur use */
++ case Opt_xinodir:
++ err = au_xinodir_set(sb, &opt->xinodir, remount);
++ if (!err)
++ *opt_xinodir = &opt->xinodir;
++ break;
++#endif
++ case Opt_noxino:
++ au_xino_clr(sb);
++ *opt_xino = (void *)-1;
++ break;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++int verify_opts(struct super_block *sb, unsigned long sb_flags,
++ unsigned int pending, int remount)
++{
++ int err;
++ aufs_bindex_t bindex, bend;
++ unsigned char do_plink, skip, do_free;
++ struct au_branch *br;
++ struct au_wbr *wbr;
++ struct dentry *root;
++ struct inode *dir, *h_dir;
++ unsigned int mnt_flags;
++
++ AuTraceEnter();
++ mnt_flags = au_mntflags(sb);
++ AuDebugOn(!(mnt_flags & AuOptMask_COO));
++ AuDebugOn(!(mnt_flags & AuOptMask_UDBA));
++
++ if (!(sb_flags & MS_RDONLY)) {
++ if (unlikely(!au_br_writable(au_sbr_perm(sb, 0))))
++ AuWarn("first branch should be rw\n");
++ if (unlikely(au_opt_test(mnt_flags, SHWH)))
++ AuWarn("shwh should be used with ro\n");
++ } else if (unlikely(!au_opt_test(mnt_flags, COO_NONE))) {
++ AuWarn("resetting coo for readonly mount\n");
++ au_opt_set_coo(au_sbi(sb)->si_mntflags, COO_NONE);
++ }
++
++ if (unlikely(au_opt_test((mnt_flags | pending), UDBA_INOTIFY)
++ && !au_opt_test_xino(mnt_flags)))
++ AuWarn("udba=inotify requires xino\n");
++
++ err = 0;
++ root = sb->s_root;
++ dir = sb->s_root->d_inode;
++ do_plink = !!au_opt_test(mnt_flags, PLINK);
++ bend = au_sbend(sb);
++ for (bindex = 0; !err && bindex <= bend; bindex++) {
++ skip = 0;
++ h_dir = au_h_iptr(dir, bindex);
++ br = au_sbr(sb, bindex);
++ do_free = 0;
++ wbr = br->br_wbr;
++ if (wbr)
++ wbr_wh_read_lock(wbr);
++ switch (br->br_perm) {
++ case AuBrPerm_RR:
++ case AuBrPerm_RO:
++ case AuBrPerm_RRWH:
++ case AuBrPerm_ROWH:
++ do_free = !!wbr;
++ skip = (!wbr
++ || (!wbr->wbr_whbase
++ && !wbr->wbr_plink
++ && !wbr->wbr_tmp));
++ break;
++
++ case AuBrPerm_RWNoLinkWH:
++ /* skip = (!br->br_whbase && !br->br_tmp); */
++ skip = (!wbr || !wbr->wbr_whbase);
++ if (skip && wbr) {
++ if (do_plink)
++ skip = !!wbr->wbr_plink;
++ else
++ skip = !wbr->wbr_plink;
++ }
++ break;
++
++ case AuBrPerm_RW:
++ /* skip = (br->br_whbase && br->br_tmp); */
++ skip = (wbr && wbr->wbr_whbase);
++ if (skip) {
++ if (do_plink)
++ skip = !!wbr->wbr_plink;
++ else
++ skip = !wbr->wbr_plink;
++ }
++ break;
++
++ default:
++ BUG();
++ }
++ if (wbr)
++ wbr_wh_read_unlock(wbr);
++
++ if (skip)
++ continue;
++
++ vfsub_i_lock_nested(h_dir, AuLsc_I_PARENT);
++ if (wbr)
++ wbr_wh_write_lock(wbr);
++ err = au_wh_init(au_h_dptr(root, bindex), br, br->br_mnt, sb,
++ bindex);
++ if (wbr)
++ wbr_wh_write_unlock(wbr);
++ vfsub_i_unlock(h_dir);
++
++ if (!err && do_free) {
++ kfree(wbr);
++ br->br_wbr = NULL;
++ }
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++int au_opts_mount(struct super_block *sb, struct au_opts *opts)
++{
++ int err;
++ struct inode *dir;
++ struct au_opt *opt;
++ struct au_opt_xino *opt_xino, xino;
++ struct au_opt_xinodir *opt_xinodir;
++ aufs_bindex_t bend;
++ struct au_sbinfo *sbinfo;
++ unsigned int tmp;
++ struct au_branch *br;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++ DiMustWriteLock(sb->s_root);
++ dir = sb->s_root->d_inode;
++ IiMustWriteLock(dir);
++
++ err = 0;
++ opt_xino = NULL;
++ opt_xinodir = NULL;
++ opt = opts->opt;
++ while (err >= 0 && opt->type != Opt_tail)
++ err = au_opt_simple(sb, opt++, opts);
++ if (err > 0)
++ err = 0;
++ else if (unlikely(err < 0))
++ goto out;
++
++ /* disable xino, xinodir, hinotify, dlgt temporary */
++ sbinfo = au_sbi(sb);
++ tmp = sbinfo->si_mntflags;
++ au_opt_clr(sbinfo->si_mntflags, XINO);
++ au_opt_clr(sbinfo->si_mntflags, XINODIR);
++ au_opt_clr(sbinfo->si_mntflags, DLGT);
++ au_opt_set_udba(sbinfo->si_mntflags, UDBA_REVAL);
++
++ opt = opts->opt;
++ while (err >= 0 && opt->type != Opt_tail)
++ err = au_opt_br(sb, opt++, opts);
++ if (err > 0)
++ err = 0;
++ else if (unlikely(err < 0))
++ goto out;
++
++ bend = au_sbend(sb);
++ if (unlikely(bend < 0)) {
++ err = -EINVAL;
++ AuErr("no branches\n");
++ goto out;
++ }
++
++ if (au_opt_test(tmp, XINO))
++ au_opt_set(sbinfo->si_mntflags, XINO);
++ else if (au_opt_test(tmp, XINODIR))
++ au_opt_set(sbinfo->si_mntflags, XINODIR);
++ opt = opts->opt;
++ while (!err && opt->type != Opt_tail)
++ err = au_opt_xino(sb, opt++, &opt_xino, &opt_xinodir, opts);
++ if (unlikely(err))
++ goto out;
++
++ /* todo: test this error case? */
++ err = verify_opts(sb, sb->s_flags, tmp, /*remount*/0);
++ if (unlikely(err))
++ goto out;
++
++ /* enable xino */
++ if (au_opt_test(tmp, XINO) && !opt_xino) {
++ xino.file = au_xino_def(sb);
++ err = PTR_ERR(xino.file);
++ if (IS_ERR(xino.file))
++ goto out;
++
++ br = au_xino_def_br(sbinfo);
++ err = au_xino_set(sb, &xino, /*remount*/0);
++ fput(xino.file);
++ if (unlikely(err))
++ goto out;
++ au_xino_def_br_set(br, sbinfo);
++ }
++
++ /* restore hinotify */
++ sbinfo->si_mntflags &= ~AuOptMask_UDBA;
++ sbinfo->si_mntflags |= (tmp & AuOptMask_UDBA);
++ if (au_opt_test(tmp, UDBA_INOTIFY))
++ au_reset_hinotify(dir, au_hi_flags(dir, 1) & ~AuHi_XINO);
++
++ /* restore dlgt */
++ if (au_opt_test(tmp, DLGT))
++ au_opt_set(sbinfo->si_mntflags, DLGT);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_opts_remount(struct super_block *sb, struct au_opts *opts)
++{
++ int err, rerr;
++ struct inode *dir;
++ struct au_opt_xino *opt_xino;
++ struct au_opt_xinodir *opt_xinodir;
++ struct au_opt *opt;
++ unsigned char dlgt;
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++ DiMustWriteLock(sb->s_root);
++ dir = sb->s_root->d_inode;
++ IiMustWriteLock(dir);
++ sbinfo = au_sbi(sb);
++
++ err = 0;
++ dlgt = !!au_opt_test(sbinfo->si_mntflags, DLGT);
++ opt_xino = NULL;
++ opt_xinodir = NULL;
++ opt = opts->opt;
++ while (err >= 0 && opt->type != Opt_tail) {
++ err = au_opt_simple(sb, opt, opts);
++
++ /* disable it temporary */
++ dlgt = !!au_opt_test(sbinfo->si_mntflags, DLGT);
++ au_opt_clr(sbinfo->si_mntflags, DLGT);
++
++ if (!err)
++ err = au_opt_br(sb, opt, opts);
++ if (!err)
++ err = au_opt_xino(sb, opt, &opt_xino, &opt_xinodir,
++ opts);
++
++ /* restore it */
++ if (dlgt)
++ au_opt_set(sbinfo->si_mntflags, DLGT);
++ opt++;
++ }
++ if (err > 0)
++ err = 0;
++ AuTraceErr(err);
++
++ /* go on even err */
++
++ /* todo: test this error case? */
++ au_opt_clr(sbinfo->si_mntflags, DLGT);
++ rerr = verify_opts(sb, opts->sb_flags, sbinfo->si_mntflags,
++ /*remount*/1);
++ if (unlikely(dlgt))
++ au_opt_set(sbinfo->si_mntflags, DLGT);
++ if (unlikely(rerr && !err))
++ err = rerr;
++
++ if (au_ftest_opts(opts->flags, TRUNC_XIB)) {
++ rerr = au_xib_trunc(sb);
++ if (unlikely(rerr && !err))
++ err = rerr;
++ }
++
++ /* they are handled by the caller */
++ if (!au_ftest_opts(opts->flags, REFRESH_DIR)
++ && (opts->given_udba || au_opt_test_xino(sbinfo->si_mntflags)))
++ au_fset_opts(opts->flags, REFRESH_DIR);
++
++ LKTRTrace("status 0x%x\n", opts->flags);
++ AuTraceErr(err);
++ return err;
++}
+diff --git a/fs/aufs/opts.h b/fs/aufs/opts.h
+new file mode 100644
+index 0000000..5a6d6ac
+--- /dev/null
++++ b/fs/aufs/opts.h
+@@ -0,0 +1,269 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * mount options/flags
++ *
++ * $Id: opts.h,v 1.37 2009/01/26 06:24:05 sfjro Exp $
++ */
++
++#ifndef __AUFS_OPTS_H__
++#define __AUFS_OPTS_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/namei.h>
++#include <linux/version.h>
++#include <linux/aufs_type.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++typedef const char *au_parser_pattern_t;
++#else
++typedef char *au_parser_pattern_t;
++#endif
++
++/* ---------------------------------------------------------------------- */
++/* mount flags */
++
++/* external inode number bitmap and translation table */
++#define AuOpt_XINO 1
++#define AuOpt_XINODIR (1 << 1)
++#define AuOpt_TRUNC_XINO (1 << 2)
++#define AuOpt_UDBA_NONE (1 << 3) /* users direct branch access */
++#define AuOpt_UDBA_REVAL (1 << 4)
++#define AuOpt_UDBA_INOTIFY (1 << 5)
++#define AuOpt_SHWH (1 << 6)
++#define AuOpt_PLINK (1 << 7)
++#define AuOpt_WARN_PERM (1 << 8)
++#define AuOpt_DIRPERM1 (1 << 9)
++#define AuOpt_DLGT (1 << 10)
++#define AuOpt_COO_NONE (1 << 11) /* copyup on open */
++#define AuOpt_COO_LEAF (1 << 12)
++#define AuOpt_COO_ALL (1 << 13)
++#define AuOpt_ALWAYS_DIROPQ (1 << 14)
++#define AuOpt_REFROF (1 << 15)
++#define AuOpt_VERBOSE (1 << 16)
++#define AuOpt_SUM (1 << 17)
++#define AuOpt_SUM_W (1 << 18) /* unimplemented */
++
++#if 1 /* ndef CONFIG_AUFS_EXPORT */ /* reserved for future use */
++#undef AuOpt_XINODIR
++#define AuOpt_XINODIR 0
++#endif
++#ifndef CONFIG_AUFS_HINOTIFY
++#undef AuOpt_UDBA_INOTIFY
++#define AuOpt_UDBA_INOTIFY 0
++#endif
++#ifndef CONFIG_AUFS_SHWH
++#undef AuOpt_SHWH
++#define AuOpt_SHWH 0
++#endif
++#ifndef CONFIG_AUFS_DLGT
++#undef AuOpt_DIRPERM1
++#define AuOpt_DIRPERM1 0
++#undef AuOpt_DLGT
++#define AuOpt_DLGT 0
++#endif
++
++/* policies to select one among multiple writable branches */
++enum {
++ AuWbrCreate_TDP, /* top down parent */
++ AuWbrCreate_RR, /* round robin */
++ AuWbrCreate_MFS, /* most free space */
++ AuWbrCreate_MFSV, /* mfs with seconds */
++ AuWbrCreate_MFSRR, /* mfs then rr */
++ AuWbrCreate_MFSRRV, /* mfs then rr with seconds */
++ AuWbrCreate_PMFS, /* parent and mfs */
++ AuWbrCreate_PMFSV, /* parent and mfs with seconds */
++
++ AuWbrCreate_Def = AuWbrCreate_TDP
++};
++
++enum {
++ AuWbrCopyup_TDP, /* top down parent */
++ AuWbrCopyup_BUP, /* bottom up parent */
++ AuWbrCopyup_BU, /* bottom up */
++
++ AuWbrCopyup_Def = AuWbrCopyup_TDP
++};
++
++#define AuOptMask_COO (AuOpt_COO_NONE \
++ | AuOpt_COO_LEAF \
++ | AuOpt_COO_ALL)
++#define AuOptMask_UDBA (AuOpt_UDBA_NONE \
++ | AuOpt_UDBA_REVAL \
++ | AuOpt_UDBA_INOTIFY)
++
++#ifdef CONFIG_AUFS_COMPAT
++#define AuOpt_DefExtra1 AuOpt_ALWAYS_DIROPQ
++#else
++#define AuOpt_DefExtra1 0
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 16)
++#define AuOpt_DefExtra2 AuOpt_PLINK
++#else
++#define AuOpt_DefExtra2 0
++#endif
++
++#define AuOpt_Def (AuOpt_XINO \
++ | AuOpt_UDBA_REVAL \
++ | AuOpt_WARN_PERM \
++ | AuOpt_COO_NONE \
++ | AuOpt_DefExtra1 \
++ | AuOpt_DefExtra2)
++
++/* ---------------------------------------------------------------------- */
++
++struct au_opt_add {
++ aufs_bindex_t bindex;
++ char *path;
++ int perm;
++ struct nameidata nd;
++};
++
++struct au_opt_del {
++ char *path;
++ struct dentry *h_root;
++};
++
++struct au_opt_mod {
++ char *path;
++ int perm;
++ struct dentry *h_root;
++};
++
++struct au_opt_xino {
++ char *path;
++ struct file *file;
++};
++
++struct au_opt_xinodir {
++#if 0 /* reserved for future use */
++ char *name;
++ struct path path;
++#endif
++};
++
++struct au_opt_xino_itrunc {
++ aufs_bindex_t bindex;
++};
++
++struct au_opt_xino_trunc_v {
++ unsigned long long upper;
++ int step;
++};
++
++struct au_opt_wbr_create {
++ int wbr_create;
++ int mfs_second;
++ unsigned long long mfsrr_watermark;
++};
++
++struct au_opt {
++ int type;
++ union {
++ struct au_opt_xino xino;
++ struct au_opt_xinodir xinodir;
++ struct au_opt_xino_itrunc xino_itrunc;
++ struct au_opt_add add;
++ struct au_opt_del del;
++ struct au_opt_mod mod;
++ int dirwh;
++ int rdcache;
++ int deblk;
++ int nhash;
++ int udba;
++ int coo;
++ struct au_opt_wbr_create wbr_create;
++ int wbr_copyup;
++ };
++};
++
++/* opts flags */
++#define AuOpts_REMOUNT 1
++#define AuOpts_REFRESH_DIR (1 << 1)
++#define AuOpts_REFRESH_NONDIR (1 << 2)
++#define AuOpts_TRUNC_XIB (1 << 3)
++#define au_ftest_opts(flags, name) ((flags) & AuOpts_##name)
++#define au_fset_opts(flags, name) { (flags) |= AuOpts_##name; }
++#define au_fclr_opts(flags, name) { (flags) &= ~AuOpts_##name; }
++
++struct au_opts {
++ struct au_opt *opt;
++ int max_opt;
++
++ unsigned int given_udba;
++ unsigned int flags;
++ unsigned long sb_flags;
++};
++
++/* ---------------------------------------------------------------------- */
++
++au_parser_pattern_t au_optstr_br_perm(int brperm);
++au_parser_pattern_t au_optstr_udba(int udba);
++au_parser_pattern_t au_optstr_coo(int coo);
++au_parser_pattern_t au_optstr_wbr_copyup(int wbr_copyup);
++au_parser_pattern_t au_optstr_wbr_create(int wbr_create);
++
++void au_opts_free(struct au_opts *opts);
++int au_opts_parse(struct super_block *sb, char *str, struct au_opts *opts);
++int verify_opts(struct super_block *sb, unsigned long sb_flags,
++ unsigned int pending, int remount);
++int au_opts_mount(struct super_block *sb, struct au_opts *opts);
++int au_opts_remount(struct super_block *sb, struct au_opts *opts);
++
++/* ---------------------------------------------------------------------- */
++
++#define au_opt_test(flags, name) (flags & AuOpt_##name)
++
++static inline int au_opt_test_xino(unsigned int flags)
++{
++ return flags & (AuOpt_XINO | AuOpt_XINODIR);
++}
++
++#define au_opt_set(flags, name) do { \
++ BUILD_BUG_ON(AuOpt_##name & (AuOptMask_COO | AuOptMask_UDBA)); \
++ ((flags) |= AuOpt_##name); \
++} while (0)
++
++#define au_opt_set_coo(flags, name) do { \
++ (flags) &= ~AuOptMask_COO; \
++ ((flags) |= AuOpt_##name); \
++} while (0)
++
++#define au_opt_set_udba(flags, name) do { \
++ (flags) &= ~AuOptMask_UDBA; \
++ ((flags) |= AuOpt_##name); \
++} while (0)
++
++#define au_opt_clr(flags, name) { ((flags) &= ~AuOpt_##name); }
++
++static inline int au_test_dlgt(unsigned int flags)
++{
++ return au_opt_test(flags, DLGT) && !au_test_wkq(current);
++}
++
++static inline int au_test_dirperm1(unsigned int flags)
++{
++ return au_opt_test(flags, DIRPERM1) && !au_test_wkq(current);
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_OPTS_H__ */
+diff --git a/fs/aufs/plink.c b/fs/aufs/plink.c
+new file mode 100644
+index 0000000..ef19ad0
+--- /dev/null
++++ b/fs/aufs/plink.c
+@@ -0,0 +1,364 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * pseudo-link
++ *
++ * $Id: plink.c,v 1.28 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++struct pseudo_link {
++ struct list_head list;
++ struct inode *inode;
++};
++
++#ifdef CONFIG_AUFS_DEBUG
++void au_plink_list(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++ struct list_head *plink_list;
++ struct pseudo_link *plink;
++
++ AuTraceEnter();
++ SiMustAnyLock(sb);
++ sbinfo = au_sbi(sb);
++ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK));
++
++ plink_list = &sbinfo->si_plink.head;
++ spin_lock(&sbinfo->si_plink.spin);
++ list_for_each_entry(plink, plink_list, list)
++ AuDbg("%lu\n", plink->inode->i_ino);
++ spin_unlock(&sbinfo->si_plink.spin);
++}
++#endif
++
++int au_plink_test(struct super_block *sb, struct inode *inode)
++{
++ int found;
++ struct au_sbinfo *sbinfo;
++ struct list_head *plink_list;
++ struct pseudo_link *plink;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++ SiMustAnyLock(sb);
++ sbinfo = au_sbi(sb);
++ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK));
++
++ found = 0;
++ plink_list = &sbinfo->si_plink.head;
++ spin_lock(&sbinfo->si_plink.spin);
++ list_for_each_entry(plink, plink_list, list)
++ if (plink->inode == inode) {
++ found = 1;
++ break;
++ }
++ spin_unlock(&sbinfo->si_plink.spin);
++ return found;
++}
++
++/* 20 is max digits length of ulong 64 */
++#define PLINK_NAME_LEN ((20 + 1) * 2)
++
++static int plink_name(char *name, int len, struct inode *inode,
++ aufs_bindex_t bindex)
++{
++ int rlen;
++ struct inode *h_inode;
++
++ LKTRTrace("i%lu, b%d\n", inode->i_ino, bindex);
++ AuDebugOn(len != PLINK_NAME_LEN);
++ h_inode = au_h_iptr(inode, bindex);
++ AuDebugOn(!h_inode);
++ rlen = snprintf(name, len, "%lu.%lu", inode->i_ino, h_inode->i_ino);
++ AuDebugOn(rlen >= len);
++ return rlen;
++}
++
++struct dentry *au_plink_lkup(struct super_block *sb, aufs_bindex_t bindex,
++ struct inode *inode)
++{
++ struct dentry *h_dentry, *h_parent;
++ struct au_branch *br;
++ struct au_wbr *wbr;
++ struct inode *h_dir;
++ char tgtname[PLINK_NAME_LEN];
++ int len;
++ struct au_ndx ndx = {
++ .flags = 0,
++ .nd = NULL,
++ /* .br = NULL */
++ };
++
++ LKTRTrace("b%d, i%lu\n", bindex, inode->i_ino);
++ br = au_sbr(sb, bindex);
++ wbr = br->br_wbr;
++ AuDebugOn(!wbr);
++ h_parent = wbr->wbr_plink;
++ AuDebugOn(!h_parent);
++ h_dir = h_parent->d_inode;
++ AuDebugOn(!h_dir);
++
++ len = plink_name(tgtname, sizeof(tgtname), inode, bindex);
++
++ /* always superio. */
++ ndx.nfsmnt = au_do_nfsmnt(br->br_mnt);
++ vfsub_i_lock_nested(h_dir, AuLsc_I_CHILD2);
++ h_dentry = au_sio_lkup_one(tgtname, h_parent, len, &ndx);
++ vfsub_i_unlock(h_dir);
++ return h_dentry;
++}
++
++static int do_whplink(char *tgt, int len, struct dentry *h_parent,
++ struct dentry *h_dentry, struct vfsmount *nfsmnt,
++ struct super_block *sb)
++{
++ int err, dlgt;
++ struct dentry *h_tgt;
++ struct inode *h_dir;
++ struct vfsub_args vargs;
++ struct au_ndx ndx = {
++ .nfsmnt = nfsmnt,
++ .flags = 0,
++ .nd = NULL,
++ /* .br = NULL */
++ };
++
++ AuTraceEnter();
++
++ dlgt = !!au_test_dlgt(au_mntflags(sb));
++ if (dlgt)
++ au_fset_ndx(ndx.flags, DLGT);
++ h_tgt = au_lkup_one(tgt, h_parent, len, &ndx);
++ err = PTR_ERR(h_tgt);
++ if (IS_ERR(h_tgt))
++ goto out;
++
++ err = 0;
++ vfsub_args_init(&vargs, NULL, dlgt, 0);
++ /* wh.plink dir is not monitored */
++ h_dir = h_parent->d_inode;
++ if (h_tgt->d_inode && h_tgt->d_inode != h_dentry->d_inode)
++ err = vfsub_unlink(h_dir, h_tgt, &vargs);
++ if (!err && !h_tgt->d_inode) {
++ err = vfsub_link(h_dentry, h_dir, h_tgt, &vargs);
++ /* todo: unnecessary? */
++ /* inc_nlink(inode); */
++ }
++ dput(h_tgt);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++struct do_whplink_args {
++ int *errp;
++ char *tgt;
++ int len;
++ struct dentry *h_parent;
++ struct dentry *h_dentry;
++ struct vfsmount *nfsmnt;
++ struct super_block *sb;
++};
++
++static void call_do_whplink(void *args)
++{
++ struct do_whplink_args *a = args;
++ *a->errp = do_whplink(a->tgt, a->len, a->h_parent, a->h_dentry,
++ a->nfsmnt, a->sb);
++}
++
++static int whplink(struct dentry *h_dentry, struct inode *inode,
++ aufs_bindex_t bindex, struct super_block *sb)
++{
++ int err, len, wkq_err;
++ struct au_branch *br;
++ struct au_wbr *wbr;
++ struct dentry *h_parent;
++ struct inode *h_dir;
++ char tgtname[PLINK_NAME_LEN];
++
++ LKTRTrace("%.*s\n", AuDLNPair(h_dentry));
++ br = au_sbr(inode->i_sb, bindex);
++ wbr = br->br_wbr;
++ AuDebugOn(!wbr);
++ h_parent = wbr->wbr_plink;
++ AuDebugOn(!h_parent);
++ h_dir = h_parent->d_inode;
++ AuDebugOn(!h_dir);
++
++ len = plink_name(tgtname, sizeof(tgtname), inode, bindex);
++
++ /* always superio. */
++ vfsub_i_lock_nested(h_dir, AuLsc_I_CHILD2);
++ if (!au_test_wkq(current)) {
++ struct do_whplink_args args = {
++ .errp = &err,
++ .tgt = tgtname,
++ .len = len,
++ .h_parent = h_parent,
++ .h_dentry = h_dentry,
++ .nfsmnt = au_do_nfsmnt(br->br_mnt),
++ .sb = sb
++ };
++ wkq_err = au_wkq_wait(call_do_whplink, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ } else
++ err = do_whplink(tgtname, len, h_parent, h_dentry,
++ au_do_nfsmnt(br->br_mnt), sb);
++ vfsub_i_unlock(h_dir);
++
++ AuTraceErr(err);
++ return err;
++}
++
++static void do_put_plink(struct pseudo_link *plink, int do_del)
++{
++ AuTraceEnter();
++
++ iput(plink->inode);
++ if (do_del)
++ list_del(&plink->list);
++ kfree(plink);
++}
++
++void au_plink_append(struct super_block *sb, struct inode *inode,
++ struct dentry *h_dentry, aufs_bindex_t bindex)
++{
++ struct au_sbinfo *sbinfo;
++ struct list_head *plink_list;
++ struct pseudo_link *plink;
++ int found, err, cnt;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++ SiMustAnyLock(sb);
++ sbinfo = au_sbi(sb);
++ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK));
++
++ cnt = 0;
++ found = 0;
++ plink_list = &sbinfo->si_plink.head;
++ spin_lock(&sbinfo->si_plink.spin);
++ list_for_each_entry(plink, plink_list, list) {
++ cnt++;
++ if (plink->inode == inode) {
++ found = 1;
++ break;
++ }
++ }
++
++ err = 0;
++ plink = NULL;
++ if (!found) {
++ plink = kmalloc(sizeof(*plink), GFP_ATOMIC);
++ if (plink) {
++ plink->inode = au_igrab(inode);
++ list_add(&plink->list, plink_list);
++ cnt++;
++ } else
++ err = -ENOMEM;
++ }
++ spin_unlock(&sbinfo->si_plink.spin);
++
++#if 0 /* todo: test here */
++ if (found)
++ return; /* success */
++#endif
++
++ if (!err)
++ err = whplink(h_dentry, inode, bindex, sb);
++
++ if (unlikely(cnt > AUFS_PLINK_WARN))
++ AuWarn1("unexpectedly many pseudo links, %d\n", cnt);
++ if (unlikely(err)) {
++ AuWarn("err %d, damaged pseudo link. ignored.\n", err);
++ if (!found && plink)
++ do_put_plink(plink, /*do_del*/1);
++ }
++}
++
++void au_plink_put(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++ struct list_head *plink_list;
++ struct pseudo_link *plink, *tmp;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++ sbinfo = au_sbi(sb);
++ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK));
++
++ plink_list = &sbinfo->si_plink.head;
++ /* spin_lock(&sbinfo->si_plink.spin); */
++ list_for_each_entry_safe(plink, tmp, plink_list, list)
++ do_put_plink(plink, 0);
++ INIT_LIST_HEAD(plink_list);
++ /* spin_unlock(&sbinfo->si_plink.head); */
++}
++
++void au_plink_half_refresh(struct super_block *sb, aufs_bindex_t br_id)
++{
++ struct au_sbinfo *sbinfo;
++ struct list_head *plink_list;
++ struct pseudo_link *plink, *tmp;
++ struct inode *inode;
++ aufs_bindex_t bstart, bend, bindex;
++ int do_put;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++ sbinfo = au_sbi(sb);
++ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK));
++
++ plink_list = &sbinfo->si_plink.head;
++ /* spin_lock(&sbinfo->si_plink.spin); */
++ list_for_each_entry_safe(plink, tmp, plink_list, list) {
++ do_put = 0;
++ inode = au_igrab(plink->inode);
++ ii_write_lock_child(inode);
++ bstart = au_ibstart(inode);
++ bend = au_ibend(inode);
++ if (bstart >= 0) {
++ for (bindex = bstart; bindex <= bend; bindex++) {
++ if (!au_h_iptr(inode, bindex)
++ || au_ii_br_id(inode, bindex) != br_id)
++ continue;
++ au_set_h_iptr(inode, bindex, NULL, 0);
++ do_put = 1;
++ break;
++ }
++ } else
++ do_put_plink(plink, 1);
++
++ if (do_put) {
++ for (bindex = bstart; bindex <= bend; bindex++)
++ if (au_h_iptr(inode, bindex)) {
++ do_put = 0;
++ break;
++ }
++ if (do_put)
++ do_put_plink(plink, 1);
++ }
++ ii_write_unlock(inode);
++ iput(inode);
++ }
++ /* spin_unlock(&sbinfo->si_plink.spin); */
++}
+diff --git a/fs/aufs/robr.c b/fs/aufs/robr.c
+new file mode 100644
+index 0000000..4e05d03
+--- /dev/null
++++ b/fs/aufs/robr.c
+@@ -0,0 +1,117 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * 'robr', aufs as readonly branch of another aufs
++ *
++ * $Id: robr.c,v 1.9 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++int au_test_robr_wh(struct qstr *name, struct dentry *h_parent,
++ struct qstr *wh_name, int try_sio, struct au_ndx *ndx)
++{
++ if (strncmp(name->name, AUFS_WH_PFX, AUFS_WH_PFX_LEN))
++ return au_wh_test(h_parent, wh_name, try_sio, ndx);
++ return -EPERM;
++}
++
++int au_test_robr_shwh(struct super_block *sb, const struct qstr *name)
++{
++ return 0;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct au_robr_lvma {
++ struct list_head list;
++ struct vm_area_struct *vma;
++};
++
++struct file *au_robr_safe_file(struct vm_area_struct *vma)
++{
++ struct file *file = vma->vm_file;
++ struct super_block *sb = file->f_dentry->d_sb;
++ struct au_robr_lvma *lvma, *entry;
++ struct au_sbinfo *sbinfo;
++ struct list_head *head;
++ unsigned char found, warn;
++
++ AuTraceEnter();
++
++ if (!file->private_data || !au_test_aufs(sb))
++ return NULL;
++
++ warn = 0;
++ found = 0;
++ sbinfo = au_sbi(sb);
++ head = &sbinfo->si_lvma.head;
++ spin_lock(&sbinfo->si_lvma.spin);
++ list_for_each_entry(entry, head, list) {
++ found = (entry->vma == vma);
++ if (unlikely(found))
++ break;
++ }
++ if (!found) {
++ lvma = kmalloc(sizeof(*lvma), GFP_ATOMIC);
++ if (lvma) {
++ lvma->vma = vma;
++ list_add(&lvma->list, head);
++ } else {
++ warn = 1;
++ file = NULL;
++ }
++ } else
++ file = NULL;
++ spin_unlock(&sbinfo->si_lvma.spin);
++
++ if (unlikely(warn))
++ AuWarn1("no memory for lvma\n");
++ return file;
++}
++
++void au_robr_reset_file(struct vm_area_struct *vma, struct file *file)
++{
++ struct super_block *sb = file->f_dentry->d_sb;
++ struct au_robr_lvma *entry, *found;
++ struct au_sbinfo *sbinfo;
++ struct list_head *head;
++
++ AuTraceEnter();
++ AuDebugOn(!au_test_aufs(sb));
++
++ vma->vm_file = file;
++ /* smp_mb(); */ /* flush vm_file */
++
++ found = NULL;
++ sbinfo = au_sbi(sb);
++ head = &sbinfo->si_lvma.head;
++ spin_lock(&sbinfo->si_lvma.spin);
++ list_for_each_entry(entry, head, list)
++ if (entry->vma == vma) {
++ found = entry;
++ break;
++ }
++ AuDebugOn(!found);
++ list_del(&found->list);
++ spin_unlock(&sbinfo->si_lvma.spin);
++ kfree(found);
++}
+diff --git a/fs/aufs/sbinfo.c b/fs/aufs/sbinfo.c
+new file mode 100644
+index 0000000..26c67bc
+--- /dev/null
++++ b/fs/aufs/sbinfo.c
+@@ -0,0 +1,223 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * superblock private data
++ *
++ * $Id: sbinfo.c,v 1.54 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++void au_si_free(struct super_block *sb, int err)
++{
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++ sbinfo = au_sbi(sb);
++ AuDebugOn(!sbinfo);
++ AuDebugOn(!list_empty(&sbinfo->si_plink.head));
++
++ if (!err) {
++ au_sbilist_lock();
++ au_sbilist_del(sbinfo);
++ si_write_lock(sb);
++ sysaufs_sbi_del(sb);
++ au_sbilist_unlock();
++ } else
++ si_write_lock(sb);
++
++ au_xino_clr(sb);
++ au_br_free(sbinfo);
++ kfree(sbinfo->si_branch);
++ au_export_put(sbinfo);
++ mutex_destroy(&sbinfo->si_xib_mtx);
++ si_write_unlock(sb);
++ au_rwsem_destroy(&sbinfo->si_rwsem);
++ sysaufs_sbi_put(sb);
++ kfree(sbinfo);
++}
++
++int au_si_alloc(struct super_block *sb)
++{
++ int err;
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ sbinfo = kmalloc(sizeof(*sbinfo), GFP_NOFS);
++ //if (LktrCond) {kfree(sbinfo); sbinfo = NULL;}
++ if (unlikely(!sbinfo))
++ goto out;
++ sbinfo->si_branch = kzalloc(sizeof(*sbinfo->si_branch), GFP_NOFS);
++ //if (LktrCond) {kfree(sbinfo->si_branch); sbinfo->si_branch = NULL;}
++ if (unlikely(!sbinfo->si_branch))
++ goto out_sbinfo;
++ err = sysaufs_si_init(sbinfo);
++ if (unlikely(err))
++ goto out_br;
++
++ au_rw_init_wlock(&sbinfo->si_rwsem);
++ //au_dbg_locked_si_reg(sb, 1);
++ sbinfo->si_generation = 0;
++ //sbinfo->si_generation = INT_MAX - 2;
++ sbinfo->au_si_status = 0;
++ sbinfo->si_bend = -1;
++ sbinfo->si_last_br_id = 0;
++
++ sbinfo->si_wbr_copyup = AuWbrCopyup_Def;
++ sbinfo->si_wbr_create = AuWbrCreate_Def;
++ sbinfo->si_wbr_copyup_ops = au_wbr_copyup_ops + AuWbrCopyup_Def;
++ sbinfo->si_wbr_create_ops = au_wbr_create_ops + AuWbrCreate_Def;
++
++ sbinfo->si_mntflags = AuOpt_Def;
++
++ sbinfo->si_xread = NULL;
++ sbinfo->si_xwrite = NULL;
++ sbinfo->si_xib = NULL;
++ mutex_init(&sbinfo->si_xib_mtx);
++ sbinfo->si_xib_buf = NULL;
++ au_xino_def_br_set(NULL, sbinfo);
++ /* leave si_xib_last_pindex and si_xib_next_bit */
++
++ au_nwt_init(&sbinfo->si_nowait);
++
++ sbinfo->si_rdcache = AUFS_RDCACHE_DEF * HZ;
++ sbinfo->si_dirwh = AUFS_DIRWH_DEF;
++
++ au_spl_init(&sbinfo->si_plink);
++
++ /* leave other members for sysaufs, si_list and si_mnt. */
++
++ au_robr_lvma_init(sbinfo);
++ sb->s_fs_info = sbinfo;
++ //sysaufs_sbi_get(sb);
++
++ au_debug_sbinfo_init(sbinfo);
++ return 0; /* success */
++
++ out_br:
++ kfree(sbinfo->si_branch);
++ out_sbinfo:
++ kfree(sbinfo);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct au_branch *au_sbr(struct super_block *sb, aufs_bindex_t bindex)
++{
++ struct au_branch *br;
++
++ SiMustAnyLock(sb);
++ AuDebugOn(bindex < 0 || au_sbend(sb) < bindex);
++ br = au_sbi(sb)->si_branch[0 + bindex];
++ AuDebugOn(!br);
++ return br;
++}
++
++au_gen_t au_sigen_inc(struct super_block *sb)
++{
++ au_gen_t gen;
++
++ SiMustWriteLock(sb);
++ gen = ++au_sbi(sb)->si_generation;
++ au_update_digen(sb->s_root);
++ au_update_iigen(sb->s_root->d_inode);
++ sb->s_root->d_inode->i_version++;
++ return gen;
++}
++
++int au_find_bindex(struct super_block *sb, struct au_branch *br)
++{
++ aufs_bindex_t bindex, bend;
++
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++)
++ if (au_sbr(sb, bindex) == br)
++ return bindex;
++ return -1;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* dentry and super_block lock. call at entry point */
++void aufs_read_lock(struct dentry *dentry, int flags)
++{
++ si_read_lock(dentry->d_sb, flags);
++ if (au_ftest_lock(flags, DW))
++ di_write_lock_child(dentry);
++ else
++ di_read_lock_child(dentry, flags);
++}
++
++void aufs_read_unlock(struct dentry *dentry, int flags)
++{
++ if (au_ftest_lock(flags, DW))
++ di_write_unlock(dentry);
++ else
++ di_read_unlock(dentry, flags);
++ si_read_unlock(dentry->d_sb);
++}
++
++void aufs_write_lock(struct dentry *dentry)
++{
++ si_write_lock(dentry->d_sb);
++ di_write_lock_child(dentry);
++}
++
++void aufs_write_unlock(struct dentry *dentry)
++{
++ di_write_unlock(dentry);
++ si_write_unlock(dentry->d_sb);
++}
++
++void aufs_read_and_write_lock2(struct dentry *d1, struct dentry *d2, int flags)
++{
++ AuDebugOn(d1 == d2 || d1->d_sb != d2->d_sb);
++ si_read_lock(d1->d_sb, flags);
++ di_write_lock2_child(d1, d2, au_ftest_lock(flags, DIR));
++}
++
++void aufs_read_and_write_unlock2(struct dentry *d1, struct dentry *d2)
++{
++ AuDebugOn(d1 == d2 || d1->d_sb != d2->d_sb);
++ di_write_unlock2(d1, d2);
++ si_read_unlock(d1->d_sb);
++}
++
++/* ---------------------------------------------------------------------- */
++
++aufs_bindex_t au_new_br_id(struct super_block *sb)
++{
++ aufs_bindex_t br_id;
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ sbinfo = au_sbi(sb);
++ while (1) {
++ br_id = ++sbinfo->si_last_br_id;
++ if (br_id && au_br_index(sb, br_id) < 0)
++ return br_id;
++ }
++}
+diff --git a/fs/aufs/super.c b/fs/aufs/super.c
+new file mode 100644
+index 0000000..1943a6b
+--- /dev/null
++++ b/fs/aufs/super.c
+@@ -0,0 +1,1032 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * mount and super_block operations
++ *
++ * $Id: super.c,v 1.103 2009/01/26 06:24:10 sfjro Exp $
++ */
++
++#include <linux/module.h>
++#include <linux/buffer_head.h>
++#include <linux/seq_file.h>
++#include <linux/smp_lock.h>
++#include <linux/statfs.h>
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
++#include <linux/mnt_namespace.h>
++typedef struct mnt_namespace au_mnt_ns_t;
++#define au_nsproxy(tsk) (tsk)->nsproxy
++#define au_mnt_ns(tsk) (tsk)->nsproxy->mnt_ns
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++#include <linux/namespace.h>
++typedef struct namespace au_mnt_ns_t;
++#define au_nsproxy(tsk) (tsk)->nsproxy
++#define au_mnt_ns(tsk) (tsk)->nsproxy->namespace
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++#include <linux/namespace.h>
++typedef struct namespace au_mnt_ns_t;
++#define au_nsproxy(tsk) (tsk)->namespace
++#define au_mnt_ns(tsk) (tsk)->namespace
++#endif
++
++#include "aufs.h"
++
++/*
++ * super_operations
++ */
++static struct inode *aufs_alloc_inode(struct super_block *sb)
++{
++ struct aufs_icntnr *c;
++
++ AuTraceEnter();
++
++ c = au_cache_alloc_icntnr();
++ if (c) {
++ inode_init_once(&c->vfs_inode);
++ c->vfs_inode.i_version = 1; /* sigen(sb); */
++ c->iinfo.ii_hinode = NULL;
++ return &c->vfs_inode;
++ }
++ return NULL;
++}
++
++static void aufs_destroy_inode(struct inode *inode)
++{
++ int err;
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++
++ if (!inode->i_nlink || IS_DEADDIR(inode)) {
++ /* in nowait task or remount, sbi is write-locked */
++ struct super_block *sb = inode->i_sb;
++ const int locked = si_noflush_read_trylock(sb);
++
++ err = au_xigen_inc(inode);
++ if (unlikely(err))
++ AuWarn1("failed resetting i_generation, %d\n", err);
++ if (locked)
++ si_read_unlock(sb);
++ }
++
++ au_iinfo_fin(inode);
++ au_cache_free_icntnr(container_of(inode, struct aufs_icntnr,
++ vfs_inode));
++}
++
++static void aufs_read_inode(struct inode *inode)
++{
++ int err;
++#if 0
++ static struct backing_dev_info bdi = {
++ .ra_pages = 0, /* No readahead */
++ .capabilities = BDI_CAP_NO_ACCT_DIRTY | BDI_CAP_NO_WRITEBACK
++ };
++#endif
++
++ LKTRTrace("i%lu\n", inode->i_ino);
++
++ err = au_xigen_new(inode);
++ if (!err)
++ err = au_iinfo_init(inode);
++ //if (LktrCond) err = -1;
++ if (!err) {
++ inode->i_version++;
++ //inode->i_mapping->backing_dev_info = &bdi;
++ return; /* success */
++ }
++
++ LKTRTrace("intializing inode info failed(%d)\n", err);
++ make_bad_inode(inode);
++}
++
++/* lock free root dinfo */
++static int au_show_brs(struct seq_file *seq, struct super_block *sb)
++{
++ int err;
++ aufs_bindex_t bindex, bend;
++ struct au_hdentry *hd;
++
++ AuTraceEnter();
++
++ err = 0;
++ bend = au_sbend(sb);
++ hd = au_di(sb->s_root)->di_hdentry;
++ for (bindex = 0; !err && bindex <= bend; bindex++) {
++ err = seq_path(seq, au_sbr_mnt(sb, bindex),
++ hd[bindex].hd_dentry, au_esc_chars);
++ if (err > 0) {
++ const char *p = au_optstr_br_perm(au_sbr_perm(sb,
++ bindex));
++ err = seq_printf(seq, "=%s", p);
++ }
++ if (!err && bindex != bend)
++ err = seq_putc(seq, ':');
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++static void au_show_wbr_create(struct seq_file *m, int v,
++ struct au_sbinfo *sbinfo)
++{
++ au_parser_pattern_t pat;
++
++ AuDebugOn(v == AuWbrCreate_Def);
++
++ seq_printf(m, ",create=");
++ pat = au_optstr_wbr_create(v);
++ switch (v) {
++ case AuWbrCreate_TDP:
++ case AuWbrCreate_RR:
++ case AuWbrCreate_MFS:
++ case AuWbrCreate_PMFS:
++ seq_printf(m, pat);
++ break;
++ case AuWbrCreate_MFSV:
++ seq_printf(m, /*pat*/"mfs:%lu",
++ sbinfo->si_wbr_mfs.mfs_expire / HZ);
++ break;
++ case AuWbrCreate_PMFSV:
++ seq_printf(m, /*pat*/"pmfs:%lu",
++ sbinfo->si_wbr_mfs.mfs_expire / HZ);
++ break;
++ case AuWbrCreate_MFSRR:
++ seq_printf(m, /*pat*/"mfsrr:%llu",
++ sbinfo->si_wbr_mfs.mfsrr_watermark);
++ break;
++ case AuWbrCreate_MFSRRV:
++ seq_printf(m, /*pat*/"mfsrr:%llu:%lu",
++ sbinfo->si_wbr_mfs.mfsrr_watermark,
++ sbinfo->si_wbr_mfs.mfs_expire / HZ);
++ break;
++ }
++}
++
++/* seq_file will re-call me in case of too long string */
++static int aufs_show_options(struct seq_file *m, struct vfsmount *mnt)
++{
++ int err, n;
++ unsigned int mnt_flags, v;
++ struct super_block *sb;
++ struct au_sbinfo *sbinfo;
++ struct file *xino;
++
++ AuTraceEnter();
++
++ sb = mnt->mnt_sb;
++ /* lock free root dinfo */
++ si_noflush_read_lock(sb);
++ sbinfo = au_sbi(sb);
++
++ /* compatibility for some aufs scripts */
++ seq_printf(m, ",si=%p", sbinfo);
++ mnt_flags = au_mntflags(sb);
++ if (au_opt_test(mnt_flags, XINO)) {
++ seq_puts(m, ",xino=");
++ xino = sbinfo->si_xib;
++ err = seq_path(m, xino->f_vfsmnt, xino->f_dentry, au_esc_chars);
++ if (unlikely(err <= 0))
++ goto out;
++ err = 0;
++#define Deleted "\\040(deleted)"
++ m->count -= sizeof(Deleted) - 1;
++ AuDebugOn(memcmp(m->buf + m->count, Deleted,
++ sizeof(Deleted) - 1));
++#undef Deleted
++#if 0 //def CONFIG_AUFS_EXPORT /* reserved for future use */
++ } else if (au_opt_test(mnt_flags, XINODIR)) {
++ seq_puts(m, ",xinodir=");
++ seq_path(m, &sbinfo->si_xinodir, au_esc_chars);
++#endif
++ } else
++ seq_puts(m, ",noxino");
++
++#define AuBool(name, str) do { \
++ v = au_opt_test(mnt_flags, name); \
++ if (v != au_opt_test(AuOpt_Def, name)) \
++ seq_printf(m, ",%s" #str, v ? "" : "no"); \
++} while (0)
++
++#define AuStr(name, str) do { \
++ v = mnt_flags & AuOptMask_##name; \
++ if (v != (AuOpt_Def & AuOptMask_##name)) \
++ seq_printf(m, "," #str "=%s", au_optstr_##str(v)); \
++} while (0)
++
++#ifdef CONFIG_AUFS_COMPAT
++#define AuStr_BrOpt "dirs="
++#else
++#define AuStr_BrOpt "br:"
++#endif
++
++ AuBool(TRUNC_XINO, trunc_xino);
++ AuBool(DIRPERM1, dirperm1);
++ AuBool(SHWH, shwh);
++ AuBool(PLINK, plink);
++ AuStr(UDBA, udba);
++
++ v = sbinfo->si_wbr_create;
++ if (v != AuWbrCreate_Def)
++ au_show_wbr_create(m, v, sbinfo);
++
++ v = sbinfo->si_wbr_copyup;
++ if (v != AuWbrCopyup_Def)
++ seq_printf(m, ",cpup=%s", au_optstr_wbr_copyup(v));
++
++ v = au_opt_test(mnt_flags, ALWAYS_DIROPQ);
++ if (v != au_opt_test(AuOpt_Def, ALWAYS_DIROPQ))
++ seq_printf(m, ",diropq=%c", v ? 'a' : 'w');
++ AuBool(REFROF, refrof);
++ AuBool(DLGT, dlgt);
++ AuBool(WARN_PERM, warn_perm);
++ AuBool(VERBOSE, verbose);
++ AuBool(SUM, sum);
++ /* AuBool(SUM_W, wsum); */
++
++ n = sbinfo->si_dirwh;
++ if (n != AUFS_DIRWH_DEF)
++ seq_printf(m, ",dirwh=%d", n);
++ n = sbinfo->si_rdcache / HZ;
++ if (n != AUFS_RDCACHE_DEF)
++ seq_printf(m, ",rdcache=%d", n);
++
++ AuStr(COO, coo);
++
++ if (!sysaufs_brs) {
++ seq_puts(m, "," AuStr_BrOpt);
++ au_show_brs(m, sb);
++ }
++
++ out:
++ si_read_unlock(sb);
++ return 0;
++
++#undef AuBool
++#undef AuStr
++#undef AuStr_BrOpt
++}
++
++#ifndef ULLONG_MAX /* before linux-2.6.18 */
++#define ULLONG_MAX (~0ULL)
++#endif
++
++static u64 au_add_till_max(u64 a, u64 b)
++{
++ u64 old;
++
++ old = a;
++ a += b;
++ if (old < a)
++ return a;
++ return ULLONG_MAX;
++}
++
++static int au_statfs_sum(struct super_block *sb, struct kstatfs *buf, int dlgt)
++{
++ int err;
++ aufs_bindex_t bend, bindex, i;
++ unsigned char shared;
++ u64 blocks, bfree, bavail, files, ffree;
++ struct super_block *h_sb;
++
++ AuTraceEnter();
++
++ blocks = 0;
++ bfree = 0;
++ bavail = 0;
++ files = 0;
++ ffree = 0;
++
++ err = 0;
++ bend = au_sbend(sb);
++ for (bindex = bend; bindex >= 0; bindex--) {
++ h_sb = au_sbr_sb(sb, bindex);
++ shared = 0;
++ for (i = bindex + 1; !shared && i <= bend; i++)
++ shared = au_sbr_sb(sb, i) == h_sb;
++ if (shared)
++ continue;
++
++ err = vfsub_statfs(h_sb->s_root, buf, dlgt);
++ if (unlikely(err))
++ goto out;
++
++ blocks = au_add_till_max(blocks, buf->f_blocks);
++ bfree = au_add_till_max(bfree, buf->f_bfree);
++ bavail = au_add_till_max(bavail, buf->f_bavail);
++ files = au_add_till_max(files, buf->f_files);
++ ffree = au_add_till_max(ffree, buf->f_ffree);
++ }
++
++ buf->f_blocks = blocks;
++ buf->f_bfree = bfree;
++ buf->f_bavail = bavail;
++ buf->f_files = files;
++ buf->f_ffree = ffree;
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++#define StatfsArg(sb) au_sbr_sb(sb, 0)->s_root
++#define StatfsSb(d) ((d)->d_sb)
++static int aufs_statfs(struct dentry *arg, struct kstatfs *buf)
++#else
++#define StatfsArg(sb) au_sbr_sb(sb, 0)
++#define StatfsSb(s) (s)
++static int aufs_statfs(struct super_block *arg, struct kstatfs *buf)
++#endif
++{
++ int err;
++ unsigned int mnt_flags;
++ unsigned char dlgt;
++ struct super_block *sb = StatfsSb(arg);
++
++ AuTraceEnter();
++
++ /* lock free root dinfo */
++ si_noflush_read_lock(sb);
++ mnt_flags = au_mntflags(sb);
++ dlgt = !!au_test_dlgt(mnt_flags);
++ if (!au_opt_test(mnt_flags, SUM))
++ err = vfsub_statfs(StatfsArg(sb), buf, dlgt);
++ else
++ err = au_statfs_sum(sb, buf, dlgt);
++ //if (LktrCond) err = -1;
++ si_read_unlock(sb);
++ if (!err) {
++ buf->f_type = AUFS_SUPER_MAGIC;
++ buf->f_namelen -= AUFS_WH_PFX_LEN;
++ //todo: support uuid?
++ memset(&buf->f_fsid, 0, sizeof(buf->f_fsid));
++ }
++ /* buf->f_bsize = buf->f_blocks = buf->f_bfree = buf->f_bavail = -1; */
++
++ AuTraceErr(err);
++ return err;
++}
++
++static void au_update_mnt(struct vfsmount *mnt, int flags)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++ struct vfsmount *pos;
++ struct super_block *sb = mnt->mnt_sb;
++ struct dentry *root = sb->s_root;
++ struct au_sbinfo *sbinfo = au_sbi(sb);
++ au_mnt_ns_t *ns;
++
++ AuTraceEnter();
++ AuDebugOn(!kernel_locked());
++
++ if (sbinfo->si_mnt != mnt
++ || atomic_read(&sb->s_active) == 1
++ || !au_nsproxy(current))
++ return;
++
++ /* no get/put */
++ ns = au_mnt_ns(current);
++ AuDebugOn(!ns);
++ sbinfo->si_mnt = NULL;
++ list_for_each_entry(pos, &ns->list, mnt_list)
++ if (pos != mnt && pos->mnt_sb->s_root == root) {
++ sbinfo->si_mnt = pos;
++ break;
++ }
++ AuDebugOn(!(flags & MNT_DETACH) && !sbinfo->si_mnt);
++#endif
++}
++
++static void au_fsync_br(struct super_block *sb)
++{
++#ifdef CONFIG_AUFS_FSYNC_SUPER_PATCH
++ aufs_bindex_t bend, bindex;
++ int brperm;
++ struct au_branch *br;
++ struct super_block *h_sb;
++
++ AuTraceEnter();
++
++ si_write_lock(sb);
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex < bend; bindex++) {
++ br = au_sbr(sb, bindex);
++ brperm = br->br_perm;
++ if (brperm == AuBrPerm_RR || brperm == AuBrPerm_RRWH)
++ continue;
++ h_sb = br->br_mnt->mnt_sb;
++ if (bdev_read_only(h_sb->s_bdev))
++ continue;
++
++ lockdep_off();
++ down_write(&h_sb->s_umount);
++ shrink_dcache_sb(h_sb);
++ fsync_super(h_sb);
++ up_write(&h_sb->s_umount);
++ lockdep_on();
++ }
++ si_write_unlock(sb);
++#endif
++}
++
++#define UmountBeginHasMnt (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18))
++
++#if UmountBeginHasMnt
++#define UmountBeginSb(mnt) ((mnt)->mnt_sb)
++#define UmountBeginMnt(mnt) (mnt)
++#define UmountBeginFlags _flags
++static void aufs_umount_begin(struct vfsmount *arg, int _flags)
++#else
++#define UmountBeginSb(sb) sb
++#define UmountBeginMnt(sb) NULL
++#define UmountBeginFlags 0
++static void aufs_umount_begin(struct super_block *arg)
++#endif
++{
++ struct super_block *sb = UmountBeginSb(arg);
++ struct vfsmount *mnt = UmountBeginMnt(arg);
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++
++ sbinfo = au_sbi(sb);
++ if (!sbinfo)
++ return;
++
++ au_fsync_br(sb);
++
++ si_write_lock(sb);
++ if (au_opt_test(au_mntflags(sb), PLINK))
++ au_plink_put(sb);
++#if 0 // remove
++ if (au_opt_test(au_mntflags(sb), UDBA_INOTIFY))
++ shrink_dcache_sb(sb);
++#endif
++ au_update_mnt(mnt, UmountBeginFlags);
++#if 0
++ if (sbinfo->si_wbr_create_ops->fin)
++ sbinfo->si_wbr_create_ops->fin(sb);
++#endif
++ si_write_unlock(sb);
++}
++
++/* final actions when unmounting a file system */
++static void aufs_put_super(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++
++ sbinfo = au_sbi(sb);
++ if (!sbinfo)
++ return;
++
++#if !UmountBeginHasMnt
++ /* umount_begin() may not be called. */
++ aufs_umount_begin(sb);
++#endif
++ au_si_free(sb, /*err*/0);
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * refresh dentry and inode at remount time.
++ */
++static int do_refresh(struct dentry *dentry, mode_t type,
++ unsigned int dir_flags)
++{
++ int err;
++ struct dentry *parent;
++ struct inode *inode;
++
++ LKTRTrace("%.*s, 0%o\n", AuDLNPair(dentry), type);
++ inode = dentry->d_inode;
++ AuDebugOn(!inode);
++
++ di_write_lock_child(dentry);
++ parent = dget_parent(dentry);
++ di_read_lock_parent(parent, AuLock_IR);
++ /* returns a number of positive dentries */
++ err = au_refresh_hdentry(dentry, type);
++ if (err >= 0) {
++ err = au_refresh_hinode(inode, dentry);
++ if (!err && type == S_IFDIR)
++ au_reset_hinotify(inode, dir_flags);
++ }
++ if (unlikely(err))
++ AuErr("unrecoverable error %d, %.*s\n", err, AuDLNPair(dentry));
++ di_read_unlock(parent, AuLock_IR);
++ dput(parent);
++ di_write_unlock(dentry);
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int test_dir(struct dentry *dentry, void *arg)
++{
++ return S_ISDIR(dentry->d_inode->i_mode);
++}
++
++/* todo: merge with refresh_nondir()? */
++static int refresh_dir(struct dentry *root, au_gen_t sgen)
++{
++ int err, i, j, ndentry, e;
++ struct au_dcsub_pages dpages;
++ struct au_dpage *dpage;
++ struct dentry **dentries;
++ struct inode *inode;
++ const unsigned int flags = au_hi_flags(root->d_inode, /*isdir*/1);
++
++ LKTRTrace("sgen %d\n", sgen);
++ SiMustWriteLock(root->d_sb);
++ /* dont trust BKL */
++ AuDebugOn(au_digen(root) != sgen || !kernel_locked());
++
++ err = 0;
++ list_for_each_entry(inode, &root->d_sb->s_inodes, i_sb_list)
++ if (S_ISDIR(inode->i_mode) && au_iigen(inode) != sgen) {
++ ii_write_lock_child(inode);
++ e = au_refresh_hinode_self(inode);
++ ii_write_unlock(inode);
++ if (unlikely(e)) {
++ LKTRTrace("e %d, i%lu\n", e, inode->i_ino);
++ if (!err)
++ err = e;
++ /* go on even if err */
++ }
++ }
++
++ e = au_dpages_init(&dpages, GFP_NOFS);
++ if (unlikely(e)) {
++ if (!err)
++ err = e;
++ goto out;
++ }
++ e = au_dcsub_pages(&dpages, root, test_dir, NULL);
++ if (unlikely(e)) {
++ if (!err)
++ err = e;
++ goto out_dpages;
++ }
++
++ for (i = 0; !e && i < dpages.ndpage; i++) {
++ dpage = dpages.dpages + i;
++ dentries = dpage->dentries;
++ ndentry = dpage->ndentry;
++ for (j = 0; !e && j < ndentry; j++) {
++ struct dentry *d;
++ d = dentries[j];
++#ifdef CONFIG_AUFS_DEBUG
++ {
++ struct dentry *parent;
++ parent = dget_parent(d);
++ AuDebugOn(!S_ISDIR(d->d_inode->i_mode)
++ || IS_ROOT(d)
++ || au_digen(parent) != sgen);
++ dput(parent);
++ }
++#endif
++ if (au_digen(d) != sgen) {
++ e = do_refresh(d, S_IFDIR, flags);
++ if (unlikely(e && !err))
++ err = e;
++ /* break on err */
++ }
++ }
++ }
++
++ out_dpages:
++ au_dpages_free(&dpages);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int test_nondir(struct dentry *dentry, void *arg)
++{
++ return !S_ISDIR(dentry->d_inode->i_mode);
++}
++
++static int refresh_nondir(struct dentry *root, au_gen_t sgen, int do_dentry)
++{
++ int err, i, j, ndentry, e;
++ struct au_dcsub_pages dpages;
++ struct au_dpage *dpage;
++ struct dentry **dentries;
++ struct inode *inode;
++
++ LKTRTrace("sgen %d\n", sgen);
++ SiMustWriteLock(root->d_sb);
++ /* dont trust BKL */
++ AuDebugOn(au_digen(root) != sgen || !kernel_locked());
++
++ err = 0;
++ list_for_each_entry(inode, &root->d_sb->s_inodes, i_sb_list)
++ if (!S_ISDIR(inode->i_mode) && au_iigen(inode) != sgen) {
++ ii_write_lock_child(inode);
++ e = au_refresh_hinode_self(inode);
++ ii_write_unlock(inode);
++ if (unlikely(e)) {
++ LKTRTrace("e %d, i%lu\n", e, inode->i_ino);
++ if (!err)
++ err = e;
++ /* go on even if err */
++ }
++ }
++
++ if (!do_dentry)
++ goto out;
++
++ e = au_dpages_init(&dpages, GFP_NOFS);
++ if (unlikely(e)) {
++ if (!err)
++ err = e;
++ goto out;
++ }
++ e = au_dcsub_pages(&dpages, root, test_nondir, NULL);
++ if (unlikely(e)) {
++ if (!err)
++ err = e;
++ goto out_dpages;
++ }
++
++ for (i = 0; i < dpages.ndpage; i++) {
++ dpage = dpages.dpages + i;
++ dentries = dpage->dentries;
++ ndentry = dpage->ndentry;
++ for (j = 0; j < ndentry; j++) {
++ struct dentry *d;
++ d = dentries[j];
++#ifdef CONFIG_AUFS_DEBUG
++ {
++ struct dentry *parent;
++ parent = dget_parent(d);
++ AuDebugOn(S_ISDIR(d->d_inode->i_mode)
++ || au_digen(parent) != sgen);
++ dput(parent);
++ }
++#endif
++ inode = d->d_inode;
++ if (inode && au_digen(d) != sgen) {
++ e = do_refresh(d, inode->i_mode & S_IFMT, 0);
++ if (unlikely(e && !err))
++ err = e;
++ /* go on even err */
++ }
++ }
++ }
++
++ out_dpages:
++ au_dpages_free(&dpages);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* stop extra interpretation of errno in mount(8), and strange error messages */
++static int cvt_err(int err)
++{
++ AuTraceErr(err);
++
++ switch (err) {
++ case -ENOENT:
++ case -ENOTDIR:
++ case -EEXIST:
++ case -EIO:
++ err = -EINVAL;
++ }
++ return err;
++}
++
++/* protected by s_umount */
++static int aufs_remount_fs(struct super_block *sb, int *flags, char *data)
++{
++ int err, rerr;
++ au_gen_t sigen;
++ struct dentry *root;
++ struct inode *inode;
++ struct au_opts opts;
++ struct au_sbinfo *sbinfo;
++ unsigned char dlgt;
++
++ LKTRTrace("flags 0x%x, data %s, len %lu\n",
++ *flags, data ? data : "NULL",
++ (unsigned long)(data ? strlen(data) : 0));
++
++ au_fsync_br(sb);
++
++ err = 0;
++ root = sb->s_root;
++ if (!data || !*data) {
++ aufs_write_lock(root);
++ err = verify_opts(sb, *flags, /*pending*/0, /*remount*/1);
++ aufs_write_unlock(root);
++ goto out; /* success */
++ }
++
++ err = -ENOMEM;
++ memset(&opts, 0, sizeof(opts));
++ opts.opt = (void *)__get_free_page(GFP_NOFS);
++ if (unlikely(!opts.opt))
++ goto out;
++ opts.max_opt = PAGE_SIZE / sizeof(*opts.opt);
++ opts.flags = AuOpts_REMOUNT;
++ opts.sb_flags = *flags;
++
++ /* parse it before aufs lock */
++ err = au_opts_parse(sb, data, &opts);
++ if (unlikely(err))
++ goto out_opts;
++
++ sbinfo = au_sbi(sb);
++ inode = root->d_inode;
++ vfsub_i_lock(inode);
++ aufs_write_lock(root);
++
++ /* au_do_opts() may return an error */
++ err = au_opts_remount(sb, &opts);
++ au_opts_free(&opts);
++
++ if (au_ftest_opts(opts.flags, REFRESH_DIR)
++ || au_ftest_opts(opts.flags, REFRESH_NONDIR)) {
++ dlgt = !!au_opt_test(sbinfo->si_mntflags, DLGT);
++ au_opt_clr(sbinfo->si_mntflags, DLGT);
++ au_sigen_inc(sb);
++ au_reset_hinotify(inode, au_hi_flags(inode, /*isdir*/1));
++ sigen = au_sigen(sb);
++ au_fclr_si(sbinfo, FAILED_REFRESH_DIRS);
++
++ DiMustNoWaiters(root);
++ IiMustNoWaiters(root->d_inode);
++ di_write_unlock(root);
++
++ rerr = refresh_dir(root, sigen);
++ if (unlikely(rerr)) {
++ au_fset_si(sbinfo, FAILED_REFRESH_DIRS);
++ AuWarn("Refreshing directories failed, ignores (%d)\n",
++ rerr);
++ }
++
++ if (au_ftest_opts(opts.flags, REFRESH_NONDIR)) {
++ rerr = refresh_nondir(root, sigen, !rerr);
++ if (unlikely(rerr))
++ AuWarn("Refreshing non-directories failed,"
++ " ignores (%d)\n", rerr);
++ }
++
++ /* aufs_write_lock() calls ..._child() */
++ di_write_lock_child(root);
++
++ au_cpup_attr_all(inode, /*force*/1);
++ if (dlgt)
++ au_opt_set(sbinfo->si_mntflags, DLGT);
++ }
++
++ aufs_write_unlock(root);
++ vfsub_i_unlock(inode);
++
++ out_opts:
++ free_page((unsigned long)opts.opt);
++ out:
++ err = cvt_err(err);
++ AuTraceErr(err);
++ return err;
++}
++
++static struct super_operations aufs_sop = {
++ .alloc_inode = aufs_alloc_inode,
++ .destroy_inode = aufs_destroy_inode,
++ .read_inode = aufs_read_inode,
++ //.dirty_inode = aufs_dirty_inode,
++ //.write_inode = aufs_write_inode,
++ //void (*put_inode) (struct inode *);
++ .drop_inode = generic_delete_inode,
++ //.delete_inode = aufs_delete_inode,
++ //.clear_inode = aufs_clear_inode,
++
++ .show_options = aufs_show_options,
++ .statfs = aufs_statfs,
++
++ .put_super = aufs_put_super,
++ //void (*write_super) (struct super_block *);
++ //int (*sync_fs)(struct super_block *sb, int wait);
++ //void (*write_super_lockfs) (struct super_block *);
++ //void (*unlockfs) (struct super_block *);
++ .remount_fs = aufs_remount_fs,
++ /* depends upon umount flags. also use put_super() (< 2.6.18) */
++ .umount_begin = aufs_umount_begin
++};
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * at first mount time.
++ */
++
++static int alloc_root(struct super_block *sb)
++{
++ int err;
++ struct inode *inode;
++ struct dentry *root;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ inode = iget(sb, AUFS_ROOT_INO);
++ //if (LktrCond) {iput(inode); inode = NULL;}
++ if (unlikely(!inode))
++ goto out;
++ err = PTR_ERR(inode);
++ if (IS_ERR(inode))
++ goto out;
++ err = -ENOMEM;
++ if (unlikely(is_bad_inode(inode)))
++ goto out_iput;
++
++ inode->i_op = &aufs_dir_iop;
++ inode->i_fop = &aufs_dir_fop;
++ inode->i_mode = S_IFDIR;
++ root = d_alloc_root(inode);
++ //if (LktrCond) {igrab(inode); dput(root); root = NULL;}
++ if (unlikely(!root))
++ goto out_iput;
++ err = PTR_ERR(root);
++ if (IS_ERR(root))
++ goto out_iput;
++
++ err = au_alloc_dinfo(root);
++ if (!err) {
++ sb->s_root = root;
++ return 0; /* success */
++ }
++ dput(root);
++ goto out; /* do not iput */
++
++ out_iput:
++ iput(inode);
++ out:
++ AuTraceErr(err);
++ return err;
++
++}
++
++static int aufs_fill_super(struct super_block *sb, void *raw_data, int silent)
++{
++ int err;
++ struct dentry *root;
++ struct inode *inode;
++ struct au_opts opts;
++ char *arg = raw_data;
++
++ if (unlikely(!arg || !*arg)) {
++ err = -EINVAL;
++ AuErr("no arg\n");
++ goto out;
++ }
++ LKTRTrace("%s, silent %d\n", arg, silent);
++
++ err = -ENOMEM;
++ memset(&opts, 0, sizeof(opts));
++ opts.opt = (void *)__get_free_page(GFP_NOFS);
++ if (unlikely(!opts.opt))
++ goto out;
++ opts.max_opt = PAGE_SIZE / sizeof(*opts.opt);
++ opts.sb_flags = sb->s_flags;
++
++ err = au_si_alloc(sb);
++ if (unlikely(err))
++ goto out_opts;
++ SiMustWriteLock(sb);
++
++ /* all timestamps always follow the ones on the branch */
++ sb->s_flags |= MS_NOATIME | MS_NODIRATIME;
++ sb->s_op = &aufs_sop;
++ sb->s_magic = AUFS_SUPER_MAGIC;
++ au_export_init(sb);
++
++ err = alloc_root(sb);
++ if (unlikely(err)) {
++ AuDebugOn(sb->s_root);
++ si_write_unlock(sb);
++ goto out_info;
++ }
++ root = sb->s_root;
++ DiMustWriteLock(root);
++ inode = root->d_inode;
++ inode->i_nlink = 2;
++
++ /*
++ * actually we can parse options regardless aufs lock here.
++ * but at remount time, parsing must be done before aufs lock.
++ * so we follow the same rule.
++ */
++ ii_write_lock_parent(inode);
++ au_dbg_locked_si_reg(sb, 1);
++ aufs_write_unlock(root);
++ err = au_opts_parse(sb, arg, &opts);
++ if (unlikely(err))
++ goto out_root;
++
++ /* lock vfs_inode first, then aufs. */
++ vfsub_i_lock(inode);
++ inode->i_op = &aufs_dir_iop;
++ inode->i_fop = &aufs_dir_fop;
++ aufs_write_lock(root);
++
++ sb->s_maxbytes = 0;
++ err = au_opts_mount(sb, &opts);
++ au_opts_free(&opts);
++ if (unlikely(err))
++ goto out_unlock;
++ AuDebugOn(!sb->s_maxbytes);
++
++ aufs_write_unlock(root);
++ vfsub_i_unlock(inode);
++ goto out_opts; /* success */
++
++ out_unlock:
++ aufs_write_unlock(root);
++ vfsub_i_unlock(inode);
++ out_root:
++ dput(root);
++ sb->s_root = NULL;
++ out_info:
++ au_si_free(sb, /*err*/1);
++ sb->s_fs_info = NULL;
++ out_opts:
++ free_page((unsigned long)opts.opt);
++ out:
++ AuTraceErr(err);
++ err = cvt_err(err);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++static int aufs_get_sb(struct file_system_type *fs_type, int flags,
++ const char *dev_name, void *raw_data,
++ struct vfsmount *mnt)
++{
++ int err;
++
++ /* all timestamps always follow the ones on the branch */
++ /* mnt->mnt_flags |= MNT_NOATIME | MNT_NODIRATIME; */
++ err = get_sb_nodev(fs_type, flags, raw_data, aufs_fill_super, mnt);
++ if (!err) {
++ struct super_block *sb = mnt->mnt_sb;
++ struct au_sbinfo *sbinfo = au_sbi(sb);
++ sbinfo->si_mnt = mnt;
++
++ au_sbilist_lock();
++ au_sbilist_add(sbinfo);
++ si_write_lock(sb);
++ sysaufs_sbi_add(sb);
++ si_write_unlock(sb);
++ au_sbilist_unlock();
++ }
++ return err;
++}
++#else
++static struct super_block *aufs_get_sb(struct file_system_type *fs_type,
++ int flags, const char *dev_name,
++ void *raw_data)
++{
++ return get_sb_nodev(fs_type, flags, raw_data, aufs_fill_super);
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18) */
++
++struct file_system_type aufs_fs_type = {
++ .name = AUFS_FSTYPE,
++ .fs_flags =
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++ FS_RENAME_DOES_D_MOVE | /* a race between rename and others */
++#endif
++ FS_REVAL_DOT, /* for NFS branch and udba */
++ .get_sb = aufs_get_sb,
++ .kill_sb = generic_shutdown_super,
++ /* no need to __module_get() and module_put(). */
++ .owner = THIS_MODULE,
++};
+diff --git a/fs/aufs/super.h b/fs/aufs/super.h
+new file mode 100644
+index 0000000..02acd04
+--- /dev/null
++++ b/fs/aufs/super.h
+@@ -0,0 +1,579 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * super_block operations
++ *
++ * $Id: super.h,v 1.91 2009/01/26 06:24:15 sfjro Exp $
++ */
++
++#ifndef __AUFS_SUPER_H__
++#define __AUFS_SUPER_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/version.h>
++#include <linux/cramfs_fs.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++#include <linux/magic.h>
++#else
++#include <linux/nfs_fs.h>
++#endif
++#include <linux/aufs_type.h>
++//#include "hinode.h"
++#include "misc.h"
++//#include "opts.h"
++#include "wkq.h"
++
++typedef ssize_t (*au_readf_t)(struct file *, char __user *, size_t, loff_t *);
++typedef ssize_t (*au_writef_t)(struct file *, const char __user *, size_t,
++ loff_t *);
++
++struct au_wbr_copyup_operations {
++ int (*copyup)(struct dentry *dentry);
++};
++
++struct au_wbr_create_operations {
++ int (*create)(struct dentry *dentry, int isdir);
++ int (*init)(struct super_block *sb);
++ int (*fin)(struct super_block *sb);
++};
++
++struct au_wbr_mfs {
++ struct mutex mfs_lock; /* protect this structure */
++ unsigned long mfs_jiffy;
++ unsigned long mfs_expire;
++ aufs_bindex_t mfs_bindex;
++
++ unsigned long long mfsrr_bytes;
++ unsigned long long mfsrr_watermark;
++};
++
++/* sbinfo status flags */
++/*
++ * set true when refresh_dirs() failed at remount time.
++ * then try refreshing dirs at access time again.
++ * if it is false, refreshing dirs at access time is unnecesary
++ */
++#define AuSi_FAILED_REFRESH_DIRS 1
++#define au_ftest_si(sbinfo, name) ((sbinfo)->au_si_status & AuSi_##name)
++#define au_fset_si(sbinfo, name) \
++ { (sbinfo)->au_si_status |= AuSi_##name; }
++#define au_fclr_si(sbinfo, name) \
++ { (sbinfo)->au_si_status &= ~AuSi_##name; }
++
++struct sysaufs_sbinfo;
++struct au_branch;
++struct au_sbinfo {
++ /* nowait tasks in the system-wide workqueue */
++ struct au_nowait_tasks si_nowait;
++
++ struct au_rwsem si_rwsem;
++
++ /* branch management */
++ au_gen_t si_generation;
++
++ /* see above flags */
++ unsigned char au_si_status;
++
++ aufs_bindex_t si_bend;
++ aufs_bindex_t si_last_br_id;
++ struct au_branch **si_branch;
++
++ /* policy to select a writable branch */
++ unsigned char si_wbr_copyup;
++ unsigned char si_wbr_create;
++ struct au_wbr_copyup_operations *si_wbr_copyup_ops;
++ struct au_wbr_create_operations *si_wbr_create_ops;
++
++ /* round robin */
++ atomic_t si_wbr_rr_next;
++
++ /* most free space */
++ struct au_wbr_mfs si_wbr_mfs;
++
++ /* mount flags */
++ /* include/asm-ia64/siginfo.h defines a macro named si_flags */
++ unsigned int si_mntflags;
++
++ /* external inode number (bitmap and translation table) */
++ au_readf_t si_xread;
++ au_writef_t si_xwrite;
++ struct file *si_xib;
++ struct mutex si_xib_mtx; /* protect xib members */
++ unsigned long *si_xib_buf;
++ unsigned long si_xib_last_pindex;
++ int si_xib_next_bit;
++ /* reserved for future use */
++ /* unsigned long long si_xib_limit; */ /* Max xib file size */
++
++#ifdef CONFIG_AUFS_HINOTIFY
++ struct au_branch *si_xino_def_br;
++#endif
++
++#ifdef CONFIG_AUFS_EXPORT
++ /* i_generation */
++ struct file *si_xigen;
++ atomic_t si_xigen_next;
++#endif
++
++ /* readdir cache time, max, in HZ */
++ unsigned long si_rdcache;
++
++ /*
++ * If the number of whiteouts are larger than si_dirwh, leave all of
++ * them after au_whtmp_ren to reduce the cost of rmdir(2).
++ * future fsck.aufs or kernel thread will remove them later.
++ * Otherwise, remove all whiteouts and the dir in rmdir(2).
++ */
++ unsigned int si_dirwh;
++
++ /*
++ * rename(2) a directory with all children.
++ */
++ /* reserved for future use */
++ /* int si_rendir; */
++
++ /* pseudo_link list */ /* todo: dirty? */
++ struct au_splhead si_plink;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++ struct vfsmount *si_mnt; /* no get/put */
++#endif
++
++ /* sysfs */
++#ifdef CONFIG_AUFS_SYSAUFS
++ /* super_blocks list is not exported */
++ struct list_head si_list;
++ struct sysaufs_sbinfo *si_sa;
++#endif
++
++#ifdef CONFIG_AUFS_ROBR
++ /* locked vma list for mmap() */ // very dirty
++ struct au_splhead si_lvma;
++#endif
++
++#if 0 //def CONFIG_AUFS_EXPORT /* reserved for future use */
++ struct path si_xinodir;
++#endif
++
++#ifdef CONFIG_AUFS_DEBUG_LOCK
++ struct au_splhead si_dbg_lock[AuDbgLock_Last];
++#endif
++};
++
++/* ---------------------------------------------------------------------- */
++
++/* policy to select one among writable branches */
++#define AuWbrCopyup(sbinfo, args...) \
++ ((sbinfo)->si_wbr_copyup_ops->copyup(args))
++#define AuWbrCreate(sbinfo, args...) \
++ ((sbinfo)->si_wbr_create_ops->create(args))
++
++/* flags for si_read_lock()/aufs_read_lock()/di_read_lock() */
++#define AuLock_DW 1 /* write-lock dentry */
++#define AuLock_IR (1 << 1) /* read-lock inode */
++#define AuLock_IW (1 << 2) /* write-lock inode */
++#define AuLock_FLUSH (1 << 3) /* wait for 'nowait' tasks */
++#define AuLock_DIR (1 << 4) /* target is a dir */
++#define au_ftest_lock(flags, name) ((flags) & AuLock_##name)
++#define au_fset_lock(flags, name) { (flags) |= AuLock_##name; }
++#define au_fclr_lock(flags, name) { (flags) &= ~AuLock_##name; }
++
++/* ---------------------------------------------------------------------- */
++
++/* super.c */
++extern struct file_system_type aufs_fs_type;
++
++/* sbinfo.c */
++void au_si_free(struct super_block *sb, int err);
++int au_si_alloc(struct super_block *sb);
++struct au_branch *au_sbr(struct super_block *sb, aufs_bindex_t bindex);
++au_gen_t au_sigen_inc(struct super_block *sb);
++int au_find_bindex(struct super_block *sb, struct au_branch *br);
++
++void aufs_read_lock(struct dentry *dentry, int flags);
++void aufs_read_unlock(struct dentry *dentry, int flags);
++void aufs_write_lock(struct dentry *dentry);
++void aufs_write_unlock(struct dentry *dentry);
++void aufs_read_and_write_lock2(struct dentry *d1, struct dentry *d2, int isdir);
++void aufs_read_and_write_unlock2(struct dentry *d1, struct dentry *d2);
++
++aufs_bindex_t au_new_br_id(struct super_block *sb);
++
++/* wbr_policy.c */
++extern struct au_wbr_copyup_operations au_wbr_copyup_ops[];
++extern struct au_wbr_create_operations au_wbr_create_ops[];
++int au_cpdown_dirs(struct dentry *dentry, aufs_bindex_t bdst);
++
++/* ---------------------------------------------------------------------- */
++
++#if 0 //LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)
++static inline int au_mnt_want_write(struct vfsmount *h_mnt)
++{
++ return mnt_want_write(h_mnt);
++}
++
++static inline void au_mnt_drop_write(struct vfsmount *h_mnt)
++{
++ mnt_drop_write(h_mnt);
++}
++#else
++static inline int au_mnt_want_write(struct vfsmount *h_mnt)
++{
++ return 0;
++}
++
++static inline void au_mnt_drop_write(struct vfsmount *h_mnt)
++{
++ /* empty */
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++static inline struct au_sbinfo *au_sbi(struct super_block *sb)
++{
++ return sb->s_fs_info;
++}
++
++static inline const char *au_sbtype(struct super_block *sb)
++{
++ return sb->s_type->name;
++}
++
++static inline int au_test_aufs(struct super_block *sb)
++{
++ return sb->s_magic == AUFS_SUPER_MAGIC;
++}
++
++static inline int au_test_nfs(struct super_block *sb)
++{
++#ifdef CONFIG_AUFS_BR_NFS
++ return sb->s_magic == NFS_SUPER_MAGIC;
++#else
++ return 0;
++#endif
++}
++
++static inline int au_test_nfs4(struct super_block *sb)
++{
++#ifdef CONFIG_AUFS_BR_NFS_V4
++ return au_test_nfs(sb) && !strcmp(sb->s_type->name, "nfs4");
++#else
++ return 0;
++#endif
++}
++
++static inline int au_test_fuse(struct super_block *sb)
++{
++#ifdef CONFIG_AUFS_WORKAROUND_FUSE
++ return sb->s_magic == FUSE_SUPER_MAGIC;
++#else
++ return 0;
++#endif
++}
++
++static inline int au_test_xfs(struct super_block *sb)
++{
++#ifdef CONFIG_AUFS_BR_XFS
++ return sb->s_magic == XFS_SB_MAGIC;
++#else
++ return 0;
++#endif
++}
++
++static inline int au_test_tmpfs(struct super_block *sb)
++{
++#ifdef CONFIG_TMPFS
++ return sb->s_magic == TMPFS_MAGIC;
++#else
++ return 0;
++#endif
++}
++
++static inline int au_test_ecryptfs(struct super_block *sb)
++{
++#if defined(CONFIG_ECRYPT_FS) || defined(CONFIG_ECRYPT_FS_MODULE)
++ /* why don't they use s_magic? */
++ return !strcmp(sb->s_type->name, "ecryptfs");
++#else
++ return 0;
++#endif
++}
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_HINOTIFY
++static inline void au_xino_def_br_set(struct au_branch *br,
++ struct au_sbinfo *sbinfo)
++{
++ sbinfo->si_xino_def_br = br;
++}
++
++static inline struct au_branch *au_xino_def_br(struct au_sbinfo *sbinfo)
++{
++ return sbinfo->si_xino_def_br;
++}
++#else
++static inline void au_xino_def_br_set(struct au_branch *br,
++ struct au_sbinfo *sbinfo)
++{
++ /* empty */
++}
++
++static inline struct au_branch *au_xino_def_br(struct au_sbinfo *sbinfo)
++{
++ return NULL;
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_EXPORT
++void au_export_init(struct super_block *sb);
++
++static inline int au_test_nfsd(struct task_struct *tsk)
++{
++ return !tsk->mm && !strcmp(tsk->comm, "nfsd");
++}
++
++static inline void au_export_put(struct au_sbinfo *sbinfo)
++{
++#if 0 /* reserved for future use */
++ path_put(&sbinfo->si_xinodir);
++#endif
++}
++
++int au_xigen_inc(struct inode *inode);
++int au_xigen_new(struct inode *inode);
++int au_xigen_set(struct super_block *sb, struct file *base);
++void au_xigen_clr(struct super_block *sb);
++#else
++static inline void au_export_init(struct super_block *sb)
++{
++ /* nothing */
++}
++
++static inline int au_test_nfsd(struct task_struct *tsk)
++{
++ return 0;
++}
++
++static inline void au_export_put(struct au_sbinfo *sbinfo)
++{
++ /* nothing */
++}
++
++static inline int au_xigen_inc(struct inode *inode)
++{
++ return 0;
++}
++
++static inline int au_xigen_new(struct inode *inode)
++{
++ return 0;
++}
++
++static inline int au_xigen_set(struct super_block *sb, struct file *base)
++{
++ return 0;
++}
++
++static inline void au_xigen_clr(struct super_block *sb)
++{
++ /* empty */
++}
++#endif /* CONFIG_AUFS_EXPORT */
++
++#ifdef CONFIG_AUFS_ROBR
++static inline int au_test_nested(struct super_block *h_sb)
++{
++ return 0;
++}
++
++static inline void au_robr_lvma_init(struct au_sbinfo *sbinfo)
++{
++ au_spl_init(&sbinfo->si_lvma);
++}
++#else
++static inline int au_test_nested(struct super_block *h_sb)
++{
++ int err = 0;
++ if (unlikely(au_test_aufs(h_sb))) {
++ err = -EINVAL;
++ AuTraceErr(err);
++ }
++ return err;
++}
++
++static inline void au_robr_lvma_init(struct au_sbinfo *sbinfo)
++{
++ /* empty */
++}
++#endif /* CONFIG_AUFS_ROBR */
++
++/* ---------------------------------------------------------------------- */
++
++/* lock superblock. mainly for entry point functions */
++/*
++ * si_do_noflush_read_lock, si_do_noflush_write_lock,
++ * si_do_read_unlock, si_do_write_unlock, si_do_downgrade_lock
++ */
++AuSimpleLockRwsemFuncs(si_do_noflush, struct super_block *sb,
++ au_sbi(sb)->si_rwsem);
++AuSimpleUnlockRwsemFuncs(si_do, struct super_block *sb, au_sbi(sb)->si_rwsem);
++
++static inline void si_noflush_read_lock(struct super_block *sb)
++{
++ au_dbg_locking_si_reg(sb, 0);
++ si_do_noflush_read_lock(sb);
++ au_dbg_locking_si_unreg(sb, 0);
++ au_dbg_locked_si_reg(sb, 0);
++}
++
++static inline void si_noflush_write_lock(struct super_block *sb)
++{
++ au_dbg_locking_si_reg(sb, 1);
++ si_do_noflush_write_lock(sb);
++ au_dbg_locking_si_unreg(sb, 1);
++ au_dbg_locked_si_reg(sb, 1);
++}
++
++static inline int si_noflush_read_trylock(struct super_block *sb)
++{
++ int locked;
++
++ au_dbg_locking_si_reg(sb, 0);
++ locked = si_do_noflush_read_trylock(sb);
++ au_dbg_locking_si_unreg(sb, 0);
++ if (locked)
++ au_dbg_locked_si_reg(sb, 0);
++ return locked;
++}
++
++static inline int si_noflush_write_trylock(struct super_block *sb)
++{
++ int locked;
++
++ au_dbg_locking_si_reg(sb, 1);
++ locked = si_do_noflush_write_trylock(sb);
++ au_dbg_locking_si_unreg(sb, 1);
++ if (locked)
++ au_dbg_locked_si_reg(sb, 1);
++ return locked;
++}
++
++static inline void si_read_unlock(struct super_block *sb)
++{
++ si_do_read_unlock(sb);
++ au_dbg_locked_si_unreg(sb, 0);
++}
++
++static inline void si_write_unlock(struct super_block *sb)
++{
++ si_do_write_unlock(sb);
++ au_dbg_locked_si_unreg(sb, 1);
++}
++
++static inline void si_downgrade_lock(struct super_block *sb)
++{
++ si_do_downgrade_lock(sb);
++}
++
++static inline void si_read_lock(struct super_block *sb, int flags)
++{
++ if (/* !au_test_nfsd(current) && */au_ftest_lock(flags, FLUSH))
++ au_nwt_flush(&au_sbi(sb)->si_nowait);
++ si_noflush_read_lock(sb);
++}
++
++static inline void si_write_lock(struct super_block *sb)
++{
++ //WARN_ON(au_test_nfsd(current));
++ au_nwt_flush(&au_sbi(sb)->si_nowait);
++ si_noflush_write_lock(sb);
++}
++
++static inline int si_read_trylock(struct super_block *sb, int flags)
++{
++ if (/* !au_test_nfsd(current) && */au_ftest_lock(flags, FLUSH))
++ au_nwt_flush(&au_sbi(sb)->si_nowait);
++ return si_noflush_read_trylock(sb);
++}
++
++static inline int si_write_trylock(struct super_block *sb, int flags)
++{
++ if (/* !au_test_nfsd(current) && */au_ftest_lock(flags, FLUSH))
++ au_nwt_flush(&au_sbi(sb)->si_nowait);
++ return si_noflush_write_trylock(sb);
++}
++
++/* to debug easier, do not make them inlined functions */
++#define SiMustReadLock(sb) AuRwMustReadLock(&au_sbi(sb)->si_rwsem)
++#define SiMustWriteLock(sb) AuRwMustWriteLock(&au_sbi(sb)->si_rwsem)
++#define SiMustAnyLock(sb) AuRwMustAnyLock(&au_sbi(sb)->si_rwsem)
++
++/* ---------------------------------------------------------------------- */
++
++static inline aufs_bindex_t au_sbend(struct super_block *sb)
++{
++ SiMustAnyLock(sb);
++ return au_sbi(sb)->si_bend;
++}
++
++static inline unsigned int au_mntflags(struct super_block *sb)
++{
++ SiMustAnyLock(sb);
++ return au_sbi(sb)->si_mntflags;
++}
++
++static inline au_gen_t au_sigen(struct super_block *sb)
++{
++ SiMustAnyLock(sb);
++ return au_sbi(sb)->si_generation;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* limited support before 2.6.18 */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++static inline void au_mntget(struct super_block *sb)
++{
++ mntget(au_sbi(sb)->si_mnt);
++}
++
++static inline void au_mntput(struct super_block *sb)
++{
++ mntput(au_sbi(sb)->si_mnt);
++}
++#else
++static inline void au_mntget(struct super_block *sb)
++{
++ /* empty */
++}
++
++static inline void au_mntput(struct super_block *sb)
++{
++ /* empty */
++}
++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18) */
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_SUPER_H__ */
+diff --git a/fs/aufs/sysaufs.c b/fs/aufs/sysaufs.c
+new file mode 100644
+index 0000000..422c7e5
+--- /dev/null
++++ b/fs/aufs/sysaufs.c
+@@ -0,0 +1,752 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * sysfs interface
++ *
++ * $Id: sysaufs.c,v 1.46 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/fs.h>
++#include <linux/module.h>
++#include <linux/seq_file.h>
++#include <linux/sysfs.h>
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++/* super_blocks list is not exported */
++DEFINE_MUTEX(au_sbilist_mtx);
++LIST_HEAD(au_sbilist);
++
++static decl_subsys(aufs, NULL, NULL);
++enum {
++ Sbi, Stat, Config,
++#ifdef CONFIG_AUFS_DEBUG
++ Debug,
++#endif
++ _Last
++};
++
++static ssize_t config_show(au_subsys_t *subsys, char *buf)
++{
++ //struct kset *kset = &au_subsys_to_kset(*subsys);
++#define conf_bool(name) "CONFIG_AUFS_" #name "=y\n"
++ static const char opt[] =
++#ifdef CONFIG_AUFS
++ "CONFIG_AUFS=y\n"
++#else
++ "CONFIG_AUFS=m\n"
++#endif
++#ifdef CONFIG_AUFS_BRANCH_MAX_127
++ conf_bool(BRANCH_MAX_127)
++#elif defined(CONFIG_AUFS_BRANCH_MAX_511)
++ conf_bool(BRANCH_MAX_511)
++#elif defined(CONFIG_AUFS_BRANCH_MAX_1023)
++ conf_bool(BRANCH_MAX_1023)
++#elif defined(CONFIG_AUFS_BRANCH_MAX_32767)
++ conf_bool(BRANCH_MAX_32767)
++#endif
++ conf_bool(SYSAUFS)
++#ifdef CONFIG_AUFS_HINOTIFY
++ conf_bool(HINOTIFY)
++#endif
++#ifdef CONFIG_AUFS_EXPORT
++ conf_bool(EXPORT)
++#endif
++#ifdef CONFIG_AUFS_INO_T_64
++ conf_bool(INO_T_64)
++#endif
++#ifdef CONFIG_AUFS_ROBR
++ conf_bool(ROBR)
++#endif
++#ifdef CONFIG_AUFS_DLGT
++ conf_bool(DLGT)
++#endif
++#ifdef CONFIG_AUFS_HIN_OR_DLGT
++ conf_bool(HIN_OR_DLGT)
++#endif
++#ifdef CONFIG_AUFS_SHWH
++ conf_bool(SHWH)
++#endif
++#ifdef CONFIG_AUFS_RR_SQUASHFS
++ conf_bool(RR_SQUASHFS)
++#endif
++#ifdef CONFIG_AUFS_SEC_PERM_PATCH
++ conf_bool(SEC_PERM_PATCH)
++#endif
++#ifdef CONFIG_AUFS_SPLICE_PATCH
++ conf_bool(SPLICE_PATCH)
++#endif
++#ifdef CONFIG_AUFS_LHASH_PATCH
++ conf_bool(LHASH_PATCH)
++#endif
++#ifdef CONFIG_AUFS_PUT_FILP_PATCH
++ conf_bool(PUT_FILP_PATCH)
++#endif
++#ifdef CONFIG_AUFS_BR_NFS
++ conf_bool(BR_NFS)
++#endif
++#ifdef CONFIG_AUFS_BR_NFS_V4
++ conf_bool(BR_NFS_V4)
++#endif
++#ifdef CONFIG_AUFS_BR_XFS
++ conf_bool(BR_XFS)
++#endif
++#ifdef CONFIG_AUFS_FSYNC_SUPER_PATCH
++ conf_bool(FSYNC_SUPER_PATCH)
++#endif
++#ifdef CONFIG_AUFS_DENY_WRITE_ACCESS_PATCH
++ conf_bool(DENY_WRITE_ACCESS_PATCH)
++#endif
++#ifdef CONFIG_AUFS_KSIZE_PATCH
++ conf_bool(KSIZE_PATCH)
++#endif
++#ifdef CONFIG_AUFS_WORKAROUND_FUSE
++ conf_bool(WORKAROUND_FUSE)
++#endif
++#ifdef CONFIG_AUFS_GETATTR
++ conf_bool(GETATTR)
++#endif
++#ifdef CONFIG_AUFS_DEBUG
++ conf_bool(DEBUG)
++#endif
++#ifdef CONFIG_AUFS_MAGIC_SYSRQ
++ conf_bool(MAGIC_SYSRQ)
++#endif
++#ifdef CONFIG_AUFS_DEBUG_LOCK
++ conf_bool(DEBUG_LOCK)
++#endif
++#ifdef CONFIG_AUFS_COMPAT
++ conf_bool(COMPAT)
++#endif
++#ifdef CONFIG_AUFS_UNIONFS23_PATCH
++ conf_bool(UNIONFS23_PATCH)
++#endif
++ ;
++#undef conf_bool
++
++ char *p = buf;
++ const char *end = buf + PAGE_SIZE;
++
++ p += snprintf(p, end - p, "%s", opt);
++#ifdef DbgUdbaRace
++ if (p < end)
++ p += snprintf(p, end - p, "DbgUdbaRace=%d\n", DbgUdbaRace);
++#endif
++ if (p < end)
++ return p - buf;
++ else
++ return -EFBIG;
++}
++
++static ssize_t stat_show(au_subsys_t *subsys, char *buf)
++{
++ //struct kset *kset = &au_subsys_to_kset(*subsys);
++ char *p = buf;
++ const char *end = buf + PAGE_SIZE;
++ int i;
++
++ p += snprintf(p, end - p, "wkq max_busy:");
++ for (i = 0; p < end && i < aufs_nwkq; i++)
++ p += snprintf(p, end - p, " %u", atomic_read(&au_wkq[i].max_busy));
++ if (p < end)
++ p += snprintf(p, end - p, ", %u(generic)\n",
++ atomic_read(&au_wkq[aufs_nwkq].max_busy));
++
++ if (p < end)
++ return p - buf;
++ else
++ return -EFBIG;
++}
++
++static ssize_t sbi_show(au_subsys_t *subsys, char *buf)
++{
++ //struct kset *kset = &au_subsys_to_kset(*subsys);
++ char *p = buf;
++ const char *end = buf + PAGE_SIZE;
++ struct au_sbinfo *sbinfo;
++
++ /* this order is important */
++ mutex_lock(&au_sbilist_mtx);
++ list_for_each_entry(sbinfo, &au_sbilist, si_list)
++ if (p < end)
++ p += snprintf(p, end - p, "%p\n", sbinfo);
++ mutex_unlock(&au_sbilist_mtx);
++
++ if (p < end)
++ return p - buf;
++ else
++ return -EFBIG;
++}
++
++#ifdef CONFIG_AUFS_DEBUG
++static ssize_t debug_show(au_subsys_t *subsys, char *buf)
++{
++ //struct kset *kset = &au_subsys_to_kset(*subsys);
++ return sprintf(buf, "%d\n", au_debug_test());
++}
++
++static ssize_t debug_store(au_subsys_t *subsys, const char *buf, size_t sz)
++{
++ //struct kset *kset = &au_subsys_to_kset(*subsys);
++
++ LKTRTrace("%.*s\n", (unsigned int)sz, buf);
++
++ if (unlikely(!sz || (*buf != '0' && *buf != '1')))
++ return -EOPNOTSUPP;
++
++ if (*buf == '0')
++ au_debug_off();
++ else if (*buf == '1')
++ au_debug_on();
++ return sz;
++}
++#endif
++
++static struct subsys_attribute sysaufs_entry[] = {
++ [Config] = __ATTR_RO(config),
++ [Stat] = __ATTR_RO(stat),
++ [Sbi] = __ATTR_RO(sbi),
++#ifdef CONFIG_AUFS_DEBUG
++ [Debug] = __ATTR(debug, S_IRUGO | S_IWUSR, debug_show,
++ debug_store)
++#endif
++};
++static struct attribute *sysaufs_attr[_Last + 1]; /* last NULL */
++static struct attribute_group sysaufs_attr_group = {
++ .attrs = sysaufs_attr,
++};
++
++/* ---------------------------------------------------------------------- */
++
++typedef int (*sysaufs_sbi_sub_show_t)(struct seq_file *seq,
++ struct super_block *sb);
++
++static int sysaufs_sbi_xi(struct seq_file *seq, struct file *xf, int dlgt,
++ int print_path)
++{
++ int err;
++ struct kstat st;
++
++ err = vfsub_getattr(xf->f_vfsmnt, xf->f_dentry, &st, dlgt);
++ if (!err) {
++ seq_printf(seq, "%llux%lu %lld",
++ st.blocks, st.blksize, (long long)st.size);
++ if (print_path) {
++ seq_putc(seq, ' ');
++ seq_path(seq, xf->f_vfsmnt, xf->f_dentry, au_esc_chars);
++ }
++ seq_putc(seq, '\n');
++ } else
++ seq_printf(seq, "err %d\n", err);
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int sysaufs_sbi_xino(struct seq_file *seq, struct super_block *sb)
++{
++ int err;
++ unsigned int mnt_flags;
++ unsigned char dlgt, xinodir;
++ aufs_bindex_t bend, bindex;
++ struct kstat st;
++ struct au_sbinfo *sbinfo;
++ struct file *xf;
++
++ AuTraceEnter();
++
++ sbinfo = au_sbi(sb);
++ mnt_flags = au_mntflags(sb);
++ xinodir = !!au_opt_test(mnt_flags, XINODIR);
++ if (!au_opt_test(mnt_flags, XINO)) {
++#ifdef CONFIG_AUFS_DEBUG
++ AuDebugOn(sbinfo->si_xib);
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++)
++ AuDebugOn(au_sbr(sb, bindex)->br_xino.xi_file);
++#endif
++ err = 0;
++ goto out; /* success */
++ }
++
++ dlgt = !!au_test_dlgt(mnt_flags);
++ err = sysaufs_sbi_xi(seq, sbinfo->si_xib, dlgt, xinodir);
++
++ bend = au_sbend(sb);
++ for (bindex = 0; !err && bindex <= bend; bindex++) {
++ xf = au_sbr(sb, bindex)->br_xino.xi_file;
++ if (!xf)
++ continue;
++ seq_printf(seq, "%d: ", bindex);
++ err = vfsub_getattr(xf->f_vfsmnt, xf->f_dentry, &st, dlgt);
++ if (!err)
++ seq_printf(seq, "%d, %Lux%lu %Ld\n",
++ file_count(xf), st.blocks, st.blksize,
++ (long long)st.size);
++ else
++ seq_printf(seq, "err %d\n", err);
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++#ifdef CONFIG_AUFS_EXPORT
++static int sysaufs_sbi_xigen(struct seq_file *seq, struct super_block *sb)
++{
++ int err;
++ unsigned int mnt_flags;
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++
++ err = 0;
++ sbinfo = au_sbi(sb);
++ mnt_flags = au_mntflags(sb);
++ if (au_opt_test_xino(mnt_flags))
++ err = sysaufs_sbi_xi(seq, sbinfo->si_xigen,
++ !!au_opt_test(mnt_flags, DLGT),
++ !!au_opt_test(mnt_flags, XINODIR));
++
++ AuTraceErr(err);
++ return err;
++}
++#endif
++
++static int sysaufs_sbi_mntpnt1(struct seq_file *seq, struct super_block *sb)
++{
++ AuTraceEnter();
++
++ seq_path(seq, au_sbi(sb)->si_mnt, sb->s_root, au_esc_chars);
++ seq_putc(seq, '\n');
++
++ return 0;
++}
++
++#define SysaufsBr_PREFIX "br"
++static int sysaufs_sbi_br(struct seq_file *seq, struct super_block *sb,
++ aufs_bindex_t bindex)
++{
++ int err;
++ struct dentry *root;
++ struct au_branch *br;
++
++ LKTRTrace("b%d\n", bindex);
++
++ err = -ENOENT;
++ if (unlikely(au_sbend(sb) < bindex))
++ goto out;
++
++ err = 0;
++ root = sb->s_root;
++ di_read_lock_parent(root, !AuLock_IR);
++ br = au_sbr(sb, bindex);
++ seq_path(seq, br->br_mnt, au_h_dptr(root, bindex), au_esc_chars);
++ di_read_unlock(root, !AuLock_IR);
++ seq_printf(seq, "=%s\n", au_optstr_br_perm(br->br_perm));
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static struct sysaufs_sbi_entry {
++ char *name;
++ sysaufs_sbi_sub_show_t show;
++} sysaufs_sbi_entry[SysaufsSb_Last] = {
++ [SysaufsSb_XINO] = {
++ .name = "xino",
++ .show = sysaufs_sbi_xino
++ },
++#ifdef CONFIG_AUFS_EXPORT
++ [SysaufsSb_XIGEN] = {
++ .name = "xigen",
++ .show = sysaufs_sbi_xigen
++ },
++#endif
++ [SysaufsSb_MNTPNT1] = {
++ .name = "mntpnt1",
++ .show = sysaufs_sbi_mntpnt1
++ }
++};
++
++static struct super_block *find_sb_lock(struct kobject *kobj)
++{
++ struct super_block *sb;
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++ MtxMustLock(&au_sbilist_mtx);
++
++ sb = NULL;
++ list_for_each_entry(sbinfo, &au_sbilist, si_list) {
++ if (&au_subsys_to_kset(sbinfo->si_sa->subsys).kobj != kobj)
++ continue;
++ sb = sbinfo->si_mnt->mnt_sb;
++ si_read_lock(sb, !AuLock_FLUSH);
++ break;
++ }
++ return sb;
++}
++
++static struct seq_file *au_seq(char *p, ssize_t len)
++{
++ struct seq_file *seq;
++
++ seq = kzalloc(sizeof(*seq), GFP_NOFS);
++ if (seq) {
++ //mutex_init(&seq.lock);
++ seq->buf = p;
++ seq->count = 0;
++ seq->size = len;
++ return seq; /* success */
++ }
++
++ seq = ERR_PTR(-ENOMEM);
++ AuTraceErrPtr(seq);
++ return seq;
++}
++
++//todo: file size may exceed PAGE_SIZE
++static ssize_t sysaufs_sbi_show(struct kobject *kobj, struct attribute *attr,
++ char *buf)
++{
++ ssize_t err;
++ struct super_block *sb;
++ struct seq_file *seq;
++ char *name;
++ int i;
++
++ LKTRTrace("%s/%s\n", kobject_name(kobj), attr->name);
++
++ err = -ENOENT;
++ mutex_lock(&au_sbilist_mtx);
++ sb = find_sb_lock(kobj);
++ if (unlikely(!sb))
++ goto out;
++
++ seq = au_seq(buf, PAGE_SIZE);
++ err = PTR_ERR(seq);
++ if (IS_ERR(seq))
++ goto out;
++
++ name = (void *)attr->name;
++ for (i = 0; i < SysaufsSb_Last; i++) {
++ if (!strcmp(name, sysaufs_sbi_entry[i].name)) {
++ err = sysaufs_sbi_entry[i].show(seq, sb);
++ goto out_seq;
++ }
++ }
++
++ if (!strncmp(name, SysaufsBr_PREFIX, sizeof(SysaufsBr_PREFIX) - 1)) {
++ name += sizeof(SysaufsBr_PREFIX) - 1;
++ err = sysaufs_sbi_br(seq, sb, simple_strtol(name, NULL, 10));
++ goto out_seq;
++ }
++ BUG();
++
++ out_seq:
++ if (!err) {
++ err = seq->count;
++ /* sysfs limit */
++ if (unlikely(err == PAGE_SIZE))
++ err = -EFBIG;
++ }
++ kfree(seq);
++ out:
++ si_read_unlock(sb);
++ mutex_unlock(&au_sbilist_mtx);
++ AuTraceErr(err);
++ return err;
++}
++
++static struct sysfs_ops sysaufs_sbi_ops = {
++ .show = sysaufs_sbi_show
++};
++
++static struct kobj_type sysaufs_sbi_ktype = {
++ //.release = dir_release,
++ .sysfs_ops = &sysaufs_sbi_ops
++};
++
++/* ---------------------------------------------------------------------- */
++
++static void sysaufs_br_free(struct kref *ref)
++{
++ AuTraceEnter();
++ //AuDbg("here\n");
++ kfree(container_of(ref, struct sysaufs_br, ref));
++}
++
++struct sysaufs_br *sysaufs_br_alloc(void)
++{
++ struct sysaufs_br *sabr;
++
++ AuTraceEnter();
++ //AuDbg("here\n");
++
++ sabr = kcalloc(sizeof(*sabr), 1, GFP_NOFS);
++ if (sabr)
++ kref_init(&sabr->ref);
++
++ AuTraceErrPtr(sabr);
++ return sabr;
++}
++
++void sysaufs_br_get(struct au_branch *br)
++{
++ kref_get(&br->br_sabr->ref);
++}
++
++void sysaufs_br_put(struct au_branch *br)
++{
++ kref_put(&br->br_sabr->ref, sysaufs_br_free);
++}
++
++//todo: they may take a long time
++void sysaufs_brs_del(struct super_block *sb)
++{
++ aufs_bindex_t bindex, bend;
++ struct sysaufs_sbinfo *sa;
++ struct sysaufs_br *sabr;
++ struct au_branch *br;
++
++ AuTraceEnter();
++
++ sa = au_sbi(sb)->si_sa;
++ if (!sysaufs_brs || !sa->added)
++ return;
++
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++) {
++ br = au_sbr(sb, bindex);
++ sabr = br->br_sabr;
++ if (unlikely(!sabr->added))
++ continue;
++
++ sabr->added = 0;
++ sysfs_remove_file(&au_subsys_to_kset(sa->subsys).kobj,
++ &sabr->attr);
++ sysaufs_br_put(br);
++ /* for older sysfs */
++ module_put(THIS_MODULE);
++ }
++}
++
++void sysaufs_brs_add(struct super_block *sb)
++{
++ int err;
++ aufs_bindex_t bindex, bend;
++ struct sysaufs_br *sabr;
++ struct sysaufs_sbinfo *sa;
++ struct au_branch *br;
++
++ AuTraceEnter();
++
++ sa = au_sbi(sb)->si_sa;
++ if (!sysaufs_brs || !sa->added)
++ return;
++
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++) {
++ br = au_sbr(sb, bindex);
++ sysaufs_br_get(br);
++ sabr = br->br_sabr;
++ AuDebugOn(sabr->added);
++ snprintf(sabr->name, sizeof(sabr->name),
++ SysaufsBr_PREFIX "%d", bindex);
++ sabr->attr.name = sabr->name;
++ sabr->attr.mode = 0444;
++ sabr->attr.owner = THIS_MODULE;
++ /* for older sysfs */
++ BUG_ON(!try_module_get(THIS_MODULE));
++ err = sysfs_create_file(&au_subsys_to_kset(sa->subsys).kobj,
++ &sabr->attr);
++ if (!err)
++ sabr->added = 1;
++ else
++ AuWarn("failed %s under sysfs(%d)\n", sabr->name, err);
++ }
++}
++
++/* ---------------------------------------------------------------------- */
++
++static void sysaufs_sbi_free(struct kref *ref)
++{
++ AuTraceEnter();
++ //AuDbg("here\n");
++ kfree(container_of(ref, struct sysaufs_sbinfo, ref));
++}
++
++int sysaufs_si_init(struct au_sbinfo *sbinfo)
++{
++ sbinfo->si_sa = kcalloc(sizeof(*sbinfo->si_sa), 1, GFP_NOFS);
++ if (sbinfo->si_sa) {
++ kref_init(&sbinfo->si_sa->ref);
++ return 0;
++ }
++ AuTraceErr(-ENOMEM);
++ return -ENOMEM;
++}
++
++void sysaufs_sbi_get(struct super_block *sb)
++{
++ kref_get(&au_sbi(sb)->si_sa->ref);
++}
++
++void sysaufs_sbi_put(struct super_block *sb)
++{
++ kref_put(&au_sbi(sb)->si_sa->ref, sysaufs_sbi_free);
++}
++
++void sysaufs_sbi_add(struct super_block *sb)
++{
++ int err, i;
++ const char *name;
++ struct au_sbinfo *sbinfo = au_sbi(sb);
++ struct sysaufs_sbinfo *sa = sbinfo->si_sa;
++
++ AuTraceEnter();
++ MtxMustLock(&au_sbilist_mtx);
++
++ err = kobject_set_name(&au_subsys_to_kset(sa->subsys).kobj,
++ "sbi_%p", sbinfo);
++ if (unlikely(err))
++ goto out;
++ name = kobject_name(&au_subsys_to_kset(sa->subsys).kobj);
++ subsys_get(&aufs_subsys);
++ kobj_set_kset_s(&au_subsys_to_kset(sa->subsys), aufs_subsys);
++ //au_subsys_to_kset(sa->subsys).kobj.ktype = &sysaufs_ktype;
++ err = subsystem_register(&sa->subsys);
++ if (unlikely(err))
++ goto out_put;
++#if 1
++ if (au_subsys_to_kset(sa->subsys).kobj.ktype)
++ sysaufs_sbi_ktype = *(au_subsys_to_kset(sa->subsys).kobj.ktype);
++ sysaufs_sbi_ktype.sysfs_ops = &sysaufs_sbi_ops;
++ au_subsys_to_kset(sa->subsys).kobj.ktype = &sysaufs_sbi_ktype;
++#endif
++
++ for (i = 0; i < SysaufsSb_Last; i++) {
++ sa->attr[i].name = sysaufs_sbi_entry[i].name;
++ sa->attr[i].mode = S_IRUGO;
++ sa->attr[i].owner = THIS_MODULE;
++ /* for older sysfs */
++ BUG_ON(!try_module_get(THIS_MODULE));
++ err = sysfs_create_file(&au_subsys_to_kset(sa->subsys).kobj,
++ sa->attr + i);
++ if (unlikely(err))
++ goto out_reg;
++ }
++
++ /* compatibility for some aufs scripts */
++ strcpy(sa->compat_name, "si_");
++ strcat(sa->compat_name, name + 4);
++ err = sysfs_create_link(&au_subsys_to_kset(aufs_subsys).kobj,
++ &au_subsys_to_kset(sa->subsys).kobj,
++ sa->compat_name);
++ if (unlikely(err)) {
++ AuWarn("failed adding %s for compatibility(%d), ignored.\n",
++ sa->compat_name, err);
++ err = 0;
++ }
++
++ sa->added = 1;
++ sysaufs_brs_add(sb);
++ goto out; /* success */
++
++ out_reg:
++ for (; i >= 0; i--) {
++ sysfs_remove_file(&au_subsys_to_kset(sa->subsys).kobj,
++ sa->attr + i);
++ /* for older sysfs */
++ module_put(THIS_MODULE);
++ }
++ subsystem_unregister(&sa->subsys);
++ out_put:
++ subsys_put(&aufs_subsys);
++ out:
++ if (!err)
++ sysaufs_sbi_get(sb);
++ else
++ AuWarn("failed adding sysfs (%d)\n", err);
++}
++
++void sysaufs_sbi_del(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo = au_sbi(sb);
++ struct sysaufs_sbinfo *sa = sbinfo->si_sa;
++ int i;
++
++ AuTraceEnter();
++ MtxMustLock(&au_sbilist_mtx);
++
++ sysaufs_brs_del(sb);
++ for (i = 0; i < SysaufsSb_Last; i++) {
++ sysfs_remove_file(&au_subsys_to_kset(sa->subsys).kobj,
++ sa->attr + i);
++ /* for older sysfs */
++ module_put(THIS_MODULE);
++ }
++ sa->added = 0;
++ sysfs_remove_link(&au_subsys_to_kset(aufs_subsys).kobj,
++ sa->compat_name);
++ subsystem_unregister(&sa->subsys);
++ subsys_put(&aufs_subsys);
++ sysaufs_sbi_put(sb);
++}
++
++/* ---------------------------------------------------------------------- */
++
++int __init sysaufs_init(void)
++{
++ int err, i;
++
++ for (i = 0; i < _Last; i++)
++ sysaufs_attr[i] = &sysaufs_entry[i].attr;
++
++ subsys_get(&fs_subsys);
++ kobj_set_kset_s(&au_subsys_to_kset(aufs_subsys), fs_subsys);
++ err = subsystem_register(&aufs_subsys);
++ if (unlikely(err))
++ goto out_put;
++ err = sysfs_create_group(&au_subsys_to_kset(aufs_subsys).kobj,
++ &sysaufs_attr_group);
++ if (!err)
++ return err; /* success */
++
++ subsystem_unregister(&aufs_subsys);
++ out_put:
++ subsys_put(&fs_subsys);
++ AuTraceErr(err);
++ return err;
++}
++
++void sysaufs_fin(void)
++{
++ AuDebugOn(!list_empty(&au_sbilist));
++ sysfs_remove_group(&au_subsys_to_kset(aufs_subsys).kobj,
++ &sysaufs_attr_group);
++ subsystem_unregister(&aufs_subsys);
++ subsys_put(&fs_subsys);
++}
+diff --git a/fs/aufs/sysaufs.h b/fs/aufs/sysaufs.h
+new file mode 100644
+index 0000000..ef96716
+--- /dev/null
++++ b/fs/aufs/sysaufs.h
+@@ -0,0 +1,211 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * sysfs interface
++ *
++ * $Id: sysaufs.h,v 1.21 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __SYSAUFS_H__
++#define __SYSAUFS_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/sysfs.h>
++#include <linux/version.h>
++
++/* ---------------------------------------------------------------------- */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
++typedef struct kset au_subsys_t;
++#define au_subsys_to_kset(subsys) (subsys)
++#else
++typedef struct subsystem au_subsys_t;
++#define au_subsys_to_kset(subsys) ((subsys).kset)
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++static inline struct kset *subsys_get(struct kset *s)
++{
++ return kset_get(s);
++}
++
++static inline void subsys_put(struct kset *s)
++{
++ kset_put(s);
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++/* entries under sysfs per super block */
++enum {
++ SysaufsSb_XINO,
++#ifdef CONFIG_AUFS_EXPORT
++ SysaufsSb_XIGEN,
++#endif
++ SysaufsSb_MNTPNT1,
++#if 0
++ SysaufsSb_PLINK,
++ SysaufsSb_files,
++#endif
++ SysaufsSb_Last
++};
++
++struct sysaufs_sbinfo {
++#ifdef CONFIG_AUFS_SYSAUFS
++ //todo: try kset directly
++ au_subsys_t subsys;
++ struct attribute attr[SysaufsSb_Last];
++ struct kref ref;
++ int added;
++ char compat_name[32];
++#endif
++};
++
++/* 'brN' entry under sysfs per super block */
++struct sysaufs_br {
++#ifdef CONFIG_AUFS_SYSAUFS
++ char name[8];
++ struct attribute attr;
++ struct kref ref;
++ int added;
++#endif
++};
++
++/* ---------------------------------------------------------------------- */
++
++struct au_branch;
++struct au_sbinfo;
++#ifdef CONFIG_AUFS_SYSAUFS
++extern struct mutex au_sbilist_mtx;
++extern struct list_head au_sbilist;
++
++static inline void au_sbilist_lock(void)
++{
++ mutex_lock(&au_sbilist_mtx);
++}
++
++static inline void au_sbilist_unlock(void)
++{
++ mutex_unlock(&au_sbilist_mtx);
++}
++
++static inline void au_sbilist_del(struct au_sbinfo *sbinfo)
++{
++ list_del(&sbinfo->si_list);
++}
++
++static inline void au_sbilist_add(struct au_sbinfo *sbinfo)
++{
++ /* the order in this list is important */
++ list_add_tail(&sbinfo->si_list, &au_sbilist);
++}
++
++struct sysaufs_br *sysaufs_br_alloc(void);
++void sysaufs_br_get(struct au_branch *br);
++void sysaufs_br_put(struct au_branch *br);
++void sysaufs_brs_add(struct super_block *sb);
++void sysaufs_brs_del(struct super_block *sb);
++int sysaufs_si_init(struct au_sbinfo *sbinfo);
++void sysaufs_sbi_get(struct super_block *sb);
++void sysaufs_sbi_put(struct super_block *sb);
++void sysaufs_sbi_add(struct super_block *sb);
++void sysaufs_sbi_del(struct super_block *sb);
++int __init sysaufs_init(void);
++void sysaufs_fin(void);
++
++#else
++
++#define au_sbilist_lock() do {} while (0)
++#define au_sbilist_unlock() do {} while (0)
++
++static inline void au_sbilist_del(struct au_sbinfo *sbinfo)
++{
++ /* empty */
++}
++
++static inline void au_sbilist_add(struct au_sbinfo *sbinfo)
++{
++ /* empty */
++}
++
++static inline struct sysaufs_br *sysaufs_br_alloc(void)
++{
++ return (void *)-1; //todo: poison
++}
++
++static inline void sysaufs_br_get(struct au_branch *br)
++{
++ /* nothing */
++}
++
++static inline void sysaufs_br_put(struct au_branch *br)
++{
++ /* nothing */
++}
++
++static inline void sysaufs_brs_add(struct super_block *sb)
++{
++ /* nothing */
++}
++
++static inline void sysaufs_brs_del(struct super_block *sb)
++{
++ /* nothing */
++}
++
++static inline int sysaufs_si_init(struct au_sbinfo *sbinfo)
++{
++ return 0;
++}
++
++static inline void sysaufs_sbi_get(struct super_block *sb)
++{
++ /* nothing */
++}
++
++static inline void sysaufs_sbi_put(struct super_block *sb)
++{
++ /* nothing */
++}
++
++static inline void sysaufs_sbi_add(struct super_block *sb)
++{
++ /* nothing */
++}
++
++static inline void sysaufs_sbi_del(struct super_block *sb)
++{
++ /* nothing */
++}
++
++static inline int sysaufs_init(void)
++{
++ sysaufs_brs = 0;
++ return 0;
++}
++
++#define sysaufs_fin() do {} while (0)
++
++#endif /* CONFIG_AUFS_SYSAUFS */
++
++#endif /* __KERNEL__ */
++#endif /* __SYSAUFS_H__ */
+diff --git a/fs/aufs/sysrq.c b/fs/aufs/sysrq.c
+new file mode 100644
+index 0000000..e7d3f53
+--- /dev/null
++++ b/fs/aufs/sysrq.c
+@@ -0,0 +1,296 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * magic sysrq hanlder
++ *
++ * $Id: sysrq.c,v 1.11 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/fs.h>
++#include <linux/module.h>
++//#include <linux/sysrq.h>
++#include <linux/version.h>
++
++#include "aufs.h"
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#error mis-configuraion or Makefile
++#elif !defined(pr_warning)
++#define pr_warning(fmt, arg...) printk(KERN_WARNING fmt, ##arg)
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_DEBUG_LOCK
++struct au_dbg_lock {
++ struct list_head list;
++ union {
++ struct super_block *sb;
++ struct dentry *dentry;
++ struct inode *inode;
++ void *any;
++ };
++ int flags;
++ unsigned int lsc;
++ pid_t pid;
++};
++
++static void au_dbg_reg(struct au_splhead *spl, void *any, int flags,
++ unsigned int lsc)
++{
++ struct au_dbg_lock *p = kmalloc(sizeof(*p), GFP_NOFS);
++
++ if (p) {
++ p->any = any;
++ p->flags = flags;
++ p->lsc = lsc;
++ p->pid = current->pid;
++ spin_lock(&spl->spin);
++ list_add(&p->list, &spl->head);
++ spin_unlock(&spl->spin);
++ }
++ WARN_ON(!p);
++}
++
++static void au_dbg_unreg(struct au_splhead *spl, void *any, int flags)
++{
++ struct au_dbg_lock *p, *tmp, *found;
++ struct list_head *head = &spl->head;
++ const pid_t pid = current->pid;
++
++ found = NULL;
++ spin_lock(&spl->spin);
++ list_for_each_entry_safe(p, tmp, head, list)
++ if (p->any == any && p->pid == pid) {
++ list_del(&p->list);
++ found = p;
++ break;
++ }
++ spin_unlock(&spl->spin);
++ kfree(found);
++ WARN_ON(!found);
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_dbg_locking_si_reg(struct super_block *sb, int flags)
++{
++ au_dbg_reg(au_sbi(sb)->si_dbg_lock + AuDbgLock_SI_LOCKING, sb, flags,
++ -1);
++}
++
++void au_dbg_locking_si_unreg(struct super_block *sb, int flags)
++{
++ au_dbg_unreg(au_sbi(sb)->si_dbg_lock + AuDbgLock_SI_LOCKING, sb, flags);
++}
++
++void au_dbg_locked_si_reg(struct super_block *sb, int flags)
++{
++ au_dbg_reg(au_sbi(sb)->si_dbg_lock + AuDbgLock_SI_LOCKED, sb, flags,
++ -1);
++}
++
++void au_dbg_locked_si_unreg(struct super_block *sb, int flags)
++{
++ au_dbg_unreg(au_sbi(sb)->si_dbg_lock + AuDbgLock_SI_LOCKED, sb, flags);
++}
++
++void au_dbg_locking_di_reg(struct dentry *d, int flags, unsigned int lsc)
++{
++ au_dbg_reg(au_sbi(d->d_sb)->si_dbg_lock + AuDbgLock_DI_LOCKING, d,
++ flags, lsc);
++}
++
++void au_dbg_locking_di_unreg(struct dentry *d, int flags)
++{
++ au_dbg_unreg(au_sbi(d->d_sb)->si_dbg_lock + AuDbgLock_DI_LOCKING, d,
++ flags);
++}
++
++void au_dbg_locked_di_reg(struct dentry *d, int flags, unsigned int lsc)
++{
++ au_dbg_reg(au_sbi(d->d_sb)->si_dbg_lock + AuDbgLock_DI_LOCKED, d, flags,
++ lsc);
++}
++
++void au_dbg_locked_di_unreg(struct dentry *d, int flags)
++{
++ au_dbg_unreg(au_sbi(d->d_sb)->si_dbg_lock + AuDbgLock_DI_LOCKED, d,
++ flags);
++}
++
++void au_dbg_locking_ii_reg(struct inode *i, int flags, unsigned int lsc)
++{
++ au_dbg_reg(au_sbi(i->i_sb)->si_dbg_lock + AuDbgLock_II_LOCKING, i,
++ flags, lsc);
++}
++
++void au_dbg_locking_ii_unreg(struct inode *i, int flags)
++{
++ au_dbg_unreg(au_sbi(i->i_sb)->si_dbg_lock + AuDbgLock_II_LOCKING, i,
++ flags);
++}
++
++void au_dbg_locked_ii_reg(struct inode *i, int flags, unsigned int lsc)
++{
++ au_dbg_reg(au_sbi(i->i_sb)->si_dbg_lock + AuDbgLock_II_LOCKED, i, flags,
++ lsc);
++}
++
++void au_dbg_locked_ii_unreg(struct inode *i, int flags)
++{
++ au_dbg_unreg(au_sbi(i->i_sb)->si_dbg_lock + AuDbgLock_II_LOCKED, i,
++ flags);
++}
++#endif /* CONFIG_AUFS_DEBUG_LOCK */
++
++/* ---------------------------------------------------------------------- */
++
++static void sysrq_sb(struct super_block *sb)
++{
++ char *plevel;
++ struct inode *i;
++ struct au_sbinfo *sbinfo;
++ struct file *file;
++
++ plevel = au_plevel;
++ au_plevel = KERN_WARNING;
++ au_debug_on();
++
++ sbinfo = au_sbi(sb);
++ pr_warning("si=%p\n", sbinfo);
++ pr_warning(AUFS_NAME ": superblock\n");
++ au_dpri_sb(sb);
++ pr_warning(AUFS_NAME ": root dentry\n");
++ au_dpri_dentry(sb->s_root);
++ pr_warning(AUFS_NAME ": root inode\n");
++ au_dpri_inode(sb->s_root->d_inode);
++ pr_warning(AUFS_NAME ": isolated inode\n");
++ list_for_each_entry(i, &sb->s_inodes, i_sb_list)
++ if (list_empty(&i->i_dentry))
++ au_dpri_inode(i);
++ pr_warning(AUFS_NAME ": files\n");
++ list_for_each_entry(file, &sb->s_files, f_u.fu_list)
++ if (au_test_aufs_file(file))
++ au_dpri_file(file);
++
++#ifdef CONFIG_AUFS_DEBUG_LOCK
++ {
++ struct au_dbg_lock *p;
++ struct list_head *head;
++
++ pr_warning(AUFS_NAME ": locking si\n");
++ head = &sbinfo->si_dbg_lock[AuDbgLock_SI_LOCKING].head;
++ list_for_each_entry(p, head, list)
++ pr_warning("pid: %d, 0x%x\n", p->pid, p->flags);
++ pr_warning(AUFS_NAME ": locked si\n");
++ head = &sbinfo->si_dbg_lock[AuDbgLock_SI_LOCKED].head;
++ list_for_each_entry(p, head, list)
++ pr_warning("pid: %d, 0x%x\n", p->pid, p->flags);
++ pr_warning(AUFS_NAME ": locking di\n");
++ head = &sbinfo->si_dbg_lock[AuDbgLock_DI_LOCKING].head;
++ list_for_each_entry(p, head, list) {
++ pr_warning("pid: %d, 0x%x, %d\n",
++ p->pid, p->flags, p->lsc);
++ au_dpri_dentry(p->dentry);
++ }
++ pr_warning(AUFS_NAME ": locked di\n");
++ head = &sbinfo->si_dbg_lock[AuDbgLock_DI_LOCKED].head;
++ list_for_each_entry(p, head, list) {
++ pr_warning("pid: %d, 0x%x, %d\n",
++ p->pid, p->flags, p->lsc);
++ au_dpri_dentry(p->dentry);
++ }
++ pr_warning(AUFS_NAME ": locking ii\n");
++ head = &sbinfo->si_dbg_lock[AuDbgLock_II_LOCKING].head;
++ list_for_each_entry(p, head, list) {
++ pr_warning("pid: %d, %d\n", p->pid, p->lsc);
++ au_dpri_inode(p->inode);
++ }
++ pr_warning(AUFS_NAME ": locked ii\n");
++ head = &sbinfo->si_dbg_lock[AuDbgLock_II_LOCKED].head;
++ list_for_each_entry(p, head, list) {
++ pr_warning("pid: %d, %d\n", p->pid, p->lsc);
++ au_dpri_inode(p->inode);
++ }
++ }
++#endif
++
++ au_plevel = plevel;
++ au_debug_off();
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* module parameter */
++static char *aufs_sysrq_key = "a";
++module_param_named(sysrq, aufs_sysrq_key, charp, S_IRUGO);
++MODULE_PARM_DESC(sysrq, "MagicSysRq key for " AUFS_NAME);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
++static void au_sysrq(int key, struct tty_struct *tty)
++#else
++static void au_sysrq(int key, struct pt_regs *regs, struct tty_struct *tty)
++#endif
++{
++ struct au_sbinfo *sbinfo;
++
++#if 0
++ if (au_debug_test())
++ au_debug_off();
++ else
++ au_debug_on();
++#endif
++
++ //mutex_lock(&au_sbilist_mtx);
++ list_for_each_entry(sbinfo, &au_sbilist, si_list)
++ sysrq_sb(sbinfo->si_mnt->mnt_sb);
++ //mutex_unlock(&au_sbilist_mtx);
++}
++
++static struct sysrq_key_op au_sysrq_op = {
++ .handler = au_sysrq,
++ .help_msg = "Aufs",
++ .action_msg = "Aufs",
++ .enable_mask = SYSRQ_ENABLE_DUMP //??
++};
++
++/* ---------------------------------------------------------------------- */
++
++int __init au_sysrq_init(void)
++{
++ int err;
++ char key;
++
++ err = -1;
++ key = *aufs_sysrq_key;
++ if ('a' <= key && key <= 'z')
++ err = register_sysrq_key(key, &au_sysrq_op);
++ if (unlikely(err))
++ AuErr("err %d, sysrq=%c\n", err, key);
++ return err;
++}
++
++void au_sysrq_fin(void)
++{
++ int err;
++ err = unregister_sysrq_key(*aufs_sysrq_key, &au_sysrq_op);
++ if (unlikely(err))
++ AuErr("err %d (ignored)\n", err);
++}
+diff --git a/fs/aufs/vdir.c b/fs/aufs/vdir.c
+new file mode 100644
+index 0000000..d3a470e
+--- /dev/null
++++ b/fs/aufs/vdir.c
+@@ -0,0 +1,941 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * virtual or vertical directory
++ *
++ * $Id: vdir.c,v 1.48 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++static int calc_size(int namelen)
++{
++ int sz;
++
++ sz = sizeof(struct au_vdir_de) + namelen;
++ if (sizeof(ino_t) == sizeof(long)) {
++ const int mask = sizeof(ino_t) - 1;
++ if (sz & mask) {
++ sz += sizeof(ino_t);
++ sz &= ~mask;
++ }
++ }
++
++ AuDebugOn(sz % sizeof(ino_t));
++ return sz;
++}
++
++static int set_deblk_end(union au_vdir_deblk_p *p,
++ union au_vdir_deblk_p *deblk_end)
++{
++ if (calc_size(0) <= deblk_end->p - p->p) {
++ p->de->de_str.len = 0;
++ /* smp_mb(); */
++ return 0;
++ }
++ return -1; /* error */
++}
++
++/* returns true or false */
++static int is_deblk_end(union au_vdir_deblk_p *p,
++ union au_vdir_deblk_p *deblk_end)
++{
++ if (calc_size(0) <= deblk_end->p - p->p)
++ return !p->de->de_str.len;
++ return 1;
++}
++
++static au_vdir_deblk_t *last_deblk(struct au_vdir *vdir)
++{
++ return vdir->vd_deblk[vdir->vd_nblk - 1];
++}
++
++void au_nhash_init(struct au_nhash *nhash)
++{
++ int i;
++ for (i = 0; i < AuSize_NHASH; i++)
++ INIT_HLIST_HEAD(nhash->heads + i);
++}
++
++struct au_nhash *au_nhash_new(gfp_t gfp)
++{
++ struct au_nhash *nhash;
++
++ nhash = kmalloc(sizeof(*nhash), gfp);
++ if (nhash) {
++ au_nhash_init(nhash);
++ return nhash;
++ }
++ return ERR_PTR(-ENOMEM);
++}
++
++void au_nhash_del(struct au_nhash *nhash)
++{
++ au_nhash_fin(nhash);
++ kfree(nhash);
++}
++
++void au_nhash_move(struct au_nhash *dst, struct au_nhash *src)
++{
++ int i;
++
++ AuTraceEnter();
++
++ *dst = *src;
++ for (i = 0; i < AuSize_NHASH; i++) {
++ struct hlist_head *h;
++ h = dst->heads + i;
++ if (h->first)
++ h->first->pprev = &h->first;
++ INIT_HLIST_HEAD(src->heads + i);
++ }
++ /* smp_mb(); */
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_nhash_fin(struct au_nhash *whlist)
++{
++ int i;
++ struct hlist_head *head;
++ struct au_vdir_wh *tpos;
++ struct hlist_node *pos, *n;
++
++ AuTraceEnter();
++
++ for (i = 0; i < AuSize_NHASH; i++) {
++ head = whlist->heads + i;
++ hlist_for_each_entry_safe(tpos, pos, n, head, wh_hash) {
++ /* hlist_del(pos); */
++ kfree(tpos);
++ }
++ }
++}
++
++int au_nhash_test_longer_wh(struct au_nhash *whlist, aufs_bindex_t btgt,
++ int limit)
++{
++ int n, i;
++ struct hlist_head *head;
++ struct au_vdir_wh *tpos;
++ struct hlist_node *pos;
++
++ LKTRTrace("limit %d\n", limit);
++
++ n = 0;
++ for (i = 0; i < AuSize_NHASH; i++) {
++ head = whlist->heads + i;
++ hlist_for_each_entry(tpos, pos, head, wh_hash)
++ if (tpos->wh_bindex == btgt && ++n > limit)
++ return 1;
++ }
++ return 0;
++}
++
++static unsigned int au_name_hash(const unsigned char *name, unsigned int len)
++{
++ return full_name_hash(name, len) % AuSize_NHASH;
++}
++
++/* returns found(true) or not */
++int au_nhash_test_known_wh(struct au_nhash *whlist, char *name, int namelen)
++{
++ struct hlist_head *head;
++ struct au_vdir_wh *tpos;
++ struct hlist_node *pos;
++ struct au_vdir_destr *str;
++
++ LKTRTrace("%.*s\n", namelen, name);
++
++ head = whlist->heads + au_name_hash(name, namelen);
++ hlist_for_each_entry(tpos, pos, head, wh_hash) {
++ str = &tpos->wh_str;
++ LKTRTrace("%.*s\n", str->len, str->name);
++ if (str->len == namelen && !memcmp(str->name, name, namelen))
++ return 1;
++ }
++ return 0;
++}
++
++int au_nhash_append_wh(struct au_nhash *whlist, char *name, int namelen,
++ ino_t ino, unsigned int d_type, aufs_bindex_t bindex,
++ unsigned char shwh)
++{
++ int err;
++ struct au_vdir_destr *str;
++ struct au_vdir_wh *wh;
++
++ LKTRTrace("%.*s\n", namelen, name);
++
++ err = -ENOMEM;
++ wh = kmalloc(sizeof(*wh) + namelen, GFP_NOFS);
++ if (unlikely(!wh))
++ goto out;
++ err = 0;
++ wh->wh_bindex = bindex;
++ if (shwh)
++ au_shwh_init_wh(wh, ino, d_type);
++ str = &wh->wh_str;
++ str->len = namelen;
++ memcpy(str->name, name, namelen);
++ hlist_add_head(&wh->wh_hash,
++ whlist->heads + au_name_hash(name, namelen));
++ /* smp_mb(); */
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_vdir_free(struct au_vdir *vdir)
++{
++ au_vdir_deblk_t **deblk;
++
++ AuTraceEnter();
++
++ deblk = vdir->vd_deblk;
++ while (vdir->vd_nblk--) {
++ kfree(*deblk);
++ deblk++;
++ }
++ kfree(vdir->vd_deblk);
++ au_cache_free_vdir(vdir);
++}
++
++static int append_deblk(struct au_vdir *vdir)
++{
++ int err, sz, i;
++ au_vdir_deblk_t **o;
++ union au_vdir_deblk_p p, deblk_end;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ sz = sizeof(*o) * vdir->vd_nblk;
++ o = au_kzrealloc(vdir->vd_deblk, sz, sz + sizeof(*o), GFP_NOFS);
++ if (unlikely(!o))
++ goto out;
++ vdir->vd_deblk = o;
++ p.deblk = kmalloc(sizeof(*p.deblk), GFP_NOFS);
++ if (p.deblk) {
++ i = vdir->vd_nblk++;
++ vdir->vd_deblk[i] = p.deblk;
++ vdir->vd_last.i = i;
++ vdir->vd_last.p.p = p.p;
++ deblk_end.deblk = p.deblk + 1;
++ err = set_deblk_end(&p, &deblk_end);
++ AuDebugOn(err);
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static struct au_vdir *alloc_vdir(void)
++{
++ struct au_vdir *vdir;
++ int err;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ vdir = au_cache_alloc_vdir();
++ if (unlikely(!vdir))
++ goto out;
++ vdir->vd_deblk = kzalloc(sizeof(*vdir->vd_deblk), GFP_NOFS);
++ if (unlikely(!vdir->vd_deblk))
++ goto out_free;
++
++ vdir->vd_nblk = 0;
++ vdir->vd_version = 0;
++ vdir->vd_jiffy = 0;
++ err = append_deblk(vdir);
++ if (!err)
++ return vdir; /* success */
++
++ kfree(vdir->vd_deblk);
++
++ out_free:
++ au_cache_free_vdir(vdir);
++ out:
++ vdir = ERR_PTR(err);
++ AuTraceErrPtr(vdir);
++ return vdir;
++}
++
++static int reinit_vdir(struct au_vdir *vdir)
++{
++ int err;
++ union au_vdir_deblk_p p, deblk_end;
++
++ AuTraceEnter();
++
++ while (vdir->vd_nblk > 1) {
++ kfree(vdir->vd_deblk[vdir->vd_nblk - 1]);
++ vdir->vd_deblk[vdir->vd_nblk - 1] = NULL;
++ vdir->vd_nblk--;
++ }
++ p.deblk = vdir->vd_deblk[0];
++ deblk_end.deblk = p.deblk + 1;
++ err = set_deblk_end(&p, &deblk_end);
++ AuDebugOn(err);
++ vdir->vd_version = 0;
++ vdir->vd_jiffy = 0;
++ vdir->vd_last.i = 0;
++ vdir->vd_last.p.deblk = vdir->vd_deblk[0];
++ /* smp_mb(); */
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static void free_dehlist(struct au_nhash *dehlist)
++{
++ int i;
++ struct hlist_head *head;
++ struct au_vdir_dehstr *tpos;
++ struct hlist_node *pos, *n;
++
++ AuTraceEnter();
++
++ for (i = 0; i < AuSize_NHASH; i++) {
++ head = dehlist->heads + i;
++ hlist_for_each_entry_safe(tpos, pos, n, head, hash) {
++ /* hlist_del(pos); */
++ au_cache_free_dehstr(tpos);
++ }
++ }
++}
++
++/* returns found(true) or not */
++static int test_known(struct au_nhash *delist, char *name, int namelen)
++{
++ struct hlist_head *head;
++ struct au_vdir_dehstr *tpos;
++ struct hlist_node *pos;
++ struct au_vdir_destr *str;
++
++ LKTRTrace("%.*s\n", namelen, name);
++
++ head = delist->heads + au_name_hash(name, namelen);
++ hlist_for_each_entry(tpos, pos, head, hash) {
++ str = tpos->str;
++ LKTRTrace("%.*s\n", str->len, str->name);
++ if (str->len == namelen && !memcmp(str->name, name, namelen))
++ return 1;
++ }
++ return 0;
++
++}
++
++static int append_de(struct au_vdir *vdir, char *name, int namelen, ino_t ino,
++ unsigned int d_type, struct au_nhash *delist)
++{
++ int err, sz;
++ union au_vdir_deblk_p p, *room, deblk_end;
++ struct au_vdir_dehstr *dehstr;
++
++ LKTRTrace("%.*s %d, i%lu, dt%u\n",
++ namelen, name, namelen, (unsigned long)ino, d_type);
++
++ p.deblk = last_deblk(vdir);
++ deblk_end.deblk = p.deblk + 1;
++ room = &vdir->vd_last.p;
++ AuDebugOn(room->p < p.p || deblk_end.p <= room->p
++ || !is_deblk_end(room, &deblk_end));
++
++ sz = calc_size(namelen);
++ if (unlikely(sz > deblk_end.p - room->p)) {
++ err = append_deblk(vdir);
++ if (unlikely(err))
++ goto out;
++ p.deblk = last_deblk(vdir);
++ deblk_end.deblk = p.deblk + 1;
++ /* smp_mb(); */
++ AuDebugOn(room->p != p.p);
++ }
++
++ err = -ENOMEM;
++ dehstr = au_cache_alloc_dehstr();
++ if (unlikely(!dehstr))
++ goto out;
++ dehstr->str = &room->de->de_str;
++ hlist_add_head(&dehstr->hash,
++ delist->heads + au_name_hash(name, namelen));
++
++ room->de->de_ino = ino;
++ room->de->de_type = d_type;
++ room->de->de_str.len = namelen;
++ memcpy(room->de->de_str.name, name, namelen);
++
++ err = 0;
++ room->p += sz;
++ if (unlikely(set_deblk_end(room, &deblk_end)))
++ err = append_deblk(vdir);
++ /* smp_mb(); */
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int au_ino(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ unsigned int d_type, ino_t *ino)
++{
++ int err;
++ struct au_xino_entry xinoe;
++ struct mutex *mtx;
++ const int isdir = (d_type == DT_DIR);
++
++ /* prevent hardlinks from race condition */
++ mtx = NULL;
++ if (!isdir) {
++ mtx = &au_sbr(sb, bindex)->br_xino.xi_nondir_mtx;
++ mutex_lock(mtx);
++ }
++ err = au_xino_read(sb, bindex, h_ino, &xinoe);
++ if (unlikely(err))
++ goto out;
++
++ if (!xinoe.ino) {
++ err = -EIO;
++ xinoe.ino = au_xino_new_ino(sb);
++ if (unlikely(!xinoe.ino))
++ goto out;
++
++#if 0 /* reserved for future use */
++ struct inode *h_inode;
++ xinoe.h_gen = AuXino_INVALID_HGEN;
++ h_inode = ilookup(au_sbr_sb(sb, bindex), h_ino);
++ if (h_inode) {
++ if (!is_bad_inode(h_inode)) {
++ xinoe.h_gen = h_inode->i_generation;
++ WARN_ON(xinoe.h_gen == AuXino_INVALID_HGEN);
++ }
++ iput(h_inode);
++ }
++#endif
++ err = au_xino_write(sb, bindex, h_ino, &xinoe);
++ if (unlikely(err))
++ goto out;
++ }
++
++ *ino = xinoe.ino;
++
++ out:
++ if (!isdir)
++ mutex_unlock(mtx);
++ AuTraceErr(err);
++ return err;
++}
++
++static int au_wh_ino(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ unsigned int d_type, ino_t *ino)
++{
++#ifdef CONFIG_AUFS_SHWH
++ return au_ino(sb, bindex, h_ino, d_type, ino);
++#else
++ return 0;
++#endif
++}
++
++#define AuFillVdir_CALLED 1
++#define AuFillVdir_SHWH (1 << 1)
++#define au_ftest_fillvdir(flags, name) ((flags) & AuFillVdir_##name)
++#define au_fset_fillvdir(flags, name) { (flags) |= AuFillVdir_##name; }
++#define au_fclr_fillvdir(flags, name) { (flags) &= ~AuFillVdir_##name; }
++#ifndef CONFIG_AUFS_SHWH
++#undef AuFillVdir_SHWH
++#define AuFillVdir_SHWH 0
++#endif
++
++struct fillvdir_arg {
++ struct file *file;
++ struct au_vdir *vdir;
++ struct au_nhash *delist;
++ struct au_nhash *whlist;
++ aufs_bindex_t bindex;
++ unsigned int flags;
++ int err;
++};
++
++static int fillvdir(void *__arg, const char *__name, int namelen, loff_t offset,
++ au_filldir_ino_t h_ino, unsigned int d_type)
++{
++ struct fillvdir_arg *arg = __arg;
++ char *name = (void *)__name;
++ aufs_bindex_t bindex, bend;
++ struct super_block *sb;
++ ino_t ino;
++
++ LKTRTrace("%.*s, namelen %d, i%llu, dt%u\n",
++ namelen, name, namelen, (unsigned long long)h_ino, d_type);
++
++ sb = arg->file->f_dentry->d_sb;
++ bend = arg->bindex;
++ arg->err = 0;
++ au_fset_fillvdir(arg->flags, CALLED);
++ /* smp_mb(); */
++ if (namelen <= AUFS_WH_PFX_LEN
++ || memcmp(name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) {
++ for (bindex = 0; bindex < bend; bindex++)
++ if (test_known(arg->delist + bindex, name, namelen)
++ || au_nhash_test_known_wh(arg->whlist + bindex,
++ name, namelen))
++ goto out; /* already exists or whiteouted */
++
++ ino = 1; /* why does gcc warns? */
++ arg->err = au_ino(sb, bend, h_ino, d_type, &ino);
++ if (!arg->err)
++ arg->err = append_de(arg->vdir, name, namelen, ino,
++ d_type, arg->delist + bend);
++ } else {
++ name += AUFS_WH_PFX_LEN;
++ namelen -= AUFS_WH_PFX_LEN;
++ for (bindex = 0; bindex < bend; bindex++)
++ if (au_nhash_test_known_wh(arg->whlist + bend, name,
++ namelen))
++ goto out; /* already whiteouted */
++
++ ino = 1; /* dummy */
++ if (au_ftest_fillvdir(arg->flags, SHWH))
++ arg->err = au_wh_ino(sb, bend, h_ino, d_type, &ino);
++ if (!arg->err)
++ arg->err = au_nhash_append_wh
++ (arg->whlist + bend, name, namelen, ino, d_type,
++ bend, au_ftest_fillvdir(arg->flags, SHWH));
++ }
++
++ out:
++ if (!arg->err)
++ arg->vdir->vd_jiffy = jiffies;
++ /* smp_mb(); */
++ AuTraceErr(arg->err);
++ return arg->err;
++}
++
++static int au_handle_shwh(struct super_block *sb, struct au_vdir *vdir,
++ aufs_bindex_t bstart, aufs_bindex_t bend,
++ struct au_nhash *_whlist, struct au_nhash *_delist)
++{
++#ifdef CONFIG_AUFS_SHWH
++ int err, i;
++ struct hlist_head *head;
++ struct au_vdir_wh *tpos;
++ struct hlist_node *pos, *n;
++ char *p, *o;
++ struct au_nhash *whlist, *delist;
++ struct au_vdir_destr *destr;
++ aufs_bindex_t bindex;
++
++ AuTraceEnter();
++ AuDebugOn(!au_opt_test(au_mntflags(sb), SHWH));
++
++ err = -ENOMEM;
++ o = p = __getname();
++ if (unlikely(!p))
++ goto out;
++
++ err = 0;
++ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN);
++ p += AUFS_WH_PFX_LEN;
++ for (bindex = bstart; !err && bindex <= bend; bindex++) {
++ whlist = _whlist + bindex;
++ delist = _delist + bindex;
++
++ for (i = 0; i < AuSize_NHASH; i++) {
++ head = whlist->heads + i;
++ hlist_for_each_entry_safe(tpos, pos, n, head, wh_hash) {
++ destr = &tpos->wh_str;
++ memcpy(p, destr->name, destr->len);
++ err = append_de(vdir, o,
++ destr->len + AUFS_WH_PFX_LEN,
++ tpos->wh_ino, tpos->wh_type,
++ delist);
++ if (unlikely(err))
++ break;
++ }
++ }
++ }
++
++ __putname(o);
++
++ out:
++ AuTraceErr(err);
++ return err;
++#else
++ return 0;
++#endif
++}
++
++static int au_do_read_vdir(struct fillvdir_arg *arg)
++{
++ int err;
++ unsigned int mnt_flags;
++ loff_t offset;
++ aufs_bindex_t bend, bindex, bstart;
++ unsigned char dlgt, shwh;
++ struct super_block *sb;
++ struct file *hf;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ bend = au_fbend(arg->file);
++ arg->delist = kmalloc(sizeof(*arg->delist) * (bend + 1), GFP_NOFS);
++ if (unlikely(!arg->delist))
++ goto out;
++ arg->whlist = kmalloc(sizeof(*arg->whlist) * (bend + 1), GFP_NOFS);
++ if (unlikely(!arg->whlist))
++ goto out_delist;
++ err = 0;
++ for (bindex = 0; bindex <= bend; bindex++) {
++ au_nhash_init(arg->delist + bindex);
++ au_nhash_init(arg->whlist + bindex);
++ }
++
++ sb = arg->file->f_dentry->d_sb;
++ mnt_flags = au_mntflags(sb);
++ dlgt = !!au_test_dlgt(mnt_flags);
++ arg->flags = 0;
++ shwh = 0;
++ if (au_opt_test(mnt_flags, SHWH)) {
++ shwh = 1;
++ au_fset_fillvdir(arg->flags, SHWH);
++ }
++ bstart = au_fbstart(arg->file);
++ for (bindex = bstart; !err && bindex <= bend; bindex++) {
++ hf = au_h_fptr(arg->file, bindex);
++ if (!hf)
++ continue;
++
++ offset = vfsub_llseek(hf, 0, SEEK_SET);
++ err = offset;
++ if (unlikely(offset))
++ break;
++ arg->bindex = bindex;
++ do {
++ arg->err = 0;
++ au_fclr_fillvdir(arg->flags, CALLED);
++ /* smp_mb(); */
++ err = vfsub_readdir(hf, fillvdir, arg, dlgt);
++ if (err >= 0)
++ err = arg->err;
++ } while (!err && au_ftest_fillvdir(arg->flags, CALLED));
++ }
++
++ if (!err && shwh)
++ err = au_handle_shwh(sb, arg->vdir, bstart, bend, arg->whlist,
++ arg->delist);
++
++ for (bindex = bstart; bindex <= bend; bindex++) {
++ free_dehlist(arg->delist + bindex);
++ au_nhash_fin(arg->whlist + bindex);
++ }
++ kfree(arg->whlist);
++
++ out_delist:
++ kfree(arg->delist);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int read_vdir(struct file *file, int may_read)
++{
++ int err;
++ unsigned long expire;
++ struct fillvdir_arg arg;
++ unsigned char do_read;
++ struct dentry *dentry;
++ struct inode *inode;
++ struct au_vdir *vdir, *allocated;
++ struct super_block *sb;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, may %d\n", AuDLNPair(dentry), may_read);
++ FiMustWriteLock(file);
++ inode = dentry->d_inode;
++ IMustLock(inode);
++ IiMustWriteLock(inode);
++ AuDebugOn(!S_ISDIR(inode->i_mode));
++
++ err = 0;
++ allocated = NULL;
++ do_read = 0;
++ sb = inode->i_sb;
++ expire = au_sbi(sb)->si_rdcache;
++ vdir = au_ivdir(inode);
++ if (!vdir) {
++ AuDebugOn(au_fvdir_cache(file));
++ do_read = 1;
++ vdir = alloc_vdir();
++ err = PTR_ERR(vdir);
++ if (IS_ERR(vdir))
++ goto out;
++ err = 0;
++ allocated = vdir;
++ } else if (may_read
++ && (inode->i_version != vdir->vd_version
++ || time_after(jiffies, vdir->vd_jiffy + expire))) {
++ LKTRTrace("iver %llu, vdver %lu, exp %lu\n",
++ (unsigned long long)inode->i_version,
++ vdir->vd_version, vdir->vd_jiffy + expire);
++ do_read = 1;
++ err = reinit_vdir(vdir);
++ if (unlikely(err))
++ goto out;
++ }
++
++ if (!do_read)
++ return 0; /* success */
++
++ arg.file = file;
++ arg.vdir = vdir;
++ err = au_do_read_vdir(&arg);
++ if (!err) {
++ /* todo: necessary? */
++ /* file->f_pos = 0; */
++ vdir->vd_version = inode->i_version;
++ vdir->vd_last.i = 0;
++ vdir->vd_last.p.deblk = vdir->vd_deblk[0];
++ if (allocated)
++ au_set_ivdir(inode, allocated);
++ } else if (allocated)
++ au_vdir_free(allocated);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int copy_vdir(struct au_vdir *tgt, struct au_vdir *src)
++{
++ int err, i, rerr, n;
++
++ AuTraceEnter();
++ AuDebugOn(tgt->vd_nblk != 1);
++
++ err = -ENOMEM;
++ if (tgt->vd_nblk < src->vd_nblk) {
++ au_vdir_deblk_t **p;
++ p = au_kzrealloc(tgt->vd_deblk, sizeof(*p) * tgt->vd_nblk,
++ sizeof(*p) * src->vd_nblk, GFP_NOFS);
++ if (unlikely(!p))
++ goto out;
++ tgt->vd_deblk = p;
++ }
++
++ tgt->vd_nblk = src->vd_nblk;
++ n = src->vd_nblk;
++ memcpy(tgt->vd_deblk[0], src->vd_deblk[0], AuSize_DEBLK);
++ /* tgt->vd_last.i = 0; */
++ /* tgt->vd_last.p.deblk = tgt->vd_deblk[0]; */
++ tgt->vd_version = src->vd_version;
++ tgt->vd_jiffy = src->vd_jiffy;
++
++ for (i = 1; i < n; i++) {
++ tgt->vd_deblk[i] = kmalloc(AuSize_DEBLK, GFP_NOFS);
++ if (tgt->vd_deblk[i])
++ memcpy(tgt->vd_deblk[i], src->vd_deblk[i],
++ AuSize_DEBLK);
++ else
++ goto out;
++ }
++ /* smp_mb(); */
++ return 0; /* success */
++
++ out:
++ rerr = reinit_vdir(tgt);
++ BUG_ON(rerr);
++ AuTraceErr(err);
++ return err;
++}
++
++int au_vdir_init(struct file *file)
++{
++ int err;
++ struct dentry *dentry;
++ struct inode *inode;
++ struct au_vdir *vdir_cache, *allocated;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, pos %lld\n", AuDLNPair(dentry), file->f_pos);
++ FiMustWriteLock(file);
++ inode = dentry->d_inode;
++ IiMustWriteLock(inode);
++ AuDebugOn(!S_ISDIR(inode->i_mode));
++
++ err = read_vdir(file, !file->f_pos);
++ if (unlikely(err))
++ goto out;
++
++ allocated = NULL;
++ vdir_cache = au_fvdir_cache(file);
++ if (!vdir_cache) {
++ vdir_cache = alloc_vdir();
++ err = PTR_ERR(vdir_cache);
++ if (IS_ERR(vdir_cache))
++ goto out;
++ allocated = vdir_cache;
++ } else if (!file->f_pos && vdir_cache->vd_version != file->f_version) {
++ err = reinit_vdir(vdir_cache);
++ if (unlikely(err))
++ goto out;
++ } else
++ return 0; /* success */
++
++ err = copy_vdir(vdir_cache, au_ivdir(inode));
++ if (!err) {
++ file->f_version = inode->i_version;
++ if (allocated)
++ au_set_fvdir_cache(file, allocated);
++ } else if (allocated)
++ au_vdir_free(allocated);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static loff_t calc_offset(struct au_vdir *vdir)
++{
++ loff_t offset;
++ union au_vdir_deblk_p p;
++
++ p.deblk = vdir->vd_deblk[vdir->vd_last.i];
++ offset = vdir->vd_last.p.p - p.p;
++ offset += sizeof(*p.deblk) * vdir->vd_last.i;
++ return offset;
++}
++
++/* returns true or false */
++static int seek_vdir(struct file *file)
++{
++ int valid, i, n;
++ struct dentry *dentry;
++ struct au_vdir *vdir_cache;
++ loff_t offset;
++ union au_vdir_deblk_p p, deblk_end;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, pos %lld\n", AuDLNPair(dentry), file->f_pos);
++ vdir_cache = au_fvdir_cache(file);
++ AuDebugOn(!vdir_cache);
++
++ valid = 1;
++ offset = calc_offset(vdir_cache);
++ LKTRTrace("offset %lld\n", offset);
++ if (file->f_pos == offset)
++ goto out;
++
++ vdir_cache->vd_last.i = 0;
++ vdir_cache->vd_last.p.deblk = vdir_cache->vd_deblk[0];
++ if (!file->f_pos)
++ goto out;
++
++ valid = 0;
++ i = file->f_pos / AuSize_DEBLK;
++ LKTRTrace("i %d\n", i);
++ if (i >= vdir_cache->vd_nblk)
++ goto out;
++
++ n = vdir_cache->vd_nblk;
++ for (; i < n; i++) {
++ p.deblk = vdir_cache->vd_deblk[i];
++ deblk_end.deblk = p.deblk + 1;
++ offset = i;
++ offset *= AuSize_DEBLK;
++ while (!is_deblk_end(&p, &deblk_end) && offset < file->f_pos) {
++ int l;
++ l = calc_size(p.de->de_str.len);
++ offset += l;
++ p.p += l;
++ }
++ if (!is_deblk_end(&p, &deblk_end)) {
++ valid = 1;
++ vdir_cache->vd_last.i = i;
++ vdir_cache->vd_last.p = p;
++ break;
++ }
++ }
++
++ out:
++ /* smp_mb(); */
++ AuTraceErr(!valid);
++ return valid;
++}
++
++int au_vdir_fill_de(struct file *file, void *dirent, filldir_t filldir)
++{
++ int err, l;
++ struct dentry *dentry;
++ struct au_vdir *vdir_cache;
++ struct au_vdir_de *de;
++ union au_vdir_deblk_p deblk_end;
++
++ dentry = file->f_dentry;
++ LKTRTrace("%.*s, pos %lld\n", AuDLNPair(dentry), file->f_pos);
++ vdir_cache = au_fvdir_cache(file);
++ AuDebugOn(!vdir_cache);
++
++ if (!seek_vdir(file))
++ return 0;
++
++ while (1) {
++ deblk_end.deblk
++ = vdir_cache->vd_deblk[vdir_cache->vd_last.i] + 1;
++ while (!is_deblk_end(&vdir_cache->vd_last.p, &deblk_end)) {
++ de = vdir_cache->vd_last.p.de;
++ LKTRTrace("%.*s, off%lld, i%lu, dt%d\n",
++ de->de_str.len, de->de_str.name,
++ file->f_pos, (unsigned long)de->de_ino,
++ de->de_type);
++ err = filldir(dirent, de->de_str.name, de->de_str.len,
++ file->f_pos, de->de_ino, de->de_type);
++ if (unlikely(err)) {
++ AuTraceErr(err);
++ /* todo: ignore the error caused by udba? */
++ /* return err; */
++ return 0;
++ }
++
++ l = calc_size(de->de_str.len);
++ vdir_cache->vd_last.p.p += l;
++ file->f_pos += l;
++ }
++ if (vdir_cache->vd_last.i < vdir_cache->vd_nblk - 1) {
++ vdir_cache->vd_last.i++;
++ vdir_cache->vd_last.p.deblk
++ = vdir_cache->vd_deblk[vdir_cache->vd_last.i];
++ file->f_pos = sizeof(*vdir_cache->vd_last.p.deblk)
++ * vdir_cache->vd_last.i;
++ continue;
++ }
++ break;
++ }
++
++ /* smp_mb(); */
++ return 0;
++}
+diff --git a/fs/aufs/vfsub.c b/fs/aufs/vfsub.c
+new file mode 100644
+index 0000000..3744387
+--- /dev/null
++++ b/fs/aufs/vfsub.c
+@@ -0,0 +1,682 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * sub-routines for VFS
++ *
++ * $Id: vfsub.c,v 1.43 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++void vfsub_args_init(struct vfsub_args *vargs, struct au_hin_ignore *ign,
++ int dlgt, int force_unlink)
++{
++ do_vfsub_args_reinit(vargs, ign);
++ vargs->flags = 0;
++ if (dlgt)
++ vfsub_fset(vargs->flags, DLGT);
++ if (force_unlink)
++ vfsub_fset(vargs->flags, FORCE_UNLINK);
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct file *vfsub_filp_open(const char *path, int oflags, int mode)
++{
++ struct file *err;
++
++ LKTRTrace("%s\n", path);
++
++ lockdep_off();
++ err = filp_open(path, oflags, mode);
++ lockdep_on();
++ if (!IS_ERR(err))
++ au_update_fuse_h_inode(err->f_vfsmnt, err->f_dentry); /*ignore*/
++ return err;
++}
++
++int vfsub_path_lookup(const char *name, unsigned int flags,
++ struct nameidata *nd)
++{
++ int err;
++
++ LKTRTrace("%s\n", name);
++
++ /* lockdep_off(); */
++ err = path_lookup(name, flags, nd);
++ /* lockdep_on(); */
++ if (!err)
++ au_update_fuse_h_inode(nd->mnt, nd->dentry);
++ /*ignore*/
++ return err;
++}
++
++struct dentry *vfsub_lookup_one_len(const char *name, struct dentry *parent,
++ int len)
++{
++ struct dentry *d;
++
++ LKTRTrace("%.*s/%.*s\n", AuDLNPair(parent), len, name);
++ IMustLock(parent->d_inode);
++
++ d = lookup_one_len(name, parent, len);
++ if (!IS_ERR(d))
++ au_update_fuse_h_inode(NULL, d); /*ignore*/
++ return d;
++}
++
++#ifdef CONFIG_AUFS_LHASH_PATCH
++struct dentry *vfsub__lookup_hash(struct qstr *name, struct dentry *parent,
++ struct nameidata *nd)
++{
++ struct dentry *d;
++
++ LKTRTrace("%.*s/%.*s, nd %d\n",
++ AuDLNPair(parent), AuLNPair(name), !!nd);
++ if (nd)
++ LKTRTrace("nd{0x%x}\n", nd->flags);
++ IMustLock(parent->d_inode);
++
++ d = __lookup_hash(name, parent, nd);
++ if (!IS_ERR(d))
++ au_update_fuse_h_inode(NULL, d); /*ignore*/
++ return d;
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++int do_vfsub_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *nd)
++{
++ int err;
++ struct vfsmount *mnt;
++
++ LKTRTrace("i%lu, %.*s, 0x%x\n", dir->i_ino, AuDLNPair(dentry), mode);
++ IMustLock(dir);
++
++ err = vfs_create(dir, dentry, mode, nd);
++ if (!err) {
++ mnt = NULL;
++ if (nd)
++ mnt = nd->mnt;
++ /* dir inode is locked */
++ au_update_fuse_h_inode(mnt, dentry->d_parent); /*ignore*/
++ au_update_fuse_h_inode(mnt, dentry); /*ignore*/
++ }
++ return err;
++}
++
++int do_vfsub_symlink(struct inode *dir, struct dentry *dentry,
++ const char *symname, int mode)
++{
++ int err;
++
++ LKTRTrace("i%lu, %.*s, %s, 0x%x\n",
++ dir->i_ino, AuDLNPair(dentry), symname, mode);
++ IMustLock(dir);
++
++ err = vfs_symlink(dir, dentry, symname, mode);
++ if (!err) {
++ /* dir inode is locked */
++ au_update_fuse_h_inode(NULL, dentry->d_parent); /*ignore*/
++ au_update_fuse_h_inode(NULL, dentry); /*ignore*/
++ }
++ return err;
++}
++
++int do_vfsub_mknod(struct inode *dir, struct dentry *dentry, int mode,
++ dev_t dev)
++{
++ int err;
++
++ LKTRTrace("i%lu, %.*s, 0x%x\n", dir->i_ino, AuDLNPair(dentry), mode);
++ IMustLock(dir);
++
++ err = vfs_mknod(dir, dentry, mode, dev);
++ if (!err) {
++ /* dir inode is locked */
++ au_update_fuse_h_inode(NULL, dentry->d_parent); /*ignore*/
++ au_update_fuse_h_inode(NULL, dentry); /*ignore*/
++ }
++ return err;
++}
++
++int do_vfsub_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry)
++{
++ int err;
++
++ LKTRTrace("%.*s, i%lu, %.*s\n",
++ AuDLNPair(src_dentry), dir->i_ino, AuDLNPair(dentry));
++ IMustLock(dir);
++
++ lockdep_off();
++ err = vfs_link(src_dentry, dir, dentry);
++ lockdep_on();
++ if (!err) {
++ LKTRTrace("src_i %p, dst_i %p\n",
++ src_dentry->d_inode, dentry->d_inode);
++ /* fuse has different memory inode for the same inumber */
++ au_update_fuse_h_inode(NULL, src_dentry); /*ignore*/
++ /* dir inode is locked */
++ au_update_fuse_h_inode(NULL, dentry->d_parent); /*ignore*/
++ au_update_fuse_h_inode(NULL, dentry); /*ignore*/
++ }
++ return err;
++}
++
++int do_vfsub_rename(struct inode *src_dir, struct dentry *src_dentry,
++ struct inode *dir, struct dentry *dentry)
++{
++ int err;
++
++ LKTRTrace("i%lu, %.*s, i%lu, %.*s\n",
++ src_dir->i_ino, AuDLNPair(src_dentry),
++ dir->i_ino, AuDLNPair(dentry));
++ IMustLock(dir);
++ IMustLock(src_dir);
++ AuDebugOn(src_dir != dir && !vfsub_is_rename_mutex_locked(dir->i_sb));
++
++ lockdep_off();
++ err = vfs_rename(src_dir, src_dentry, dir, dentry);
++ lockdep_on();
++ if (!err) {
++ /* dir inode is locked */
++ au_update_fuse_h_inode(NULL, dentry->d_parent); /*ignore*/
++ au_update_fuse_h_inode(NULL, src_dentry->d_parent); /*ignore*/
++ au_update_fuse_h_inode(NULL, src_dentry); /*ignore*/
++ }
++ return err;
++}
++
++int do_vfsub_mkdir(struct inode *dir, struct dentry *dentry, int mode)
++{
++ int err;
++
++ LKTRTrace("i%lu, %.*s, 0x%x\n", dir->i_ino, AuDLNPair(dentry), mode);
++ IMustLock(dir);
++
++ err = vfs_mkdir(dir, dentry, mode);
++ if (!err) {
++ /* dir inode is locked */
++ au_update_fuse_h_inode(NULL, dentry->d_parent); /*ignore*/
++ au_update_fuse_h_inode(NULL, dentry); /*ignore*/
++ }
++ return err;
++}
++
++int do_vfsub_rmdir(struct inode *dir, struct dentry *dentry)
++{
++ int err;
++
++ LKTRTrace("i%lu, %.*s\n", dir->i_ino, AuDLNPair(dentry));
++ IMustLock(dir);
++
++ lockdep_off();
++ err = vfs_rmdir(dir, dentry);
++ lockdep_on();
++ /* dir inode is locked */
++ if (!err)
++ au_update_fuse_h_inode(NULL, dentry->d_parent); /*ignore*/
++ return err;
++}
++
++int do_vfsub_unlink(struct inode *dir, struct dentry *dentry)
++{
++ int err;
++
++ LKTRTrace("i%lu, %.*s\n", dir->i_ino, AuDLNPair(dentry));
++ IMustLock(dir);
++
++ /* vfs_unlink() locks inode */
++ lockdep_off();
++ err = vfs_unlink(dir, dentry);
++ lockdep_on();
++ /* dir inode is locked */
++ if (!err)
++ au_update_fuse_h_inode(NULL, dentry->d_parent); /*ignore*/
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++ssize_t do_vfsub_read_u(struct file *file, char __user *ubuf, size_t count,
++ loff_t *ppos)
++{
++ ssize_t err;
++
++ LKTRTrace("%.*s, cnt %zu, pos %lld\n",
++ AuDLNPair(file->f_dentry), count, *ppos);
++
++ if (0 /*!au_test_nfs(file->f_vfsmnt->mnt_sb)*/)
++ err = vfs_read(file, ubuf, count, ppos);
++ else {
++ lockdep_off();
++ err = vfs_read(file, ubuf, count, ppos);
++ lockdep_on();
++ }
++ if (err >= 0)
++ au_update_fuse_h_inode(file->f_vfsmnt, file->f_dentry);
++ /*ignore*/
++ return err;
++}
++
++/* todo: kernel_read()? */
++ssize_t do_vfsub_read_k(struct file *file, void *kbuf, size_t count,
++ loff_t *ppos)
++{
++ ssize_t err;
++ mm_segment_t oldfs;
++
++ oldfs = get_fs();
++ set_fs(KERNEL_DS);
++ err = do_vfsub_read_u(file, (char __user *)kbuf, count, ppos);
++ set_fs(oldfs);
++ return err;
++}
++
++ssize_t do_vfsub_write_u(struct file *file, const char __user *ubuf,
++ size_t count, loff_t *ppos)
++{
++ ssize_t err;
++
++ LKTRTrace("%.*s, cnt %zu, pos %lld\n",
++ AuDLNPair(file->f_dentry), count, *ppos);
++
++ lockdep_off();
++ err = vfs_write(file, ubuf, count, ppos);
++ lockdep_on();
++ if (err >= 0)
++ au_update_fuse_h_inode(file->f_vfsmnt, file->f_dentry);
++ /*ignore*/
++ return err;
++}
++
++ssize_t do_vfsub_write_k(struct file *file, void *kbuf, size_t count,
++ loff_t *ppos)
++{
++ ssize_t err;
++ mm_segment_t oldfs;
++
++ oldfs = get_fs();
++ set_fs(KERNEL_DS);
++ err = do_vfsub_write_u(file, (const char __user *)kbuf, count, ppos);
++ set_fs(oldfs);
++ return err;
++}
++
++int do_vfsub_readdir(struct file *file, filldir_t filldir, void *arg)
++{
++ int err;
++
++ LKTRTrace("%.*s\n", AuDLNPair(file->f_dentry));
++
++ lockdep_off();
++ err = vfs_readdir(file, filldir, arg);
++ lockdep_on();
++ if (err >= 0)
++ au_update_fuse_h_inode(file->f_vfsmnt, file->f_dentry);
++ /*ignore*/
++ return err;
++}
++
++#ifdef CONFIG_AUFS_SPLICE_PATCH
++long do_vfsub_splice_to(struct file *in, loff_t *ppos,
++ struct pipe_inode_info *pipe, size_t len,
++ unsigned int flags)
++{
++ long err;
++
++ LKTRTrace("%.*s, pos %lld, len %zu, 0x%x\n",
++ AuDLNPair(in->f_dentry), *ppos, len, flags);
++
++ lockdep_off();
++ err = vfs_splice_to(in, ppos, pipe, len, flags);
++ lockdep_on();
++ if (err >= 0)
++ au_update_fuse_h_inode(in->f_vfsmnt, in->f_dentry); /*ignore*/
++ return err;
++}
++
++long do_vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out,
++ loff_t *ppos, size_t len, unsigned int flags)
++{
++ long err;
++
++ LKTRTrace("%.*s, pos %lld, len %zu, 0x%x\n",
++ AuDLNPair(out->f_dentry), *ppos, len, flags);
++
++ lockdep_off();
++ err = vfs_splice_from(pipe, out, ppos, len, flags);
++ lockdep_on();
++ if (err >= 0)
++ au_update_fuse_h_inode(out->f_vfsmnt, out->f_dentry); /*ignore*/
++ return err;
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++struct au_vfsub_mkdir_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ int mode;
++ struct vfsub_args *vargs;
++};
++
++static void au_call_vfsub_mkdir(void *args)
++{
++ struct au_vfsub_mkdir_args *a = args;
++ *a->errp = vfsub_mkdir(a->dir, a->dentry, a->mode, a->vargs);
++}
++
++int vfsub_sio_mkdir(struct au_hinode *hdir, struct dentry *dentry, int mode,
++ int dlgt)
++{
++ int err, do_sio, wkq_err;
++ struct inode *dir = hdir->hi_inode;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++
++ LKTRTrace("i%lu, %.*s\n", dir->i_ino, AuDLNPair(dentry));
++
++ vfsub_args_init(&vargs, &ign, dlgt, /*force_unlink*/0);
++ vfsub_ign_hinode(&vargs, IN_CREATE, hdir);
++ do_sio = au_test_h_perm_sio(dir, MAY_EXEC | MAY_WRITE, dlgt);
++ if (!do_sio)
++ err = vfsub_mkdir(dir, dentry, mode, &vargs);
++ else {
++ struct au_vfsub_mkdir_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .mode = mode,
++ .vargs = &vargs
++ };
++ vfsub_fclr(vargs.flags, DLGT);
++ wkq_err = au_wkq_wait(au_call_vfsub_mkdir, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++struct au_vfsub_rmdir_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ struct vfsub_args *vargs;
++};
++
++static void au_call_vfsub_rmdir(void *args)
++{
++ struct au_vfsub_rmdir_args *a = args;
++ *a->errp = vfsub_rmdir(a->dir, a->dentry, a->vargs);
++}
++
++int vfsub_sio_rmdir(struct au_hinode *hdir, struct dentry *dentry, int dlgt)
++{
++ int err, do_sio, wkq_err;
++ struct inode *dir = hdir->hi_inode;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++
++ LKTRTrace("i%lu, %.*s\n", dir->i_ino, AuDLNPair(dentry));
++
++ vfsub_args_init(&vargs, &ign, dlgt, /*force_unlink*/0);
++ vfsub_ign_hinode(&vargs, IN_DELETE, hdir);
++ do_sio = au_test_h_perm_sio(dir, MAY_EXEC | MAY_WRITE, dlgt);
++ if (!do_sio)
++ err = vfsub_rmdir(dir, dentry, &vargs);
++ else {
++ struct au_vfsub_rmdir_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .vargs = &vargs
++ };
++ vfsub_fclr(vargs.flags, DLGT);
++ wkq_err = au_wkq_wait(au_call_vfsub_rmdir, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct notify_change_args {
++ int *errp;
++ struct dentry *h_dentry;
++ struct iattr *ia;
++ struct vfsub_args *vargs;
++};
++
++static void call_notify_change(void *args)
++{
++ struct notify_change_args *a = args;
++ struct inode *h_inode;
++
++ LKTRTrace("%.*s, ia_valid 0x%x\n",
++ AuDLNPair(a->h_dentry), a->ia->ia_valid);
++ h_inode = a->h_dentry->d_inode;
++ IMustLock(h_inode);
++
++ *a->errp = -EPERM;
++ if (!IS_IMMUTABLE(h_inode) && !IS_APPEND(h_inode)) {
++ vfsub_ignore(a->vargs);
++ lockdep_off();
++ *a->errp = notify_change(a->h_dentry, a->ia);
++ lockdep_on();
++ if (!*a->errp)
++ au_update_fuse_h_inode(NULL, a->h_dentry); /*ignore*/
++ else
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++ }
++ AuTraceErr(*a->errp);
++}
++
++#ifdef CONFIG_AUFS_DLGT
++static void vfsub_notify_change_dlgt(struct notify_change_args *args,
++ unsigned int flags)
++{
++ if (!vfsub_ftest(flags, DLGT))
++ call_notify_change(args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_notify_change, args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ *args->errp = wkq_err;
++ }
++}
++#else
++static void vfsub_notify_change_dlgt(struct notify_change_args *args,
++ unsigned int flags)
++{
++ call_notify_change(args);
++}
++#endif
++
++int vfsub_notify_change(struct dentry *dentry, struct iattr *ia,
++ struct vfsub_args *vargs)
++{
++ int err;
++ struct notify_change_args args = {
++ .errp = &err,
++ .h_dentry = dentry,
++ .ia = ia,
++ .vargs = vargs
++ };
++
++ vfsub_notify_change_dlgt(&args, vargs->flags);
++
++ AuTraceErr(err);
++ return err;
++}
++
++int vfsub_sio_notify_change(struct au_hinode *hdir, struct dentry *dentry,
++ struct iattr *ia)
++{
++ int err, wkq_err;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ __u32 events;
++ struct notify_change_args args = {
++ .errp = &err,
++ .h_dentry = dentry,
++ .ia = ia,
++ .vargs = &vargs
++ };
++
++ LKTRTrace("%.*s, 0x%x\n", AuDLNPair(dentry), ia->ia_valid);
++
++ vfsub_args_init(&vargs, &ign, /*dlgt*/0, /*force_unlink*/0);
++ events = vfsub_events_notify_change(ia);
++ if (events)
++ vfsub_ign_hinode(&vargs, events, hdir);
++ wkq_err = au_wkq_wait(call_notify_change, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct unlink_args {
++ int *errp;
++ struct inode *dir;
++ struct dentry *dentry;
++ struct vfsub_args *vargs;
++};
++
++static void call_unlink(void *args)
++{
++ struct unlink_args *a = args;
++ struct inode *h_inode;
++ const int stop_sillyrename = (au_test_nfs(a->dentry->d_sb)
++ && atomic_read(&a->dentry->d_count) == 1);
++
++ LKTRTrace("%.*s, stop_silly %d, cnt %d\n",
++ AuDLNPair(a->dentry), stop_sillyrename,
++ atomic_read(&a->dentry->d_count));
++
++ if (!stop_sillyrename)
++ dget(a->dentry);
++ h_inode = a->dentry->d_inode;
++ if (h_inode)
++ atomic_inc_return(&h_inode->i_count);
++ vfsub_ignore(a->vargs);
++ *a->errp = do_vfsub_unlink(a->dir, a->dentry);
++ if (unlikely(*a->errp || (a->dentry->d_flags & DCACHE_NFSFS_RENAMED)))
++ vfsub_unignore(a->vargs);
++ au_dbg_hin_list(a->vargs);
++ if (!stop_sillyrename)
++ dput(a->dentry);
++ if (h_inode)
++ iput(h_inode);
++
++ AuTraceErr(*a->errp);
++}
++
++/*
++ * @dir: must be locked.
++ * @dentry: target dentry.
++ */
++int vfsub_unlink(struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs)
++{
++ int err;
++ struct unlink_args args = {
++ .errp = &err,
++ .dir = dir,
++ .dentry = dentry,
++ .vargs = vargs
++ };
++
++ if (!vfsub_ftest(vargs->flags, DLGT)
++ && !vfsub_ftest(vargs->flags, FORCE_UNLINK))
++ call_unlink(&args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_unlink, &args,
++ vfsub_ftest(vargs->flags, DLGT));
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ }
++
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct statfs_args {
++ int *errp;
++ void *arg;
++ struct kstatfs *buf;
++};
++
++static void call_statfs(void *args)
++{
++ struct statfs_args *a = args;
++ *a->errp = vfs_statfs(a->arg, a->buf);
++}
++
++#ifdef CONFIG_AUFS_DLGT
++static void vfsub_statfs_dlgt(struct statfs_args *args, int dlgt)
++{
++ if (!dlgt)
++ call_statfs(args);
++ else {
++ int wkq_err;
++ wkq_err = au_wkq_wait(call_statfs, args, /*dlgt*/1);
++ if (unlikely(wkq_err))
++ *args->errp = wkq_err;
++ }
++}
++#else
++static void vfsub_statfs_dlgt(struct statfs_args *args, int dlgt)
++{
++ call_statfs(args);
++}
++#endif
++
++int vfsub_statfs(void *arg, struct kstatfs *buf, int dlgt)
++{
++ int err;
++ struct statfs_args args = {
++ .errp = &err,
++ .arg = arg,
++ .buf = buf
++ };
++
++ vfsub_statfs_dlgt(&args, dlgt);
++
++ return err;
++}
+diff --git a/fs/aufs/vfsub.h b/fs/aufs/vfsub.h
+new file mode 100644
+index 0000000..0bd9719
+--- /dev/null
++++ b/fs/aufs/vfsub.h
+@@ -0,0 +1,600 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * sub-routines for VFS
++ *
++ * $Id: vfsub.h,v 1.44 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_VFSUB_H__
++#define __AUFS_VFSUB_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/namei.h>
++#include <linux/version.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)
++#include <linux/splice.h>
++#endif
++#include <linux/inotify.h>
++
++/* ---------------------------------------------------------------------- */
++
++/* vfsub flags */
++#define Vfsub_DLGT 1 /* operation with delegation */
++#define Vfsub_FORCE_UNLINK (1 << 1) /* force unlinking */
++#define vfsub_ftest(flags, name) ((flags) & Vfsub_##name)
++#define vfsub_fset(flags, name) { (flags) |= Vfsub_##name; }
++#define vfsub_fclr(flags, name) { (flags) &= ~Vfsub_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef Vfsub_DLGT
++#define Vfsub_DLGT 0
++#endif
++
++struct au_hin_ignore;
++struct vfsub_args {
++#ifdef CONFIG_AUFS_HINOTIFY
++ /* inotify events to be ignored */
++ int nignore;
++ struct au_hin_ignore *ignore;
++#endif
++
++ unsigned int flags;
++};
++
++struct au_hinode;
++#ifdef CONFIG_AUFS_HINOTIFY
++static inline
++void do_vfsub_args_reinit(struct vfsub_args *vargs, struct au_hin_ignore *ign)
++{
++ vargs->nignore = 0;
++ vargs->ignore = ign;
++}
++
++static inline void vfsub_args_reinit(struct vfsub_args *vargs)
++{
++ vargs->nignore = 0;
++}
++
++__u32 vfsub_events_notify_change(struct iattr *ia);
++void vfsub_ign_hinode(struct vfsub_args *vargs, __u32 events,
++ struct au_hinode *hinode);
++void vfsub_ignore(struct vfsub_args *vargs);
++void vfsub_unignore(struct vfsub_args *vargs);
++#else
++static inline
++void do_vfsub_args_reinit(struct vfsub_args *vargs, struct au_hin_ignore *ign)
++{
++ /* empty */
++}
++
++static inline void vfsub_args_reinit(struct vfsub_args *vargs)
++{
++ /* empty */
++}
++
++static inline __u32 vfsub_events_notify_change(struct iattr *ia)
++{
++ return 0;
++}
++
++static inline void vfsub_ign_hinode(struct vfsub_args *vargs, __u32 events,
++ struct au_hinode *hinode)
++{
++ /* empty */
++}
++
++static inline void vfsub_ignore(struct vfsub_args *vargs)
++{
++ /* empty */
++}
++
++static inline void vfsub_unignore(struct vfsub_args *vargs)
++{
++ /* empty */
++}
++#endif /* CONFIG_AUFS_HINOTIFY */
++
++void vfsub_args_init(struct vfsub_args *vargs, struct au_hin_ignore *ign,
++ int dlgt, int force_unlink);
++
++/* ---------------------------------------------------------------------- */
++
++/* inotify_inode_watched() is not exported */
++static inline int au_test_inotify(struct inode *inode)
++{
++#ifdef CONFIG_INOTIFY
++ return !list_empty(&inode->inotify_watches);
++#endif
++ return 0;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* lock subclass for hidden inode */
++/* default MAX_LOCKDEP_SUBCLASSES(8) is not enough */
++/* reduce? gave up. */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#define I_MUTEX_QUOTA 0
++#endif
++
++enum {
++ AuLsc_I_Begin = I_MUTEX_QUOTA, /* 4 */
++ AuLsc_I_PARENT, /* hidden inode, parent first */
++ AuLsc_I_PARENT2, /* copyup dirs */
++ AuLsc_I_PARENT3, /* rename with hinotify */
++ AuLsc_I_PARENT4, /* ditto */
++ AuLsc_I_CHILD,
++ AuLsc_I_CHILD2,
++ AuLsc_I_End
++};
++
++/* simple abstraction */
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 16)
++static inline void vfsub_i_lock(struct inode *i)
++{
++ down(&i->i_sem);
++}
++
++static inline void vfsub_i_lock_nested(struct inode *i, unsigned lsc)
++{
++ vfsub_i_lock(i);
++}
++
++static inline void vfsub_i_unlock(struct inode *i)
++{
++ up(&i->i_sem);
++}
++
++static inline int vfsub_i_trylock(struct inode *i)
++{
++ return !down_trylock(&i->i_sem);
++}
++
++#define IMustLock(i) AuDebugOn(!down_trylock(&(i)->i_sem))
++#else
++static inline void vfsub_i_lock(struct inode *i)
++{
++ mutex_lock(&i->i_mutex);
++}
++
++static inline void vfsub_i_lock_nested(struct inode *i, unsigned lsc)
++{
++ mutex_lock_nested(&i->i_mutex, lsc);
++}
++
++static inline void vfsub_i_unlock(struct inode *i)
++{
++ mutex_unlock(&i->i_mutex);
++}
++
++static inline int vfsub_i_trylock(struct inode *i)
++{
++ return mutex_trylock(&i->i_mutex);
++}
++
++#define IMustLock(i) MtxMustLock(&(i)->i_mutex)
++#endif /* LINUX_VERSION_CODE */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17)
++static inline void vfsub_lock_rename_mutex(struct super_block *sb)
++{
++ lockdep_off();
++ down(&sb->s_vfs_rename_sem);
++ lockdep_on();
++}
++
++static inline void vfsub_unlock_rename_mutex(struct super_block *sb)
++{
++ lockdep_off();
++ up(&sb->s_vfs_rename_sem);
++ lockdep_on();
++}
++
++static inline int vfsub_is_rename_mutex_locked(struct super_block *sb)
++{
++ int res;
++
++ lockdep_off();
++ res = down_trylock(&sb->s_vfs_rename_sem);
++ if (!res)
++ up(&sb->s_vfs_rename_sem);
++ lockdep_on();
++
++ return res;
++}
++#else
++static inline void vfsub_lock_rename_mutex(struct super_block *sb)
++{
++ lockdep_off();
++ mutex_lock(&sb->s_vfs_rename_mutex);
++ lockdep_on();
++}
++
++static inline void vfsub_unlock_rename_mutex(struct super_block *sb)
++{
++ lockdep_off();
++ mutex_unlock(&sb->s_vfs_rename_mutex);
++ lockdep_on();
++}
++
++static inline int vfsub_is_rename_mutex_locked(struct super_block *sb)
++{
++ int res;
++
++ lockdep_off();
++ res = mutex_is_locked(&sb->s_vfs_rename_mutex);
++ lockdep_on();
++
++ return res;
++}
++#endif /* LINUX_VERSION_CODE */
++
++static inline
++struct dentry *vfsub_lock_rename(struct dentry *d1, struct dentry *d2)
++{
++ struct dentry *d;
++
++ lockdep_off();
++ d = lock_rename(d1, d2);
++ lockdep_on();
++ return d;
++}
++
++static inline void vfsub_unlock_rename(struct dentry *d1, struct dentry *d2)
++{
++ lockdep_off();
++ unlock_rename(d1, d2);
++ lockdep_on();
++}
++
++static inline int au_verify_parent(struct dentry *dentry, struct inode *dir)
++{
++ IMustLock(dir);
++ return /* !dir->i_nlink || */ dentry->d_parent->d_inode != dir;
++}
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_WORKAROUND_FUSE
++/* br_fuse.c */
++int au_update_fuse_h_inode(struct vfsmount *h_mnt, struct dentry *h_dentry);
++#else
++static inline
++int au_update_fuse_h_inode(struct vfsmount *h_mnt, struct dentry *h_dentry)
++{
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_AUFS_BR_XFS
++/* br_xfs.c */
++dev_t au_h_rdev(struct inode *h_inode, struct vfsmount *h_mnt,
++ struct dentry *h_dentry);
++#else
++static inline
++dev_t au_h_rdev(struct inode *h_inode, struct vfsmount *h_mnt,
++ struct dentry *h_dentry)
++{
++ return h_inode->i_rdev;
++}
++#endif
++
++/* simple abstractions, for future use */
++static inline
++int do_vfsub_permission(struct inode *inode, int mask, struct nameidata *nd)
++{
++ LKTRTrace("i%lu, mask 0x%x, nd %d\n", inode->i_ino, mask, !!nd);
++ IMustLock(inode);
++ return permission(inode, mask, nd);
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct file *vfsub_filp_open(const char *path, int oflags, int mode);
++int vfsub_path_lookup(const char *name, unsigned int flags,
++ struct nameidata *nd);
++struct dentry *vfsub_lookup_one_len(const char *name, struct dentry *parent,
++ int len);
++
++#ifdef CONFIG_AUFS_LHASH_PATCH
++struct dentry *vfsub__lookup_hash(struct qstr *name, struct dentry *parent,
++ struct nameidata *nd);
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++int do_vfsub_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *nd);
++int do_vfsub_symlink(struct inode *dir, struct dentry *dentry,
++ const char *symname, int mode);
++int do_vfsub_mknod(struct inode *dir, struct dentry *dentry, int mode,
++ dev_t dev);
++int do_vfsub_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry);
++int do_vfsub_rename(struct inode *src_dir, struct dentry *src_dentry,
++ struct inode *dir, struct dentry *dentry);
++int do_vfsub_mkdir(struct inode *dir, struct dentry *dentry, int mode);
++int do_vfsub_rmdir(struct inode *dir, struct dentry *dentry);
++int do_vfsub_unlink(struct inode *dir, struct dentry *dentry);
++
++/* ---------------------------------------------------------------------- */
++
++ssize_t do_vfsub_read_u(struct file *file, char __user *ubuf, size_t count,
++ loff_t *ppos);
++/* todo: kernel_read()? */
++ssize_t do_vfsub_read_k(struct file *file, void *kbuf, size_t count,
++ loff_t *ppos);
++ssize_t do_vfsub_write_u(struct file *file, const char __user *ubuf,
++ size_t count, loff_t *ppos);
++ssize_t do_vfsub_write_k(struct file *file, void *kbuf, size_t count,
++ loff_t *ppos);
++int do_vfsub_readdir(struct file *file, filldir_t filldir, void *arg);
++
++/* ---------------------------------------------------------------------- */
++
++#ifndef CONFIG_AUFS_UNIONFS23_PATCH
++#define vfs_splice_to do_splice_to
++#define vfs_splice_from do_splice_from
++#endif
++
++#ifdef CONFIG_AUFS_SPLICE_PATCH
++long do_vfsub_splice_to(struct file *in, loff_t *ppos,
++ struct pipe_inode_info *pipe, size_t len,
++ unsigned int flags);
++long do_vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out,
++ loff_t *ppos, size_t len, unsigned int flags);
++#else
++static inline
++long do_vfsub_splice_to(struct file *in, loff_t *ppos,
++ struct pipe_inode_info *pipe, size_t len,
++ unsigned int flags)
++{
++ return -ENOSYS;
++}
++
++static inline
++long do_vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out,
++ loff_t *ppos, size_t len, unsigned int flags)
++{
++ return -ENOSYS;
++}
++#endif /* CONFIG_AUFS_SPLICE_PATCH */
++
++/* ---------------------------------------------------------------------- */
++
++static inline loff_t vfsub_llseek(struct file *file, loff_t offset, int origin)
++{
++ loff_t err;
++
++ LKTRTrace("%.*s\n", AuDLNPair(file->f_dentry));
++
++ lockdep_off();
++ err = vfs_llseek(file, offset, origin);
++ lockdep_on();
++ return err;
++}
++
++static inline int do_vfsub_getattr(struct vfsmount *mnt, struct dentry *dentry,
++ struct kstat *st)
++{
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++ return vfs_getattr(mnt, dentry, st);
++}
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_HIN_OR_DLGT
++/* hin_or_dlgt.c */
++int vfsub_permission(struct inode *inode, int mask, struct nameidata *nd,
++ int dlgt);
++
++int vfsub_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *nd, struct vfsub_args *vargs);
++int vfsub_symlink(struct inode *dir, struct dentry *dentry, const char *symname,
++ int mode, struct vfsub_args *vargs);
++int vfsub_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev,
++ struct vfsub_args *vargs);
++int vfsub_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry, struct vfsub_args *vargs);
++int vfsub_rename(struct inode *src_dir, struct dentry *src_dentry,
++ struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs);
++int vfsub_mkdir(struct inode *dir, struct dentry *dentry, int mode,
++ struct vfsub_args *vargs);
++int vfsub_rmdir(struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs);
++
++ssize_t vfsub_read_u(struct file *file, char __user *ubuf, size_t count,
++ loff_t *ppos, int dlgt);
++ssize_t vfsub_read_k(struct file *file, void *kbuf, size_t count, loff_t *ppos,
++ int dlgt);
++ssize_t vfsub_write_u(struct file *file, const char __user *ubuf, size_t count,
++ loff_t *ppos, struct vfsub_args *vargs);
++ssize_t vfsub_write_k(struct file *file, void *kbuf, size_t count, loff_t *ppos,
++ struct vfsub_args *vargs);
++int vfsub_readdir(struct file *file, filldir_t filldir, void *arg, int dlgt);
++long vfsub_splice_to(struct file *in, loff_t *ppos,
++ struct pipe_inode_info *pipe, size_t len,
++ unsigned int flags, int dlgt);
++long vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out,
++ loff_t *ppos, size_t len, unsigned int flags,
++ struct vfsub_args *vargs);
++
++int vfsub_getattr(struct vfsmount *mnt, struct dentry *dentry, struct kstat *st,
++ int dlgt);
++#else
++
++static inline
++int vfsub_permission(struct inode *inode, int mask, struct nameidata *nd,
++ int dlgt)
++{
++ return do_vfsub_permission(inode, mask, nd);
++}
++
++static inline
++int vfsub_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *nd, struct vfsub_args *vargs)
++{
++ return do_vfsub_create(dir, dentry, mode, nd);
++}
++
++static inline
++int vfsub_symlink(struct inode *dir, struct dentry *dentry, const char *symname,
++ int mode, struct vfsub_args *vargs)
++{
++ return do_vfsub_symlink(dir, dentry, symname, mode);
++}
++
++static inline
++int vfsub_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev,
++ struct vfsub_args *vargs)
++{
++ return do_vfsub_mknod(dir, dentry, mode, dev);
++}
++
++static inline
++int vfsub_link(struct dentry *src_dentry, struct inode *dir,
++ struct dentry *dentry, struct vfsub_args *vargs)
++{
++ return do_vfsub_link(src_dentry, dir, dentry);
++}
++
++static inline
++int vfsub_rename(struct inode *src_dir, struct dentry *src_dentry,
++ struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs)
++{
++ return do_vfsub_rename(src_dir, src_dentry, dir, dentry);
++}
++
++static inline
++int vfsub_mkdir(struct inode *dir, struct dentry *dentry, int mode,
++ struct vfsub_args *vargs)
++{
++ return do_vfsub_mkdir(dir, dentry, mode);
++}
++
++static inline
++int vfsub_rmdir(struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs)
++{
++ return do_vfsub_rmdir(dir, dentry);
++}
++
++static inline
++ssize_t vfsub_read_u(struct file *file, char __user *ubuf, size_t count,
++ loff_t *ppos, int dlgt)
++{
++ return do_vfsub_read_u(file, ubuf, count, ppos);
++}
++
++static inline
++ssize_t vfsub_read_k(struct file *file, void *kbuf, size_t count, loff_t *ppos,
++ int dlgt)
++{
++ return do_vfsub_read_k(file, kbuf, count, ppos);
++}
++
++static inline
++ssize_t vfsub_write_u(struct file *file, const char __user *ubuf, size_t count,
++ loff_t *ppos, struct vfsub_args *vargs)
++{
++ return do_vfsub_write_u(file, ubuf, count, ppos);
++}
++
++static inline
++ssize_t vfsub_write_k(struct file *file, void *kbuf, size_t count, loff_t *ppos,
++ struct vfsub_args *vargs)
++{
++ return do_vfsub_write_k(file, kbuf, count, ppos);
++}
++
++static inline
++int vfsub_readdir(struct file *file, filldir_t filldir, void *arg, int dlgt)
++{
++ return do_vfsub_readdir(file, filldir, arg);
++}
++
++static inline
++long vfsub_splice_to(struct file *in, loff_t *ppos,
++ struct pipe_inode_info *pipe, size_t len,
++ unsigned int flags, int dlgt)
++{
++ return do_vfsub_splice_to(in, ppos, pipe, len, flags);
++}
++
++static inline
++long vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out,
++ loff_t *ppos, size_t len, unsigned int flags,
++ struct vfsub_args *vargs)
++{
++ return do_vfsub_splice_from(pipe, out, ppos, len, flags);
++}
++
++static inline
++int vfsub_getattr(struct vfsmount *mnt, struct dentry *dentry, struct kstat *st,
++ int dlgt)
++{
++ return do_vfsub_getattr(mnt, dentry, st);
++}
++#endif /* HIN_OR_DLGT */
++
++/* ---------------------------------------------------------------------- */
++
++int vfsub_sio_mkdir(struct au_hinode *hdir, struct dentry *dentry, int mode,
++ int dlgt);
++int vfsub_sio_rmdir(struct au_hinode *hdir, struct dentry *dentry, int dlgt);
++int vfsub_sio_notify_change(struct au_hinode *hdir, struct dentry *dentry,
++ struct iattr *ia);
++
++/* ---------------------------------------------------------------------- */
++
++int vfsub_notify_change(struct dentry *dentry, struct iattr *ia,
++ struct vfsub_args *vargs);
++int vfsub_unlink(struct inode *dir, struct dentry *dentry,
++ struct vfsub_args *vargs);
++int vfsub_statfs(void *arg, struct kstatfs *buf, int dlgt);
++
++/* ---------------------------------------------------------------------- */
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
++/* introduced in linux-2.6.20 */
++struct path {
++ struct vfsmount *mnt;
++ struct dentry *dentry;
++};
++#endif
++
++/* introduced in linux-2.6.25 */
++static inline void path_get(struct path *path)
++{
++ mntget(path->mnt);
++ dget(path->dentry);
++}
++
++static inline void path_put(struct path *path)
++{
++ dput(path->dentry);
++ mntput(path->mnt);
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_VFSUB_H__ */
+diff --git a/fs/aufs/wbr_policy.c b/fs/aufs/wbr_policy.c
+new file mode 100644
+index 0000000..701b4a1
+--- /dev/null
++++ b/fs/aufs/wbr_policy.c
+@@ -0,0 +1,702 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * policies for selecting one among multiple writable branches
++ *
++ * $Id: wbr_policy.c,v 1.20 2009/01/26 06:23:51 sfjro Exp $
++ */
++
++#include <linux/statfs.h>
++#include "aufs.h"
++
++static int au_cpdown_attr(struct au_hinode *hdir, struct dentry *h_dst,
++ struct dentry *h_src)
++{
++ int err, sbits;
++ struct iattr ia;
++ struct inode *h_idst, *h_isrc;
++
++ LKTRTrace("%.*s\n", AuDLNPair(h_dst));
++ h_idst = h_dst->d_inode;
++ /* todo? IMustLock(h_idst); */
++ h_isrc = h_src->d_inode;
++ /* todo? IMustLock(h_isrc); */
++
++ ia.ia_valid = ATTR_FORCE | ATTR_MODE | ATTR_UID | ATTR_GID;
++ ia.ia_mode = h_isrc->i_mode;
++ ia.ia_uid = h_isrc->i_uid;
++ ia.ia_gid = h_isrc->i_gid;
++ sbits = !!(ia.ia_mode & (S_ISUID | S_ISGID));
++ au_cpup_attr_flags(h_idst, h_isrc);
++ err = vfsub_sio_notify_change(hdir, h_dst, &ia);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)
++ /* is this nfs only? */
++ if (!err && sbits && au_test_nfs(h_dst->d_sb)) {
++ ia.ia_valid = ATTR_FORCE | ATTR_MODE;
++ ia.ia_mode = h_isrc->i_mode;
++ err = vfsub_sio_notify_change(hdir, h_dst, &ia);
++ }
++#endif
++
++ AuTraceErr(err);
++ return err;
++}
++
++struct au_cpdown_dir_args {
++ struct dentry *parent;
++ unsigned int parent_opq; /* bit-flags */
++};
++
++static int au_cpdown_dir(struct dentry *dentry, aufs_bindex_t bdst,
++ struct dentry *h_parent, void *arg)
++{
++ int err, rerr;
++ struct au_cpdown_dir_args *args = arg;
++ aufs_bindex_t bend, bopq, bstart;
++ unsigned char parent_opq, whed, dlgt, do_opq, made_dir, diropq;
++ struct dentry *h_dentry, *opq_dentry, *wh_dentry, *parent;
++ struct inode *h_dir, *h_inode, *inode, *dir;
++
++ LKTRTrace("%.*s, b%d\n", AuDLNPair(dentry), bdst);
++ bstart = au_dbstart(dentry);
++ AuDebugOn(bstart <= bdst
++ && bdst <= au_dbend(dentry)
++ && au_h_dptr(dentry, bdst));
++ AuDebugOn(!h_parent);
++ /* todo: safe? */
++ parent = dget_parent(dentry);
++ dir = parent->d_inode;
++ dput(parent);
++ h_dir = h_parent->d_inode;
++ AuDebugOn(!h_dir);
++ AuDebugOn(h_dir != au_h_iptr(dir, bdst));
++ IMustLock(h_dir);
++
++ err = au_lkup_neg(dentry, bdst);
++ if (unlikely(err < 0))
++ goto out;
++ h_dentry = au_h_dptr(dentry, bdst);
++ dlgt = !!au_test_dlgt(au_mntflags(dentry->d_sb));
++ err = vfsub_sio_mkdir(au_hi(dir, bdst), h_dentry,
++ S_IRWXU | S_IRUGO | S_IXUGO, dlgt);
++ if (unlikely(err))
++ goto out_put;
++
++ made_dir = 1;
++ bend = au_dbend(dentry);
++ bopq = au_dbdiropq(dentry);
++ whed = (au_dbwh(dentry) == bdst);
++ if (!args->parent_opq)
++ args->parent_opq |= (bopq <= bdst);
++ parent_opq = (args->parent_opq && args->parent == dentry);
++ do_opq = 0;
++ diropq = 0;
++ h_inode = h_dentry->d_inode;
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ if (whed || (parent_opq && do_opq)) {
++ opq_dentry = au_diropq_create(dentry, bdst, dlgt);
++ err = PTR_ERR(opq_dentry);
++ if (IS_ERR(opq_dentry)) {
++ vfsub_i_unlock(h_inode);
++ goto out_dir;
++ }
++ dput(opq_dentry);
++ diropq = 1;
++ }
++
++ err = au_cpdown_attr(au_hi(dir, bdst), h_dentry,
++ au_h_dptr(dentry, bstart));
++ vfsub_i_unlock(h_inode);
++ if (unlikely(err))
++ goto out_opq;
++
++ wh_dentry = NULL;
++ if (whed) {
++ wh_dentry = au_wh_lkup(h_parent, &dentry->d_name, /*ndx*/NULL);
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out_opq;
++ err = 0;
++ if (wh_dentry->d_inode)
++ err = au_wh_unlink_dentry(au_hi(dir, bdst), wh_dentry,
++ dentry, dlgt);
++ dput(wh_dentry);
++ if (unlikely(err))
++ goto out_opq;
++ }
++
++ inode = dentry->d_inode;
++ if (au_ibend(inode) < bdst)
++ au_set_ibend(inode, bdst);
++ au_set_h_iptr(inode, bdst, au_igrab(h_inode), au_hi_flags(inode, 1));
++ goto out; /* success */
++
++ /* revert */
++ out_opq:
++ if (diropq) {
++ vfsub_i_lock_nested(h_inode, AuLsc_I_CHILD);
++ rerr = au_diropq_remove(dentry, bdst, dlgt);
++ vfsub_i_unlock(h_inode);
++ if (unlikely(rerr)) {
++ AuIOErr("failed removing diropq for %.*s b%d (%d)\n",
++ AuDLNPair(dentry), bdst, rerr);
++ err = -EIO;
++ goto out;
++ }
++ }
++ out_dir:
++ if (made_dir) {
++ rerr = vfsub_sio_rmdir(au_hi(dir, bdst), h_dentry, dlgt);
++ if (unlikely(rerr)) {
++ AuIOErr("failed removing %.*s b%d (%d)\n",
++ AuDLNPair(dentry), bdst, rerr);
++ err = -EIO;
++ }
++ }
++ out_put:
++ au_set_h_dptr(dentry, bdst, NULL);
++ if (au_dbend(dentry) == bdst)
++ au_update_dbend(dentry);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_cpdown_dirs(struct dentry *dentry, aufs_bindex_t bdst)
++{
++ int err;
++ struct au_cpdown_dir_args args = {
++ .parent = dget_parent(dentry),
++ .parent_opq = 0
++ };
++
++ LKTRTrace("%.*s, b%d\n", AuDLNPair(dentry), bdst);
++
++ err = au_cp_dirs(dentry, bdst, au_cpdown_dir, &args);
++ dput(args.parent);
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* policies for create */
++
++static int au_wbr_bu(struct super_block *sb, aufs_bindex_t bindex)
++{
++ for (; bindex >= 0; bindex--)
++ if (!au_br_rdonly(au_sbr(sb, bindex)))
++ return bindex;
++ return -EROFS;
++}
++
++/* top down parent */
++static int au_wbr_create_tdp(struct dentry *dentry, int isdir)
++{
++ int err;
++ struct super_block *sb;
++ aufs_bindex_t bstart, bindex;
++ unsigned char dirperm1;
++ struct dentry *parent, *h_parent;
++ struct inode *h_dir;
++
++ LKTRTrace("%.*s, dir %d\n", AuDLNPair(dentry), isdir);
++
++ sb = dentry->d_sb;
++ dirperm1 = !!au_test_dirperm1(au_mntflags(sb));
++ bstart = au_dbstart(dentry);
++ AuDebugOn(bstart < 0);
++ err = bstart;
++ /* todo: can 'err' be an illegal? */
++ if (/* err >= 0 && */ !au_br_rdonly(au_sbr(sb, bstart)))
++ goto out;
++
++ err = -EROFS;
++ parent = dget_parent(dentry);
++ for (bindex = au_dbstart(parent); bindex < bstart; bindex++) {
++ h_parent = au_h_dptr(parent, bindex);
++ if (!h_parent)
++ continue;
++ h_dir = h_parent->d_inode;
++ if (!h_dir)
++ continue;
++
++ if (!au_br_rdonly(au_sbr(sb, bindex))
++ && (!dirperm1
++ || au_test_h_perm(h_dir, MAY_WRITE | MAY_EXEC,
++ /*dlgt*/0))) {
++ err = bindex;
++ break;
++ }
++ }
++ dput(parent);
++
++ /* bottom up here */
++ if (unlikely(err < 0))
++ err = au_wbr_bu(sb, bstart - 1);
++
++ out:
++ LKTRTrace("b%d\n", err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* an exception for the policy other than tdp */
++static int au_wbr_create_exp(struct dentry *dentry)
++{
++ int err;
++ struct dentry *parent;
++ aufs_bindex_t bwh, bdiropq;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ err = -1;
++ bwh = au_dbwh(dentry);
++ parent = dget_parent(dentry);
++ bdiropq = au_dbdiropq(parent);
++ if (bwh >= 0) {
++ if (bdiropq >= 0)
++ err = min(bdiropq, bwh);
++ else
++ err = bwh;
++ LKTRTrace("%d\n", err);
++ } else if (bdiropq >= 0) {
++ err = bdiropq;
++ LKTRTrace("%d\n", err);
++ }
++ dput(parent);
++
++ if (err >= 0 && au_br_rdonly(au_sbr(dentry->d_sb, err)))
++ err = -1;
++
++ LKTRTrace("%d\n", err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* round robin */
++static int au_wbr_create_init_rr(struct super_block *sb)
++{
++ int err;
++
++ err = au_wbr_bu(sb, au_sbend(sb));
++ atomic_set(&au_sbi(sb)->si_wbr_rr_next, -err); /* less important */
++
++ LKTRTrace("b%d\n", err);
++ return err;
++}
++
++static int au_wbr_create_rr(struct dentry *dentry, int isdir)
++{
++ int err, nbr;
++ struct super_block *sb;
++ atomic_t *next;
++ unsigned int u;
++ aufs_bindex_t bindex, bend;
++
++ LKTRTrace("%.*s, dir %d\n", AuDLNPair(dentry), isdir);
++
++ sb = dentry->d_sb;
++ next = NULL;
++ err = au_wbr_create_exp(dentry);
++ if (err >= 0)
++ goto out;
++
++ next = &au_sbi(sb)->si_wbr_rr_next;
++ bend = au_sbend(sb);
++ nbr = bend + 1;
++ for (bindex = 0; bindex <= bend; bindex++) {
++ if (!isdir) {
++ err = atomic_dec_return(next) + 1;
++ /* modulo for 0 is meaningless */
++ if (unlikely(!err))
++ err = atomic_dec_return(next) + 1;
++ } else
++ err = atomic_read(next);
++ LKTRTrace("%d\n", err);
++ u = err;
++ err = u % nbr;
++ LKTRTrace("%d\n", err);
++ if (!au_br_rdonly(au_sbr(sb, err)))
++ break;
++ err = -EROFS;
++ }
++
++ out:
++ LKTRTrace("%d\n", err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* most free space */
++static void *au_wbr_statfs_arg(struct au_branch *br, struct super_block *sb,
++ aufs_bindex_t bindex)
++{
++ struct super_block *h_sb;
++
++ h_sb = br->br_mnt->mnt_sb;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++ return h_sb;
++#else
++ if (!au_test_nfs(h_sb))
++ return h_sb->s_root;
++
++ /* sigh,,, why nfs s_root has wrong inode? */
++ return au_di(sb->s_root)->di_hdentry[0 + bindex].hd_dentry;
++#endif
++}
++
++static void au_mfs(struct dentry *dentry)
++{
++ struct super_block *sb;
++ aufs_bindex_t bindex, bend;
++ unsigned char dlgt;
++ int err;
++ struct kstatfs st;
++ unsigned long long b, bavail;
++ void *arg;
++ struct au_branch *br;
++ struct au_wbr_mfs *mfs;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ bavail = 0;
++ sb = dentry->d_sb;
++ mfs = &au_sbi(sb)->si_wbr_mfs;
++ mfs->mfs_bindex = -EROFS;
++ mfs->mfsrr_bytes = 0;
++ dlgt = !!au_test_dlgt(au_mntflags(sb));
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++) {
++ br = au_sbr(sb, bindex);
++ if (au_br_rdonly(br))
++ continue;
++ AuDebugOn(!br->br_wbr);
++ arg = au_wbr_statfs_arg(br, sb, bindex);
++ if (!arg)
++ continue;
++
++ err = vfsub_statfs(arg, &st, dlgt);
++ LKTRTrace("b%d, %d, %llu\n",
++ bindex, err, (unsigned long long)st.f_bavail);
++ if (unlikely(err)) {
++ AuWarn1("failed statfs, b%d, %d\n", bindex, err);
++ continue;
++ }
++
++ /* when the available size is equal, select lower one */
++ b = st.f_bavail * st.f_bsize;
++ br->br_wbr->wbr_bytes = b;
++ if (b >= bavail) {
++ bavail = b;
++ mfs->mfs_bindex = bindex;
++ mfs->mfs_jiffy = jiffies;
++ }
++ }
++
++ mfs->mfsrr_bytes = bavail;
++ LKTRTrace("b%d\n", mfs->mfs_bindex);
++}
++
++static int au_wbr_create_mfs(struct dentry *dentry, int isdir)
++{
++ int err;
++ struct super_block *sb;
++ struct au_wbr_mfs *mfs;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ sb = dentry->d_sb;
++ err = au_wbr_create_exp(dentry);
++ if (err >= 0)
++ goto out;
++
++ mfs = &au_sbi(sb)->si_wbr_mfs;
++ mutex_lock(&mfs->mfs_lock);
++ if (unlikely(time_after(jiffies, mfs->mfs_jiffy + mfs->mfs_expire)
++ || mfs->mfs_bindex < 0
++ || au_br_rdonly(au_sbr(sb, mfs->mfs_bindex))))
++ au_mfs(dentry);
++ mutex_unlock(&mfs->mfs_lock);
++ err = mfs->mfs_bindex;
++
++ out:
++ LKTRTrace("b%d\n", err);
++ return err;
++}
++
++static int au_wbr_create_init_mfs(struct super_block *sb)
++{
++ struct au_wbr_mfs *mfs;
++
++ mfs = &au_sbi(sb)->si_wbr_mfs;
++ LKTRTrace("expire %lu\n", mfs->mfs_expire);
++
++ mutex_init(&mfs->mfs_lock);
++ mfs->mfs_jiffy = 0;
++ mfs->mfs_bindex = -EROFS;
++
++ return 0;
++}
++
++static int au_wbr_create_fin_mfs(struct super_block *sb)
++{
++ AuTraceEnter();
++ mutex_destroy(&au_sbi(sb)->si_wbr_mfs.mfs_lock);
++ return 0;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* most free space and then round robin */
++static int au_wbr_create_mfsrr(struct dentry *dentry, int isdir)
++{
++ int err;
++ struct au_wbr_mfs *mfs;
++
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), isdir);
++
++ err = au_wbr_create_mfs(dentry, isdir);
++ if (err >= 0) {
++ mfs = &au_sbi(dentry->d_sb)->si_wbr_mfs;
++ LKTRTrace("%llu bytes, %llu wmark\n",
++ mfs->mfsrr_bytes, mfs->mfsrr_watermark);
++ if (mfs->mfsrr_bytes < mfs->mfsrr_watermark)
++ err = au_wbr_create_rr(dentry, isdir);
++ }
++
++ LKTRTrace("b%d\n", err);
++ return err;
++}
++
++static int au_wbr_create_init_mfsrr(struct super_block *sb)
++{
++ int err;
++
++ au_wbr_create_init_mfs(sb); /* ignore */
++ err = au_wbr_create_init_rr(sb);
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* top down parent and most free space */
++static int au_wbr_create_pmfs(struct dentry *dentry, int isdir)
++{
++ int err, e2;
++ struct super_block *sb;
++ struct dentry *parent, *h_parent;
++ aufs_bindex_t bindex, bstart, bend;
++ unsigned char dirperm1;
++ struct au_branch *br;
++ unsigned long long b;
++ struct inode *h_dir;
++
++ LKTRTrace("%.*s, %d\n", AuDLNPair(dentry), isdir);
++
++ err = au_wbr_create_tdp(dentry, isdir);
++ if (unlikely(err < 0))
++ goto out;
++ parent = dget_parent(dentry);
++ bstart = au_dbstart(parent);
++ bend = au_dbtaildir(parent);
++ if (bstart == bend)
++ goto out_parent; /* success */
++
++ e2 = au_wbr_create_mfs(dentry, isdir);
++ if (e2 < 0)
++ goto out_parent; /* success */
++
++ /* when the available size is equal, select upper one */
++ sb = dentry->d_sb;
++ br = au_sbr(sb, err);
++ AuDebugOn(!br->br_wbr);
++ dirperm1 = !!au_test_dirperm1(au_mntflags(sb));
++ b = br->br_wbr->wbr_bytes;
++ LKTRTrace("b%d, %llu\n", err, b);
++
++ if (dirperm1) {
++ for (bindex = bstart; bindex <= bend; bindex++) {
++ h_parent = au_h_dptr(parent, bindex);
++ if (!h_parent)
++ continue;
++ h_dir = h_parent->d_inode;
++ if (!h_dir)
++ continue;
++
++ br = au_sbr(sb, bindex);
++ if (!au_br_rdonly(br)
++ && au_test_h_perm(h_dir, MAY_WRITE | MAY_EXEC,
++ /*dlgt*/0)
++ && br->br_wbr->wbr_bytes > b) {
++ b = br->br_wbr->wbr_bytes;
++ err = bindex;
++ LKTRTrace("b%d, %llu\n", err, b);
++ }
++ }
++ if (err >= 0)
++ goto out_parent;
++ }
++ for (bindex = bstart; bindex <= bend; bindex++) {
++ h_parent = au_h_dptr(parent, bindex);
++ if (!h_parent || !h_parent->d_inode)
++ continue;
++
++ br = au_sbr(sb, bindex);
++ if (!au_br_rdonly(br) && br->br_wbr->wbr_bytes > b) {
++ b = br->br_wbr->wbr_bytes;
++ err = bindex;
++ LKTRTrace("b%d, %llu\n", err, b);
++ }
++ }
++
++ out_parent:
++ dput(parent);
++ out:
++ LKTRTrace("b%d\n", err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* policies for copyup */
++
++/* top down parent */
++static int au_wbr_copyup_tdp(struct dentry *dentry)
++{
++ return au_wbr_create_tdp(dentry, /*isdir, anything is ok*/0);
++}
++
++/* bottom up parent */
++static int au_wbr_copyup_bup(struct dentry *dentry)
++{
++ int err;
++ struct dentry *parent, *h_parent;
++ aufs_bindex_t bindex, bstart;
++ unsigned char dirperm1;
++ struct super_block *sb;
++ struct inode *h_dir;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ err = -EROFS;
++ sb = dentry->d_sb;
++ dirperm1 = !!au_test_dirperm1(au_mntflags(sb));
++ parent = dget_parent(dentry);
++ bstart = au_dbstart(parent);
++ for (bindex = au_dbstart(dentry); bindex >= bstart; bindex--) {
++ h_parent = au_h_dptr(parent, bindex);
++ if (!h_parent)
++ continue;
++ h_dir = h_parent->d_inode;
++ if (!h_dir)
++ continue;
++
++ if (!au_br_rdonly(au_sbr(sb, bindex))
++ && (!dirperm1
++ || au_test_h_perm(h_dir, MAY_WRITE | MAY_EXEC,
++ /*dlgt*/0))) {
++ err = bindex;
++ break;
++ }
++ }
++ dput(parent);
++
++ /* bottom up here */
++ if (unlikely(err < 0))
++ err = au_wbr_bu(sb, bstart - 1);
++
++ LKTRTrace("b%d\n", err);
++ return err;
++}
++
++/* bottom up */
++static int au_wbr_copyup_bu(struct dentry *dentry)
++{
++ int err;
++
++ LKTRTrace("%.*s\n", AuDLNPair(dentry));
++
++ err = au_wbr_bu(dentry->d_sb, au_dbstart(dentry));
++
++ LKTRTrace("b%d\n", err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct au_wbr_copyup_operations au_wbr_copyup_ops[] = {
++ [AuWbrCopyup_TDP] = {
++ .copyup = au_wbr_copyup_tdp
++ },
++ [AuWbrCopyup_BUP] = {
++ .copyup = au_wbr_copyup_bup
++ },
++ [AuWbrCopyup_BU] = {
++ .copyup = au_wbr_copyup_bu
++ }
++};
++
++struct au_wbr_create_operations au_wbr_create_ops[] = {
++ [AuWbrCreate_TDP] = {
++ .create = au_wbr_create_tdp
++ },
++ [AuWbrCreate_RR] = {
++ .create = au_wbr_create_rr,
++ .init = au_wbr_create_init_rr
++ },
++ [AuWbrCreate_MFS] = {
++ .create = au_wbr_create_mfs,
++ .init = au_wbr_create_init_mfs,
++ .fin = au_wbr_create_fin_mfs
++ },
++ [AuWbrCreate_MFSV] = {
++ .create = au_wbr_create_mfs,
++ .init = au_wbr_create_init_mfs,
++ .fin = au_wbr_create_fin_mfs
++ },
++ [AuWbrCreate_MFSRR] = {
++ .create = au_wbr_create_mfsrr,
++ .init = au_wbr_create_init_mfsrr,
++ .fin = au_wbr_create_fin_mfs
++ },
++ [AuWbrCreate_MFSRRV] = {
++ .create = au_wbr_create_mfsrr,
++ .init = au_wbr_create_init_mfsrr,
++ .fin = au_wbr_create_fin_mfs
++ },
++ [AuWbrCreate_PMFS] = {
++ .create = au_wbr_create_pmfs,
++ .init = au_wbr_create_init_mfs,
++ .fin = au_wbr_create_fin_mfs
++ },
++ [AuWbrCreate_PMFSV] = {
++ .create = au_wbr_create_pmfs,
++ .init = au_wbr_create_init_mfs,
++ .fin = au_wbr_create_fin_mfs
++ }
++};
+diff --git a/fs/aufs/whout.c b/fs/aufs/whout.c
+new file mode 100644
+index 0000000..79f44dd
+--- /dev/null
++++ b/fs/aufs/whout.c
+@@ -0,0 +1,1162 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * whiteout for logical deletion and opaque directory
++ *
++ * $Id: whout.c,v 1.47 2009/01/26 06:24:19 sfjro Exp $
++ */
++
++#include <linux/fs.h>
++#include <linux/namei.h>
++#include <linux/random.h>
++#include <linux/security.h>
++#include "aufs.h"
++
++#define WH_MASK S_IRUGO
++
++/* If a directory contains this file, then it is opaque. We start with the
++ * .wh. flag so that it is blocked by lookup.
++ */
++static struct qstr diropq_name = {
++ .name = AUFS_WH_DIROPQ,
++ .len = sizeof(AUFS_WH_DIROPQ) - 1
++};
++
++/*
++ * generate whiteout name, which is NOT terminated by NULL.
++ * @name: original d_name.name
++ * @len: original d_name.len
++ * @wh: whiteout qstr
++ * returns zero when succeeds, otherwise error.
++ * succeeded value as wh->name should be freed by au_wh_name_free().
++ */
++int au_wh_name_alloc(const char *name, int len, struct qstr *wh)
++{
++ char *p;
++
++ AuDebugOn(!name || !len || !wh);
++
++ if (unlikely(len > PATH_MAX - AUFS_WH_PFX_LEN))
++ return -ENAMETOOLONG;
++
++ wh->len = len + AUFS_WH_PFX_LEN;
++ p = kmalloc(wh->len, GFP_NOFS);
++ wh->name = p;
++ if (p) {
++ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN);
++ memcpy(p + AUFS_WH_PFX_LEN, name, len);
++ /* smp_mb(); */
++ return 0;
++ }
++ return -ENOMEM;
++}
++
++void au_wh_name_free(struct qstr *wh)
++{
++ AuDebugOn(!wh || !wh->name);
++ kfree(wh->name);
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * test if the @wh_name exists under @h_parent.
++ * @try_sio specifies the necessary of super-io.
++ */
++int au_wh_test(struct dentry *h_parent, struct qstr *wh_name, int try_sio,
++ struct au_ndx *ndx)
++{
++ int err;
++ struct dentry *wh_dentry;
++ struct inode *h_dir;
++ unsigned int flags;
++
++ LKTRTrace("%.*s/%.*s, ndx{%p, 0x%x}\n", AuDLNPair(h_parent),
++ wh_name->len, wh_name->name, ndx->nfsmnt, ndx->flags);
++ h_dir = h_parent->d_inode;
++ AuDebugOn(!S_ISDIR(h_dir->i_mode));
++
++ flags = 0;
++ if (ndx && ndx->nd) {
++ flags = ndx->nd->flags;
++ ndx->nd->flags &= ~(LOOKUP_OPEN | LOOKUP_CREATE);
++ }
++
++ if (!try_sio)
++ wh_dentry = au_lkup_one(wh_name->name, h_parent,
++ wh_name->len, ndx);
++ else
++ wh_dentry = au_sio_lkup_one(wh_name->name, h_parent,
++ wh_name->len, ndx);
++ if (flags)
++ ndx->nd->flags = flags;
++ err = PTR_ERR(wh_dentry);
++ if (IS_ERR(wh_dentry))
++ goto out;
++
++ err = 0;
++ if (!wh_dentry->d_inode)
++ goto out_wh; /* success */
++
++ err = 1;
++ if (S_ISREG(wh_dentry->d_inode->i_mode))
++ goto out_wh; /* success */
++
++ err = -EIO;
++ AuIOErr("%.*s Invalid whiteout entry type 0%o.\n",
++ AuDLNPair(wh_dentry), wh_dentry->d_inode->i_mode);
++
++ out_wh:
++ dput(wh_dentry);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * test if the @h_dentry sets opaque or not.
++ */
++int au_diropq_test(struct dentry *h_dentry, struct au_ndx *ndx)
++{
++ int err, try_sio;
++ struct inode *h_dir;
++
++ LKTRTrace("dentry %.*s\n", AuDLNPair(h_dentry));
++ h_dir = h_dentry->d_inode;
++ AuDebugOn(!S_ISDIR(h_dir->i_mode));
++
++ try_sio = au_test_h_perm_sio(h_dir, MAY_EXEC,
++ au_ftest_ndx(ndx->flags, DLGT));
++ err = au_wh_test(h_dentry, &diropq_name, try_sio, ndx);
++ AuTraceErr(err);
++ return err;
++}
++
++/*
++ * returns a negative dentry whose name is unique and temporary.
++ */
++struct dentry *au_whtmp_lkup(struct dentry *h_parent, struct qstr *prefix,
++ struct au_ndx *ndx)
++{
++#define HEX_LEN 4
++ struct dentry *dentry;
++ int len, i;
++ char defname[AUFS_WH_PFX_LEN * 2 + DNAME_INLINE_LEN_MIN + 1
++ + HEX_LEN + 1], *name, *p;
++ static unsigned char cnt;
++
++ LKTRTrace("hp %.*s, prefix %.*s\n",
++ AuDLNPair(h_parent), prefix->len, prefix->name);
++ AuDebugOn(!h_parent->d_inode);
++
++ name = defname;
++ len = sizeof(defname) - DNAME_INLINE_LEN_MIN + prefix->len - 1;
++ if (unlikely(prefix->len > DNAME_INLINE_LEN_MIN)) {
++ dentry = ERR_PTR(-ENAMETOOLONG);
++ if (unlikely(len >= PATH_MAX))
++ goto out;
++ dentry = ERR_PTR(-ENOMEM);
++ name = kmalloc(len + 1, GFP_NOFS);
++ if (unlikely(!name))
++ goto out;
++ }
++
++ /* doubly whiteout-ed */
++ memcpy(name, AUFS_WH_PFX AUFS_WH_PFX, AUFS_WH_PFX_LEN * 2);
++ p = name + AUFS_WH_PFX_LEN * 2;
++ memcpy(p, prefix->name, prefix->len);
++ p += prefix->len;
++ *p++ = '.';
++ AuDebugOn(name + len + 1 - p <= HEX_LEN);
++
++ for (i = 0; i < 3; i++) {
++ sprintf(p, "%.*d", HEX_LEN, cnt++);
++ dentry = au_sio_lkup_one(name, h_parent, len, ndx);
++ if (IS_ERR(dentry) || !dentry->d_inode)
++ goto out_name;
++ dput(dentry);
++ }
++ /* AuWarn("could not get random name\n"); */
++ dentry = ERR_PTR(-EEXIST);
++ AuDbg("%.*s\n", len, name);
++ BUG();
++
++ out_name:
++ if (name != defname)
++ kfree(name);
++ out:
++ AuTraceErrPtr(dentry);
++ return dentry;
++#undef HEX_LEN
++}
++
++/*
++ * rename the @dentry of @bindex to the whiteouted temporary name.
++ */
++int au_whtmp_ren(struct inode *dir, aufs_bindex_t bindex,
++ struct dentry *h_dentry)
++{
++ int err, dlgt;
++ struct inode *h_dir;
++ struct dentry *h_parent, *tmp_dentry;
++ struct super_block *sb;
++ unsigned int mnt_flags;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ struct au_ndx ndx = {
++ .flags = 0,
++ .nd = NULL,
++ /* .br = NULL */
++ };
++
++ LKTRTrace("%.*s\n", AuDLNPair(h_dentry));
++ AuDebugOn(!h_dentry->d_inode);
++ h_parent = h_dentry->d_parent; /* dir inode is locked */
++ h_dir = h_parent->d_inode;
++ IMustLock(h_dir);
++
++ sb = dir->i_sb;
++ mnt_flags = au_mntflags(sb);
++ dlgt = !!au_test_dlgt(mnt_flags);
++ if (dlgt)
++ au_fset_ndx(ndx.flags, DLGT);
++ ndx.nfsmnt = au_nfsmnt(sb, bindex);
++ tmp_dentry = au_whtmp_lkup(h_parent, &h_dentry->d_name, &ndx);
++ err = PTR_ERR(tmp_dentry);
++ if (IS_ERR(tmp_dentry))
++ goto out;
++
++ /* under the same dir, no need to lock_rename() */
++ vfsub_args_init(&vargs, &ign, dlgt, 0);
++ AuDebugOn(!S_ISDIR(h_dentry->d_inode->i_mode));
++ vfsub_ign_hinode(&vargs, IN_MOVED_FROM | IN_MOVED_TO,
++ au_hi(dir, bindex));
++ err = vfsub_rename(h_dir, h_dentry, h_dir, tmp_dentry, &vargs);
++ AuTraceErr(err);
++ dput(tmp_dentry);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static int do_unlink_wh(struct au_hinode *hdir, struct inode *h_dir,
++ struct dentry *wh_dentry, const int dlgt)
++{
++ int err;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++
++ AuDebugOn(hdir && h_dir);
++ AuDebugOn(!hdir && !h_dir);
++ if (!h_dir)
++ h_dir = hdir->hi_inode;
++ LKTRTrace("hi%lu, wh %.*s\n", h_dir->i_ino, AuDLNPair(wh_dentry));
++ AuDebugOn(!wh_dentry->d_inode || !S_ISREG(wh_dentry->d_inode->i_mode));
++
++ /*
++ * forces superio when the dir has a sticky bit.
++ * this may be a violation of unix fs semantics.
++ */
++ vfsub_args_init(&vargs, &ign, dlgt,
++ (h_dir->i_mode & S_ISVTX)
++ && wh_dentry->d_inode->i_uid != current->fsuid);
++ vfsub_ign_hinode(&vargs, IN_DELETE, hdir);
++ err = vfsub_unlink(h_dir, wh_dentry, &vargs);
++ AuTraceErr(err);
++ return err;
++}
++
++int au_wh_unlink_dentry(struct au_hinode *hdir, struct dentry *wh_dentry,
++ struct dentry *dentry, int dlgt)
++{
++ int err;
++
++ LKTRTrace("i%lu, wh %.*s, d %p\n",
++ hdir->hi_inode->i_ino, AuDLNPair(wh_dentry), dentry);
++ AuDebugOn((dentry && au_dbwh(dentry) < 0)
++ || !wh_dentry->d_inode
++ || !S_ISREG(wh_dentry->d_inode->i_mode));
++
++ err = do_unlink_wh(hdir, /*h_dir*/NULL, wh_dentry, dlgt);
++ if (!err && dentry)
++ au_set_dbwh(dentry, -1);
++
++ AuTraceErr(err);
++ return err;
++}
++
++static int unlink_wh_name(struct dentry *h_parent, struct qstr *wh,
++ struct au_ndx *ndx)
++{
++ int err;
++ struct dentry *wh_dentry;
++
++ LKTRTrace("%.*s/%.*s\n", AuDLNPair(h_parent), AuLNPair(wh));
++
++ /* au_test_h_perm() is already done */
++ wh_dentry = au_lkup_one(wh->name, h_parent, wh->len, ndx);
++ if (IS_ERR(wh_dentry))
++ err = PTR_ERR(wh_dentry);
++ else {
++ err = 0;
++ if (wh_dentry->d_inode && S_ISREG(wh_dentry->d_inode->i_mode))
++ err = do_unlink_wh(/*hdir*/NULL, h_parent->d_inode,
++ wh_dentry,
++ au_ftest_ndx(ndx->flags, DLGT));
++ dput(wh_dentry);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static void clean_wh(struct inode *h_dir, struct path *whpath,
++ struct au_hinode *hdir, struct vfsub_args *vargs)
++{
++ int err;
++
++ AuTraceEnter();
++
++ if (!whpath->dentry->d_inode)
++ return;
++
++ err = au_mnt_want_write(whpath->mnt);
++ if (!err) {
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_DELETE, hdir);
++ err = vfsub_unlink(h_dir, whpath->dentry, vargs);
++ au_mnt_drop_write(whpath->mnt);
++ }
++ if (unlikely(err))
++ AuWarn("failed unlink %.*s (%d), ignored.\n",
++ AuDLNPair(whpath->dentry), err);
++}
++
++static void au_whdir_clean(struct inode *h_dir, struct path *whpath,
++ struct au_hinode *hdir, struct vfsub_args *vargs)
++{
++ int err;
++
++ AuTraceEnter();
++
++ if (!whpath->dentry->d_inode)
++ return;
++
++ err = au_mnt_want_write(whpath->mnt);
++ if (!err) {
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_DELETE, hdir);
++ err = vfsub_rmdir(h_dir, whpath->dentry, vargs);
++ au_mnt_drop_write(whpath->mnt);
++ }
++ if (unlikely(err))
++ AuWarn("failed rmdir %.*s (%d), ignored.\n",
++ AuDLNPair(whpath->dentry), err);
++}
++
++static int test_linkable(struct inode *h_dir)
++{
++ if (h_dir->i_op && h_dir->i_op->link)
++ return 0;
++ return -ENOSYS;
++}
++
++/* todo: should this mkdir be done in /sbin/mount.aufs script? */
++static int au_whdir(struct inode *h_dir, struct path *path,
++ struct au_hinode *hdir, struct vfsub_args *vargs)
++{
++ int err;
++
++ err = -EEXIST;
++ if (!path->dentry->d_inode) {
++ int mode = S_IRWXU;
++ if (au_test_nfs(path->dentry->d_sb))
++ mode |= S_IXUGO;
++ err = au_mnt_want_write(path->mnt);
++ if (!err) {
++ vfsub_args_reinit(vargs);
++ vfsub_ign_hinode(vargs, IN_CREATE, hdir);
++ err = vfsub_mkdir(h_dir, path->dentry, mode, vargs);
++ au_mnt_drop_write(path->mnt);
++ }
++ } else if (S_ISDIR(path->dentry->d_inode->i_mode))
++ err = 0;
++ else
++ AuErr("unknown %.*s exists\n", AuDLNPair(path->dentry));
++
++ return err;
++}
++
++/*
++ * initialize the whiteout base file/dir for @br.
++ */
++int au_wh_init(struct dentry *h_root, struct au_branch *br,
++ struct vfsmount *h_mnt, struct super_block *sb,
++ aufs_bindex_t bindex)
++{
++ int err, i;
++ const unsigned int mnt_flags = au_mntflags(sb);
++ const unsigned char do_plink = !!au_opt_test(mnt_flags, PLINK),
++ do_hinotify = au_opt_test(mnt_flags, UDBA_INOTIFY);
++ struct path path = {
++ .mnt = h_mnt
++ };
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ struct inode *h_dir;
++ struct au_hinode *hdir;
++ struct au_wbr *wbr = br->br_wbr;
++ struct vfsmount *nfsmnt = au_do_nfsmnt(h_mnt);
++ static const struct qstr base_name[] = {
++ [AuBrWh_BASE] = {
++ .name = AUFS_BASE_NAME,
++ .len = sizeof(AUFS_BASE_NAME) - 1
++ },
++ [AuBrWh_PLINK] = {
++ .name = AUFS_PLINKDIR_NAME,
++ .len = sizeof(AUFS_PLINKDIR_NAME) - 1
++ },
++ [AuBrWh_TMP] = {
++ .name = AUFS_TMPDIR_NAME,
++ .len = sizeof(AUFS_TMPDIR_NAME) - 1
++ }
++ };
++ struct {
++ const struct qstr *name;
++ struct dentry *dentry;
++ } base[] = {
++ [AuBrWh_BASE] = {
++ .name = base_name + AuBrWh_BASE,
++ .dentry = NULL
++ },
++ [AuBrWh_PLINK] = {
++ .name = base_name + AuBrWh_PLINK,
++ .dentry = NULL
++ },
++ [AuBrWh_TMP] = {
++ .name = base_name + AuBrWh_TMP,
++ .dentry = NULL
++ }
++ };
++ struct au_ndx ndx = {
++ .nfsmnt = nfsmnt,
++ .flags = 0, /* always no dlgt */
++ .nd = NULL,
++ /* .br = NULL */
++ };
++
++ LKTRTrace("nfsmnt %p\n", nfsmnt);
++ WbrWhMustWriteLock(wbr);
++ SiMustWriteLock(sb);
++ h_dir = h_root->d_inode;
++
++ for (i = 0; i < AuBrWh_Last; i++) {
++ /* doubly whiteouted */
++ struct dentry *d;
++ d = au_wh_lkup(h_root, (void *)base[i].name, &ndx);
++ err = PTR_ERR(d);
++ if (IS_ERR(d))
++ goto out;
++ base[i].dentry = d;
++ if (!au_test_ecryptfs(d->d_sb))
++ AuDebugOn(wbr
++ && wbr->wbr_wh[i]
++ && wbr->wbr_wh[i] != base[i].dentry);
++ else
++ /* ecryptfs problem?: it returns different dentry */
++ AuDebugOn(wbr
++ && wbr->wbr_wh[i]
++ && !!wbr->wbr_wh[i] != !!base[i].dentry);
++ }
++
++ if (wbr)
++ for (i = 0; i < AuBrWh_Last; i++) {
++ dput(wbr->wbr_wh[i]);
++ wbr->wbr_wh[i] = NULL;
++ }
++
++ err = 0;
++ hdir = NULL;
++ if (bindex >= 0 && do_hinotify)
++ hdir = au_hi(sb->s_root->d_inode, bindex);
++ vfsub_args_init(&vargs, &ign, au_test_dlgt(mnt_flags), 0);
++
++ switch (br->br_perm) {
++ case AuBrPerm_RR:
++ case AuBrPerm_RO:
++ case AuBrPerm_RRWH:
++ case AuBrPerm_ROWH:
++ path.dentry = base[AuBrWh_BASE].dentry;
++ clean_wh(h_dir, &path, hdir, &vargs);
++ path.dentry = base[AuBrWh_PLINK].dentry;
++ au_whdir_clean(h_dir, &path, hdir, &vargs);
++ path.dentry = base[AuBrWh_TMP].dentry;
++ au_whdir_clean(h_dir, &path, hdir, &vargs);
++ break;
++
++ case AuBrPerm_RWNoLinkWH:
++ path.dentry = base[AuBrWh_BASE].dentry;
++ clean_wh(h_dir, &path, hdir, &vargs);
++ path.dentry = base[AuBrWh_PLINK].dentry;
++ if (do_plink) {
++ err = test_linkable(h_dir);
++ if (unlikely(err))
++ goto out_nolink;
++
++ err = au_whdir(h_dir, &path, hdir, &vargs);
++ if (unlikely(err))
++ goto out_err;
++ wbr->wbr_plink = dget(base[AuBrWh_PLINK].dentry);
++ } else
++ au_whdir_clean(h_dir, &path, hdir, &vargs);
++ path.dentry = base[AuBrWh_TMP].dentry;
++ err = au_whdir(h_dir, &path, hdir, &vargs);
++ if (unlikely(err))
++ goto out_err;
++ wbr->wbr_tmp = dget(base[AuBrWh_TMP].dentry);
++ break;
++
++ case AuBrPerm_RW:
++ /*
++ * for the moment, aufs supports the branch filesystem
++ * which does not support link(2).
++ * testing on FAT which does not support i_op->setattr() fully
++ * either, copyup failed.
++ * finally, such filesystem will not be used as the writable
++ * branch.
++ */
++ err = test_linkable(h_dir);
++ if (unlikely(err))
++ goto out_nolink;
++
++ err = -EEXIST;
++ /*
++ * todo: should this create be done
++ * in /sbin/mount.aufs script?
++ */
++ if (!base[AuBrWh_BASE].dentry->d_inode) {
++ err = au_mnt_want_write(h_mnt);
++ if (!err) {
++ vfsub_args_reinit(&vargs);
++ vfsub_ign_hinode(&vargs, IN_CREATE, hdir);
++ err = au_h_create
++ (h_dir, base[AuBrWh_BASE].dentry,
++ WH_MASK, &vargs, /*nd*/NULL, nfsmnt);
++ au_mnt_drop_write(h_mnt);
++ }
++ } else if (S_ISREG(base[AuBrWh_BASE].dentry->d_inode->i_mode))
++ err = 0;
++ else
++ AuErr("unknown %.*s/%.*s exists\n",
++ AuDLNPair(h_root),
++ AuDLNPair(base[AuBrWh_BASE].dentry));
++ if (unlikely(err))
++ goto out_err;
++
++ path.dentry = base[AuBrWh_PLINK].dentry;
++ if (do_plink) {
++ err = au_whdir(h_dir, &path, hdir, &vargs);
++ if (unlikely(err))
++ goto out_err;
++ wbr->wbr_plink = dget(base[AuBrWh_PLINK].dentry);
++ } else
++ au_whdir_clean(h_dir, &path, hdir, &vargs);
++ wbr->wbr_whbase = dget(base[AuBrWh_BASE].dentry);
++
++ path.dentry = base[AuBrWh_TMP].dentry;
++ err = au_whdir(h_dir, &path, hdir, &vargs);
++ if (unlikely(err))
++ goto out_err;
++ wbr->wbr_tmp = dget(base[AuBrWh_TMP].dentry);
++ break;
++
++ default:
++ BUG();
++ }
++
++ out:
++ for (i = 0; i < AuBrWh_Last; i++)
++ dput(base[i].dentry);
++ AuTraceErr(err);
++ return err;
++ out_nolink:
++ AuErr("%.*s doesn't support link(2), use noplink and rw+nolwh\n",
++ AuDLNPair(h_root));
++ goto out;
++ out_err:
++ AuErr("an error(%d) on the writable branch %.*s(%s)\n",
++ err, AuDLNPair(h_root), au_sbtype(h_root->d_sb));
++ goto out;
++}
++
++struct reinit_br_wh {
++ struct super_block *sb;
++ struct au_branch *br;
++};
++
++static void reinit_br_wh(void *arg)
++{
++ int err;
++ struct reinit_br_wh *a = arg;
++ struct au_wbr *wbr;
++ struct inode *h_dir, *dir;
++ struct dentry *h_root;
++ aufs_bindex_t bindex;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++
++ AuTraceEnter();
++ AuDebugOn(current->fsuid);
++
++ err = 0;
++ wbr = a->br->br_wbr;
++ /* big aufs lock */
++ si_noflush_write_lock(a->sb);
++ if (!au_br_writable(a->br->br_perm))
++ goto out;
++ bindex = au_br_index(a->sb, a->br->br_id);
++ if (unlikely(bindex < 0))
++ goto out;
++
++ AuDebugOn(!wbr);
++ AuDebugOn(!wbr->wbr_whbase || !wbr->wbr_whbase->d_inode);
++
++ dir = a->sb->s_root->d_inode;
++ ii_read_lock_parent(dir);
++ h_root = dget_parent(wbr->wbr_whbase);
++ h_dir = h_root->d_inode;
++ AuDebugOn(!h_dir->i_op || !h_dir->i_op->link);
++ vfsub_i_lock_nested(h_dir, AuLsc_I_PARENT);
++ wbr_wh_write_lock(wbr);
++ if (!au_verify_parent(wbr->wbr_whbase, h_dir)) {
++ err = au_br_want_write(a->br);
++ if (!err) {
++ vfsub_args_init(&vargs, &ign, /*dlgt*/0, 0);
++ vfsub_ign_hinode(&vargs, IN_DELETE, au_hi(dir, bindex));
++ err = vfsub_unlink(h_dir, wbr->wbr_whbase, &vargs);
++ au_br_drop_write(a->br);
++ }
++ } else {
++ AuWarn("%.*s is moved, ignored\n", AuDLNPair(wbr->wbr_whbase));
++ err = 0;
++ }
++ dput(wbr->wbr_whbase);
++ wbr->wbr_whbase = NULL;
++ if (!err)
++ err = au_wh_init(h_root, a->br, a->br->br_mnt, a->sb, bindex);
++ wbr_wh_write_unlock(wbr);
++ vfsub_i_unlock(h_dir);
++ dput(h_root);
++ ii_read_unlock(dir);
++
++ out:
++ if (wbr)
++ atomic_dec_return(&wbr->wbr_wh_running);
++ au_br_put(a->br);
++ au_nwt_done(&au_sbi(a->sb)->si_nowait);
++ si_write_unlock(a->sb);
++ kfree(arg);
++ if (unlikely(err))
++ AuIOErr("err %d\n", err);
++}
++
++static void kick_reinit_br_wh(struct super_block *sb, struct au_branch *br)
++{
++ int do_dec, wkq_err;
++ struct reinit_br_wh *arg;
++
++ AuTraceEnter();
++ AuDebugOn(!br->br_wbr);
++
++ do_dec = 1;
++ if (atomic_inc_return(&br->br_wbr->wbr_wh_running) != 1)
++ goto out;
++
++ /* ignore ENOMEM */
++ arg = kmalloc(sizeof(*arg), GFP_NOFS);
++ if (arg) {
++ /*
++ * dec(wh_running), kfree(arg) and au_br_put()
++ * in reinit function
++ */
++ arg->sb = sb;
++ arg->br = br;
++ au_br_get(br);
++ wkq_err = au_wkq_nowait(reinit_br_wh, arg, sb, /*dlgt*/0);
++ if (unlikely(wkq_err)) {
++ atomic_dec_return(&br->br_wbr->wbr_wh_running);
++ au_br_put(br);
++ kfree(arg);
++ }
++ do_dec = 0;
++ }
++
++ out:
++ if (do_dec)
++ atomic_dec_return(&br->br_wbr->wbr_wh_running);
++}
++
++/*
++ * create the whiteout @wh.
++ */
++static int link_or_create_wh(struct super_block *sb, aufs_bindex_t bindex,
++ struct dentry *wh, struct inode *dir)
++{
++ int err, dlgt;
++ struct au_branch *br;
++ struct au_wbr *wbr;
++ struct dentry *h_parent;
++ struct inode *h_dir;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++
++ LKTRTrace("%.*s\n", AuDLNPair(wh));
++ h_parent = wh->d_parent; /* dir inode is locked */
++ h_dir = h_parent->d_inode;
++ IMustLock(h_dir);
++ br = au_sbr(sb, bindex);
++ wbr = br->br_wbr;
++ AuDebugOn(!wbr);
++
++ dlgt = !!au_test_dlgt(au_mntflags(sb));
++ wbr_wh_read_lock(wbr);
++ if (wbr->wbr_whbase) {
++ vfsub_args_init(&vargs, &ign, dlgt, 0);
++ if (dir)
++ vfsub_ign_hinode(&vargs, IN_CREATE, au_hi(dir, bindex));
++ err = vfsub_link(wbr->wbr_whbase, h_dir, wh, &vargs);
++ if (!err || err != -EMLINK)
++ goto out;
++
++ /* link count full. re-initialize br_whbase. */
++ kick_reinit_br_wh(sb, br);
++ }
++
++ /* return this error in this context */
++ vfsub_args_init(&vargs, &ign, dlgt, 0);
++ if (dir)
++ vfsub_ign_hinode(&vargs, IN_CREATE, au_hi(dir, bindex));
++ err = au_h_create(h_dir, wh, WH_MASK, &vargs, /*nd*/NULL,
++ au_do_nfsmnt(br->br_mnt));
++
++ out:
++ wbr_wh_read_unlock(wbr);
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * create or remove the diropq.
++ */
++static struct dentry *do_diropq(struct dentry *dentry, aufs_bindex_t bindex,
++ unsigned int flags)
++{
++ struct dentry *opq_dentry, *h_dentry;
++ struct inode *h_dir;
++ int err, dlgt;
++ struct super_block *sb;
++ struct au_ndx ndx = {
++ .flags = 0,
++ .nd = NULL,
++ /* .br = NULL */
++ };
++
++ LKTRTrace("%.*s, bindex %d, flags 0x%x\n",
++ AuDLNPair(dentry), bindex, flags);
++ h_dentry = au_h_dptr(dentry, bindex);
++ AuDebugOn(!h_dentry);
++ h_dir = h_dentry->d_inode;
++ AuDebugOn(!h_dir || !S_ISDIR(h_dir->i_mode));
++
++ /* already checked by au_test_h_perm(). */
++ sb = dentry->d_sb;
++ ndx.nfsmnt = au_nfsmnt(sb, bindex);
++ dlgt = 0;
++ if (au_ftest_diropq(flags, DLGT)) {
++ dlgt = 1;
++ au_fset_ndx(ndx.flags, DLGT);
++ }
++ opq_dentry = au_lkup_one(diropq_name.name, h_dentry, diropq_name.len,
++ &ndx);
++ if (IS_ERR(opq_dentry))
++ goto out;
++
++ if (au_ftest_diropq(flags, CREATE)) {
++ AuDebugOn(opq_dentry->d_inode);
++ err = link_or_create_wh(dentry->d_sb, bindex, opq_dentry,
++ dentry->d_inode);
++ if (!err) {
++ au_set_dbdiropq(dentry, bindex);
++ goto out; /* success */
++ }
++ } else {
++ AuDebugOn(/* !S_ISDIR(dentry->d_inode->i_mode)
++ * || */!opq_dentry->d_inode);
++ err = do_unlink_wh(au_hi(dentry->d_inode, bindex),
++ /*h_dir*/NULL, opq_dentry, dlgt);
++ if (!err)
++ au_set_dbdiropq(dentry, -1);
++ }
++ dput(opq_dentry);
++ opq_dentry = ERR_PTR(err);
++
++ out:
++ AuTraceErrPtr(opq_dentry);
++ return opq_dentry;
++}
++
++struct do_diropq_args {
++ struct dentry **errp;
++ struct dentry *dentry;
++ aufs_bindex_t bindex;
++ unsigned int flags;
++};
++
++static void call_do_diropq(void *args)
++{
++ struct do_diropq_args *a = args;
++ *a->errp = do_diropq(a->dentry, a->bindex, a->flags);
++}
++
++struct dentry *au_diropq_sio(struct dentry *dentry, aufs_bindex_t bindex,
++ unsigned int flags)
++{
++ struct dentry *diropq, *h_dentry;
++
++ LKTRTrace("%.*s, bindex %d, flags 0x%x\n",
++ AuDLNPair(dentry), bindex, flags);
++
++ h_dentry = au_h_dptr(dentry, bindex);
++ if (!au_test_h_perm_sio(h_dentry->d_inode, MAY_EXEC | MAY_WRITE,
++ au_ftest_diropq(flags, DLGT)))
++ diropq = do_diropq(dentry, bindex, flags);
++ else {
++ int wkq_err;
++ struct do_diropq_args args = {
++ .errp = &diropq,
++ .dentry = dentry,
++ .bindex = bindex,
++ .flags = flags
++ };
++ wkq_err = au_wkq_wait(call_do_diropq, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ diropq = ERR_PTR(wkq_err);
++ }
++
++ AuTraceErrPtr(diropq);
++ return diropq;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * lookup whiteout dentry.
++ * @h_parent: hidden parent dentry which must exist and be locked
++ * @base_name: name of dentry which will be whiteouted
++ * returns dentry for whiteout.
++ */
++struct dentry *au_wh_lkup(struct dentry *h_parent, struct qstr *base_name,
++ struct au_ndx *ndx)
++{
++ int err;
++ struct qstr wh_name;
++ struct dentry *wh_dentry;
++
++ LKTRTrace("%.*s/%.*s\n", AuDLNPair(h_parent), AuLNPair(base_name));
++
++ err = au_wh_name_alloc(base_name->name, base_name->len, &wh_name);
++ wh_dentry = ERR_PTR(err);
++ if (!err) {
++ /* do not superio. */
++ wh_dentry = au_lkup_one(wh_name.name, h_parent,
++ wh_name.len, ndx);
++ au_wh_name_free(&wh_name);
++ }
++ AuTraceErrPtr(wh_dentry);
++ return wh_dentry;
++}
++
++/*
++ * link/create a whiteout for @dentry on @bindex.
++ */
++struct dentry *au_wh_create(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_parent, struct au_ndx *ndx)
++{
++ struct dentry *wh_dentry;
++ struct inode *dir;
++ int err;
++ struct super_block *sb;
++
++ LKTRTrace("%.*s/%.*s on b%d\n", AuDLNPair(h_parent),
++ AuDLNPair(dentry), bindex);
++
++ sb = dentry->d_sb;
++ wh_dentry = au_wh_lkup(h_parent, &dentry->d_name, ndx);
++ if (!IS_ERR(wh_dentry) && !wh_dentry->d_inode) {
++ dir = dentry->d_parent->d_inode; /* dir is locked */
++ IMustLock(dir);
++ err = link_or_create_wh(sb, bindex, wh_dentry, dir);
++ if (!err)
++ au_set_dbwh(dentry, bindex);
++ else {
++ dput(wh_dentry);
++ wh_dentry = ERR_PTR(err);
++ }
++ }
++
++ AuTraceErrPtr(wh_dentry);
++ return wh_dentry;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/* Delete all whiteouts in this directory on branch bindex. */
++static int del_wh_children(struct dentry *h_dentry, struct au_nhash *whlist,
++ aufs_bindex_t bindex, struct au_ndx *ndx)
++{
++ int err, i;
++ struct qstr wh_name;
++ char *p;
++ struct inode *h_inode;
++ struct hlist_head *head;
++ struct au_vdir_wh *tpos;
++ struct hlist_node *pos;
++ struct au_vdir_destr *str;
++
++ LKTRTrace("%.*s\n", AuDLNPair(h_dentry));
++ h_inode = h_dentry->d_inode;
++ AuDebugOn(IS_RDONLY(h_inode));
++
++ err = -ENOMEM;
++ p = __getname();
++ wh_name.name = p;
++ if (unlikely(!wh_name.name))
++ goto out;
++ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN);
++ p += AUFS_WH_PFX_LEN;
++
++ /* already checked by au_test_h_perm(). */
++ err = 0;
++ for (i = 0; !err && i < AuSize_NHASH; i++) {
++ head = whlist->heads + i;
++ hlist_for_each_entry(tpos, pos, head, wh_hash) {
++ if (tpos->wh_bindex != bindex)
++ continue;
++ str = &tpos->wh_str;
++ if (str->len + AUFS_WH_PFX_LEN <= PATH_MAX) {
++ memcpy(p, str->name, str->len);
++ wh_name.len = AUFS_WH_PFX_LEN + str->len;
++ err = unlink_wh_name(h_dentry, &wh_name, ndx);
++ if (!err)
++ continue;
++ break;
++ }
++ AuIOErr("whiteout name too long %.*s\n",
++ str->len, str->name);
++ err = -EIO;
++ break;
++ }
++ }
++ __putname(wh_name.name);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++struct del_wh_children_args {
++ int *errp;
++ struct dentry *h_dentry;
++ struct au_nhash *whlist;
++ aufs_bindex_t bindex;
++ struct au_ndx *ndx;
++};
++
++static void call_del_wh_children(void *args)
++{
++ struct del_wh_children_args *a = args;
++ *a->errp = del_wh_children(a->h_dentry, a->whlist, a->bindex, a->ndx);
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * rmdir the whiteouted temporary named dir @h_dentry.
++ * @whlist: whiteouted children.
++ */
++int au_whtmp_rmdir(struct inode *dir, aufs_bindex_t bindex,
++ struct dentry *wh_dentry, struct au_nhash *whlist)
++{
++ int err, dlgt;
++ struct inode *wh_inode, *h_dir;
++ struct super_block *sb;
++ unsigned int mnt_flags;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ struct au_ndx ndx = {
++ .flags = 0,
++ .nd = NULL,
++ /* .br = NULL */
++ };
++
++ LKTRTrace("i%lu, %.*s, b%d\n",
++ dir->i_ino, AuDLNPair(wh_dentry), bindex);
++ /* IMustLock(dir); */
++ IiMustAnyLock(dir);
++ h_dir = wh_dentry->d_parent->d_inode; /* dir inode is locked */
++ IMustLock(h_dir);
++
++ sb = dir->i_sb;
++ mnt_flags = au_mntflags(sb);
++ dlgt = !!au_test_dlgt(mnt_flags);
++ if (dlgt)
++ au_fset_ndx(ndx.flags, DLGT);
++ ndx.nfsmnt = au_nfsmnt(sb, bindex);
++ wh_inode = wh_dentry->d_inode;
++ vfsub_i_lock_nested(wh_inode, AuLsc_I_CHILD);
++
++ /*
++ * someone else might change some whiteouts while we were sleeping.
++ * it means this whlist may have an obsoleted entry.
++ */
++ if (!au_test_h_perm_sio(wh_inode, MAY_EXEC | MAY_WRITE, dlgt))
++ err = del_wh_children(wh_dentry, whlist, bindex, &ndx);
++ else {
++ int wkq_err;
++ /* ugly */
++ unsigned int flags = ndx.flags;
++ struct del_wh_children_args args = {
++ .errp = &err,
++ .h_dentry = wh_dentry,
++ .whlist = whlist,
++ .bindex = bindex,
++ .ndx = &ndx
++ };
++
++ ndx.flags = 0;
++ wkq_err = au_wkq_wait(call_del_wh_children, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ ndx.flags = flags;
++ }
++ vfsub_i_unlock(wh_inode);
++
++ if (!err) {
++ vfsub_args_init(&vargs, &ign, dlgt, 0);
++ vfsub_ign_hinode(&vargs, IN_DELETE, au_hi(dir, bindex));
++ err = vfsub_rmdir(h_dir, wh_dentry, &vargs);
++ /* d_drop(h_dentry); */
++ }
++
++ if (!err) {
++ if (au_ibstart(dir) == bindex) {
++ au_cpup_attr_timesizes(dir);
++ /* au_cpup_attr_nlink(dir); */
++ dir->i_nlink--;
++ }
++ return 0; /* success */
++ }
++
++ AuWarn("failed removing %.*s(%d), ignored\n",
++ AuDLNPair(wh_dentry), err);
++ return err;
++}
++
++static void au_whtmp_rmdir_free_args(struct au_whtmp_rmdir_args *args)
++{
++ au_nhash_fin(&args->whlist);
++ dput(args->wh_dentry);
++ iput(args->dir);
++ kfree(args);
++}
++
++static void call_rmdir_whtmp(void *args)
++{
++ int err;
++ struct au_whtmp_rmdir_args *a = args;
++ struct super_block *sb;
++ struct dentry *h_parent;
++ struct inode *h_dir;
++
++ LKTRTrace("%.*s, b%d, dir i%lu\n",
++ AuDLNPair(a->wh_dentry), a->bindex, a->dir->i_ino);
++
++ /* rmdir by nfsd may cause deadlock with this i_mutex */
++ /* vfsub_i_lock(a->dir); */
++ sb = a->dir->i_sb;
++ si_noflush_read_lock(sb);
++ err = au_test_ro(sb, a->bindex, NULL);
++ if (unlikely(err))
++ goto out;
++
++ err = -EIO;
++ ii_write_lock_parent(a->dir);
++ h_parent = dget_parent(a->wh_dentry);
++ h_dir = h_parent->d_inode;
++ vfsub_i_lock_nested(h_dir, AuLsc_I_PARENT);
++ if (!au_verify_parent(a->wh_dentry, h_dir)) {
++ err = au_br_want_write(au_sbr(sb, a->bindex));
++ if (!err) {
++ err = au_whtmp_rmdir(a->dir, a->bindex, a->wh_dentry,
++ &a->whlist);
++ au_br_drop_write(au_sbr(sb, a->bindex));
++ }
++ }
++ vfsub_i_unlock(h_dir);
++ dput(h_parent);
++ ii_write_unlock(a->dir);
++
++ out:
++ /* vfsub_i_unlock(a->dir); */
++ au_nwt_done(&au_sbi(sb)->si_nowait);
++ si_read_unlock(sb);
++ au_whtmp_rmdir_free_args(a);
++ if (unlikely(err))
++ AuIOErr("err %d\n", err);
++}
++
++void au_whtmp_kick_rmdir(struct inode *dir, aufs_bindex_t bindex,
++ struct dentry *wh_dentry, struct au_nhash *whlist,
++ struct au_whtmp_rmdir_args *args)
++{
++ int wkq_err;
++
++ LKTRTrace("%.*s\n", AuDLNPair(wh_dentry));
++ IMustLock(dir);
++
++ /* all post-process will be done in do_rmdir_whtmp(). */
++ args->dir = au_igrab(dir);
++ args->bindex = bindex;
++ args->wh_dentry = dget(wh_dentry);
++ au_nhash_init(&args->whlist);
++ au_nhash_move(&args->whlist, whlist);
++ wkq_err = au_wkq_nowait(call_rmdir_whtmp, args, dir->i_sb, /*dlgt*/0);
++ if (unlikely(wkq_err)) {
++ AuWarn("rmdir error %.*s (%d), ignored\n",
++ AuDLNPair(wh_dentry), wkq_err);
++ au_whtmp_rmdir_free_args(args);
++ }
++}
+diff --git a/fs/aufs/whout.h b/fs/aufs/whout.h
+new file mode 100644
+index 0000000..056ca13
+--- /dev/null
++++ b/fs/aufs/whout.h
+@@ -0,0 +1,134 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * whiteout for logical deletion and opaque directory
++ *
++ * $Id: whout.h,v 1.20 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_WHOUT_H__
++#define __AUFS_WHOUT_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/aufs_type.h>
++
++int au_wh_name_alloc(const char *name, int len, struct qstr *wh);
++void au_wh_name_free(struct qstr *wh);
++
++struct au_ndx;
++int au_wh_test(struct dentry *h_parent, struct qstr *wh_name, int try_sio,
++ struct au_ndx *ndx);
++int au_diropq_test(struct dentry *h_dentry, struct au_ndx *ndx);
++
++struct dentry *au_whtmp_lkup(struct dentry *h_parent, struct qstr *prefix,
++ struct au_ndx *ndx);
++int au_whtmp_ren(struct inode *dir, aufs_bindex_t bindex,
++ struct dentry *h_dentry);
++int au_wh_unlink_dentry(struct au_hinode *dir, struct dentry *wh_dentry,
++ struct dentry *dentry, int dlgt);
++
++struct au_branch;
++int au_wh_init(struct dentry *h_parent, struct au_branch *br,
++ struct vfsmount *nfsmnt, struct super_block *sb,
++ aufs_bindex_t bindex);
++
++/* diropq flags */
++#define AuDiropq_CREATE 1
++#define AuDiropq_DLGT (1 << 1)
++#define au_ftest_diropq(flags, name) ((flags) & AuDiropq_##name)
++#define au_fset_diropq(flags, name) { (flags) |= AuDiropq_##name; }
++#define au_fclr_diropq(flags, name) { (flags) &= ~AuDiropq_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef AuDiropq_DLGT
++#define AuDiropq_DLGT 0
++#endif
++
++struct dentry *au_diropq_sio(struct dentry *dentry, aufs_bindex_t bindex,
++ unsigned int flags);
++
++struct dentry *au_wh_lkup(struct dentry *h_parent, struct qstr *base_name,
++ struct au_ndx *ndx);
++struct dentry *au_wh_create(struct dentry *dentry, aufs_bindex_t bindex,
++ struct dentry *h_parent, struct au_ndx *ndx);
++
++/* real rmdir the whiteout-ed dir */
++struct au_whtmp_rmdir_args {
++ struct inode *dir;
++ aufs_bindex_t bindex;
++ struct dentry *wh_dentry;
++ struct au_nhash whlist;
++};
++
++struct au_nhash;
++int au_whtmp_rmdir(struct inode *dir, aufs_bindex_t bindex,
++ struct dentry *wh_dentry, struct au_nhash *whlist);
++void au_whtmp_kick_rmdir(struct inode *dir, aufs_bindex_t bindex,
++ struct dentry *wh_dentry, struct au_nhash *whlist,
++ struct au_whtmp_rmdir_args *args);
++
++/* ---------------------------------------------------------------------- */
++
++static inline
++struct dentry *au_diropq_create(struct dentry *dentry, aufs_bindex_t bindex,
++ int dlgt)
++{
++ unsigned int flags = AuDiropq_CREATE;
++ if (dlgt)
++ au_fset_diropq(flags, DLGT);
++ return au_diropq_sio(dentry, bindex, flags);
++}
++
++static inline
++int au_diropq_remove(struct dentry *dentry, aufs_bindex_t bindex, int dlgt)
++{
++ unsigned int flags = !AuDiropq_CREATE;
++ if (dlgt)
++ au_fset_diropq(flags, DLGT);
++ return PTR_ERR(au_diropq_sio(dentry, bindex, flags));
++}
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_ROBR
++/* robr.c */
++int au_test_robr_wh(struct qstr *name, struct dentry *h_parent,
++ struct qstr *wh_name, int try_sio, struct au_ndx *ndx);
++int au_test_robr_shwh(struct super_block *sb, const struct qstr *name);
++#else
++static inline
++int au_test_robr_wh(struct qstr *name, struct dentry *h_parent,
++ struct qstr *wh_name, int try_sio, struct au_ndx *ndx)
++{
++ return au_wh_test(h_parent, wh_name, try_sio, ndx);
++}
++
++static inline
++int au_test_robr_shwh(struct super_block *sb, const struct qstr *name)
++{
++ if (unlikely(!au_opt_test(au_mntflags(sb), SHWH)
++ && !strncmp(name->name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)))
++ return -EPERM;
++ return 0;
++}
++#endif /* CONFIG_AUFS_ROBR */
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_WHOUT_H__ */
+diff --git a/fs/aufs/wkq.c b/fs/aufs/wkq.c
+new file mode 100644
+index 0000000..e770747
+--- /dev/null
++++ b/fs/aufs/wkq.c
+@@ -0,0 +1,385 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * workqueue for asynchronous/super-io/delegated operations
++ *
++ * $Id: wkq.c,v 1.40 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#include <linux/module.h>
++#include "aufs.h"
++
++struct au_wkq *au_wkq;
++
++struct au_cred {
++#ifdef CONFIG_AUFS_DLGT
++ int umask;
++ uid_t fsuid;
++ gid_t fsgid;
++ kernel_cap_t cap_effective, cap_inheritable, cap_permitted;
++#if 0 /* reserved for future use */
++ unsigned keep_capabilities:1;
++ struct user_struct *user;
++ struct fs_struct *fs;
++ struct nsproxy *nsproxy;
++#endif
++#endif
++};
++
++struct au_wkinfo {
++ struct work_struct wk;
++ struct super_block *sb;
++
++ unsigned int flags;
++ struct au_cred cred;
++
++ au_wkq_func_t func;
++ void *args;
++
++ atomic_t *busyp;
++ struct completion *comp;
++};
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_DLGT
++static void cred_store(struct au_cred *cred)
++{
++ cred->umask = current->fs->umask;
++ cred->fsuid = current->fsuid;
++ cred->fsgid = current->fsgid;
++ cred->cap_effective = current->cap_effective;
++ cred->cap_inheritable = current->cap_inheritable;
++ cred->cap_permitted = current->cap_permitted;
++}
++
++static void cred_revert(struct au_cred *cred)
++{
++ AuDebugOn(!au_test_wkq(current));
++ current->fs->umask = cred->umask;
++ current->fsuid = cred->fsuid;
++ current->fsgid = cred->fsgid;
++ current->cap_effective = cred->cap_effective;
++ current->cap_inheritable = cred->cap_inheritable;
++ current->cap_permitted = cred->cap_permitted;
++}
++
++static void cred_switch(struct au_cred *old, struct au_cred *new)
++{
++ cred_store(old);
++ cred_revert(new);
++}
++
++static void dlgt_cred_store(unsigned int flags, struct au_wkinfo *wkinfo)
++{
++ if (au_ftest_wkq(flags, DLGT))
++ cred_store(&wkinfo->cred);
++}
++
++static void dlgt_func(struct au_wkinfo *wkinfo)
++{
++ if (!au_ftest_wkq(wkinfo->flags, DLGT))
++ wkinfo->func(wkinfo->args);
++ else {
++ struct au_cred cred;
++ cred_switch(&cred, &wkinfo->cred);
++ wkinfo->func(wkinfo->args);
++ cred_revert(&cred);
++ }
++}
++#else
++static void dlgt_cred_store(unsigned int flags, struct au_wkinfo *wkinfo)
++{
++ /* empty */
++}
++
++static void dlgt_func(struct au_wkinfo *wkinfo)
++{
++ wkinfo->func(wkinfo->args);
++}
++#endif /* CONFIG_AUFS_DLGT */
++
++/* ---------------------------------------------------------------------- */
++
++static void update_busy(struct au_wkq *wkq, struct au_wkinfo *wkinfo)
++{
++#ifdef CONFIG_AUFS_SYSAUFS
++ unsigned int new, old;
++
++ do {
++ new = atomic_read(wkinfo->busyp);
++ old = atomic_read(&wkq->max_busy);
++ if (new <= old)
++ break;
++ } while (atomic_cmpxchg(&wkq->max_busy, old, new) == old);
++#endif
++}
++
++static int enqueue(struct au_wkq *wkq, struct au_wkinfo *wkinfo)
++{
++ AuTraceEnter();
++
++ wkinfo->busyp = &wkq->busy;
++ update_busy(wkq, wkinfo);
++ if (au_ftest_wkq(wkinfo->flags, WAIT))
++ return !queue_work(wkq->q, &wkinfo->wk);
++ else
++ return !schedule_work(&wkinfo->wk);
++}
++
++static void do_wkq(struct au_wkinfo *wkinfo)
++{
++ unsigned int idle, n;
++ int i, idle_idx;
++
++ AuTraceEnter();
++
++ while (1) {
++ if (au_ftest_wkq(wkinfo->flags, WAIT)) {
++ idle_idx = 0;
++ idle = UINT_MAX;
++ for (i = 0; i < aufs_nwkq; i++) {
++ n = atomic_inc_return(&au_wkq[i].busy);
++ if (n == 1 && !enqueue(au_wkq + i, wkinfo))
++ return; /* success */
++
++ if (n < idle) {
++ idle_idx = i;
++ idle = n;
++ }
++ atomic_dec_return(&au_wkq[i].busy);
++ }
++ } else
++ idle_idx = aufs_nwkq;
++
++ atomic_inc_return(&au_wkq[idle_idx].busy);
++ if (!enqueue(au_wkq + idle_idx, wkinfo))
++ return; /* success */
++
++ /* impossible? */
++ AuWarn1("failed to queue_work()\n");
++ yield();
++ }
++}
++
++static AuWkqFunc(wkq_func, wk)
++{
++ struct au_wkinfo *wkinfo = container_of(wk, struct au_wkinfo, wk);
++
++ LKTRTrace("wkinfo{0x%x, %p, %p, %p}\n",
++ wkinfo->flags, wkinfo->func, wkinfo->busyp, wkinfo->comp);
++
++ dlgt_func(wkinfo);
++ atomic_dec_return(wkinfo->busyp);
++ if (au_ftest_wkq(wkinfo->flags, WAIT))
++ complete(wkinfo->comp);
++ else {
++ au_mntput(wkinfo->sb);
++ module_put(THIS_MODULE);
++ kfree(wkinfo);
++ }
++}
++
++#if defined(CONFIG_4KSTACKS) || defined(Test4KSTACKS)
++#define AuWkqCompDeclare(name) struct completion *comp = NULL
++
++static int au_wkq_comp_alloc(struct au_wkinfo *wkinfo, struct completion **comp)
++{
++ *comp = kmalloc(sizeof(**comp), GFP_NOFS);
++ if (*comp) {
++ init_completion(*comp);
++ wkinfo->comp = *comp;
++ return 0;
++ }
++ return -ENOMEM;
++}
++
++static void au_wkq_comp_free(struct completion *comp)
++{
++ kfree(comp);
++}
++
++#else
++
++/* no braces */
++#define AuWkqCompDeclare(name) \
++ DECLARE_COMPLETION_ONSTACK(_ ## name); \
++ struct completion *comp = &_ ## name
++
++static int au_wkq_comp_alloc(struct au_wkinfo *wkinfo, struct completion **comp)
++{
++ wkinfo->comp = *comp;
++ return 0;
++}
++
++static void au_wkq_comp_free(struct completion *comp)
++{
++ /* empty */
++}
++#endif /* 4KSTACKS */
++
++static void au_wkq_run(struct au_wkinfo *wkinfo)
++{
++#if 1 /* tmp debug */
++ if (au_test_wkq(current))
++ au_dbg_blocked();
++#endif
++ AuDebugOn(au_test_wkq(current));
++
++ AuInitWkq(&wkinfo->wk, wkq_func);
++ dlgt_cred_store(wkinfo->flags, wkinfo);
++ do_wkq(wkinfo);
++}
++
++int au_wkq_wait(au_wkq_func_t func, void *args, int dlgt)
++{
++ int err;
++ AuWkqCompDeclare(comp);
++ struct au_wkinfo wkinfo = {
++ .flags = AuWkq_WAIT,
++ .func = func,
++ .args = args
++ };
++
++ LKTRTrace("dlgt %d\n", dlgt);
++
++ err = au_wkq_comp_alloc(&wkinfo, &comp);
++ if (!err) {
++ if (dlgt)
++ au_fset_wkq(wkinfo.flags, DLGT);
++ au_wkq_run(&wkinfo);
++ /* no timeout, no interrupt */
++ wait_for_completion(wkinfo.comp);
++ au_wkq_comp_free(comp);
++ }
++
++ AuTraceErr(err);
++ return err;
++
++}
++
++int au_wkq_nowait(au_wkq_func_t func, void *args, struct super_block *sb,
++ int dlgt)
++{
++ int err;
++ struct au_wkinfo *wkinfo;
++
++ LKTRTrace("dlgt %d\n", dlgt);
++ AuDebugOn(!sb);
++
++ atomic_inc_return(&au_sbi(sb)->si_nowait.nw_len);
++
++ /*
++ * wkq_func() must free this wkinfo.
++ * it highly depends upon the implementation of workqueue.
++ */
++ err = 0;
++ wkinfo = kmalloc(sizeof(*wkinfo), GFP_NOFS);
++ if (wkinfo) {
++ wkinfo->sb = sb;
++ wkinfo->flags = !AuWkq_WAIT;
++ wkinfo->func = func;
++ wkinfo->args = args;
++ wkinfo->comp = NULL;
++ if (dlgt)
++ au_fset_wkq(wkinfo->flags, DLGT);
++ /* prohibit umount */
++ __module_get(THIS_MODULE);
++ au_mntget(sb);
++
++ au_wkq_run(wkinfo);
++ } else {
++ err = -ENOMEM;
++ atomic_dec_return(&au_sbi(sb)->si_nowait.nw_len);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++void au_wkq_fin(void)
++{
++ int i;
++
++ AuTraceEnter();
++
++ for (i = 0; i < aufs_nwkq; i++)
++ if (au_wkq[i].q && !IS_ERR(au_wkq[i].q))
++ destroy_workqueue(au_wkq[i].q);
++ kfree(au_wkq);
++}
++
++int __init au_wkq_init(void)
++{
++ int err, i;
++ struct au_wkq *nowaitq;
++
++ LKTRTrace("%d\n", aufs_nwkq);
++
++ /* '+1' is for accounting of nowait queue */
++ err = -ENOMEM;
++ au_wkq = kcalloc(aufs_nwkq + 1, sizeof(*au_wkq), GFP_NOFS);
++ if (unlikely(!au_wkq))
++ goto out;
++
++ err = 0;
++ for (i = 0; i < aufs_nwkq; i++) {
++ au_wkq[i].q = create_singlethread_workqueue(AUFS_WKQ_NAME);
++ if (au_wkq[i].q && !IS_ERR(au_wkq[i].q)) {
++ atomic_set(&au_wkq[i].busy, 0);
++ atomic_set(&au_wkq[i].max_busy, 0);
++ continue;
++ }
++
++ err = PTR_ERR(au_wkq[i].q);
++ au_wkq_fin();
++ break;
++ }
++
++ /* nowait accounting */
++ nowaitq = au_wkq + aufs_nwkq;
++ atomic_set(&nowaitq->busy, 0);
++ atomic_set(&nowaitq->max_busy, 0);
++ nowaitq->q = NULL;
++ /* smp_mb(); */ /* atomic_set */
++
++#if 0 // test accouting
++ if (!err) {
++ static void f(void *args)
++ {
++ DbgSleep(1);
++ }
++ int i;
++ //au_debug_on();
++ LKTRTrace("f %p\n", f);
++ for (i = 0; i < 10; i++)
++ au_wkq_nowait(f, NULL, 0);
++ for (i = 0; i < aufs_nwkq; i++)
++ au_wkq_wait(f, NULL, 0);
++ DbgSleep(11);
++ //au_debug_off();
++ }
++#endif
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
+diff --git a/fs/aufs/wkq.h b/fs/aufs/wkq.h
+new file mode 100644
+index 0000000..ae14367
+--- /dev/null
++++ b/fs/aufs/wkq.h
+@@ -0,0 +1,128 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * workqueue for asynchronous/super-io/delegated operations
++ *
++ * $Id: wkq.h,v 1.26 2009/01/26 06:24:45 sfjro Exp $
++ */
++
++#ifndef __AUFS_WKQ_H__
++#define __AUFS_WKQ_H__
++
++#ifdef __KERNEL__
++
++#include <linux/fs.h>
++#include <linux/sched.h>
++#include <linux/version.h>
++#include <linux/workqueue.h>
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
++#define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work)
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
++#define AuInitWkq(wk, func) INIT_WORK(wk, func)
++#define AuWkqFunc(name, arg) void name(struct work_struct *arg)
++#else
++#define AuInitWkq(wk, func) INIT_WORK(wk, func, wk)
++#define AuWkqFunc(name, arg) void name(void *arg)
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++/* internal workqueue named AUFS_WKQ_NAME */
++struct au_wkq {
++ struct workqueue_struct *q;
++
++ /* accounting */
++ atomic_t busy;
++ atomic_t max_busy;
++};
++
++/*
++ * in the next operation, wait for the 'nowait' tasks in system-wide workqueue
++ */
++struct au_nowait_tasks {
++ atomic_t nw_len;
++ wait_queue_head_t nw_wq;
++};
++
++/* ---------------------------------------------------------------------- */
++
++extern struct au_wkq *au_wkq;
++typedef void (*au_wkq_func_t)(void *args);
++
++/* wkq flags */
++#define AuWkq_WAIT 1
++#define AuWkq_DLGT (1 << 1)
++#define au_ftest_wkq(flags, name) ((flags) & AuWkq_##name)
++#define au_fset_wkq(flags, name) { (flags) |= AuWkq_##name; }
++#define au_fclr_wkq(flags, name) { (flags) &= ~AuWkq_##name; }
++#ifndef CONFIG_AUFS_DLGT
++#undef AuWkq_DLGT
++#define AuWkq_DLGT 0
++#endif
++
++int au_wkq_wait(au_wkq_func_t func, void *args, int dlgt);
++int au_wkq_nowait(au_wkq_func_t func, void *args, struct super_block *sb,
++ int dlgt);
++int __init au_wkq_init(void);
++void au_wkq_fin(void);
++
++/* ---------------------------------------------------------------------- */
++
++static inline int au_test_nowait_wkq(struct task_struct *tsk)
++{
++ static const char *p = "events";
++ return !tsk->mm && !strncmp(tsk->comm, p, strlen(p));
++}
++
++static inline int au_test_wkq(struct task_struct *tsk)
++{
++ return !tsk->mm && !strcmp(tsk->comm, AUFS_WKQ_NAME);
++#if 0 /* reserved for future use, per-cpu workqueue */
++ return !tsk->mm
++ && !memcmp(tsk->comm, AUFS_WKQ_NAME "/",
++ sizeof(AUFS_WKQ_NAME));
++#endif
++}
++
++static inline void au_nwt_init(struct au_nowait_tasks *nwt)
++{
++ atomic_set(&nwt->nw_len, 0);
++ smp_mb(); /* atomic_set */
++ init_waitqueue_head(&nwt->nw_wq);
++}
++
++static inline void au_nwt_done(struct au_nowait_tasks *nwt)
++{
++ AuTraceEnter();
++
++ if (!atomic_dec_return(&nwt->nw_len))
++ wake_up_all(&nwt->nw_wq);
++}
++
++static inline int au_nwt_flush(struct au_nowait_tasks *nwt)
++{
++ wait_event(nwt->nw_wq, !atomic_read(&nwt->nw_len));
++ return 0;
++}
++
++#endif /* __KERNEL__ */
++#endif /* __AUFS_WKQ_H__ */
+diff --git a/fs/aufs/xino.c b/fs/aufs/xino.c
+new file mode 100644
+index 0000000..8c4bb7f
+--- /dev/null
++++ b/fs/aufs/xino.c
+@@ -0,0 +1,1276 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/*
++ * external inode number translation table and bitmap
++ *
++ * $Id: xino.c,v 1.65 2009/01/26 06:24:24 sfjro Exp $
++ */
++
++#include <linux/fsnotify.h>
++#include <linux/smp_lock.h>
++#include "aufs.h"
++
++/* ---------------------------------------------------------------------- */
++
++ssize_t xino_fread(au_readf_t func, struct file *file, void *buf, size_t size,
++ loff_t *pos)
++{
++ ssize_t err;
++ mm_segment_t oldfs;
++
++ LKTRTrace("%.*s, sz %zu, *pos %lld\n",
++ AuDLNPair(file->f_dentry), size, *pos);
++
++ oldfs = get_fs();
++ set_fs(KERNEL_DS);
++ do {
++ /* todo: signal_pending? */
++ err = func(file, (char __user *)buf, size, pos);
++ } while (err == -EAGAIN || err == -EINTR);
++ set_fs(oldfs);
++
++#if 0 /* reserved for future use */
++ if (err > 0)
++ fsnotify_access(file->f_dentry);
++#endif
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static ssize_t do_xino_fwrite(au_writef_t func, struct file *file, void *buf,
++ size_t size, loff_t *pos)
++{
++ ssize_t err;
++ mm_segment_t oldfs;
++
++ lockdep_off();
++ oldfs = get_fs();
++ set_fs(KERNEL_DS);
++ do {
++ /* todo: signal_pending? */
++ err = func(file, (const char __user *)buf, size, pos);
++ } while (err == -EAGAIN || err == -EINTR);
++ set_fs(oldfs);
++ lockdep_on();
++
++ if (err >= 0)
++ au_update_fuse_h_inode(file->f_vfsmnt, file->f_dentry);
++ /*ignore*/
++
++#if 0 /* reserved for future use */
++ if (err > 0)
++ fsnotify_modify(file->f_dentry);
++#endif
++
++ AuTraceErr(err);
++ return err;
++}
++
++struct do_xino_fwrite_args {
++ ssize_t *errp;
++ au_writef_t func;
++ struct file *file;
++ void *buf;
++ size_t size;
++ loff_t *pos;
++};
++
++static void call_do_xino_fwrite(void *args)
++{
++ struct do_xino_fwrite_args *a = args;
++ *a->errp = do_xino_fwrite(a->func, a->file, a->buf, a->size, a->pos);
++}
++
++ssize_t xino_fwrite(au_writef_t func, struct file *file, void *buf, size_t size,
++ loff_t *pos)
++{
++ ssize_t err;
++
++ LKTRTrace("%.*s, sz %zu, *pos %lld\n",
++ AuDLNPair(file->f_dentry), size, *pos);
++
++ /* todo: signal block and no wkq? */
++ /*
++ * it breaks RLIMIT_FSIZE and normal user's limit,
++ * users should care about quota and real 'filesystem full.'
++ */
++ if (!au_test_wkq(current)) {
++ int wkq_err;
++ struct do_xino_fwrite_args args = {
++ .errp = &err,
++ .func = func,
++ .file = file,
++ .buf = buf,
++ .size = size,
++ .pos = pos
++ };
++ wkq_err = au_wkq_wait(call_do_xino_fwrite, &args, /*dlgt*/0);
++ if (unlikely(wkq_err))
++ err = wkq_err;
++ } else
++ err = do_xino_fwrite(func, file, buf, size, pos);
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)
++struct xino_do_trunc_args {
++ struct vfsmount *mnt;
++ struct au_branch *br;
++};
++
++static void xino_do_trunc(void *_args)
++{
++ struct xino_do_trunc_args *args = _args;
++ struct super_block *sb;
++ aufs_bindex_t bindex;
++ int err;
++ struct file *file;
++ struct inode *dir;
++
++ err = 0;
++ sb = args->mnt->mnt_sb;
++ dir = sb->s_root->d_inode;
++ si_noflush_write_lock(sb);
++ ii_read_lock_parent(dir);
++ bindex = au_br_index(sb, args->br->br_id);
++ AuDebugOn(bindex < 0);
++ err = au_xino_trunc(sb, bindex);
++ if (unlikely(err))
++ goto out;
++
++ file = args->br->br_xino.xi_file;
++ au_update_fuse_h_inode(args->br->br_mnt, file->f_dentry); /*ignore*/
++ if (file->f_dentry->d_inode->i_blocks >= args->br->br_xino_upper)
++ args->br->br_xino_upper += AUFS_XINO_TRUNC_STEP;
++
++ out:
++ ii_read_unlock(dir);
++ if (unlikely(err))
++ AuWarn("err b%d, (%d)\n", bindex, err);
++ atomic_dec_return(&args->br->br_xino_running);
++ au_br_put(args->br);
++ au_nwt_done(&au_sbi(sb)->si_nowait);
++ si_write_unlock(sb);
++ mntput(args->mnt);
++ kfree(args);
++}
++
++static void xino_try_trunc(struct super_block *sb, struct au_branch *br)
++{
++ struct xino_do_trunc_args *args;
++ struct au_sbinfo *sbinfo;
++ struct file *file = br->br_xino.xi_file;
++ int wkq_err;
++
++ au_update_fuse_h_inode(br->br_mnt, file->f_dentry); /*ignore*/
++ if (file->f_dentry->d_inode->i_blocks < br->br_xino_upper)
++ return;
++ if (atomic_inc_return(&br->br_xino_running) > 1)
++ goto out;
++
++ /* lock and kfree() will be called in trunc_xino() */
++ args = kmalloc(sizeof(*args), GFP_NOFS);
++ if (unlikely(!args)) {
++ AuErr1("no memory\n");
++ goto out_args;
++ }
++
++ sbinfo = au_sbi(sb);
++ args->mnt = mntget(sbinfo->si_mnt);
++ au_br_get(br);
++ args->br = br;
++ wkq_err = au_wkq_nowait(xino_do_trunc, args, sb, /*dlgt*/0);
++ if (!wkq_err)
++ return; /* success */
++
++ AuErr("wkq %d\n", wkq_err);
++ mntput(sbinfo->si_mnt);
++ au_br_put(br);
++
++ out_args:
++ kfree(args);
++ out:
++ atomic_dec_return(&br->br_xino_running);
++}
++#else
++static void xino_try_trunc(struct super_block *sb, struct au_branch *br)
++{
++ /* nothing */
++}
++#endif
++
++/* ---------------------------------------------------------------------- */
++
++static int au_xino_do_write(au_writef_t write, struct file *file,
++ ino_t h_ino, struct au_xino_entry *xinoe)
++{
++ loff_t pos;
++ ssize_t sz;
++
++ AuTraceEnter();
++
++ pos = h_ino;
++ if (unlikely(Au_LOFF_MAX / sizeof(*xinoe) - 1 < pos)) {
++ AuIOErr1("too large hi%lu\n", (unsigned long)h_ino);
++ return -EFBIG;
++ }
++ pos *= sizeof(*xinoe);
++ sz = xino_fwrite(write, file, xinoe, sizeof(*xinoe), &pos);
++ if (sz == sizeof(*xinoe))
++ return 0; /* success */
++
++ AuIOErr("write failed (%zd)\n", sz);
++ return -EIO;
++}
++
++/*
++ * write @ino to the xinofile for the specified branch{@sb, @bindex}
++ * at the position of @_ino.
++ * when @ino is zero, it is written to the xinofile and means no entry.
++ */
++int au_xino_write(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ struct au_xino_entry *xinoe)
++{
++ int err;
++ struct file *file;
++ struct au_branch *br;
++ unsigned int mnt_flags;
++
++ LKTRTrace("b%d, hi%lu, i%lu\n",
++ bindex, (unsigned long)h_ino, (unsigned long)xinoe->ino);
++ BUILD_BUG_ON(sizeof(long long) != sizeof(Au_LOFF_MAX)
++ || ((loff_t)-1) > 0);
++
++ mnt_flags = au_mntflags(sb);
++ if (!au_opt_test_xino(mnt_flags))
++ return 0;
++
++ br = au_sbr(sb, bindex);
++ file = br->br_xino.xi_file;
++ AuDebugOn(!file);
++
++ err = au_xino_do_write(au_sbi(sb)->si_xwrite, file, h_ino, xinoe);
++ if (!err) {
++ if (au_opt_test(mnt_flags, TRUNC_XINO)
++ && au_test_trunc_xino(br->br_mnt->mnt_sb))
++ xino_try_trunc(sb, br);
++ return 0; /* success */
++ }
++
++ AuIOErr("write failed (%d)\n", err);
++ return -EIO;
++}
++
++/* ---------------------------------------------------------------------- */
++
++static const int page_bits = (int)PAGE_SIZE * BITS_PER_BYTE;
++//static const int page_bits = 4;
++static ino_t xib_calc_ino(unsigned long pindex, int bit)
++{
++ ino_t ino;
++
++ AuDebugOn(bit < 0 || page_bits <= bit);
++ ino = AUFS_FIRST_INO + pindex * page_bits + bit;
++ return ino;
++}
++
++static void xib_calc_bit(ino_t ino, unsigned long *pindex, int *bit)
++{
++ AuDebugOn(ino < AUFS_FIRST_INO);
++ ino -= AUFS_FIRST_INO;
++ *pindex = ino / page_bits;
++ *bit = ino % page_bits;
++}
++
++static int xib_pindex(struct super_block *sb, unsigned long pindex)
++{
++ int err;
++ struct au_sbinfo *sbinfo;
++ loff_t pos;
++ ssize_t sz;
++ struct file *xib;
++ unsigned long *p;
++
++ LKTRTrace("pindex %lu\n", pindex);
++ sbinfo = au_sbi(sb);
++ MtxMustLock(&sbinfo->si_xib_mtx);
++ AuDebugOn(pindex > ULONG_MAX / PAGE_SIZE
++ || !au_opt_test_xino(sbinfo->si_mntflags));
++
++ if (pindex == sbinfo->si_xib_last_pindex)
++ return 0;
++
++ xib = sbinfo->si_xib;
++ p = sbinfo->si_xib_buf;
++ pos = sbinfo->si_xib_last_pindex;
++ pos *= PAGE_SIZE;
++ sz = xino_fwrite(sbinfo->si_xwrite, xib, p, PAGE_SIZE, &pos);
++ if (unlikely(sz != PAGE_SIZE))
++ goto out;
++
++ pos = pindex;
++ pos *= PAGE_SIZE;
++ if (i_size_read(xib->f_dentry->d_inode) >= pos + PAGE_SIZE)
++ sz = xino_fread(sbinfo->si_xread, xib, p, PAGE_SIZE, &pos);
++ else {
++ memset(p, 0, PAGE_SIZE);
++ sz = xino_fwrite(sbinfo->si_xwrite, xib, p, PAGE_SIZE, &pos);
++ }
++ if (sz == PAGE_SIZE) {
++ sbinfo->si_xib_last_pindex = pindex;
++ return 0; /* success */
++ }
++
++ out:
++ AuIOErr1("write failed (%zd)\n", sz);
++ err = sz;
++ if (sz >= 0)
++ err = -EIO;
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++int au_xino_write0(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ ino_t ino)
++{
++ int err, bit;
++ unsigned long pindex;
++ struct au_sbinfo *sbinfo;
++ struct au_xino_entry xinoe = {
++ .ino = 0
++ };
++
++ LKTRTrace("b%d, hi%lu, i%lu\n",
++ bindex, (unsigned long)h_ino, (unsigned long)ino);
++
++ if (!au_opt_test_xino(au_mntflags(sb)))
++ return 0;
++
++ err = 0;
++ sbinfo = au_sbi(sb);
++ if (ino) {
++ AuDebugOn(ino < AUFS_FIRST_INO);
++ xib_calc_bit(ino, &pindex, &bit);
++ AuDebugOn(page_bits <= bit);
++ mutex_lock(&sbinfo->si_xib_mtx);
++ err = xib_pindex(sb, pindex);
++ if (!err) {
++ clear_bit(bit, sbinfo->si_xib_buf);
++ sbinfo->si_xib_next_bit = bit;
++ }
++ mutex_unlock(&sbinfo->si_xib_mtx);
++ }
++
++ if (!err)
++ err = au_xino_write(sb, bindex, h_ino, &xinoe);
++ return err;
++}
++
++ino_t au_xino_new_ino(struct super_block *sb)
++{
++ ino_t ino;
++ struct au_sbinfo *sbinfo;
++ int free_bit, err;
++ unsigned long *p, pindex, ul, pend;
++ struct file *file;
++
++ AuTraceEnter();
++
++ if (!au_opt_test_xino(au_mntflags(sb)))
++ return iunique(sb, AUFS_FIRST_INO);
++
++ sbinfo = au_sbi(sb);
++ mutex_lock(&sbinfo->si_xib_mtx);
++ p = sbinfo->si_xib_buf;
++ free_bit = sbinfo->si_xib_next_bit;
++ if (free_bit < page_bits && !test_bit(free_bit, p))
++ goto out; /* success */
++ free_bit = find_first_zero_bit(p, page_bits);
++ if (free_bit < page_bits)
++ goto out; /* success */
++
++ pindex = sbinfo->si_xib_last_pindex;
++ for (ul = pindex - 1; ul < ULONG_MAX; ul--) {
++ err = xib_pindex(sb, ul);
++ if (unlikely(err))
++ goto out_err;
++ free_bit = find_first_zero_bit(p, page_bits);
++ if (free_bit < page_bits)
++ goto out; /* success */
++ }
++
++ file = sbinfo->si_xib;
++ pend = i_size_read(file->f_dentry->d_inode) / PAGE_SIZE;
++ for (ul = pindex + 1; ul <= pend; ul++) {
++ err = xib_pindex(sb, ul);
++ if (unlikely(err))
++ goto out_err;
++ free_bit = find_first_zero_bit(p, page_bits);
++ if (free_bit < page_bits)
++ goto out; /* success */
++ }
++ BUG();
++
++ out:
++ set_bit(free_bit, p);
++ sbinfo->si_xib_next_bit++;
++ pindex = sbinfo->si_xib_last_pindex;
++ mutex_unlock(&sbinfo->si_xib_mtx);
++ ino = xib_calc_ino(pindex, free_bit);
++ LKTRTrace("i%lu\n", (unsigned long)ino);
++ return ino;
++ out_err:
++ mutex_unlock(&sbinfo->si_xib_mtx);
++ LKTRTrace("i0\n");
++ return 0;
++}
++
++/*
++ * read @ino from xinofile for the specified branch{@sb, @bindex}
++ * at the position of @h_ino.
++ * if @ino does not exist and @do_new is true, get new one.
++ */
++int au_xino_read(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino,
++ struct au_xino_entry *xinoe)
++{
++ int err;
++ struct file *file;
++ loff_t pos;
++ ssize_t sz;
++ struct au_sbinfo *sbinfo;
++
++ LKTRTrace("b%d, hi%lu\n", bindex, (unsigned long)h_ino);
++
++ xinoe->ino = 0;
++ if (!au_opt_test_xino(au_mntflags(sb)))
++ return 0; /* no ino */
++
++ err = 0;
++ sbinfo = au_sbi(sb);
++ pos = h_ino;
++ if (unlikely(Au_LOFF_MAX / sizeof(*xinoe) - 1 < pos)) {
++ AuIOErr1("too large hi%lu\n", (unsigned long)h_ino);
++ return -EFBIG;
++ }
++ pos *= sizeof(*xinoe);
++
++ file = au_sbr(sb, bindex)->br_xino.xi_file;
++ AuDebugOn(!file);
++ if (i_size_read(file->f_dentry->d_inode) < pos + sizeof(*xinoe))
++ return 0; /* no ino */
++
++ sz = xino_fread(sbinfo->si_xread, file, xinoe, sizeof(*xinoe), &pos);
++ if (sz == sizeof(*xinoe))
++ return 0; /* success */
++
++ err = sz;
++ if (unlikely(sz >= 0)) {
++ err = -EIO;
++ AuIOErr("xino read error (%zd)\n", sz);
++ }
++
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++struct file *au_xino_create(struct super_block *sb, char *fname, int silent)
++{
++ struct file *file;
++ int err;
++ struct dentry *h_parent;
++ struct inode *h_dir;
++ struct vfsub_args vargs;
++
++ LKTRTrace("%s\n", fname);
++
++ /*
++ * at mount-time, and the xino file is the default path,
++ * hinotify is disabled so we have no inotify events to ignore.
++ * when a user specified the xino, we cannot get au_hdir to be ignored.
++ */
++ vfsub_args_init(&vargs, /*ign*/NULL, /*dlgt*/0, 0);
++ file = vfsub_filp_open(fname, O_RDWR | O_CREAT | O_EXCL | O_LARGEFILE,
++ S_IRUGO | S_IWUGO);
++ if (IS_ERR(file)) {
++ if (!silent)
++ AuErr("open %s(%ld)\n", fname, PTR_ERR(file));
++ return file;
++ }
++
++ /* keep file count */
++ h_parent = dget_parent(file->f_dentry);
++ h_dir = h_parent->d_inode;
++ vfsub_i_lock_nested(h_dir, AuLsc_I_PARENT);
++ /* mnt_want_write() is unnecessary here */
++ err = vfsub_unlink(h_dir, file->f_dentry, &vargs);
++ vfsub_i_unlock(h_dir);
++ dput(h_parent);
++ if (unlikely(err)) {
++ if (!silent)
++ AuErr("unlink %s(%d)\n", fname, err);
++ goto out;
++ }
++
++ if (sb != file->f_dentry->d_sb)
++ return file; /* success */
++
++ if (!silent)
++ AuErr("%s must be outside\n", fname);
++ err = -EINVAL;
++
++ out:
++ fput(file);
++ file = ERR_PTR(err);
++ return file;
++}
++
++/*
++ * find another branch who is on the same filesystem of the specified
++ * branch{@btgt}. search until @bend.
++ */
++static int is_sb_shared(struct super_block *sb, aufs_bindex_t btgt,
++ aufs_bindex_t bend)
++{
++ aufs_bindex_t bindex;
++ struct super_block *tgt_sb = au_sbr_sb(sb, btgt);
++
++ for (bindex = 0; bindex < btgt; bindex++)
++ if (unlikely(tgt_sb == au_sbr_sb(sb, bindex)))
++ return bindex;
++ for (bindex++; bindex <= bend; bindex++)
++ if (unlikely(tgt_sb == au_sbr_sb(sb, bindex)))
++ return bindex;
++ return -1;
++}
++
++/*
++ * create a new xinofile at the same place/path as @base_file.
++ */
++struct file *au_xino_create2(struct super_block *sb, struct file *base_file,
++ struct file *copy_src)
++{
++ struct file *file;
++ int err;
++ struct dentry *base, *dentry, *parent;
++ struct inode *dir, *inode;
++ struct qstr *name;
++ struct au_hinode *hdir;
++ struct au_branch *br;
++ aufs_bindex_t bindex;
++ struct au_hin_ignore ign;
++ struct vfsub_args vargs;
++ struct au_ndx ndx = {
++ .nfsmnt = NULL,
++ .flags = 0,
++ .nd = NULL,
++ /* .br = NULL */
++ };
++
++ base = base_file->f_dentry;
++ LKTRTrace("%.*s\n", AuDLNPair(base));
++ parent = base->d_parent; /* dir inode is locked */
++ dir = parent->d_inode;
++ IMustLock(dir);
++
++ file = ERR_PTR(-EINVAL);
++ if (unlikely(au_test_nfs(parent->d_sb)
++ || au_test_ecryptfs(parent->d_sb)))
++ goto out;
++
++ /* do not superio, nor NFS. */
++ name = &base->d_name;
++ dentry = au_lkup_one(name->name, parent, name->len, &ndx);
++ if (IS_ERR(dentry)) {
++ file = (void *)dentry;
++ AuErr("%.*s lookup err %ld\n", AuLNPair(name), PTR_ERR(dentry));
++ goto out;
++ }
++
++ hdir = NULL;
++ br = au_xino_def_br(au_sbi(sb));
++ if (br) {
++ bindex = au_find_bindex(sb, br);
++ if (bindex >= 0)
++ hdir = au_hi(sb->s_root->d_inode, bindex);
++ }
++ vfsub_args_init(&vargs, &ign, 0, 0);
++ vfsub_ign_hinode(&vargs, IN_CREATE, hdir);
++ /* no need to mnt_want_write() since we call dentry_open() later */
++ err = vfsub_create(dir, dentry, S_IRUGO | S_IWUGO, NULL, &vargs);
++ if (unlikely(err)) {
++ file = ERR_PTR(err);
++ AuErr("%.*s create err %d\n", AuLNPair(name), err);
++ goto out_dput;
++ }
++ file = dentry_open(dget(dentry), mntget(base_file->f_vfsmnt),
++ O_RDWR | O_CREAT | O_EXCL | O_LARGEFILE);
++ if (IS_ERR(file)) {
++ AuErr("%.*s open err %ld\n", AuLNPair(name), PTR_ERR(file));
++ goto out_dput;
++ }
++ vfsub_args_reinit(&vargs);
++ vfsub_ign_hinode(&vargs, IN_DELETE, hdir);
++ err = vfsub_unlink(dir, dentry, &vargs);
++ if (unlikely(err)) {
++ AuErr("%.*s unlink err %d\n", AuLNPair(name), err);
++ goto out_fput;
++ }
++
++ if (copy_src) {
++ inode = copy_src->f_dentry->d_inode;
++ err = au_copy_file(file, copy_src, i_size_read(inode),
++ hdir, sb, &vargs);
++ if (unlikely(err)) {
++ AuErr("%.*s copy err %d\n", AuLNPair(name), err);
++ goto out_fput;
++ }
++ }
++ goto out_dput; /* success */
++
++ out_fput:
++ fput(file);
++ file = ERR_PTR(err);
++ out_dput:
++ dput(dentry);
++ out:
++ AuTraceErrPtr(file);
++ return file;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * initialize the xinofile for the specified branch{@sb, @bindex}
++ * at the place/path where @base_file indicates.
++ * test whether another branch is on the same filesystem or not,
++ * if @do_test is true.
++ */
++int au_xino_br(struct super_block *sb, struct au_branch *br, ino_t h_ino,
++ struct file *base_file, int do_test)
++{
++ int err;
++ struct au_branch *shared_br;
++ aufs_bindex_t bshared, bend, bindex;
++ unsigned char do_create;
++ struct inode *dir;
++ struct au_xino_entry xinoe;
++ struct dentry *parent;
++ struct file *file;
++ struct super_block *tgt_sb;
++
++ LKTRTrace("base_file %p, do_test %d\n", base_file, do_test);
++ SiMustWriteLock(sb);
++ AuDebugOn(!au_opt_test_xino(au_mntflags(sb)));
++ AuDebugOn(br->br_xino.xi_file);
++
++ do_create = 1;
++ bshared = -1;
++ shared_br = NULL;
++ bend = au_sbend(sb);
++ if (do_test) {
++ tgt_sb = br->br_mnt->mnt_sb;
++ for (bindex = 0; bindex <= bend; bindex++)
++ if (tgt_sb == au_sbr_sb(sb, bindex)) {
++ bshared = bindex;
++ break;
++ }
++ }
++ if (bshared >= 0) {
++ shared_br = au_sbr(sb, bshared);
++ do_create = !shared_br->br_xino.xi_file;
++ }
++
++ if (do_create) {
++ parent = dget_parent(base_file->f_dentry);
++ dir = parent->d_inode;
++ vfsub_i_lock_nested(dir, AuLsc_I_PARENT);
++ /* mnt_want_write() is unnecessary here */
++ file = au_xino_create2(sb, base_file, NULL);
++ vfsub_i_unlock(dir);
++ dput(parent);
++ err = PTR_ERR(file);
++ if (IS_ERR(file))
++ goto out;
++ br->br_xino.xi_file = file;
++ } else {
++ br->br_xino.xi_file = shared_br->br_xino.xi_file;
++ get_file(br->br_xino.xi_file);
++ }
++
++ xinoe.ino = AUFS_ROOT_INO;
++#if 0 /* reserved for future use */
++ xinoe.h_gen = h_inode->i_generation;
++ WARN_ON(xinoe.h_gen == AuXino_INVALID_HGEN);
++#endif
++ err = au_xino_do_write(au_sbi(sb)->si_xwrite, br->br_xino.xi_file,
++ h_ino, &xinoe);
++ if (!err)
++ return 0; /* success */
++
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* too slow */
++static int do_xib_restore(struct super_block *sb, struct file *file, void *page)
++{
++ int err, bit;
++ struct au_sbinfo *sbinfo;
++ au_readf_t func;
++ loff_t pos, pend;
++ ssize_t sz;
++ struct au_xino_entry *xinoe;
++ unsigned long pindex;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ err = 0;
++ sbinfo = au_sbi(sb);
++ func = sbinfo->si_xread;
++ pend = i_size_read(file->f_dentry->d_inode);
++#ifdef CONFIG_AUFS_DEBUG
++ if (unlikely(pend > (1 << 22)))
++ AuWarn("testing a large xino file %lld\n", (long long)pend);
++#endif
++ pos = 0;
++ while (pos < pend) {
++ sz = xino_fread(func, file, page, PAGE_SIZE, &pos);
++ err = sz;
++ if (unlikely(sz <= 0))
++ goto out;
++
++ err = 0;
++ for (xinoe = page; sz > 0; xinoe++, sz -= sizeof(xinoe)) {
++ if (unlikely(xinoe->ino < AUFS_FIRST_INO))
++ continue;
++
++ xib_calc_bit(xinoe->ino, &pindex, &bit);
++ AuDebugOn(page_bits <= bit);
++ err = xib_pindex(sb, pindex);
++ if (!err)
++ set_bit(bit, sbinfo->si_xib_buf);
++ else
++ goto out;
++ }
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++static int xib_restore(struct super_block *sb)
++{
++ int err;
++ aufs_bindex_t bindex, bend;
++ void *page;
++
++ AuTraceEnter();
++
++ err = -ENOMEM;
++ page = (void *)__get_free_page(GFP_NOFS);
++ if (unlikely(!page))
++ goto out;
++
++ err = 0;
++ bend = au_sbend(sb);
++ for (bindex = 0; !err && bindex <= bend; bindex++)
++ if (!bindex || is_sb_shared(sb, bindex, bindex - 1) < 0)
++ err = do_xib_restore
++ (sb, au_sbr(sb, bindex)->br_xino.xi_file, page);
++ else
++ LKTRTrace("b%d\n", bindex);
++ free_page((unsigned long)page);
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++int au_xib_trunc(struct super_block *sb)
++{
++ int err;
++ unsigned int mnt_flags;
++ ssize_t sz;
++ loff_t pos;
++ struct au_sbinfo *sbinfo;
++ unsigned long *p;
++ struct dentry *parent;
++ struct inode *dir;
++ struct file *file;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ err = 0;
++ mnt_flags = au_mntflags(sb);
++ if (!au_opt_test_xino(mnt_flags))
++ goto out;
++
++ sbinfo = au_sbi(sb);
++ if (i_size_read(sbinfo->si_xib->f_dentry->d_inode) <= PAGE_SIZE)
++ goto out;
++ parent = dget_parent(sbinfo->si_xib->f_dentry);
++ dir = parent->d_inode;
++ vfsub_i_lock_nested(dir, AuLsc_I_PARENT);
++ /* mnt_want_write() is unnecessary here */
++ file = au_xino_create2(sb, sbinfo->si_xib, NULL);
++ vfsub_i_unlock(dir);
++ dput(parent);
++ err = PTR_ERR(file);
++ if (IS_ERR(file))
++ goto out;
++ fput(sbinfo->si_xib);
++ sbinfo->si_xib = file;
++
++ p = sbinfo->si_xib_buf;
++ memset(p, 0, PAGE_SIZE);
++ pos = 0;
++ sz = xino_fwrite(sbinfo->si_xwrite, sbinfo->si_xib, p, PAGE_SIZE, &pos);
++ if (unlikely(sz != PAGE_SIZE)) {
++ err = sz;
++ AuIOErr("err %d\n", err);
++ if (sz >= 0)
++ err = -EIO;
++ goto out;
++ }
++
++ if (au_opt_test_xino(mnt_flags)) {
++ mutex_lock(&sbinfo->si_xib_mtx);
++ /* mnt_want_write() is unnecessary here */
++ err = xib_restore(sb);
++ mutex_unlock(&sbinfo->si_xib_mtx);
++#if 0 /* reserved for future use */
++ } else {
++ /* is it really safe? */
++ /* dont trust BKL */
++ AuDebugOn(!kernel_locked());
++ ino = AUFS_FIRST_INO;
++ list_for_each_entry(inode, &sb->s_inodes, i_sb_list)
++ if (ino < inode->i_ino)
++ ino = inode->i_ino;
++
++ /* make iunique to return larger than active max inode number */
++ iunique(sb, ino);
++ err = 0;
++#endif
++ }
++
++out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * xino mount option handlers
++ */
++static au_readf_t find_readf(struct file *h_file)
++{
++ const struct file_operations *fop = h_file->f_op;
++
++ if (fop) {
++ if (fop->read)
++ return fop->read;
++ if (fop->aio_read)
++ return do_sync_read;
++ }
++ return ERR_PTR(-ENOSYS);
++}
++
++static au_writef_t find_writef(struct file *h_file)
++{
++ const struct file_operations *fop = h_file->f_op;
++
++ if (fop) {
++ if (fop->write)
++ return fop->write;
++ if (fop->aio_write)
++ return do_sync_write;
++ }
++ return ERR_PTR(-ENOSYS);
++}
++
++/* xino bitmap */
++static void xino_clear_xib(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ sbinfo = au_sbi(sb);
++ sbinfo->si_xread = NULL;
++ sbinfo->si_xwrite = NULL;
++ if (sbinfo->si_xib)
++ fput(sbinfo->si_xib);
++ sbinfo->si_xib = NULL;
++ free_page((unsigned long)sbinfo->si_xib_buf);
++ sbinfo->si_xib_buf = NULL;
++}
++
++static int au_xino_set_xib(struct super_block *sb, struct file *base)
++{
++ int err;
++ struct au_sbinfo *sbinfo;
++ struct file *file;
++ loff_t pos;
++
++ LKTRTrace("%.*s\n", AuDLNPair(base->f_dentry));
++ SiMustWriteLock(sb);
++
++ sbinfo = au_sbi(sb);
++ file = au_xino_create2(sb, base, sbinfo->si_xib);
++ err = PTR_ERR(file);
++ if (IS_ERR(file))
++ goto out;
++ if (sbinfo->si_xib)
++ fput(sbinfo->si_xib);
++ sbinfo->si_xib = file;
++ sbinfo->si_xread = find_readf(file);
++ AuDebugOn(IS_ERR(sbinfo->si_xread));
++ sbinfo->si_xwrite = find_writef(file);
++ AuDebugOn(IS_ERR(sbinfo->si_xwrite));
++
++ err = -ENOMEM;
++ if (!sbinfo->si_xib_buf)
++ sbinfo->si_xib_buf = (void *)get_zeroed_page(GFP_NOFS);
++ if (unlikely(!sbinfo->si_xib_buf))
++ goto out_unset;
++
++ sbinfo->si_xib_last_pindex = 0;
++ sbinfo->si_xib_next_bit = 0;
++
++ /* no need to lock for i_size_read() */
++ if (i_size_read(file->f_dentry->d_inode) < PAGE_SIZE) {
++ pos = 0;
++ err = xino_fwrite(sbinfo->si_xwrite, file, sbinfo->si_xib_buf,
++ PAGE_SIZE, &pos);
++ if (unlikely(err != PAGE_SIZE))
++ goto out_free;
++ }
++ err = 0;
++ goto out; /* success */
++
++ out_free:
++ free_page((unsigned long)sbinfo->si_xib_buf);
++ sbinfo->si_xib_buf = NULL;
++ if (err >= 0)
++ err = -EIO;
++ out_unset:
++ fput(sbinfo->si_xib);
++ sbinfo->si_xib = NULL;
++ sbinfo->si_xread = NULL;
++ sbinfo->si_xwrite = NULL;
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* xino for each branch */
++static void xino_clear_br(struct super_block *sb)
++{
++ aufs_bindex_t bindex, bend;
++ struct au_branch *br;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ bend = au_sbend(sb);
++ for (bindex = 0; bindex <= bend; bindex++) {
++ br = au_sbr(sb, bindex);
++ if (!br || !br->br_xino.xi_file)
++ continue;
++
++ fput(br->br_xino.xi_file);
++ br->br_xino.xi_file = NULL;
++ }
++}
++
++static int au_xino_set_br(struct super_block *sb, struct file *base)
++{
++ int err;
++ aufs_bindex_t bindex, bend, bshared;
++ struct {
++ struct file *old, *new;
++ } *fpair, *p;
++ struct au_branch *br;
++ struct au_xino_entry xinoe;
++ struct inode *inode;
++ au_writef_t writef;
++
++ LKTRTrace("%.*s\n", AuDLNPair(base->f_dentry));
++ SiMustWriteLock(sb);
++
++ err = -ENOMEM;
++ bend = au_sbend(sb);
++ fpair = kcalloc(bend + 1, sizeof(*fpair), GFP_NOFS);
++ if (unlikely(!fpair))
++ goto out;
++
++ inode = sb->s_root->d_inode;
++ xinoe.ino = AUFS_ROOT_INO;
++ writef = au_sbi(sb)->si_xwrite;
++ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) {
++ br = au_sbr(sb, bindex);
++ bshared = is_sb_shared(sb, bindex, bindex - 1);
++ if (bshared >= 0) {
++ /* shared xino */
++ *p = fpair[bshared];
++ get_file(p->new);
++ }
++
++ if (!p->new) {
++ /* new xino */
++ p->old = br->br_xino.xi_file;
++ p->new = au_xino_create2(sb, base, br->br_xino.xi_file);
++ err = PTR_ERR(p->new);
++ if (IS_ERR(p->new)) {
++ p->new = NULL;
++ goto out_pair;
++ }
++ }
++
++ err = au_xino_do_write(writef, p->new,
++ au_h_iptr(inode, bindex)->i_ino, &xinoe);
++ if (unlikely(err))
++ goto out_pair;
++ }
++
++ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) {
++ br = au_sbr(sb, bindex);
++ AuDebugOn(p->old != br->br_xino.xi_file);
++ if (br->br_xino.xi_file)
++ fput(br->br_xino.xi_file);
++ get_file(p->new);
++ br->br_xino.xi_file = p->new;
++ }
++
++ out_pair:
++ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++)
++ if (p->new)
++ fput(p->new);
++ else
++ break;
++ kfree(fpair);
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++void au_xino_clr(struct super_block *sb)
++{
++ struct au_sbinfo *sbinfo;
++
++ AuTraceEnter();
++ SiMustWriteLock(sb);
++
++ au_xigen_clr(sb);
++ xino_clear_xib(sb);
++ xino_clear_br(sb);
++ sbinfo = au_sbi(sb);
++ /* lvalue, do not call au_mntflags() */
++ au_opt_clr(sbinfo->si_mntflags, XINO);
++ au_xino_def_br_set(NULL, sbinfo);
++}
++
++int au_xino_set(struct super_block *sb, struct au_opt_xino *xino, int remount)
++{
++ int err, skip;
++ struct dentry *parent, *cur_parent;
++ struct qstr *dname, *cur_name;
++ struct file *cur_xino;
++ struct inode *dir;
++ struct au_sbinfo *sbinfo;
++
++ LKTRTrace("remount %d\n", remount);
++ SiMustWriteLock(sb);
++
++ err = 0;
++ sbinfo = au_sbi(sb);
++ parent = dget_parent(xino->file->f_dentry);
++ if (remount) {
++ skip = 0;
++ dname = &xino->file->f_dentry->d_name;
++ cur_xino = sbinfo->si_xib;
++ if (cur_xino) {
++ cur_parent = dget_parent(cur_xino->f_dentry);
++ cur_name = &cur_xino->f_dentry->d_name;
++ skip = (cur_parent == parent
++ && dname->len == cur_name->len
++ && !memcmp(dname->name, cur_name->name,
++ dname->len));
++ dput(cur_parent);
++ }
++ if (skip)
++ goto out;
++ }
++
++ au_opt_set(sbinfo->si_mntflags, XINO);
++ au_xino_def_br_set(NULL, sbinfo);
++ dir = parent->d_inode;
++ vfsub_i_lock_nested(dir, AuLsc_I_PARENT);
++ /* mnt_want_write() is unnecessary here */
++ err = au_xino_set_xib(sb, xino->file);
++ if (!err)
++ err = au_xigen_set(sb, xino->file);
++ if (!err)
++ err = au_xino_set_br(sb, xino->file);
++ vfsub_i_unlock(dir);
++ if (!err)
++ goto out; /* success */
++
++ /* reset all */
++ AuIOErr("failed creating xino(%d).\n", err);
++
++ out:
++ dput(parent);
++ AuTraceErr(err);
++ return err;
++}
++
++int au_xino_trunc(struct super_block *sb, aufs_bindex_t bindex)
++{
++ int err;
++ struct au_branch *br;
++ struct file *new_xino;
++ struct super_block *h_sb;
++ aufs_bindex_t bi, bend;
++ struct dentry *parent;
++ struct inode *dir;
++
++ LKTRTrace("b%d\n", bindex);
++ SiMustWriteLock(sb);
++
++ err = -EINVAL;
++ bend = au_sbend(sb);
++ if (unlikely(bindex < 0 || bend < bindex))
++ goto out;
++ br = au_sbr(sb, bindex);
++ if (!br->br_xino.xi_file)
++ goto out;
++
++ parent = dget_parent(br->br_xino.xi_file->f_dentry);
++ dir = parent->d_inode;
++ vfsub_i_lock_nested(dir, AuLsc_I_PARENT);
++ /* mnt_want_write() is unnecessary here */
++ new_xino = au_xino_create2(sb, br->br_xino.xi_file,
++ br->br_xino.xi_file);
++ vfsub_i_unlock(dir);
++ dput(parent);
++ err = PTR_ERR(new_xino);
++ if (IS_ERR(new_xino))
++ goto out;
++ err = 0;
++ fput(br->br_xino.xi_file);
++ br->br_xino.xi_file = new_xino;
++
++ h_sb = br->br_mnt->mnt_sb;
++ for (bi = 0; bi <= bend; bi++) {
++ if (unlikely(bi == bindex))
++ continue;
++ br = au_sbr(sb, bi);
++ if (br->br_mnt->mnt_sb != h_sb)
++ continue;
++
++ fput(br->br_xino.xi_file);
++ br->br_xino.xi_file = new_xino;
++ get_file(new_xino);
++ }
++
++ out:
++ AuTraceErr(err);
++ return err;
++}
++
++/* ---------------------------------------------------------------------- */
++
++/*
++ * create a xinofile at the default place/path.
++ */
++struct file *au_xino_def(struct super_block *sb)
++{
++ struct file *file;
++ aufs_bindex_t bend, bindex, bwr;
++ char *page, *p;
++ struct au_branch *br;
++
++ AuTraceEnter();
++
++ bend = au_sbend(sb);
++ bwr = -1;
++ for (bindex = 0; bindex <= bend; bindex++) {
++ br = au_sbr(sb, bindex);
++ if (au_br_writable(br->br_perm)
++ && !au_test_nfs(br->br_mnt->mnt_sb)
++ && !au_test_ecryptfs(br->br_mnt->mnt_sb)) {
++ bwr = bindex;
++ break;
++ }
++ }
++
++ if (bwr >= 0) {
++ file = ERR_PTR(-ENOMEM);
++ page = __getname();
++ if (unlikely(!page))
++ goto out;
++ p = d_path(au_h_dptr(sb->s_root, bwr), au_sbr_mnt(sb, bwr),
++ page, PATH_MAX - sizeof(AUFS_XINO_FNAME));
++ //if (LktrCond) p = ERR_PTR(-1);
++ file = (void *)p;
++ if (!IS_ERR(p)) {
++ strcat(p, "/" AUFS_XINO_FNAME);
++ LKTRTrace("%s\n", p);
++ file = au_xino_create(sb, p, /*silent*/0);
++ if (!IS_ERR(file))
++ au_xino_def_br_set(au_sbr(sb, bwr), au_sbi(sb));
++ }
++ __putname(page);
++ } else {
++ file = au_xino_create(sb, AUFS_XINO_DEFPATH, /*silent*/0);
++ if (unlikely(au_test_nfs(file->f_dentry->d_sb)
++ || au_test_ecryptfs(file->f_dentry->d_sb))) {
++ AuErr("xino or noxino option is required "
++ "since %s is NFS\n", AUFS_XINO_DEFPATH);
++ fput(file);
++ file = ERR_PTR(-EINVAL);
++ }
++ if (!IS_ERR(file))
++ au_xino_def_br_set(NULL, au_sbi(sb));
++ }
++
++ out:
++ AuTraceErrPtr(file);
++ return file;
++}
+diff --git a/fs/yaffs2/Kconfig b/fs/yaffs2/Kconfig
+new file mode 100644
+index 0000000..de15163
+--- /dev/null
++++ b/fs/yaffs2/Kconfig
+@@ -0,0 +1,156 @@
++#
++# YAFFS file system configurations
++#
++
++config YAFFS_FS
++ tristate "YAFFS2 file system support"
++ default n
++ depends on MTD
++ select YAFFS_YAFFS1
++ select YAFFS_YAFFS2
++ help
++ YAFFS2, or Yet Another Flash Filing System, is a filing system
++ optimised for NAND Flash chips.
++
++ To compile the YAFFS2 file system support as a module, choose M
++ here: the module will be called yaffs2.
++
++ If unsure, say N.
++
++ Further information on YAFFS2 is available at
++ <http://www.aleph1.co.uk/yaffs/>.
++
++config YAFFS_YAFFS1
++ bool "512 byte / page devices"
++ depends on YAFFS_FS
++ default y
++ help
++ Enable YAFFS1 support -- yaffs for 512 byte / page devices
++
++ Not needed for 2K-page devices.
++
++ If unsure, say Y.
++
++config YAFFS_9BYTE_TAGS
++ bool "Use older-style on-NAND data format with pageStatus byte"
++ depends on YAFFS_YAFFS1
++ default n
++ help
++
++ Older-style on-NAND data format has a "pageStatus" byte to record
++ chunk/page state. This byte is zero when the page is discarded.
++ Choose this option if you have existing on-NAND data using this
++ format that you need to continue to support. New data written
++ also uses the older-style format. Note: Use of this option
++ generally requires that MTD's oob layout be adjusted to use the
++ older-style format. See notes on tags formats and MTD versions
++ in yaffs_mtdif1.c.
++
++ If unsure, say N.
++
++config YAFFS_DOES_ECC
++ bool "Lets Yaffs do its own ECC"
++ depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS
++ default n
++ help
++ This enables Yaffs to use its own ECC functions instead of using
++ the ones from the generic MTD-NAND driver.
++
++ If unsure, say N.
++
++config YAFFS_ECC_WRONG_ORDER
++ bool "Use the same ecc byte order as Steven Hill's nand_ecc.c"
++ depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS
++ default n
++ help
++ This makes yaffs_ecc.c use the same ecc byte order as Steven
++ Hill's nand_ecc.c. If not set, then you get the same ecc byte
++ order as SmartMedia.
++
++ If unsure, say N.
++
++config YAFFS_YAFFS2
++ bool "2048 byte (or larger) / page devices"
++ depends on YAFFS_FS
++ default y
++ help
++ Enable YAFFS2 support -- yaffs for >= 2K bytes per page devices
++
++ If unsure, say Y.
++
++config YAFFS_AUTO_YAFFS2
++ bool "Autoselect yaffs2 format"
++ depends on YAFFS_YAFFS2
++ default y
++ help
++ Without this, you need to explicitely use yaffs2 as the file
++ system type. With this, you can say "yaffs" and yaffs or yaffs2
++ will be used depending on the device page size (yaffs on
++ 512-byte page devices, yaffs2 on 2K page devices).
++
++ If unsure, say Y.
++
++config YAFFS_DISABLE_LAZY_LOAD
++ bool "Disable lazy loading"
++ depends on YAFFS_YAFFS2
++ default n
++ help
++ "Lazy loading" defers loading file details until they are
++ required. This saves mount time, but makes the first look-up
++ a bit longer.
++
++ Lazy loading will only happen if enabled by this option being 'n'
++ and if the appropriate tags are available, else yaffs2 will
++ automatically fall back to immediate loading and do the right
++ thing.
++
++ Lazy laoding will be required by checkpointing.
++
++ Setting this to 'y' will disable lazy loading.
++
++ If unsure, say N.
++
++
++config YAFFS_DISABLE_WIDE_TNODES
++ bool "Turn off wide tnodes"
++ depends on YAFFS_FS
++ default n
++ help
++ Wide tnodes are only used for NAND arrays >=32MB for 512-byte
++ page devices and >=128MB for 2k page devices. They use slightly
++ more RAM but are faster since they eliminate chunk group
++ searching.
++
++ Setting this to 'y' will force tnode width to 16 bits and save
++ memory but make large arrays slower.
++
++ If unsure, say N.
++
++config YAFFS_ALWAYS_CHECK_CHUNK_ERASED
++ bool "Force chunk erase check"
++ depends on YAFFS_FS
++ default n
++ help
++ Normally YAFFS only checks chunks before writing until an erased
++ chunk is found. This helps to detect any partially written
++ chunks that might have happened due to power loss.
++
++ Enabling this forces on the test that chunks are erased in flash
++ before writing to them. This takes more time but is potentially
++ a bit more secure.
++
++ Suggest setting Y during development and ironing out driver
++ issues etc. Suggest setting to N if you want faster writing.
++
++ If unsure, say Y.
++
++config YAFFS_SHORT_NAMES_IN_RAM
++ bool "Cache short names in RAM"
++ depends on YAFFS_FS
++ default y
++ help
++ If this config is set, then short names are stored with the
++ yaffs_Object. This costs an extra 16 bytes of RAM per object,
++ but makes look-ups faster.
++
++ If unsure, say Y.
+diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile
+new file mode 100644
+index 0000000..382ee61
+--- /dev/null
++++ b/fs/yaffs2/Makefile
+@@ -0,0 +1,10 @@
++#
++# Makefile for the linux YAFFS filesystem routines.
++#
++
++obj-$(CONFIG_YAFFS_FS) += yaffs.o
++
++yaffs-y := yaffs_ecc.o yaffs_fs.o yaffs_guts.o yaffs_checkptrw.o
++yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o yaffs_qsort.o
++yaffs-y += yaffs_tagscompat.o yaffs_tagsvalidity.o
++yaffs-y += yaffs_mtdif.o yaffs_mtdif1.o yaffs_mtdif2.o
+diff --git a/fs/yaffs2/devextras.h b/fs/yaffs2/devextras.h
+new file mode 100644
+index 0000000..a9366fd
+--- /dev/null
++++ b/fs/yaffs2/devextras.h
+@@ -0,0 +1,199 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++/*
++ * This file is just holds extra declarations of macros that would normally
++ * be providesd in the Linux kernel. These macros have been written from
++ * scratch but are functionally equivalent to the Linux ones.
++ *
++ */
++
++#ifndef __EXTRAS_H__
++#define __EXTRAS_H__
++
++
++#if !(defined __KERNEL__)
++
++/* Definition of types */
++typedef unsigned char __u8;
++typedef unsigned short __u16;
++typedef unsigned __u32;
++
++#endif
++
++/*
++ * This is a simple doubly linked list implementation that matches the
++ * way the Linux kernel doubly linked list implementation works.
++ */
++
++struct ylist_head {
++ struct ylist_head *next; /* next in chain */
++ struct ylist_head *prev; /* previous in chain */
++};
++
++
++/* Initialise a static list */
++#define YLIST_HEAD(name) \
++struct ylist_head name = { &(name),&(name)}
++
++
++
++/* Initialise a list head to an empty list */
++#define YINIT_LIST_HEAD(p) \
++do { \
++ (p)->next = (p);\
++ (p)->prev = (p); \
++} while(0)
++
++
++/* Add an element to a list */
++static __inline__ void ylist_add(struct ylist_head *newEntry,
++ struct ylist_head *list)
++{
++ struct ylist_head *listNext = list->next;
++
++ list->next = newEntry;
++ newEntry->prev = list;
++ newEntry->next = listNext;
++ listNext->prev = newEntry;
++
++}
++
++static __inline__ void ylist_add_tail(struct ylist_head *newEntry,
++ struct ylist_head *list)
++{
++ struct ylist_head *listPrev = list->prev;
++
++ list->prev = newEntry;
++ newEntry->next = list;
++ newEntry->prev = listPrev;
++ listPrev->next = newEntry;
++
++}
++
++
++/* Take an element out of its current list, with or without
++ * reinitialising the links.of the entry*/
++static __inline__ void ylist_del(struct ylist_head *entry)
++{
++ struct ylist_head *listNext = entry->next;
++ struct ylist_head *listPrev = entry->prev;
++
++ listNext->prev = listPrev;
++ listPrev->next = listNext;
++
++}
++
++static __inline__ void ylist_del_init(struct ylist_head *entry)
++{
++ ylist_del(entry);
++ entry->next = entry->prev = entry;
++}
++
++
++/* Test if the list is empty */
++static __inline__ int ylist_empty(struct ylist_head *entry)
++{
++ return (entry->next == entry);
++}
++
++
++/* ylist_entry takes a pointer to a list entry and offsets it to that
++ * we can find a pointer to the object it is embedded in.
++ */
++
++
++#define ylist_entry(entry, type, member) \
++ ((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member)))
++
++
++/* ylist_for_each and list_for_each_safe iterate over lists.
++ * ylist_for_each_safe uses temporary storage to make the list delete safe
++ */
++
++#define ylist_for_each(itervar, list) \
++ for (itervar = (list)->next; itervar != (list); itervar = itervar->next )
++
++#define ylist_for_each_safe(itervar,saveVar, list) \
++ for (itervar = (list)->next, saveVar = (list)->next->next; itervar != (list); \
++ itervar = saveVar, saveVar = saveVar->next)
++
++
++#if !(defined __KERNEL__)
++
++
++#ifndef WIN32
++#include <sys/stat.h>
++#endif
++
++
++#ifdef CONFIG_YAFFS_PROVIDE_DEFS
++/* File types */
++
++
++#define DT_UNKNOWN 0
++#define DT_FIFO 1
++#define DT_CHR 2
++#define DT_DIR 4
++#define DT_BLK 6
++#define DT_REG 8
++#define DT_LNK 10
++#define DT_SOCK 12
++#define DT_WHT 14
++
++
++#ifndef WIN32
++#include <sys/stat.h>
++#endif
++
++/*
++ * Attribute flags. These should be or-ed together to figure out what
++ * has been changed!
++ */
++#define ATTR_MODE 1
++#define ATTR_UID 2
++#define ATTR_GID 4
++#define ATTR_SIZE 8
++#define ATTR_ATIME 16
++#define ATTR_MTIME 32
++#define ATTR_CTIME 64
++
++struct iattr {
++ unsigned int ia_valid;
++ unsigned ia_mode;
++ unsigned ia_uid;
++ unsigned ia_gid;
++ unsigned ia_size;
++ unsigned ia_atime;
++ unsigned ia_mtime;
++ unsigned ia_ctime;
++ unsigned int ia_attr_flags;
++};
++
++#endif
++
++
++#define KERN_DEBUG
++
++#else
++
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/stat.h>
++
++#endif
++
++
++#endif
+diff --git a/fs/yaffs2/moduleconfig.h b/fs/yaffs2/moduleconfig.h
+new file mode 100644
+index 0000000..ac5af6f
+--- /dev/null
++++ b/fs/yaffs2/moduleconfig.h
+@@ -0,0 +1,65 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Martin Fouts <Martin.Fouts@palmsource.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_CONFIG_H__
++#define __YAFFS_CONFIG_H__
++
++#ifdef YAFFS_OUT_OF_TREE
++
++/* DO NOT UNSET THESE THREE. YAFFS2 will not compile if you do. */
++#define CONFIG_YAFFS_FS
++#define CONFIG_YAFFS_YAFFS1
++#define CONFIG_YAFFS_YAFFS2
++
++/* These options are independent of each other. Select those that matter. */
++
++/* Default: Not selected */
++/* Meaning: Yaffs does its own ECC, rather than using MTD ECC */
++//#define CONFIG_YAFFS_DOES_ECC
++
++/* Default: Not selected */
++/* Meaning: ECC byte order is 'wrong'. Only meaningful if */
++/* CONFIG_YAFFS_DOES_ECC is set */
++//#define CONFIG_YAFFS_ECC_WRONG_ORDER
++
++/* Default: Selected */
++/* Meaning: Disables testing whether chunks are erased before writing to them*/
++#define CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK
++
++/* Default: Selected */
++/* Meaning: Cache short names, taking more RAM, but faster look-ups */
++#define CONFIG_YAFFS_SHORT_NAMES_IN_RAM
++
++/* Default: 10 */
++/* Meaning: set the count of blocks to reserve for checkpointing */
++#define CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS 10
++
++/*
++Older-style on-NAND data format has a "pageStatus" byte to record
++chunk/page state. This byte is zeroed when the page is discarded.
++Choose this option if you have existing on-NAND data in this format
++that you need to continue to support. New data written also uses the
++older-style format.
++Note: Use of this option generally requires that MTD's oob layout be
++adjusted to use the older-style format. See notes on tags formats and
++MTD versions in yaffs_mtdif1.c.
++*/
++/* Default: Not selected */
++/* Meaning: Use older-style on-NAND data format with pageStatus byte */
++//#define CONFIG_YAFFS_9BYTE_TAGS
++
++#endif /* YAFFS_OUT_OF_TREE */
++
++#endif /* __YAFFS_CONFIG_H__ */
+diff --git a/fs/yaffs2/yaffs_checkptrw.c b/fs/yaffs2/yaffs_checkptrw.c
+new file mode 100644
+index 0000000..7cf3776
+--- /dev/null
++++ b/fs/yaffs2/yaffs_checkptrw.c
+@@ -0,0 +1,405 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++const char *yaffs_checkptrw_c_version =
++ "$Id: yaffs_checkptrw.c,v 1.17 2008/08/12 22:51:57 charles Exp $";
++
++
++#include "yaffs_checkptrw.h"
++#include "yaffs_getblockinfo.h"
++
++static int yaffs_CheckpointSpaceOk(yaffs_Device *dev)
++{
++
++ int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks;
++
++ T(YAFFS_TRACE_CHECKPOINT,
++ (TSTR("checkpt blocks available = %d" TENDSTR),
++ blocksAvailable));
++
++
++ return (blocksAvailable <= 0) ? 0 : 1;
++}
++
++
++static int yaffs_CheckpointErase(yaffs_Device *dev)
++{
++
++ int i;
++
++
++ if(!dev->eraseBlockInNAND)
++ return 0;
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checking blocks %d to %d"TENDSTR),
++ dev->internalStartBlock,dev->internalEndBlock));
++
++ for(i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i);
++ if(bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("erasing checkpt block %d"TENDSTR),i));
++ if(dev->eraseBlockInNAND(dev,i- dev->blockOffset /* realign */)){
++ bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
++ dev->nErasedBlocks++;
++ dev->nFreeChunks += dev->nChunksPerBlock;
++ }
++ else {
++ dev->markNANDBlockBad(dev,i);
++ bi->blockState = YAFFS_BLOCK_STATE_DEAD;
++ }
++ }
++ }
++
++ dev->blocksInCheckpoint = 0;
++
++ return 1;
++}
++
++
++static void yaffs_CheckpointFindNextErasedBlock(yaffs_Device *dev)
++{
++ int i;
++ int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks;
++ T(YAFFS_TRACE_CHECKPOINT,
++ (TSTR("allocating checkpt block: erased %d reserved %d avail %d next %d "TENDSTR),
++ dev->nErasedBlocks,dev->nReservedBlocks,blocksAvailable,dev->checkpointNextBlock));
++
++ if(dev->checkpointNextBlock >= 0 &&
++ dev->checkpointNextBlock <= dev->internalEndBlock &&
++ blocksAvailable > 0){
++
++ for(i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++){
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i);
++ if(bi->blockState == YAFFS_BLOCK_STATE_EMPTY){
++ dev->checkpointNextBlock = i + 1;
++ dev->checkpointCurrentBlock = i;
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("allocating checkpt block %d"TENDSTR),i));
++ return;
++ }
++ }
++ }
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("out of checkpt blocks"TENDSTR)));
++
++ dev->checkpointNextBlock = -1;
++ dev->checkpointCurrentBlock = -1;
++}
++
++static void yaffs_CheckpointFindNextCheckpointBlock(yaffs_Device *dev)
++{
++ int i;
++ yaffs_ExtendedTags tags;
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("find next checkpt block: start: blocks %d next %d" TENDSTR),
++ dev->blocksInCheckpoint, dev->checkpointNextBlock));
++
++ if(dev->blocksInCheckpoint < dev->checkpointMaxBlocks)
++ for(i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++){
++ int chunk = i * dev->nChunksPerBlock;
++ int realignedChunk = chunk - dev->chunkOffset;
++
++ dev->readChunkWithTagsFromNAND(dev,realignedChunk,NULL,&tags);
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("find next checkpt block: search: block %d oid %d seq %d eccr %d" TENDSTR),
++ i, tags.objectId,tags.sequenceNumber,tags.eccResult));
++
++ if(tags.sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA){
++ /* Right kind of block */
++ dev->checkpointNextBlock = tags.objectId;
++ dev->checkpointCurrentBlock = i;
++ dev->checkpointBlockList[dev->blocksInCheckpoint] = i;
++ dev->blocksInCheckpoint++;
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("found checkpt block %d"TENDSTR),i));
++ return;
++ }
++ }
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("found no more checkpt blocks"TENDSTR)));
++
++ dev->checkpointNextBlock = -1;
++ dev->checkpointCurrentBlock = -1;
++}
++
++
++int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting)
++{
++
++ /* Got the functions we need? */
++ if (!dev->writeChunkWithTagsToNAND ||
++ !dev->readChunkWithTagsFromNAND ||
++ !dev->eraseBlockInNAND ||
++ !dev->markNANDBlockBad)
++ return 0;
++
++ if(forWriting && !yaffs_CheckpointSpaceOk(dev))
++ return 0;
++
++ if(!dev->checkpointBuffer)
++ dev->checkpointBuffer = YMALLOC_DMA(dev->totalBytesPerChunk);
++ if(!dev->checkpointBuffer)
++ return 0;
++
++
++ dev->checkpointPageSequence = 0;
++
++ dev->checkpointOpenForWrite = forWriting;
++
++ dev->checkpointByteCount = 0;
++ dev->checkpointSum = 0;
++ dev->checkpointXor = 0;
++ dev->checkpointCurrentBlock = -1;
++ dev->checkpointCurrentChunk = -1;
++ dev->checkpointNextBlock = dev->internalStartBlock;
++
++ /* Erase all the blocks in the checkpoint area */
++ if(forWriting){
++ memset(dev->checkpointBuffer,0,dev->nDataBytesPerChunk);
++ dev->checkpointByteOffset = 0;
++ return yaffs_CheckpointErase(dev);
++
++
++ } else {
++ int i;
++ /* Set to a value that will kick off a read */
++ dev->checkpointByteOffset = dev->nDataBytesPerChunk;
++ /* A checkpoint block list of 1 checkpoint block per 16 block is (hopefully)
++ * going to be way more than we need */
++ dev->blocksInCheckpoint = 0;
++ dev->checkpointMaxBlocks = (dev->internalEndBlock - dev->internalStartBlock)/16 + 2;
++ dev->checkpointBlockList = YMALLOC(sizeof(int) * dev->checkpointMaxBlocks);
++ for(i = 0; i < dev->checkpointMaxBlocks; i++)
++ dev->checkpointBlockList[i] = -1;
++ }
++
++ return 1;
++}
++
++int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum)
++{
++ __u32 compositeSum;
++ compositeSum = (dev->checkpointSum << 8) | (dev->checkpointXor & 0xFF);
++ *sum = compositeSum;
++ return 1;
++}
++
++static int yaffs_CheckpointFlushBuffer(yaffs_Device *dev)
++{
++
++ int chunk;
++ int realignedChunk;
++
++ yaffs_ExtendedTags tags;
++
++ if(dev->checkpointCurrentBlock < 0){
++ yaffs_CheckpointFindNextErasedBlock(dev);
++ dev->checkpointCurrentChunk = 0;
++ }
++
++ if(dev->checkpointCurrentBlock < 0)
++ return 0;
++
++ tags.chunkDeleted = 0;
++ tags.objectId = dev->checkpointNextBlock; /* Hint to next place to look */
++ tags.chunkId = dev->checkpointPageSequence + 1;
++ tags.sequenceNumber = YAFFS_SEQUENCE_CHECKPOINT_DATA;
++ tags.byteCount = dev->nDataBytesPerChunk;
++ if(dev->checkpointCurrentChunk == 0){
++ /* First chunk we write for the block? Set block state to
++ checkpoint */
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,dev->checkpointCurrentBlock);
++ bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
++ dev->blocksInCheckpoint++;
++ }
++
++ chunk = dev->checkpointCurrentBlock * dev->nChunksPerBlock + dev->checkpointCurrentChunk;
++
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint wite buffer nand %d(%d:%d) objid %d chId %d" TENDSTR),
++ chunk, dev->checkpointCurrentBlock, dev->checkpointCurrentChunk,tags.objectId,tags.chunkId));
++
++ realignedChunk = chunk - dev->chunkOffset;
++
++ dev->writeChunkWithTagsToNAND(dev,realignedChunk,dev->checkpointBuffer,&tags);
++ dev->checkpointByteOffset = 0;
++ dev->checkpointPageSequence++;
++ dev->checkpointCurrentChunk++;
++ if(dev->checkpointCurrentChunk >= dev->nChunksPerBlock){
++ dev->checkpointCurrentChunk = 0;
++ dev->checkpointCurrentBlock = -1;
++ }
++ memset(dev->checkpointBuffer,0,dev->nDataBytesPerChunk);
++
++ return 1;
++}
++
++
++int yaffs_CheckpointWrite(yaffs_Device *dev,const void *data, int nBytes)
++{
++ int i=0;
++ int ok = 1;
++
++
++ __u8 * dataBytes = (__u8 *)data;
++
++
++
++ if(!dev->checkpointBuffer)
++ return 0;
++
++ if(!dev->checkpointOpenForWrite)
++ return -1;
++
++ while(i < nBytes && ok) {
++
++
++
++ dev->checkpointBuffer[dev->checkpointByteOffset] = *dataBytes ;
++ dev->checkpointSum += *dataBytes;
++ dev->checkpointXor ^= *dataBytes;
++
++ dev->checkpointByteOffset++;
++ i++;
++ dataBytes++;
++ dev->checkpointByteCount++;
++
++
++ if(dev->checkpointByteOffset < 0 ||
++ dev->checkpointByteOffset >= dev->nDataBytesPerChunk)
++ ok = yaffs_CheckpointFlushBuffer(dev);
++
++ }
++
++ return i;
++}
++
++int yaffs_CheckpointRead(yaffs_Device *dev, void *data, int nBytes)
++{
++ int i=0;
++ int ok = 1;
++ yaffs_ExtendedTags tags;
++
++
++ int chunk;
++ int realignedChunk;
++
++ __u8 *dataBytes = (__u8 *)data;
++
++ if(!dev->checkpointBuffer)
++ return 0;
++
++ if(dev->checkpointOpenForWrite)
++ return -1;
++
++ while(i < nBytes && ok) {
++
++
++ if(dev->checkpointByteOffset < 0 ||
++ dev->checkpointByteOffset >= dev->nDataBytesPerChunk) {
++
++ if(dev->checkpointCurrentBlock < 0){
++ yaffs_CheckpointFindNextCheckpointBlock(dev);
++ dev->checkpointCurrentChunk = 0;
++ }
++
++ if(dev->checkpointCurrentBlock < 0)
++ ok = 0;
++ else {
++
++ chunk = dev->checkpointCurrentBlock * dev->nChunksPerBlock +
++ dev->checkpointCurrentChunk;
++
++ realignedChunk = chunk - dev->chunkOffset;
++
++ /* read in the next chunk */
++ /* printf("read checkpoint page %d\n",dev->checkpointPage); */
++ dev->readChunkWithTagsFromNAND(dev, realignedChunk,
++ dev->checkpointBuffer,
++ &tags);
++
++ if(tags.chunkId != (dev->checkpointPageSequence + 1) ||
++ tags.eccResult > YAFFS_ECC_RESULT_FIXED ||
++ tags.sequenceNumber != YAFFS_SEQUENCE_CHECKPOINT_DATA)
++ ok = 0;
++
++ dev->checkpointByteOffset = 0;
++ dev->checkpointPageSequence++;
++ dev->checkpointCurrentChunk++;
++
++ if(dev->checkpointCurrentChunk >= dev->nChunksPerBlock)
++ dev->checkpointCurrentBlock = -1;
++ }
++ }
++
++ if(ok){
++ *dataBytes = dev->checkpointBuffer[dev->checkpointByteOffset];
++ dev->checkpointSum += *dataBytes;
++ dev->checkpointXor ^= *dataBytes;
++ dev->checkpointByteOffset++;
++ i++;
++ dataBytes++;
++ dev->checkpointByteCount++;
++ }
++ }
++
++ return i;
++}
++
++int yaffs_CheckpointClose(yaffs_Device *dev)
++{
++
++ if(dev->checkpointOpenForWrite){
++ if(dev->checkpointByteOffset != 0)
++ yaffs_CheckpointFlushBuffer(dev);
++ } else {
++ int i;
++ for(i = 0; i < dev->blocksInCheckpoint && dev->checkpointBlockList[i] >= 0; i++){
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,dev->checkpointBlockList[i]);
++ if(bi->blockState == YAFFS_BLOCK_STATE_EMPTY)
++ bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
++ else {
++ // Todo this looks odd...
++ }
++ }
++ YFREE(dev->checkpointBlockList);
++ dev->checkpointBlockList = NULL;
++ }
++
++ dev->nFreeChunks -= dev->blocksInCheckpoint * dev->nChunksPerBlock;
++ dev->nErasedBlocks -= dev->blocksInCheckpoint;
++
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint byte count %d" TENDSTR),
++ dev->checkpointByteCount));
++
++ if(dev->checkpointBuffer){
++ /* free the buffer */
++ YFREE(dev->checkpointBuffer);
++ dev->checkpointBuffer = NULL;
++ return 1;
++ }
++ else
++ return 0;
++
++}
++
++int yaffs_CheckpointInvalidateStream(yaffs_Device *dev)
++{
++ /* Erase the first checksum block */
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint invalidate"TENDSTR)));
++
++ if(!yaffs_CheckpointSpaceOk(dev))
++ return 0;
++
++ return yaffs_CheckpointErase(dev);
++}
++
++
++
+diff --git a/fs/yaffs2/yaffs_checkptrw.h b/fs/yaffs2/yaffs_checkptrw.h
+new file mode 100644
+index 0000000..d3ff174
+--- /dev/null
++++ b/fs/yaffs2/yaffs_checkptrw.h
+@@ -0,0 +1,35 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_CHECKPTRW_H__
++#define __YAFFS_CHECKPTRW_H__
++
++#include "yaffs_guts.h"
++
++int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting);
++
++int yaffs_CheckpointWrite(yaffs_Device *dev,const void *data, int nBytes);
++
++int yaffs_CheckpointRead(yaffs_Device *dev,void *data, int nBytes);
++
++int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum);
++
++int yaffs_CheckpointClose(yaffs_Device *dev);
++
++int yaffs_CheckpointInvalidateStream(yaffs_Device *dev);
++
++
++#endif
++
+diff --git a/fs/yaffs2/yaffs_ecc.c b/fs/yaffs2/yaffs_ecc.c
+new file mode 100644
+index 0000000..b099835
+--- /dev/null
++++ b/fs/yaffs2/yaffs_ecc.c
+@@ -0,0 +1,331 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/*
++ * This code implements the ECC algorithm used in SmartMedia.
++ *
++ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
++ * The two unused bit are set to 1.
++ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
++ * blocks are used on a 512-byte NAND page.
++ *
++ */
++
++/* Table generated by gen-ecc.c
++ * Using a table means we do not have to calculate p1..p4 and p1'..p4'
++ * for each byte of data. These are instead provided in a table in bits7..2.
++ * Bit 0 of each entry indicates whether the entry has an odd or even parity, and therefore
++ * this bytes influence on the line parity.
++ */
++
++const char *yaffs_ecc_c_version =
++ "$Id: yaffs_ecc.c,v 1.10 2007/12/13 15:35:17 wookey Exp $";
++
++#include "yportenv.h"
++
++#include "yaffs_ecc.h"
++
++static const unsigned char column_parity_table[] = {
++ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69,
++ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
++ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc,
++ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95,
++ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0,
++ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99,
++ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65,
++ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c,
++ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc,
++ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5,
++ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59,
++ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30,
++ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55,
++ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c,
++ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0,
++ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9,
++ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0,
++ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9,
++ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55,
++ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c,
++ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59,
++ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30,
++ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc,
++ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5,
++ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65,
++ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c,
++ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0,
++ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99,
++ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc,
++ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95,
++ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69,
++ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
++};
++
++/* Count the bits in an unsigned char or a U32 */
++
++static int yaffs_CountBits(unsigned char x)
++{
++ int r = 0;
++ while (x) {
++ if (x & 1)
++ r++;
++ x >>= 1;
++ }
++ return r;
++}
++
++static int yaffs_CountBits32(unsigned x)
++{
++ int r = 0;
++ while (x) {
++ if (x & 1)
++ r++;
++ x >>= 1;
++ }
++ return r;
++}
++
++/* Calculate the ECC for a 256-byte block of data */
++void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc)
++{
++ unsigned int i;
++
++ unsigned char col_parity = 0;
++ unsigned char line_parity = 0;
++ unsigned char line_parity_prime = 0;
++ unsigned char t;
++ unsigned char b;
++
++ for (i = 0; i < 256; i++) {
++ b = column_parity_table[*data++];
++ col_parity ^= b;
++
++ if (b & 0x01) // odd number of bits in the byte
++ {
++ line_parity ^= i;
++ line_parity_prime ^= ~i;
++ }
++
++ }
++
++ ecc[2] = (~col_parity) | 0x03;
++
++ t = 0;
++ if (line_parity & 0x80)
++ t |= 0x80;
++ if (line_parity_prime & 0x80)
++ t |= 0x40;
++ if (line_parity & 0x40)
++ t |= 0x20;
++ if (line_parity_prime & 0x40)
++ t |= 0x10;
++ if (line_parity & 0x20)
++ t |= 0x08;
++ if (line_parity_prime & 0x20)
++ t |= 0x04;
++ if (line_parity & 0x10)
++ t |= 0x02;
++ if (line_parity_prime & 0x10)
++ t |= 0x01;
++ ecc[1] = ~t;
++
++ t = 0;
++ if (line_parity & 0x08)
++ t |= 0x80;
++ if (line_parity_prime & 0x08)
++ t |= 0x40;
++ if (line_parity & 0x04)
++ t |= 0x20;
++ if (line_parity_prime & 0x04)
++ t |= 0x10;
++ if (line_parity & 0x02)
++ t |= 0x08;
++ if (line_parity_prime & 0x02)
++ t |= 0x04;
++ if (line_parity & 0x01)
++ t |= 0x02;
++ if (line_parity_prime & 0x01)
++ t |= 0x01;
++ ecc[0] = ~t;
++
++#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
++ // Swap the bytes into the wrong order
++ t = ecc[0];
++ ecc[0] = ecc[1];
++ ecc[1] = t;
++#endif
++}
++
++
++/* Correct the ECC on a 256 byte block of data */
++
++int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
++ const unsigned char *test_ecc)
++{
++ unsigned char d0, d1, d2; /* deltas */
++
++ d0 = read_ecc[0] ^ test_ecc[0];
++ d1 = read_ecc[1] ^ test_ecc[1];
++ d2 = read_ecc[2] ^ test_ecc[2];
++
++ if ((d0 | d1 | d2) == 0)
++ return 0; /* no error */
++
++ if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 &&
++ ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 &&
++ ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) {
++ /* Single bit (recoverable) error in data */
++
++ unsigned byte;
++ unsigned bit;
++
++#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
++ // swap the bytes to correct for the wrong order
++ unsigned char t;
++
++ t = d0;
++ d0 = d1;
++ d1 = t;
++#endif
++
++ bit = byte = 0;
++
++ if (d1 & 0x80)
++ byte |= 0x80;
++ if (d1 & 0x20)
++ byte |= 0x40;
++ if (d1 & 0x08)
++ byte |= 0x20;
++ if (d1 & 0x02)
++ byte |= 0x10;
++ if (d0 & 0x80)
++ byte |= 0x08;
++ if (d0 & 0x20)
++ byte |= 0x04;
++ if (d0 & 0x08)
++ byte |= 0x02;
++ if (d0 & 0x02)
++ byte |= 0x01;
++
++ if (d2 & 0x80)
++ bit |= 0x04;
++ if (d2 & 0x20)
++ bit |= 0x02;
++ if (d2 & 0x08)
++ bit |= 0x01;
++
++ data[byte] ^= (1 << bit);
++
++ return 1; /* Corrected the error */
++ }
++
++ if ((yaffs_CountBits(d0) +
++ yaffs_CountBits(d1) +
++ yaffs_CountBits(d2)) == 1) {
++ /* Reccoverable error in ecc */
++
++ read_ecc[0] = test_ecc[0];
++ read_ecc[1] = test_ecc[1];
++ read_ecc[2] = test_ecc[2];
++
++ return 1; /* Corrected the error */
++ }
++
++ /* Unrecoverable error */
++
++ return -1;
++
++}
++
++
++/*
++ * ECCxxxOther does ECC calcs on arbitrary n bytes of data
++ */
++void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
++ yaffs_ECCOther * eccOther)
++{
++ unsigned int i;
++
++ unsigned char col_parity = 0;
++ unsigned line_parity = 0;
++ unsigned line_parity_prime = 0;
++ unsigned char b;
++
++ for (i = 0; i < nBytes; i++) {
++ b = column_parity_table[*data++];
++ col_parity ^= b;
++
++ if (b & 0x01) {
++ /* odd number of bits in the byte */
++ line_parity ^= i;
++ line_parity_prime ^= ~i;
++ }
++
++ }
++
++ eccOther->colParity = (col_parity >> 2) & 0x3f;
++ eccOther->lineParity = line_parity;
++ eccOther->lineParityPrime = line_parity_prime;
++}
++
++int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
++ yaffs_ECCOther * read_ecc,
++ const yaffs_ECCOther * test_ecc)
++{
++ unsigned char cDelta; /* column parity delta */
++ unsigned lDelta; /* line parity delta */
++ unsigned lDeltaPrime; /* line parity delta */
++ unsigned bit;
++
++ cDelta = read_ecc->colParity ^ test_ecc->colParity;
++ lDelta = read_ecc->lineParity ^ test_ecc->lineParity;
++ lDeltaPrime = read_ecc->lineParityPrime ^ test_ecc->lineParityPrime;
++
++ if ((cDelta | lDelta | lDeltaPrime) == 0)
++ return 0; /* no error */
++
++ if (lDelta == ~lDeltaPrime &&
++ (((cDelta ^ (cDelta >> 1)) & 0x15) == 0x15))
++ {
++ /* Single bit (recoverable) error in data */
++
++ bit = 0;
++
++ if (cDelta & 0x20)
++ bit |= 0x04;
++ if (cDelta & 0x08)
++ bit |= 0x02;
++ if (cDelta & 0x02)
++ bit |= 0x01;
++
++ if(lDelta >= nBytes)
++ return -1;
++
++ data[lDelta] ^= (1 << bit);
++
++ return 1; /* corrected */
++ }
++
++ if ((yaffs_CountBits32(lDelta) + yaffs_CountBits32(lDeltaPrime) +
++ yaffs_CountBits(cDelta)) == 1) {
++ /* Reccoverable error in ecc */
++
++ *read_ecc = *test_ecc;
++ return 1; /* corrected */
++ }
++
++ /* Unrecoverable error */
++
++ return -1;
++
++}
++
+diff --git a/fs/yaffs2/yaffs_ecc.h b/fs/yaffs2/yaffs_ecc.h
+new file mode 100644
+index 0000000..79bc3d1
+--- /dev/null
++++ b/fs/yaffs2/yaffs_ecc.h
+@@ -0,0 +1,44 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++ /*
++ * This code implements the ECC algorithm used in SmartMedia.
++ *
++ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
++ * The two unused bit are set to 1.
++ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
++ * blocks are used on a 512-byte NAND page.
++ *
++ */
++
++#ifndef __YAFFS_ECC_H__
++#define __YAFFS_ECC_H__
++
++typedef struct {
++ unsigned char colParity;
++ unsigned lineParity;
++ unsigned lineParityPrime;
++} yaffs_ECCOther;
++
++void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc);
++int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
++ const unsigned char *test_ecc);
++
++void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
++ yaffs_ECCOther * ecc);
++int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
++ yaffs_ECCOther * read_ecc,
++ const yaffs_ECCOther * test_ecc);
++#endif
+diff --git a/fs/yaffs2/yaffs_fs.c b/fs/yaffs2/yaffs_fs.c
+new file mode 100644
+index 0000000..0c09033
+--- /dev/null
++++ b/fs/yaffs2/yaffs_fs.c
+@@ -0,0 +1,2393 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ * Acknowledgements:
++ * Luc van OostenRyck for numerous patches.
++ * Nick Bane for numerous patches.
++ * Nick Bane for 2.5/2.6 integration.
++ * Andras Toth for mknod rdev issue.
++ * Michael Fischer for finding the problem with inode inconsistency.
++ * Some code bodily lifted from JFFS
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/*
++ *
++ * This is the file system front-end to YAFFS that hooks it up to
++ * the VFS.
++ *
++ * Special notes:
++ * >> 2.4: sb->u.generic_sbp points to the yaffs_Device associated with
++ * this superblock
++ * >> 2.6: sb->s_fs_info points to the yaffs_Device associated with this
++ * superblock
++ * >> inode->u.generic_ip points to the associated yaffs_Object.
++ */
++
++const char *yaffs_fs_c_version =
++ "$Id: yaffs_fs.c,v 1.69 2008/08/28 02:42:11 charles Exp $";
++extern const char *yaffs_guts_c_version;
++
++#include <linux/version.h>
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
++#include <linux/config.h>
++#endif
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <linux/proc_fs.h>
++#include <linux/smp_lock.h>
++#include <linux/pagemap.h>
++#include <linux/mtd/mtd.h>
++#include <linux/interrupt.h>
++#include <linux/string.h>
++#include <linux/ctype.h>
++
++#include "asm/div64.h"
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++
++#include <linux/statfs.h> /* Added NCB 15-8-2003 */
++#include <asm/statfs.h>
++#define UnlockPage(p) unlock_page(p)
++#define Page_Uptodate(page) test_bit(PG_uptodate, &(page)->flags)
++
++/* FIXME: use sb->s_id instead ? */
++#define yaffs_devname(sb, buf) bdevname(sb->s_bdev, buf)
++
++#else
++
++#include <linux/locks.h>
++#define BDEVNAME_SIZE 0
++#define yaffs_devname(sb, buf) kdevname(sb->s_dev)
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
++/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */
++#define __user
++#endif
++
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
++#define YPROC_ROOT &proc_root
++#else
++#define YPROC_ROOT NULL
++#endif
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++#define WRITE_SIZE_STR "writesize"
++#define WRITE_SIZE(mtd) (mtd)->writesize
++#else
++#define WRITE_SIZE_STR "oobblock"
++#define WRITE_SIZE(mtd) (mtd)->oobblock
++#endif
++
++#include <asm/uaccess.h>
++
++#include "yportenv.h"
++#include "yaffs_guts.h"
++
++#include <linux/mtd/mtd.h>
++#include "yaffs_mtdif.h"
++#include "yaffs_mtdif1.h"
++#include "yaffs_mtdif2.h"
++
++unsigned int yaffs_traceMask = YAFFS_TRACE_BAD_BLOCKS;
++unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS;
++
++/* Module Parameters */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++module_param(yaffs_traceMask,uint,0644);
++module_param(yaffs_wr_attempts,uint,0644);
++#else
++MODULE_PARM(yaffs_traceMask,"i");
++MODULE_PARM(yaffs_wr_attempts,"i");
++#endif
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25))
++/* use iget and read_inode */
++#define Y_IGET(sb,inum) iget((sb),(inum))
++static void yaffs_read_inode(struct inode *inode);
++
++#else
++/* Call local equivalent */
++#define YAFFS_USE_OWN_IGET
++#define Y_IGET(sb,inum) yaffs_iget((sb),(inum))
++
++static struct inode * yaffs_iget(struct super_block *sb, unsigned long ino);
++#endif
++
++/*#define T(x) printk x */
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
++#define yaffs_InodeToObjectLV(iptr) (iptr)->i_private
++#else
++#define yaffs_InodeToObjectLV(iptr) (iptr)->u.generic_ip
++#endif
++
++#define yaffs_InodeToObject(iptr) ((yaffs_Object *)(yaffs_InodeToObjectLV(iptr)))
++#define yaffs_DentryToObject(dptr) yaffs_InodeToObject((dptr)->d_inode)
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++#define yaffs_SuperToDevice(sb) ((yaffs_Device *)sb->s_fs_info)
++#else
++#define yaffs_SuperToDevice(sb) ((yaffs_Device *)sb->u.generic_sbp)
++#endif
++
++static void yaffs_put_super(struct super_block *sb);
++
++static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n,
++ loff_t * pos);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs_file_flush(struct file *file, fl_owner_t id);
++#else
++static int yaffs_file_flush(struct file *file);
++#endif
++
++static int yaffs_sync_object(struct file *file, struct dentry *dentry,
++ int datasync);
++
++static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *n);
++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry,
++ struct nameidata *n);
++#else
++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode);
++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry);
++#endif
++static int yaffs_link(struct dentry *old_dentry, struct inode *dir,
++ struct dentry *dentry);
++static int yaffs_unlink(struct inode *dir, struct dentry *dentry);
++static int yaffs_symlink(struct inode *dir, struct dentry *dentry,
++ const char *symname);
++static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
++ dev_t dev);
++#else
++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
++ int dev);
++#endif
++static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry,
++ struct inode *new_dir, struct dentry *new_dentry);
++static int yaffs_setattr(struct dentry *dentry, struct iattr *attr);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs_sync_fs(struct super_block *sb, int wait);
++static void yaffs_write_super(struct super_block *sb);
++#else
++static int yaffs_sync_fs(struct super_block *sb);
++static int yaffs_write_super(struct super_block *sb);
++#endif
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf);
++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf);
++#else
++static int yaffs_statfs(struct super_block *sb, struct statfs *buf);
++#endif
++
++#ifdef YAFFS_HAS_PUT_INODE
++static void yaffs_put_inode(struct inode *inode);
++#endif
++
++static void yaffs_delete_inode(struct inode *);
++static void yaffs_clear_inode(struct inode *);
++
++static int yaffs_readpage(struct file *file, struct page *page);
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_writepage(struct page *page, struct writeback_control *wbc);
++#else
++static int yaffs_writepage(struct page *page);
++#endif
++static int yaffs_prepare_write(struct file *f, struct page *pg,
++ unsigned offset, unsigned to);
++static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset,
++ unsigned to);
++
++static int yaffs_readlink(struct dentry *dentry, char __user * buffer,
++ int buflen);
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13))
++static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd);
++#else
++static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd);
++#endif
++
++static struct address_space_operations yaffs_file_address_operations = {
++ .readpage = yaffs_readpage,
++ .writepage = yaffs_writepage,
++ .prepare_write = yaffs_prepare_write,
++ .commit_write = yaffs_commit_write,
++};
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22))
++static struct file_operations yaffs_file_operations = {
++ .read = do_sync_read,
++ .write = do_sync_write,
++ .aio_read = generic_file_aio_read,
++ .aio_write = generic_file_aio_write,
++ .mmap = generic_file_mmap,
++ .flush = yaffs_file_flush,
++ .fsync = yaffs_sync_object,
++ .splice_read = generic_file_splice_read,
++ .splice_write = generic_file_splice_write,
++};
++
++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
++
++static struct file_operations yaffs_file_operations = {
++ .read = do_sync_read,
++ .write = do_sync_write,
++ .aio_read = generic_file_aio_read,
++ .aio_write = generic_file_aio_write,
++ .mmap = generic_file_mmap,
++ .flush = yaffs_file_flush,
++ .fsync = yaffs_sync_object,
++ .sendfile = generic_file_sendfile,
++};
++
++#else
++
++static struct file_operations yaffs_file_operations = {
++ .read = generic_file_read,
++ .write = generic_file_write,
++ .mmap = generic_file_mmap,
++ .flush = yaffs_file_flush,
++ .fsync = yaffs_sync_object,
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++ .sendfile = generic_file_sendfile,
++#endif
++};
++#endif
++
++static struct inode_operations yaffs_file_inode_operations = {
++ .setattr = yaffs_setattr,
++};
++
++static struct inode_operations yaffs_symlink_inode_operations = {
++ .readlink = yaffs_readlink,
++ .follow_link = yaffs_follow_link,
++ .setattr = yaffs_setattr,
++};
++
++static struct inode_operations yaffs_dir_inode_operations = {
++ .create = yaffs_create,
++ .lookup = yaffs_lookup,
++ .link = yaffs_link,
++ .unlink = yaffs_unlink,
++ .symlink = yaffs_symlink,
++ .mkdir = yaffs_mkdir,
++ .rmdir = yaffs_unlink,
++ .mknod = yaffs_mknod,
++ .rename = yaffs_rename,
++ .setattr = yaffs_setattr,
++};
++
++static struct file_operations yaffs_dir_operations = {
++ .read = generic_read_dir,
++ .readdir = yaffs_readdir,
++ .fsync = yaffs_sync_object,
++};
++
++static struct super_operations yaffs_super_ops = {
++ .statfs = yaffs_statfs,
++
++#ifndef YAFFS_USE_OWN_IGET
++ .read_inode = yaffs_read_inode,
++#endif
++#ifdef YAFFS_HAS_PUT_INODE
++ .put_inode = yaffs_put_inode,
++#endif
++ .put_super = yaffs_put_super,
++ .delete_inode = yaffs_delete_inode,
++ .clear_inode = yaffs_clear_inode,
++ .sync_fs = yaffs_sync_fs,
++ .write_super = yaffs_write_super,
++};
++
++static void yaffs_GrossLock(yaffs_Device * dev)
++{
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs locking\n"));
++
++ down(&dev->grossLock);
++}
++
++static void yaffs_GrossUnlock(yaffs_Device * dev)
++{
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs unlocking\n"));
++ up(&dev->grossLock);
++
++}
++
++static int yaffs_readlink(struct dentry *dentry, char __user * buffer,
++ int buflen)
++{
++ unsigned char *alias;
++ int ret;
++
++ yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
++
++ yaffs_GrossLock(dev);
++
++ alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry));
++
++ yaffs_GrossUnlock(dev);
++
++ if (!alias)
++ return -ENOMEM;
++
++ ret = vfs_readlink(dentry, buffer, buflen, alias);
++ kfree(alias);
++ return ret;
++}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13))
++static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd)
++#else
++static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd)
++#endif
++{
++ unsigned char *alias;
++ int ret;
++ yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
++
++ yaffs_GrossLock(dev);
++
++ alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry));
++
++ yaffs_GrossUnlock(dev);
++
++ if (!alias)
++ {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ ret = vfs_follow_link(nd, alias);
++ kfree(alias);
++out:
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13))
++ return ERR_PTR (ret);
++#else
++ return ret;
++#endif
++}
++
++struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev,
++ yaffs_Object * obj);
++
++/*
++ * Lookup is used to find objects in the fs
++ */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++
++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry,
++ struct nameidata *n)
++#else
++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry)
++#endif
++{
++ yaffs_Object *obj;
++ struct inode *inode = NULL; /* NCB 2.5/2.6 needs NULL here */
++
++ yaffs_Device *dev = yaffs_InodeToObject(dir)->myDev;
++
++ yaffs_GrossLock(dev);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_lookup for %d:%s\n",
++ yaffs_InodeToObject(dir)->objectId, dentry->d_name.name));
++
++ obj =
++ yaffs_FindObjectByName(yaffs_InodeToObject(dir),
++ dentry->d_name.name);
++
++ obj = yaffs_GetEquivalentObject(obj); /* in case it was a hardlink */
++
++ /* Can't hold gross lock when calling yaffs_get_inode() */
++ yaffs_GrossUnlock(dev);
++
++ if (obj) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_lookup found %d\n", obj->objectId));
++
++ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj);
++
++ if (inode) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_loookup dentry \n"));
++/* #if 0 asserted by NCB for 2.5/6 compatability - falls through to
++ * d_add even if NULL inode */
++#if 0
++ /*dget(dentry); // try to solve directory bug */
++ d_add(dentry, inode);
++
++ /* return dentry; */
++ return NULL;
++#endif
++ }
++
++ } else {
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_lookup not found\n"));
++
++ }
++
++/* added NCB for 2.5/6 compatability - forces add even if inode is
++ * NULL which creates dentry hash */
++ d_add(dentry, inode);
++
++ return NULL;
++ /* return (ERR_PTR(-EIO)); */
++
++}
++
++
++#ifdef YAFFS_HAS_PUT_INODE
++
++/* For now put inode is just for debugging
++ * Put inode is called when the inode **structure** is put.
++ */
++static void yaffs_put_inode(struct inode *inode)
++{
++ T(YAFFS_TRACE_OS,
++ ("yaffs_put_inode: ino %d, count %d\n", (int)inode->i_ino,
++ atomic_read(&inode->i_count)));
++
++}
++#endif
++
++/* clear is called to tell the fs to release any per-inode data it holds */
++static void yaffs_clear_inode(struct inode *inode)
++{
++ yaffs_Object *obj;
++ yaffs_Device *dev;
++
++ obj = yaffs_InodeToObject(inode);
++
++ T(YAFFS_TRACE_OS,
++ ("yaffs_clear_inode: ino %d, count %d %s\n", (int)inode->i_ino,
++ atomic_read(&inode->i_count),
++ obj ? "object exists" : "null object"));
++
++ if (obj) {
++ dev = obj->myDev;
++ yaffs_GrossLock(dev);
++
++ /* Clear the association between the inode and
++ * the yaffs_Object.
++ */
++ obj->myInode = NULL;
++ yaffs_InodeToObjectLV(inode) = NULL;
++
++ /* If the object freeing was deferred, then the real
++ * free happens now.
++ * This should fix the inode inconsistency problem.
++ */
++
++ yaffs_HandleDeferedFree(obj);
++
++ yaffs_GrossUnlock(dev);
++ }
++
++}
++
++/* delete is called when the link count is zero and the inode
++ * is put (ie. nobody wants to know about it anymore, time to
++ * delete the file).
++ * NB Must call clear_inode()
++ */
++static void yaffs_delete_inode(struct inode *inode)
++{
++ yaffs_Object *obj = yaffs_InodeToObject(inode);
++ yaffs_Device *dev;
++
++ T(YAFFS_TRACE_OS,
++ ("yaffs_delete_inode: ino %d, count %d %s\n", (int)inode->i_ino,
++ atomic_read(&inode->i_count),
++ obj ? "object exists" : "null object"));
++
++ if (obj) {
++ dev = obj->myDev;
++ yaffs_GrossLock(dev);
++ yaffs_DeleteFile(obj);
++ yaffs_GrossUnlock(dev);
++ }
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13))
++ truncate_inode_pages (&inode->i_data, 0);
++#endif
++ clear_inode(inode);
++}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs_file_flush(struct file *file, fl_owner_t id)
++#else
++static int yaffs_file_flush(struct file *file)
++#endif
++{
++ yaffs_Object *obj = yaffs_DentryToObject(file->f_dentry);
++
++ yaffs_Device *dev = obj->myDev;
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_file_flush object %d (%s)\n", obj->objectId,
++ obj->dirty ? "dirty" : "clean"));
++
++ yaffs_GrossLock(dev);
++
++ yaffs_FlushFile(obj, 1);
++
++ yaffs_GrossUnlock(dev);
++
++ return 0;
++}
++
++static int yaffs_readpage_nolock(struct file *f, struct page *pg)
++{
++ /* Lifted from jffs2 */
++
++ yaffs_Object *obj;
++ unsigned char *pg_buf;
++ int ret;
++
++ yaffs_Device *dev;
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_readpage at %08x, size %08x\n",
++ (unsigned)(pg->index << PAGE_CACHE_SHIFT),
++ (unsigned)PAGE_CACHE_SIZE));
++
++ obj = yaffs_DentryToObject(f->f_dentry);
++
++ dev = obj->myDev;
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++ BUG_ON(!PageLocked(pg));
++#else
++ if (!PageLocked(pg))
++ PAGE_BUG(pg);
++#endif
++
++ pg_buf = kmap(pg);
++ /* FIXME: Can kmap fail? */
++
++ yaffs_GrossLock(dev);
++
++ ret =
++ yaffs_ReadDataFromFile(obj, pg_buf, pg->index << PAGE_CACHE_SHIFT,
++ PAGE_CACHE_SIZE);
++
++ yaffs_GrossUnlock(dev);
++
++ if (ret >= 0)
++ ret = 0;
++
++ if (ret) {
++ ClearPageUptodate(pg);
++ SetPageError(pg);
++ } else {
++ SetPageUptodate(pg);
++ ClearPageError(pg);
++ }
++
++ flush_dcache_page(pg);
++ kunmap(pg);
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_readpage done\n"));
++ return ret;
++}
++
++static int yaffs_readpage_unlock(struct file *f, struct page *pg)
++{
++ int ret = yaffs_readpage_nolock(f, pg);
++ UnlockPage(pg);
++ return ret;
++}
++
++static int yaffs_readpage(struct file *f, struct page *pg)
++{
++ return yaffs_readpage_unlock(f, pg);
++}
++
++/* writepage inspired by/stolen from smbfs */
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_writepage(struct page *page, struct writeback_control *wbc)
++#else
++static int yaffs_writepage(struct page *page)
++#endif
++{
++ struct address_space *mapping = page->mapping;
++ loff_t offset = (loff_t) page->index << PAGE_CACHE_SHIFT;
++ struct inode *inode;
++ unsigned long end_index;
++ char *buffer;
++ yaffs_Object *obj;
++ int nWritten = 0;
++ unsigned nBytes;
++
++ if (!mapping)
++ BUG();
++ inode = mapping->host;
++ if (!inode)
++ BUG();
++
++ if (offset > inode->i_size) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG
++ "yaffs_writepage at %08x, inode size = %08x!!!\n",
++ (unsigned)(page->index << PAGE_CACHE_SHIFT),
++ (unsigned)inode->i_size));
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG " -> don't care!!\n"));
++ unlock_page(page);
++ return 0;
++ }
++
++ end_index = inode->i_size >> PAGE_CACHE_SHIFT;
++
++ /* easy case */
++ if (page->index < end_index) {
++ nBytes = PAGE_CACHE_SIZE;
++ } else {
++ nBytes = inode->i_size & (PAGE_CACHE_SIZE - 1);
++ }
++
++ get_page(page);
++
++ buffer = kmap(page);
++
++ obj = yaffs_InodeToObject(inode);
++ yaffs_GrossLock(obj->myDev);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_writepage at %08x, size %08x\n",
++ (unsigned)(page->index << PAGE_CACHE_SHIFT), nBytes));
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "writepag0: obj = %05x, ino = %05x\n",
++ (int)obj->variant.fileVariant.fileSize, (int)inode->i_size));
++
++ nWritten =
++ yaffs_WriteDataToFile(obj, buffer, page->index << PAGE_CACHE_SHIFT,
++ nBytes, 0);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "writepag1: obj = %05x, ino = %05x\n",
++ (int)obj->variant.fileVariant.fileSize, (int)inode->i_size));
++
++ yaffs_GrossUnlock(obj->myDev);
++
++ kunmap(page);
++ SetPageUptodate(page);
++ UnlockPage(page);
++ put_page(page);
++
++ return (nWritten == nBytes) ? 0 : -ENOSPC;
++}
++
++static int yaffs_prepare_write(struct file *f, struct page *pg,
++ unsigned offset, unsigned to)
++{
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_prepair_write\n"));
++ if (!Page_Uptodate(pg) && (offset || to < PAGE_CACHE_SIZE))
++ return yaffs_readpage_nolock(f, pg);
++
++ return 0;
++
++}
++
++static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset,
++ unsigned to)
++{
++
++ void *addr, *kva;
++
++ loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset;
++ int nBytes = to - offset;
++ int nWritten;
++
++ unsigned spos = pos;
++ unsigned saddr = (unsigned)addr;
++
++ kva=kmap(pg);
++ addr = kva + offset;
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_commit_write addr %x pos %x nBytes %d\n", saddr,
++ spos, nBytes));
++
++ nWritten = yaffs_file_write(f, addr, nBytes, &pos);
++
++ if (nWritten != nBytes) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG
++ "yaffs_commit_write not same size nWritten %d nBytes %d\n",
++ nWritten, nBytes));
++ SetPageError(pg);
++ ClearPageUptodate(pg);
++ } else {
++ SetPageUptodate(pg);
++ }
++
++ kunmap(pg);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_commit_write returning %d\n",
++ nWritten == nBytes ? 0 : nWritten));
++
++ return nWritten == nBytes ? 0 : nWritten;
++
++}
++
++static void yaffs_FillInodeFromObject(struct inode *inode, yaffs_Object * obj)
++{
++ if (inode && obj) {
++
++
++ /* Check mode against the variant type and attempt to repair if broken. */
++ __u32 mode = obj->yst_mode;
++ switch( obj->variantType ){
++ case YAFFS_OBJECT_TYPE_FILE :
++ if( ! S_ISREG(mode) ){
++ obj->yst_mode &= ~S_IFMT;
++ obj->yst_mode |= S_IFREG;
++ }
++
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK :
++ if( ! S_ISLNK(mode) ){
++ obj->yst_mode &= ~S_IFMT;
++ obj->yst_mode |= S_IFLNK;
++ }
++
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY :
++ if( ! S_ISDIR(mode) ){
++ obj->yst_mode &= ~S_IFMT;
++ obj->yst_mode |= S_IFDIR;
++ }
++
++ break;
++ case YAFFS_OBJECT_TYPE_UNKNOWN :
++ case YAFFS_OBJECT_TYPE_HARDLINK :
++ case YAFFS_OBJECT_TYPE_SPECIAL :
++ default:
++ /* TODO? */
++ break;
++ }
++
++ inode->i_flags |= S_NOATIME;
++
++ inode->i_ino = obj->objectId;
++ inode->i_mode = obj->yst_mode;
++ inode->i_uid = obj->yst_uid;
++ inode->i_gid = obj->yst_gid;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
++ inode->i_blksize = inode->i_sb->s_blocksize;
++#endif
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++
++ inode->i_rdev = old_decode_dev(obj->yst_rdev);
++ inode->i_atime.tv_sec = (time_t) (obj->yst_atime);
++ inode->i_atime.tv_nsec = 0;
++ inode->i_mtime.tv_sec = (time_t) obj->yst_mtime;
++ inode->i_mtime.tv_nsec = 0;
++ inode->i_ctime.tv_sec = (time_t) obj->yst_ctime;
++ inode->i_ctime.tv_nsec = 0;
++#else
++ inode->i_rdev = obj->yst_rdev;
++ inode->i_atime = obj->yst_atime;
++ inode->i_mtime = obj->yst_mtime;
++ inode->i_ctime = obj->yst_ctime;
++#endif
++ inode->i_size = yaffs_GetObjectFileLength(obj);
++ inode->i_blocks = (inode->i_size + 511) >> 9;
++
++ inode->i_nlink = yaffs_GetObjectLinkCount(obj);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG
++ "yaffs_FillInode mode %x uid %d gid %d size %d count %d\n",
++ inode->i_mode, inode->i_uid, inode->i_gid,
++ (int)inode->i_size, atomic_read(&inode->i_count)));
++
++ switch (obj->yst_mode & S_IFMT) {
++ default: /* fifo, device or socket */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++ init_special_inode(inode, obj->yst_mode,
++ old_decode_dev(obj->yst_rdev));
++#else
++ init_special_inode(inode, obj->yst_mode,
++ (dev_t) (obj->yst_rdev));
++#endif
++ break;
++ case S_IFREG: /* file */
++ inode->i_op = &yaffs_file_inode_operations;
++ inode->i_fop = &yaffs_file_operations;
++ inode->i_mapping->a_ops =
++ &yaffs_file_address_operations;
++ break;
++ case S_IFDIR: /* directory */
++ inode->i_op = &yaffs_dir_inode_operations;
++ inode->i_fop = &yaffs_dir_operations;
++ break;
++ case S_IFLNK: /* symlink */
++ inode->i_op = &yaffs_symlink_inode_operations;
++ break;
++ }
++
++ yaffs_InodeToObjectLV(inode) = obj;
++
++ obj->myInode = inode;
++
++ } else {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_FileInode invalid parameters\n"));
++ }
++
++}
++
++struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev,
++ yaffs_Object * obj)
++{
++ struct inode *inode;
++
++ if (!sb) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_get_inode for NULL super_block!!\n"));
++ return NULL;
++
++ }
++
++ if (!obj) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_get_inode for NULL object!!\n"));
++ return NULL;
++
++ }
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_get_inode for object %d\n", obj->objectId));
++
++ inode = Y_IGET(sb, obj->objectId);
++ if(IS_ERR(inode))
++ return NULL;
++
++ /* NB Side effect: iget calls back to yaffs_read_inode(). */
++ /* iget also increments the inode's i_count */
++ /* NB You can't be holding grossLock or deadlock will happen! */
++
++ return inode;
++}
++
++static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n,
++ loff_t * pos)
++{
++ yaffs_Object *obj;
++ int nWritten, ipos;
++ struct inode *inode;
++ yaffs_Device *dev;
++
++ obj = yaffs_DentryToObject(f->f_dentry);
++
++ dev = obj->myDev;
++
++ yaffs_GrossLock(dev);
++
++ inode = f->f_dentry->d_inode;
++
++ if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) {
++ ipos = inode->i_size;
++ } else {
++ ipos = *pos;
++ }
++
++ if (!obj) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_file_write: hey obj is null!\n"));
++ } else {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG
++ "yaffs_file_write about to write writing %d bytes"
++ "to object %d at %d\n",
++ n, obj->objectId, ipos));
++ }
++
++ nWritten = yaffs_WriteDataToFile(obj, buf, ipos, n, 0);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_file_write writing %d bytes, %d written at %d\n",
++ n, nWritten, ipos));
++ if (nWritten > 0) {
++ ipos += nWritten;
++ *pos = ipos;
++ if (ipos > inode->i_size) {
++ inode->i_size = ipos;
++ inode->i_blocks = (ipos + 511) >> 9;
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG
++ "yaffs_file_write size updated to %d bytes, "
++ "%d blocks\n",
++ ipos, (int)(inode->i_blocks)));
++ }
++
++ }
++ yaffs_GrossUnlock(dev);
++ return nWritten == 0 ? -ENOSPC : nWritten;
++}
++
++static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir)
++{
++ yaffs_Object *obj;
++ yaffs_Device *dev;
++ struct inode *inode = f->f_dentry->d_inode;
++ unsigned long offset, curoffs;
++ struct ylist_head *i;
++ yaffs_Object *l;
++
++ char name[YAFFS_MAX_NAME_LENGTH + 1];
++
++ obj = yaffs_DentryToObject(f->f_dentry);
++ dev = obj->myDev;
++
++ yaffs_GrossLock(dev);
++
++ offset = f->f_pos;
++
++ T(YAFFS_TRACE_OS, ("yaffs_readdir: starting at %d\n", (int)offset));
++
++ if (offset == 0) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_readdir: entry . ino %d \n",
++ (int)inode->i_ino));
++ if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR)
++ < 0) {
++ goto out;
++ }
++ offset++;
++ f->f_pos++;
++ }
++ if (offset == 1) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_readdir: entry .. ino %d \n",
++ (int)f->f_dentry->d_parent->d_inode->i_ino));
++ if (filldir
++ (dirent, "..", 2, offset,
++ f->f_dentry->d_parent->d_inode->i_ino, DT_DIR) < 0) {
++ goto out;
++ }
++ offset++;
++ f->f_pos++;
++ }
++
++ curoffs = 1;
++
++ /* If the directory has changed since the open or last call to
++ readdir, rewind to after the 2 canned entries. */
++
++ if (f->f_version != inode->i_version) {
++ offset = 2;
++ f->f_pos = offset;
++ f->f_version = inode->i_version;
++ }
++
++ ylist_for_each(i, &obj->variant.directoryVariant.children) {
++ curoffs++;
++ if (curoffs >= offset) {
++ l = ylist_entry(i, yaffs_Object, siblings);
++
++ yaffs_GetObjectName(l, name,
++ YAFFS_MAX_NAME_LENGTH + 1);
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_readdir: %s inode %d\n", name,
++ yaffs_GetObjectInode(l)));
++
++ if (filldir(dirent,
++ name,
++ strlen(name),
++ offset,
++ yaffs_GetObjectInode(l),
++ yaffs_GetObjectType(l))
++ < 0) {
++ goto up_and_out;
++ }
++
++ offset++;
++ f->f_pos++;
++ }
++ }
++
++ up_and_out:
++ out:
++
++ yaffs_GrossUnlock(dev);
++
++ return 0;
++}
++
++/*
++ * File creation. Allocate an inode, and we're done..
++ */
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
++ dev_t rdev)
++#else
++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
++ int rdev)
++#endif
++{
++ struct inode *inode;
++
++ yaffs_Object *obj = NULL;
++ yaffs_Device *dev;
++
++ yaffs_Object *parent = yaffs_InodeToObject(dir);
++
++ int error = -ENOSPC;
++ uid_t uid = current->fsuid;
++ gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : current->fsgid;
++
++ if((dir->i_mode & S_ISGID) && S_ISDIR(mode))
++ mode |= S_ISGID;
++
++ if (parent) {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_mknod: parent object %d type %d\n",
++ parent->objectId, parent->variantType));
++ } else {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_mknod: could not get parent object\n"));
++ return -EPERM;
++ }
++
++ T(YAFFS_TRACE_OS, ("yaffs_mknod: making oject for %s, "
++ "mode %x dev %x\n",
++ dentry->d_name.name, mode, rdev));
++
++ dev = parent->myDev;
++
++ yaffs_GrossLock(dev);
++
++ switch (mode & S_IFMT) {
++ default:
++ /* Special (socket, fifo, device...) */
++ T(YAFFS_TRACE_OS, (KERN_DEBUG
++ "yaffs_mknod: making special\n"));
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++ obj =
++ yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid,
++ gid, old_encode_dev(rdev));
++#else
++ obj =
++ yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid,
++ gid, rdev);
++#endif
++ break;
++ case S_IFREG: /* file */
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_mknod: making file\n"));
++ obj =
++ yaffs_MknodFile(parent, dentry->d_name.name, mode, uid,
++ gid);
++ break;
++ case S_IFDIR: /* directory */
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_mknod: making directory\n"));
++ obj =
++ yaffs_MknodDirectory(parent, dentry->d_name.name, mode,
++ uid, gid);
++ break;
++ case S_IFLNK: /* symlink */
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_mknod: making file\n"));
++ obj = NULL; /* Do we ever get here? */
++ break;
++ }
++
++ /* Can not call yaffs_get_inode() with gross lock held */
++ yaffs_GrossUnlock(dev);
++
++ if (obj) {
++ inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj);
++ d_instantiate(dentry, inode);
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_mknod created object %d count = %d\n",
++ obj->objectId, atomic_read(&inode->i_count)));
++ error = 0;
++ } else {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_mknod failed making object\n"));
++ error = -ENOMEM;
++ }
++
++ return error;
++}
++
++static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
++{
++ int retVal;
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_mkdir\n"));
++ retVal = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0);
++#if 0
++ /* attempt to fix dir bug - didn't work */
++ if (!retVal) {
++ dget(dentry);
++ }
++#endif
++ return retVal;
++}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode,
++ struct nameidata *n)
++#else
++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode)
++#endif
++{
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_create\n"));
++ return yaffs_mknod(dir, dentry, mode | S_IFREG, 0);
++}
++
++static int yaffs_unlink(struct inode *dir, struct dentry *dentry)
++{
++ int retVal;
++
++ yaffs_Device *dev;
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_unlink %d:%s\n", (int)(dir->i_ino),
++ dentry->d_name.name));
++
++ dev = yaffs_InodeToObject(dir)->myDev;
++
++ yaffs_GrossLock(dev);
++
++ retVal = yaffs_Unlink(yaffs_InodeToObject(dir), dentry->d_name.name);
++
++ if (retVal == YAFFS_OK) {
++ dentry->d_inode->i_nlink--;
++ dir->i_version++;
++ yaffs_GrossUnlock(dev);
++ mark_inode_dirty(dentry->d_inode);
++ return 0;
++ }
++ yaffs_GrossUnlock(dev);
++ return -ENOTEMPTY;
++}
++
++/*
++ * Create a link...
++ */
++static int yaffs_link(struct dentry *old_dentry, struct inode *dir,
++ struct dentry *dentry)
++{
++ struct inode *inode = old_dentry->d_inode;
++ yaffs_Object *obj = NULL;
++ yaffs_Object *link = NULL;
++ yaffs_Device *dev;
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_link\n"));
++
++ obj = yaffs_InodeToObject(inode);
++ dev = obj->myDev;
++
++ yaffs_GrossLock(dev);
++
++ if (!S_ISDIR(inode->i_mode)) /* Don't link directories */
++ {
++ link =
++ yaffs_Link(yaffs_InodeToObject(dir), dentry->d_name.name,
++ obj);
++ }
++
++ if (link) {
++ old_dentry->d_inode->i_nlink = yaffs_GetObjectLinkCount(obj);
++ d_instantiate(dentry, old_dentry->d_inode);
++ atomic_inc(&old_dentry->d_inode->i_count);
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_link link count %d i_count %d\n",
++ old_dentry->d_inode->i_nlink,
++ atomic_read(&old_dentry->d_inode->i_count)));
++
++ }
++
++ yaffs_GrossUnlock(dev);
++
++ if (link) {
++
++ return 0;
++ }
++
++ return -EPERM;
++}
++
++static int yaffs_symlink(struct inode *dir, struct dentry *dentry,
++ const char *symname)
++{
++ yaffs_Object *obj;
++ yaffs_Device *dev;
++ uid_t uid = current->fsuid;
++ gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : current->fsgid;
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_symlink\n"));
++
++ dev = yaffs_InodeToObject(dir)->myDev;
++ yaffs_GrossLock(dev);
++ obj = yaffs_MknodSymLink(yaffs_InodeToObject(dir), dentry->d_name.name,
++ S_IFLNK | S_IRWXUGO, uid, gid, symname);
++ yaffs_GrossUnlock(dev);
++
++ if (obj) {
++
++ struct inode *inode;
++
++ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj);
++ d_instantiate(dentry, inode);
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "symlink created OK\n"));
++ return 0;
++ } else {
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "symlink not created\n"));
++
++ }
++
++ return -ENOMEM;
++}
++
++static int yaffs_sync_object(struct file *file, struct dentry *dentry,
++ int datasync)
++{
++
++ yaffs_Object *obj;
++ yaffs_Device *dev;
++
++ obj = yaffs_DentryToObject(dentry);
++
++ dev = obj->myDev;
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_sync_object\n"));
++ yaffs_GrossLock(dev);
++ yaffs_FlushFile(obj, 1);
++ yaffs_GrossUnlock(dev);
++ return 0;
++}
++
++/*
++ * The VFS layer already does all the dentry stuff for rename.
++ *
++ * NB: POSIX says you can rename an object over an old object of the same name
++ */
++static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry,
++ struct inode *new_dir, struct dentry *new_dentry)
++{
++ yaffs_Device *dev;
++ int retVal = YAFFS_FAIL;
++ yaffs_Object *target;
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_rename\n"));
++ dev = yaffs_InodeToObject(old_dir)->myDev;
++
++ yaffs_GrossLock(dev);
++
++ /* Check if the target is an existing directory that is not empty. */
++ target =
++ yaffs_FindObjectByName(yaffs_InodeToObject(new_dir),
++ new_dentry->d_name.name);
++
++
++
++ if (target &&
++ target->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
++ !ylist_empty(&target->variant.directoryVariant.children)) {
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "target is non-empty dir\n"));
++
++ retVal = YAFFS_FAIL;
++ } else {
++
++ /* Now does unlinking internally using shadowing mechanism */
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "calling yaffs_RenameObject\n"));
++
++ retVal =
++ yaffs_RenameObject(yaffs_InodeToObject(old_dir),
++ old_dentry->d_name.name,
++ yaffs_InodeToObject(new_dir),
++ new_dentry->d_name.name);
++
++ }
++ yaffs_GrossUnlock(dev);
++
++ if (retVal == YAFFS_OK) {
++ if(target) {
++ new_dentry->d_inode->i_nlink--;
++ mark_inode_dirty(new_dentry->d_inode);
++ }
++
++ return 0;
++ } else {
++ return -ENOTEMPTY;
++ }
++
++}
++
++static int yaffs_setattr(struct dentry *dentry, struct iattr *attr)
++{
++ struct inode *inode = dentry->d_inode;
++ int error;
++ yaffs_Device *dev;
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_setattr of object %d\n",
++ yaffs_InodeToObject(inode)->objectId));
++
++ if ((error = inode_change_ok(inode, attr)) == 0) {
++
++ dev = yaffs_InodeToObject(inode)->myDev;
++ yaffs_GrossLock(dev);
++ if (yaffs_SetAttributes(yaffs_InodeToObject(inode), attr) ==
++ YAFFS_OK) {
++ error = 0;
++ } else {
++ error = -EPERM;
++ }
++ yaffs_GrossUnlock(dev);
++ if (!error)
++ error = inode_setattr(inode, attr);
++ }
++ return error;
++}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf)
++{
++ yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
++ struct super_block *sb = dentry->d_sb;
++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf)
++{
++ yaffs_Device *dev = yaffs_SuperToDevice(sb);
++#else
++static int yaffs_statfs(struct super_block *sb, struct statfs *buf)
++{
++ yaffs_Device *dev = yaffs_SuperToDevice(sb);
++#endif
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_statfs\n"));
++
++ yaffs_GrossLock(dev);
++
++ buf->f_type = YAFFS_MAGIC;
++ buf->f_bsize = sb->s_blocksize;
++ buf->f_namelen = 255;
++
++ if(dev->nDataBytesPerChunk & (dev->nDataBytesPerChunk - 1)){
++ /* Do this if chunk size is not a power of 2 */
++
++ uint64_t bytesInDev;
++ uint64_t bytesFree;
++
++ bytesInDev = ((uint64_t)((dev->endBlock - dev->startBlock +1))) *
++ ((uint64_t)(dev->nChunksPerBlock * dev->nDataBytesPerChunk));
++
++ do_div(bytesInDev,sb->s_blocksize); /* bytesInDev becomes the number of blocks */
++ buf->f_blocks = bytesInDev;
++
++ bytesFree = ((uint64_t)(yaffs_GetNumberOfFreeChunks(dev))) *
++ ((uint64_t)(dev->nDataBytesPerChunk));
++
++ do_div(bytesFree,sb->s_blocksize);
++
++ buf->f_bfree = bytesFree;
++
++ } else if (sb->s_blocksize > dev->nDataBytesPerChunk) {
++
++ buf->f_blocks =
++ (dev->endBlock - dev->startBlock + 1) *
++ dev->nChunksPerBlock /
++ (sb->s_blocksize / dev->nDataBytesPerChunk);
++ buf->f_bfree =
++ yaffs_GetNumberOfFreeChunks(dev) /
++ (sb->s_blocksize / dev->nDataBytesPerChunk);
++ } else {
++ buf->f_blocks =
++ (dev->endBlock - dev->startBlock + 1) *
++ dev->nChunksPerBlock *
++ (dev->nDataBytesPerChunk / sb->s_blocksize);
++
++ buf->f_bfree =
++ yaffs_GetNumberOfFreeChunks(dev) *
++ (dev->nDataBytesPerChunk / sb->s_blocksize);
++ }
++
++
++ buf->f_files = 0;
++ buf->f_ffree = 0;
++ buf->f_bavail = buf->f_bfree;
++
++ yaffs_GrossUnlock(dev);
++ return 0;
++}
++
++
++static int yaffs_do_sync_fs(struct super_block *sb)
++{
++
++ yaffs_Device *dev = yaffs_SuperToDevice(sb);
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_do_sync_fs\n"));
++
++ if(sb->s_dirt) {
++ yaffs_GrossLock(dev);
++
++ if(dev){
++ yaffs_FlushEntireDeviceCache(dev);
++ yaffs_CheckpointSave(dev);
++ }
++
++ yaffs_GrossUnlock(dev);
++
++ sb->s_dirt = 0;
++ }
++ return 0;
++}
++
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static void yaffs_write_super(struct super_block *sb)
++#else
++static int yaffs_write_super(struct super_block *sb)
++#endif
++{
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_write_super\n"));
++ yaffs_do_sync_fs(sb);
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
++ return 0;
++#endif
++}
++
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs_sync_fs(struct super_block *sb, int wait)
++#else
++static int yaffs_sync_fs(struct super_block *sb)
++#endif
++{
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_sync_fs\n"));
++
++ yaffs_do_sync_fs(sb);
++
++ return 0;
++
++}
++
++#ifdef YAFFS_USE_OWN_IGET
++
++static struct inode * yaffs_iget(struct super_block *sb, unsigned long ino)
++{
++ struct inode *inode;
++ yaffs_Object *obj;
++ yaffs_Device *dev = yaffs_SuperToDevice(sb);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_iget for %lu\n", ino));
++
++ inode = iget_locked(sb, ino);
++ if (!inode)
++ return ERR_PTR(-ENOMEM);
++ if (!(inode->i_state & I_NEW))
++ return inode;
++
++ /* NB This is called as a side effect of other functions, but
++ * we had to release the lock to prevent deadlocks, so
++ * need to lock again.
++ */
++
++ yaffs_GrossLock(dev);
++
++ obj = yaffs_FindObjectByNumber(dev, inode->i_ino);
++
++ yaffs_FillInodeFromObject(inode, obj);
++
++ yaffs_GrossUnlock(dev);
++
++ unlock_new_inode(inode);
++ return inode;
++}
++
++#else
++
++static void yaffs_read_inode(struct inode *inode)
++{
++ /* NB This is called as a side effect of other functions, but
++ * we had to release the lock to prevent deadlocks, so
++ * need to lock again.
++ */
++
++ yaffs_Object *obj;
++ yaffs_Device *dev = yaffs_SuperToDevice(inode->i_sb);
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_read_inode for %d\n", (int)inode->i_ino));
++
++ yaffs_GrossLock(dev);
++
++ obj = yaffs_FindObjectByNumber(dev, inode->i_ino);
++
++ yaffs_FillInodeFromObject(inode, obj);
++
++ yaffs_GrossUnlock(dev);
++}
++
++#endif
++
++static YLIST_HEAD(yaffs_dev_list);
++
++#if 0 // not used
++static int yaffs_remount_fs(struct super_block *sb, int *flags, char *data)
++{
++ yaffs_Device *dev = yaffs_SuperToDevice(sb);
++
++ if( *flags & MS_RDONLY ) {
++ struct mtd_info *mtd = yaffs_SuperToDevice(sb)->genericDevice;
++
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_remount_fs: %s: RO\n", dev->name ));
++
++ yaffs_GrossLock(dev);
++
++ yaffs_FlushEntireDeviceCache(dev);
++
++ yaffs_CheckpointSave(dev);
++
++ if (mtd->sync)
++ mtd->sync(mtd);
++
++ yaffs_GrossUnlock(dev);
++ }
++ else {
++ T(YAFFS_TRACE_OS,
++ (KERN_DEBUG "yaffs_remount_fs: %s: RW\n", dev->name ));
++ }
++
++ return 0;
++}
++#endif
++
++static void yaffs_put_super(struct super_block *sb)
++{
++ yaffs_Device *dev = yaffs_SuperToDevice(sb);
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_put_super\n"));
++
++ yaffs_GrossLock(dev);
++
++ yaffs_FlushEntireDeviceCache(dev);
++
++ yaffs_CheckpointSave(dev);
++
++ if (dev->putSuperFunc) {
++ dev->putSuperFunc(sb);
++ }
++
++ yaffs_Deinitialise(dev);
++
++ yaffs_GrossUnlock(dev);
++
++ /* we assume this is protected by lock_kernel() in mount/umount */
++ ylist_del(&dev->devList);
++
++ if(dev->spareBuffer){
++ YFREE(dev->spareBuffer);
++ dev->spareBuffer = NULL;
++ }
++
++ kfree(dev);
++}
++
++
++static void yaffs_MTDPutSuper(struct super_block *sb)
++{
++
++ struct mtd_info *mtd = yaffs_SuperToDevice(sb)->genericDevice;
++
++ if (mtd->sync) {
++ mtd->sync(mtd);
++ }
++
++ put_mtd_device(mtd);
++}
++
++
++static void yaffs_MarkSuperBlockDirty(void *vsb)
++{
++ struct super_block *sb = (struct super_block *)vsb;
++
++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_MarkSuperBlockDirty() sb = %p\n",sb));
++// if(sb)
++// sb->s_dirt = 1;
++}
++
++typedef struct {
++ int inband_tags;
++ int skip_checkpoint_read;
++ int skip_checkpoint_write;
++ int no_cache;
++} yaffs_options;
++
++#define MAX_OPT_LEN 20
++static int yaffs_parse_options(yaffs_options *options, const char *options_str)
++{
++ char cur_opt[MAX_OPT_LEN+1];
++ int p;
++ int error = 0;
++
++ /* Parse through the options which is a comma seperated list */
++
++ while(options_str && *options_str && !error){
++ memset(cur_opt,0,MAX_OPT_LEN+1);
++ p = 0;
++
++ while(*options_str && *options_str != ','){
++ if(p < MAX_OPT_LEN){
++ cur_opt[p] = *options_str;
++ p++;
++ }
++ options_str++;
++ }
++
++ if(!strcmp(cur_opt,"inband-tags"))
++ options->inband_tags = 1;
++ else if(!strcmp(cur_opt,"no-cache"))
++ options->no_cache = 1;
++ else if(!strcmp(cur_opt,"no-checkpoint-read"))
++ options->skip_checkpoint_read = 1;
++ else if(!strcmp(cur_opt,"no-checkpoint-write"))
++ options->skip_checkpoint_write = 1;
++ else if(!strcmp(cur_opt,"no-checkpoint")){
++ options->skip_checkpoint_read = 1;
++ options->skip_checkpoint_write = 1;
++ } else {
++ printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n",cur_opt);
++ error = 1;
++ }
++
++ }
++
++ return error;
++}
++
++static struct super_block *yaffs_internal_read_super(int yaffsVersion,
++ struct super_block *sb,
++ void *data, int silent)
++{
++ int nBlocks;
++ struct inode *inode = NULL;
++ struct dentry *root;
++ yaffs_Device *dev = 0;
++ char devname_buf[BDEVNAME_SIZE + 1];
++ struct mtd_info *mtd;
++ int err;
++ char *data_str = (char *)data;
++
++ yaffs_options options;
++
++ sb->s_magic = YAFFS_MAGIC;
++ sb->s_op = &yaffs_super_ops;
++ sb->s_flags |= MS_NOATIME;
++
++ if (!sb)
++ printk(KERN_INFO "yaffs: sb is NULL\n");
++ else if (!sb->s_dev)
++ printk(KERN_INFO "yaffs: sb->s_dev is NULL\n");
++ else if (!yaffs_devname(sb, devname_buf))
++ printk(KERN_INFO "yaffs: devname is NULL\n");
++ else
++ printk(KERN_INFO "yaffs: dev is %d name is \"%s\"\n",
++ sb->s_dev,
++ yaffs_devname(sb, devname_buf));
++
++ if(!data_str)
++ data_str = "";
++
++ printk(KERN_INFO "yaffs: passed flags \"%s\"\n",data_str);
++
++ memset(&options,0,sizeof(options));
++
++ if(yaffs_parse_options(&options,data_str)){
++ /* Option parsing failed */
++ return NULL;
++ }
++
++
++ sb->s_blocksize = PAGE_CACHE_SIZE;
++ sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
++ T(YAFFS_TRACE_OS, ("yaffs_read_super: Using yaffs%d\n", yaffsVersion));
++ T(YAFFS_TRACE_OS,
++ ("yaffs_read_super: block size %d\n", (int)(sb->s_blocksize)));
++
++#ifdef CONFIG_YAFFS_DISABLE_WRITE_VERIFY
++ T(YAFFS_TRACE_OS,
++ ("yaffs: Write verification disabled. All guarantees "
++ "null and void\n"));
++#endif
++
++ T(YAFFS_TRACE_ALWAYS, ("yaffs: Attempting MTD mount on %u.%u, "
++ "\"%s\"\n",
++ MAJOR(sb->s_dev), MINOR(sb->s_dev),
++ yaffs_devname(sb, devname_buf)));
++
++ /* Check it's an mtd device..... */
++ if (MAJOR(sb->s_dev) != MTD_BLOCK_MAJOR) {
++ return NULL; /* This isn't an mtd device */
++ }
++ /* Get the device */
++ mtd = get_mtd_device(NULL, MINOR(sb->s_dev));
++ if (!mtd) {
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs: MTD device #%u doesn't appear to exist\n",
++ MINOR(sb->s_dev)));
++ return NULL;
++ }
++ /* Check it's NAND */
++ if (mtd->type != MTD_NANDFLASH) {
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs: MTD device is not NAND it's type %d\n", mtd->type));
++ return NULL;
++ }
++
++ T(YAFFS_TRACE_OS, (" erase %p\n", mtd->erase));
++ T(YAFFS_TRACE_OS, (" read %p\n", mtd->read));
++ T(YAFFS_TRACE_OS, (" write %p\n", mtd->write));
++ T(YAFFS_TRACE_OS, (" readoob %p\n", mtd->read_oob));
++ T(YAFFS_TRACE_OS, (" writeoob %p\n", mtd->write_oob));
++ T(YAFFS_TRACE_OS, (" block_isbad %p\n", mtd->block_isbad));
++ T(YAFFS_TRACE_OS, (" block_markbad %p\n", mtd->block_markbad));
++ T(YAFFS_TRACE_OS, (" %s %d\n", WRITE_SIZE_STR, WRITE_SIZE(mtd)));
++ T(YAFFS_TRACE_OS, (" oobsize %d\n", mtd->oobsize));
++ T(YAFFS_TRACE_OS, (" erasesize %d\n", mtd->erasesize));
++ T(YAFFS_TRACE_OS, (" size %d\n", mtd->size));
++
++#ifdef CONFIG_YAFFS_AUTO_YAFFS2
++
++ if (yaffsVersion == 1 &&
++ WRITE_SIZE(mtd) >= 2048) {
++ T(YAFFS_TRACE_ALWAYS,("yaffs: auto selecting yaffs2\n"));
++ yaffsVersion = 2;
++ }
++
++ /* Added NCB 26/5/2006 for completeness */
++ if (yaffsVersion == 2 &&
++ !options.inband_tags &&
++ WRITE_SIZE(mtd) == 512){
++ T(YAFFS_TRACE_ALWAYS,("yaffs: auto selecting yaffs1\n"));
++ yaffsVersion = 1;
++ }
++
++#endif
++
++ if (yaffsVersion == 2) {
++ /* Check for version 2 style functions */
++ if (!mtd->erase ||
++ !mtd->block_isbad ||
++ !mtd->block_markbad ||
++ !mtd->read ||
++ !mtd->write ||
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++ !mtd->read_oob || !mtd->write_oob) {
++#else
++ !mtd->write_ecc ||
++ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) {
++#endif
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs: MTD device does not support required "
++ "functions\n"));;
++ return NULL;
++ }
++
++ if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE ||
++ mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) &&
++ !options.inband_tags) {
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs: MTD device does not have the "
++ "right page sizes\n"));
++ return NULL;
++ }
++ } else {
++ /* Check for V1 style functions */
++ if (!mtd->erase ||
++ !mtd->read ||
++ !mtd->write ||
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++ !mtd->read_oob || !mtd->write_oob) {
++#else
++ !mtd->write_ecc ||
++ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) {
++#endif
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs: MTD device does not support required "
++ "functions\n"));;
++ return NULL;
++ }
++
++ if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK ||
++ mtd->oobsize != YAFFS_BYTES_PER_SPARE) {
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs: MTD device does not support have the "
++ "right page sizes\n"));
++ return NULL;
++ }
++ }
++
++ /* OK, so if we got here, we have an MTD that's NAND and looks
++ * like it has the right capabilities
++ * Set the yaffs_Device up for mtd
++ */
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++ sb->s_fs_info = dev = kmalloc(sizeof(yaffs_Device), GFP_KERNEL);
++#else
++ sb->u.generic_sbp = dev = kmalloc(sizeof(yaffs_Device), GFP_KERNEL);
++#endif
++ if (!dev) {
++ /* Deep shit could not allocate device structure */
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs_read_super: Failed trying to allocate "
++ "yaffs_Device. \n"));
++ return NULL;
++ }
++
++ memset(dev, 0, sizeof(yaffs_Device));
++ dev->genericDevice = mtd;
++ dev->name = mtd->name;
++
++ /* Set up the memory size parameters.... */
++
++ nBlocks = mtd->size / (YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK);
++ dev->startBlock = 0;
++ dev->endBlock = nBlocks - 1;
++ dev->nChunksPerBlock = YAFFS_CHUNKS_PER_BLOCK;
++ dev->totalBytesPerChunk = YAFFS_BYTES_PER_CHUNK;
++ dev->nReservedBlocks = 5;
++ dev->nShortOpCaches = (options.no_cache) ? 0 : 10;
++ dev->inbandTags = options.inband_tags;
++
++ /* ... and the functions. */
++ if (yaffsVersion == 2) {
++ dev->writeChunkWithTagsToNAND =
++ nandmtd2_WriteChunkWithTagsToNAND;
++ dev->readChunkWithTagsFromNAND =
++ nandmtd2_ReadChunkWithTagsFromNAND;
++ dev->markNANDBlockBad = nandmtd2_MarkNANDBlockBad;
++ dev->queryNANDBlock = nandmtd2_QueryNANDBlock;
++ dev->spareBuffer = YMALLOC(mtd->oobsize);
++ dev->isYaffs2 = 1;
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++ dev->totalBytesPerChunk = mtd->writesize;
++ dev->nChunksPerBlock = mtd->erasesize / mtd->writesize;
++#else
++ dev->totalBytesPerChunk = mtd->oobblock;
++ dev->nChunksPerBlock = mtd->erasesize / mtd->oobblock;
++#endif
++ nBlocks = mtd->size / mtd->erasesize;
++
++ dev->startBlock = 0;
++ dev->endBlock = nBlocks - 1;
++ } else {
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++ /* use the MTD interface in yaffs_mtdif1.c */
++ dev->writeChunkWithTagsToNAND =
++ nandmtd1_WriteChunkWithTagsToNAND;
++ dev->readChunkWithTagsFromNAND =
++ nandmtd1_ReadChunkWithTagsFromNAND;
++ dev->markNANDBlockBad = nandmtd1_MarkNANDBlockBad;
++ dev->queryNANDBlock = nandmtd1_QueryNANDBlock;
++#else
++ dev->writeChunkToNAND = nandmtd_WriteChunkToNAND;
++ dev->readChunkFromNAND = nandmtd_ReadChunkFromNAND;
++#endif
++ dev->isYaffs2 = 0;
++ }
++ /* ... and common functions */
++ dev->eraseBlockInNAND = nandmtd_EraseBlockInNAND;
++ dev->initialiseNAND = nandmtd_InitialiseNAND;
++
++ dev->putSuperFunc = yaffs_MTDPutSuper;
++
++ dev->superBlock = (void *)sb;
++ dev->markSuperBlockDirty = yaffs_MarkSuperBlockDirty;
++
++
++#ifndef CONFIG_YAFFS_DOES_ECC
++ dev->useNANDECC = 1;
++#endif
++
++#ifdef CONFIG_YAFFS_DISABLE_WIDE_TNODES
++ dev->wideTnodesDisabled = 1;
++#endif
++
++ dev->skipCheckpointRead = options.skip_checkpoint_read;
++ dev->skipCheckpointWrite = options.skip_checkpoint_write;
++
++ /* we assume this is protected by lock_kernel() in mount/umount */
++ ylist_add_tail(&dev->devList, &yaffs_dev_list);
++
++ init_MUTEX(&dev->grossLock);
++
++ yaffs_GrossLock(dev);
++
++ err = yaffs_GutsInitialise(dev);
++
++ T(YAFFS_TRACE_OS,
++ ("yaffs_read_super: guts initialised %s\n",
++ (err == YAFFS_OK) ? "OK" : "FAILED"));
++
++ /* Release lock before yaffs_get_inode() */
++ yaffs_GrossUnlock(dev);
++
++ /* Create root inode */
++ if (err == YAFFS_OK)
++ inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0,
++ yaffs_Root(dev));
++
++ if (!inode)
++ return NULL;
++
++ inode->i_op = &yaffs_dir_inode_operations;
++ inode->i_fop = &yaffs_dir_operations;
++
++ T(YAFFS_TRACE_OS, ("yaffs_read_super: got root inode\n"));
++
++ root = d_alloc_root(inode);
++
++ T(YAFFS_TRACE_OS, ("yaffs_read_super: d_alloc_root done\n"));
++
++ if (!root) {
++ iput(inode);
++ return NULL;
++ }
++ sb->s_root = root;
++
++ T(YAFFS_TRACE_OS, ("yaffs_read_super: done\n"));
++ return sb;
++}
++
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data,
++ int silent)
++{
++ return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL;
++}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs_read_super(struct file_system_type *fs,
++ int flags, const char *dev_name,
++ void *data, struct vfsmount *mnt)
++{
++
++ return get_sb_bdev(fs, flags, dev_name, data,
++ yaffs_internal_read_super_mtd, mnt);
++}
++#else
++static struct super_block *yaffs_read_super(struct file_system_type *fs,
++ int flags, const char *dev_name,
++ void *data)
++{
++
++ return get_sb_bdev(fs, flags, dev_name, data,
++ yaffs_internal_read_super_mtd);
++}
++#endif
++
++static struct file_system_type yaffs_fs_type = {
++ .owner = THIS_MODULE,
++ .name = "yaffs",
++ .get_sb = yaffs_read_super,
++ .kill_sb = kill_block_super,
++ .fs_flags = FS_REQUIRES_DEV,
++};
++#else
++static struct super_block *yaffs_read_super(struct super_block *sb, void *data,
++ int silent)
++{
++ return yaffs_internal_read_super(1, sb, data, silent);
++}
++
++static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super,
++ FS_REQUIRES_DEV);
++#endif
++
++
++#ifdef CONFIG_YAFFS_YAFFS2
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data,
++ int silent)
++{
++ return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL;
++}
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++static int yaffs2_read_super(struct file_system_type *fs,
++ int flags, const char *dev_name, void *data,
++ struct vfsmount *mnt)
++{
++ return get_sb_bdev(fs, flags, dev_name, data,
++ yaffs2_internal_read_super_mtd, mnt);
++}
++#else
++static struct super_block *yaffs2_read_super(struct file_system_type *fs,
++ int flags, const char *dev_name,
++ void *data)
++{
++
++ return get_sb_bdev(fs, flags, dev_name, data,
++ yaffs2_internal_read_super_mtd);
++}
++#endif
++
++static struct file_system_type yaffs2_fs_type = {
++ .owner = THIS_MODULE,
++ .name = "yaffs2",
++ .get_sb = yaffs2_read_super,
++ .kill_sb = kill_block_super,
++ .fs_flags = FS_REQUIRES_DEV,
++};
++#else
++static struct super_block *yaffs2_read_super(struct super_block *sb,
++ void *data, int silent)
++{
++ return yaffs_internal_read_super(2, sb, data, silent);
++}
++
++static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super,
++ FS_REQUIRES_DEV);
++#endif
++
++#endif /* CONFIG_YAFFS_YAFFS2 */
++
++static struct proc_dir_entry *my_proc_entry;
++
++static char *yaffs_dump_dev(char *buf, yaffs_Device * dev)
++{
++ buf += sprintf(buf, "startBlock......... %d\n", dev->startBlock);
++ buf += sprintf(buf, "endBlock........... %d\n", dev->endBlock);
++ buf += sprintf(buf, "totalBytesPerChunk. %d\n", dev->totalBytesPerChunk);
++ buf += sprintf(buf, "nDataBytesPerChunk. %d\n", dev->nDataBytesPerChunk);
++ buf += sprintf(buf, "chunkGroupBits..... %d\n", dev->chunkGroupBits);
++ buf += sprintf(buf, "chunkGroupSize..... %d\n", dev->chunkGroupSize);
++ buf += sprintf(buf, "nErasedBlocks...... %d\n", dev->nErasedBlocks);
++ buf += sprintf(buf, "nReservedBlocks.... %d\n", dev->nReservedBlocks);
++ buf += sprintf(buf, "blocksInCheckpoint. %d\n", dev->blocksInCheckpoint);
++ buf += sprintf(buf, "nTnodesCreated..... %d\n", dev->nTnodesCreated);
++ buf += sprintf(buf, "nFreeTnodes........ %d\n", dev->nFreeTnodes);
++ buf += sprintf(buf, "nObjectsCreated.... %d\n", dev->nObjectsCreated);
++ buf += sprintf(buf, "nFreeObjects....... %d\n", dev->nFreeObjects);
++ buf += sprintf(buf, "nFreeChunks........ %d\n", dev->nFreeChunks);
++ buf += sprintf(buf, "nPageWrites........ %d\n", dev->nPageWrites);
++ buf += sprintf(buf, "nPageReads......... %d\n", dev->nPageReads);
++ buf += sprintf(buf, "nBlockErasures..... %d\n", dev->nBlockErasures);
++ buf += sprintf(buf, "nGCCopies.......... %d\n", dev->nGCCopies);
++ buf += sprintf(buf, "garbageCollections. %d\n", dev->garbageCollections);
++ buf += sprintf(buf, "passiveGCs......... %d\n",
++ dev->passiveGarbageCollections);
++ buf += sprintf(buf, "nRetriedWrites..... %d\n", dev->nRetriedWrites);
++ buf += sprintf(buf, "nShortOpCaches..... %d\n", dev->nShortOpCaches);
++ buf += sprintf(buf, "nRetireBlocks...... %d\n", dev->nRetiredBlocks);
++ buf += sprintf(buf, "eccFixed........... %d\n", dev->eccFixed);
++ buf += sprintf(buf, "eccUnfixed......... %d\n", dev->eccUnfixed);
++ buf += sprintf(buf, "tagsEccFixed....... %d\n", dev->tagsEccFixed);
++ buf += sprintf(buf, "tagsEccUnfixed..... %d\n", dev->tagsEccUnfixed);
++ buf += sprintf(buf, "cacheHits.......... %d\n", dev->cacheHits);
++ buf += sprintf(buf, "nDeletedFiles...... %d\n", dev->nDeletedFiles);
++ buf += sprintf(buf, "nUnlinkedFiles..... %d\n", dev->nUnlinkedFiles);
++ buf +=
++ sprintf(buf, "nBackgroudDeletions %d\n", dev->nBackgroundDeletions);
++ buf += sprintf(buf, "useNANDECC......... %d\n", dev->useNANDECC);
++ buf += sprintf(buf, "isYaffs2........... %d\n", dev->isYaffs2);
++ buf += sprintf(buf, "inbandTags......... %d\n", dev->inbandTags);
++
++ return buf;
++}
++
++static int yaffs_proc_read(char *page,
++ char **start,
++ off_t offset, int count, int *eof, void *data)
++{
++ struct ylist_head *item;
++ char *buf = page;
++ int step = offset;
++ int n = 0;
++
++ /* Get proc_file_read() to step 'offset' by one on each sucessive call.
++ * We use 'offset' (*ppos) to indicate where we are in devList.
++ * This also assumes the user has posted a read buffer large
++ * enough to hold the complete output; but that's life in /proc.
++ */
++
++ *(int *)start = 1;
++
++ /* Print header first */
++ if (step == 0) {
++ buf += sprintf(buf, "YAFFS built:" __DATE__ " " __TIME__
++ "\n%s\n%s\n", yaffs_fs_c_version,
++ yaffs_guts_c_version);
++ }
++
++ /* hold lock_kernel while traversing yaffs_dev_list */
++ lock_kernel();
++
++ /* Locate and print the Nth entry. Order N-squared but N is small. */
++ ylist_for_each(item, &yaffs_dev_list) {
++ yaffs_Device *dev = ylist_entry(item, yaffs_Device, devList);
++ if (n < step) {
++ n++;
++ continue;
++ }
++ buf += sprintf(buf, "\nDevice %d \"%s\"\n", n, dev->name);
++ buf = yaffs_dump_dev(buf, dev);
++ break;
++ }
++ unlock_kernel();
++
++ return buf - page < count ? buf - page : count;
++}
++
++/**
++ * Set the verbosity of the warnings and error messages.
++ *
++ * Note that the names can only be a..z or _ with the current code.
++ */
++
++static struct {
++ char *mask_name;
++ unsigned mask_bitfield;
++} mask_flags[] = {
++ {"allocate", YAFFS_TRACE_ALLOCATE},
++ {"always", YAFFS_TRACE_ALWAYS},
++ {"bad_blocks", YAFFS_TRACE_BAD_BLOCKS},
++ {"buffers", YAFFS_TRACE_BUFFERS},
++ {"bug", YAFFS_TRACE_BUG},
++ {"checkpt", YAFFS_TRACE_CHECKPOINT},
++ {"deletion", YAFFS_TRACE_DELETION},
++ {"erase", YAFFS_TRACE_ERASE},
++ {"error", YAFFS_TRACE_ERROR},
++ {"gc_detail", YAFFS_TRACE_GC_DETAIL},
++ {"gc", YAFFS_TRACE_GC},
++ {"mtd", YAFFS_TRACE_MTD},
++ {"nandaccess", YAFFS_TRACE_NANDACCESS},
++ {"os", YAFFS_TRACE_OS},
++ {"scan_debug", YAFFS_TRACE_SCAN_DEBUG},
++ {"scan", YAFFS_TRACE_SCAN},
++ {"tracing", YAFFS_TRACE_TRACING},
++
++ {"verify", YAFFS_TRACE_VERIFY},
++ {"verify_nand", YAFFS_TRACE_VERIFY_NAND},
++ {"verify_full", YAFFS_TRACE_VERIFY_FULL},
++ {"verify_all", YAFFS_TRACE_VERIFY_ALL},
++
++ {"write", YAFFS_TRACE_WRITE},
++ {"all", 0xffffffff},
++ {"none", 0},
++ {NULL, 0},
++};
++
++#define MAX_MASK_NAME_LENGTH 40
++static int yaffs_proc_write(struct file *file, const char *buf,
++ unsigned long count, void *data)
++{
++ unsigned rg = 0, mask_bitfield;
++ char *end;
++ char *mask_name;
++ const char *x;
++ char substring[MAX_MASK_NAME_LENGTH+1];
++ int i;
++ int done = 0;
++ int add, len = 0;
++ int pos = 0;
++
++ rg = yaffs_traceMask;
++
++ while (!done && (pos < count)) {
++ done = 1;
++ while ((pos < count) && isspace(buf[pos])) {
++ pos++;
++ }
++
++ switch (buf[pos]) {
++ case '+':
++ case '-':
++ case '=':
++ add = buf[pos];
++ pos++;
++ break;
++
++ default:
++ add = ' ';
++ break;
++ }
++ mask_name = NULL;
++
++ mask_bitfield = simple_strtoul(buf + pos, &end, 0);
++ if (end > buf + pos) {
++ mask_name = "numeral";
++ len = end - (buf + pos);
++ pos += len;
++ done = 0;
++ } else {
++ for(x = buf + pos, i = 0;
++ (*x == '_' || (*x >='a' && *x <= 'z')) &&
++ i <MAX_MASK_NAME_LENGTH; x++, i++, pos++)
++ substring[i] = *x;
++ substring[i] = '\0';
++
++ for (i = 0; mask_flags[i].mask_name != NULL; i++) {
++ if(strcmp(substring,mask_flags[i].mask_name) == 0){
++ mask_name = mask_flags[i].mask_name;
++ mask_bitfield = mask_flags[i].mask_bitfield;
++ done = 0;
++ break;
++ }
++ }
++ }
++
++ if (mask_name != NULL) {
++ done = 0;
++ switch(add) {
++ case '-':
++ rg &= ~mask_bitfield;
++ break;
++ case '+':
++ rg |= mask_bitfield;
++ break;
++ case '=':
++ rg = mask_bitfield;
++ break;
++ default:
++ rg |= mask_bitfield;
++ break;
++ }
++ }
++ }
++
++ yaffs_traceMask = rg | YAFFS_TRACE_ALWAYS;
++
++ printk("new trace = 0x%08X\n",yaffs_traceMask);
++
++ if (rg & YAFFS_TRACE_ALWAYS) {
++ for (i = 0; mask_flags[i].mask_name != NULL; i++) {
++ char flag;
++ flag = ((rg & mask_flags[i].mask_bitfield) == mask_flags[i].mask_bitfield) ? '+' : '-';
++ printk("%c%s\n", flag, mask_flags[i].mask_name);
++ }
++ }
++
++ return count;
++}
++
++/* Stuff to handle installation of file systems */
++struct file_system_to_install {
++ struct file_system_type *fst;
++ int installed;
++};
++
++static struct file_system_to_install fs_to_install[] = {
++//#ifdef CONFIG_YAFFS_YAFFS1
++ {&yaffs_fs_type, 0},
++//#endif
++//#ifdef CONFIG_YAFFS_YAFFS2
++ {&yaffs2_fs_type, 0},
++//#endif
++ {NULL, 0}
++};
++
++static int __init init_yaffs_fs(void)
++{
++ int error = 0;
++ struct file_system_to_install *fsinst;
++
++ T(YAFFS_TRACE_ALWAYS,
++ ("yaffs " __DATE__ " " __TIME__ " Installing. \n"));
++
++ /* Install the proc_fs entry */
++ my_proc_entry = create_proc_entry("yaffs",
++ S_IRUGO | S_IFREG,
++ YPROC_ROOT);
++
++ if (my_proc_entry) {
++ my_proc_entry->write_proc = yaffs_proc_write;
++ my_proc_entry->read_proc = yaffs_proc_read;
++ my_proc_entry->data = NULL;
++ } else {
++ return -ENOMEM;
++ }
++
++ /* Now add the file system entries */
++
++ fsinst = fs_to_install;
++
++ while (fsinst->fst && !error) {
++ error = register_filesystem(fsinst->fst);
++ if (!error) {
++ fsinst->installed = 1;
++ }
++ fsinst++;
++ }
++
++ /* Any errors? uninstall */
++ if (error) {
++ fsinst = fs_to_install;
++
++ while (fsinst->fst) {
++ if (fsinst->installed) {
++ unregister_filesystem(fsinst->fst);
++ fsinst->installed = 0;
++ }
++ fsinst++;
++ }
++ }
++
++ return error;
++}
++
++static void __exit exit_yaffs_fs(void)
++{
++
++ struct file_system_to_install *fsinst;
++
++ T(YAFFS_TRACE_ALWAYS, ("yaffs " __DATE__ " " __TIME__
++ " removing. \n"));
++
++ remove_proc_entry("yaffs", YPROC_ROOT);
++
++ fsinst = fs_to_install;
++
++ while (fsinst->fst) {
++ if (fsinst->installed) {
++ unregister_filesystem(fsinst->fst);
++ fsinst->installed = 0;
++ }
++ fsinst++;
++ }
++
++}
++
++module_init(init_yaffs_fs)
++module_exit(exit_yaffs_fs)
++
++MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system");
++MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2006");
++MODULE_LICENSE("GPL");
+diff --git a/fs/yaffs2/yaffs_getblockinfo.h b/fs/yaffs2/yaffs_getblockinfo.h
+new file mode 100644
+index 0000000..b9742ac
+--- /dev/null
++++ b/fs/yaffs2/yaffs_getblockinfo.h
+@@ -0,0 +1,34 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_GETBLOCKINFO_H__
++#define __YAFFS_GETBLOCKINFO_H__
++
++#include "yaffs_guts.h"
++
++/* Function to manipulate block info */
++static Y_INLINE yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blk)
++{
++ if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>> yaffs: getBlockInfo block %d is not valid" TENDSTR),
++ blk));
++ YBUG();
++ }
++ return &dev->blockInfo[blk - dev->internalStartBlock];
++}
++
++#endif
+diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c
+new file mode 100644
+index 0000000..8ea033a
+--- /dev/null
++++ b/fs/yaffs2/yaffs_guts.c
+@@ -0,0 +1,7676 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++const char *yaffs_guts_c_version =
++ "$Id: yaffs_guts.c,v 1.71 2009/01/12 00:53:47 charles Exp $";
++
++#include "yportenv.h"
++
++#include "yaffsinterface.h"
++#include "yaffs_guts.h"
++#include "yaffs_tagsvalidity.h"
++#include "yaffs_getblockinfo.h"
++
++#include "yaffs_tagscompat.h"
++#ifndef CONFIG_YAFFS_USE_OWN_SORT
++#include "yaffs_qsort.h"
++#endif
++#include "yaffs_nand.h"
++
++#include "yaffs_checkptrw.h"
++
++#include "yaffs_nand.h"
++#include "yaffs_packedtags2.h"
++
++
++#ifdef CONFIG_YAFFS_WINCE
++void yfsd_LockYAFFS(BOOL fsLockOnly);
++void yfsd_UnlockYAFFS(BOOL fsLockOnly);
++#endif
++
++#define YAFFS_PASSIVE_GC_CHUNKS 2
++
++#include "yaffs_ecc.h"
++
++
++/* Robustification (if it ever comes about...) */
++static void yaffs_RetireBlock(yaffs_Device * dev, int blockInNAND);
++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND, int erasedOk);
++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data,
++ const yaffs_ExtendedTags * tags);
++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
++ const yaffs_ExtendedTags * tags);
++
++/* Other local prototypes */
++static int yaffs_UnlinkObject( yaffs_Object *obj);
++static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj);
++
++static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList);
++
++static int yaffs_WriteNewChunkWithTagsToNAND(yaffs_Device * dev,
++ const __u8 * buffer,
++ yaffs_ExtendedTags * tags,
++ int useReserve);
++static int yaffs_PutChunkIntoFile(yaffs_Object * in, int chunkInInode,
++ int chunkInNAND, int inScan);
++
++static yaffs_Object *yaffs_CreateNewObject(yaffs_Device * dev, int number,
++ yaffs_ObjectType type);
++static void yaffs_AddObjectToDirectory(yaffs_Object * directory,
++ yaffs_Object * obj);
++static int yaffs_UpdateObjectHeader(yaffs_Object * in, const YCHAR * name,
++ int force, int isShrink, int shadows);
++static void yaffs_RemoveObjectFromDirectory(yaffs_Object * obj);
++static int yaffs_CheckStructures(void);
++static int yaffs_DeleteWorker(yaffs_Object * in, yaffs_Tnode * tn, __u32 level,
++ int chunkOffset, int *limit);
++static int yaffs_DoGenericObjectDeletion(yaffs_Object * in);
++
++static yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blockNo);
++
++
++static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
++ int chunkInNAND);
++
++static int yaffs_UnlinkWorker(yaffs_Object * obj);
++static void yaffs_DestroyObject(yaffs_Object * obj);
++
++static int yaffs_TagsMatch(const yaffs_ExtendedTags * tags, int objectId,
++ int chunkInObject);
++
++loff_t yaffs_GetFileSize(yaffs_Object * obj);
++
++static int yaffs_AllocateChunk(yaffs_Device * dev, int useReserve, yaffs_BlockInfo **blockUsedPtr);
++
++static void yaffs_VerifyFreeChunks(yaffs_Device * dev);
++
++static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in);
++
++static void yaffs_VerifyDirectory(yaffs_Object *directory);
++#ifdef YAFFS_PARANOID
++static int yaffs_CheckFileSanity(yaffs_Object * in);
++#else
++#define yaffs_CheckFileSanity(in)
++#endif
++
++static void yaffs_InvalidateWholeChunkCache(yaffs_Object * in);
++static void yaffs_InvalidateChunkCache(yaffs_Object * object, int chunkId);
++
++static void yaffs_InvalidateCheckpoint(yaffs_Device *dev);
++
++static int yaffs_FindChunkInFile(yaffs_Object * in, int chunkInInode,
++ yaffs_ExtendedTags * tags);
++
++static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos);
++static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device * dev,
++ yaffs_FileStructure * fStruct,
++ __u32 chunkId);
++
++
++/* Function to calculate chunk and offset */
++
++static void yaffs_AddrToChunk(yaffs_Device *dev, loff_t addr, int *chunkOut, __u32 *offsetOut)
++{
++ int chunk;
++ __u32 offset;
++
++ chunk = (__u32)(addr >> dev->chunkShift);
++
++ if(dev->chunkDiv == 1)
++ {
++ /* easy power of 2 case */
++ offset = (__u32)(addr & dev->chunkMask);
++ }
++ else
++ {
++ /* Non power-of-2 case */
++
++ loff_t chunkBase;
++
++ chunk /= dev->chunkDiv;
++
++ chunkBase = ((loff_t)chunk) * dev->nDataBytesPerChunk;
++ offset = (__u32)(addr - chunkBase);
++ }
++
++ *chunkOut = chunk;
++ *offsetOut = offset;
++}
++
++/* Function to return the number of shifts for a power of 2 greater than or equal
++ * to the given number
++ * Note we don't try to cater for all possible numbers and this does not have to
++ * be hellishly efficient.
++ */
++
++static __u32 ShiftsGE(__u32 x)
++{
++ int extraBits;
++ int nShifts;
++
++ nShifts = extraBits = 0;
++
++ while(x>1){
++ if(x & 1) extraBits++;
++ x>>=1;
++ nShifts++;
++ }
++
++ if(extraBits)
++ nShifts++;
++
++ return nShifts;
++}
++
++/* Function to return the number of shifts to get a 1 in bit 0
++ */
++
++static __u32 Shifts(__u32 x)
++{
++ int nShifts;
++
++ nShifts = 0;
++
++ if(!x) return 0;
++
++ while( !(x&1)){
++ x>>=1;
++ nShifts++;
++ }
++
++ return nShifts;
++}
++
++
++
++/*
++ * Temporary buffer manipulations.
++ */
++
++static int yaffs_InitialiseTempBuffers(yaffs_Device *dev)
++{
++ int i;
++ __u8 *buf = (__u8 *)1;
++
++ memset(dev->tempBuffer,0,sizeof(dev->tempBuffer));
++
++ for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) {
++ dev->tempBuffer[i].line = 0; /* not in use */
++ dev->tempBuffer[i].buffer = buf =
++ YMALLOC_DMA(dev->totalBytesPerChunk);
++ }
++
++ return buf ? YAFFS_OK : YAFFS_FAIL;
++
++}
++
++__u8 *yaffs_GetTempBuffer(yaffs_Device * dev, int lineNo)
++{
++ int i, j;
++
++ dev->tempInUse++;
++ if(dev->tempInUse > dev->maxTemp)
++ dev->maxTemp = dev->tempInUse;
++
++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
++ if (dev->tempBuffer[i].line == 0) {
++ dev->tempBuffer[i].line = lineNo;
++ if ((i + 1) > dev->maxTemp) {
++ dev->maxTemp = i + 1;
++ for (j = 0; j <= i; j++)
++ dev->tempBuffer[j].maxLine =
++ dev->tempBuffer[j].line;
++ }
++
++ return dev->tempBuffer[i].buffer;
++ }
++ }
++
++ T(YAFFS_TRACE_BUFFERS,
++ (TSTR("Out of temp buffers at line %d, other held by lines:"),
++ lineNo));
++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
++ T(YAFFS_TRACE_BUFFERS, (TSTR(" %d "), dev->tempBuffer[i].line));
++ }
++ T(YAFFS_TRACE_BUFFERS, (TSTR(" " TENDSTR)));
++
++ /*
++ * If we got here then we have to allocate an unmanaged one
++ * This is not good.
++ */
++
++ dev->unmanagedTempAllocations++;
++ return YMALLOC(dev->nDataBytesPerChunk);
++
++}
++
++void yaffs_ReleaseTempBuffer(yaffs_Device * dev, __u8 * buffer,
++ int lineNo)
++{
++ int i;
++
++ dev->tempInUse--;
++
++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
++ if (dev->tempBuffer[i].buffer == buffer) {
++ dev->tempBuffer[i].line = 0;
++ return;
++ }
++ }
++
++ if (buffer) {
++ /* assume it is an unmanaged one. */
++ T(YAFFS_TRACE_BUFFERS,
++ (TSTR("Releasing unmanaged temp buffer in line %d" TENDSTR),
++ lineNo));
++ YFREE(buffer);
++ dev->unmanagedTempDeallocations++;
++ }
++
++}
++
++/*
++ * Determine if we have a managed buffer.
++ */
++int yaffs_IsManagedTempBuffer(yaffs_Device * dev, const __u8 * buffer)
++{
++ int i;
++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
++ if (dev->tempBuffer[i].buffer == buffer)
++ return 1;
++
++ }
++
++ for (i = 0; i < dev->nShortOpCaches; i++) {
++ if( dev->srCache[i].data == buffer )
++ return 1;
++
++ }
++
++ if (buffer == dev->checkpointBuffer)
++ return 1;
++
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs: unmaged buffer detected.\n" TENDSTR)));
++ return 0;
++}
++
++
++
++/*
++ * Chunk bitmap manipulations
++ */
++
++static Y_INLINE __u8 *yaffs_BlockBits(yaffs_Device * dev, int blk)
++{
++ if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("**>> yaffs: BlockBits block %d is not valid" TENDSTR),
++ blk));
++ YBUG();
++ }
++ return dev->chunkBits +
++ (dev->chunkBitmapStride * (blk - dev->internalStartBlock));
++}
++
++static Y_INLINE void yaffs_VerifyChunkBitId(yaffs_Device *dev, int blk, int chunk)
++{
++ if(blk < dev->internalStartBlock || blk > dev->internalEndBlock ||
++ chunk < 0 || chunk >= dev->nChunksPerBlock) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("**>> yaffs: Chunk Id (%d:%d) invalid"TENDSTR),blk,chunk));
++ YBUG();
++ }
++}
++
++static Y_INLINE void yaffs_ClearChunkBits(yaffs_Device * dev, int blk)
++{
++ __u8 *blkBits = yaffs_BlockBits(dev, blk);
++
++ memset(blkBits, 0, dev->chunkBitmapStride);
++}
++
++static Y_INLINE void yaffs_ClearChunkBit(yaffs_Device * dev, int blk, int chunk)
++{
++ __u8 *blkBits = yaffs_BlockBits(dev, blk);
++
++ yaffs_VerifyChunkBitId(dev,blk,chunk);
++
++ blkBits[chunk / 8] &= ~(1 << (chunk & 7));
++}
++
++static Y_INLINE void yaffs_SetChunkBit(yaffs_Device * dev, int blk, int chunk)
++{
++ __u8 *blkBits = yaffs_BlockBits(dev, blk);
++
++ yaffs_VerifyChunkBitId(dev,blk,chunk);
++
++ blkBits[chunk / 8] |= (1 << (chunk & 7));
++}
++
++static Y_INLINE int yaffs_CheckChunkBit(yaffs_Device * dev, int blk, int chunk)
++{
++ __u8 *blkBits = yaffs_BlockBits(dev, blk);
++ yaffs_VerifyChunkBitId(dev,blk,chunk);
++
++ return (blkBits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0;
++}
++
++static Y_INLINE int yaffs_StillSomeChunkBits(yaffs_Device * dev, int blk)
++{
++ __u8 *blkBits = yaffs_BlockBits(dev, blk);
++ int i;
++ for (i = 0; i < dev->chunkBitmapStride; i++) {
++ if (*blkBits)
++ return 1;
++ blkBits++;
++ }
++ return 0;
++}
++
++static int yaffs_CountChunkBits(yaffs_Device * dev, int blk)
++{
++ __u8 *blkBits = yaffs_BlockBits(dev, blk);
++ int i;
++ int n = 0;
++ for (i = 0; i < dev->chunkBitmapStride; i++) {
++ __u8 x = *blkBits;
++ while(x){
++ if(x & 1)
++ n++;
++ x >>=1;
++ }
++
++ blkBits++;
++ }
++ return n;
++}
++
++/*
++ * Verification code
++ */
++
++static int yaffs_SkipVerification(yaffs_Device *dev)
++{
++ return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL));
++}
++
++static int yaffs_SkipFullVerification(yaffs_Device *dev)
++{
++ return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_FULL));
++}
++
++static int yaffs_SkipNANDVerification(yaffs_Device *dev)
++{
++ return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_NAND));
++}
++
++static const char * blockStateName[] = {
++"Unknown",
++"Needs scanning",
++"Scanning",
++"Empty",
++"Allocating",
++"Full",
++"Dirty",
++"Checkpoint",
++"Collecting",
++"Dead"
++};
++
++static void yaffs_VerifyBlock(yaffs_Device *dev,yaffs_BlockInfo *bi,int n)
++{
++ int actuallyUsed;
++ int inUse;
++
++ if(yaffs_SkipVerification(dev))
++ return;
++
++ /* Report illegal runtime states */
++ if(bi->blockState >= YAFFS_NUMBER_OF_BLOCK_STATES)
++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has undefined state %d"TENDSTR),n,bi->blockState));
++
++ switch(bi->blockState){
++ case YAFFS_BLOCK_STATE_UNKNOWN:
++ case YAFFS_BLOCK_STATE_SCANNING:
++ case YAFFS_BLOCK_STATE_NEEDS_SCANNING:
++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has bad run-state %s"TENDSTR),
++ n,blockStateName[bi->blockState]));
++ }
++
++ /* Check pages in use and soft deletions are legal */
++
++ actuallyUsed = bi->pagesInUse - bi->softDeletions;
++
++ if(bi->pagesInUse < 0 || bi->pagesInUse > dev->nChunksPerBlock ||
++ bi->softDeletions < 0 || bi->softDeletions > dev->nChunksPerBlock ||
++ actuallyUsed < 0 || actuallyUsed > dev->nChunksPerBlock)
++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has illegal values pagesInUsed %d softDeletions %d"TENDSTR),
++ n,bi->pagesInUse,bi->softDeletions));
++
++
++ /* Check chunk bitmap legal */
++ inUse = yaffs_CountChunkBits(dev,n);
++ if(inUse != bi->pagesInUse)
++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has inconsistent values pagesInUse %d counted chunk bits %d"TENDSTR),
++ n,bi->pagesInUse,inUse));
++
++ /* Check that the sequence number is valid.
++ * Ten million is legal, but is very unlikely
++ */
++ if(dev->isYaffs2 &&
++ (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING || bi->blockState == YAFFS_BLOCK_STATE_FULL) &&
++ (bi->sequenceNumber < YAFFS_LOWEST_SEQUENCE_NUMBER || bi->sequenceNumber > 10000000 ))
++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has suspect sequence number of %d"TENDSTR),
++ n,bi->sequenceNumber));
++
++}
++
++static void yaffs_VerifyCollectedBlock(yaffs_Device *dev,yaffs_BlockInfo *bi,int n)
++{
++ yaffs_VerifyBlock(dev,bi,n);
++
++ /* After collection the block should be in the erased state */
++ /* This will need to change if we do partial gc */
++
++ if(bi->blockState != YAFFS_BLOCK_STATE_COLLECTING &&
++ bi->blockState != YAFFS_BLOCK_STATE_EMPTY){
++ T(YAFFS_TRACE_ERROR,(TSTR("Block %d is in state %d after gc, should be erased"TENDSTR),
++ n,bi->blockState));
++ }
++}
++
++static void yaffs_VerifyBlocks(yaffs_Device *dev)
++{
++ int i;
++ int nBlocksPerState[YAFFS_NUMBER_OF_BLOCK_STATES];
++ int nIllegalBlockStates = 0;
++
++
++ if(yaffs_SkipVerification(dev))
++ return;
++
++ memset(nBlocksPerState,0,sizeof(nBlocksPerState));
++
++
++ for(i = dev->internalStartBlock; i <= dev->internalEndBlock; i++){
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i);
++ yaffs_VerifyBlock(dev,bi,i);
++
++ if(bi->blockState < YAFFS_NUMBER_OF_BLOCK_STATES)
++ nBlocksPerState[bi->blockState]++;
++ else
++ nIllegalBlockStates++;
++
++ }
++
++ T(YAFFS_TRACE_VERIFY,(TSTR(""TENDSTR)));
++ T(YAFFS_TRACE_VERIFY,(TSTR("Block summary"TENDSTR)));
++
++ T(YAFFS_TRACE_VERIFY,(TSTR("%d blocks have illegal states"TENDSTR),nIllegalBlockStates));
++ if(nBlocksPerState[YAFFS_BLOCK_STATE_ALLOCATING] > 1)
++ T(YAFFS_TRACE_VERIFY,(TSTR("Too many allocating blocks"TENDSTR)));
++
++ for(i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++)
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("%s %d blocks"TENDSTR),
++ blockStateName[i],nBlocksPerState[i]));
++
++ if(dev->blocksInCheckpoint != nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT])
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Checkpoint block count wrong dev %d count %d"TENDSTR),
++ dev->blocksInCheckpoint, nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT]));
++
++ if(dev->nErasedBlocks != nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY])
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Erased block count wrong dev %d count %d"TENDSTR),
++ dev->nErasedBlocks, nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY]));
++
++ if(nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING] > 1)
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Too many collecting blocks %d (max is 1)"TENDSTR),
++ nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING]));
++
++ T(YAFFS_TRACE_VERIFY,(TSTR(""TENDSTR)));
++
++}
++
++/*
++ * Verify the object header. oh must be valid, but obj and tags may be NULL in which
++ * case those tests will not be performed.
++ */
++static void yaffs_VerifyObjectHeader(yaffs_Object *obj, yaffs_ObjectHeader *oh, yaffs_ExtendedTags *tags, int parentCheck)
++{
++ if(obj && yaffs_SkipVerification(obj->myDev))
++ return;
++
++ if(!(tags && obj && oh)){
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Verifying object header tags %x obj %x oh %x"TENDSTR),
++ (__u32)tags,(__u32)obj,(__u32)oh));
++ return;
++ }
++
++ if(oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN ||
++ oh->type > YAFFS_OBJECT_TYPE_MAX)
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d header type is illegal value 0x%x"TENDSTR),
++ tags->objectId, oh->type));
++
++ if(tags->objectId != obj->objectId)
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d header mismatch objectId %d"TENDSTR),
++ tags->objectId, obj->objectId));
++
++
++ /*
++ * Check that the object's parent ids match if parentCheck requested.
++ *
++ * Tests do not apply to the root object.
++ */
++
++ if(parentCheck && tags->objectId > 1 && !obj->parent)
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d header mismatch parentId %d obj->parent is NULL"TENDSTR),
++ tags->objectId, oh->parentObjectId));
++
++
++ if(parentCheck && obj->parent &&
++ oh->parentObjectId != obj->parent->objectId &&
++ (oh->parentObjectId != YAFFS_OBJECTID_UNLINKED ||
++ obj->parent->objectId != YAFFS_OBJECTID_DELETED))
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d header mismatch parentId %d parentObjectId %d"TENDSTR),
++ tags->objectId, oh->parentObjectId, obj->parent->objectId));
++
++
++ if(tags->objectId > 1 && oh->name[0] == 0) /* Null name */
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d header name is NULL"TENDSTR),
++ obj->objectId));
++
++ if(tags->objectId > 1 && ((__u8)(oh->name[0])) == 0xff) /* Trashed name */
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d header name is 0xFF"TENDSTR),
++ obj->objectId));
++}
++
++
++
++static int yaffs_VerifyTnodeWorker(yaffs_Object * obj, yaffs_Tnode * tn,
++ __u32 level, int chunkOffset)
++{
++ int i;
++ yaffs_Device *dev = obj->myDev;
++ int ok = 1;
++
++ if (tn) {
++ if (level > 0) {
++
++ for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++){
++ if (tn->internal[i]) {
++ ok = yaffs_VerifyTnodeWorker(obj,
++ tn->internal[i],
++ level - 1,
++ (chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
++ }
++ }
++ } else if (level == 0) {
++ yaffs_ExtendedTags tags;
++ __u32 objectId = obj->objectId;
++
++ chunkOffset <<= YAFFS_TNODES_LEVEL0_BITS;
++
++ for(i = 0; i < YAFFS_NTNODES_LEVEL0; i++){
++ __u32 theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
++
++ if(theChunk > 0){
++ /* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),tags.objectId,tags.chunkId,theChunk)); */
++ yaffs_ReadChunkWithTagsFromNAND(dev,theChunk,NULL, &tags);
++ if(tags.objectId != objectId || tags.chunkId != chunkOffset){
++ T(~0,(TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
++ objectId, chunkOffset, theChunk,
++ tags.objectId, tags.chunkId));
++ }
++ }
++ chunkOffset++;
++ }
++ }
++ }
++
++ return ok;
++
++}
++
++
++static void yaffs_VerifyFile(yaffs_Object *obj)
++{
++ int requiredTallness;
++ int actualTallness;
++ __u32 lastChunk;
++ __u32 x;
++ __u32 i;
++ yaffs_Device *dev;
++ yaffs_ExtendedTags tags;
++ yaffs_Tnode *tn;
++ __u32 objectId;
++
++ if(!obj)
++ return;
++
++ if(yaffs_SkipVerification(obj->myDev))
++ return;
++
++ dev = obj->myDev;
++ objectId = obj->objectId;
++
++ /* Check file size is consistent with tnode depth */
++ lastChunk = obj->variant.fileVariant.fileSize / dev->nDataBytesPerChunk + 1;
++ x = lastChunk >> YAFFS_TNODES_LEVEL0_BITS;
++ requiredTallness = 0;
++ while (x> 0) {
++ x >>= YAFFS_TNODES_INTERNAL_BITS;
++ requiredTallness++;
++ }
++
++ actualTallness = obj->variant.fileVariant.topLevel;
++
++ if(requiredTallness > actualTallness )
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d had tnode tallness %d, needs to be %d"TENDSTR),
++ obj->objectId,actualTallness, requiredTallness));
++
++
++ /* Check that the chunks in the tnode tree are all correct.
++ * We do this by scanning through the tnode tree and
++ * checking the tags for every chunk match.
++ */
++
++ if(yaffs_SkipNANDVerification(dev))
++ return;
++
++ for(i = 1; i <= lastChunk; i++){
++ tn = yaffs_FindLevel0Tnode(dev, &obj->variant.fileVariant,i);
++
++ if (tn) {
++ __u32 theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
++ if(theChunk > 0){
++ /* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),objectId,i,theChunk)); */
++ yaffs_ReadChunkWithTagsFromNAND(dev,theChunk,NULL, &tags);
++ if(tags.objectId != objectId || tags.chunkId != i){
++ T(~0,(TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
++ objectId, i, theChunk,
++ tags.objectId, tags.chunkId));
++ }
++ }
++ }
++
++ }
++
++}
++
++
++static void yaffs_VerifyHardLink(yaffs_Object *obj)
++{
++ if(obj && yaffs_SkipVerification(obj->myDev))
++ return;
++
++ /* Verify sane equivalent object */
++}
++
++static void yaffs_VerifySymlink(yaffs_Object *obj)
++{
++ if(obj && yaffs_SkipVerification(obj->myDev))
++ return;
++
++ /* Verify symlink string */
++}
++
++static void yaffs_VerifySpecial(yaffs_Object *obj)
++{
++ if(obj && yaffs_SkipVerification(obj->myDev))
++ return;
++}
++
++static void yaffs_VerifyObject(yaffs_Object *obj)
++{
++ yaffs_Device *dev;
++
++ __u32 chunkMin;
++ __u32 chunkMax;
++
++ __u32 chunkIdOk;
++ __u32 chunkIsLive;
++
++ if(!obj)
++ return;
++
++ dev = obj->myDev;
++
++ if(yaffs_SkipVerification(dev))
++ return;
++
++ /* Check sane object header chunk */
++
++ chunkMin = dev->internalStartBlock * dev->nChunksPerBlock;
++ chunkMax = (dev->internalEndBlock+1) * dev->nChunksPerBlock - 1;
++
++ chunkIdOk = (((unsigned)(obj->hdrChunk)) >= chunkMin && ((unsigned)(obj->hdrChunk)) <= chunkMax);
++ chunkIsLive = chunkIdOk &&
++ yaffs_CheckChunkBit(dev,
++ obj->hdrChunk / dev->nChunksPerBlock,
++ obj->hdrChunk % dev->nChunksPerBlock);
++ if(!obj->fake &&
++ (!chunkIdOk || !chunkIsLive)) {
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d has chunkId %d %s %s"TENDSTR),
++ obj->objectId,obj->hdrChunk,
++ chunkIdOk ? "" : ",out of range",
++ chunkIsLive || !chunkIdOk ? "" : ",marked as deleted"));
++ }
++
++ if(chunkIdOk && chunkIsLive &&!yaffs_SkipNANDVerification(dev)) {
++ yaffs_ExtendedTags tags;
++ yaffs_ObjectHeader *oh;
++ __u8 *buffer = yaffs_GetTempBuffer(dev,__LINE__);
++
++ oh = (yaffs_ObjectHeader *)buffer;
++
++ yaffs_ReadChunkWithTagsFromNAND(dev, obj->hdrChunk,buffer, &tags);
++
++ yaffs_VerifyObjectHeader(obj,oh,&tags,1);
++
++ yaffs_ReleaseTempBuffer(dev,buffer,__LINE__);
++ }
++
++ /* Verify it has a parent */
++ if(obj && !obj->fake &&
++ (!obj->parent || obj->parent->myDev != dev)){
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d has parent pointer %p which does not look like an object"TENDSTR),
++ obj->objectId,obj->parent));
++ }
++
++ /* Verify parent is a directory */
++ if(obj->parent && obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY){
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d's parent is not a directory (type %d)"TENDSTR),
++ obj->objectId,obj->parent->variantType));
++ }
++
++ switch(obj->variantType){
++ case YAFFS_OBJECT_TYPE_FILE:
++ yaffs_VerifyFile(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ yaffs_VerifySymlink(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ yaffs_VerifyDirectory(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ yaffs_VerifyHardLink(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ yaffs_VerifySpecial(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ default:
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Obj %d has illegaltype %d"TENDSTR),
++ obj->objectId,obj->variantType));
++ break;
++ }
++
++
++}
++
++static void yaffs_VerifyObjects(yaffs_Device *dev)
++{
++ yaffs_Object *obj;
++ int i;
++ struct ylist_head *lh;
++
++ if(yaffs_SkipVerification(dev))
++ return;
++
++ /* Iterate through the objects in each hash entry */
++
++ for(i = 0; i < YAFFS_NOBJECT_BUCKETS; i++){
++ ylist_for_each(lh, &dev->objectBucket[i].list) {
++ if (lh) {
++ obj = ylist_entry(lh, yaffs_Object, hashLink);
++ yaffs_VerifyObject(obj);
++ }
++ }
++ }
++
++}
++
++
++/*
++ * Simple hash function. Needs to have a reasonable spread
++ */
++
++static Y_INLINE int yaffs_HashFunction(int n)
++{
++ n = abs(n);
++ return (n % YAFFS_NOBJECT_BUCKETS);
++}
++
++/*
++ * Access functions to useful fake objects.
++ * Note that root might have a presence in NAND if permissions are set.
++ */
++
++yaffs_Object *yaffs_Root(yaffs_Device * dev)
++{
++ return dev->rootDir;
++}
++
++yaffs_Object *yaffs_LostNFound(yaffs_Device * dev)
++{
++ return dev->lostNFoundDir;
++}
++
++
++/*
++ * Erased NAND checking functions
++ */
++
++int yaffs_CheckFF(__u8 * buffer, int nBytes)
++{
++ /* Horrible, slow implementation */
++ while (nBytes--) {
++ if (*buffer != 0xFF)
++ return 0;
++ buffer++;
++ }
++ return 1;
++}
++
++static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
++ int chunkInNAND)
++{
++
++ int retval = YAFFS_OK;
++ __u8 *data = yaffs_GetTempBuffer(dev, __LINE__);
++ yaffs_ExtendedTags tags;
++ int result;
++
++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunkInNAND, data, &tags);
++
++ if(tags.eccResult > YAFFS_ECC_RESULT_NO_ERROR)
++ retval = YAFFS_FAIL;
++
++
++ if (!yaffs_CheckFF(data, dev->nDataBytesPerChunk) || tags.chunkUsed) {
++ T(YAFFS_TRACE_NANDACCESS,
++ (TSTR("Chunk %d not erased" TENDSTR), chunkInNAND));
++ retval = YAFFS_FAIL;
++ }
++
++ yaffs_ReleaseTempBuffer(dev, data, __LINE__);
++
++ return retval;
++
++}
++
++static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
++ const __u8 * data,
++ yaffs_ExtendedTags * tags,
++ int useReserve)
++{
++ int attempts = 0;
++ int writeOk = 0;
++ int chunk;
++
++ yaffs_InvalidateCheckpoint(dev);
++
++ do {
++ yaffs_BlockInfo *bi = 0;
++ int erasedOk = 0;
++
++ chunk = yaffs_AllocateChunk(dev, useReserve, &bi);
++ if (chunk < 0) {
++ /* no space */
++ break;
++ }
++
++ /* First check this chunk is erased, if it needs
++ * checking. The checking policy (unless forced
++ * always on) is as follows:
++ *
++ * Check the first page we try to write in a block.
++ * If the check passes then we don't need to check any
++ * more. If the check fails, we check again...
++ * If the block has been erased, we don't need to check.
++ *
++ * However, if the block has been prioritised for gc,
++ * then we think there might be something odd about
++ * this block and stop using it.
++ *
++ * Rationale: We should only ever see chunks that have
++ * not been erased if there was a partially written
++ * chunk due to power loss. This checking policy should
++ * catch that case with very few checks and thus save a
++ * lot of checks that are most likely not needed.
++ */
++ if (bi->gcPrioritise) {
++ yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
++ /* try another chunk */
++ continue;
++ }
++
++ /* let's give it a try */
++ attempts++;
++
++#ifdef CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED
++ bi->skipErasedCheck = 0;
++#endif
++ if (!bi->skipErasedCheck) {
++ erasedOk = yaffs_CheckChunkErased(dev, chunk);
++ if (erasedOk != YAFFS_OK) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR ("**>> yaffs chunk %d was not erased"
++ TENDSTR), chunk));
++
++ /* try another chunk */
++ continue;
++ }
++ bi->skipErasedCheck = 1;
++ }
++
++ writeOk = yaffs_WriteChunkWithTagsToNAND(dev, chunk,
++ data, tags);
++ if (writeOk != YAFFS_OK) {
++ yaffs_HandleWriteChunkError(dev, chunk, erasedOk);
++ /* try another chunk */
++ continue;
++ }
++
++ /* Copy the data into the robustification buffer */
++ yaffs_HandleWriteChunkOk(dev, chunk, data, tags);
++
++ } while (writeOk != YAFFS_OK &&
++ (yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts));
++
++ if(!writeOk)
++ chunk = -1;
++
++ if (attempts > 1) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("**>> yaffs write required %d attempts" TENDSTR),
++ attempts));
++
++ dev->nRetriedWrites += (attempts - 1);
++ }
++
++ return chunk;
++}
++
++/*
++ * Block retiring for handling a broken block.
++ */
++
++static void yaffs_RetireBlock(yaffs_Device * dev, int blockInNAND)
++{
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
++
++ yaffs_InvalidateCheckpoint(dev);
++
++ yaffs_MarkBlockBad(dev, blockInNAND);
++
++ bi->blockState = YAFFS_BLOCK_STATE_DEAD;
++ bi->gcPrioritise = 0;
++ bi->needsRetiring = 0;
++
++ dev->nRetiredBlocks++;
++}
++
++/*
++ * Functions for robustisizing TODO
++ *
++ */
++
++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data,
++ const yaffs_ExtendedTags * tags)
++{
++}
++
++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
++ const yaffs_ExtendedTags * tags)
++{
++}
++
++void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi)
++{
++ if(!bi->gcPrioritise){
++ bi->gcPrioritise = 1;
++ dev->hasPendingPrioritisedGCs = 1;
++ bi->chunkErrorStrikes ++;
++
++ if(bi->chunkErrorStrikes > 3){
++ bi->needsRetiring = 1; /* Too many stikes, so retire this */
++ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Block struck out" TENDSTR)));
++
++ }
++
++ }
++}
++
++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND, int erasedOk)
++{
++
++ int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
++
++ yaffs_HandleChunkError(dev,bi);
++
++
++ if(erasedOk ) {
++ /* Was an actual write failure, so mark the block for retirement */
++ bi->needsRetiring = 1;
++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
++ (TSTR("**>> Block %d needs retiring" TENDSTR), blockInNAND));
++
++
++ }
++
++ /* Delete the chunk */
++ yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
++}
++
++
++/*---------------- Name handling functions ------------*/
++
++static __u16 yaffs_CalcNameSum(const YCHAR * name)
++{
++ __u16 sum = 0;
++ __u16 i = 1;
++
++ const YUCHAR *bname = (const YUCHAR *) name;
++ if (bname) {
++ while ((*bname) && (i < (YAFFS_MAX_NAME_LENGTH/2))) {
++
++#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
++ sum += yaffs_toupper(*bname) * i;
++#else
++ sum += (*bname) * i;
++#endif
++ i++;
++ bname++;
++ }
++ }
++
++ return sum;
++}
++
++static void yaffs_SetObjectName(yaffs_Object * obj, const YCHAR * name)
++{
++#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
++ memset(obj->shortName,0,sizeof (YCHAR) * (YAFFS_SHORT_NAME_LENGTH+1));
++ if (name && yaffs_strlen(name) <= YAFFS_SHORT_NAME_LENGTH) {
++ yaffs_strcpy(obj->shortName, name);
++ } else {
++ obj->shortName[0] = _Y('\0');
++ }
++#endif
++ obj->sum = yaffs_CalcNameSum(name);
++}
++
++/*-------------------- TNODES -------------------
++
++ * List of spare tnodes
++ * The list is hooked together using the first pointer
++ * in the tnode.
++ */
++
++/* yaffs_CreateTnodes creates a bunch more tnodes and
++ * adds them to the tnode free list.
++ * Don't use this function directly
++ */
++
++static int yaffs_CreateTnodes(yaffs_Device * dev, int nTnodes)
++{
++ int i;
++ int tnodeSize;
++ yaffs_Tnode *newTnodes;
++ __u8 *mem;
++ yaffs_Tnode *curr;
++ yaffs_Tnode *next;
++ yaffs_TnodeList *tnl;
++
++ if (nTnodes < 1)
++ return YAFFS_OK;
++
++ /* Calculate the tnode size in bytes for variable width tnode support.
++ * Must be a multiple of 32-bits */
++ tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
++
++ if(tnodeSize < sizeof(yaffs_Tnode))
++ tnodeSize = sizeof(yaffs_Tnode);
++
++
++ /* make these things */
++
++ newTnodes = YMALLOC(nTnodes * tnodeSize);
++ mem = (__u8 *)newTnodes;
++
++ if (!newTnodes) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("yaffs: Could not allocate Tnodes" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ /* Hook them into the free list */
++#if 0
++ for (i = 0; i < nTnodes - 1; i++) {
++ newTnodes[i].internal[0] = &newTnodes[i + 1];
++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
++ newTnodes[i].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
++#endif
++ }
++
++ newTnodes[nTnodes - 1].internal[0] = dev->freeTnodes;
++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
++ newTnodes[nTnodes - 1].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
++#endif
++ dev->freeTnodes = newTnodes;
++#else
++ /* New hookup for wide tnodes */
++ for(i = 0; i < nTnodes -1; i++) {
++ curr = (yaffs_Tnode *) &mem[i * tnodeSize];
++ next = (yaffs_Tnode *) &mem[(i+1) * tnodeSize];
++ curr->internal[0] = next;
++ }
++
++ curr = (yaffs_Tnode *) &mem[(nTnodes - 1) * tnodeSize];
++ curr->internal[0] = dev->freeTnodes;
++ dev->freeTnodes = (yaffs_Tnode *)mem;
++
++#endif
++
++
++ dev->nFreeTnodes += nTnodes;
++ dev->nTnodesCreated += nTnodes;
++
++ /* Now add this bunch of tnodes to a list for freeing up.
++ * NB If we can't add this to the management list it isn't fatal
++ * but it just means we can't free this bunch of tnodes later.
++ */
++
++ tnl = YMALLOC(sizeof(yaffs_TnodeList));
++ if (!tnl) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("yaffs: Could not add tnodes to management list" TENDSTR)));
++ return YAFFS_FAIL;
++
++ } else {
++ tnl->tnodes = newTnodes;
++ tnl->next = dev->allocatedTnodeList;
++ dev->allocatedTnodeList = tnl;
++ }
++
++ T(YAFFS_TRACE_ALLOCATE, (TSTR("yaffs: Tnodes added" TENDSTR)));
++
++ return YAFFS_OK;
++}
++
++/* GetTnode gets us a clean tnode. Tries to make allocate more if we run out */
++
++static yaffs_Tnode *yaffs_GetTnodeRaw(yaffs_Device * dev)
++{
++ yaffs_Tnode *tn = NULL;
++
++ /* If there are none left make more */
++ if (!dev->freeTnodes) {
++ yaffs_CreateTnodes(dev, YAFFS_ALLOCATION_NTNODES);
++ }
++
++ if (dev->freeTnodes) {
++ tn = dev->freeTnodes;
++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
++ if (tn->internal[YAFFS_NTNODES_INTERNAL] != (void *)1) {
++ /* Hoosterman, this thing looks like it isn't in the list */
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs: Tnode list bug 1" TENDSTR)));
++ }
++#endif
++ dev->freeTnodes = dev->freeTnodes->internal[0];
++ dev->nFreeTnodes--;
++ }
++
++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
++
++ return tn;
++}
++
++static yaffs_Tnode *yaffs_GetTnode(yaffs_Device * dev)
++{
++ yaffs_Tnode *tn = yaffs_GetTnodeRaw(dev);
++ int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
++
++ if(tnodeSize < sizeof(yaffs_Tnode))
++ tnodeSize = sizeof(yaffs_Tnode);
++
++ if(tn)
++ memset(tn, 0, tnodeSize);
++
++ return tn;
++}
++
++/* FreeTnode frees up a tnode and puts it back on the free list */
++static void yaffs_FreeTnode(yaffs_Device * dev, yaffs_Tnode * tn)
++{
++ if (tn) {
++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
++ if (tn->internal[YAFFS_NTNODES_INTERNAL] != 0) {
++ /* Hoosterman, this thing looks like it is already in the list */
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs: Tnode list bug 2" TENDSTR)));
++ }
++ tn->internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
++#endif
++ tn->internal[0] = dev->freeTnodes;
++ dev->freeTnodes = tn;
++ dev->nFreeTnodes++;
++ }
++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
++
++}
++
++static void yaffs_DeinitialiseTnodes(yaffs_Device * dev)
++{
++ /* Free the list of allocated tnodes */
++ yaffs_TnodeList *tmp;
++
++ while (dev->allocatedTnodeList) {
++ tmp = dev->allocatedTnodeList->next;
++
++ YFREE(dev->allocatedTnodeList->tnodes);
++ YFREE(dev->allocatedTnodeList);
++ dev->allocatedTnodeList = tmp;
++
++ }
++
++ dev->freeTnodes = NULL;
++ dev->nFreeTnodes = 0;
++}
++
++static void yaffs_InitialiseTnodes(yaffs_Device * dev)
++{
++ dev->allocatedTnodeList = NULL;
++ dev->freeTnodes = NULL;
++ dev->nFreeTnodes = 0;
++ dev->nTnodesCreated = 0;
++
++}
++
++
++void yaffs_PutLevel0Tnode(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos, unsigned val)
++{
++ __u32 *map = (__u32 *)tn;
++ __u32 bitInMap;
++ __u32 bitInWord;
++ __u32 wordInMap;
++ __u32 mask;
++
++ pos &= YAFFS_TNODES_LEVEL0_MASK;
++ val >>= dev->chunkGroupBits;
++
++ bitInMap = pos * dev->tnodeWidth;
++ wordInMap = bitInMap /32;
++ bitInWord = bitInMap & (32 -1);
++
++ mask = dev->tnodeMask << bitInWord;
++
++ map[wordInMap] &= ~mask;
++ map[wordInMap] |= (mask & (val << bitInWord));
++
++ if(dev->tnodeWidth > (32-bitInWord)) {
++ bitInWord = (32 - bitInWord);
++ wordInMap++;;
++ mask = dev->tnodeMask >> (/*dev->tnodeWidth -*/ bitInWord);
++ map[wordInMap] &= ~mask;
++ map[wordInMap] |= (mask & (val >> bitInWord));
++ }
++}
++
++static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos)
++{
++ __u32 *map = (__u32 *)tn;
++ __u32 bitInMap;
++ __u32 bitInWord;
++ __u32 wordInMap;
++ __u32 val;
++
++ pos &= YAFFS_TNODES_LEVEL0_MASK;
++
++ bitInMap = pos * dev->tnodeWidth;
++ wordInMap = bitInMap /32;
++ bitInWord = bitInMap & (32 -1);
++
++ val = map[wordInMap] >> bitInWord;
++
++ if(dev->tnodeWidth > (32-bitInWord)) {
++ bitInWord = (32 - bitInWord);
++ wordInMap++;;
++ val |= (map[wordInMap] << bitInWord);
++ }
++
++ val &= dev->tnodeMask;
++ val <<= dev->chunkGroupBits;
++
++ return val;
++}
++
++/* ------------------- End of individual tnode manipulation -----------------*/
++
++/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------
++ * The look up tree is represented by the top tnode and the number of topLevel
++ * in the tree. 0 means only the level 0 tnode is in the tree.
++ */
++
++/* FindLevel0Tnode finds the level 0 tnode, if one exists. */
++static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device * dev,
++ yaffs_FileStructure * fStruct,
++ __u32 chunkId)
++{
++
++ yaffs_Tnode *tn = fStruct->top;
++ __u32 i;
++ int requiredTallness;
++ int level = fStruct->topLevel;
++
++ /* Check sane level and chunk Id */
++ if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) {
++ return NULL;
++ }
++
++ if (chunkId > YAFFS_MAX_CHUNK_ID) {
++ return NULL;
++ }
++
++ /* First check we're tall enough (ie enough topLevel) */
++
++ i = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
++ requiredTallness = 0;
++ while (i) {
++ i >>= YAFFS_TNODES_INTERNAL_BITS;
++ requiredTallness++;
++ }
++
++ if (requiredTallness > fStruct->topLevel) {
++ /* Not tall enough, so we can't find it, return NULL. */
++ return NULL;
++ }
++
++ /* Traverse down to level 0 */
++ while (level > 0 && tn) {
++ tn = tn->
++ internal[(chunkId >>
++ ( YAFFS_TNODES_LEVEL0_BITS +
++ (level - 1) *
++ YAFFS_TNODES_INTERNAL_BITS)
++ ) &
++ YAFFS_TNODES_INTERNAL_MASK];
++ level--;
++
++ }
++
++ return tn;
++}
++
++/* AddOrFindLevel0Tnode finds the level 0 tnode if it exists, otherwise first expands the tree.
++ * This happens in two steps:
++ * 1. If the tree isn't tall enough, then make it taller.
++ * 2. Scan down the tree towards the level 0 tnode adding tnodes if required.
++ *
++ * Used when modifying the tree.
++ *
++ * If the tn argument is NULL, then a fresh tnode will be added otherwise the specified tn will
++ * be plugged into the ttree.
++ */
++
++static yaffs_Tnode *yaffs_AddOrFindLevel0Tnode(yaffs_Device * dev,
++ yaffs_FileStructure * fStruct,
++ __u32 chunkId,
++ yaffs_Tnode *passedTn)
++{
++
++ int requiredTallness;
++ int i;
++ int l;
++ yaffs_Tnode *tn;
++
++ __u32 x;
++
++
++ /* Check sane level and page Id */
++ if (fStruct->topLevel < 0 || fStruct->topLevel > YAFFS_TNODES_MAX_LEVEL) {
++ return NULL;
++ }
++
++ if (chunkId > YAFFS_MAX_CHUNK_ID) {
++ return NULL;
++ }
++
++ /* First check we're tall enough (ie enough topLevel) */
++
++ x = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
++ requiredTallness = 0;
++ while (x) {
++ x >>= YAFFS_TNODES_INTERNAL_BITS;
++ requiredTallness++;
++ }
++
++
++ if (requiredTallness > fStruct->topLevel) {
++ /* Not tall enough,gotta make the tree taller */
++ for (i = fStruct->topLevel; i < requiredTallness; i++) {
++
++ tn = yaffs_GetTnode(dev);
++
++ if (tn) {
++ tn->internal[0] = fStruct->top;
++ fStruct->top = tn;
++ } else {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("yaffs: no more tnodes" TENDSTR)));
++ }
++ }
++
++ fStruct->topLevel = requiredTallness;
++ }
++
++ /* Traverse down to level 0, adding anything we need */
++
++ l = fStruct->topLevel;
++ tn = fStruct->top;
++
++ if(l > 0) {
++ while (l > 0 && tn) {
++ x = (chunkId >>
++ ( YAFFS_TNODES_LEVEL0_BITS +
++ (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) &
++ YAFFS_TNODES_INTERNAL_MASK;
++
++
++ if((l>1) && !tn->internal[x]){
++ /* Add missing non-level-zero tnode */
++ tn->internal[x] = yaffs_GetTnode(dev);
++
++ } else if(l == 1) {
++ /* Looking from level 1 at level 0 */
++ if (passedTn) {
++ /* If we already have one, then release it.*/
++ if(tn->internal[x])
++ yaffs_FreeTnode(dev,tn->internal[x]);
++ tn->internal[x] = passedTn;
++
++ } else if(!tn->internal[x]) {
++ /* Don't have one, none passed in */
++ tn->internal[x] = yaffs_GetTnode(dev);
++ }
++ }
++
++ tn = tn->internal[x];
++ l--;
++ }
++ } else {
++ /* top is level 0 */
++ if(passedTn) {
++ memcpy(tn,passedTn,(dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8);
++ yaffs_FreeTnode(dev,passedTn);
++ }
++ }
++
++ return tn;
++}
++
++static int yaffs_FindChunkInGroup(yaffs_Device * dev, int theChunk,
++ yaffs_ExtendedTags * tags, int objectId,
++ int chunkInInode)
++{
++ int j;
++
++ for (j = 0; theChunk && j < dev->chunkGroupSize; j++) {
++ if (yaffs_CheckChunkBit
++ (dev, theChunk / dev->nChunksPerBlock,
++ theChunk % dev->nChunksPerBlock)) {
++ yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL,
++ tags);
++ if (yaffs_TagsMatch(tags, objectId, chunkInInode)) {
++ /* found it; */
++ return theChunk;
++
++ }
++ }
++ theChunk++;
++ }
++ return -1;
++}
++
++
++/* DeleteWorker scans backwards through the tnode tree and deletes all the
++ * chunks and tnodes in the file
++ * Returns 1 if the tree was deleted.
++ * Returns 0 if it stopped early due to hitting the limit and the delete is incomplete.
++ */
++
++static int yaffs_DeleteWorker(yaffs_Object * in, yaffs_Tnode * tn, __u32 level,
++ int chunkOffset, int *limit)
++{
++ int i;
++ int chunkInInode;
++ int theChunk;
++ yaffs_ExtendedTags tags;
++ int foundChunk;
++ yaffs_Device *dev = in->myDev;
++
++ int allDone = 1;
++
++ if (tn) {
++ if (level > 0) {
++
++ for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
++ i--) {
++ if (tn->internal[i]) {
++ if (limit && (*limit) < 0) {
++ allDone = 0;
++ } else {
++ allDone =
++ yaffs_DeleteWorker(in,
++ tn->
++ internal
++ [i],
++ level -
++ 1,
++ (chunkOffset
++ <<
++ YAFFS_TNODES_INTERNAL_BITS)
++ + i,
++ limit);
++ }
++ if (allDone) {
++ yaffs_FreeTnode(dev,
++ tn->
++ internal[i]);
++ tn->internal[i] = NULL;
++ }
++ }
++
++ }
++ return (allDone) ? 1 : 0;
++ } else if (level == 0) {
++ int hitLimit = 0;
++
++ for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0 && !hitLimit;
++ i--) {
++ theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
++ if (theChunk) {
++
++ chunkInInode =
++ (chunkOffset <<
++ YAFFS_TNODES_LEVEL0_BITS) + i;
++
++ foundChunk =
++ yaffs_FindChunkInGroup(dev,
++ theChunk,
++ &tags,
++ in->objectId,
++ chunkInInode);
++
++ if (foundChunk > 0) {
++ yaffs_DeleteChunk(dev,
++ foundChunk, 1,
++ __LINE__);
++ in->nDataChunks--;
++ if (limit) {
++ *limit = *limit - 1;
++ if (*limit <= 0) {
++ hitLimit = 1;
++ }
++ }
++
++ }
++
++ yaffs_PutLevel0Tnode(dev,tn,i,0);
++ }
++
++ }
++ return (i < 0) ? 1 : 0;
++
++ }
++
++ }
++
++ return 1;
++
++}
++
++static void yaffs_SoftDeleteChunk(yaffs_Device * dev, int chunk)
++{
++
++ yaffs_BlockInfo *theBlock;
++
++ T(YAFFS_TRACE_DELETION, (TSTR("soft delete chunk %d" TENDSTR), chunk));
++
++ theBlock = yaffs_GetBlockInfo(dev, chunk / dev->nChunksPerBlock);
++ if (theBlock) {
++ theBlock->softDeletions++;
++ dev->nFreeChunks++;
++ }
++}
++
++/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all the chunks in the file.
++ * All soft deleting does is increment the block's softdelete count and pulls the chunk out
++ * of the tnode.
++ * Thus, essentially this is the same as DeleteWorker except that the chunks are soft deleted.
++ */
++
++static int yaffs_SoftDeleteWorker(yaffs_Object * in, yaffs_Tnode * tn,
++ __u32 level, int chunkOffset)
++{
++ int i;
++ int theChunk;
++ int allDone = 1;
++ yaffs_Device *dev = in->myDev;
++
++ if (tn) {
++ if (level > 0) {
++
++ for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
++ i--) {
++ if (tn->internal[i]) {
++ allDone =
++ yaffs_SoftDeleteWorker(in,
++ tn->
++ internal[i],
++ level - 1,
++ (chunkOffset
++ <<
++ YAFFS_TNODES_INTERNAL_BITS)
++ + i);
++ if (allDone) {
++ yaffs_FreeTnode(dev,
++ tn->
++ internal[i]);
++ tn->internal[i] = NULL;
++ } else {
++ /* Hoosterman... how could this happen? */
++ }
++ }
++ }
++ return (allDone) ? 1 : 0;
++ } else if (level == 0) {
++
++ for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) {
++ theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
++ if (theChunk) {
++ /* Note this does not find the real chunk, only the chunk group.
++ * We make an assumption that a chunk group is not larger than
++ * a block.
++ */
++ yaffs_SoftDeleteChunk(dev, theChunk);
++ yaffs_PutLevel0Tnode(dev,tn,i,0);
++ }
++
++ }
++ return 1;
++
++ }
++
++ }
++
++ return 1;
++
++}
++
++static void yaffs_SoftDeleteFile(yaffs_Object * obj)
++{
++ if (obj->deleted &&
++ obj->variantType == YAFFS_OBJECT_TYPE_FILE && !obj->softDeleted) {
++ if (obj->nDataChunks <= 0) {
++ /* Empty file with no duplicate object headers, just delete it immediately */
++ yaffs_FreeTnode(obj->myDev,
++ obj->variant.fileVariant.top);
++ obj->variant.fileVariant.top = NULL;
++ T(YAFFS_TRACE_TRACING,
++ (TSTR("yaffs: Deleting empty file %d" TENDSTR),
++ obj->objectId));
++ yaffs_DoGenericObjectDeletion(obj);
++ } else {
++ yaffs_SoftDeleteWorker(obj,
++ obj->variant.fileVariant.top,
++ obj->variant.fileVariant.
++ topLevel, 0);
++ obj->softDeleted = 1;
++ }
++ }
++}
++
++/* Pruning removes any part of the file structure tree that is beyond the
++ * bounds of the file (ie that does not point to chunks).
++ *
++ * A file should only get pruned when its size is reduced.
++ *
++ * Before pruning, the chunks must be pulled from the tree and the
++ * level 0 tnode entries must be zeroed out.
++ * Could also use this for file deletion, but that's probably better handled
++ * by a special case.
++ */
++
++static yaffs_Tnode *yaffs_PruneWorker(yaffs_Device * dev, yaffs_Tnode * tn,
++ __u32 level, int del0)
++{
++ int i;
++ int hasData;
++
++ if (tn) {
++ hasData = 0;
++
++ for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) {
++ if (tn->internal[i] && level > 0) {
++ tn->internal[i] =
++ yaffs_PruneWorker(dev, tn->internal[i],
++ level - 1,
++ (i == 0) ? del0 : 1);
++ }
++
++ if (tn->internal[i]) {
++ hasData++;
++ }
++ }
++
++ if (hasData == 0 && del0) {
++ /* Free and return NULL */
++
++ yaffs_FreeTnode(dev, tn);
++ tn = NULL;
++ }
++
++ }
++
++ return tn;
++
++}
++
++static int yaffs_PruneFileStructure(yaffs_Device * dev,
++ yaffs_FileStructure * fStruct)
++{
++ int i;
++ int hasData;
++ int done = 0;
++ yaffs_Tnode *tn;
++
++ if (fStruct->topLevel > 0) {
++ fStruct->top =
++ yaffs_PruneWorker(dev, fStruct->top, fStruct->topLevel, 0);
++
++ /* Now we have a tree with all the non-zero branches NULL but the height
++ * is the same as it was.
++ * Let's see if we can trim internal tnodes to shorten the tree.
++ * We can do this if only the 0th element in the tnode is in use
++ * (ie all the non-zero are NULL)
++ */
++
++ while (fStruct->topLevel && !done) {
++ tn = fStruct->top;
++
++ hasData = 0;
++ for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) {
++ if (tn->internal[i]) {
++ hasData++;
++ }
++ }
++
++ if (!hasData) {
++ fStruct->top = tn->internal[0];
++ fStruct->topLevel--;
++ yaffs_FreeTnode(dev, tn);
++ } else {
++ done = 1;
++ }
++ }
++ }
++
++ return YAFFS_OK;
++}
++
++/*-------------------- End of File Structure functions.-------------------*/
++
++/* yaffs_CreateFreeObjects creates a bunch more objects and
++ * adds them to the object free list.
++ */
++static int yaffs_CreateFreeObjects(yaffs_Device * dev, int nObjects)
++{
++ int i;
++ yaffs_Object *newObjects;
++ yaffs_ObjectList *list;
++
++ if (nObjects < 1)
++ return YAFFS_OK;
++
++ /* make these things */
++ newObjects = YMALLOC(nObjects * sizeof(yaffs_Object));
++ list = YMALLOC(sizeof(yaffs_ObjectList));
++
++ if (!newObjects || !list) {
++ if(newObjects)
++ YFREE(newObjects);
++ if(list)
++ YFREE(list);
++ T(YAFFS_TRACE_ALLOCATE,
++ (TSTR("yaffs: Could not allocate more objects" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ /* Hook them into the free list */
++ for (i = 0; i < nObjects - 1; i++) {
++ newObjects[i].siblings.next =
++ (struct ylist_head *)(&newObjects[i + 1]);
++ }
++
++ newObjects[nObjects - 1].siblings.next = (void *)dev->freeObjects;
++ dev->freeObjects = newObjects;
++ dev->nFreeObjects += nObjects;
++ dev->nObjectsCreated += nObjects;
++
++ /* Now add this bunch of Objects to a list for freeing up. */
++
++ list->objects = newObjects;
++ list->next = dev->allocatedObjectList;
++ dev->allocatedObjectList = list;
++
++ return YAFFS_OK;
++}
++
++
++/* AllocateEmptyObject gets us a clean Object. Tries to make allocate more if we run out */
++static yaffs_Object *yaffs_AllocateEmptyObject(yaffs_Device * dev)
++{
++ yaffs_Object *tn = NULL;
++
++#ifdef VALGRIND_TEST
++ tn = YMALLOC(sizeof(yaffs_Object));
++#else
++ /* If there are none left make more */
++ if (!dev->freeObjects) {
++ yaffs_CreateFreeObjects(dev, YAFFS_ALLOCATION_NOBJECTS);
++ }
++
++ if (dev->freeObjects) {
++ tn = dev->freeObjects;
++ dev->freeObjects =
++ (yaffs_Object *) (dev->freeObjects->siblings.next);
++ dev->nFreeObjects--;
++ }
++#endif
++ if(tn){
++ /* Now sweeten it up... */
++
++ memset(tn, 0, sizeof(yaffs_Object));
++ tn->myDev = dev;
++ tn->hdrChunk = 0;
++ tn->variantType = YAFFS_OBJECT_TYPE_UNKNOWN;
++ YINIT_LIST_HEAD(&(tn->hardLinks));
++ YINIT_LIST_HEAD(&(tn->hashLink));
++ YINIT_LIST_HEAD(&tn->siblings);
++
++
++ /* Now make the directory sane */
++ if(dev->rootDir){
++ tn->parent = dev->rootDir;
++ ylist_add(&(tn->siblings),&dev->rootDir->variant.directoryVariant.children);
++ }
++
++ /* Add it to the lost and found directory.
++ * NB Can't put root or lostNFound in lostNFound so
++ * check if lostNFound exists first
++ */
++ if (dev->lostNFoundDir) {
++ yaffs_AddObjectToDirectory(dev->lostNFoundDir, tn);
++ }
++ }
++
++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
++
++ return tn;
++}
++
++static yaffs_Object *yaffs_CreateFakeDirectory(yaffs_Device * dev, int number,
++ __u32 mode)
++{
++
++ yaffs_Object *obj =
++ yaffs_CreateNewObject(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY);
++ if (obj) {
++ obj->fake = 1; /* it is fake so it might have no NAND presence... */
++ obj->renameAllowed = 0; /* ... and we're not allowed to rename it... */
++ obj->unlinkAllowed = 0; /* ... or unlink it */
++ obj->deleted = 0;
++ obj->unlinked = 0;
++ obj->yst_mode = mode;
++ obj->myDev = dev;
++ obj->hdrChunk = 0; /* Not a valid chunk. */
++ }
++
++ return obj;
++
++}
++
++static void yaffs_UnhashObject(yaffs_Object * tn)
++{
++ int bucket;
++ yaffs_Device *dev = tn->myDev;
++
++ /* If it is still linked into the bucket list, free from the list */
++ if (!ylist_empty(&tn->hashLink)) {
++ ylist_del_init(&tn->hashLink);
++ bucket = yaffs_HashFunction(tn->objectId);
++ dev->objectBucket[bucket].count--;
++ }
++
++}
++
++/* FreeObject frees up a Object and puts it back on the free list */
++static void yaffs_FreeObject(yaffs_Object * tn)
++{
++
++ yaffs_Device *dev = tn->myDev;
++
++
++ if(tn->parent)
++ YBUG();
++ if(!ylist_empty(&tn->siblings))
++ YBUG();
++
++
++#ifdef __KERNEL__
++ if (tn->myInode) {
++ /* We're still hooked up to a cached inode.
++ * Don't delete now, but mark for later deletion
++ */
++ tn->deferedFree = 1;
++ return;
++ }
++#endif
++
++ yaffs_UnhashObject(tn);
++
++#ifdef VALGRIND_TEST
++ YFREE(tn);
++#else
++ /* Link into the free list. */
++ tn->siblings.next = (struct ylist_head *)(dev->freeObjects);
++ dev->freeObjects = tn;
++ dev->nFreeObjects++;
++#endif
++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
++
++}
++
++#ifdef __KERNEL__
++
++void yaffs_HandleDeferedFree(yaffs_Object * obj)
++{
++ if (obj->deferedFree) {
++ yaffs_FreeObject(obj);
++ }
++}
++
++#endif
++
++static void yaffs_DeinitialiseObjects(yaffs_Device * dev)
++{
++ /* Free the list of allocated Objects */
++
++ yaffs_ObjectList *tmp;
++
++ while (dev->allocatedObjectList) {
++ tmp = dev->allocatedObjectList->next;
++ YFREE(dev->allocatedObjectList->objects);
++ YFREE(dev->allocatedObjectList);
++
++ dev->allocatedObjectList = tmp;
++ }
++
++ dev->freeObjects = NULL;
++ dev->nFreeObjects = 0;
++}
++
++static void yaffs_InitialiseObjects(yaffs_Device * dev)
++{
++ int i;
++
++ dev->allocatedObjectList = NULL;
++ dev->freeObjects = NULL;
++ dev->nFreeObjects = 0;
++
++ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) {
++ YINIT_LIST_HEAD(&dev->objectBucket[i].list);
++ dev->objectBucket[i].count = 0;
++ }
++
++}
++
++static int yaffs_FindNiceObjectBucket(yaffs_Device * dev)
++{
++ static int x = 0;
++ int i;
++ int l = 999;
++ int lowest = 999999;
++
++ /* First let's see if we can find one that's empty. */
++
++ for (i = 0; i < 10 && lowest > 0; i++) {
++ x++;
++ x %= YAFFS_NOBJECT_BUCKETS;
++ if (dev->objectBucket[x].count < lowest) {
++ lowest = dev->objectBucket[x].count;
++ l = x;
++ }
++
++ }
++
++ /* If we didn't find an empty list, then try
++ * looking a bit further for a short one
++ */
++
++ for (i = 0; i < 10 && lowest > 3; i++) {
++ x++;
++ x %= YAFFS_NOBJECT_BUCKETS;
++ if (dev->objectBucket[x].count < lowest) {
++ lowest = dev->objectBucket[x].count;
++ l = x;
++ }
++
++ }
++
++ return l;
++}
++
++static int yaffs_CreateNewObjectNumber(yaffs_Device * dev)
++{
++ int bucket = yaffs_FindNiceObjectBucket(dev);
++
++ /* Now find an object value that has not already been taken
++ * by scanning the list.
++ */
++
++ int found = 0;
++ struct ylist_head *i;
++
++ __u32 n = (__u32) bucket;
++
++ /* yaffs_CheckObjectHashSanity(); */
++
++ while (!found) {
++ found = 1;
++ n += YAFFS_NOBJECT_BUCKETS;
++ if (1 || dev->objectBucket[bucket].count > 0) {
++ ylist_for_each(i, &dev->objectBucket[bucket].list) {
++ /* If there is already one in the list */
++ if (i
++ && ylist_entry(i, yaffs_Object,
++ hashLink)->objectId == n) {
++ found = 0;
++ }
++ }
++ }
++ }
++
++
++ return n;
++}
++
++static void yaffs_HashObject(yaffs_Object * in)
++{
++ int bucket = yaffs_HashFunction(in->objectId);
++ yaffs_Device *dev = in->myDev;
++
++ ylist_add(&in->hashLink, &dev->objectBucket[bucket].list);
++ dev->objectBucket[bucket].count++;
++
++}
++
++yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device * dev, __u32 number)
++{
++ int bucket = yaffs_HashFunction(number);
++ struct ylist_head *i;
++ yaffs_Object *in;
++
++ ylist_for_each(i, &dev->objectBucket[bucket].list) {
++ /* Look if it is in the list */
++ if (i) {
++ in = ylist_entry(i, yaffs_Object, hashLink);
++ if (in->objectId == number) {
++#ifdef __KERNEL__
++ /* Don't tell the VFS about this one if it is defered free */
++ if (in->deferedFree)
++ return NULL;
++#endif
++
++ return in;
++ }
++ }
++ }
++
++ return NULL;
++}
++
++yaffs_Object *yaffs_CreateNewObject(yaffs_Device * dev, int number,
++ yaffs_ObjectType type)
++{
++
++ yaffs_Object *theObject;
++ yaffs_Tnode *tn = NULL;
++
++ if (number < 0) {
++ number = yaffs_CreateNewObjectNumber(dev);
++ }
++
++ theObject = yaffs_AllocateEmptyObject(dev);
++ if(!theObject)
++ return NULL;
++
++ if(type == YAFFS_OBJECT_TYPE_FILE){
++ tn = yaffs_GetTnode(dev);
++ if(!tn){
++ yaffs_FreeObject(theObject);
++ return NULL;
++ }
++ }
++
++
++
++ if (theObject) {
++ theObject->fake = 0;
++ theObject->renameAllowed = 1;
++ theObject->unlinkAllowed = 1;
++ theObject->objectId = number;
++ yaffs_HashObject(theObject);
++ theObject->variantType = type;
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_WinFileTimeNow(theObject->win_atime);
++ theObject->win_ctime[0] = theObject->win_mtime[0] =
++ theObject->win_atime[0];
++ theObject->win_ctime[1] = theObject->win_mtime[1] =
++ theObject->win_atime[1];
++
++#else
++
++ theObject->yst_atime = theObject->yst_mtime =
++ theObject->yst_ctime = Y_CURRENT_TIME;
++#endif
++
++#if 0
++ theObject->sum_prev = 12345;
++ theObject->sum_trailer = 6789;
++#endif
++
++ switch (type) {
++ case YAFFS_OBJECT_TYPE_FILE:
++ theObject->variant.fileVariant.fileSize = 0;
++ theObject->variant.fileVariant.scannedFileSize = 0;
++ theObject->variant.fileVariant.shrinkSize = 0xFFFFFFFF; /* max __u32 */
++ theObject->variant.fileVariant.topLevel = 0;
++ theObject->variant.fileVariant.top = tn;
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ YINIT_LIST_HEAD(&theObject->variant.directoryVariant.
++ children);
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ /* No action required */
++ break;
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ /* todo this should not happen */
++ break;
++ }
++ }
++
++ return theObject;
++}
++
++static yaffs_Object *yaffs_FindOrCreateObjectByNumber(yaffs_Device * dev,
++ int number,
++ yaffs_ObjectType type)
++{
++ yaffs_Object *theObject = NULL;
++
++ if (number > 0) {
++ theObject = yaffs_FindObjectByNumber(dev, number);
++ }
++
++ if (!theObject) {
++ theObject = yaffs_CreateNewObject(dev, number, type);
++ }
++
++ return theObject;
++
++}
++
++
++static YCHAR *yaffs_CloneString(const YCHAR * str)
++{
++ YCHAR *newStr = NULL;
++
++ if (str && *str) {
++ newStr = YMALLOC((yaffs_strlen(str) + 1) * sizeof(YCHAR));
++ if(newStr)
++ yaffs_strcpy(newStr, str);
++ }
++
++ return newStr;
++
++}
++
++/*
++ * Mknod (create) a new object.
++ * equivalentObject only has meaning for a hard link;
++ * aliasString only has meaning for a sumlink.
++ * rdev only has meaning for devices (a subset of special objects)
++ */
++
++static yaffs_Object *yaffs_MknodObject(yaffs_ObjectType type,
++ yaffs_Object * parent,
++ const YCHAR * name,
++ __u32 mode,
++ __u32 uid,
++ __u32 gid,
++ yaffs_Object * equivalentObject,
++ const YCHAR * aliasString, __u32 rdev)
++{
++ yaffs_Object *in;
++ YCHAR *str = NULL;
++
++ yaffs_Device *dev = parent->myDev;
++
++ /* Check if the entry exists. If it does then fail the call since we don't want a dup.*/
++ if (yaffs_FindObjectByName(parent, name)) {
++ return NULL;
++ }
++
++ in = yaffs_CreateNewObject(dev, -1, type);
++
++ if(!in)
++ return YAFFS_FAIL;
++
++ if(type == YAFFS_OBJECT_TYPE_SYMLINK){
++ str = yaffs_CloneString(aliasString);
++ if(!str){
++ yaffs_FreeObject(in);
++ return NULL;
++ }
++ }
++
++
++
++ if (in) {
++ in->hdrChunk = 0;
++ in->valid = 1;
++ in->variantType = type;
++
++ in->yst_mode = mode;
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_WinFileTimeNow(in->win_atime);
++ in->win_ctime[0] = in->win_mtime[0] = in->win_atime[0];
++ in->win_ctime[1] = in->win_mtime[1] = in->win_atime[1];
++
++#else
++ in->yst_atime = in->yst_mtime = in->yst_ctime = Y_CURRENT_TIME;
++
++ in->yst_rdev = rdev;
++ in->yst_uid = uid;
++ in->yst_gid = gid;
++#endif
++ in->nDataChunks = 0;
++
++ yaffs_SetObjectName(in, name);
++ in->dirty = 1;
++
++ yaffs_AddObjectToDirectory(parent, in);
++
++ in->myDev = parent->myDev;
++
++ switch (type) {
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ in->variant.symLinkVariant.alias = str;
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ in->variant.hardLinkVariant.equivalentObject =
++ equivalentObject;
++ in->variant.hardLinkVariant.equivalentObjectId =
++ equivalentObject->objectId;
++ ylist_add(&in->hardLinks, &equivalentObject->hardLinks);
++ break;
++ case YAFFS_OBJECT_TYPE_FILE:
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ /* do nothing */
++ break;
++ }
++
++ if (yaffs_UpdateObjectHeader(in, name, 0, 0, 0) < 0) {
++ /* Could not create the object header, fail the creation */
++ yaffs_DestroyObject(in);
++ in = NULL;
++ }
++
++ }
++
++ return in;
++}
++
++yaffs_Object *yaffs_MknodFile(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid)
++{
++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_FILE, parent, name, mode,
++ uid, gid, NULL, NULL, 0);
++}
++
++yaffs_Object *yaffs_MknodDirectory(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid)
++{
++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name,
++ mode, uid, gid, NULL, NULL, 0);
++}
++
++yaffs_Object *yaffs_MknodSpecial(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid, __u32 rdev)
++{
++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode,
++ uid, gid, NULL, NULL, rdev);
++}
++
++yaffs_Object *yaffs_MknodSymLink(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid,
++ const YCHAR * alias)
++{
++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode,
++ uid, gid, NULL, alias, 0);
++}
++
++/* yaffs_Link returns the object id of the equivalent object.*/
++yaffs_Object *yaffs_Link(yaffs_Object * parent, const YCHAR * name,
++ yaffs_Object * equivalentObject)
++{
++ /* Get the real object in case we were fed a hard link as an equivalent object */
++ equivalentObject = yaffs_GetEquivalentObject(equivalentObject);
++
++ if (yaffs_MknodObject
++ (YAFFS_OBJECT_TYPE_HARDLINK, parent, name, 0, 0, 0,
++ equivalentObject, NULL, 0)) {
++ return equivalentObject;
++ } else {
++ return NULL;
++ }
++
++}
++
++static int yaffs_ChangeObjectName(yaffs_Object * obj, yaffs_Object * newDir,
++ const YCHAR * newName, int force, int shadows)
++{
++ int unlinkOp;
++ int deleteOp;
++
++ yaffs_Object *existingTarget;
++
++ if (newDir == NULL) {
++ newDir = obj->parent; /* use the old directory */
++ }
++
++ if (newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("tragedy: yaffs_ChangeObjectName: newDir is not a directory"
++ TENDSTR)));
++ YBUG();
++ }
++
++ /* TODO: Do we need this different handling for YAFFS2 and YAFFS1?? */
++ if (obj->myDev->isYaffs2) {
++ unlinkOp = (newDir == obj->myDev->unlinkedDir);
++ } else {
++ unlinkOp = (newDir == obj->myDev->unlinkedDir
++ && obj->variantType == YAFFS_OBJECT_TYPE_FILE);
++ }
++
++ deleteOp = (newDir == obj->myDev->deletedDir);
++
++ existingTarget = yaffs_FindObjectByName(newDir, newName);
++
++ /* If the object is a file going into the unlinked directory,
++ * then it is OK to just stuff it in since duplicate names are allowed.
++ * else only proceed if the new name does not exist and if we're putting
++ * it into a directory.
++ */
++ if ((unlinkOp ||
++ deleteOp ||
++ force ||
++ (shadows > 0) ||
++ !existingTarget) &&
++ newDir->variantType == YAFFS_OBJECT_TYPE_DIRECTORY) {
++ yaffs_SetObjectName(obj, newName);
++ obj->dirty = 1;
++
++ yaffs_AddObjectToDirectory(newDir, obj);
++
++ if (unlinkOp)
++ obj->unlinked = 1;
++
++ /* If it is a deletion then we mark it as a shrink for gc purposes. */
++ if (yaffs_UpdateObjectHeader(obj, newName, 0, deleteOp, shadows)>= 0)
++ return YAFFS_OK;
++ }
++
++ return YAFFS_FAIL;
++}
++
++int yaffs_RenameObject(yaffs_Object * oldDir, const YCHAR * oldName,
++ yaffs_Object * newDir, const YCHAR * newName)
++{
++ yaffs_Object *obj=NULL;
++ yaffs_Object *existingTarget=NULL;
++ int force = 0;
++
++
++ if(!oldDir || oldDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
++ YBUG();
++ if(!newDir || newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
++ YBUG();
++
++#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
++ /* Special case for case insemsitive systems (eg. WinCE).
++ * While look-up is case insensitive, the name isn't.
++ * Therefore we might want to change x.txt to X.txt
++ */
++ if (oldDir == newDir && yaffs_strcmp(oldName, newName) == 0) {
++ force = 1;
++ }
++#endif
++
++ else if (yaffs_strlen(newName) > YAFFS_MAX_NAME_LENGTH)
++ /* ENAMETOOLONG */
++ return YAFFS_FAIL;
++
++ obj = yaffs_FindObjectByName(oldDir, oldName);
++
++ if (obj && obj->renameAllowed) {
++
++ /* Now do the handling for an existing target, if there is one */
++
++ existingTarget = yaffs_FindObjectByName(newDir, newName);
++ if (existingTarget &&
++ existingTarget->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
++ !ylist_empty(&existingTarget->variant.directoryVariant.children)) {
++ /* There is a target that is a non-empty directory, so we fail */
++ return YAFFS_FAIL; /* EEXIST or ENOTEMPTY */
++ } else if (existingTarget && existingTarget != obj) {
++ /* Nuke the target first, using shadowing,
++ * but only if it isn't the same object
++ */
++ yaffs_ChangeObjectName(obj, newDir, newName, force,
++ existingTarget->objectId);
++ yaffs_UnlinkObject(existingTarget);
++ }
++
++ return yaffs_ChangeObjectName(obj, newDir, newName, 1, 0);
++ }
++ return YAFFS_FAIL;
++}
++
++/*------------------------- Block Management and Page Allocation ----------------*/
++
++static int yaffs_InitialiseBlocks(yaffs_Device * dev)
++{
++ int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
++
++ dev->blockInfo = NULL;
++ dev->chunkBits = NULL;
++
++ dev->allocationBlock = -1; /* force it to get a new one */
++
++ /* If the first allocation strategy fails, thry the alternate one */
++ dev->blockInfo = YMALLOC(nBlocks * sizeof(yaffs_BlockInfo));
++ if(!dev->blockInfo){
++ dev->blockInfo = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockInfo));
++ dev->blockInfoAlt = 1;
++ }
++ else
++ dev->blockInfoAlt = 0;
++
++ if(dev->blockInfo){
++
++ /* Set up dynamic blockinfo stuff. */
++ dev->chunkBitmapStride = (dev->nChunksPerBlock + 7) / 8; /* round up bytes */
++ dev->chunkBits = YMALLOC(dev->chunkBitmapStride * nBlocks);
++ if(!dev->chunkBits){
++ dev->chunkBits = YMALLOC_ALT(dev->chunkBitmapStride * nBlocks);
++ dev->chunkBitsAlt = 1;
++ }
++ else
++ dev->chunkBitsAlt = 0;
++ }
++
++ if (dev->blockInfo && dev->chunkBits) {
++ memset(dev->blockInfo, 0, nBlocks * sizeof(yaffs_BlockInfo));
++ memset(dev->chunkBits, 0, dev->chunkBitmapStride * nBlocks);
++ return YAFFS_OK;
++ }
++
++ return YAFFS_FAIL;
++
++}
++
++static void yaffs_DeinitialiseBlocks(yaffs_Device * dev)
++{
++ if(dev->blockInfoAlt && dev->blockInfo)
++ YFREE_ALT(dev->blockInfo);
++ else if(dev->blockInfo)
++ YFREE(dev->blockInfo);
++
++ dev->blockInfoAlt = 0;
++
++ dev->blockInfo = NULL;
++
++ if(dev->chunkBitsAlt && dev->chunkBits)
++ YFREE_ALT(dev->chunkBits);
++ else if(dev->chunkBits)
++ YFREE(dev->chunkBits);
++ dev->chunkBitsAlt = 0;
++ dev->chunkBits = NULL;
++}
++
++static int yaffs_BlockNotDisqualifiedFromGC(yaffs_Device * dev,
++ yaffs_BlockInfo * bi)
++{
++ int i;
++ __u32 seq;
++ yaffs_BlockInfo *b;
++
++ if (!dev->isYaffs2)
++ return 1; /* disqualification only applies to yaffs2. */
++
++ if (!bi->hasShrinkHeader)
++ return 1; /* can gc */
++
++ /* Find the oldest dirty sequence number if we don't know it and save it
++ * so we don't have to keep recomputing it.
++ */
++ if (!dev->oldestDirtySequence) {
++ seq = dev->sequenceNumber;
++
++ for (i = dev->internalStartBlock; i <= dev->internalEndBlock;
++ i++) {
++ b = yaffs_GetBlockInfo(dev, i);
++ if (b->blockState == YAFFS_BLOCK_STATE_FULL &&
++ (b->pagesInUse - b->softDeletions) <
++ dev->nChunksPerBlock && b->sequenceNumber < seq) {
++ seq = b->sequenceNumber;
++ }
++ }
++ dev->oldestDirtySequence = seq;
++ }
++
++ /* Can't do gc of this block if there are any blocks older than this one that have
++ * discarded pages.
++ */
++ return (bi->sequenceNumber <= dev->oldestDirtySequence);
++
++}
++
++/* FindDiretiestBlock is used to select the dirtiest block (or close enough)
++ * for garbage collection.
++ */
++
++static int yaffs_FindBlockForGarbageCollection(yaffs_Device * dev,
++ int aggressive)
++{
++
++ int b = dev->currentDirtyChecker;
++
++ int i;
++ int iterations;
++ int dirtiest = -1;
++ int pagesInUse = 0;
++ int prioritised=0;
++ yaffs_BlockInfo *bi;
++ int pendingPrioritisedExist = 0;
++
++ /* First let's see if we need to grab a prioritised block */
++ if(dev->hasPendingPrioritisedGCs){
++ for(i = dev->internalStartBlock; i < dev->internalEndBlock && !prioritised; i++){
++
++ bi = yaffs_GetBlockInfo(dev, i);
++ //yaffs_VerifyBlock(dev,bi,i);
++
++ if(bi->gcPrioritise) {
++ pendingPrioritisedExist = 1;
++ if(bi->blockState == YAFFS_BLOCK_STATE_FULL &&
++ yaffs_BlockNotDisqualifiedFromGC(dev, bi)){
++ pagesInUse = (bi->pagesInUse - bi->softDeletions);
++ dirtiest = i;
++ prioritised = 1;
++ aggressive = 1; /* Fool the non-aggressive skip logiv below */
++ }
++ }
++ }
++
++ if(!pendingPrioritisedExist) /* None found, so we can clear this */
++ dev->hasPendingPrioritisedGCs = 0;
++ }
++
++ /* If we're doing aggressive GC then we are happy to take a less-dirty block, and
++ * search harder.
++ * else (we're doing a leasurely gc), then we only bother to do this if the
++ * block has only a few pages in use.
++ */
++
++ dev->nonAggressiveSkip--;
++
++ if (!aggressive && (dev->nonAggressiveSkip > 0)) {
++ return -1;
++ }
++
++ if(!prioritised)
++ pagesInUse =
++ (aggressive) ? dev->nChunksPerBlock : YAFFS_PASSIVE_GC_CHUNKS + 1;
++
++ if (aggressive) {
++ iterations =
++ dev->internalEndBlock - dev->internalStartBlock + 1;
++ } else {
++ iterations =
++ dev->internalEndBlock - dev->internalStartBlock + 1;
++ iterations = iterations / 16;
++ if (iterations > 200) {
++ iterations = 200;
++ }
++ }
++
++ for (i = 0; i <= iterations && pagesInUse > 0 && !prioritised; i++) {
++ b++;
++ if (b < dev->internalStartBlock || b > dev->internalEndBlock) {
++ b = dev->internalStartBlock;
++ }
++
++ if (b < dev->internalStartBlock || b > dev->internalEndBlock) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("**>> Block %d is not valid" TENDSTR), b));
++ YBUG();
++ }
++
++ bi = yaffs_GetBlockInfo(dev, b);
++
++#if 0
++ if (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT) {
++ dirtiest = b;
++ pagesInUse = 0;
++ }
++ else
++#endif
++
++ if (bi->blockState == YAFFS_BLOCK_STATE_FULL &&
++ (bi->pagesInUse - bi->softDeletions) < pagesInUse &&
++ yaffs_BlockNotDisqualifiedFromGC(dev, bi)) {
++ dirtiest = b;
++ pagesInUse = (bi->pagesInUse - bi->softDeletions);
++ }
++ }
++
++ dev->currentDirtyChecker = b;
++
++ if (dirtiest > 0) {
++ T(YAFFS_TRACE_GC,
++ (TSTR("GC Selected block %d with %d free, prioritised:%d" TENDSTR), dirtiest,
++ dev->nChunksPerBlock - pagesInUse,prioritised));
++ }
++
++ dev->oldestDirtySequence = 0;
++
++ if (dirtiest > 0) {
++ dev->nonAggressiveSkip = 4;
++ }
++
++ return dirtiest;
++}
++
++static void yaffs_BlockBecameDirty(yaffs_Device * dev, int blockNo)
++{
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockNo);
++
++ int erasedOk = 0;
++
++ /* If the block is still healthy erase it and mark as clean.
++ * If the block has had a data failure, then retire it.
++ */
++
++ T(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE,
++ (TSTR("yaffs_BlockBecameDirty block %d state %d %s"TENDSTR),
++ blockNo, bi->blockState, (bi->needsRetiring) ? "needs retiring" : ""));
++
++ bi->blockState = YAFFS_BLOCK_STATE_DIRTY;
++
++ if (!bi->needsRetiring) {
++ yaffs_InvalidateCheckpoint(dev);
++ erasedOk = yaffs_EraseBlockInNAND(dev, blockNo);
++ if (!erasedOk) {
++ dev->nErasureFailures++;
++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
++ (TSTR("**>> Erasure failed %d" TENDSTR), blockNo));
++ }
++ }
++
++ if (erasedOk &&
++ ((yaffs_traceMask & YAFFS_TRACE_ERASE) || !yaffs_SkipVerification(dev))) {
++ int i;
++ for (i = 0; i < dev->nChunksPerBlock; i++) {
++ if (!yaffs_CheckChunkErased
++ (dev, blockNo * dev->nChunksPerBlock + i)) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ (">>Block %d erasure supposedly OK, but chunk %d not erased"
++ TENDSTR), blockNo, i));
++ }
++ }
++ }
++
++ if (erasedOk) {
++ /* Clean it up... */
++ bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
++ dev->nErasedBlocks++;
++ bi->pagesInUse = 0;
++ bi->softDeletions = 0;
++ bi->hasShrinkHeader = 0;
++ bi->skipErasedCheck = 1; /* This is clean, so no need to check */
++ bi->gcPrioritise = 0;
++ yaffs_ClearChunkBits(dev, blockNo);
++
++ T(YAFFS_TRACE_ERASE,
++ (TSTR("Erased block %d" TENDSTR), blockNo));
++ } else {
++ dev->nFreeChunks -= dev->nChunksPerBlock; /* We lost a block of free space */
++
++ yaffs_RetireBlock(dev, blockNo);
++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
++ (TSTR("**>> Block %d retired" TENDSTR), blockNo));
++ }
++}
++
++static int yaffs_FindBlockForAllocation(yaffs_Device * dev)
++{
++ int i;
++
++ yaffs_BlockInfo *bi;
++
++ if (dev->nErasedBlocks < 1) {
++ /* Hoosterman we've got a problem.
++ * Can't get space to gc
++ */
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("yaffs tragedy: no more erased blocks" TENDSTR)));
++
++ return -1;
++ }
++
++ /* Find an empty block. */
++
++ for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
++ dev->allocationBlockFinder++;
++ if (dev->allocationBlockFinder < dev->internalStartBlock
++ || dev->allocationBlockFinder > dev->internalEndBlock) {
++ dev->allocationBlockFinder = dev->internalStartBlock;
++ }
++
++ bi = yaffs_GetBlockInfo(dev, dev->allocationBlockFinder);
++
++ if (bi->blockState == YAFFS_BLOCK_STATE_EMPTY) {
++ bi->blockState = YAFFS_BLOCK_STATE_ALLOCATING;
++ dev->sequenceNumber++;
++ bi->sequenceNumber = dev->sequenceNumber;
++ dev->nErasedBlocks--;
++ T(YAFFS_TRACE_ALLOCATE,
++ (TSTR("Allocated block %d, seq %d, %d left" TENDSTR),
++ dev->allocationBlockFinder, dev->sequenceNumber,
++ dev->nErasedBlocks));
++ return dev->allocationBlockFinder;
++ }
++ }
++
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("yaffs tragedy: no more erased blocks, but there should have been %d"
++ TENDSTR), dev->nErasedBlocks));
++
++ return -1;
++}
++
++
++
++static int yaffs_CalcCheckpointBlocksRequired(yaffs_Device *dev)
++{
++ if(!dev->nCheckpointBlocksRequired &&
++ dev->isYaffs2){
++ /* Not a valid value so recalculate */
++ int nBytes = 0;
++ int nBlocks;
++ int devBlocks = (dev->endBlock - dev->startBlock + 1);
++ int tnodeSize;
++
++ tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
++
++ if(tnodeSize < sizeof(yaffs_Tnode))
++ tnodeSize = sizeof(yaffs_Tnode);
++
++ nBytes += sizeof(yaffs_CheckpointValidity);
++ nBytes += sizeof(yaffs_CheckpointDevice);
++ nBytes += devBlocks * sizeof(yaffs_BlockInfo);
++ nBytes += devBlocks * dev->chunkBitmapStride;
++ nBytes += (sizeof(yaffs_CheckpointObject) + sizeof(__u32)) * (dev->nObjectsCreated - dev->nFreeObjects);
++ nBytes += (tnodeSize + sizeof(__u32)) * (dev->nTnodesCreated - dev->nFreeTnodes);
++ nBytes += sizeof(yaffs_CheckpointValidity);
++ nBytes += sizeof(__u32); /* checksum*/
++
++ /* Round up and add 2 blocks to allow for some bad blocks, so add 3 */
++
++ nBlocks = (nBytes/(dev->nDataBytesPerChunk * dev->nChunksPerBlock)) + 3;
++
++ dev->nCheckpointBlocksRequired = nBlocks;
++ }
++
++ return dev->nCheckpointBlocksRequired;
++}
++
++// Check if there's space to allocate...
++// Thinks.... do we need top make this ths same as yaffs_GetFreeChunks()?
++static int yaffs_CheckSpaceForAllocation(yaffs_Device * dev)
++{
++ int reservedChunks;
++ int reservedBlocks = dev->nReservedBlocks;
++ int checkpointBlocks;
++
++ if(dev->isYaffs2){
++ checkpointBlocks = yaffs_CalcCheckpointBlocksRequired(dev) -
++ dev->blocksInCheckpoint;
++ if(checkpointBlocks < 0)
++ checkpointBlocks = 0;
++ } else {
++ checkpointBlocks =0;
++ }
++
++ reservedChunks = ((reservedBlocks + checkpointBlocks) * dev->nChunksPerBlock);
++
++ return (dev->nFreeChunks > reservedChunks);
++}
++
++static int yaffs_AllocateChunk(yaffs_Device * dev, int useReserve, yaffs_BlockInfo **blockUsedPtr)
++{
++ int retVal;
++ yaffs_BlockInfo *bi;
++
++ if (dev->allocationBlock < 0) {
++ /* Get next block to allocate off */
++ dev->allocationBlock = yaffs_FindBlockForAllocation(dev);
++ dev->allocationPage = 0;
++ }
++
++ if (!useReserve && !yaffs_CheckSpaceForAllocation(dev)) {
++ /* Not enough space to allocate unless we're allowed to use the reserve. */
++ return -1;
++ }
++
++ if (dev->nErasedBlocks < dev->nReservedBlocks
++ && dev->allocationPage == 0) {
++ T(YAFFS_TRACE_ALLOCATE, (TSTR("Allocating reserve" TENDSTR)));
++ }
++
++ /* Next page please.... */
++ if (dev->allocationBlock >= 0) {
++ bi = yaffs_GetBlockInfo(dev, dev->allocationBlock);
++
++ retVal = (dev->allocationBlock * dev->nChunksPerBlock) +
++ dev->allocationPage;
++ bi->pagesInUse++;
++ yaffs_SetChunkBit(dev, dev->allocationBlock,
++ dev->allocationPage);
++
++ dev->allocationPage++;
++
++ dev->nFreeChunks--;
++
++ /* If the block is full set the state to full */
++ if (dev->allocationPage >= dev->nChunksPerBlock) {
++ bi->blockState = YAFFS_BLOCK_STATE_FULL;
++ dev->allocationBlock = -1;
++ }
++
++ if(blockUsedPtr)
++ *blockUsedPtr = bi;
++
++ return retVal;
++ }
++
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!" TENDSTR)));
++
++ return -1;
++}
++
++static int yaffs_GetErasedChunks(yaffs_Device * dev)
++{
++ int n;
++
++ n = dev->nErasedBlocks * dev->nChunksPerBlock;
++
++ if (dev->allocationBlock > 0) {
++ n += (dev->nChunksPerBlock - dev->allocationPage);
++ }
++
++ return n;
++
++}
++
++static int yaffs_GarbageCollectBlock(yaffs_Device * dev, int block, int wholeBlock)
++{
++ int oldChunk;
++ int newChunk;
++ int markNAND;
++ int retVal = YAFFS_OK;
++ int cleanups = 0;
++ int i;
++ int isCheckpointBlock;
++ int matchingChunk;
++ int maxCopies;
++
++ int chunksBefore = yaffs_GetErasedChunks(dev);
++ int chunksAfter;
++
++ yaffs_ExtendedTags tags;
++
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, block);
++
++ yaffs_Object *object;
++
++ isCheckpointBlock = (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT);
++
++ bi->blockState = YAFFS_BLOCK_STATE_COLLECTING;
++
++ T(YAFFS_TRACE_TRACING,
++ (TSTR("Collecting block %d, in use %d, shrink %d, wholeBlock %d" TENDSTR),
++ block,
++ bi->pagesInUse,
++ bi->hasShrinkHeader,
++ wholeBlock));
++
++ /*yaffs_VerifyFreeChunks(dev); */
++
++ bi->hasShrinkHeader = 0; /* clear the flag so that the block can erase */
++
++ /* Take off the number of soft deleted entries because
++ * they're going to get really deleted during GC.
++ */
++ dev->nFreeChunks -= bi->softDeletions;
++
++ dev->isDoingGC = 1;
++
++ if (isCheckpointBlock ||
++ !yaffs_StillSomeChunkBits(dev, block)) {
++ T(YAFFS_TRACE_TRACING,
++ (TSTR
++ ("Collecting block %d that has no chunks in use" TENDSTR),
++ block));
++ yaffs_BlockBecameDirty(dev, block);
++ } else {
++
++ __u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
++
++ yaffs_VerifyBlock(dev,bi,block);
++
++ maxCopies = (wholeBlock) ? dev->nChunksPerBlock : 10;
++ oldChunk = block * dev->nChunksPerBlock + dev->gcChunk;
++
++ for ( /* init already done */;
++ retVal == YAFFS_OK &&
++ dev->gcChunk < dev->nChunksPerBlock &&
++ (bi->blockState == YAFFS_BLOCK_STATE_COLLECTING)&&
++ maxCopies > 0;
++ dev->gcChunk++, oldChunk++) {
++ if (yaffs_CheckChunkBit(dev, block, dev->gcChunk)) {
++
++ /* This page is in use and might need to be copied off */
++
++ maxCopies--;
++
++ markNAND = 1;
++
++ yaffs_InitialiseTags(&tags);
++
++ yaffs_ReadChunkWithTagsFromNAND(dev, oldChunk,
++ buffer, &tags);
++
++ object =
++ yaffs_FindObjectByNumber(dev,
++ tags.objectId);
++
++ T(YAFFS_TRACE_GC_DETAIL,
++ (TSTR
++ ("Collecting chunk in block %d, %d %d %d " TENDSTR),
++ dev->gcChunk, tags.objectId, tags.chunkId,
++ tags.byteCount));
++
++ if(object && !yaffs_SkipVerification(dev)){
++ if(tags.chunkId == 0)
++ matchingChunk = object->hdrChunk;
++ else if(object->softDeleted)
++ matchingChunk = oldChunk; /* Defeat the test */
++ else
++ matchingChunk = yaffs_FindChunkInFile(object,tags.chunkId,NULL);
++
++ if(oldChunk != matchingChunk)
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("gc: page in gc mismatch: %d %d %d %d"TENDSTR),
++ oldChunk,matchingChunk,tags.objectId, tags.chunkId));
++
++ }
++
++ if (!object) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("page %d in gc has no object: %d %d %d "
++ TENDSTR), oldChunk,
++ tags.objectId, tags.chunkId, tags.byteCount));
++ }
++
++ if (object &&
++ object->deleted &&
++ object->softDeleted &&
++ tags.chunkId != 0) {
++ /* Data chunk in a soft deleted file, throw it away
++ * It's a soft deleted data chunk,
++ * No need to copy this, just forget about it and
++ * fix up the object.
++ */
++
++ object->nDataChunks--;
++
++ if (object->nDataChunks <= 0) {
++ /* remeber to clean up the object */
++ dev->gcCleanupList[cleanups] =
++ tags.objectId;
++ cleanups++;
++ }
++ markNAND = 0;
++ } else if (0
++ /* Todo object && object->deleted && object->nDataChunks == 0 */
++ ) {
++ /* Deleted object header with no data chunks.
++ * Can be discarded and the file deleted.
++ */
++ object->hdrChunk = 0;
++ yaffs_FreeTnode(object->myDev,
++ object->variant.
++ fileVariant.top);
++ object->variant.fileVariant.top = NULL;
++ yaffs_DoGenericObjectDeletion(object);
++
++ } else if (object) {
++ /* It's either a data chunk in a live file or
++ * an ObjectHeader, so we're interested in it.
++ * NB Need to keep the ObjectHeaders of deleted files
++ * until the whole file has been deleted off
++ */
++ tags.serialNumber++;
++
++ dev->nGCCopies++;
++
++ if (tags.chunkId == 0) {
++ /* It is an object Id,
++ * We need to nuke the shrinkheader flags first
++ * We no longer want the shrinkHeader flag since its work is done
++ * and if it is left in place it will mess up scanning.
++ * Also, clear out any shadowing stuff
++ */
++
++ yaffs_ObjectHeader *oh;
++ oh = (yaffs_ObjectHeader *)buffer;
++ oh->isShrink = 0;
++ tags.extraShadows = 0;
++ tags.extraIsShrinkHeader = 0;
++
++ yaffs_VerifyObjectHeader(object,oh,&tags,1);
++ }
++
++ newChunk =
++ yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &tags, 1);
++
++ if (newChunk < 0) {
++ retVal = YAFFS_FAIL;
++ } else {
++
++ /* Ok, now fix up the Tnodes etc. */
++
++ if (tags.chunkId == 0) {
++ /* It's a header */
++ object->hdrChunk = newChunk;
++ object->serial = tags.serialNumber;
++ } else {
++ /* It's a data chunk */
++ yaffs_PutChunkIntoFile
++ (object,
++ tags.chunkId,
++ newChunk, 0);
++ }
++ }
++ }
++
++ if(retVal == YAFFS_OK)
++ yaffs_DeleteChunk(dev, oldChunk, markNAND, __LINE__);
++
++ }
++ }
++
++ yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
++
++
++
++ /* Do any required cleanups */
++ for (i = 0; i < cleanups; i++) {
++ /* Time to delete the file too */
++ object =
++ yaffs_FindObjectByNumber(dev,
++ dev->gcCleanupList[i]);
++ if (object) {
++ yaffs_FreeTnode(dev,
++ object->variant.fileVariant.
++ top);
++ object->variant.fileVariant.top = NULL;
++ T(YAFFS_TRACE_GC,
++ (TSTR
++ ("yaffs: About to finally delete object %d"
++ TENDSTR), object->objectId));
++ yaffs_DoGenericObjectDeletion(object);
++ object->myDev->nDeletedFiles--;
++ }
++
++ }
++
++ }
++
++ yaffs_VerifyCollectedBlock(dev,bi,block);
++
++ if (chunksBefore >= (chunksAfter = yaffs_GetErasedChunks(dev))) {
++ T(YAFFS_TRACE_GC,
++ (TSTR
++ ("gc did not increase free chunks before %d after %d"
++ TENDSTR), chunksBefore, chunksAfter));
++ }
++
++ /* If the gc completed then clear the current gcBlock so that we find another. */
++ if(bi->blockState != YAFFS_BLOCK_STATE_COLLECTING){
++ dev->gcBlock = -1;
++ dev->gcChunk = 0;
++ }
++
++ dev->isDoingGC = 0;
++
++ return retVal;
++}
++
++/* New garbage collector
++ * If we're very low on erased blocks then we do aggressive garbage collection
++ * otherwise we do "leasurely" garbage collection.
++ * Aggressive gc looks further (whole array) and will accept less dirty blocks.
++ * Passive gc only inspects smaller areas and will only accept more dirty blocks.
++ *
++ * The idea is to help clear out space in a more spread-out manner.
++ * Dunno if it really does anything useful.
++ */
++static int yaffs_CheckGarbageCollection(yaffs_Device * dev)
++{
++ int block;
++ int aggressive;
++ int gcOk = YAFFS_OK;
++ int maxTries = 0;
++
++ int checkpointBlockAdjust;
++
++ if (dev->isDoingGC) {
++ /* Bail out so we don't get recursive gc */
++ return YAFFS_OK;
++ }
++
++ /* This loop should pass the first time.
++ * We'll only see looping here if the erase of the collected block fails.
++ */
++
++ do {
++ maxTries++;
++
++ checkpointBlockAdjust = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint;
++ if(checkpointBlockAdjust < 0)
++ checkpointBlockAdjust = 0;
++
++ if (dev->nErasedBlocks < (dev->nReservedBlocks + checkpointBlockAdjust + 2)) {
++ /* We need a block soon...*/
++ aggressive = 1;
++ } else {
++ /* We're in no hurry */
++ aggressive = 0;
++ }
++
++ if(dev->gcBlock <= 0){
++ dev->gcBlock = yaffs_FindBlockForGarbageCollection(dev, aggressive);
++ dev->gcChunk = 0;
++ }
++
++ block = dev->gcBlock;
++
++ if (block > 0) {
++ dev->garbageCollections++;
++ if (!aggressive) {
++ dev->passiveGarbageCollections++;
++ }
++
++ T(YAFFS_TRACE_GC,
++ (TSTR
++ ("yaffs: GC erasedBlocks %d aggressive %d" TENDSTR),
++ dev->nErasedBlocks, aggressive));
++
++ gcOk = yaffs_GarbageCollectBlock(dev,block,aggressive);
++ }
++
++ if (dev->nErasedBlocks < (dev->nReservedBlocks) && block > 0) {
++ T(YAFFS_TRACE_GC,
++ (TSTR
++ ("yaffs: GC !!!no reclaim!!! erasedBlocks %d after try %d block %d"
++ TENDSTR), dev->nErasedBlocks, maxTries, block));
++ }
++ } while ((dev->nErasedBlocks < dev->nReservedBlocks) &&
++ (block > 0) &&
++ (maxTries < 2));
++
++ return aggressive ? gcOk : YAFFS_OK;
++}
++
++/*------------------------- TAGS --------------------------------*/
++
++static int yaffs_TagsMatch(const yaffs_ExtendedTags * tags, int objectId,
++ int chunkInObject)
++{
++ return (tags->chunkId == chunkInObject &&
++ tags->objectId == objectId && !tags->chunkDeleted) ? 1 : 0;
++
++}
++
++
++/*-------------------- Data file manipulation -----------------*/
++
++static int yaffs_FindChunkInFile(yaffs_Object * in, int chunkInInode,
++ yaffs_ExtendedTags * tags)
++{
++ /*Get the Tnode, then get the level 0 offset chunk offset */
++ yaffs_Tnode *tn;
++ int theChunk = -1;
++ yaffs_ExtendedTags localTags;
++ int retVal = -1;
++
++ yaffs_Device *dev = in->myDev;
++
++ if (!tags) {
++ /* Passed a NULL, so use our own tags space */
++ tags = &localTags;
++ }
++
++ tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
++
++ if (tn) {
++ theChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode);
++
++ retVal =
++ yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
++ chunkInInode);
++ }
++ return retVal;
++}
++
++static int yaffs_FindAndDeleteChunkInFile(yaffs_Object * in, int chunkInInode,
++ yaffs_ExtendedTags * tags)
++{
++ /* Get the Tnode, then get the level 0 offset chunk offset */
++ yaffs_Tnode *tn;
++ int theChunk = -1;
++ yaffs_ExtendedTags localTags;
++
++ yaffs_Device *dev = in->myDev;
++ int retVal = -1;
++
++ if (!tags) {
++ /* Passed a NULL, so use our own tags space */
++ tags = &localTags;
++ }
++
++ tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
++
++ if (tn) {
++
++ theChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode);
++
++ retVal =
++ yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
++ chunkInInode);
++
++ /* Delete the entry in the filestructure (if found) */
++ if (retVal != -1) {
++ yaffs_PutLevel0Tnode(dev,tn,chunkInInode,0);
++ }
++ } else {
++ /*T(("No level 0 found for %d\n", chunkInInode)); */
++ }
++
++ if (retVal == -1) {
++ /* T(("Could not find %d to delete\n",chunkInInode)); */
++ }
++ return retVal;
++}
++
++#ifdef YAFFS_PARANOID
++
++static int yaffs_CheckFileSanity(yaffs_Object * in)
++{
++ int chunk;
++ int nChunks;
++ int fSize;
++ int failed = 0;
++ int objId;
++ yaffs_Tnode *tn;
++ yaffs_Tags localTags;
++ yaffs_Tags *tags = &localTags;
++ int theChunk;
++ int chunkDeleted;
++
++ if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
++ /* T(("Object not a file\n")); */
++ return YAFFS_FAIL;
++ }
++
++ objId = in->objectId;
++ fSize = in->variant.fileVariant.fileSize;
++ nChunks =
++ (fSize + in->myDev->nDataBytesPerChunk - 1) / in->myDev->nDataBytesPerChunk;
++
++ for (chunk = 1; chunk <= nChunks; chunk++) {
++ tn = yaffs_FindLevel0Tnode(in->myDev, &in->variant.fileVariant,
++ chunk);
++
++ if (tn) {
++
++ theChunk = yaffs_GetChunkGroupBase(dev,tn,chunk);
++
++ if (yaffs_CheckChunkBits
++ (dev, theChunk / dev->nChunksPerBlock,
++ theChunk % dev->nChunksPerBlock)) {
++
++ yaffs_ReadChunkTagsFromNAND(in->myDev, theChunk,
++ tags,
++ &chunkDeleted);
++ if (yaffs_TagsMatch
++ (tags, in->objectId, chunk, chunkDeleted)) {
++ /* found it; */
++
++ }
++ } else {
++
++ failed = 1;
++ }
++
++ } else {
++ /* T(("No level 0 found for %d\n", chunk)); */
++ }
++ }
++
++ return failed ? YAFFS_FAIL : YAFFS_OK;
++}
++
++#endif
++
++static int yaffs_PutChunkIntoFile(yaffs_Object * in, int chunkInInode,
++ int chunkInNAND, int inScan)
++{
++ /* NB inScan is zero unless scanning.
++ * For forward scanning, inScan is > 0;
++ * for backward scanning inScan is < 0
++ */
++
++ yaffs_Tnode *tn;
++ yaffs_Device *dev = in->myDev;
++ int existingChunk;
++ yaffs_ExtendedTags existingTags;
++ yaffs_ExtendedTags newTags;
++ unsigned existingSerial, newSerial;
++
++ if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
++ /* Just ignore an attempt at putting a chunk into a non-file during scanning
++ * If it is not during Scanning then something went wrong!
++ */
++ if (!inScan) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("yaffs tragedy:attempt to put data chunk into a non-file"
++ TENDSTR)));
++ YBUG();
++ }
++
++ yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
++ return YAFFS_OK;
++ }
++
++ tn = yaffs_AddOrFindLevel0Tnode(dev,
++ &in->variant.fileVariant,
++ chunkInInode,
++ NULL);
++ if (!tn) {
++ return YAFFS_FAIL;
++ }
++
++ existingChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode);
++
++ if (inScan != 0) {
++ /* If we're scanning then we need to test for duplicates
++ * NB This does not need to be efficient since it should only ever
++ * happen when the power fails during a write, then only one
++ * chunk should ever be affected.
++ *
++ * Correction for YAFFS2: This could happen quite a lot and we need to think about efficiency! TODO
++ * Update: For backward scanning we don't need to re-read tags so this is quite cheap.
++ */
++
++ if (existingChunk > 0) {
++ /* NB Right now existing chunk will not be real chunkId if the device >= 32MB
++ * thus we have to do a FindChunkInFile to get the real chunk id.
++ *
++ * We have a duplicate now we need to decide which one to use:
++ *
++ * Backwards scanning YAFFS2: The old one is what we use, dump the new one.
++ * Forward scanning YAFFS2: The new one is what we use, dump the old one.
++ * YAFFS1: Get both sets of tags and compare serial numbers.
++ */
++
++ if (inScan > 0) {
++ /* Only do this for forward scanning */
++ yaffs_ReadChunkWithTagsFromNAND(dev,
++ chunkInNAND,
++ NULL, &newTags);
++
++ /* Do a proper find */
++ existingChunk =
++ yaffs_FindChunkInFile(in, chunkInInode,
++ &existingTags);
++ }
++
++ if (existingChunk <= 0) {
++ /*Hoosterman - how did this happen? */
++
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("yaffs tragedy: existing chunk < 0 in scan"
++ TENDSTR)));
++
++ }
++
++ /* NB The deleted flags should be false, otherwise the chunks will
++ * not be loaded during a scan
++ */
++
++ if(inScan > 0) {
++ newSerial = newTags.serialNumber;
++ existingSerial = existingTags.serialNumber;
++ }
++
++ if ((inScan > 0) &&
++ (in->myDev->isYaffs2 ||
++ existingChunk <= 0 ||
++ ((existingSerial + 1) & 3) == newSerial)) {
++ /* Forward scanning.
++ * Use new
++ * Delete the old one and drop through to update the tnode
++ */
++ yaffs_DeleteChunk(dev, existingChunk, 1,
++ __LINE__);
++ } else {
++ /* Backward scanning or we want to use the existing one
++ * Use existing.
++ * Delete the new one and return early so that the tnode isn't changed
++ */
++ yaffs_DeleteChunk(dev, chunkInNAND, 1,
++ __LINE__);
++ return YAFFS_OK;
++ }
++ }
++
++ }
++
++ if (existingChunk == 0) {
++ in->nDataChunks++;
++ }
++
++ yaffs_PutLevel0Tnode(dev,tn,chunkInInode,chunkInNAND);
++
++ return YAFFS_OK;
++}
++
++static int yaffs_ReadChunkDataFromObject(yaffs_Object * in, int chunkInInode,
++ __u8 * buffer)
++{
++ int chunkInNAND = yaffs_FindChunkInFile(in, chunkInInode, NULL);
++
++ if (chunkInNAND >= 0) {
++ return yaffs_ReadChunkWithTagsFromNAND(in->myDev, chunkInNAND,
++ buffer,NULL);
++ } else {
++ T(YAFFS_TRACE_NANDACCESS,
++ (TSTR("Chunk %d not found zero instead" TENDSTR),
++ chunkInNAND));
++ /* get sane (zero) data if you read a hole */
++ memset(buffer, 0, in->myDev->nDataBytesPerChunk);
++ return 0;
++ }
++
++}
++
++void yaffs_DeleteChunk(yaffs_Device * dev, int chunkId, int markNAND, int lyn)
++{
++ int block;
++ int page;
++ yaffs_ExtendedTags tags;
++ yaffs_BlockInfo *bi;
++
++ if (chunkId <= 0)
++ return;
++
++
++ dev->nDeletions++;
++ block = chunkId / dev->nChunksPerBlock;
++ page = chunkId % dev->nChunksPerBlock;
++
++
++ if(!yaffs_CheckChunkBit(dev,block,page))
++ T(YAFFS_TRACE_VERIFY,
++ (TSTR("Deleting invalid chunk %d"TENDSTR),
++ chunkId));
++
++ bi = yaffs_GetBlockInfo(dev, block);
++
++ T(YAFFS_TRACE_DELETION,
++ (TSTR("line %d delete of chunk %d" TENDSTR), lyn, chunkId));
++
++ if (markNAND &&
++ bi->blockState != YAFFS_BLOCK_STATE_COLLECTING && !dev->isYaffs2) {
++
++ yaffs_InitialiseTags(&tags);
++
++ tags.chunkDeleted = 1;
++
++ yaffs_WriteChunkWithTagsToNAND(dev, chunkId, NULL, &tags);
++ yaffs_HandleUpdateChunk(dev, chunkId, &tags);
++ } else {
++ dev->nUnmarkedDeletions++;
++ }
++
++ /* Pull out of the management area.
++ * If the whole block became dirty, this will kick off an erasure.
++ */
++ if (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING ||
++ bi->blockState == YAFFS_BLOCK_STATE_FULL ||
++ bi->blockState == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
++ bi->blockState == YAFFS_BLOCK_STATE_COLLECTING) {
++ dev->nFreeChunks++;
++
++ yaffs_ClearChunkBit(dev, block, page);
++
++ bi->pagesInUse--;
++
++ if (bi->pagesInUse == 0 &&
++ !bi->hasShrinkHeader &&
++ bi->blockState != YAFFS_BLOCK_STATE_ALLOCATING &&
++ bi->blockState != YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
++ yaffs_BlockBecameDirty(dev, block);
++ }
++
++ } else {
++ /* T(("Bad news deleting chunk %d\n",chunkId)); */
++ }
++
++}
++
++static int yaffs_WriteChunkDataToObject(yaffs_Object * in, int chunkInInode,
++ const __u8 * buffer, int nBytes,
++ int useReserve)
++{
++ /* Find old chunk Need to do this to get serial number
++ * Write new one and patch into tree.
++ * Invalidate old tags.
++ */
++
++ int prevChunkId;
++ yaffs_ExtendedTags prevTags;
++
++ int newChunkId;
++ yaffs_ExtendedTags newTags;
++
++ yaffs_Device *dev = in->myDev;
++
++ yaffs_CheckGarbageCollection(dev);
++
++ /* Get the previous chunk at this location in the file if it exists */
++ prevChunkId = yaffs_FindChunkInFile(in, chunkInInode, &prevTags);
++
++ /* Set up new tags */
++ yaffs_InitialiseTags(&newTags);
++
++ newTags.chunkId = chunkInInode;
++ newTags.objectId = in->objectId;
++ newTags.serialNumber =
++ (prevChunkId >= 0) ? prevTags.serialNumber + 1 : 1;
++ newTags.byteCount = nBytes;
++
++ if(nBytes < 1 || nBytes > dev->totalBytesPerChunk){
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("Writing %d bytes to chunk!!!!!!!!!" TENDSTR), nBytes));
++ while(1){}
++ }
++
++
++
++ newChunkId =
++ yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
++ useReserve);
++
++ if (newChunkId >= 0) {
++ yaffs_PutChunkIntoFile(in, chunkInInode, newChunkId, 0);
++
++ if (prevChunkId >= 0) {
++ yaffs_DeleteChunk(dev, prevChunkId, 1, __LINE__);
++
++ }
++
++ yaffs_CheckFileSanity(in);
++ }
++ return newChunkId;
++
++}
++
++/* UpdateObjectHeader updates the header on NAND for an object.
++ * If name is not NULL, then that new name is used.
++ */
++int yaffs_UpdateObjectHeader(yaffs_Object * in, const YCHAR * name, int force,
++ int isShrink, int shadows)
++{
++
++ yaffs_BlockInfo *bi;
++
++ yaffs_Device *dev = in->myDev;
++
++ int prevChunkId;
++ int retVal = 0;
++ int result = 0;
++
++ int newChunkId;
++ yaffs_ExtendedTags newTags;
++ yaffs_ExtendedTags oldTags;
++
++ __u8 *buffer = NULL;
++ YCHAR oldName[YAFFS_MAX_NAME_LENGTH + 1];
++
++ yaffs_ObjectHeader *oh = NULL;
++
++ yaffs_strcpy(oldName,_Y("silly old name"));
++
++
++ if (!in->fake ||
++ in == dev->rootDir || /* The rootDir should also be saved */
++ force) {
++
++ yaffs_CheckGarbageCollection(dev);
++ yaffs_CheckObjectDetailsLoaded(in);
++
++ buffer = yaffs_GetTempBuffer(in->myDev, __LINE__);
++ oh = (yaffs_ObjectHeader *) buffer;
++
++ prevChunkId = in->hdrChunk;
++
++ if (prevChunkId > 0) {
++ result = yaffs_ReadChunkWithTagsFromNAND(dev, prevChunkId,
++ buffer, &oldTags);
++
++ yaffs_VerifyObjectHeader(in,oh,&oldTags,0);
++
++ memcpy(oldName, oh->name, sizeof(oh->name));
++ }
++
++ memset(buffer, 0xFF, dev->nDataBytesPerChunk);
++
++ oh->type = in->variantType;
++ oh->yst_mode = in->yst_mode;
++ oh->shadowsObject = oh->inbandShadowsObject = shadows;
++
++#ifdef CONFIG_YAFFS_WINCE
++ oh->win_atime[0] = in->win_atime[0];
++ oh->win_ctime[0] = in->win_ctime[0];
++ oh->win_mtime[0] = in->win_mtime[0];
++ oh->win_atime[1] = in->win_atime[1];
++ oh->win_ctime[1] = in->win_ctime[1];
++ oh->win_mtime[1] = in->win_mtime[1];
++#else
++ oh->yst_uid = in->yst_uid;
++ oh->yst_gid = in->yst_gid;
++ oh->yst_atime = in->yst_atime;
++ oh->yst_mtime = in->yst_mtime;
++ oh->yst_ctime = in->yst_ctime;
++ oh->yst_rdev = in->yst_rdev;
++#endif
++ if (in->parent) {
++ oh->parentObjectId = in->parent->objectId;
++ } else {
++ oh->parentObjectId = 0;
++ }
++
++ if (name && *name) {
++ memset(oh->name, 0, sizeof(oh->name));
++ yaffs_strncpy(oh->name, name, YAFFS_MAX_NAME_LENGTH);
++ } else if (prevChunkId>=0) {
++ memcpy(oh->name, oldName, sizeof(oh->name));
++ } else {
++ memset(oh->name, 0, sizeof(oh->name));
++ }
++
++ oh->isShrink = isShrink;
++
++ switch (in->variantType) {
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ /* Should not happen */
++ break;
++ case YAFFS_OBJECT_TYPE_FILE:
++ oh->fileSize =
++ (oh->parentObjectId == YAFFS_OBJECTID_DELETED
++ || oh->parentObjectId ==
++ YAFFS_OBJECTID_UNLINKED) ? 0 : in->variant.
++ fileVariant.fileSize;
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ oh->equivalentObjectId =
++ in->variant.hardLinkVariant.equivalentObjectId;
++ break;
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ /* Do nothing */
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ /* Do nothing */
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ yaffs_strncpy(oh->alias,
++ in->variant.symLinkVariant.alias,
++ YAFFS_MAX_ALIAS_LENGTH);
++ oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0;
++ break;
++ }
++
++ /* Tags */
++ yaffs_InitialiseTags(&newTags);
++ in->serial++;
++ newTags.chunkId = 0;
++ newTags.objectId = in->objectId;
++ newTags.serialNumber = in->serial;
++
++ /* Add extra info for file header */
++
++ newTags.extraHeaderInfoAvailable = 1;
++ newTags.extraParentObjectId = oh->parentObjectId;
++ newTags.extraFileLength = oh->fileSize;
++ newTags.extraIsShrinkHeader = oh->isShrink;
++ newTags.extraEquivalentObjectId = oh->equivalentObjectId;
++ newTags.extraShadows = (oh->shadowsObject > 0) ? 1 : 0;
++ newTags.extraObjectType = in->variantType;
++
++ yaffs_VerifyObjectHeader(in,oh,&newTags,1);
++
++ /* Create new chunk in NAND */
++ newChunkId =
++ yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
++ (prevChunkId >= 0) ? 1 : 0);
++
++ if (newChunkId >= 0) {
++
++ in->hdrChunk = newChunkId;
++
++ if (prevChunkId >= 0) {
++ yaffs_DeleteChunk(dev, prevChunkId, 1,
++ __LINE__);
++ }
++
++ if(!yaffs_ObjectHasCachedWriteData(in))
++ in->dirty = 0;
++
++ /* If this was a shrink, then mark the block that the chunk lives on */
++ if (isShrink) {
++ bi = yaffs_GetBlockInfo(in->myDev,
++ newChunkId /in->myDev-> nChunksPerBlock);
++ bi->hasShrinkHeader = 1;
++ }
++
++ }
++
++ retVal = newChunkId;
++
++ }
++
++ if (buffer)
++ yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
++
++ return retVal;
++}
++
++/*------------------------ Short Operations Cache ----------------------------------------
++ * In many situations where there is no high level buffering (eg WinCE) a lot of
++ * reads might be short sequential reads, and a lot of writes may be short
++ * sequential writes. eg. scanning/writing a jpeg file.
++ * In these cases, a short read/write cache can provide a huge perfomance benefit
++ * with dumb-as-a-rock code.
++ * In Linux, the page cache provides read buffering aand the short op cache provides write
++ * buffering.
++ *
++ * There are a limited number (~10) of cache chunks per device so that we don't
++ * need a very intelligent search.
++ */
++
++static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj)
++{
++ yaffs_Device *dev = obj->myDev;
++ int i;
++ yaffs_ChunkCache *cache;
++ int nCaches = obj->myDev->nShortOpCaches;
++
++ for(i = 0; i < nCaches; i++){
++ cache = &dev->srCache[i];
++ if (cache->object == obj &&
++ cache->dirty)
++ return 1;
++ }
++
++ return 0;
++}
++
++
++static void yaffs_FlushFilesChunkCache(yaffs_Object * obj)
++{
++ yaffs_Device *dev = obj->myDev;
++ int lowest = -99; /* Stop compiler whining. */
++ int i;
++ yaffs_ChunkCache *cache;
++ int chunkWritten = 0;
++ int nCaches = obj->myDev->nShortOpCaches;
++
++ if (nCaches > 0) {
++ do {
++ cache = NULL;
++
++ /* Find the dirty cache for this object with the lowest chunk id. */
++ for (i = 0; i < nCaches; i++) {
++ if (dev->srCache[i].object == obj &&
++ dev->srCache[i].dirty) {
++ if (!cache
++ || dev->srCache[i].chunkId <
++ lowest) {
++ cache = &dev->srCache[i];
++ lowest = cache->chunkId;
++ }
++ }
++ }
++
++ if (cache && !cache->locked) {
++ /* Write it out and free it up */
++
++ chunkWritten =
++ yaffs_WriteChunkDataToObject(cache->object,
++ cache->chunkId,
++ cache->data,
++ cache->nBytes,
++ 1);
++ cache->dirty = 0;
++ cache->object = NULL;
++ }
++
++ } while (cache && chunkWritten > 0);
++
++ if (cache) {
++ /* Hoosterman, disk full while writing cache out. */
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("yaffs tragedy: no space during cache write" TENDSTR)));
++
++ }
++ }
++
++}
++
++/*yaffs_FlushEntireDeviceCache(dev)
++ *
++ *
++ */
++
++void yaffs_FlushEntireDeviceCache(yaffs_Device *dev)
++{
++ yaffs_Object *obj;
++ int nCaches = dev->nShortOpCaches;
++ int i;
++
++ /* Find a dirty object in the cache and flush it...
++ * until there are no further dirty objects.
++ */
++ do {
++ obj = NULL;
++ for( i = 0; i < nCaches && !obj; i++) {
++ if (dev->srCache[i].object &&
++ dev->srCache[i].dirty)
++ obj = dev->srCache[i].object;
++
++ }
++ if(obj)
++ yaffs_FlushFilesChunkCache(obj);
++
++ } while(obj);
++
++}
++
++
++/* Grab us a cache chunk for use.
++ * First look for an empty one.
++ * Then look for the least recently used non-dirty one.
++ * Then look for the least recently used dirty one...., flush and look again.
++ */
++static yaffs_ChunkCache *yaffs_GrabChunkCacheWorker(yaffs_Device * dev)
++{
++ int i;
++
++ if (dev->nShortOpCaches > 0) {
++ for (i = 0; i < dev->nShortOpCaches; i++) {
++ if (!dev->srCache[i].object)
++ return &dev->srCache[i];
++ }
++ }
++
++ return NULL;
++}
++
++static yaffs_ChunkCache *yaffs_GrabChunkCache(yaffs_Device * dev)
++{
++ yaffs_ChunkCache *cache;
++ yaffs_Object *theObj;
++ int usage;
++ int i;
++ int pushout;
++
++ if (dev->nShortOpCaches > 0) {
++ /* Try find a non-dirty one... */
++
++ cache = yaffs_GrabChunkCacheWorker(dev);
++
++ if (!cache) {
++ /* They were all dirty, find the last recently used object and flush
++ * its cache, then find again.
++ * NB what's here is not very accurate, we actually flush the object
++ * the last recently used page.
++ */
++
++ /* With locking we can't assume we can use entry zero */
++
++ theObj = NULL;
++ usage = -1;
++ cache = NULL;
++ pushout = -1;
++
++ for (i = 0; i < dev->nShortOpCaches; i++) {
++ if (dev->srCache[i].object &&
++ !dev->srCache[i].locked &&
++ (dev->srCache[i].lastUse < usage || !cache))
++ {
++ usage = dev->srCache[i].lastUse;
++ theObj = dev->srCache[i].object;
++ cache = &dev->srCache[i];
++ pushout = i;
++ }
++ }
++
++ if (!cache || cache->dirty) {
++ /* Flush and try again */
++ yaffs_FlushFilesChunkCache(theObj);
++ cache = yaffs_GrabChunkCacheWorker(dev);
++ }
++
++ }
++ return cache;
++ } else
++ return NULL;
++
++}
++
++/* Find a cached chunk */
++static yaffs_ChunkCache *yaffs_FindChunkCache(const yaffs_Object * obj,
++ int chunkId)
++{
++ yaffs_Device *dev = obj->myDev;
++ int i;
++ if (dev->nShortOpCaches > 0) {
++ for (i = 0; i < dev->nShortOpCaches; i++) {
++ if (dev->srCache[i].object == obj &&
++ dev->srCache[i].chunkId == chunkId) {
++ dev->cacheHits++;
++
++ return &dev->srCache[i];
++ }
++ }
++ }
++ return NULL;
++}
++
++/* Mark the chunk for the least recently used algorithym */
++static void yaffs_UseChunkCache(yaffs_Device * dev, yaffs_ChunkCache * cache,
++ int isAWrite)
++{
++
++ if (dev->nShortOpCaches > 0) {
++ if (dev->srLastUse < 0 || dev->srLastUse > 100000000) {
++ /* Reset the cache usages */
++ int i;
++ for (i = 1; i < dev->nShortOpCaches; i++) {
++ dev->srCache[i].lastUse = 0;
++ }
++ dev->srLastUse = 0;
++ }
++
++ dev->srLastUse++;
++
++ cache->lastUse = dev->srLastUse;
++
++ if (isAWrite) {
++ cache->dirty = 1;
++ }
++ }
++}
++
++/* Invalidate a single cache page.
++ * Do this when a whole page gets written,
++ * ie the short cache for this page is no longer valid.
++ */
++static void yaffs_InvalidateChunkCache(yaffs_Object * object, int chunkId)
++{
++ if (object->myDev->nShortOpCaches > 0) {
++ yaffs_ChunkCache *cache = yaffs_FindChunkCache(object, chunkId);
++
++ if (cache) {
++ cache->object = NULL;
++ }
++ }
++}
++
++/* Invalidate all the cache pages associated with this object
++ * Do this whenever ther file is deleted or resized.
++ */
++static void yaffs_InvalidateWholeChunkCache(yaffs_Object * in)
++{
++ int i;
++ yaffs_Device *dev = in->myDev;
++
++ if (dev->nShortOpCaches > 0) {
++ /* Invalidate it. */
++ for (i = 0; i < dev->nShortOpCaches; i++) {
++ if (dev->srCache[i].object == in) {
++ dev->srCache[i].object = NULL;
++ }
++ }
++ }
++}
++
++/*--------------------- Checkpointing --------------------*/
++
++
++static int yaffs_WriteCheckpointValidityMarker(yaffs_Device *dev,int head)
++{
++ yaffs_CheckpointValidity cp;
++
++ memset(&cp,0,sizeof(cp));
++
++ cp.structType = sizeof(cp);
++ cp.magic = YAFFS_MAGIC;
++ cp.version = YAFFS_CHECKPOINT_VERSION;
++ cp.head = (head) ? 1 : 0;
++
++ return (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp))?
++ 1 : 0;
++}
++
++static int yaffs_ReadCheckpointValidityMarker(yaffs_Device *dev, int head)
++{
++ yaffs_CheckpointValidity cp;
++ int ok;
++
++ ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp));
++
++ if(ok)
++ ok = (cp.structType == sizeof(cp)) &&
++ (cp.magic == YAFFS_MAGIC) &&
++ (cp.version == YAFFS_CHECKPOINT_VERSION) &&
++ (cp.head == ((head) ? 1 : 0));
++ return ok ? 1 : 0;
++}
++
++static void yaffs_DeviceToCheckpointDevice(yaffs_CheckpointDevice *cp,
++ yaffs_Device *dev)
++{
++ cp->nErasedBlocks = dev->nErasedBlocks;
++ cp->allocationBlock = dev->allocationBlock;
++ cp->allocationPage = dev->allocationPage;
++ cp->nFreeChunks = dev->nFreeChunks;
++
++ cp->nDeletedFiles = dev->nDeletedFiles;
++ cp->nUnlinkedFiles = dev->nUnlinkedFiles;
++ cp->nBackgroundDeletions = dev->nBackgroundDeletions;
++ cp->sequenceNumber = dev->sequenceNumber;
++ cp->oldestDirtySequence = dev->oldestDirtySequence;
++
++}
++
++static void yaffs_CheckpointDeviceToDevice(yaffs_Device *dev,
++ yaffs_CheckpointDevice *cp)
++{
++ dev->nErasedBlocks = cp->nErasedBlocks;
++ dev->allocationBlock = cp->allocationBlock;
++ dev->allocationPage = cp->allocationPage;
++ dev->nFreeChunks = cp->nFreeChunks;
++
++ dev->nDeletedFiles = cp->nDeletedFiles;
++ dev->nUnlinkedFiles = cp->nUnlinkedFiles;
++ dev->nBackgroundDeletions = cp->nBackgroundDeletions;
++ dev->sequenceNumber = cp->sequenceNumber;
++ dev->oldestDirtySequence = cp->oldestDirtySequence;
++}
++
++
++static int yaffs_WriteCheckpointDevice(yaffs_Device *dev)
++{
++ yaffs_CheckpointDevice cp;
++ __u32 nBytes;
++ __u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
++
++ int ok;
++
++ /* Write device runtime values*/
++ yaffs_DeviceToCheckpointDevice(&cp,dev);
++ cp.structType = sizeof(cp);
++
++ ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp));
++
++ /* Write block info */
++ if(ok) {
++ nBytes = nBlocks * sizeof(yaffs_BlockInfo);
++ ok = (yaffs_CheckpointWrite(dev,dev->blockInfo,nBytes) == nBytes);
++ }
++
++ /* Write chunk bits */
++ if(ok) {
++ nBytes = nBlocks * dev->chunkBitmapStride;
++ ok = (yaffs_CheckpointWrite(dev,dev->chunkBits,nBytes) == nBytes);
++ }
++ return ok ? 1 : 0;
++
++}
++
++static int yaffs_ReadCheckpointDevice(yaffs_Device *dev)
++{
++ yaffs_CheckpointDevice cp;
++ __u32 nBytes;
++ __u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
++
++ int ok;
++
++ ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp));
++ if(!ok)
++ return 0;
++
++ if(cp.structType != sizeof(cp))
++ return 0;
++
++
++ yaffs_CheckpointDeviceToDevice(dev,&cp);
++
++ nBytes = nBlocks * sizeof(yaffs_BlockInfo);
++
++ ok = (yaffs_CheckpointRead(dev,dev->blockInfo,nBytes) == nBytes);
++
++ if(!ok)
++ return 0;
++ nBytes = nBlocks * dev->chunkBitmapStride;
++
++ ok = (yaffs_CheckpointRead(dev,dev->chunkBits,nBytes) == nBytes);
++
++ return ok ? 1 : 0;
++}
++
++static void yaffs_ObjectToCheckpointObject(yaffs_CheckpointObject *cp,
++ yaffs_Object *obj)
++{
++
++ cp->objectId = obj->objectId;
++ cp->parentId = (obj->parent) ? obj->parent->objectId : 0;
++ cp->hdrChunk = obj->hdrChunk;
++ cp->variantType = obj->variantType;
++ cp->deleted = obj->deleted;
++ cp->softDeleted = obj->softDeleted;
++ cp->unlinked = obj->unlinked;
++ cp->fake = obj->fake;
++ cp->renameAllowed = obj->renameAllowed;
++ cp->unlinkAllowed = obj->unlinkAllowed;
++ cp->serial = obj->serial;
++ cp->nDataChunks = obj->nDataChunks;
++
++ if(obj->variantType == YAFFS_OBJECT_TYPE_FILE)
++ cp->fileSizeOrEquivalentObjectId = obj->variant.fileVariant.fileSize;
++ else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
++ cp->fileSizeOrEquivalentObjectId = obj->variant.hardLinkVariant.equivalentObjectId;
++}
++
++static void yaffs_CheckpointObjectToObject( yaffs_Object *obj,yaffs_CheckpointObject *cp)
++{
++
++ yaffs_Object *parent;
++
++ obj->objectId = cp->objectId;
++
++ if(cp->parentId)
++ parent = yaffs_FindOrCreateObjectByNumber(
++ obj->myDev,
++ cp->parentId,
++ YAFFS_OBJECT_TYPE_DIRECTORY);
++ else
++ parent = NULL;
++
++ if(parent)
++ yaffs_AddObjectToDirectory(parent, obj);
++
++ obj->hdrChunk = cp->hdrChunk;
++ obj->variantType = cp->variantType;
++ obj->deleted = cp->deleted;
++ obj->softDeleted = cp->softDeleted;
++ obj->unlinked = cp->unlinked;
++ obj->fake = cp->fake;
++ obj->renameAllowed = cp->renameAllowed;
++ obj->unlinkAllowed = cp->unlinkAllowed;
++ obj->serial = cp->serial;
++ obj->nDataChunks = cp->nDataChunks;
++
++ if(obj->variantType == YAFFS_OBJECT_TYPE_FILE)
++ obj->variant.fileVariant.fileSize = cp->fileSizeOrEquivalentObjectId;
++ else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
++ obj->variant.hardLinkVariant.equivalentObjectId = cp->fileSizeOrEquivalentObjectId;
++
++ if(obj->hdrChunk > 0)
++ obj->lazyLoaded = 1;
++}
++
++
++
++static int yaffs_CheckpointTnodeWorker(yaffs_Object * in, yaffs_Tnode * tn,
++ __u32 level, int chunkOffset)
++{
++ int i;
++ yaffs_Device *dev = in->myDev;
++ int ok = 1;
++ int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
++
++ if(tnodeSize < sizeof(yaffs_Tnode))
++ tnodeSize = sizeof(yaffs_Tnode);
++
++
++ if (tn) {
++ if (level > 0) {
++
++ for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++){
++ if (tn->internal[i]) {
++ ok = yaffs_CheckpointTnodeWorker(in,
++ tn->internal[i],
++ level - 1,
++ (chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
++ }
++ }
++ } else if (level == 0) {
++ __u32 baseOffset = chunkOffset << YAFFS_TNODES_LEVEL0_BITS;
++ /* printf("write tnode at %d\n",baseOffset); */
++ ok = (yaffs_CheckpointWrite(dev,&baseOffset,sizeof(baseOffset)) == sizeof(baseOffset));
++ if(ok)
++ ok = (yaffs_CheckpointWrite(dev,tn,tnodeSize) == tnodeSize);
++ }
++ }
++
++ return ok;
++
++}
++
++static int yaffs_WriteCheckpointTnodes(yaffs_Object *obj)
++{
++ __u32 endMarker = ~0;
++ int ok = 1;
++
++ if(obj->variantType == YAFFS_OBJECT_TYPE_FILE){
++ ok = yaffs_CheckpointTnodeWorker(obj,
++ obj->variant.fileVariant.top,
++ obj->variant.fileVariant.topLevel,
++ 0);
++ if(ok)
++ ok = (yaffs_CheckpointWrite(obj->myDev,&endMarker,sizeof(endMarker)) ==
++ sizeof(endMarker));
++ }
++
++ return ok ? 1 : 0;
++}
++
++static int yaffs_ReadCheckpointTnodes(yaffs_Object *obj)
++{
++ __u32 baseChunk;
++ int ok = 1;
++ yaffs_Device *dev = obj->myDev;
++ yaffs_FileStructure *fileStructPtr = &obj->variant.fileVariant;
++ yaffs_Tnode *tn;
++ int nread = 0;
++ int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
++
++ if(tnodeSize < sizeof(yaffs_Tnode))
++ tnodeSize = sizeof(yaffs_Tnode);
++
++ ok = (yaffs_CheckpointRead(dev,&baseChunk,sizeof(baseChunk)) == sizeof(baseChunk));
++
++ while(ok && (~baseChunk)){
++ nread++;
++ /* Read level 0 tnode */
++
++
++ /* printf("read tnode at %d\n",baseChunk); */
++ tn = yaffs_GetTnodeRaw(dev);
++ if(tn)
++ ok = (yaffs_CheckpointRead(dev,tn,tnodeSize) == tnodeSize);
++ else
++ ok = 0;
++
++ if(tn && ok){
++ ok = yaffs_AddOrFindLevel0Tnode(dev,
++ fileStructPtr,
++ baseChunk,
++ tn) ? 1 : 0;
++
++ }
++
++ if(ok)
++ ok = (yaffs_CheckpointRead(dev,&baseChunk,sizeof(baseChunk)) == sizeof(baseChunk));
++
++ }
++
++ T(YAFFS_TRACE_CHECKPOINT,(
++ TSTR("Checkpoint read tnodes %d records, last %d. ok %d" TENDSTR),
++ nread,baseChunk,ok));
++
++ return ok ? 1 : 0;
++}
++
++
++static int yaffs_WriteCheckpointObjects(yaffs_Device *dev)
++{
++ yaffs_Object *obj;
++ yaffs_CheckpointObject cp;
++ int i;
++ int ok = 1;
++ struct ylist_head *lh;
++
++
++ /* Iterate through the objects in each hash entry,
++ * dumping them to the checkpointing stream.
++ */
++
++ for(i = 0; ok && i < YAFFS_NOBJECT_BUCKETS; i++){
++ ylist_for_each(lh, &dev->objectBucket[i].list) {
++ if (lh) {
++ obj = ylist_entry(lh, yaffs_Object, hashLink);
++ if (!obj->deferedFree) {
++ yaffs_ObjectToCheckpointObject(&cp,obj);
++ cp.structType = sizeof(cp);
++
++ T(YAFFS_TRACE_CHECKPOINT,(
++ TSTR("Checkpoint write object %d parent %d type %d chunk %d obj addr %x" TENDSTR),
++ cp.objectId,cp.parentId,cp.variantType,cp.hdrChunk,(unsigned) obj));
++
++ ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp));
++
++ if(ok && obj->variantType == YAFFS_OBJECT_TYPE_FILE){
++ ok = yaffs_WriteCheckpointTnodes(obj);
++ }
++ }
++ }
++ }
++ }
++
++ /* Dump end of list */
++ memset(&cp,0xFF,sizeof(yaffs_CheckpointObject));
++ cp.structType = sizeof(cp);
++
++ if(ok)
++ ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp));
++
++ return ok ? 1 : 0;
++}
++
++static int yaffs_ReadCheckpointObjects(yaffs_Device *dev)
++{
++ yaffs_Object *obj;
++ yaffs_CheckpointObject cp;
++ int ok = 1;
++ int done = 0;
++ yaffs_Object *hardList = NULL;
++
++ while(ok && !done) {
++ ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp));
++ if(cp.structType != sizeof(cp)) {
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("struct size %d instead of %d ok %d"TENDSTR),
++ cp.structType,sizeof(cp),ok));
++ ok = 0;
++ }
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("Checkpoint read object %d parent %d type %d chunk %d " TENDSTR),
++ cp.objectId,cp.parentId,cp.variantType,cp.hdrChunk));
++
++ if(ok && cp.objectId == ~0)
++ done = 1;
++ else if(ok){
++ obj = yaffs_FindOrCreateObjectByNumber(dev,cp.objectId, cp.variantType);
++ if(obj) {
++ yaffs_CheckpointObjectToObject(obj,&cp);
++ if(obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
++ ok = yaffs_ReadCheckpointTnodes(obj);
++ } else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
++ obj->hardLinks.next =
++ (struct ylist_head *)
++ hardList;
++ hardList = obj;
++ }
++
++ }
++ }
++ }
++
++ if(ok)
++ yaffs_HardlinkFixup(dev,hardList);
++
++ return ok ? 1 : 0;
++}
++
++static int yaffs_WriteCheckpointSum(yaffs_Device *dev)
++{
++ __u32 checkpointSum;
++ int ok;
++
++ yaffs_GetCheckpointSum(dev,&checkpointSum);
++
++ ok = (yaffs_CheckpointWrite(dev,&checkpointSum,sizeof(checkpointSum)) == sizeof(checkpointSum));
++
++ if(!ok)
++ return 0;
++
++ return 1;
++}
++
++static int yaffs_ReadCheckpointSum(yaffs_Device *dev)
++{
++ __u32 checkpointSum0;
++ __u32 checkpointSum1;
++ int ok;
++
++ yaffs_GetCheckpointSum(dev,&checkpointSum0);
++
++ ok = (yaffs_CheckpointRead(dev,&checkpointSum1,sizeof(checkpointSum1)) == sizeof(checkpointSum1));
++
++ if(!ok)
++ return 0;
++
++ if(checkpointSum0 != checkpointSum1)
++ return 0;
++
++ return 1;
++}
++
++
++static int yaffs_WriteCheckpointData(yaffs_Device *dev)
++{
++
++ int ok = 1;
++
++ if(dev->skipCheckpointWrite || !dev->isYaffs2){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("skipping checkpoint write" TENDSTR)));
++ ok = 0;
++ }
++
++ if(ok)
++ ok = yaffs_CheckpointOpen(dev,1);
++
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint validity" TENDSTR)));
++ ok = yaffs_WriteCheckpointValidityMarker(dev,1);
++ }
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint device" TENDSTR)));
++ ok = yaffs_WriteCheckpointDevice(dev);
++ }
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint objects" TENDSTR)));
++ ok = yaffs_WriteCheckpointObjects(dev);
++ }
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint validity" TENDSTR)));
++ ok = yaffs_WriteCheckpointValidityMarker(dev,0);
++ }
++
++ if(ok){
++ ok = yaffs_WriteCheckpointSum(dev);
++ }
++
++
++ if(!yaffs_CheckpointClose(dev))
++ ok = 0;
++
++ if(ok)
++ dev->isCheckpointed = 1;
++ else
++ dev->isCheckpointed = 0;
++
++ return dev->isCheckpointed;
++}
++
++static int yaffs_ReadCheckpointData(yaffs_Device *dev)
++{
++ int ok = 1;
++
++ if(dev->skipCheckpointRead || !dev->isYaffs2){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("skipping checkpoint read" TENDSTR)));
++ ok = 0;
++ }
++
++ if(ok)
++ ok = yaffs_CheckpointOpen(dev,0); /* open for read */
++
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint validity" TENDSTR)));
++ ok = yaffs_ReadCheckpointValidityMarker(dev,1);
++ }
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint device" TENDSTR)));
++ ok = yaffs_ReadCheckpointDevice(dev);
++ }
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint objects" TENDSTR)));
++ ok = yaffs_ReadCheckpointObjects(dev);
++ }
++ if(ok){
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint validity" TENDSTR)));
++ ok = yaffs_ReadCheckpointValidityMarker(dev,0);
++ }
++
++ if(ok){
++ ok = yaffs_ReadCheckpointSum(dev);
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint checksum %d" TENDSTR),ok));
++ }
++
++ if(!yaffs_CheckpointClose(dev))
++ ok = 0;
++
++ if(ok)
++ dev->isCheckpointed = 1;
++ else
++ dev->isCheckpointed = 0;
++
++ return ok ? 1 : 0;
++
++}
++
++static void yaffs_InvalidateCheckpoint(yaffs_Device *dev)
++{
++ if(dev->isCheckpointed ||
++ dev->blocksInCheckpoint > 0){
++ dev->isCheckpointed = 0;
++ yaffs_CheckpointInvalidateStream(dev);
++ if(dev->superBlock && dev->markSuperBlockDirty)
++ dev->markSuperBlockDirty(dev->superBlock);
++ }
++}
++
++
++int yaffs_CheckpointSave(yaffs_Device *dev)
++{
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("save entry: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
++
++ yaffs_VerifyObjects(dev);
++ yaffs_VerifyBlocks(dev);
++ yaffs_VerifyFreeChunks(dev);
++
++ if(!dev->isCheckpointed) {
++ yaffs_InvalidateCheckpoint(dev);
++ yaffs_WriteCheckpointData(dev);
++ }
++
++ T(YAFFS_TRACE_ALWAYS,(TSTR("save exit: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
++
++ return dev->isCheckpointed;
++}
++
++int yaffs_CheckpointRestore(yaffs_Device *dev)
++{
++ int retval;
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("restore entry: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
++
++ retval = yaffs_ReadCheckpointData(dev);
++
++ if(dev->isCheckpointed){
++ yaffs_VerifyObjects(dev);
++ yaffs_VerifyBlocks(dev);
++ yaffs_VerifyFreeChunks(dev);
++ }
++
++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("restore exit: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
++
++ return retval;
++}
++
++/*--------------------- File read/write ------------------------
++ * Read and write have very similar structures.
++ * In general the read/write has three parts to it
++ * An incomplete chunk to start with (if the read/write is not chunk-aligned)
++ * Some complete chunks
++ * An incomplete chunk to end off with
++ *
++ * Curve-balls: the first chunk might also be the last chunk.
++ */
++
++int yaffs_ReadDataFromFile(yaffs_Object * in, __u8 * buffer, loff_t offset,
++ int nBytes)
++{
++
++ int chunk;
++ __u32 start;
++ int nToCopy;
++ int n = nBytes;
++ int nDone = 0;
++ yaffs_ChunkCache *cache;
++
++ yaffs_Device *dev;
++
++ dev = in->myDev;
++
++ while (n > 0) {
++ //chunk = offset / dev->nDataBytesPerChunk + 1;
++ //start = offset % dev->nDataBytesPerChunk;
++ yaffs_AddrToChunk(dev,offset,&chunk,&start);
++ chunk++;
++
++ /* OK now check for the curveball where the start and end are in
++ * the same chunk.
++ */
++ if ((start + n) < dev->nDataBytesPerChunk) {
++ nToCopy = n;
++ } else {
++ nToCopy = dev->nDataBytesPerChunk - start;
++ }
++
++ cache = yaffs_FindChunkCache(in, chunk);
++
++ /* If the chunk is already in the cache or it is less than a whole chunk
++ * or we're using inband tags then use the cache (if there is caching)
++ * else bypass the cache.
++ */
++ if (cache || nToCopy != dev->nDataBytesPerChunk || dev->inbandTags) {
++ if (dev->nShortOpCaches > 0) {
++
++ /* If we can't find the data in the cache, then load it up. */
++
++ if (!cache) {
++ cache = yaffs_GrabChunkCache(in->myDev);
++ cache->object = in;
++ cache->chunkId = chunk;
++ cache->dirty = 0;
++ cache->locked = 0;
++ yaffs_ReadChunkDataFromObject(in, chunk,
++ cache->
++ data);
++ cache->nBytes = 0;
++ }
++
++ yaffs_UseChunkCache(dev, cache, 0);
++
++ cache->locked = 1;
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_UnlockYAFFS(TRUE);
++#endif
++ memcpy(buffer, &cache->data[start], nToCopy);
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_LockYAFFS(TRUE);
++#endif
++ cache->locked = 0;
++ } else {
++ /* Read into the local buffer then copy..*/
++
++ __u8 *localBuffer =
++ yaffs_GetTempBuffer(dev, __LINE__);
++ yaffs_ReadChunkDataFromObject(in, chunk,
++ localBuffer);
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_UnlockYAFFS(TRUE);
++#endif
++ memcpy(buffer, &localBuffer[start], nToCopy);
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_LockYAFFS(TRUE);
++#endif
++ yaffs_ReleaseTempBuffer(dev, localBuffer,
++ __LINE__);
++ }
++
++ } else {
++#ifdef CONFIG_YAFFS_WINCE
++ __u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
++
++ /* Under WinCE can't do direct transfer. Need to use a local buffer.
++ * This is because we otherwise screw up WinCE's memory mapper
++ */
++ yaffs_ReadChunkDataFromObject(in, chunk, localBuffer);
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_UnlockYAFFS(TRUE);
++#endif
++ memcpy(buffer, localBuffer, dev->nDataBytesPerChunk);
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_LockYAFFS(TRUE);
++ yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
++#endif
++
++#else
++ /* A full chunk. Read directly into the supplied buffer. */
++ yaffs_ReadChunkDataFromObject(in, chunk, buffer);
++#endif
++ }
++
++ n -= nToCopy;
++ offset += nToCopy;
++ buffer += nToCopy;
++ nDone += nToCopy;
++
++ }
++
++ return nDone;
++}
++
++int yaffs_WriteDataToFile(yaffs_Object * in, const __u8 * buffer, loff_t offset,
++ int nBytes, int writeThrough)
++{
++
++ int chunk;
++ __u32 start;
++ int nToCopy;
++ int n = nBytes;
++ int nDone = 0;
++ int nToWriteBack;
++ int startOfWrite = offset;
++ int chunkWritten = 0;
++ __u32 nBytesRead;
++ __u32 chunkStart;
++
++ yaffs_Device *dev;
++
++ dev = in->myDev;
++
++ while (n > 0 && chunkWritten >= 0) {
++ //chunk = offset / dev->nDataBytesPerChunk + 1;
++ //start = offset % dev->nDataBytesPerChunk;
++ yaffs_AddrToChunk(dev,offset,&chunk,&start);
++
++ if(chunk * dev->nDataBytesPerChunk + start != offset ||
++ start >= dev->nDataBytesPerChunk){
++ T(YAFFS_TRACE_ERROR,(TSTR("AddrToChunk of offset %d gives chunk %d start %d"TENDSTR),
++ (int)offset, chunk,start));
++ }
++ chunk++;
++
++ /* OK now check for the curveball where the start and end are in
++ * the same chunk.
++ */
++
++ if ((start + n) < dev->nDataBytesPerChunk) {
++ nToCopy = n;
++
++ /* Now folks, to calculate how many bytes to write back....
++ * If we're overwriting and not writing to then end of file then
++ * we need to write back as much as was there before.
++ */
++
++ chunkStart = ((chunk - 1) * dev->nDataBytesPerChunk);
++
++ if(chunkStart > in->variant.fileVariant.fileSize)
++ nBytesRead = 0; /* Past end of file */
++ else
++ nBytesRead = in->variant.fileVariant.fileSize - chunkStart;
++
++ if (nBytesRead > dev->nDataBytesPerChunk) {
++ nBytesRead = dev->nDataBytesPerChunk;
++ }
++
++ nToWriteBack =
++ (nBytesRead >
++ (start + n)) ? nBytesRead : (start + n);
++
++ if(nToWriteBack < 0 || nToWriteBack > dev->nDataBytesPerChunk)
++ YBUG();
++
++ } else {
++ nToCopy = dev->nDataBytesPerChunk - start;
++ nToWriteBack = dev->nDataBytesPerChunk;
++ }
++
++ if (nToCopy != dev->nDataBytesPerChunk || dev->inbandTags) {
++ /* An incomplete start or end chunk (or maybe both start and end chunk),
++ * or we're using inband tags, so we want to use the cache buffers.
++ */
++ if (dev->nShortOpCaches > 0) {
++ yaffs_ChunkCache *cache;
++ /* If we can't find the data in the cache, then load the cache */
++ cache = yaffs_FindChunkCache(in, chunk);
++
++ if (!cache
++ && yaffs_CheckSpaceForAllocation(in->
++ myDev)) {
++ cache = yaffs_GrabChunkCache(in->myDev);
++ cache->object = in;
++ cache->chunkId = chunk;
++ cache->dirty = 0;
++ cache->locked = 0;
++ yaffs_ReadChunkDataFromObject(in, chunk,
++ cache->
++ data);
++ }
++ else if(cache &&
++ !cache->dirty &&
++ !yaffs_CheckSpaceForAllocation(in->myDev)){
++ /* Drop the cache if it was a read cache item and
++ * no space check has been made for it.
++ */
++ cache = NULL;
++ }
++
++ if (cache) {
++ yaffs_UseChunkCache(dev, cache, 1);
++ cache->locked = 1;
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_UnlockYAFFS(TRUE);
++#endif
++
++ memcpy(&cache->data[start], buffer,
++ nToCopy);
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_LockYAFFS(TRUE);
++#endif
++ cache->locked = 0;
++ cache->nBytes = nToWriteBack;
++
++ if (writeThrough) {
++ chunkWritten =
++ yaffs_WriteChunkDataToObject
++ (cache->object,
++ cache->chunkId,
++ cache->data, cache->nBytes,
++ 1);
++ cache->dirty = 0;
++ }
++
++ } else {
++ chunkWritten = -1; /* fail the write */
++ }
++ } else {
++ /* An incomplete start or end chunk (or maybe both start and end chunk)
++ * Read into the local buffer then copy, then copy over and write back.
++ */
++
++ __u8 *localBuffer =
++ yaffs_GetTempBuffer(dev, __LINE__);
++
++ yaffs_ReadChunkDataFromObject(in, chunk,
++ localBuffer);
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_UnlockYAFFS(TRUE);
++#endif
++
++ memcpy(&localBuffer[start], buffer, nToCopy);
++
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_LockYAFFS(TRUE);
++#endif
++ chunkWritten =
++ yaffs_WriteChunkDataToObject(in, chunk,
++ localBuffer,
++ nToWriteBack,
++ 0);
++
++ yaffs_ReleaseTempBuffer(dev, localBuffer,
++ __LINE__);
++
++ }
++
++ } else {
++ /* A full chunk. Write directly from the supplied buffer. */
++
++#ifdef CONFIG_YAFFS_WINCE
++ /* Under WinCE can't do direct transfer. Need to use a local buffer.
++ * This is because we otherwise screw up WinCE's memory mapper
++ */
++ __u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_UnlockYAFFS(TRUE);
++#endif
++ memcpy(localBuffer, buffer, dev->nDataBytesPerChunk);
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_LockYAFFS(TRUE);
++#endif
++ chunkWritten =
++ yaffs_WriteChunkDataToObject(in, chunk, localBuffer,
++ dev->nDataBytesPerChunk,
++ 0);
++ yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
++#else
++
++ chunkWritten =
++ yaffs_WriteChunkDataToObject(in, chunk, buffer,
++ dev->nDataBytesPerChunk,
++ 0);
++#endif
++ /* Since we've overwritten the cached data, we better invalidate it. */
++ yaffs_InvalidateChunkCache(in, chunk);
++ }
++
++ if (chunkWritten >= 0) {
++ n -= nToCopy;
++ offset += nToCopy;
++ buffer += nToCopy;
++ nDone += nToCopy;
++ }
++
++ }
++
++ /* Update file object */
++
++ if ((startOfWrite + nDone) > in->variant.fileVariant.fileSize) {
++ in->variant.fileVariant.fileSize = (startOfWrite + nDone);
++ }
++
++ in->dirty = 1;
++
++ return nDone;
++}
++
++
++/* ---------------------- File resizing stuff ------------------ */
++
++static void yaffs_PruneResizedChunks(yaffs_Object * in, int newSize)
++{
++
++ yaffs_Device *dev = in->myDev;
++ int oldFileSize = in->variant.fileVariant.fileSize;
++
++ int lastDel = 1 + (oldFileSize - 1) / dev->nDataBytesPerChunk;
++
++ int startDel = 1 + (newSize + dev->nDataBytesPerChunk - 1) /
++ dev->nDataBytesPerChunk;
++ int i;
++ int chunkId;
++
++ /* Delete backwards so that we don't end up with holes if
++ * power is lost part-way through the operation.
++ */
++ for (i = lastDel; i >= startDel; i--) {
++ /* NB this could be optimised somewhat,
++ * eg. could retrieve the tags and write them without
++ * using yaffs_DeleteChunk
++ */
++
++ chunkId = yaffs_FindAndDeleteChunkInFile(in, i, NULL);
++ if (chunkId > 0) {
++ if (chunkId <
++ (dev->internalStartBlock * dev->nChunksPerBlock)
++ || chunkId >=
++ ((dev->internalEndBlock +
++ 1) * dev->nChunksPerBlock)) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("Found daft chunkId %d for %d" TENDSTR),
++ chunkId, i));
++ } else {
++ in->nDataChunks--;
++ yaffs_DeleteChunk(dev, chunkId, 1, __LINE__);
++ }
++ }
++ }
++
++}
++
++int yaffs_ResizeFile(yaffs_Object * in, loff_t newSize)
++{
++
++ int oldFileSize = in->variant.fileVariant.fileSize;
++ __u32 newSizeOfPartialChunk;
++ int newFullChunks;
++
++ yaffs_Device *dev = in->myDev;
++
++ yaffs_AddrToChunk(dev, newSize, &newFullChunks, &newSizeOfPartialChunk);
++
++ yaffs_FlushFilesChunkCache(in);
++ yaffs_InvalidateWholeChunkCache(in);
++
++ yaffs_CheckGarbageCollection(dev);
++
++ if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
++ return YAFFS_FAIL;
++ }
++
++ if (newSize == oldFileSize) {
++ return YAFFS_OK;
++ }
++
++ if (newSize < oldFileSize) {
++
++ yaffs_PruneResizedChunks(in, newSize);
++
++ if (newSizeOfPartialChunk != 0) {
++ int lastChunk = 1 + newFullChunks;
++
++ __u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
++
++ /* Got to read and rewrite the last chunk with its new size and zero pad */
++ yaffs_ReadChunkDataFromObject(in, lastChunk,
++ localBuffer);
++
++ memset(localBuffer + newSizeOfPartialChunk, 0,
++ dev->nDataBytesPerChunk - newSizeOfPartialChunk);
++
++ yaffs_WriteChunkDataToObject(in, lastChunk, localBuffer,
++ newSizeOfPartialChunk, 1);
++
++ yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
++ }
++
++ in->variant.fileVariant.fileSize = newSize;
++
++ yaffs_PruneFileStructure(dev, &in->variant.fileVariant);
++ } else {
++ /* newsSize > oldFileSize */
++ in->variant.fileVariant.fileSize = newSize;
++ }
++
++
++
++ /* Write a new object header.
++ * show we've shrunk the file, if need be
++ * Do this only if the file is not in the deleted directories.
++ */
++ if (in->parent &&
++ in->parent->objectId != YAFFS_OBJECTID_UNLINKED &&
++ in->parent->objectId != YAFFS_OBJECTID_DELETED) {
++ yaffs_UpdateObjectHeader(in, NULL, 0,
++ (newSize < oldFileSize) ? 1 : 0, 0);
++ }
++
++ return YAFFS_OK;
++}
++
++loff_t yaffs_GetFileSize(yaffs_Object * obj)
++{
++ obj = yaffs_GetEquivalentObject(obj);
++
++ switch (obj->variantType) {
++ case YAFFS_OBJECT_TYPE_FILE:
++ return obj->variant.fileVariant.fileSize;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ return yaffs_strlen(obj->variant.symLinkVariant.alias);
++ default:
++ return 0;
++ }
++}
++
++
++
++int yaffs_FlushFile(yaffs_Object * in, int updateTime)
++{
++ int retVal;
++ if (in->dirty) {
++ yaffs_FlushFilesChunkCache(in);
++ if (updateTime) {
++#ifdef CONFIG_YAFFS_WINCE
++ yfsd_WinFileTimeNow(in->win_mtime);
++#else
++
++ in->yst_mtime = Y_CURRENT_TIME;
++
++#endif
++ }
++
++ retVal =
++ (yaffs_UpdateObjectHeader(in, NULL, 0, 0, 0) >=
++ 0) ? YAFFS_OK : YAFFS_FAIL;
++ } else {
++ retVal = YAFFS_OK;
++ }
++
++ return retVal;
++
++}
++
++static int yaffs_DoGenericObjectDeletion(yaffs_Object * in)
++{
++
++ /* First off, invalidate the file's data in the cache, without flushing. */
++ yaffs_InvalidateWholeChunkCache(in);
++
++ if (in->myDev->isYaffs2 && (in->parent != in->myDev->deletedDir)) {
++ /* Move to the unlinked directory so we have a record that it was deleted. */
++ yaffs_ChangeObjectName(in, in->myDev->deletedDir,_Y("deleted"), 0, 0);
++
++ }
++
++ yaffs_RemoveObjectFromDirectory(in);
++ yaffs_DeleteChunk(in->myDev, in->hdrChunk, 1, __LINE__);
++ in->hdrChunk = 0;
++
++ yaffs_FreeObject(in);
++ return YAFFS_OK;
++
++}
++
++/* yaffs_DeleteFile deletes the whole file data
++ * and the inode associated with the file.
++ * It does not delete the links associated with the file.
++ */
++
++static int yaffs_UnlinkFile(yaffs_Object * in)
++{
++
++ int retVal;
++ int immediateDeletion = 0;
++
++#ifdef __KERNEL__
++ if (!in->myInode) {
++ immediateDeletion = 1;
++ }
++#else
++ if (in->inUse <= 0) {
++ immediateDeletion = 1;
++ }
++#endif
++
++ if (immediateDeletion) {
++ retVal =
++ yaffs_ChangeObjectName(in, in->myDev->deletedDir,
++ _Y("deleted"), 0, 0);
++ T(YAFFS_TRACE_TRACING,
++ (TSTR("yaffs: immediate deletion of file %d" TENDSTR),
++ in->objectId));
++ in->deleted = 1;
++ in->myDev->nDeletedFiles++;
++ if (1 || in->myDev->isYaffs2) {
++ yaffs_ResizeFile(in, 0);
++ }
++ yaffs_SoftDeleteFile(in);
++ } else {
++ retVal =
++ yaffs_ChangeObjectName(in, in->myDev->unlinkedDir,
++ _Y("unlinked"), 0, 0);
++ }
++
++
++ return retVal;
++}
++
++int yaffs_DeleteFile(yaffs_Object * in)
++{
++ int retVal = YAFFS_OK;
++ int deleted = in->deleted;
++
++ yaffs_ResizeFile(in,0);
++
++ if (in->nDataChunks > 0) {
++ /* Use soft deletion if there is data in the file.
++ * That won't be the case if it has been resized to zero.
++ */
++ if (!in->unlinked) {
++ retVal = yaffs_UnlinkFile(in);
++ }
++ if (retVal == YAFFS_OK && in->unlinked && !in->deleted) {
++ in->deleted = deleted = 1;
++ in->myDev->nDeletedFiles++;
++ yaffs_SoftDeleteFile(in);
++ }
++ return deleted ? YAFFS_OK : YAFFS_FAIL;
++ } else {
++ /* The file has no data chunks so we toss it immediately */
++ yaffs_FreeTnode(in->myDev, in->variant.fileVariant.top);
++ in->variant.fileVariant.top = NULL;
++ yaffs_DoGenericObjectDeletion(in);
++
++ return YAFFS_OK;
++ }
++}
++
++static int yaffs_DeleteDirectory(yaffs_Object * in)
++{
++ /* First check that the directory is empty. */
++ if (ylist_empty(&in->variant.directoryVariant.children)) {
++ return yaffs_DoGenericObjectDeletion(in);
++ }
++
++ return YAFFS_FAIL;
++
++}
++
++static int yaffs_DeleteSymLink(yaffs_Object * in)
++{
++ YFREE(in->variant.symLinkVariant.alias);
++
++ return yaffs_DoGenericObjectDeletion(in);
++}
++
++static int yaffs_DeleteHardLink(yaffs_Object * in)
++{
++ /* remove this hardlink from the list assocaited with the equivalent
++ * object
++ */
++ ylist_del_init(&in->hardLinks);
++ return yaffs_DoGenericObjectDeletion(in);
++}
++
++static void yaffs_DestroyObject(yaffs_Object * obj)
++{
++ switch (obj->variantType) {
++ case YAFFS_OBJECT_TYPE_FILE:
++ yaffs_DeleteFile(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ yaffs_DeleteDirectory(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ yaffs_DeleteSymLink(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ yaffs_DeleteHardLink(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ yaffs_DoGenericObjectDeletion(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ break; /* should not happen. */
++ }
++}
++
++static int yaffs_UnlinkWorker(yaffs_Object * obj)
++{
++
++ if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
++ return yaffs_DeleteHardLink(obj);
++ } else if (!ylist_empty(&obj->hardLinks)) {
++ /* Curve ball: We're unlinking an object that has a hardlink.
++ *
++ * This problem arises because we are not strictly following
++ * The Linux link/inode model.
++ *
++ * We can't really delete the object.
++ * Instead, we do the following:
++ * - Select a hardlink.
++ * - Unhook it from the hard links
++ * - Unhook it from its parent directory (so that the rename can work)
++ * - Rename the object to the hardlink's name.
++ * - Delete the hardlink
++ */
++
++ yaffs_Object *hl;
++ int retVal;
++ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
++
++ hl = ylist_entry(obj->hardLinks.next, yaffs_Object, hardLinks);
++
++ ylist_del_init(&hl->hardLinks);
++ ylist_del_init(&hl->siblings);
++
++ yaffs_GetObjectName(hl, name, YAFFS_MAX_NAME_LENGTH + 1);
++
++ retVal = yaffs_ChangeObjectName(obj, hl->parent, name, 0, 0);
++
++ if (retVal == YAFFS_OK) {
++ retVal = yaffs_DoGenericObjectDeletion(hl);
++ }
++ return retVal;
++
++ } else {
++ switch (obj->variantType) {
++ case YAFFS_OBJECT_TYPE_FILE:
++ return yaffs_UnlinkFile(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ return yaffs_DeleteDirectory(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ return yaffs_DeleteSymLink(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ return yaffs_DoGenericObjectDeletion(obj);
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ default:
++ return YAFFS_FAIL;
++ }
++ }
++}
++
++
++static int yaffs_UnlinkObject( yaffs_Object *obj)
++{
++
++ if (obj && obj->unlinkAllowed) {
++ return yaffs_UnlinkWorker(obj);
++ }
++
++ return YAFFS_FAIL;
++
++}
++int yaffs_Unlink(yaffs_Object * dir, const YCHAR * name)
++{
++ yaffs_Object *obj;
++
++ obj = yaffs_FindObjectByName(dir, name);
++ return yaffs_UnlinkObject(obj);
++}
++
++/*----------------------- Initialisation Scanning ---------------------- */
++
++static void yaffs_HandleShadowedObject(yaffs_Device * dev, int objId,
++ int backwardScanning)
++{
++ yaffs_Object *obj;
++
++ if (!backwardScanning) {
++ /* Handle YAFFS1 forward scanning case
++ * For YAFFS1 we always do the deletion
++ */
++
++ } else {
++ /* Handle YAFFS2 case (backward scanning)
++ * If the shadowed object exists then ignore.
++ */
++ if (yaffs_FindObjectByNumber(dev, objId)) {
++ return;
++ }
++ }
++
++ /* Let's create it (if it does not exist) assuming it is a file so that it can do shrinking etc.
++ * We put it in unlinked dir to be cleaned up after the scanning
++ */
++ obj =
++ yaffs_FindOrCreateObjectByNumber(dev, objId,
++ YAFFS_OBJECT_TYPE_FILE);
++ yaffs_AddObjectToDirectory(dev->unlinkedDir, obj);
++ obj->variant.fileVariant.shrinkSize = 0;
++ obj->valid = 1; /* So that we don't read any other info for this file */
++
++}
++
++typedef struct {
++ int seq;
++ int block;
++} yaffs_BlockIndex;
++
++
++static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList)
++{
++ yaffs_Object *hl;
++ yaffs_Object *in;
++
++ while (hardList) {
++ hl = hardList;
++ hardList = (yaffs_Object *) (hardList->hardLinks.next);
++
++ in = yaffs_FindObjectByNumber(dev,
++ hl->variant.hardLinkVariant.
++ equivalentObjectId);
++
++ if (in) {
++ /* Add the hardlink pointers */
++ hl->variant.hardLinkVariant.equivalentObject = in;
++ ylist_add(&hl->hardLinks, &in->hardLinks);
++ } else {
++ /* Todo Need to report/handle this better.
++ * Got a problem... hardlink to a non-existant object
++ */
++ hl->variant.hardLinkVariant.equivalentObject = NULL;
++ YINIT_LIST_HEAD(&hl->hardLinks);
++
++ }
++
++ }
++
++}
++
++
++
++
++
++static int ybicmp(const void *a, const void *b){
++ register int aseq = ((yaffs_BlockIndex *)a)->seq;
++ register int bseq = ((yaffs_BlockIndex *)b)->seq;
++ register int ablock = ((yaffs_BlockIndex *)a)->block;
++ register int bblock = ((yaffs_BlockIndex *)b)->block;
++ if( aseq == bseq )
++ return ablock - bblock;
++ else
++ return aseq - bseq;
++
++}
++
++
++struct yaffs_ShadowFixerStruct {
++ int objectId;
++ int shadowedId;
++ struct yaffs_ShadowFixerStruct *next;
++};
++
++
++static void yaffs_StripDeletedObjects(yaffs_Device *dev)
++{
++ /*
++ * Sort out state of unlinked and deleted objects after scanning.
++ */
++ struct ylist_head *i;
++ struct ylist_head *n;
++ yaffs_Object *l;
++
++ /* Soft delete all the unlinked files */
++ ylist_for_each_safe(i, n,
++ &dev->unlinkedDir->variant.directoryVariant.children) {
++ if (i) {
++ l = ylist_entry(i, yaffs_Object, siblings);
++ yaffs_DestroyObject(l);
++ }
++ }
++
++ ylist_for_each_safe(i, n,
++ &dev->deletedDir->variant.directoryVariant.children) {
++ if (i) {
++ l = ylist_entry(i, yaffs_Object, siblings);
++ yaffs_DestroyObject(l);
++ }
++ }
++
++}
++
++static int yaffs_Scan(yaffs_Device * dev)
++{
++ yaffs_ExtendedTags tags;
++ int blk;
++ int blockIterator;
++ int startIterator;
++ int endIterator;
++ int result;
++
++ int chunk;
++ int c;
++ int deleted;
++ yaffs_BlockState state;
++ yaffs_Object *hardList = NULL;
++ yaffs_BlockInfo *bi;
++ __u32 sequenceNumber;
++ yaffs_ObjectHeader *oh;
++ yaffs_Object *in;
++ yaffs_Object *parent;
++
++ int alloc_failed = 0;
++
++ struct yaffs_ShadowFixerStruct *shadowFixerList = NULL;
++
++
++ __u8 *chunkData;
++
++
++
++ T(YAFFS_TRACE_SCAN,
++ (TSTR("yaffs_Scan starts intstartblk %d intendblk %d..." TENDSTR),
++ dev->internalStartBlock, dev->internalEndBlock));
++
++ chunkData = yaffs_GetTempBuffer(dev, __LINE__);
++
++ dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
++
++ /* Scan all the blocks to determine their state */
++ for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
++ bi = yaffs_GetBlockInfo(dev, blk);
++ yaffs_ClearChunkBits(dev, blk);
++ bi->pagesInUse = 0;
++ bi->softDeletions = 0;
++
++ yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
++
++ bi->blockState = state;
++ bi->sequenceNumber = sequenceNumber;
++
++ T(YAFFS_TRACE_SCAN_DEBUG,
++ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
++ state, sequenceNumber));
++
++ if (state == YAFFS_BLOCK_STATE_DEAD) {
++ T(YAFFS_TRACE_BAD_BLOCKS,
++ (TSTR("block %d is bad" TENDSTR), blk));
++ } else if (state == YAFFS_BLOCK_STATE_EMPTY) {
++ T(YAFFS_TRACE_SCAN_DEBUG,
++ (TSTR("Block empty " TENDSTR)));
++ dev->nErasedBlocks++;
++ dev->nFreeChunks += dev->nChunksPerBlock;
++ }
++ }
++
++ startIterator = dev->internalStartBlock;
++ endIterator = dev->internalEndBlock;
++
++ /* For each block.... */
++ for (blockIterator = startIterator; !alloc_failed && blockIterator <= endIterator;
++ blockIterator++) {
++
++ YYIELD();
++
++ YYIELD();
++
++ blk = blockIterator;
++
++ bi = yaffs_GetBlockInfo(dev, blk);
++ state = bi->blockState;
++
++ deleted = 0;
++
++ /* For each chunk in each block that needs scanning....*/
++ for (c = 0; !alloc_failed && c < dev->nChunksPerBlock &&
++ state == YAFFS_BLOCK_STATE_NEEDS_SCANNING; c++) {
++ /* Read the tags and decide what to do */
++ chunk = blk * dev->nChunksPerBlock + c;
++
++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
++ &tags);
++
++ /* Let's have a good look at this chunk... */
++
++ if (tags.eccResult == YAFFS_ECC_RESULT_UNFIXED || tags.chunkDeleted) {
++ /* YAFFS1 only...
++ * A deleted chunk
++ */
++ deleted++;
++ dev->nFreeChunks++;
++ /*T((" %d %d deleted\n",blk,c)); */
++ } else if (!tags.chunkUsed) {
++ /* An unassigned chunk in the block
++ * This means that either the block is empty or
++ * this is the one being allocated from
++ */
++
++ if (c == 0) {
++ /* We're looking at the first chunk in the block so the block is unused */
++ state = YAFFS_BLOCK_STATE_EMPTY;
++ dev->nErasedBlocks++;
++ } else {
++ /* this is the block being allocated from */
++ T(YAFFS_TRACE_SCAN,
++ (TSTR
++ (" Allocating from %d %d" TENDSTR),
++ blk, c));
++ state = YAFFS_BLOCK_STATE_ALLOCATING;
++ dev->allocationBlock = blk;
++ dev->allocationPage = c;
++ dev->allocationBlockFinder = blk;
++ /* Set it to here to encourage the allocator to go forth from here. */
++
++ }
++
++ dev->nFreeChunks += (dev->nChunksPerBlock - c);
++ } else if (tags.chunkId > 0) {
++ /* chunkId > 0 so it is a data chunk... */
++ unsigned int endpos;
++
++ yaffs_SetChunkBit(dev, blk, c);
++ bi->pagesInUse++;
++
++ in = yaffs_FindOrCreateObjectByNumber(dev,
++ tags.
++ objectId,
++ YAFFS_OBJECT_TYPE_FILE);
++ /* PutChunkIntoFile checks for a clash (two data chunks with
++ * the same chunkId).
++ */
++
++ if(!in)
++ alloc_failed = 1;
++
++ if(in){
++ if(!yaffs_PutChunkIntoFile(in, tags.chunkId, chunk,1))
++ alloc_failed = 1;
++ }
++
++ endpos =
++ (tags.chunkId - 1) * dev->nDataBytesPerChunk +
++ tags.byteCount;
++ if (in &&
++ in->variantType == YAFFS_OBJECT_TYPE_FILE
++ && in->variant.fileVariant.scannedFileSize <
++ endpos) {
++ in->variant.fileVariant.
++ scannedFileSize = endpos;
++ if (!dev->useHeaderFileSize) {
++ in->variant.fileVariant.
++ fileSize =
++ in->variant.fileVariant.
++ scannedFileSize;
++ }
++
++ }
++ /* T((" %d %d data %d %d\n",blk,c,tags.objectId,tags.chunkId)); */
++ } else {
++ /* chunkId == 0, so it is an ObjectHeader.
++ * Thus, we read in the object header and make the object
++ */
++ yaffs_SetChunkBit(dev, blk, c);
++ bi->pagesInUse++;
++
++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk,
++ chunkData,
++ NULL);
++
++ oh = (yaffs_ObjectHeader *) chunkData;
++
++ in = yaffs_FindObjectByNumber(dev,
++ tags.objectId);
++ if (in && in->variantType != oh->type) {
++ /* This should not happen, but somehow
++ * Wev'e ended up with an objectId that has been reused but not yet
++ * deleted, and worse still it has changed type. Delete the old object.
++ */
++
++ yaffs_DestroyObject(in);
++
++ in = 0;
++ }
++
++ in = yaffs_FindOrCreateObjectByNumber(dev,
++ tags.
++ objectId,
++ oh->type);
++
++ if(!in)
++ alloc_failed = 1;
++
++ if (in && oh->shadowsObject > 0) {
++
++ struct yaffs_ShadowFixerStruct *fixer;
++ fixer = YMALLOC(sizeof(struct yaffs_ShadowFixerStruct));
++ if(fixer){
++ fixer-> next = shadowFixerList;
++ shadowFixerList = fixer;
++ fixer->objectId = tags.objectId;
++ fixer->shadowedId = oh->shadowsObject;
++ }
++
++ }
++
++ if (in && in->valid) {
++ /* We have already filled this one. We have a duplicate and need to resolve it. */
++
++ unsigned existingSerial = in->serial;
++ unsigned newSerial = tags.serialNumber;
++
++ if (((existingSerial + 1) & 3) == newSerial) {
++ /* Use new one - destroy the exisiting one */
++ yaffs_DeleteChunk(dev,
++ in->hdrChunk,
++ 1, __LINE__);
++ in->valid = 0;
++ } else {
++ /* Use existing - destroy this one. */
++ yaffs_DeleteChunk(dev, chunk, 1,
++ __LINE__);
++ }
++ }
++
++ if (in && !in->valid &&
++ (tags.objectId == YAFFS_OBJECTID_ROOT ||
++ tags.objectId == YAFFS_OBJECTID_LOSTNFOUND)) {
++ /* We only load some info, don't fiddle with directory structure */
++ in->valid = 1;
++ in->variantType = oh->type;
++
++ in->yst_mode = oh->yst_mode;
++#ifdef CONFIG_YAFFS_WINCE
++ in->win_atime[0] = oh->win_atime[0];
++ in->win_ctime[0] = oh->win_ctime[0];
++ in->win_mtime[0] = oh->win_mtime[0];
++ in->win_atime[1] = oh->win_atime[1];
++ in->win_ctime[1] = oh->win_ctime[1];
++ in->win_mtime[1] = oh->win_mtime[1];
++#else
++ in->yst_uid = oh->yst_uid;
++ in->yst_gid = oh->yst_gid;
++ in->yst_atime = oh->yst_atime;
++ in->yst_mtime = oh->yst_mtime;
++ in->yst_ctime = oh->yst_ctime;
++ in->yst_rdev = oh->yst_rdev;
++#endif
++ in->hdrChunk = chunk;
++ in->serial = tags.serialNumber;
++
++ } else if (in && !in->valid) {
++ /* we need to load this info */
++
++ in->valid = 1;
++ in->variantType = oh->type;
++
++ in->yst_mode = oh->yst_mode;
++#ifdef CONFIG_YAFFS_WINCE
++ in->win_atime[0] = oh->win_atime[0];
++ in->win_ctime[0] = oh->win_ctime[0];
++ in->win_mtime[0] = oh->win_mtime[0];
++ in->win_atime[1] = oh->win_atime[1];
++ in->win_ctime[1] = oh->win_ctime[1];
++ in->win_mtime[1] = oh->win_mtime[1];
++#else
++ in->yst_uid = oh->yst_uid;
++ in->yst_gid = oh->yst_gid;
++ in->yst_atime = oh->yst_atime;
++ in->yst_mtime = oh->yst_mtime;
++ in->yst_ctime = oh->yst_ctime;
++ in->yst_rdev = oh->yst_rdev;
++#endif
++ in->hdrChunk = chunk;
++ in->serial = tags.serialNumber;
++
++ yaffs_SetObjectName(in, oh->name);
++ in->dirty = 0;
++
++ /* directory stuff...
++ * hook up to parent
++ */
++
++ parent =
++ yaffs_FindOrCreateObjectByNumber
++ (dev, oh->parentObjectId,
++ YAFFS_OBJECT_TYPE_DIRECTORY);
++ if (parent->variantType ==
++ YAFFS_OBJECT_TYPE_UNKNOWN) {
++ /* Set up as a directory */
++ parent->variantType =
++ YAFFS_OBJECT_TYPE_DIRECTORY;
++ YINIT_LIST_HEAD(&parent->variant.
++ directoryVariant.
++ children);
++ } else if (parent->variantType !=
++ YAFFS_OBJECT_TYPE_DIRECTORY)
++ {
++ /* Hoosterman, another problem....
++ * We're trying to use a non-directory as a directory
++ */
++
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
++ TENDSTR)));
++ parent = dev->lostNFoundDir;
++ }
++
++ yaffs_AddObjectToDirectory(parent, in);
++
++ if (0 && (parent == dev->deletedDir ||
++ parent == dev->unlinkedDir)) {
++ in->deleted = 1; /* If it is unlinked at start up then it wants deleting */
++ dev->nDeletedFiles++;
++ }
++ /* Note re hardlinks.
++ * Since we might scan a hardlink before its equivalent object is scanned
++ * we put them all in a list.
++ * After scanning is complete, we should have all the objects, so we run through this
++ * list and fix up all the chains.
++ */
++
++ switch (in->variantType) {
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ /* Todo got a problem */
++ break;
++ case YAFFS_OBJECT_TYPE_FILE:
++ if (dev->useHeaderFileSize)
++
++ in->variant.fileVariant.
++ fileSize =
++ oh->fileSize;
++
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ in->variant.hardLinkVariant.
++ equivalentObjectId =
++ oh->equivalentObjectId;
++ in->hardLinks.next =
++ (struct ylist_head *)
++ hardList;
++ hardList = in;
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ /* Do nothing */
++ break;
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ /* Do nothing */
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ in->variant.symLinkVariant.alias =
++ yaffs_CloneString(oh->alias);
++ if(!in->variant.symLinkVariant.alias)
++ alloc_failed = 1;
++ break;
++ }
++
++/*
++ if (parent == dev->deletedDir) {
++ yaffs_DestroyObject(in);
++ bi->hasShrinkHeader = 1;
++ }
++*/
++ }
++ }
++ }
++
++ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
++ /* If we got this far while scanning, then the block is fully allocated.*/
++ state = YAFFS_BLOCK_STATE_FULL;
++ }
++
++ bi->blockState = state;
++
++ /* Now let's see if it was dirty */
++ if (bi->pagesInUse == 0 &&
++ !bi->hasShrinkHeader &&
++ bi->blockState == YAFFS_BLOCK_STATE_FULL) {
++ yaffs_BlockBecameDirty(dev, blk);
++ }
++
++ }
++
++
++ /* Ok, we've done all the scanning.
++ * Fix up the hard link chains.
++ * We should now have scanned all the objects, now it's time to add these
++ * hardlinks.
++ */
++
++ yaffs_HardlinkFixup(dev,hardList);
++
++ /* Fix up any shadowed objects */
++ {
++ struct yaffs_ShadowFixerStruct *fixer;
++ yaffs_Object *obj;
++
++ while(shadowFixerList){
++ fixer = shadowFixerList;
++ shadowFixerList = fixer->next;
++ /* Complete the rename transaction by deleting the shadowed object
++ * then setting the object header to unshadowed.
++ */
++ obj = yaffs_FindObjectByNumber(dev,fixer->shadowedId);
++ if(obj)
++ yaffs_DestroyObject(obj);
++
++ obj = yaffs_FindObjectByNumber(dev,fixer->objectId);
++ if(obj){
++ yaffs_UpdateObjectHeader(obj,NULL,1,0,0);
++ }
++
++ YFREE(fixer);
++ }
++ }
++
++ yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
++
++ if(alloc_failed){
++ return YAFFS_FAIL;
++ }
++
++ T(YAFFS_TRACE_SCAN, (TSTR("yaffs_Scan ends" TENDSTR)));
++
++
++ return YAFFS_OK;
++}
++
++static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in)
++{
++ __u8 *chunkData;
++ yaffs_ObjectHeader *oh;
++ yaffs_Device *dev;
++ yaffs_ExtendedTags tags;
++ int result;
++ int alloc_failed = 0;
++
++ if(!in)
++ return;
++
++ dev = in->myDev;
++
++#if 0
++ T(YAFFS_TRACE_SCAN,(TSTR("details for object %d %s loaded" TENDSTR),
++ in->objectId,
++ in->lazyLoaded ? "not yet" : "already"));
++#endif
++
++ if(in->lazyLoaded && in->hdrChunk > 0){
++ in->lazyLoaded = 0;
++ chunkData = yaffs_GetTempBuffer(dev, __LINE__);
++
++ result = yaffs_ReadChunkWithTagsFromNAND(dev,in->hdrChunk,chunkData,&tags);
++ oh = (yaffs_ObjectHeader *) chunkData;
++
++ in->yst_mode = oh->yst_mode;
++#ifdef CONFIG_YAFFS_WINCE
++ in->win_atime[0] = oh->win_atime[0];
++ in->win_ctime[0] = oh->win_ctime[0];
++ in->win_mtime[0] = oh->win_mtime[0];
++ in->win_atime[1] = oh->win_atime[1];
++ in->win_ctime[1] = oh->win_ctime[1];
++ in->win_mtime[1] = oh->win_mtime[1];
++#else
++ in->yst_uid = oh->yst_uid;
++ in->yst_gid = oh->yst_gid;
++ in->yst_atime = oh->yst_atime;
++ in->yst_mtime = oh->yst_mtime;
++ in->yst_ctime = oh->yst_ctime;
++ in->yst_rdev = oh->yst_rdev;
++
++#endif
++ yaffs_SetObjectName(in, oh->name);
++
++ if(in->variantType == YAFFS_OBJECT_TYPE_SYMLINK){
++ in->variant.symLinkVariant.alias =
++ yaffs_CloneString(oh->alias);
++ if(!in->variant.symLinkVariant.alias)
++ alloc_failed = 1; /* Not returned to caller */
++ }
++
++ yaffs_ReleaseTempBuffer(dev,chunkData, __LINE__);
++ }
++}
++
++static int yaffs_ScanBackwards(yaffs_Device * dev)
++{
++ yaffs_ExtendedTags tags;
++ int blk;
++ int blockIterator;
++ int startIterator;
++ int endIterator;
++ int nBlocksToScan = 0;
++
++ int chunk;
++ int result;
++ int c;
++ int deleted;
++ yaffs_BlockState state;
++ yaffs_Object *hardList = NULL;
++ yaffs_BlockInfo *bi;
++ __u32 sequenceNumber;
++ yaffs_ObjectHeader *oh;
++ yaffs_Object *in;
++ yaffs_Object *parent;
++ int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
++ int itsUnlinked;
++ __u8 *chunkData;
++
++ int fileSize;
++ int isShrink;
++ int foundChunksInBlock;
++ int equivalentObjectId;
++ int alloc_failed = 0;
++
++
++ yaffs_BlockIndex *blockIndex = NULL;
++ int altBlockIndex = 0;
++
++ if (!dev->isYaffs2) {
++ T(YAFFS_TRACE_SCAN,
++ (TSTR("yaffs_ScanBackwards is only for YAFFS2!" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ T(YAFFS_TRACE_SCAN,
++ (TSTR
++ ("yaffs_ScanBackwards starts intstartblk %d intendblk %d..."
++ TENDSTR), dev->internalStartBlock, dev->internalEndBlock));
++
++
++ dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
++
++ blockIndex = YMALLOC(nBlocks * sizeof(yaffs_BlockIndex));
++
++ if(!blockIndex) {
++ blockIndex = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockIndex));
++ altBlockIndex = 1;
++ }
++
++ if(!blockIndex) {
++ T(YAFFS_TRACE_SCAN,
++ (TSTR("yaffs_Scan() could not allocate block index!" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ dev->blocksInCheckpoint = 0;
++
++ chunkData = yaffs_GetTempBuffer(dev, __LINE__);
++
++ /* Scan all the blocks to determine their state */
++ for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
++ bi = yaffs_GetBlockInfo(dev, blk);
++ yaffs_ClearChunkBits(dev, blk);
++ bi->pagesInUse = 0;
++ bi->softDeletions = 0;
++
++ yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
++
++ bi->blockState = state;
++ bi->sequenceNumber = sequenceNumber;
++
++ if(bi->sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA)
++ bi->blockState = state = YAFFS_BLOCK_STATE_CHECKPOINT;
++
++ T(YAFFS_TRACE_SCAN_DEBUG,
++ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
++ state, sequenceNumber));
++
++
++ if(state == YAFFS_BLOCK_STATE_CHECKPOINT){
++ dev->blocksInCheckpoint++;
++
++ } else if (state == YAFFS_BLOCK_STATE_DEAD) {
++ T(YAFFS_TRACE_BAD_BLOCKS,
++ (TSTR("block %d is bad" TENDSTR), blk));
++ } else if (state == YAFFS_BLOCK_STATE_EMPTY) {
++ T(YAFFS_TRACE_SCAN_DEBUG,
++ (TSTR("Block empty " TENDSTR)));
++ dev->nErasedBlocks++;
++ dev->nFreeChunks += dev->nChunksPerBlock;
++ } else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
++
++ /* Determine the highest sequence number */
++ if (sequenceNumber >= YAFFS_LOWEST_SEQUENCE_NUMBER &&
++ sequenceNumber < YAFFS_HIGHEST_SEQUENCE_NUMBER) {
++
++ blockIndex[nBlocksToScan].seq = sequenceNumber;
++ blockIndex[nBlocksToScan].block = blk;
++
++ nBlocksToScan++;
++
++ if (sequenceNumber >= dev->sequenceNumber) {
++ dev->sequenceNumber = sequenceNumber;
++ }
++ } else {
++ /* TODO: Nasty sequence number! */
++ T(YAFFS_TRACE_SCAN,
++ (TSTR
++ ("Block scanning block %d has bad sequence number %d"
++ TENDSTR), blk, sequenceNumber));
++
++ }
++ }
++ }
++
++ T(YAFFS_TRACE_SCAN,
++ (TSTR("%d blocks to be sorted..." TENDSTR), nBlocksToScan));
++
++
++
++ YYIELD();
++
++ /* Sort the blocks */
++#ifndef CONFIG_YAFFS_USE_OWN_SORT
++ {
++ /* Use qsort now. */
++ yaffs_qsort(blockIndex, nBlocksToScan, sizeof(yaffs_BlockIndex), ybicmp);
++ }
++#else
++ {
++ /* Dungy old bubble sort... */
++
++ yaffs_BlockIndex temp;
++ int i;
++ int j;
++
++ for (i = 0; i < nBlocksToScan; i++)
++ for (j = i + 1; j < nBlocksToScan; j++)
++ if (blockIndex[i].seq > blockIndex[j].seq) {
++ temp = blockIndex[j];
++ blockIndex[j] = blockIndex[i];
++ blockIndex[i] = temp;
++ }
++ }
++#endif
++
++ YYIELD();
++
++ T(YAFFS_TRACE_SCAN, (TSTR("...done" TENDSTR)));
++
++ /* Now scan the blocks looking at the data. */
++ startIterator = 0;
++ endIterator = nBlocksToScan - 1;
++ T(YAFFS_TRACE_SCAN_DEBUG,
++ (TSTR("%d blocks to be scanned" TENDSTR), nBlocksToScan));
++
++ /* For each block.... backwards */
++ for (blockIterator = endIterator; !alloc_failed && blockIterator >= startIterator;
++ blockIterator--) {
++ /* Cooperative multitasking! This loop can run for so
++ long that watchdog timers expire. */
++ YYIELD();
++
++ /* get the block to scan in the correct order */
++ blk = blockIndex[blockIterator].block;
++
++ bi = yaffs_GetBlockInfo(dev, blk);
++
++
++ state = bi->blockState;
++
++ deleted = 0;
++
++ /* For each chunk in each block that needs scanning.... */
++ foundChunksInBlock = 0;
++ for (c = dev->nChunksPerBlock - 1;
++ !alloc_failed && c >= 0 &&
++ (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
++ state == YAFFS_BLOCK_STATE_ALLOCATING); c--) {
++ /* Scan backwards...
++ * Read the tags and decide what to do
++ */
++
++ chunk = blk * dev->nChunksPerBlock + c;
++
++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
++ &tags);
++
++ /* Let's have a good look at this chunk... */
++
++ if (!tags.chunkUsed) {
++ /* An unassigned chunk in the block.
++ * If there are used chunks after this one, then
++ * it is a chunk that was skipped due to failing the erased
++ * check. Just skip it so that it can be deleted.
++ * But, more typically, We get here when this is an unallocated
++ * chunk and his means that either the block is empty or
++ * this is the one being allocated from
++ */
++
++ if(foundChunksInBlock)
++ {
++ /* This is a chunk that was skipped due to failing the erased check */
++
++ } else if (c == 0) {
++ /* We're looking at the first chunk in the block so the block is unused */
++ state = YAFFS_BLOCK_STATE_EMPTY;
++ dev->nErasedBlocks++;
++ } else {
++ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
++ state == YAFFS_BLOCK_STATE_ALLOCATING) {
++ if(dev->sequenceNumber == bi->sequenceNumber) {
++ /* this is the block being allocated from */
++
++ T(YAFFS_TRACE_SCAN,
++ (TSTR
++ (" Allocating from %d %d"
++ TENDSTR), blk, c));
++
++ state = YAFFS_BLOCK_STATE_ALLOCATING;
++ dev->allocationBlock = blk;
++ dev->allocationPage = c;
++ dev->allocationBlockFinder = blk;
++ }
++ else {
++ /* This is a partially written block that is not
++ * the current allocation block. This block must have
++ * had a write failure, so set up for retirement.
++ */
++
++ /* bi->needsRetiring = 1; ??? TODO */
++ bi->gcPrioritise = 1;
++
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("Partially written block %d detected" TENDSTR),
++ blk));
++ }
++
++ }
++
++ }
++
++ dev->nFreeChunks++;
++
++ } else if (tags.chunkId > 0) {
++ /* chunkId > 0 so it is a data chunk... */
++ unsigned int endpos;
++ __u32 chunkBase =
++ (tags.chunkId - 1) * dev->nDataBytesPerChunk;
++
++ foundChunksInBlock = 1;
++
++
++ yaffs_SetChunkBit(dev, blk, c);
++ bi->pagesInUse++;
++
++ in = yaffs_FindOrCreateObjectByNumber(dev,
++ tags.
++ objectId,
++ YAFFS_OBJECT_TYPE_FILE);
++ if(!in){
++ /* Out of memory */
++ alloc_failed = 1;
++ }
++
++ if (in &&
++ in->variantType == YAFFS_OBJECT_TYPE_FILE
++ && chunkBase <
++ in->variant.fileVariant.shrinkSize) {
++ /* This has not been invalidated by a resize */
++ if(!yaffs_PutChunkIntoFile(in, tags.chunkId,
++ chunk, -1)){
++ alloc_failed = 1;
++ }
++
++ /* File size is calculated by looking at the data chunks if we have not
++ * seen an object header yet. Stop this practice once we find an object header.
++ */
++ endpos =
++ (tags.chunkId -
++ 1) * dev->nDataBytesPerChunk +
++ tags.byteCount;
++
++ if (!in->valid && /* have not got an object header yet */
++ in->variant.fileVariant.
++ scannedFileSize < endpos) {
++ in->variant.fileVariant.
++ scannedFileSize = endpos;
++ in->variant.fileVariant.
++ fileSize =
++ in->variant.fileVariant.
++ scannedFileSize;
++ }
++
++ } else if(in) {
++ /* This chunk has been invalidated by a resize, so delete */
++ yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
++
++ }
++ } else {
++ /* chunkId == 0, so it is an ObjectHeader.
++ * Thus, we read in the object header and make the object
++ */
++ foundChunksInBlock = 1;
++
++ yaffs_SetChunkBit(dev, blk, c);
++ bi->pagesInUse++;
++
++ oh = NULL;
++ in = NULL;
++
++ if (tags.extraHeaderInfoAvailable) {
++ in = yaffs_FindOrCreateObjectByNumber
++ (dev, tags.objectId,
++ tags.extraObjectType);
++ }
++
++ if (!in ||
++#ifdef CONFIG_YAFFS_DISABLE_LAZY_LOAD
++ !in->valid ||
++#endif
++ tags.extraShadows ||
++ (!in->valid &&
++ (tags.objectId == YAFFS_OBJECTID_ROOT ||
++ tags.objectId == YAFFS_OBJECTID_LOSTNFOUND))
++ ) {
++
++ /* If we don't have valid info then we need to read the chunk
++ * TODO In future we can probably defer reading the chunk and
++ * living with invalid data until needed.
++ */
++
++ result = yaffs_ReadChunkWithTagsFromNAND(dev,
++ chunk,
++ chunkData,
++ NULL);
++
++ oh = (yaffs_ObjectHeader *) chunkData;
++
++ if(dev->inbandTags){
++ /* Fix up the header if they got corrupted by inband tags */
++ oh->shadowsObject = oh->inbandShadowsObject;
++ oh->isShrink = oh->inbandIsShrink;
++ }
++
++ if (!in)
++ in = yaffs_FindOrCreateObjectByNumber(dev, tags.objectId, oh->type);
++
++ }
++
++ if (!in) {
++ /* TODO Hoosterman we have a problem! */
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("yaffs tragedy: Could not make object for object %d at chunk %d during scan"
++ TENDSTR), tags.objectId, chunk));
++
++ }
++
++ if (in->valid) {
++ /* We have already filled this one.
++ * We have a duplicate that will be discarded, but
++ * we first have to suck out resize info if it is a file.
++ */
++
++ if ((in->variantType == YAFFS_OBJECT_TYPE_FILE) &&
++ ((oh &&
++ oh-> type == YAFFS_OBJECT_TYPE_FILE)||
++ (tags.extraHeaderInfoAvailable &&
++ tags.extraObjectType == YAFFS_OBJECT_TYPE_FILE))
++ ) {
++ __u32 thisSize =
++ (oh) ? oh->fileSize : tags.
++ extraFileLength;
++ __u32 parentObjectId =
++ (oh) ? oh->
++ parentObjectId : tags.
++ extraParentObjectId;
++
++
++ isShrink =
++ (oh) ? oh->isShrink : tags.
++ extraIsShrinkHeader;
++
++ /* If it is deleted (unlinked at start also means deleted)
++ * we treat the file size as being zeroed at this point.
++ */
++ if (parentObjectId ==
++ YAFFS_OBJECTID_DELETED
++ || parentObjectId ==
++ YAFFS_OBJECTID_UNLINKED) {
++ thisSize = 0;
++ isShrink = 1;
++ }
++
++ if (isShrink &&
++ in->variant.fileVariant.
++ shrinkSize > thisSize) {
++ in->variant.fileVariant.
++ shrinkSize =
++ thisSize;
++ }
++
++ if (isShrink) {
++ bi->hasShrinkHeader = 1;
++ }
++
++ }
++ /* Use existing - destroy this one. */
++ yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
++
++ }
++
++ if (!in->valid &&
++ (tags.objectId == YAFFS_OBJECTID_ROOT ||
++ tags.objectId ==
++ YAFFS_OBJECTID_LOSTNFOUND)) {
++ /* We only load some info, don't fiddle with directory structure */
++ in->valid = 1;
++
++ if(oh) {
++ in->variantType = oh->type;
++
++ in->yst_mode = oh->yst_mode;
++#ifdef CONFIG_YAFFS_WINCE
++ in->win_atime[0] = oh->win_atime[0];
++ in->win_ctime[0] = oh->win_ctime[0];
++ in->win_mtime[0] = oh->win_mtime[0];
++ in->win_atime[1] = oh->win_atime[1];
++ in->win_ctime[1] = oh->win_ctime[1];
++ in->win_mtime[1] = oh->win_mtime[1];
++#else
++ in->yst_uid = oh->yst_uid;
++ in->yst_gid = oh->yst_gid;
++ in->yst_atime = oh->yst_atime;
++ in->yst_mtime = oh->yst_mtime;
++ in->yst_ctime = oh->yst_ctime;
++ in->yst_rdev = oh->yst_rdev;
++
++#endif
++ } else {
++ in->variantType = tags.extraObjectType;
++ in->lazyLoaded = 1;
++ }
++
++ in->hdrChunk = chunk;
++
++ } else if (!in->valid) {
++ /* we need to load this info */
++
++ in->valid = 1;
++ in->hdrChunk = chunk;
++
++ if(oh) {
++ in->variantType = oh->type;
++
++ in->yst_mode = oh->yst_mode;
++#ifdef CONFIG_YAFFS_WINCE
++ in->win_atime[0] = oh->win_atime[0];
++ in->win_ctime[0] = oh->win_ctime[0];
++ in->win_mtime[0] = oh->win_mtime[0];
++ in->win_atime[1] = oh->win_atime[1];
++ in->win_ctime[1] = oh->win_ctime[1];
++ in->win_mtime[1] = oh->win_mtime[1];
++#else
++ in->yst_uid = oh->yst_uid;
++ in->yst_gid = oh->yst_gid;
++ in->yst_atime = oh->yst_atime;
++ in->yst_mtime = oh->yst_mtime;
++ in->yst_ctime = oh->yst_ctime;
++ in->yst_rdev = oh->yst_rdev;
++#endif
++
++ if (oh->shadowsObject > 0)
++ yaffs_HandleShadowedObject(dev,
++ oh->
++ shadowsObject,
++ 1);
++
++
++ yaffs_SetObjectName(in, oh->name);
++ parent =
++ yaffs_FindOrCreateObjectByNumber
++ (dev, oh->parentObjectId,
++ YAFFS_OBJECT_TYPE_DIRECTORY);
++
++ fileSize = oh->fileSize;
++ isShrink = oh->isShrink;
++ equivalentObjectId = oh->equivalentObjectId;
++
++ }
++ else {
++ in->variantType = tags.extraObjectType;
++ parent =
++ yaffs_FindOrCreateObjectByNumber
++ (dev, tags.extraParentObjectId,
++ YAFFS_OBJECT_TYPE_DIRECTORY);
++ fileSize = tags.extraFileLength;
++ isShrink = tags.extraIsShrinkHeader;
++ equivalentObjectId = tags.extraEquivalentObjectId;
++ in->lazyLoaded = 1;
++
++ }
++ in->dirty = 0;
++
++ /* directory stuff...
++ * hook up to parent
++ */
++
++ if (parent->variantType ==
++ YAFFS_OBJECT_TYPE_UNKNOWN) {
++ /* Set up as a directory */
++ parent->variantType =
++ YAFFS_OBJECT_TYPE_DIRECTORY;
++ YINIT_LIST_HEAD(&parent->variant.
++ directoryVariant.
++ children);
++ } else if (parent->variantType !=
++ YAFFS_OBJECT_TYPE_DIRECTORY)
++ {
++ /* Hoosterman, another problem....
++ * We're trying to use a non-directory as a directory
++ */
++
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
++ TENDSTR)));
++ parent = dev->lostNFoundDir;
++ }
++
++ yaffs_AddObjectToDirectory(parent, in);
++
++ itsUnlinked = (parent == dev->deletedDir) ||
++ (parent == dev->unlinkedDir);
++
++ if (isShrink) {
++ /* Mark the block as having a shrinkHeader */
++ bi->hasShrinkHeader = 1;
++ }
++
++ /* Note re hardlinks.
++ * Since we might scan a hardlink before its equivalent object is scanned
++ * we put them all in a list.
++ * After scanning is complete, we should have all the objects, so we run
++ * through this list and fix up all the chains.
++ */
++
++ switch (in->variantType) {
++ case YAFFS_OBJECT_TYPE_UNKNOWN:
++ /* Todo got a problem */
++ break;
++ case YAFFS_OBJECT_TYPE_FILE:
++
++ if (in->variant.fileVariant.
++ scannedFileSize < fileSize) {
++ /* This covers the case where the file size is greater
++ * than where the data is
++ * This will happen if the file is resized to be larger
++ * than its current data extents.
++ */
++ in->variant.fileVariant.fileSize = fileSize;
++ in->variant.fileVariant.scannedFileSize =
++ in->variant.fileVariant.fileSize;
++ }
++
++ if (isShrink &&
++ in->variant.fileVariant.shrinkSize > fileSize) {
++ in->variant.fileVariant.shrinkSize = fileSize;
++ }
++
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ if(!itsUnlinked) {
++ in->variant.hardLinkVariant.equivalentObjectId =
++ equivalentObjectId;
++ in->hardLinks.next =
++ (struct ylist_head *) hardList;
++ hardList = in;
++ }
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ /* Do nothing */
++ break;
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ /* Do nothing */
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ if(oh){
++ in->variant.symLinkVariant.alias =
++ yaffs_CloneString(oh->
++ alias);
++ if(!in->variant.symLinkVariant.alias)
++ alloc_failed = 1;
++ }
++ break;
++ }
++
++ }
++
++ }
++
++ } /* End of scanning for each chunk */
++
++ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
++ /* If we got this far while scanning, then the block is fully allocated. */
++ state = YAFFS_BLOCK_STATE_FULL;
++ }
++
++ bi->blockState = state;
++
++ /* Now let's see if it was dirty */
++ if (bi->pagesInUse == 0 &&
++ !bi->hasShrinkHeader &&
++ bi->blockState == YAFFS_BLOCK_STATE_FULL) {
++ yaffs_BlockBecameDirty(dev, blk);
++ }
++
++ }
++
++ if (altBlockIndex)
++ YFREE_ALT(blockIndex);
++ else
++ YFREE(blockIndex);
++
++ /* Ok, we've done all the scanning.
++ * Fix up the hard link chains.
++ * We should now have scanned all the objects, now it's time to add these
++ * hardlinks.
++ */
++ yaffs_HardlinkFixup(dev,hardList);
++
++
++ yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
++
++ if(alloc_failed){
++ return YAFFS_FAIL;
++ }
++
++ T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards ends" TENDSTR)));
++
++ return YAFFS_OK;
++}
++
++/*------------------------------ Directory Functions ----------------------------- */
++
++static void yaffs_VerifyObjectInDirectory(yaffs_Object *obj)
++{
++ struct ylist_head *lh;
++ yaffs_Object *listObj;
++
++ int count = 0;
++
++ if(!obj){
++ T(YAFFS_TRACE_ALWAYS, (TSTR("No object to verify" TENDSTR)));
++ YBUG();
++ }
++
++ if(yaffs_SkipVerification(obj->myDev))
++ return;
++
++ if(!obj->parent){
++ T(YAFFS_TRACE_ALWAYS, (TSTR("Object does not have parent" TENDSTR)));
++ YBUG();
++ }
++
++ if(obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY){
++ T(YAFFS_TRACE_ALWAYS, (TSTR("Parent is not directory" TENDSTR)));
++ YBUG();
++ }
++
++ /* Iterate through the objects in each hash entry */
++
++ ylist_for_each(lh, &obj->parent->variant.directoryVariant.children) {
++ if (lh) {
++ listObj = ylist_entry(lh, yaffs_Object, siblings);
++ yaffs_VerifyObject(listObj);
++ if(obj == listObj)
++ count ++;
++ }
++ }
++
++ if(count != 1){
++ T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory %d times" TENDSTR),count));
++ YBUG();
++ }
++
++}
++
++static void yaffs_VerifyDirectory(yaffs_Object *directory)
++{
++
++ struct ylist_head *lh;
++ yaffs_Object *listObj;
++
++ if(!directory)
++ YBUG();
++
++ if(yaffs_SkipFullVerification(directory->myDev))
++ return;
++
++
++ if(directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY){
++ T(YAFFS_TRACE_ALWAYS, (TSTR("Directory has wrong type: %d" TENDSTR),directory->variantType));
++ YBUG();
++ }
++
++ /* Iterate through the objects in each hash entry */
++
++ ylist_for_each(lh, &directory->variant.directoryVariant.children) {
++ if (lh) {
++ listObj = ylist_entry(lh, yaffs_Object, siblings);
++ if(listObj->parent != directory){
++ T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory list has wrong parent %p" TENDSTR),listObj->parent));
++ YBUG();
++ }
++ yaffs_VerifyObjectInDirectory(listObj);
++ }
++ }
++
++}
++
++
++static void yaffs_RemoveObjectFromDirectory(yaffs_Object * obj)
++{
++ yaffs_Device *dev = obj->myDev;
++ yaffs_Object *parent;
++
++ yaffs_VerifyObjectInDirectory(obj);
++ parent = obj->parent;
++
++ yaffs_VerifyDirectory(parent);
++
++ if(dev && dev->removeObjectCallback)
++ dev->removeObjectCallback(obj);
++
++
++ ylist_del_init(&obj->siblings);
++ obj->parent = NULL;
++
++ yaffs_VerifyDirectory(parent);
++
++}
++
++
++static void yaffs_AddObjectToDirectory(yaffs_Object * directory,
++ yaffs_Object * obj)
++{
++
++ if (!directory) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("tragedy: Trying to add an object to a null pointer directory"
++ TENDSTR)));
++ YBUG();
++ }
++ if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("tragedy: Trying to add an object to a non-directory"
++ TENDSTR)));
++ YBUG();
++ }
++
++ if (obj->siblings.prev == NULL) {
++ /* Not initialised */
++ YBUG();
++
++ } else if (ylist_empty(&obj->siblings)) {
++ YBUG();
++ }
++
++
++ yaffs_VerifyDirectory(directory);
++
++ yaffs_RemoveObjectFromDirectory(obj);
++
++
++ /* Now add it */
++ ylist_add(&obj->siblings, &directory->variant.directoryVariant.children);
++ obj->parent = directory;
++
++ if (directory == obj->myDev->unlinkedDir
++ || directory == obj->myDev->deletedDir) {
++ obj->unlinked = 1;
++ obj->myDev->nUnlinkedFiles++;
++ obj->renameAllowed = 0;
++ }
++
++ yaffs_VerifyDirectory(directory);
++ yaffs_VerifyObjectInDirectory(obj);
++
++
++}
++
++yaffs_Object *yaffs_FindObjectByName(yaffs_Object * directory,
++ const YCHAR * name)
++{
++ int sum;
++
++ struct ylist_head *i;
++ YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1];
++
++ yaffs_Object *l;
++
++ if (!name) {
++ return NULL;
++ }
++
++ if (!directory) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("tragedy: yaffs_FindObjectByName: null pointer directory"
++ TENDSTR)));
++ YBUG();
++ }
++ if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
++ YBUG();
++ }
++
++ sum = yaffs_CalcNameSum(name);
++
++ ylist_for_each(i, &directory->variant.directoryVariant.children) {
++ if (i) {
++ l = ylist_entry(i, yaffs_Object, siblings);
++
++ if(l->parent != directory)
++ YBUG();
++
++ yaffs_CheckObjectDetailsLoaded(l);
++
++ /* Special case for lost-n-found */
++ if (l->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
++ if (yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME) == 0) {
++ return l;
++ }
++ } else if (yaffs_SumCompare(l->sum, sum) || l->hdrChunk <= 0){
++ /* LostnFound chunk called Objxxx
++ * Do a real check
++ */
++ yaffs_GetObjectName(l, buffer,
++ YAFFS_MAX_NAME_LENGTH);
++ if (yaffs_strncmp(name, buffer,YAFFS_MAX_NAME_LENGTH) == 0) {
++ return l;
++ }
++
++ }
++ }
++ }
++
++ return NULL;
++}
++
++
++#if 0
++int yaffs_ApplyToDirectoryChildren(yaffs_Object * theDir,
++ int (*fn) (yaffs_Object *))
++{
++ struct ylist_head *i;
++ yaffs_Object *l;
++
++ if (!theDir) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("tragedy: yaffs_FindObjectByName: null pointer directory"
++ TENDSTR)));
++ YBUG();
++ }
++ if (theDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
++ YBUG();
++ }
++
++ ylist_for_each(i, &theDir->variant.directoryVariant.children) {
++ if (i) {
++ l = ylist_entry(i, yaffs_Object, siblings);
++ if (l && !fn(l)) {
++ return YAFFS_FAIL;
++ }
++ }
++ }
++
++ return YAFFS_OK;
++
++}
++#endif
++
++/* GetEquivalentObject dereferences any hard links to get to the
++ * actual object.
++ */
++
++yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object * obj)
++{
++ if (obj && obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
++ /* We want the object id of the equivalent object, not this one */
++ obj = obj->variant.hardLinkVariant.equivalentObject;
++ yaffs_CheckObjectDetailsLoaded(obj);
++ }
++ return obj;
++
++}
++
++int yaffs_GetObjectName(yaffs_Object * obj, YCHAR * name, int buffSize)
++{
++ memset(name, 0, buffSize * sizeof(YCHAR));
++
++ yaffs_CheckObjectDetailsLoaded(obj);
++
++ if (obj->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
++ yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffSize - 1);
++ } else if (obj->hdrChunk <= 0) {
++ YCHAR locName[20];
++ YCHAR numString[20];
++ YCHAR *x = &numString[19];
++ unsigned v = obj->objectId;
++ numString[19] = 0;
++ while(v>0){
++ x--;
++ *x = '0' + (v % 10);
++ v /= 10;
++ }
++ /* make up a name */
++ yaffs_strcpy(locName, YAFFS_LOSTNFOUND_PREFIX);
++ yaffs_strcat(locName,x);
++ yaffs_strncpy(name, locName, buffSize - 1);
++
++ }
++#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
++ else if (obj->shortName[0]) {
++ yaffs_strcpy(name, obj->shortName);
++ }
++#endif
++ else {
++ int result;
++ __u8 *buffer = yaffs_GetTempBuffer(obj->myDev, __LINE__);
++
++ yaffs_ObjectHeader *oh = (yaffs_ObjectHeader *) buffer;
++
++ memset(buffer, 0, obj->myDev->nDataBytesPerChunk);
++
++ if (obj->hdrChunk > 0) {
++ result = yaffs_ReadChunkWithTagsFromNAND(obj->myDev,
++ obj->hdrChunk, buffer,
++ NULL);
++ }
++ yaffs_strncpy(name, oh->name, buffSize - 1);
++
++ yaffs_ReleaseTempBuffer(obj->myDev, buffer, __LINE__);
++ }
++
++ return yaffs_strlen(name);
++}
++
++int yaffs_GetObjectFileLength(yaffs_Object * obj)
++{
++
++ /* Dereference any hard linking */
++ obj = yaffs_GetEquivalentObject(obj);
++
++ if (obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
++ return obj->variant.fileVariant.fileSize;
++ }
++ if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK) {
++ return yaffs_strlen(obj->variant.symLinkVariant.alias);
++ } else {
++ /* Only a directory should drop through to here */
++ return obj->myDev->nDataBytesPerChunk;
++ }
++}
++
++int yaffs_GetObjectLinkCount(yaffs_Object * obj)
++{
++ int count = 0;
++ struct ylist_head *i;
++
++ if (!obj->unlinked) {
++ count++; /* the object itself */
++ }
++ ylist_for_each(i, &obj->hardLinks) {
++ count++; /* add the hard links; */
++ }
++ return count;
++
++}
++
++int yaffs_GetObjectInode(yaffs_Object * obj)
++{
++ obj = yaffs_GetEquivalentObject(obj);
++
++ return obj->objectId;
++}
++
++unsigned yaffs_GetObjectType(yaffs_Object * obj)
++{
++ obj = yaffs_GetEquivalentObject(obj);
++
++ switch (obj->variantType) {
++ case YAFFS_OBJECT_TYPE_FILE:
++ return DT_REG;
++ break;
++ case YAFFS_OBJECT_TYPE_DIRECTORY:
++ return DT_DIR;
++ break;
++ case YAFFS_OBJECT_TYPE_SYMLINK:
++ return DT_LNK;
++ break;
++ case YAFFS_OBJECT_TYPE_HARDLINK:
++ return DT_REG;
++ break;
++ case YAFFS_OBJECT_TYPE_SPECIAL:
++ if (S_ISFIFO(obj->yst_mode))
++ return DT_FIFO;
++ if (S_ISCHR(obj->yst_mode))
++ return DT_CHR;
++ if (S_ISBLK(obj->yst_mode))
++ return DT_BLK;
++ if (S_ISSOCK(obj->yst_mode))
++ return DT_SOCK;
++ default:
++ return DT_REG;
++ break;
++ }
++}
++
++YCHAR *yaffs_GetSymlinkAlias(yaffs_Object * obj)
++{
++ obj = yaffs_GetEquivalentObject(obj);
++ if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK) {
++ return yaffs_CloneString(obj->variant.symLinkVariant.alias);
++ } else {
++ return yaffs_CloneString(_Y(""));
++ }
++}
++
++#ifndef CONFIG_YAFFS_WINCE
++
++int yaffs_SetAttributes(yaffs_Object * obj, struct iattr *attr)
++{
++ unsigned int valid = attr->ia_valid;
++
++ if (valid & ATTR_MODE)
++ obj->yst_mode = attr->ia_mode;
++ if (valid & ATTR_UID)
++ obj->yst_uid = attr->ia_uid;
++ if (valid & ATTR_GID)
++ obj->yst_gid = attr->ia_gid;
++
++ if (valid & ATTR_ATIME)
++ obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime);
++ if (valid & ATTR_CTIME)
++ obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime);
++ if (valid & ATTR_MTIME)
++ obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime);
++
++ if (valid & ATTR_SIZE)
++ yaffs_ResizeFile(obj, attr->ia_size);
++
++ yaffs_UpdateObjectHeader(obj, NULL, 1, 0, 0);
++
++ return YAFFS_OK;
++
++}
++int yaffs_GetAttributes(yaffs_Object * obj, struct iattr *attr)
++{
++ unsigned int valid = 0;
++
++ attr->ia_mode = obj->yst_mode;
++ valid |= ATTR_MODE;
++ attr->ia_uid = obj->yst_uid;
++ valid |= ATTR_UID;
++ attr->ia_gid = obj->yst_gid;
++ valid |= ATTR_GID;
++
++ Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime;
++ valid |= ATTR_ATIME;
++ Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime;
++ valid |= ATTR_CTIME;
++ Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime;
++ valid |= ATTR_MTIME;
++
++ attr->ia_size = yaffs_GetFileSize(obj);
++ valid |= ATTR_SIZE;
++
++ attr->ia_valid = valid;
++
++ return YAFFS_OK;
++
++}
++
++#endif
++
++#if 0
++int yaffs_DumpObject(yaffs_Object * obj)
++{
++ YCHAR name[257];
++
++ yaffs_GetObjectName(obj, name, 256);
++
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("Object %d, inode %d \"%s\"\n dirty %d valid %d serial %d sum %d"
++ " chunk %d type %d size %d\n"
++ TENDSTR), obj->objectId, yaffs_GetObjectInode(obj), name,
++ obj->dirty, obj->valid, obj->serial, obj->sum, obj->hdrChunk,
++ yaffs_GetObjectType(obj), yaffs_GetObjectFileLength(obj)));
++
++ return YAFFS_OK;
++}
++#endif
++
++/*---------------------------- Initialisation code -------------------------------------- */
++
++static int yaffs_CheckDevFunctions(const yaffs_Device * dev)
++{
++
++ /* Common functions, gotta have */
++ if (!dev->eraseBlockInNAND || !dev->initialiseNAND)
++ return 0;
++
++#ifdef CONFIG_YAFFS_YAFFS2
++
++ /* Can use the "with tags" style interface for yaffs1 or yaffs2 */
++ if (dev->writeChunkWithTagsToNAND &&
++ dev->readChunkWithTagsFromNAND &&
++ !dev->writeChunkToNAND &&
++ !dev->readChunkFromNAND &&
++ dev->markNANDBlockBad && dev->queryNANDBlock)
++ return 1;
++#endif
++
++ /* Can use the "spare" style interface for yaffs1 */
++ if (!dev->isYaffs2 &&
++ !dev->writeChunkWithTagsToNAND &&
++ !dev->readChunkWithTagsFromNAND &&
++ dev->writeChunkToNAND &&
++ dev->readChunkFromNAND &&
++ !dev->markNANDBlockBad && !dev->queryNANDBlock)
++ return 1;
++
++ return 0; /* bad */
++}
++
++
++static int yaffs_CreateInitialDirectories(yaffs_Device *dev)
++{
++ /* Initialise the unlinked, deleted, root and lost and found directories */
++
++ dev->lostNFoundDir = dev->rootDir = NULL;
++ dev->unlinkedDir = dev->deletedDir = NULL;
++
++ dev->unlinkedDir =
++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR);
++
++ dev->deletedDir =
++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_DELETED, S_IFDIR);
++
++ dev->rootDir =
++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_ROOT,
++ YAFFS_ROOT_MODE | S_IFDIR);
++ dev->lostNFoundDir =
++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_LOSTNFOUND,
++ YAFFS_LOSTNFOUND_MODE | S_IFDIR);
++
++ if(dev->lostNFoundDir && dev->rootDir && dev->unlinkedDir && dev->deletedDir){
++ yaffs_AddObjectToDirectory(dev->rootDir, dev->lostNFoundDir);
++ return YAFFS_OK;
++ }
++
++ return YAFFS_FAIL;
++}
++
++int yaffs_GutsInitialise(yaffs_Device * dev)
++{
++ int init_failed = 0;
++ unsigned x;
++ int bits;
++
++ T(YAFFS_TRACE_TRACING, (TSTR("yaffs: yaffs_GutsInitialise()" TENDSTR)));
++
++ /* Check stuff that must be set */
++
++ if (!dev) {
++ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Need a device" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ dev->internalStartBlock = dev->startBlock;
++ dev->internalEndBlock = dev->endBlock;
++ dev->blockOffset = 0;
++ dev->chunkOffset = 0;
++ dev->nFreeChunks = 0;
++
++ dev->gcBlock = -1;
++
++ if (dev->startBlock == 0) {
++ dev->internalStartBlock = dev->startBlock + 1;
++ dev->internalEndBlock = dev->endBlock + 1;
++ dev->blockOffset = 1;
++ dev->chunkOffset = dev->nChunksPerBlock;
++ }
++
++ /* Check geometry parameters. */
++
++ if ((!dev->inbandTags && dev->isYaffs2 && dev->totalBytesPerChunk < 1024) ||
++ (!dev->isYaffs2 && dev->totalBytesPerChunk < 512) ||
++ (dev->inbandTags && !dev->isYaffs2 ) ||
++ dev->nChunksPerBlock < 2 ||
++ dev->nReservedBlocks < 2 ||
++ dev->internalStartBlock <= 0 ||
++ dev->internalEndBlock <= 0 ||
++ dev->internalEndBlock <= (dev->internalStartBlock + dev->nReservedBlocks + 2) // otherwise it is too small
++ ) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("yaffs: NAND geometry problems: chunk size %d, type is yaffs%s, inbandTags %d "
++ TENDSTR), dev->totalBytesPerChunk, dev->isYaffs2 ? "2" : "", dev->inbandTags));
++ return YAFFS_FAIL;
++ }
++
++ if (yaffs_InitialiseNAND(dev) != YAFFS_OK) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs: InitialiseNAND failed" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ /* Sort out space for inband tags, if required */
++ if(dev->inbandTags)
++ dev->nDataBytesPerChunk = dev->totalBytesPerChunk - sizeof(yaffs_PackedTags2TagsPart);
++ else
++ dev->nDataBytesPerChunk = dev->totalBytesPerChunk;
++
++ /* Got the right mix of functions? */
++ if (!yaffs_CheckDevFunctions(dev)) {
++ /* Function missing */
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR
++ ("yaffs: device function(s) missing or wrong\n" TENDSTR)));
++
++ return YAFFS_FAIL;
++ }
++
++ /* This is really a compilation check. */
++ if (!yaffs_CheckStructures()) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs_CheckStructures failed\n" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ if (dev->isMounted) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs: device already mounted\n" TENDSTR)));
++ return YAFFS_FAIL;
++ }
++
++ /* Finished with most checks. One or two more checks happen later on too. */
++
++ dev->isMounted = 1;
++
++ /* OK now calculate a few things for the device */
++
++ /*
++ * Calculate all the chunk size manipulation numbers:
++ */
++ x = dev->nDataBytesPerChunk;
++ /* We always use dev->chunkShift and dev->chunkDiv */
++ dev->chunkShift = Shifts(x);
++ x >>= dev->chunkShift;
++ dev->chunkDiv = x;
++ /* We only use chunk mask if chunkDiv is 1 */
++ dev->chunkMask = (1<<dev->chunkShift) - 1;
++
++ /*
++ * Calculate chunkGroupBits.
++ * We need to find the next power of 2 > than internalEndBlock
++ */
++
++ x = dev->nChunksPerBlock * (dev->internalEndBlock + 1);
++
++ bits = ShiftsGE(x);
++
++ /* Set up tnode width if wide tnodes are enabled. */
++ if(!dev->wideTnodesDisabled){
++ /* bits must be even so that we end up with 32-bit words */
++ if(bits & 1)
++ bits++;
++ if(bits < 16)
++ dev->tnodeWidth = 16;
++ else
++ dev->tnodeWidth = bits;
++ }
++ else
++ dev->tnodeWidth = 16;
++
++ dev->tnodeMask = (1<<dev->tnodeWidth)-1;
++
++ /* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled),
++ * so if the bitwidth of the
++ * chunk range we're using is greater than 16 we need
++ * to figure out chunk shift and chunkGroupSize
++ */
++
++ if (bits <= dev->tnodeWidth)
++ dev->chunkGroupBits = 0;
++ else
++ dev->chunkGroupBits = bits - dev->tnodeWidth;
++
++
++ dev->chunkGroupSize = 1 << dev->chunkGroupBits;
++
++ if (dev->nChunksPerBlock < dev->chunkGroupSize) {
++ /* We have a problem because the soft delete won't work if
++ * the chunk group size > chunks per block.
++ * This can be remedied by using larger "virtual blocks".
++ */
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs: chunk group too large\n" TENDSTR)));
++
++ return YAFFS_FAIL;
++ }
++
++ /* OK, we've finished verifying the device, lets continue with initialisation */
++
++ /* More device initialisation */
++ dev->garbageCollections = 0;
++ dev->passiveGarbageCollections = 0;
++ dev->currentDirtyChecker = 0;
++ dev->bufferedBlock = -1;
++ dev->doingBufferedBlockRewrite = 0;
++ dev->nDeletedFiles = 0;
++ dev->nBackgroundDeletions = 0;
++ dev->nUnlinkedFiles = 0;
++ dev->eccFixed = 0;
++ dev->eccUnfixed = 0;
++ dev->tagsEccFixed = 0;
++ dev->tagsEccUnfixed = 0;
++ dev->nErasureFailures = 0;
++ dev->nErasedBlocks = 0;
++ dev->isDoingGC = 0;
++ dev->hasPendingPrioritisedGCs = 1; /* Assume the worst for now, will get fixed on first GC */
++
++ /* Initialise temporary buffers and caches. */
++ if(!yaffs_InitialiseTempBuffers(dev))
++ init_failed = 1;
++
++ dev->srCache = NULL;
++ dev->gcCleanupList = NULL;
++
++
++ if (!init_failed &&
++ dev->nShortOpCaches > 0) {
++ int i;
++ void *buf;
++ int srCacheBytes = dev->nShortOpCaches * sizeof(yaffs_ChunkCache);
++
++ if (dev->nShortOpCaches > YAFFS_MAX_SHORT_OP_CACHES) {
++ dev->nShortOpCaches = YAFFS_MAX_SHORT_OP_CACHES;
++ }
++
++ dev->srCache = YMALLOC(srCacheBytes);
++
++ buf = (__u8 *) dev->srCache;
++
++ if(dev->srCache)
++ memset(dev->srCache,0,srCacheBytes);
++
++ for (i = 0; i < dev->nShortOpCaches && buf; i++) {
++ dev->srCache[i].object = NULL;
++ dev->srCache[i].lastUse = 0;
++ dev->srCache[i].dirty = 0;
++ dev->srCache[i].data = buf = YMALLOC_DMA(dev->totalBytesPerChunk);
++ }
++ if(!buf)
++ init_failed = 1;
++
++ dev->srLastUse = 0;
++ }
++
++ dev->cacheHits = 0;
++
++ if(!init_failed){
++ dev->gcCleanupList = YMALLOC(dev->nChunksPerBlock * sizeof(__u32));
++ if(!dev->gcCleanupList)
++ init_failed = 1;
++ }
++
++ if (dev->isYaffs2) {
++ dev->useHeaderFileSize = 1;
++ }
++ if(!init_failed && !yaffs_InitialiseBlocks(dev))
++ init_failed = 1;
++
++ yaffs_InitialiseTnodes(dev);
++ yaffs_InitialiseObjects(dev);
++
++ if(!init_failed && !yaffs_CreateInitialDirectories(dev))
++ init_failed = 1;
++
++
++ if(!init_failed){
++ /* Now scan the flash. */
++ if (dev->isYaffs2) {
++ if(yaffs_CheckpointRestore(dev)) {
++ yaffs_CheckObjectDetailsLoaded(dev->rootDir);
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("yaffs: restored from checkpoint" TENDSTR)));
++ } else {
++
++ /* Clean up the mess caused by an aborted checkpoint load
++ * and scan backwards.
++ */
++ yaffs_DeinitialiseBlocks(dev);
++ yaffs_DeinitialiseTnodes(dev);
++ yaffs_DeinitialiseObjects(dev);
++
++
++ dev->nErasedBlocks = 0;
++ dev->nFreeChunks = 0;
++ dev->allocationBlock = -1;
++ dev->allocationPage = -1;
++ dev->nDeletedFiles = 0;
++ dev->nUnlinkedFiles = 0;
++ dev->nBackgroundDeletions = 0;
++ dev->oldestDirtySequence = 0;
++
++ if(!init_failed && !yaffs_InitialiseBlocks(dev))
++ init_failed = 1;
++
++ yaffs_InitialiseTnodes(dev);
++ yaffs_InitialiseObjects(dev);
++
++ if(!init_failed && !yaffs_CreateInitialDirectories(dev))
++ init_failed = 1;
++
++ if(!init_failed && !yaffs_ScanBackwards(dev))
++ init_failed = 1;
++ }
++ }else
++ if(!yaffs_Scan(dev))
++ init_failed = 1;
++
++ yaffs_StripDeletedObjects(dev);
++ }
++
++ if(init_failed){
++ /* Clean up the mess */
++ T(YAFFS_TRACE_TRACING,
++ (TSTR("yaffs: yaffs_GutsInitialise() aborted.\n" TENDSTR)));
++
++ yaffs_Deinitialise(dev);
++ return YAFFS_FAIL;
++ }
++
++ /* Zero out stats */
++ dev->nPageReads = 0;
++ dev->nPageWrites = 0;
++ dev->nBlockErasures = 0;
++ dev->nGCCopies = 0;
++ dev->nRetriedWrites = 0;
++
++ dev->nRetiredBlocks = 0;
++
++ yaffs_VerifyFreeChunks(dev);
++ yaffs_VerifyBlocks(dev);
++
++
++ T(YAFFS_TRACE_TRACING,
++ (TSTR("yaffs: yaffs_GutsInitialise() done.\n" TENDSTR)));
++ return YAFFS_OK;
++
++}
++
++void yaffs_Deinitialise(yaffs_Device * dev)
++{
++ if (dev->isMounted) {
++ int i;
++
++ yaffs_DeinitialiseBlocks(dev);
++ yaffs_DeinitialiseTnodes(dev);
++ yaffs_DeinitialiseObjects(dev);
++ if (dev->nShortOpCaches > 0 &&
++ dev->srCache) {
++
++ for (i = 0; i < dev->nShortOpCaches; i++) {
++ if(dev->srCache[i].data)
++ YFREE(dev->srCache[i].data);
++ dev->srCache[i].data = NULL;
++ }
++
++ YFREE(dev->srCache);
++ dev->srCache = NULL;
++ }
++
++ YFREE(dev->gcCleanupList);
++
++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
++ YFREE(dev->tempBuffer[i].buffer);
++ }
++
++
++ dev->isMounted = 0;
++
++ if(dev->deinitialiseNAND)
++ dev->deinitialiseNAND(dev);
++ }
++
++}
++
++static int yaffs_CountFreeChunks(yaffs_Device * dev)
++{
++ int nFree;
++ int b;
++
++ yaffs_BlockInfo *blk;
++
++ for (nFree = 0, b = dev->internalStartBlock; b <= dev->internalEndBlock;
++ b++) {
++ blk = yaffs_GetBlockInfo(dev, b);
++
++ switch (blk->blockState) {
++ case YAFFS_BLOCK_STATE_EMPTY:
++ case YAFFS_BLOCK_STATE_ALLOCATING:
++ case YAFFS_BLOCK_STATE_COLLECTING:
++ case YAFFS_BLOCK_STATE_FULL:
++ nFree +=
++ (dev->nChunksPerBlock - blk->pagesInUse +
++ blk->softDeletions);
++ break;
++ default:
++ break;
++ }
++
++ }
++
++ return nFree;
++}
++
++int yaffs_GetNumberOfFreeChunks(yaffs_Device * dev)
++{
++ /* This is what we report to the outside world */
++
++ int nFree;
++ int nDirtyCacheChunks;
++ int blocksForCheckpoint;
++
++#if 1
++ nFree = dev->nFreeChunks;
++#else
++ nFree = yaffs_CountFreeChunks(dev);
++#endif
++
++ nFree += dev->nDeletedFiles;
++
++ /* Now count the number of dirty chunks in the cache and subtract those */
++
++ {
++ int i;
++ for (nDirtyCacheChunks = 0, i = 0; i < dev->nShortOpCaches; i++) {
++ if (dev->srCache[i].dirty)
++ nDirtyCacheChunks++;
++ }
++ }
++
++ nFree -= nDirtyCacheChunks;
++
++ nFree -= ((dev->nReservedBlocks + 1) * dev->nChunksPerBlock);
++
++ /* Now we figure out how much to reserve for the checkpoint and report that... */
++ blocksForCheckpoint = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint;
++ if(blocksForCheckpoint < 0)
++ blocksForCheckpoint = 0;
++
++ nFree -= (blocksForCheckpoint * dev->nChunksPerBlock);
++
++ if (nFree < 0)
++ nFree = 0;
++
++ return nFree;
++
++}
++
++static int yaffs_freeVerificationFailures;
++
++static void yaffs_VerifyFreeChunks(yaffs_Device * dev)
++{
++ int counted;
++ int difference;
++
++ if(yaffs_SkipVerification(dev))
++ return;
++
++ counted = yaffs_CountFreeChunks(dev);
++
++ difference = dev->nFreeChunks - counted;
++
++ if (difference) {
++ T(YAFFS_TRACE_ALWAYS,
++ (TSTR("Freechunks verification failure %d %d %d" TENDSTR),
++ dev->nFreeChunks, counted, difference));
++ yaffs_freeVerificationFailures++;
++ }
++}
++
++/*---------------------------------------- YAFFS test code ----------------------*/
++
++#define yaffs_CheckStruct(structure,syze, name) \
++ do { \
++ if(sizeof(structure) != syze) \
++ { \
++ T(YAFFS_TRACE_ALWAYS,(TSTR("%s should be %d but is %d\n" TENDSTR),\
++ name,syze,sizeof(structure))); \
++ return YAFFS_FAIL; \
++ } \
++ } while(0)
++
++static int yaffs_CheckStructures(void)
++{
++/* yaffs_CheckStruct(yaffs_Tags,8,"yaffs_Tags"); */
++/* yaffs_CheckStruct(yaffs_TagsUnion,8,"yaffs_TagsUnion"); */
++/* yaffs_CheckStruct(yaffs_Spare,16,"yaffs_Spare"); */
++#ifndef CONFIG_YAFFS_TNODE_LIST_DEBUG
++ yaffs_CheckStruct(yaffs_Tnode, 2 * YAFFS_NTNODES_LEVEL0, "yaffs_Tnode");
++#endif
++#ifndef CONFIG_YAFFS_WINCE
++ yaffs_CheckStruct(yaffs_ObjectHeader, 512, "yaffs_ObjectHeader");
++#endif
++ return YAFFS_OK;
++}
+diff --git a/fs/yaffs2/yaffs_guts.h b/fs/yaffs2/yaffs_guts.h
+new file mode 100644
+index 0000000..849d951
+--- /dev/null
++++ b/fs/yaffs2/yaffs_guts.h
+@@ -0,0 +1,906 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_GUTS_H__
++#define __YAFFS_GUTS_H__
++
++#include "devextras.h"
++#include "yportenv.h"
++
++#define YAFFS_OK 1
++#define YAFFS_FAIL 0
++
++/* Give us a Y=0x59,
++ * Give us an A=0x41,
++ * Give us an FF=0xFF
++ * Give us an S=0x53
++ * And what have we got...
++ */
++#define YAFFS_MAGIC 0x5941FF53
++
++#define YAFFS_NTNODES_LEVEL0 16
++#define YAFFS_TNODES_LEVEL0_BITS 4
++#define YAFFS_TNODES_LEVEL0_MASK 0xf
++
++#define YAFFS_NTNODES_INTERNAL (YAFFS_NTNODES_LEVEL0 / 2)
++#define YAFFS_TNODES_INTERNAL_BITS (YAFFS_TNODES_LEVEL0_BITS - 1)
++#define YAFFS_TNODES_INTERNAL_MASK 0x7
++#define YAFFS_TNODES_MAX_LEVEL 6
++
++#ifndef CONFIG_YAFFS_NO_YAFFS1
++#define YAFFS_BYTES_PER_SPARE 16
++#define YAFFS_BYTES_PER_CHUNK 512
++#define YAFFS_CHUNK_SIZE_SHIFT 9
++#define YAFFS_CHUNKS_PER_BLOCK 32
++#define YAFFS_BYTES_PER_BLOCK (YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK)
++#endif
++
++#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 1024
++#define YAFFS_MIN_YAFFS2_SPARE_SIZE 32
++
++#define YAFFS_MAX_CHUNK_ID 0x000FFFFF
++
++#define YAFFS_UNUSED_OBJECT_ID 0x0003FFFF
++
++#define YAFFS_ALLOCATION_NOBJECTS 100
++#define YAFFS_ALLOCATION_NTNODES 100
++#define YAFFS_ALLOCATION_NLINKS 100
++
++#define YAFFS_NOBJECT_BUCKETS 256
++
++
++#define YAFFS_OBJECT_SPACE 0x40000
++
++#define YAFFS_CHECKPOINT_VERSION 3
++
++#ifdef CONFIG_YAFFS_UNICODE
++#define YAFFS_MAX_NAME_LENGTH 127
++#define YAFFS_MAX_ALIAS_LENGTH 79
++#else
++#define YAFFS_MAX_NAME_LENGTH 255
++#define YAFFS_MAX_ALIAS_LENGTH 159
++#endif
++
++#define YAFFS_SHORT_NAME_LENGTH 15
++
++/* Some special object ids for pseudo objects */
++#define YAFFS_OBJECTID_ROOT 1
++#define YAFFS_OBJECTID_LOSTNFOUND 2
++#define YAFFS_OBJECTID_UNLINKED 3
++#define YAFFS_OBJECTID_DELETED 4
++
++/* Sseudo object ids for checkpointing */
++#define YAFFS_OBJECTID_SB_HEADER 0x10
++#define YAFFS_OBJECTID_CHECKPOINT_DATA 0x20
++#define YAFFS_SEQUENCE_CHECKPOINT_DATA 0x21
++
++/* */
++
++#define YAFFS_MAX_SHORT_OP_CACHES 20
++
++#define YAFFS_N_TEMP_BUFFERS 6
++
++/* We limit the number attempts at sucessfully saving a chunk of data.
++ * Small-page devices have 32 pages per block; large-page devices have 64.
++ * Default to something in the order of 5 to 10 blocks worth of chunks.
++ */
++#define YAFFS_WR_ATTEMPTS (5*64)
++
++/* Sequence numbers are used in YAFFS2 to determine block allocation order.
++ * The range is limited slightly to help distinguish bad numbers from good.
++ * This also allows us to perhaps in the future use special numbers for
++ * special purposes.
++ * EFFFFF00 allows the allocation of 8 blocks per second (~1Mbytes) for 15 years,
++ * and is a larger number than the lifetime of a 2GB device.
++ */
++#define YAFFS_LOWEST_SEQUENCE_NUMBER 0x00001000
++#define YAFFS_HIGHEST_SEQUENCE_NUMBER 0xEFFFFF00
++
++/* ChunkCache is used for short read/write operations.*/
++typedef struct {
++ struct yaffs_ObjectStruct *object;
++ int chunkId;
++ int lastUse;
++ int dirty;
++ int nBytes; /* Only valid if the cache is dirty */
++ int locked; /* Can't push out or flush while locked. */
++#ifdef CONFIG_YAFFS_YAFFS2
++ __u8 *data;
++#else
++ __u8 data[YAFFS_BYTES_PER_CHUNK];
++#endif
++} yaffs_ChunkCache;
++
++
++
++/* Tags structures in RAM
++ * NB This uses bitfield. Bitfields should not straddle a u32 boundary otherwise
++ * the structure size will get blown out.
++ */
++
++#ifndef CONFIG_YAFFS_NO_YAFFS1
++typedef struct {
++ unsigned chunkId:20;
++ unsigned serialNumber:2;
++ unsigned byteCountLSB:10;
++ unsigned objectId:18;
++ unsigned ecc:12;
++ unsigned byteCountMSB:2;
++
++} yaffs_Tags;
++
++typedef union {
++ yaffs_Tags asTags;
++ __u8 asBytes[8];
++} yaffs_TagsUnion;
++
++#endif
++
++/* Stuff used for extended tags in YAFFS2 */
++
++typedef enum {
++ YAFFS_ECC_RESULT_UNKNOWN,
++ YAFFS_ECC_RESULT_NO_ERROR,
++ YAFFS_ECC_RESULT_FIXED,
++ YAFFS_ECC_RESULT_UNFIXED
++} yaffs_ECCResult;
++
++typedef enum {
++ YAFFS_OBJECT_TYPE_UNKNOWN,
++ YAFFS_OBJECT_TYPE_FILE,
++ YAFFS_OBJECT_TYPE_SYMLINK,
++ YAFFS_OBJECT_TYPE_DIRECTORY,
++ YAFFS_OBJECT_TYPE_HARDLINK,
++ YAFFS_OBJECT_TYPE_SPECIAL
++} yaffs_ObjectType;
++
++#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL
++
++typedef struct {
++
++ unsigned validMarker0;
++ unsigned chunkUsed; /* Status of the chunk: used or unused */
++ unsigned objectId; /* If 0 then this is not part of an object (unused) */
++ unsigned chunkId; /* If 0 then this is a header, else a data chunk */
++ unsigned byteCount; /* Only valid for data chunks */
++
++ /* The following stuff only has meaning when we read */
++ yaffs_ECCResult eccResult;
++ unsigned blockBad;
++
++ /* YAFFS 1 stuff */
++ unsigned chunkDeleted; /* The chunk is marked deleted */
++ unsigned serialNumber; /* Yaffs1 2-bit serial number */
++
++ /* YAFFS2 stuff */
++ unsigned sequenceNumber; /* The sequence number of this block */
++
++ /* Extra info if this is an object header (YAFFS2 only) */
++
++ unsigned extraHeaderInfoAvailable; /* There is extra info available if this is not zero */
++ unsigned extraParentObjectId; /* The parent object */
++ unsigned extraIsShrinkHeader; /* Is it a shrink header? */
++ unsigned extraShadows; /* Does this shadow another object? */
++
++ yaffs_ObjectType extraObjectType; /* What object type? */
++
++ unsigned extraFileLength; /* Length if it is a file */
++ unsigned extraEquivalentObjectId; /* Equivalent object Id if it is a hard link */
++
++ unsigned validMarker1;
++
++} yaffs_ExtendedTags;
++
++/* Spare structure for YAFFS1 */
++typedef struct {
++ __u8 tagByte0;
++ __u8 tagByte1;
++ __u8 tagByte2;
++ __u8 tagByte3;
++ __u8 pageStatus; /* set to 0 to delete the chunk */
++ __u8 blockStatus;
++ __u8 tagByte4;
++ __u8 tagByte5;
++ __u8 ecc1[3];
++ __u8 tagByte6;
++ __u8 tagByte7;
++ __u8 ecc2[3];
++} yaffs_Spare;
++
++/*Special structure for passing through to mtd */
++struct yaffs_NANDSpare {
++ yaffs_Spare spare;
++ int eccres1;
++ int eccres2;
++};
++
++/* Block data in RAM */
++
++typedef enum {
++ YAFFS_BLOCK_STATE_UNKNOWN = 0,
++
++ YAFFS_BLOCK_STATE_SCANNING,
++ YAFFS_BLOCK_STATE_NEEDS_SCANNING,
++ /* The block might have something on it (ie it is allocating or full, perhaps empty)
++ * but it needs to be scanned to determine its true state.
++ * This state is only valid during yaffs_Scan.
++ * NB We tolerate empty because the pre-scanner might be incapable of deciding
++ * However, if this state is returned on a YAFFS2 device, then we expect a sequence number
++ */
++
++ YAFFS_BLOCK_STATE_EMPTY,
++ /* This block is empty */
++
++ YAFFS_BLOCK_STATE_ALLOCATING,
++ /* This block is partially allocated.
++ * At least one page holds valid data.
++ * This is the one currently being used for page
++ * allocation. Should never be more than one of these
++ */
++
++ YAFFS_BLOCK_STATE_FULL,
++ /* All the pages in this block have been allocated.
++ */
++
++ YAFFS_BLOCK_STATE_DIRTY,
++ /* All pages have been allocated and deleted.
++ * Erase me, reuse me.
++ */
++
++ YAFFS_BLOCK_STATE_CHECKPOINT,
++ /* This block is assigned to holding checkpoint data.
++ */
++
++ YAFFS_BLOCK_STATE_COLLECTING,
++ /* This block is being garbage collected */
++
++ YAFFS_BLOCK_STATE_DEAD
++ /* This block has failed and is not in use */
++} yaffs_BlockState;
++
++#define YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1)
++
++
++typedef struct {
++
++ int softDeletions:10; /* number of soft deleted pages */
++ int pagesInUse:10; /* number of pages in use */
++ unsigned blockState:4; /* One of the above block states. NB use unsigned because enum is sometimes an int */
++ __u32 needsRetiring:1; /* Data has failed on this block, need to get valid data off */
++ /* and retire the block. */
++ __u32 skipErasedCheck: 1; /* If this is set we can skip the erased check on this block */
++ __u32 gcPrioritise: 1; /* An ECC check or blank check has failed on this block.
++ It should be prioritised for GC */
++ __u32 chunkErrorStrikes:3; /* How many times we've had ecc etc failures on this block and tried to reuse it */
++
++#ifdef CONFIG_YAFFS_YAFFS2
++ __u32 hasShrinkHeader:1; /* This block has at least one shrink object header */
++ __u32 sequenceNumber; /* block sequence number for yaffs2 */
++#endif
++
++} yaffs_BlockInfo;
++
++/* -------------------------- Object structure -------------------------------*/
++/* This is the object structure as stored on NAND */
++
++typedef struct {
++ yaffs_ObjectType type;
++
++ /* Apply to everything */
++ int parentObjectId;
++ __u16 sum__NoLongerUsed; /* checksum of name. No longer used */
++ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
++
++ /* The following apply to directories, files, symlinks - not hard links */
++ __u32 yst_mode; /* protection */
++
++#ifdef CONFIG_YAFFS_WINCE
++ __u32 notForWinCE[5];
++#else
++ __u32 yst_uid;
++ __u32 yst_gid;
++ __u32 yst_atime;
++ __u32 yst_mtime;
++ __u32 yst_ctime;
++#endif
++
++ /* File size applies to files only */
++ int fileSize;
++
++ /* Equivalent object id applies to hard links only. */
++ int equivalentObjectId;
++
++ /* Alias is for symlinks only. */
++ YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1];
++
++ __u32 yst_rdev; /* device stuff for block and char devices (major/min) */
++
++#ifdef CONFIG_YAFFS_WINCE
++ __u32 win_ctime[2];
++ __u32 win_atime[2];
++ __u32 win_mtime[2];
++#else
++ __u32 roomToGrow[6];
++
++#endif
++ __u32 inbandShadowsObject;
++ __u32 inbandIsShrink;
++
++ __u32 reservedSpace[2];
++ int shadowsObject; /* This object header shadows the specified object if > 0 */
++
++ /* isShrink applies to object headers written when we shrink the file (ie resize) */
++ __u32 isShrink;
++
++} yaffs_ObjectHeader;
++
++/*--------------------------- Tnode -------------------------- */
++
++union yaffs_Tnode_union {
++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
++ union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL + 1];
++#else
++ union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL];
++#endif
++/* __u16 level0[YAFFS_NTNODES_LEVEL0]; */
++
++};
++
++typedef union yaffs_Tnode_union yaffs_Tnode;
++
++struct yaffs_TnodeList_struct {
++ struct yaffs_TnodeList_struct *next;
++ yaffs_Tnode *tnodes;
++};
++
++typedef struct yaffs_TnodeList_struct yaffs_TnodeList;
++
++/*------------------------ Object -----------------------------*/
++/* An object can be one of:
++ * - a directory (no data, has children links
++ * - a regular file (data.... not prunes :->).
++ * - a symlink [symbolic link] (the alias).
++ * - a hard link
++ */
++
++typedef struct {
++ __u32 fileSize;
++ __u32 scannedFileSize;
++ __u32 shrinkSize;
++ int topLevel;
++ yaffs_Tnode *top;
++} yaffs_FileStructure;
++
++typedef struct {
++ struct ylist_head children; /* list of child links */
++} yaffs_DirectoryStructure;
++
++typedef struct {
++ YCHAR *alias;
++} yaffs_SymLinkStructure;
++
++typedef struct {
++ struct yaffs_ObjectStruct *equivalentObject;
++ __u32 equivalentObjectId;
++} yaffs_HardLinkStructure;
++
++typedef union {
++ yaffs_FileStructure fileVariant;
++ yaffs_DirectoryStructure directoryVariant;
++ yaffs_SymLinkStructure symLinkVariant;
++ yaffs_HardLinkStructure hardLinkVariant;
++} yaffs_ObjectVariant;
++
++struct yaffs_ObjectStruct {
++ __u8 deleted:1; /* This should only apply to unlinked files. */
++ __u8 softDeleted:1; /* it has also been soft deleted */
++ __u8 unlinked:1; /* An unlinked file. The file should be in the unlinked directory.*/
++ __u8 fake:1; /* A fake object has no presence on NAND. */
++ __u8 renameAllowed:1; /* Some objects are not allowed to be renamed. */
++ __u8 unlinkAllowed:1;
++ __u8 dirty:1; /* the object needs to be written to flash */
++ __u8 valid:1; /* When the file system is being loaded up, this
++ * object might be created before the data
++ * is available (ie. file data records appear before the header).
++ */
++ __u8 lazyLoaded:1; /* This object has been lazy loaded and is missing some detail */
++
++ __u8 deferedFree:1; /* For Linux kernel. Object is removed from NAND, but is
++ * still in the inode cache. Free of object is defered.
++ * until the inode is released.
++ */
++
++ __u8 serial; /* serial number of chunk in NAND. Cached here */
++/* __u16 sum_prev; */
++ __u16 sum; /* sum of the name to speed searching */
++/* __u16 sum_trailer; */
++
++ struct yaffs_DeviceStruct *myDev; /* The device I'm on */
++
++ struct ylist_head hashLink; /* list of objects in this hash bucket */
++
++ struct ylist_head hardLinks; /* all the equivalent hard linked objects */
++
++ /* directory structure stuff */
++ /* also used for linking up the free list */
++ struct yaffs_ObjectStruct *parent;
++ struct ylist_head siblings;
++
++ /* Where's my object header in NAND? */
++ int hdrChunk;
++
++ int nDataChunks; /* Number of data chunks attached to the file. */
++
++ __u32 objectId; /* the object id value */
++
++ __u32 yst_mode;
++
++#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
++ YCHAR shortName[YAFFS_SHORT_NAME_LENGTH + 1];
++#endif
++
++#ifndef __KERNEL__
++ __u32 inUse;
++#endif
++
++#ifdef CONFIG_YAFFS_WINCE
++ __u32 win_ctime[2];
++ __u32 win_mtime[2];
++ __u32 win_atime[2];
++#else
++ __u32 yst_uid;
++ __u32 yst_gid;
++ __u32 yst_atime;
++ __u32 yst_mtime;
++ __u32 yst_ctime;
++#endif
++
++ __u32 yst_rdev;
++
++#ifdef __KERNEL__
++ struct inode *myInode;
++
++#endif
++
++ yaffs_ObjectType variantType;
++
++ yaffs_ObjectVariant variant;
++
++};
++
++typedef struct yaffs_ObjectStruct yaffs_Object;
++
++struct yaffs_ObjectList_struct {
++ yaffs_Object *objects;
++ struct yaffs_ObjectList_struct *next;
++};
++
++typedef struct yaffs_ObjectList_struct yaffs_ObjectList;
++
++typedef struct {
++ struct ylist_head list;
++ int count;
++} yaffs_ObjectBucket;
++
++
++/* yaffs_CheckpointObject holds the definition of an object as dumped
++ * by checkpointing.
++ */
++
++typedef struct {
++ int structType;
++ __u32 objectId;
++ __u32 parentId;
++ int hdrChunk;
++ yaffs_ObjectType variantType:3;
++ __u8 deleted:1;
++ __u8 softDeleted:1;
++ __u8 unlinked:1;
++ __u8 fake:1;
++ __u8 renameAllowed:1;
++ __u8 unlinkAllowed:1;
++ __u8 serial;
++
++ int nDataChunks;
++ __u32 fileSizeOrEquivalentObjectId;
++
++}yaffs_CheckpointObject;
++
++/*--------------------- Temporary buffers ----------------
++ *
++ * These are chunk-sized working buffers. Each device has a few
++ */
++
++typedef struct {
++ __u8 *buffer;
++ int line; /* track from whence this buffer was allocated */
++ int maxLine;
++} yaffs_TempBuffer;
++
++/*----------------- Device ---------------------------------*/
++
++struct yaffs_DeviceStruct {
++ struct ylist_head devList;
++ const char *name;
++
++ /* Entry parameters set up way early. Yaffs sets up the rest.*/
++ int nDataBytesPerChunk; /* Should be a power of 2 >= 512 */
++ int nChunksPerBlock; /* does not need to be a power of 2 */
++ int spareBytesPerChunk;/* spare area size */
++ int startBlock; /* Start block we're allowed to use */
++ int endBlock; /* End block we're allowed to use */
++ int nReservedBlocks; /* We want this tuneable so that we can reduce */
++ /* reserved blocks on NOR and RAM. */
++
++
++ /* Stuff used by the shared space checkpointing mechanism */
++ /* If this value is zero, then this mechanism is disabled */
++
++// int nCheckpointReservedBlocks; /* Blocks to reserve for checkpoint data */
++
++
++
++
++ int nShortOpCaches; /* If <= 0, then short op caching is disabled, else
++ * the number of short op caches (don't use too many)
++ */
++
++ int useHeaderFileSize; /* Flag to determine if we should use file sizes from the header */
++
++ int useNANDECC; /* Flag to decide whether or not to use NANDECC */
++
++ void *genericDevice; /* Pointer to device context
++ * On an mtd this holds the mtd pointer.
++ */
++ void *superBlock;
++
++ /* NAND access functions (Must be set before calling YAFFS)*/
++
++ int (*writeChunkToNAND) (struct yaffs_DeviceStruct * dev,
++ int chunkInNAND, const __u8 * data,
++ const yaffs_Spare * spare);
++ int (*readChunkFromNAND) (struct yaffs_DeviceStruct * dev,
++ int chunkInNAND, __u8 * data,
++ yaffs_Spare * spare);
++ int (*eraseBlockInNAND) (struct yaffs_DeviceStruct * dev,
++ int blockInNAND);
++ int (*initialiseNAND) (struct yaffs_DeviceStruct * dev);
++ int (*deinitialiseNAND) (struct yaffs_DeviceStruct * dev);
++
++#ifdef CONFIG_YAFFS_YAFFS2
++ int (*writeChunkWithTagsToNAND) (struct yaffs_DeviceStruct * dev,
++ int chunkInNAND, const __u8 * data,
++ const yaffs_ExtendedTags * tags);
++ int (*readChunkWithTagsFromNAND) (struct yaffs_DeviceStruct * dev,
++ int chunkInNAND, __u8 * data,
++ yaffs_ExtendedTags * tags);
++ int (*markNANDBlockBad) (struct yaffs_DeviceStruct * dev, int blockNo);
++ int (*queryNANDBlock) (struct yaffs_DeviceStruct * dev, int blockNo,
++ yaffs_BlockState * state, __u32 *sequenceNumber);
++#endif
++
++ int isYaffs2;
++
++ /* The removeObjectCallback function must be supplied by OS flavours that
++ * need it. The Linux kernel does not use this, but yaffs direct does use
++ * it to implement the faster readdir
++ */
++ void (*removeObjectCallback)(struct yaffs_ObjectStruct *obj);
++
++ /* Callback to mark the superblock dirsty */
++ void (*markSuperBlockDirty)(void * superblock);
++
++ int wideTnodesDisabled; /* Set to disable wide tnodes */
++
++ YCHAR *pathDividers; /* String of legal path dividers */
++
++
++ /* End of stuff that must be set before initialisation. */
++
++ /* Checkpoint control. Can be set before or after initialisation */
++ __u8 skipCheckpointRead;
++ __u8 skipCheckpointWrite;
++
++ /* Runtime parameters. Set up by YAFFS. */
++
++ __u16 chunkGroupBits; /* 0 for devices <= 32MB. else log2(nchunks) - 16 */
++ __u16 chunkGroupSize; /* == 2^^chunkGroupBits */
++
++ /* Stuff to support wide tnodes */
++ __u32 tnodeWidth;
++ __u32 tnodeMask;
++
++ /* Stuff for figuring out file offset to chunk conversions */
++ __u32 chunkShift; /* Shift value */
++ __u32 chunkDiv; /* Divisor after shifting: 1 for power-of-2 sizes */
++ __u32 chunkMask; /* Mask to use for power-of-2 case */
++
++ /* Stuff to handle inband tags */
++ int inbandTags;
++ __u32 totalBytesPerChunk;
++
++#ifdef __KERNEL__
++
++ struct semaphore sem; /* Semaphore for waiting on erasure.*/
++ struct semaphore grossLock; /* Gross locking semaphore */
++ __u8 *spareBuffer; /* For mtdif2 use. Don't know the size of the buffer
++ * at compile time so we have to allocate it.
++ */
++ void (*putSuperFunc) (struct super_block * sb);
++#endif
++
++ int isMounted;
++
++ int isCheckpointed;
++
++
++ /* Stuff to support block offsetting to support start block zero */
++ int internalStartBlock;
++ int internalEndBlock;
++ int blockOffset;
++ int chunkOffset;
++
++
++ /* Runtime checkpointing stuff */
++ int checkpointPageSequence; /* running sequence number of checkpoint pages */
++ int checkpointByteCount;
++ int checkpointByteOffset;
++ __u8 *checkpointBuffer;
++ int checkpointOpenForWrite;
++ int blocksInCheckpoint;
++ int checkpointCurrentChunk;
++ int checkpointCurrentBlock;
++ int checkpointNextBlock;
++ int *checkpointBlockList;
++ int checkpointMaxBlocks;
++ __u32 checkpointSum;
++ __u32 checkpointXor;
++
++ int nCheckpointBlocksRequired; /* Number of blocks needed to store current checkpoint set */
++
++ /* Block Info */
++ yaffs_BlockInfo *blockInfo;
++ __u8 *chunkBits; /* bitmap of chunks in use */
++ unsigned blockInfoAlt:1; /* was allocated using alternative strategy */
++ unsigned chunkBitsAlt:1; /* was allocated using alternative strategy */
++ int chunkBitmapStride; /* Number of bytes of chunkBits per block.
++ * Must be consistent with nChunksPerBlock.
++ */
++
++ int nErasedBlocks;
++ int allocationBlock; /* Current block being allocated off */
++ __u32 allocationPage;
++ int allocationBlockFinder; /* Used to search for next allocation block */
++
++ /* Runtime state */
++ int nTnodesCreated;
++ yaffs_Tnode *freeTnodes;
++ int nFreeTnodes;
++ yaffs_TnodeList *allocatedTnodeList;
++
++ int isDoingGC;
++ int gcBlock;
++ int gcChunk;
++
++ int nObjectsCreated;
++ yaffs_Object *freeObjects;
++ int nFreeObjects;
++
++ int nHardLinks;
++
++ yaffs_ObjectList *allocatedObjectList;
++
++ yaffs_ObjectBucket objectBucket[YAFFS_NOBJECT_BUCKETS];
++
++ int nFreeChunks;
++
++ int currentDirtyChecker; /* Used to find current dirtiest block */
++
++ __u32 *gcCleanupList; /* objects to delete at the end of a GC. */
++ int nonAggressiveSkip; /* GC state/mode */
++
++ /* Statistcs */
++ int nPageWrites;
++ int nPageReads;
++ int nBlockErasures;
++ int nErasureFailures;
++ int nGCCopies;
++ int garbageCollections;
++ int passiveGarbageCollections;
++ int nRetriedWrites;
++ int nRetiredBlocks;
++ int eccFixed;
++ int eccUnfixed;
++ int tagsEccFixed;
++ int tagsEccUnfixed;
++ int nDeletions;
++ int nUnmarkedDeletions;
++
++ int hasPendingPrioritisedGCs; /* We think this device might have pending prioritised gcs */
++
++ /* Special directories */
++ yaffs_Object *rootDir;
++ yaffs_Object *lostNFoundDir;
++
++ /* Buffer areas for storing data to recover from write failures TODO
++ * __u8 bufferedData[YAFFS_CHUNKS_PER_BLOCK][YAFFS_BYTES_PER_CHUNK];
++ * yaffs_Spare bufferedSpare[YAFFS_CHUNKS_PER_BLOCK];
++ */
++
++ int bufferedBlock; /* Which block is buffered here? */
++ int doingBufferedBlockRewrite;
++
++ yaffs_ChunkCache *srCache;
++ int srLastUse;
++
++ int cacheHits;
++
++ /* Stuff for background deletion and unlinked files.*/
++ yaffs_Object *unlinkedDir; /* Directory where unlinked and deleted files live. */
++ yaffs_Object *deletedDir; /* Directory where deleted objects are sent to disappear. */
++ yaffs_Object *unlinkedDeletion; /* Current file being background deleted.*/
++ int nDeletedFiles; /* Count of files awaiting deletion;*/
++ int nUnlinkedFiles; /* Count of unlinked files. */
++ int nBackgroundDeletions; /* Count of background deletions. */
++
++
++ /* Temporary buffer management */
++ yaffs_TempBuffer tempBuffer[YAFFS_N_TEMP_BUFFERS];
++ int maxTemp;
++ int tempInUse;
++ int unmanagedTempAllocations;
++ int unmanagedTempDeallocations;
++
++ /* yaffs2 runtime stuff */
++ unsigned sequenceNumber; /* Sequence number of currently allocating block */
++ unsigned oldestDirtySequence;
++
++};
++
++typedef struct yaffs_DeviceStruct yaffs_Device;
++
++/* The static layout of block usage etc is stored in the super block header */
++typedef struct {
++ int StructType;
++ int version;
++ int checkpointStartBlock;
++ int checkpointEndBlock;
++ int startBlock;
++ int endBlock;
++ int rfu[100];
++} yaffs_SuperBlockHeader;
++
++/* The CheckpointDevice structure holds the device information that changes at runtime and
++ * must be preserved over unmount/mount cycles.
++ */
++typedef struct {
++ int structType;
++ int nErasedBlocks;
++ int allocationBlock; /* Current block being allocated off */
++ __u32 allocationPage;
++ int nFreeChunks;
++
++ int nDeletedFiles; /* Count of files awaiting deletion;*/
++ int nUnlinkedFiles; /* Count of unlinked files. */
++ int nBackgroundDeletions; /* Count of background deletions. */
++
++ /* yaffs2 runtime stuff */
++ unsigned sequenceNumber; /* Sequence number of currently allocating block */
++ unsigned oldestDirtySequence;
++
++} yaffs_CheckpointDevice;
++
++
++typedef struct {
++ int structType;
++ __u32 magic;
++ __u32 version;
++ __u32 head;
++} yaffs_CheckpointValidity;
++
++
++/*----------------------- YAFFS Functions -----------------------*/
++
++int yaffs_GutsInitialise(yaffs_Device * dev);
++void yaffs_Deinitialise(yaffs_Device * dev);
++
++int yaffs_GetNumberOfFreeChunks(yaffs_Device * dev);
++
++int yaffs_RenameObject(yaffs_Object * oldDir, const YCHAR * oldName,
++ yaffs_Object * newDir, const YCHAR * newName);
++
++int yaffs_Unlink(yaffs_Object * dir, const YCHAR * name);
++int yaffs_DeleteFile(yaffs_Object * obj);
++
++int yaffs_GetObjectName(yaffs_Object * obj, YCHAR * name, int buffSize);
++int yaffs_GetObjectFileLength(yaffs_Object * obj);
++int yaffs_GetObjectInode(yaffs_Object * obj);
++unsigned yaffs_GetObjectType(yaffs_Object * obj);
++int yaffs_GetObjectLinkCount(yaffs_Object * obj);
++
++int yaffs_SetAttributes(yaffs_Object * obj, struct iattr *attr);
++int yaffs_GetAttributes(yaffs_Object * obj, struct iattr *attr);
++
++/* File operations */
++int yaffs_ReadDataFromFile(yaffs_Object * obj, __u8 * buffer, loff_t offset,
++ int nBytes);
++int yaffs_WriteDataToFile(yaffs_Object * obj, const __u8 * buffer, loff_t offset,
++ int nBytes, int writeThrough);
++int yaffs_ResizeFile(yaffs_Object * obj, loff_t newSize);
++
++yaffs_Object *yaffs_MknodFile(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid);
++int yaffs_FlushFile(yaffs_Object * obj, int updateTime);
++
++/* Flushing and checkpointing */
++void yaffs_FlushEntireDeviceCache(yaffs_Device *dev);
++
++int yaffs_CheckpointSave(yaffs_Device *dev);
++int yaffs_CheckpointRestore(yaffs_Device *dev);
++
++/* Directory operations */
++yaffs_Object *yaffs_MknodDirectory(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid);
++yaffs_Object *yaffs_FindObjectByName(yaffs_Object * theDir, const YCHAR * name);
++int yaffs_ApplyToDirectoryChildren(yaffs_Object * theDir,
++ int (*fn) (yaffs_Object *));
++
++yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device * dev, __u32 number);
++
++/* Link operations */
++yaffs_Object *yaffs_Link(yaffs_Object * parent, const YCHAR * name,
++ yaffs_Object * equivalentObject);
++
++yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object * obj);
++
++/* Symlink operations */
++yaffs_Object *yaffs_MknodSymLink(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid,
++ const YCHAR * alias);
++YCHAR *yaffs_GetSymlinkAlias(yaffs_Object * obj);
++
++/* Special inodes (fifos, sockets and devices) */
++yaffs_Object *yaffs_MknodSpecial(yaffs_Object * parent, const YCHAR * name,
++ __u32 mode, __u32 uid, __u32 gid, __u32 rdev);
++
++/* Special directories */
++yaffs_Object *yaffs_Root(yaffs_Device * dev);
++yaffs_Object *yaffs_LostNFound(yaffs_Device * dev);
++
++#ifdef CONFIG_YAFFS_WINCE
++/* CONFIG_YAFFS_WINCE special stuff */
++void yfsd_WinFileTimeNow(__u32 target[2]);
++#endif
++
++#ifdef __KERNEL__
++
++void yaffs_HandleDeferedFree(yaffs_Object * obj);
++#endif
++
++/* Debug dump */
++int yaffs_DumpObject(yaffs_Object * obj);
++
++void yaffs_GutsTest(yaffs_Device * dev);
++
++/* A few useful functions */
++void yaffs_InitialiseTags(yaffs_ExtendedTags * tags);
++void yaffs_DeleteChunk(yaffs_Device * dev, int chunkId, int markNAND, int lyn);
++int yaffs_CheckFF(__u8 * buffer, int nBytes);
++void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi);
++
++__u8 *yaffs_GetTempBuffer(yaffs_Device * dev, int lineNo);
++void yaffs_ReleaseTempBuffer(yaffs_Device * dev, __u8 * buffer, int lineNo);
++
++#endif
+diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c
+new file mode 100644
+index 0000000..56bb225
+--- /dev/null
++++ b/fs/yaffs2/yaffs_mtdif.c
+@@ -0,0 +1,241 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++const char *yaffs_mtdif_c_version =
++ "$Id: yaffs_mtdif.c,v 1.21 2007/12/13 15:35:18 wookey Exp $";
++
++#include "yportenv.h"
++
++
++#include "yaffs_mtdif.h"
++
++#include "linux/mtd/mtd.h"
++#include "linux/types.h"
++#include "linux/time.h"
++#include "linux/mtd/nand.h"
++
++#if (MTD_VERSION_CODE < MTD_VERSION(2,6,18))
++static struct nand_oobinfo yaffs_oobinfo = {
++ .useecc = 1,
++ .eccbytes = 6,
++ .eccpos = {8, 9, 10, 13, 14, 15}
++};
++
++static struct nand_oobinfo yaffs_noeccinfo = {
++ .useecc = 0,
++};
++#endif
++
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++static inline void translate_spare2oob(const yaffs_Spare *spare, __u8 *oob)
++{
++ oob[0] = spare->tagByte0;
++ oob[1] = spare->tagByte1;
++ oob[2] = spare->tagByte2;
++ oob[3] = spare->tagByte3;
++ oob[4] = spare->tagByte4;
++ oob[5] = spare->tagByte5 & 0x3f;
++ oob[5] |= spare->blockStatus == 'Y' ? 0: 0x80;
++ oob[5] |= spare->pageStatus == 0 ? 0: 0x40;
++ oob[6] = spare->tagByte6;
++ oob[7] = spare->tagByte7;
++}
++
++static inline void translate_oob2spare(yaffs_Spare *spare, __u8 *oob)
++{
++ struct yaffs_NANDSpare *nspare = (struct yaffs_NANDSpare *)spare;
++ spare->tagByte0 = oob[0];
++ spare->tagByte1 = oob[1];
++ spare->tagByte2 = oob[2];
++ spare->tagByte3 = oob[3];
++ spare->tagByte4 = oob[4];
++ spare->tagByte5 = oob[5] == 0xff ? 0xff : oob[5] & 0x3f;
++ spare->blockStatus = oob[5] & 0x80 ? 0xff : 'Y';
++ spare->pageStatus = oob[5] & 0x40 ? 0xff : 0;
++ spare->ecc1[0] = spare->ecc1[1] = spare->ecc1[2] = 0xff;
++ spare->tagByte6 = oob[6];
++ spare->tagByte7 = oob[7];
++ spare->ecc2[0] = spare->ecc2[1] = spare->ecc2[2] = 0xff;
++
++ nspare->eccres1 = nspare->eccres2 = 0; /* FIXME */
++}
++#endif
++
++int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data, const yaffs_Spare * spare)
++{
++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++ struct mtd_oob_ops ops;
++#endif
++ size_t dummy;
++ int retval = 0;
++
++ loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++ __u8 spareAsBytes[8]; /* OOB */
++
++ if (data && !spare)
++ retval = mtd->write(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data);
++ else if (spare) {
++ if (dev->useNANDECC) {
++ translate_spare2oob(spare, spareAsBytes);
++ ops.mode = MTD_OOB_AUTO;
++ ops.ooblen = 8; /* temp hack */
++ } else {
++ ops.mode = MTD_OOB_RAW;
++ ops.ooblen = YAFFS_BYTES_PER_SPARE;
++ }
++ ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen;
++ ops.datbuf = (u8 *)data;
++ ops.ooboffs = 0;
++ ops.oobbuf = spareAsBytes;
++ retval = mtd->write_oob(mtd, addr, &ops);
++ }
++#else
++ __u8 *spareAsBytes = (__u8 *) spare;
++
++ if (data && spare) {
++ if (dev->useNANDECC)
++ retval =
++ mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data, spareAsBytes,
++ &yaffs_oobinfo);
++ else
++ retval =
++ mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data, spareAsBytes,
++ &yaffs_noeccinfo);
++ } else {
++ if (data)
++ retval =
++ mtd->write(mtd, addr, dev->nDataBytesPerChunk, &dummy,
++ data);
++ if (spare)
++ retval =
++ mtd->write_oob(mtd, addr, YAFFS_BYTES_PER_SPARE,
++ &dummy, spareAsBytes);
++ }
++#endif
++
++ if (retval == 0)
++ return YAFFS_OK;
++ else
++ return YAFFS_FAIL;
++}
++
++int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
++ yaffs_Spare * spare)
++{
++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++ struct mtd_oob_ops ops;
++#endif
++ size_t dummy;
++ int retval = 0;
++
++ loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++ __u8 spareAsBytes[8]; /* OOB */
++
++ if (data && !spare)
++ retval = mtd->read(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data);
++ else if (spare) {
++ if (dev->useNANDECC) {
++ ops.mode = MTD_OOB_AUTO;
++ ops.ooblen = 8; /* temp hack */
++ } else {
++ ops.mode = MTD_OOB_RAW;
++ ops.ooblen = YAFFS_BYTES_PER_SPARE;
++ }
++ ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen;
++ ops.datbuf = data;
++ ops.ooboffs = 0;
++ ops.oobbuf = spareAsBytes;
++ retval = mtd->read_oob(mtd, addr, &ops);
++ if (dev->useNANDECC)
++ translate_oob2spare(spare, spareAsBytes);
++ }
++#else
++ __u8 *spareAsBytes = (__u8 *) spare;
++
++ if (data && spare) {
++ if (dev->useNANDECC) {
++ /* Careful, this call adds 2 ints */
++ /* to the end of the spare data. Calling function */
++ /* should allocate enough memory for spare, */
++ /* i.e. [YAFFS_BYTES_PER_SPARE+2*sizeof(int)]. */
++ retval =
++ mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data, spareAsBytes,
++ &yaffs_oobinfo);
++ } else {
++ retval =
++ mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data, spareAsBytes,
++ &yaffs_noeccinfo);
++ }
++ } else {
++ if (data)
++ retval =
++ mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy,
++ data);
++ if (spare)
++ retval =
++ mtd->read_oob(mtd, addr, YAFFS_BYTES_PER_SPARE,
++ &dummy, spareAsBytes);
++ }
++#endif
++
++ if (retval == 0)
++ return YAFFS_OK;
++ else
++ return YAFFS_FAIL;
++}
++
++int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber)
++{
++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
++ __u32 addr =
++ ((loff_t) blockNumber) * dev->nDataBytesPerChunk
++ * dev->nChunksPerBlock;
++ struct erase_info ei;
++ int retval = 0;
++
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = dev->nDataBytesPerChunk * dev->nChunksPerBlock;
++ ei.time = 1000;
++ ei.retries = 2;
++ ei.callback = NULL;
++ ei.priv = (u_long) dev;
++
++ /* Todo finish off the ei if required */
++
++ sema_init(&dev->sem, 0);
++
++ retval = mtd->erase(mtd, &ei);
++
++ if (retval == 0)
++ return YAFFS_OK;
++ else
++ return YAFFS_FAIL;
++}
++
++int nandmtd_InitialiseNAND(yaffs_Device * dev)
++{
++ return YAFFS_OK;
++}
++
+diff --git a/fs/yaffs2/yaffs_mtdif.h b/fs/yaffs2/yaffs_mtdif.h
+new file mode 100644
+index 0000000..511b017
+--- /dev/null
++++ b/fs/yaffs2/yaffs_mtdif.h
+@@ -0,0 +1,32 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_MTDIF_H__
++#define __YAFFS_MTDIF_H__
++
++#include "yaffs_guts.h"
++
++#if (MTD_VERSION_CODE < MTD_VERSION(2,6,18))
++extern struct nand_oobinfo yaffs_oobinfo;
++extern struct nand_oobinfo yaffs_noeccinfo;
++#endif
++
++int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data, const yaffs_Spare * spare);
++int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
++ yaffs_Spare * spare);
++int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber);
++int nandmtd_InitialiseNAND(yaffs_Device * dev);
++#endif
+diff --git a/fs/yaffs2/yaffs_mtdif1.c b/fs/yaffs2/yaffs_mtdif1.c
+new file mode 100644
+index 0000000..f00d6ef
+--- /dev/null
++++ b/fs/yaffs2/yaffs_mtdif1.c
+@@ -0,0 +1,369 @@
++/*
++ * YAFFS: Yet another FFS. A NAND-flash specific file system.
++ * yaffs_mtdif1.c NAND mtd interface functions for small-page NAND.
++ *
++ * Copyright (C) 2002 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/*
++ * This module provides the interface between yaffs_nand.c and the
++ * MTD API. This version is used when the MTD interface supports the
++ * 'mtd_oob_ops' style calls to read_oob and write_oob, circa 2.6.17,
++ * and we have small-page NAND device.
++ *
++ * These functions are invoked via function pointers in yaffs_nand.c.
++ * This replaces functionality provided by functions in yaffs_mtdif.c
++ * and the yaffs_TagsCompatability functions in yaffs_tagscompat.c that are
++ * called in yaffs_mtdif.c when the function pointers are NULL.
++ * We assume the MTD layer is performing ECC (useNANDECC is true).
++ */
++
++#include "yportenv.h"
++#include "yaffs_guts.h"
++#include "yaffs_packedtags1.h"
++#include "yaffs_tagscompat.h" // for yaffs_CalcTagsECC
++
++#include "linux/kernel.h"
++#include "linux/version.h"
++#include "linux/types.h"
++#include "linux/mtd/mtd.h"
++
++/* Don't compile this module if we don't have MTD's mtd_oob_ops interface */
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++
++const char *yaffs_mtdif1_c_version = "$Id: yaffs_mtdif1.c,v 1.8 2008/07/23 03:35:12 charles Exp $";
++
++#ifndef CONFIG_YAFFS_9BYTE_TAGS
++# define YTAG1_SIZE 8
++#else
++# define YTAG1_SIZE 9
++#endif
++
++#if 0
++/* Use the following nand_ecclayout with MTD when using
++ * CONFIG_YAFFS_9BYTE_TAGS and the older on-NAND tags layout.
++ * If you have existing Yaffs images and the byte order differs from this,
++ * adjust 'oobfree' to match your existing Yaffs data.
++ *
++ * This nand_ecclayout scatters/gathers to/from the old-yaffs layout with the
++ * pageStatus byte (at NAND spare offset 4) scattered/gathered from/to
++ * the 9th byte.
++ *
++ * Old-style on-NAND format: T0,T1,T2,T3,P,B,T4,T5,E0,E1,E2,T6,T7,E3,E4,E5
++ * We have/need PackedTags1 plus pageStatus: T0,T1,T2,T3,T4,T5,T6,T7,P
++ * where Tn are the tag bytes, En are MTD's ECC bytes, P is the pageStatus
++ * byte and B is the small-page bad-block indicator byte.
++ */
++static struct nand_ecclayout nand_oob_16 = {
++ .eccbytes = 6,
++ .eccpos = { 8, 9, 10, 13, 14, 15 },
++ .oobavail = 9,
++ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
++};
++#endif
++
++/* Write a chunk (page) of data to NAND.
++ *
++ * Caller always provides ExtendedTags data which are converted to a more
++ * compact (packed) form for storage in NAND. A mini-ECC runs over the
++ * contents of the tags meta-data; used to valid the tags when read.
++ *
++ * - Pack ExtendedTags to PackedTags1 form
++ * - Compute mini-ECC for PackedTags1
++ * - Write data and packed tags to NAND.
++ *
++ * Note: Due to the use of the PackedTags1 meta-data which does not include
++ * a full sequence number (as found in the larger PackedTags2 form) it is
++ * necessary for Yaffs to re-write a chunk/page (just once) to mark it as
++ * discarded and dirty. This is not ideal: newer NAND parts are supposed
++ * to be written just once. When Yaffs performs this operation, this
++ * function is called with a NULL data pointer -- calling MTD write_oob
++ * without data is valid usage (2.6.17).
++ *
++ * Any underlying MTD error results in YAFFS_FAIL.
++ * Returns YAFFS_OK or YAFFS_FAIL.
++ */
++int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device *dev,
++ int chunkInNAND, const __u8 * data, const yaffs_ExtendedTags * etags)
++{
++ struct mtd_info * mtd = dev->genericDevice;
++ int chunkBytes = dev->nDataBytesPerChunk;
++ loff_t addr = ((loff_t)chunkInNAND) * chunkBytes;
++ struct mtd_oob_ops ops;
++ yaffs_PackedTags1 pt1;
++ int retval;
++
++ /* we assume that PackedTags1 and yaffs_Tags are compatible */
++ compile_time_assertion(sizeof(yaffs_PackedTags1) == 12);
++ compile_time_assertion(sizeof(yaffs_Tags) == 8);
++
++ dev->nPageWrites++;
++
++ yaffs_PackTags1(&pt1, etags);
++ yaffs_CalcTagsECC((yaffs_Tags *)&pt1);
++
++ /* When deleting a chunk, the upper layer provides only skeletal
++ * etags, one with chunkDeleted set. However, we need to update the
++ * tags, not erase them completely. So we use the NAND write property
++ * that only zeroed-bits stick and set tag bytes to all-ones and
++ * zero just the (not) deleted bit.
++ */
++#ifndef CONFIG_YAFFS_9BYTE_TAGS
++ if (etags->chunkDeleted) {
++ memset(&pt1, 0xff, 8);
++ /* clear delete status bit to indicate deleted */
++ pt1.deleted = 0;
++ }
++#else
++ ((__u8 *)&pt1)[8] = 0xff;
++ if (etags->chunkDeleted) {
++ memset(&pt1, 0xff, 8);
++ /* zero pageStatus byte to indicate deleted */
++ ((__u8 *)&pt1)[8] = 0;
++ }
++#endif
++
++ memset(&ops, 0, sizeof(ops));
++ ops.mode = MTD_OOB_AUTO;
++ ops.len = (data) ? chunkBytes : 0;
++ ops.ooblen = YTAG1_SIZE;
++ ops.datbuf = (__u8 *)data;
++ ops.oobbuf = (__u8 *)&pt1;
++
++ retval = mtd->write_oob(mtd, addr, &ops);
++ if (retval) {
++ yaffs_trace(YAFFS_TRACE_MTD,
++ "write_oob failed, chunk %d, mtd error %d\n",
++ chunkInNAND, retval);
++ }
++ return retval ? YAFFS_FAIL : YAFFS_OK;
++}
++
++/* Return with empty ExtendedTags but add eccResult.
++ */
++static int rettags(yaffs_ExtendedTags * etags, int eccResult, int retval)
++{
++ if (etags) {
++ memset(etags, 0, sizeof(*etags));
++ etags->eccResult = eccResult;
++ }
++ return retval;
++}
++
++/* Read a chunk (page) from NAND.
++ *
++ * Caller expects ExtendedTags data to be usable even on error; that is,
++ * all members except eccResult and blockBad are zeroed.
++ *
++ * - Check ECC results for data (if applicable)
++ * - Check for blank/erased block (return empty ExtendedTags if blank)
++ * - Check the PackedTags1 mini-ECC (correct if necessary/possible)
++ * - Convert PackedTags1 to ExtendedTags
++ * - Update eccResult and blockBad members to refect state.
++ *
++ * Returns YAFFS_OK or YAFFS_FAIL.
++ */
++int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device *dev,
++ int chunkInNAND, __u8 * data, yaffs_ExtendedTags * etags)
++{
++ struct mtd_info * mtd = dev->genericDevice;
++ int chunkBytes = dev->nDataBytesPerChunk;
++ loff_t addr = ((loff_t)chunkInNAND) * chunkBytes;
++ int eccres = YAFFS_ECC_RESULT_NO_ERROR;
++ struct mtd_oob_ops ops;
++ yaffs_PackedTags1 pt1;
++ int retval;
++ int deleted;
++
++ dev->nPageReads++;
++
++ memset(&ops, 0, sizeof(ops));
++ ops.mode = MTD_OOB_AUTO;
++ ops.len = (data) ? chunkBytes : 0;
++ ops.ooblen = YTAG1_SIZE;
++ ops.datbuf = data;
++ ops.oobbuf = (__u8 *)&pt1;
++
++#if (MTD_VERSION_CODE < MTD_VERSION(2,6,20))
++ /* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug;
++ * help it out with ops.len = ops.ooblen when ops.datbuf == NULL.
++ */
++ ops.len = (ops.datbuf) ? ops.len : ops.ooblen;
++#endif
++ /* Read page and oob using MTD.
++ * Check status and determine ECC result.
++ */
++ retval = mtd->read_oob(mtd, addr, &ops);
++ if (retval) {
++ yaffs_trace(YAFFS_TRACE_MTD,
++ "read_oob failed, chunk %d, mtd error %d\n",
++ chunkInNAND, retval);
++ }
++
++ switch (retval) {
++ case 0:
++ /* no error */
++ break;
++
++ case -EUCLEAN:
++ /* MTD's ECC fixed the data */
++ eccres = YAFFS_ECC_RESULT_FIXED;
++ dev->eccFixed++;
++ break;
++
++ case -EBADMSG:
++ /* MTD's ECC could not fix the data */
++ dev->eccUnfixed++;
++ /* fall into... */
++ default:
++ rettags(etags, YAFFS_ECC_RESULT_UNFIXED, 0);
++ etags->blockBad = (mtd->block_isbad)(mtd, addr);
++ return YAFFS_FAIL;
++ }
++
++ /* Check for a blank/erased chunk.
++ */
++ if (yaffs_CheckFF((__u8 *)&pt1, 8)) {
++ /* when blank, upper layers want eccResult to be <= NO_ERROR */
++ return rettags(etags, YAFFS_ECC_RESULT_NO_ERROR, YAFFS_OK);
++ }
++
++#ifndef CONFIG_YAFFS_9BYTE_TAGS
++ /* Read deleted status (bit) then return it to it's non-deleted
++ * state before performing tags mini-ECC check. pt1.deleted is
++ * inverted.
++ */
++ deleted = !pt1.deleted;
++ pt1.deleted = 1;
++#else
++ deleted = (yaffs_CountBits(((__u8 *)&pt1)[8]) < 7);
++#endif
++
++ /* Check the packed tags mini-ECC and correct if necessary/possible.
++ */
++ retval = yaffs_CheckECCOnTags((yaffs_Tags *)&pt1);
++ switch (retval) {
++ case 0:
++ /* no tags error, use MTD result */
++ break;
++ case 1:
++ /* recovered tags-ECC error */
++ dev->tagsEccFixed++;
++ if (eccres == YAFFS_ECC_RESULT_NO_ERROR)
++ eccres = YAFFS_ECC_RESULT_FIXED;
++ break;
++ default:
++ /* unrecovered tags-ECC error */
++ dev->tagsEccUnfixed++;
++ return rettags(etags, YAFFS_ECC_RESULT_UNFIXED, YAFFS_FAIL);
++ }
++
++ /* Unpack the tags to extended form and set ECC result.
++ * [set shouldBeFF just to keep yaffs_UnpackTags1 happy]
++ */
++ pt1.shouldBeFF = 0xFFFFFFFF;
++ yaffs_UnpackTags1(etags, &pt1);
++ etags->eccResult = eccres;
++
++ /* Set deleted state */
++ etags->chunkDeleted = deleted;
++ return YAFFS_OK;
++}
++
++/* Mark a block bad.
++ *
++ * This is a persistant state.
++ * Use of this function should be rare.
++ *
++ * Returns YAFFS_OK or YAFFS_FAIL.
++ */
++int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
++{
++ struct mtd_info * mtd = dev->genericDevice;
++ int blocksize = dev->nChunksPerBlock * dev->nDataBytesPerChunk;
++ int retval;
++
++ yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, "marking block %d bad\n", blockNo);
++
++ retval = mtd->block_markbad(mtd, (loff_t)blocksize * blockNo);
++ return (retval) ? YAFFS_FAIL : YAFFS_OK;
++}
++
++/* Check any MTD prerequists.
++ *
++ * Returns YAFFS_OK or YAFFS_FAIL.
++ */
++static int nandmtd1_TestPrerequists(struct mtd_info * mtd)
++{
++ /* 2.6.18 has mtd->ecclayout->oobavail */
++ /* 2.6.21 has mtd->ecclayout->oobavail and mtd->oobavail */
++ int oobavail = mtd->ecclayout->oobavail;
++
++ if (oobavail < YTAG1_SIZE) {
++ yaffs_trace(YAFFS_TRACE_ERROR,
++ "mtd device has only %d bytes for tags, need %d\n",
++ oobavail, YTAG1_SIZE);
++ return YAFFS_FAIL;
++ }
++ return YAFFS_OK;
++}
++
++/* Query for the current state of a specific block.
++ *
++ * Examine the tags of the first chunk of the block and return the state:
++ * - YAFFS_BLOCK_STATE_DEAD, the block is marked bad
++ * - YAFFS_BLOCK_STATE_NEEDS_SCANNING, the block is in use
++ * - YAFFS_BLOCK_STATE_EMPTY, the block is clean
++ *
++ * Always returns YAFFS_OK.
++ */
++int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
++ yaffs_BlockState * pState, __u32 *pSequenceNumber)
++{
++ struct mtd_info * mtd = dev->genericDevice;
++ int chunkNo = blockNo * dev->nChunksPerBlock;
++ loff_t addr = (loff_t)chunkNo * dev->nDataBytesPerChunk;
++ yaffs_ExtendedTags etags;
++ int state = YAFFS_BLOCK_STATE_DEAD;
++ int seqnum = 0;
++ int retval;
++
++ /* We don't yet have a good place to test for MTD config prerequists.
++ * Do it here as we are called during the initial scan.
++ */
++ if (nandmtd1_TestPrerequists(mtd) != YAFFS_OK) {
++ return YAFFS_FAIL;
++ }
++
++ retval = nandmtd1_ReadChunkWithTagsFromNAND(dev, chunkNo, NULL, &etags);
++ etags.blockBad = (mtd->block_isbad)(mtd, addr);
++ if (etags.blockBad) {
++ yaffs_trace(YAFFS_TRACE_BAD_BLOCKS,
++ "block %d is marked bad\n", blockNo);
++ state = YAFFS_BLOCK_STATE_DEAD;
++ }
++ else if (etags.eccResult != YAFFS_ECC_RESULT_NO_ERROR) {
++ /* bad tags, need to look more closely */
++ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
++ }
++ else if (etags.chunkUsed) {
++ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
++ seqnum = etags.sequenceNumber;
++ }
++ else {
++ state = YAFFS_BLOCK_STATE_EMPTY;
++ }
++
++ *pState = state;
++ *pSequenceNumber = seqnum;
++
++ /* query always succeeds */
++ return YAFFS_OK;
++}
++
++#endif /*MTD_VERSION*/
+diff --git a/fs/yaffs2/yaffs_mtdif1.h b/fs/yaffs2/yaffs_mtdif1.h
+new file mode 100644
+index 0000000..5fa056c
+--- /dev/null
++++ b/fs/yaffs2/yaffs_mtdif1.h
+@@ -0,0 +1,28 @@
++/*
++ * YAFFS: Yet another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_MTDIF1_H__
++#define __YAFFS_MTDIF1_H__
++
++int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data, const yaffs_ExtendedTags * tags);
++
++int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
++ __u8 * data, yaffs_ExtendedTags * tags);
++
++int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
++
++int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
++ yaffs_BlockState * state, __u32 *sequenceNumber);
++
++#endif
+diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c
+new file mode 100644
+index 0000000..ff4531b
+--- /dev/null
++++ b/fs/yaffs2/yaffs_mtdif2.c
+@@ -0,0 +1,248 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/* mtd interface for YAFFS2 */
++
++const char *yaffs_mtdif2_c_version =
++ "$Id: yaffs_mtdif2.c,v 1.22 2008/11/02 22:47:13 charles Exp $";
++
++#include "yportenv.h"
++
++
++#include "yaffs_mtdif2.h"
++
++#include "linux/mtd/mtd.h"
++#include "linux/types.h"
++#include "linux/time.h"
++
++#include "yaffs_packedtags2.h"
++
++/* NB For use with inband tags....
++ * We assume that the data buffer is of size totalBytersPerChunk so that we can also
++ * use it to load the tags.
++ */
++int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data,
++ const yaffs_ExtendedTags * tags)
++{
++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++ struct mtd_oob_ops ops;
++#else
++ size_t dummy;
++#endif
++ int retval = 0;
++
++ loff_t addr;
++
++ yaffs_PackedTags2 pt;
++
++ T(YAFFS_TRACE_MTD,
++ (TSTR
++ ("nandmtd2_WriteChunkWithTagsToNAND chunk %d data %p tags %p"
++ TENDSTR), chunkInNAND, data, tags));
++
++
++ addr = ((loff_t) chunkInNAND) * dev->totalBytesPerChunk;
++
++ /* For yaffs2 writing there must be both data and tags.
++ * If we're using inband tags, then the tags are stuffed into
++ * the end of the data buffer.
++ */
++ if(!data || !tags)
++ BUG();
++ else if(dev->inbandTags){
++ yaffs_PackedTags2TagsPart *pt2tp;
++ pt2tp = (yaffs_PackedTags2TagsPart *)(data + dev->nDataBytesPerChunk);
++ yaffs_PackTags2TagsPart(pt2tp,tags);
++ }
++ else
++ yaffs_PackTags2(&pt, tags);
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++ ops.mode = MTD_OOB_AUTO;
++ ops.ooblen = (dev->inbandTags) ? 0 : sizeof(pt);
++ ops.len = dev->totalBytesPerChunk;
++ ops.ooboffs = 0;
++ ops.datbuf = (__u8 *)data;
++ ops.oobbuf = (dev->inbandTags) ? NULL : (void *)&pt;
++ retval = mtd->write_oob(mtd, addr, &ops);
++
++#else
++ if (!dev->inbandTags) {
++ retval =
++ mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data, (__u8 *) & pt, NULL);
++ } else {
++ retval =
++ mtd->write(mtd, addr, dev->totalBytesPerChunk, &dummy,
++ data);
++ }
++#endif
++
++ if (retval == 0)
++ return YAFFS_OK;
++ else
++ return YAFFS_FAIL;
++}
++
++int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
++ __u8 * data, yaffs_ExtendedTags * tags)
++{
++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17))
++ struct mtd_oob_ops ops;
++#endif
++ size_t dummy;
++ int retval = 0;
++ int localData = 0;
++
++ loff_t addr = ((loff_t) chunkInNAND) * dev->totalBytesPerChunk;
++
++ yaffs_PackedTags2 pt;
++
++ T(YAFFS_TRACE_MTD,
++ (TSTR
++ ("nandmtd2_ReadChunkWithTagsFromNAND chunk %d data %p tags %p"
++ TENDSTR), chunkInNAND, data, tags));
++
++ if(dev->inbandTags){
++
++ if(!data) {
++ localData = 1;
++ data = yaffs_GetTempBuffer(dev,__LINE__);
++ }
++
++
++ }
++
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
++ if (dev->inbandTags || (data && !tags))
++ retval = mtd->read(mtd, addr, dev->totalBytesPerChunk,
++ &dummy, data);
++ else if (tags) {
++ ops.mode = MTD_OOB_AUTO;
++ ops.ooblen = sizeof(pt);
++ ops.len = data ? dev->nDataBytesPerChunk : sizeof(pt);
++ ops.ooboffs = 0;
++ ops.datbuf = data;
++ ops.oobbuf = dev->spareBuffer;
++ retval = mtd->read_oob(mtd, addr, &ops);
++ }
++#else
++ if (!dev->inbandTags && data && tags) {
++
++ retval = mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
++ &dummy, data, dev->spareBuffer,
++ NULL);
++ } else {
++ if (data)
++ retval =
++ mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy,
++ data);
++ if (!dev->inbandTags && tags)
++ retval =
++ mtd->read_oob(mtd, addr, mtd->oobsize, &dummy,
++ dev->spareBuffer);
++ }
++#endif
++
++
++ if(dev->inbandTags){
++ if(tags){
++ yaffs_PackedTags2TagsPart * pt2tp;
++ pt2tp = (yaffs_PackedTags2TagsPart *)&data[dev->nDataBytesPerChunk];
++ yaffs_UnpackTags2TagsPart(tags,pt2tp);
++ }
++ }
++ else {
++ if (tags){
++ memcpy(&pt, dev->spareBuffer, sizeof(pt));
++ yaffs_UnpackTags2(tags, &pt);
++ }
++ }
++
++ if(localData)
++ yaffs_ReleaseTempBuffer(dev,data,__LINE__);
++
++ if(tags && retval == -EBADMSG && tags->eccResult == YAFFS_ECC_RESULT_NO_ERROR)
++ tags->eccResult = YAFFS_ECC_RESULT_UNFIXED;
++ if (retval == 0)
++ return YAFFS_OK;
++ else
++ return YAFFS_FAIL;
++}
++
++int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
++{
++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
++ int retval;
++ T(YAFFS_TRACE_MTD,
++ (TSTR("nandmtd2_MarkNANDBlockBad %d" TENDSTR), blockNo));
++
++ retval =
++ mtd->block_markbad(mtd,
++ blockNo * dev->nChunksPerBlock *
++ dev->totalBytesPerChunk);
++
++ if (retval == 0)
++ return YAFFS_OK;
++ else
++ return YAFFS_FAIL;
++
++}
++
++int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
++ yaffs_BlockState * state, __u32 *sequenceNumber)
++{
++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
++ int retval;
++
++ T(YAFFS_TRACE_MTD,
++ (TSTR("nandmtd2_QueryNANDBlock %d" TENDSTR), blockNo));
++ retval =
++ mtd->block_isbad(mtd,
++ blockNo * dev->nChunksPerBlock *
++ dev->totalBytesPerChunk);
++
++ if (retval) {
++ T(YAFFS_TRACE_MTD, (TSTR("block is bad" TENDSTR)));
++
++ *state = YAFFS_BLOCK_STATE_DEAD;
++ *sequenceNumber = 0;
++ } else {
++ yaffs_ExtendedTags t;
++ nandmtd2_ReadChunkWithTagsFromNAND(dev,
++ blockNo *
++ dev->nChunksPerBlock, NULL,
++ &t);
++
++ if (t.chunkUsed) {
++ *sequenceNumber = t.sequenceNumber;
++ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
++ } else {
++ *sequenceNumber = 0;
++ *state = YAFFS_BLOCK_STATE_EMPTY;
++ }
++ }
++ T(YAFFS_TRACE_MTD,
++ (TSTR("block is bad seq %d state %d" TENDSTR), *sequenceNumber,
++ *state));
++
++ if (retval == 0)
++ return YAFFS_OK;
++ else
++ return YAFFS_FAIL;
++}
++
+diff --git a/fs/yaffs2/yaffs_mtdif2.h b/fs/yaffs2/yaffs_mtdif2.h
+new file mode 100644
+index 0000000..19f63b3
+--- /dev/null
++++ b/fs/yaffs2/yaffs_mtdif2.h
+@@ -0,0 +1,29 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_MTDIF2_H__
++#define __YAFFS_MTDIF2_H__
++
++#include "yaffs_guts.h"
++int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data,
++ const yaffs_ExtendedTags * tags);
++int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
++ __u8 * data, yaffs_ExtendedTags * tags);
++int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
++int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
++ yaffs_BlockState * state, __u32 *sequenceNumber);
++
++#endif
+diff --git a/fs/yaffs2/yaffs_nand.c b/fs/yaffs2/yaffs_nand.c
+new file mode 100644
+index 0000000..932b2b5
+--- /dev/null
++++ b/fs/yaffs2/yaffs_nand.c
+@@ -0,0 +1,135 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++const char *yaffs_nand_c_version =
++ "$Id: yaffs_nand.c,v 1.9 2008/05/05 07:58:58 charles Exp $";
++
++#include "yaffs_nand.h"
++#include "yaffs_tagscompat.h"
++#include "yaffs_tagsvalidity.h"
++
++#include "yaffs_getblockinfo.h"
++
++int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
++ __u8 * buffer,
++ yaffs_ExtendedTags * tags)
++{
++ int result;
++ yaffs_ExtendedTags localTags;
++
++ int realignedChunkInNAND = chunkInNAND - dev->chunkOffset;
++
++ /* If there are no tags provided, use local tags to get prioritised gc working */
++ if(!tags)
++ tags = &localTags;
++
++ if (dev->readChunkWithTagsFromNAND)
++ result = dev->readChunkWithTagsFromNAND(dev, realignedChunkInNAND, buffer,
++ tags);
++ else
++ result = yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(dev,
++ realignedChunkInNAND,
++ buffer,
++ tags);
++ if(tags &&
++ tags->eccResult > YAFFS_ECC_RESULT_NO_ERROR){
++
++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, chunkInNAND/dev->nChunksPerBlock);
++ yaffs_HandleChunkError(dev,bi);
++ }
++
++ return result;
++}
++
++int yaffs_WriteChunkWithTagsToNAND(yaffs_Device * dev,
++ int chunkInNAND,
++ const __u8 * buffer,
++ yaffs_ExtendedTags * tags)
++{
++ chunkInNAND -= dev->chunkOffset;
++
++
++ if (tags) {
++ tags->sequenceNumber = dev->sequenceNumber;
++ tags->chunkUsed = 1;
++ if (!yaffs_ValidateTags(tags)) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("Writing uninitialised tags" TENDSTR)));
++ YBUG();
++ }
++ T(YAFFS_TRACE_WRITE,
++ (TSTR("Writing chunk %d tags %d %d" TENDSTR), chunkInNAND,
++ tags->objectId, tags->chunkId));
++ } else {
++ T(YAFFS_TRACE_ERROR, (TSTR("Writing with no tags" TENDSTR)));
++ YBUG();
++ }
++
++ if (dev->writeChunkWithTagsToNAND)
++ return dev->writeChunkWithTagsToNAND(dev, chunkInNAND, buffer,
++ tags);
++ else
++ return yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(dev,
++ chunkInNAND,
++ buffer,
++ tags);
++}
++
++int yaffs_MarkBlockBad(yaffs_Device * dev, int blockNo)
++{
++ blockNo -= dev->blockOffset;
++
++;
++ if (dev->markNANDBlockBad)
++ return dev->markNANDBlockBad(dev, blockNo);
++ else
++ return yaffs_TagsCompatabilityMarkNANDBlockBad(dev, blockNo);
++}
++
++int yaffs_QueryInitialBlockState(yaffs_Device * dev,
++ int blockNo,
++ yaffs_BlockState * state,
++ __u32 *sequenceNumber)
++{
++ blockNo -= dev->blockOffset;
++
++ if (dev->queryNANDBlock)
++ return dev->queryNANDBlock(dev, blockNo, state, sequenceNumber);
++ else
++ return yaffs_TagsCompatabilityQueryNANDBlock(dev, blockNo,
++ state,
++ sequenceNumber);
++}
++
++
++int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
++ int blockInNAND)
++{
++ int result;
++
++ blockInNAND -= dev->blockOffset;
++
++
++ dev->nBlockErasures++;
++ result = dev->eraseBlockInNAND(dev, blockInNAND);
++
++ return result;
++}
++
++int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev)
++{
++ return dev->initialiseNAND(dev);
++}
++
++
++
+diff --git a/fs/yaffs2/yaffs_nand.h b/fs/yaffs2/yaffs_nand.h
+new file mode 100644
+index 0000000..5fa334b
+--- /dev/null
++++ b/fs/yaffs2/yaffs_nand.h
+@@ -0,0 +1,44 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_NAND_H__
++#define __YAFFS_NAND_H__
++#include "yaffs_guts.h"
++
++
++
++int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
++ __u8 * buffer,
++ yaffs_ExtendedTags * tags);
++
++int yaffs_WriteChunkWithTagsToNAND(yaffs_Device * dev,
++ int chunkInNAND,
++ const __u8 * buffer,
++ yaffs_ExtendedTags * tags);
++
++int yaffs_MarkBlockBad(yaffs_Device * dev, int blockNo);
++
++int yaffs_QueryInitialBlockState(yaffs_Device * dev,
++ int blockNo,
++ yaffs_BlockState * state,
++ unsigned *sequenceNumber);
++
++int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
++ int blockInNAND);
++
++int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev);
++
++#endif
++
+diff --git a/fs/yaffs2/yaffs_nandemul2k.h b/fs/yaffs2/yaffs_nandemul2k.h
+new file mode 100644
+index 0000000..c8576b3
+--- /dev/null
++++ b/fs/yaffs2/yaffs_nandemul2k.h
+@@ -0,0 +1,39 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++/* Interface to emulated NAND functions (2k page size) */
++
++#ifndef __YAFFS_NANDEMUL2K_H__
++#define __YAFFS_NANDEMUL2K_H__
++
++#include "yaffs_guts.h"
++
++int nandemul2k_WriteChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
++ int chunkInNAND, const __u8 * data,
++ const yaffs_ExtendedTags * tags);
++int nandemul2k_ReadChunkWithTagsFromNAND(struct yaffs_DeviceStruct *dev,
++ int chunkInNAND, __u8 * data,
++ yaffs_ExtendedTags * tags);
++int nandemul2k_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
++int nandemul2k_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
++ yaffs_BlockState * state, __u32 *sequenceNumber);
++int nandemul2k_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
++ int blockInNAND);
++int nandemul2k_InitialiseNAND(struct yaffs_DeviceStruct *dev);
++int nandemul2k_GetBytesPerChunk(void);
++int nandemul2k_GetChunksPerBlock(void);
++int nandemul2k_GetNumberOfBlocks(void);
++
++#endif
+diff --git a/fs/yaffs2/yaffs_packedtags1.c b/fs/yaffs2/yaffs_packedtags1.c
+new file mode 100644
+index 0000000..f480bf1
+--- /dev/null
++++ b/fs/yaffs2/yaffs_packedtags1.c
+@@ -0,0 +1,52 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "yaffs_packedtags1.h"
++#include "yportenv.h"
++
++void yaffs_PackTags1(yaffs_PackedTags1 * pt, const yaffs_ExtendedTags * t)
++{
++ pt->chunkId = t->chunkId;
++ pt->serialNumber = t->serialNumber;
++ pt->byteCount = t->byteCount;
++ pt->objectId = t->objectId;
++ pt->ecc = 0;
++ pt->deleted = (t->chunkDeleted) ? 0 : 1;
++ pt->unusedStuff = 0;
++ pt->shouldBeFF = 0xFFFFFFFF;
++
++}
++
++void yaffs_UnpackTags1(yaffs_ExtendedTags * t, const yaffs_PackedTags1 * pt)
++{
++ static const __u8 allFF[] =
++ { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++0xff };
++
++ if (memcmp(allFF, pt, sizeof(yaffs_PackedTags1))) {
++ t->blockBad = 0;
++ if (pt->shouldBeFF != 0xFFFFFFFF) {
++ t->blockBad = 1;
++ }
++ t->chunkUsed = 1;
++ t->objectId = pt->objectId;
++ t->chunkId = pt->chunkId;
++ t->byteCount = pt->byteCount;
++ t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
++ t->chunkDeleted = (pt->deleted) ? 0 : 1;
++ t->serialNumber = pt->serialNumber;
++ } else {
++ memset(t, 0, sizeof(yaffs_ExtendedTags));
++
++ }
++}
+diff --git a/fs/yaffs2/yaffs_packedtags1.h b/fs/yaffs2/yaffs_packedtags1.h
+new file mode 100644
+index 0000000..776c5c2
+--- /dev/null
++++ b/fs/yaffs2/yaffs_packedtags1.h
+@@ -0,0 +1,37 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */
++
++#ifndef __YAFFS_PACKEDTAGS1_H__
++#define __YAFFS_PACKEDTAGS1_H__
++
++#include "yaffs_guts.h"
++
++typedef struct {
++ unsigned chunkId:20;
++ unsigned serialNumber:2;
++ unsigned byteCount:10;
++ unsigned objectId:18;
++ unsigned ecc:12;
++ unsigned deleted:1;
++ unsigned unusedStuff:1;
++ unsigned shouldBeFF;
++
++} yaffs_PackedTags1;
++
++void yaffs_PackTags1(yaffs_PackedTags1 * pt, const yaffs_ExtendedTags * t);
++void yaffs_UnpackTags1(yaffs_ExtendedTags * t, const yaffs_PackedTags1 * pt);
++#endif
+diff --git a/fs/yaffs2/yaffs_packedtags2.c b/fs/yaffs2/yaffs_packedtags2.c
+new file mode 100644
+index 0000000..957ed8b
+--- /dev/null
++++ b/fs/yaffs2/yaffs_packedtags2.c
+@@ -0,0 +1,208 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "yaffs_packedtags2.h"
++#include "yportenv.h"
++#include "yaffs_tagsvalidity.h"
++
++/* This code packs a set of extended tags into a binary structure for
++ * NAND storage
++ */
++
++/* Some of the information is "extra" struff which can be packed in to
++ * speed scanning
++ * This is defined by having the EXTRA_HEADER_INFO_FLAG set.
++ */
++
++/* Extra flags applied to chunkId */
++
++#define EXTRA_HEADER_INFO_FLAG 0x80000000
++#define EXTRA_SHRINK_FLAG 0x40000000
++#define EXTRA_SHADOWS_FLAG 0x20000000
++#define EXTRA_SPARE_FLAGS 0x10000000
++
++#define ALL_EXTRA_FLAGS 0xF0000000
++
++/* Also, the top 4 bits of the object Id are set to the object type. */
++#define EXTRA_OBJECT_TYPE_SHIFT (28)
++#define EXTRA_OBJECT_TYPE_MASK ((0x0F) << EXTRA_OBJECT_TYPE_SHIFT)
++
++
++static void yaffs_DumpPackedTags2TagsPart(const yaffs_PackedTags2TagsPart * ptt)
++{
++ T(YAFFS_TRACE_MTD,
++ (TSTR("packed tags obj %d chunk %d byte %d seq %d" TENDSTR),
++ ptt->objectId, ptt->chunkId, ptt->byteCount,
++ ptt->sequenceNumber));
++}
++static void yaffs_DumpPackedTags2(const yaffs_PackedTags2 * pt)
++{
++ yaffs_DumpPackedTags2TagsPart(&pt->t);
++}
++
++static void yaffs_DumpTags2(const yaffs_ExtendedTags * t)
++{
++ T(YAFFS_TRACE_MTD,
++ (TSTR
++ ("ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d"
++ TENDSTR), t->eccResult, t->blockBad, t->chunkUsed, t->objectId,
++ t->chunkId, t->byteCount, t->chunkDeleted, t->serialNumber,
++ t->sequenceNumber));
++
++}
++
++void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart * ptt, const yaffs_ExtendedTags * t)
++{
++ ptt->chunkId = t->chunkId;
++ ptt->sequenceNumber = t->sequenceNumber;
++ ptt->byteCount = t->byteCount;
++ ptt->objectId = t->objectId;
++
++ if (t->chunkId == 0 && t->extraHeaderInfoAvailable) {
++ /* Store the extra header info instead */
++ /* We save the parent object in the chunkId */
++ ptt->chunkId = EXTRA_HEADER_INFO_FLAG
++ | t->extraParentObjectId;
++ if (t->extraIsShrinkHeader) {
++ ptt->chunkId |= EXTRA_SHRINK_FLAG;
++ }
++ if (t->extraShadows) {
++ ptt->chunkId |= EXTRA_SHADOWS_FLAG;
++ }
++
++ ptt->objectId &= ~EXTRA_OBJECT_TYPE_MASK;
++ ptt->objectId |=
++ (t->extraObjectType << EXTRA_OBJECT_TYPE_SHIFT);
++
++ if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK) {
++ ptt->byteCount = t->extraEquivalentObjectId;
++ } else if (t->extraObjectType == YAFFS_OBJECT_TYPE_FILE) {
++ ptt->byteCount = t->extraFileLength;
++ } else {
++ ptt->byteCount = 0;
++ }
++ }
++
++ yaffs_DumpPackedTags2TagsPart(ptt);
++ yaffs_DumpTags2(t);
++}
++
++
++void yaffs_PackTags2(yaffs_PackedTags2 * pt, const yaffs_ExtendedTags * t)
++{
++ yaffs_PackTags2TagsPart(&pt->t,t);
++
++#ifndef YAFFS_IGNORE_TAGS_ECC
++ {
++ yaffs_ECCCalculateOther((unsigned char *)&pt->t,
++ sizeof(yaffs_PackedTags2TagsPart),
++ &pt->ecc);
++ }
++#endif
++}
++
++
++void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags * t, yaffs_PackedTags2TagsPart * ptt)
++{
++
++ memset(t, 0, sizeof(yaffs_ExtendedTags));
++
++ yaffs_InitialiseTags(t);
++
++ if (ptt->sequenceNumber != 0xFFFFFFFF) {
++ t->blockBad = 0;
++ t->chunkUsed = 1;
++ t->objectId = ptt->objectId;
++ t->chunkId = ptt->chunkId;
++ t->byteCount = ptt->byteCount;
++ t->chunkDeleted = 0;
++ t->serialNumber = 0;
++ t->sequenceNumber = ptt->sequenceNumber;
++
++ /* Do extra header info stuff */
++
++ if (ptt->chunkId & EXTRA_HEADER_INFO_FLAG) {
++ t->chunkId = 0;
++ t->byteCount = 0;
++
++ t->extraHeaderInfoAvailable = 1;
++ t->extraParentObjectId =
++ ptt->chunkId & (~(ALL_EXTRA_FLAGS));
++ t->extraIsShrinkHeader =
++ (ptt->chunkId & EXTRA_SHRINK_FLAG) ? 1 : 0;
++ t->extraShadows =
++ (ptt->chunkId & EXTRA_SHADOWS_FLAG) ? 1 : 0;
++ t->extraObjectType =
++ ptt->objectId >> EXTRA_OBJECT_TYPE_SHIFT;
++ t->objectId &= ~EXTRA_OBJECT_TYPE_MASK;
++
++ if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK) {
++ t->extraEquivalentObjectId = ptt->byteCount;
++ } else {
++ t->extraFileLength = ptt->byteCount;
++ }
++ }
++ }
++
++ yaffs_DumpPackedTags2TagsPart(ptt);
++ yaffs_DumpTags2(t);
++
++}
++
++
++void yaffs_UnpackTags2(yaffs_ExtendedTags * t, yaffs_PackedTags2 * pt)
++{
++
++ yaffs_UnpackTags2TagsPart(t,&pt->t);
++
++ if (pt->t.sequenceNumber != 0xFFFFFFFF) {
++ /* Page is in use */
++#ifdef YAFFS_IGNORE_TAGS_ECC
++ {
++ t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
++ }
++#else
++ {
++ yaffs_ECCOther ecc;
++ int result;
++ yaffs_ECCCalculateOther((unsigned char *)&pt->t,
++ sizeof
++ (yaffs_PackedTags2TagsPart),
++ &ecc);
++ result =
++ yaffs_ECCCorrectOther((unsigned char *)&pt->t,
++ sizeof
++ (yaffs_PackedTags2TagsPart),
++ &pt->ecc, &ecc);
++ switch(result){
++ case 0:
++ t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
++ break;
++ case 1:
++ t->eccResult = YAFFS_ECC_RESULT_FIXED;
++ break;
++ case -1:
++ t->eccResult = YAFFS_ECC_RESULT_UNFIXED;
++ break;
++ default:
++ t->eccResult = YAFFS_ECC_RESULT_UNKNOWN;
++ }
++ }
++#endif
++ }
++
++ yaffs_DumpPackedTags2(pt);
++ yaffs_DumpTags2(t);
++
++}
++
+diff --git a/fs/yaffs2/yaffs_packedtags2.h b/fs/yaffs2/yaffs_packedtags2.h
+new file mode 100644
+index 0000000..75761d3
+--- /dev/null
++++ b/fs/yaffs2/yaffs_packedtags2.h
+@@ -0,0 +1,43 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++/* This is used to pack YAFFS2 tags, not YAFFS1tags. */
++
++#ifndef __YAFFS_PACKEDTAGS2_H__
++#define __YAFFS_PACKEDTAGS2_H__
++
++#include "yaffs_guts.h"
++#include "yaffs_ecc.h"
++
++typedef struct {
++ unsigned sequenceNumber;
++ unsigned objectId;
++ unsigned chunkId;
++ unsigned byteCount;
++} yaffs_PackedTags2TagsPart;
++
++typedef struct {
++ yaffs_PackedTags2TagsPart t;
++ yaffs_ECCOther ecc;
++} yaffs_PackedTags2;
++
++/* Full packed tags with ECC, used for oob tags */
++void yaffs_PackTags2(yaffs_PackedTags2 * pt, const yaffs_ExtendedTags * t);
++void yaffs_UnpackTags2(yaffs_ExtendedTags * t, yaffs_PackedTags2 * pt);
++
++/* Only the tags part (no ECC for use with inband tags */
++void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart * pt, const yaffs_ExtendedTags * t);
++void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags * t, yaffs_PackedTags2TagsPart * pt);
++#endif
+diff --git a/fs/yaffs2/yaffs_qsort.c b/fs/yaffs2/yaffs_qsort.c
+new file mode 100644
+index 0000000..474be9c
+--- /dev/null
++++ b/fs/yaffs2/yaffs_qsort.c
+@@ -0,0 +1,160 @@
++/*
++ * Copyright (c) 1992, 1993
++ * The Regents of the University of California. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ * 1. Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * 2. Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * 3. Neither the name of the University nor the names of its contributors
++ * may be used to endorse or promote products derived from this software
++ * without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ */
++
++#include "yportenv.h"
++//#include <linux/string.h>
++
++/*
++ * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function".
++ */
++#define swapcode(TYPE, parmi, parmj, n) { \
++ long i = (n) / sizeof (TYPE); \
++ register TYPE *pi = (TYPE *) (parmi); \
++ register TYPE *pj = (TYPE *) (parmj); \
++ do { \
++ register TYPE t = *pi; \
++ *pi++ = *pj; \
++ *pj++ = t; \
++ } while (--i > 0); \
++}
++
++#define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \
++ es % sizeof(long) ? 2 : es == sizeof(long)? 0 : 1;
++
++static __inline void
++swapfunc(char *a, char *b, int n, int swaptype)
++{
++ if (swaptype <= 1)
++ swapcode(long, a, b, n)
++ else
++ swapcode(char, a, b, n)
++}
++
++#define swap(a, b) \
++ if (swaptype == 0) { \
++ long t = *(long *)(a); \
++ *(long *)(a) = *(long *)(b); \
++ *(long *)(b) = t; \
++ } else \
++ swapfunc(a, b, es, swaptype)
++
++#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype)
++
++static __inline char *
++med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *))
++{
++ return cmp(a, b) < 0 ?
++ (cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a ))
++ :(cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c ));
++}
++
++#ifndef min
++#define min(a,b) (((a) < (b)) ? (a) : (b))
++#endif
++
++void
++yaffs_qsort(void *aa, size_t n, size_t es,
++ int (*cmp)(const void *, const void *))
++{
++ char *pa, *pb, *pc, *pd, *pl, *pm, *pn;
++ int d, r, swaptype, swap_cnt;
++ register char *a = aa;
++
++loop: SWAPINIT(a, es);
++ swap_cnt = 0;
++ if (n < 7) {
++ for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es)
++ for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
++ pl -= es)
++ swap(pl, pl - es);
++ return;
++ }
++ pm = (char *)a + (n / 2) * es;
++ if (n > 7) {
++ pl = (char *)a;
++ pn = (char *)a + (n - 1) * es;
++ if (n > 40) {
++ d = (n / 8) * es;
++ pl = med3(pl, pl + d, pl + 2 * d, cmp);
++ pm = med3(pm - d, pm, pm + d, cmp);
++ pn = med3(pn - 2 * d, pn - d, pn, cmp);
++ }
++ pm = med3(pl, pm, pn, cmp);
++ }
++ swap(a, pm);
++ pa = pb = (char *)a + es;
++
++ pc = pd = (char *)a + (n - 1) * es;
++ for (;;) {
++ while (pb <= pc && (r = cmp(pb, a)) <= 0) {
++ if (r == 0) {
++ swap_cnt = 1;
++ swap(pa, pb);
++ pa += es;
++ }
++ pb += es;
++ }
++ while (pb <= pc && (r = cmp(pc, a)) >= 0) {
++ if (r == 0) {
++ swap_cnt = 1;
++ swap(pc, pd);
++ pd -= es;
++ }
++ pc -= es;
++ }
++ if (pb > pc)
++ break;
++ swap(pb, pc);
++ swap_cnt = 1;
++ pb += es;
++ pc -= es;
++ }
++ if (swap_cnt == 0) { /* Switch to insertion sort */
++ for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es)
++ for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
++ pl -= es)
++ swap(pl, pl - es);
++ return;
++ }
++
++ pn = (char *)a + n * es;
++ r = min(pa - (char *)a, pb - pa);
++ vecswap(a, pb - r, r);
++ r = min((long)(pd - pc), (long)(pn - pd - es));
++ vecswap(pb, pn - r, r);
++ if ((r = pb - pa) > es)
++ yaffs_qsort(a, r / es, es, cmp);
++ if ((r = pd - pc) > es) {
++ /* Iterate rather than recurse to save stack space */
++ a = pn - r;
++ n = r / es;
++ goto loop;
++ }
++/* yaffs_qsort(pn - r, r / es, es, cmp);*/
++}
+diff --git a/fs/yaffs2/yaffs_qsort.h b/fs/yaffs2/yaffs_qsort.h
+new file mode 100644
+index 0000000..610b7ec
+--- /dev/null
++++ b/fs/yaffs2/yaffs_qsort.h
+@@ -0,0 +1,23 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++
++#ifndef __YAFFS_QSORT_H__
++#define __YAFFS_QSORT_H__
++
++extern void yaffs_qsort (void *const base, size_t total_elems, size_t size,
++ int (*cmp)(const void *, const void *));
++
++#endif
+diff --git a/fs/yaffs2/yaffs_tagscompat.c b/fs/yaffs2/yaffs_tagscompat.c
+new file mode 100644
+index 0000000..f6c4053
+--- /dev/null
++++ b/fs/yaffs2/yaffs_tagscompat.c
+@@ -0,0 +1,547 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "yaffs_guts.h"
++#include "yaffs_tagscompat.h"
++#include "yaffs_ecc.h"
++#include "yaffs_getblockinfo.h"
++
++static void yaffs_HandleReadDataError(yaffs_Device * dev, int chunkInNAND);
++#ifdef NOTYET
++static void yaffs_CheckWrittenBlock(yaffs_Device * dev, int chunkInNAND);
++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data,
++ const yaffs_Spare * spare);
++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
++ const yaffs_Spare * spare);
++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND);
++#endif
++
++static const char yaffs_countBitsTable[256] = {
++ 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4,
++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
++ 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8
++};
++
++int yaffs_CountBits(__u8 x)
++{
++ int retVal;
++ retVal = yaffs_countBitsTable[x];
++ return retVal;
++}
++
++/********** Tags ECC calculations *********/
++
++void yaffs_CalcECC(const __u8 * data, yaffs_Spare * spare)
++{
++ yaffs_ECCCalculate(data, spare->ecc1);
++ yaffs_ECCCalculate(&data[256], spare->ecc2);
++}
++
++void yaffs_CalcTagsECC(yaffs_Tags * tags)
++{
++ /* Calculate an ecc */
++
++ unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
++ unsigned i, j;
++ unsigned ecc = 0;
++ unsigned bit = 0;
++
++ tags->ecc = 0;
++
++ for (i = 0; i < 8; i++) {
++ for (j = 1; j & 0xff; j <<= 1) {
++ bit++;
++ if (b[i] & j) {
++ ecc ^= bit;
++ }
++ }
++ }
++
++ tags->ecc = ecc;
++
++}
++
++int yaffs_CheckECCOnTags(yaffs_Tags * tags)
++{
++ unsigned ecc = tags->ecc;
++
++ yaffs_CalcTagsECC(tags);
++
++ ecc ^= tags->ecc;
++
++ if (ecc && ecc <= 64) {
++ /* TODO: Handle the failure better. Retire? */
++ unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
++
++ ecc--;
++
++ b[ecc / 8] ^= (1 << (ecc & 7));
++
++ /* Now recvalc the ecc */
++ yaffs_CalcTagsECC(tags);
++
++ return 1; /* recovered error */
++ } else if (ecc) {
++ /* Wierd ecc failure value */
++ /* TODO Need to do somethiong here */
++ return -1; /* unrecovered error */
++ }
++
++ return 0;
++}
++
++/********** Tags **********/
++
++static void yaffs_LoadTagsIntoSpare(yaffs_Spare * sparePtr,
++ yaffs_Tags * tagsPtr)
++{
++ yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
++
++ yaffs_CalcTagsECC(tagsPtr);
++
++ sparePtr->tagByte0 = tu->asBytes[0];
++ sparePtr->tagByte1 = tu->asBytes[1];
++ sparePtr->tagByte2 = tu->asBytes[2];
++ sparePtr->tagByte3 = tu->asBytes[3];
++ sparePtr->tagByte4 = tu->asBytes[4];
++ sparePtr->tagByte5 = tu->asBytes[5];
++ sparePtr->tagByte6 = tu->asBytes[6];
++ sparePtr->tagByte7 = tu->asBytes[7];
++}
++
++static void yaffs_GetTagsFromSpare(yaffs_Device * dev, yaffs_Spare * sparePtr,
++ yaffs_Tags * tagsPtr)
++{
++ yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
++ int result;
++
++ tu->asBytes[0] = sparePtr->tagByte0;
++ tu->asBytes[1] = sparePtr->tagByte1;
++ tu->asBytes[2] = sparePtr->tagByte2;
++ tu->asBytes[3] = sparePtr->tagByte3;
++ tu->asBytes[4] = sparePtr->tagByte4;
++ tu->asBytes[5] = sparePtr->tagByte5;
++ tu->asBytes[6] = sparePtr->tagByte6;
++ tu->asBytes[7] = sparePtr->tagByte7;
++
++ result = yaffs_CheckECCOnTags(tagsPtr);
++ if (result > 0) {
++ dev->tagsEccFixed++;
++ } else if (result < 0) {
++ dev->tagsEccUnfixed++;
++ }
++}
++
++static void yaffs_SpareInitialise(yaffs_Spare * spare)
++{
++ memset(spare, 0xFF, sizeof(yaffs_Spare));
++}
++
++static int yaffs_WriteChunkToNAND(struct yaffs_DeviceStruct *dev,
++ int chunkInNAND, const __u8 * data,
++ yaffs_Spare * spare)
++{
++ if (chunkInNAND < dev->startBlock * dev->nChunksPerBlock) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR("**>> yaffs chunk %d is not valid" TENDSTR),
++ chunkInNAND));
++ return YAFFS_FAIL;
++ }
++
++ dev->nPageWrites++;
++ return dev->writeChunkToNAND(dev, chunkInNAND, data, spare);
++}
++
++static int yaffs_ReadChunkFromNAND(struct yaffs_DeviceStruct *dev,
++ int chunkInNAND,
++ __u8 * data,
++ yaffs_Spare * spare,
++ yaffs_ECCResult * eccResult,
++ int doErrorCorrection)
++{
++ int retVal;
++ yaffs_Spare localSpare;
++
++ dev->nPageReads++;
++
++ if (!spare && data) {
++ /* If we don't have a real spare, then we use a local one. */
++ /* Need this for the calculation of the ecc */
++ spare = &localSpare;
++ }
++
++ if (!dev->useNANDECC) {
++ retVal = dev->readChunkFromNAND(dev, chunkInNAND, data, spare);
++ if (data && doErrorCorrection) {
++ /* Do ECC correction */
++ /* Todo handle any errors */
++ int eccResult1, eccResult2;
++ __u8 calcEcc[3];
++
++ yaffs_ECCCalculate(data, calcEcc);
++ eccResult1 =
++ yaffs_ECCCorrect(data, spare->ecc1, calcEcc);
++ yaffs_ECCCalculate(&data[256], calcEcc);
++ eccResult2 =
++ yaffs_ECCCorrect(&data[256], spare->ecc2, calcEcc);
++
++ if (eccResult1 > 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>yaffs ecc error fix performed on chunk %d:0"
++ TENDSTR), chunkInNAND));
++ dev->eccFixed++;
++ } else if (eccResult1 < 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>yaffs ecc error unfixed on chunk %d:0"
++ TENDSTR), chunkInNAND));
++ dev->eccUnfixed++;
++ }
++
++ if (eccResult2 > 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>yaffs ecc error fix performed on chunk %d:1"
++ TENDSTR), chunkInNAND));
++ dev->eccFixed++;
++ } else if (eccResult2 < 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>yaffs ecc error unfixed on chunk %d:1"
++ TENDSTR), chunkInNAND));
++ dev->eccUnfixed++;
++ }
++
++ if (eccResult1 || eccResult2) {
++ /* We had a data problem on this page */
++ yaffs_HandleReadDataError(dev, chunkInNAND);
++ }
++
++ if (eccResult1 < 0 || eccResult2 < 0)
++ *eccResult = YAFFS_ECC_RESULT_UNFIXED;
++ else if (eccResult1 > 0 || eccResult2 > 0)
++ *eccResult = YAFFS_ECC_RESULT_FIXED;
++ else
++ *eccResult = YAFFS_ECC_RESULT_NO_ERROR;
++ }
++ } else {
++ /* Must allocate enough memory for spare+2*sizeof(int) */
++ /* for ecc results from device. */
++ struct yaffs_NANDSpare nspare;
++
++ memset(&nspare,0,sizeof(nspare));
++
++ retVal =
++ dev->readChunkFromNAND(dev, chunkInNAND, data,
++ (yaffs_Spare *) & nspare);
++ memcpy(spare, &nspare, sizeof(yaffs_Spare));
++ if (data && doErrorCorrection) {
++ if (nspare.eccres1 > 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>mtd ecc error fix performed on chunk %d:0"
++ TENDSTR), chunkInNAND));
++ } else if (nspare.eccres1 < 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>mtd ecc error unfixed on chunk %d:0"
++ TENDSTR), chunkInNAND));
++ }
++
++ if (nspare.eccres2 > 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>mtd ecc error fix performed on chunk %d:1"
++ TENDSTR), chunkInNAND));
++ } else if (nspare.eccres2 < 0) {
++ T(YAFFS_TRACE_ERROR,
++ (TSTR
++ ("**>>mtd ecc error unfixed on chunk %d:1"
++ TENDSTR), chunkInNAND));
++ }
++
++ if (nspare.eccres1 || nspare.eccres2) {
++ /* We had a data problem on this page */
++ yaffs_HandleReadDataError(dev, chunkInNAND);
++ }
++
++ if (nspare.eccres1 < 0 || nspare.eccres2 < 0)
++ *eccResult = YAFFS_ECC_RESULT_UNFIXED;
++ else if (nspare.eccres1 > 0 || nspare.eccres2 > 0)
++ *eccResult = YAFFS_ECC_RESULT_FIXED;
++ else
++ *eccResult = YAFFS_ECC_RESULT_NO_ERROR;
++
++ }
++ }
++ return retVal;
++}
++
++#ifdef NOTYET
++static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
++ int chunkInNAND)
++{
++
++ static int init = 0;
++ static __u8 cmpbuf[YAFFS_BYTES_PER_CHUNK];
++ static __u8 data[YAFFS_BYTES_PER_CHUNK];
++ /* Might as well always allocate the larger size for */
++ /* dev->useNANDECC == true; */
++ static __u8 spare[sizeof(struct yaffs_NANDSpare)];
++
++ dev->readChunkFromNAND(dev, chunkInNAND, data, (yaffs_Spare *) spare);
++
++ if (!init) {
++ memset(cmpbuf, 0xff, YAFFS_BYTES_PER_CHUNK);
++ init = 1;
++ }
++
++ if (memcmp(cmpbuf, data, YAFFS_BYTES_PER_CHUNK))
++ return YAFFS_FAIL;
++ if (memcmp(cmpbuf, spare, 16))
++ return YAFFS_FAIL;
++
++ return YAFFS_OK;
++
++}
++#endif
++
++/*
++ * Functions for robustisizing
++ */
++
++static void yaffs_HandleReadDataError(yaffs_Device * dev, int chunkInNAND)
++{
++ int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
++
++ /* Mark the block for retirement */
++ yaffs_GetBlockInfo(dev, blockInNAND + dev->blockOffset)->needsRetiring = 1;
++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
++ (TSTR("**>>Block %d marked for retirement" TENDSTR), blockInNAND));
++
++ /* TODO:
++ * Just do a garbage collection on the affected block
++ * then retire the block
++ * NB recursion
++ */
++}
++
++#ifdef NOTYET
++static void yaffs_CheckWrittenBlock(yaffs_Device * dev, int chunkInNAND)
++{
++}
++
++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
++ const __u8 * data,
++ const yaffs_Spare * spare)
++{
++}
++
++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
++ const yaffs_Spare * spare)
++{
++}
++
++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND)
++{
++ int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
++
++ /* Mark the block for retirement */
++ yaffs_GetBlockInfo(dev, blockInNAND)->needsRetiring = 1;
++ /* Delete the chunk */
++ yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
++}
++
++static int yaffs_VerifyCompare(const __u8 * d0, const __u8 * d1,
++ const yaffs_Spare * s0, const yaffs_Spare * s1)
++{
++
++ if (memcmp(d0, d1, YAFFS_BYTES_PER_CHUNK) != 0 ||
++ s0->tagByte0 != s1->tagByte0 ||
++ s0->tagByte1 != s1->tagByte1 ||
++ s0->tagByte2 != s1->tagByte2 ||
++ s0->tagByte3 != s1->tagByte3 ||
++ s0->tagByte4 != s1->tagByte4 ||
++ s0->tagByte5 != s1->tagByte5 ||
++ s0->tagByte6 != s1->tagByte6 ||
++ s0->tagByte7 != s1->tagByte7 ||
++ s0->ecc1[0] != s1->ecc1[0] ||
++ s0->ecc1[1] != s1->ecc1[1] ||
++ s0->ecc1[2] != s1->ecc1[2] ||
++ s0->ecc2[0] != s1->ecc2[0] ||
++ s0->ecc2[1] != s1->ecc2[1] || s0->ecc2[2] != s1->ecc2[2]) {
++ return 0;
++ }
++
++ return 1;
++}
++#endif /* NOTYET */
++
++int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device * dev,
++ int chunkInNAND,
++ const __u8 * data,
++ const yaffs_ExtendedTags *
++ eTags)
++{
++ yaffs_Spare spare;
++ yaffs_Tags tags;
++
++ yaffs_SpareInitialise(&spare);
++
++ if (eTags->chunkDeleted) {
++ spare.pageStatus = 0;
++ } else {
++ tags.objectId = eTags->objectId;
++ tags.chunkId = eTags->chunkId;
++
++ tags.byteCountLSB = eTags->byteCount & 0x3ff;
++
++ if(dev->nDataBytesPerChunk >= 1024){
++ tags.byteCountMSB = (eTags->byteCount >> 10) & 3;
++ } else {
++ tags.byteCountMSB = 3;
++ }
++
++
++ tags.serialNumber = eTags->serialNumber;
++
++ if (!dev->useNANDECC && data) {
++ yaffs_CalcECC(data, &spare);
++ }
++ yaffs_LoadTagsIntoSpare(&spare, &tags);
++
++ }
++
++ return yaffs_WriteChunkToNAND(dev, chunkInNAND, data, &spare);
++}
++
++int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device * dev,
++ int chunkInNAND,
++ __u8 * data,
++ yaffs_ExtendedTags * eTags)
++{
++
++ yaffs_Spare spare;
++ yaffs_Tags tags;
++ yaffs_ECCResult eccResult = YAFFS_ECC_RESULT_UNKNOWN;
++
++ static yaffs_Spare spareFF;
++ static int init = 0;
++
++ if (!init) {
++ memset(&spareFF, 0xFF, sizeof(spareFF));
++ init = 1;
++ }
++
++ if (yaffs_ReadChunkFromNAND
++ (dev, chunkInNAND, data, &spare, &eccResult, 1)) {
++ /* eTags may be NULL */
++ if (eTags) {
++
++ int deleted =
++ (yaffs_CountBits(spare.pageStatus) < 7) ? 1 : 0;
++
++ eTags->chunkDeleted = deleted;
++ eTags->eccResult = eccResult;
++ eTags->blockBad = 0; /* We're reading it */
++ /* therefore it is not a bad block */
++ eTags->chunkUsed =
++ (memcmp(&spareFF, &spare, sizeof(spareFF)) !=
++ 0) ? 1 : 0;
++
++ if (eTags->chunkUsed) {
++ yaffs_GetTagsFromSpare(dev, &spare, &tags);
++
++ eTags->objectId = tags.objectId;
++ eTags->chunkId = tags.chunkId;
++ eTags->byteCount = tags.byteCountLSB;
++
++ if(dev->nDataBytesPerChunk >= 1024)
++ eTags->byteCount |= (((unsigned) tags.byteCountMSB) << 10);
++
++ eTags->serialNumber = tags.serialNumber;
++ }
++ }
++
++ return YAFFS_OK;
++ } else {
++ return YAFFS_FAIL;
++ }
++}
++
++int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
++ int blockInNAND)
++{
++
++ yaffs_Spare spare;
++
++ memset(&spare, 0xff, sizeof(yaffs_Spare));
++
++ spare.blockStatus = 'Y';
++
++ yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock, NULL,
++ &spare);
++ yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock + 1,
++ NULL, &spare);
++
++ return YAFFS_OK;
++
++}
++
++int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
++ int blockNo,
++ yaffs_BlockState *state,
++ __u32 *sequenceNumber)
++{
++
++ yaffs_Spare spare0, spare1;
++ static yaffs_Spare spareFF;
++ static int init;
++ yaffs_ECCResult dummy;
++
++ if (!init) {
++ memset(&spareFF, 0xFF, sizeof(spareFF));
++ init = 1;
++ }
++
++ *sequenceNumber = 0;
++
++ yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock, NULL,
++ &spare0, &dummy, 1);
++ yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock + 1, NULL,
++ &spare1, &dummy, 1);
++
++ if (yaffs_CountBits(spare0.blockStatus & spare1.blockStatus) < 7)
++ *state = YAFFS_BLOCK_STATE_DEAD;
++ else if (memcmp(&spareFF, &spare0, sizeof(spareFF)) == 0)
++ *state = YAFFS_BLOCK_STATE_EMPTY;
++ else
++ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
++
++ return YAFFS_OK;
++}
+diff --git a/fs/yaffs2/yaffs_tagscompat.h b/fs/yaffs2/yaffs_tagscompat.h
+new file mode 100644
+index 0000000..6549398
+--- /dev/null
++++ b/fs/yaffs2/yaffs_tagscompat.h
+@@ -0,0 +1,41 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFS_TAGSCOMPAT_H__
++#define __YAFFS_TAGSCOMPAT_H__
++
++#include "yaffs_guts.h"
++int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device * dev,
++ int chunkInNAND,
++ const __u8 * data,
++ const yaffs_ExtendedTags *
++ tags);
++int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device * dev,
++ int chunkInNAND,
++ __u8 * data,
++ yaffs_ExtendedTags *
++ tags);
++int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
++ int blockNo);
++int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
++ int blockNo,
++ yaffs_BlockState *state,
++ __u32 *sequenceNumber);
++
++void yaffs_CalcTagsECC(yaffs_Tags * tags);
++int yaffs_CheckECCOnTags(yaffs_Tags * tags);
++int yaffs_CountBits(__u8 byte);
++
++#endif
+diff --git a/fs/yaffs2/yaffs_tagsvalidity.c b/fs/yaffs2/yaffs_tagsvalidity.c
+new file mode 100644
+index 0000000..9e0bd1c
+--- /dev/null
++++ b/fs/yaffs2/yaffs_tagsvalidity.c
+@@ -0,0 +1,28 @@
++/*
++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "yaffs_tagsvalidity.h"
++
++void yaffs_InitialiseTags(yaffs_ExtendedTags * tags)
++{
++ memset(tags, 0, sizeof(yaffs_ExtendedTags));
++ tags->validMarker0 = 0xAAAAAAAA;
++ tags->validMarker1 = 0x55555555;
++}
++
++int yaffs_ValidateTags(yaffs_ExtendedTags * tags)
++{
++ return (tags->validMarker0 == 0xAAAAAAAA &&
++ tags->validMarker1 == 0x55555555);
++
++}
+diff --git a/fs/yaffs2/yaffs_tagsvalidity.h b/fs/yaffs2/yaffs_tagsvalidity.h
+new file mode 100644
+index 0000000..2fd0c24
+--- /dev/null
++++ b/fs/yaffs2/yaffs_tagsvalidity.h
+@@ -0,0 +1,24 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++
++#ifndef __YAFFS_TAGS_VALIDITY_H__
++#define __YAFFS_TAGS_VALIDITY_H__
++
++#include "yaffs_guts.h"
++
++void yaffs_InitialiseTags(yaffs_ExtendedTags * tags);
++int yaffs_ValidateTags(yaffs_ExtendedTags * tags);
++#endif
+diff --git a/fs/yaffs2/yaffsinterface.h b/fs/yaffs2/yaffsinterface.h
+new file mode 100644
+index 0000000..810837a
+--- /dev/null
++++ b/fs/yaffs2/yaffsinterface.h
+@@ -0,0 +1,21 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++#ifndef __YAFFSINTERFACE_H__
++#define __YAFFSINTERFACE_H__
++
++int yaffs_Initialise(unsigned nBlocks);
++
++#endif
+diff --git a/fs/yaffs2/yportenv.h b/fs/yaffs2/yportenv.h
+new file mode 100644
+index 0000000..bfda36e
+--- /dev/null
++++ b/fs/yaffs2/yportenv.h
+@@ -0,0 +1,202 @@
++/*
++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
++ *
++ * Copyright (C) 2002-2007 Aleph One Ltd.
++ * for Toby Churchill Ltd and Brightstar Engineering
++ *
++ * Created by Charles Manning <charles@aleph1.co.uk>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU Lesser General Public License version 2.1 as
++ * published by the Free Software Foundation.
++ *
++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
++ */
++
++
++#ifndef __YPORTENV_H__
++#define __YPORTENV_H__
++
++/*
++ * Define the MTD version in terms of Linux Kernel versions
++ * This allows yaffs to be used independantly of the kernel
++ * as well as with it.
++ */
++
++#define MTD_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
++
++#if defined CONFIG_YAFFS_WINCE
++
++#include "ywinceenv.h"
++
++#elif defined __KERNEL__
++
++#include "moduleconfig.h"
++
++/* Linux kernel */
++
++#include <linux/version.h>
++#define MTD_VERSION_CODE LINUX_VERSION_CODE
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
++#include <linux/config.h>
++#endif
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/string.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++
++#define YCHAR char
++#define YUCHAR unsigned char
++#define _Y(x) x
++#define yaffs_strcat(a,b) strcat(a,b)
++#define yaffs_strcpy(a,b) strcpy(a,b)
++#define yaffs_strncpy(a,b,c) strncpy(a,b,c)
++#define yaffs_strncmp(a,b,c) strncmp(a,b,c)
++#define yaffs_strlen(s) strlen(s)
++#define yaffs_sprintf sprintf
++#define yaffs_toupper(a) toupper(a)
++
++#define Y_INLINE inline
++
++#define YAFFS_LOSTNFOUND_NAME "lost+found"
++#define YAFFS_LOSTNFOUND_PREFIX "obj"
++
++/* #define YPRINTF(x) printk x */
++#define YMALLOC(x) kmalloc(x,GFP_KERNEL)
++#define YFREE(x) kfree(x)
++#define YMALLOC_ALT(x) vmalloc(x)
++#define YFREE_ALT(x) vfree(x)
++#define YMALLOC_DMA(x) YMALLOC(x)
++
++// KR - added for use in scan so processes aren't blocked indefinitely.
++#define YYIELD() schedule()
++
++#define YAFFS_ROOT_MODE 0666
++#define YAFFS_LOSTNFOUND_MODE 0666
++
++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
++#define Y_CURRENT_TIME CURRENT_TIME.tv_sec
++#define Y_TIME_CONVERT(x) (x).tv_sec
++#else
++#define Y_CURRENT_TIME CURRENT_TIME
++#define Y_TIME_CONVERT(x) (x)
++#endif
++
++#define yaffs_SumCompare(x,y) ((x) == (y))
++#define yaffs_strcmp(a,b) strcmp(a,b)
++
++#define TENDSTR "\n"
++#define TSTR(x) KERN_WARNING x
++#define TOUT(p) printk p
++
++#define yaffs_trace(mask, fmt, args...) \
++ do { if ((mask) & (yaffs_traceMask|YAFFS_TRACE_ERROR)) \
++ printk(KERN_WARNING "yaffs: " fmt, ## args); \
++ } while (0)
++
++#define compile_time_assertion(assertion) \
++ ({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; })
++
++#elif defined CONFIG_YAFFS_DIRECT
++
++#define MTD_VERSION_CODE MTD_VERSION(2,6,22)
++
++/* Direct interface */
++#include "ydirectenv.h"
++
++#elif defined CONFIG_YAFFS_UTIL
++
++/* Stuff for YAFFS utilities */
++
++#include "stdlib.h"
++#include "stdio.h"
++#include "string.h"
++
++#include "devextras.h"
++
++#define YMALLOC(x) malloc(x)
++#define YFREE(x) free(x)
++#define YMALLOC_ALT(x) malloc(x)
++#define YFREE_ALT(x) free(x)
++
++#define YCHAR char
++#define YUCHAR unsigned char
++#define _Y(x) x
++#define yaffs_strcat(a,b) strcat(a,b)
++#define yaffs_strcpy(a,b) strcpy(a,b)
++#define yaffs_strncpy(a,b,c) strncpy(a,b,c)
++#define yaffs_strlen(s) strlen(s)
++#define yaffs_sprintf sprintf
++#define yaffs_toupper(a) toupper(a)
++
++#define Y_INLINE inline
++
++/* #define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s)) */
++/* #define YALERT(s) YINFO(s) */
++
++#define TENDSTR "\n"
++#define TSTR(x) x
++#define TOUT(p) printf p
++
++#define YAFFS_LOSTNFOUND_NAME "lost+found"
++#define YAFFS_LOSTNFOUND_PREFIX "obj"
++/* #define YPRINTF(x) printf x */
++
++#define YAFFS_ROOT_MODE 0666
++#define YAFFS_LOSTNFOUND_MODE 0666
++
++#define yaffs_SumCompare(x,y) ((x) == (y))
++#define yaffs_strcmp(a,b) strcmp(a,b)
++
++#else
++/* Should have specified a configuration type */
++#error Unknown configuration
++
++#endif
++
++/* see yaffs_fs.c */
++extern unsigned int yaffs_traceMask;
++extern unsigned int yaffs_wr_attempts;
++
++/*
++ * Tracing flags.
++ * The flags masked in YAFFS_TRACE_ALWAYS are always traced.
++ */
++
++#define YAFFS_TRACE_OS 0x00000002
++#define YAFFS_TRACE_ALLOCATE 0x00000004
++#define YAFFS_TRACE_SCAN 0x00000008
++#define YAFFS_TRACE_BAD_BLOCKS 0x00000010
++#define YAFFS_TRACE_ERASE 0x00000020
++#define YAFFS_TRACE_GC 0x00000040
++#define YAFFS_TRACE_WRITE 0x00000080
++#define YAFFS_TRACE_TRACING 0x00000100
++#define YAFFS_TRACE_DELETION 0x00000200
++#define YAFFS_TRACE_BUFFERS 0x00000400
++#define YAFFS_TRACE_NANDACCESS 0x00000800
++#define YAFFS_TRACE_GC_DETAIL 0x00001000
++#define YAFFS_TRACE_SCAN_DEBUG 0x00002000
++#define YAFFS_TRACE_MTD 0x00004000
++#define YAFFS_TRACE_CHECKPOINT 0x00008000
++
++#define YAFFS_TRACE_VERIFY 0x00010000
++#define YAFFS_TRACE_VERIFY_NAND 0x00020000
++#define YAFFS_TRACE_VERIFY_FULL 0x00040000
++#define YAFFS_TRACE_VERIFY_ALL 0x000F0000
++
++
++#define YAFFS_TRACE_ERROR 0x40000000
++#define YAFFS_TRACE_BUG 0x80000000
++#define YAFFS_TRACE_ALWAYS 0xF0000000
++
++
++#define T(mask,p) do{ if((mask) & (yaffs_traceMask | YAFFS_TRACE_ALWAYS)) TOUT(p);} while(0)
++
++#ifndef YBUG
++#define YBUG() do {T(YAFFS_TRACE_BUG,(TSTR("==>> yaffs bug: " __FILE__ " %d" TENDSTR),__LINE__));} while(0)
++#endif
++
++#endif
+diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h
+index c1b9a09..6cd4eb6 100644
+--- a/include/asm-arm/arch-s3c2410/gpio.h
++++ b/include/asm-arm/arch-s3c2410/gpio.h
+@@ -87,6 +87,7 @@ static inline void gpio_free(unsigned int gpio)
+ static inline int gpio_direction_input(unsigned int gpio)
+ {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT);
++ s3c_gpio_pullup(gpio, 0); // pull-up/down disable
+
+ return 0;
+ }
+diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
+index 4c305ba..594c44f 100644
+--- a/include/asm-arm/arch-s3c2410/hardware.h
++++ b/include/asm-arm/arch-s3c2410/hardware.h
+@@ -45,7 +45,7 @@ extern unsigned int s5p_gpio_getcfg(unsigned int pin);
+ * >=0 = interrupt number for the pin
+ */
+
+-//extern int s3c_gpio_getirq(unsigned int pin);
++extern int s3c_gpio_getirq(unsigned int pin);
+
+ /* s3c_gpio_irqfilter
+ *
+@@ -126,7 +126,7 @@ extern unsigned int s3c_gpio_getcfg(unsigned int pin);
+ * >=0 = interrupt number for the pin
+ */
+
+-//extern int s3c_gpio_getirq(unsigned int pin);
++extern int s3c_gpio_getirq(unsigned int pin);
+
+ /* s3c_gpio_irqfilter
+ *
+diff --git a/include/asm-arm/arch-s3c2410/hsmmc.h b/include/asm-arm/arch-s3c2410/hsmmc.h
+index 5700206..7abe2c0 100644
+--- a/include/asm-arm/arch-s3c2410/hsmmc.h
++++ b/include/asm-arm/arch-s3c2410/hsmmc.h
+@@ -36,8 +36,9 @@ struct s3c_hsmmc_cfg {
+
+ u8 highspeed; /* ENHIGHSPD bit configuration */
+
+- /* feedback delay control configuration (0: mmc, 1: sd) */
+- struct s3c_hsmmc_fd_cfg fd_ctrl[2];
++ u32 max_clock; /* MAX clock for this port */
++ /* feedback delay control configuration (0: mmc, 1: sd, 2:sdio) */
++ struct s3c_hsmmc_fd_cfg fd_ctrl[3];
+
+ /* clock source control */
+ struct s3c_hsmmc_clk_cfg clocks[NUM_OF_HSMMC_CLKSOURCES];
+diff --git a/include/asm-arm/arch-s3c2410/regs-s3c6410-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c6410-clock.h
+new file mode 100644
+index 0000000..5c79755
+--- /dev/null
++++ b/include/asm-arm/arch-s3c2410/regs-s3c6410-clock.h
+@@ -0,0 +1,262 @@
++/* linux/include/asm-arm/arch-s3c2410/regs-s3c6400-clock.h
++ *
++ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
++ * http://armlinux.simtec.co.uk/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * S3C6400 clock register definitions
++*/
++
++#ifndef __ASM_ARM_REGS_CLOCK
++#define __ASM_ARM_REGS_CLOCK "$Id: regs-s3c6410-clock.h,v 1.3 2008/04/10 05:53:03 ihlee215 Exp $"
++
++#define S3C_CLKREG(x) ((x) + S3C24XX_VA_SYSCON)
++
++#define S3C_PLLVAL(_m,_p,_s) ((_m) << 16 | ((_p) << 8) | ((_s)))
++
++#define S3C_APLL_LOCK S3C_CLKREG(0x00)
++#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
++#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
++#define S3C_APLL_CON S3C_CLKREG(0x0C)
++#define S3C_MPLL_CON S3C_CLKREG(0x10)
++#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
++#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
++#define S3C_CLK_SRC S3C_CLKREG(0x1C)
++#define S3C_CLK_SRC2 S3C_CLKREG(0x10C)
++#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
++#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
++#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
++#define S3C_CLK_OUT S3C_CLKREG(0x2C)
++#define S3C_HCLK_GATE S3C_CLKREG(0x30)
++#define S3C_PCLK_GATE S3C_CLKREG(0x34)
++#define S3C_SCLK_GATE S3C_CLKREG(0x38)
++#define S3C_AHB_CON0 S3C_CLKREG(0x100)
++#define S3C_AHB_CON1 S3C_CLKREG(0x104)
++#define S3C_AHB_CON2 S3C_CLKREG(0x108)
++#define S3C_SDMA_SEL S3C_CLKREG(0x110)
++#define S3C_SW_RST S3C_CLKREG(0x114)
++#define S3C_SYS_ID S3C_CLKREG(0x118)
++#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
++#define S3C_QOS_OVERRIDE0 S3C_CLKREG(0x124)
++#define S3C_QOS_OVERRIDE1 S3C_CLKREG(0x128)
++#define S3C_MEM_CFG_STAT S3C_CLKREG(0x12C)
++#define S3C_PWR_CFG S3C_CLKREG(0x804)
++#define S3C_EINT_MASK S3C_CLKREG(0x808)
++#define S3C_NORMAL_CFG S3C_CLKREG(0x810)
++#define S3C_STOP_CFG S3C_CLKREG(0x814)
++#define S3C_SLEEP_CFG S3C_CLKREG(0x818)
++#define S3C_OSC_FREQ S3C_CLKREG(0x820)
++#define S3C_OSC_STABLE S3C_CLKREG(0x824)
++#define S3C_PWR_STABLE S3C_CLKREG(0x828)
++#define S3C_FPC_STABLE S3C_CLKREG(0x82C)
++#define S3C_MTC_STABLE S3C_CLKREG(0x830)
++#define S3C_OTHERS S3C_CLKREG(0x900)
++#define S3C_RST_STAT S3C_CLKREG(0x904)
++#define S3C_WAKEUP_STAT S3C_CLKREG(0x908)
++#define S3C_BLK_PWR_STAT S3C_CLKREG(0x90C)
++#define S3C_INFORM0 S3C_CLKREG(0xA00)
++#define S3C_INFORM1 S3C_CLKREG(0xA04)
++#define S3C_INFORM2 S3C_CLKREG(0xA08)
++#define S3C_INFORM3 S3C_CLKREG(0xA0C)
++#define S3C_INFORM4 S3C_CLKREG(0xA10)
++#define S3C_INFORM5 S3C_CLKREG(0xA14)
++#define S3C_INFORM6 S3C_CLKREG(0xA18)
++#define S3C_INFORM7 S3C_CLKREG(0xA1C)
++
++/* Block power status register bit field */
++#define S3C_BLK_ETM (1<<6)
++#define S3C_BLK_S (1<<5)
++#define S3C_BLK_F (1<<4)
++#define S3C_BLK_P (1<<3)
++#define S3C_BLK_I (1<<2)
++#define S3C_BLK_V (1<<1)
++#define S3C_BLK_TOP (1<<0)
++
++/* Power gating registers */
++#define S3C_PWRGATE_IROM (1<<30)
++#define S3C_PWRGATE_DOMAIN_ETM (1<<16)
++#define S3C_PWRGATE_DOMAIN_S (1<<15)
++#define S3C_PWRGATE_DOMAIN_F (1<<14)
++#define S3C_PWRGATE_DOMAIN_P (1<<13)
++#define S3C_PWRGATE_DOMAIN_I (1<<12)
++#define S3C_PWRGATE_DOMAIN_V (1<<9)
++
++/* MTC stable registers */
++#define S3C_STABLE_DOMAIN_ETM (0xF<<24)
++#define S3C_STABLE_DOMAIN_S (0xF<<20)
++#define S3C_STABLE_DOMAIN_F (0xF<<16)
++#define S3C_STABLE_DOMAIN_P (0xF<<12)
++#define S3C_STABLE_DOMAIN_I (0xF<<8)
++#define S3C_STABLE_DOMAIN_V (0xF<<4)
++#define S3C_STABLE_DOMAIN_TOP (0xF<<0)
++
++/* HCLK GATE Registers */
++#define S3C_CLKCON_HCLK_3DSE (1<<31)
++#define S3C_CLKCON_HCLK_UHOST (1<<29)
++#define S3C_CLKCON_HCLK_SECUR (1<<28)
++#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
++#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
++#define S3C_CLKCON_HCLK_IROM (1<<25)
++#define S3C_CLKCON_HCLK_DDR1 (1<<24)
++#define S3C_CLKCON_HCLK_DDR0 (1<<23)
++#define S3C_CLKCON_HCLK_MEM1 (1<<22)
++#define S3C_CLKCON_HCLK_MEM0 (1<<21)
++#define S3C_CLKCON_HCLK_USB (1<<20)
++#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
++#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
++#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
++#define S3C_CLKCON_HCLK_MDP (1<<16)
++#define S3C_CLKCON_HCLK_DHOST (1<<15)
++#define S3C_CLKCON_HCLK_IHOST (1<<14)
++#define S3C_CLKCON_HCLK_DMA1 (1<<13)
++#define S3C_CLKCON_HCLK_DMA0 (1<<12)
++#define S3C_CLKCON_HCLK_JPEG (1<<11)
++#define S3C_CLKCON_HCLK_CAMIF (1<<10)
++#define S3C_CLKCON_HCLK_SCALER (1<<9)
++#define S3C_CLKCON_HCLK_2D (1<<8)
++#define S3C_CLKCON_HCLK_TV (1<<7)
++#define S3C_CLKCON_HCLK_POST0 (1<<5)
++#define S3C_CLKCON_HCLK_ROT (1<<4)
++#define S3C_CLKCON_HCLK_LCD (1<<3)
++#define S3C_CLKCON_HCLK_TZIC (1<<2)
++#define S3C_CLKCON_HCLK_INTC (1<<1)
++#define S3C_CLKCON_HCLK_MFC (1<<0)
++
++/* PCLK GATE Registers */
++#define S3C_CLKCON_PCLK_IIC1 (1<<27)
++#define S3C_CLKCON_PCLK_IIS2 (1<<26)
++#define S3C_CLKCON_PCLK_SKEY (1<<24)
++#define S3C_CLKCON_PCLK_CHIPID (1<<23)
++#define S3C_CLKCON_PCLK_SPI1 (1<<22)
++#define S3C_CLKCON_PCLK_SPI0 (1<<21)
++#define S3C_CLKCON_PCLK_HSIRX (1<<20)
++#define S3C_CLKCON_PCLK_HSITX (1<<19)
++#define S3C_CLKCON_PCLK_GPIO (1<<18)
++#define S3C_CLKCON_PCLK_IIC (1<<17)
++#define S3C_CLKCON_PCLK_IIS1 (1<<16)
++#define S3C_CLKCON_PCLK_IIS0 (1<<15)
++#define S3C_CLKCON_PCLK_AC97 (1<<14)
++#define S3C_CLKCON_PCLK_TZPC (1<<13)
++#define S3C_CLKCON_PCLK_TSADC (1<<12)
++#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
++#define S3C_CLKCON_PCLK_IRDA (1<<10)
++#define S3C_CLKCON_PCLK_PCM1 (1<<9)
++#define S3C_CLKCON_PCLK_PCM0 (1<<8)
++#define S3C_CLKCON_PCLK_PWM (1<<7)
++#define S3C_CLKCON_PCLK_RTC (1<<6)
++#define S3C_CLKCON_PCLK_WDT (1<<5)
++#define S3C_CLKCON_PCLK_UART3 (1<<4)
++#define S3C_CLKCON_PCLK_UART2 (1<<3)
++#define S3C_CLKCON_PCLK_UART1 (1<<2)
++#define S3C_CLKCON_PCLK_UART0 (1<<1)
++#define S3C_CLKCON_PCLK_MFC (1<<0)
++
++/* SCLK GATE Registers */
++#define S3C_CLKCON_SCLK_UHOST (1<<30)
++#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
++#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
++#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
++#define S3C_CLKCON_SCLK_MMC2 (1<<26)
++#define S3C_CLKCON_SCLK_MMC1 (1<<25)
++#define S3C_CLKCON_SCLK_MMC0 (1<<24)
++#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
++#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
++#define S3C_CLKCON_SCLK_SPI1 (1<<21)
++#define S3C_CLKCON_SCLK_SPI0 (1<<20)
++#define S3C_CLKCON_SCLK_DAC27 (1<<19)
++#define S3C_CLKCON_SCLK_TV27 (1<<18)
++#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
++#define S3C_CLKCON_SCLK_SCALER (1<<16)
++#define S3C_CLKCON_SCLK_LCD27 (1<<15)
++#define S3C_CLKCON_SCLK_LCD (1<<14)
++#define S3C_CLKCON_SCLK_FIMC (1<<13)
++#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
++#define S3C_CLKCON_SCLK_AUDIO2 (1<<11)
++#define S3C_CLKCON_SCLK_POST0 (1<<10)
++#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
++#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
++#define S3C_CLKCON_SCLK_SECUR (1<<7)
++#define S3C_CLKCON_SCLK_IRDA (1<<6)
++#define S3C_CLKCON_SCLK_UART (1<<5)
++#define S3C_CLKCON_SCLK_ONENAND (1<<4)
++#define S3C_CLKCON_SCLK_MFC (1<<3)
++#define S3C_CLKCON_SCLK_CAM (1<<2)
++#define S3C_CLKCON_SCLK_JPEG (1<<1)
++
++/*OTHERS Resgister */
++#define S3C_OTHERS_USB_SIG_MASK (1<<16)
++
++/*CLK SRC BITS*/
++#define S3C_CLKSRC_APLL_CLKSEL (1<<0)
++#define S3C_CLKSRC_MPLL_CLKSEL (1<<1)
++#define S3C_CLKSRC_EPLL_CLKSEL (1<<2)
++#define S3C_CLKSRC_UHOST_EPLL (1<<5)
++#define S3C_CLKSRC_UHOST_MASK (3<<5)
++#if 0
++#define S3C_CLKSRC_CAM_CLKSEL_HCLK (1<<9)
++#define S3C_CLKSRC_I2SDIV_CLKSRC (1<<10)
++#define S3C_CLKSRC_I2SCLK_CLKSEL (1<<11)
++#define S3C_CLKSRC_UARTDIV_CLKSRC (1<<12)
++#define S3C_CLKSRC_SPIDIV_CLKSRC (1<<13)
++#endif
++
++/*CLKDIV1 Reg bits */
++#define S3C_CLKDIV1_USBDIV2 (1<<20)
++
++#define S3C_CLKDIV1_HSMMCDIV2_MASK (0xf<<8)
++#define S3C_CLKDIV1_HSMMCDIV2_SHIFT (8)
++#define S3C_CLKDIV1_HSMMCDIV1_MASK (0xf<<4)
++#define S3C_CLKDIV1_HSMMCDIV1_SHIFT (4)
++#define S3C_CLKDIV1_HSMMCDIV0_MASK (0xf<<0)
++#define S3C_CLKDIV1_HSMMCDIV0_SHIFT (0)
++#define S3C_CLKDIV1_HSMMCDIV_MASK (0xfff<<0)
++#define S3C_CLKDIV1_HSMMCDIV_SHIFT (0)
++
++/*EPLL_CON0 Reg bits */
++#define S3C_EPLL_EN (1<<31)
++#define S3C_EPLLVAL(_m,_p,_s) ((_m) << 16 | ((_p) << 8) | ((_s)))
++
++
++
++#define S3C_CLKDIVN_APLL_MASK (0xF<<0)
++#define S3C_CLKDIVN_MPLL_MASK (0x1<<4)
++#define S3C_CLKDIVN_HCLK_MASK (0x1<<8)
++#define S3C_CLKDIVN_HCLKX2_MASK (0x7<<9)
++#define S3C_CLKDIVN_PCLK_MASK (0xF<<12)
++#define S3C_CLKDIVN_UHOST_MASK (0xF<<20)
++
++static inline unsigned int
++s3c6400_get_pll(unsigned long pllval, unsigned long baseclk)
++{
++ unsigned long mdiv, pdiv, sdiv;
++
++ /* To prevent overflow in calculation -JaeCheol Lee */
++ baseclk /= 1000;
++
++ mdiv = (pllval & (0x3ff << 16))>>16;
++ pdiv = (pllval & (0x3f << 8))>>8;
++ sdiv = (pllval & (0x03 << 0))>>0;
++ return (baseclk * (mdiv)) / ((pdiv) << sdiv)*1000;
++}
++
++static inline unsigned int
++s3c6400_get_epll(unsigned long baseclk)
++{
++ unsigned long pllval, mdiv, pdiv, sdiv, kdiv;
++
++ /* To prevent overflow in calculation -JaeCheol Lee */
++ baseclk /= 1000;
++
++ pllval = readl(S3C_EPLL_CON0);
++ mdiv = (pllval & (0x3ff << 16))>>16;
++ pdiv = (pllval & (0x3f << 8))>>8;
++ sdiv = (pllval & (0x03 << 0))>>0;
++ kdiv = readl(S3C_EPLL_CON1) & (0xffff);
++
++ return (baseclk * (mdiv+kdiv/65536) / (pdiv << sdiv))*1000;
++}
++
++#endif /* __ASM_ARM_REGS_CLOCK */
+diff --git a/include/asm-arm/arch-s3c2410/reserved_mem.h b/include/asm-arm/arch-s3c2410/reserved_mem.h
+index 4fa5611..ba921a4 100644
+--- a/include/asm-arm/arch-s3c2410/reserved_mem.h
++++ b/include/asm-arm/arch-s3c2410/reserved_mem.h
+@@ -17,7 +17,7 @@
+ //#define CONFIG_RESERVED_MEM_JPEG
+ //#define CONFIG_RESERVED_MEM_JPEG_POST
+ //#define CONFIG_RESERVED_MEM_MFC
+-//#define CONFIG_RESERVED_MEM_MFC_POST
++#define CONFIG_RESERVED_MEM_MFC_POST
+ //#define CONFIG_RESERVED_MEM_JPEG_MFC_POST
+ //#define CONFIG_RESERVED_MEM_JPEG_CAMERA
+ //#define CONFIG_RESERVED_MEM_JPEG_POST_CAMERA
+diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
+index 91a0d0c..f1c4430 100644
+--- a/include/asm-arm/arch-s3c2410/system.h
++++ b/include/asm-arm/arch-s3c2410/system.h
+@@ -89,6 +89,7 @@ arch_reset(char mode)
+ }
+ #else
+ #define S3C6400_SW_RESET_OFF 0x114
++extern int s3c2410wdt_reboot(void);
+ static void
+ arch_reset(char mode)
+ {
+@@ -101,7 +102,7 @@ arch_reset(char mode)
+
+ printk("arch_reset: attempting watchdog reset\n");
+
+- __raw_writel(0x6400, S3C24XX_VA_SYSCON + S3C6400_SW_RESET_OFF);
++ s3c2410wdt_reboot();
+
+ /* wait for reset to assert... */
+ mdelay(5000);
+diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
+index 5dc27eb..899cc73 100644
+--- a/include/asm-arm/plat-s3c24xx/devs.h
++++ b/include/asm-arm/plat-s3c24xx/devs.h
+@@ -75,4 +75,6 @@ extern struct platform_device s3c_device_smc911x;
+
+ #ifdef CONFIG_PLAT_S3C64XX
+ extern struct platform_device s3c_device_usb_otghcd;
++extern struct platform_device s3c_gpio;
+ #endif
++
+diff --git a/include/asm-arm/plat-s3c64xx/hhtech_gpio.h b/include/asm-arm/plat-s3c64xx/hhtech_gpio.h
+new file mode 100644
+index 0000000..8637e5e
+--- /dev/null
++++ b/include/asm-arm/plat-s3c64xx/hhtech_gpio.h
+@@ -0,0 +1,64 @@
++/****************************************************************
++ * $ID: hhtech_gpio.h 三, 18 2月 2009 10:16:56 +0800 wk $ *
++ * *
++ * Description: *
++ * *
++ * Maintainer: wk@hhcn.com *
++ * *
++ * CopyRight (c) 2009 HHTech *
++ * www.hhcn.com, www.hhcn.org *
++ * All rights reserved. *
++ * *
++ * This file is free software; *
++ * you are free to modify and/or redistribute it *
++ * under the terms of the GNU General Public Licence (GPL). *
++ * *
++ * Last modified: Fri, 24 Apr 2009 09:25:41 +0800 by root #
++ ****************************************************************/
++
++
++/*======================================================================
++ * GPIO
++ */
++
++//SD
++#define GPIO_SD_WP S3C_GPK0 /* GPK0 ,SD write protect detect,*/
++
++//USB
++#define GPIO_USB_EN S3C_GPL0 /* GPL0 USB Improving voltage Enable, 1:open 0:off */
++#define GPIO_USB_HOSTPWR_EN S3C_GPL1 /* GPL1 1:5V on 0:5Voff */
++#define GPIO_USB_HOST_STATUS S3C_GPL10 /* GPL10 USB protect status ,0:error*/
++#define GPIO_USB_OTG_STATUS S3C_GPL11 /* GPL11 USB otg Over-current protection status ,0:error*/
++#define GPIO_USB_OTGDRV_EN S3C_GPL8 /* GPL0 USB otg drv Enable, 1:open 0:off */
++
++//Headphone Sperker
++#define GPIO_HEADPHONE_S S3C_GPL12 /* GPL12 headphone audio detect,0:insert */
++#define GPIO_SPEAKER_EN S3C_GPK12 /* GPK12 Speaker 0:off 1:open */
++
++//Backlight
++#define GPIO_LCD_BLIGHT_EN S3C_GPM3 /* GPM3,MP1530 LCD backlight,1:enable 0:off */
++#define GPIO_LCD_BLIGHT_S S3C_GPM4 /* GPM4,MP1530 status */
++
++//Charging
++#define GPIO_DC_DETE S3C_GPL13 /* GPL13 DC insert Detect */
++#define GPIO_CHARG_S1 S3C_GPK4 /* GPK4 ,Charging status 1,*/
++#define GPIO_CHARG_S2 S3C_GPK5 /* GPK5 ,Charging status 2,*/
++#define GPIO_CHARGER_EN S3C_GPK6 /* GPK6 DC 0:200ma 1:860ma */
++
++// System Power
++#define GPIO_PWR_EN S3C_GPK15 /* GPK15 System power control 0:off 1:open */
++#define GPIO_PWR_HOLD S3C_GPL14 /* GPL14 System power hold over 5 second time,pull up GPK15 */
++
++//Vidoe amplifier
++#define GPIO_VIDEOAMP_EN S3C_GPK13 /* GPK13,Vidoe amplifier output control,0:off*/
++
++#define GPIO_WIFI_EN S3C_GPK1 /* Wifi switch*/
++#define GPIO_WIFI_RESET S3C_GPK2 /* Wifi reset*/
++
++#if defined(CONFIG_LCD_4)
++#define GPIO_LED1_EN S3C_GPN8
++#define GPIO_LED2_EN S3C_GPN9
++#else
++#define GPIO_LED1_EN S3C_GPN9
++#define GPIO_LED2_EN S3C_GPN8
++#endif
+diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
+index bd6be9d..f4ab34f 100644
+--- a/include/asm-arm/vfp.h
++++ b/include/asm-arm/vfp.h
+@@ -1,5 +1,5 @@
+ /*
+- * linux/include/asm-arm/vfp.h
++ * arch/arm/include/asm/vfp.h
+ *
+ * VFP register definitions.
+ * First, the standard VFP set.
+@@ -7,7 +7,11 @@
+
+ #define FPSID cr0
+ #define FPSCR cr1
++#define MVFR1 cr6
++#define MVFR0 cr7
+ #define FPEXC cr8
++#define FPINST cr9
++#define FPINST2 cr10
+
+ /* FPSID bits */
+ #define FPSID_IMPLEMENTER_BIT (24)
+@@ -28,6 +32,19 @@
+ /* FPEXC bits */
+ #define FPEXC_EX (1 << 31)
+ #define FPEXC_EN (1 << 30)
++#define FPEXC_DEX (1 << 29)
++#define FPEXC_FP2V (1 << 28)
++#define FPEXC_VV (1 << 27)
++#define FPEXC_TFV (1 << 26)
++#define FPEXC_LENGTH_BIT (8)
++#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
++#define FPEXC_IDF (1 << 7)
++#define FPEXC_IXF (1 << 4)
++#define FPEXC_UFF (1 << 3)
++#define FPEXC_OFF (1 << 2)
++#define FPEXC_DZF (1 << 1)
++#define FPEXC_IOF (1 << 0)
++#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
+
+ /* FPSCR bits */
+ #define FPSCR_DEFAULT_NAN (1<<25)
+@@ -55,20 +72,9 @@
+ #define FPSCR_IXC (1<<4)
+ #define FPSCR_IDC (1<<7)
+
+-/*
+- * VFP9-S specific.
+- */
+-#define FPINST cr9
+-#define FPINST2 cr10
+-
+-/* FPEXC bits */
+-#define FPEXC_FPV2 (1<<28)
+-#define FPEXC_LENGTH_BIT (8)
+-#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
+-#define FPEXC_INV (1 << 7)
+-#define FPEXC_UFC (1 << 3)
+-#define FPEXC_OFC (1 << 2)
+-#define FPEXC_IOC (1 << 0)
++/* MVFR0 bits */
++#define MVFR0_A_SIMD_BIT (0)
++#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
+
+ /* Bit patterns for decoding the packaged operation descriptors */
+ #define VFPOPDESC_LENGTH_BIT (9)
+diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h
+index 27fe028..422f3cc 100644
+--- a/include/asm-arm/vfpmacros.h
++++ b/include/asm-arm/vfpmacros.h
+@@ -1,5 +1,5 @@
+ /*
+- * linux/include/asm-arm/vfpmacros.h
++ * arch/arm/include/asm/vfpmacros.h
+ *
+ * Assembler-only file containing VFP macros and register definitions.
+ */
+@@ -15,19 +15,33 @@
+ .endm
+
+ @ read all the working registers back into the VFP
+- .macro VFPFLDMIA, base
++ .macro VFPFLDMIA, base, tmp
+ #if __LINUX_ARM_ARCH__ < 6
+ LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
+ #else
+ LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
+ #endif
++#ifdef CONFIG_VFPv3
++ VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
++ and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
++ cmp \tmp, #2 @ 32 x 64bit registers?
++ ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
++ addne \base, \base, #32*4 @ step over unused register space
++#endif
+ .endm
+
+ @ write all the working registers out of the VFP
+- .macro VFPFSTMIA, base
++ .macro VFPFSTMIA, base, tmp
+ #if __LINUX_ARM_ARCH__ < 6
+ STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
+ #else
+ STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
+ #endif
++#ifdef CONFIG_VFPv3
++ VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
++ and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
++ cmp \tmp, #2 @ 32 x 64bit registers?
++ stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
++ addne \base, \base, #32*4 @ step over unused register space
++#endif
+ .endm
+diff --git a/include/linux/aufs_type.h b/include/linux/aufs_type.h
+new file mode 100644
+index 0000000..cee8d68
+--- /dev/null
++++ b/include/linux/aufs_type.h
+@@ -0,0 +1,127 @@
++/*
++ * Copyright (C) 2005-2009 Junjiro Okajima
++ *
++ * This program, aufs is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++/* $Id: aufs_type.h,v 1.134 2009/01/26 06:24:45 sfjro Exp $ */
++
++#include <linux/ioctl.h>
++
++#ifndef __AUFS_TYPE_H__
++#define __AUFS_TYPE_H__
++
++#define AUFS_VERSION "20090126"
++
++/* move this to linux-2.6.19/include/magic.h */
++#define AUFS_SUPER_MAGIC ('a' << 24 | 'u' << 16 | 'f' << 8 | 's')
++
++/* ---------------------------------------------------------------------- */
++
++#ifdef CONFIG_AUFS_BRANCH_MAX_127
++/* some environments treat 'char' as 'unsigned char' by default */
++typedef signed char aufs_bindex_t;
++#define AUFS_BRANCH_MAX 127
++#else
++typedef short aufs_bindex_t;
++#ifdef CONFIG_AUFS_BRANCH_MAX_511
++#define AUFS_BRANCH_MAX 511
++#elif defined(CONFIG_AUFS_BRANCH_MAX_1023)
++#define AUFS_BRANCH_MAX 1023
++#elif defined(CONFIG_AUFS_BRANCH_MAX_32767)
++#define AUFS_BRANCH_MAX 32767
++#else
++#error unknown CONFIG_AUFS_BRANCH_MAX value
++#endif
++#endif
++
++#define AUFS_NAME "aufs"
++#define AUFS_FSTYPE AUFS_NAME
++
++#define AUFS_ROOT_INO 2
++#define AUFS_FIRST_INO 11
++
++#define AUFS_WH_PFX ".wh."
++#define AUFS_WH_PFX_LEN ((int)sizeof(AUFS_WH_PFX) - 1)
++#define AUFS_XINO_FNAME "." AUFS_NAME ".xino"
++#define AUFS_XINO_DEFPATH "/tmp/" AUFS_XINO_FNAME
++#define AUFS_XINO_TRUNC_INIT 64 /* blocks */
++#define AUFS_XINO_TRUNC_STEP 4 /* blocks */
++#define AUFS_DIRWH_DEF 3
++#define AUFS_RDCACHE_DEF 10 /* seconds */
++#define AUFS_WKQ_NAME AUFS_NAME "d"
++#define AUFS_NWKQ_DEF 4
++#define AUFS_MFS_SECOND_DEF 30 /* seconds */
++#define AUFS_PLINK_WARN 100 /* number of plinks */
++
++#ifdef CONFIG_AUFS_COMPAT
++#define AUFS_DIROPQ_NAME "__dir_opaque"
++#else
++#define AUFS_DIROPQ_NAME AUFS_WH_PFX ".opq" /* whiteouted doubly */
++#endif
++#define AUFS_WH_DIROPQ AUFS_WH_PFX AUFS_DIROPQ_NAME
++
++#define AUFS_BASE_NAME AUFS_WH_PFX AUFS_NAME
++#define AUFS_PLINKDIR_NAME AUFS_WH_PFX "plnk"
++#define AUFS_TMPDIR_NAME AUFS_WH_PFX ".tmp"
++
++/* doubly whiteouted */
++#define AUFS_WH_BASE AUFS_WH_PFX AUFS_BASE_NAME
++#define AUFS_WH_PLINKDIR AUFS_WH_PFX AUFS_PLINKDIR_NAME
++#define AUFS_WH_TMPDIR AUFS_WH_PFX AUFS_TMPDIR_NAME
++
++/* ---------------------------------------------------------------------- */
++
++/* ioctl */
++#if 0 /* reserved for future use */
++enum {
++ AuCtlErr,
++ AuCtlErr_Last
++};
++enum {
++ AuCtl_DIROPQ_GET, AuCtl_DIROPQ_SET,
++ AuCtl_MOVE,
++ AuCtl_MVDOWN,
++
++ /* unimplmented */
++ AuCtl_REFRESH, AuCtl_REFRESHV,
++ AuCtl_FLUSH_PLINK,
++ AuCtl_CPUP,
++ AuCtl_CPDOWN
++};
++
++struct aufs_ctl {
++ int err;
++ aufs_bindex_t bsrc, bdst;
++ char *path;
++};
++
++#define AuCtlType 'A'
++#define AUFS_CTL_DIROPQ_GET _IO(AuCtlType, AuCtl_DIROPQ_GET)
++#define AUFS_CTL_DIROPQ_SET _IOW(AuCtlType, AuCtl_DIROPQ_SET, aufs_bindex_t)
++#define AUFS_CTL_MOVE \
++ _IOW(AuCtlType, AuCtl_MVDOWN, aufs_bindex_t)
++#define AUFS_CTL_MVDOWN \
++ _IOWR(AuCtlType, AuCtl_MVDOWN, struct aufs_ctl)
++
++#define AUFS_CTL_REFRESH _IO(AuCtlType, AuCtl_REFRESH)
++#define AUFS_CTL_REFRESHV _IO(AuCtlType, AuCtl_REFRESHV)
++#define AUFS_CTL_FLUSH_PLINK _IOR(AuCtlType, AuCtl_FLUSH_PLINK)
++#define AUFS_CTL_CPUP _IOWR(AuCtlType, AuCtl_CPUP, struct aufs_ctl)
++#define AUFS_CTL_CPDOWN \
++ _IOWR(AuCtlType, AuCtl_CPDOWN, struct aufs_ctl_cp)
++#endif
++
++#endif /* __AUFS_TYPE_H__ */
+diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h
+index c6d3a9d..1289fa7 100644
+--- a/include/linux/gpio_keys.h
++++ b/include/linux/gpio_keys.h
+@@ -9,11 +9,13 @@ struct gpio_keys_button {
+ char *desc;
+ int type; /* input event type (EV_KEY, EV_SW) */
+ int wakeup; /* configure the button as a wake-up source */
++ int debounce_interval; /* debounce ticks interval in msecs */
+ };
+
+ struct gpio_keys_platform_data {
+ struct gpio_keys_button *buttons;
+ int nbuttons;
++ unsigned int rep:1; /* enable input subsystem auto repeat */
+ };
+
+ #endif
+diff --git a/kernel/power/main.c b/kernel/power/main.c
+index f71c950..8237545 100644
+--- a/kernel/power/main.c
++++ b/kernel/power/main.c
+@@ -21,6 +21,9 @@
+ #include <linux/freezer.h>
+ #include <linux/vmstat.h>
+ #include <linux/syscalls.h>
++#include <asm/gpio.h>
++#include <asm/arch/gpio.h>
++#include <asm/plat-s3c64xx/hhtech_gpio.h>
+
+ #include "power.h"
+
+@@ -217,7 +220,6 @@ static inline int valid_state(suspend_state_t state)
+ return 1;
+ }
+
+-
+ /**
+ * enter_state - Do common work of entering low-power state.
+ * @state: pm_state structure for state we're entering.
+@@ -231,6 +233,8 @@ static inline int valid_state(suspend_state_t state)
+ static int enter_state(suspend_state_t state)
+ {
+ int error;
++ int usb_otgdrv_en = 0;
++ int dc_status;
+
+ if (!valid_state(state))
+ return -ENODEV;
+@@ -238,6 +242,36 @@ static int enter_state(suspend_state_t state)
+ if (!mutex_trylock(&pm_mutex))
+ return -EBUSY;
+
++#if defined (CONFIG_LCD_4)
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 1 : 0;
++#else
++ dc_status = gpio_get_value(GPIO_DC_DETE) ? 0 : 1;
++#endif
++
++ if(0 == dc_status) {
++ extern int current_battery;
++ extern unsigned long rtc_wakeup_time;
++
++ if(current_battery > 905) // battery volume > 3.8 v
++ rtc_wakeup_time = 2 * 60 * 60; // 2 hours
++ else if(current_battery > 881) // battery volume > 3.7 v
++ rtc_wakeup_time = 60 * 60; // 1 hours
++ else if(current_battery > 858) // battery volume > 3.6 v
++ rtc_wakeup_time = 30 * 60; // 30 mins
++ else if(current_battery > 846) // battery volume > 3.55 v
++ rtc_wakeup_time = 15 * 60; // 15 mins
++ else if(current_battery > 834) // battery volume > 3.5 v
++ rtc_wakeup_time = 5 * 60; // 5 mins
++ else // battery volume <= 3.5 v
++ rtc_wakeup_time = 60; // 1 mins
++ printk("--->enter_state: rtc_wakeup_time = %ld\n", rtc_wakeup_time);
++ }
++
++ if(gpio_get_value(S3C_GPL8)) {
++ usb_otgdrv_en = 1;
++ gpio_set_value(S3C_GPL8, 0); // close the USB_OTGDRV_EN
++ }
++
+ printk("Syncing filesystems ... ");
+ sys_sync();
+ printk("done.\n");
+@@ -249,6 +283,8 @@ static int enter_state(suspend_state_t state)
+ pr_debug("PM: Entering %s sleep\n", pm_states[state]);
+ error = suspend_devices_and_enter(state);
+
++ if(usb_otgdrv_en)
++ gpio_set_value(S3C_GPL8, 1); // open the USB_OTGDRV_EN
+ pr_debug("PM: Finishing wakeup.\n");
+ suspend_finish();
+ Unlock:
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 7be7510..b5193d8 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -17,7 +17,11 @@ config SND_SOC_WM8750
+ config SND_SOC_WM8753
+ tristate
+ depends on SND_SOC
+-
++
++config SND_SOC_WM8987
++ tristate
++ depends on SND_SOC
++
+ config SND_SOC_WM8990
+ tristate
+ depends on SND_SOC
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index ca67a02..7559d55 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -14,6 +14,7 @@ snd-soc-wm8974-objs := wm8974.o
+ snd-soc-wm8976-objs := wm8976.o
+ snd-soc-wm8978-objs := wm8978.o
+ snd-soc-wm8980-objs := wm8980.o
++snd-soc-wm8987-objs := wm8987.o
+ snd-soc-wm8990-objs := wm8990.o
+ snd-soc-wm8991-objs := wm8991.o
+ snd-soc-wm9713-objs := wm9713.o
+@@ -35,6 +36,7 @@ obj-$(CONFIG_SND_SOC_WM8974) += snd-soc-wm8974.o
+ obj-$(CONFIG_SND_SOC_WM8976) += snd-soc-wm8976.o
+ obj-$(CONFIG_SND_SOC_WM8978) += snd-soc-wm8978.o
+ obj-$(CONFIG_SND_SOC_WM8980) += snd-soc-wm8980.o
++obj-$(CONFIG_SND_SOC_WM8987) += snd-soc-wm8987.o
+ obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
+ obj-$(CONFIG_SND_SOC_WM8991) += snd-soc-wm8991.o
+ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
+diff --git a/sound/soc/codecs/wm8987.c b/sound/soc/codecs/wm8987.c
+new file mode 100644
+index 0000000..43028ff
+--- /dev/null
++++ b/sound/soc/codecs/wm8987.c
+@@ -0,0 +1,1330 @@
++/*
++ * wm8987.c -- WM8987 ALSA SoC audio driver
++ *
++ * Copyright 2005 Openedhand Ltd.
++ *
++ * Author: Richard Purdie <richard@openedhand.com>
++ *
++ * Based on WM8987.c
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/initval.h>
++
++#ifdef CONFIG_HHBF_FAST_REBOOT
++#include <asm/reboot.h>
++#endif
++
++#include "wm8987.h"
++
++#define AUDIO_NAME "WM8987"
++#define WM8987_VERSION "v0.12"
++
++#include <asm/gpio.h>
++#include <asm/io.h>
++static int volume;
++static struct snd_soc_codec *p_codec = NULL;
++/*
++ * Debug
++ */
++
++//#define WM8987_DEBUG 1
++
++#ifdef WM8987_DEBUG
++#define dbg(format, arg...) \
++ printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg)
++#else
++#define dbg(format, arg...) do {} while (0)
++#endif
++#define err(format, arg...) \
++ printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
++#define info(format, arg...) \
++ printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
++#define warn(format, arg...) \
++ printk(KERN_WARNING AUDIO_NAME ": " format "\n" , ## arg)
++
++/* codec private data */
++#ifndef CONFIG_HHTECH_MINIPMP
++struct wm8987_priv {
++ unsigned int sysclk;
++};
++#else
++static unsigned wm8987_sysclk;
++
++void (*hhbf_audio_switch)(int flag) = NULL;
++EXPORT_SYMBOL(hhbf_audio_switch);
++static unsigned short init_reboot = 0;
++#endif//CONFIG_HHTECH_MINIPMP
++
++/*
++ * wm8987 register cache
++ * We can't read the WM8987 register space when we
++ * are using 2 wire for device control, so we cache them instead.
++ */
++static const u16 wm8987_reg[] = {
++ 0x00b7, 0x0097, 0x0000, 0x0000, /* 0 */
++ 0x0000, 0x0008, 0x0000, 0x002a, /* 4 */
++ 0x0000, 0x0000, 0x007F, 0x007F, /* 8 */
++ 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
++ 0x0080, 0x007b, 0x0000, 0x0032, /* 16 */
++ 0x0000, 0x00E0, 0x00E0, 0x00c0, /* 20 */
++ 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
++ 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
++ 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
++ 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
++ 0x0000, 0x0000, 0x0079, /* 40 */
++};
++
++/*
++ * read wm8987 register cache
++ */
++static inline unsigned int wm8987_read_reg_cache(struct snd_soc_codec *codec,
++ unsigned int reg)
++{
++ u16 *cache = codec->reg_cache;
++#ifndef CONFIG_HHTECH_MINIPMP
++ if (reg > WM8987_CACHE_REGNUM)
++#else// mhfan
++ if (reg > ARRAY_SIZE(wm8987_reg))
++#endif//CONFIG_HHTECH_MINIPMP
++ return -1;
++ return cache[reg];
++}
++
++/*
++ * write wm8987 register cache
++ */
++static inline void wm8987_write_reg_cache(struct snd_soc_codec *codec,
++ unsigned int reg, unsigned int value)
++{
++ u16 *cache = codec->reg_cache;
++#ifndef CONFIG_HHTECH_MINIPMP
++ if (reg > WM8987_CACHE_REGNUM)
++#else// mhfan
++ if (reg > ARRAY_SIZE(wm8987_reg))
++#endif//CONFIG_HHTECH_MINIPMP
++ return;
++ cache[reg] = value;
++}
++
++#if 0//def CONFIG_HHTECH_MINIPMP
++static int playtvo = 0;
++#endif//CONFIG_HHTECH_MINIPMP
++
++static int wm8987_write(struct snd_soc_codec *codec, unsigned int reg,
++ unsigned int value)
++{
++ u8 data[2];
++ int pin_level = gpio_get_value(S3C_GPL12);
++
++#if 0 //def CONFIG_SND_SOC_WM8987
++ if((10 == reg || 11 == reg) && value == 0x1C2) value = 0x1C4;
++ if((40 == reg || 41 == reg) && value == 0x1C2) value = 0x1C4;
++#endif
++
++#if 0 /* comment by whg HHTECH */
++#if( !defined(CONFIG_HHBF_I2C_MCU) || (defined(CONFIG_SND_SOC_WM8987)))
++ if (WM8987_PWR2 == reg) { // XXX: FIXME
++ u16 tmp, *cache = codec->reg_cache;
++ if (reg > ARRAY_SIZE(wm8987_reg)) return -EIO;
++ else tmp = cache[reg];
++ #ifdef CONFIG_SND_SOC_WM8987
++ if ( (value & 0x100) && !(tmp & 0x100)) value |= 0x198;
++ if (!(value & 0x080) && (tmp & 0x080)) value &= ~0x198;
++ if ( (value & 0x010) && !(tmp & 0x010)) value |= 0x198;
++ if (!(value & 0x008) && (tmp & 0x008)) value &= ~0x198;
++ if( value == tmp) return 0;
++ #else
++ if ( (value & 0x100) && !(tmp & 0x100)) value |= 0x180;
++ if (!(value & 0x100) && (tmp & 0x100)) value &= ~0x180;
++ if ( (value & 0x040) && !(tmp & 0x040)) value |= 0x07a;
++ if (!(value & 0x040) && (tmp & 0x040)) value &= ~0x07a;
++ if ( (value & ~0x1a) == (tmp & ~0x1a)) return 0;
++ #endif
++ value = 0x198;
++ }
++#endif//CONFIG_HHBF_I2C_MCU
++#endif /* comment by WangGang */
++
++ /* data is
++ * D15..D9 WM8987 register offset
++ * D8...D0 register data
++ */
++ data[0] = (reg << 1) | ((value >> 8) & 0x0001);
++ data[1] = value & 0x00ff;
++
++////////////////////// HHTECH wk ////////////////
++ volume = wm8987_read_reg_cache(codec, WM8987_LDAC);
++ if ((!pin_level)&& (reg==0xa || reg==0xb)){
++ data[1] = (data[1] * 95 /100) & 0x00ff; //0x1be:70% 0x1e8:91% 0x1d9:85% 0x1c9:79%
++ }
++////////////////////// HHTECH wk ////////////////
++#ifdef WM8987_DEBUG
++ if (value == wm8987_read_reg_cache(codec, reg)) return 0;
++
++ printk(KERN_INFO AUDIO_NAME ": 0x%02x%02x, R%02d <= 0x%03x\n",
++ data[0], data[1], reg, value);
++#endif//WM8987_DEBUG
++
++ wm8987_write_reg_cache (codec, reg, value);
++
++#ifdef CONFIG_HHTECH_MINIPMP
++ if (init_reboot) return 0;
++#endif//CONFIG_HHTECH_MINIPMP
++
++ if (codec->hw_write(codec->control_data, data, 2) == 2)
++ return 0;
++ else
++ return -EIO;
++}
++
++#define wm8987_reset(c) wm8987_write(c, WM8987_RESET, 0)
++
++/*
++ * WM8987 Controls
++ */
++static const char *wm8987_bass[] = {"Linear Control", "Adaptive Boost"};
++static const char *wm8987_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
++static const char *wm8987_treble[] = {"8kHz", "4kHz"};
++static const char *wm8987_3d_lc[] = {"200Hz", "500Hz"};
++static const char *wm8987_3d_uc[] = {"2.2kHz", "1.5kHz"};
++static const char *wm8987_3d_func[] = {"Capture", "Playback"};
++static const char *wm8987_alc_func[] = {"Off", "Right", "Left", "Stereo"};
++static const char *wm8987_ng_type[] = {"Constant PGA Gain",
++ "Mute ADC Output"};
++static const char *wm8987_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
++ "Differential"};
++static const char *wm8987_pga_sel[] = {"Line 1", "Line 2", "Line 3",
++ "Differential"};
++static const char *wm8987_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
++ "ROUT1"};
++static const char *wm8987_diff_sel[] = {"Line 1", "Line 2"};
++static const char *wm8987_adcpol[] = {"Normal", "L Invert", "R Invert",
++ "L + R Invert"};
++static const char *wm8987_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
++static const char *wm8987_mono_mux[] = {"Stereo", "Mono (Left)",
++ "Mono (Right)", "Digital Mono"};
++
++static const struct soc_enum wm8987_enum[] = {
++SOC_ENUM_SINGLE(WM8987_BASS, 7, 2, wm8987_bass),
++SOC_ENUM_SINGLE(WM8987_BASS, 6, 2, wm8987_bass_filter),
++SOC_ENUM_SINGLE(WM8987_TREBLE, 6, 2, wm8987_treble),
++SOC_ENUM_SINGLE(WM8987_3D, 5, 2, wm8987_3d_lc),
++SOC_ENUM_SINGLE(WM8987_3D, 6, 2, wm8987_3d_uc),
++SOC_ENUM_SINGLE(WM8987_3D, 7, 2, wm8987_3d_func),
++SOC_ENUM_SINGLE(WM8987_ALC1, 7, 4, wm8987_alc_func),
++SOC_ENUM_SINGLE(WM8987_NGATE, 1, 2, wm8987_ng_type),
++SOC_ENUM_SINGLE(WM8987_LOUTM1, 0, 5, wm8987_line_mux),
++SOC_ENUM_SINGLE(WM8987_ROUTM1, 0, 5, wm8987_line_mux),
++SOC_ENUM_SINGLE(WM8987_LADCIN, 6, 4, wm8987_pga_sel), /* 10 */
++SOC_ENUM_SINGLE(WM8987_RADCIN, 6, 4, wm8987_pga_sel),
++SOC_ENUM_SINGLE(WM8987_ADCTL2, 7, 4, wm8987_out3),
++SOC_ENUM_SINGLE(WM8987_ADCIN, 8, 2, wm8987_diff_sel),
++SOC_ENUM_SINGLE(WM8987_ADCDAC, 5, 4, wm8987_adcpol),
++SOC_ENUM_SINGLE(WM8987_ADCDAC, 1, 4, wm8987_deemph),
++SOC_ENUM_SINGLE(WM8987_ADCIN, 6, 4, wm8987_mono_mux), /* 16 */
++
++};
++
++static const struct snd_kcontrol_new wm8987_snd_controls[] = {
++
++SOC_DOUBLE_R("Capture Volume", WM8987_LINVOL, WM8987_RINVOL, 0, 63, 0),
++SOC_DOUBLE_R("Capture ZC Switch", WM8987_LINVOL, WM8987_RINVOL, 6, 1, 0),
++SOC_DOUBLE_R("Capture Switch", WM8987_LINVOL, WM8987_RINVOL, 7, 1, 1),
++
++#ifndef CONFIG_HHTECH_MINIPMP
++SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8987_LOUT1V,
++ WM8987_ROUT1V, 7, 1, 0),
++#endif
++SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8987_LOUT2V,
++ WM8987_ROUT2V, 7, 1, 0),
++
++SOC_ENUM("Playback De-emphasis", wm8987_enum[15]),
++
++SOC_ENUM("Capture Polarity", wm8987_enum[14]),
++SOC_SINGLE("Playback 6dB Attenuate", WM8987_ADCDAC, 7, 1, 0),
++SOC_SINGLE("Capture 6dB Attenuate", WM8987_ADCDAC, 8, 1, 0),
++
++#ifndef CONFIG_HHTECH_MINIPMP
++SOC_DOUBLE_R("PCM Volume", WM8987_LDAC, WM8987_RDAC, 0, 255, 0),
++#else// mhfan, XXX:
++SOC_DOUBLE_R("Master Playback Volume", WM8987_LDAC, WM8987_RDAC, 0, 255, 0),
++#endif//CONFIG_HHTECH_MINIPMP
++
++SOC_ENUM("Bass Boost", wm8987_enum[0]),
++SOC_ENUM("Bass Filter", wm8987_enum[1]),
++SOC_SINGLE("Bass Volume", WM8987_BASS, 0, 15, 1),
++
++SOC_SINGLE("Treble Volume", WM8987_TREBLE, 0, 15, 0),
++SOC_ENUM("Treble Cut-off", wm8987_enum[2]),
++
++SOC_SINGLE("3D Switch", WM8987_3D, 0, 1, 0),
++SOC_SINGLE("3D Volume", WM8987_3D, 1, 15, 0),
++SOC_ENUM("3D Lower Cut-off", wm8987_enum[3]),
++SOC_ENUM("3D Upper Cut-off", wm8987_enum[4]),
++SOC_ENUM("3D Mode", wm8987_enum[5]),
++
++SOC_SINGLE("ALC Capture Target Volume", WM8987_ALC1, 0, 7, 0),
++SOC_SINGLE("ALC Capture Max Volume", WM8987_ALC1, 4, 7, 0),
++SOC_ENUM("ALC Capture Function", wm8987_enum[6]),
++SOC_SINGLE("ALC Capture ZC Switch", WM8987_ALC2, 7, 1, 0),
++SOC_SINGLE("ALC Capture Hold Time", WM8987_ALC2, 0, 15, 0),
++SOC_SINGLE("ALC Capture Decay Time", WM8987_ALC3, 4, 15, 0),
++SOC_SINGLE("ALC Capture Attack Time", WM8987_ALC3, 0, 15, 0),
++SOC_SINGLE("ALC Capture NG Threshold", WM8987_NGATE, 3, 31, 0),
++SOC_ENUM("ALC Capture NG Type", wm8987_enum[4]),
++SOC_SINGLE("ALC Capture NG Switch", WM8987_NGATE, 0, 1, 0),
++
++SOC_SINGLE("Left ADC Capture Volume", WM8987_LADC, 0, 255, 0),
++SOC_SINGLE("Right ADC Capture Volume", WM8987_RADC, 0, 255, 0),
++
++SOC_SINGLE("ZC Timeout Switch", WM8987_ADCTL1, 0, 1, 0),
++SOC_SINGLE("Playback Invert Switch", WM8987_ADCTL1, 1, 1, 0),
++
++SOC_SINGLE("Right Speaker Playback Invert Switch", WM8987_ADCTL2, 4, 1, 0),
++
++/* Unimplemented */
++/* ADCDAC Bit 0 - ADCHPD */
++/* ADCDAC Bit 4 - HPOR */
++/* ADCTL1 Bit 2,3 - DATSEL */
++/* ADCTL1 Bit 4,5 - DMONOMIX */
++/* ADCTL1 Bit 6,7 - VSEL */
++/* ADCTL2 Bit 2 - LRCM */
++/* ADCTL2 Bit 3 - TRI */
++/* ADCTL3 Bit 5 - HPFLREN */
++/* ADCTL3 Bit 6 - VROI */
++/* ADCTL3 Bit 7,8 - ADCLRM */
++/* ADCIN Bit 4 - LDCM */
++/* ADCIN Bit 5 - RDCM */
++
++SOC_DOUBLE_R("Mic Boost", WM8987_LADCIN, WM8987_RADCIN, 4, 3, 0),
++
++SOC_DOUBLE_R("Bypass Left Playback Volume", WM8987_LOUTM1,
++ WM8987_LOUTM2, 4, 7, 1),
++SOC_DOUBLE_R("Bypass Right Playback Volume", WM8987_ROUTM1,
++ WM8987_ROUTM2, 4, 7, 1),
++SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8987_MOUTM1,
++ WM8987_MOUTM2, 4, 7, 1),
++
++SOC_SINGLE("Mono Playback ZC Switch", WM8987_MOUTV, 7, 1, 0),
++
++#ifndef CONFIG_HHTECH_MINIPMP
++SOC_DOUBLE_R("Headphone Playback Volume", WM8987_LOUT1V, WM8987_ROUT1V,
++ 0, 127, 0),
++#endif
++SOC_DOUBLE_R("Speaker Playback Volume", WM8987_LOUT2V, WM8987_ROUT2V,
++ 0, 127, 0),
++
++SOC_SINGLE("Mono Playback Volume", WM8987_MOUTV, 0, 127, 0),
++
++};
++
++/* add non dapm controls */
++static int wm8987_add_controls(struct snd_soc_codec *codec)
++{
++ int err, i;
++
++ for (i = 0; i < ARRAY_SIZE(wm8987_snd_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm8987_snd_controls[i],codec, NULL));
++ if (err < 0)
++ return err;
++ }
++ return 0;
++}
++
++/*
++ * DAPM Controls
++ */
++
++/* Left Mixer */
++static const struct snd_kcontrol_new wm8987_left_mixer_controls[] = {
++SOC_DAPM_SINGLE("Playback Switch", WM8987_LOUTM1, 8, 1, 0),
++SOC_DAPM_SINGLE("Left Bypass Switch", WM8987_LOUTM1, 7, 1, 0),
++SOC_DAPM_SINGLE("Right Playback Switch", WM8987_LOUTM2, 8, 1, 0),
++SOC_DAPM_SINGLE("Right Bypass Switch", WM8987_LOUTM2, 7, 1, 0),
++};
++
++/* Right Mixer */
++static const struct snd_kcontrol_new wm8987_right_mixer_controls[] = {
++SOC_DAPM_SINGLE("Left Playback Switch", WM8987_ROUTM1, 8, 1, 0),
++SOC_DAPM_SINGLE("Left Bypass Switch", WM8987_ROUTM1, 7, 1, 0),
++SOC_DAPM_SINGLE("Playback Switch", WM8987_ROUTM2, 8, 1, 0),
++SOC_DAPM_SINGLE("Right Bypass Switch", WM8987_ROUTM2, 7, 1, 0),
++};
++
++/* Mono Mixer */
++static const struct snd_kcontrol_new wm8987_mono_mixer_controls[] = {
++SOC_DAPM_SINGLE("Left Playback Switch", WM8987_MOUTM1, 8, 1, 0),
++SOC_DAPM_SINGLE("Left Bypass Switch", WM8987_MOUTM1, 7, 1, 0),
++SOC_DAPM_SINGLE("Right Playback Switch", WM8987_MOUTM2, 8, 1, 0),
++SOC_DAPM_SINGLE("Right Bypass Switch", WM8987_MOUTM2, 7, 1, 0),
++};
++
++/* Left Line Mux */
++static const struct snd_kcontrol_new wm8987_left_line_controls =
++SOC_DAPM_ENUM("Route", wm8987_enum[8]);
++
++/* Right Line Mux */
++static const struct snd_kcontrol_new wm8987_right_line_controls =
++SOC_DAPM_ENUM("Route", wm8987_enum[9]);
++
++/* Left PGA Mux */
++static const struct snd_kcontrol_new wm8987_left_pga_controls =
++SOC_DAPM_ENUM("Route", wm8987_enum[10]);
++
++/* Right PGA Mux */
++static const struct snd_kcontrol_new wm8987_right_pga_controls =
++SOC_DAPM_ENUM("Route", wm8987_enum[11]);
++
++/* Out 3 Mux */
++static const struct snd_kcontrol_new wm8987_out3_controls =
++SOC_DAPM_ENUM("Route", wm8987_enum[12]);
++
++/* Differential Mux */
++static const struct snd_kcontrol_new wm8987_diffmux_controls =
++SOC_DAPM_ENUM("Route", wm8987_enum[13]);
++
++/* Mono ADC Mux */
++static const struct snd_kcontrol_new wm8987_monomux_controls =
++SOC_DAPM_ENUM("Route", wm8987_enum[16]);
++
++static const struct snd_soc_dapm_widget wm8987_dapm_widgets[] = {
++ SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
++ &wm8987_left_mixer_controls[0],
++ ARRAY_SIZE(wm8987_left_mixer_controls)),
++ SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
++ &wm8987_right_mixer_controls[0],
++ ARRAY_SIZE(wm8987_right_mixer_controls)),
++ SND_SOC_DAPM_MIXER("Mono Mixer", WM8987_PWR2, 2, 0,
++ &wm8987_mono_mixer_controls[0],
++ ARRAY_SIZE(wm8987_mono_mixer_controls)),
++
++ SND_SOC_DAPM_PGA("Right Out 2", WM8987_PWR2, 3, 0, NULL, 0),
++ SND_SOC_DAPM_PGA("Left Out 2", WM8987_PWR2, 4, 0, NULL, 0),
++
++// SND_SOC_DAPM_PGA("Right Out 1", WM8987_PWR2, 5, 0,
++// wm8987_rout1_ctrls, ARRAY_SIZE(wm8987_rout1_ctrls)),
++// SND_SOC_DAPM_PGA("Left Out 1", WM8987_PWR2, 6, 0,
++// wm8987_lout1_ctrls, ARRAY_SIZE(wm8987_lout1_ctrls)),
++ SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8987_PWR2, 7, 0),
++ SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8987_PWR2, 8, 0),
++
++ SND_SOC_DAPM_MICBIAS("Mic Bias", WM8987_PWR1, 1, 0),
++ //SND_SOC_DAPM_MICBIAS("Mic Bias", WM8987_PWR1, 1, 1), //lzcx
++ SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8987_PWR1, 2, 0),
++ SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8987_PWR1, 3, 0),
++
++ SND_SOC_DAPM_MUX("Left PGA Mux", WM8987_PWR1, 5, 0,
++ &wm8987_left_pga_controls),
++ SND_SOC_DAPM_MUX("Right PGA Mux", WM8987_PWR1, 4, 0,
++ &wm8987_right_pga_controls),
++ SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
++ &wm8987_left_line_controls),
++ SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
++ &wm8987_right_line_controls),
++
++ SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8987_out3_controls),
++ SND_SOC_DAPM_PGA("Out 3", WM8987_PWR2, 1, 0, NULL, 0),
++ SND_SOC_DAPM_PGA("Mono Out 1", WM8987_PWR2, 2, 0, NULL, 0),
++
++ SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
++ &wm8987_diffmux_controls),
++ SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
++ &wm8987_monomux_controls),
++ SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
++ &wm8987_monomux_controls),
++
++ SND_SOC_DAPM_OUTPUT("LOUT1"),
++ SND_SOC_DAPM_OUTPUT("ROUT1"),
++ SND_SOC_DAPM_OUTPUT("LOUT2"),
++ SND_SOC_DAPM_OUTPUT("ROUT2"),
++ SND_SOC_DAPM_OUTPUT("MONO"),
++ SND_SOC_DAPM_OUTPUT("OUT3"),
++
++ SND_SOC_DAPM_INPUT("LINPUT1"),
++ SND_SOC_DAPM_INPUT("LINPUT2"),
++ SND_SOC_DAPM_INPUT("LINPUT3"),
++ SND_SOC_DAPM_INPUT("RINPUT1"),
++ SND_SOC_DAPM_INPUT("RINPUT2"),
++ SND_SOC_DAPM_INPUT("RINPUT3"),
++};
++
++static const char *audio_map[][3] = {
++ /* left mixer */
++ {"Left Mixer", "Playback Switch", "Left DAC"},
++ {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
++ {"Left Mixer", "Right Playback Switch", "Right DAC"},
++ {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
++
++ /* right mixer */
++ {"Right Mixer", "Left Playback Switch", "Left DAC"},
++ {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
++ {"Right Mixer", "Playback Switch", "Right DAC"},
++ {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
++
++ /* left out 1 */
++ {"Left Out 1", NULL, "Left Mixer"},
++ {"LOUT1", NULL, "Left Out 1"},
++
++ /* left out 2 */
++ {"Left Out 2", NULL, "Left Mixer"},
++ {"LOUT2", NULL, "Left Out 2"},
++
++ /* right out 1 */
++ {"Right Out 1", NULL, "Right Mixer"},
++ {"ROUT1", NULL, "Right Out 1"},
++
++ /* right out 2 */
++ {"Right Out 2", NULL, "Right Mixer"},
++ {"ROUT2", NULL, "Right Out 2"},
++
++ /* mono mixer */
++ {"Mono Mixer", "Left Playback Switch", "Left DAC"},
++ {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
++ {"Mono Mixer", "Right Playback Switch", "Right DAC"},
++ {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
++
++ /* mono out */
++ {"Mono Out 1", NULL, "Mono Mixer"},
++ {"MONO1", NULL, "Mono Out 1"},
++
++ /* out 3 */
++ {"Out3 Mux", "VREF", "VREF"},
++ {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
++ {"Out3 Mux", "ROUT1", "Right Mixer"},
++ {"Out3 Mux", "MonoOut", "MONO1"},
++ {"Out 3", NULL, "Out3 Mux"},
++ {"OUT3", NULL, "Out 3"},
++
++ /* Left Line Mux */
++ {"Left Line Mux", "Line 1", "LINPUT1"},
++ {"Left Line Mux", "Line 2", "LINPUT2"},
++ {"Left Line Mux", "Line 3", "LINPUT3"},
++ {"Left Line Mux", "PGA", "Left PGA Mux"},
++ {"Left Line Mux", "Differential", "Differential Mux"},
++
++ /* Right Line Mux */
++ {"Right Line Mux", "Line 1", "RINPUT1"},
++ {"Right Line Mux", "Line 2", "RINPUT2"},
++ {"Right Line Mux", "Line 3", "RINPUT3"},
++ {"Right Line Mux", "PGA", "Right PGA Mux"},
++ {"Right Line Mux", "Differential", "Differential Mux"},
++
++ /* Left PGA Mux */
++ {"Left PGA Mux", "Line 1", "LINPUT1"},
++ {"Left PGA Mux", "Line 2", "LINPUT2"},
++ {"Left PGA Mux", "Line 3", "LINPUT3"},
++ {"Left PGA Mux", "Differential", "Differential Mux"},
++
++ /* Right PGA Mux */
++ {"Right PGA Mux", "Line 1", "RINPUT1"},
++ {"Right PGA Mux", "Line 2", "RINPUT2"},
++ {"Right PGA Mux", "Line 3", "RINPUT3"},
++ {"Right PGA Mux", "Differential", "Differential Mux"},
++
++ /* Differential Mux */
++ {"Differential Mux", "Line 1", "LINPUT1"},
++ {"Differential Mux", "Line 1", "RINPUT1"},
++ {"Differential Mux", "Line 2", "LINPUT2"},
++ {"Differential Mux", "Line 2", "RINPUT2"},
++
++ /* Left ADC Mux */
++ {"Left ADC Mux", "Stereo", "Left PGA Mux"},
++ {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
++ {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
++
++ /* Right ADC Mux */
++ {"Right ADC Mux", "Stereo", "Right PGA Mux"},
++ {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
++ {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
++
++ /* ADC */
++ {"Left ADC", NULL, "Left ADC Mux"},
++ {"Right ADC", NULL, "Right ADC Mux"},
++
++ /* terminator */
++ {NULL, NULL, NULL},
++};
++
++static int wm8987_add_widgets(struct snd_soc_codec *codec)
++{
++ int i;
++
++ for(i = 0; i < ARRAY_SIZE(wm8987_dapm_widgets); i++) {
++ snd_soc_dapm_new_control(codec, &wm8987_dapm_widgets[i]);
++ }
++
++ /* set up audio path audio_mapnects */
++ for(i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ snd_soc_dapm_new_widgets(codec);
++ return 0;
++}
++
++struct _coeff_div {
++ u32 mclk;
++ u32 rate;
++ u16 fs;
++ u8 sr:5;
++ u8 usb:1;
++};
++
++/* codec hifi mclk clock divider coefficients */
++static const struct _coeff_div coeff_div[] = {
++ /* 8k */
++ {12288000, 8000, 1536, 0x6, 0x0},
++ {18432000, 8000, 2304, 0x7, 0x0},
++ {12000000, 8000, 1500, 0x6, 0x1},
++
++ /* 80182 */
++ {11289600, 8018, 1408, 0x16, 0x0},
++ {16934400, 8018, 2112, 0x17, 0x0},
++
++ /* 8.0214k */
++ {12000000, 8021, 1496, 0x17, 0x1},
++
++ /* 11.025k */
++ {11289600, 11025, 1024, 0x18, 0x0},
++ {16934400, 11025, 1536, 0x19, 0x0},
++ {12000000, 11025, 1088, 0x19, 0x1},
++
++ /* 12k */
++ {12288000, 12000, 1024, 0x8, 0x0},
++ {18432000, 12000, 1536, 0x9, 0x0},
++ {12000000, 12000, 1000, 0x8, 0x1},
++
++ /* 16k */
++ {12288000, 16000, 768, 0xa, 0x0},
++ {18432000, 16000, 1152, 0xb, 0x0},
++ {12000000, 16000, 750, 0xa, 0x1},
++
++ /* 22.05k */
++ {11289600, 22050, 512, 0x1a, 0x0},
++ {16934400, 22050, 768, 0x1b, 0x0},
++ {12000000, 22050, 544, 0x1b, 0x1},
++
++ /* 24k */
++ {12288000, 24000, 512, 0x1c, 0x0},
++ {18432000, 24000, 768, 0x1d, 0x0},
++ {12000000, 24000, 500, 0x1c, 0x1},
++
++ /* 32k */
++ {12288000, 32000, 384, 0xc, 0x0},
++ {18432000, 32000, 576, 0xd, 0x0},
++ {12000000, 32000, 375, 0xc, 0x1}, // mhfan
++
++ /* 44.1k */
++ {11289600, 44100, 256, 0x10, 0x0},
++ {16934400, 44100, 384, 0x11, 0x0},
++ {12000000, 44100, 272, 0x11, 0x1},
++
++ /* 48k */
++ {12288000, 48000, 256, 0x0, 0x0},
++ {18432000, 48000, 384, 0x1, 0x0},
++ {12000000, 48000, 250, 0x0, 0x1},
++
++ /* 88.2k */
++ {11289600, 88200, 128, 0x1e, 0x0},
++ {16934400, 88200, 192, 0x1f, 0x0},
++ {12000000, 88200, 136, 0x1f, 0x1},
++
++ /* 96k */
++ {12288000, 96000, 128, 0xe, 0x0},
++ {18432000, 96000, 192, 0xf, 0x0},
++ {12000000, 96000, 125, 0xe, 0x1},
++};
++
++static inline int get_coeff(int mclk, int rate)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
++ if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
++ return i;
++ }
++
++ printk(KERN_ERR "wm8987: could not get coeff for mclk %d @ rate %d\n",
++ mclk, rate);
++ return -EINVAL;
++}
++
++#if 1 //lzcx
++static int wm8987_set_dai_clkdiv(struct snd_soc_codec_dai *codec_dai,
++ int div_id, int div)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ u16 reg;
++ return 0; //lzcx
++
++ //printk("id is %d div is 0x%x setdaiclkdiv\n",div_id,div);
++ reg = wm8987_read_reg_cache(codec, WM8987_SRATE) & 0x003f;
++ wm8987_write(codec, WM8987_SRATE, reg | div);
++#if 0
++ switch (div_id) {
++ case WM8987_PCMDIV:
++ reg = wm8987_read_reg_cache(codec, WM8987_CLOCK) & 0x003f;
++ wm8987_write(codec, WM8987_CLOCK, reg | div);
++ break;
++ case WM8987_BCLKDIV:
++ reg = wm8987_read_reg_cache(codec, WM8987_SRATE2) & 0x01c7;
++ wm8987_write(codec, WM8987_SRATE2, reg | div);
++ break;
++ case WM8987_VXCLKDIV:
++ reg = wm8987_read_reg_cache(codec, WM8987_SRATE2) & 0x003f;
++ wm8987_write(codec, WM8987_SRATE2, reg | div);
++ break;
++ default:
++ return -EINVAL;
++ }
++#endif
++ return 0;
++}
++
++#endif
++static int wm8987_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++#ifndef CONFIG_HHTECH_MINIPMP
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct wm8987_priv *wm8987 = codec->private_data;
++#endif//CONFIG_HHTECH_MINIPMP
++ //printk("freq is %ld \n",freq);
++
++ switch (freq) {
++ case 11289600:
++ case 12000000:
++ case 12288000:
++ case 16934400:
++ case 18432000:
++#ifndef CONFIG_HHTECH_MINIPMP
++ wm8987->sysclk = freq;
++#else// mhfan
++ case 24576000:
++ wm8987_sysclk = freq;
++#endif//CONFIG_HHTECH_MINIPMP
++ return 0;
++ }
++ return -EINVAL;
++}
++
++static int wm8987_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
++ unsigned int fmt)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ u16 iface = 0;
++
++ /* set master/slave audio interface */
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBM_CFM:
++ iface = 0x0040;
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* interface format */
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ iface |= 0x0002;
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ break;
++ case SND_SOC_DAIFMT_LEFT_J:
++ iface |= 0x0001;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ iface |= 0x0003;
++ break;
++ case SND_SOC_DAIFMT_DSP_B:
++ iface |= 0x0013;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* clock inversion */
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_NB_NF:
++ break;
++ case SND_SOC_DAIFMT_IB_IF:
++ iface |= 0x0090;
++ break;
++ case SND_SOC_DAIFMT_IB_NF:
++ iface |= 0x0080;
++ break;
++ case SND_SOC_DAIFMT_NB_IF:
++ iface |= 0x0010;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++#if 1
++#ifdef CONFIG_HHTECH_MINIPMP
++ iface |= 0x20; // XXX: mhfan
++#endif//CONFIG_HHTECH_MINIPMP
++#endif //lzcx
++
++ if(iface != wm8987_read_reg_cache(codec, WM8987_IFACE))
++ wm8987_write(codec, WM8987_IFACE, iface);
++ return 0;
++}
++
++static int wm8987_pcm_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_device *socdev = rtd->socdev;
++ struct snd_soc_codec *codec = socdev->codec;
++ static int ifirst = 1;
++ u16 valface, valrate;
++ u16 iface = (valface = wm8987_read_reg_cache(codec, WM8987_IFACE)) & 0x1f3;
++ u16 srate = (valrate = wm8987_read_reg_cache(codec, WM8987_SRATE)) & 0x1c0;
++
++#ifndef CONFIG_HHTECH_MINIPMP
++ struct wm8987_priv *wm8987 = codec->private_data;
++ int coeff = get_coeff(wm8987->sysclk, params_rate(params));
++#else// mhfan
++ int coeff = get_coeff(wm8987_sysclk, params_rate(params));
++#endif//CONFIG_HHTECH_MINIPMP
++
++
++ /* bit size */
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ iface |= 0x0004;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ iface |= 0x0008;
++ break;
++ case SNDRV_PCM_FORMAT_S32_LE:
++ iface |= 0x000c;
++ break;
++ }
++
++ if(1 == ifirst || valface != iface)
++ wm8987_write(codec, WM8987_IFACE, iface);
++ if(coeff >= 0) {
++ srate = srate | ((coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
++ //printk("state write is 0x%x\n",srate);
++ if(valrate != srate || 1 == ifirst)
++ wm8987_write(codec, WM8987_SRATE, srate);
++ }
++ ifirst = 0;
++
++ return 0;
++}
++
++static int wm8987_mute(struct snd_soc_codec_dai *dai, int mute)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ u16 mute_reg = wm8987_read_reg_cache(codec, WM8987_ADCDAC) & 0xfff7;
++
++#if 0 /* comment by mhfan */
++ if (mute)
++ wm8987_write(codec, WM8987_ADCDAC, mute_reg | 0x8);
++ else
++ wm8987_write(codec, WM8987_ADCDAC, mute_reg);
++#else
++// static int _mute_flag = -1;
++
++// if(mute == _mute_flag) return 0;
++// _mute_flag = mute;
++
++ if (mute) {
++ wm8987_write(codec, WM8987_ADCDAC, mute_reg | 0x8);
++ if (hhbf_audio_switch) hhbf_audio_switch(0);
++ } else {if (hhbf_audio_switch) hhbf_audio_switch(1);
++ wm8987_write(codec, WM8987_ADCDAC, mute_reg);
++ }
++#endif /* comment by mhfan */
++ return 0;
++}
++
++static int wm8987_dapm_event(struct snd_soc_codec *codec, int event)
++{
++ u16 pwr_reg = wm8987_read_reg_cache(codec, WM8987_PWR1) & 0xfe3e;
++ pwr_reg |= 0x2;//lzcx micbias on
++
++ switch (event) {
++ case SNDRV_CTL_POWER_D0: /* full On */
++ /* set vmid to 50k and unmute dac */
++ wm8987_write(codec, WM8987_PWR1, pwr_reg | 0x00c0);
++ break;
++ case SNDRV_CTL_POWER_D1: /* partial On */
++ wm8987_write(codec, WM8987_PWR1, pwr_reg | 0x01c0);
++ break;
++ case SNDRV_CTL_POWER_D2: /* partial On */
++ /* set vmid to 5k for quick power up */
++ wm8987_write(codec, WM8987_PWR1, pwr_reg | 0x01c1);
++ break;
++ case SNDRV_CTL_POWER_D3hot: /* Off, with power */
++ /* mute dac and set vmid to 500k, enable VREF */
++ wm8987_write(codec, WM8987_PWR1, pwr_reg | 0x0141);
++ break;
++ case SNDRV_CTL_POWER_D3cold: /* Off, without power */
++ wm8987_write(codec, WM8987_PWR1, 0x0001);
++ break;
++ }
++ codec->dapm_state = event;
++ return 0;
++}
++
++#define WM8987_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \
++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
++ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
++ SNDRV_PCM_RATE_96000)
++
++#define WM8987_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE)
++
++struct snd_soc_codec_dai wm8987_dai = {
++ .name = "WM8987",
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = WM8987_RATES,
++ .formats = WM8987_FORMATS,},
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = WM8987_RATES,
++ .formats = WM8987_FORMATS,},
++ .ops = {
++ .hw_params = wm8987_pcm_hw_params,
++ },
++ .dai_ops = {
++ .digital_mute = wm8987_mute,
++ .set_fmt = wm8987_set_dai_fmt,
++ .set_sysclk = wm8987_set_dai_sysclk,
++ .set_clkdiv = wm8987_set_dai_clkdiv,
++ },
++};
++EXPORT_SYMBOL_GPL(wm8987_dai);
++
++static void wm8987_work(struct work_struct *work)
++{
++ struct snd_soc_codec *codec =
++//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
++// (struct snd_soc_codec*)work; // XXX:
++//#else// XXX: mhfan
++ container_of(work, struct snd_soc_codec, delayed_work.work);
++//#endif//LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
++ wm8987_dapm_event(codec, codec->dapm_state);
++}
++
++static int wm8987_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++
++ wm8987_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
++ return 0;
++}
++
++static int wm8987_resume(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++ int i;
++ u8 data[2];
++ u16 *cache = codec->reg_cache;
++
++ /* Sync reg_cache with the hardware */
++ for (i = 0; i < ARRAY_SIZE(wm8987_reg); i++) {
++ if (i == WM8987_RESET)
++ continue;
++ data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
++ data[1] = cache[i] & 0x00ff;
++ codec->hw_write(codec->control_data, data, 2);
++ }
++
++ wm8987_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
++
++ /* charge wm8987 caps */
++ if (codec->suspend_dapm_state == SNDRV_CTL_POWER_D0) {
++ wm8987_dapm_event(codec, SNDRV_CTL_POWER_D2);
++ codec->dapm_state = SNDRV_CTL_POWER_D0;
++ schedule_delayed_work(&codec->delayed_work, msecs_to_jiffies(1000));
++ }
++
++ return 0;
++}
++
++void headp_update_volume(struct work_struct* work)
++{
++ if (p_codec == NULL)
++ return;
++ wm8987_write(p_codec, WM8987_LDAC, volume );
++ // mdelay(500);
++ wm8987_write(p_codec, WM8987_RDAC, volume );
++}
++EXPORT_SYMBOL(headp_update_volume);
++
++
++/*
++ * initialise the WM8987 driver
++ * register the mixer and dsp interfaces with the kernel
++ */
++static int wm8987_init(struct snd_soc_device *socdev)
++{
++ struct snd_soc_codec *codec = socdev->codec;
++ int reg, ret = 0;
++
++ codec->name = "WM8987";
++ codec->owner = THIS_MODULE;
++ codec->read = wm8987_read_reg_cache;
++ codec->write = wm8987_write;
++ codec->dapm_event = wm8987_dapm_event;
++ codec->dai = &wm8987_dai;
++ codec->num_dai = 1;
++#ifndef CONFIG_HHTECH_MINIPMP
++ //codec->reg_cache_size = ARRAY_SIZE(wm8987_reg);
++
++ codec->reg_cache =
++ kzalloc(sizeof(u16) * ARRAY_SIZE(wm8987_reg), GFP_KERNEL);
++ if (codec->reg_cache == NULL)
++ return -ENOMEM;
++ memcpy(codec->reg_cache, wm8987_reg,
++ sizeof(u16) * ARRAY_SIZE(wm8987_reg));
++ codec->reg_cache_size = sizeof(u16) * ARRAY_SIZE(wm8987_reg);
++#else// XXX: mhfan
++ codec->reg_cache = (void*)wm8987_reg;
++ codec->reg_cache_size = ARRAY_SIZE(wm8987_reg);
++
++#ifdef CONFIG_HHBF_FAST_REBOOT
++ if (_bfin_swrst & FAST_REBOOT_FLAG) init_reboot = 1;
++ // XXX: read register values from codec?
++#endif
++#endif//CONFIG_HHTECH_MINIPMP
++
++ wm8987_reset(codec);
++
++ /* register pcms */
++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
++ if (ret < 0) {
++ printk(KERN_ERR "wm8987: failed to create pcms\n");
++ goto pcm_err;
++ }
++
++ /* charge output caps */
++ wm8987_dapm_event(codec, SNDRV_CTL_POWER_D1); // XXX:
++ codec->dapm_state = SNDRV_CTL_POWER_D3hot;
++ schedule_delayed_work(&codec->delayed_work, msecs_to_jiffies(1000));
++
++#ifdef CONFIG_HHTECH_MINIPMP
++ // init first mutes
++ reg = wm8987_read_reg_cache(codec, WM8987_ADCDAC) & 0xfff7;
++ wm8987_write(codec, WM8987_ADCDAC, reg | 0x008);
++// wm8987_write(codec, WM8987_PWR2, 0x180); // reboot
++
++ //wm8987_mute(codec->dai, 1); // XXX:
++ reg = wm8987_read_reg_cache(codec, WM8987_LOUTM1);
++ wm8987_write(codec, WM8987_LOUTM1, reg | 0x0100);
++ reg = wm8987_read_reg_cache(codec, WM8987_ROUTM2);
++ wm8987_write(codec, WM8987_ROUTM2, reg | 0x0100);
++
++ reg = wm8987_read_reg_cache(codec, WM8987_ADCTL1);
++ wm8987_write(codec, WM8987_ADCTL1, reg | 0x0005); // XXX:
++ reg = wm8987_read_reg_cache(codec, WM8987_ADCTL2);
++
++ reg = wm8987_read_reg_cache(codec, WM8987_LADCIN);
++ wm8987_write(codec, WM8987_LADCIN, reg | 0x0060); // XXX: LINP2
++
++ reg = wm8987_read_reg_cache(codec, WM8987_LADC);
++ wm8987_write(codec, WM8987_LADC, reg | 0x0100);
++ reg = wm8987_read_reg_cache(codec, WM8987_RADC);
++ wm8987_write(codec, WM8987_RADC, reg | 0x0100);
++#endif//CONFIG_HHTECH_MINIPMP
++
++ /* set the update bits */
++ reg = wm8987_read_reg_cache(codec, WM8987_LDAC);
++ //wm8987_write(codec, WM8987_LDAC, 0x0100);
++ wm8987_write(codec, WM8987_LDAC, 0x01c7);
++ reg = wm8987_read_reg_cache(codec, WM8987_RDAC);
++ //wm8987_write(codec, WM8987_RDAC, 0x0100);
++ wm8987_write(codec, WM8987_RDAC, 0x01c7);
++
++ reg = wm8987_read_reg_cache(codec, WM8987_LINVOL);
++ wm8987_write(codec, WM8987_LINVOL, (reg & ~0x080) | 0x0140);
++ //wm8987_write(codec, WM8987_LINVOL, (reg & ~0x080) | 0x080); //lzcx
++ reg = wm8987_read_reg_cache(codec, WM8987_RINVOL);
++ wm8987_write(codec, WM8987_RINVOL, (reg & ~0x080) | 0x0140);
++ //wm8987_write(codec, WM8987_RINVOL, (reg & ~0x080) | 0x080); //lzcx
++ reg = wm8987_read_reg_cache(codec, WM8987_3D);
++ wm8987_write(codec, WM8987_3D, (reg | 0x80));
++ wm8987_write(codec, WM8987_LOUT2V, 0x079); //lzcx
++// wm8987_write(codec, WM8987_LOUT2V, 0x0100);
++// wm8987_write(codec, WM8987_ROUT2V, 0x0100);
++ wm8987_write(codec, WM8987_ROUT2V, 0x17a);
++
++
++ wm8987_add_controls(codec);
++ wm8987_add_widgets(codec);
++ ret = snd_soc_register_card(socdev);
++ if (ret < 0) {
++ printk(KERN_ERR "wm8987: failed to register card\n");
++ goto card_err;
++ }
++
++#ifdef CONFIG_HHTECH_MINIPMP
++ init_reboot = 0;
++#endif//CONFIG_HHTECH_MINIPMP
++
++ volume = wm8987_read_reg_cache(codec, WM8987_LDAC); //HHTECH wk
++ p_codec = codec ;
++ headp_update_volume(NULL);
++ return ret;
++
++card_err:
++ snd_soc_free_pcms(socdev);
++ snd_soc_dapm_free(socdev);
++pcm_err:
++#ifndef CONFIG_HHTECH_MINIPMP
++ kfree(codec->reg_cache);
++#endif//CONFIG_HHTECH_MINIPMP
++ return ret;
++}
++
++/* If the i2c layer weren't so broken, we could pass this kind of data
++ around */
++static struct snd_soc_device *wm8987_socdev;
++
++#ifdef CONFIG_HHTECH_MINIPMP
++void hhbf_audio_close(void)
++{
++ if (!wm8987_socdev) return;
++ cancel_delayed_work(&wm8987_socdev->delayed_work);
++ wm8987_reset(wm8987_socdev->codec);
++}
++EXPORT_SYMBOL(hhbf_audio_close);
++#endif//CONFIG_HHTECH_MINIPMP
++
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++/*
++ * WM8731 2 wire address is determined by GPIO5
++ * state during powerup.
++ * low = 0x1a
++ * high = 0x1b
++ */
++static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
++
++/* Magic definition of all other variables and things */
++I2C_CLIENT_INSMOD;
++
++static struct i2c_driver wm8987_i2c_driver;
++static struct i2c_client client_template;
++
++static int wm8987_codec_probe(struct i2c_adapter *adap, int addr, int kind)
++{
++ struct snd_soc_device *socdev = wm8987_socdev;
++ struct wm8987_setup_data *setup = socdev->codec_data;
++ struct snd_soc_codec *codec = socdev->codec;
++ struct i2c_client *i2c;
++ int ret;
++
++ if (addr != setup->i2c_address)
++ return -ENODEV;
++
++ client_template.adapter = adap;
++ client_template.addr = addr;
++
++#ifndef CONFIG_HHTECH_MINIPMP
++ i2c = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
++ if (i2c == NULL) {
++ kfree(codec);
++ return -ENOMEM;
++ }
++ memcpy(i2c, &client_template, sizeof(struct i2c_client));
++#else// mhfan
++ i2c = &client_template;
++#endif//CONFIG_HHTECH_MINIPMP
++ i2c_set_clientdata(i2c, codec);
++ codec->control_data = i2c;
++
++ ret = i2c_attach_client(i2c);
++ if (ret < 0) {
++ err("failed to attach codec at addr %x\n", addr);
++ goto err;
++ }
++
++ ret = wm8987_init(socdev);
++ if (ret < 0) {
++ err("failed to initialise WM8987\n");
++ goto err;
++ }
++ //printk("init WM8987 OK\n");
++ return ret;
++
++err:
++ kfree(codec);
++#ifndef CONFIG_HHTECH_MINIPMP
++ kfree(i2c);
++#endif//CONFIG_HHTECH_MINIPMP
++ return ret;
++}
++
++static int wm8987_i2c_detach(struct i2c_client *client)
++{
++#ifndef CONFIG_HHTECH_MINIPMP
++ struct snd_soc_codec *codec = i2c_get_clientdata(client);
++ i2c_detach_client(client);
++ kfree(codec->reg_cache);
++ kfree(client);
++#else// mhfan
++ i2c_detach_client(client);
++#endif//CONFIG_HHTECH_MINIPMP
++ return 0;
++}
++
++static int wm8987_i2c_attach(struct i2c_adapter *adap)
++{
++ return i2c_probe(adap, &addr_data, wm8987_codec_probe);
++}
++
++/* corgi i2c codec control layer */
++static struct i2c_driver wm8987_i2c_driver = {
++ .driver = {
++ .name = "WM8987 I2C Codec",
++ .owner = THIS_MODULE,
++ },
++ .id = I2C_DRIVERID_WM8753,
++ .attach_adapter = wm8987_i2c_attach,
++ .detach_client = wm8987_i2c_detach,
++ .command = NULL,
++};
++
++static struct i2c_client client_template = {
++ .name = "WM8987",
++ .driver = &wm8987_i2c_driver,
++};
++#endif
++
++static int wm8987_probe(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct wm8987_setup_data *setup = socdev->codec_data;
++ struct snd_soc_codec *codec;
++ //struct wm8987_priv *wm8987; // mhfan
++ int ret = 0;
++
++ info("Audio Codec Driver %s", WM8987_VERSION);
++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
++ if (codec == NULL)
++ return -ENOMEM;
++
++#ifndef CONFIG_HHTECH_MINIPMP
++ wm8987 = kzalloc(sizeof(struct wm8987_priv), GFP_KERNEL);
++ if (wm8987 == NULL) {
++ kfree(codec);
++ return -ENOMEM;
++ }
++
++ codec->private_data = wm8987;
++#endif//CONFIG_HHTECH_MINIPMP
++ socdev->codec = codec;
++ mutex_init(&codec->mutex);
++ INIT_LIST_HEAD(&codec->dapm_widgets);
++ INIT_LIST_HEAD(&codec->dapm_paths);
++ wm8987_socdev = socdev;
++//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
++// INIT_WORK(&codec->delayed_work, wm8987_work, codec);
++//#else// XXX: mhfan
++ INIT_DELAYED_WORK(&codec->delayed_work, wm8987_work);
++//#endif// LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
++
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++ if (setup->i2c_address) {
++ normal_i2c[0] = setup->i2c_address;
++ codec->hw_write = (hw_write_t)i2c_master_send;
++ ret = i2c_add_driver(&wm8987_i2c_driver);
++ if (ret != 0)
++ printk(KERN_ERR "can't add i2c driver");
++ }
++#else
++ /* Add other interfaces here */
++#endif
++
++ return ret;
++}
++
++/*
++ * This function forces any delayed work to be queued and run.
++ */
++static int run_delayed_work(struct delayed_work *dwork)
++{
++ int ret;
++
++ /* cancel any work waiting to be queued. */
++ ret = cancel_delayed_work(dwork);
++
++ /* if there was any work waiting then we run it now and
++ * wait for it's completion */
++ if (ret) {
++ schedule_delayed_work(dwork, 0);
++ flush_scheduled_work();
++ }
++ return ret;
++}
++
++/* power down chip */
++static int wm8987_remove(struct platform_device *pdev)
++{
++ struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++ struct snd_soc_codec *codec = socdev->codec;
++
++ if (codec->control_data)
++ wm8987_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
++ run_delayed_work(&codec->delayed_work);
++ snd_soc_free_pcms(socdev);
++ snd_soc_dapm_free(socdev);
++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
++ i2c_del_driver(&wm8987_i2c_driver);
++#endif
++#ifndef CONFIG_HHTECH_MINIPMP
++ kfree(codec->private_data);
++#endif//CONFIG_HHTECH_MINIPMP
++ kfree(codec);
++
++ return 0;
++}
++
++struct snd_soc_codec_device soc_codec_dev_wm8987 = {
++ .probe = wm8987_probe,
++ .remove = wm8987_remove,
++ .suspend = wm8987_suspend,
++ .resume = wm8987_resume,
++};
++
++EXPORT_SYMBOL_GPL(soc_codec_dev_wm8987);
++
++MODULE_DESCRIPTION("ASoC WM8987 driver");
++MODULE_AUTHOR("Liam Girdwood");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/codecs/wm8987.h b/sound/soc/codecs/wm8987.h
+new file mode 100644
+index 0000000..fa9820b
+--- /dev/null
++++ b/sound/soc/codecs/wm8987.h
+@@ -0,0 +1,110 @@
++/*
++ * Copyright 2005 Openedhand Ltd.
++ *
++ * Author: Richard Purdie <richard@openedhand.com>
++ *
++ * Based on WM8987.h
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef _WM8987_H
++#define _WM8987_H
++
++#define CONFIG_HHTECH_MINIPMP 1
++
++/* WM8987 register space */
++
++#define WM8987_LINVOL 0x00
++#define WM8987_RINVOL 0x01
++#define WM8987_LOUT1V 0x02
++#define WM8987_ROUT1V 0x03
++#define WM8987_ADCDAC 0x05
++#define WM8987_IFACE 0x07
++#define WM8987_SRATE 0x08
++#define WM8987_LDAC 0x0a
++#define WM8987_RDAC 0x0b
++#define WM8987_BASS 0x0c
++#define WM8987_TREBLE 0x0d
++#define WM8987_RESET 0x0f
++#define WM8987_3D 0x10
++#define WM8987_ALC1 0x11
++#define WM8987_ALC2 0x12
++#define WM8987_ALC3 0x13
++#define WM8987_NGATE 0x14
++#define WM8987_LADC 0x15
++#define WM8987_RADC 0x16
++#define WM8987_ADCTL1 0x17
++#define WM8987_ADCTL2 0x18
++#define WM8987_PWR1 0x19
++#define WM8987_PWR2 0x1a
++#define WM8987_ADCTL3 0x1b
++#define WM8987_ADCIN 0x1f
++#define WM8987_LADCIN 0x20
++#define WM8987_RADCIN 0x21
++#define WM8987_LOUTM1 0x22
++#define WM8987_LOUTM2 0x23
++#define WM8987_ROUTM1 0x24
++#define WM8987_ROUTM2 0x25
++#define WM8987_MOUTM1 0x26
++#define WM8987_MOUTM2 0x27
++#define WM8987_LOUT2V 0x28
++#define WM8987_ROUT2V 0x29
++#define WM8987_MOUTV 0x2a
++
++#define WM8987_CACHE_REGNUM 0x2a
++
++#define WM8987_SYSCLK 0
++
++struct wm8987_setup_data {
++ unsigned short i2c_address;
++};
++
++extern struct snd_soc_codec_dai wm8987_dai;
++extern struct snd_soc_codec_device soc_codec_dev_wm8987;
++
++#if 1 //lzcx
++#define WM8987_PLL1 0
++#define WM8987_PLL2 1
++
++/* clock inputs */
++#define WM8987_MCLK 0
++#define WM8987_PCMCLK 1
++
++/* clock divider id's */
++#define WM8987_PCMDIV 0
++#define WM8987_BCLKDIV 1
++#define WM8987_VXCLKDIV 2
++
++/* PCM clock dividers */
++#define WM8987_PCM_DIV_1 (0 << 6)
++#define WM8987_PCM_DIV_3 (2 << 6)
++#define WM8987_PCM_DIV_5_5 (3 << 6)
++#define WM8987_PCM_DIV_2 (4 << 6)
++#define WM8987_PCM_DIV_4 (5 << 6)
++#define WM8987_PCM_DIV_6 (6 << 6)
++#define WM8987_PCM_DIV_8 (7 << 6)
++
++/* BCLK clock dividers */
++#define WM8987_BCLK_DIV_1 (0 << 7)
++#define WM8987_BCLK_DIV_2 (1 << 7)
++#define WM8987_BCLK_DIV_4 (2 << 7)
++#define WM8987_BCLK_DIV_8 (3 << 7)
++
++/* VXCLK clock dividers */
++#define WM8987_VXCLK_DIV_1 (0 << 6)
++#define WM8987_VXCLK_DIV_2 (1 << 6)
++#define WM8987_VXCLK_DIV_4 (2 << 6)
++#define WM8987_VXCLK_DIV_8 (3 << 6)
++#define WM8987_VXCLK_DIV_16 (4 << 6)
++
++#define WM8987_DAI_HIFI 0
++#define WM8987_DAI_VOICE 1
++
++
++#endif
++
++#endif
+diff --git a/sound/soc/s3c64xx/Kconfig b/sound/soc/s3c64xx/Kconfig
+index 705c677..1faeeae 100644
+--- a/sound/soc/s3c64xx/Kconfig
++++ b/sound/soc/s3c64xx/Kconfig
+@@ -17,6 +17,9 @@ config SND_S3C_SOC_I2S
+ config SND_S3C6410_SOC_I2S_V32
+ tristate
+
++config SND_S3C6410_SOC_I2S_V40
++ tristate
++
+ config SND_S3C6410_SOC_I2S
+ tristate
+
+@@ -38,19 +41,17 @@ choice
+
+ config SOUND_WM9713_INPUT_STREAM_LINE
+ bool "Input Stream is LINE-IN"
+- depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713
+ help
+ Say Y here to make input stream as LINE-IN.
+
+ config SOUND_WM9713_INPUT_STREAM_MIC
+ bool "Input Stream is MIC"
+- depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713
+ help
+ Say Y here to make input stream as MIC.
+ endchoice
+
+ config SND_S3C6410_SOC_AC97
+- tristate
++ tristate "AC97 support for SMDK6410"
+ select AC97_BUS
+ select SND_AC97_CODEC
+ select SND_SOC_AC97_BUS
+@@ -70,17 +71,29 @@ choice
+
+ config SOUND_WM8580_INPUT_STREAM_LINE
+ bool "Input Stream is LINE-IN"
+- depends on SND_S3C6410_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580
+ help
+ Say Y here to make input stream as LINE-IN.
+
+ config SOUND_WM8580_INPUT_STREAM_MIC
+ bool "Input Stream is MIC"
+- depends on SND_S3C6410_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580
+ help
+ Say Y here to make input stream as MIC.
+ endchoice
+
++config SND_S3C64XX_SOC_SMDK6410_WM8987
++ tristate "SoC I2S Audio support for SMDK6410 - WM8987"
++ depends on SND_S3C_SOC && (MACH_SMDK6410)
++ select SND_S3C6410_SOC_I2S_V32
++ select SND_SOC_WM8987
++ help
++ Say Y if you want to add support for SoC audio on smdk6410
++ with the WM8987.
++
++config AUDIO_CODEC_PROCFS
++ bool "Proc-FS interface for audio codec control"
++ depends on SND_S3C64XX_SOC_SMDK6410_WM8987 && PROC_FS
++ default y
++
+ config SND_S3C64XX_SOC_SMDK6410_WM8990
+ tristate "SoC I2S Audio support for SMDK6410 - WM8990"
+ depends on SND_S3C_SOC && (MACH_SMDK6410)
+@@ -96,13 +109,11 @@ choice
+
+ config SOUND_WM8990_INPUT_STREAM_LINE_IN
+ bool "Input Stream is LINE-IN"
+- depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990
+ help
+ Say Y here to make input stream as LINE-IN.
+
+ config SOUND_WM8990_INPUT_STREAM_MIC_IN
+ bool "Input Stream is MIC"
+- depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990
+ help
+ Say Y here to make input stream as MIC.
+ endchoice
+diff --git a/sound/soc/s3c64xx/Makefile b/sound/soc/s3c64xx/Makefile
+index 2865391..85e848d 100644
+--- a/sound/soc/s3c64xx/Makefile
++++ b/sound/soc/s3c64xx/Makefile
+@@ -11,8 +11,10 @@ obj-$(CONFIG_SND_S3C6410_SOC_I2S_V32) += snd-soc-s3c6410-i2s-v32.o
+ snd-soc-neo1973-wm8753-objs := neo1973_wm8753.o
+ snd-soc-smdk64xx-wm9713-objs := smdk64xx_wm9713.o
+ snd-soc-smdk6410-wm8580-objs := smdk6410_wm8580.o
++snd-soc-smdk6410-wm8987-objs := smdk6410_wm8987.o
+ snd-soc-smdk6410-wm8990-objs := smdk6410_wm8990.o
+
+ obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713) += snd-soc-smdk64xx-wm9713.o
+ obj-$(CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580) += snd-soc-smdk6410-wm8580.o
++obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8987) += snd-soc-smdk6410-wm8987.o
+ obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) += snd-soc-smdk6410-wm8990.o
+diff --git a/sound/soc/s3c64xx/s3c6410-i2s-v32.c b/sound/soc/s3c64xx/s3c6410-i2s-v32.c
+index 6c7446e..7a08bc8 100644
+--- a/sound/soc/s3c64xx/s3c6410-i2s-v32.c
++++ b/sound/soc/s3c64xx/s3c6410-i2s-v32.c
+@@ -265,8 +265,8 @@ static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
+ /*Set I2C port to controll WM8753 codec*/
+ s3c_gpio_pullup(S3C_GPB5, 0);
+ s3c_gpio_pullup(S3C_GPB6, 0);
+- s3c_gpio_cfgpin(S3C_GPB5, S3C_GPB5_I2C_SCL);
+- s3c_gpio_cfgpin(S3C_GPB6, S3C_GPB6_I2C_SDA);
++ s3c_gpio_cfgpin(S3C_GPB5, S3C_GPB5_I2C_SCL0);
++ s3c_gpio_cfgpin(S3C_GPB6, S3C_GPB6_I2C_SDA0);
+
+ s3c24xx_i2s.master = 1;
+
+diff --git a/sound/soc/s3c64xx/smdk6410_wm8987.c b/sound/soc/s3c64xx/smdk6410_wm8987.c
+new file mode 100644
+index 0000000..c862d0f
+--- /dev/null
++++ b/sound/soc/s3c64xx/smdk6410_wm8987.c
+@@ -0,0 +1,623 @@
++/*
++ * smdk64xx_wm8987.c -- SoC audio for Neo1973
++ *
++ * Copyright 2007 Wolfson Microelectronics PLC.
++ * Author: Graeme Gregory
++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Revision history
++ * 20th Jan 2007 Initial version.
++ * 05th Feb 2007 Rename all to Neo1973
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/timer.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <linux/proc_fs.h>
++#include <linux/ctype.h> //lzcx
++#include <sound/driver.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware/scoop.h>
++#include <asm-arm/plat-s3c64xx/regs-iis.h>
++
++#include <asm/arch/regs-gpio.h>
++#include <asm/hardware.h>
++#include <asm/arch/audio.h>
++#include <asm/io.h>
++#include <asm/arch/spi-gpio.h>
++
++#ifdef CONFIG_CPU_S3C6400
++#include <asm/arch/regs-s3c6400-clock.h>
++#elif defined CONFIG_CPU_S3C6410
++#include <asm/arch/regs-s3c6410-clock.h>
++#else
++
++#endif
++
++#include "../codecs/wm8987.h"
++#include "../s3c24xx/s3c-pcm.h"
++#include "../s3c24xx/s3c-i2s.h"
++
++/* define the scenarios */
++#define SMDK6400_AUDIO_OFF 0
++#define SMDK6400_CAPTURE_MIC1 3
++#define SMDK6400_STEREO_TO_HEADPHONES 2
++#define SMDK6400_CAPTURE_LINE_IN 1
++
++#ifdef CONFIG_SND_DEBUG
++#define s3cdbg(x...) printk(x)
++#else
++#define s3cdbg(x...)
++#endif
++
++static struct snd_soc_machine smdk6400;
++
++static int smdk6400_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++ unsigned int pll_out = 0, bclk = 0;
++ int ret = 0;
++ unsigned int iispsr, iismod;
++ unsigned int prescaler = 4;
++ unsigned long regs = ioremap(S3C6400_PA_IIS, 0x100);
++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params));
++
++ /*PCLK & SCLK gating enable*/
++ writel(readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_IIS0, S3C_PCLK_GATE);
++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE);
++
++ iismod = readl((regs + S3C64XX_IIS0MOD));
++ iismod &=~(0x3<<3);
++
++ /*Clear I2S prescaler value [13:8] and disable prescaler*/
++ iispsr = readl((regs + S3C64XX_IIS0PSR));
++ iispsr &=~((0x3f<<8)|(1<<15));
++ writel(iispsr, (regs+S3C64XX_IIS0PSR));
++
++ switch (params_rate(params)) {
++ case 16000:
++ case 32000:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++ break;
++ case 8000:
++ prescaler = 0xe;
++ case 48000:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(192<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0);
++ break;
++ case 11025:
++ prescaler = 9;
++ case 22050:
++ case 44100:
++ writel(0, S3C_EPLL_CON1);
++ writel((1<<31)|(254<<16)|(9<<8)|(2<<0) ,S3C_EPLL_CON0);
++ break;
++ default:
++ break;
++ }
++
++ s3cdbg("%s, IISCON: %x IISMOD: %x,IISFIC: %x,IISPSR: %x",
++ __FUNCTION__ , readl(S3C_IIS0CON), readl(S3C_IIS0MOD),
++ readl(S3C_IIS0FIC), readl(S3C_IIS0PSR));
++
++ while(!(__raw_readl(S3C_EPLL_CON0)&(1<<30)));
++
++ /* MUXepll : FOUTepll */
++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC);
++ /* AUDIO0 sel : FOUTepll */
++ //writel((readl(S3C_CLK_SRC)&~(0x7<<7))|(0<<7), S3C_CLK_SRC);
++ writel((readl(S3C_CLK_SRC)&~(0x7<<7))|(0x0<<7), S3C_CLK_SRC); //lzcx
++
++ /* CLK_DIV2 setting */
++ writel(0x0,S3C_CLK_DIV2);
++
++ switch (params_rate(params)) {
++ case 8000:
++ iismod |= S3C64XX_IIS0MOD_768FS;
++ pll_out = 12288000;
++ //pll_out = 6144000; //lzcx
++ break;
++ case 11025:
++ iismod |= S3C64XX_IIS0MOD_768FS;
++ //bclk = WM8987_BCLK_DIV_16;
++ bclk = WM8987_BCLK_DIV_8 | (1<<6); //lzcx
++ pll_out = 16934400;
++ break;
++ case 16000:
++ iismod |= S3C64XX_IIS0MOD_768FS;
++ bclk = WM8987_BCLK_DIV_2;
++ pll_out = 12288000;
++ break;
++ case 22050:
++ iismod |= S3C64XX_IIS0MOD_768FS;
++ bclk = WM8987_BCLK_DIV_8;
++ pll_out = 16934400;
++ break;
++ case 96000: //lzcx add
++ case 32000:
++ iismod |= S3C64XX_IIS0MOD_384FS;
++ bclk = WM8987_BCLK_DIV_2;
++ pll_out = 12288000;
++ break;
++ case 44100:
++ iismod |= S3C64XX_IIS0MOD_384FS;
++ bclk = WM8987_BCLK_DIV_4;
++ pll_out = 16934400;
++ break;
++ case 48000:
++ iismod |= S3C64XX_IIS0MOD_384FS;
++ bclk = WM8987_BCLK_DIV_4;
++ pll_out = 18432000;
++ break;
++ }
++
++ writel(iismod , (regs+S3C64XX_IIS0MOD));
++
++ /* set codec DAI configuration */
++ ret = codec_dai->dai_ops.set_fmt(codec_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS );
++ if (ret < 0)
++ { printk("aaa\n");
++ return ret;
++ }
++
++ /* set cpu DAI configuration */
++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS );
++ if (ret < 0)
++ { printk("aaa1\n");
++ return ret;
++ }
++
++ /* set the codec system clock for DAC and ADC */
++ ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8987_MCLK, pll_out,
++ SND_SOC_CLOCK_IN);
++ if (ret < 0)
++ { printk("aaa2 pll_out %ld \n",pll_out);
++ return ret;
++ }
++
++ /* set MCLK division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK,
++ S3C64XX_IISMOD_32FS );
++ if (ret < 0)
++ { printk("aaa3\n");
++ return ret;
++ }
++
++ /* set codec BCLK division for sample rate */
++ ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8987_BCLKDIV, bclk);
++ if (ret < 0)
++ { printk("aaa4\n");
++ return ret;
++ }
++
++ /* set prescaler division for sample rate */
++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
++ (prescaler << 0x8));
++ if (ret < 0)
++ { printk("aaa5\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static int smdk6400_hifi_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++
++ /* disable the PLL */
++ return 0;//lzcx codec_dai->dai_ops.set_pll(codec_dai, WM8987_PLL1, 0, 0);
++ //return codec_dai->dai_ops.set_pll(codec_dai, WM8987_PLL1, 0, 0);
++}
++
++/*
++ * Neo1973 WM8987 HiFi DAI opserations.
++ */
++static struct snd_soc_ops smdk6400_hifi_ops = {
++ .hw_params = smdk6400_hifi_hw_params,
++ .hw_free = smdk6400_hifi_hw_free,
++};
++
++static int smdk6400_scenario = 0;
++
++static int smdk6400_get_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ ucontrol->value.integer.value[0] = smdk6400_scenario;
++ return 0;
++}
++
++static int set_scenario_endpoints(struct snd_soc_codec *codec, int scenario)
++{
++ switch(smdk6400_scenario) {
++ printk("smdk6400_scenario is %d\n",smdk6400_scenario);//lzcx
++ case SMDK6400_AUDIO_OFF:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic Bias", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6400_STEREO_TO_HEADPHONES:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic Bias", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6400_CAPTURE_MIC1:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic Bias", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0);
++ break;
++ case SMDK6400_CAPTURE_LINE_IN:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0);
++ snd_soc_dapm_set_endpoint(codec, "Mic Bias", 0);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ default:
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Mic Bias", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++ break;
++ }
++
++ snd_soc_dapm_sync_endpoints(codec);
++
++ return 0;
++}
++
++static int smdk6400_set_scenario(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++
++ if (smdk6400_scenario == ucontrol->value.integer.value[0])
++ return 0;
++
++ smdk6400_scenario = ucontrol->value.integer.value[0];
++ set_scenario_endpoints(codec, smdk6400_scenario);
++ return 1;
++}
++
++static const struct snd_soc_dapm_widget wm8987_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headphone Jack", NULL),
++ SND_SOC_DAPM_MIC("Mic Bias", NULL),
++ SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++
++/* example machine audio_mapnections */
++static const char* audio_map[][3] = {
++
++ {"Headphone Jack", NULL, "LOUT2"},
++ {"Headphone Jack", NULL, "ROUT2"}, //lzcx 1
++
++// mic is connected to line2 //lzcx
++
++ { "LINPUT2", NULL, "Mic Bias" },
++ { "Mic Bias", NULL, "Mic Jack" }, //lzcx
++
++ {"LINPUT1", NULL, "Line In Jack"},
++ {"RINPUT1", NULL, "Line In Jack"},
++
++#if 0
++ /* Connect the ALC pins */
++ {"ACIN", NULL, "ACOP"},
++#endif
++
++ {NULL, NULL, NULL},
++};
++
++static const char *smdk_scenarios[] = {
++ "Off",
++ "Capture Line In",
++ "Headphones",
++ "Capture Mic1",
++};
++
++static const struct soc_enum smdk_scenario_enum[] = {
++ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(smdk_scenarios),smdk_scenarios),
++};
++
++static const struct snd_kcontrol_new wm8987_smdk6400_controls[] = {
++ SOC_ENUM_EXT("SMDK Mode", smdk_scenario_enum[0],
++ smdk6400_get_scenario, smdk6400_set_scenario),
++};
++
++/*
++ * This is an example machine initialisation for a wm8987 connected to a
++ * smdk6400. It is missing logic to detect hp/mic insertions and logic
++ * to re-route the audio in such an event.
++ */
++static int smdk6400_wm8987_init(struct snd_soc_codec *codec)
++{
++ int i, err;
++
++ /* set endpoints to default mode */
++ set_scenario_endpoints(codec, SMDK6400_AUDIO_OFF);
++
++ /* Add smdk6400 specific widgets */
++ for (i = 0; i < ARRAY_SIZE(wm8987_dapm_widgets); i++)
++ snd_soc_dapm_new_control(codec, &wm8987_dapm_widgets[i]);
++
++ /* add smdk6400 specific controls */
++ for (i = 0; i < ARRAY_SIZE(wm8987_smdk6400_controls); i++) {
++ err = snd_ctl_add(codec->card,
++ snd_soc_cnew(&wm8987_smdk6400_controls[i],
++ codec, NULL));
++ if (err < 0)
++ return err;
++ }
++
++ /* set up smdk6400 specific audio path audio_mapnects */
++ for (i = 0; audio_map[i][0] != NULL; i++) {
++ snd_soc_dapm_connect_input(codec, audio_map[i][0],
++ audio_map[i][1], audio_map[i][2]);
++ }
++
++ /* always connected */
++ snd_soc_dapm_set_endpoint(codec, "Mic Bias", 1);
++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1);
++
++ snd_soc_dapm_sync_endpoints(codec);
++ return 0;
++}
++
++static int smdk6400_probe(struct platform_device *pdev)
++{
++ /*Set I2C port to controll WM8987 codec*/
++ s3c_gpio_pullup(S3C_GPB5, 0);
++ s3c_gpio_pullup(S3C_GPB6, 0);
++ s3c_gpio_cfgpin(S3C_GPB5, S3C_GPB5_I2C_SCL0);
++ s3c_gpio_cfgpin(S3C_GPB6, S3C_GPB6_I2C_SDA0);
++ return 0;
++}
++
++static struct snd_soc_dai_link smdk6400_dai[] = {
++{ /* Hifi Playback - for similatious use with voice below */
++ .name = "WM8987",
++ .stream_name = "WM8987 HiFi",
++ .cpu_dai = &s3c_i2s_dai,
++ //.codec_dai = &wm8987_dai[WM8987_DAI_HIFI],
++ .codec_dai = &wm8987_dai,
++ .init = smdk6400_wm8987_init,
++ .ops = &smdk6400_hifi_ops,
++},
++};
++
++static struct snd_soc_machine smdk6400 = {
++ .name = "smdk6400",
++ .probe = smdk6400_probe,
++ .dai_link = smdk6400_dai,
++ .num_links = ARRAY_SIZE(smdk6400_dai),
++};
++
++static struct wm8987_setup_data smdk6400_wm8987_setup = {
++ .i2c_address = 0x1a,
++};
++
++static struct snd_soc_device smdk6400_snd_devdata = {
++ .machine = &smdk6400,
++ .platform = &s3c24xx_soc_platform,
++ .codec_dev = &soc_codec_dev_wm8987,
++ .codec_data = &smdk6400_wm8987_setup,
++};
++
++static struct platform_device *smdk6400_snd_device;
++
++#ifdef CONFIG_AUDIO_CODEC_PROCFS
++
++// This function forces any delayed work to be queued and run.
++static int proc_run_delayed_work(struct delayed_work *dwork)
++{
++ int ret;
++
++ // cancel any work waiting to be queued.
++ ret = cancel_delayed_work(dwork);
++
++ // if there was any work waiting then we run it now and
++ // wait for it's completion.
++ if (ret) {
++ schedule_delayed_work(dwork, 0);
++ flush_scheduled_work();
++ }
++
++ return ret;
++}
++
++static int aud_proc_read(char* page, char** start, off_t off, int count,
++ int* eof, void* data)
++{
++ struct snd_soc_codec* codec = smdk6400_snd_devdata.codec;
++
++ if (!codec || !codec->read) return count;
++
++ if (off) return 0; data = (void*)page;
++
++ page += sprintf(page, "%s registers cached settings: ", codec->name);
++ for (count=0; count < codec->reg_cache_size; ++count) {
++ if (!(count % 16)) page += sprintf(page, "\n R%02x: ", count);
++ page += sprintf(page, "%03x ", codec->read(codec, count));
++ if ((count % 8) == 7) page += sprintf(page, " ");
++ }
++
++ return ((page += sprintf(page, "\n")) - (char*)data);
++}
++
++
++static int aud_proc_write(struct file* file, const char* buffer,
++ unsigned long count, void* data)
++{
++#define MAX_BUFLEN 16
++ u8 reg;
++ u16 val = MAX_BUFLEN - 1;
++ char *ptr, tmp_buf[MAX_BUFLEN];
++ struct snd_soc_codec* codec = smdk6400_snd_devdata.codec;
++
++ if (!codec || !codec->write) return count;
++
++ if (count < MAX_BUFLEN) val = count - 1; tmp_buf[val] = 0;
++ if (copy_from_user(tmp_buf, buffer, val)) return -EFAULT;
++
++ for (ptr = tmp_buf; isspace(*ptr); ++ptr) ;
++
++#if 0
++ if (strncasecmp(ptr, "FmOn", val) == 0) { // enter fmmode
++ ptr += 4;
++ proc_run_delayed_work(&smdk6400_snd_devdata.delayed_work);
++ cancel_delayed_work(&codec->delayed_work);
++ codec->write(codec, 0x1A, 0x018);
++ codec->write(codec, 0x22, 0x0D0);
++ codec->write(codec, 0x25, 0x0D0);
++ return count;
++ } else
++ if (strncasecmp(ptr, "FmOff", val) == 0) { // leave fmmode
++ ptr += 5;
++ codec->write(codec, 0x1A, 0x000);
++ codec->write(codec, 0x22, 0x150);
++ codec->write(codec, 0x25, 0x150);
++ return count;
++ } else
++ if (strncasecmp(ptr, "FmRecOn", val) == 0) { // record fm
++#if 0
++ struct snd_soc_dapm_path *p;
++ list_for_each_entry(p, &codec->dapm_paths, list) {
++ if(strncmp(p->sink->name, "Left PGA Mux", 12)) continue;
++ if(!p->connect && !strcmp(p->source->name, "LINPUT1"))
++ p->connect = 1;
++ if(p->connect && !strnmp(p->source->name, "LINPUT2"))
++ p->connect = 0;
++ }
++#endif
++ proc_run_delayed_work(&smdk6400_snd_devdata.delayed_work);
++ cancel_delayed_work_sync(&codec->delayed_work);
++ codec->write(codec, 0x20, 0x000);
++ //smdk6400_snd_devdata.s_rec = 1;
++ ptr += 7;
++ return count;
++ } else
++ if (strncasecmp(ptr, "FmRecOff", val) == 0) { // leave record fm
++ codec->write(codec, 0x20, 0x060);
++ //smdk6400_snd_devdata.s_rec = 0;
++ ptr += 8;
++ return count;
++ }
++#endif //lzcx
++
++ reg = simple_strtoul(ptr, &ptr, 16);
++
++ if (!(reg < codec->reg_cache_size)) {
++ printk(KERN_DEBUG "wrong register no %d, max %d\n",
++ reg, codec->reg_cache_size);
++ return count;
++ }
++
++ while (isspace(*ptr)) ++ptr;
++ val = simple_strtoul(ptr, &ptr, 16);
++
++ if (codec->write(codec, reg, val)) ;
++
++ return count;
++}
++
++#if 0 /* comment by mhfan */
++/*
++ * Initial:
++ * R00: 157 157 1f9 1f9 000 008 000 00a 000 000 1ff 1ff 00f 00f 000 000
++ * R10: 000 07b 000 032 000 1c3 1c3 0c5 050 141 000 000 000 000 000 000
++ * R20: 0a0 000 150 050 050 150 050 050 1f9 1f9 079
++ *
++ * Playback:
++ * R00: 157 157 1f9 1f9 000 000 000 042 023 000 1ff 1ff 00f 00f 000 000
++ * R10: 000 07b 000 032 000 1c3 1c3 0c5 050 0c0 1fa 000 000 000 000 000
++ * R20: 0a0 000 150 050 050 150 050 050 1f9 1f9 079 (44.1 KHz)
++ *
++ * R00: 157 157 1f9 1f9 000 000 000 042 037 000 1ff 1ff 00f 00f 000 000
++ * R10: 000 07b 000 032 000 1c3 1c3 0c5 050 0c0 1fa 000 000 000 000 000
++ * R20: 0a0 000 150 050 050 150 050 050 1f9 1f9 079 (22050 Hz)
++ *
++ * Capture:
++ */
++#endif /* comment by mhfan */
++
++#define AUD_PROC_ENTRY "driver/audregs"
++
++static int __init aud_proc_init(void)
++{
++ struct proc_dir_entry* aud_entry;
++
++ if (!(aud_entry = create_proc_entry(AUD_PROC_ENTRY,
++ S_IRUGO | S_IWUSR, NULL))) return -ENOMEM;
++
++ printk(KERN_INFO "Proc-FS interface for audio codec\n");
++
++ aud_entry->owner = THIS_MODULE;
++ aud_entry->write_proc = aud_proc_write;
++ aud_entry->read_proc = aud_proc_read;
++ aud_entry->data = NULL;
++
++ return 0;
++}
++
++static void __exit aud_proc_exit(void)
++{
++ remove_proc_entry(AUD_PROC_ENTRY, NULL);
++}
++#endif//CONFIG_AUDIO_CODEC_PROCFS
++
++
++static int __init smdk6400_init(void)
++{
++ int ret;
++
++ smdk6400_snd_device = platform_device_alloc("soc-audio", -1);
++ if (!smdk6400_snd_device)
++ return -ENOMEM;
++
++ platform_set_drvdata(smdk6400_snd_device, &smdk6400_snd_devdata);
++ smdk6400_snd_devdata.dev = &smdk6400_snd_device->dev;
++ ret = platform_device_add(smdk6400_snd_device);
++
++ if (ret)
++ platform_device_put(smdk6400_snd_device);
++#ifdef CONFIG_AUDIO_CODEC_PROCFS
++ if (aud_proc_init()) ;
++#endif//CONFIG_AUDIO_CODEC_PROCFS
++
++
++ return ret;
++}
++
++static void __exit smdk6400_exit(void)
++{
++ platform_device_unregister(smdk6400_snd_device);
++}
++
++module_init(smdk6400_init);
++module_exit(smdk6400_exit);
++
++/* Module information */
++MODULE_AUTHOR("Graeme Gregory, graeme.gregory@wolfsonmicro.com, www.wolfsonmicro.com");
++MODULE_DESCRIPTION("ALSA SoC WM8987 Neo1973");
++MODULE_LICENSE("GPL");
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/defconfig b/recipes/linux/linux-2.6.24/smartq5/defconfig
new file mode 100644
index 0000000000..e71e588314
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/defconfig
@@ -0,0 +1,1624 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24.7
+# Thu Aug 6 11:55:46 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=13
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_UID16 is not set
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_BUG is not set
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_S3C2410=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+CONFIG_PLAT_S3C64XX=y
+CONFIG_S3C64XX_DMA=y
+# CONFIG_S3C64XX_ADC is not set
+CONFIG_PLAT_S3C=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_WATCHDOG is not set
+CONFIG_S3C_BOOT_ERROR_RESET=y
+
+#
+# Power management
+#
+# CONFIG_S3C2410_PM_DEBUG is not set
+# CONFIG_S3C2410_PM_CHECK is not set
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+CONFIG_MACH_SMDK=y
+
+#
+# S3C2400 Machines
+#
+
+#
+# S3C2410 Machines
+#
+# CONFIG_ARCH_SMDK2410 is not set
+# CONFIG_ARCH_H1940 is not set
+# CONFIG_MACH_N30 is not set
+# CONFIG_ARCH_BAST is not set
+# CONFIG_MACH_OTOM is not set
+# CONFIG_MACH_AML_M5900 is not set
+# CONFIG_MACH_VR1000 is not set
+# CONFIG_MACH_QT2410 is not set
+
+#
+# S3C2412 Machines
+#
+# CONFIG_MACH_SMDK2413 is not set
+# CONFIG_MACH_SMDK2412 is not set
+# CONFIG_MACH_VSTMS is not set
+
+#
+# S3C2440 Machines
+#
+# CONFIG_MACH_ANUBIS is not set
+# CONFIG_MACH_OSIRIS is not set
+# CONFIG_MACH_RX3715 is not set
+# CONFIG_ARCH_S3C2440 is not set
+# CONFIG_MACH_NEXCODER_2440 is not set
+
+#
+# S3C2442 Machines
+#
+
+#
+# S3C2443 Machines
+#
+# CONFIG_MACH_SMDK2443 is not set
+
+#
+# S3C2450 Machines
+#
+# CONFIG_MACH_SMDK2450 is not set
+
+#
+# S3C2416 Machines
+#
+# CONFIG_MACH_SMDK2416 is not set
+
+#
+# S3C6400 Machines
+#
+# CONFIG_MACH_SMDK6400 is not set
+
+#
+# S3C6410 Machines
+#
+CONFIG_MACH_SMDK6410=y
+# CONFIG_MACH_SMDK6430 is not set
+CONFIG_S3C6410_PDFW=m
+CONFIG_S3C6410_PDFW_PROC=y
+CONFIG_S3C6410_KDPMD=m
+CONFIG_CPU_S3C6410=y
+CONFIG_S3C6410_PM=y
+
+#
+# S5PC100 Machines
+#
+# CONFIG_MACH_SMDKC100 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+CONFIG_ISA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+CONFIG_NO_IDLE_HZ=y
+CONFIG_HZ=200
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rootwait splash"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=m
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+CONFIG_APM_EMULATION=m
+
+#
+# DVFS support
+#
+CONFIG_S3C64XX_DVFS=m
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RCSIMPLE=y
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_SMARTQ5_ENCRYPT=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+# CONFIG_AX88796 is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=m
+# CONFIG_SMC911X is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+CONFIG_MARVELL_8686_SDIO=m
+CONFIG_MARVELL_8686_PROC_FS=y
+CONFIG_MARVELL_8686_DEBUG=y
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_RT2X00 is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYPAD_S3C=m
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+CONFIG_INPUT_TABLET=y
+# CONFIG_TABLET_USB_ACECAD is not set
+# CONFIG_TABLET_USB_AIPTEK is not set
+# CONFIG_TABLET_USB_GTCO is not set
+# CONFIG_TABLET_USB_KBTAB is not set
+# CONFIG_TABLET_USB_WACOM is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_S3C=y
+# CONFIG_TOUCHSCREEN_NEW is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_S3C2410 is not set
+CONFIG_SERIAL_S3C6400=y
+CONFIG_SERIAL_S3C64XX_CONSOLE=y
+# CONFIG_SERIAL_S3C64XX_HS_UART is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_S3C_ADC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_S3C_MEM=y
+CONFIG_LCD_4=y
+# CONFIG_LCD_7 is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ELEKTOR is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+CONFIG_I2C_S3C64XX=y
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=m
+CONFIG_APM_POWER=m
+# CONFIG_BATTERY_DS2760 is not set
+CONFIG_HWMON=m
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_S3C2410_WATCHDOG=y
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_VIDEO_V4L2 is not set
+# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_SAMSUNG is not set
+# CONFIG_VIDEO_SAMSUNG_TVENC is not set
+# CONFIG_VIDEO_SAMSUNG_TVSCALER is not set
+# CONFIG_V4L_USB_DRIVERS is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_RADIO_CADET is not set
+# CONFIG_RADIO_RTRACK is not set
+# CONFIG_RADIO_RTRACK2 is not set
+# CONFIG_RADIO_AZTECH is not set
+# CONFIG_RADIO_GEMTEK is not set
+# CONFIG_RADIO_SF16FMI is not set
+# CONFIG_RADIO_SF16FMR2 is not set
+# CONFIG_RADIO_TERRATEC is not set
+# CONFIG_RADIO_TRUST is not set
+# CONFIG_RADIO_TYPHOON is not set
+# CONFIG_RADIO_ZOLTRIX is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_S3C=y
+# CONFIG_FB_S3C_LTE480WV is not set
+# CONFIG_FB_S3C_LTV350QV is not set
+# CONFIG_FB_S3C_LTS222QV is not set
+# CONFIG_FB_S3C_A070VW04 is not set
+CONFIG_FB_S3C_TD043MTEX=y
+CONFIG_FB_S3C_BPP=y
+# CONFIG_FB_S3C_BPP_8 is not set
+CONFIG_FB_S3C_BPP_16=y
+# CONFIG_FB_S3C_BPP_24 is not set
+# CONFIG_FB_S3C_BPP_32 is not set
+CONFIG_FB_S3C_NUM=1
+# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set
+# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_S3C2410 is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+# CONFIG_BACKLIGHT_CORGI is not set
+CONFIG_BACKLIGHT_SMDK=m
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=m
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# System on Chip audio support
+#
+CONFIG_SND_SOC=y
+CONFIG_SND_S3C_SOC=y
+
+#
+# SoC Audio for the Samsung S3C
+#
+CONFIG_SND_S3C6410_SOC_I2S_V32=y
+# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713 is not set
+# CONFIG_SND_S3C6410_SOC_AC97 is not set
+# CONFIG_SND_S3C6410_SOC_SMDK6410_WM8580 is not set
+CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8987=y
+CONFIG_AUDIO_CODEC_PROCFS=y
+# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set
+CONFIG_SND_SOC_WM8987=y
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+CONFIG_HID_DEBUG=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_PERSIST is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+CONFIG_USB_S3C_OTG_HOST=m
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+# CONFIG_USB_STORAGE_DPCM is not set
+CONFIG_USB_STORAGE_USBAT=y
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_AIRPRIME is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_OPTION=m
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_JZ4755 is not set
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C_FS is not set
+# CONFIG_USB_GADGET_S3C_HS is not set
+CONFIG_USB_GADGET_S3C_OTGD_HS=y
+CONFIG_USB_S3C=y
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+
+#
+# NOTE: S3C OTG device role enables the controller driver below
+#
+CONFIG_USB_S3C_OTGD_HS=y
+CONFIG_USB_GADGET_S3C_OTGD_HS_DMA_MODE=y
+# CONFIG_USB_GADGET_S3C_OTGD_HS_SLAVE_MODE is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_SDIO_UART=m
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_HSMMC_S3C=y
+CONFIG_USE_MMC_AS_ROOT=y
+CONFIG_HSMMC_S3C_IRQ_WORKAROUND=y
+CONFIG_HSMMC_SCATTERGATHER=y
+# CONFIG_S3CMMC_DEBUG is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_S3C24XX is not set
+CONFIG_LEDS_GPIO=m
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_S3C=y
+
+#
+# Pulse Width Modulation Timer
+#
+CONFIG_PWM=y
+CONFIG_S3C6410_PWM=y
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="cp437"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_AUFS=y
+
+#
+# These options are for 2.6.24.7
+#
+CONFIG_AUFS_BRANCH_MAX_127=y
+# CONFIG_AUFS_BRANCH_MAX_511 is not set
+# CONFIG_AUFS_BRANCH_MAX_1023 is not set
+# CONFIG_AUFS_BRANCH_MAX_32767 is not set
+CONFIG_AUFS_SYSAUFS=y
+# CONFIG_AUFS_HINOTIFY is not set
+
+#
+# EXPORTFS and AUFS_EXPORT are disabled
+#
+# CONFIG_AUFS_ROBR is not set
+# CONFIG_AUFS_DLGT is not set
+# CONFIG_AUFS_SHWH is not set
+CONFIG_AUFS_RR_SQUASHFS=y
+
+#
+# SECURITY and AUFS_SEC_PERM_PATCH are disabled
+#
+# CONFIG_AUFS_SPLICE_PATCH is not set
+# CONFIG_AUFS_LHASH_PATCH is not set
+
+#
+# NFS_V4 and AUFS_PUT_FILP_PATCH are disabled
+#
+# CONFIG_AUFS_WORKAROUND_FUSE is not set
+# CONFIG_AUFS_DEBUG is not set
+# CONFIG_AUFS_COMPAT is not set
+# CONFIG_AUFS_UNIONFS23_PATCH is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_NFS_DIRECTIO=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_S3C_UART=0
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=m
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=m
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0001-Mer-keymappings-change.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0001-Mer-keymappings-change.patch
new file mode 100644
index 0000000000..a95ff35c04
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0001-Mer-keymappings-change.patch
@@ -0,0 +1,66 @@
+From 8dd9e60b445d8e002fdf3b4da5199a54ac87c422 Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 09:24:12 +0000
+Subject: [PATCH 01/13] Mer: keymappings change
+
+---
+ arch/arm/mach-s3c6410/mach-smdk6410.c | 12 ++++++------
+ 1 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
+index 74dadd1..bdcfc59 100644
+--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
++++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
+@@ -299,21 +299,21 @@ static struct gpio_keys_button hhmid_buttons[] = {
+ #if defined (CONFIG_LCD_4)
+ {
+ .gpio = S3C_GPN2, //32*16 + 2
+- .code = KEY_PAGEDOWN,
++ .code = 196,
+ .desc = "Button 0",
+ .active_low = 1,
+ .debounce_interval = 5,
+ },
+ {
+ .gpio = S3C_GPN12,
+- .code = KEY_PAGEUP,
++ .code = 197,
+ .desc = "Button 3",
+ .active_low = 1,
+ .debounce_interval = 5,
+ },
+ {
+ .gpio = S3C_GPN15,
+- .code = KEY_LEFTALT,
++ .code = 195,
+ .desc = "Button 4",
+ .active_low = 1,
+ .debounce_interval = 5,
+@@ -321,21 +321,21 @@ static struct gpio_keys_button hhmid_buttons[] = {
+ #else
+ {
+ .gpio = S3C_GPN4,
+- .code = KEY_PAGEUP,
++ .code = KEY_F7,
+ .desc = "Button 0",
+ .active_low = 1,
+ .debounce_interval = 5,
+ },
+ {
+ .gpio = S3C_GPN3,
+- .code = KEY_PAGEDOWN,
++ .code = KEY_F8,
+ .desc = "Button 1",
+ .active_low = 1,
+ .debounce_interval = 5,
+ },
+ {
+ .gpio = S3C_GPN2, //32*16 + 2
+- .code = KEY_LEFTALT,
++ .code = KEY_F6,
+ .desc = "Button 2",
+ .active_low = 1,
+ .debounce_interval = 5,
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0002-no-DM9000.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0002-no-DM9000.patch
new file mode 100644
index 0000000000..c08915dce6
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0002-no-DM9000.patch
@@ -0,0 +1,25 @@
+From 34c76c67a3f790ff87a0111eee31ffb967b1ae78 Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 09:26:30 +0000
+Subject: [PATCH 02/13] no DM9000
+
+---
+ arch/arm/mach-s3c6410/mach-smdk6410.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
+index 74dadd1..6e3c2ec 100644
+--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
++++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
+@@ -434,7 +434,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
+ &s3c_device_g3d,
+ &s3c_device_rotator,
+ #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+- &s3c_device_dm9000,
++// &s3c_device_dm9000,
+ #endif
+ };
+
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0003-Mer-WPA-fix.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0003-Mer-WPA-fix.patch
new file mode 100644
index 0000000000..4d7228d1b7
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0003-Mer-WPA-fix.patch
@@ -0,0 +1,27 @@
+From 5884edb0b88bd1cad2c39ad7e88786c0fd1fbd09 Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 09:28:34 +0000
+Subject: [PATCH 03/13] Mer: WPA fix
+
+---
+ drivers/net/wireless/marvell8686/wlan_wext.c | 4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/net/wireless/marvell8686/wlan_wext.c b/drivers/net/wireless/marvell8686/wlan_wext.c
+index 85ee593..adef3ab 100644
+--- a/drivers/net/wireless/marvell8686/wlan_wext.c
++++ b/drivers/net/wireless/marvell8686/wlan_wext.c
+@@ -2567,7 +2567,9 @@ wlan_get_range(struct net_device *dev, struct iw_request_info *info,
+ range->throughput = 5000 * 1000;
+ else
+ range->throughput = 1500 * 1000;
+-
++ range->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 |
++ IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP;
++
+ range->min_rts = MRVDRV_RTS_MIN_VALUE;
+ range->max_rts = MRVDRV_RTS_MAX_VALUE;
+ range->min_frag = MRVDRV_FRAG_MIN_VALUE;
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0004-Mer-hardwire-USB-OTG-gadget-type.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0004-Mer-hardwire-USB-OTG-gadget-type.patch
new file mode 100644
index 0000000000..325a12c81b
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0004-Mer-hardwire-USB-OTG-gadget-type.patch
@@ -0,0 +1,25 @@
+From 1f8979f17ddd3af08784d10171328a06dbb19181 Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 09:30:08 +0000
+Subject: [PATCH 04/13] Mer: hardwire USB OTG gadget type
+
+---
+ drivers/usb/gadget/Kconfig | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
+index f71d038..31888dc 100644
+--- a/drivers/usb/gadget/Kconfig
++++ b/drivers/usb/gadget/Kconfig
+@@ -307,7 +307,7 @@ config USB_GADGET_S3C_OTGD_HS
+
+ config USB_S3C
+ tristate
+- depends on USB_GADGET_S3C_FS || USB_GADGET_S3C_HS || USB_GADGET_S3C_OTGD_HS
++ depends on USB_GADGET_S3C_OTGD_HS
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0005-backlight-parameter-and-fixes.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0005-backlight-parameter-and-fixes.patch
new file mode 100644
index 0000000000..c50e721c54
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0005-backlight-parameter-and-fixes.patch
@@ -0,0 +1,67 @@
+From 64d9ed38c8e6c71ffdbc4640ae38cca3dbcbe782 Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 09:31:09 +0000
+Subject: [PATCH 05/13] backlight parameter and fixes
+
+---
+ drivers/video/s3c/s3cfb.c | 14 +++++++++++++-
+ 1 files changed, 13 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/video/s3c/s3cfb.c b/drivers/video/s3c/s3cfb.c
+index 19ab25f..b854645 100644
+--- a/drivers/video/s3c/s3cfb.c
++++ b/drivers/video/s3c/s3cfb.c
+@@ -14,6 +14,7 @@
+ */
+
+ #include <linux/module.h>
++#include <linux/moduleparam.h>
+ #include <linux/kernel.h>
+ #include <linux/errno.h>
+ #include <linux/string.h>
+@@ -40,8 +41,10 @@
+
+ #include "s3cfb.h"
+
+-//#define CONFIG_FB_COLORBAR 1
++/*
++#define CONFIG_FB_COLORBAR 1
+ #include "colorbar.c"
++*/
+
+ /*
+ * Globals
+@@ -270,7 +273,10 @@ static int s3cfb_blank(int blank_mode, struct fb_info *info)
+ switch (blank_mode) {
+ case VESA_NO_BLANKING: /* lcd on, backlight on */
+ if(!backlight_power)
++ {
+ s3cfb_set_backlight_power(1);
++ s3cfb_set_lcd_power(1);
++ }
+ break;
+
+ case VESA_VSYNC_SUSPEND: /* lcd on, backlight off */
+@@ -923,6 +929,10 @@ static int __init s3cfb_probe(struct platform_device *pdev)
+
+ s3cfb_set_par(&(s3c_fb_info[0].fb));
+ mdelay(10);
++
++ if(backlight_level != S3C_FB_MIN_BACKLIGHT_LEVEL)
++ s3cfb_set_backlight_level(backlight_level);
++
+ //draw_colorbar(&(s3c_fb_info[0].fb));
+
+ return 0;
+@@ -1004,6 +1014,8 @@ static void __exit s3cfb_cleanup(void)
+ module_init(s3cfb_init);
+ module_exit(s3cfb_cleanup);
+
++module_param_named(backlight, backlight_level, int, 0);
++
+ MODULE_AUTHOR("Jinsung Yang");
+ MODULE_DESCRIPTION("S3C Framebuffer Driver");
+ MODULE_LICENSE("GPL");
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0006-tv-encoder.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0006-tv-encoder.patch
new file mode 100644
index 0000000000..624b9c317e
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0006-tv-encoder.patch
@@ -0,0 +1,2624 @@
+From 002a069a3a52b8a2286e8c559a2d3d9a0a954501 Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 11:32:58 +0000
+Subject: [PATCH 06/13] tv encoder
+
+---
+ drivers/media/video/Kconfig | 16 +
+ drivers/media/video/samsung/Makefile | 2 +
+ drivers/media/video/samsung/s3c-tvenc.c | 1479 ++++++++++++++++++++++++++++
+ drivers/media/video/samsung/s3c-tvenc.h | 165 +++
+ drivers/media/video/samsung/s3c-tvscaler.c | 802 +++++++++++++++
+ drivers/media/video/samsung/s3c-tvscaler.h | 96 ++
+ 6 files changed, 2560 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/media/video/samsung/s3c-tvenc.c
+ create mode 100644 drivers/media/video/samsung/s3c-tvenc.h
+ create mode 100644 drivers/media/video/samsung/s3c-tvscaler.c
+ create mode 100644 drivers/media/video/samsung/s3c-tvscaler.h
+
+diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
+index 6506263..8797184 100644
+--- a/drivers/media/video/Kconfig
++++ b/drivers/media/video/Kconfig
+@@ -545,6 +545,22 @@ config VIDEO_ADV7180
+
+ endchoice
+
++config VIDEO_SAMSUNG_TVENC
++ tristate "Samsung TV encoder"
++ depends on I2C && VIDEO_V4L2
++ help
++ Samsung encoder
++
++ To compile this driver as a module, choose M here
++
++config VIDEO_SAMSUNG_TVSCALER
++ tristate "Samsung TV scaler"
++ depends on I2C && VIDEO_V4L2
++ help
++ Samsung TV scaler
++
++ To compile this driver as a module, choose M here
++
+
+ config VIDEO_VINO
+ tristate "SGI Vino Video For Linux (EXPERIMENTAL)"
+diff --git a/drivers/media/video/samsung/Makefile b/drivers/media/video/samsung/Makefile
+index 885512c..ede0269 100644
+--- a/drivers/media/video/samsung/Makefile
++++ b/drivers/media/video/samsung/Makefile
+@@ -7,3 +7,5 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5K4BA) += 4xa_sensor.o
+ obj-$(CONFIG_VIDEO_ADV7180) += adv7180.o
+ obj-$(CONFIG_VIDEO_APTINA_MT9P012) += mt9p012.o
+
++obj-$(CONFIG_VIDEO_SAMSUNG_TVENC) += s3c_tvenc.o
++obj-$(CONFIG_VIDEO_SAMSUNG_TVSCALER) += s3c_tvenc.o
+diff --git a/drivers/media/video/samsung/s3c-tvenc.c b/drivers/media/video/samsung/s3c-tvenc.c
+new file mode 100644
+index 0000000..11dfd37
+--- /dev/null
++++ b/drivers/media/video/samsung/s3c-tvenc.c
+@@ -0,0 +1,1479 @@
++
++/*
++ * linux/drivers/tvenc/s3c-tvenc.c
++ *
++ * Revision 1.0
++ *
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C TV Encoder driver
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h> /* error codes */
++#include <asm/div64.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++#include <asm/arch/map.h>
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,16)
++#include <linux/config.h>
++#include <asm/arch/registers.h>
++#include <linux/videodev2.h>
++#else
++#include <asm/arch/regs-tvenc.h>
++#include <asm/arch/regs-lcd.h>
++#include <media/v4l2-common.h>
++#endif
++
++#include "s3c-tvenc.h"
++
++#define PFX "s3c_tvenc"
++
++static struct clk *tvenc_clock;
++static struct clk *h_clk;
++static int s3c_tvenc_irq = NO_IRQ;
++static struct resource *s3c_tvenc_mem;
++static void __iomem *base;
++static wait_queue_head_t waitq;
++static tv_out_params_t tv_param = {0,};
++
++/* Backup SFR value */
++static u32 backup_reg[2];
++
++
++/* Structure that declares the access functions*/
++
++static void s3c_tvenc_switch(tv_enc_switch_t sw)
++{
++ if(sw == OFF) {
++ __raw_writel(__raw_readl(base + S3C_TVCTRL)
++ &~ S3C_TVCTRL_ON, base + S3C_TVCTRL);
++ } else if(sw == ON) {
++ __raw_writel(__raw_readl(base + S3C_TVCTRL)
++ | S3C_TVCTRL_ON, base + S3C_TVCTRL);
++ } else
++ printk("Error func:%s line:%d\n", __FUNCTION__, __LINE__);
++}
++
++static void s3c_tvenc_set_image_size(u32 width, u32 height)
++{
++ __raw_writel(IIS_WIDTH(width)| IIS_HEIGHT(height),
++ base + S3C_INIMAGESIZE);
++}
++
++#if 0
++static void s3c_tvenc_enable_macrovision(tv_standard_t tvmode, macro_pattern_t pattern)
++{
++ switch(pattern) {
++ case AGC4L :
++ break;
++ case AGC2L :
++ break;
++ case N01 :
++ break;
++ case N02 :
++ break;
++ case P01 :
++ break;
++ case P02 :
++ break;
++ default :
++ break;
++ }
++}
++
++static void s3c_tvenc_disable_macrovision(void)
++{
++ __raw_writel(__raw_readl(base + S3C_MACROVISION0)
++ &~0xff, base + S3C_MACROVISION0);
++}
++#endif
++
++static void s3c_tvenc_set_tv_mode(tv_standard_t mode, tv_conn_type_t out)
++{
++ u32 signal_type = 0, output_type = 0;
++
++ switch(mode) {
++ case PAL_N :
++ __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_ON,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_26|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_PAL,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_PAL,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case PAL_NC :
++ case PAL_BGHID :
++ __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_OFF,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_26|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_PAL,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_PAL,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case NTSC_443 :
++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_ON,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_26|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_NTSC,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_NTSC,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case NTSC_J :
++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_OFF,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_21|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_NTSC,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_NTSC,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case PAL_M :
++ case NTSC_M :
++ default :
++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_ON,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_21|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_NTSC,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_NTSC,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ }
++
++ if(out == S_VIDEO) {
++ __raw_writel(YFB_YBW_60|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ output_type = S3C_TVCTRL_OUTTYPE_S;
++ } else
++ output_type = S3C_TVCTRL_OUTTYPE_C;
++
++ switch(mode) {
++ case NTSC_M :
++ signal_type = S3C_TVCTRL_OUTFMT_NTSC_M;
++ break;
++ case NTSC_J :
++ signal_type = S3C_TVCTRL_OUTFMT_NTSC_J;
++ break;
++ case PAL_BGHID :
++ signal_type = S3C_TVCTRL_OUTFMT_PAL_BDG;
++ break;
++ case PAL_M :
++ signal_type = S3C_TVCTRL_OUTFMT_PAL_M;
++ break;
++ case PAL_NC :
++ signal_type = S3C_TVCTRL_OUTFMT_PAL_NC;
++ break;
++ default:
++ printk("s3c_tvenc_set_tv_mode : No matching signal_type!\n");
++ break;
++ }
++
++ __raw_writel((__raw_readl(base + S3C_TVCTRL)
++ &~(0x1f<<4))| output_type | signal_type,
++ base + S3C_TVCTRL);
++
++ __raw_writel(0x01, base + S3C_FSCAUXCTRL);
++}
++
++#if 0
++static void s3c_tvenc_set_pedestal(tv_enc_switch_t sw)
++{
++ if(sw)
++ __raw_writel(EPC_PED_ON, base + S3C_PEDCTRL);
++ else
++ __raw_writel(EPC_PED_OFF, base + S3C_PEDCTRL);
++}
++
++static void s3c_tvenc_set_sub_carrier_freq(u32 freq)
++{
++ __raw_writel(FSC_CTRL(freq), base + S3C_FSCCTRL);
++}
++
++static void s3c_tvenc_set_fsc_dto(u32 val)
++{
++ unsigned int temp;
++
++ temp = (0x1<<31)|(val&0x7fffffff);
++ __raw_writel(temp, base + S3C_FSCDTOMANCTRL);
++}
++
++static void s3c_tvenc_disable_fsc_dto(void)
++{
++ __raw_writel(__raw_readl(base + S3C_FSCDTOMANCTRL)&~(1<<31),
++ base + S3C_FSCDTOMANCTRL);
++}
++
++static void s3c_tvenc_set_bg(u32 soft_mix, u32 color, u32 lum_offset)
++{
++ unsigned int bg_color;
++ switch(color) {
++ case 0 :
++ bg_color = BGC_BGCS_BLACK;
++ break;
++ case 1 :
++ bg_color = BGC_BGCS_BLUE;
++ break;
++ case 2 :
++ bg_color = BGC_BGCS_RED;
++ break;
++ case 3 :
++ bg_color = BGC_BGCS_MAGENTA;
++ break;
++ case 4 :
++ bg_color = BGC_BGCS_GREEN;
++ break;
++ case 5 :
++ bg_color = BGC_BGCS_CYAN;
++ break;
++ case 6 :
++ bg_color = BGC_BGCS_YELLOW;
++ break;
++ case 7 :
++ bg_color = BGC_BGCS_WHITE;
++ break;
++ }
++ if(soft_mix)
++ __raw_writel(BGC_SME_ENA|bg_color|BGC_BGYOFS(lum_offset),
++ base + S3C_BGCTRL);
++ else
++ __raw_writel(BGC_SME_DIS|bg_color|BGC_BGYOFS(lum_offset),
++ base + S3C_BGCTRL);
++
++}
++
++static void s3c_tvenc_set_bg_vav_hav(u32 hav_len, u32 vav_len, u32 hav_st, u32 vav_st)
++{
++ __raw_writel(BVH_BG_HL(hav_len)|BVH_BG_HS(hav_st)|BVH_BG_VL(vav_len)|BVH_BG_VS(vav_st),
++ base + S3C_BGHVAVCTRL);
++}
++#endif
++
++static void s3c_tvenc_set_hue_phase(u32 phase_val)
++{
++ __raw_writel(HUE_CTRL(phase_val),
++ base + S3C_HUECTRL);
++}
++
++#if 0
++static u32 s3c_tvenc_get_hue_phase(void)
++{
++ return __raw_readl(base + S3C_HUECTRL)&0xff;
++}
++#endif
++
++static void s3c_tvenc_set_contrast(u32 contrast)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CONTRABRIGHT);
++
++ __raw_writel((temp &~0xff)|contrast,
++ base + S3C_CONTRABRIGHT);
++}
++
++#if 0
++static u32 s3c_tvenc_get_contrast(void)
++{
++ return (__raw_readl(base + S3C_CONTRABRIGHT)&0xff);
++}
++#endif
++
++static void s3c_tvenc_set_bright(u32 bright)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CONTRABRIGHT);
++
++ __raw_writel((temp &~(0xff<<16))| (bright<<16),
++ base + S3C_CONTRABRIGHT);
++}
++
++#if 0
++static u32 s3c_tvenc_get_bright(void)
++{
++ return ((__raw_readl(base + S3C_CONTRABRIGHT)&(0xff<<16))>>16);
++}
++
++
++static void s3c_tvenc_set_cbgain(u32 cbgain)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CBCRGAINCTRL);
++
++ __raw_writel((temp &~0xff)|cbgain,
++ base + S3C_CBCRGAINCTRL);
++}
++
++
++static u32 s3c_tvenc_get_cbgain(void)
++{
++ return (__raw_readl(base + S3C_CBCRGAINCTRL)&0xff);
++}
++
++static void s3c_tvenc_set_crgain(u32 crgain)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CBCRGAINCTRL);
++
++ __raw_writel((temp &~(0xff<<16))| (crgain<<16),
++ base + S3C_CBCRGAINCTRL);
++}
++
++static u32 s3c_tvenc_get_crgain(void)
++{
++ return ((__raw_readl(base + S3C_CBCRGAINCTRL)&(0xff<<16))>>16);
++}
++#endif
++
++static void s3c_tvenc_enable_gamma_control(tv_enc_switch_t enable)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_GAMMACTRL);
++ if(enable == ON)
++ temp |= (1<<12);
++ else
++ temp &= ~(1<<12);
++
++ __raw_writel(temp, base + S3C_GAMMACTRL);
++}
++
++static void s3c_tvenc_set_gamma_gain(u32 ggain)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_GAMMACTRL);
++
++ __raw_writel((temp &~(0x7<<8))| (ggain<<8),
++ base + S3C_GAMMACTRL);
++}
++
++#if 0
++static u32 s3c_tvenc_get_gamma_gain(void)
++{
++ return ((__raw_readl(base + S3C_GAMMACTRL)&(0x7<<8))>>8);
++}
++
++static void s3c_tvenc_enable_mute_control(tv_enc_switch_t enable)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_GAMMACTRL);
++ if(enable == ON)
++ temp |= (1<<12);
++ else
++ temp &= ~(1<<12);
++
++ __raw_writel(temp, base + S3C_GAMMACTRL);
++}
++
++static void s3c_tvenc_set_mute(u32 y, u32 cb, u32 cr)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_MUTECTRL);
++
++ temp &=~(0xffffff<<8);
++ temp |= (cr & 0xff)<<24;
++ temp |= (cb & 0xff)<<16;
++ temp |= (y & 0xff)<<8;
++
++ __raw_writel(temp, base + S3C_MUTECTRL);
++}
++
++static void s3c_tvenc_get_mute(u32 *y, u32 *cb, u32 *cr)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_MUTECTRL);
++
++ *y = (temp&(0xff<<8))>>8;
++ *cb = (temp&(0xff<<16))>>16;
++ *cr = (temp&(0xff<<24))>>24;
++}
++#endif
++
++static void s3c_tvenc_get_active_win_center(u32 *vert, u32 *horz)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_HENHOFFSET);
++
++ *vert = (temp&(0x3f<<24))>>24;
++ *horz = (temp&(0xff<<16))>>16;
++}
++
++static void s3c_tvenc_set_active_win_center(u32 vert, u32 horz)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_HENHOFFSET);
++
++ temp &=~(0x3ffff<<16);
++ temp |= (vert&0x3f)<<24;
++ temp |= (horz&0xff)<<16;
++
++ __raw_writel(temp, base + S3C_HENHOFFSET);
++}
++
++// LCD display controller configuration functions
++static void s3c_lcd_set_output_path(lcd_local_output_t out)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_set_output_path(out);
++#else // peter for 2.6.24 kernel
++ s3cfb_set_output_path(out);
++#endif
++}
++
++static void s3c_lcd_set_clkval(u32 clkval)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_set_clkval(clkval);
++#else // peter for 2.6.24 kernel
++ s3cfb_set_clock(clkval);
++#endif
++}
++
++static void s3c_lcd_enable_rgbport(u32 on_off)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_enable_rgbport(on_off);
++#else // peter for 2.6.24 kernel
++ s3cfb_enable_rgbport(on_off);
++#endif
++}
++
++static void s3c_lcd_start(void)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_start_lcd();
++#else // peter for 2.6.24 kernel
++ s3cfb_start_lcd();
++#endif
++}
++
++static void s3c_lcd_stop(void)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_stop_lcd();
++#else // peter for 2.6.24 kernel
++ s3cfb_stop_lcd();
++#endif
++}
++
++
++static void s3c_lcd_set_config(void)
++{
++ backup_reg[0] = __raw_readl(S3C_VIDCON0);
++ backup_reg[1] = __raw_readl(S3C_VIDCON2);
++
++ s3c_lcd_set_output_path(LCD_TVRGB);
++ tv_param.lcd_output_mode = LCD_TVRGB;
++
++ s3c_lcd_set_clkval(4);
++ s3c_lcd_enable_rgbport(1);
++}
++
++static void s3c_lcd_exit_config(void)
++{
++ __raw_writel(backup_reg[0], S3C_VIDCON0);
++ __raw_writel(backup_reg[1], S3C_VIDCON2);
++ tv_param.lcd_output_mode = LCD_RGB;
++}
++
++static int scaler_test_start(void)
++{
++ tv_param.sp.DstFullWidth = 640;
++ tv_param.sp.DstFullHeight= 480;
++ tv_param.sp.DstCSpace = RGB16;
++
++ s3c_tvscaler_config(&tv_param.sp);
++
++ s3c_tvscaler_int_enable(1);
++
++ s3c_tvscaler_start();
++
++ return 0;
++}
++
++static int scaler_test_stop(void)
++{
++ s3c_tvscaler_int_disable();
++
++ return 0;
++}
++
++
++static int tvout_start(void)
++{
++ u32 width, height;
++ tv_standard_t type;
++ tv_conn_type_t conn;
++
++ tv_param.sp.DstFullWidth *= 2; // For TV OUT
++
++ width = tv_param.sp.DstFullWidth;
++ height = tv_param.sp.DstFullHeight;
++ type = tv_param.sig_type;
++ conn = tv_param.connect;
++
++ /* Set TV-SCALER parameter */
++ switch(tv_param.v2.input->type) {
++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
++ tv_param.sp.Mode = FREE_RUN;
++ tv_param.sp.DstCSpace = YCBYCR;
++ /* Display controller setting */
++ s3c_lcd_stop();
++ s3c_lcd_set_config();
++ break;
++ case V4L2_INPUT_TYPE_MSDMA: // MSDMA
++ tv_param.sp.Mode = FREE_RUN;
++ tv_param.sp.DstCSpace = YCBYCR;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ s3c_tvenc_set_tv_mode(type, conn);
++ s3c_tvenc_set_image_size(width, height);
++ s3c_tvenc_switch(ON);
++
++ s3c_tvscaler_config(&tv_param.sp); // for setting DstStartX/Y, DstWidth/Height
++ s3c_tvscaler_set_interlace(1);
++ if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO)
++ s3c_tvscaler_int_disable();
++ else
++ s3c_tvscaler_int_enable(1);
++ s3c_tvscaler_start();
++
++ if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO)
++ s3c_lcd_start();
++
++ return 0;
++}
++
++static int tvout_stop(void)
++{
++
++ s3c_tvscaler_set_interlace(0);
++ s3c_tvscaler_stop_freerun();
++ s3c_tvscaler_int_disable();
++ s3c_tvenc_switch(OFF);
++
++ switch(tv_param.v2.input->type) {
++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
++ /* Display controller setting */
++ s3c_lcd_stop();
++ s3c_lcd_exit_config();
++ s3c_lcd_start();
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++/* ------------------------------------------ V4L2 SUPPORT ----------------------------------------------*/
++/* ------------- In FIFO and MSDMA, v4l2_input supported by S3C TVENC controller ------------------*/
++static struct v4l2_input tvenc_inputs[] = {
++ {
++ .index = 0,
++ .name = "LCD FIFO_OUT",
++ .type = V4L2_INPUT_TYPE_FIFO,
++ .audioset = 1,
++ .tuner = 0, /* ignored */
++ .std = 0,
++ .status = 0,
++ },
++ {
++ .index = 1,
++ .name = "Memory input (MSDMA)",
++ .type = V4L2_INPUT_TYPE_MSDMA,
++ .audioset = 2,
++ .tuner = 0,
++ .std = 0,
++ .status = 0,
++ }
++};
++
++/* ------------ Out FIFO and MADMA, v4l2_output supported by S3C TVENC controller ----------------*/
++static struct v4l2_output tvenc_outputs[] = {
++ {
++ .index = 0,
++ .name = "TV-OUT",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_PAL | V4L2_STD_NTSC_M,
++ },
++ {
++ .index = 1,
++ .name = "Memory output (MSDMA)",
++ .type = V4L2_OUTPUT_TYPE_MSDMA,
++ .audioset = 0,
++ .modulator = 0,
++ .std = 0,
++ },
++
++};
++
++const struct v4l2_fmtdesc tvenc_input_formats[] = {
++ {
++ .index = 0,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .description = "16 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ .flags = FORMAT_FLAGS_PACKED,
++ },
++ {
++ .index = 1,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "24 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB24,
++ },
++ {
++ .index = 2,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:2, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++
++ },
++ {
++ .index = 3,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:0, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ }
++};
++
++
++const struct v4l2_fmtdesc tvenc_output_formats[] = {
++ {
++ .index = 0,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .description = "16 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ .flags = FORMAT_FLAGS_PACKED,
++ },
++ {
++ .index = 1,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "24 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB24,
++ },
++ {
++ .index = 2,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:2, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++
++ },
++ {
++ .index = 3,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:0, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ }
++};
++
++const struct v4l2_standard tvout_standards[] = {
++ {
++ .index = 0,
++ .id = V4L2_STD_NTSC_M,
++ .name = "NTSC type",
++ },
++ {
++ .index = 1,
++ .id = V4L2_STD_PAL,
++ .name = "PAL type",
++ }
++};
++
++#define NUMBER_OF_INPUT_FORMATS ARRAY_SIZE(tvenc_input_formats)
++#define NUMBER_OF_OUTPUT_FORMATS ARRAY_SIZE(tvenc_output_formats)
++#define NUMBER_OF_INPUTS ARRAY_SIZE(tvenc_inputs)
++#define NUMBER_OF_OUTPUTS ARRAY_SIZE(tvenc_outputs)
++#define NUMBER_OF_STANDARDS ARRAY_SIZE(tvout_standards)
++
++static int s3c_tvenc_g_fmt(struct v4l2_format *f)
++{
++ int size = sizeof(struct v4l2_pix_format);
++
++ memset(&f->fmt.pix, 0, size);
++ memcpy(&f->fmt.pix, &tv_param.v2.pixfmt, size);
++
++ return 0;
++}
++
++static int s3c_tvenc_s_fmt(struct v4l2_format *f)
++{
++ /* update our state informations */
++ tv_param.v2.pixfmt= f->fmt.pix;
++
++ // peter LCD output related operation
++ if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_RGB565 ) {
++
++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width;
++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height;
++ tv_param.sp.SrcStartX = 0;
++ tv_param.sp.SrcStartY = 0;
++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth;
++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight;
++
++ printk("TV-OUT: LCD path operation set\n");
++
++ // peter for padded data of mfc output
++ } else if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_YUV420) {
++
++#ifdef DIVX_TEST // padded output
++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width + 2*16;
++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height + 2*16;
++ tv_param.sp.SrcStartX = 16;
++ tv_param.sp.SrcStartY = 16;
++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth - 2*tv_param.sp.SrcStartX;
++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight - 2*tv_param.sp.SrcStartY;
++#else // not padded output
++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width;
++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height;
++ tv_param.sp.SrcStartX = 0;
++ tv_param.sp.SrcStartY = 0;
++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth;
++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight;
++#endif
++
++ printk("TV-OUT: MFC path operation set\n");
++
++ }
++
++ switch(tv_param.v2.pixfmt.pixelformat) {
++ case V4L2_PIX_FMT_RGB565:
++ tv_param.sp.SrcCSpace = RGB16;
++ break;
++ case V4L2_PIX_FMT_RGB24:
++ tv_param.sp.SrcCSpace = RGB24;
++ break;
++ case V4L2_PIX_FMT_YUV420:
++ tv_param.sp.SrcCSpace = YC420;
++ break;
++ case V4L2_PIX_FMT_YUV422P:
++ tv_param.sp.SrcCSpace = YC422;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++// camif_convert_into_camif_cfg_t(cfg, 1);
++ return 0;
++}
++
++static int s3c_tvenc_s_input(int index)
++{
++
++ tv_param.v2.input = &tvenc_inputs[index];
++ switch(tv_param.v2.input->type) {
++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
++ tv_param.sp.InPath = POST_FIFO;
++ break;
++ case V4L2_INPUT_TYPE_MSDMA: // MSDMA
++ tv_param.sp.InPath = POST_DMA;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_s_output(int index)
++{
++ tv_param.v2.output = &tvenc_outputs[index];
++ switch(tv_param.v2.output->type) {
++ case V4L2_OUTPUT_TYPE_ANALOG: // TV-OUT (FIFO-OUT)
++ tv_param.sp.OutPath = POST_FIFO;
++ break;
++ case V4L2_OUTPUT_TYPE_MSDMA: // MSDMA
++ tv_param.sp.OutPath = POST_DMA;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_s_std(v4l2_std_id *id)
++{
++// printk("s3c_tvenc_s_std: *id=0x%x",*id);
++ switch(*id) {
++ case V4L2_STD_NTSC_M:
++ tv_param.sig_type = NTSC_M;
++ tv_param.sp.DstFullWidth = 720;
++ tv_param.sp.DstFullHeight = 480;
++ break;
++ case V4L2_STD_PAL:
++ tv_param.sig_type = PAL_M;
++ tv_param.sp.DstFullWidth = 720;
++ tv_param.sp.DstFullHeight = 576;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_v4l2_control(struct v4l2_control *ctrl)
++{
++ switch(ctrl->id) {
++
++ // peter added for MFC related op.
++ case V4L2_CID_MPEG_STREAM_PID_VIDEO:
++ {
++ tv_param.sp.SrcFrmSt = ctrl->value;
++ return 0;
++ }
++
++ case V4L2_CID_CONNECT_TYPE:
++ {
++ if(ctrl->value == 0) { // COMPOSITE
++ tv_param.connect = COMPOSITE;
++ } else if(ctrl->value == 1) { //S-VIDEO
++ tv_param.connect = S_VIDEO;
++ } else {
++ return -EINVAL;
++ }
++ return 0;
++ }
++
++ case V4L2_CID_BRIGHTNESS:
++ {
++ s32 val = ctrl->value;
++ if((val > 0xff)||(val < 0))
++ return -EINVAL;
++ else
++ s3c_tvenc_set_bright(val);
++
++ return 0;
++ }
++
++ case V4L2_CID_CONTRAST:
++ {
++ s32 val = ctrl->value;
++ if((val > 0xff)||(val < 0))
++ return -EINVAL;
++ else
++ s3c_tvenc_set_contrast(val);
++
++ return 0;
++ }
++
++ case V4L2_CID_GAMMA:
++ {
++ s32 val = ctrl->value;
++ if((val > 0x3)||(val < 0)) {
++ return -EINVAL;
++ } else {
++ s3c_tvenc_enable_gamma_control(ON);
++ s3c_tvenc_set_gamma_gain(val);
++ s3c_tvenc_enable_gamma_control(OFF);
++ }
++ return 0;
++ }
++
++ case V4L2_CID_HUE:
++ {
++ s32 val = ctrl->value;
++ if((val > 0xff)||(val < 0))
++ return -EINVAL;
++ else
++ s3c_tvenc_set_hue_phase(val);
++
++ return 0;
++ }
++
++ case V4L2_CID_HCENTER:
++ {
++ s32 val = ctrl->value;
++ u32 curr_horz, curr_vert;
++
++ if((val > 0xff)||(val < 0)) {
++ return -EINVAL;
++ } else {
++ s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz);
++ s3c_tvenc_set_active_win_center(curr_vert, val);
++ }
++
++ return 0;
++ }
++
++ case V4L2_CID_VCENTER:
++ {
++ s32 val = ctrl->value;
++ u32 curr_horz, curr_vert;
++
++ if((val > 0x3f)||(val < 0)) {
++ return -EINVAL;
++ } else {
++ s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz);
++ s3c_tvenc_set_active_win_center(val, curr_horz);
++ }
++
++ return 0;
++ }
++
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++int s3c_tvenc_open(struct inode *inode, struct file *filp)
++{
++ int err;
++
++ err = video_exclusive_open(inode, filp); // One function of V4l2 driver
++
++ if(err < 0)
++ return err;
++ filp->private_data = &tv_param;
++
++ s3c_tvscaler_init();
++
++ /* Success */
++ return 0;
++}
++
++int s3c_tvenc_release(struct inode *inode, struct file *filp)
++{
++ video_exclusive_release(inode, filp);
++
++ /* Success */
++ return 0;
++}
++
++static int s3c_tvenc_do_ioctl(struct inode *inode,struct file *filp,unsigned int cmd,void *arg)
++{
++ int ret;
++
++ switch(cmd){
++ case VIDIOC_QUERYCAP:
++ {
++ struct v4l2_capability *cap = arg;
++ strcpy(cap->driver, "S3C TV-OUT driver");
++ strlcpy(cap->card, tv_param.v->name, sizeof(cap->card));
++ sprintf(cap->bus_info, "ARM AHB BUS");
++ cap->version = 0;
++ cap->capabilities = tv_param.v->type2;
++ return 0;
++ }
++
++ case VIDIOC_OVERLAY:
++ {
++ int on = *(int *)arg;
++
++ printk("TV-OUT: VIDIOC_OVERLAY on:%d\n", on);
++ if (on != 0) {
++ ret = tvout_start();
++ } else {
++ ret = tvout_stop();
++ }
++ return ret;
++ }
++
++ case VIDIOC_ENUMINPUT:
++ {
++ struct v4l2_input *i = arg;
++ printk("TV-OUT: VIDIOC_ENUMINPUT : index = %d\n", i->index);
++
++ if ((i->index) >= NUMBER_OF_INPUTS) {
++ return -EINVAL;
++ }
++ memcpy(i, &tvenc_inputs[i->index], sizeof(struct v4l2_input));
++ return 0;
++ }
++
++ case VIDIOC_S_INPUT: // 0 -> LCD FIFO-OUT, 1 -> MSDMA
++ {
++ int index = *((int *)arg);
++ printk("TV-OUT: VIDIOC_S_INPUT \n");
++
++ if (index >= NUMBER_OF_INPUTS) {
++ return -EINVAL;
++ }
++ else {
++ s3c_tvenc_s_input(index);
++ return 0;
++ }
++ }
++
++ case VIDIOC_G_INPUT:
++ {
++ u32 *i = arg;
++ printk("TV-OUT: VIDIOC_G_INPUT \n");
++ *i = tv_param.v2.input->type;
++ return 0;
++ }
++
++ case VIDIOC_ENUMOUTPUT:
++ {
++ struct v4l2_output *i = arg;
++ printk("TV-OUT: VIDIOC_ENUMOUTPUT : index = %d\n", i->index);
++
++ if ((i->index) >= NUMBER_OF_OUTPUTS) {
++ return -EINVAL;
++ }
++ memcpy(i, &tvenc_outputs[i->index], sizeof(struct v4l2_output));
++ return 0;
++ }
++
++ case VIDIOC_S_OUTPUT: // 0 -> TV / FIFO , 1 -> MSDMA
++ {
++ int index = *((int *)arg);
++ printk("TV-OUT: VIDIOC_S_OUTPUT \n");
++
++ if (index >= NUMBER_OF_OUTPUTS) {
++ return -EINVAL;
++ }
++ else {
++ s3c_tvenc_s_output(index);
++ return 0;
++ }
++ }
++
++ case VIDIOC_G_OUTPUT:
++ {
++ u32 *i = arg;
++ printk("VIDIOC_G_OUTPUT \n");
++ *i = tv_param.v2.output->type;
++ return 0;
++ }
++
++ case VIDIOC_ENUM_FMT:
++ { struct v4l2_fmtdesc *f = arg;
++ enum v4l2_buf_type type = f->type;
++ int index = f->index;
++
++ printk("C: VIDIOC_ENUM_FMT : index = %d\n", index);
++ if (index >= NUMBER_OF_INPUT_FORMATS)
++ return -EINVAL;
++
++ switch (type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ default:
++ return -EINVAL;
++ }
++ memset(f, 0, sizeof(*f));
++ memcpy(f, tv_param.v2.fmtdesc+index, sizeof(*f));
++ return 0;
++ }
++
++ case VIDIOC_G_FMT:
++ {
++ struct v4l2_format *f = arg;
++ printk("C: VIDIOC_G_FMT \n");
++ ret = s3c_tvenc_g_fmt(f);
++ return ret;
++ }
++
++ case VIDIOC_S_FMT:
++ {
++ struct v4l2_format *f = arg;
++ printk("C: VIDIOC_S_FMT \n");
++ ret = s3c_tvenc_s_fmt(f);
++ if(ret != 0) {
++ printk("s3c_tvenc_set_fmt() failed !\n");
++ return -EINVAL;
++ }
++ return ret;
++ }
++
++ case VIDIOC_S_CTRL:
++ {
++ struct v4l2_control *ctrl = arg;
++ //printk("P: VIDIOC_S_CTRL \n");
++ ret = s3c_tvenc_v4l2_control(ctrl);
++ return ret;
++ }
++
++ case VIDIOC_ENUMSTD:
++ {
++ struct v4l2_standard *e = arg;
++ unsigned int index = e->index;
++
++ if (index >= NUMBER_OF_STANDARDS)
++ return -EINVAL;
++ v4l2_video_std_construct(e, tvout_standards[e->index].id,
++ &tvout_standards[e->index].name);
++ e->index = index;
++ return 0;
++ }
++
++ case VIDIOC_G_STD:
++ {
++ v4l2_std_id *id = arg;
++ *id = tvout_standards[0].id;
++ return 0;
++ }
++
++ case VIDIOC_S_STD:
++ {
++ v4l2_std_id *id = arg;
++ unsigned int i;
++
++ for (i = 0; i < NUMBER_OF_STANDARDS; i++) {
++ //printk("P: *id = %d, tvout_standards[i].id = %d\n", *id, tvout_standards[i].id);
++ if (*id & tvout_standards[i].id)
++ break;
++ }
++ if (i == NUMBER_OF_STANDARDS)
++ return -EINVAL;
++
++ ret = s3c_tvenc_s_std(id);
++ return ret;
++ }
++
++ case VIDIOC_S_TVOUT_ON:
++ {
++ //int *SrcFrmSt = arg;
++ //printk("---peter VIDIOC_S_TVOUT_ON : SrcFrmSt = 0x%08x\n", *SrcFrmSt);
++ ret = tvout_start();
++ return ret;
++ }
++
++ case VIDIOC_S_TVOUT_OFF:
++ {
++ ret = tvout_stop();
++ return ret;
++ }
++
++ case VIDIOC_S_SCALER_TEST:
++ {
++ ret = scaler_test_start();
++ mdelay(1);
++ ret = scaler_test_stop();
++ return ret;
++ }
++
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_ioctl_v4l2(struct inode *inode, struct file *filp, unsigned int cmd,
++ unsigned long arg)
++{
++ return video_usercopy(inode, filp, cmd, arg, s3c_tvenc_do_ioctl);
++}
++
++int s3c_tvenc_read(struct file *filp, char *buf, size_t count,
++ loff_t *f_pos)
++{
++ return 0;
++}
++
++int s3c_tvenc_write(struct file *filp, const char *buf, size_t
++ count, loff_t *f_pos)
++{
++ return 0;
++}
++
++int s3c_tvenc_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++ u32 size = vma->vm_end - vma->vm_start;
++ u32 max_size;
++ u32 page_frame_no;
++
++ page_frame_no = __phys_to_pfn(POST_BUFF_BASE_ADDR);
++
++ max_size = RESERVE_POST_MEM + PAGE_SIZE - (RESERVE_POST_MEM % PAGE_SIZE);
++
++ if(size > max_size) {
++ return -EINVAL;
++ }
++
++ vma->vm_flags |= VM_RESERVED;
++
++ if( remap_pfn_range(vma, vma->vm_start, page_frame_no,
++ size, vma->vm_page_prot)) {
++ printk(KERN_ERR "%s: mmap_error\n", __FUNCTION__);
++ return -EAGAIN;
++
++ }
++
++ return 0;
++}
++
++struct file_operations s3c_tvenc_fops = {
++ .owner = THIS_MODULE,
++ .open = s3c_tvenc_open,
++ .ioctl = s3c_tvenc_ioctl_v4l2,
++ .release = s3c_tvenc_release,
++ .read = s3c_tvenc_read,
++ .write = s3c_tvenc_write,
++ .mmap = s3c_tvenc_mmap,
++};
++
++void s3c_tvenc_vdev_release (struct video_device *vdev) {
++ kfree(vdev);
++}
++
++struct video_device tvencoder = {
++ .name = "TVENCODER",
++ .type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_SCALES,
++ .type2 = V4L2_CAP_VIDEO_OUTPUT| V4L2_CAP_VIDEO_CAPTURE, /* V4L2 */
++ //.hardware = 0x01, // peter for 2.6.24 kernel
++ .fops = &s3c_tvenc_fops,
++ .release = s3c_tvenc_vdev_release,
++ .minor = TVENC_MINOR,
++};
++
++irqreturn_t s3c_tvenc_isr(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ u32 mode;
++
++ mode = __raw_readl(base + S3C_TVCTRL);
++
++ // Clear FIFO under-run status pending bit
++ mode |= (1<<12);
++
++ __raw_writel(mode, base + S3C_TVCTRL);
++
++ wake_up_interruptible(&waitq);
++ return IRQ_HANDLED;
++}
++
++static int s3c_tvenc_probe(struct platform_device *pdev)
++{
++
++ struct resource *res;
++
++ int ret;
++
++ /* find the IRQs */
++ s3c_tvenc_irq = platform_get_irq(pdev, 0);
++ if(s3c_tvenc_irq <= 0) {
++ printk(KERN_ERR PFX "failed to get irq resouce\n");
++ return -ENOENT;
++ }
++
++ /* get the memory region for the tv scaler driver */
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if(res == NULL) {
++ printk(KERN_ERR PFX "failed to get memory region resouce\n");
++ return -ENOENT;
++ }
++
++ s3c_tvenc_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name);
++ if(s3c_tvenc_mem == NULL) {
++ printk(KERN_ERR PFX "failed to reserve memory region\n");
++ return -ENOENT;
++ }
++
++
++ base = ioremap(s3c_tvenc_mem->start, s3c_tvenc_mem->end - res->start + 1);
++ if(s3c_tvenc_mem == NULL) {
++ printk(KERN_ERR PFX "failed ioremap\n");
++ return -ENOENT;
++ }
++
++ tvenc_clock = clk_get(&pdev->dev, "tv_encoder");
++ if(tvenc_clock == NULL) {
++ printk(KERN_ERR PFX "failed to find tvenc clock source\n");
++ return -ENOENT;
++ }
++
++ clk_enable(tvenc_clock);
++
++ h_clk = clk_get(&pdev->dev, "hclk");
++ if(h_clk == NULL) {
++ printk(KERN_ERR PFX "failed to find h_clk clock source\n");
++ return -ENOENT;
++ }
++
++ init_waitqueue_head(&waitq);
++
++ tv_param.v = video_device_alloc();
++ if(!tv_param.v) {
++ printk(KERN_ERR "s3c-tvenc: video_device_alloc() failed\n");
++ return -ENOMEM;
++ }
++ memcpy(tv_param.v, &tvencoder, sizeof(tvencoder));
++ if(video_register_device(tv_param.v, VFL_TYPE_GRABBER, TVENC_MINOR) != 0) {
++ printk("s3c_camera_driver.c : Couldn't register this codec driver.\n");
++ return 0;
++ }
++
++ ret = request_irq(s3c_tvenc_irq, s3c_tvenc_isr, SA_INTERRUPT,
++ "TV_ENCODER", NULL);
++ if (ret) {
++ printk("request_irq(TV_ENCODER) failed.\n");
++ return ret;
++ }
++
++ printk(" Success\n");
++ return 0;
++}
++
++static int s3c_tvenc_remove(struct platform_device *dev)
++{
++ printk(KERN_INFO "s3c_tvenc_remove called !\n");
++ clk_disable(tvenc_clock);
++ free_irq(s3c_tvenc_irq, NULL);
++ if (s3c_tvenc_mem != NULL) {
++ pr_debug("s3-tvenc: releasing s3c_tvenc_mem\n");
++ iounmap(base);
++ release_resource(s3c_tvenc_mem);
++ kfree(s3c_tvenc_mem);
++ }
++// video_unregister_device(tv_param.v);
++ return 0;
++}
++
++static int s3c_tvenc_suspend(struct platform_device *dev, pm_message_t state)
++{
++ clk_disable(tvenc_clock);
++ return 0;
++}
++
++static int s3c_tvenc_resume(struct platform_device *pdev)
++{
++ clk_enable(tvenc_clock);
++ return 0;
++}
++
++static struct platform_driver s3c_tvenc_driver = {
++ .probe = s3c_tvenc_probe,
++ .remove = s3c_tvenc_remove,
++ .suspend = s3c_tvenc_suspend,
++ .resume = s3c_tvenc_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-tvenc",
++ },
++};
++
++static char banner[] __initdata = KERN_INFO "S3C6410 TV encoder Driver, (c) 2008 Samsung Electronics\n";
++
++static int __init s3c_tvenc_init(void)
++{
++
++ printk(banner);
++
++ if(platform_driver_register(&s3c_tvenc_driver) != 0)
++ {
++ printk("Platform Device Register Failed \n");
++ return -1;
++ }
++
++ printk(" S3C6410 TV encoder Driver module init OK. \n");
++ return 0;
++}
++
++static void __exit s3c_tvenc_exit(void)
++{
++
++ video_unregister_device(tv_param.v);
++ platform_driver_unregister(&s3c_tvenc_driver);
++
++ printk("S3C6410 TV encoder Driver module exit. \n");
++}
++
++
++module_init(s3c_tvenc_init);
++module_exit(s3c_tvenc_exit);
++
++
++MODULE_AUTHOR("Peter, Oh");
++MODULE_DESCRIPTION("S3C TV Encoder Device Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/media/video/samsung/s3c-tvenc.h b/drivers/media/video/samsung/s3c-tvenc.h
+new file mode 100644
+index 0000000..30a66a2
+--- /dev/null
++++ b/drivers/media/video/samsung/s3c-tvenc.h
+@@ -0,0 +1,165 @@
++#ifndef __S3CTVENC_H_
++#define __S3CTVENC_H_
++
++#include "s3c-tvscaler.h"
++
++
++#define TVENC_IOCTL_MAGIC 'T'
++
++typedef struct {
++
++} s3c_tvenc_info;
++
++#define TV_ON _IO(TVENC_IOCTL_MAGIC, 0)
++#define TV_OFF _IO(TVENC_IOCTL_MAGIC, 1)
++#define SELECT_TV_OUT_FORMAT _IO(TVENC_IOCTL_MAGIC, 2)
++
++#define TVENC_IOCTL_MAXNR 6
++
++#define TVENC_MINOR 14 // Just some number
++
++typedef enum {
++ OFF,
++ ON
++} tv_enc_switch_t;
++
++typedef enum {
++ NTSC_M,
++ PAL_M,
++ PAL_BGHID,
++ PAL_N,
++ PAL_NC,
++ PAL_60,
++ NTSC_443,
++ NTSC_J
++} tv_standard_t;
++
++typedef enum {
++ QCIF, CIF/*352x288*/,
++ QQVGA, QVGA, VGA, SVGA/*800x600*/, SXGA/*1280x1024*/, UXGA/*1600x1200*/, QXGA/*2048x1536*/,
++ WVGA/*854x480*/, HD720/*1280x720*/, HD1080/*1920x1080*/
++} img_size_t;
++
++typedef enum {
++ BLACKSTRETCH, WHITESTRETCH, BLUESTRETCH
++} stretch_color_t;
++
++typedef enum {
++ COMPOSITE, S_VIDEO
++} tv_conn_type_t;
++
++typedef enum {
++ BLACK, BLUE, RED, MAGENTA, GREEN, CYAN, YELLOW, WHITE
++} bg_color_t;
++
++typedef enum {
++ MUTE_Y, MUTE_CB, MUTE_CR
++} mute_type_t;
++
++typedef enum {
++ AGC4L, AGC2L, N01, N02, P01, P02
++} macro_pattern_t;
++
++typedef enum {
++ LCD_RGB, LCD_TV, LCD_I80F, LCD_I80S,
++ LCD_TVRGB, LCD_TVI80F, LCD_TVI80S
++} lcd_local_output_t;
++
++/* when App want to change v4l2 parameter,
++ * we instantly store it into v4l2_t v2
++ * and then reflect it to hardware
++ */
++typedef struct v4l2 {
++ struct v4l2_fmtdesc *fmtdesc;
++// struct v4l2_framebuffer frmbuf; /* current frame buffer */
++ struct v4l2_pix_format pixfmt;
++ struct v4l2_input *input;
++ struct v4l2_output *output;
++// enum v4l2_status status;
++} v4l2_t;
++
++
++typedef struct {
++ tv_standard_t sig_type;
++ tv_conn_type_t connect;
++ /* Width of input image. The input value is twice original output image
++ * width. For example, you must set 1440 when the image width is 720.
++ * Max value is 1440
++ */
++ unsigned int in_width;
++ /* Height of input image
++ * Max value is 576
++ */
++ unsigned int in_height;
++
++ // Setting value of VIDOUT[28:26] in Display
++ // controller(VIDCON0)
++ lcd_local_output_t lcd_output_mode;
++ // Set CLKVAL_F[13:6] of VIDCON0 with
++ // this value
++ unsigned int lcd_clkval_f;
++
++ // Flag of lcd rgb port
++ // 0 : disable, 1 : enable
++ unsigned int lcd_rgb_port_flag;
++
++ scaler_params_t sp;
++
++ struct video_device *v;
++ v4l2_t v2;
++
++} tv_out_params_t;
++
++#define V4L2_INPUT_TYPE_MSDMA 3
++#define V4L2_INPUT_TYPE_FIFO 4
++#define V4L2_OUTPUT_TYPE_MSDMA 4
++
++#define FORMAT_FLAGS_DITHER 0x01
++#define FORMAT_FLAGS_PACKED 0x02
++#define FORMAT_FLAGS_PLANAR 0x04
++#define FORMAT_FLAGS_RAW 0x08
++#define FORMAT_FLAGS_CrCb 0x10
++
++/****************************************************************
++* struct v4l2_control
++* Control IDs defined by S3C
++*****************************************************************/
++
++/* TV-OUT connector type */
++#define V4L2_CID_CONNECT_TYPE (V4L2_CID_PRIVATE_BASE+0)
++
++/****************************************************************
++* I O C T L C O D E S F O R V I D E O D E V I C E S
++* It's only for S3C
++*****************************************************************/
++#define VIDIOC_S_TVOUT_ON _IO ('V', BASE_VIDIOC_PRIVATE+0)
++#define VIDIOC_S_TVOUT_OFF _IO ('V', BASE_VIDIOC_PRIVATE+1)
++#define VIDIOC_S_SCALER_TEST _IO ('V', BASE_VIDIOC_PRIVATE+3)
++
++
++extern void s3c_tvscaler_config(scaler_params_t * sp);
++extern void s3c_tvscaler_int_enable(unsigned int int_type);
++extern void s3c_tvscaler_int_disable(void);
++extern void s3c_tvscaler_start(void);
++extern void s3c_tvscaler_stop_freerun(void);
++extern void s3c_tvscaler_init(void);
++extern void s3c_tvscaler_set_interlace(unsigned int on_off);
++extern int video_exclusive_release(struct inode * inode, struct file * file);
++extern int video_exclusive_open(struct inode * inode, struct file * file);
++
++#if 0 // peter for 2.6.21 kernel
++extern void s3c_fb_start_lcd(void);
++extern void s3c_fb_stop_lcd(void);
++extern void s3c_fb_set_output_path(int out);
++extern void s3c_fb_set_clkval(unsigned int clkval);
++extern void s3c_fb_enable_rgbport(unsigned int on_off);
++#else // peter for 2.6.24 kernel
++extern void s3cfb_start_lcd(void);
++extern void s3cfb_stop_lcd(void);
++extern void s3cfb_set_output_path(int out);
++extern void s3cfb_set_clock(unsigned int clkval);
++extern void s3cfb_enable_rgbport(unsigned int on_off);
++#endif
++
++
++#endif // __S3CTVENC_H_
+diff --git a/drivers/media/video/samsung/s3c-tvscaler.c b/drivers/media/video/samsung/s3c-tvscaler.c
+new file mode 100644
+index 0000000..376c866
+--- /dev/null
++++ b/drivers/media/video/samsung/s3c-tvscaler.c
+@@ -0,0 +1,802 @@
++
++/*
++ * linux/drivers/tvenc/s3c-tvscaler.c
++ *
++ * Revision 1.0
++ *
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C TV Scaler driver
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h> /* error codes */
++#include <asm/div64.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++#include <asm/arch/map.h>
++#include <linux/miscdevice.h>
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,16)
++#include <linux/config.h>
++#include <asm/arch/registers.h>
++#else
++#include <asm/arch/regs-tvscaler.h>
++#include <asm/arch/regs-s3c6400-clock.h>
++#endif
++
++#include "s3c-tvscaler.h"
++
++#define PFX "s3c_tv_scaler"
++
++#define SINGLE_BUF 1 // Single buffer mode
++
++
++static struct clk *h_clk;
++static struct clk *tvscaler_clock;
++static void __iomem *base;
++static int s3c_tvscaler_irq = NO_IRQ;
++static struct resource *s3c_tvscaler_mem;
++
++
++//static unsigned char *addr_start_y;
++//static unsigned char *addr_start_rgb;
++
++static wait_queue_head_t waitq;
++
++irqreturn_t s3c_tvscaler_isr(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ u32 mode;
++ mode = __raw_readl(base + S3C_MODE);
++ mode &= ~(1 << 6); /* Clear Source in POST Processor */
++ __raw_writel(mode, base + S3C_MODE);
++
++// wake_up_interruptible(&waitq);
++ return IRQ_HANDLED;
++}
++
++#if 0
++static buff_addr_t buf_addr = { NULL };
++
++
++static u32 post_alloc_pre_buff(scaler_params_t *sp)
++{
++ u32 size;
++
++#ifdef USE_DEDICATED_MEM
++
++ buf_addr.pre_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM);
++ buf_addr.pre_virt_addr = ioremap_nocache(buf_addr.pre_phy_addr, PRE_BUFF_SIZE);
++ if( !buf_addr.pre_virt_addr ) {
++ printk(KERN_ERR "%s: Failed to allocate pre buffer \n",__FUNCTION__);
++ return -ENOMEM;
++ }
++
++ sp->SrcFrmSt = buf_addr.pre_phy_addr;
++#else
++ size = sp->SrcWidth * sp->SrcHeight * 2;
++ addr_start_y = kmalloc(size, GFP_DMA);
++ if(addr_start_y != NULL) return -ENOMEM;
++#endif
++ return 0;
++}
++
++static u32 post_alloc_post_buff(scaler_params_t *sp)
++{
++ u32 size;
++
++#ifdef USE_DEDICATED_MEM
++
++ buf_addr.post_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM + PRE_BUFF_SIZE);
++ buf_addr.post_virt_addr = ioremap_nocache(buf_addr.post_phy_addr, POST_BUFF_SIZE);
++ if( !buf_addr.post_virt_addr ) {
++ printk(KERN_ERR "%s: Failed to allocate post buffer \n",__FUNCTION__);
++ return -ENOMEM;
++ }
++
++ sp->DstFrmSt = buf_addr.post_phy_addr;
++#else
++ size = sp->DstWidth * sp->DstHeight * 2;
++ addr_start_rgb = kmalloc(size, GFP_DMA);
++ if(addr_start_rgb != NULL) return -ENOMEM;
++#endif
++ return 0;
++}
++
++static u32 post_free_all_buffer(void)
++{
++#ifdef USE_DEDICATED_MEM
++ if( buf_addr.pre_virt_addr ) {
++ iounmap(buf_addr.pre_virt_addr);
++ }
++ if( buf_addr.post_virt_addr ) {
++ iounmap(buf_addr.post_virt_addr);
++ }
++#endif
++ return 0;
++}
++#endif
++
++static void s3c_tvscaler_set_clk_src(scaler_clk_src_t clk_src)
++{
++ u32 tmp, rate;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ h_clk = clk_get(NULL, "hclk");
++
++ rate = clk_get_rate(h_clk);
++
++ if(clk_src == HCLK) {
++ if(rate > 66000000) {
++ tmp &= ~(0x7f<<23);
++ tmp |= (1<<24);
++ tmp |= (1<<23);
++ } else {
++ tmp &=~ (0x7f<<23);
++ }
++
++ } else if(clk_src == PLL_EXT) {
++ } else {
++ tmp &=~(0x7f<<23);
++ }
++
++ tmp = (tmp &~ (0x3<<21)) | (clk_src<<21);
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++
++static void s3c_tvscaler_set_fmt(cspace_t src, cspace_t dst, s3c_scaler_path_t in,
++ s3c_scaler_path_t out, u32 *in_pixel_size,
++ u32 *out_pixel_size)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++ tmp |= (0x1<<16);
++ tmp |= (0x2<<10);
++
++ if(in == POST_DMA) {
++
++ switch(src) {
++ case YC420:
++ tmp &=~((0x1<<3)|(0x1<<2));
++ tmp |= (0x1<<8)|(0x1<<1);
++ *in_pixel_size = 1;
++ break;
++ case CRYCBY:
++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3)|(0x1<<0));
++ tmp |= (0x1<<2)|(0x1<<1);
++ *in_pixel_size = 2;
++ break;
++ case CBYCRY:
++ tmp &= ~((0x1<<8)|(0x1<<3)|(0x1<<0));
++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1);
++ *in_pixel_size = 2;
++ break;
++ case YCRYCB:
++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3));
++ tmp |= (0x1<<2)|(0x1<<1)|(0x1<<0);
++ *in_pixel_size = 2;
++ break;
++ case YCBYCR:
++ tmp &= ~((0x1<<8)|(0x1<<3));
++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1)|(0x1<<0);
++ *in_pixel_size = 2;
++ break;
++ case RGB24:
++ tmp &= ~(0x1<<8);
++ tmp |= (0x1<<3)|(0x1<<2)|(0x1<<1);
++ *in_pixel_size = 4;
++ break;
++ case RGB16:
++ tmp &= ~((0x1<<8)|(0x1<<1));
++ tmp |= (0x1<<3)|(0x1<<2);
++ *in_pixel_size = 2;
++ break;
++ default:
++ break;
++ }
++
++ }
++ else if(in == POST_FIFO) {
++ }
++
++ if(out == POST_DMA) {
++ switch(dst) {
++ case YC420:
++ tmp &= ~(0x1<<18);
++ tmp |= (0x1<<17);
++ *out_pixel_size = 1;
++ break;
++ case CRYCBY:
++ tmp &= ~((0x1<<20)|(0x1<<19)|(0x1<<18)|(0x1<<17));
++ *out_pixel_size = 2;
++ break;
++ case CBYCRY:
++ tmp &= ~((0x1<<19)|(0x1<<18)|(0x1<<17));
++ tmp |= (0x1<<20);
++ *out_pixel_size = 2;
++ break;
++ case YCRYCB:
++ tmp &= ~((0x1<<20)|(0x1<<18)|(0x1<<17));
++ tmp |= (0x1<<19);
++ *out_pixel_size = 2;
++ break;
++ case YCBYCR:
++ tmp &= ~((0x1<<18)|(0x1<<17));
++ tmp |= (0x1<<20)|(0x1<<19);
++ *out_pixel_size = 2;
++ break;
++ case RGB24:
++ tmp |= (0x1<<18)|(0x1<<4);
++ *out_pixel_size = 4;
++ break;
++ case RGB16:
++ tmp &= ~(0x1<<4);
++ tmp |= (0x1<<18);
++ *out_pixel_size = 2;
++ break;
++ default:
++ break;
++ }
++ }
++ else if(out == POST_FIFO) {
++ if(dst == RGB24) {
++ tmp |= (0x1<<18)|(0x1<<13);
++
++ } else if(dst == YCBYCR) {
++ tmp |= (0x1<<13);
++ tmp &= ~(0x1<<18)|(0x1<<17);
++ } else {
++ }
++ }
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++
++static void s3c_tvscaler_set_path(s3c_scaler_path_t in, s3c_scaler_path_t out)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ tmp &=~(0x1<<12); // 0: progressive mode, 1: interlace mode
++
++ if(in == POST_FIFO) {
++ tmp |= (0x1<<31);
++ } else if(in == POST_DMA) {
++ tmp &=~(0x1<<31);
++ }
++
++ if(out == POST_FIFO) {
++ tmp |= (0x1<<13);
++ } else if(out == POST_DMA) {
++ tmp &=~(0x1<<13);
++ }
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++
++static void s3c_tvscaler_set_addr(scaler_params_t *sp, u32 in_pixel_size, u32 out_pixel_size)
++{
++ u32 offset_y, offset_cb, offset_cr;
++ u32 src_start_y, src_start_cb, src_start_cr;
++ u32 src_end_y, src_end_cb, src_end_cr;
++ u32 start_pos_y, end_pos_y;
++ u32 start_pos_cb, end_pos_cb;
++ u32 start_pos_cr, end_pos_cr;
++ u32 start_pos_rgb, end_pos_rgb;
++ u32 dst_start_rgb, dst_end_rgb;
++ u32 src_frm_start_addr;
++
++ u32 offset_rgb, out_offset_cb, out_offset_cr;
++ u32 out_start_pos_cb, out_start_pos_cr;
++ u32 out_end_pos_cb, out_end_pos_cr;
++ u32 out_src_start_cb, out_src_start_cr;
++ u32 out_src_end_cb, out_src_end_cr;
++
++ if(sp->InPath == POST_DMA) {
++ offset_y = (sp->SrcFullWidth - sp->SrcWidth) * in_pixel_size;
++ start_pos_y = (sp->SrcFullWidth*sp->SrcStartY+sp->SrcStartX)*in_pixel_size;
++ end_pos_y = sp->SrcWidth*sp->SrcHeight*in_pixel_size + offset_y*(sp->SrcHeight-1);
++ src_frm_start_addr = sp->SrcFrmSt;
++ src_start_y = sp->SrcFrmSt + start_pos_y;
++ src_end_y = src_start_y + end_pos_y;
++
++ __raw_writel(src_start_y, base + S3C_ADDRSTART_Y);
++ __raw_writel(offset_y, base + S3C_OFFSET_Y);
++ __raw_writel(src_end_y, base + S3C_ADDREND_Y);
++
++ if(sp->SrcCSpace == YC420) {
++ offset_cb = offset_cr = ((sp->SrcFullWidth - sp->SrcWidth) / 2) * in_pixel_size;
++ start_pos_cb = sp->SrcFullWidth * sp->SrcFullHeight * 1 \
++ + (sp->SrcFullWidth * sp->SrcStartY / 2 + sp->SrcStartX) /2 * 1;
++
++ end_pos_cb = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \
++ + (sp->SrcHeight/2 -1)*offset_cb;
++ start_pos_cr = sp->SrcFullWidth * sp->SrcFullHeight *1 \
++ + sp->SrcFullWidth*sp->SrcFullHeight/4 *1 \
++ + (sp->SrcFullWidth*sp->SrcStartY/2 + sp->SrcStartX)/2*1;
++ end_pos_cr = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \
++ + (sp->SrcHeight/2-1)*offset_cr;
++
++ src_start_cb = sp->SrcFrmSt + start_pos_cb;
++ src_end_cb = src_start_cb + end_pos_cb;
++
++ src_start_cr = sp->SrcFrmSt + start_pos_cr;
++ src_end_cr = src_start_cr + end_pos_cr;
++
++ __raw_writel(src_start_cb, base + S3C_ADDRSTART_CB);
++ __raw_writel(offset_cr, base + S3C_OFFSET_CB);
++ __raw_writel(src_end_cb, base + S3C_ADDREND_CB);
++ __raw_writel(src_start_cr, base + S3C_ADDRSTART_CR);
++ __raw_writel(offset_cb, base + S3C_OFFSET_CR);
++ __raw_writel(src_end_cr, base + S3C_ADDREND_CR);
++ }
++ }
++ if(sp->OutPath == POST_DMA) {
++ offset_rgb = (sp->DstFullWidth - sp->DstWidth)*out_pixel_size;
++ start_pos_rgb = (sp->DstFullWidth*sp->DstStartY + sp->DstStartX)*out_pixel_size;
++ end_pos_rgb = sp->DstWidth*sp->DstHeight*out_pixel_size + offset_rgb*(sp->DstHeight - 1);
++ dst_start_rgb = sp->DstFrmSt + start_pos_rgb;
++ dst_end_rgb = dst_start_rgb + end_pos_rgb;
++
++ __raw_writel(dst_start_rgb, base + S3C_ADDRSTART_RGB);
++ __raw_writel(offset_rgb, base + S3C_OFFSET_RGB);
++ __raw_writel(dst_end_rgb, base + S3C_ADDREND_RGB);
++
++ if(sp->DstCSpace == YC420) {
++ out_offset_cb = out_offset_cr = ((sp->DstFullWidth - sp->DstWidth)/2)*out_pixel_size;
++ out_start_pos_cb = sp->DstFullWidth*sp->DstFullHeight*1 \
++ + (sp->DstFullWidth*sp->DstStartY/2 + sp->DstStartX)/2*1;
++ out_end_pos_cb = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \
++ + (sp->DstHeight/2 -1)*out_offset_cr;
++
++ out_start_pos_cr = sp->DstFullWidth*sp->DstFullHeight*1 \
++ + (sp->DstFullWidth*sp->DstFullHeight/4)*1 \
++ + (sp->DstFullWidth*sp->DstStartY/2 +sp->DstStartX)/2*1;
++ out_end_pos_cr = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \
++ + (sp->DstHeight/2 -1)*out_offset_cb;
++
++ out_src_start_cb = sp->DstFrmSt + out_start_pos_cb;
++ out_src_end_cb = out_src_start_cb + out_end_pos_cb;
++ out_src_start_cr = sp->DstFrmSt + out_start_pos_cr;
++ out_src_end_cr = out_src_start_cr + out_end_pos_cr;
++
++ __raw_writel(out_src_start_cb, base + S3C_ADDRSTART_OCB);
++ __raw_writel(out_offset_cb, base + S3C_OFFSET_OCB);
++ __raw_writel(out_src_end_cb, base + S3C_ADDREND_OCB);
++ __raw_writel(out_src_start_cr, base + S3C_ADDRSTART_OCR);
++ __raw_writel(out_offset_cr, base + S3C_OFFSET_OCR);
++ __raw_writel(out_src_end_cr, base + S3C_ADDREND_OCR);
++
++ }
++ }
++
++
++}
++
++#if 0
++static void s3c_tvscaler_set_fifo_in(s3c_scaler_path_t in_path)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(in_path == POST_FIFO) tmp |= (0x1<<31);
++ else tmp &=~(0x1<<31);
++
++ __raw_writel(tmp, base + S3C_MODE);
++
++}
++#endif
++
++void s3c_tvscaler_set_interlace(u32 on_off)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(on_off == 1) tmp |=(1<<12);
++ else tmp &=~(1<<12);
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++EXPORT_SYMBOL(s3c_tvscaler_set_interlace);
++
++static void s3c_tvscaler_set_size(scaler_params_t *sp)
++{
++ u32 pre_h_ratio, pre_v_ratio, h_shift, v_shift, sh_factor;
++ u32 pre_dst_width, pre_dst_height, dx, dy;
++
++ if (sp->SrcWidth >= (sp->DstWidth<<6)) {
++ printk("Out of PreScalar range !!!\n");
++ return;
++ }
++ if(sp->SrcWidth >= (sp->DstWidth<<5)) {
++ pre_h_ratio = 32;
++ h_shift = 5;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<4)) {
++ pre_h_ratio = 16;
++ h_shift = 4;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<3)) {
++ pre_h_ratio = 8;
++ h_shift = 3;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<2)) {
++ pre_h_ratio = 4;
++ h_shift = 2;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<1)) {
++ pre_h_ratio = 2;
++ h_shift = 1;
++ } else {
++ pre_h_ratio = 1;
++ h_shift = 0;
++ }
++
++ pre_dst_width = sp->SrcWidth / pre_h_ratio;
++ dx = (sp->SrcWidth<<8) / (sp->DstWidth<<h_shift);
++
++
++ if (sp->SrcHeight >= (sp->DstHeight<<6)) {
++ printk("Out of PreScalar range !!!\n");
++ return;
++ }
++ if(sp->SrcHeight>= (sp->DstHeight<<5)) {
++ pre_v_ratio = 32;
++ v_shift = 5;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<4)) {
++ pre_v_ratio = 16;
++ v_shift = 4;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<3)) {
++ pre_v_ratio = 8;
++ v_shift = 3;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<2)) {
++ pre_v_ratio = 4;
++ v_shift = 2;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<1)) {
++ pre_v_ratio = 2;
++ v_shift = 1;
++ } else {
++ pre_v_ratio = 1;
++ v_shift = 0;
++ }
++
++ pre_dst_height = sp->SrcHeight / pre_v_ratio;
++ dy = (sp->SrcHeight<<8) / (sp->DstHeight<<v_shift);
++ sh_factor = 10 - (h_shift + v_shift);
++
++ __raw_writel((pre_v_ratio<<7)|(pre_h_ratio<<0), base + S3C_PRESCALE_RATIO);
++ __raw_writel((pre_dst_height<<12)|(pre_dst_width<<0), base + S3C_PRESCALEIMGSIZE);
++ __raw_writel(sh_factor, base + S3C_PRESCALE_SHFACTOR);
++ __raw_writel(dx, base + S3C_MAINSCALE_H_RATIO);
++ __raw_writel(dy, base + S3C_MAINSCALE_V_RATIO);
++ __raw_writel((sp->SrcHeight<<12)|(sp->SrcWidth), base + S3C_SRCIMGSIZE);
++ __raw_writel((sp->DstHeight<<12)|(sp->DstWidth), base + S3C_DSTIMGSIZE);
++
++}
++
++
++static void s3c_tvscaler_set_auto_load(scaler_params_t *sp)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(sp->Mode == FREE_RUN) {
++ tmp |= (1<<14);
++ } else if(sp->Mode == ONE_SHOT) {
++ tmp &=~(1<<14);
++ }
++
++ __raw_writel(tmp, base + S3C_MODE);
++
++}
++
++void s3c_tvscaler_set_base_addr(void __iomem * base_addr)
++{
++ base = base_addr;
++}
++EXPORT_SYMBOL(s3c_tvscaler_set_base_addr);
++
++void s3c_tvscaler_free_base_addr(void)
++{
++ base = NULL;
++}
++EXPORT_SYMBOL(s3c_tvscaler_free_base_addr);
++
++void s3c_tvscaler_int_enable(u32 int_type)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(int_type == 0) { //Edge triggering
++ tmp &= ~(S3C_MODE_IRQ_LEVEL);
++ } else if(int_type == 1) { //level triggering
++ tmp |= S3C_MODE_IRQ_LEVEL;
++ }
++
++ tmp |= S3C_MODE_POST_INT_ENABLE;
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++EXPORT_SYMBOL(s3c_tvscaler_int_enable);
++
++void s3c_tvscaler_int_disable(void)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ tmp &=~ (S3C_MODE_POST_INT_ENABLE);
++
++ __raw_writel(tmp, base + S3C_MODE);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_int_disable);
++
++
++void s3c_tvscaler_start(void)
++{
++ __raw_writel(S3C_POSTENVID_ENABLE, base + S3C_POSTENVID);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_start);
++
++void s3c_tvscaler_stop_freerun(void)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ tmp &=~(1<<14);
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++EXPORT_SYMBOL(s3c_tvscaler_stop_freerun);
++
++
++void s3c_tvscaler_config(scaler_params_t *sp)
++{
++ u32 tmp = 0;
++ u32 in_pixel_size = 0;
++ u32 out_pixel_size = 0;
++ u32 loop = 0;
++
++ tmp = __raw_readl(base + S3C_POSTENVID);
++ tmp &= ~S3C_POSTENVID_ENABLE;
++ __raw_writel(tmp, base + S3C_POSTENVID);
++#ifdef SINGLE_BUF
++ tmp = S3C_MODE2_ADDR_CHANGE_DISABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER;
++#else
++ tmp = S3C_MODE2_ADDR_CHANGE_ENABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER;
++#endif
++ __raw_writel(tmp, base + S3C_MODE2);
++
++// peter mod. start
++ sp->DstStartX = sp->DstStartY = 0;
++ sp->DstWidth = sp->DstFullWidth;
++ sp->DstHeight = sp->DstFullHeight;
++// peter mod. end
++
++ sp->DstFrmSt = ( POST_BUFF_BASE_ADDR + PRE_BUFF_SIZE );
++ //printk("\n---peter s3c_tvscaler_config : SrcFrmSt = 0x%08x\n", sp->SrcFrmSt);
++ //printk("---peter s3c_tvscaler_config : DstFrmSt = 0x%08x\n", sp->DstFrmSt);
++
++ s3c_tvscaler_set_clk_src(HCLK);
++
++ s3c_tvscaler_set_path(sp->InPath, sp->OutPath);
++
++ s3c_tvscaler_set_fmt(sp->SrcCSpace, sp->DstCSpace, sp->InPath,
++ sp->OutPath, &in_pixel_size, &out_pixel_size);
++
++ s3c_tvscaler_set_size(sp);
++
++ s3c_tvscaler_set_addr(sp, in_pixel_size, out_pixel_size);
++
++ s3c_tvscaler_set_auto_load(sp);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_config);
++
++void s3c_tvscaler_set_param(scaler_params_t *sp)
++{
++#if 0
++ param.SrcFullWidth = sp->SrcFullWidth;
++ param.SrcFullHeight = sp->SrcFullHeight;
++ param.SrcStartX = sp->SrcStartX;
++ param.SrcStartY = sp->SrcStartY;
++ param.SrcWidth = sp->SrcWidth;
++ param.SrcHeight = sp->SrcHeight;
++ param.SrcFrmSt = sp->SrcFrmSt;
++ param.SrcCSpace = sp->SrcCSpace;
++ param.DstFullWidth = sp->DstFullWidth;
++ param.DstFullHeight = sp->DstFullHeight;
++ param.DstStartX = sp->DstStartX;
++ param.DstStartY = sp->DstStartY;
++ param.DstWidth = sp->DstWidth;
++ param.DstHeight = sp->DstHeight;
++ param.DstFrmSt = sp->DstFrmSt;
++ param.DstCSpace = sp->DstCSpace;
++ param.SrcFrmBufNum = sp->SrcFrmBufNum;
++ param.DstFrmSt = sp->DstFrmSt;
++ param.Mode = sp->Mode;
++ param.InPath = sp->InPath;
++ param.OutPath = sp->OutPath;
++#endif
++}
++EXPORT_SYMBOL(s3c_tvscaler_set_param);
++
++void s3c_tvscaler_init(void)
++{
++
++ int tmp;
++
++ // Use DOUTmpll source clock as a scaler clock
++ tmp = __raw_readl(S3C_CLK_SRC);
++
++ tmp &=~(0x3<<28);
++ tmp |= (0x1<<28);
++ __raw_writel(tmp, S3C_CLK_SRC);
++
++ printk(" %s \n", __FUNCTION__);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_init);
++
++
++static int s3c_tvscaler_probe(struct platform_device *pdev)
++{
++
++ struct resource *res;
++
++ int ret;
++
++ /* find the IRQs */
++ s3c_tvscaler_irq = platform_get_irq(pdev, 0);
++ if(s3c_tvscaler_irq <= 0) {
++ printk(KERN_ERR PFX "failed to get irq resouce\n");
++ return -ENOENT;
++ }
++
++ /* get the memory region for the tv scaler driver */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if(res == NULL) {
++ printk(KERN_ERR PFX "failed to get memory region resouce\n");
++ return -ENOENT;
++ }
++
++ s3c_tvscaler_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name);
++ if(s3c_tvscaler_mem == NULL) {
++ printk(KERN_ERR PFX "failed to reserve memory region\n");
++ return -ENOENT;
++ }
++
++ base = ioremap(s3c_tvscaler_mem->start, s3c_tvscaler_mem->end - res->start + 1);
++ if(s3c_tvscaler_mem == NULL) {
++ printk(KERN_ERR PFX "failed ioremap\n");
++ return -ENOENT;
++ }
++
++ tvscaler_clock = clk_get(&pdev->dev, "tv_encoder");
++ if(tvscaler_clock == NULL) {
++ printk(KERN_ERR PFX "failed to find tvscaler clock source\n");
++ return -ENOENT;
++ }
++
++ clk_enable(tvscaler_clock);
++
++ h_clk = clk_get(&pdev->dev, "hclk");
++ if(h_clk == NULL) {
++ printk(KERN_ERR PFX "failed to find h_clk clock source\n");
++ return -ENOENT;
++ }
++
++ init_waitqueue_head(&waitq);
++
++ ret = request_irq(s3c_tvscaler_irq, s3c_tvscaler_isr, SA_INTERRUPT,
++ "TV_SCALER", NULL);
++ if (ret) {
++ printk("request_irq(TV_SCALER) failed.\n");
++ return ret;
++ }
++
++ printk(" Success\n");
++
++ return 0;
++}
++
++static int s3c_tvscaler_remove(struct platform_device *dev)
++{
++ printk(KERN_INFO "s3c_tvscaler_remove called !\n");
++ clk_disable(tvscaler_clock);
++ free_irq(s3c_tvscaler_irq, NULL);
++ if (s3c_tvscaler_mem != NULL) {
++ pr_debug("s3-tvscaler: releasing s3c_tvscaler_mem\n");
++ iounmap(base);
++ release_resource(s3c_tvscaler_mem);
++ kfree(s3c_tvscaler_mem);
++ }
++
++ return 0;
++}
++
++static int s3c_tvscaler_suspend(struct platform_device *dev, pm_message_t state)
++{
++ clk_disable(tvscaler_clock);
++ return 0;
++}
++
++static int s3c_tvscaler_resume(struct platform_device *pdev)
++{
++ clk_enable(tvscaler_clock);
++ return 0;
++}
++
++static struct platform_driver s3c_tvscaler_driver = {
++ .probe = s3c_tvscaler_probe,
++ .remove = s3c_tvscaler_remove,
++ .suspend = s3c_tvscaler_suspend,
++ .resume = s3c_tvscaler_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-tvscaler",
++ },
++};
++
++static char banner[] __initdata = KERN_INFO "S3C6410 TV scaler Driver, (c) 2008 Samsung Electronics\n";
++
++
++int __init s3c_tvscaler_pre_init(void)
++{
++
++ printk(banner);
++
++ if(platform_driver_register(&s3c_tvscaler_driver) != 0)
++ {
++ printk("platform device register Failed \n");
++ return -1;
++ }
++
++ printk(" S3C6410 TV scaler Driver module init OK. \n");
++
++ return 0;
++}
++
++void s3c_tvscaler_exit(void)
++{
++ platform_driver_unregister(&s3c_tvscaler_driver);
++ printk("S3C: tvscaler module exit\n");
++}
++
++module_init(s3c_tvscaler_pre_init);
++module_exit(s3c_tvscaler_exit);
++
++
++MODULE_AUTHOR("Peter, Oh");
++MODULE_DESCRIPTION("S3C TV Controller Device Driver");
++MODULE_LICENSE("GPL");
++
++
+diff --git a/drivers/media/video/samsung/s3c-tvscaler.h b/drivers/media/video/samsung/s3c-tvscaler.h
+new file mode 100644
+index 0000000..d8079a3
+--- /dev/null
++++ b/drivers/media/video/samsung/s3c-tvscaler.h
+@@ -0,0 +1,96 @@
++#ifndef __S3CTVSCALER_H_
++#define __S3CTVSCALER_H_
++
++#include <asm-arm/arch-s3c2410/reserved_mem.h>
++
++#define TVSCALER_IOCTL_MAGIC 'S'
++
++#define PPROC_SET_PARAMS _IO(TVSCALER_IOCTL_MAGIC, 0)
++#define PPROC_START _IO(TVSCALER_IOCTL_MAGIC, 1)
++#define PPROC_STOP _IO(TVSCALER_IOCTL_MAGIC, 2)
++#define PPROC_INTERLACE_MODE _IO(TVSCALER_IOCTL_MAGIC, 3)
++#define PPROC_PROGRESSIVE_MODE _IO(TVSCALER_IOCTL_MAGIC, 4)
++
++
++#define QVGA_XSIZE 320
++#define QVGA_YSIZE 240
++
++#define LCD_XSIZE 320
++#define LCD_YSIZE 240
++
++#define SCALER_MINOR 251 // Just some number
++
++
++//#define SYSTEM_RAM 0x08000000 // 128mb
++#define SYSTEM_RAM 0x07800000 // 120mb
++#define RESERVE_POST_MEM 8*1024*1024 // 8mb
++#define PRE_BUFF_SIZE 4*1024*1024 //4 // 4mb
++#define POST_BUFF_SIZE ( RESERVE_POST_MEM - PRE_BUFF_SIZE )
++#if 0
++#define POST_BUFF_BASE_ADDR (0x50000000 + (SYSTEM_RAM - RESERVE_POST_MEM))
++#else // TV_RESERVED_MEM_START is defined in the s3c-linux-2.6.21_dev_4_4_15
++#define POST_BUFF_BASE_ADDR TV_RESERVED_MEM_START
++#endif
++
++#define USE_DEDICATED_MEM 1
++
++typedef enum {
++ INTERLACE_MODE,
++ PROGRESSIVE_MODE
++} s3c_scaler_scan_mode_t;
++
++typedef enum {
++ POST_DMA, POST_FIFO
++} s3c_scaler_path_t;
++
++typedef enum {
++ ONE_SHOT, FREE_RUN
++} s3c_scaler_run_mode_t;
++
++typedef enum {
++ PAL1, PAL2, PAL4, PAL8,
++ RGB8, ARGB8, RGB16, ARGB16, RGB18, RGB24, RGB30, ARGB24,
++ YC420, YC422, // Non-interleave
++ CRYCBY, CBYCRY, YCRYCB, YCBYCR, YUV444 // Interleave
++} cspace_t;
++
++typedef enum
++{
++ HCLK = 0, PLL_EXT = 1, EXT_27MHZ = 3
++} scaler_clk_src_t;
++
++typedef struct{
++ unsigned int SrcFullWidth; // Source Image Full Width(Virtual screen size)
++ unsigned int SrcFullHeight; // Source Image Full Height(Virtual screen size)
++ unsigned int SrcStartX; // Source Image Start width offset
++ unsigned int SrcStartY; // Source Image Start height offset
++ unsigned int SrcWidth; // Source Image Width
++ unsigned int SrcHeight; // Source Image Height
++ unsigned int SrcFrmSt; // Base Address of the Source Image : Physical Address
++ cspace_t SrcCSpace; // Color Space ot the Source Image
++
++ unsigned int DstFullWidth; // Source Image Full Width(Virtual screen size)
++ unsigned int DstFullHeight; // Source Image Full Height(Virtual screen size)
++ unsigned int DstStartX; // Source Image Start width offset
++ unsigned int DstStartY; // Source Image Start height offset
++ unsigned int DstWidth; // Source Image Width
++ unsigned int DstHeight; // Source Image Height
++ unsigned int DstFrmSt; // Base Address of the Source Image : Physical Address
++ cspace_t DstCSpace; // Color Space ot the Source Image
++
++ unsigned int SrcFrmBufNum; // Frame buffer number
++ s3c_scaler_run_mode_t Mode; // POST running mode(PER_FRAME or FREE_RUN)
++ s3c_scaler_path_t InPath; // Data path of the source image
++ s3c_scaler_path_t OutPath; // Data path of the desitination image
++
++}scaler_params_t;
++
++typedef struct{
++ unsigned int pre_phy_addr;
++ unsigned char *pre_virt_addr;
++
++ unsigned int post_phy_addr;
++ unsigned char *post_virt_addr;
++} buff_addr_t;
++
++#endif //__S3CTVSCALER_H_
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0007-make-tv-encoder-scaler-compile.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0007-make-tv-encoder-scaler-compile.patch
new file mode 100644
index 0000000000..9dfa4cc6e9
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0007-make-tv-encoder-scaler-compile.patch
@@ -0,0 +1,5208 @@
+From 148e57efdb357f7178ef2610caa9e33974965b4f Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 12:03:27 +0000
+Subject: [PATCH 07/13] make tv encoder + scaler compile
+
+---
+ drivers/media/video/Makefile | 3 +
+ drivers/media/video/s3c-tvenc.c | 1479 +++++++++++++++++++++++++++
+ drivers/media/video/s3c-tvenc.h | 165 +++
+ drivers/media/video/s3c-tvscaler.c | 802 +++++++++++++++
+ drivers/media/video/s3c-tvscaler.h | 96 ++
+ drivers/media/video/samsung/Makefile | 2 -
+ drivers/media/video/samsung/s3c-tvenc.c | 1479 ---------------------------
+ drivers/media/video/samsung/s3c-tvenc.h | 165 ---
+ drivers/media/video/samsung/s3c-tvscaler.c | 802 ---------------
+ drivers/media/video/samsung/s3c-tvscaler.h | 96 --
+ include/asm-arm/arch-s3c2410/reserved_mem.h | 4 +-
+ 11 files changed, 2547 insertions(+), 2546 deletions(-)
+ create mode 100644 drivers/media/video/s3c-tvenc.c
+ create mode 100644 drivers/media/video/s3c-tvenc.h
+ create mode 100644 drivers/media/video/s3c-tvscaler.c
+ create mode 100644 drivers/media/video/s3c-tvscaler.h
+ delete mode 100644 drivers/media/video/samsung/s3c-tvenc.c
+ delete mode 100644 drivers/media/video/samsung/s3c-tvenc.h
+ delete mode 100644 drivers/media/video/samsung/s3c-tvscaler.c
+ delete mode 100644 drivers/media/video/samsung/s3c-tvscaler.h
+
+diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
+index cd3d371..92a1e45 100644
+--- a/drivers/media/video/Makefile
++++ b/drivers/media/video/Makefile
+@@ -126,6 +126,9 @@ obj-$(CONFIG_USB_QUICKCAM_MESSENGER) += usbvideo/
+ obj-$(CONFIG_VIDEO_IVTV) += ivtv/
+
+ obj-$(CONFIG_VIDEO_SAMSUNG) += s3c_camera_driver.o s3c_camif.o samsung/
++obj-$(CONFIG_VIDEO_SAMSUNG_TVENC) += s3c-tvenc.o
++obj-$(CONFIG_VIDEO_SAMSUNG_TVSCALER) += s3c-tvscaler.o
++
+ obj-$(CONFIG_VIDEO_VIVI) += vivi.o
+ obj-$(CONFIG_VIDEO_CX23885) += cx23885/
+
+diff --git a/drivers/media/video/s3c-tvenc.c b/drivers/media/video/s3c-tvenc.c
+new file mode 100644
+index 0000000..11dfd37
+--- /dev/null
++++ b/drivers/media/video/s3c-tvenc.c
+@@ -0,0 +1,1479 @@
++
++/*
++ * linux/drivers/tvenc/s3c-tvenc.c
++ *
++ * Revision 1.0
++ *
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C TV Encoder driver
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h> /* error codes */
++#include <asm/div64.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++#include <asm/arch/map.h>
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,16)
++#include <linux/config.h>
++#include <asm/arch/registers.h>
++#include <linux/videodev2.h>
++#else
++#include <asm/arch/regs-tvenc.h>
++#include <asm/arch/regs-lcd.h>
++#include <media/v4l2-common.h>
++#endif
++
++#include "s3c-tvenc.h"
++
++#define PFX "s3c_tvenc"
++
++static struct clk *tvenc_clock;
++static struct clk *h_clk;
++static int s3c_tvenc_irq = NO_IRQ;
++static struct resource *s3c_tvenc_mem;
++static void __iomem *base;
++static wait_queue_head_t waitq;
++static tv_out_params_t tv_param = {0,};
++
++/* Backup SFR value */
++static u32 backup_reg[2];
++
++
++/* Structure that declares the access functions*/
++
++static void s3c_tvenc_switch(tv_enc_switch_t sw)
++{
++ if(sw == OFF) {
++ __raw_writel(__raw_readl(base + S3C_TVCTRL)
++ &~ S3C_TVCTRL_ON, base + S3C_TVCTRL);
++ } else if(sw == ON) {
++ __raw_writel(__raw_readl(base + S3C_TVCTRL)
++ | S3C_TVCTRL_ON, base + S3C_TVCTRL);
++ } else
++ printk("Error func:%s line:%d\n", __FUNCTION__, __LINE__);
++}
++
++static void s3c_tvenc_set_image_size(u32 width, u32 height)
++{
++ __raw_writel(IIS_WIDTH(width)| IIS_HEIGHT(height),
++ base + S3C_INIMAGESIZE);
++}
++
++#if 0
++static void s3c_tvenc_enable_macrovision(tv_standard_t tvmode, macro_pattern_t pattern)
++{
++ switch(pattern) {
++ case AGC4L :
++ break;
++ case AGC2L :
++ break;
++ case N01 :
++ break;
++ case N02 :
++ break;
++ case P01 :
++ break;
++ case P02 :
++ break;
++ default :
++ break;
++ }
++}
++
++static void s3c_tvenc_disable_macrovision(void)
++{
++ __raw_writel(__raw_readl(base + S3C_MACROVISION0)
++ &~0xff, base + S3C_MACROVISION0);
++}
++#endif
++
++static void s3c_tvenc_set_tv_mode(tv_standard_t mode, tv_conn_type_t out)
++{
++ u32 signal_type = 0, output_type = 0;
++
++ switch(mode) {
++ case PAL_N :
++ __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_ON,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_26|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_PAL,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_PAL,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case PAL_NC :
++ case PAL_BGHID :
++ __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_OFF,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_26|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_PAL,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_PAL,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case NTSC_443 :
++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_ON,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_26|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_NTSC,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_NTSC,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case NTSC_J :
++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_OFF,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_21|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_NTSC,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_NTSC,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ case PAL_M :
++ case NTSC_M :
++ default :
++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
++ base + S3C_VBPORCH);
++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
++ base + S3C_HBPORCH);
++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
++ base + S3C_HENHOFFSET);
++ __raw_writel(EPC_PED_ON,
++ base + S3C_PEDCTRL);
++ __raw_writel(YFB_YBW_21|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ __raw_writel(SSC_HSYNC_NTSC,
++ base + S3C_SYNCSIZECTRL);
++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
++ base + S3C_BURSTCTRL);
++ __raw_writel(MBS_BSTART_NTSC,
++ base + S3C_MACROBURSTCTRL);
++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
++ base + S3C_ACTVIDPOCTRL);
++ break;
++ }
++
++ if(out == S_VIDEO) {
++ __raw_writel(YFB_YBW_60|YFB_CBW_06,
++ base + S3C_YCFILTERBW);
++ output_type = S3C_TVCTRL_OUTTYPE_S;
++ } else
++ output_type = S3C_TVCTRL_OUTTYPE_C;
++
++ switch(mode) {
++ case NTSC_M :
++ signal_type = S3C_TVCTRL_OUTFMT_NTSC_M;
++ break;
++ case NTSC_J :
++ signal_type = S3C_TVCTRL_OUTFMT_NTSC_J;
++ break;
++ case PAL_BGHID :
++ signal_type = S3C_TVCTRL_OUTFMT_PAL_BDG;
++ break;
++ case PAL_M :
++ signal_type = S3C_TVCTRL_OUTFMT_PAL_M;
++ break;
++ case PAL_NC :
++ signal_type = S3C_TVCTRL_OUTFMT_PAL_NC;
++ break;
++ default:
++ printk("s3c_tvenc_set_tv_mode : No matching signal_type!\n");
++ break;
++ }
++
++ __raw_writel((__raw_readl(base + S3C_TVCTRL)
++ &~(0x1f<<4))| output_type | signal_type,
++ base + S3C_TVCTRL);
++
++ __raw_writel(0x01, base + S3C_FSCAUXCTRL);
++}
++
++#if 0
++static void s3c_tvenc_set_pedestal(tv_enc_switch_t sw)
++{
++ if(sw)
++ __raw_writel(EPC_PED_ON, base + S3C_PEDCTRL);
++ else
++ __raw_writel(EPC_PED_OFF, base + S3C_PEDCTRL);
++}
++
++static void s3c_tvenc_set_sub_carrier_freq(u32 freq)
++{
++ __raw_writel(FSC_CTRL(freq), base + S3C_FSCCTRL);
++}
++
++static void s3c_tvenc_set_fsc_dto(u32 val)
++{
++ unsigned int temp;
++
++ temp = (0x1<<31)|(val&0x7fffffff);
++ __raw_writel(temp, base + S3C_FSCDTOMANCTRL);
++}
++
++static void s3c_tvenc_disable_fsc_dto(void)
++{
++ __raw_writel(__raw_readl(base + S3C_FSCDTOMANCTRL)&~(1<<31),
++ base + S3C_FSCDTOMANCTRL);
++}
++
++static void s3c_tvenc_set_bg(u32 soft_mix, u32 color, u32 lum_offset)
++{
++ unsigned int bg_color;
++ switch(color) {
++ case 0 :
++ bg_color = BGC_BGCS_BLACK;
++ break;
++ case 1 :
++ bg_color = BGC_BGCS_BLUE;
++ break;
++ case 2 :
++ bg_color = BGC_BGCS_RED;
++ break;
++ case 3 :
++ bg_color = BGC_BGCS_MAGENTA;
++ break;
++ case 4 :
++ bg_color = BGC_BGCS_GREEN;
++ break;
++ case 5 :
++ bg_color = BGC_BGCS_CYAN;
++ break;
++ case 6 :
++ bg_color = BGC_BGCS_YELLOW;
++ break;
++ case 7 :
++ bg_color = BGC_BGCS_WHITE;
++ break;
++ }
++ if(soft_mix)
++ __raw_writel(BGC_SME_ENA|bg_color|BGC_BGYOFS(lum_offset),
++ base + S3C_BGCTRL);
++ else
++ __raw_writel(BGC_SME_DIS|bg_color|BGC_BGYOFS(lum_offset),
++ base + S3C_BGCTRL);
++
++}
++
++static void s3c_tvenc_set_bg_vav_hav(u32 hav_len, u32 vav_len, u32 hav_st, u32 vav_st)
++{
++ __raw_writel(BVH_BG_HL(hav_len)|BVH_BG_HS(hav_st)|BVH_BG_VL(vav_len)|BVH_BG_VS(vav_st),
++ base + S3C_BGHVAVCTRL);
++}
++#endif
++
++static void s3c_tvenc_set_hue_phase(u32 phase_val)
++{
++ __raw_writel(HUE_CTRL(phase_val),
++ base + S3C_HUECTRL);
++}
++
++#if 0
++static u32 s3c_tvenc_get_hue_phase(void)
++{
++ return __raw_readl(base + S3C_HUECTRL)&0xff;
++}
++#endif
++
++static void s3c_tvenc_set_contrast(u32 contrast)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CONTRABRIGHT);
++
++ __raw_writel((temp &~0xff)|contrast,
++ base + S3C_CONTRABRIGHT);
++}
++
++#if 0
++static u32 s3c_tvenc_get_contrast(void)
++{
++ return (__raw_readl(base + S3C_CONTRABRIGHT)&0xff);
++}
++#endif
++
++static void s3c_tvenc_set_bright(u32 bright)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CONTRABRIGHT);
++
++ __raw_writel((temp &~(0xff<<16))| (bright<<16),
++ base + S3C_CONTRABRIGHT);
++}
++
++#if 0
++static u32 s3c_tvenc_get_bright(void)
++{
++ return ((__raw_readl(base + S3C_CONTRABRIGHT)&(0xff<<16))>>16);
++}
++
++
++static void s3c_tvenc_set_cbgain(u32 cbgain)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CBCRGAINCTRL);
++
++ __raw_writel((temp &~0xff)|cbgain,
++ base + S3C_CBCRGAINCTRL);
++}
++
++
++static u32 s3c_tvenc_get_cbgain(void)
++{
++ return (__raw_readl(base + S3C_CBCRGAINCTRL)&0xff);
++}
++
++static void s3c_tvenc_set_crgain(u32 crgain)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_CBCRGAINCTRL);
++
++ __raw_writel((temp &~(0xff<<16))| (crgain<<16),
++ base + S3C_CBCRGAINCTRL);
++}
++
++static u32 s3c_tvenc_get_crgain(void)
++{
++ return ((__raw_readl(base + S3C_CBCRGAINCTRL)&(0xff<<16))>>16);
++}
++#endif
++
++static void s3c_tvenc_enable_gamma_control(tv_enc_switch_t enable)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_GAMMACTRL);
++ if(enable == ON)
++ temp |= (1<<12);
++ else
++ temp &= ~(1<<12);
++
++ __raw_writel(temp, base + S3C_GAMMACTRL);
++}
++
++static void s3c_tvenc_set_gamma_gain(u32 ggain)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_GAMMACTRL);
++
++ __raw_writel((temp &~(0x7<<8))| (ggain<<8),
++ base + S3C_GAMMACTRL);
++}
++
++#if 0
++static u32 s3c_tvenc_get_gamma_gain(void)
++{
++ return ((__raw_readl(base + S3C_GAMMACTRL)&(0x7<<8))>>8);
++}
++
++static void s3c_tvenc_enable_mute_control(tv_enc_switch_t enable)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_GAMMACTRL);
++ if(enable == ON)
++ temp |= (1<<12);
++ else
++ temp &= ~(1<<12);
++
++ __raw_writel(temp, base + S3C_GAMMACTRL);
++}
++
++static void s3c_tvenc_set_mute(u32 y, u32 cb, u32 cr)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_MUTECTRL);
++
++ temp &=~(0xffffff<<8);
++ temp |= (cr & 0xff)<<24;
++ temp |= (cb & 0xff)<<16;
++ temp |= (y & 0xff)<<8;
++
++ __raw_writel(temp, base + S3C_MUTECTRL);
++}
++
++static void s3c_tvenc_get_mute(u32 *y, u32 *cb, u32 *cr)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_MUTECTRL);
++
++ *y = (temp&(0xff<<8))>>8;
++ *cb = (temp&(0xff<<16))>>16;
++ *cr = (temp&(0xff<<24))>>24;
++}
++#endif
++
++static void s3c_tvenc_get_active_win_center(u32 *vert, u32 *horz)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_HENHOFFSET);
++
++ *vert = (temp&(0x3f<<24))>>24;
++ *horz = (temp&(0xff<<16))>>16;
++}
++
++static void s3c_tvenc_set_active_win_center(u32 vert, u32 horz)
++{
++ u32 temp;
++
++ temp = __raw_readl(base + S3C_HENHOFFSET);
++
++ temp &=~(0x3ffff<<16);
++ temp |= (vert&0x3f)<<24;
++ temp |= (horz&0xff)<<16;
++
++ __raw_writel(temp, base + S3C_HENHOFFSET);
++}
++
++// LCD display controller configuration functions
++static void s3c_lcd_set_output_path(lcd_local_output_t out)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_set_output_path(out);
++#else // peter for 2.6.24 kernel
++ s3cfb_set_output_path(out);
++#endif
++}
++
++static void s3c_lcd_set_clkval(u32 clkval)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_set_clkval(clkval);
++#else // peter for 2.6.24 kernel
++ s3cfb_set_clock(clkval);
++#endif
++}
++
++static void s3c_lcd_enable_rgbport(u32 on_off)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_enable_rgbport(on_off);
++#else // peter for 2.6.24 kernel
++ s3cfb_enable_rgbport(on_off);
++#endif
++}
++
++static void s3c_lcd_start(void)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_start_lcd();
++#else // peter for 2.6.24 kernel
++ s3cfb_start_lcd();
++#endif
++}
++
++static void s3c_lcd_stop(void)
++{
++#if 0 // peter for 2.6.21 kernel
++ s3c_fb_stop_lcd();
++#else // peter for 2.6.24 kernel
++ s3cfb_stop_lcd();
++#endif
++}
++
++
++static void s3c_lcd_set_config(void)
++{
++ backup_reg[0] = __raw_readl(S3C_VIDCON0);
++ backup_reg[1] = __raw_readl(S3C_VIDCON2);
++
++ s3c_lcd_set_output_path(LCD_TVRGB);
++ tv_param.lcd_output_mode = LCD_TVRGB;
++
++ s3c_lcd_set_clkval(4);
++ s3c_lcd_enable_rgbport(1);
++}
++
++static void s3c_lcd_exit_config(void)
++{
++ __raw_writel(backup_reg[0], S3C_VIDCON0);
++ __raw_writel(backup_reg[1], S3C_VIDCON2);
++ tv_param.lcd_output_mode = LCD_RGB;
++}
++
++static int scaler_test_start(void)
++{
++ tv_param.sp.DstFullWidth = 640;
++ tv_param.sp.DstFullHeight= 480;
++ tv_param.sp.DstCSpace = RGB16;
++
++ s3c_tvscaler_config(&tv_param.sp);
++
++ s3c_tvscaler_int_enable(1);
++
++ s3c_tvscaler_start();
++
++ return 0;
++}
++
++static int scaler_test_stop(void)
++{
++ s3c_tvscaler_int_disable();
++
++ return 0;
++}
++
++
++static int tvout_start(void)
++{
++ u32 width, height;
++ tv_standard_t type;
++ tv_conn_type_t conn;
++
++ tv_param.sp.DstFullWidth *= 2; // For TV OUT
++
++ width = tv_param.sp.DstFullWidth;
++ height = tv_param.sp.DstFullHeight;
++ type = tv_param.sig_type;
++ conn = tv_param.connect;
++
++ /* Set TV-SCALER parameter */
++ switch(tv_param.v2.input->type) {
++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
++ tv_param.sp.Mode = FREE_RUN;
++ tv_param.sp.DstCSpace = YCBYCR;
++ /* Display controller setting */
++ s3c_lcd_stop();
++ s3c_lcd_set_config();
++ break;
++ case V4L2_INPUT_TYPE_MSDMA: // MSDMA
++ tv_param.sp.Mode = FREE_RUN;
++ tv_param.sp.DstCSpace = YCBYCR;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ s3c_tvenc_set_tv_mode(type, conn);
++ s3c_tvenc_set_image_size(width, height);
++ s3c_tvenc_switch(ON);
++
++ s3c_tvscaler_config(&tv_param.sp); // for setting DstStartX/Y, DstWidth/Height
++ s3c_tvscaler_set_interlace(1);
++ if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO)
++ s3c_tvscaler_int_disable();
++ else
++ s3c_tvscaler_int_enable(1);
++ s3c_tvscaler_start();
++
++ if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO)
++ s3c_lcd_start();
++
++ return 0;
++}
++
++static int tvout_stop(void)
++{
++
++ s3c_tvscaler_set_interlace(0);
++ s3c_tvscaler_stop_freerun();
++ s3c_tvscaler_int_disable();
++ s3c_tvenc_switch(OFF);
++
++ switch(tv_param.v2.input->type) {
++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
++ /* Display controller setting */
++ s3c_lcd_stop();
++ s3c_lcd_exit_config();
++ s3c_lcd_start();
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++/* ------------------------------------------ V4L2 SUPPORT ----------------------------------------------*/
++/* ------------- In FIFO and MSDMA, v4l2_input supported by S3C TVENC controller ------------------*/
++static struct v4l2_input tvenc_inputs[] = {
++ {
++ .index = 0,
++ .name = "LCD FIFO_OUT",
++ .type = V4L2_INPUT_TYPE_FIFO,
++ .audioset = 1,
++ .tuner = 0, /* ignored */
++ .std = 0,
++ .status = 0,
++ },
++ {
++ .index = 1,
++ .name = "Memory input (MSDMA)",
++ .type = V4L2_INPUT_TYPE_MSDMA,
++ .audioset = 2,
++ .tuner = 0,
++ .std = 0,
++ .status = 0,
++ }
++};
++
++/* ------------ Out FIFO and MADMA, v4l2_output supported by S3C TVENC controller ----------------*/
++static struct v4l2_output tvenc_outputs[] = {
++ {
++ .index = 0,
++ .name = "TV-OUT",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_PAL | V4L2_STD_NTSC_M,
++ },
++ {
++ .index = 1,
++ .name = "Memory output (MSDMA)",
++ .type = V4L2_OUTPUT_TYPE_MSDMA,
++ .audioset = 0,
++ .modulator = 0,
++ .std = 0,
++ },
++
++};
++
++const struct v4l2_fmtdesc tvenc_input_formats[] = {
++ {
++ .index = 0,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .description = "16 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ .flags = FORMAT_FLAGS_PACKED,
++ },
++ {
++ .index = 1,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "24 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB24,
++ },
++ {
++ .index = 2,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:2, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++
++ },
++ {
++ .index = 3,
++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:0, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ }
++};
++
++
++const struct v4l2_fmtdesc tvenc_output_formats[] = {
++ {
++ .index = 0,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .description = "16 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ .flags = FORMAT_FLAGS_PACKED,
++ },
++ {
++ .index = 1,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .flags = FORMAT_FLAGS_PACKED,
++ .description = "24 bpp RGB, le",
++ .pixelformat = V4L2_PIX_FMT_RGB24,
++ },
++ {
++ .index = 2,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:2, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++
++ },
++ {
++ .index = 3,
++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ .flags = FORMAT_FLAGS_PLANAR,
++ .description = "4:2:0, planar, Y-Cb-Cr",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ }
++};
++
++const struct v4l2_standard tvout_standards[] = {
++ {
++ .index = 0,
++ .id = V4L2_STD_NTSC_M,
++ .name = "NTSC type",
++ },
++ {
++ .index = 1,
++ .id = V4L2_STD_PAL,
++ .name = "PAL type",
++ }
++};
++
++#define NUMBER_OF_INPUT_FORMATS ARRAY_SIZE(tvenc_input_formats)
++#define NUMBER_OF_OUTPUT_FORMATS ARRAY_SIZE(tvenc_output_formats)
++#define NUMBER_OF_INPUTS ARRAY_SIZE(tvenc_inputs)
++#define NUMBER_OF_OUTPUTS ARRAY_SIZE(tvenc_outputs)
++#define NUMBER_OF_STANDARDS ARRAY_SIZE(tvout_standards)
++
++static int s3c_tvenc_g_fmt(struct v4l2_format *f)
++{
++ int size = sizeof(struct v4l2_pix_format);
++
++ memset(&f->fmt.pix, 0, size);
++ memcpy(&f->fmt.pix, &tv_param.v2.pixfmt, size);
++
++ return 0;
++}
++
++static int s3c_tvenc_s_fmt(struct v4l2_format *f)
++{
++ /* update our state informations */
++ tv_param.v2.pixfmt= f->fmt.pix;
++
++ // peter LCD output related operation
++ if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_RGB565 ) {
++
++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width;
++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height;
++ tv_param.sp.SrcStartX = 0;
++ tv_param.sp.SrcStartY = 0;
++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth;
++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight;
++
++ printk("TV-OUT: LCD path operation set\n");
++
++ // peter for padded data of mfc output
++ } else if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_YUV420) {
++
++#ifdef DIVX_TEST // padded output
++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width + 2*16;
++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height + 2*16;
++ tv_param.sp.SrcStartX = 16;
++ tv_param.sp.SrcStartY = 16;
++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth - 2*tv_param.sp.SrcStartX;
++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight - 2*tv_param.sp.SrcStartY;
++#else // not padded output
++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width;
++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height;
++ tv_param.sp.SrcStartX = 0;
++ tv_param.sp.SrcStartY = 0;
++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth;
++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight;
++#endif
++
++ printk("TV-OUT: MFC path operation set\n");
++
++ }
++
++ switch(tv_param.v2.pixfmt.pixelformat) {
++ case V4L2_PIX_FMT_RGB565:
++ tv_param.sp.SrcCSpace = RGB16;
++ break;
++ case V4L2_PIX_FMT_RGB24:
++ tv_param.sp.SrcCSpace = RGB24;
++ break;
++ case V4L2_PIX_FMT_YUV420:
++ tv_param.sp.SrcCSpace = YC420;
++ break;
++ case V4L2_PIX_FMT_YUV422P:
++ tv_param.sp.SrcCSpace = YC422;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++// camif_convert_into_camif_cfg_t(cfg, 1);
++ return 0;
++}
++
++static int s3c_tvenc_s_input(int index)
++{
++
++ tv_param.v2.input = &tvenc_inputs[index];
++ switch(tv_param.v2.input->type) {
++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
++ tv_param.sp.InPath = POST_FIFO;
++ break;
++ case V4L2_INPUT_TYPE_MSDMA: // MSDMA
++ tv_param.sp.InPath = POST_DMA;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_s_output(int index)
++{
++ tv_param.v2.output = &tvenc_outputs[index];
++ switch(tv_param.v2.output->type) {
++ case V4L2_OUTPUT_TYPE_ANALOG: // TV-OUT (FIFO-OUT)
++ tv_param.sp.OutPath = POST_FIFO;
++ break;
++ case V4L2_OUTPUT_TYPE_MSDMA: // MSDMA
++ tv_param.sp.OutPath = POST_DMA;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_s_std(v4l2_std_id *id)
++{
++// printk("s3c_tvenc_s_std: *id=0x%x",*id);
++ switch(*id) {
++ case V4L2_STD_NTSC_M:
++ tv_param.sig_type = NTSC_M;
++ tv_param.sp.DstFullWidth = 720;
++ tv_param.sp.DstFullHeight = 480;
++ break;
++ case V4L2_STD_PAL:
++ tv_param.sig_type = PAL_M;
++ tv_param.sp.DstFullWidth = 720;
++ tv_param.sp.DstFullHeight = 576;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_v4l2_control(struct v4l2_control *ctrl)
++{
++ switch(ctrl->id) {
++
++ // peter added for MFC related op.
++ case V4L2_CID_MPEG_STREAM_PID_VIDEO:
++ {
++ tv_param.sp.SrcFrmSt = ctrl->value;
++ return 0;
++ }
++
++ case V4L2_CID_CONNECT_TYPE:
++ {
++ if(ctrl->value == 0) { // COMPOSITE
++ tv_param.connect = COMPOSITE;
++ } else if(ctrl->value == 1) { //S-VIDEO
++ tv_param.connect = S_VIDEO;
++ } else {
++ return -EINVAL;
++ }
++ return 0;
++ }
++
++ case V4L2_CID_BRIGHTNESS:
++ {
++ s32 val = ctrl->value;
++ if((val > 0xff)||(val < 0))
++ return -EINVAL;
++ else
++ s3c_tvenc_set_bright(val);
++
++ return 0;
++ }
++
++ case V4L2_CID_CONTRAST:
++ {
++ s32 val = ctrl->value;
++ if((val > 0xff)||(val < 0))
++ return -EINVAL;
++ else
++ s3c_tvenc_set_contrast(val);
++
++ return 0;
++ }
++
++ case V4L2_CID_GAMMA:
++ {
++ s32 val = ctrl->value;
++ if((val > 0x3)||(val < 0)) {
++ return -EINVAL;
++ } else {
++ s3c_tvenc_enable_gamma_control(ON);
++ s3c_tvenc_set_gamma_gain(val);
++ s3c_tvenc_enable_gamma_control(OFF);
++ }
++ return 0;
++ }
++
++ case V4L2_CID_HUE:
++ {
++ s32 val = ctrl->value;
++ if((val > 0xff)||(val < 0))
++ return -EINVAL;
++ else
++ s3c_tvenc_set_hue_phase(val);
++
++ return 0;
++ }
++
++ case V4L2_CID_HCENTER:
++ {
++ s32 val = ctrl->value;
++ u32 curr_horz, curr_vert;
++
++ if((val > 0xff)||(val < 0)) {
++ return -EINVAL;
++ } else {
++ s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz);
++ s3c_tvenc_set_active_win_center(curr_vert, val);
++ }
++
++ return 0;
++ }
++
++ case V4L2_CID_VCENTER:
++ {
++ s32 val = ctrl->value;
++ u32 curr_horz, curr_vert;
++
++ if((val > 0x3f)||(val < 0)) {
++ return -EINVAL;
++ } else {
++ s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz);
++ s3c_tvenc_set_active_win_center(val, curr_horz);
++ }
++
++ return 0;
++ }
++
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++int s3c_tvenc_open(struct inode *inode, struct file *filp)
++{
++ int err;
++
++ err = video_exclusive_open(inode, filp); // One function of V4l2 driver
++
++ if(err < 0)
++ return err;
++ filp->private_data = &tv_param;
++
++ s3c_tvscaler_init();
++
++ /* Success */
++ return 0;
++}
++
++int s3c_tvenc_release(struct inode *inode, struct file *filp)
++{
++ video_exclusive_release(inode, filp);
++
++ /* Success */
++ return 0;
++}
++
++static int s3c_tvenc_do_ioctl(struct inode *inode,struct file *filp,unsigned int cmd,void *arg)
++{
++ int ret;
++
++ switch(cmd){
++ case VIDIOC_QUERYCAP:
++ {
++ struct v4l2_capability *cap = arg;
++ strcpy(cap->driver, "S3C TV-OUT driver");
++ strlcpy(cap->card, tv_param.v->name, sizeof(cap->card));
++ sprintf(cap->bus_info, "ARM AHB BUS");
++ cap->version = 0;
++ cap->capabilities = tv_param.v->type2;
++ return 0;
++ }
++
++ case VIDIOC_OVERLAY:
++ {
++ int on = *(int *)arg;
++
++ printk("TV-OUT: VIDIOC_OVERLAY on:%d\n", on);
++ if (on != 0) {
++ ret = tvout_start();
++ } else {
++ ret = tvout_stop();
++ }
++ return ret;
++ }
++
++ case VIDIOC_ENUMINPUT:
++ {
++ struct v4l2_input *i = arg;
++ printk("TV-OUT: VIDIOC_ENUMINPUT : index = %d\n", i->index);
++
++ if ((i->index) >= NUMBER_OF_INPUTS) {
++ return -EINVAL;
++ }
++ memcpy(i, &tvenc_inputs[i->index], sizeof(struct v4l2_input));
++ return 0;
++ }
++
++ case VIDIOC_S_INPUT: // 0 -> LCD FIFO-OUT, 1 -> MSDMA
++ {
++ int index = *((int *)arg);
++ printk("TV-OUT: VIDIOC_S_INPUT \n");
++
++ if (index >= NUMBER_OF_INPUTS) {
++ return -EINVAL;
++ }
++ else {
++ s3c_tvenc_s_input(index);
++ return 0;
++ }
++ }
++
++ case VIDIOC_G_INPUT:
++ {
++ u32 *i = arg;
++ printk("TV-OUT: VIDIOC_G_INPUT \n");
++ *i = tv_param.v2.input->type;
++ return 0;
++ }
++
++ case VIDIOC_ENUMOUTPUT:
++ {
++ struct v4l2_output *i = arg;
++ printk("TV-OUT: VIDIOC_ENUMOUTPUT : index = %d\n", i->index);
++
++ if ((i->index) >= NUMBER_OF_OUTPUTS) {
++ return -EINVAL;
++ }
++ memcpy(i, &tvenc_outputs[i->index], sizeof(struct v4l2_output));
++ return 0;
++ }
++
++ case VIDIOC_S_OUTPUT: // 0 -> TV / FIFO , 1 -> MSDMA
++ {
++ int index = *((int *)arg);
++ printk("TV-OUT: VIDIOC_S_OUTPUT \n");
++
++ if (index >= NUMBER_OF_OUTPUTS) {
++ return -EINVAL;
++ }
++ else {
++ s3c_tvenc_s_output(index);
++ return 0;
++ }
++ }
++
++ case VIDIOC_G_OUTPUT:
++ {
++ u32 *i = arg;
++ printk("VIDIOC_G_OUTPUT \n");
++ *i = tv_param.v2.output->type;
++ return 0;
++ }
++
++ case VIDIOC_ENUM_FMT:
++ { struct v4l2_fmtdesc *f = arg;
++ enum v4l2_buf_type type = f->type;
++ int index = f->index;
++
++ printk("C: VIDIOC_ENUM_FMT : index = %d\n", index);
++ if (index >= NUMBER_OF_INPUT_FORMATS)
++ return -EINVAL;
++
++ switch (type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ default:
++ return -EINVAL;
++ }
++ memset(f, 0, sizeof(*f));
++ memcpy(f, tv_param.v2.fmtdesc+index, sizeof(*f));
++ return 0;
++ }
++
++ case VIDIOC_G_FMT:
++ {
++ struct v4l2_format *f = arg;
++ printk("C: VIDIOC_G_FMT \n");
++ ret = s3c_tvenc_g_fmt(f);
++ return ret;
++ }
++
++ case VIDIOC_S_FMT:
++ {
++ struct v4l2_format *f = arg;
++ printk("C: VIDIOC_S_FMT \n");
++ ret = s3c_tvenc_s_fmt(f);
++ if(ret != 0) {
++ printk("s3c_tvenc_set_fmt() failed !\n");
++ return -EINVAL;
++ }
++ return ret;
++ }
++
++ case VIDIOC_S_CTRL:
++ {
++ struct v4l2_control *ctrl = arg;
++ //printk("P: VIDIOC_S_CTRL \n");
++ ret = s3c_tvenc_v4l2_control(ctrl);
++ return ret;
++ }
++
++ case VIDIOC_ENUMSTD:
++ {
++ struct v4l2_standard *e = arg;
++ unsigned int index = e->index;
++
++ if (index >= NUMBER_OF_STANDARDS)
++ return -EINVAL;
++ v4l2_video_std_construct(e, tvout_standards[e->index].id,
++ &tvout_standards[e->index].name);
++ e->index = index;
++ return 0;
++ }
++
++ case VIDIOC_G_STD:
++ {
++ v4l2_std_id *id = arg;
++ *id = tvout_standards[0].id;
++ return 0;
++ }
++
++ case VIDIOC_S_STD:
++ {
++ v4l2_std_id *id = arg;
++ unsigned int i;
++
++ for (i = 0; i < NUMBER_OF_STANDARDS; i++) {
++ //printk("P: *id = %d, tvout_standards[i].id = %d\n", *id, tvout_standards[i].id);
++ if (*id & tvout_standards[i].id)
++ break;
++ }
++ if (i == NUMBER_OF_STANDARDS)
++ return -EINVAL;
++
++ ret = s3c_tvenc_s_std(id);
++ return ret;
++ }
++
++ case VIDIOC_S_TVOUT_ON:
++ {
++ //int *SrcFrmSt = arg;
++ //printk("---peter VIDIOC_S_TVOUT_ON : SrcFrmSt = 0x%08x\n", *SrcFrmSt);
++ ret = tvout_start();
++ return ret;
++ }
++
++ case VIDIOC_S_TVOUT_OFF:
++ {
++ ret = tvout_stop();
++ return ret;
++ }
++
++ case VIDIOC_S_SCALER_TEST:
++ {
++ ret = scaler_test_start();
++ mdelay(1);
++ ret = scaler_test_stop();
++ return ret;
++ }
++
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int s3c_tvenc_ioctl_v4l2(struct inode *inode, struct file *filp, unsigned int cmd,
++ unsigned long arg)
++{
++ return video_usercopy(inode, filp, cmd, arg, s3c_tvenc_do_ioctl);
++}
++
++int s3c_tvenc_read(struct file *filp, char *buf, size_t count,
++ loff_t *f_pos)
++{
++ return 0;
++}
++
++int s3c_tvenc_write(struct file *filp, const char *buf, size_t
++ count, loff_t *f_pos)
++{
++ return 0;
++}
++
++int s3c_tvenc_mmap(struct file *filp, struct vm_area_struct *vma)
++{
++ u32 size = vma->vm_end - vma->vm_start;
++ u32 max_size;
++ u32 page_frame_no;
++
++ page_frame_no = __phys_to_pfn(POST_BUFF_BASE_ADDR);
++
++ max_size = RESERVE_POST_MEM + PAGE_SIZE - (RESERVE_POST_MEM % PAGE_SIZE);
++
++ if(size > max_size) {
++ return -EINVAL;
++ }
++
++ vma->vm_flags |= VM_RESERVED;
++
++ if( remap_pfn_range(vma, vma->vm_start, page_frame_no,
++ size, vma->vm_page_prot)) {
++ printk(KERN_ERR "%s: mmap_error\n", __FUNCTION__);
++ return -EAGAIN;
++
++ }
++
++ return 0;
++}
++
++struct file_operations s3c_tvenc_fops = {
++ .owner = THIS_MODULE,
++ .open = s3c_tvenc_open,
++ .ioctl = s3c_tvenc_ioctl_v4l2,
++ .release = s3c_tvenc_release,
++ .read = s3c_tvenc_read,
++ .write = s3c_tvenc_write,
++ .mmap = s3c_tvenc_mmap,
++};
++
++void s3c_tvenc_vdev_release (struct video_device *vdev) {
++ kfree(vdev);
++}
++
++struct video_device tvencoder = {
++ .name = "TVENCODER",
++ .type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_SCALES,
++ .type2 = V4L2_CAP_VIDEO_OUTPUT| V4L2_CAP_VIDEO_CAPTURE, /* V4L2 */
++ //.hardware = 0x01, // peter for 2.6.24 kernel
++ .fops = &s3c_tvenc_fops,
++ .release = s3c_tvenc_vdev_release,
++ .minor = TVENC_MINOR,
++};
++
++irqreturn_t s3c_tvenc_isr(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ u32 mode;
++
++ mode = __raw_readl(base + S3C_TVCTRL);
++
++ // Clear FIFO under-run status pending bit
++ mode |= (1<<12);
++
++ __raw_writel(mode, base + S3C_TVCTRL);
++
++ wake_up_interruptible(&waitq);
++ return IRQ_HANDLED;
++}
++
++static int s3c_tvenc_probe(struct platform_device *pdev)
++{
++
++ struct resource *res;
++
++ int ret;
++
++ /* find the IRQs */
++ s3c_tvenc_irq = platform_get_irq(pdev, 0);
++ if(s3c_tvenc_irq <= 0) {
++ printk(KERN_ERR PFX "failed to get irq resouce\n");
++ return -ENOENT;
++ }
++
++ /* get the memory region for the tv scaler driver */
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if(res == NULL) {
++ printk(KERN_ERR PFX "failed to get memory region resouce\n");
++ return -ENOENT;
++ }
++
++ s3c_tvenc_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name);
++ if(s3c_tvenc_mem == NULL) {
++ printk(KERN_ERR PFX "failed to reserve memory region\n");
++ return -ENOENT;
++ }
++
++
++ base = ioremap(s3c_tvenc_mem->start, s3c_tvenc_mem->end - res->start + 1);
++ if(s3c_tvenc_mem == NULL) {
++ printk(KERN_ERR PFX "failed ioremap\n");
++ return -ENOENT;
++ }
++
++ tvenc_clock = clk_get(&pdev->dev, "tv_encoder");
++ if(tvenc_clock == NULL) {
++ printk(KERN_ERR PFX "failed to find tvenc clock source\n");
++ return -ENOENT;
++ }
++
++ clk_enable(tvenc_clock);
++
++ h_clk = clk_get(&pdev->dev, "hclk");
++ if(h_clk == NULL) {
++ printk(KERN_ERR PFX "failed to find h_clk clock source\n");
++ return -ENOENT;
++ }
++
++ init_waitqueue_head(&waitq);
++
++ tv_param.v = video_device_alloc();
++ if(!tv_param.v) {
++ printk(KERN_ERR "s3c-tvenc: video_device_alloc() failed\n");
++ return -ENOMEM;
++ }
++ memcpy(tv_param.v, &tvencoder, sizeof(tvencoder));
++ if(video_register_device(tv_param.v, VFL_TYPE_GRABBER, TVENC_MINOR) != 0) {
++ printk("s3c_camera_driver.c : Couldn't register this codec driver.\n");
++ return 0;
++ }
++
++ ret = request_irq(s3c_tvenc_irq, s3c_tvenc_isr, SA_INTERRUPT,
++ "TV_ENCODER", NULL);
++ if (ret) {
++ printk("request_irq(TV_ENCODER) failed.\n");
++ return ret;
++ }
++
++ printk(" Success\n");
++ return 0;
++}
++
++static int s3c_tvenc_remove(struct platform_device *dev)
++{
++ printk(KERN_INFO "s3c_tvenc_remove called !\n");
++ clk_disable(tvenc_clock);
++ free_irq(s3c_tvenc_irq, NULL);
++ if (s3c_tvenc_mem != NULL) {
++ pr_debug("s3-tvenc: releasing s3c_tvenc_mem\n");
++ iounmap(base);
++ release_resource(s3c_tvenc_mem);
++ kfree(s3c_tvenc_mem);
++ }
++// video_unregister_device(tv_param.v);
++ return 0;
++}
++
++static int s3c_tvenc_suspend(struct platform_device *dev, pm_message_t state)
++{
++ clk_disable(tvenc_clock);
++ return 0;
++}
++
++static int s3c_tvenc_resume(struct platform_device *pdev)
++{
++ clk_enable(tvenc_clock);
++ return 0;
++}
++
++static struct platform_driver s3c_tvenc_driver = {
++ .probe = s3c_tvenc_probe,
++ .remove = s3c_tvenc_remove,
++ .suspend = s3c_tvenc_suspend,
++ .resume = s3c_tvenc_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-tvenc",
++ },
++};
++
++static char banner[] __initdata = KERN_INFO "S3C6410 TV encoder Driver, (c) 2008 Samsung Electronics\n";
++
++static int __init s3c_tvenc_init(void)
++{
++
++ printk(banner);
++
++ if(platform_driver_register(&s3c_tvenc_driver) != 0)
++ {
++ printk("Platform Device Register Failed \n");
++ return -1;
++ }
++
++ printk(" S3C6410 TV encoder Driver module init OK. \n");
++ return 0;
++}
++
++static void __exit s3c_tvenc_exit(void)
++{
++
++ video_unregister_device(tv_param.v);
++ platform_driver_unregister(&s3c_tvenc_driver);
++
++ printk("S3C6410 TV encoder Driver module exit. \n");
++}
++
++
++module_init(s3c_tvenc_init);
++module_exit(s3c_tvenc_exit);
++
++
++MODULE_AUTHOR("Peter, Oh");
++MODULE_DESCRIPTION("S3C TV Encoder Device Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/media/video/s3c-tvenc.h b/drivers/media/video/s3c-tvenc.h
+new file mode 100644
+index 0000000..30a66a2
+--- /dev/null
++++ b/drivers/media/video/s3c-tvenc.h
+@@ -0,0 +1,165 @@
++#ifndef __S3CTVENC_H_
++#define __S3CTVENC_H_
++
++#include "s3c-tvscaler.h"
++
++
++#define TVENC_IOCTL_MAGIC 'T'
++
++typedef struct {
++
++} s3c_tvenc_info;
++
++#define TV_ON _IO(TVENC_IOCTL_MAGIC, 0)
++#define TV_OFF _IO(TVENC_IOCTL_MAGIC, 1)
++#define SELECT_TV_OUT_FORMAT _IO(TVENC_IOCTL_MAGIC, 2)
++
++#define TVENC_IOCTL_MAXNR 6
++
++#define TVENC_MINOR 14 // Just some number
++
++typedef enum {
++ OFF,
++ ON
++} tv_enc_switch_t;
++
++typedef enum {
++ NTSC_M,
++ PAL_M,
++ PAL_BGHID,
++ PAL_N,
++ PAL_NC,
++ PAL_60,
++ NTSC_443,
++ NTSC_J
++} tv_standard_t;
++
++typedef enum {
++ QCIF, CIF/*352x288*/,
++ QQVGA, QVGA, VGA, SVGA/*800x600*/, SXGA/*1280x1024*/, UXGA/*1600x1200*/, QXGA/*2048x1536*/,
++ WVGA/*854x480*/, HD720/*1280x720*/, HD1080/*1920x1080*/
++} img_size_t;
++
++typedef enum {
++ BLACKSTRETCH, WHITESTRETCH, BLUESTRETCH
++} stretch_color_t;
++
++typedef enum {
++ COMPOSITE, S_VIDEO
++} tv_conn_type_t;
++
++typedef enum {
++ BLACK, BLUE, RED, MAGENTA, GREEN, CYAN, YELLOW, WHITE
++} bg_color_t;
++
++typedef enum {
++ MUTE_Y, MUTE_CB, MUTE_CR
++} mute_type_t;
++
++typedef enum {
++ AGC4L, AGC2L, N01, N02, P01, P02
++} macro_pattern_t;
++
++typedef enum {
++ LCD_RGB, LCD_TV, LCD_I80F, LCD_I80S,
++ LCD_TVRGB, LCD_TVI80F, LCD_TVI80S
++} lcd_local_output_t;
++
++/* when App want to change v4l2 parameter,
++ * we instantly store it into v4l2_t v2
++ * and then reflect it to hardware
++ */
++typedef struct v4l2 {
++ struct v4l2_fmtdesc *fmtdesc;
++// struct v4l2_framebuffer frmbuf; /* current frame buffer */
++ struct v4l2_pix_format pixfmt;
++ struct v4l2_input *input;
++ struct v4l2_output *output;
++// enum v4l2_status status;
++} v4l2_t;
++
++
++typedef struct {
++ tv_standard_t sig_type;
++ tv_conn_type_t connect;
++ /* Width of input image. The input value is twice original output image
++ * width. For example, you must set 1440 when the image width is 720.
++ * Max value is 1440
++ */
++ unsigned int in_width;
++ /* Height of input image
++ * Max value is 576
++ */
++ unsigned int in_height;
++
++ // Setting value of VIDOUT[28:26] in Display
++ // controller(VIDCON0)
++ lcd_local_output_t lcd_output_mode;
++ // Set CLKVAL_F[13:6] of VIDCON0 with
++ // this value
++ unsigned int lcd_clkval_f;
++
++ // Flag of lcd rgb port
++ // 0 : disable, 1 : enable
++ unsigned int lcd_rgb_port_flag;
++
++ scaler_params_t sp;
++
++ struct video_device *v;
++ v4l2_t v2;
++
++} tv_out_params_t;
++
++#define V4L2_INPUT_TYPE_MSDMA 3
++#define V4L2_INPUT_TYPE_FIFO 4
++#define V4L2_OUTPUT_TYPE_MSDMA 4
++
++#define FORMAT_FLAGS_DITHER 0x01
++#define FORMAT_FLAGS_PACKED 0x02
++#define FORMAT_FLAGS_PLANAR 0x04
++#define FORMAT_FLAGS_RAW 0x08
++#define FORMAT_FLAGS_CrCb 0x10
++
++/****************************************************************
++* struct v4l2_control
++* Control IDs defined by S3C
++*****************************************************************/
++
++/* TV-OUT connector type */
++#define V4L2_CID_CONNECT_TYPE (V4L2_CID_PRIVATE_BASE+0)
++
++/****************************************************************
++* I O C T L C O D E S F O R V I D E O D E V I C E S
++* It's only for S3C
++*****************************************************************/
++#define VIDIOC_S_TVOUT_ON _IO ('V', BASE_VIDIOC_PRIVATE+0)
++#define VIDIOC_S_TVOUT_OFF _IO ('V', BASE_VIDIOC_PRIVATE+1)
++#define VIDIOC_S_SCALER_TEST _IO ('V', BASE_VIDIOC_PRIVATE+3)
++
++
++extern void s3c_tvscaler_config(scaler_params_t * sp);
++extern void s3c_tvscaler_int_enable(unsigned int int_type);
++extern void s3c_tvscaler_int_disable(void);
++extern void s3c_tvscaler_start(void);
++extern void s3c_tvscaler_stop_freerun(void);
++extern void s3c_tvscaler_init(void);
++extern void s3c_tvscaler_set_interlace(unsigned int on_off);
++extern int video_exclusive_release(struct inode * inode, struct file * file);
++extern int video_exclusive_open(struct inode * inode, struct file * file);
++
++#if 0 // peter for 2.6.21 kernel
++extern void s3c_fb_start_lcd(void);
++extern void s3c_fb_stop_lcd(void);
++extern void s3c_fb_set_output_path(int out);
++extern void s3c_fb_set_clkval(unsigned int clkval);
++extern void s3c_fb_enable_rgbport(unsigned int on_off);
++#else // peter for 2.6.24 kernel
++extern void s3cfb_start_lcd(void);
++extern void s3cfb_stop_lcd(void);
++extern void s3cfb_set_output_path(int out);
++extern void s3cfb_set_clock(unsigned int clkval);
++extern void s3cfb_enable_rgbport(unsigned int on_off);
++#endif
++
++
++#endif // __S3CTVENC_H_
+diff --git a/drivers/media/video/s3c-tvscaler.c b/drivers/media/video/s3c-tvscaler.c
+new file mode 100644
+index 0000000..376c866
+--- /dev/null
++++ b/drivers/media/video/s3c-tvscaler.c
+@@ -0,0 +1,802 @@
++
++/*
++ * linux/drivers/tvenc/s3c-tvscaler.c
++ *
++ * Revision 1.0
++ *
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ * S3C TV Scaler driver
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <asm/uaccess.h>
++#include <linux/errno.h> /* error codes */
++#include <asm/div64.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/uaccess.h>
++#include <asm/arch/map.h>
++#include <linux/miscdevice.h>
++
++#include <linux/version.h>
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,16)
++#include <linux/config.h>
++#include <asm/arch/registers.h>
++#else
++#include <asm/arch/regs-tvscaler.h>
++#include <asm/arch/regs-s3c6400-clock.h>
++#endif
++
++#include "s3c-tvscaler.h"
++
++#define PFX "s3c_tv_scaler"
++
++#define SINGLE_BUF 1 // Single buffer mode
++
++
++static struct clk *h_clk;
++static struct clk *tvscaler_clock;
++static void __iomem *base;
++static int s3c_tvscaler_irq = NO_IRQ;
++static struct resource *s3c_tvscaler_mem;
++
++
++//static unsigned char *addr_start_y;
++//static unsigned char *addr_start_rgb;
++
++static wait_queue_head_t waitq;
++
++irqreturn_t s3c_tvscaler_isr(int irq, void *dev_id,
++ struct pt_regs *regs)
++{
++ u32 mode;
++ mode = __raw_readl(base + S3C_MODE);
++ mode &= ~(1 << 6); /* Clear Source in POST Processor */
++ __raw_writel(mode, base + S3C_MODE);
++
++// wake_up_interruptible(&waitq);
++ return IRQ_HANDLED;
++}
++
++#if 0
++static buff_addr_t buf_addr = { NULL };
++
++
++static u32 post_alloc_pre_buff(scaler_params_t *sp)
++{
++ u32 size;
++
++#ifdef USE_DEDICATED_MEM
++
++ buf_addr.pre_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM);
++ buf_addr.pre_virt_addr = ioremap_nocache(buf_addr.pre_phy_addr, PRE_BUFF_SIZE);
++ if( !buf_addr.pre_virt_addr ) {
++ printk(KERN_ERR "%s: Failed to allocate pre buffer \n",__FUNCTION__);
++ return -ENOMEM;
++ }
++
++ sp->SrcFrmSt = buf_addr.pre_phy_addr;
++#else
++ size = sp->SrcWidth * sp->SrcHeight * 2;
++ addr_start_y = kmalloc(size, GFP_DMA);
++ if(addr_start_y != NULL) return -ENOMEM;
++#endif
++ return 0;
++}
++
++static u32 post_alloc_post_buff(scaler_params_t *sp)
++{
++ u32 size;
++
++#ifdef USE_DEDICATED_MEM
++
++ buf_addr.post_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM + PRE_BUFF_SIZE);
++ buf_addr.post_virt_addr = ioremap_nocache(buf_addr.post_phy_addr, POST_BUFF_SIZE);
++ if( !buf_addr.post_virt_addr ) {
++ printk(KERN_ERR "%s: Failed to allocate post buffer \n",__FUNCTION__);
++ return -ENOMEM;
++ }
++
++ sp->DstFrmSt = buf_addr.post_phy_addr;
++#else
++ size = sp->DstWidth * sp->DstHeight * 2;
++ addr_start_rgb = kmalloc(size, GFP_DMA);
++ if(addr_start_rgb != NULL) return -ENOMEM;
++#endif
++ return 0;
++}
++
++static u32 post_free_all_buffer(void)
++{
++#ifdef USE_DEDICATED_MEM
++ if( buf_addr.pre_virt_addr ) {
++ iounmap(buf_addr.pre_virt_addr);
++ }
++ if( buf_addr.post_virt_addr ) {
++ iounmap(buf_addr.post_virt_addr);
++ }
++#endif
++ return 0;
++}
++#endif
++
++static void s3c_tvscaler_set_clk_src(scaler_clk_src_t clk_src)
++{
++ u32 tmp, rate;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ h_clk = clk_get(NULL, "hclk");
++
++ rate = clk_get_rate(h_clk);
++
++ if(clk_src == HCLK) {
++ if(rate > 66000000) {
++ tmp &= ~(0x7f<<23);
++ tmp |= (1<<24);
++ tmp |= (1<<23);
++ } else {
++ tmp &=~ (0x7f<<23);
++ }
++
++ } else if(clk_src == PLL_EXT) {
++ } else {
++ tmp &=~(0x7f<<23);
++ }
++
++ tmp = (tmp &~ (0x3<<21)) | (clk_src<<21);
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++
++static void s3c_tvscaler_set_fmt(cspace_t src, cspace_t dst, s3c_scaler_path_t in,
++ s3c_scaler_path_t out, u32 *in_pixel_size,
++ u32 *out_pixel_size)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++ tmp |= (0x1<<16);
++ tmp |= (0x2<<10);
++
++ if(in == POST_DMA) {
++
++ switch(src) {
++ case YC420:
++ tmp &=~((0x1<<3)|(0x1<<2));
++ tmp |= (0x1<<8)|(0x1<<1);
++ *in_pixel_size = 1;
++ break;
++ case CRYCBY:
++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3)|(0x1<<0));
++ tmp |= (0x1<<2)|(0x1<<1);
++ *in_pixel_size = 2;
++ break;
++ case CBYCRY:
++ tmp &= ~((0x1<<8)|(0x1<<3)|(0x1<<0));
++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1);
++ *in_pixel_size = 2;
++ break;
++ case YCRYCB:
++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3));
++ tmp |= (0x1<<2)|(0x1<<1)|(0x1<<0);
++ *in_pixel_size = 2;
++ break;
++ case YCBYCR:
++ tmp &= ~((0x1<<8)|(0x1<<3));
++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1)|(0x1<<0);
++ *in_pixel_size = 2;
++ break;
++ case RGB24:
++ tmp &= ~(0x1<<8);
++ tmp |= (0x1<<3)|(0x1<<2)|(0x1<<1);
++ *in_pixel_size = 4;
++ break;
++ case RGB16:
++ tmp &= ~((0x1<<8)|(0x1<<1));
++ tmp |= (0x1<<3)|(0x1<<2);
++ *in_pixel_size = 2;
++ break;
++ default:
++ break;
++ }
++
++ }
++ else if(in == POST_FIFO) {
++ }
++
++ if(out == POST_DMA) {
++ switch(dst) {
++ case YC420:
++ tmp &= ~(0x1<<18);
++ tmp |= (0x1<<17);
++ *out_pixel_size = 1;
++ break;
++ case CRYCBY:
++ tmp &= ~((0x1<<20)|(0x1<<19)|(0x1<<18)|(0x1<<17));
++ *out_pixel_size = 2;
++ break;
++ case CBYCRY:
++ tmp &= ~((0x1<<19)|(0x1<<18)|(0x1<<17));
++ tmp |= (0x1<<20);
++ *out_pixel_size = 2;
++ break;
++ case YCRYCB:
++ tmp &= ~((0x1<<20)|(0x1<<18)|(0x1<<17));
++ tmp |= (0x1<<19);
++ *out_pixel_size = 2;
++ break;
++ case YCBYCR:
++ tmp &= ~((0x1<<18)|(0x1<<17));
++ tmp |= (0x1<<20)|(0x1<<19);
++ *out_pixel_size = 2;
++ break;
++ case RGB24:
++ tmp |= (0x1<<18)|(0x1<<4);
++ *out_pixel_size = 4;
++ break;
++ case RGB16:
++ tmp &= ~(0x1<<4);
++ tmp |= (0x1<<18);
++ *out_pixel_size = 2;
++ break;
++ default:
++ break;
++ }
++ }
++ else if(out == POST_FIFO) {
++ if(dst == RGB24) {
++ tmp |= (0x1<<18)|(0x1<<13);
++
++ } else if(dst == YCBYCR) {
++ tmp |= (0x1<<13);
++ tmp &= ~(0x1<<18)|(0x1<<17);
++ } else {
++ }
++ }
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++
++static void s3c_tvscaler_set_path(s3c_scaler_path_t in, s3c_scaler_path_t out)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ tmp &=~(0x1<<12); // 0: progressive mode, 1: interlace mode
++
++ if(in == POST_FIFO) {
++ tmp |= (0x1<<31);
++ } else if(in == POST_DMA) {
++ tmp &=~(0x1<<31);
++ }
++
++ if(out == POST_FIFO) {
++ tmp |= (0x1<<13);
++ } else if(out == POST_DMA) {
++ tmp &=~(0x1<<13);
++ }
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++
++static void s3c_tvscaler_set_addr(scaler_params_t *sp, u32 in_pixel_size, u32 out_pixel_size)
++{
++ u32 offset_y, offset_cb, offset_cr;
++ u32 src_start_y, src_start_cb, src_start_cr;
++ u32 src_end_y, src_end_cb, src_end_cr;
++ u32 start_pos_y, end_pos_y;
++ u32 start_pos_cb, end_pos_cb;
++ u32 start_pos_cr, end_pos_cr;
++ u32 start_pos_rgb, end_pos_rgb;
++ u32 dst_start_rgb, dst_end_rgb;
++ u32 src_frm_start_addr;
++
++ u32 offset_rgb, out_offset_cb, out_offset_cr;
++ u32 out_start_pos_cb, out_start_pos_cr;
++ u32 out_end_pos_cb, out_end_pos_cr;
++ u32 out_src_start_cb, out_src_start_cr;
++ u32 out_src_end_cb, out_src_end_cr;
++
++ if(sp->InPath == POST_DMA) {
++ offset_y = (sp->SrcFullWidth - sp->SrcWidth) * in_pixel_size;
++ start_pos_y = (sp->SrcFullWidth*sp->SrcStartY+sp->SrcStartX)*in_pixel_size;
++ end_pos_y = sp->SrcWidth*sp->SrcHeight*in_pixel_size + offset_y*(sp->SrcHeight-1);
++ src_frm_start_addr = sp->SrcFrmSt;
++ src_start_y = sp->SrcFrmSt + start_pos_y;
++ src_end_y = src_start_y + end_pos_y;
++
++ __raw_writel(src_start_y, base + S3C_ADDRSTART_Y);
++ __raw_writel(offset_y, base + S3C_OFFSET_Y);
++ __raw_writel(src_end_y, base + S3C_ADDREND_Y);
++
++ if(sp->SrcCSpace == YC420) {
++ offset_cb = offset_cr = ((sp->SrcFullWidth - sp->SrcWidth) / 2) * in_pixel_size;
++ start_pos_cb = sp->SrcFullWidth * sp->SrcFullHeight * 1 \
++ + (sp->SrcFullWidth * sp->SrcStartY / 2 + sp->SrcStartX) /2 * 1;
++
++ end_pos_cb = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \
++ + (sp->SrcHeight/2 -1)*offset_cb;
++ start_pos_cr = sp->SrcFullWidth * sp->SrcFullHeight *1 \
++ + sp->SrcFullWidth*sp->SrcFullHeight/4 *1 \
++ + (sp->SrcFullWidth*sp->SrcStartY/2 + sp->SrcStartX)/2*1;
++ end_pos_cr = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \
++ + (sp->SrcHeight/2-1)*offset_cr;
++
++ src_start_cb = sp->SrcFrmSt + start_pos_cb;
++ src_end_cb = src_start_cb + end_pos_cb;
++
++ src_start_cr = sp->SrcFrmSt + start_pos_cr;
++ src_end_cr = src_start_cr + end_pos_cr;
++
++ __raw_writel(src_start_cb, base + S3C_ADDRSTART_CB);
++ __raw_writel(offset_cr, base + S3C_OFFSET_CB);
++ __raw_writel(src_end_cb, base + S3C_ADDREND_CB);
++ __raw_writel(src_start_cr, base + S3C_ADDRSTART_CR);
++ __raw_writel(offset_cb, base + S3C_OFFSET_CR);
++ __raw_writel(src_end_cr, base + S3C_ADDREND_CR);
++ }
++ }
++ if(sp->OutPath == POST_DMA) {
++ offset_rgb = (sp->DstFullWidth - sp->DstWidth)*out_pixel_size;
++ start_pos_rgb = (sp->DstFullWidth*sp->DstStartY + sp->DstStartX)*out_pixel_size;
++ end_pos_rgb = sp->DstWidth*sp->DstHeight*out_pixel_size + offset_rgb*(sp->DstHeight - 1);
++ dst_start_rgb = sp->DstFrmSt + start_pos_rgb;
++ dst_end_rgb = dst_start_rgb + end_pos_rgb;
++
++ __raw_writel(dst_start_rgb, base + S3C_ADDRSTART_RGB);
++ __raw_writel(offset_rgb, base + S3C_OFFSET_RGB);
++ __raw_writel(dst_end_rgb, base + S3C_ADDREND_RGB);
++
++ if(sp->DstCSpace == YC420) {
++ out_offset_cb = out_offset_cr = ((sp->DstFullWidth - sp->DstWidth)/2)*out_pixel_size;
++ out_start_pos_cb = sp->DstFullWidth*sp->DstFullHeight*1 \
++ + (sp->DstFullWidth*sp->DstStartY/2 + sp->DstStartX)/2*1;
++ out_end_pos_cb = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \
++ + (sp->DstHeight/2 -1)*out_offset_cr;
++
++ out_start_pos_cr = sp->DstFullWidth*sp->DstFullHeight*1 \
++ + (sp->DstFullWidth*sp->DstFullHeight/4)*1 \
++ + (sp->DstFullWidth*sp->DstStartY/2 +sp->DstStartX)/2*1;
++ out_end_pos_cr = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \
++ + (sp->DstHeight/2 -1)*out_offset_cb;
++
++ out_src_start_cb = sp->DstFrmSt + out_start_pos_cb;
++ out_src_end_cb = out_src_start_cb + out_end_pos_cb;
++ out_src_start_cr = sp->DstFrmSt + out_start_pos_cr;
++ out_src_end_cr = out_src_start_cr + out_end_pos_cr;
++
++ __raw_writel(out_src_start_cb, base + S3C_ADDRSTART_OCB);
++ __raw_writel(out_offset_cb, base + S3C_OFFSET_OCB);
++ __raw_writel(out_src_end_cb, base + S3C_ADDREND_OCB);
++ __raw_writel(out_src_start_cr, base + S3C_ADDRSTART_OCR);
++ __raw_writel(out_offset_cr, base + S3C_OFFSET_OCR);
++ __raw_writel(out_src_end_cr, base + S3C_ADDREND_OCR);
++
++ }
++ }
++
++
++}
++
++#if 0
++static void s3c_tvscaler_set_fifo_in(s3c_scaler_path_t in_path)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(in_path == POST_FIFO) tmp |= (0x1<<31);
++ else tmp &=~(0x1<<31);
++
++ __raw_writel(tmp, base + S3C_MODE);
++
++}
++#endif
++
++void s3c_tvscaler_set_interlace(u32 on_off)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(on_off == 1) tmp |=(1<<12);
++ else tmp &=~(1<<12);
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++EXPORT_SYMBOL(s3c_tvscaler_set_interlace);
++
++static void s3c_tvscaler_set_size(scaler_params_t *sp)
++{
++ u32 pre_h_ratio, pre_v_ratio, h_shift, v_shift, sh_factor;
++ u32 pre_dst_width, pre_dst_height, dx, dy;
++
++ if (sp->SrcWidth >= (sp->DstWidth<<6)) {
++ printk("Out of PreScalar range !!!\n");
++ return;
++ }
++ if(sp->SrcWidth >= (sp->DstWidth<<5)) {
++ pre_h_ratio = 32;
++ h_shift = 5;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<4)) {
++ pre_h_ratio = 16;
++ h_shift = 4;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<3)) {
++ pre_h_ratio = 8;
++ h_shift = 3;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<2)) {
++ pre_h_ratio = 4;
++ h_shift = 2;
++ } else if(sp->SrcWidth >= (sp->DstWidth<<1)) {
++ pre_h_ratio = 2;
++ h_shift = 1;
++ } else {
++ pre_h_ratio = 1;
++ h_shift = 0;
++ }
++
++ pre_dst_width = sp->SrcWidth / pre_h_ratio;
++ dx = (sp->SrcWidth<<8) / (sp->DstWidth<<h_shift);
++
++
++ if (sp->SrcHeight >= (sp->DstHeight<<6)) {
++ printk("Out of PreScalar range !!!\n");
++ return;
++ }
++ if(sp->SrcHeight>= (sp->DstHeight<<5)) {
++ pre_v_ratio = 32;
++ v_shift = 5;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<4)) {
++ pre_v_ratio = 16;
++ v_shift = 4;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<3)) {
++ pre_v_ratio = 8;
++ v_shift = 3;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<2)) {
++ pre_v_ratio = 4;
++ v_shift = 2;
++ } else if(sp->SrcHeight >= (sp->DstHeight<<1)) {
++ pre_v_ratio = 2;
++ v_shift = 1;
++ } else {
++ pre_v_ratio = 1;
++ v_shift = 0;
++ }
++
++ pre_dst_height = sp->SrcHeight / pre_v_ratio;
++ dy = (sp->SrcHeight<<8) / (sp->DstHeight<<v_shift);
++ sh_factor = 10 - (h_shift + v_shift);
++
++ __raw_writel((pre_v_ratio<<7)|(pre_h_ratio<<0), base + S3C_PRESCALE_RATIO);
++ __raw_writel((pre_dst_height<<12)|(pre_dst_width<<0), base + S3C_PRESCALEIMGSIZE);
++ __raw_writel(sh_factor, base + S3C_PRESCALE_SHFACTOR);
++ __raw_writel(dx, base + S3C_MAINSCALE_H_RATIO);
++ __raw_writel(dy, base + S3C_MAINSCALE_V_RATIO);
++ __raw_writel((sp->SrcHeight<<12)|(sp->SrcWidth), base + S3C_SRCIMGSIZE);
++ __raw_writel((sp->DstHeight<<12)|(sp->DstWidth), base + S3C_DSTIMGSIZE);
++
++}
++
++
++static void s3c_tvscaler_set_auto_load(scaler_params_t *sp)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(sp->Mode == FREE_RUN) {
++ tmp |= (1<<14);
++ } else if(sp->Mode == ONE_SHOT) {
++ tmp &=~(1<<14);
++ }
++
++ __raw_writel(tmp, base + S3C_MODE);
++
++}
++
++void s3c_tvscaler_set_base_addr(void __iomem * base_addr)
++{
++ base = base_addr;
++}
++EXPORT_SYMBOL(s3c_tvscaler_set_base_addr);
++
++void s3c_tvscaler_free_base_addr(void)
++{
++ base = NULL;
++}
++EXPORT_SYMBOL(s3c_tvscaler_free_base_addr);
++
++void s3c_tvscaler_int_enable(u32 int_type)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ if(int_type == 0) { //Edge triggering
++ tmp &= ~(S3C_MODE_IRQ_LEVEL);
++ } else if(int_type == 1) { //level triggering
++ tmp |= S3C_MODE_IRQ_LEVEL;
++ }
++
++ tmp |= S3C_MODE_POST_INT_ENABLE;
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++EXPORT_SYMBOL(s3c_tvscaler_int_enable);
++
++void s3c_tvscaler_int_disable(void)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ tmp &=~ (S3C_MODE_POST_INT_ENABLE);
++
++ __raw_writel(tmp, base + S3C_MODE);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_int_disable);
++
++
++void s3c_tvscaler_start(void)
++{
++ __raw_writel(S3C_POSTENVID_ENABLE, base + S3C_POSTENVID);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_start);
++
++void s3c_tvscaler_stop_freerun(void)
++{
++ u32 tmp;
++
++ tmp = __raw_readl(base + S3C_MODE);
++
++ tmp &=~(1<<14);
++
++ __raw_writel(tmp, base + S3C_MODE);
++}
++EXPORT_SYMBOL(s3c_tvscaler_stop_freerun);
++
++
++void s3c_tvscaler_config(scaler_params_t *sp)
++{
++ u32 tmp = 0;
++ u32 in_pixel_size = 0;
++ u32 out_pixel_size = 0;
++ u32 loop = 0;
++
++ tmp = __raw_readl(base + S3C_POSTENVID);
++ tmp &= ~S3C_POSTENVID_ENABLE;
++ __raw_writel(tmp, base + S3C_POSTENVID);
++#ifdef SINGLE_BUF
++ tmp = S3C_MODE2_ADDR_CHANGE_DISABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER;
++#else
++ tmp = S3C_MODE2_ADDR_CHANGE_ENABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER;
++#endif
++ __raw_writel(tmp, base + S3C_MODE2);
++
++// peter mod. start
++ sp->DstStartX = sp->DstStartY = 0;
++ sp->DstWidth = sp->DstFullWidth;
++ sp->DstHeight = sp->DstFullHeight;
++// peter mod. end
++
++ sp->DstFrmSt = ( POST_BUFF_BASE_ADDR + PRE_BUFF_SIZE );
++ //printk("\n---peter s3c_tvscaler_config : SrcFrmSt = 0x%08x\n", sp->SrcFrmSt);
++ //printk("---peter s3c_tvscaler_config : DstFrmSt = 0x%08x\n", sp->DstFrmSt);
++
++ s3c_tvscaler_set_clk_src(HCLK);
++
++ s3c_tvscaler_set_path(sp->InPath, sp->OutPath);
++
++ s3c_tvscaler_set_fmt(sp->SrcCSpace, sp->DstCSpace, sp->InPath,
++ sp->OutPath, &in_pixel_size, &out_pixel_size);
++
++ s3c_tvscaler_set_size(sp);
++
++ s3c_tvscaler_set_addr(sp, in_pixel_size, out_pixel_size);
++
++ s3c_tvscaler_set_auto_load(sp);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_config);
++
++void s3c_tvscaler_set_param(scaler_params_t *sp)
++{
++#if 0
++ param.SrcFullWidth = sp->SrcFullWidth;
++ param.SrcFullHeight = sp->SrcFullHeight;
++ param.SrcStartX = sp->SrcStartX;
++ param.SrcStartY = sp->SrcStartY;
++ param.SrcWidth = sp->SrcWidth;
++ param.SrcHeight = sp->SrcHeight;
++ param.SrcFrmSt = sp->SrcFrmSt;
++ param.SrcCSpace = sp->SrcCSpace;
++ param.DstFullWidth = sp->DstFullWidth;
++ param.DstFullHeight = sp->DstFullHeight;
++ param.DstStartX = sp->DstStartX;
++ param.DstStartY = sp->DstStartY;
++ param.DstWidth = sp->DstWidth;
++ param.DstHeight = sp->DstHeight;
++ param.DstFrmSt = sp->DstFrmSt;
++ param.DstCSpace = sp->DstCSpace;
++ param.SrcFrmBufNum = sp->SrcFrmBufNum;
++ param.DstFrmSt = sp->DstFrmSt;
++ param.Mode = sp->Mode;
++ param.InPath = sp->InPath;
++ param.OutPath = sp->OutPath;
++#endif
++}
++EXPORT_SYMBOL(s3c_tvscaler_set_param);
++
++void s3c_tvscaler_init(void)
++{
++
++ int tmp;
++
++ // Use DOUTmpll source clock as a scaler clock
++ tmp = __raw_readl(S3C_CLK_SRC);
++
++ tmp &=~(0x3<<28);
++ tmp |= (0x1<<28);
++ __raw_writel(tmp, S3C_CLK_SRC);
++
++ printk(" %s \n", __FUNCTION__);
++
++}
++EXPORT_SYMBOL(s3c_tvscaler_init);
++
++
++static int s3c_tvscaler_probe(struct platform_device *pdev)
++{
++
++ struct resource *res;
++
++ int ret;
++
++ /* find the IRQs */
++ s3c_tvscaler_irq = platform_get_irq(pdev, 0);
++ if(s3c_tvscaler_irq <= 0) {
++ printk(KERN_ERR PFX "failed to get irq resouce\n");
++ return -ENOENT;
++ }
++
++ /* get the memory region for the tv scaler driver */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if(res == NULL) {
++ printk(KERN_ERR PFX "failed to get memory region resouce\n");
++ return -ENOENT;
++ }
++
++ s3c_tvscaler_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name);
++ if(s3c_tvscaler_mem == NULL) {
++ printk(KERN_ERR PFX "failed to reserve memory region\n");
++ return -ENOENT;
++ }
++
++ base = ioremap(s3c_tvscaler_mem->start, s3c_tvscaler_mem->end - res->start + 1);
++ if(s3c_tvscaler_mem == NULL) {
++ printk(KERN_ERR PFX "failed ioremap\n");
++ return -ENOENT;
++ }
++
++ tvscaler_clock = clk_get(&pdev->dev, "tv_encoder");
++ if(tvscaler_clock == NULL) {
++ printk(KERN_ERR PFX "failed to find tvscaler clock source\n");
++ return -ENOENT;
++ }
++
++ clk_enable(tvscaler_clock);
++
++ h_clk = clk_get(&pdev->dev, "hclk");
++ if(h_clk == NULL) {
++ printk(KERN_ERR PFX "failed to find h_clk clock source\n");
++ return -ENOENT;
++ }
++
++ init_waitqueue_head(&waitq);
++
++ ret = request_irq(s3c_tvscaler_irq, s3c_tvscaler_isr, SA_INTERRUPT,
++ "TV_SCALER", NULL);
++ if (ret) {
++ printk("request_irq(TV_SCALER) failed.\n");
++ return ret;
++ }
++
++ printk(" Success\n");
++
++ return 0;
++}
++
++static int s3c_tvscaler_remove(struct platform_device *dev)
++{
++ printk(KERN_INFO "s3c_tvscaler_remove called !\n");
++ clk_disable(tvscaler_clock);
++ free_irq(s3c_tvscaler_irq, NULL);
++ if (s3c_tvscaler_mem != NULL) {
++ pr_debug("s3-tvscaler: releasing s3c_tvscaler_mem\n");
++ iounmap(base);
++ release_resource(s3c_tvscaler_mem);
++ kfree(s3c_tvscaler_mem);
++ }
++
++ return 0;
++}
++
++static int s3c_tvscaler_suspend(struct platform_device *dev, pm_message_t state)
++{
++ clk_disable(tvscaler_clock);
++ return 0;
++}
++
++static int s3c_tvscaler_resume(struct platform_device *pdev)
++{
++ clk_enable(tvscaler_clock);
++ return 0;
++}
++
++static struct platform_driver s3c_tvscaler_driver = {
++ .probe = s3c_tvscaler_probe,
++ .remove = s3c_tvscaler_remove,
++ .suspend = s3c_tvscaler_suspend,
++ .resume = s3c_tvscaler_resume,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "s3c-tvscaler",
++ },
++};
++
++static char banner[] __initdata = KERN_INFO "S3C6410 TV scaler Driver, (c) 2008 Samsung Electronics\n";
++
++
++int __init s3c_tvscaler_pre_init(void)
++{
++
++ printk(banner);
++
++ if(platform_driver_register(&s3c_tvscaler_driver) != 0)
++ {
++ printk("platform device register Failed \n");
++ return -1;
++ }
++
++ printk(" S3C6410 TV scaler Driver module init OK. \n");
++
++ return 0;
++}
++
++void s3c_tvscaler_exit(void)
++{
++ platform_driver_unregister(&s3c_tvscaler_driver);
++ printk("S3C: tvscaler module exit\n");
++}
++
++module_init(s3c_tvscaler_pre_init);
++module_exit(s3c_tvscaler_exit);
++
++
++MODULE_AUTHOR("Peter, Oh");
++MODULE_DESCRIPTION("S3C TV Controller Device Driver");
++MODULE_LICENSE("GPL");
++
++
+diff --git a/drivers/media/video/s3c-tvscaler.h b/drivers/media/video/s3c-tvscaler.h
+new file mode 100644
+index 0000000..d8079a3
+--- /dev/null
++++ b/drivers/media/video/s3c-tvscaler.h
+@@ -0,0 +1,96 @@
++#ifndef __S3CTVSCALER_H_
++#define __S3CTVSCALER_H_
++
++#include <asm-arm/arch-s3c2410/reserved_mem.h>
++
++#define TVSCALER_IOCTL_MAGIC 'S'
++
++#define PPROC_SET_PARAMS _IO(TVSCALER_IOCTL_MAGIC, 0)
++#define PPROC_START _IO(TVSCALER_IOCTL_MAGIC, 1)
++#define PPROC_STOP _IO(TVSCALER_IOCTL_MAGIC, 2)
++#define PPROC_INTERLACE_MODE _IO(TVSCALER_IOCTL_MAGIC, 3)
++#define PPROC_PROGRESSIVE_MODE _IO(TVSCALER_IOCTL_MAGIC, 4)
++
++
++#define QVGA_XSIZE 320
++#define QVGA_YSIZE 240
++
++#define LCD_XSIZE 320
++#define LCD_YSIZE 240
++
++#define SCALER_MINOR 251 // Just some number
++
++
++//#define SYSTEM_RAM 0x08000000 // 128mb
++#define SYSTEM_RAM 0x07800000 // 120mb
++#define RESERVE_POST_MEM 8*1024*1024 // 8mb
++#define PRE_BUFF_SIZE 4*1024*1024 //4 // 4mb
++#define POST_BUFF_SIZE ( RESERVE_POST_MEM - PRE_BUFF_SIZE )
++#if 0
++#define POST_BUFF_BASE_ADDR (0x50000000 + (SYSTEM_RAM - RESERVE_POST_MEM))
++#else // TV_RESERVED_MEM_START is defined in the s3c-linux-2.6.21_dev_4_4_15
++#define POST_BUFF_BASE_ADDR TV_RESERVED_MEM_START
++#endif
++
++#define USE_DEDICATED_MEM 1
++
++typedef enum {
++ INTERLACE_MODE,
++ PROGRESSIVE_MODE
++} s3c_scaler_scan_mode_t;
++
++typedef enum {
++ POST_DMA, POST_FIFO
++} s3c_scaler_path_t;
++
++typedef enum {
++ ONE_SHOT, FREE_RUN
++} s3c_scaler_run_mode_t;
++
++typedef enum {
++ PAL1, PAL2, PAL4, PAL8,
++ RGB8, ARGB8, RGB16, ARGB16, RGB18, RGB24, RGB30, ARGB24,
++ YC420, YC422, // Non-interleave
++ CRYCBY, CBYCRY, YCRYCB, YCBYCR, YUV444 // Interleave
++} cspace_t;
++
++typedef enum
++{
++ HCLK = 0, PLL_EXT = 1, EXT_27MHZ = 3
++} scaler_clk_src_t;
++
++typedef struct{
++ unsigned int SrcFullWidth; // Source Image Full Width(Virtual screen size)
++ unsigned int SrcFullHeight; // Source Image Full Height(Virtual screen size)
++ unsigned int SrcStartX; // Source Image Start width offset
++ unsigned int SrcStartY; // Source Image Start height offset
++ unsigned int SrcWidth; // Source Image Width
++ unsigned int SrcHeight; // Source Image Height
++ unsigned int SrcFrmSt; // Base Address of the Source Image : Physical Address
++ cspace_t SrcCSpace; // Color Space ot the Source Image
++
++ unsigned int DstFullWidth; // Source Image Full Width(Virtual screen size)
++ unsigned int DstFullHeight; // Source Image Full Height(Virtual screen size)
++ unsigned int DstStartX; // Source Image Start width offset
++ unsigned int DstStartY; // Source Image Start height offset
++ unsigned int DstWidth; // Source Image Width
++ unsigned int DstHeight; // Source Image Height
++ unsigned int DstFrmSt; // Base Address of the Source Image : Physical Address
++ cspace_t DstCSpace; // Color Space ot the Source Image
++
++ unsigned int SrcFrmBufNum; // Frame buffer number
++ s3c_scaler_run_mode_t Mode; // POST running mode(PER_FRAME or FREE_RUN)
++ s3c_scaler_path_t InPath; // Data path of the source image
++ s3c_scaler_path_t OutPath; // Data path of the desitination image
++
++}scaler_params_t;
++
++typedef struct{
++ unsigned int pre_phy_addr;
++ unsigned char *pre_virt_addr;
++
++ unsigned int post_phy_addr;
++ unsigned char *post_virt_addr;
++} buff_addr_t;
++
++#endif //__S3CTVSCALER_H_
+diff --git a/drivers/media/video/samsung/Makefile b/drivers/media/video/samsung/Makefile
+index ede0269..885512c 100644
+--- a/drivers/media/video/samsung/Makefile
++++ b/drivers/media/video/samsung/Makefile
+@@ -7,5 +7,3 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5K4BA) += 4xa_sensor.o
+ obj-$(CONFIG_VIDEO_ADV7180) += adv7180.o
+ obj-$(CONFIG_VIDEO_APTINA_MT9P012) += mt9p012.o
+
+-obj-$(CONFIG_VIDEO_SAMSUNG_TVENC) += s3c_tvenc.o
+-obj-$(CONFIG_VIDEO_SAMSUNG_TVSCALER) += s3c_tvenc.o
+diff --git a/drivers/media/video/samsung/s3c-tvenc.c b/drivers/media/video/samsung/s3c-tvenc.c
+deleted file mode 100644
+index 11dfd37..0000000
+--- a/drivers/media/video/samsung/s3c-tvenc.c
++++ /dev/null
+@@ -1,1479 +0,0 @@
+-
+-/*
+- * linux/drivers/tvenc/s3c-tvenc.c
+- *
+- * Revision 1.0
+- *
+- *
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License. See the file COPYING in the main directory of this archive for
+- * more details.
+- *
+- * S3C TV Encoder driver
+- *
+- */
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/types.h>
+-#include <linux/timer.h>
+-#include <linux/kernel.h>
+-#include <linux/fs.h>
+-#include <linux/platform_device.h>
+-#include <linux/interrupt.h>
+-#include <linux/clk.h>
+-#include <linux/delay.h>
+-#include <asm/uaccess.h>
+-#include <linux/errno.h> /* error codes */
+-#include <asm/div64.h>
+-#include <linux/mm.h>
+-#include <linux/tty.h>
+-#include <asm/io.h>
+-#include <asm/irq.h>
+-#include <asm/hardware.h>
+-#include <asm/uaccess.h>
+-#include <asm/arch/map.h>
+-
+-#include <linux/version.h>
+-#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,16)
+-#include <linux/config.h>
+-#include <asm/arch/registers.h>
+-#include <linux/videodev2.h>
+-#else
+-#include <asm/arch/regs-tvenc.h>
+-#include <asm/arch/regs-lcd.h>
+-#include <media/v4l2-common.h>
+-#endif
+-
+-#include "s3c-tvenc.h"
+-
+-#define PFX "s3c_tvenc"
+-
+-static struct clk *tvenc_clock;
+-static struct clk *h_clk;
+-static int s3c_tvenc_irq = NO_IRQ;
+-static struct resource *s3c_tvenc_mem;
+-static void __iomem *base;
+-static wait_queue_head_t waitq;
+-static tv_out_params_t tv_param = {0,};
+-
+-/* Backup SFR value */
+-static u32 backup_reg[2];
+-
+-
+-/* Structure that declares the access functions*/
+-
+-static void s3c_tvenc_switch(tv_enc_switch_t sw)
+-{
+- if(sw == OFF) {
+- __raw_writel(__raw_readl(base + S3C_TVCTRL)
+- &~ S3C_TVCTRL_ON, base + S3C_TVCTRL);
+- } else if(sw == ON) {
+- __raw_writel(__raw_readl(base + S3C_TVCTRL)
+- | S3C_TVCTRL_ON, base + S3C_TVCTRL);
+- } else
+- printk("Error func:%s line:%d\n", __FUNCTION__, __LINE__);
+-}
+-
+-static void s3c_tvenc_set_image_size(u32 width, u32 height)
+-{
+- __raw_writel(IIS_WIDTH(width)| IIS_HEIGHT(height),
+- base + S3C_INIMAGESIZE);
+-}
+-
+-#if 0
+-static void s3c_tvenc_enable_macrovision(tv_standard_t tvmode, macro_pattern_t pattern)
+-{
+- switch(pattern) {
+- case AGC4L :
+- break;
+- case AGC2L :
+- break;
+- case N01 :
+- break;
+- case N02 :
+- break;
+- case P01 :
+- break;
+- case P02 :
+- break;
+- default :
+- break;
+- }
+-}
+-
+-static void s3c_tvenc_disable_macrovision(void)
+-{
+- __raw_writel(__raw_readl(base + S3C_MACROVISION0)
+- &~0xff, base + S3C_MACROVISION0);
+-}
+-#endif
+-
+-static void s3c_tvenc_set_tv_mode(tv_standard_t mode, tv_conn_type_t out)
+-{
+- u32 signal_type = 0, output_type = 0;
+-
+- switch(mode) {
+- case PAL_N :
+- __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL,
+- base + S3C_VBPORCH);
+- __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL,
+- base + S3C_HBPORCH);
+- __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL,
+- base + S3C_HENHOFFSET);
+- __raw_writel(EPC_PED_ON,
+- base + S3C_PEDCTRL);
+- __raw_writel(YFB_YBW_26|YFB_CBW_06,
+- base + S3C_YCFILTERBW);
+- __raw_writel(SSC_HSYNC_PAL,
+- base + S3C_SYNCSIZECTRL);
+- __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL,
+- base + S3C_BURSTCTRL);
+- __raw_writel(MBS_BSTART_PAL,
+- base + S3C_MACROBURSTCTRL);
+- __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL,
+- base + S3C_ACTVIDPOCTRL);
+- break;
+- case PAL_NC :
+- case PAL_BGHID :
+- __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL,
+- base + S3C_VBPORCH);
+- __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL,
+- base + S3C_HBPORCH);
+- __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL,
+- base + S3C_HENHOFFSET);
+- __raw_writel(EPC_PED_OFF,
+- base + S3C_PEDCTRL);
+- __raw_writel(YFB_YBW_26|YFB_CBW_06,
+- base + S3C_YCFILTERBW);
+- __raw_writel(SSC_HSYNC_PAL,
+- base + S3C_SYNCSIZECTRL);
+- __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL,
+- base + S3C_BURSTCTRL);
+- __raw_writel(MBS_BSTART_PAL,
+- base + S3C_MACROBURSTCTRL);
+- __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL,
+- base + S3C_ACTVIDPOCTRL);
+- break;
+- case NTSC_443 :
+- __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
+- base + S3C_VBPORCH);
+- __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
+- base + S3C_HBPORCH);
+- __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
+- base + S3C_HENHOFFSET);
+- __raw_writel(EPC_PED_ON,
+- base + S3C_PEDCTRL);
+- __raw_writel(YFB_YBW_26|YFB_CBW_06,
+- base + S3C_YCFILTERBW);
+- __raw_writel(SSC_HSYNC_NTSC,
+- base + S3C_SYNCSIZECTRL);
+- __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
+- base + S3C_BURSTCTRL);
+- __raw_writel(MBS_BSTART_NTSC,
+- base + S3C_MACROBURSTCTRL);
+- __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
+- base + S3C_ACTVIDPOCTRL);
+- break;
+- case NTSC_J :
+- __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
+- base + S3C_VBPORCH);
+- __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
+- base + S3C_HBPORCH);
+- __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
+- base + S3C_HENHOFFSET);
+- __raw_writel(EPC_PED_OFF,
+- base + S3C_PEDCTRL);
+- __raw_writel(YFB_YBW_21|YFB_CBW_06,
+- base + S3C_YCFILTERBW);
+- __raw_writel(SSC_HSYNC_NTSC,
+- base + S3C_SYNCSIZECTRL);
+- __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
+- base + S3C_BURSTCTRL);
+- __raw_writel(MBS_BSTART_NTSC,
+- base + S3C_MACROBURSTCTRL);
+- __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
+- base + S3C_ACTVIDPOCTRL);
+- break;
+- case PAL_M :
+- case NTSC_M :
+- default :
+- __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC,
+- base + S3C_VBPORCH);
+- __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC,
+- base + S3C_HBPORCH);
+- __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC,
+- base + S3C_HENHOFFSET);
+- __raw_writel(EPC_PED_ON,
+- base + S3C_PEDCTRL);
+- __raw_writel(YFB_YBW_21|YFB_CBW_06,
+- base + S3C_YCFILTERBW);
+- __raw_writel(SSC_HSYNC_NTSC,
+- base + S3C_SYNCSIZECTRL);
+- __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC,
+- base + S3C_BURSTCTRL);
+- __raw_writel(MBS_BSTART_NTSC,
+- base + S3C_MACROBURSTCTRL);
+- __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC,
+- base + S3C_ACTVIDPOCTRL);
+- break;
+- }
+-
+- if(out == S_VIDEO) {
+- __raw_writel(YFB_YBW_60|YFB_CBW_06,
+- base + S3C_YCFILTERBW);
+- output_type = S3C_TVCTRL_OUTTYPE_S;
+- } else
+- output_type = S3C_TVCTRL_OUTTYPE_C;
+-
+- switch(mode) {
+- case NTSC_M :
+- signal_type = S3C_TVCTRL_OUTFMT_NTSC_M;
+- break;
+- case NTSC_J :
+- signal_type = S3C_TVCTRL_OUTFMT_NTSC_J;
+- break;
+- case PAL_BGHID :
+- signal_type = S3C_TVCTRL_OUTFMT_PAL_BDG;
+- break;
+- case PAL_M :
+- signal_type = S3C_TVCTRL_OUTFMT_PAL_M;
+- break;
+- case PAL_NC :
+- signal_type = S3C_TVCTRL_OUTFMT_PAL_NC;
+- break;
+- default:
+- printk("s3c_tvenc_set_tv_mode : No matching signal_type!\n");
+- break;
+- }
+-
+- __raw_writel((__raw_readl(base + S3C_TVCTRL)
+- &~(0x1f<<4))| output_type | signal_type,
+- base + S3C_TVCTRL);
+-
+- __raw_writel(0x01, base + S3C_FSCAUXCTRL);
+-}
+-
+-#if 0
+-static void s3c_tvenc_set_pedestal(tv_enc_switch_t sw)
+-{
+- if(sw)
+- __raw_writel(EPC_PED_ON, base + S3C_PEDCTRL);
+- else
+- __raw_writel(EPC_PED_OFF, base + S3C_PEDCTRL);
+-}
+-
+-static void s3c_tvenc_set_sub_carrier_freq(u32 freq)
+-{
+- __raw_writel(FSC_CTRL(freq), base + S3C_FSCCTRL);
+-}
+-
+-static void s3c_tvenc_set_fsc_dto(u32 val)
+-{
+- unsigned int temp;
+-
+- temp = (0x1<<31)|(val&0x7fffffff);
+- __raw_writel(temp, base + S3C_FSCDTOMANCTRL);
+-}
+-
+-static void s3c_tvenc_disable_fsc_dto(void)
+-{
+- __raw_writel(__raw_readl(base + S3C_FSCDTOMANCTRL)&~(1<<31),
+- base + S3C_FSCDTOMANCTRL);
+-}
+-
+-static void s3c_tvenc_set_bg(u32 soft_mix, u32 color, u32 lum_offset)
+-{
+- unsigned int bg_color;
+- switch(color) {
+- case 0 :
+- bg_color = BGC_BGCS_BLACK;
+- break;
+- case 1 :
+- bg_color = BGC_BGCS_BLUE;
+- break;
+- case 2 :
+- bg_color = BGC_BGCS_RED;
+- break;
+- case 3 :
+- bg_color = BGC_BGCS_MAGENTA;
+- break;
+- case 4 :
+- bg_color = BGC_BGCS_GREEN;
+- break;
+- case 5 :
+- bg_color = BGC_BGCS_CYAN;
+- break;
+- case 6 :
+- bg_color = BGC_BGCS_YELLOW;
+- break;
+- case 7 :
+- bg_color = BGC_BGCS_WHITE;
+- break;
+- }
+- if(soft_mix)
+- __raw_writel(BGC_SME_ENA|bg_color|BGC_BGYOFS(lum_offset),
+- base + S3C_BGCTRL);
+- else
+- __raw_writel(BGC_SME_DIS|bg_color|BGC_BGYOFS(lum_offset),
+- base + S3C_BGCTRL);
+-
+-}
+-
+-static void s3c_tvenc_set_bg_vav_hav(u32 hav_len, u32 vav_len, u32 hav_st, u32 vav_st)
+-{
+- __raw_writel(BVH_BG_HL(hav_len)|BVH_BG_HS(hav_st)|BVH_BG_VL(vav_len)|BVH_BG_VS(vav_st),
+- base + S3C_BGHVAVCTRL);
+-}
+-#endif
+-
+-static void s3c_tvenc_set_hue_phase(u32 phase_val)
+-{
+- __raw_writel(HUE_CTRL(phase_val),
+- base + S3C_HUECTRL);
+-}
+-
+-#if 0
+-static u32 s3c_tvenc_get_hue_phase(void)
+-{
+- return __raw_readl(base + S3C_HUECTRL)&0xff;
+-}
+-#endif
+-
+-static void s3c_tvenc_set_contrast(u32 contrast)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_CONTRABRIGHT);
+-
+- __raw_writel((temp &~0xff)|contrast,
+- base + S3C_CONTRABRIGHT);
+-}
+-
+-#if 0
+-static u32 s3c_tvenc_get_contrast(void)
+-{
+- return (__raw_readl(base + S3C_CONTRABRIGHT)&0xff);
+-}
+-#endif
+-
+-static void s3c_tvenc_set_bright(u32 bright)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_CONTRABRIGHT);
+-
+- __raw_writel((temp &~(0xff<<16))| (bright<<16),
+- base + S3C_CONTRABRIGHT);
+-}
+-
+-#if 0
+-static u32 s3c_tvenc_get_bright(void)
+-{
+- return ((__raw_readl(base + S3C_CONTRABRIGHT)&(0xff<<16))>>16);
+-}
+-
+-
+-static void s3c_tvenc_set_cbgain(u32 cbgain)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_CBCRGAINCTRL);
+-
+- __raw_writel((temp &~0xff)|cbgain,
+- base + S3C_CBCRGAINCTRL);
+-}
+-
+-
+-static u32 s3c_tvenc_get_cbgain(void)
+-{
+- return (__raw_readl(base + S3C_CBCRGAINCTRL)&0xff);
+-}
+-
+-static void s3c_tvenc_set_crgain(u32 crgain)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_CBCRGAINCTRL);
+-
+- __raw_writel((temp &~(0xff<<16))| (crgain<<16),
+- base + S3C_CBCRGAINCTRL);
+-}
+-
+-static u32 s3c_tvenc_get_crgain(void)
+-{
+- return ((__raw_readl(base + S3C_CBCRGAINCTRL)&(0xff<<16))>>16);
+-}
+-#endif
+-
+-static void s3c_tvenc_enable_gamma_control(tv_enc_switch_t enable)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_GAMMACTRL);
+- if(enable == ON)
+- temp |= (1<<12);
+- else
+- temp &= ~(1<<12);
+-
+- __raw_writel(temp, base + S3C_GAMMACTRL);
+-}
+-
+-static void s3c_tvenc_set_gamma_gain(u32 ggain)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_GAMMACTRL);
+-
+- __raw_writel((temp &~(0x7<<8))| (ggain<<8),
+- base + S3C_GAMMACTRL);
+-}
+-
+-#if 0
+-static u32 s3c_tvenc_get_gamma_gain(void)
+-{
+- return ((__raw_readl(base + S3C_GAMMACTRL)&(0x7<<8))>>8);
+-}
+-
+-static void s3c_tvenc_enable_mute_control(tv_enc_switch_t enable)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_GAMMACTRL);
+- if(enable == ON)
+- temp |= (1<<12);
+- else
+- temp &= ~(1<<12);
+-
+- __raw_writel(temp, base + S3C_GAMMACTRL);
+-}
+-
+-static void s3c_tvenc_set_mute(u32 y, u32 cb, u32 cr)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_MUTECTRL);
+-
+- temp &=~(0xffffff<<8);
+- temp |= (cr & 0xff)<<24;
+- temp |= (cb & 0xff)<<16;
+- temp |= (y & 0xff)<<8;
+-
+- __raw_writel(temp, base + S3C_MUTECTRL);
+-}
+-
+-static void s3c_tvenc_get_mute(u32 *y, u32 *cb, u32 *cr)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_MUTECTRL);
+-
+- *y = (temp&(0xff<<8))>>8;
+- *cb = (temp&(0xff<<16))>>16;
+- *cr = (temp&(0xff<<24))>>24;
+-}
+-#endif
+-
+-static void s3c_tvenc_get_active_win_center(u32 *vert, u32 *horz)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_HENHOFFSET);
+-
+- *vert = (temp&(0x3f<<24))>>24;
+- *horz = (temp&(0xff<<16))>>16;
+-}
+-
+-static void s3c_tvenc_set_active_win_center(u32 vert, u32 horz)
+-{
+- u32 temp;
+-
+- temp = __raw_readl(base + S3C_HENHOFFSET);
+-
+- temp &=~(0x3ffff<<16);
+- temp |= (vert&0x3f)<<24;
+- temp |= (horz&0xff)<<16;
+-
+- __raw_writel(temp, base + S3C_HENHOFFSET);
+-}
+-
+-// LCD display controller configuration functions
+-static void s3c_lcd_set_output_path(lcd_local_output_t out)
+-{
+-#if 0 // peter for 2.6.21 kernel
+- s3c_fb_set_output_path(out);
+-#else // peter for 2.6.24 kernel
+- s3cfb_set_output_path(out);
+-#endif
+-}
+-
+-static void s3c_lcd_set_clkval(u32 clkval)
+-{
+-#if 0 // peter for 2.6.21 kernel
+- s3c_fb_set_clkval(clkval);
+-#else // peter for 2.6.24 kernel
+- s3cfb_set_clock(clkval);
+-#endif
+-}
+-
+-static void s3c_lcd_enable_rgbport(u32 on_off)
+-{
+-#if 0 // peter for 2.6.21 kernel
+- s3c_fb_enable_rgbport(on_off);
+-#else // peter for 2.6.24 kernel
+- s3cfb_enable_rgbport(on_off);
+-#endif
+-}
+-
+-static void s3c_lcd_start(void)
+-{
+-#if 0 // peter for 2.6.21 kernel
+- s3c_fb_start_lcd();
+-#else // peter for 2.6.24 kernel
+- s3cfb_start_lcd();
+-#endif
+-}
+-
+-static void s3c_lcd_stop(void)
+-{
+-#if 0 // peter for 2.6.21 kernel
+- s3c_fb_stop_lcd();
+-#else // peter for 2.6.24 kernel
+- s3cfb_stop_lcd();
+-#endif
+-}
+-
+-
+-static void s3c_lcd_set_config(void)
+-{
+- backup_reg[0] = __raw_readl(S3C_VIDCON0);
+- backup_reg[1] = __raw_readl(S3C_VIDCON2);
+-
+- s3c_lcd_set_output_path(LCD_TVRGB);
+- tv_param.lcd_output_mode = LCD_TVRGB;
+-
+- s3c_lcd_set_clkval(4);
+- s3c_lcd_enable_rgbport(1);
+-}
+-
+-static void s3c_lcd_exit_config(void)
+-{
+- __raw_writel(backup_reg[0], S3C_VIDCON0);
+- __raw_writel(backup_reg[1], S3C_VIDCON2);
+- tv_param.lcd_output_mode = LCD_RGB;
+-}
+-
+-static int scaler_test_start(void)
+-{
+- tv_param.sp.DstFullWidth = 640;
+- tv_param.sp.DstFullHeight= 480;
+- tv_param.sp.DstCSpace = RGB16;
+-
+- s3c_tvscaler_config(&tv_param.sp);
+-
+- s3c_tvscaler_int_enable(1);
+-
+- s3c_tvscaler_start();
+-
+- return 0;
+-}
+-
+-static int scaler_test_stop(void)
+-{
+- s3c_tvscaler_int_disable();
+-
+- return 0;
+-}
+-
+-
+-static int tvout_start(void)
+-{
+- u32 width, height;
+- tv_standard_t type;
+- tv_conn_type_t conn;
+-
+- tv_param.sp.DstFullWidth *= 2; // For TV OUT
+-
+- width = tv_param.sp.DstFullWidth;
+- height = tv_param.sp.DstFullHeight;
+- type = tv_param.sig_type;
+- conn = tv_param.connect;
+-
+- /* Set TV-SCALER parameter */
+- switch(tv_param.v2.input->type) {
+- case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
+- tv_param.sp.Mode = FREE_RUN;
+- tv_param.sp.DstCSpace = YCBYCR;
+- /* Display controller setting */
+- s3c_lcd_stop();
+- s3c_lcd_set_config();
+- break;
+- case V4L2_INPUT_TYPE_MSDMA: // MSDMA
+- tv_param.sp.Mode = FREE_RUN;
+- tv_param.sp.DstCSpace = YCBYCR;
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- s3c_tvenc_set_tv_mode(type, conn);
+- s3c_tvenc_set_image_size(width, height);
+- s3c_tvenc_switch(ON);
+-
+- s3c_tvscaler_config(&tv_param.sp); // for setting DstStartX/Y, DstWidth/Height
+- s3c_tvscaler_set_interlace(1);
+- if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO)
+- s3c_tvscaler_int_disable();
+- else
+- s3c_tvscaler_int_enable(1);
+- s3c_tvscaler_start();
+-
+- if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO)
+- s3c_lcd_start();
+-
+- return 0;
+-}
+-
+-static int tvout_stop(void)
+-{
+-
+- s3c_tvscaler_set_interlace(0);
+- s3c_tvscaler_stop_freerun();
+- s3c_tvscaler_int_disable();
+- s3c_tvenc_switch(OFF);
+-
+- switch(tv_param.v2.input->type) {
+- case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
+- /* Display controller setting */
+- s3c_lcd_stop();
+- s3c_lcd_exit_config();
+- s3c_lcd_start();
+- break;
+- default:
+- break;
+- }
+- return 0;
+-}
+-
+-/* ------------------------------------------ V4L2 SUPPORT ----------------------------------------------*/
+-/* ------------- In FIFO and MSDMA, v4l2_input supported by S3C TVENC controller ------------------*/
+-static struct v4l2_input tvenc_inputs[] = {
+- {
+- .index = 0,
+- .name = "LCD FIFO_OUT",
+- .type = V4L2_INPUT_TYPE_FIFO,
+- .audioset = 1,
+- .tuner = 0, /* ignored */
+- .std = 0,
+- .status = 0,
+- },
+- {
+- .index = 1,
+- .name = "Memory input (MSDMA)",
+- .type = V4L2_INPUT_TYPE_MSDMA,
+- .audioset = 2,
+- .tuner = 0,
+- .std = 0,
+- .status = 0,
+- }
+-};
+-
+-/* ------------ Out FIFO and MADMA, v4l2_output supported by S3C TVENC controller ----------------*/
+-static struct v4l2_output tvenc_outputs[] = {
+- {
+- .index = 0,
+- .name = "TV-OUT",
+- .type = V4L2_OUTPUT_TYPE_ANALOG,
+- .audioset = 0,
+- .modulator = 0,
+- .std = V4L2_STD_PAL | V4L2_STD_NTSC_M,
+- },
+- {
+- .index = 1,
+- .name = "Memory output (MSDMA)",
+- .type = V4L2_OUTPUT_TYPE_MSDMA,
+- .audioset = 0,
+- .modulator = 0,
+- .std = 0,
+- },
+-
+-};
+-
+-const struct v4l2_fmtdesc tvenc_input_formats[] = {
+- {
+- .index = 0,
+- .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+- .description = "16 bpp RGB, le",
+- .pixelformat = V4L2_PIX_FMT_RGB565,
+- .flags = FORMAT_FLAGS_PACKED,
+- },
+- {
+- .index = 1,
+- .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+- .flags = FORMAT_FLAGS_PACKED,
+- .description = "24 bpp RGB, le",
+- .pixelformat = V4L2_PIX_FMT_RGB24,
+- },
+- {
+- .index = 2,
+- .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+- .flags = FORMAT_FLAGS_PLANAR,
+- .description = "4:2:2, planar, Y-Cb-Cr",
+- .pixelformat = V4L2_PIX_FMT_YUV422P,
+-
+- },
+- {
+- .index = 3,
+- .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+- .flags = FORMAT_FLAGS_PLANAR,
+- .description = "4:2:0, planar, Y-Cb-Cr",
+- .pixelformat = V4L2_PIX_FMT_YUV420,
+- }
+-};
+-
+-
+-const struct v4l2_fmtdesc tvenc_output_formats[] = {
+- {
+- .index = 0,
+- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
+- .description = "16 bpp RGB, le",
+- .pixelformat = V4L2_PIX_FMT_RGB565,
+- .flags = FORMAT_FLAGS_PACKED,
+- },
+- {
+- .index = 1,
+- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
+- .flags = FORMAT_FLAGS_PACKED,
+- .description = "24 bpp RGB, le",
+- .pixelformat = V4L2_PIX_FMT_RGB24,
+- },
+- {
+- .index = 2,
+- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
+- .flags = FORMAT_FLAGS_PLANAR,
+- .description = "4:2:2, planar, Y-Cb-Cr",
+- .pixelformat = V4L2_PIX_FMT_YUV422P,
+-
+- },
+- {
+- .index = 3,
+- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT,
+- .flags = FORMAT_FLAGS_PLANAR,
+- .description = "4:2:0, planar, Y-Cb-Cr",
+- .pixelformat = V4L2_PIX_FMT_YUV420,
+- }
+-};
+-
+-const struct v4l2_standard tvout_standards[] = {
+- {
+- .index = 0,
+- .id = V4L2_STD_NTSC_M,
+- .name = "NTSC type",
+- },
+- {
+- .index = 1,
+- .id = V4L2_STD_PAL,
+- .name = "PAL type",
+- }
+-};
+-
+-#define NUMBER_OF_INPUT_FORMATS ARRAY_SIZE(tvenc_input_formats)
+-#define NUMBER_OF_OUTPUT_FORMATS ARRAY_SIZE(tvenc_output_formats)
+-#define NUMBER_OF_INPUTS ARRAY_SIZE(tvenc_inputs)
+-#define NUMBER_OF_OUTPUTS ARRAY_SIZE(tvenc_outputs)
+-#define NUMBER_OF_STANDARDS ARRAY_SIZE(tvout_standards)
+-
+-static int s3c_tvenc_g_fmt(struct v4l2_format *f)
+-{
+- int size = sizeof(struct v4l2_pix_format);
+-
+- memset(&f->fmt.pix, 0, size);
+- memcpy(&f->fmt.pix, &tv_param.v2.pixfmt, size);
+-
+- return 0;
+-}
+-
+-static int s3c_tvenc_s_fmt(struct v4l2_format *f)
+-{
+- /* update our state informations */
+- tv_param.v2.pixfmt= f->fmt.pix;
+-
+- // peter LCD output related operation
+- if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_RGB565 ) {
+-
+- tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width;
+- tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height;
+- tv_param.sp.SrcStartX = 0;
+- tv_param.sp.SrcStartY = 0;
+- tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth;
+- tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight;
+-
+- printk("TV-OUT: LCD path operation set\n");
+-
+- // peter for padded data of mfc output
+- } else if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_YUV420) {
+-
+-#ifdef DIVX_TEST // padded output
+- tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width + 2*16;
+- tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height + 2*16;
+- tv_param.sp.SrcStartX = 16;
+- tv_param.sp.SrcStartY = 16;
+- tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth - 2*tv_param.sp.SrcStartX;
+- tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight - 2*tv_param.sp.SrcStartY;
+-#else // not padded output
+- tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width;
+- tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height;
+- tv_param.sp.SrcStartX = 0;
+- tv_param.sp.SrcStartY = 0;
+- tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth;
+- tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight;
+-#endif
+-
+- printk("TV-OUT: MFC path operation set\n");
+-
+- }
+-
+- switch(tv_param.v2.pixfmt.pixelformat) {
+- case V4L2_PIX_FMT_RGB565:
+- tv_param.sp.SrcCSpace = RGB16;
+- break;
+- case V4L2_PIX_FMT_RGB24:
+- tv_param.sp.SrcCSpace = RGB24;
+- break;
+- case V4L2_PIX_FMT_YUV420:
+- tv_param.sp.SrcCSpace = YC420;
+- break;
+- case V4L2_PIX_FMT_YUV422P:
+- tv_param.sp.SrcCSpace = YC422;
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+-// camif_convert_into_camif_cfg_t(cfg, 1);
+- return 0;
+-}
+-
+-static int s3c_tvenc_s_input(int index)
+-{
+-
+- tv_param.v2.input = &tvenc_inputs[index];
+- switch(tv_param.v2.input->type) {
+- case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT
+- tv_param.sp.InPath = POST_FIFO;
+- break;
+- case V4L2_INPUT_TYPE_MSDMA: // MSDMA
+- tv_param.sp.InPath = POST_DMA;
+- break;
+- default:
+- return -EINVAL;
+- }
+- return 0;
+-}
+-
+-static int s3c_tvenc_s_output(int index)
+-{
+- tv_param.v2.output = &tvenc_outputs[index];
+- switch(tv_param.v2.output->type) {
+- case V4L2_OUTPUT_TYPE_ANALOG: // TV-OUT (FIFO-OUT)
+- tv_param.sp.OutPath = POST_FIFO;
+- break;
+- case V4L2_OUTPUT_TYPE_MSDMA: // MSDMA
+- tv_param.sp.OutPath = POST_DMA;
+- break;
+- default:
+- return -EINVAL;
+- }
+- return 0;
+-}
+-
+-static int s3c_tvenc_s_std(v4l2_std_id *id)
+-{
+-// printk("s3c_tvenc_s_std: *id=0x%x",*id);
+- switch(*id) {
+- case V4L2_STD_NTSC_M:
+- tv_param.sig_type = NTSC_M;
+- tv_param.sp.DstFullWidth = 720;
+- tv_param.sp.DstFullHeight = 480;
+- break;
+- case V4L2_STD_PAL:
+- tv_param.sig_type = PAL_M;
+- tv_param.sp.DstFullWidth = 720;
+- tv_param.sp.DstFullHeight = 576;
+- break;
+- default:
+- return -EINVAL;
+- }
+- return 0;
+-}
+-
+-static int s3c_tvenc_v4l2_control(struct v4l2_control *ctrl)
+-{
+- switch(ctrl->id) {
+-
+- // peter added for MFC related op.
+- case V4L2_CID_MPEG_STREAM_PID_VIDEO:
+- {
+- tv_param.sp.SrcFrmSt = ctrl->value;
+- return 0;
+- }
+-
+- case V4L2_CID_CONNECT_TYPE:
+- {
+- if(ctrl->value == 0) { // COMPOSITE
+- tv_param.connect = COMPOSITE;
+- } else if(ctrl->value == 1) { //S-VIDEO
+- tv_param.connect = S_VIDEO;
+- } else {
+- return -EINVAL;
+- }
+- return 0;
+- }
+-
+- case V4L2_CID_BRIGHTNESS:
+- {
+- s32 val = ctrl->value;
+- if((val > 0xff)||(val < 0))
+- return -EINVAL;
+- else
+- s3c_tvenc_set_bright(val);
+-
+- return 0;
+- }
+-
+- case V4L2_CID_CONTRAST:
+- {
+- s32 val = ctrl->value;
+- if((val > 0xff)||(val < 0))
+- return -EINVAL;
+- else
+- s3c_tvenc_set_contrast(val);
+-
+- return 0;
+- }
+-
+- case V4L2_CID_GAMMA:
+- {
+- s32 val = ctrl->value;
+- if((val > 0x3)||(val < 0)) {
+- return -EINVAL;
+- } else {
+- s3c_tvenc_enable_gamma_control(ON);
+- s3c_tvenc_set_gamma_gain(val);
+- s3c_tvenc_enable_gamma_control(OFF);
+- }
+- return 0;
+- }
+-
+- case V4L2_CID_HUE:
+- {
+- s32 val = ctrl->value;
+- if((val > 0xff)||(val < 0))
+- return -EINVAL;
+- else
+- s3c_tvenc_set_hue_phase(val);
+-
+- return 0;
+- }
+-
+- case V4L2_CID_HCENTER:
+- {
+- s32 val = ctrl->value;
+- u32 curr_horz, curr_vert;
+-
+- if((val > 0xff)||(val < 0)) {
+- return -EINVAL;
+- } else {
+- s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz);
+- s3c_tvenc_set_active_win_center(curr_vert, val);
+- }
+-
+- return 0;
+- }
+-
+- case V4L2_CID_VCENTER:
+- {
+- s32 val = ctrl->value;
+- u32 curr_horz, curr_vert;
+-
+- if((val > 0x3f)||(val < 0)) {
+- return -EINVAL;
+- } else {
+- s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz);
+- s3c_tvenc_set_active_win_center(val, curr_horz);
+- }
+-
+- return 0;
+- }
+-
+- default:
+- return -EINVAL;
+- }
+- return 0;
+-}
+-
+-int s3c_tvenc_open(struct inode *inode, struct file *filp)
+-{
+- int err;
+-
+- err = video_exclusive_open(inode, filp); // One function of V4l2 driver
+-
+- if(err < 0)
+- return err;
+- filp->private_data = &tv_param;
+-
+- s3c_tvscaler_init();
+-
+- /* Success */
+- return 0;
+-}
+-
+-int s3c_tvenc_release(struct inode *inode, struct file *filp)
+-{
+- video_exclusive_release(inode, filp);
+-
+- /* Success */
+- return 0;
+-}
+-
+-static int s3c_tvenc_do_ioctl(struct inode *inode,struct file *filp,unsigned int cmd,void *arg)
+-{
+- int ret;
+-
+- switch(cmd){
+- case VIDIOC_QUERYCAP:
+- {
+- struct v4l2_capability *cap = arg;
+- strcpy(cap->driver, "S3C TV-OUT driver");
+- strlcpy(cap->card, tv_param.v->name, sizeof(cap->card));
+- sprintf(cap->bus_info, "ARM AHB BUS");
+- cap->version = 0;
+- cap->capabilities = tv_param.v->type2;
+- return 0;
+- }
+-
+- case VIDIOC_OVERLAY:
+- {
+- int on = *(int *)arg;
+-
+- printk("TV-OUT: VIDIOC_OVERLAY on:%d\n", on);
+- if (on != 0) {
+- ret = tvout_start();
+- } else {
+- ret = tvout_stop();
+- }
+- return ret;
+- }
+-
+- case VIDIOC_ENUMINPUT:
+- {
+- struct v4l2_input *i = arg;
+- printk("TV-OUT: VIDIOC_ENUMINPUT : index = %d\n", i->index);
+-
+- if ((i->index) >= NUMBER_OF_INPUTS) {
+- return -EINVAL;
+- }
+- memcpy(i, &tvenc_inputs[i->index], sizeof(struct v4l2_input));
+- return 0;
+- }
+-
+- case VIDIOC_S_INPUT: // 0 -> LCD FIFO-OUT, 1 -> MSDMA
+- {
+- int index = *((int *)arg);
+- printk("TV-OUT: VIDIOC_S_INPUT \n");
+-
+- if (index >= NUMBER_OF_INPUTS) {
+- return -EINVAL;
+- }
+- else {
+- s3c_tvenc_s_input(index);
+- return 0;
+- }
+- }
+-
+- case VIDIOC_G_INPUT:
+- {
+- u32 *i = arg;
+- printk("TV-OUT: VIDIOC_G_INPUT \n");
+- *i = tv_param.v2.input->type;
+- return 0;
+- }
+-
+- case VIDIOC_ENUMOUTPUT:
+- {
+- struct v4l2_output *i = arg;
+- printk("TV-OUT: VIDIOC_ENUMOUTPUT : index = %d\n", i->index);
+-
+- if ((i->index) >= NUMBER_OF_OUTPUTS) {
+- return -EINVAL;
+- }
+- memcpy(i, &tvenc_outputs[i->index], sizeof(struct v4l2_output));
+- return 0;
+- }
+-
+- case VIDIOC_S_OUTPUT: // 0 -> TV / FIFO , 1 -> MSDMA
+- {
+- int index = *((int *)arg);
+- printk("TV-OUT: VIDIOC_S_OUTPUT \n");
+-
+- if (index >= NUMBER_OF_OUTPUTS) {
+- return -EINVAL;
+- }
+- else {
+- s3c_tvenc_s_output(index);
+- return 0;
+- }
+- }
+-
+- case VIDIOC_G_OUTPUT:
+- {
+- u32 *i = arg;
+- printk("VIDIOC_G_OUTPUT \n");
+- *i = tv_param.v2.output->type;
+- return 0;
+- }
+-
+- case VIDIOC_ENUM_FMT:
+- { struct v4l2_fmtdesc *f = arg;
+- enum v4l2_buf_type type = f->type;
+- int index = f->index;
+-
+- printk("C: VIDIOC_ENUM_FMT : index = %d\n", index);
+- if (index >= NUMBER_OF_INPUT_FORMATS)
+- return -EINVAL;
+-
+- switch (type) {
+- case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+- break;
+- case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+- default:
+- return -EINVAL;
+- }
+- memset(f, 0, sizeof(*f));
+- memcpy(f, tv_param.v2.fmtdesc+index, sizeof(*f));
+- return 0;
+- }
+-
+- case VIDIOC_G_FMT:
+- {
+- struct v4l2_format *f = arg;
+- printk("C: VIDIOC_G_FMT \n");
+- ret = s3c_tvenc_g_fmt(f);
+- return ret;
+- }
+-
+- case VIDIOC_S_FMT:
+- {
+- struct v4l2_format *f = arg;
+- printk("C: VIDIOC_S_FMT \n");
+- ret = s3c_tvenc_s_fmt(f);
+- if(ret != 0) {
+- printk("s3c_tvenc_set_fmt() failed !\n");
+- return -EINVAL;
+- }
+- return ret;
+- }
+-
+- case VIDIOC_S_CTRL:
+- {
+- struct v4l2_control *ctrl = arg;
+- //printk("P: VIDIOC_S_CTRL \n");
+- ret = s3c_tvenc_v4l2_control(ctrl);
+- return ret;
+- }
+-
+- case VIDIOC_ENUMSTD:
+- {
+- struct v4l2_standard *e = arg;
+- unsigned int index = e->index;
+-
+- if (index >= NUMBER_OF_STANDARDS)
+- return -EINVAL;
+- v4l2_video_std_construct(e, tvout_standards[e->index].id,
+- &tvout_standards[e->index].name);
+- e->index = index;
+- return 0;
+- }
+-
+- case VIDIOC_G_STD:
+- {
+- v4l2_std_id *id = arg;
+- *id = tvout_standards[0].id;
+- return 0;
+- }
+-
+- case VIDIOC_S_STD:
+- {
+- v4l2_std_id *id = arg;
+- unsigned int i;
+-
+- for (i = 0; i < NUMBER_OF_STANDARDS; i++) {
+- //printk("P: *id = %d, tvout_standards[i].id = %d\n", *id, tvout_standards[i].id);
+- if (*id & tvout_standards[i].id)
+- break;
+- }
+- if (i == NUMBER_OF_STANDARDS)
+- return -EINVAL;
+-
+- ret = s3c_tvenc_s_std(id);
+- return ret;
+- }
+-
+- case VIDIOC_S_TVOUT_ON:
+- {
+- //int *SrcFrmSt = arg;
+- //printk("---peter VIDIOC_S_TVOUT_ON : SrcFrmSt = 0x%08x\n", *SrcFrmSt);
+- ret = tvout_start();
+- return ret;
+- }
+-
+- case VIDIOC_S_TVOUT_OFF:
+- {
+- ret = tvout_stop();
+- return ret;
+- }
+-
+- case VIDIOC_S_SCALER_TEST:
+- {
+- ret = scaler_test_start();
+- mdelay(1);
+- ret = scaler_test_stop();
+- return ret;
+- }
+-
+- default:
+- return -EINVAL;
+- }
+- return 0;
+-}
+-
+-static int s3c_tvenc_ioctl_v4l2(struct inode *inode, struct file *filp, unsigned int cmd,
+- unsigned long arg)
+-{
+- return video_usercopy(inode, filp, cmd, arg, s3c_tvenc_do_ioctl);
+-}
+-
+-int s3c_tvenc_read(struct file *filp, char *buf, size_t count,
+- loff_t *f_pos)
+-{
+- return 0;
+-}
+-
+-int s3c_tvenc_write(struct file *filp, const char *buf, size_t
+- count, loff_t *f_pos)
+-{
+- return 0;
+-}
+-
+-int s3c_tvenc_mmap(struct file *filp, struct vm_area_struct *vma)
+-{
+- u32 size = vma->vm_end - vma->vm_start;
+- u32 max_size;
+- u32 page_frame_no;
+-
+- page_frame_no = __phys_to_pfn(POST_BUFF_BASE_ADDR);
+-
+- max_size = RESERVE_POST_MEM + PAGE_SIZE - (RESERVE_POST_MEM % PAGE_SIZE);
+-
+- if(size > max_size) {
+- return -EINVAL;
+- }
+-
+- vma->vm_flags |= VM_RESERVED;
+-
+- if( remap_pfn_range(vma, vma->vm_start, page_frame_no,
+- size, vma->vm_page_prot)) {
+- printk(KERN_ERR "%s: mmap_error\n", __FUNCTION__);
+- return -EAGAIN;
+-
+- }
+-
+- return 0;
+-}
+-
+-struct file_operations s3c_tvenc_fops = {
+- .owner = THIS_MODULE,
+- .open = s3c_tvenc_open,
+- .ioctl = s3c_tvenc_ioctl_v4l2,
+- .release = s3c_tvenc_release,
+- .read = s3c_tvenc_read,
+- .write = s3c_tvenc_write,
+- .mmap = s3c_tvenc_mmap,
+-};
+-
+-void s3c_tvenc_vdev_release (struct video_device *vdev) {
+- kfree(vdev);
+-}
+-
+-struct video_device tvencoder = {
+- .name = "TVENCODER",
+- .type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_SCALES,
+- .type2 = V4L2_CAP_VIDEO_OUTPUT| V4L2_CAP_VIDEO_CAPTURE, /* V4L2 */
+- //.hardware = 0x01, // peter for 2.6.24 kernel
+- .fops = &s3c_tvenc_fops,
+- .release = s3c_tvenc_vdev_release,
+- .minor = TVENC_MINOR,
+-};
+-
+-irqreturn_t s3c_tvenc_isr(int irq, void *dev_id,
+- struct pt_regs *regs)
+-{
+- u32 mode;
+-
+- mode = __raw_readl(base + S3C_TVCTRL);
+-
+- // Clear FIFO under-run status pending bit
+- mode |= (1<<12);
+-
+- __raw_writel(mode, base + S3C_TVCTRL);
+-
+- wake_up_interruptible(&waitq);
+- return IRQ_HANDLED;
+-}
+-
+-static int s3c_tvenc_probe(struct platform_device *pdev)
+-{
+-
+- struct resource *res;
+-
+- int ret;
+-
+- /* find the IRQs */
+- s3c_tvenc_irq = platform_get_irq(pdev, 0);
+- if(s3c_tvenc_irq <= 0) {
+- printk(KERN_ERR PFX "failed to get irq resouce\n");
+- return -ENOENT;
+- }
+-
+- /* get the memory region for the tv scaler driver */
+-
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if(res == NULL) {
+- printk(KERN_ERR PFX "failed to get memory region resouce\n");
+- return -ENOENT;
+- }
+-
+- s3c_tvenc_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name);
+- if(s3c_tvenc_mem == NULL) {
+- printk(KERN_ERR PFX "failed to reserve memory region\n");
+- return -ENOENT;
+- }
+-
+-
+- base = ioremap(s3c_tvenc_mem->start, s3c_tvenc_mem->end - res->start + 1);
+- if(s3c_tvenc_mem == NULL) {
+- printk(KERN_ERR PFX "failed ioremap\n");
+- return -ENOENT;
+- }
+-
+- tvenc_clock = clk_get(&pdev->dev, "tv_encoder");
+- if(tvenc_clock == NULL) {
+- printk(KERN_ERR PFX "failed to find tvenc clock source\n");
+- return -ENOENT;
+- }
+-
+- clk_enable(tvenc_clock);
+-
+- h_clk = clk_get(&pdev->dev, "hclk");
+- if(h_clk == NULL) {
+- printk(KERN_ERR PFX "failed to find h_clk clock source\n");
+- return -ENOENT;
+- }
+-
+- init_waitqueue_head(&waitq);
+-
+- tv_param.v = video_device_alloc();
+- if(!tv_param.v) {
+- printk(KERN_ERR "s3c-tvenc: video_device_alloc() failed\n");
+- return -ENOMEM;
+- }
+- memcpy(tv_param.v, &tvencoder, sizeof(tvencoder));
+- if(video_register_device(tv_param.v, VFL_TYPE_GRABBER, TVENC_MINOR) != 0) {
+- printk("s3c_camera_driver.c : Couldn't register this codec driver.\n");
+- return 0;
+- }
+-
+- ret = request_irq(s3c_tvenc_irq, s3c_tvenc_isr, SA_INTERRUPT,
+- "TV_ENCODER", NULL);
+- if (ret) {
+- printk("request_irq(TV_ENCODER) failed.\n");
+- return ret;
+- }
+-
+- printk(" Success\n");
+- return 0;
+-}
+-
+-static int s3c_tvenc_remove(struct platform_device *dev)
+-{
+- printk(KERN_INFO "s3c_tvenc_remove called !\n");
+- clk_disable(tvenc_clock);
+- free_irq(s3c_tvenc_irq, NULL);
+- if (s3c_tvenc_mem != NULL) {
+- pr_debug("s3-tvenc: releasing s3c_tvenc_mem\n");
+- iounmap(base);
+- release_resource(s3c_tvenc_mem);
+- kfree(s3c_tvenc_mem);
+- }
+-// video_unregister_device(tv_param.v);
+- return 0;
+-}
+-
+-static int s3c_tvenc_suspend(struct platform_device *dev, pm_message_t state)
+-{
+- clk_disable(tvenc_clock);
+- return 0;
+-}
+-
+-static int s3c_tvenc_resume(struct platform_device *pdev)
+-{
+- clk_enable(tvenc_clock);
+- return 0;
+-}
+-
+-static struct platform_driver s3c_tvenc_driver = {
+- .probe = s3c_tvenc_probe,
+- .remove = s3c_tvenc_remove,
+- .suspend = s3c_tvenc_suspend,
+- .resume = s3c_tvenc_resume,
+- .driver = {
+- .owner = THIS_MODULE,
+- .name = "s3c-tvenc",
+- },
+-};
+-
+-static char banner[] __initdata = KERN_INFO "S3C6410 TV encoder Driver, (c) 2008 Samsung Electronics\n";
+-
+-static int __init s3c_tvenc_init(void)
+-{
+-
+- printk(banner);
+-
+- if(platform_driver_register(&s3c_tvenc_driver) != 0)
+- {
+- printk("Platform Device Register Failed \n");
+- return -1;
+- }
+-
+- printk(" S3C6410 TV encoder Driver module init OK. \n");
+- return 0;
+-}
+-
+-static void __exit s3c_tvenc_exit(void)
+-{
+-
+- video_unregister_device(tv_param.v);
+- platform_driver_unregister(&s3c_tvenc_driver);
+-
+- printk("S3C6410 TV encoder Driver module exit. \n");
+-}
+-
+-
+-module_init(s3c_tvenc_init);
+-module_exit(s3c_tvenc_exit);
+-
+-
+-MODULE_AUTHOR("Peter, Oh");
+-MODULE_DESCRIPTION("S3C TV Encoder Device Driver");
+-MODULE_LICENSE("GPL");
+diff --git a/drivers/media/video/samsung/s3c-tvenc.h b/drivers/media/video/samsung/s3c-tvenc.h
+deleted file mode 100644
+index 30a66a2..0000000
+--- a/drivers/media/video/samsung/s3c-tvenc.h
++++ /dev/null
+@@ -1,165 +0,0 @@
+-#ifndef __S3CTVENC_H_
+-#define __S3CTVENC_H_
+-
+-#include "s3c-tvscaler.h"
+-
+-
+-#define TVENC_IOCTL_MAGIC 'T'
+-
+-typedef struct {
+-
+-} s3c_tvenc_info;
+-
+-#define TV_ON _IO(TVENC_IOCTL_MAGIC, 0)
+-#define TV_OFF _IO(TVENC_IOCTL_MAGIC, 1)
+-#define SELECT_TV_OUT_FORMAT _IO(TVENC_IOCTL_MAGIC, 2)
+-
+-#define TVENC_IOCTL_MAXNR 6
+-
+-#define TVENC_MINOR 14 // Just some number
+-
+-typedef enum {
+- OFF,
+- ON
+-} tv_enc_switch_t;
+-
+-typedef enum {
+- NTSC_M,
+- PAL_M,
+- PAL_BGHID,
+- PAL_N,
+- PAL_NC,
+- PAL_60,
+- NTSC_443,
+- NTSC_J
+-} tv_standard_t;
+-
+-typedef enum {
+- QCIF, CIF/*352x288*/,
+- QQVGA, QVGA, VGA, SVGA/*800x600*/, SXGA/*1280x1024*/, UXGA/*1600x1200*/, QXGA/*2048x1536*/,
+- WVGA/*854x480*/, HD720/*1280x720*/, HD1080/*1920x1080*/
+-} img_size_t;
+-
+-typedef enum {
+- BLACKSTRETCH, WHITESTRETCH, BLUESTRETCH
+-} stretch_color_t;
+-
+-typedef enum {
+- COMPOSITE, S_VIDEO
+-} tv_conn_type_t;
+-
+-typedef enum {
+- BLACK, BLUE, RED, MAGENTA, GREEN, CYAN, YELLOW, WHITE
+-} bg_color_t;
+-
+-typedef enum {
+- MUTE_Y, MUTE_CB, MUTE_CR
+-} mute_type_t;
+-
+-typedef enum {
+- AGC4L, AGC2L, N01, N02, P01, P02
+-} macro_pattern_t;
+-
+-typedef enum {
+- LCD_RGB, LCD_TV, LCD_I80F, LCD_I80S,
+- LCD_TVRGB, LCD_TVI80F, LCD_TVI80S
+-} lcd_local_output_t;
+-
+-/* when App want to change v4l2 parameter,
+- * we instantly store it into v4l2_t v2
+- * and then reflect it to hardware
+- */
+-typedef struct v4l2 {
+- struct v4l2_fmtdesc *fmtdesc;
+-// struct v4l2_framebuffer frmbuf; /* current frame buffer */
+- struct v4l2_pix_format pixfmt;
+- struct v4l2_input *input;
+- struct v4l2_output *output;
+-// enum v4l2_status status;
+-} v4l2_t;
+-
+-
+-typedef struct {
+- tv_standard_t sig_type;
+- tv_conn_type_t connect;
+- /* Width of input image. The input value is twice original output image
+- * width. For example, you must set 1440 when the image width is 720.
+- * Max value is 1440
+- */
+- unsigned int in_width;
+- /* Height of input image
+- * Max value is 576
+- */
+- unsigned int in_height;
+-
+- // Setting value of VIDOUT[28:26] in Display
+- // controller(VIDCON0)
+- lcd_local_output_t lcd_output_mode;
+- // Set CLKVAL_F[13:6] of VIDCON0 with
+- // this value
+- unsigned int lcd_clkval_f;
+-
+- // Flag of lcd rgb port
+- // 0 : disable, 1 : enable
+- unsigned int lcd_rgb_port_flag;
+-
+- scaler_params_t sp;
+-
+- struct video_device *v;
+- v4l2_t v2;
+-
+-} tv_out_params_t;
+-
+-#define V4L2_INPUT_TYPE_MSDMA 3
+-#define V4L2_INPUT_TYPE_FIFO 4
+-#define V4L2_OUTPUT_TYPE_MSDMA 4
+-
+-#define FORMAT_FLAGS_DITHER 0x01
+-#define FORMAT_FLAGS_PACKED 0x02
+-#define FORMAT_FLAGS_PLANAR 0x04
+-#define FORMAT_FLAGS_RAW 0x08
+-#define FORMAT_FLAGS_CrCb 0x10
+-
+-/****************************************************************
+-* struct v4l2_control
+-* Control IDs defined by S3C
+-*****************************************************************/
+-
+-/* TV-OUT connector type */
+-#define V4L2_CID_CONNECT_TYPE (V4L2_CID_PRIVATE_BASE+0)
+-
+-/****************************************************************
+-* I O C T L C O D E S F O R V I D E O D E V I C E S
+-* It's only for S3C
+-*****************************************************************/
+-#define VIDIOC_S_TVOUT_ON _IO ('V', BASE_VIDIOC_PRIVATE+0)
+-#define VIDIOC_S_TVOUT_OFF _IO ('V', BASE_VIDIOC_PRIVATE+1)
+-#define VIDIOC_S_SCALER_TEST _IO ('V', BASE_VIDIOC_PRIVATE+3)
+-
+-
+-extern void s3c_tvscaler_config(scaler_params_t * sp);
+-extern void s3c_tvscaler_int_enable(unsigned int int_type);
+-extern void s3c_tvscaler_int_disable(void);
+-extern void s3c_tvscaler_start(void);
+-extern void s3c_tvscaler_stop_freerun(void);
+-extern void s3c_tvscaler_init(void);
+-extern void s3c_tvscaler_set_interlace(unsigned int on_off);
+-extern int video_exclusive_release(struct inode * inode, struct file * file);
+-extern int video_exclusive_open(struct inode * inode, struct file * file);
+-
+-#if 0 // peter for 2.6.21 kernel
+-extern void s3c_fb_start_lcd(void);
+-extern void s3c_fb_stop_lcd(void);
+-extern void s3c_fb_set_output_path(int out);
+-extern void s3c_fb_set_clkval(unsigned int clkval);
+-extern void s3c_fb_enable_rgbport(unsigned int on_off);
+-#else // peter for 2.6.24 kernel
+-extern void s3cfb_start_lcd(void);
+-extern void s3cfb_stop_lcd(void);
+-extern void s3cfb_set_output_path(int out);
+-extern void s3cfb_set_clock(unsigned int clkval);
+-extern void s3cfb_enable_rgbport(unsigned int on_off);
+-#endif
+-
+-
+-#endif // __S3CTVENC_H_
+diff --git a/drivers/media/video/samsung/s3c-tvscaler.c b/drivers/media/video/samsung/s3c-tvscaler.c
+deleted file mode 100644
+index 376c866..0000000
+--- a/drivers/media/video/samsung/s3c-tvscaler.c
++++ /dev/null
+@@ -1,802 +0,0 @@
+-
+-/*
+- * linux/drivers/tvenc/s3c-tvscaler.c
+- *
+- * Revision 1.0
+- *
+- *
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License. See the file COPYING in the main directory of this archive for
+- * more details.
+- *
+- * S3C TV Scaler driver
+- *
+- */
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/types.h>
+-#include <linux/timer.h>
+-#include <linux/kernel.h>
+-#include <linux/fs.h>
+-#include <linux/platform_device.h>
+-#include <linux/interrupt.h>
+-#include <linux/clk.h>
+-#include <linux/delay.h>
+-#include <asm/uaccess.h>
+-#include <linux/errno.h> /* error codes */
+-#include <asm/div64.h>
+-#include <linux/mm.h>
+-#include <linux/tty.h>
+-#include <asm/io.h>
+-#include <asm/irq.h>
+-#include <asm/hardware.h>
+-#include <asm/uaccess.h>
+-#include <asm/arch/map.h>
+-#include <linux/miscdevice.h>
+-
+-#include <linux/version.h>
+-#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,16)
+-#include <linux/config.h>
+-#include <asm/arch/registers.h>
+-#else
+-#include <asm/arch/regs-tvscaler.h>
+-#include <asm/arch/regs-s3c6400-clock.h>
+-#endif
+-
+-#include "s3c-tvscaler.h"
+-
+-#define PFX "s3c_tv_scaler"
+-
+-#define SINGLE_BUF 1 // Single buffer mode
+-
+-
+-static struct clk *h_clk;
+-static struct clk *tvscaler_clock;
+-static void __iomem *base;
+-static int s3c_tvscaler_irq = NO_IRQ;
+-static struct resource *s3c_tvscaler_mem;
+-
+-
+-//static unsigned char *addr_start_y;
+-//static unsigned char *addr_start_rgb;
+-
+-static wait_queue_head_t waitq;
+-
+-irqreturn_t s3c_tvscaler_isr(int irq, void *dev_id,
+- struct pt_regs *regs)
+-{
+- u32 mode;
+- mode = __raw_readl(base + S3C_MODE);
+- mode &= ~(1 << 6); /* Clear Source in POST Processor */
+- __raw_writel(mode, base + S3C_MODE);
+-
+-// wake_up_interruptible(&waitq);
+- return IRQ_HANDLED;
+-}
+-
+-#if 0
+-static buff_addr_t buf_addr = { NULL };
+-
+-
+-static u32 post_alloc_pre_buff(scaler_params_t *sp)
+-{
+- u32 size;
+-
+-#ifdef USE_DEDICATED_MEM
+-
+- buf_addr.pre_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM);
+- buf_addr.pre_virt_addr = ioremap_nocache(buf_addr.pre_phy_addr, PRE_BUFF_SIZE);
+- if( !buf_addr.pre_virt_addr ) {
+- printk(KERN_ERR "%s: Failed to allocate pre buffer \n",__FUNCTION__);
+- return -ENOMEM;
+- }
+-
+- sp->SrcFrmSt = buf_addr.pre_phy_addr;
+-#else
+- size = sp->SrcWidth * sp->SrcHeight * 2;
+- addr_start_y = kmalloc(size, GFP_DMA);
+- if(addr_start_y != NULL) return -ENOMEM;
+-#endif
+- return 0;
+-}
+-
+-static u32 post_alloc_post_buff(scaler_params_t *sp)
+-{
+- u32 size;
+-
+-#ifdef USE_DEDICATED_MEM
+-
+- buf_addr.post_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM + PRE_BUFF_SIZE);
+- buf_addr.post_virt_addr = ioremap_nocache(buf_addr.post_phy_addr, POST_BUFF_SIZE);
+- if( !buf_addr.post_virt_addr ) {
+- printk(KERN_ERR "%s: Failed to allocate post buffer \n",__FUNCTION__);
+- return -ENOMEM;
+- }
+-
+- sp->DstFrmSt = buf_addr.post_phy_addr;
+-#else
+- size = sp->DstWidth * sp->DstHeight * 2;
+- addr_start_rgb = kmalloc(size, GFP_DMA);
+- if(addr_start_rgb != NULL) return -ENOMEM;
+-#endif
+- return 0;
+-}
+-
+-static u32 post_free_all_buffer(void)
+-{
+-#ifdef USE_DEDICATED_MEM
+- if( buf_addr.pre_virt_addr ) {
+- iounmap(buf_addr.pre_virt_addr);
+- }
+- if( buf_addr.post_virt_addr ) {
+- iounmap(buf_addr.post_virt_addr);
+- }
+-#endif
+- return 0;
+-}
+-#endif
+-
+-static void s3c_tvscaler_set_clk_src(scaler_clk_src_t clk_src)
+-{
+- u32 tmp, rate;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- h_clk = clk_get(NULL, "hclk");
+-
+- rate = clk_get_rate(h_clk);
+-
+- if(clk_src == HCLK) {
+- if(rate > 66000000) {
+- tmp &= ~(0x7f<<23);
+- tmp |= (1<<24);
+- tmp |= (1<<23);
+- } else {
+- tmp &=~ (0x7f<<23);
+- }
+-
+- } else if(clk_src == PLL_EXT) {
+- } else {
+- tmp &=~(0x7f<<23);
+- }
+-
+- tmp = (tmp &~ (0x3<<21)) | (clk_src<<21);
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-}
+-
+-static void s3c_tvscaler_set_fmt(cspace_t src, cspace_t dst, s3c_scaler_path_t in,
+- s3c_scaler_path_t out, u32 *in_pixel_size,
+- u32 *out_pixel_size)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+- tmp |= (0x1<<16);
+- tmp |= (0x2<<10);
+-
+- if(in == POST_DMA) {
+-
+- switch(src) {
+- case YC420:
+- tmp &=~((0x1<<3)|(0x1<<2));
+- tmp |= (0x1<<8)|(0x1<<1);
+- *in_pixel_size = 1;
+- break;
+- case CRYCBY:
+- tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3)|(0x1<<0));
+- tmp |= (0x1<<2)|(0x1<<1);
+- *in_pixel_size = 2;
+- break;
+- case CBYCRY:
+- tmp &= ~((0x1<<8)|(0x1<<3)|(0x1<<0));
+- tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1);
+- *in_pixel_size = 2;
+- break;
+- case YCRYCB:
+- tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3));
+- tmp |= (0x1<<2)|(0x1<<1)|(0x1<<0);
+- *in_pixel_size = 2;
+- break;
+- case YCBYCR:
+- tmp &= ~((0x1<<8)|(0x1<<3));
+- tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1)|(0x1<<0);
+- *in_pixel_size = 2;
+- break;
+- case RGB24:
+- tmp &= ~(0x1<<8);
+- tmp |= (0x1<<3)|(0x1<<2)|(0x1<<1);
+- *in_pixel_size = 4;
+- break;
+- case RGB16:
+- tmp &= ~((0x1<<8)|(0x1<<1));
+- tmp |= (0x1<<3)|(0x1<<2);
+- *in_pixel_size = 2;
+- break;
+- default:
+- break;
+- }
+-
+- }
+- else if(in == POST_FIFO) {
+- }
+-
+- if(out == POST_DMA) {
+- switch(dst) {
+- case YC420:
+- tmp &= ~(0x1<<18);
+- tmp |= (0x1<<17);
+- *out_pixel_size = 1;
+- break;
+- case CRYCBY:
+- tmp &= ~((0x1<<20)|(0x1<<19)|(0x1<<18)|(0x1<<17));
+- *out_pixel_size = 2;
+- break;
+- case CBYCRY:
+- tmp &= ~((0x1<<19)|(0x1<<18)|(0x1<<17));
+- tmp |= (0x1<<20);
+- *out_pixel_size = 2;
+- break;
+- case YCRYCB:
+- tmp &= ~((0x1<<20)|(0x1<<18)|(0x1<<17));
+- tmp |= (0x1<<19);
+- *out_pixel_size = 2;
+- break;
+- case YCBYCR:
+- tmp &= ~((0x1<<18)|(0x1<<17));
+- tmp |= (0x1<<20)|(0x1<<19);
+- *out_pixel_size = 2;
+- break;
+- case RGB24:
+- tmp |= (0x1<<18)|(0x1<<4);
+- *out_pixel_size = 4;
+- break;
+- case RGB16:
+- tmp &= ~(0x1<<4);
+- tmp |= (0x1<<18);
+- *out_pixel_size = 2;
+- break;
+- default:
+- break;
+- }
+- }
+- else if(out == POST_FIFO) {
+- if(dst == RGB24) {
+- tmp |= (0x1<<18)|(0x1<<13);
+-
+- } else if(dst == YCBYCR) {
+- tmp |= (0x1<<13);
+- tmp &= ~(0x1<<18)|(0x1<<17);
+- } else {
+- }
+- }
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-}
+-
+-static void s3c_tvscaler_set_path(s3c_scaler_path_t in, s3c_scaler_path_t out)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- tmp &=~(0x1<<12); // 0: progressive mode, 1: interlace mode
+-
+- if(in == POST_FIFO) {
+- tmp |= (0x1<<31);
+- } else if(in == POST_DMA) {
+- tmp &=~(0x1<<31);
+- }
+-
+- if(out == POST_FIFO) {
+- tmp |= (0x1<<13);
+- } else if(out == POST_DMA) {
+- tmp &=~(0x1<<13);
+- }
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-}
+-
+-static void s3c_tvscaler_set_addr(scaler_params_t *sp, u32 in_pixel_size, u32 out_pixel_size)
+-{
+- u32 offset_y, offset_cb, offset_cr;
+- u32 src_start_y, src_start_cb, src_start_cr;
+- u32 src_end_y, src_end_cb, src_end_cr;
+- u32 start_pos_y, end_pos_y;
+- u32 start_pos_cb, end_pos_cb;
+- u32 start_pos_cr, end_pos_cr;
+- u32 start_pos_rgb, end_pos_rgb;
+- u32 dst_start_rgb, dst_end_rgb;
+- u32 src_frm_start_addr;
+-
+- u32 offset_rgb, out_offset_cb, out_offset_cr;
+- u32 out_start_pos_cb, out_start_pos_cr;
+- u32 out_end_pos_cb, out_end_pos_cr;
+- u32 out_src_start_cb, out_src_start_cr;
+- u32 out_src_end_cb, out_src_end_cr;
+-
+- if(sp->InPath == POST_DMA) {
+- offset_y = (sp->SrcFullWidth - sp->SrcWidth) * in_pixel_size;
+- start_pos_y = (sp->SrcFullWidth*sp->SrcStartY+sp->SrcStartX)*in_pixel_size;
+- end_pos_y = sp->SrcWidth*sp->SrcHeight*in_pixel_size + offset_y*(sp->SrcHeight-1);
+- src_frm_start_addr = sp->SrcFrmSt;
+- src_start_y = sp->SrcFrmSt + start_pos_y;
+- src_end_y = src_start_y + end_pos_y;
+-
+- __raw_writel(src_start_y, base + S3C_ADDRSTART_Y);
+- __raw_writel(offset_y, base + S3C_OFFSET_Y);
+- __raw_writel(src_end_y, base + S3C_ADDREND_Y);
+-
+- if(sp->SrcCSpace == YC420) {
+- offset_cb = offset_cr = ((sp->SrcFullWidth - sp->SrcWidth) / 2) * in_pixel_size;
+- start_pos_cb = sp->SrcFullWidth * sp->SrcFullHeight * 1 \
+- + (sp->SrcFullWidth * sp->SrcStartY / 2 + sp->SrcStartX) /2 * 1;
+-
+- end_pos_cb = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \
+- + (sp->SrcHeight/2 -1)*offset_cb;
+- start_pos_cr = sp->SrcFullWidth * sp->SrcFullHeight *1 \
+- + sp->SrcFullWidth*sp->SrcFullHeight/4 *1 \
+- + (sp->SrcFullWidth*sp->SrcStartY/2 + sp->SrcStartX)/2*1;
+- end_pos_cr = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \
+- + (sp->SrcHeight/2-1)*offset_cr;
+-
+- src_start_cb = sp->SrcFrmSt + start_pos_cb;
+- src_end_cb = src_start_cb + end_pos_cb;
+-
+- src_start_cr = sp->SrcFrmSt + start_pos_cr;
+- src_end_cr = src_start_cr + end_pos_cr;
+-
+- __raw_writel(src_start_cb, base + S3C_ADDRSTART_CB);
+- __raw_writel(offset_cr, base + S3C_OFFSET_CB);
+- __raw_writel(src_end_cb, base + S3C_ADDREND_CB);
+- __raw_writel(src_start_cr, base + S3C_ADDRSTART_CR);
+- __raw_writel(offset_cb, base + S3C_OFFSET_CR);
+- __raw_writel(src_end_cr, base + S3C_ADDREND_CR);
+- }
+- }
+- if(sp->OutPath == POST_DMA) {
+- offset_rgb = (sp->DstFullWidth - sp->DstWidth)*out_pixel_size;
+- start_pos_rgb = (sp->DstFullWidth*sp->DstStartY + sp->DstStartX)*out_pixel_size;
+- end_pos_rgb = sp->DstWidth*sp->DstHeight*out_pixel_size + offset_rgb*(sp->DstHeight - 1);
+- dst_start_rgb = sp->DstFrmSt + start_pos_rgb;
+- dst_end_rgb = dst_start_rgb + end_pos_rgb;
+-
+- __raw_writel(dst_start_rgb, base + S3C_ADDRSTART_RGB);
+- __raw_writel(offset_rgb, base + S3C_OFFSET_RGB);
+- __raw_writel(dst_end_rgb, base + S3C_ADDREND_RGB);
+-
+- if(sp->DstCSpace == YC420) {
+- out_offset_cb = out_offset_cr = ((sp->DstFullWidth - sp->DstWidth)/2)*out_pixel_size;
+- out_start_pos_cb = sp->DstFullWidth*sp->DstFullHeight*1 \
+- + (sp->DstFullWidth*sp->DstStartY/2 + sp->DstStartX)/2*1;
+- out_end_pos_cb = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \
+- + (sp->DstHeight/2 -1)*out_offset_cr;
+-
+- out_start_pos_cr = sp->DstFullWidth*sp->DstFullHeight*1 \
+- + (sp->DstFullWidth*sp->DstFullHeight/4)*1 \
+- + (sp->DstFullWidth*sp->DstStartY/2 +sp->DstStartX)/2*1;
+- out_end_pos_cr = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \
+- + (sp->DstHeight/2 -1)*out_offset_cb;
+-
+- out_src_start_cb = sp->DstFrmSt + out_start_pos_cb;
+- out_src_end_cb = out_src_start_cb + out_end_pos_cb;
+- out_src_start_cr = sp->DstFrmSt + out_start_pos_cr;
+- out_src_end_cr = out_src_start_cr + out_end_pos_cr;
+-
+- __raw_writel(out_src_start_cb, base + S3C_ADDRSTART_OCB);
+- __raw_writel(out_offset_cb, base + S3C_OFFSET_OCB);
+- __raw_writel(out_src_end_cb, base + S3C_ADDREND_OCB);
+- __raw_writel(out_src_start_cr, base + S3C_ADDRSTART_OCR);
+- __raw_writel(out_offset_cr, base + S3C_OFFSET_OCR);
+- __raw_writel(out_src_end_cr, base + S3C_ADDREND_OCR);
+-
+- }
+- }
+-
+-
+-}
+-
+-#if 0
+-static void s3c_tvscaler_set_fifo_in(s3c_scaler_path_t in_path)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- if(in_path == POST_FIFO) tmp |= (0x1<<31);
+- else tmp &=~(0x1<<31);
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-
+-}
+-#endif
+-
+-void s3c_tvscaler_set_interlace(u32 on_off)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- if(on_off == 1) tmp |=(1<<12);
+- else tmp &=~(1<<12);
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_set_interlace);
+-
+-static void s3c_tvscaler_set_size(scaler_params_t *sp)
+-{
+- u32 pre_h_ratio, pre_v_ratio, h_shift, v_shift, sh_factor;
+- u32 pre_dst_width, pre_dst_height, dx, dy;
+-
+- if (sp->SrcWidth >= (sp->DstWidth<<6)) {
+- printk("Out of PreScalar range !!!\n");
+- return;
+- }
+- if(sp->SrcWidth >= (sp->DstWidth<<5)) {
+- pre_h_ratio = 32;
+- h_shift = 5;
+- } else if(sp->SrcWidth >= (sp->DstWidth<<4)) {
+- pre_h_ratio = 16;
+- h_shift = 4;
+- } else if(sp->SrcWidth >= (sp->DstWidth<<3)) {
+- pre_h_ratio = 8;
+- h_shift = 3;
+- } else if(sp->SrcWidth >= (sp->DstWidth<<2)) {
+- pre_h_ratio = 4;
+- h_shift = 2;
+- } else if(sp->SrcWidth >= (sp->DstWidth<<1)) {
+- pre_h_ratio = 2;
+- h_shift = 1;
+- } else {
+- pre_h_ratio = 1;
+- h_shift = 0;
+- }
+-
+- pre_dst_width = sp->SrcWidth / pre_h_ratio;
+- dx = (sp->SrcWidth<<8) / (sp->DstWidth<<h_shift);
+-
+-
+- if (sp->SrcHeight >= (sp->DstHeight<<6)) {
+- printk("Out of PreScalar range !!!\n");
+- return;
+- }
+- if(sp->SrcHeight>= (sp->DstHeight<<5)) {
+- pre_v_ratio = 32;
+- v_shift = 5;
+- } else if(sp->SrcHeight >= (sp->DstHeight<<4)) {
+- pre_v_ratio = 16;
+- v_shift = 4;
+- } else if(sp->SrcHeight >= (sp->DstHeight<<3)) {
+- pre_v_ratio = 8;
+- v_shift = 3;
+- } else if(sp->SrcHeight >= (sp->DstHeight<<2)) {
+- pre_v_ratio = 4;
+- v_shift = 2;
+- } else if(sp->SrcHeight >= (sp->DstHeight<<1)) {
+- pre_v_ratio = 2;
+- v_shift = 1;
+- } else {
+- pre_v_ratio = 1;
+- v_shift = 0;
+- }
+-
+- pre_dst_height = sp->SrcHeight / pre_v_ratio;
+- dy = (sp->SrcHeight<<8) / (sp->DstHeight<<v_shift);
+- sh_factor = 10 - (h_shift + v_shift);
+-
+- __raw_writel((pre_v_ratio<<7)|(pre_h_ratio<<0), base + S3C_PRESCALE_RATIO);
+- __raw_writel((pre_dst_height<<12)|(pre_dst_width<<0), base + S3C_PRESCALEIMGSIZE);
+- __raw_writel(sh_factor, base + S3C_PRESCALE_SHFACTOR);
+- __raw_writel(dx, base + S3C_MAINSCALE_H_RATIO);
+- __raw_writel(dy, base + S3C_MAINSCALE_V_RATIO);
+- __raw_writel((sp->SrcHeight<<12)|(sp->SrcWidth), base + S3C_SRCIMGSIZE);
+- __raw_writel((sp->DstHeight<<12)|(sp->DstWidth), base + S3C_DSTIMGSIZE);
+-
+-}
+-
+-
+-static void s3c_tvscaler_set_auto_load(scaler_params_t *sp)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- if(sp->Mode == FREE_RUN) {
+- tmp |= (1<<14);
+- } else if(sp->Mode == ONE_SHOT) {
+- tmp &=~(1<<14);
+- }
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-
+-}
+-
+-void s3c_tvscaler_set_base_addr(void __iomem * base_addr)
+-{
+- base = base_addr;
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_set_base_addr);
+-
+-void s3c_tvscaler_free_base_addr(void)
+-{
+- base = NULL;
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_free_base_addr);
+-
+-void s3c_tvscaler_int_enable(u32 int_type)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- if(int_type == 0) { //Edge triggering
+- tmp &= ~(S3C_MODE_IRQ_LEVEL);
+- } else if(int_type == 1) { //level triggering
+- tmp |= S3C_MODE_IRQ_LEVEL;
+- }
+-
+- tmp |= S3C_MODE_POST_INT_ENABLE;
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_int_enable);
+-
+-void s3c_tvscaler_int_disable(void)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- tmp &=~ (S3C_MODE_POST_INT_ENABLE);
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_int_disable);
+-
+-
+-void s3c_tvscaler_start(void)
+-{
+- __raw_writel(S3C_POSTENVID_ENABLE, base + S3C_POSTENVID);
+-
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_start);
+-
+-void s3c_tvscaler_stop_freerun(void)
+-{
+- u32 tmp;
+-
+- tmp = __raw_readl(base + S3C_MODE);
+-
+- tmp &=~(1<<14);
+-
+- __raw_writel(tmp, base + S3C_MODE);
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_stop_freerun);
+-
+-
+-void s3c_tvscaler_config(scaler_params_t *sp)
+-{
+- u32 tmp = 0;
+- u32 in_pixel_size = 0;
+- u32 out_pixel_size = 0;
+- u32 loop = 0;
+-
+- tmp = __raw_readl(base + S3C_POSTENVID);
+- tmp &= ~S3C_POSTENVID_ENABLE;
+- __raw_writel(tmp, base + S3C_POSTENVID);
+-#ifdef SINGLE_BUF
+- tmp = S3C_MODE2_ADDR_CHANGE_DISABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER;
+-#else
+- tmp = S3C_MODE2_ADDR_CHANGE_ENABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER;
+-#endif
+- __raw_writel(tmp, base + S3C_MODE2);
+-
+-// peter mod. start
+- sp->DstStartX = sp->DstStartY = 0;
+- sp->DstWidth = sp->DstFullWidth;
+- sp->DstHeight = sp->DstFullHeight;
+-// peter mod. end
+-
+- sp->DstFrmSt = ( POST_BUFF_BASE_ADDR + PRE_BUFF_SIZE );
+- //printk("\n---peter s3c_tvscaler_config : SrcFrmSt = 0x%08x\n", sp->SrcFrmSt);
+- //printk("---peter s3c_tvscaler_config : DstFrmSt = 0x%08x\n", sp->DstFrmSt);
+-
+- s3c_tvscaler_set_clk_src(HCLK);
+-
+- s3c_tvscaler_set_path(sp->InPath, sp->OutPath);
+-
+- s3c_tvscaler_set_fmt(sp->SrcCSpace, sp->DstCSpace, sp->InPath,
+- sp->OutPath, &in_pixel_size, &out_pixel_size);
+-
+- s3c_tvscaler_set_size(sp);
+-
+- s3c_tvscaler_set_addr(sp, in_pixel_size, out_pixel_size);
+-
+- s3c_tvscaler_set_auto_load(sp);
+-
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_config);
+-
+-void s3c_tvscaler_set_param(scaler_params_t *sp)
+-{
+-#if 0
+- param.SrcFullWidth = sp->SrcFullWidth;
+- param.SrcFullHeight = sp->SrcFullHeight;
+- param.SrcStartX = sp->SrcStartX;
+- param.SrcStartY = sp->SrcStartY;
+- param.SrcWidth = sp->SrcWidth;
+- param.SrcHeight = sp->SrcHeight;
+- param.SrcFrmSt = sp->SrcFrmSt;
+- param.SrcCSpace = sp->SrcCSpace;
+- param.DstFullWidth = sp->DstFullWidth;
+- param.DstFullHeight = sp->DstFullHeight;
+- param.DstStartX = sp->DstStartX;
+- param.DstStartY = sp->DstStartY;
+- param.DstWidth = sp->DstWidth;
+- param.DstHeight = sp->DstHeight;
+- param.DstFrmSt = sp->DstFrmSt;
+- param.DstCSpace = sp->DstCSpace;
+- param.SrcFrmBufNum = sp->SrcFrmBufNum;
+- param.DstFrmSt = sp->DstFrmSt;
+- param.Mode = sp->Mode;
+- param.InPath = sp->InPath;
+- param.OutPath = sp->OutPath;
+-#endif
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_set_param);
+-
+-void s3c_tvscaler_init(void)
+-{
+-
+- int tmp;
+-
+- // Use DOUTmpll source clock as a scaler clock
+- tmp = __raw_readl(S3C_CLK_SRC);
+-
+- tmp &=~(0x3<<28);
+- tmp |= (0x1<<28);
+- __raw_writel(tmp, S3C_CLK_SRC);
+-
+- printk(" %s \n", __FUNCTION__);
+-
+-}
+-EXPORT_SYMBOL(s3c_tvscaler_init);
+-
+-
+-static int s3c_tvscaler_probe(struct platform_device *pdev)
+-{
+-
+- struct resource *res;
+-
+- int ret;
+-
+- /* find the IRQs */
+- s3c_tvscaler_irq = platform_get_irq(pdev, 0);
+- if(s3c_tvscaler_irq <= 0) {
+- printk(KERN_ERR PFX "failed to get irq resouce\n");
+- return -ENOENT;
+- }
+-
+- /* get the memory region for the tv scaler driver */
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if(res == NULL) {
+- printk(KERN_ERR PFX "failed to get memory region resouce\n");
+- return -ENOENT;
+- }
+-
+- s3c_tvscaler_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name);
+- if(s3c_tvscaler_mem == NULL) {
+- printk(KERN_ERR PFX "failed to reserve memory region\n");
+- return -ENOENT;
+- }
+-
+- base = ioremap(s3c_tvscaler_mem->start, s3c_tvscaler_mem->end - res->start + 1);
+- if(s3c_tvscaler_mem == NULL) {
+- printk(KERN_ERR PFX "failed ioremap\n");
+- return -ENOENT;
+- }
+-
+- tvscaler_clock = clk_get(&pdev->dev, "tv_encoder");
+- if(tvscaler_clock == NULL) {
+- printk(KERN_ERR PFX "failed to find tvscaler clock source\n");
+- return -ENOENT;
+- }
+-
+- clk_enable(tvscaler_clock);
+-
+- h_clk = clk_get(&pdev->dev, "hclk");
+- if(h_clk == NULL) {
+- printk(KERN_ERR PFX "failed to find h_clk clock source\n");
+- return -ENOENT;
+- }
+-
+- init_waitqueue_head(&waitq);
+-
+- ret = request_irq(s3c_tvscaler_irq, s3c_tvscaler_isr, SA_INTERRUPT,
+- "TV_SCALER", NULL);
+- if (ret) {
+- printk("request_irq(TV_SCALER) failed.\n");
+- return ret;
+- }
+-
+- printk(" Success\n");
+-
+- return 0;
+-}
+-
+-static int s3c_tvscaler_remove(struct platform_device *dev)
+-{
+- printk(KERN_INFO "s3c_tvscaler_remove called !\n");
+- clk_disable(tvscaler_clock);
+- free_irq(s3c_tvscaler_irq, NULL);
+- if (s3c_tvscaler_mem != NULL) {
+- pr_debug("s3-tvscaler: releasing s3c_tvscaler_mem\n");
+- iounmap(base);
+- release_resource(s3c_tvscaler_mem);
+- kfree(s3c_tvscaler_mem);
+- }
+-
+- return 0;
+-}
+-
+-static int s3c_tvscaler_suspend(struct platform_device *dev, pm_message_t state)
+-{
+- clk_disable(tvscaler_clock);
+- return 0;
+-}
+-
+-static int s3c_tvscaler_resume(struct platform_device *pdev)
+-{
+- clk_enable(tvscaler_clock);
+- return 0;
+-}
+-
+-static struct platform_driver s3c_tvscaler_driver = {
+- .probe = s3c_tvscaler_probe,
+- .remove = s3c_tvscaler_remove,
+- .suspend = s3c_tvscaler_suspend,
+- .resume = s3c_tvscaler_resume,
+- .driver = {
+- .owner = THIS_MODULE,
+- .name = "s3c-tvscaler",
+- },
+-};
+-
+-static char banner[] __initdata = KERN_INFO "S3C6410 TV scaler Driver, (c) 2008 Samsung Electronics\n";
+-
+-
+-int __init s3c_tvscaler_pre_init(void)
+-{
+-
+- printk(banner);
+-
+- if(platform_driver_register(&s3c_tvscaler_driver) != 0)
+- {
+- printk("platform device register Failed \n");
+- return -1;
+- }
+-
+- printk(" S3C6410 TV scaler Driver module init OK. \n");
+-
+- return 0;
+-}
+-
+-void s3c_tvscaler_exit(void)
+-{
+- platform_driver_unregister(&s3c_tvscaler_driver);
+- printk("S3C: tvscaler module exit\n");
+-}
+-
+-module_init(s3c_tvscaler_pre_init);
+-module_exit(s3c_tvscaler_exit);
+-
+-
+-MODULE_AUTHOR("Peter, Oh");
+-MODULE_DESCRIPTION("S3C TV Controller Device Driver");
+-MODULE_LICENSE("GPL");
+-
+-
+diff --git a/drivers/media/video/samsung/s3c-tvscaler.h b/drivers/media/video/samsung/s3c-tvscaler.h
+deleted file mode 100644
+index d8079a3..0000000
+--- a/drivers/media/video/samsung/s3c-tvscaler.h
++++ /dev/null
+@@ -1,96 +0,0 @@
+-#ifndef __S3CTVSCALER_H_
+-#define __S3CTVSCALER_H_
+-
+-#include <asm-arm/arch-s3c2410/reserved_mem.h>
+-
+-#define TVSCALER_IOCTL_MAGIC 'S'
+-
+-#define PPROC_SET_PARAMS _IO(TVSCALER_IOCTL_MAGIC, 0)
+-#define PPROC_START _IO(TVSCALER_IOCTL_MAGIC, 1)
+-#define PPROC_STOP _IO(TVSCALER_IOCTL_MAGIC, 2)
+-#define PPROC_INTERLACE_MODE _IO(TVSCALER_IOCTL_MAGIC, 3)
+-#define PPROC_PROGRESSIVE_MODE _IO(TVSCALER_IOCTL_MAGIC, 4)
+-
+-
+-#define QVGA_XSIZE 320
+-#define QVGA_YSIZE 240
+-
+-#define LCD_XSIZE 320
+-#define LCD_YSIZE 240
+-
+-#define SCALER_MINOR 251 // Just some number
+-
+-
+-//#define SYSTEM_RAM 0x08000000 // 128mb
+-#define SYSTEM_RAM 0x07800000 // 120mb
+-#define RESERVE_POST_MEM 8*1024*1024 // 8mb
+-#define PRE_BUFF_SIZE 4*1024*1024 //4 // 4mb
+-#define POST_BUFF_SIZE ( RESERVE_POST_MEM - PRE_BUFF_SIZE )
+-#if 0
+-#define POST_BUFF_BASE_ADDR (0x50000000 + (SYSTEM_RAM - RESERVE_POST_MEM))
+-#else // TV_RESERVED_MEM_START is defined in the s3c-linux-2.6.21_dev_4_4_15
+-#define POST_BUFF_BASE_ADDR TV_RESERVED_MEM_START
+-#endif
+-
+-#define USE_DEDICATED_MEM 1
+-
+-typedef enum {
+- INTERLACE_MODE,
+- PROGRESSIVE_MODE
+-} s3c_scaler_scan_mode_t;
+-
+-typedef enum {
+- POST_DMA, POST_FIFO
+-} s3c_scaler_path_t;
+-
+-typedef enum {
+- ONE_SHOT, FREE_RUN
+-} s3c_scaler_run_mode_t;
+-
+-typedef enum {
+- PAL1, PAL2, PAL4, PAL8,
+- RGB8, ARGB8, RGB16, ARGB16, RGB18, RGB24, RGB30, ARGB24,
+- YC420, YC422, // Non-interleave
+- CRYCBY, CBYCRY, YCRYCB, YCBYCR, YUV444 // Interleave
+-} cspace_t;
+-
+-typedef enum
+-{
+- HCLK = 0, PLL_EXT = 1, EXT_27MHZ = 3
+-} scaler_clk_src_t;
+-
+-typedef struct{
+- unsigned int SrcFullWidth; // Source Image Full Width(Virtual screen size)
+- unsigned int SrcFullHeight; // Source Image Full Height(Virtual screen size)
+- unsigned int SrcStartX; // Source Image Start width offset
+- unsigned int SrcStartY; // Source Image Start height offset
+- unsigned int SrcWidth; // Source Image Width
+- unsigned int SrcHeight; // Source Image Height
+- unsigned int SrcFrmSt; // Base Address of the Source Image : Physical Address
+- cspace_t SrcCSpace; // Color Space ot the Source Image
+-
+- unsigned int DstFullWidth; // Source Image Full Width(Virtual screen size)
+- unsigned int DstFullHeight; // Source Image Full Height(Virtual screen size)
+- unsigned int DstStartX; // Source Image Start width offset
+- unsigned int DstStartY; // Source Image Start height offset
+- unsigned int DstWidth; // Source Image Width
+- unsigned int DstHeight; // Source Image Height
+- unsigned int DstFrmSt; // Base Address of the Source Image : Physical Address
+- cspace_t DstCSpace; // Color Space ot the Source Image
+-
+- unsigned int SrcFrmBufNum; // Frame buffer number
+- s3c_scaler_run_mode_t Mode; // POST running mode(PER_FRAME or FREE_RUN)
+- s3c_scaler_path_t InPath; // Data path of the source image
+- s3c_scaler_path_t OutPath; // Data path of the desitination image
+-
+-}scaler_params_t;
+-
+-typedef struct{
+- unsigned int pre_phy_addr;
+- unsigned char *pre_virt_addr;
+-
+- unsigned int post_phy_addr;
+- unsigned char *post_virt_addr;
+-} buff_addr_t;
+-
+-#endif //__S3CTVSCALER_H_
+diff --git a/include/asm-arm/arch-s3c2410/reserved_mem.h b/include/asm-arm/arch-s3c2410/reserved_mem.h
+index ba921a4..e6c029d 100644
+--- a/include/asm-arm/arch-s3c2410/reserved_mem.h
++++ b/include/asm-arm/arch-s3c2410/reserved_mem.h
+@@ -17,7 +17,7 @@
+ //#define CONFIG_RESERVED_MEM_JPEG
+ //#define CONFIG_RESERVED_MEM_JPEG_POST
+ //#define CONFIG_RESERVED_MEM_MFC
+-#define CONFIG_RESERVED_MEM_MFC_POST
++//#define CONFIG_RESERVED_MEM_MFC_POST
+ //#define CONFIG_RESERVED_MEM_JPEG_MFC_POST
+ //#define CONFIG_RESERVED_MEM_JPEG_CAMERA
+ //#define CONFIG_RESERVED_MEM_JPEG_POST_CAMERA
+@@ -26,7 +26,7 @@
+ //#define CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA
+ //#define CONFIG_RESERVED_MEM_CMM_MFC_POST
+ //#define CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA
+-//#define CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA
++#define CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA
+
+ #if defined(CONFIG_RESERVED_MEM_JPEG)
+ #define JPEG_RESERVED_MEM_START 0x57800000
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0008-build-TV-by-default.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0008-build-TV-by-default.patch
new file mode 100644
index 0000000000..9425f55361
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0008-build-TV-by-default.patch
@@ -0,0 +1,136 @@
+From fc4f45f5d2c2fd7fa5e4a1b5923129bd6722f102 Mon Sep 17 00:00:00 2001
+From: Carsten V. Munk <carsten.munk@gmail.com>
+Date: Thu, 6 Aug 2009 12:18:57 +0000
+Subject: [PATCH 08/13] build TV by default.
+
+---
+ arch/arm/configs/hhs3c6410_4_3_defconfig | 36 ++++++++++++++++++++-
+ arch/arm/configs/hhs3c6410_7_defconfig | 51 ++++++++++++++++++++++++++++-
+ 2 files changed, 83 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/configs/hhs3c6410_4_3_defconfig b/arch/arm/configs/hhs3c6410_4_3_defconfig
+index aa1758a..d503e12 100644
+--- a/arch/arm/configs/hhs3c6410_4_3_defconfig
++++ b/arch/arm/configs/hhs3c6410_4_3_defconfig
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+ # Linux kernel version: 2.6.24.7
+-# Tue Jun 16 10:48:11 2009
++# Thu Aug 6 11:55:46 2009
+ #
+ CONFIG_ARM=y
+ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+@@ -910,7 +910,39 @@ CONFIG_SSB_POSSIBLE=y
+ #
+ # Multimedia devices
+ #
+-# CONFIG_VIDEO_DEV is not set
++CONFIG_VIDEO_DEV=m
++# CONFIG_VIDEO_V4L1 is not set
++CONFIG_VIDEO_V4L1_COMPAT=y
++CONFIG_VIDEO_V4L2=y
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
++# CONFIG_VIDEO_VIVI is not set
++# CONFIG_VIDEO_SAA5246A is not set
++# CONFIG_VIDEO_SAA5249 is not set
++# CONFIG_VIDEO_SAMSUNG is not set
++CONFIG_VIDEO_SAMSUNG_TVENC=m
++CONFIG_VIDEO_SAMSUNG_TVSCALER=m
++CONFIG_V4L_USB_DRIVERS=y
++# CONFIG_VIDEO_PVRUSB2 is not set
++# CONFIG_VIDEO_USBVISION is not set
++# CONFIG_USB_ET61X251 is not set
++# CONFIG_USB_SN9C102 is not set
++# CONFIG_USB_ZC0301 is not set
++# CONFIG_USB_ZR364XX is not set
++CONFIG_RADIO_ADAPTERS=y
++# CONFIG_RADIO_CADET is not set
++# CONFIG_RADIO_RTRACK is not set
++# CONFIG_RADIO_RTRACK2 is not set
++# CONFIG_RADIO_AZTECH is not set
++# CONFIG_RADIO_GEMTEK is not set
++# CONFIG_RADIO_SF16FMI is not set
++# CONFIG_RADIO_SF16FMR2 is not set
++# CONFIG_RADIO_TERRATEC is not set
++# CONFIG_RADIO_TRUST is not set
++# CONFIG_RADIO_TYPHOON is not set
++# CONFIG_RADIO_ZOLTRIX is not set
++# CONFIG_USB_DSBR is not set
+ # CONFIG_DVB_CORE is not set
+ # CONFIG_DAB is not set
+
+diff --git a/arch/arm/configs/hhs3c6410_7_defconfig b/arch/arm/configs/hhs3c6410_7_defconfig
+index 2d3147a..b0a4f48 100644
+--- a/arch/arm/configs/hhs3c6410_7_defconfig
++++ b/arch/arm/configs/hhs3c6410_7_defconfig
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+ # Linux kernel version: 2.6.24.7
+-# Tue Jun 16 10:44:09 2009
++# Thu Aug 6 12:17:50 2009
+ #
+ CONFIG_ARM=y
+ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+@@ -910,7 +910,54 @@ CONFIG_SSB_POSSIBLE=y
+ #
+ # Multimedia devices
+ #
+-# CONFIG_VIDEO_DEV is not set
++CONFIG_VIDEO_DEV=m
++CONFIG_VIDEO_V4L1=y
++CONFIG_VIDEO_V4L1_COMPAT=y
++CONFIG_VIDEO_V4L2=y
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_ADV_DEBUG is not set
++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
++# CONFIG_VIDEO_VIVI is not set
++# CONFIG_VIDEO_PMS is not set
++# CONFIG_VIDEO_CPIA is not set
++# CONFIG_VIDEO_CPIA2 is not set
++# CONFIG_VIDEO_SAA5246A is not set
++# CONFIG_VIDEO_SAA5249 is not set
++# CONFIG_TUNER_3036 is not set
++# CONFIG_VIDEO_SAMSUNG is not set
++CONFIG_VIDEO_SAMSUNG_TVENC=m
++CONFIG_VIDEO_SAMSUNG_TVSCALER=m
++CONFIG_V4L_USB_DRIVERS=y
++# CONFIG_VIDEO_PVRUSB2 is not set
++# CONFIG_VIDEO_EM28XX is not set
++# CONFIG_VIDEO_USBVISION is not set
++# CONFIG_USB_VICAM is not set
++# CONFIG_USB_IBMCAM is not set
++# CONFIG_USB_KONICAWC is not set
++# CONFIG_USB_QUICKCAM_MESSENGER is not set
++# CONFIG_USB_ET61X251 is not set
++# CONFIG_VIDEO_OVCAMCHIP is not set
++# CONFIG_USB_W9968CF is not set
++# CONFIG_USB_OV511 is not set
++# CONFIG_USB_SE401 is not set
++# CONFIG_USB_SN9C102 is not set
++# CONFIG_USB_STV680 is not set
++# CONFIG_USB_ZC0301 is not set
++# CONFIG_USB_PWC is not set
++# CONFIG_USB_ZR364XX is not set
++CONFIG_RADIO_ADAPTERS=y
++# CONFIG_RADIO_CADET is not set
++# CONFIG_RADIO_RTRACK is not set
++# CONFIG_RADIO_RTRACK2 is not set
++# CONFIG_RADIO_AZTECH is not set
++# CONFIG_RADIO_GEMTEK is not set
++# CONFIG_RADIO_SF16FMI is not set
++# CONFIG_RADIO_SF16FMR2 is not set
++# CONFIG_RADIO_TERRATEC is not set
++# CONFIG_RADIO_TRUST is not set
++# CONFIG_RADIO_TYPHOON is not set
++# CONFIG_RADIO_ZOLTRIX is not set
++# CONFIG_USB_DSBR is not set
+ # CONFIG_DVB_CORE is not set
+ # CONFIG_DAB is not set
+
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0009-Apply-cpufreq-patch-from-gqwang.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0009-Apply-cpufreq-patch-from-gqwang.patch
new file mode 100644
index 0000000000..f83a944e05
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0009-Apply-cpufreq-patch-from-gqwang.patch
@@ -0,0 +1,113 @@
+From 6a2a98218695242634c6f601dd956ef06369d1d3 Mon Sep 17 00:00:00 2001
+From: YouSheng <david.ysh@gmail.com>
+Date: Thu, 20 Aug 2009 13:58:48 +0800
+Subject: [PATCH 09/13] Apply cpufreq patch from gqwang
+
+---
+ arch/arm/plat-s3c64xx/clock.c | 23 +++++++++++------------
+ arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c | 18 +++++++++---------
+ 2 files changed, 20 insertions(+), 21 deletions(-)
+
+diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
+index a776437..1cb7fd4 100644
+--- a/arch/arm/plat-s3c64xx/clock.c
++++ b/arch/arm/plat-s3c64xx/clock.c
+@@ -63,14 +63,17 @@
+ #define PLL_CALC_VAL(MDIV,PDIV,SDIV) ((1<<31)|(MDIV)<<16 |(PDIV)<<8 |(SDIV))
+ #define GET_ARM_CLOCK(baseclk) s3c6400_get_pll(__raw_readl(S3C_APLL_CON),baseclk)
+
+-#define MHZ 1000*1000
+ #define INIT_XTAL 12 * MHZ
+
+ /* enable and disable calls for use with the clk struct */
+ static const u32 s3c_cpu_clock_table[][6] = {
++ //{1100*MHZ, 266, 3, 1, 0, 0},
++ //{800*MHZ, 266, 3, 1, 0, 0},
++ {666*MHZ, 266, 3, 1, 0, 0},
+ {532*MHZ, 266, 3, 1, 0, 0},
+- {266*MHZ, 266, 3, 1, 0, 1},
+- {133*MHZ, 266, 3, 1, 0, 3},
++ {266*MHZ, 266, 3, 1, 0, 0},
++ {133*MHZ, 266, 3, 1, 0, 0},
++ {100*MHZ, 266, 3, 1, 0, 0},
+ };
+
+ /* clock information */
+@@ -286,6 +289,7 @@ unsigned long s3c_fclk_round_rate(struct clk *clk, unsigned long rate)
+ return s3c_cpu_clock_table[ARRAY_SIZE(s3c_cpu_clock_table) - 1][0];
+ }
+
++#define APLL_MDIV_MASK (0x3ff << 16)
+ int s3c_fclk_set_rate(struct clk *clk, unsigned long rate)
+ {
+ u32 ret = -EINVAL;
+@@ -296,20 +300,15 @@ int s3c_fclk_set_rate(struct clk *clk, unsigned long rate)
+
+ round_tmp = s3c_fclk_round_rate(clk,rate);
+
+- if(round_tmp == (int)s3c_fclk_get_rate())
+- return 0;
+-
+ for (iter = 0 ; iter < ARRAY_SIZE(s3c_cpu_clock_table) ; iter++){
+ if(round_tmp == s3c_cpu_clock_table[iter][0])
+ break;
+ }
+
+- clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
+- clk_div0_tmp |= s3c_cpu_clock_table[iter][5];
+-
+- __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+-
+- if (__raw_readl(ARM_CLK_DIV) == clk_div0_tmp)
++ apll_con_tmp = __raw_readl(S3C_APLL_CON) & ~(APLL_MDIV_MASK);
++ apll_con_tmp |= (round_tmp / 2000000) << 16;
++ __raw_writel(apll_con_tmp, S3C_APLL_CON);
++ if (__raw_readl(S3C_APLL_CON) == apll_con_tmp)
+ ret = 0;
+
+ clk->rate = s3c_cpu_clock_table[iter][0];
+diff --git a/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c b/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
+index a509071..fae9890 100644
+--- a/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
++++ b/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c
+@@ -44,13 +44,13 @@ extern int ltc3714_init(void);
+
+ /* frequency */
+ static struct cpufreq_frequency_table s3c6410_freq_table[] = {
+- {APLL_GEN_CLK, 667*1000},
+- {APLL_GEN_CLK, APLL_GEN_CLK},
+- {APLL_GEN_CLK, APLL_GEN_CLK2},
+- {APLL_GEN_CLK, APLL_GEN_CLK/2},
+- {APLL_GEN_CLK, APLL_GEN_CLK2/2},
+- {APLL_GEN_CLK, APLL_GEN_CLK/4},
+- {APLL_GEN_CLK, APLL_GEN_CLK2/4},
++// {0, 1100*1000},
++// {1, 800*1000},
++ {2, 666*1000},
++ {3, 532*1000},
++ {4, 266*1000},
++ {5, 133*1000},
++ {6, 100*1000},
+ {0, CPUFREQ_TABLE_END},
+ };
+
+@@ -142,14 +142,14 @@ static int s3c6410_target(struct cpufreq_policy *policy,
+ set_power(freqs.new);
+
+ /* frequency scaling */
+- ret = clk_set_rate(mpu_clk, target_freq * KHZ_T);
++ ret = clk_set_rate(mpu_clk, freqs.new * KHZ_T);
+ if(ret != 0)
+ printk("frequency scaling error\n");
+ }
+
+
+ #else
+- ret = clk_set_rate(mpu_clk, target_freq * KHZ_T);
++ ret = clk_set_rate(mpu_clk, freqs.new * KHZ_T);
+ if(ret != 0)
+ printk("frequency scaling error\n");
+
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0010-Better-compatibility-with-some-memory-chips.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0010-Better-compatibility-with-some-memory-chips.patch
new file mode 100644
index 0000000000..162335e0c2
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0010-Better-compatibility-with-some-memory-chips.patch
@@ -0,0 +1,77 @@
+From 112a485fecdaeabe2b5fc7c1eea0832d2da26c0d Mon Sep 17 00:00:00 2001
+From: YouSheng <david.ysh@gmail.com>
+Date: Thu, 20 Aug 2009 13:59:22 +0800
+Subject: [PATCH 10/13] Better compatibility with some memory chips
+
+---
+ arch/arm/mach-s3c6410/pm.c | 21 ++++++++++++++++++++-
+ arch/arm/plat-s3c64xx/clock.c | 1 +
+ 2 files changed, 21 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-s3c6410/pm.c b/arch/arm/mach-s3c6410/pm.c
+index af53fdc..4d4ef08 100644
+--- a/arch/arm/mach-s3c6410/pm.c
++++ b/arch/arm/mach-s3c6410/pm.c
+@@ -25,6 +25,7 @@
+ #include <linux/errno.h>
+ #include <linux/time.h>
+ #include <linux/sysdev.h>
++#include <linux/delay.h>
+
+ #include <asm/hardware.h>
+ #include <asm/io.h>
+@@ -84,20 +85,38 @@ static struct sleep_save s3c6410_sleep[] = {
+
+ static int s3c6410_pm_suspend(struct sys_device *dev, pm_message_t state)
+ {
++ u32 apll_con;
+ s3c2410_pm_do_save(s3c6410_sleep, ARRAY_SIZE(s3c6410_sleep));
++
++ /* CPU speed set to 532MHZ */
++ apll_con = __raw_readl(S3C_APLL_CON);
++ apll_con &= ~(0x3FF << 16);
++ apll_con |= 266 << 16;
++ __raw_writel(apll_con, S3C_APLL_CON);
++ udelay(200);
++ /* CPU into sync mode. System clock from APLL */
++ __raw_writel(__raw_readl(S3C_OTHERS) | 0xC0, S3C_OTHERS);
++ /* Wait sync finish */
++ while ((__raw_readl(S3C_OTHERS) & 0xF00) != 0xF00);
++
+ return 0;
+ }
+
+ static int s3c6410_pm_resume(struct sys_device *dev)
+ {
+- unsigned long tmp;
+ #if 0
++ unsigned long tmp;
+ tmp = __raw_readl(S3C_PWR_CFG);
+ tmp &= ~(0x60<<0);
+ tmp |= (0x1<<5);
+ __raw_writel(tmp, S3C_PWR_CFG);
+ #endif
++ /* CPU into async mode. System clock from MPLL */
++ __raw_writel(__raw_readl(S3C_OTHERS) & 0xFF3F, S3C_OTHERS);
++ /* Wait async finish */
++ while (__raw_readl(S3C_OTHERS) & 0xF00);
+ s3c2410_pm_do_restore(s3c6410_sleep, ARRAY_SIZE(s3c6410_sleep));
++
+ return 0;
+ }
+
+diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
+index 1cb7fd4..2eb7e99 100644
+--- a/arch/arm/plat-s3c64xx/clock.c
++++ b/arch/arm/plat-s3c64xx/clock.c
+@@ -308,6 +308,7 @@ int s3c_fclk_set_rate(struct clk *clk, unsigned long rate)
+ apll_con_tmp = __raw_readl(S3C_APLL_CON) & ~(APLL_MDIV_MASK);
+ apll_con_tmp |= (round_tmp / 2000000) << 16;
+ __raw_writel(apll_con_tmp, S3C_APLL_CON);
++ udelay(200);
+ if (__raw_readl(S3C_APLL_CON) == apll_con_tmp)
+ ret = 0;
+
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0011-Only-reserve-memory-for-TV-if-CONFIG_VIDEO_SAMSUNG_T.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0011-Only-reserve-memory-for-TV-if-CONFIG_VIDEO_SAMSUNG_T.patch
new file mode 100644
index 0000000000..1a39d4cbc0
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0011-Only-reserve-memory-for-TV-if-CONFIG_VIDEO_SAMSUNG_T.patch
@@ -0,0 +1,32 @@
+From d4c0c216128feee090df41f81552cca7ff3f44bc Mon Sep 17 00:00:00 2001
+From: David Greaves <david@dgreaves.com>
+Date: Mon, 21 Sep 2009 23:19:36 +0100
+Subject: [PATCH 11/13] Only reserve memory for TV if CONFIG_VIDEO_SAMSUNG_TVENC/TVSCALER are defined
+
+---
+ include/asm-arm/arch-s3c2410/reserved_mem.h | 8 ++++++++
+ 1 files changed, 8 insertions(+), 0 deletions(-)
+
+diff --git a/include/asm-arm/arch-s3c2410/reserved_mem.h b/include/asm-arm/arch-s3c2410/reserved_mem.h
+index e6c029d..9ac227b 100644
+--- a/include/asm-arm/arch-s3c2410/reserved_mem.h
++++ b/include/asm-arm/arch-s3c2410/reserved_mem.h
+@@ -26,7 +26,15 @@
+ //#define CONFIG_RESERVED_MEM_JPEG_MFC_POST_CAMERA
+ //#define CONFIG_RESERVED_MEM_CMM_MFC_POST
+ //#define CONFIG_RESERVED_MEM_CMM_JPEG_MFC_POST_CAMERA
++//#define CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA
++
++// Should do a full config logic here...
++#if defined(CONFIG_VIDEO_SAMSUNG_TVENC) || defined(CONFIG_VIDEO_SAMSUNG_TVSCALER)
+ #define CONFIG_RESERVED_MEM_TV_MFC_POST_CAMERA
++#else
++#define CONFIG_RESERVED_MEM_MFC_POST
++#endif
++
+
+ #if defined(CONFIG_RESERVED_MEM_JPEG)
+ #define JPEG_RESERVED_MEM_START 0x57800000
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/mer/0012-Disable-TV-out-to-save-RAM.patch b/recipes/linux/linux-2.6.24/smartq5/mer/0012-Disable-TV-out-to-save-RAM.patch
new file mode 100644
index 0000000000..8e0d311714
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/mer/0012-Disable-TV-out-to-save-RAM.patch
@@ -0,0 +1,100 @@
+From aa8822574f0c07f391b29737ca00f08d641cb93f Mon Sep 17 00:00:00 2001
+From: David Greaves <david@dgreaves.com>
+Date: Tue, 22 Sep 2009 10:01:40 +0100
+Subject: [PATCH 12/13] Disable TV-out to save RAM
+
+---
+ arch/arm/configs/hhs3c6410_4_3_defconfig | 18 +++++++++---------
+ arch/arm/configs/hhs3c6410_7_defconfig | 20 ++++++++++----------
+ 2 files changed, 19 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/configs/hhs3c6410_4_3_defconfig b/arch/arm/configs/hhs3c6410_4_3_defconfig
+index d503e12..e71e588 100644
+--- a/arch/arm/configs/hhs3c6410_4_3_defconfig
++++ b/arch/arm/configs/hhs3c6410_4_3_defconfig
+@@ -910,27 +910,27 @@ CONFIG_SSB_POSSIBLE=y
+ #
+ # Multimedia devices
+ #
+-CONFIG_VIDEO_DEV=m
++# CONFIG_VIDEO_DEV is not set
+ # CONFIG_VIDEO_V4L1 is not set
+-CONFIG_VIDEO_V4L1_COMPAT=y
+-CONFIG_VIDEO_V4L2=y
+-CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_V4L1_COMPAT is not set
++# CONFIG_VIDEO_V4L2 is not set
++# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
+ # CONFIG_VIDEO_ADV_DEBUG is not set
+-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+ # CONFIG_VIDEO_VIVI is not set
+ # CONFIG_VIDEO_SAA5246A is not set
+ # CONFIG_VIDEO_SAA5249 is not set
+ # CONFIG_VIDEO_SAMSUNG is not set
+-CONFIG_VIDEO_SAMSUNG_TVENC=m
+-CONFIG_VIDEO_SAMSUNG_TVSCALER=m
+-CONFIG_V4L_USB_DRIVERS=y
++# CONFIG_VIDEO_SAMSUNG_TVENC is not set
++# CONFIG_VIDEO_SAMSUNG_TVSCALER is not set
++# CONFIG_V4L_USB_DRIVERS is not set
+ # CONFIG_VIDEO_PVRUSB2 is not set
+ # CONFIG_VIDEO_USBVISION is not set
+ # CONFIG_USB_ET61X251 is not set
+ # CONFIG_USB_SN9C102 is not set
+ # CONFIG_USB_ZC0301 is not set
+ # CONFIG_USB_ZR364XX is not set
+-CONFIG_RADIO_ADAPTERS=y
++# CONFIG_RADIO_ADAPTERS is not set
+ # CONFIG_RADIO_CADET is not set
+ # CONFIG_RADIO_RTRACK is not set
+ # CONFIG_RADIO_RTRACK2 is not set
+diff --git a/arch/arm/configs/hhs3c6410_7_defconfig b/arch/arm/configs/hhs3c6410_7_defconfig
+index b0a4f48..2694716 100644
+--- a/arch/arm/configs/hhs3c6410_7_defconfig
++++ b/arch/arm/configs/hhs3c6410_7_defconfig
+@@ -910,13 +910,13 @@ CONFIG_SSB_POSSIBLE=y
+ #
+ # Multimedia devices
+ #
+-CONFIG_VIDEO_DEV=m
+-CONFIG_VIDEO_V4L1=y
+-CONFIG_VIDEO_V4L1_COMPAT=y
+-CONFIG_VIDEO_V4L2=y
+-CONFIG_VIDEO_CAPTURE_DRIVERS=y
++# CONFIG_VIDEO_DEV is not set
++# CONFIG_VIDEO_V4L1 is not set
++# CONFIG_VIDEO_V4L1_COMPAT is not set
++# CONFIG_VIDEO_V4L2 is not set
++# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
+ # CONFIG_VIDEO_ADV_DEBUG is not set
+-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+ # CONFIG_VIDEO_VIVI is not set
+ # CONFIG_VIDEO_PMS is not set
+ # CONFIG_VIDEO_CPIA is not set
+@@ -925,9 +925,9 @@ CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+ # CONFIG_VIDEO_SAA5249 is not set
+ # CONFIG_TUNER_3036 is not set
+ # CONFIG_VIDEO_SAMSUNG is not set
+-CONFIG_VIDEO_SAMSUNG_TVENC=m
+-CONFIG_VIDEO_SAMSUNG_TVSCALER=m
+-CONFIG_V4L_USB_DRIVERS=y
++# CONFIG_VIDEO_SAMSUNG_TVENC is not set
++# CONFIG_VIDEO_SAMSUNG_TVSCALER is not set
++# CONFIG_V4L_USB_DRIVERS is not set
+ # CONFIG_VIDEO_PVRUSB2 is not set
+ # CONFIG_VIDEO_EM28XX is not set
+ # CONFIG_VIDEO_USBVISION is not set
+@@ -945,7 +945,7 @@ CONFIG_V4L_USB_DRIVERS=y
+ # CONFIG_USB_ZC0301 is not set
+ # CONFIG_USB_PWC is not set
+ # CONFIG_USB_ZR364XX is not set
+-CONFIG_RADIO_ADAPTERS=y
++# CONFIG_RADIO_ADAPTERS is not set
+ # CONFIG_RADIO_CADET is not set
+ # CONFIG_RADIO_RTRACK is not set
+ # CONFIG_RADIO_RTRACK2 is not set
+--
+1.6.2.4
+
diff --git a/recipes/linux/linux-2.6.24/smartq5/smartq-gitupdate.diff b/recipes/linux/linux-2.6.24/smartq5/smartq-gitupdate.diff
new file mode 100644
index 0000000000..d9acf581ab
--- /dev/null
+++ b/recipes/linux/linux-2.6.24/smartq5/smartq-gitupdate.diff
@@ -0,0 +1,8974 @@
+ Makefile | 2
+ arch/mips/Kconfig | 28
+ arch/mips/Makefile | 4
+ arch/mips/au1000/common/clocks.c | 1
+ arch/mips/au1000/common/cputable.c | 36
+ arch/mips/au1000/common/dbdma.c | 34
+ arch/mips/au1000/common/gpio.c | 6
+ arch/mips/au1000/common/platform.c | 14
+ arch/mips/au1000/common/setup.c | 13
+ arch/mips/au1000/common/time.c | 24
+ arch/mips/fw/arc/identify.c | 5
+ arch/mips/kernel/Makefile | 3
+ arch/mips/kernel/asm-offsets.c | 108 +
+ arch/mips/kernel/cevt-r4k.c | 173 -
+ arch/mips/kernel/cevt-smtc.c | 321 +++
+ arch/mips/kernel/cevt-txx9.c | 3
+ arch/mips/kernel/cpu-bugs64.c | 2
+ arch/mips/kernel/cpu-probe.c | 36
+ arch/mips/kernel/csrc-r4k.c | 9
+ arch/mips/kernel/entry.S | 10
+ arch/mips/kernel/gdb-low.S | 24
+ arch/mips/kernel/gdb-stub.c | 3
+ arch/mips/kernel/genex.S | 41
+ arch/mips/kernel/head.S | 4
+ arch/mips/kernel/i8253.c | 1
+ arch/mips/kernel/irixelf.c | 11
+ arch/mips/kernel/irq-rm7000.c | 1
+ arch/mips/kernel/irq-rm9000.c | 1
+ arch/mips/kernel/kspd.c | 5
+ arch/mips/kernel/mips-mt-fpaff.c | 4
+ arch/mips/kernel/proc.c | 2
+ arch/mips/kernel/process.c | 19
+ arch/mips/kernel/ptrace.c | 2
+ arch/mips/kernel/rtlx.c | 65
+ arch/mips/kernel/scall32-o32.S | 15
+ arch/mips/kernel/scall64-64.S | 2
+ arch/mips/kernel/scall64-n32.S | 2
+ arch/mips/kernel/scall64-o32.S | 16
+ arch/mips/kernel/setup.c | 5
+ arch/mips/kernel/smp.c | 6
+ arch/mips/kernel/smtc.c | 257 +-
+ arch/mips/kernel/sysirix.c | 2
+ arch/mips/kernel/time.c | 2
+ arch/mips/kernel/traps.c | 124 -
+ arch/mips/kernel/unaligned.c | 8
+ arch/mips/kernel/vpe.c | 46
+ arch/mips/lasat/interrupt.c | 2
+ arch/mips/lasat/lasat_board.c | 13
+ arch/mips/lasat/sysctl.c | 172 -
+ arch/mips/lasat/sysctl.h | 24
+ arch/mips/lib/csum_partial.S | 21
+ arch/mips/lib/ucmpdi2.c | 2
+ arch/mips/lib/uncached.c | 2
+ arch/mips/math-emu/cp1emu.c | 8
+ arch/mips/mips-boards/generic/time.c | 2
+ arch/mips/mips-boards/malta/Makefile | 3
+ arch/mips/mips-boards/malta/malta_smtc.c | 12
+ arch/mips/mipssim/sim_time.c | 2
+ arch/mips/mm/c-r3k.c | 8
+ arch/mips/mm/c-r4k.c | 60
+ arch/mips/mm/c-tx39.c | 17
+ arch/mips/mm/cache.c | 23
+ arch/mips/mm/cex-sb1.S | 8
+ arch/mips/mm/dma-default.c | 5
+ arch/mips/mm/init.c | 9
+ arch/mips/mm/pg-r4k.c | 22
+ arch/mips/mm/pg-sb1.c | 18
+ arch/mips/mm/sc-ip22.c | 2
+ arch/mips/mm/sc-mips.c | 3
+ arch/mips/mm/sc-r5k.c | 2
+ arch/mips/mm/sc-rm7k.c | 6
+ arch/mips/mm/tlb-r3k.c | 6
+ arch/mips/mm/tlb-r4k.c | 15
+ arch/mips/mm/tlb-r8k.c | 4
+ arch/mips/mm/tlbex.c | 160 -
+ arch/mips/pci/pci-bcm1480.c | 11
+ arch/mips/pci/pci-bcm1480ht.c | 21
+ arch/mips/pci/pci-ip27.c | 42
+ arch/mips/pci/pci.c | 9
+ arch/mips/pmc-sierra/yosemite/smp.c | 6
+ arch/mips/sgi-ip22/ip22-int.c | 8
+ arch/mips/sgi-ip22/ip22-platform.c | 2
+ arch/mips/sgi-ip27/ip27-init.c | 2
+ arch/mips/sgi-ip27/ip27-timer.c | 6
+ arch/mips/sgi-ip27/ip27-xtalk.c | 6
+ arch/mips/sgi-ip32/ip32-irq.c | 5
+ arch/mips/sibyte/bcm1480/irq.c | 1
+ arch/mips/sibyte/sb1250/irq.c | 1
+ arch/mips/vr41xx/common/irq.c | 6
+ drivers/net/Kconfig | 7
+ drivers/net/Makefile | 2
+ drivers/net/titan_ge.c | 2069 +++++++++++++++++++++
+ drivers/net/titan_ge.h | 415 ++++
+ drivers/net/titan_mdio.c | 217 ++
+ drivers/net/titan_mdio.h | 56
+ drivers/scsi/NCR53C9x.h | 7
+ include/asm-mips/asmmacro.h | 10
+ include/asm-mips/atomic.h | 4
+ include/asm-mips/byteorder.h | 5
+ include/asm-mips/cacheflush.h | 20
+ include/asm-mips/cevt-r4k.h | 46
+ include/asm-mips/elf.h | 2
+ include/asm-mips/gdb-stub.h | 149 -
+ include/asm-mips/irqflags.h | 26
+ include/asm-mips/lasat/serial.h | 4
+ include/asm-mips/mach-au1x00/au1000.h | 1
+ include/asm-mips/mach-ip27/cpu-feature-overrides.h | 4
+ include/asm-mips/mach-ip27/dma-coherence.h | 2
+ include/asm-mips/mach-jmr3927/ioremap.h | 2
+ include/asm-mips/mach-lasat/irq.h | 2
+ include/asm-mips/mach-pb1x00/pb1200.h | 2
+ include/asm-mips/mach-qemu/cpu-feature-overrides.h | 2
+ include/asm-mips/mipsregs.h | 6
+ include/asm-mips/pgtable-32.h | 2
+ include/asm-mips/pgtable.h | 3
+ include/asm-mips/rtlx.h | 6
+ include/asm-mips/smtc.h | 8
+ include/asm-mips/sn/mapped_kernel.h | 8
+ include/asm-mips/stackframe.h | 72
+ include/asm-mips/time.h | 7
+ 120 files changed, 4344 insertions(+), 1079 deletions(-)
+diff -Nurd linux-2.6.24/arch/mips/au1000/common/clocks.c mer-smartq-kernel/arch/mips/au1000/common/clocks.c
+--- linux-2.6.24/arch/mips/au1000/common/clocks.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/au1000/common/clocks.c 2009-11-17 12:13:28.000000000 +0100
+@@ -46,6 +46,7 @@
+ {
+ return au1x00_clock;
+ }
++EXPORT_SYMBOL(get_au1x00_speed);
+
+
+
+diff -Nurd linux-2.6.24/arch/mips/au1000/common/cputable.c mer-smartq-kernel/arch/mips/au1000/common/cputable.c
+--- linux-2.6.24/arch/mips/au1000/common/cputable.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/au1000/common/cputable.c 2009-11-17 12:13:28.000000000 +0100
+@@ -22,24 +22,24 @@
+ /* With some thought, we can probably use the mask to reduce the
+ * size of the table.
+ */
+-struct cpu_spec cpu_specs[] = {
+- { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0 },
+- { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0 },
+- { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0 },
+- { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1 },
+- { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1 },
+- { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1 },
+- { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1 },
+- { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1 },
+- { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1 },
+- { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1 },
+- { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1 },
+- { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
+- { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
+- { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
+- { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
+- { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0 },
+- { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
++struct cpu_spec cpu_specs[] = {
++ { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
++ { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
++ { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
++ { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
++ { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
++ { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
++ { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
++ { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
++ { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
++ { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
++ { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
++ { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
++ { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
++ { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
++ { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
++ { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
++ { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
+ };
+
+ void
+diff -Nurd linux-2.6.24/arch/mips/au1000/common/dbdma.c mer-smartq-kernel/arch/mips/au1000/common/dbdma.c
+--- linux-2.6.24/arch/mips/au1000/common/dbdma.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/au1000/common/dbdma.c 2009-11-17 12:13:28.000000000 +0100
+@@ -161,22 +161,22 @@
+ { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+ /* Provide 16 user definable device types */
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
+- { 0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
++ { ~0, 0, 0, 0, 0, 0, 0 },
+ };
+
+ #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
+@@ -209,7 +209,7 @@
+ dbdev_tab_t *p=NULL;
+ static u16 new_id=0x1000;
+
+- p = find_dbdev_id(0);
++ p = find_dbdev_id(~0);
+ if ( NULL != p )
+ {
+ memcpy(p, dev, sizeof(dbdev_tab_t));
+diff -Nurd linux-2.6.24/arch/mips/au1000/common/gpio.c mer-smartq-kernel/arch/mips/au1000/common/gpio.c
+--- linux-2.6.24/arch/mips/au1000/common/gpio.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/au1000/common/gpio.c 2009-11-17 12:13:28.000000000 +0100
+@@ -54,7 +54,7 @@
+ {
+ gpio -= AU1XXX_GPIO_BASE;
+
+- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | (value << gpio);
++ gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
+ }
+
+ static int au1xxx_gpio2_direction_input(unsigned gpio)
+@@ -67,7 +67,8 @@
+ static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
+ {
+ gpio -= AU1XXX_GPIO_BASE;
+- gpio2->dir = (0x01 << gpio) | (value << gpio);
++ gpio2->dir |= 0x01 << gpio;
++ gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
+ return 0;
+ }
+
+@@ -96,6 +97,7 @@
+ static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
+ {
+ gpio1->trioutclr = (0x01 & gpio);
++ au1xxx_gpio1_write(gpio, value);
+ return 0;
+ }
+
+diff -Nurd linux-2.6.24/arch/mips/au1000/common/platform.c mer-smartq-kernel/arch/mips/au1000/common/platform.c
+--- linux-2.6.24/arch/mips/au1000/common/platform.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/au1000/common/platform.c 2009-11-17 12:13:28.000000000 +0100
+@@ -118,12 +118,12 @@
+ static struct resource au1xxx_mmc_resources[] = {
+ [0] = {
+ .start = SD0_PHYS_ADDR,
+- .end = SD0_PHYS_ADDR + 0x40,
++ .end = SD0_PHYS_ADDR + 0x7ffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = SD1_PHYS_ADDR,
+- .end = SD1_PHYS_ADDR + 0x40,
++ .end = SD1_PHYS_ADDR + 0x7ffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+@@ -245,13 +245,12 @@
+ .id = 0,
+ };
+
+-#ifdef CONFIG_MIPS_DB1200
+-
++#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
+ static struct resource smc91x_resources[] = {
+ [0] = {
+ .name = "smc91x-regs",
+ .start = AU1XXX_SMC91111_PHYS_ADDR,
+- .end = AU1XXX_SMC91111_PHYS_ADDR + 0xfffff,
++ .end = AU1XXX_SMC91111_PHYS_ADDR + 0xf,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+@@ -267,8 +266,7 @@
+ .num_resources = ARRAY_SIZE(smc91x_resources),
+ .resource = smc91x_resources,
+ };
+-
+-#endif
++#endif /* defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) */
+
+ static struct platform_device *au1xxx_platform_devices[] __initdata = {
+ &au1xxx_usb_ohci_device,
+@@ -284,7 +282,7 @@
+ &au1200_ide0_device,
+ &au1xxx_mmc_device,
+ #endif
+-#ifdef CONFIG_MIPS_DB1200
++#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
+ &smc91x_device,
+ #endif
+ };
+diff -Nurd linux-2.6.24/arch/mips/au1000/common/setup.c mer-smartq-kernel/arch/mips/au1000/common/setup.c
+--- linux-2.6.24/arch/mips/au1000/common/setup.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/au1000/common/setup.c 2009-11-17 12:13:28.000000000 +0100
+@@ -57,7 +57,7 @@
+ {
+ struct cpu_spec *sp;
+ char *argptr;
+- unsigned long prid, cpupll, bclk = 1;
++ unsigned long prid, cpufreq, bclk = 1;
+
+ set_cpuspec();
+ sp = cur_cpu_spec[0];
+@@ -65,8 +65,15 @@
+ board_setup(); /* board specific setup */
+
+ prid = read_c0_prid();
+- cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
+- printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
++ if (sp->cpu_pll_wo)
++#ifdef CONFIG_SOC_AU1000_FREQUENCY
++ cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
++#else
++ cpufreq = 396;
++#endif
++ else
++ cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
++ printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
+
+ bclk = sp->cpu_bclk;
+ if (bclk)
+diff -Nurd linux-2.6.24/arch/mips/au1000/common/time.c mer-smartq-kernel/arch/mips/au1000/common/time.c
+--- linux-2.6.24/arch/mips/au1000/common/time.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/au1000/common/time.c 2009-11-17 12:13:28.000000000 +0100
+@@ -209,18 +209,22 @@
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+ au_writel(0, SYS_TOYWRITE);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
++ } else
++ no_au1xxx_32khz = 1;
+
+- cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
+- AU1000_SRC_CLK;
+- }
+- else {
+- /* The 32KHz oscillator isn't running, so assume there
+- * isn't one and grab the processor speed from the PLL.
+- * NOTE: some old silicon doesn't allow reading the PLL.
+- */
++ /*
++ * On early Au1000, sys_cpupll was write-only. Since these
++ * silicon versions of Au1000 are not sold by AMD, we don't bend
++ * over backwards trying to determine the frequency.
++ */
++ if (cur_cpu_spec[0]->cpu_pll_wo)
++#ifdef CONFIG_SOC_AU1000_FREQUENCY
++ cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
++#else
++ cpu_speed = 396000000;
++#endif
++ else
+ cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
+- no_au1xxx_32khz = 1;
+- }
+ mips_hpt_frequency = cpu_speed;
+ // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
+ set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
+diff -Nurd linux-2.6.24/arch/mips/fw/arc/identify.c mer-smartq-kernel/arch/mips/fw/arc/identify.c
+--- linux-2.6.24/arch/mips/fw/arc/identify.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/fw/arc/identify.c 2009-11-17 12:13:29.000000000 +0100
+@@ -67,6 +67,11 @@
+ .liname = "SNI RM200_PCI",
+ .type = MACH_SNI_RM200_PCI,
+ .flags = PROM_FLAG_DONT_FREE_TEMP,
++ }, {
++ .arcname = "RM200PCI-R5K",
++ .liname = "SNI RM200_PCI-R5K",
++ .type = MACH_SNI_RM200_PCI,
++ .flags = PROM_FLAG_DONT_FREE_TEMP,
+ }
+ };
+
+diff -Nurd linux-2.6.24/arch/mips/Kconfig mer-smartq-kernel/arch/mips/Kconfig
+--- linux-2.6.24/arch/mips/Kconfig 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/Kconfig 2009-11-17 12:13:28.000000000 +0100
+@@ -1453,7 +1453,6 @@
+ depends on CPU_MIPS32_R2
+ #depends on CPU_MIPS64_R2 # once there is hardware ...
+ depends on SYS_SUPPORTS_MULTITHREADING
+- select GENERIC_CLOCKEVENTS_BROADCAST
+ select CPU_MIPSR2_IRQ_VI
+ select CPU_MIPSR2_IRQ_EI
+ select MIPS_MT
+@@ -1487,32 +1486,17 @@
+ Includes a loader for loading an elf relocatable object
+ onto another VPE and running it.
+
+-config MIPS_MT_SMTC_INSTANT_REPLAY
+- bool "Low-latency Dispatch of Deferred SMTC IPIs"
+- depends on MIPS_MT_SMTC && !PREEMPT
+- default y
+- help
+- SMTC pseudo-interrupts between TCs are deferred and queued
+- if the target TC is interrupt-inhibited (IXMT). In the first
+- SMTC prototypes, these queued IPIs were serviced on return
+- to user mode, or on entry into the kernel idle loop. The
+- INSTANT_REPLAY option dispatches them as part of local_irq_restore()
+- processing, which adds runtime overhead (hence the option to turn
+- it off), but ensures that IPIs are handled promptly even under
+- heavy I/O interrupt load.
+-
+ config MIPS_MT_SMTC_IM_BACKSTOP
+ bool "Use per-TC register bits as backstop for inhibited IM bits"
+ depends on MIPS_MT_SMTC
+- default y
++ default n
+ help
+ To support multiple TC microthreads acting as "CPUs" within
+ a VPE, VPE-wide interrupt mask bits must be specially manipulated
+ during interrupt handling. To support legacy drivers and interrupt
+ controller management code, SMTC has a "backstop" to track and
+ if necessary restore the interrupt mask. This has some performance
+- impact on interrupt service overhead. Disable it only if you know
+- what you are doing.
++ impact on interrupt service overhead.
+
+ config MIPS_MT_SMTC_IRQAFF
+ bool "Support IRQ affinity API"
+@@ -1522,10 +1506,8 @@
+ Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
+ for SMTC Linux kernel. Requires platform support, of which
+ an example can be found in the MIPS kernel i8259 and Malta
+- platform code. It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY
+- be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to
+- interrupt dispatch, and should be used only if you know what
+- you are doing.
++ platform code. Adds some overhead to interrupt dispatch, and
++ should be used only if you know what you are doing.
+
+ config MIPS_VPE_LOADER_TOM
+ bool "Load VPE program into memory hidden from linux"
+@@ -1781,7 +1763,7 @@
+ Allows the configuration of the timer frequency.
+
+ config HZ_48
+- bool "48 HZ" if SYS_SUPPORTS_48HZ
++ bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
+
+ config HZ_100
+ bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
+diff -Nurd linux-2.6.24/arch/mips/kernel/asm-offsets.c mer-smartq-kernel/arch/mips/kernel/asm-offsets.c
+--- linux-2.6.24/arch/mips/kernel/asm-offsets.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/asm-offsets.c 2009-11-17 12:13:29.000000000 +0100
+@@ -13,7 +13,7 @@
+ #include <linux/sched.h>
+ #include <linux/mm.h>
+ #include <linux/interrupt.h>
+-
++#include <asm/gdb-stub.h>
+ #include <asm/ptrace.h>
+ #include <asm/processor.h>
+
+@@ -337,3 +337,109 @@
+ size("#define IC_IRQ_CPUSTAT_T ", irq_cpustat_t);
+ linefeed;
+ }
++
++void output_gdbreg_defines(void)
++{
++ text("/* MIPS struct gdb_regs offsets. */");
++ offset("#define GDB_FR_REG0 ", struct gdb_regs, reg0);
++ offset("#define GDB_FR_REG1 ", struct gdb_regs, reg1);
++ offset("#define GDB_FR_REG2 ", struct gdb_regs, reg2);
++ offset("#define GDB_FR_REG3 ", struct gdb_regs, reg3);
++ offset("#define GDB_FR_REG4 ", struct gdb_regs, reg4);
++ offset("#define GDB_FR_REG5 ", struct gdb_regs, reg5);
++ offset("#define GDB_FR_REG6 ", struct gdb_regs, reg6);
++ offset("#define GDB_FR_REG7 ", struct gdb_regs, reg7);
++ offset("#define GDB_FR_REG8 ", struct gdb_regs, reg8);
++ offset("#define GDB_FR_REG9 ", struct gdb_regs, reg9);
++ offset("#define GDB_FR_REG10 ", struct gdb_regs, reg10);
++ offset("#define GDB_FR_REG11 ", struct gdb_regs, reg11);
++ offset("#define GDB_FR_REG12 ", struct gdb_regs, reg12);
++ offset("#define GDB_FR_REG13 ", struct gdb_regs, reg13);
++ offset("#define GDB_FR_REG14 ", struct gdb_regs, reg14);
++ offset("#define GDB_FR_REG15 ", struct gdb_regs, reg15);
++ offset("#define GDB_FR_REG16 ", struct gdb_regs, reg16);
++ offset("#define GDB_FR_REG17 ", struct gdb_regs, reg17);
++ offset("#define GDB_FR_REG18 ", struct gdb_regs, reg18);
++ offset("#define GDB_FR_REG19 ", struct gdb_regs, reg19);
++ offset("#define GDB_FR_REG20 ", struct gdb_regs, reg20);
++ offset("#define GDB_FR_REG21 ", struct gdb_regs, reg21);
++ offset("#define GDB_FR_REG22 ", struct gdb_regs, reg22);
++ offset("#define GDB_FR_REG23 ", struct gdb_regs, reg23);
++ offset("#define GDB_FR_REG24 ", struct gdb_regs, reg24);
++ offset("#define GDB_FR_REG25 ", struct gdb_regs, reg25);
++ offset("#define GDB_FR_REG26 ", struct gdb_regs, reg26);
++ offset("#define GDB_FR_REG27 ", struct gdb_regs, reg27);
++ offset("#define GDB_FR_REG28 ", struct gdb_regs, reg28);
++ offset("#define GDB_FR_REG29 ", struct gdb_regs, reg29);
++ offset("#define GDB_FR_REG30 ", struct gdb_regs, reg30);
++ offset("#define GDB_FR_REG31 ", struct gdb_regs, reg31);
++ linefeed;
++
++ offset("#define GDB_FR_STATUS ", struct gdb_regs, cp0_status);
++ offset("#define GDB_FR_HI ", struct gdb_regs, hi);
++ offset("#define GDB_FR_LO ", struct gdb_regs, lo);
++#ifdef CONFIG_CPU_HAS_SMARTMIPS
++ offset("#define GDB_FR_ACX ", struct gdb_regs, acx);
++#endif
++ offset("#define GDB_FR_BADVADDR ", struct gdb_regs, cp0_badvaddr);
++ offset("#define GDB_FR_CAUSE ", struct gdb_regs, cp0_cause);
++ offset("#define GDB_FR_EPC ", struct gdb_regs, cp0_epc);
++ linefeed;
++
++ offset("#define GDB_FR_FPR0 ", struct gdb_regs, fpr0);
++ offset("#define GDB_FR_FPR1 ", struct gdb_regs, fpr1);
++ offset("#define GDB_FR_FPR2 ", struct gdb_regs, fpr2);
++ offset("#define GDB_FR_FPR3 ", struct gdb_regs, fpr3);
++ offset("#define GDB_FR_FPR4 ", struct gdb_regs, fpr4);
++ offset("#define GDB_FR_FPR5 ", struct gdb_regs, fpr5);
++ offset("#define GDB_FR_FPR6 ", struct gdb_regs, fpr6);
++ offset("#define GDB_FR_FPR7 ", struct gdb_regs, fpr7);
++ offset("#define GDB_FR_FPR8 ", struct gdb_regs, fpr8);
++ offset("#define GDB_FR_FPR9 ", struct gdb_regs, fpr9);
++ offset("#define GDB_FR_FPR10 ", struct gdb_regs, fpr10);
++ offset("#define GDB_FR_FPR11 ", struct gdb_regs, fpr11);
++ offset("#define GDB_FR_FPR12 ", struct gdb_regs, fpr12);
++ offset("#define GDB_FR_FPR13 ", struct gdb_regs, fpr13);
++ offset("#define GDB_FR_FPR14 ", struct gdb_regs, fpr14);
++ offset("#define GDB_FR_FPR15 ", struct gdb_regs, fpr15);
++ offset("#define GDB_FR_FPR16 ", struct gdb_regs, fpr16);
++ offset("#define GDB_FR_FPR17 ", struct gdb_regs, fpr17);
++ offset("#define GDB_FR_FPR18 ", struct gdb_regs, fpr18);
++ offset("#define GDB_FR_FPR19 ", struct gdb_regs, fpr19);
++ offset("#define GDB_FR_FPR20 ", struct gdb_regs, fpr20);
++ offset("#define GDB_FR_FPR21 ", struct gdb_regs, fpr21);
++ offset("#define GDB_FR_FPR22 ", struct gdb_regs, fpr22);
++ offset("#define GDB_FR_FPR23 ", struct gdb_regs, fpr23);
++ offset("#define GDB_FR_FPR24 ", struct gdb_regs, fpr24);
++ offset("#define GDB_FR_FPR25 ", struct gdb_regs, fpr25);
++ offset("#define GDB_FR_FPR26 ", struct gdb_regs, fpr26);
++ offset("#define GDB_FR_FPR27 ", struct gdb_regs, fpr27);
++ offset("#define GDB_FR_FPR28 ", struct gdb_regs, fpr28);
++ offset("#define GDB_FR_FPR29 ", struct gdb_regs, fpr29);
++ offset("#define GDB_FR_FPR30 ", struct gdb_regs, fpr30);
++ offset("#define GDB_FR_FPR31 ", struct gdb_regs, fpr31);
++ linefeed;
++
++ offset("#define GDB_FR_FSR ", struct gdb_regs, cp1_fsr);
++ offset("#define GDB_FR_FIR ", struct gdb_regs, cp1_fir);
++ offset("#define GDB_FR_FRP ", struct gdb_regs, frame_ptr);
++ offset("#define GDB_FR_DUMMY ", struct gdb_regs, dummy);
++
++ offset("#define GDB_FR_CP0_INDEX ", struct gdb_regs, cp0_index);
++ offset("#define GDB_FR_CP0_RANDOM ", struct gdb_regs, cp0_random);
++ offset("#define GDB_FR_CP0_ENTRYLO0 ", struct gdb_regs, cp0_entrylo0);
++ offset("#define GDB_FR_CP0_ENTRYLO1 ", struct gdb_regs, cp0_entrylo1);
++ offset("#define GDB_FR_CP0_CONTEXT ", struct gdb_regs, cp0_context);
++ offset("#define GDB_FR_CP0_PAGEMASK ", struct gdb_regs, cp0_pagemask);
++ offset("#define GDB_FR_CP0_WIRED ", struct gdb_regs, cp0_wired);
++ offset("#define GDB_FR_CP0_REG7 ", struct gdb_regs, cp0_reg7);
++ offset("#define GDB_FR_CP0_REG8 ", struct gdb_regs, cp0_reg8);
++ offset("#define GDB_FR_CP0_REG9 ", struct gdb_regs, cp0_reg9);
++ offset("#define GDB_FR_CP0_ENTRYHI ", struct gdb_regs, cp0_entryhi);
++ offset("#define GDB_FR_CP0_REG11 ", struct gdb_regs, cp0_reg11);
++ offset("#define GDB_FR_CP0_REG12 ", struct gdb_regs, cp0_reg12);
++ offset("#define GDB_FR_CP0_REG13 ", struct gdb_regs, cp0_reg13);
++ offset("#define GDB_FR_CP0_REG14 ", struct gdb_regs, cp0_reg14);
++ offset("#define GDB_FR_CP0_PRID ", struct gdb_regs, cp0_prid);
++ size("#define GDB_FR_SIZE ", struct gdb_regs);
++}
+diff -Nurd linux-2.6.24/arch/mips/kernel/cevt-r4k.c mer-smartq-kernel/arch/mips/kernel/cevt-r4k.c
+--- linux-2.6.24/arch/mips/kernel/cevt-r4k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/cevt-r4k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -12,6 +12,14 @@
+
+ #include <asm/smtc_ipi.h>
+ #include <asm/time.h>
++#include <asm/cevt-r4k.h>
++
++/*
++ * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
++ * of these routines with SMTC-specific variants.
++ */
++
++#ifndef CONFIG_MIPS_MT_SMTC
+
+ static int mips_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+@@ -19,60 +27,27 @@
+ unsigned int cnt;
+ int res;
+
+-#ifdef CONFIG_MIPS_MT_SMTC
+- {
+- unsigned long flags, vpflags;
+- local_irq_save(flags);
+- vpflags = dvpe();
+-#endif
+ cnt = read_c0_count();
+ cnt += delta;
+ write_c0_compare(cnt);
+ res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
+-#ifdef CONFIG_MIPS_MT_SMTC
+- evpe(vpflags);
+- local_irq_restore(flags);
+- }
+-#endif
+ return res;
+ }
+
+-static void mips_set_mode(enum clock_event_mode mode,
+- struct clock_event_device *evt)
++#endif /* CONFIG_MIPS_MT_SMTC */
++
++void mips_set_clock_mode(enum clock_event_mode mode,
++ struct clock_event_device *evt)
+ {
+ /* Nothing to do ... */
+ }
+
+-static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+-static int cp0_timer_irq_installed;
+-
+-/*
+- * Timer ack for an R4k-compatible timer of a known frequency.
+- */
+-static void c0_timer_ack(void)
+-{
+- write_c0_compare(read_c0_compare());
+-}
++DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
++int cp0_timer_irq_installed;
+
+-/*
+- * Possibly handle a performance counter interrupt.
+- * Return true if the timer interrupt should not be checked
+- */
+-static inline int handle_perf_irq(int r2)
+-{
+- /*
+- * The performance counter overflow interrupt may be shared with the
+- * timer interrupt (cp0_perfcount_irq < 0). If it is and a
+- * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
+- * and we can't reliably determine if a counter interrupt has also
+- * happened (!r2) then don't check for a timer interrupt.
+- */
+- return (cp0_perfcount_irq < 0) &&
+- perf_irq() == IRQ_HANDLED &&
+- !r2;
+-}
++#ifndef CONFIG_MIPS_MT_SMTC
+
+-static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
++irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
+ {
+ const int r2 = cpu_has_mips_r2;
+ struct clock_event_device *cd;
+@@ -93,12 +68,8 @@
+ * interrupt. Being the paranoiacs we are we check anyway.
+ */
+ if (!r2 || (read_c0_cause() & (1 << 30))) {
+- c0_timer_ack();
+-#ifdef CONFIG_MIPS_MT_SMTC
+- if (cpu_data[cpu].vpe_id)
+- goto out;
+- cpu = 0;
+-#endif
++ /* Clear Count/Compare Interrupt */
++ write_c0_compare(read_c0_compare());
+ cd = &per_cpu(mips_clockevent_device, cpu);
+ cd->event_handler(cd);
+ }
+@@ -107,65 +78,16 @@
+ return IRQ_HANDLED;
+ }
+
+-static struct irqaction c0_compare_irqaction = {
++#endif /* Not CONFIG_MIPS_MT_SMTC */
++
++struct irqaction c0_compare_irqaction = {
+ .handler = c0_compare_interrupt,
+-#ifdef CONFIG_MIPS_MT_SMTC
+- .flags = IRQF_DISABLED,
+-#else
+ .flags = IRQF_DISABLED | IRQF_PERCPU,
+-#endif
+ .name = "timer",
+ };
+
+-#ifdef CONFIG_MIPS_MT_SMTC
+-DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
+
+-static void smtc_set_mode(enum clock_event_mode mode,
+- struct clock_event_device *evt)
+-{
+-}
+-
+-static void mips_broadcast(cpumask_t mask)
+-{
+- unsigned int cpu;
+-
+- for_each_cpu_mask(cpu, mask)
+- smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
+-}
+-
+-static void setup_smtc_dummy_clockevent_device(void)
+-{
+- //uint64_t mips_freq = mips_hpt_^frequency;
+- unsigned int cpu = smp_processor_id();
+- struct clock_event_device *cd;
+-
+- cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
+-
+- cd->name = "SMTC";
+- cd->features = CLOCK_EVT_FEAT_DUMMY;
+-
+- /* Calculate the min / max delta */
+- cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
+- cd->shift = 0; //32;
+- cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
+- cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
+-
+- cd->rating = 200;
+- cd->irq = 17; //-1;
+-// if (cpu)
+-// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
+-// else
+- cd->cpumask = cpumask_of_cpu(cpu);
+-
+- cd->set_mode = smtc_set_mode;
+-
+- cd->broadcast = mips_broadcast;
+-
+- clockevents_register_device(cd);
+-}
+-#endif
+-
+-static void mips_event_handler(struct clock_event_device *dev)
++void mips_event_handler(struct clock_event_device *dev)
+ {
+ }
+
+@@ -177,7 +99,23 @@
+ return (read_c0_cause() >> cp0_compare_irq) & 0x100;
+ }
+
+-static int c0_compare_int_usable(void)
++/*
++ * Compare interrupt can be routed and latched outside the core,
++ * so a single execution hazard barrier may not be enough to give
++ * it time to clear as seen in the Cause register. 4 time the
++ * pipeline depth seems reasonably conservative, and empirically
++ * works better in configurations with high CPU/bus clock ratios.
++ */
++
++#define compare_change_hazard() \
++ do { \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ } while (0)
++
++int c0_compare_int_usable(void)
+ {
+ unsigned int delta;
+ unsigned int cnt;
+@@ -187,7 +125,7 @@
+ */
+ if (c0_compare_int_pending()) {
+ write_c0_compare(read_c0_count());
+- irq_disable_hazard();
++ compare_change_hazard();
+ if (c0_compare_int_pending())
+ return 0;
+ }
+@@ -196,7 +134,7 @@
+ cnt = read_c0_count();
+ cnt += delta;
+ write_c0_compare(cnt);
+- irq_disable_hazard();
++ compare_change_hazard();
+ if ((int)(read_c0_count() - cnt) < 0)
+ break;
+ /* increase delta if the timer was already expired */
+@@ -205,11 +143,12 @@
+ while ((int)(read_c0_count() - cnt) <= 0)
+ ; /* Wait for expiry */
+
++ compare_change_hazard();
+ if (!c0_compare_int_pending())
+ return 0;
+
+ write_c0_compare(read_c0_count());
+- irq_disable_hazard();
++ compare_change_hazard();
+ if (c0_compare_int_pending())
+ return 0;
+
+@@ -219,6 +158,8 @@
+ return 1;
+ }
+
++#ifndef CONFIG_MIPS_MT_SMTC
++
+ int __cpuinit mips_clockevent_init(void)
+ {
+ uint64_t mips_freq = mips_hpt_frequency;
+@@ -229,17 +170,6 @@
+ if (!cpu_has_counter || !mips_hpt_frequency)
+ return -ENXIO;
+
+-#ifdef CONFIG_MIPS_MT_SMTC
+- setup_smtc_dummy_clockevent_device();
+-
+- /*
+- * On SMTC we only register VPE0's compare interrupt as clockevent
+- * device.
+- */
+- if (cpu)
+- return 0;
+-#endif
+-
+ if (!c0_compare_int_usable())
+ return -ENXIO;
+
+@@ -265,13 +195,9 @@
+
+ cd->rating = 300;
+ cd->irq = irq;
+-#ifdef CONFIG_MIPS_MT_SMTC
+- cd->cpumask = CPU_MASK_ALL;
+-#else
+ cd->cpumask = cpumask_of_cpu(cpu);
+-#endif
+ cd->set_next_event = mips_next_event;
+- cd->set_mode = mips_set_mode;
++ cd->set_mode = mips_set_clock_mode;
+ cd->event_handler = mips_event_handler;
+
+ clockevents_register_device(cd);
+@@ -281,12 +207,9 @@
+
+ cp0_timer_irq_installed = 1;
+
+-#ifdef CONFIG_MIPS_MT_SMTC
+-#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
+- setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);
+-#else
+ setup_irq(irq, &c0_compare_irqaction);
+-#endif
+
+ return 0;
+ }
++
++#endif /* Not CONFIG_MIPS_MT_SMTC */
+diff -Nurd linux-2.6.24/arch/mips/kernel/cevt-smtc.c mer-smartq-kernel/arch/mips/kernel/cevt-smtc.c
+--- linux-2.6.24/arch/mips/kernel/cevt-smtc.c 1970-01-01 01:00:00.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/cevt-smtc.c 2009-11-17 12:13:29.000000000 +0100
+@@ -0,0 +1,321 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2007 MIPS Technologies, Inc.
++ * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
++ * Copyright (C) 2008 Kevin D. Kissell, Paralogos sarl
++ */
++#include <linux/clockchips.h>
++#include <linux/interrupt.h>
++#include <linux/percpu.h>
++
++#include <asm/smtc_ipi.h>
++#include <asm/time.h>
++#include <asm/cevt-r4k.h>
++
++/*
++ * Variant clock event timer support for SMTC on MIPS 34K, 1004K
++ * or other MIPS MT cores.
++ *
++ * Notes on SMTC Support:
++ *
++ * SMTC has multiple microthread TCs pretending to be Linux CPUs.
++ * But there's only one Count/Compare pair per VPE, and Compare
++ * interrupts are taken opportunisitically by available TCs
++ * bound to the VPE with the Count register. The new timer
++ * framework provides for global broadcasts, but we really
++ * want VPE-level multicasts for best behavior. So instead
++ * of invoking the high-level clock-event broadcast code,
++ * this version of SMTC support uses the historical SMTC
++ * multicast mechanisms "under the hood", appearing to the
++ * generic clock layer as if the interrupts are per-CPU.
++ *
++ * The approach taken here is to maintain a set of NR_CPUS
++ * virtual timers, and track which "CPU" needs to be alerted
++ * at each event.
++ *
++ * It's unlikely that we'll see a MIPS MT core with more than
++ * 2 VPEs, but we *know* that we won't need to handle more
++ * VPEs than we have "CPUs". So NCPUs arrays of NCPUs elements
++ * is always going to be overkill, but always going to be enough.
++ */
++
++unsigned long smtc_nexttime[NR_CPUS][NR_CPUS];
++static int smtc_nextinvpe[NR_CPUS];
++
++/*
++ * Timestamps stored are absolute values to be programmed
++ * into Count register. Valid timestamps will never be zero.
++ * If a Zero Count value is actually calculated, it is converted
++ * to be a 1, which will introduce 1 or two CPU cycles of error
++ * roughly once every four billion events, which at 1000 HZ means
++ * about once every 50 days. If that's actually a problem, one
++ * could alternate squashing 0 to 1 and to -1.
++ */
++
++#define MAKEVALID(x) (((x) == 0L) ? 1L : (x))
++#define ISVALID(x) ((x) != 0L)
++
++/*
++ * Time comparison is subtle, as it's really truncated
++ * modular arithmetic.
++ */
++
++#define IS_SOONER(a, b, reference) \
++ (((a) - (unsigned long)(reference)) < ((b) - (unsigned long)(reference)))
++
++/*
++ * CATCHUP_INCREMENT, used when the function falls behind the counter.
++ * Could be an increasing function instead of a constant;
++ */
++
++#define CATCHUP_INCREMENT 64
++
++static int mips_next_event(unsigned long delta,
++ struct clock_event_device *evt)
++{
++ unsigned long flags;
++ unsigned int mtflags;
++ unsigned long timestamp, reference, previous;
++ unsigned long nextcomp = 0L;
++ int vpe = current_cpu_data.vpe_id;
++ int cpu = smp_processor_id();
++ local_irq_save(flags);
++ mtflags = dmt();
++
++ /*
++ * Maintain the per-TC virtual timer
++ * and program the per-VPE shared Count register
++ * as appropriate here...
++ */
++ reference = (unsigned long)read_c0_count();
++ timestamp = MAKEVALID(reference + delta);
++ /*
++ * To really model the clock, we have to catch the case
++ * where the current next-in-VPE timestamp is the old
++ * timestamp for the calling CPE, but the new value is
++ * in fact later. In that case, we have to do a full
++ * scan and discover the new next-in-VPE CPU id and
++ * timestamp.
++ */
++ previous = smtc_nexttime[vpe][cpu];
++ if (cpu == smtc_nextinvpe[vpe] && ISVALID(previous)
++ && IS_SOONER(previous, timestamp, reference)) {
++ int i;
++ int soonest = cpu;
++
++ /*
++ * Update timestamp array here, so that new
++ * value gets considered along with those of
++ * other virtual CPUs on the VPE.
++ */
++ smtc_nexttime[vpe][cpu] = timestamp;
++ for_each_online_cpu(i) {
++ if (ISVALID(smtc_nexttime[vpe][i])
++ && IS_SOONER(smtc_nexttime[vpe][i],
++ smtc_nexttime[vpe][soonest], reference)) {
++ soonest = i;
++ }
++ }
++ smtc_nextinvpe[vpe] = soonest;
++ nextcomp = smtc_nexttime[vpe][soonest];
++ /*
++ * Otherwise, we don't have to process the whole array rank,
++ * we just have to see if the event horizon has gotten closer.
++ */
++ } else {
++ if (!ISVALID(smtc_nexttime[vpe][smtc_nextinvpe[vpe]]) ||
++ IS_SOONER(timestamp,
++ smtc_nexttime[vpe][smtc_nextinvpe[vpe]], reference)) {
++ smtc_nextinvpe[vpe] = cpu;
++ nextcomp = timestamp;
++ }
++ /*
++ * Since next-in-VPE may me the same as the executing
++ * virtual CPU, we update the array *after* checking
++ * its value.
++ */
++ smtc_nexttime[vpe][cpu] = timestamp;
++ }
++
++ /*
++ * It may be that, in fact, we don't need to update Compare,
++ * but if we do, we want to make sure we didn't fall into
++ * a crack just behind Count.
++ */
++ if (ISVALID(nextcomp)) {
++ write_c0_compare(nextcomp);
++ ehb();
++ /*
++ * We never return an error, we just make sure
++ * that we trigger the handlers as quickly as
++ * we can if we fell behind.
++ */
++ while ((nextcomp - (unsigned long)read_c0_count())
++ > (unsigned long)LONG_MAX) {
++ nextcomp += CATCHUP_INCREMENT;
++ write_c0_compare(nextcomp);
++ ehb();
++ }
++ }
++ emt(mtflags);
++ local_irq_restore(flags);
++ return 0;
++}
++
++
++void smtc_distribute_timer(int vpe)
++{
++ unsigned long flags;
++ unsigned int mtflags;
++ int cpu;
++ struct clock_event_device *cd;
++ unsigned long nextstamp = 0L;
++ unsigned long reference;
++
++
++repeat:
++ for_each_online_cpu(cpu) {
++ /*
++ * Find virtual CPUs within the current VPE who have
++ * unserviced timer requests whose time is now past.
++ */
++ local_irq_save(flags);
++ mtflags = dmt();
++ if (cpu_data[cpu].vpe_id == vpe &&
++ ISVALID(smtc_nexttime[vpe][cpu])) {
++ reference = (unsigned long)read_c0_count();
++ if ((smtc_nexttime[vpe][cpu] - reference)
++ > (unsigned long)LONG_MAX) {
++ smtc_nexttime[vpe][cpu] = 0L;
++ emt(mtflags);
++ local_irq_restore(flags);
++ /*
++ * We don't send IPIs to ourself.
++ */
++ if (cpu != smp_processor_id()) {
++ smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
++ } else {
++ cd = &per_cpu(mips_clockevent_device, cpu);
++ cd->event_handler(cd);
++ }
++ } else {
++ /* Local to VPE but Valid Time not yet reached. */
++ if (!ISVALID(nextstamp) ||
++ IS_SOONER(smtc_nexttime[vpe][cpu], nextstamp,
++ reference)) {
++ smtc_nextinvpe[vpe] = cpu;
++ nextstamp = smtc_nexttime[vpe][cpu];
++ }
++ emt(mtflags);
++ local_irq_restore(flags);
++ }
++ } else {
++ emt(mtflags);
++ local_irq_restore(flags);
++
++ }
++ }
++ /* Reprogram for interrupt at next soonest timestamp for VPE */
++ if (ISVALID(nextstamp)) {
++ write_c0_compare(nextstamp);
++ ehb();
++ if ((nextstamp - (unsigned long)read_c0_count())
++ > (unsigned long)LONG_MAX)
++ goto repeat;
++ }
++}
++
++
++irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
++{
++ int cpu = smp_processor_id();
++
++ /* If we're running SMTC, we've got MIPS MT and therefore MIPS32R2 */
++ handle_perf_irq(1);
++
++ if (read_c0_cause() & (1 << 30)) {
++ /* Clear Count/Compare Interrupt */
++ write_c0_compare(read_c0_compare());
++ smtc_distribute_timer(cpu_data[cpu].vpe_id);
++ }
++ return IRQ_HANDLED;
++}
++
++
++int __cpuinit mips_clockevent_init(void)
++{
++ uint64_t mips_freq = mips_hpt_frequency;
++ unsigned int cpu = smp_processor_id();
++ struct clock_event_device *cd;
++ unsigned int irq;
++ int i;
++ int j;
++
++ if (!cpu_has_counter || !mips_hpt_frequency)
++ return -ENXIO;
++ if (cpu == 0) {
++ for (i = 0; i < num_possible_cpus(); i++) {
++ smtc_nextinvpe[i] = 0;
++ for (j = 0; j < num_possible_cpus(); j++)
++ smtc_nexttime[i][j] = 0L;
++ }
++ /*
++ * SMTC also can't have the usablility test
++ * run by secondary TCs once Compare is in use.
++ */
++ if (!c0_compare_int_usable())
++ return -ENXIO;
++ }
++
++ /*
++ * With vectored interrupts things are getting platform specific.
++ * get_c0_compare_int is a hook to allow a platform to return the
++ * interrupt number of it's liking.
++ */
++ irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
++ if (get_c0_compare_int)
++ irq = get_c0_compare_int();
++
++ cd = &per_cpu(mips_clockevent_device, cpu);
++
++ cd->name = "MIPS";
++ cd->features = CLOCK_EVT_FEAT_ONESHOT;
++
++ /* Calculate the min / max delta */
++ cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
++ cd->shift = 32;
++ cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
++ cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
++
++ cd->rating = 300;
++ cd->irq = irq;
++ cd->cpumask = cpumask_of_cpu(cpu);
++ cd->set_next_event = mips_next_event;
++ cd->set_mode = mips_set_clock_mode;
++ cd->event_handler = mips_event_handler;
++
++ clockevents_register_device(cd);
++
++ /*
++ * On SMTC we only want to do the data structure
++ * initialization and IRQ setup once.
++ */
++ if (cpu)
++ return 0;
++ /*
++ * And we need the hwmask associated with the c0_compare
++ * vector to be initialized.
++ */
++ irq_hwmask[irq] = (0x100 << cp0_compare_irq);
++ if (cp0_timer_irq_installed)
++ return 0;
++
++ cp0_timer_irq_installed = 1;
++
++ setup_irq(irq, &c0_compare_irqaction);
++
++ return 0;
++}
+diff -Nurd linux-2.6.24/arch/mips/kernel/cevt-txx9.c mer-smartq-kernel/arch/mips/kernel/cevt-txx9.c
+--- linux-2.6.24/arch/mips/kernel/cevt-txx9.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/cevt-txx9.c 2009-11-17 12:13:29.000000000 +0100
+@@ -161,6 +161,9 @@
+ struct txx9_tmr_reg __iomem *tmrptr;
+
+ tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
++ /* Start once to make CounterResetEnable effective */
++ __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
++ /* Stop and reset the counter */
+ __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
+ __raw_writel(0, &tmrptr->tisr);
+ __raw_writel(0xffffffff, &tmrptr->cpra);
+diff -Nurd linux-2.6.24/arch/mips/kernel/cpu-bugs64.c mer-smartq-kernel/arch/mips/kernel/cpu-bugs64.c
+--- linux-2.6.24/arch/mips/kernel/cpu-bugs64.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/cpu-bugs64.c 2009-11-17 12:13:29.000000000 +0100
+@@ -164,7 +164,7 @@
+ );
+ }
+
+-static volatile int daddi_ov __initdata = 0;
++static volatile int daddi_ov __cpuinitdata = 0;
+
+ asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
+ {
+diff -Nurd linux-2.6.24/arch/mips/kernel/cpu-probe.c mer-smartq-kernel/arch/mips/kernel/cpu-probe.c
+--- linux-2.6.24/arch/mips/kernel/cpu-probe.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/cpu-probe.c 2009-11-17 12:13:29.000000000 +0100
+@@ -45,18 +45,7 @@
+ local_irq_enable();
+ }
+
+-/*
+- * There is a race when WAIT instruction executed with interrupt
+- * enabled.
+- * But it is implementation-dependent wheter the pipelie restarts when
+- * a non-enabled interrupt is requested.
+- */
+-static void r4k_wait(void)
+-{
+- __asm__(" .set mips3 \n"
+- " wait \n"
+- " .set mips0 \n");
+-}
++extern void r4k_wait(void);
+
+ /*
+ * This variant is preferable as it allows testing need_resched and going to
+@@ -65,14 +54,18 @@
+ * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
+ * using this version a gamble.
+ */
+-static void r4k_wait_irqoff(void)
++void r4k_wait_irqoff(void)
+ {
+ local_irq_disable();
+ if (!need_resched())
+- __asm__(" .set mips3 \n"
++ __asm__(" .set push \n"
++ " .set mips3 \n"
+ " wait \n"
+- " .set mips0 \n");
++ " .set pop \n");
+ local_irq_enable();
++ __asm__(" .globl __pastwait \n"
++ "__pastwait: \n");
++ return;
+ }
+
+ /*
+@@ -128,7 +121,7 @@
+
+ __setup("nowait", wait_disable);
+
+-static inline void check_wait(void)
++void __init check_wait(void)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+
+@@ -239,7 +232,6 @@
+
+ void __init check_bugs32(void)
+ {
+- check_wait();
+ check_errata();
+ }
+
+@@ -548,7 +540,7 @@
+ }
+ }
+
+-static char unknown_isa[] __initdata = KERN_ERR \
++static char unknown_isa[] __cpuinitdata = KERN_ERR \
+ "Unsupported ISA type, c0.config0: %d.";
+
+ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
+@@ -654,7 +646,7 @@
+ return config3 & MIPS_CONF_M;
+ }
+
+-static void __init decode_configs(struct cpuinfo_mips *c)
++static void __cpuinit decode_configs(struct cpuinfo_mips *c)
+ {
+ /* MIPS32 or MIPS64 compliant CPU. */
+ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
+@@ -807,7 +799,7 @@
+ /*
+ * Name a CPU
+ */
+-static __init const char *cpu_to_name(struct cpuinfo_mips *c)
++static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
+ {
+ const char *name = NULL;
+
+@@ -887,7 +879,7 @@
+ return name;
+ }
+
+-__init void cpu_probe(void)
++__cpuinit void cpu_probe(void)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+ unsigned int cpu = smp_processor_id();
+@@ -950,7 +942,7 @@
+ c->srsets = 1;
+ }
+
+-__init void cpu_report(void)
++__cpuinit void cpu_report(void)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+
+diff -Nurd linux-2.6.24/arch/mips/kernel/csrc-r4k.c mer-smartq-kernel/arch/mips/kernel/csrc-r4k.c
+--- linux-2.6.24/arch/mips/kernel/csrc-r4k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/csrc-r4k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -22,12 +22,17 @@
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ };
+
+-void __init init_mips_clocksource(void)
++int __init init_mips_clocksource(void)
+ {
+- /* Calclate a somewhat reasonable rating value */
++ if (!cpu_has_counter || !mips_hpt_frequency)
++ return -ENXIO;
++
++ /* Calculate a somewhat reasonable rating value */
+ clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+
+ clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+
+ clocksource_register(&clocksource_mips);
++
++ return 0;
+ }
+diff -Nurd linux-2.6.24/arch/mips/kernel/entry.S mer-smartq-kernel/arch/mips/kernel/entry.S
+--- linux-2.6.24/arch/mips/kernel/entry.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/entry.S 2009-11-17 12:13:29.000000000 +0100
+@@ -79,11 +79,6 @@
+
+ FEXPORT(restore_all) # restore full frame
+ #ifdef CONFIG_MIPS_MT_SMTC
+-/* Detect and execute deferred IPI "interrupts" */
+- LONG_L s0, TI_REGS($28)
+- LONG_S sp, TI_REGS($28)
+- jal deferred_smtc_ipi
+- LONG_S s0, TI_REGS($28)
+ #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
+ /* Re-arm any temporarily masked interrupts not explicitly "acked" */
+ mfc0 v0, CP0_TCSTATUS
+@@ -112,6 +107,11 @@
+ xor t0, t0, t3
+ mtc0 t0, CP0_TCCONTEXT
+ #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
++/* Detect and execute deferred IPI "interrupts" */
++ LONG_L s0, TI_REGS($28)
++ LONG_S sp, TI_REGS($28)
++ jal deferred_smtc_ipi
++ LONG_S s0, TI_REGS($28)
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ .set noat
+ RESTORE_TEMP
+diff -Nurd linux-2.6.24/arch/mips/kernel/gdb-low.S mer-smartq-kernel/arch/mips/kernel/gdb-low.S
+--- linux-2.6.24/arch/mips/kernel/gdb-low.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/gdb-low.S 2009-11-17 12:13:29.000000000 +0100
+@@ -9,21 +9,21 @@
+ #include <asm/errno.h>
+ #include <asm/irqflags.h>
+ #include <asm/mipsregs.h>
++#include <asm/asm-offsets.h>
+ #include <asm/regdef.h>
+ #include <asm/stackframe.h>
+-#include <asm/gdb-stub.h>
+
+ #ifdef CONFIG_32BIT
+ #define DMFC0 mfc0
+ #define DMTC0 mtc0
+ #define LDC1 lwc1
+-#define SDC1 lwc1
++#define SDC1 swc1
+ #endif
+ #ifdef CONFIG_64BIT
+ #define DMFC0 dmfc0
+ #define DMTC0 dmtc0
+ #define LDC1 ldc1
+-#define SDC1 ldc1
++#define SDC1 sdc1
+ #endif
+
+ /*
+@@ -78,10 +78,19 @@
+ LONG_S v0, GDB_FR_EPC(sp)
+ DMFC0 v0, CP0_BADVADDR
+ LONG_S v0, GDB_FR_BADVADDR(sp)
++#ifdef CONFIG_CPU_HAS_SMARTMIPS
++ mflhxu v0
++ LONG_S v0, GDB_FR_LO(sp)
++ mflhxu v0
++ LONG_S v0, GDB_FR_HI(sp)
++ mflhxu v0
++ LONG_S v0, GDB_FR_ACX(sp)
++#else
+ mfhi v0
+ LONG_S v0, GDB_FR_HI(sp)
+ mflo v0
+ LONG_S v0, GDB_FR_LO(sp)
++#endif
+
+ /*
+ * Now the integer registers
+@@ -317,10 +326,19 @@
+ LONG_L v1, GDB_FR_EPC(sp)
+ mtc0 v0, CP0_STATUS
+ DMTC0 v1, CP0_EPC
++#ifdef CONFIG_CPU_HAS_SMARTMIPS
++ LONG_L v0, GDB_FR_ACX(sp)
++ mtlhx v0
++ LONG_L v0, GDB_FR_HI(sp)
++ mtlhx v0
++ LONG_L v0, GDB_FR_LO(sp)
++ mtlhx v0
++#else
+ LONG_L v0, GDB_FR_HI(sp)
+ LONG_L v1, GDB_FR_LO(sp)
+ mthi v0
+ mtlo v1
++#endif
+ LONG_L $31, GDB_FR_REG31(sp)
+ LONG_L $30, GDB_FR_REG30(sp)
+ LONG_L $28, GDB_FR_REG28(sp)
+diff -Nurd linux-2.6.24/arch/mips/kernel/gdb-stub.c mer-smartq-kernel/arch/mips/kernel/gdb-stub.c
+--- linux-2.6.24/arch/mips/kernel/gdb-stub.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/gdb-stub.c 2009-11-17 12:13:29.000000000 +0100
+@@ -139,7 +139,6 @@
+ #include <asm/system.h>
+ #include <asm/gdb-stub.h>
+ #include <asm/inst.h>
+-#include <asm/smp.h>
+
+ /*
+ * external low-level support routines
+@@ -656,6 +655,7 @@
+ *epc = (unsigned long)async_breakpoint;
+ }
+
++#ifdef CONFIG_SMP
+ static void kgdb_wait(void *arg)
+ {
+ unsigned flags;
+@@ -668,6 +668,7 @@
+
+ local_irq_restore(flags);
+ }
++#endif
+
+ /*
+ * GDB stub needs to call kgdb_wait on all processor with interrupts
+diff -Nurd linux-2.6.24/arch/mips/kernel/genex.S mer-smartq-kernel/arch/mips/kernel/genex.S
+--- linux-2.6.24/arch/mips/kernel/genex.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/genex.S 2009-11-17 12:13:29.000000000 +0100
+@@ -20,6 +20,7 @@
+ #include <asm/stackframe.h>
+ #include <asm/war.h>
+ #include <asm/page.h>
++#include <asm/thread_info.h>
+
+ #define PANIC_PIC(msg) \
+ .set push; \
+@@ -126,7 +127,42 @@
+
+ __FINIT
+
++ .align 5 /* 32 byte rollback region */
++LEAF(r4k_wait)
++ .set push
++ .set noreorder
++ /* start of rollback region */
++ LONG_L t0, TI_FLAGS($28)
++ nop
++ andi t0, _TIF_NEED_RESCHED
++ bnez t0, 1f
++ nop
++ nop
++ nop
++ .set mips3
++ wait
++ /* end of rollback region (the region size must be power of two) */
++ .set pop
++1:
++ jr ra
++ END(r4k_wait)
++
++ .macro BUILD_ROLLBACK_PROLOGUE handler
++ FEXPORT(rollback_\handler)
++ .set push
++ .set noat
++ MFC0 k0, CP0_EPC
++ PTR_LA k1, r4k_wait
++ ori k0, 0x1f /* 32 byte rollback region */
++ xori k0, 0x1f
++ bne k0, k1, 9f
++ MTC0 k0, CP0_EPC
++9:
++ .set pop
++ .endm
++
+ .align 5
++BUILD_ROLLBACK_PROLOGUE handle_int
+ NESTED(handle_int, PT_SIZE, sp)
+ #ifdef CONFIG_TRACE_IRQFLAGS
+ /*
+@@ -201,6 +237,7 @@
+ * This prototype is copied to ebase + n*IntCtl.VS and patched
+ * to invoke the handler
+ */
++BUILD_ROLLBACK_PROLOGUE except_vec_vi
+ NESTED(except_vec_vi, 0, sp)
+ SAVE_SOME
+ SAVE_AT
+@@ -245,8 +282,8 @@
+ and t0, a0, t1
+ #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
+ mfc0 t2, CP0_TCCONTEXT
+- or t0, t0, t2
+- mtc0 t0, CP0_TCCONTEXT
++ or t2, t0, t2
++ mtc0 t2, CP0_TCCONTEXT
+ #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
+ xor t1, t1, t0
+ mtc0 t1, CP0_STATUS
+diff -Nurd linux-2.6.24/arch/mips/kernel/head.S mer-smartq-kernel/arch/mips/kernel/head.S
+--- linux-2.6.24/arch/mips/kernel/head.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/head.S 2009-11-17 12:13:29.000000000 +0100
+@@ -22,6 +22,7 @@
+ #include <asm/irqflags.h>
+ #include <asm/regdef.h>
+ #include <asm/page.h>
++#include <asm/pgtable-bits.h>
+ #include <asm/mipsregs.h>
+ #include <asm/stackframe.h>
+
+@@ -194,8 +195,11 @@
+
+ j start_kernel
+ END(kernel_entry)
++ __FINIT
+
++#ifndef CONFIG_HOTPLUG_CPU
+ __INIT
++#endif
+
+ #ifdef CONFIG_SMP
+ /*
+diff -Nurd linux-2.6.24/arch/mips/kernel/i8253.c mer-smartq-kernel/arch/mips/kernel/i8253.c
+--- linux-2.6.24/arch/mips/kernel/i8253.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/i8253.c 2009-11-17 12:13:29.000000000 +0100
+@@ -15,6 +15,7 @@
+ #include <asm/time.h>
+
+ DEFINE_SPINLOCK(i8253_lock);
++EXPORT_SYMBOL(i8253_lock);
+
+ /*
+ * Initialize the PIT timer.
+diff -Nurd linux-2.6.24/arch/mips/kernel/irixelf.c mer-smartq-kernel/arch/mips/kernel/irixelf.c
+--- linux-2.6.24/arch/mips/kernel/irixelf.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/irixelf.c 2009-11-17 12:13:29.000000000 +0100
+@@ -578,7 +578,7 @@
+ * process and the system, here we map the page and fill the
+ * structure
+ */
+-static void irix_map_prda_page(void)
++static int irix_map_prda_page(void)
+ {
+ unsigned long v;
+ struct prda *pp;
+@@ -587,8 +587,8 @@
+ v = do_brk(PRDA_ADDRESS, PAGE_SIZE);
+ up_write(&current->mm->mmap_sem);
+
+- if (v < 0)
+- return;
++ if (v != PRDA_ADDRESS)
++ return v; /* v must be an error code */
+
+ pp = (struct prda *) v;
+ pp->prda_sys.t_pid = current->pid;
+@@ -596,6 +596,8 @@
+ pp->prda_sys.t_rpid = current->pid;
+
+ /* We leave the rest set to zero */
++
++ return 0;
+ }
+
+
+@@ -781,7 +783,8 @@
+ * IRIX maps a page at 0x200000 which holds some system
+ * information. Programs depend on this.
+ */
+- irix_map_prda_page();
++ if (irix_map_prda_page())
++ goto out_free_dentry;
+
+ padzero(elf_bss);
+
+diff -Nurd linux-2.6.24/arch/mips/kernel/irq-rm7000.c mer-smartq-kernel/arch/mips/kernel/irq-rm7000.c
+--- linux-2.6.24/arch/mips/kernel/irq-rm7000.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/irq-rm7000.c 2009-11-17 12:13:29.000000000 +0100
+@@ -33,6 +33,7 @@
+ .mask = mask_rm7k_irq,
+ .mask_ack = mask_rm7k_irq,
+ .unmask = unmask_rm7k_irq,
++ .eoi = unmask_rm7k_irq
+ };
+
+ void __init rm7k_cpu_irq_init(void)
+diff -Nurd linux-2.6.24/arch/mips/kernel/irq-rm9000.c mer-smartq-kernel/arch/mips/kernel/irq-rm9000.c
+--- linux-2.6.24/arch/mips/kernel/irq-rm9000.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/irq-rm9000.c 2009-11-17 12:13:29.000000000 +0100
+@@ -75,6 +75,7 @@
+ .mask = mask_rm9k_irq,
+ .mask_ack = mask_rm9k_irq,
+ .unmask = unmask_rm9k_irq,
++ .eoi = unmask_rm9k_irq
+ };
+
+ static struct irq_chip rm9k_perfcounter_irq = {
+diff -Nurd linux-2.6.24/arch/mips/kernel/kspd.c mer-smartq-kernel/arch/mips/kernel/kspd.c
+--- linux-2.6.24/arch/mips/kernel/kspd.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/kspd.c 2009-11-17 12:13:29.000000000 +0100
+@@ -257,7 +257,7 @@
+
+ vcwd = vpe_getcwd(tclimit);
+
+- /* change to the cwd of the process that loaded the SP program */
++ /* change to cwd of the process that loaded the SP program */
+ old_fs = get_fs();
+ set_fs(KERNEL_DS);
+ sys_chdir(vcwd);
+@@ -323,6 +323,9 @@
+ set >>= 1;
+ }
+ }
++
++ /* Put daemon cwd back to root to avoid umount problems */
++ sys_chdir("/");
+ }
+
+ static int channel_open = 0;
+diff -Nurd linux-2.6.24/arch/mips/kernel/Makefile mer-smartq-kernel/arch/mips/kernel/Makefile
+--- linux-2.6.24/arch/mips/kernel/Makefile 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/Makefile 2009-11-17 12:13:29.000000000 +0100
+@@ -10,6 +10,7 @@
+
+ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
+ obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
++obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
+ obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
+ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
+ obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
+@@ -51,9 +52,9 @@
+ obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o
+ obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
+
+-obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o
+ obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
+ obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
++obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o
+
+ obj-$(CONFIG_I8259) += i8259.o
+ obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
+diff -Nurd linux-2.6.24/arch/mips/kernel/mips-mt-fpaff.c mer-smartq-kernel/arch/mips/kernel/mips-mt-fpaff.c
+--- linux-2.6.24/arch/mips/kernel/mips-mt-fpaff.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/mips-mt-fpaff.c 2009-11-17 12:13:29.000000000 +0100
+@@ -36,7 +36,7 @@
+ */
+ static inline struct task_struct *find_process_by_pid(pid_t pid)
+ {
+- return pid ? find_task_by_pid(pid) : current;
++ return pid ? find_task_by_vpid(pid) : current;
+ }
+
+
+@@ -159,7 +159,7 @@
+ /*
+ * FPU Use Factor empirically derived from experiments on 34K
+ */
+-#define FPUSEFACTOR 333
++#define FPUSEFACTOR 2000
+
+ static __init int mt_fp_affinity_init(void)
+ {
+diff -Nurd linux-2.6.24/arch/mips/kernel/proc.c mer-smartq-kernel/arch/mips/kernel/proc.c
+--- linux-2.6.24/arch/mips/kernel/proc.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/proc.c 2009-11-17 12:13:29.000000000 +0100
+@@ -38,7 +38,7 @@
+ seq_printf(m, "processor\t\t: %ld\n", n);
+ sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
+ cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
+- seq_printf(m, fmt, __cpu_name[smp_processor_id()],
++ seq_printf(m, fmt, __cpu_name[n],
+ (version >> 4) & 0x0f, version & 0x0f,
+ (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
+ seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
+diff -Nurd linux-2.6.24/arch/mips/kernel/process.c mer-smartq-kernel/arch/mips/kernel/process.c
+--- linux-2.6.24/arch/mips/kernel/process.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/process.c 2009-11-17 12:13:29.000000000 +0100
+@@ -55,7 +55,7 @@
+ while (1) {
+ tick_nohz_stop_sched_tick();
+ while (!need_resched()) {
+-#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
++#ifdef CONFIG_MIPS_MT_SMTC
+ extern void smtc_idle_loop_hook(void);
+
+ smtc_idle_loop_hook();
+@@ -152,17 +152,18 @@
+ */
+ p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
+ childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
+- clear_tsk_thread_flag(p, TIF_USEDFPU);
+
+-#ifdef CONFIG_MIPS_MT_FPAFF
++#ifdef CONFIG_MIPS_MT_SMTC
+ /*
+- * FPU affinity support is cleaner if we track the
+- * user-visible CPU affinity from the very beginning.
+- * The generic cpus_allowed mask will already have
+- * been copied from the parent before copy_thread
+- * is invoked.
++ * SMTC restores TCStatus after Status, and the CU bits
++ * are aliased there.
+ */
+- p->thread.user_cpus_allowed = p->cpus_allowed;
++ childregs->cp0_tcstatus &= ~(ST0_CU2|ST0_CU1);
++#endif
++ clear_tsk_thread_flag(p, TIF_USEDFPU);
++
++#ifdef CONFIG_MIPS_MT_FPAFF
++ clear_tsk_thread_flag(p, TIF_FPUBOUND);
+ #endif /* CONFIG_MIPS_MT_FPAFF */
+
+ if (clone_flags & CLONE_SETTLS)
+diff -Nurd linux-2.6.24/arch/mips/kernel/ptrace.c mer-smartq-kernel/arch/mips/kernel/ptrace.c
+--- linux-2.6.24/arch/mips/kernel/ptrace.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/ptrace.c 2009-11-17 12:13:29.000000000 +0100
+@@ -238,7 +238,7 @@
+ case FPC_EIR: { /* implementation / version register */
+ unsigned int flags;
+ #ifdef CONFIG_MIPS_MT_SMTC
+- unsigned int irqflags;
++ unsigned long irqflags;
+ unsigned int mtflags;
+ #endif /* CONFIG_MIPS_MT_SMTC */
+
+diff -Nurd linux-2.6.24/arch/mips/kernel/rtlx.c mer-smartq-kernel/arch/mips/kernel/rtlx.c
+--- linux-2.6.24/arch/mips/kernel/rtlx.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/rtlx.c 2009-11-17 12:13:29.000000000 +0100
+@@ -73,6 +73,15 @@
+ static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
+ {
+ int i;
++ unsigned int flags, vpeflags;
++
++ /* Ought not to be strictly necessary for SMTC builds */
++ local_irq_save(flags);
++ vpeflags = dvpe();
++ set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ);
++ irq_enable_hazard();
++ evpe(vpeflags);
++ local_irq_restore(flags);
+
+ for (i = 0; i < RTLX_CHANNELS; i++) {
+ wake_up(&channel_wqs[i].lx_queue);
+@@ -109,7 +118,8 @@
+ static int rtlx_init(struct rtlx_info *rtlxi)
+ {
+ if (rtlxi->id != RTLX_ID) {
+- printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id);
++ printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n",
++ rtlxi, rtlxi->id);
+ return -ENOEXEC;
+ }
+
+@@ -163,18 +173,17 @@
+
+ if (rtlx == NULL) {
+ if( (p = vpe_get_shared(tclimit)) == NULL) {
+- if (can_sleep) {
+- __wait_event_interruptible(channel_wqs[index].lx_queue,
+- (p = vpe_get_shared(tclimit)),
+- ret);
+- if (ret)
+- goto out_fail;
+- } else {
+- printk(KERN_DEBUG "No SP program loaded, and device "
+- "opened with O_NONBLOCK\n");
+- ret = -ENOSYS;
++ if (can_sleep) {
++ __wait_event_interruptible(channel_wqs[index].lx_queue,
++ (p = vpe_get_shared(tclimit)), ret);
++ if (ret)
+ goto out_fail;
+- }
++ } else {
++ printk(KERN_DEBUG "No SP program loaded, and device "
++ "opened with O_NONBLOCK\n");
++ ret = -ENOSYS;
++ goto out_fail;
++ }
+ }
+
+ smp_rmb();
+@@ -183,7 +192,9 @@
+ DEFINE_WAIT(wait);
+
+ for (;;) {
+- prepare_to_wait(&channel_wqs[index].lx_queue, &wait, TASK_INTERRUPTIBLE);
++ prepare_to_wait(
++ &channel_wqs[index].lx_queue,
++ &wait, TASK_INTERRUPTIBLE);
+ smp_rmb();
+ if (*p != NULL)
+ break;
+@@ -196,7 +207,7 @@
+ }
+ finish_wait(&channel_wqs[index].lx_queue, &wait);
+ } else {
+- printk(" *vpe_get_shared is NULL. "
++ pr_err(" *vpe_get_shared is NULL. "
+ "Has an SP program been loaded?\n");
+ ret = -ENOSYS;
+ goto out_fail;
+@@ -204,8 +215,9 @@
+ }
+
+ if ((unsigned int)*p < KSEG0) {
+- printk(KERN_WARNING "vpe_get_shared returned an invalid pointer "
+- "maybe an error code %d\n", (int)*p);
++ printk(KERN_WARNING "vpe_get_shared returned an "
++ "invalid pointer maybe an error code %d\n",
++ (int)*p);
+ ret = -ENOSYS;
+ goto out_fail;
+ }
+@@ -233,6 +245,10 @@
+
+ int rtlx_release(int index)
+ {
++ if (rtlx == NULL) {
++ pr_err("rtlx_release() with null rtlx\n");
++ return 0;
++ }
+ rtlx->channel[index].lx_state = RTLX_STATE_UNUSED;
+ return 0;
+ }
+@@ -252,8 +268,8 @@
+ int ret = 0;
+
+ __wait_event_interruptible(channel_wqs[index].lx_queue,
+- chan->lx_read != chan->lx_write || sp_stopping,
+- ret);
++ (chan->lx_read != chan->lx_write) ||
++ sp_stopping, ret);
+ if (ret)
+ return ret;
+
+@@ -283,7 +299,9 @@
+ unsigned int rtlx_write_poll(int index)
+ {
+ struct rtlx_channel *chan = &rtlx->channel[index];
+- return write_spacefree(chan->rt_read, chan->rt_write, chan->buffer_size);
++
++ return write_spacefree(chan->rt_read, chan->rt_write,
++ chan->buffer_size);
+ }
+
+ ssize_t rtlx_read(int index, void __user *buff, size_t count)
+@@ -345,8 +363,8 @@
+ rt_read = rt->rt_read;
+
+ /* total number of bytes to copy */
+- count = min(count,
+- (size_t)write_spacefree(rt_read, rt->rt_write, rt->buffer_size));
++ count = min(count, (size_t)write_spacefree(rt_read, rt->rt_write,
++ rt->buffer_size));
+
+ /* first bit from write pointer to the end of the buffer, or count */
+ fl = min(count, (size_t) rt->buffer_size - rt->rt_write);
+@@ -515,6 +533,11 @@
+
+ if (cpu_has_vint)
+ set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
++ else {
++ pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
++ err = -ENODEV;
++ goto out_chrdev;
++ }
+
+ rtlx_irq.dev_id = rtlx;
+ setup_irq(rtlx_irq_num, &rtlx_irq);
+diff -Nurd linux-2.6.24/arch/mips/kernel/scall32-o32.S mer-smartq-kernel/arch/mips/kernel/scall32-o32.S
+--- linux-2.6.24/arch/mips/kernel/scall32-o32.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/scall32-o32.S 2009-11-17 12:13:29.000000000 +0100
+@@ -184,7 +184,7 @@
+ * The system call does not exist in this kernel
+ */
+ illegal_syscall:
+- li v0, -ENOSYS # error
++ li v0, ENOSYS # error
+ sw v0, PT_R2(sp)
+ li t0, 1 # set error flag
+ sw t0, PT_R7(sp)
+@@ -270,18 +270,11 @@
+ subu t0, a0, __NR_O32_Linux # check syscall number
+ sltiu v0, t0, __NR_O32_Linux_syscalls + 1
+ #endif
++ beqz t0, einval # do not recurse
+ sll t1, t0, 3
+ beqz v0, einval
+-
+ lw t2, sys_call_table(t1) # syscall routine
+
+-#if defined(CONFIG_BINFMT_IRIX)
+- li v1, 4000 # nr of sys_syscall
+-#else
+- li v1, 4000 - __NR_O32_Linux # index of sys_syscall
+-#endif
+- beq t0, v1, einval # do not recurse
+-
+ /* Some syscalls like execve get their arguments from struct pt_regs
+ and claim zero arguments in the syscall table. Thus we have to
+ assume the worst case and shuffle around all potential arguments.
+@@ -305,7 +298,7 @@
+ jr t2
+ /* Unreached */
+
+-einval: li v0, -EINVAL
++einval: li v0, -ENOSYS
+ jr ra
+ END(sys_syscall)
+
+@@ -646,7 +639,7 @@
+ sys sys_pselect6 6
+ sys sys_ppoll 5
+ sys sys_unshare 1
+- sys sys_splice 4
++ sys sys_splice 6
+ sys sys_sync_file_range 7 /* 4305 */
+ sys sys_tee 4
+ sys sys_vmsplice 4
+diff -Nurd linux-2.6.24/arch/mips/kernel/scall64-64.S mer-smartq-kernel/arch/mips/kernel/scall64-64.S
+--- linux-2.6.24/arch/mips/kernel/scall64-64.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/scall64-64.S 2009-11-17 12:13:29.000000000 +0100
+@@ -117,7 +117,7 @@
+
+ illegal_syscall:
+ /* This also isn't a 64-bit syscall, throw an error. */
+- li v0, -ENOSYS # error
++ li v0, ENOSYS # error
+ sd v0, PT_R2(sp)
+ li t0, 1 # set error flag
+ sd t0, PT_R7(sp)
+diff -Nurd linux-2.6.24/arch/mips/kernel/scall64-n32.S mer-smartq-kernel/arch/mips/kernel/scall64-n32.S
+--- linux-2.6.24/arch/mips/kernel/scall64-n32.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/scall64-n32.S 2009-11-17 12:13:29.000000000 +0100
+@@ -390,7 +390,7 @@
+ PTR sys_splice
+ PTR sys_sync_file_range
+ PTR sys_tee
+- PTR sys_vmsplice /* 6270 */
++ PTR compat_sys_vmsplice /* 6270 */
+ PTR sys_move_pages
+ PTR compat_sys_set_robust_list
+ PTR compat_sys_get_robust_list
+diff -Nurd linux-2.6.24/arch/mips/kernel/scall64-o32.S mer-smartq-kernel/arch/mips/kernel/scall64-o32.S
+--- linux-2.6.24/arch/mips/kernel/scall64-o32.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/scall64-o32.S 2009-11-17 12:13:29.000000000 +0100
+@@ -174,14 +174,12 @@
+ END(handle_sys)
+
+ LEAF(sys32_syscall)
+- sltu v0, a0, __NR_O32_Linux + __NR_O32_Linux_syscalls + 1
++ subu t0, a0, __NR_O32_Linux # check syscall number
++ sltiu v0, t0, __NR_O32_Linux_syscalls + 1
++ beqz t0, einval # do not recurse
++ dsll t1, t0, 3
+ beqz v0, einval
+-
+- dsll v0, a0, 3
+- ld t2, (sys_call_table - (__NR_O32_Linux * 8))(v0)
+-
+- li v1, 4000 # indirect syscall number
+- beq a0, v1, einval # do not recurse
++ ld t2, sys_call_table(t1) # syscall routine
+
+ move a0, a1 # shift argument registers
+ move a1, a2
+@@ -198,7 +196,7 @@
+ jr t2
+ /* Unreached */
+
+-einval: li v0, -EINVAL
++einval: li v0, -ENOSYS
+ jr ra
+ END(sys32_syscall)
+
+@@ -512,7 +510,7 @@
+ PTR sys_splice
+ PTR sys32_sync_file_range /* 4305 */
+ PTR sys_tee
+- PTR sys_vmsplice
++ PTR compat_sys_vmsplice
+ PTR compat_sys_move_pages
+ PTR compat_sys_set_robust_list
+ PTR compat_sys_get_robust_list /* 4310 */
+diff -Nurd linux-2.6.24/arch/mips/kernel/setup.c mer-smartq-kernel/arch/mips/kernel/setup.c
+--- linux-2.6.24/arch/mips/kernel/setup.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/setup.c 2009-11-17 12:13:29.000000000 +0100
+@@ -329,6 +329,7 @@
+ /*
+ * Determine low and high memory ranges
+ */
++ max_pfn = max_low_pfn;
+ if (max_low_pfn > PFN_DOWN(HIGHMEM_START)) {
+ #ifdef CONFIG_HIGHMEM
+ highstart_pfn = PFN_DOWN(HIGHMEM_START);
+@@ -609,8 +610,8 @@
+ struct dentry *d;
+
+ d = debugfs_create_dir("mips", NULL);
+- if (IS_ERR(d))
+- return PTR_ERR(d);
++ if (!d)
++ return -ENOMEM;
+ mips_debugfs_dir = d;
+ return 0;
+ }
+diff -Nurd linux-2.6.24/arch/mips/kernel/smp.c mer-smartq-kernel/arch/mips/kernel/smp.c
+--- linux-2.6.24/arch/mips/kernel/smp.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/smp.c 2009-11-17 12:13:29.000000000 +0100
+@@ -238,8 +238,10 @@
+ * Remove this CPU:
+ */
+ cpu_clear(smp_processor_id(), cpu_online_map);
+- local_irq_enable(); /* May need to service _machine_restart IPI */
+- for (;;); /* Wait if available. */
++ for (;;) {
++ if (cpu_wait)
++ (*cpu_wait)(); /* Wait if available. */
++ }
+ }
+
+ void smp_send_stop(void)
+diff -Nurd linux-2.6.24/arch/mips/kernel/smtc.c mer-smartq-kernel/arch/mips/kernel/smtc.c
+--- linux-2.6.24/arch/mips/kernel/smtc.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/smtc.c 2009-11-17 12:13:29.000000000 +0100
+@@ -1,4 +1,21 @@
+-/* Copyright (C) 2004 Mips Technologies, Inc */
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Copyright (C) 2004 Mips Technologies, Inc
++ * Copyright (C) 2008 Kevin D. Kissell
++ */
+
+ #include <linux/clockchips.h>
+ #include <linux/kernel.h>
+@@ -22,7 +39,6 @@
+ #include <asm/time.h>
+ #include <asm/addrspace.h>
+ #include <asm/smtc.h>
+-#include <asm/smtc_ipi.h>
+ #include <asm/smtc_proc.h>
+
+ /*
+@@ -59,11 +75,6 @@
+
+ asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
+
+-/*
+- * Clock interrupt "latch" buffers, per "CPU"
+- */
+-
+-static atomic_t ipi_timer_latch[NR_CPUS];
+
+ /*
+ * Number of InterProcessor Interupt (IPI) message buffers to allocate
+@@ -71,7 +82,7 @@
+
+ #define IPIBUF_PER_CPU 4
+
+-static struct smtc_ipi_q IPIQ[NR_CPUS];
++struct smtc_ipi_q IPIQ[NR_CPUS];
+ static struct smtc_ipi_q freeIPIq;
+
+
+@@ -291,7 +302,7 @@
+ * phys_cpu_present_map and the logical/physical mappings.
+ */
+
+-int __init mipsmt_build_cpu_map(int start_cpu_slot)
++int __init smtc_build_cpu_map(int start_cpu_slot)
+ {
+ int i, ntcs;
+
+@@ -334,7 +345,12 @@
+ write_tc_c0_tcstatus((read_tc_c0_tcstatus()
+ & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
+ | TCSTATUS_A);
+- write_tc_c0_tccontext(0);
++ /*
++ * TCContext gets an offset from the base of the IPIQ array
++ * to be used in low-level code to detect the presence of
++ * an active IPI queue
++ */
++ write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
+ /* Bind tc to vpe */
+ write_tc_c0_tcbind(vpe);
+ /* In general, all TCs should have the same cpu_data indications */
+@@ -346,8 +362,14 @@
+ cpu_data[cpu].tc_id = tc;
+ }
+
++/*
++ * Tweak to get Count registes in as close a sync as possible.
++ * Value seems good for 34K-class cores.
++ */
+
+-void mipsmt_prepare_cpus(void)
++#define CP0_SKEW 8
++
++void smtc_prepare_cpus(int cpus)
+ {
+ int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
+ unsigned long flags;
+@@ -371,7 +393,6 @@
+ IPIQ[i].head = IPIQ[i].tail = NULL;
+ spin_lock_init(&IPIQ[i].lock);
+ IPIQ[i].depth = 0;
+- atomic_set(&ipi_timer_latch[i], 0);
+ }
+
+ /* cpu_data index starts at zero */
+@@ -492,7 +513,8 @@
+ write_vpe_c0_compare(0);
+ /* Propagate Config7 */
+ write_vpe_c0_config7(read_c0_config7());
+- write_vpe_c0_count(read_c0_count());
++ write_vpe_c0_count(read_c0_count() + CP0_SKEW);
++ ehb();
+ }
+ /* enable multi-threading within VPE */
+ write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
+@@ -564,7 +586,7 @@
+ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
+ {
+ extern u32 kernelsp[NR_CPUS];
+- long flags;
++ unsigned long flags;
+ int mtflags;
+
+ LOCK_MT_PRA();
+@@ -593,24 +615,22 @@
+
+ void smtc_init_secondary(void)
+ {
+- /*
+- * Start timer on secondary VPEs if necessary.
+- * plat_timer_setup has already have been invoked by init/main
+- * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that
+- * SMTC init code assigns TCs consdecutively and in ascending order
+- * to across available VPEs.
+- */
+- if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
+- ((read_c0_tcbind() & TCBIND_CURVPE)
+- != cpu_data[smp_processor_id() - 1].vpe_id)){
+- write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
+- }
+-
+ local_irq_enable();
+ }
+
+ void smtc_smp_finish(void)
+ {
++ int cpu = smp_processor_id();
++
++ /*
++ * Lowest-numbered CPU per VPE starts a clock tick.
++ * Like per_cpu_trap_init() hack, this assumes that
++ * SMTC init code assigns TCs consdecutively and
++ * in ascending order across available VPEs.
++ */
++ if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
++ write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
++
+ printk("TC %d going on-line as CPU %d\n",
+ cpu_data[smp_processor_id()].tc_id, smp_processor_id());
+ }
+@@ -761,8 +781,10 @@
+ {
+ int tcstatus;
+ struct smtc_ipi *pipi;
+- long flags;
++ unsigned long flags;
+ int mtflags;
++ unsigned long tcrestart;
++ extern void r4k_wait_irqoff(void), __pastwait(void);
+
+ if (cpu == smp_processor_id()) {
+ printk("Cannot Send IPI to self!\n");
+@@ -779,9 +801,7 @@
+ pipi->arg = (void *)action;
+ pipi->dest = cpu;
+ if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
+- if (type == SMTC_CLOCK_TICK)
+- atomic_inc(&ipi_timer_latch[cpu]);
+- /* If not on same VPE, enqueue and send cross-VPE interupt */
++ /* If not on same VPE, enqueue and send cross-VPE interrupt */
+ smtc_ipi_nq(&IPIQ[cpu], pipi);
+ LOCK_CORE_PRA();
+ settc(cpu_data[cpu].tc_id);
+@@ -808,22 +828,29 @@
+
+ if ((tcstatus & TCSTATUS_IXMT) != 0) {
+ /*
+- * Spin-waiting here can deadlock,
+- * so we queue the message for the target TC.
++ * If we're in the the irq-off version of the wait
++ * loop, we need to force exit from the wait and
++ * do a direct post of the IPI.
++ */
++ if (cpu_wait == r4k_wait_irqoff) {
++ tcrestart = read_tc_c0_tcrestart();
++ if (tcrestart >= (unsigned long)r4k_wait_irqoff
++ && tcrestart < (unsigned long)__pastwait) {
++ write_tc_c0_tcrestart(__pastwait);
++ tcstatus &= ~TCSTATUS_IXMT;
++ write_tc_c0_tcstatus(tcstatus);
++ goto postdirect;
++ }
++ }
++ /*
++ * Otherwise we queue the message for the target TC
++ * to pick up when he does a local_irq_restore()
+ */
+ write_tc_c0_tchalt(0);
+ UNLOCK_CORE_PRA();
+- /* Try to reduce redundant timer interrupt messages */
+- if (type == SMTC_CLOCK_TICK) {
+- if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){
+- smtc_ipi_nq(&freeIPIq, pipi);
+- return;
+- }
+- }
+ smtc_ipi_nq(&IPIQ[cpu], pipi);
+ } else {
+- if (type == SMTC_CLOCK_TICK)
+- atomic_inc(&ipi_timer_latch[cpu]);
++postdirect:
+ post_direct_ipi(cpu, pipi);
+ write_tc_c0_tchalt(0);
+ UNLOCK_CORE_PRA();
+@@ -892,7 +919,7 @@
+ smp_call_function_interrupt();
+ }
+
+-DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
++DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+
+ void ipi_decode(struct smtc_ipi *pipi)
+ {
+@@ -900,20 +927,13 @@
+ struct clock_event_device *cd;
+ void *arg_copy = pipi->arg;
+ int type_copy = pipi->type;
+- int ticks;
+-
+ smtc_ipi_nq(&freeIPIq, pipi);
+ switch (type_copy) {
+ case SMTC_CLOCK_TICK:
+ irq_enter();
+ kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++;
+- cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
+- ticks = atomic_read(&ipi_timer_latch[cpu]);
+- atomic_sub(ticks, &ipi_timer_latch[cpu]);
+- while (ticks) {
+- cd->event_handler(cd);
+- ticks--;
+- }
++ cd = &per_cpu(mips_clockevent_device, cpu);
++ cd->event_handler(cd);
+ irq_exit();
+ break;
+
+@@ -946,24 +966,48 @@
+ }
+ }
+
++/*
++ * Similar to smtc_ipi_replay(), but invoked from context restore,
++ * so it reuses the current exception frame rather than set up a
++ * new one with self_ipi.
++ */
++
+ void deferred_smtc_ipi(void)
+ {
+- struct smtc_ipi *pipi;
+- unsigned long flags;
+-/* DEBUG */
+- int q = smp_processor_id();
++ int cpu = smp_processor_id();
+
+ /*
+ * Test is not atomic, but much faster than a dequeue,
+ * and the vast majority of invocations will have a null queue.
++ * If irq_disabled when this was called, then any IPIs queued
++ * after we test last will be taken on the next irq_enable/restore.
++ * If interrupts were enabled, then any IPIs added after the
++ * last test will be taken directly.
+ */
+- if (IPIQ[q].head != NULL) {
+- while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
+- /* ipi_decode() should be called with interrupts off */
+- local_irq_save(flags);
++
++ while (IPIQ[cpu].head != NULL) {
++ struct smtc_ipi_q *q = &IPIQ[cpu];
++ struct smtc_ipi *pipi;
++ unsigned long flags;
++
++ /*
++ * It may be possible we'll come in with interrupts
++ * already enabled.
++ */
++ local_irq_save(flags);
++
++ spin_lock(&q->lock);
++ pipi = __smtc_ipi_dq(q);
++ spin_unlock(&q->lock);
++ if (pipi != NULL)
+ ipi_decode(pipi);
+- local_irq_restore(flags);
+- }
++ /*
++ * The use of the __raw_local restore isn't
++ * as obviously necessary here as in smtc_ipi_replay(),
++ * but it's more efficient, given that we're already
++ * running down the IPI queue.
++ */
++ __raw_local_irq_restore(flags);
+ }
+ }
+
+@@ -984,7 +1028,7 @@
+ struct smtc_ipi *pipi;
+ unsigned long tcstatus;
+ int sent;
+- long flags;
++ unsigned long flags;
+ unsigned int mtflags;
+ unsigned int vpflags;
+
+@@ -1075,55 +1119,53 @@
+
+ /*
+ * SMTC-specific hacks invoked from elsewhere in the kernel.
+- *
+- * smtc_ipi_replay is called from raw_local_irq_restore which is only ever
+- * called with interrupts disabled. We do rely on interrupts being disabled
+- * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would
+- * result in a recursive call to raw_local_irq_restore().
+ */
+
+-static void __smtc_ipi_replay(void)
++ /*
++ * smtc_ipi_replay is called from raw_local_irq_restore
++ */
++
++void smtc_ipi_replay(void)
+ {
+ unsigned int cpu = smp_processor_id();
+
+ /*
+ * To the extent that we've ever turned interrupts off,
+ * we may have accumulated deferred IPIs. This is subtle.
+- * If we use the smtc_ipi_qdepth() macro, we'll get an
+- * exact number - but we'll also disable interrupts
+- * and create a window of failure where a new IPI gets
+- * queued after we test the depth but before we re-enable
+- * interrupts. So long as IXMT never gets set, however,
+ * we should be OK: If we pick up something and dispatch
+ * it here, that's great. If we see nothing, but concurrent
+ * with this operation, another TC sends us an IPI, IXMT
+ * is clear, and we'll handle it as a real pseudo-interrupt
+- * and not a pseudo-pseudo interrupt.
++ * and not a pseudo-pseudo interrupt. The important thing
++ * is to do the last check for queued message *after* the
++ * re-enabling of interrupts.
+ */
+- if (IPIQ[cpu].depth > 0) {
+- while (1) {
+- struct smtc_ipi_q *q = &IPIQ[cpu];
+- struct smtc_ipi *pipi;
+- extern void self_ipi(struct smtc_ipi *);
++ while (IPIQ[cpu].head != NULL) {
++ struct smtc_ipi_q *q = &IPIQ[cpu];
++ struct smtc_ipi *pipi;
++ unsigned long flags;
+
+- spin_lock(&q->lock);
+- pipi = __smtc_ipi_dq(q);
+- spin_unlock(&q->lock);
+- if (!pipi)
+- break;
++ /*
++ * It's just possible we'll come in with interrupts
++ * already enabled.
++ */
++ local_irq_save(flags);
+
++ spin_lock(&q->lock);
++ pipi = __smtc_ipi_dq(q);
++ spin_unlock(&q->lock);
++ /*
++ ** But use a raw restore here to avoid recursion.
++ */
++ __raw_local_irq_restore(flags);
++
++ if (pipi) {
+ self_ipi(pipi);
+ smtc_cpu_stats[cpu].selfipis++;
+ }
+ }
+ }
+
+-void smtc_ipi_replay(void)
+-{
+- raw_local_irq_disable();
+- __smtc_ipi_replay();
+-}
+-
+ EXPORT_SYMBOL(smtc_ipi_replay);
+
+ void smtc_idle_loop_hook(void)
+@@ -1202,40 +1244,13 @@
+ }
+ }
+
+- /*
+- * Now that we limit outstanding timer IPIs, check for hung TC
+- */
+- for (tc = 0; tc < NR_CPUS; tc++) {
+- /* Don't check ourself - we'll dequeue IPIs just below */
+- if ((tc != smp_processor_id()) &&
+- atomic_read(&ipi_timer_latch[tc]) > timerq_limit) {
+- if (clock_hang_reported[tc] == 0) {
+- pdb_msg += sprintf(pdb_msg,
+- "TC %d looks hung with timer latch at %d\n",
+- tc, atomic_read(&ipi_timer_latch[tc]));
+- clock_hang_reported[tc]++;
+- }
+- }
+- }
+ emt(mtflags);
+ local_irq_restore(flags);
+ if (pdb_msg != &id_ho_db_msg[0])
+ printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
+ #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
+
+- /*
+- * Replay any accumulated deferred IPIs. If "Instant Replay"
+- * is in use, there should never be any.
+- */
+-#ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
+- {
+- unsigned long flags;
+-
+- local_irq_save(flags);
+- __smtc_ipi_replay();
+- local_irq_restore(flags);
+- }
+-#endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
++ smtc_ipi_replay();
+ }
+
+ void smtc_soft_dump(void)
+@@ -1251,10 +1266,6 @@
+ printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
+ }
+ smtc_ipi_qdump();
+- printk("Timer IPI Backlogs:\n");
+- for (i=0; i < NR_CPUS; i++) {
+- printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i]));
+- }
+ printk("%d Recoveries of \"stolen\" FPU\n",
+ atomic_read(&smtc_fpu_recoveries));
+ }
+diff -Nurd linux-2.6.24/arch/mips/kernel/sysirix.c mer-smartq-kernel/arch/mips/kernel/sysirix.c
+--- linux-2.6.24/arch/mips/kernel/sysirix.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/sysirix.c 2009-11-17 12:13:29.000000000 +0100
+@@ -111,7 +111,7 @@
+ printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n",
+ current->comm, current->pid);
+ read_lock(&tasklist_lock);
+- task = find_task_by_pid(va_arg(args, pid_t));
++ task = find_task_by_vpid(va_arg(args, pid_t));
+ error = -ESRCH;
+ if (error)
+ error = (task->run_list.next != NULL);
+diff -Nurd linux-2.6.24/arch/mips/kernel/time.c mer-smartq-kernel/arch/mips/kernel/time.c
+--- linux-2.6.24/arch/mips/kernel/time.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/time.c 2009-11-17 12:13:29.000000000 +0100
+@@ -159,6 +159,6 @@
+ {
+ plat_time_init();
+
+- if (mips_clockevent_init() || !cpu_has_mfc0_count_bug())
++ if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
+ init_mips_clocksource();
+ }
+diff -Nurd linux-2.6.24/arch/mips/kernel/traps.c mer-smartq-kernel/arch/mips/kernel/traps.c
+--- linux-2.6.24/arch/mips/kernel/traps.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/traps.c 2009-11-17 12:13:29.000000000 +0100
+@@ -43,6 +43,9 @@
+ #include <asm/types.h>
+ #include <asm/stacktrace.h>
+
++extern void check_wait(void);
++extern asmlinkage void r4k_wait(void);
++extern asmlinkage void rollback_handle_int(void);
+ extern asmlinkage void handle_int(void);
+ extern asmlinkage void handle_tlbm(void);
+ extern asmlinkage void handle_tlbl(void);
+@@ -638,35 +641,24 @@
+ force_sig_info(SIGFPE, &info, current);
+ }
+
+-asmlinkage void do_bp(struct pt_regs *regs)
++static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
++ const char *str)
+ {
+- unsigned int opcode, bcode;
+ siginfo_t info;
+-
+- if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
+- goto out_sigsegv;
+-
+- /*
+- * There is the ancient bug in the MIPS assemblers that the break
+- * code starts left to bit 16 instead to bit 6 in the opcode.
+- * Gas is bug-compatible, but not always, grrr...
+- * We handle both cases with a simple heuristics. --macro
+- */
+- bcode = ((opcode >> 6) & ((1 << 20) - 1));
+- if (bcode < (1 << 10))
+- bcode <<= 10;
++ char b[40];
+
+ /*
+- * (A short test says that IRIX 5.3 sends SIGTRAP for all break
+- * insns, even for break codes that indicate arithmetic failures.
+- * Weird ...)
++ * A short test says that IRIX 5.3 sends SIGTRAP for all trap
++ * insns, even for trap and break codes that indicate arithmetic
++ * failures. Weird ...
+ * But should we continue the brokenness??? --macro
+ */
+- switch (bcode) {
+- case BRK_OVERFLOW << 10:
+- case BRK_DIVZERO << 10:
+- die_if_kernel("Break instruction in kernel code", regs);
+- if (bcode == (BRK_DIVZERO << 10))
++ switch (code) {
++ case BRK_OVERFLOW:
++ case BRK_DIVZERO:
++ scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
++ die_if_kernel(b, regs);
++ if (code == BRK_DIVZERO)
+ info.si_code = FPE_INTDIV;
+ else
+ info.si_code = FPE_INTOVF;
+@@ -676,12 +668,34 @@
+ force_sig_info(SIGFPE, &info, current);
+ break;
+ case BRK_BUG:
+- die("Kernel bug detected", regs);
++ die_if_kernel("Kernel bug detected", regs);
++ force_sig(SIGTRAP, current);
+ break;
+ default:
+- die_if_kernel("Break instruction in kernel code", regs);
++ scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
++ die_if_kernel(b, regs);
+ force_sig(SIGTRAP, current);
+ }
++}
++
++asmlinkage void do_bp(struct pt_regs *regs)
++{
++ unsigned int opcode, bcode;
++
++ if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
++ goto out_sigsegv;
++
++ /*
++ * There is the ancient bug in the MIPS assemblers that the break
++ * code starts left to bit 16 instead to bit 6 in the opcode.
++ * Gas is bug-compatible, but not always, grrr...
++ * We handle both cases with a simple heuristics. --macro
++ */
++ bcode = ((opcode >> 6) & ((1 << 20) - 1));
++ if (bcode >= (1 << 10))
++ bcode >>= 10;
++
++ do_trap_or_bp(regs, bcode, "Break");
+ return;
+
+ out_sigsegv:
+@@ -691,7 +705,6 @@
+ asmlinkage void do_tr(struct pt_regs *regs)
+ {
+ unsigned int opcode, tcode = 0;
+- siginfo_t info;
+
+ if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
+ goto out_sigsegv;
+@@ -700,32 +713,7 @@
+ if (!(opcode & OPCODE))
+ tcode = ((opcode >> 6) & ((1 << 10) - 1));
+
+- /*
+- * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
+- * insns, even for trap codes that indicate arithmetic failures.
+- * Weird ...)
+- * But should we continue the brokenness??? --macro
+- */
+- switch (tcode) {
+- case BRK_OVERFLOW:
+- case BRK_DIVZERO:
+- die_if_kernel("Trap instruction in kernel code", regs);
+- if (tcode == BRK_DIVZERO)
+- info.si_code = FPE_INTDIV;
+- else
+- info.si_code = FPE_INTOVF;
+- info.si_signo = SIGFPE;
+- info.si_errno = 0;
+- info.si_addr = (void __user *) regs->cp0_epc;
+- force_sig_info(SIGFPE, &info, current);
+- break;
+- case BRK_BUG:
+- die("Kernel bug detected", regs);
+- break;
+- default:
+- die_if_kernel("Trap instruction in kernel code", regs);
+- force_sig(SIGTRAP, current);
+- }
++ do_trap_or_bp(regs, tcode, "Trap");
+ return;
+
+ out_sigsegv:
+@@ -783,8 +771,10 @@
+ if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
+ cpumask_t tmask;
+
+- cpus_and(tmask, current->thread.user_cpus_allowed,
+- mt_fpu_cpumask);
++ current->thread.user_cpus_allowed
++ = current->cpus_allowed;
++ cpus_and(tmask, current->cpus_allowed,
++ mt_fpu_cpumask);
+ set_cpus_allowed(current, tmask);
+ set_thread_flag(TIF_FPUBOUND);
+ }
+@@ -1146,6 +1136,9 @@
+
+ extern char except_vec_vi, except_vec_vi_lui;
+ extern char except_vec_vi_ori, except_vec_vi_end;
++ extern char rollback_except_vec_vi;
++ char *vec_start = (cpu_wait == r4k_wait) ?
++ &rollback_except_vec_vi : &except_vec_vi;
+ #ifdef CONFIG_MIPS_MT_SMTC
+ /*
+ * We need to provide the SMTC vectored interrupt handler
+@@ -1153,11 +1146,11 @@
+ * Status.IM bit to be masked before going there.
+ */
+ extern char except_vec_vi_mori;
+- const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
++ const int mori_offset = &except_vec_vi_mori - vec_start;
+ #endif /* CONFIG_MIPS_MT_SMTC */
+- const int handler_len = &except_vec_vi_end - &except_vec_vi;
+- const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
+- const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
++ const int handler_len = &except_vec_vi_end - vec_start;
++ const int lui_offset = &except_vec_vi_lui - vec_start;
++ const int ori_offset = &except_vec_vi_ori - vec_start;
+
+ if (handler_len > VECTORSPACING) {
+ /*
+@@ -1167,7 +1160,7 @@
+ panic("VECTORSPACING too small");
+ }
+
+- memcpy(b, &except_vec_vi, handler_len);
++ memcpy(b, vec_start, handler_len);
+ #ifdef CONFIG_MIPS_MT_SMTC
+ BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
+
+@@ -1287,7 +1280,7 @@
+ int cp0_perfcount_irq;
+ EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
+
+-void __init per_cpu_trap_init(void)
++void __cpuinit per_cpu_trap_init(void)
+ {
+ unsigned int cpu = smp_processor_id();
+ unsigned int status_set = ST0_CU0;
+@@ -1404,11 +1397,12 @@
+ flush_icache_range(ebase + offset, ebase + offset + size);
+ }
+
+-static char panic_null_cerr[] __initdata =
++static char panic_null_cerr[] __cpuinitdata =
+ "Trying to set NULL cache error exception handler";
+
+ /* Install uncached CPU exception handler */
+-void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
++void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
++ unsigned long size)
+ {
+ #ifdef CONFIG_32BIT
+ unsigned long uncached_ebase = KSEG1ADDR(ebase);
+@@ -1437,6 +1431,10 @@
+ extern char except_vec3_generic, except_vec3_r4000;
+ extern char except_vec4;
+ unsigned long i;
++ int rollback;
++
++ check_wait();
++ rollback = (cpu_wait == r4k_wait);
+
+ if (cpu_has_veic || cpu_has_vint)
+ ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
+@@ -1496,7 +1494,7 @@
+ if (board_be_init)
+ board_be_init();
+
+- set_except_vector(0, handle_int);
++ set_except_vector(0, rollback ? rollback_handle_int : handle_int);
+ set_except_vector(1, handle_tlbm);
+ set_except_vector(2, handle_tlbl);
+ set_except_vector(3, handle_tlbs);
+diff -Nurd linux-2.6.24/arch/mips/kernel/unaligned.c mer-smartq-kernel/arch/mips/kernel/unaligned.c
+--- linux-2.6.24/arch/mips/kernel/unaligned.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/unaligned.c 2009-11-17 12:13:29.000000000 +0100
+@@ -560,12 +560,12 @@
+ return -ENODEV;
+ d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
+ mips_debugfs_dir, &unaligned_instructions);
+- if (IS_ERR(d))
+- return PTR_ERR(d);
++ if (!d)
++ return -ENOMEM;
+ d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
+ mips_debugfs_dir, &unaligned_action);
+- if (IS_ERR(d))
+- return PTR_ERR(d);
++ if (!d)
++ return -ENOMEM;
+ return 0;
+ }
+ __initcall(debugfs_unaligned);
+diff -Nurd linux-2.6.24/arch/mips/kernel/vpe.c mer-smartq-kernel/arch/mips/kernel/vpe.c
+--- linux-2.6.24/arch/mips/kernel/vpe.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/kernel/vpe.c 2009-11-17 12:13:29.000000000 +0100
+@@ -263,13 +263,21 @@
+ /* Find some VPE program space */
+ static void *alloc_progmem(unsigned long len)
+ {
++ void *addr;
++
+ #ifdef CONFIG_MIPS_VPE_LOADER_TOM
+- /* this means you must tell linux to use less memory than you physically have */
+- return pfn_to_kaddr(max_pfn);
++ /*
++ * This means you must tell Linux to use less memory than you
++ * physically have, for example by passing a mem= boot argument.
++ */
++ addr = pfn_to_kaddr(max_pfn);
++ memset(addr, 0, len);
+ #else
+- // simple grab some mem for now
+- return kmalloc(len, GFP_KERNEL);
++ /* simple grab some mem for now */
++ addr = kzalloc(len, GFP_KERNEL);
+ #endif
++
++ return addr;
+ }
+
+ static void release_progmem(void *ptr)
+@@ -774,10 +782,15 @@
+ /* take system out of configuration state */
+ clear_c0_mvpcontrol(MVPCONTROL_VPC);
+
++ /*
++ * SMTC/SMVP kernels manage VPE enable independently,
++ * but uniprocessor kernels need to turn it on, even
++ * if that wasn't the pre-dvpe() state.
++ */
+ #ifdef CONFIG_SMP
+- evpe(EVPE_ENABLE);
+-#else
+ evpe(vpeflags);
++#else
++ evpe(EVPE_ENABLE);
+ #endif
+ emt(dmt_flag);
+ local_irq_restore(flags);
+@@ -885,9 +898,10 @@
+ }
+
+ v->load_addr = alloc_progmem(mod.core_size);
+- memset(v->load_addr, 0, mod.core_size);
++ if (!v->load_addr)
++ return -ENOMEM;
+
+- printk("VPE loader: loading to %p\n", v->load_addr);
++ pr_info("VPE loader: loading to %p\n", v->load_addr);
+
+ if (relocate) {
+ for (i = 0; i < hdr->e_shnum; i++) {
+@@ -939,12 +953,14 @@
+ struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
+
+ for (i = 0; i < hdr->e_phnum; i++) {
+- if (phdr->p_type != PT_LOAD)
+- continue;
+-
+- memcpy((void *)phdr->p_paddr, (char *)hdr + phdr->p_offset, phdr->p_filesz);
+- memset((void *)phdr->p_paddr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz);
+- phdr++;
++ if (phdr->p_type == PT_LOAD) {
++ memcpy((void *)phdr->p_paddr,
++ (char *)hdr + phdr->p_offset,
++ phdr->p_filesz);
++ memset((void *)phdr->p_paddr + phdr->p_filesz,
++ 0, phdr->p_memsz - phdr->p_filesz);
++ }
++ phdr++;
+ }
+
+ for (i = 0; i < hdr->e_shnum; i++) {
+@@ -1113,7 +1129,7 @@
+
+ /* It's good to be able to run the SP and if it chokes have a look at
+ the /dev/rt?. But if we reset the pointer to the shared struct we
+- loose what has happened. So perhaps if garbage is sent to the vpe
++ lose what has happened. So perhaps if garbage is sent to the vpe
+ device, use it as a trigger for the reset. Hopefully a nice
+ executable will be along shortly. */
+ if (ret < 0)
+diff -Nurd linux-2.6.24/arch/mips/lasat/interrupt.c mer-smartq-kernel/arch/mips/lasat/interrupt.c
+--- linux-2.6.24/arch/mips/lasat/interrupt.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/lasat/interrupt.c 2009-11-17 12:13:29.000000000 +0100
+@@ -34,11 +34,13 @@
+
+ void disable_lasat_irq(unsigned int irq_nr)
+ {
++ irq_nr -= LASAT_IRQ_BASE;
+ *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
+ }
+
+ void enable_lasat_irq(unsigned int irq_nr)
+ {
++ irq_nr -= LASAT_IRQ_BASE;
+ *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
+ }
+
+diff -Nurd linux-2.6.24/arch/mips/lasat/lasat_board.c mer-smartq-kernel/arch/mips/lasat/lasat_board.c
+--- linux-2.6.24/arch/mips/lasat/lasat_board.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/lasat/lasat_board.c 2009-11-17 12:13:29.000000000 +0100
+@@ -23,18 +23,19 @@
+ #include <linux/kernel.h>
+ #include <linux/string.h>
+ #include <linux/ctype.h>
++#include <linux/mutex.h>
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
+ #include "at93c.h"
+ /* New model description table */
+ #include "lasat_models.h"
+
++static DEFINE_MUTEX(lasat_eeprom_mutex);
++
+ #define EEPROM_CRC(data, len) (~crc32(~0, data, len))
+
+ struct lasat_info lasat_board_info;
+
+-void update_bcastaddr(void);
+-
+ int EEPROMRead(unsigned int pos, unsigned char *data, int len)
+ {
+ int i;
+@@ -258,10 +259,6 @@
+ sprintf(lasat_board_info.li_typestr, "%d", 10 * c);
+ }
+
+-#if defined(CONFIG_INET) && defined(CONFIG_SYSCTL)
+- update_bcastaddr();
+-#endif
+-
+ return 0;
+ }
+
+@@ -269,6 +266,8 @@
+ {
+ unsigned long crc;
+
++ mutex_lock(&lasat_eeprom_mutex);
++
+ /* Generate the CRC */
+ crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info),
+ sizeof(struct lasat_eeprom_struct) - 4);
+@@ -277,4 +276,6 @@
+ /* Write the EEPROM info */
+ EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
+ sizeof(struct lasat_eeprom_struct));
++
++ mutex_unlock(&lasat_eeprom_mutex);
+ }
+diff -Nurd linux-2.6.24/arch/mips/lasat/sysctl.c mer-smartq-kernel/arch/mips/lasat/sysctl.c
+--- linux-2.6.24/arch/mips/lasat/sysctl.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/lasat/sysctl.c 2009-11-17 12:13:29.000000000 +0100
+@@ -29,15 +29,13 @@
+ #include <linux/string.h>
+ #include <linux/net.h>
+ #include <linux/inet.h>
+-#include <linux/mutex.h>
+ #include <linux/uaccess.h>
+
+ #include <asm/time.h>
+
+-#include "sysctl.h"
++#ifdef CONFIG_DS1603
+ #include "ds1603.h"
+-
+-static DEFINE_MUTEX(lasat_info_mutex);
++#endif
+
+ /* Strategy function to write EEPROM after changing string entry */
+ int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
+@@ -46,18 +44,15 @@
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ r = sysctl_string(table, name,
+ nlen, oldval, oldlenp, newval, newlen);
+- if (r < 0) {
+- mutex_unlock(&lasat_info_mutex);
++ if (r < 0)
+ return r;
+- }
++
+ if (newval && newlen)
+ lasat_write_eeprom_info();
+- mutex_unlock(&lasat_info_mutex);
+
+- return 1;
++ return 0;
+ }
+
+
+@@ -67,14 +62,11 @@
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ r = proc_dostring(table, write, filp, buffer, lenp, ppos);
+- if ((!write) || r) {
+- mutex_unlock(&lasat_info_mutex);
++ if ((!write) || r)
+ return r;
+- }
++
+ lasat_write_eeprom_info();
+- mutex_unlock(&lasat_info_mutex);
+
+ return 0;
+ }
+@@ -85,28 +77,24 @@
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
+- if ((!write) || r) {
+- mutex_unlock(&lasat_info_mutex);
++ if ((!write) || r)
+ return r;
+- }
++
+ lasat_write_eeprom_info();
+- mutex_unlock(&lasat_info_mutex);
+
+ return 0;
+ }
+
++#ifdef CONFIG_DS1603
+ static int rtctmp;
+
+-#ifdef CONFIG_DS1603
+ /* proc function to read/write RealTime Clock */
+ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
+ void *buffer, size_t *lenp, loff_t *ppos)
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ if (!write) {
+ rtctmp = read_persistent_clock();
+ /* check for time < 0 and set to 0 */
+@@ -114,12 +102,11 @@
+ rtctmp = 0;
+ }
+ r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
+- if ((!write) || r) {
+- mutex_unlock(&lasat_info_mutex);
++ if (r)
+ return r;
+- }
+- rtc_mips_set_mmss(rtctmp);
+- mutex_unlock(&lasat_info_mutex);
++
++ if (write)
++ rtc_mips_set_mmss(rtctmp);
+
+ return 0;
+ }
+@@ -132,17 +119,14 @@
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
+- if (r < 0) {
+- mutex_unlock(&lasat_info_mutex);
++ if (r < 0)
+ return r;
+- }
++
+ if (newval && newlen)
+ lasat_write_eeprom_info();
+- mutex_unlock(&lasat_info_mutex);
+
+- return 1;
++ return 0;
+ }
+
+ #ifdef CONFIG_DS1603
+@@ -153,50 +137,27 @@
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ rtctmp = read_persistent_clock();
+ if (rtctmp < 0)
+ rtctmp = 0;
+ r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
+- if (r < 0) {
+- mutex_unlock(&lasat_info_mutex);
++ if (r < 0)
+ return r;
+- }
+ if (newval && newlen)
+ rtc_mips_set_mmss(rtctmp);
+- mutex_unlock(&lasat_info_mutex);
+
+- return 1;
++ return r;
+ }
+ #endif
+
+ #ifdef CONFIG_INET
+-static char lasat_bcastaddr[16];
+-
+-void update_bcastaddr(void)
+-{
+- unsigned int ip;
+-
+- ip = (lasat_board_info.li_eeprom_info.ipaddr &
+- lasat_board_info.li_eeprom_info.netmask) |
+- ~lasat_board_info.li_eeprom_info.netmask;
+-
+- sprintf(lasat_bcastaddr, "%d.%d.%d.%d",
+- (ip) & 0xff,
+- (ip >> 8) & 0xff,
+- (ip >> 16) & 0xff,
+- (ip >> 24) & 0xff);
+-}
+-
+-static char proc_lasat_ipbuf[32];
+-
+-/* Parsing of IP address */
+ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
+ void *buffer, size_t *lenp, loff_t *ppos)
+ {
+ unsigned int ip;
+ char *p, c;
+ int len;
++ char ipbuf[32];
+
+ if (!table->data || !table->maxlen || !*lenp ||
+ (*ppos && !write)) {
+@@ -204,117 +165,88 @@
+ return 0;
+ }
+
+- mutex_lock(&lasat_info_mutex);
+ if (write) {
+ len = 0;
+ p = buffer;
+ while (len < *lenp) {
+- if (get_user(c, p++)) {
+- mutex_unlock(&lasat_info_mutex);
++ if (get_user(c, p++))
+ return -EFAULT;
+- }
+ if (c == 0 || c == '\n')
+ break;
+ len++;
+ }
+- if (len >= sizeof(proc_lasat_ipbuf)-1)
+- len = sizeof(proc_lasat_ipbuf) - 1;
+- if (copy_from_user(proc_lasat_ipbuf, buffer, len)) {
+- mutex_unlock(&lasat_info_mutex);
++ if (len >= sizeof(ipbuf)-1)
++ len = sizeof(ipbuf) - 1;
++ if (copy_from_user(ipbuf, buffer, len))
+ return -EFAULT;
+- }
+- proc_lasat_ipbuf[len] = 0;
++ ipbuf[len] = 0;
+ *ppos += *lenp;
+ /* Now see if we can convert it to a valid IP */
+- ip = in_aton(proc_lasat_ipbuf);
++ ip = in_aton(ipbuf);
+ *(unsigned int *)(table->data) = ip;
+ lasat_write_eeprom_info();
+ } else {
+ ip = *(unsigned int *)(table->data);
+- sprintf(proc_lasat_ipbuf, "%d.%d.%d.%d",
++ sprintf(ipbuf, "%d.%d.%d.%d",
+ (ip) & 0xff,
+ (ip >> 8) & 0xff,
+ (ip >> 16) & 0xff,
+ (ip >> 24) & 0xff);
+- len = strlen(proc_lasat_ipbuf);
++ len = strlen(ipbuf);
+ if (len > *lenp)
+ len = *lenp;
+ if (len)
+- if (copy_to_user(buffer, proc_lasat_ipbuf, len)) {
+- mutex_unlock(&lasat_info_mutex);
++ if (copy_to_user(buffer, ipbuf, len))
+ return -EFAULT;
+- }
+ if (len < *lenp) {
+- if (put_user('\n', ((char *) buffer) + len)) {
+- mutex_unlock(&lasat_info_mutex);
++ if (put_user('\n', ((char *) buffer) + len))
+ return -EFAULT;
+- }
+ len++;
+ }
+ *lenp = len;
+ *ppos += len;
+ }
+- update_bcastaddr();
+- mutex_unlock(&lasat_info_mutex);
+
+ return 0;
+ }
+-#endif /* defined(CONFIG_INET) */
++#endif
+
+-static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
++static int sysctl_lasat_prid(ctl_table *table, int *name, int nlen,
+ void *oldval, size_t *oldlenp,
+ void *newval, size_t newlen)
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
+- if (r < 0) {
+- mutex_unlock(&lasat_info_mutex);
++ if (r < 0)
+ return r;
+- }
+-
+ if (newval && newlen) {
+- if (name && *name == LASAT_PRID)
+- lasat_board_info.li_eeprom_info.prid = *(int *)newval;
+-
++ lasat_board_info.li_eeprom_info.prid = *(int *)newval;
+ lasat_write_eeprom_info();
+ lasat_init_board_info();
+ }
+- mutex_unlock(&lasat_info_mutex);
+-
+ return 0;
+ }
+
+-int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
++int proc_lasat_prid(ctl_table *table, int write, struct file *filp,
+ void *buffer, size_t *lenp, loff_t *ppos)
+ {
+ int r;
+
+- mutex_lock(&lasat_info_mutex);
+ r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
+- if ((!write) || r) {
+- mutex_unlock(&lasat_info_mutex);
++ if (r < 0)
+ return r;
++ if (write) {
++ lasat_board_info.li_eeprom_info.prid =
++ lasat_board_info.li_prid;
++ lasat_write_eeprom_info();
++ lasat_init_board_info();
+ }
+- if (filp && filp->f_path.dentry) {
+- if (!strcmp(filp->f_path.dentry->d_name.name, "prid"))
+- lasat_board_info.li_eeprom_info.prid =
+- lasat_board_info.li_prid;
+- if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess"))
+- lasat_board_info.li_eeprom_info.debugaccess =
+- lasat_board_info.li_debugaccess;
+- }
+- lasat_write_eeprom_info();
+- mutex_unlock(&lasat_info_mutex);
+-
+ return 0;
+ }
+
+ extern int lasat_boot_to_service;
+
+-#ifdef CONFIG_SYSCTL
+-
+ static ctl_table lasat_table[] = {
+ {
+ .ctl_name = CTL_UNNUMBERED,
+@@ -349,8 +281,8 @@
+ .data = &lasat_board_info.li_prid,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+- .proc_handler = &proc_lasat_eeprom_value,
+- .strategy = &sysctl_lasat_eeprom_value
++ .proc_handler = &proc_lasat_prid,
++ .strategy = &sysctl_lasat_prid
+ },
+ #ifdef CONFIG_INET
+ {
+@@ -363,7 +295,7 @@
+ .strategy = &sysctl_lasat_intvec
+ },
+ {
+- .ctl_name = LASAT_NETMASK,
++ .ctl_name = CTL_UNNUMBERED,
+ .procname = "netmask",
+ .data = &lasat_board_info.li_eeprom_info.netmask,
+ .maxlen = sizeof(int),
+@@ -371,15 +303,6 @@
+ .proc_handler = &proc_lasat_ip,
+ .strategy = &sysctl_lasat_intvec
+ },
+- {
+- .ctl_name = CTL_UNNUMBERED,
+- .procname = "bcastaddr",
+- .data = &lasat_bcastaddr,
+- .maxlen = sizeof(lasat_bcastaddr),
+- .mode = 0600,
+- .proc_handler = &proc_dostring,
+- .strategy = &sysctl_string
+- },
+ #endif
+ {
+ .ctl_name = CTL_UNNUMBERED,
+@@ -417,7 +340,7 @@
+ .data = &lasat_board_info.li_namestr,
+ .maxlen = sizeof(lasat_board_info.li_namestr),
+ .mode = 0444,
+- .proc_handler = &proc_dostring,
++ .proc_handler = &proc_dostring,
+ .strategy = &sysctl_string
+ },
+ {
+@@ -448,9 +371,12 @@
+
+ lasat_table_header =
+ register_sysctl_table(lasat_root_table);
++ if (!lasat_table_header) {
++ printk(KERN_ERR "Unable to register LASAT sysctl\n");
++ return -ENOMEM;
++ }
+
+ return 0;
+ }
+
+ __initcall(lasat_register_sysctl);
+-#endif /* CONFIG_SYSCTL */
+diff -Nurd linux-2.6.24/arch/mips/lasat/sysctl.h mer-smartq-kernel/arch/mips/lasat/sysctl.h
+--- linux-2.6.24/arch/mips/lasat/sysctl.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/lasat/sysctl.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,24 +0,0 @@
+-/*
+- * LASAT sysctl values
+- */
+-
+-#ifndef _LASAT_SYSCTL_H
+-#define _LASAT_SYSCTL_H
+-
+-/* /proc/sys/lasat */
+-enum {
+- LASAT_CPU_HZ = 1,
+- LASAT_BUS_HZ,
+- LASAT_MODEL,
+- LASAT_PRID,
+- LASAT_IPADDR,
+- LASAT_NETMASK,
+- LASAT_BCAST,
+- LASAT_PASSWORD,
+- LASAT_SBOOT,
+- LASAT_RTC,
+- LASAT_NAMESTR,
+- LASAT_TYPESTR,
+-};
+-
+-#endif /* _LASAT_SYSCTL_H */
+diff -Nurd linux-2.6.24/arch/mips/lib/csum_partial.S mer-smartq-kernel/arch/mips/lib/csum_partial.S
+--- linux-2.6.24/arch/mips/lib/csum_partial.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/lib/csum_partial.S 2009-11-17 12:13:29.000000000 +0100
+@@ -38,12 +38,14 @@
+ #ifdef USE_DOUBLE
+
+ #define LOAD ld
++#define LOAD32 lwu
+ #define ADD daddu
+ #define NBYTES 8
+
+ #else
+
+ #define LOAD lw
++#define LOAD32 lw
+ #define ADD addu
+ #define NBYTES 4
+
+@@ -56,6 +58,14 @@
+ sltu v1, sum, reg; \
+ ADD sum, v1
+
++#define ADDC32(sum,reg) \
++ .set push; \
++ .set noat; \
++ addu sum, reg; \
++ sltu v1, sum, reg; \
++ addu sum, v1; \
++ .set pop
++
+ #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
+ LOAD _t0, (offset + UNIT(0))(src); \
+ LOAD _t1, (offset + UNIT(1))(src); \
+@@ -128,7 +138,7 @@
+ beqz t8, qword_align
+ andi t8, src, 0x8
+
+- lw t0, 0x00(src)
++ LOAD32 t0, 0x00(src)
+ LONG_SUBU a1, a1, 0x4
+ ADDC(sum, t0)
+ PTR_ADDU src, src, 0x4
+@@ -205,7 +215,7 @@
+ LONG_SRL t8, t8, 0x2
+
+ end_words:
+- lw t0, (src)
++ LOAD32 t0, (src)
+ LONG_SUBU t8, t8, 0x1
+ ADDC(sum, t0)
+ bnez t8, end_words
+@@ -222,6 +232,9 @@
+ /* Still a full word to go */
+ ulw t1, (src)
+ PTR_ADDIU src, 4
++#ifdef USE_DOUBLE
++ dsll t1, t1, 32 /* clear lower 32bit */
++#endif
+ ADDC(sum, t1)
+
+ 1: move t1, zero
+@@ -269,7 +282,7 @@
+ 1:
+ .set reorder
+ /* Add the passed partial csum. */
+- ADDC(sum, a2)
++ ADDC32(sum, a2)
+ jr ra
+ .set noreorder
+ END(csum_partial)
+@@ -653,7 +666,7 @@
+ andi sum, 0xffff
+ 1:
+ .set reorder
+- ADDC(sum, psum)
++ ADDC32(sum, psum)
+ jr ra
+ .set noreorder
+
+diff -Nurd linux-2.6.24/arch/mips/lib/ucmpdi2.c mer-smartq-kernel/arch/mips/lib/ucmpdi2.c
+--- linux-2.6.24/arch/mips/lib/ucmpdi2.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/lib/ucmpdi2.c 2009-11-17 12:13:29.000000000 +0100
+@@ -17,3 +17,5 @@
+ return 2;
+ return 1;
+ }
++
++EXPORT_SYMBOL(__ucmpdi2);
+diff -Nurd linux-2.6.24/arch/mips/lib/uncached.c mer-smartq-kernel/arch/mips/lib/uncached.c
+--- linux-2.6.24/arch/mips/lib/uncached.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/lib/uncached.c 2009-11-17 12:13:29.000000000 +0100
+@@ -36,7 +36,7 @@
+ * values, so we can avoid sharing the same stack area between a cached
+ * and the uncached mode.
+ */
+-unsigned long __init run_uncached(void *func)
++unsigned long __cpuinit run_uncached(void *func)
+ {
+ register long sp __asm__("$sp");
+ register long ret __asm__("$2");
+diff -Nurd linux-2.6.24/arch/mips/Makefile mer-smartq-kernel/arch/mips/Makefile
+--- linux-2.6.24/arch/mips/Makefile 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/Makefile 2009-11-17 12:13:28.000000000 +0100
+@@ -548,7 +548,11 @@
+ #
+ core-$(CONFIG_SNI_RM) += arch/mips/sni/
+ cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm
++ifdef CONFIG_CPU_LITTLE_ENDIAN
+ load-$(CONFIG_SNI_RM) += 0xffffffff80600000
++else
++load-$(CONFIG_SNI_RM) += 0xffffffff80030000
++endif
+ all-$(CONFIG_SNI_RM) := vmlinux.ecoff
+
+ #
+diff -Nurd linux-2.6.24/arch/mips/math-emu/cp1emu.c mer-smartq-kernel/arch/mips/math-emu/cp1emu.c
+--- linux-2.6.24/arch/mips/math-emu/cp1emu.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/math-emu/cp1emu.c 2009-11-17 12:13:29.000000000 +0100
+@@ -1299,12 +1299,12 @@
+ if (!mips_debugfs_dir)
+ return -ENODEV;
+ dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
+- if (IS_ERR(dir))
+- return PTR_ERR(dir);
++ if (!dir)
++ return -ENOMEM;
+ for (i = 0; i < ARRAY_SIZE(vars); i++) {
+ d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
+- if (IS_ERR(d))
+- return PTR_ERR(d);
++ if (!d)
++ return -ENOMEM;
+ }
+ return 0;
+ }
+diff -Nurd linux-2.6.24/arch/mips/mips-boards/generic/time.c mer-smartq-kernel/arch/mips/mips-boards/generic/time.c
+--- linux-2.6.24/arch/mips/mips-boards/generic/time.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mips-boards/generic/time.c 2009-11-17 12:13:29.000000000 +0100
+@@ -146,7 +146,7 @@
+ }
+ }
+
+-unsigned int __init get_c0_compare_int(void)
++unsigned int __cpuinit get_c0_compare_int(void)
+ {
+ #ifdef MSC01E_INT_BASE
+ if (cpu_has_veic) {
+diff -Nurd linux-2.6.24/arch/mips/mips-boards/malta/Makefile mer-smartq-kernel/arch/mips/mips-boards/malta/Makefile
+--- linux-2.6.24/arch/mips/mips-boards/malta/Makefile 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mips-boards/malta/Makefile 2009-11-17 12:13:29.000000000 +0100
+@@ -19,9 +19,8 @@
+ # under Linux.
+ #
+
+-obj-y := malta_int.o malta_platform.o malta_setup.o
++obj-y := malta_int.o malta_mtd.o malta_platform.o malta_setup.o
+
+-obj-$(CONFIG_MTD) += malta_mtd.o
+ obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o
+
+ EXTRA_CFLAGS += -Werror
+diff -Nurd linux-2.6.24/arch/mips/mips-boards/malta/malta_smtc.c mer-smartq-kernel/arch/mips/mips-boards/malta/malta_smtc.c
+--- linux-2.6.24/arch/mips/mips-boards/malta/malta_smtc.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mips-boards/malta/malta_smtc.c 2009-11-17 12:13:29.000000000 +0100
+@@ -62,14 +62,20 @@
+
+ void __cpuinit plat_smp_setup(void)
+ {
+- if (read_c0_config3() & (1<<2))
+- mipsmt_build_cpu_map(0);
++ if (read_c0_config3() & (1<<2)) {
++ /*
++ * we won't get the definitive value until
++ * we've run smtc_prepare_cpus later, but
++ * we would appear to need an upper bound now.
++ */
++ smtc_build_cpu_map(0);
++ }
+ }
+
+ void __init plat_prepare_cpus(unsigned int max_cpus)
+ {
+ if (read_c0_config3() & (1<<2))
+- mipsmt_prepare_cpus();
++ smtc_prepare_cpus(max_cpus);
+ }
+
+ /*
+diff -Nurd linux-2.6.24/arch/mips/mipssim/sim_time.c mer-smartq-kernel/arch/mips/mipssim/sim_time.c
+--- linux-2.6.24/arch/mips/mipssim/sim_time.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mipssim/sim_time.c 2009-11-17 12:13:29.000000000 +0100
+@@ -83,7 +83,7 @@
+ }
+
+
+-unsigned __init get_c0_compare_int(void)
++unsigned __cpuinit get_c0_compare_int(void)
+ {
+ #ifdef MSC01E_INT_BASE
+ if (cpu_has_veic) {
+diff -Nurd linux-2.6.24/arch/mips/mm/cache.c mer-smartq-kernel/arch/mips/mm/cache.c
+--- linux-2.6.24/arch/mips/mm/cache.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/cache.c 2009-11-17 12:13:29.000000000 +0100
+@@ -30,6 +30,9 @@
+ unsigned long pfn);
+ void (*flush_icache_range)(unsigned long start, unsigned long end);
+
++void (*__flush_cache_vmap)(void);
++void (*__flush_cache_vunmap)(void);
++
+ /* MIPS specific cache operations */
+ void (*flush_cache_sigtramp)(unsigned long addr);
+ void (*local_flush_data_cache_page)(void * addr);
+@@ -92,12 +95,17 @@
+
+ void __flush_anon_page(struct page *page, unsigned long vmaddr)
+ {
+- if (pages_do_alias((unsigned long)page_address(page), vmaddr)) {
+- void *kaddr;
++ unsigned long addr = (unsigned long) page_address(page);
+
+- kaddr = kmap_coherent(page, vmaddr);
+- flush_data_cache_page((unsigned long)kaddr);
+- kunmap_coherent();
++ if (pages_do_alias(addr, vmaddr)) {
++ if (page_mapped(page) && !Page_dcache_dirty(page)) {
++ void *kaddr;
++
++ kaddr = kmap_coherent(page, vmaddr);
++ flush_data_cache_page((unsigned long)kaddr);
++ kunmap_coherent();
++ } else
++ flush_data_cache_page(addr);
+ }
+ }
+
+@@ -122,9 +130,10 @@
+ }
+ }
+
+-static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
++static char cache_panic[] __cpuinitdata =
++ "Yeee, unsupported cache architecture.";
+
+-void __init cpu_cache_init(void)
++void __cpuinit cpu_cache_init(void)
+ {
+ if (cpu_has_3k_cache) {
+ extern void __weak r3k_cache_init(void);
+diff -Nurd linux-2.6.24/arch/mips/mm/cex-sb1.S mer-smartq-kernel/arch/mips/mm/cex-sb1.S
+--- linux-2.6.24/arch/mips/mm/cex-sb1.S 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/cex-sb1.S 2009-11-17 12:13:29.000000000 +0100
+@@ -34,8 +34,6 @@
+ * is changed.
+ */
+
+- __INIT
+-
+ .set mips64
+ .set noreorder
+ .set noat
+@@ -51,6 +49,10 @@
+ * (0x170-0x17f) are used to preserve k0, k1, and ra.
+ */
+
++#ifndef CONFIG_HOTPLUG_CPU
++ __INIT /* no __CPUINIT; it's a 2.6.25 thing */
++#endif
++
+ LEAF(except_vec2_sb1)
+ /*
+ * If this error is recoverable, we need to exit the handler
+@@ -142,7 +144,9 @@
+
+ END(except_vec2_sb1)
+
++#ifndef CONFIG_HOTPLUG_CPU
+ __FINIT
++#endif
+
+ LEAF(handle_vec2_sb1)
+ mfc0 k0,CP0_CONFIG
+diff -Nurd linux-2.6.24/arch/mips/mm/c-r3k.c mer-smartq-kernel/arch/mips/mm/c-r3k.c
+--- linux-2.6.24/arch/mips/mm/c-r3k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/c-r3k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -26,7 +26,7 @@
+ static unsigned long icache_size, dcache_size; /* Size in bytes */
+ static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */
+
+-unsigned long __init r3k_cache_size(unsigned long ca_flags)
++unsigned long __cpuinit r3k_cache_size(unsigned long ca_flags)
+ {
+ unsigned long flags, status, dummy, size;
+ volatile unsigned long *p;
+@@ -61,7 +61,7 @@
+ return size * sizeof(*p);
+ }
+
+-unsigned long __init r3k_cache_lsize(unsigned long ca_flags)
++unsigned long __cpuinit r3k_cache_lsize(unsigned long ca_flags)
+ {
+ unsigned long flags, status, lsize, i;
+ volatile unsigned long *p;
+@@ -90,7 +90,7 @@
+ return lsize * sizeof(*p);
+ }
+
+-static void __init r3k_probe_cache(void)
++static void __cpuinit r3k_probe_cache(void)
+ {
+ dcache_size = r3k_cache_size(ST0_ISC);
+ if (dcache_size)
+@@ -307,7 +307,7 @@
+ r3k_flush_dcache_range(start, start + size);
+ }
+
+-void __init r3k_cache_init(void)
++void __cpuinit r3k_cache_init(void)
+ {
+ extern void build_clear_page(void);
+ extern void build_copy_page(void);
+diff -Nurd linux-2.6.24/arch/mips/mm/c-r4k.c mer-smartq-kernel/arch/mips/mm/c-r4k.c
+--- linux-2.6.24/arch/mips/mm/c-r4k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/c-r4k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -93,7 +93,7 @@
+ blast_dcache32_page(addr);
+ }
+
+-static void __init r4k_blast_dcache_page_setup(void)
++static void __cpuinit r4k_blast_dcache_page_setup(void)
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
+@@ -107,7 +107,7 @@
+
+ static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
+
+-static void __init r4k_blast_dcache_page_indexed_setup(void)
++static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
+@@ -121,7 +121,7 @@
+
+ static void (* r4k_blast_dcache)(void);
+
+-static void __init r4k_blast_dcache_setup(void)
++static void __cpuinit r4k_blast_dcache_setup(void)
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
+@@ -206,7 +206,7 @@
+
+ static void (* r4k_blast_icache_page)(unsigned long addr);
+
+-static void __init r4k_blast_icache_page_setup(void)
++static void __cpuinit r4k_blast_icache_page_setup(void)
+ {
+ unsigned long ic_lsize = cpu_icache_line_size();
+
+@@ -223,7 +223,7 @@
+
+ static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
+
+-static void __init r4k_blast_icache_page_indexed_setup(void)
++static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
+ {
+ unsigned long ic_lsize = cpu_icache_line_size();
+
+@@ -247,7 +247,7 @@
+
+ static void (* r4k_blast_icache)(void);
+
+-static void __init r4k_blast_icache_setup(void)
++static void __cpuinit r4k_blast_icache_setup(void)
+ {
+ unsigned long ic_lsize = cpu_icache_line_size();
+
+@@ -268,7 +268,7 @@
+
+ static void (* r4k_blast_scache_page)(unsigned long addr);
+
+-static void __init r4k_blast_scache_page_setup(void)
++static void __cpuinit r4k_blast_scache_page_setup(void)
+ {
+ unsigned long sc_lsize = cpu_scache_line_size();
+
+@@ -286,7 +286,7 @@
+
+ static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
+
+-static void __init r4k_blast_scache_page_indexed_setup(void)
++static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
+ {
+ unsigned long sc_lsize = cpu_scache_line_size();
+
+@@ -304,7 +304,7 @@
+
+ static void (* r4k_blast_scache)(void);
+
+-static void __init r4k_blast_scache_setup(void)
++static void __cpuinit r4k_blast_scache_setup(void)
+ {
+ unsigned long sc_lsize = cpu_scache_line_size();
+
+@@ -361,23 +361,36 @@
+ #endif
+ }
+
++static void r4k__flush_cache_vmap(void)
++{
++ r4k_blast_dcache();
++}
++
++static void r4k__flush_cache_vunmap(void)
++{
++ r4k_blast_dcache();
++}
++
+ static inline void local_r4k_flush_cache_range(void * args)
+ {
+ struct vm_area_struct *vma = args;
++ int exec = vma->vm_flags & VM_EXEC;
+
+ if (!(has_valid_asid(vma->vm_mm)))
+ return;
+
+ r4k_blast_dcache();
++ if (exec)
++ r4k_blast_icache();
+ }
+
+ static void r4k_flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+ {
+- if (!cpu_has_dc_aliases)
+- return;
++ int exec = vma->vm_flags & VM_EXEC;
+
+- r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
++ if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
++ r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
+ }
+
+ static inline void local_r4k_flush_cache_mm(void * args)
+@@ -426,6 +439,7 @@
+ struct page *page = pfn_to_page(fcp_args->pfn);
+ int exec = vma->vm_flags & VM_EXEC;
+ struct mm_struct *mm = vma->vm_mm;
++ int map_coherent = 0;
+ pgd_t *pgdp;
+ pud_t *pudp;
+ pmd_t *pmdp;
+@@ -459,7 +473,9 @@
+ * Use kmap_coherent or kmap_atomic to do flushes for
+ * another ASID than the current one.
+ */
+- if (cpu_has_dc_aliases)
++ map_coherent = (cpu_has_dc_aliases &&
++ page_mapped(page) && !Page_dcache_dirty(page));
++ if (map_coherent)
+ vaddr = kmap_coherent(page, addr);
+ else
+ vaddr = kmap_atomic(page, KM_USER0);
+@@ -482,7 +498,7 @@
+ }
+
+ if (vaddr) {
+- if (cpu_has_dc_aliases)
++ if (map_coherent)
+ kunmap_coherent();
+ else
+ kunmap_atomic(vaddr, KM_USER0);
+@@ -697,11 +713,11 @@
+ }
+ }
+
+-static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
++static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
+ "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+ };
+
+-static void __init probe_pcache(void)
++static void __cpuinit probe_pcache(void)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+ unsigned int config = read_c0_config();
+@@ -1020,7 +1036,7 @@
+ * executes in KSEG1 space or else you will crash and burn badly. You have
+ * been warned.
+ */
+-static int __init probe_scache(void)
++static int __cpuinit probe_scache(void)
+ {
+ unsigned long flags, addr, begin, end, pow2;
+ unsigned int config = read_c0_config();
+@@ -1099,7 +1115,7 @@
+ extern int rm7k_sc_init(void);
+ extern int mips_sc_init(void);
+
+-static void __init setup_scache(void)
++static void __cpuinit setup_scache(void)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+ unsigned int config = read_c0_config();
+@@ -1210,7 +1226,7 @@
+ }
+ }
+
+-static void __init coherency_setup(void)
++static void __cpuinit coherency_setup(void)
+ {
+ change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
+
+@@ -1242,7 +1258,7 @@
+ }
+ }
+
+-void __init r4k_cache_init(void)
++void __cpuinit r4k_cache_init(void)
+ {
+ extern void build_clear_page(void);
+ extern void build_copy_page(void);
+@@ -1285,6 +1301,10 @@
+ PAGE_SIZE - 1);
+ else
+ shm_align_mask = PAGE_SIZE-1;
++
++ __flush_cache_vmap = r4k__flush_cache_vmap;
++ __flush_cache_vunmap = r4k__flush_cache_vunmap;
++
+ flush_cache_all = cache_noop;
+ __flush_cache_all = r4k___flush_cache_all;
+ flush_cache_mm = r4k_flush_cache_mm;
+diff -Nurd linux-2.6.24/arch/mips/mm/c-tx39.c mer-smartq-kernel/arch/mips/mm/c-tx39.c
+--- linux-2.6.24/arch/mips/mm/c-tx39.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/c-tx39.c 2009-11-17 12:13:29.000000000 +0100
+@@ -122,6 +122,16 @@
+ local_irq_restore(flags);
+ }
+
++static void tx39__flush_cache_vmap(void)
++{
++ tx39_blast_dcache();
++}
++
++static void tx39__flush_cache_vunmap(void)
++{
++ tx39_blast_dcache();
++}
++
+ static inline void tx39_flush_cache_all(void)
+ {
+ if (!cpu_has_dc_aliases)
+@@ -329,7 +339,7 @@
+ }
+ }
+
+-void __init tx39_cache_init(void)
++void __cpuinit tx39_cache_init(void)
+ {
+ extern void build_clear_page(void);
+ extern void build_copy_page(void);
+@@ -344,6 +354,8 @@
+ switch (current_cpu_type()) {
+ case CPU_TX3912:
+ /* TX39/H core (writethru direct-map cache) */
++ __flush_cache_vmap = tx39__flush_cache_vmap;
++ __flush_cache_vunmap = tx39__flush_cache_vunmap;
+ flush_cache_all = tx39h_flush_icache_all;
+ __flush_cache_all = tx39h_flush_icache_all;
+ flush_cache_mm = (void *) tx39h_flush_icache_all;
+@@ -369,6 +381,9 @@
+ write_c0_wired(0); /* set 8 on reset... */
+ /* board-dependent init code may set WBON */
+
++ __flush_cache_vmap = tx39__flush_cache_vmap;
++ __flush_cache_vunmap = tx39__flush_cache_vunmap;
++
+ flush_cache_all = tx39_flush_cache_all;
+ __flush_cache_all = tx39___flush_cache_all;
+ flush_cache_mm = tx39_flush_cache_mm;
+diff -Nurd linux-2.6.24/arch/mips/mm/dma-default.c mer-smartq-kernel/arch/mips/mm/dma-default.c
+--- linux-2.6.24/arch/mips/mm/dma-default.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/dma-default.c 2009-11-17 12:13:29.000000000 +0100
+@@ -111,6 +111,7 @@
+ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
+ dma_addr_t dma_handle)
+ {
++ plat_unmap_dma_mem(dma_handle);
+ free_pages((unsigned long) vaddr, get_order(size));
+ }
+
+@@ -121,6 +122,8 @@
+ {
+ unsigned long addr = (unsigned long) vaddr;
+
++ plat_unmap_dma_mem(dma_handle);
++
+ if (!plat_device_is_coherent(dev))
+ addr = CAC_ADDR(addr);
+
+@@ -324,7 +327,6 @@
+ if (cpu_is_noncoherent_r10000(dev))
+ __dma_sync((unsigned long)page_address(sg_page(sg)),
+ sg->length, direction);
+- plat_unmap_dma_mem(sg->dma_address);
+ }
+ }
+
+@@ -342,7 +344,6 @@
+ if (!plat_device_is_coherent(dev))
+ __dma_sync((unsigned long)page_address(sg_page(sg)),
+ sg->length, direction);
+- plat_unmap_dma_mem(sg->dma_address);
+ }
+ }
+
+diff -Nurd linux-2.6.24/arch/mips/mm/init.c mer-smartq-kernel/arch/mips/mm/init.c
+--- linux-2.6.24/arch/mips/mm/init.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/init.c 2009-11-17 12:13:29.000000000 +0100
+@@ -211,7 +211,8 @@
+ void *vfrom, *vto;
+
+ vto = kmap_atomic(to, KM_USER1);
+- if (cpu_has_dc_aliases && page_mapped(from)) {
++ if (cpu_has_dc_aliases &&
++ page_mapped(from) && !Page_dcache_dirty(from)) {
+ vfrom = kmap_coherent(from, vaddr);
+ copy_page(vto, vfrom);
+ kunmap_coherent();
+@@ -234,7 +235,8 @@
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases && page_mapped(page)) {
++ if (cpu_has_dc_aliases &&
++ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(vto, src, len);
+ kunmap_coherent();
+@@ -253,7 +255,8 @@
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
+ {
+- if (cpu_has_dc_aliases && page_mapped(page)) {
++ if (cpu_has_dc_aliases &&
++ page_mapped(page) && !Page_dcache_dirty(page)) {
+ void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(dst, vfrom, len);
+ kunmap_coherent();
+diff -Nurd linux-2.6.24/arch/mips/mm/pg-r4k.c mer-smartq-kernel/arch/mips/mm/pg-r4k.c
+--- linux-2.6.24/arch/mips/mm/pg-r4k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/pg-r4k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -64,21 +64,21 @@
+ * with 64-bit kernels. The prefetch offsets have been experimentally tuned
+ * an Origin 200.
+ */
+-static int pref_offset_clear __initdata = 512;
+-static int pref_offset_copy __initdata = 256;
++static int pref_offset_clear __cpuinitdata = 512;
++static int pref_offset_copy __cpuinitdata = 256;
+
+-static unsigned int pref_src_mode __initdata;
+-static unsigned int pref_dst_mode __initdata;
++static unsigned int pref_src_mode __cpuinitdata;
++static unsigned int pref_dst_mode __cpuinitdata;
+
+-static int load_offset __initdata;
+-static int store_offset __initdata;
++static int load_offset __cpuinitdata;
++static int store_offset __cpuinitdata;
+
+-static unsigned int __initdata *dest, *epc;
++static unsigned int __cpuinitdata *dest, *epc;
+
+ static unsigned int instruction_pending;
+ static union mips_instruction delayed_mi;
+
+-static void __init emit_instruction(union mips_instruction mi)
++static void __cpuinit emit_instruction(union mips_instruction mi)
+ {
+ if (instruction_pending)
+ *epc++ = delayed_mi.word;
+@@ -220,7 +220,7 @@
+ emit_instruction(mi);
+ }
+
+-static void __init __build_store_reg(int reg)
++static void __cpuinit __build_store_reg(int reg)
+ {
+ union mips_instruction mi;
+ unsigned int width;
+@@ -343,7 +343,7 @@
+ flush_delay_slot_or_nop();
+ }
+
+-void __init build_clear_page(void)
++void __cpuinit build_clear_page(void)
+ {
+ unsigned int loop_start;
+ unsigned long off;
+@@ -446,7 +446,7 @@
+ pr_debug("\t.set pop\n");
+ }
+
+-void __init build_copy_page(void)
++void __cpuinit build_copy_page(void)
+ {
+ unsigned int loop_start;
+ unsigned long off;
+diff -Nurd linux-2.6.24/arch/mips/mm/pg-sb1.c mer-smartq-kernel/arch/mips/mm/pg-sb1.c
+--- linux-2.6.24/arch/mips/mm/pg-sb1.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/pg-sb1.c 2009-11-17 12:13:29.000000000 +0100
+@@ -216,7 +216,7 @@
+ int i;
+
+ for (i = 0; i < DM_NUM_CHANNELS; i++) {
+- const u64 base_val = CPHYSADDR(&page_descr[i]) |
++ const u64 base_val = CPHYSADDR((unsigned long)&page_descr[i]) |
+ V_DM_DSCR_BASE_RINGSZ(1);
+ void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
+
+@@ -228,11 +228,11 @@
+
+ void clear_page(void *page)
+ {
+- u64 to_phys = CPHYSADDR(page);
++ u64 to_phys = CPHYSADDR((unsigned long)page);
+ unsigned int cpu = smp_processor_id();
+
+ /* if the page is not in KSEG0, use old way */
+- if ((long)KSEGX(page) != (long)CKSEG0)
++ if ((long)KSEGX((unsigned long)page) != (long)CKSEG0)
+ return clear_page_cpu(page);
+
+ page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
+@@ -252,13 +252,13 @@
+
+ void copy_page(void *to, void *from)
+ {
+- u64 from_phys = CPHYSADDR(from);
+- u64 to_phys = CPHYSADDR(to);
++ u64 from_phys = CPHYSADDR((unsigned long)from);
++ u64 to_phys = CPHYSADDR((unsigned long)to);
+ unsigned int cpu = smp_processor_id();
+
+ /* if any page is not in KSEG0, use old way */
+- if ((long)KSEGX(to) != (long)CKSEG0
+- || (long)KSEGX(from) != (long)CKSEG0)
++ if ((long)KSEGX((unsigned long)to) != (long)CKSEG0
++ || (long)KSEGX((unsigned long)from) != (long)CKSEG0)
+ return copy_page_cpu(to, from);
+
+ page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
+@@ -293,10 +293,10 @@
+ EXPORT_SYMBOL(clear_page);
+ EXPORT_SYMBOL(copy_page);
+
+-void __init build_clear_page(void)
++void __cpuinit build_clear_page(void)
+ {
+ }
+
+-void __init build_copy_page(void)
++void __cpuinit build_copy_page(void)
+ {
+ }
+diff -Nurd linux-2.6.24/arch/mips/mm/sc-ip22.c mer-smartq-kernel/arch/mips/mm/sc-ip22.c
+--- linux-2.6.24/arch/mips/mm/sc-ip22.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/sc-ip22.c 2009-11-17 12:13:29.000000000 +0100
+@@ -168,7 +168,7 @@
+ .bc_inv = indy_sc_wback_invalidate
+ };
+
+-void __init indy_sc_init(void)
++void __cpuinit indy_sc_init(void)
+ {
+ if (indy_sc_probe()) {
+ indy_sc_enable();
+diff -Nurd linux-2.6.24/arch/mips/mm/sc-mips.c mer-smartq-kernel/arch/mips/mm/sc-mips.c
+--- linux-2.6.24/arch/mips/mm/sc-mips.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/sc-mips.c 2009-11-17 12:13:29.000000000 +0100
+@@ -100,7 +100,7 @@
+ return 1;
+ }
+
+-int __init mips_sc_init(void)
++int __cpuinit mips_sc_init(void)
+ {
+ int found = mips_sc_probe();
+ if (found) {
+@@ -109,4 +109,3 @@
+ }
+ return found;
+ }
+-
+diff -Nurd linux-2.6.24/arch/mips/mm/sc-r5k.c mer-smartq-kernel/arch/mips/mm/sc-r5k.c
+--- linux-2.6.24/arch/mips/mm/sc-r5k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/sc-r5k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -99,7 +99,7 @@
+ .bc_inv = r5k_dma_cache_inv_sc
+ };
+
+-void __init r5k_sc_init(void)
++void __cpuinit r5k_sc_init(void)
+ {
+ if (r5k_sc_probe()) {
+ r5k_sc_enable();
+diff -Nurd linux-2.6.24/arch/mips/mm/sc-rm7k.c mer-smartq-kernel/arch/mips/mm/sc-rm7k.c
+--- linux-2.6.24/arch/mips/mm/sc-rm7k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/sc-rm7k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -86,7 +86,7 @@
+ /*
+ * This function is executed in uncached address space.
+ */
+-static __init void __rm7k_sc_enable(void)
++static __cpuinit void __rm7k_sc_enable(void)
+ {
+ int i;
+
+@@ -107,7 +107,7 @@
+ }
+ }
+
+-static __init void rm7k_sc_enable(void)
++static __cpuinit void rm7k_sc_enable(void)
+ {
+ if (read_c0_config() & RM7K_CONF_SE)
+ return;
+@@ -128,7 +128,7 @@
+ .bc_inv = rm7k_sc_inv
+ };
+
+-void __init rm7k_sc_init(void)
++void __cpuinit rm7k_sc_init(void)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+ unsigned int config = read_c0_config();
+diff -Nurd linux-2.6.24/arch/mips/mm/tlbex.c mer-smartq-kernel/arch/mips/mm/tlbex.c
+--- linux-2.6.24/arch/mips/mm/tlbex.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/tlbex.c 2009-11-17 12:13:29.000000000 +0100
+@@ -66,7 +66,7 @@
+ * why; it's not an issue caused by the core RTL.
+ *
+ */
+-static __init int __attribute__((unused)) m4kc_tlbp_war(void)
++static __cpuinit int __attribute__((unused)) m4kc_tlbp_war(void)
+ {
+ return (current_cpu_data.processor_id & 0xffff00) ==
+ (PRID_COMP_MIPS | PRID_IMP_4KC);
+@@ -140,7 +140,7 @@
+ | (e) << RE_SH \
+ | (f) << FUNC_SH)
+
+-static __initdata struct insn insn_table[] = {
++static __cpuinitdata struct insn insn_table[] = {
+ { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
+ { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
+ { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
+@@ -193,7 +193,7 @@
+
+ #undef M
+
+-static __init u32 build_rs(u32 arg)
++static __cpuinit u32 build_rs(u32 arg)
+ {
+ if (arg & ~RS_MASK)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -201,7 +201,7 @@
+ return (arg & RS_MASK) << RS_SH;
+ }
+
+-static __init u32 build_rt(u32 arg)
++static __cpuinit u32 build_rt(u32 arg)
+ {
+ if (arg & ~RT_MASK)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -209,7 +209,7 @@
+ return (arg & RT_MASK) << RT_SH;
+ }
+
+-static __init u32 build_rd(u32 arg)
++static __cpuinit u32 build_rd(u32 arg)
+ {
+ if (arg & ~RD_MASK)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -217,7 +217,7 @@
+ return (arg & RD_MASK) << RD_SH;
+ }
+
+-static __init u32 build_re(u32 arg)
++static __cpuinit u32 build_re(u32 arg)
+ {
+ if (arg & ~RE_MASK)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -225,7 +225,7 @@
+ return (arg & RE_MASK) << RE_SH;
+ }
+
+-static __init u32 build_simm(s32 arg)
++static __cpuinit u32 build_simm(s32 arg)
+ {
+ if (arg > 0x7fff || arg < -0x8000)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -233,7 +233,7 @@
+ return arg & 0xffff;
+ }
+
+-static __init u32 build_uimm(u32 arg)
++static __cpuinit u32 build_uimm(u32 arg)
+ {
+ if (arg & ~IMM_MASK)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -241,7 +241,7 @@
+ return arg & IMM_MASK;
+ }
+
+-static __init u32 build_bimm(s32 arg)
++static __cpuinit u32 build_bimm(s32 arg)
+ {
+ if (arg > 0x1ffff || arg < -0x20000)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -252,7 +252,7 @@
+ return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
+ }
+
+-static __init u32 build_jimm(u32 arg)
++static __cpuinit u32 build_jimm(u32 arg)
+ {
+ if (arg & ~((JIMM_MASK) << 2))
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -260,7 +260,7 @@
+ return (arg >> 2) & JIMM_MASK;
+ }
+
+-static __init u32 build_func(u32 arg)
++static __cpuinit u32 build_func(u32 arg)
+ {
+ if (arg & ~FUNC_MASK)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -268,7 +268,7 @@
+ return arg & FUNC_MASK;
+ }
+
+-static __init u32 build_set(u32 arg)
++static __cpuinit u32 build_set(u32 arg)
+ {
+ if (arg & ~SET_MASK)
+ printk(KERN_WARNING "TLB synthesizer field overflow\n");
+@@ -280,7 +280,7 @@
+ * The order of opcode arguments is implicitly left to right,
+ * starting with RS and ending with FUNC or IMM.
+ */
+-static void __init build_insn(u32 **buf, enum opcode opc, ...)
++static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
+ {
+ struct insn *ip = NULL;
+ unsigned int i;
+@@ -315,69 +315,69 @@
+ }
+
+ #define I_u1u2u3(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ unsigned int b, unsigned int c) \
+ { \
+ build_insn(buf, insn##op, a, b, c); \
+ }
+
+ #define I_u2u1u3(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ unsigned int b, unsigned int c) \
+ { \
+ build_insn(buf, insn##op, b, a, c); \
+ }
+
+ #define I_u3u1u2(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ unsigned int b, unsigned int c) \
+ { \
+ build_insn(buf, insn##op, b, c, a); \
+ }
+
+ #define I_u1u2s3(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ unsigned int b, signed int c) \
+ { \
+ build_insn(buf, insn##op, a, b, c); \
+ }
+
+ #define I_u2s3u1(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ signed int b, unsigned int c) \
+ { \
+ build_insn(buf, insn##op, c, a, b); \
+ }
+
+ #define I_u2u1s3(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ unsigned int b, signed int c) \
+ { \
+ build_insn(buf, insn##op, b, a, c); \
+ }
+
+ #define I_u1u2(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ unsigned int b) \
+ { \
+ build_insn(buf, insn##op, a, b); \
+ }
+
+ #define I_u1s2(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a, \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a, \
+ signed int b) \
+ { \
+ build_insn(buf, insn##op, a, b); \
+ }
+
+ #define I_u1(op) \
+- static inline void __init i##op(u32 **buf, unsigned int a) \
++ static inline void __cpuinit i##op(u32 **buf, unsigned int a) \
+ { \
+ build_insn(buf, insn##op, a); \
+ }
+
+ #define I_0(op) \
+- static inline void __init i##op(u32 **buf) \
++ static inline void __cpuinit i##op(u32 **buf) \
+ { \
+ build_insn(buf, insn##op); \
+ }
+@@ -457,7 +457,7 @@
+ enum label_id lab;
+ };
+
+-static __init void build_label(struct label **lab, u32 *addr,
++static __cpuinit void build_label(struct label **lab, u32 *addr,
+ enum label_id l)
+ {
+ (*lab)->addr = addr;
+@@ -526,34 +526,34 @@
+ #define i_ehb(buf) i_sll(buf, 0, 0, 3)
+
+ #ifdef CONFIG_64BIT
+-static __init int __maybe_unused in_compat_space_p(long addr)
++static __cpuinit int __maybe_unused in_compat_space_p(long addr)
+ {
+ /* Is this address in 32bit compat space? */
+ return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
+ }
+
+-static __init int __maybe_unused rel_highest(long val)
++static __cpuinit int __maybe_unused rel_highest(long val)
+ {
+ return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
+ }
+
+-static __init int __maybe_unused rel_higher(long val)
++static __cpuinit int __maybe_unused rel_higher(long val)
+ {
+ return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
+ }
+ #endif
+
+-static __init int rel_hi(long val)
++static __cpuinit int rel_hi(long val)
+ {
+ return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
+ }
+
+-static __init int rel_lo(long val)
++static __cpuinit int rel_lo(long val)
+ {
+ return ((val & 0xffff) ^ 0x8000) - 0x8000;
+ }
+
+-static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
++static __cpuinit void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
+ {
+ #ifdef CONFIG_64BIT
+ if (!in_compat_space_p(addr)) {
+@@ -571,7 +571,7 @@
+ i_lui(buf, rs, rel_hi(addr));
+ }
+
+-static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs,
++static __cpuinit void __maybe_unused i_LA(u32 **buf, unsigned int rs,
+ long addr)
+ {
+ i_LA_mostly(buf, rs, addr);
+@@ -589,7 +589,7 @@
+ enum label_id lab;
+ };
+
+-static __init void r_mips_pc16(struct reloc **rel, u32 *addr,
++static __cpuinit void r_mips_pc16(struct reloc **rel, u32 *addr,
+ enum label_id l)
+ {
+ (*rel)->addr = addr;
+@@ -614,7 +614,7 @@
+ }
+ }
+
+-static __init void resolve_relocs(struct reloc *rel, struct label *lab)
++static __cpuinit void resolve_relocs(struct reloc *rel, struct label *lab)
+ {
+ struct label *l;
+
+@@ -624,7 +624,7 @@
+ __resolve_relocs(rel, l);
+ }
+
+-static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
++static __cpuinit void move_relocs(struct reloc *rel, u32 *first, u32 *end,
+ long off)
+ {
+ for (; rel->lab != label_invalid; rel++)
+@@ -632,7 +632,7 @@
+ rel->addr += off;
+ }
+
+-static __init void move_labels(struct label *lab, u32 *first, u32 *end,
++static __cpuinit void move_labels(struct label *lab, u32 *first, u32 *end,
+ long off)
+ {
+ for (; lab->lab != label_invalid; lab++)
+@@ -640,7 +640,7 @@
+ lab->addr += off;
+ }
+
+-static __init void copy_handler(struct reloc *rel, struct label *lab,
++static __cpuinit void copy_handler(struct reloc *rel, struct label *lab,
+ u32 *first, u32 *end, u32 *target)
+ {
+ long off = (long)(target - first);
+@@ -651,7 +651,7 @@
+ move_labels(lab, first, end, off);
+ }
+
+-static __init int __maybe_unused insn_has_bdelay(struct reloc *rel,
++static __cpuinit int __maybe_unused insn_has_bdelay(struct reloc *rel,
+ u32 *addr)
+ {
+ for (; rel->lab != label_invalid; rel++) {
+@@ -665,49 +665,49 @@
+ }
+
+ /* convenience functions for labeled branches */
+-static void __init __maybe_unused
++static void __cpuinit __maybe_unused
+ il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
+ {
+ r_mips_pc16(r, *p, l);
+ i_bltz(p, reg, 0);
+ }
+
+-static void __init __maybe_unused il_b(u32 **p, struct reloc **r,
++static void __cpuinit __maybe_unused il_b(u32 **p, struct reloc **r,
+ enum label_id l)
+ {
+ r_mips_pc16(r, *p, l);
+ i_b(p, 0);
+ }
+
+-static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg,
++static void __cpuinit il_beqz(u32 **p, struct reloc **r, unsigned int reg,
+ enum label_id l)
+ {
+ r_mips_pc16(r, *p, l);
+ i_beqz(p, reg, 0);
+ }
+
+-static void __init __maybe_unused
++static void __cpuinit __maybe_unused
+ il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
+ {
+ r_mips_pc16(r, *p, l);
+ i_beqzl(p, reg, 0);
+ }
+
+-static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg,
++static void __cpuinit il_bnez(u32 **p, struct reloc **r, unsigned int reg,
+ enum label_id l)
+ {
+ r_mips_pc16(r, *p, l);
+ i_bnez(p, reg, 0);
+ }
+
+-static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
++static void __cpuinit il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
+ enum label_id l)
+ {
+ r_mips_pc16(r, *p, l);
+ i_bgezl(p, reg, 0);
+ }
+
+-static void __init __maybe_unused
++static void __cpuinit __maybe_unused
+ il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
+ {
+ r_mips_pc16(r, *p, l);
+@@ -743,16 +743,16 @@
+ * We deliberately chose a buffer size of 128, so we won't scribble
+ * over anything important on overflow before we panic.
+ */
+-static __initdata u32 tlb_handler[128];
++static __cpuinitdata u32 tlb_handler[128];
+
+ /* simply assume worst case size for labels and relocs */
+-static __initdata struct label labels[128];
+-static __initdata struct reloc relocs[128];
++static __cpuinitdata struct label labels[128];
++static __cpuinitdata struct reloc relocs[128];
+
+ /*
+ * The R3000 TLB handler is simple.
+ */
+-static void __init build_r3000_tlb_refill_handler(void)
++static void __cpuinit build_r3000_tlb_refill_handler(void)
+ {
+ long pgdc = (long)pgd_current;
+ u32 *p;
+@@ -801,7 +801,7 @@
+ * other one.To keep things simple, we first assume linear space,
+ * then we relocate it to the final handler layout as needed.
+ */
+-static __initdata u32 final_handler[64];
++static __cpuinitdata u32 final_handler[64];
+
+ /*
+ * Hazards
+@@ -825,11 +825,12 @@
+ *
+ * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
+ */
+-static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
++static __cpuinit void __maybe_unused build_tlb_probe_entry(u32 **p)
+ {
+ switch (current_cpu_type()) {
+- /* Found by experiment: R4600 v2.0 needs this, too. */
++ /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
+ case CPU_R4600:
++ case CPU_R4700:
+ case CPU_R5000:
+ case CPU_R5000A:
+ case CPU_NEVADA:
+@@ -849,7 +850,7 @@
+ */
+ enum tlb_write_entry { tlb_random, tlb_indexed };
+
+-static __init void build_tlb_write_entry(u32 **p, struct label **l,
++static __cpuinit void build_tlb_write_entry(u32 **p, struct label **l,
+ struct reloc **r,
+ enum tlb_write_entry wmode)
+ {
+@@ -993,7 +994,7 @@
+ * TMP and PTR are scratch.
+ * TMP will be clobbered, PTR will hold the pmd entry.
+ */
+-static __init void
++static __cpuinit void
+ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
+ unsigned int tmp, unsigned int ptr)
+ {
+@@ -1054,7 +1055,7 @@
+ * BVADDR is the faulting address, PTR is scratch.
+ * PTR will hold the pgd for vmalloc.
+ */
+-static __init void
++static __cpuinit void
+ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
+ unsigned int bvaddr, unsigned int ptr)
+ {
+@@ -1118,7 +1119,7 @@
+ * TMP and PTR are scratch.
+ * TMP will be clobbered, PTR will hold the pgd entry.
+ */
+-static __init void __maybe_unused
++static __cpuinit void __maybe_unused
+ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
+ {
+ long pgdc = (long)pgd_current;
+@@ -1153,7 +1154,7 @@
+
+ #endif /* !CONFIG_64BIT */
+
+-static __init void build_adjust_context(u32 **p, unsigned int ctx)
++static __cpuinit void build_adjust_context(u32 **p, unsigned int ctx)
+ {
+ unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
+ unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
+@@ -1179,7 +1180,8 @@
+ i_andi(p, ctx, ctx, mask);
+ }
+
+-static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
++static __cpuinit void build_get_ptep(u32 **p, unsigned int tmp,
++ unsigned int ptr)
+ {
+ /*
+ * Bug workaround for the Nevada. It seems as if under certain
+@@ -1204,7 +1206,7 @@
+ i_ADDU(p, ptr, ptr, tmp); /* add in offset */
+ }
+
+-static __init void build_update_entries(u32 **p, unsigned int tmp,
++static __cpuinit void build_update_entries(u32 **p, unsigned int tmp,
+ unsigned int ptep)
+ {
+ /*
+@@ -1247,7 +1249,7 @@
+ #endif
+ }
+
+-static void __init build_r4000_tlb_refill_handler(void)
++static void __cpuinit build_r4000_tlb_refill_handler(void)
+ {
+ u32 *p = tlb_handler;
+ struct label *l = labels;
+@@ -1394,7 +1396,7 @@
+ u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
+ u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
+
+-static void __init
++static void __cpuinit
+ iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
+ {
+ #ifdef CONFIG_SMP
+@@ -1414,7 +1416,7 @@
+ #endif
+ }
+
+-static void __init
++static void __cpuinit
+ iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
+ unsigned int mode)
+ {
+@@ -1474,7 +1476,7 @@
+ * the page table where this PTE is located, PTE will be re-loaded
+ * with it's original value.
+ */
+-static void __init
++static void __cpuinit
+ build_pte_present(u32 **p, struct label **l, struct reloc **r,
+ unsigned int pte, unsigned int ptr, enum label_id lid)
+ {
+@@ -1485,7 +1487,7 @@
+ }
+
+ /* Make PTE valid, store result in PTR. */
+-static void __init
++static void __cpuinit
+ build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
+ unsigned int ptr)
+ {
+@@ -1498,7 +1500,7 @@
+ * Check if PTE can be written to, if not branch to LABEL. Regardless
+ * restore PTE with value from PTR when done.
+ */
+-static void __init
++static void __cpuinit
+ build_pte_writable(u32 **p, struct label **l, struct reloc **r,
+ unsigned int pte, unsigned int ptr, enum label_id lid)
+ {
+@@ -1511,7 +1513,7 @@
+ /* Make PTE writable, update software status bits as well, then store
+ * at PTR.
+ */
+-static void __init
++static void __cpuinit
+ build_make_write(u32 **p, struct reloc **r, unsigned int pte,
+ unsigned int ptr)
+ {
+@@ -1525,7 +1527,7 @@
+ * Check if PTE can be modified, if not branch to LABEL. Regardless
+ * restore PTE with value from PTR when done.
+ */
+-static void __init
++static void __cpuinit
+ build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
+ unsigned int pte, unsigned int ptr, enum label_id lid)
+ {
+@@ -1542,7 +1544,7 @@
+ * This places the pte into ENTRYLO0 and writes it with tlbwi.
+ * Then it returns.
+ */
+-static void __init
++static void __cpuinit
+ build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
+ {
+ i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
+@@ -1558,7 +1560,7 @@
+ * may have the probe fail bit set as a result of a trap on a
+ * kseg2 access, i.e. without refill. Then it returns.
+ */
+-static void __init
++static void __cpuinit
+ build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r,
+ unsigned int pte, unsigned int tmp)
+ {
+@@ -1575,7 +1577,7 @@
+ i_rfe(p); /* branch delay */
+ }
+
+-static void __init
++static void __cpuinit
+ build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
+ unsigned int ptr)
+ {
+@@ -1595,7 +1597,7 @@
+ i_tlbp(p); /* load delay */
+ }
+
+-static void __init build_r3000_tlb_load_handler(void)
++static void __cpuinit build_r3000_tlb_load_handler(void)
+ {
+ u32 *p = handle_tlbl;
+ struct label *l = labels;
+@@ -1630,7 +1632,7 @@
+ pr_debug("\t.set pop\n");
+ }
+
+-static void __init build_r3000_tlb_store_handler(void)
++static void __cpuinit build_r3000_tlb_store_handler(void)
+ {
+ u32 *p = handle_tlbs;
+ struct label *l = labels;
+@@ -1665,7 +1667,7 @@
+ pr_debug("\t.set pop\n");
+ }
+
+-static void __init build_r3000_tlb_modify_handler(void)
++static void __cpuinit build_r3000_tlb_modify_handler(void)
+ {
+ u32 *p = handle_tlbm;
+ struct label *l = labels;
+@@ -1703,7 +1705,7 @@
+ /*
+ * R4000 style TLB load/store/modify handlers.
+ */
+-static void __init
++static void __cpuinit
+ build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
+ struct reloc **r, unsigned int pte,
+ unsigned int ptr)
+@@ -1728,7 +1730,7 @@
+ build_tlb_probe_entry(p);
+ }
+
+-static void __init
++static void __cpuinit
+ build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
+ struct reloc **r, unsigned int tmp,
+ unsigned int ptr)
+@@ -1745,7 +1747,7 @@
+ #endif
+ }
+
+-static void __init build_r4000_tlb_load_handler(void)
++static void __cpuinit build_r4000_tlb_load_handler(void)
+ {
+ u32 *p = handle_tlbl;
+ struct label *l = labels;
+@@ -1790,7 +1792,7 @@
+ pr_debug("\t.set pop\n");
+ }
+
+-static void __init build_r4000_tlb_store_handler(void)
++static void __cpuinit build_r4000_tlb_store_handler(void)
+ {
+ u32 *p = handle_tlbs;
+ struct label *l = labels;
+@@ -1826,7 +1828,7 @@
+ pr_debug("\t.set pop\n");
+ }
+
+-static void __init build_r4000_tlb_modify_handler(void)
++static void __cpuinit build_r4000_tlb_modify_handler(void)
+ {
+ u32 *p = handle_tlbm;
+ struct label *l = labels;
+@@ -1863,7 +1865,7 @@
+ pr_debug("\t.set pop\n");
+ }
+
+-void __init build_tlb_refill_handler(void)
++void __cpuinit build_tlb_refill_handler(void)
+ {
+ /*
+ * The refill handler is generated per-CPU, multi-node systems
+@@ -1909,7 +1911,7 @@
+ }
+ }
+
+-void __init flush_tlb_handlers(void)
++void __cpuinit flush_tlb_handlers(void)
+ {
+ flush_icache_range((unsigned long)handle_tlbl,
+ (unsigned long)handle_tlbl + sizeof(handle_tlbl));
+diff -Nurd linux-2.6.24/arch/mips/mm/tlb-r3k.c mer-smartq-kernel/arch/mips/mm/tlb-r3k.c
+--- linux-2.6.24/arch/mips/mm/tlb-r3k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/tlb-r3k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -246,10 +246,6 @@
+ old_pagemask = read_c0_pagemask();
+ w = read_c0_wired();
+ write_c0_wired(w + 1);
+- if (read_c0_wired() != w + 1) {
+- printk("[tlbwired] No WIRED reg?\n");
+- return;
+- }
+ write_c0_index(w << 8);
+ write_c0_pagemask(pagemask);
+ write_c0_entryhi(entryhi);
+@@ -281,7 +277,7 @@
+ }
+ }
+
+-void __init tlb_init(void)
++void __cpuinit tlb_init(void)
+ {
+ local_flush_tlb_all();
+
+diff -Nurd linux-2.6.24/arch/mips/mm/tlb-r4k.c mer-smartq-kernel/arch/mips/mm/tlb-r4k.c
+--- linux-2.6.24/arch/mips/mm/tlb-r4k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/tlb-r4k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -388,7 +388,7 @@
+ * lifetime of the system
+ */
+
+-static int temp_tlb_entry __initdata;
++static int temp_tlb_entry __cpuinitdata;
+
+ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+ unsigned long entryhi, unsigned long pagemask)
+@@ -427,7 +427,7 @@
+ return ret;
+ }
+
+-static void __init probe_tlb(unsigned long config)
++static void __cpuinit probe_tlb(unsigned long config)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+ unsigned int reg;
+@@ -455,7 +455,7 @@
+ c->tlbsize = ((reg >> 25) & 0x3f) + 1;
+ }
+
+-static int __initdata ntlb = 0;
++static int __cpuinitdata ntlb = 0;
+ static int __init set_ntlb(char *str)
+ {
+ get_option(&str, &ntlb);
+@@ -464,7 +464,7 @@
+
+ __setup("ntlb=", set_ntlb);
+
+-void __init tlb_init(void)
++void __cpuinit tlb_init(void)
+ {
+ unsigned int config = read_c0_config();
+
+@@ -473,12 +473,15 @@
+ * - On R4600 1.7 the tlbp never hits for pages smaller than
+ * the value in the c0_pagemask register.
+ * - The entire mm handling assumes the c0_pagemask register to
+- * be set for 4kb pages.
++ * be set to fixed-size pages.
+ */
+ probe_tlb(config);
+ write_c0_pagemask(PM_DEFAULT_MASK);
+ write_c0_wired(0);
+- write_c0_framemask(0);
++ if (current_cpu_type() == CPU_R10000 ||
++ current_cpu_type() == CPU_R12000 ||
++ current_cpu_type() == CPU_R14000)
++ write_c0_framemask(0);
+ temp_tlb_entry = current_cpu_data.tlbsize - 1;
+
+ /* From this point on the ARC firmware is dead. */
+diff -Nurd linux-2.6.24/arch/mips/mm/tlb-r8k.c mer-smartq-kernel/arch/mips/mm/tlb-r8k.c
+--- linux-2.6.24/arch/mips/mm/tlb-r8k.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/mm/tlb-r8k.c 2009-11-17 12:13:29.000000000 +0100
+@@ -214,14 +214,14 @@
+ local_irq_restore(flags);
+ }
+
+-static void __init probe_tlb(unsigned long config)
++static void __cpuinit probe_tlb(unsigned long config)
+ {
+ struct cpuinfo_mips *c = &current_cpu_data;
+
+ c->tlbsize = 3 * 128; /* 3 sets each 128 entries */
+ }
+
+-void __init tlb_init(void)
++void __cpuinit tlb_init(void)
+ {
+ unsigned int config = read_c0_config();
+ unsigned long status;
+diff -Nurd linux-2.6.24/arch/mips/pci/pci-bcm1480.c mer-smartq-kernel/arch/mips/pci/pci-bcm1480.c
+--- linux-2.6.24/arch/mips/pci/pci-bcm1480.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/pci/pci-bcm1480.c 2009-11-17 12:13:29.000000000 +0100
+@@ -185,8 +185,8 @@
+
+ static struct resource bcm1480_io_resource = {
+ .name = "BCM1480 PCI I/O",
+- .start = 0x2c000000UL,
+- .end = 0x2dffffffUL,
++ .start = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
++ .end = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
+ .flags = IORESOURCE_IO,
+ };
+
+@@ -194,6 +194,7 @@
+ .pci_ops = &bcm1480_pci_ops,
+ .mem_resource = &bcm1480_mem_resource,
+ .io_resource = &bcm1480_io_resource,
++ .io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
+ };
+
+
+@@ -249,8 +250,10 @@
+ * XXX ehs: Should this happen in PCI Device mode?
+ */
+
+- set_io_port_base((unsigned long)
+- ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
++ bcm1480_controller.io_map_base = (unsigned long)
++ ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
++ bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
++ set_io_port_base(bcm1480_controller.io_map_base);
+ isa_slot_offset = (unsigned long)
+ ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
+
+diff -Nurd linux-2.6.24/arch/mips/pci/pci-bcm1480ht.c mer-smartq-kernel/arch/mips/pci/pci-bcm1480ht.c
+--- linux-2.6.24/arch/mips/pci/pci-bcm1480ht.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/pci/pci-bcm1480ht.c 2009-11-17 12:13:29.000000000 +0100
+@@ -180,8 +180,8 @@
+
+ static struct resource bcm1480ht_io_resource = {
+ .name = "BCM1480 HT I/O",
+- .start = 0x00000000UL,
+- .end = 0x01ffffffUL,
++ .start = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
++ .end = A_BCM1480_PHYS_HT_IO_MATCH_BYTES + 0x01ffffffUL,
+ .flags = IORESOURCE_IO,
+ };
+
+@@ -191,29 +191,22 @@
+ .io_resource = &bcm1480ht_io_resource,
+ .index = 1,
+ .get_busno = bcm1480ht_pcibios_get_busno,
++ .io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
+ };
+
+ static int __init bcm1480ht_pcibios_init(void)
+ {
+- uint32_t cmdreg;
+-
+ ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
+
+- /*
+- * See if the PCI bus has been configured by the firmware.
+- */
+- cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
+- PCI_COMMAND));
+- if (!(cmdreg & PCI_COMMAND_MASTER)) {
+- printk("HT: Skipping HT probe. Bus is not initialized.\n");
+- iounmap(ht_cfg_space);
+- return 1; /* XXX */
+- }
++ /* CFE doesn't always init all HT paths, so we always scan */
+ bcm1480ht_bus_status |= PCI_BUS_ENABLED;
+
+ ht_eoi_space = (unsigned long)
+ ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
+ 4 * 1024 * 1024);
++ bcm1480ht_controller.io_map_base = (unsigned long)
++ ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 65536);
++ bcm1480ht_controller.io_map_base -= bcm1480ht_controller.io_offset;
+
+ register_pci_controller(&bcm1480ht_controller);
+
+diff -Nurd linux-2.6.24/arch/mips/pci/pci.c mer-smartq-kernel/arch/mips/pci/pci.c
+--- linux-2.6.24/arch/mips/pci/pci.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/pci/pci.c 2009-11-17 12:13:29.000000000 +0100
+@@ -177,6 +177,11 @@
+ continue;
+
+ r = &dev->resource[idx];
++ if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
++ continue;
++ if ((idx == PCI_ROM_RESOURCE) &&
++ (!(r->flags & IORESOURCE_ROM_ENABLE)))
++ continue;
+ if (!r->start && r->end) {
+ printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
+ return -EINVAL;
+@@ -186,8 +191,6 @@
+ if (r->flags & IORESOURCE_MEM)
+ cmd |= PCI_COMMAND_MEMORY;
+ }
+- if (dev->resource[PCI_ROM_RESOURCE].start)
+- cmd |= PCI_COMMAND_MEMORY;
+ if (cmd != old_cmd) {
+ printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+@@ -254,7 +257,7 @@
+ }
+ }
+
+-void pcibios_fixup_bus(struct pci_bus *bus)
++void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+ {
+ /* Propagate hose info into the subordinate devices. */
+
+diff -Nurd linux-2.6.24/arch/mips/pci/pci-ip27.c mer-smartq-kernel/arch/mips/pci/pci-ip27.c
+--- linux-2.6.24/arch/mips/pci/pci-ip27.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/pci/pci-ip27.c 2009-11-17 12:13:29.000000000 +0100
+@@ -40,7 +40,7 @@
+
+ extern struct pci_ops bridge_pci_ops;
+
+-int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
++int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
+ {
+ unsigned long offset = NODE_OFFSET(nasid);
+ struct bridge_controller *bc;
+@@ -136,25 +136,47 @@
+ */
+ int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
++ return 0;
++}
++
++/* Most MIPS systems have straight-forward swizzling needs. */
++static inline u8 bridge_swizzle(u8 pin, u8 slot)
++{
++ return (((pin - 1) + slot) % 4) + 1;
++}
++
++static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
++{
++ while (dev->bus->parent) {
++ /* Move up the chain of bridges. */
++ dev = dev->bus->self;
++ }
++
++ return dev;
++}
++
++/* Do platform specific device initialization at pci_enable_device() time */
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
+ struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
+- int irq = bc->pci_int[slot];
++ struct pci_dev *rdev = bridge_root_dev(dev);
++ int slot = PCI_SLOT(rdev->devfn);
++ int irq;
+
++ irq = bc->pci_int[slot];
+ if (irq == -1) {
+- irq = bc->pci_int[slot] = request_bridge_irq(bc);
++ irq = request_bridge_irq(bc);
+ if (irq < 0)
+- panic("Can't allocate interrupt for PCI device %s\n",
+- pci_name(dev));
++ return irq;
++
++ bc->pci_int[slot] = irq;
+ }
+
+ irq_to_bridge[irq] = bc;
+ irq_to_slot[irq] = slot;
+
+- return irq;
+-}
++ dev->irq = irq;
+
+-/* Do platform specific device initialization at pci_enable_device() time */
+-int pcibios_plat_dev_init(struct pci_dev *dev)
+-{
+ return 0;
+ }
+
+diff -Nurd linux-2.6.24/arch/mips/pmc-sierra/yosemite/smp.c mer-smartq-kernel/arch/mips/pmc-sierra/yosemite/smp.c
+--- linux-2.6.24/arch/mips/pmc-sierra/yosemite/smp.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/pmc-sierra/yosemite/smp.c 2009-11-17 12:13:29.000000000 +0100
+@@ -7,10 +7,10 @@
+
+ #define LAUNCHSTACK_SIZE 256
+
+-static __initdata DEFINE_SPINLOCK(launch_lock);
++static __cpuinitdata DEFINE_SPINLOCK(launch_lock);
+
+-static unsigned long secondary_sp __initdata;
+-static unsigned long secondary_gp __initdata;
++static unsigned long secondary_sp __cpuinitdata;
++static unsigned long secondary_gp __cpuinitdata;
+
+ static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
+ __attribute__((aligned(2 * sizeof(long))));
+diff -Nurd linux-2.6.24/arch/mips/sgi-ip22/ip22-int.c mer-smartq-kernel/arch/mips/sgi-ip22/ip22-int.c
+--- linux-2.6.24/arch/mips/sgi-ip22/ip22-int.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sgi-ip22/ip22-int.c 2009-11-17 12:13:29.000000000 +0100
+@@ -68,7 +68,7 @@
+ sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
+ }
+
+-void disable_local1_irq(unsigned int irq)
++static void disable_local1_irq(unsigned int irq)
+ {
+ sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
+ }
+@@ -87,7 +87,7 @@
+ sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
+ }
+
+-void disable_local2_irq(unsigned int irq)
++static void disable_local2_irq(unsigned int irq)
+ {
+ sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
+ if (!sgint->cmeimask0)
+@@ -108,7 +108,7 @@
+ sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
+ }
+
+-void disable_local3_irq(unsigned int irq)
++static void disable_local3_irq(unsigned int irq)
+ {
+ sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
+ if (!sgint->cmeimask1)
+@@ -344,6 +344,6 @@
+
+ #ifdef CONFIG_EISA
+ if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
+- ip22_eisa_init();
++ ip22_eisa_init();
+ #endif
+ }
+diff -Nurd linux-2.6.24/arch/mips/sgi-ip22/ip22-platform.c mer-smartq-kernel/arch/mips/sgi-ip22/ip22-platform.c
+--- linux-2.6.24/arch/mips/sgi-ip22/ip22-platform.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sgi-ip22/ip22-platform.c 2009-11-17 12:13:29.000000000 +0100
+@@ -150,7 +150,7 @@
+ return res;
+
+ /* Second HPC is missing? */
+- if (!ip22_is_fullhouse() ||
++ if (ip22_is_fullhouse() ||
+ get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1]))
+ return 0;
+
+diff -Nurd linux-2.6.24/arch/mips/sgi-ip27/ip27-init.c mer-smartq-kernel/arch/mips/sgi-ip27/ip27-init.c
+--- linux-2.6.24/arch/mips/sgi-ip27/ip27-init.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sgi-ip27/ip27-init.c 2009-11-17 12:13:29.000000000 +0100
+@@ -54,7 +54,7 @@
+
+ extern void xtalk_probe_node(cnodeid_t nid);
+
+-static void __init per_hub_init(cnodeid_t cnode)
++static void __cpuinit per_hub_init(cnodeid_t cnode)
+ {
+ struct hub_data *hub = hub_data(cnode);
+ nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode);
+diff -Nurd linux-2.6.24/arch/mips/sgi-ip27/ip27-timer.c mer-smartq-kernel/arch/mips/sgi-ip27/ip27-timer.c
+--- linux-2.6.24/arch/mips/sgi-ip27/ip27-timer.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sgi-ip27/ip27-timer.c 2009-11-17 12:13:29.000000000 +0100
+@@ -158,7 +158,7 @@
+ }
+ }
+
+-unsigned int rt_timer_irq;
++int rt_timer_irq;
+
+ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id)
+ {
+@@ -219,7 +219,7 @@
+
+ static void __init hub_rt_clock_event_global_init(void)
+ {
+- unsigned int irq;
++ int irq;
+
+ do {
+ smp_wmb();
+@@ -285,7 +285,7 @@
+ set_c0_status(SRB_TIMOCLK);
+ }
+
+-void __init hub_rtc_init(cnodeid_t cnode)
++void __cpuinit hub_rtc_init(cnodeid_t cnode)
+ {
+ /*
+ * We only need to initialize the current node.
+diff -Nurd linux-2.6.24/arch/mips/sgi-ip27/ip27-xtalk.c mer-smartq-kernel/arch/mips/sgi-ip27/ip27-xtalk.c
+--- linux-2.6.24/arch/mips/sgi-ip27/ip27-xtalk.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sgi-ip27/ip27-xtalk.c 2009-11-17 12:13:29.000000000 +0100
+@@ -22,7 +22,7 @@
+
+ extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
+
+-static int __init probe_one_port(nasid_t nasid, int widget, int masterwid)
++static int __cpuinit probe_one_port(nasid_t nasid, int widget, int masterwid)
+ {
+ widgetreg_t widget_id;
+ xwidget_part_num_t partnum;
+@@ -46,7 +46,7 @@
+ return 0;
+ }
+
+-static int __init xbow_probe(nasid_t nasid)
++static int __cpuinit xbow_probe(nasid_t nasid)
+ {
+ lboard_t *brd;
+ klxbow_t *xbow_p;
+@@ -99,7 +99,7 @@
+ return 0;
+ }
+
+-void __init xtalk_probe_node(cnodeid_t nid)
++void __cpuinit xtalk_probe_node(cnodeid_t nid)
+ {
+ volatile u64 hubreg;
+ nasid_t nasid;
+diff -Nurd linux-2.6.24/arch/mips/sgi-ip32/ip32-irq.c mer-smartq-kernel/arch/mips/sgi-ip32/ip32-irq.c
+--- linux-2.6.24/arch/mips/sgi-ip32/ip32-irq.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sgi-ip32/ip32-irq.c 2009-11-17 12:13:29.000000000 +0100
+@@ -425,6 +425,11 @@
+ BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
+
+ crime_int = crime->istat & crime_mask;
++
++ /* crime sometime delivers spurious interrupts, ignore them */
++ if (unlikely(crime_int == 0))
++ return;
++
+ irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
+
+ if (crime_int & CRIME_MACEISA_INT_MASK) {
+diff -Nurd linux-2.6.24/arch/mips/sibyte/bcm1480/irq.c mer-smartq-kernel/arch/mips/sibyte/bcm1480/irq.c
+--- linux-2.6.24/arch/mips/sibyte/bcm1480/irq.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sibyte/bcm1480/irq.c 2009-11-17 12:13:29.000000000 +0100
+@@ -25,6 +25,7 @@
+ #include <linux/kernel_stat.h>
+
+ #include <asm/errno.h>
++#include <asm/gdb-stub.h>
+ #include <asm/irq_regs.h>
+ #include <asm/signal.h>
+ #include <asm/system.h>
+diff -Nurd linux-2.6.24/arch/mips/sibyte/sb1250/irq.c mer-smartq-kernel/arch/mips/sibyte/sb1250/irq.c
+--- linux-2.6.24/arch/mips/sibyte/sb1250/irq.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/sibyte/sb1250/irq.c 2009-11-17 12:13:29.000000000 +0100
+@@ -26,6 +26,7 @@
+ #include <linux/kernel_stat.h>
+
+ #include <asm/errno.h>
++#include <asm/gdb-stub.h>
+ #include <asm/signal.h>
+ #include <asm/system.h>
+ #include <asm/time.h>
+diff -Nurd linux-2.6.24/arch/mips/vr41xx/common/irq.c mer-smartq-kernel/arch/mips/vr41xx/common/irq.c
+--- linux-2.6.24/arch/mips/vr41xx/common/irq.c 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/arch/mips/vr41xx/common/irq.c 2009-11-17 12:13:29.000000000 +0100
+@@ -72,6 +72,7 @@
+ cascade = irq_cascade + irq;
+ if (cascade->get_irq != NULL) {
+ unsigned int source_irq = irq;
++ int ret;
+ desc = irq_desc + source_irq;
+ if (desc->chip->mask_ack)
+ desc->chip->mask_ack(source_irq);
+@@ -79,8 +80,9 @@
+ desc->chip->mask(source_irq);
+ desc->chip->ack(source_irq);
+ }
+- irq = cascade->get_irq(irq);
+- if (irq < 0)
++ ret = cascade->get_irq(irq);
++ irq = ret;
++ if (ret < 0)
+ atomic_inc(&irq_err_count);
+ else
+ irq_dispatch(irq);
+diff -Nurd linux-2.6.24/drivers/net/Kconfig mer-smartq-kernel/drivers/net/Kconfig
+--- linux-2.6.24/drivers/net/Kconfig 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/drivers/net/Kconfig 2009-11-17 18:05:55.000000000 +0100
+@@ -2348,6 +2348,13 @@
+ Some boards that use the Discovery chipset are the Momenco
+ Ocelot C and Jaguar ATX and Pegasos II.
+
++config TITAN_GE
++ bool "PMC-Sierra TITAN Gigabit Ethernet Support"
++ depends on PMC_YOSEMITE
++ help
++ This enables support for the the integrated ethernet of
++ PMC-Sierra's Titan SoC.
++
+ config QLA3XXX
+ tristate "QLogic QLA3XXX Network Driver Support"
+ depends on PCI
+diff -Nurd linux-2.6.24/drivers/net/Makefile mer-smartq-kernel/drivers/net/Makefile
+--- linux-2.6.24/drivers/net/Makefile 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/drivers/net/Makefile 2009-11-17 12:13:31.000000000 +0100
+@@ -124,6 +124,8 @@
+ obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
+ obj-$(CONFIG_QLA3XXX) += qla3xxx.o
+
++obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o
++
+ obj-$(CONFIG_PPP) += ppp_generic.o
+ obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
+ obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o
+diff -Nurd linux-2.6.24/drivers/net/titan_ge.c mer-smartq-kernel/drivers/net/titan_ge.c
+--- linux-2.6.24/drivers/net/titan_ge.c 1970-01-01 01:00:00.000000000 +0100
++++ mer-smartq-kernel/drivers/net/titan_ge.c 2009-11-17 12:13:31.000000000 +0100
+@@ -0,0 +1,2069 @@
++/*
++ * drivers/net/titan_ge.c - Driver for Titan ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++/*
++ * The MAC unit of the Titan consists of the following:
++ *
++ * -> XDMA Engine to move data to from the memory to the MAC packet FIFO
++ * -> FIFO is where the incoming and outgoing data is placed
++ * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes
++ * the data into the FIFO for Rx
++ * -> TMAC is the outgoing MAC interface and RMAC is the incoming.
++ * -> AFX is the address filtering block
++ * -> GMII block to communicate with the PHY
++ *
++ * Rx will look like the following:
++ * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory
++ *
++ * Tx will look like the following:
++ * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII
++ *
++ * The Titan driver has support for the following performance features:
++ * -> Rx side checksumming
++ * -> Jumbo Frames
++ * -> Interrupt Coalscing
++ * -> Rx NAPI
++ * -> SKB Recycling
++ * -> Transmit/Receive descriptors in SRAM
++ * -> Fast routing for IP forwarding
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/ioport.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/ip.h>
++#include <linux/init.h>
++#include <linux/in.h>
++#include <linux/platform_device.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/mii.h>
++#include <linux/delay.h>
++#include <linux/skbuff.h>
++#include <linux/prefetch.h>
++
++/* For MII specifc registers, titan_mdio.h should be included */
++#include <net/ip.h>
++
++#include <asm/bitops.h>
++#include <asm/io.h>
++#include <asm/types.h>
++#include <asm/pgtable.h>
++#include <asm/system.h>
++#include <asm/titan_dep.h>
++
++#include "titan_ge.h"
++#include "titan_mdio.h"
++
++/* Static Function Declarations */
++static int titan_ge_eth_open(struct net_device *);
++static void titan_ge_eth_stop(struct net_device *);
++static struct net_device_stats *titan_ge_get_stats(struct net_device *);
++static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int,
++ unsigned long, unsigned long,
++ unsigned long);
++static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int,
++ unsigned long, unsigned long);
++
++static int titan_ge_open(struct net_device *);
++static int titan_ge_start_xmit(struct sk_buff *, struct net_device *);
++static int titan_ge_stop(struct net_device *);
++
++static unsigned long titan_ge_tx_coal(unsigned long, int);
++
++static void titan_ge_port_reset(unsigned int);
++static int titan_ge_free_tx_queue(titan_ge_port_info *);
++static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *);
++static int titan_ge_port_start(struct net_device *, titan_ge_port_info *);
++
++static int titan_ge_return_tx_desc(titan_ge_port_info *, int);
++
++/*
++ * Some configuration for the FIFO and the XDMA channel needs
++ * to be done only once for all the ports. This flag controls
++ * that
++ */
++static unsigned long config_done;
++
++/*
++ * One time out of memory flag
++ */
++static unsigned int oom_flag;
++
++static int titan_ge_poll(struct net_device *netdev, int *budget);
++
++static int titan_ge_receive_queue(struct net_device *, unsigned int);
++
++static struct platform_device *titan_ge_device[3];
++
++/* MAC Address */
++extern unsigned char titan_ge_mac_addr_base[6];
++
++unsigned long titan_ge_base;
++static unsigned long titan_ge_sram;
++
++static char titan_string[] = "titan";
++
++/*
++ * The Titan GE has two alignment requirements:
++ * -> skb->data to be cacheline aligned (32 byte)
++ * -> IP header alignment to 16 bytes
++ *
++ * The latter is not implemented. So, that results in an extra copy on
++ * the Rx. This is a big performance hog. For the former case, the
++ * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size
++ * requested is calculated:
++ *
++ * Ethernet Frame Size : 1518
++ * Ethernet Header : 14
++ * Future Titan change for IP header alignment : 2
++ *
++ * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes. For IP header
++ * alignment, we use skb_reserve().
++ */
++
++#define ALIGNED_RX_SKB_ADDR(addr) \
++ ((((unsigned long)(addr) + (64UL - 1UL)) \
++ & ~(64UL - 1UL)) - (unsigned long)(addr))
++
++#define titan_ge_alloc_skb(__length, __gfp_flags) \
++({ struct sk_buff *__skb; \
++ __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
++ if(__skb) { \
++ int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
++ if(__offset) \
++ skb_reserve(__skb, __offset); \
++ } \
++ __skb; \
++})
++
++/*
++ * Configure the GMII block of the Titan based on what the PHY tells us
++ */
++static void titan_ge_gmii_config(int port_num)
++{
++ unsigned int reg_data = 0, phy_reg;
++ int err;
++
++ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
++
++ if (err == TITAN_GE_MDIO_ERROR) {
++ printk(KERN_ERR
++ "Could not read PHY control register 0x11 \n");
++ printk(KERN_ERR
++ "Setting speed to 1000 Mbps and Duplex to Full \n");
++
++ return;
++ }
++
++ err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0);
++
++ if (phy_reg & 0x8000) {
++ if (phy_reg & 0x2000) {
++ /* Full Duplex and 1000 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x201);
++ } else {
++ /* Half Duplex and 1000 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x2201);
++ }
++ }
++ if (phy_reg & 0x4000) {
++ if (phy_reg & 0x2000) {
++ /* Full Duplex and 100 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x100);
++ } else {
++ /* Half Duplex and 100 Mbps */
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++ (port_num << 12)), 0x2100);
++ }
++ }
++ reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL +
++ (port_num << 12));
++ reg_data |= 0x3;
++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL +
++ (port_num << 12)), reg_data);
++}
++
++/*
++ * Enable the TMAC if it is not
++ */
++static void titan_ge_enable_tx(unsigned int port_num)
++{
++ unsigned long reg_data;
++
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
++ if (!(reg_data & 0x8000)) {
++ printk("TMAC disabled for port %d!! \n", port_num);
++
++ reg_data |= 0x0001; /* Enable TMAC */
++ reg_data |= 0x4000; /* CRC Check Enable */
++ reg_data |= 0x2000; /* Padding enable */
++ reg_data |= 0x0800; /* CRC Add enable */
++ reg_data |= 0x0080; /* PAUSE frame */
++
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++ }
++}
++
++/*
++ * Tx Timeout function
++ */
++static void titan_ge_tx_timeout(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ printk(KERN_INFO "%s: TX timeout ", netdev->name);
++ printk(KERN_INFO "Resetting card \n");
++
++ /* Do the reset outside of interrupt context */
++ schedule_work(&titan_ge_eth->tx_timeout_task);
++}
++
++/*
++ * Update the AFX tables for UC and MC for slice 0 only
++ */
++static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth)
++{
++ int port = titan_ge_eth->port_num;
++ unsigned int i;
++ volatile unsigned long reg_data = 0;
++ u8 p_addr[6];
++
++ memcpy(p_addr, titan_ge_eth->port_mac_addr, 6);
++
++ /* Set the MAC address here for TMAC and RMAC */
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++
++ TITAN_GE_WRITE((0x112c | (port << 12)), 0x1);
++ /* Configure the eight address filters */
++ for (i = 0; i < 8; i++) {
++ /* Select each of the eight filters */
++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 +
++ (port << 12)), i);
++
++ /* Configure the match */
++ reg_data = 0x9; /* Forward Enable Bit */
++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 +
++ (port << 12)), reg_data);
++
++ /* Finally, AFX Exact Match Address Registers */
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++
++ /* VLAN id set to 0 */
++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID +
++ (port << 12)), 0);
++ }
++}
++
++/*
++ * Actual Routine to reset the adapter when the timeout occurred
++ */
++static void titan_ge_tx_timeout_task(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ int port = titan_ge_eth->port_num;
++
++ printk("Titan GE: Transmit timed out. Resetting ... \n");
++
++ /* Dump debug info */
++ printk(KERN_ERR "TRTG cause : %x \n",
++ TITAN_GE_READ(0x100c + (port << 12)));
++
++ /* Fix this for the other ports */
++ printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c));
++ printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040));
++ printk(KERN_ERR "XDMA GDI ERROR : %x \n",
++ TITAN_GE_READ(0x5008 + (port << 8)));
++ printk(KERN_ERR "CHANNEL ERROR: %x \n",
++ TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT
++ + (port << 8)));
++
++ netif_device_detach(netdev);
++ titan_ge_port_reset(titan_ge_eth->port_num);
++ titan_ge_port_start(netdev, titan_ge_eth);
++ netif_device_attach(netdev);
++}
++
++/*
++ * Change the MTU of the Ethernet Device
++ */
++static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned long flags;
++
++ if ((new_mtu > 9500) || (new_mtu < 64))
++ return -EINVAL;
++
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++ netdev->mtu = new_mtu;
++
++ /* Now we have to reopen the interface so that SKBs with the new
++ * size will be allocated */
++
++ if (netif_running(netdev)) {
++ titan_ge_eth_stop(netdev);
++
++ if (titan_ge_eth_open(netdev) != TITAN_OK) {
++ printk(KERN_ERR
++ "%s: Fatal error on opening device\n",
++ netdev->name);
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ return -1;
++ }
++ }
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ return 0;
++}
++
++/*
++ * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line
++ * only. Once an interrupt is triggered, figure out the port and then check
++ * the channel.
++ */
++static irqreturn_t titan_ge_int_handler(int irq, void *dev_id)
++{
++ struct net_device *netdev = (struct net_device *) dev_id;
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int reg_data;
++ unsigned int eth_int_cause_error = 0, is;
++ unsigned long eth_int_cause1;
++ int err = 0;
++#ifdef CONFIG_SMP
++ unsigned long eth_int_cause2;
++#endif
++
++ /* Ack the CPU interrupt */
++ switch (port_num) {
++ case 0:
++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS1);
++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is);
++
++#ifdef CONFIG_SMP
++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS1);
++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is);
++#endif
++ break;
++
++ case 1:
++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS0);
++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is);
++
++#ifdef CONFIG_SMP
++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS0);
++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is);
++#endif
++ break;
++
++ case 2:
++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is);
++
++#ifdef CONFIG_SMP
++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is);
++#endif
++ }
++
++ eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
++#ifdef CONFIG_SMP
++ eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B);
++#endif
++
++ /* Spurious interrupt */
++#ifdef CONFIG_SMP
++ if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) {
++#else
++ if (eth_int_cause1 == 0) {
++#endif
++ eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT +
++ (port_num << 8));
++
++ if (eth_int_cause_error == 0)
++ return IRQ_NONE;
++ }
++
++ /* Handle Tx first. No need to ack interrupts */
++#ifdef CONFIG_SMP
++ if ( (eth_int_cause1 & 0x20202) ||
++ (eth_int_cause2 & 0x20202) )
++#else
++ if (eth_int_cause1 & 0x20202)
++#endif
++ titan_ge_free_tx_queue(titan_ge_eth);
++
++ /* Handle the Rx next */
++#ifdef CONFIG_SMP
++ if ( (eth_int_cause1 & 0x10101) ||
++ (eth_int_cause2 & 0x10101)) {
++#else
++ if (eth_int_cause1 & 0x10101) {
++#endif
++ if (netif_rx_schedule_prep(netdev)) {
++ unsigned int ack;
++
++ ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++ /* Disable Tx and Rx both */
++ if (port_num == 0)
++ ack &= ~(0x3);
++ if (port_num == 1)
++ ack &= ~(0x300);
++
++ if (port_num == 2)
++ ack &= ~(0x30000);
++
++ /* Interrupts have been disabled */
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
++
++ __netif_rx_schedule(netdev);
++ }
++ }
++
++ /* Handle error interrupts */
++ if (eth_int_cause_error && (eth_int_cause_error != 0x2)) {
++ printk(KERN_ERR
++ "XDMA Channel Error : %x on port %d\n",
++ eth_int_cause_error, port_num);
++
++ printk(KERN_ERR
++ "XDMA GDI Hardware error : %x on port %d\n",
++ TITAN_GE_READ(0x5008 + (port_num << 8)), port_num);
++
++ printk(KERN_ERR
++ "XDMA currently has %d Rx descriptors \n",
++ TITAN_GE_READ(0x5048 + (port_num << 8)));
++
++ printk(KERN_ERR
++ "XDMA currently has prefetcted %d Rx descriptors \n",
++ TITAN_GE_READ(0x505c + (port_num << 8)));
++
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
++ (port_num << 8)), eth_int_cause_error);
++ }
++
++ /*
++ * PHY interrupt to inform abt the changes. Reading the
++ * PHY Status register will clear the interrupt
++ */
++ if ((!(eth_int_cause1 & 0x30303)) &&
++ (eth_int_cause_error == 0)) {
++ err =
++ titan_ge_mdio_read(port_num,
++ TITAN_GE_MDIO_PHY_IS, &reg_data);
++
++ if (reg_data & 0x0400) {
++ /* Link status change */
++ titan_ge_mdio_read(port_num,
++ TITAN_GE_MDIO_PHY_STATUS, &reg_data);
++ if (!(reg_data & 0x0400)) {
++ /* Link is down */
++ netif_carrier_off(netdev);
++ netif_stop_queue(netdev);
++ } else {
++ /* Link is up */
++ netif_carrier_on(netdev);
++ netif_wake_queue(netdev);
++
++ /* Enable the queue */
++ titan_ge_enable_tx(port_num);
++ }
++ }
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * Multicast and Promiscuous mode set. The
++ * set_multi entry point is called whenever the
++ * multicast address list or the network interface
++ * flags are updated.
++ */
++static void titan_ge_set_multi(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned long reg_data;
++
++ reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
++ (port_num << 12));
++
++ if (netdev->flags & IFF_PROMISC) {
++ reg_data |= 0x2;
++ }
++ else if (netdev->flags & IFF_ALLMULTI) {
++ reg_data |= 0x01;
++ reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */
++ }
++ else {
++ reg_data = 0x2;
++ }
++
++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
++ (port_num << 12)), reg_data);
++ if (reg_data & 0x01) {
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
++ (port_num << 12)), 0xffff);
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
++ (port_num << 12)), 0xffff);
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
++ (port_num << 12)), 0xffff);
++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
++ (port_num << 12)), 0xffff);
++ }
++}
++
++/*
++ * Open the network device
++ */
++static int titan_ge_open(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int irq = TITAN_ETH_PORT_IRQ - port_num;
++ int retval;
++
++ retval = request_irq(irq, titan_ge_int_handler,
++ SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev);
++
++ if (retval != 0) {
++ printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n");
++ return -1;
++ }
++
++ netdev->irq = irq;
++ printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num);
++
++ spin_lock_irq(&(titan_ge_eth->lock));
++
++ if (titan_ge_eth_open(netdev) != TITAN_OK) {
++ spin_unlock_irq(&(titan_ge_eth->lock));
++ printk("%s: Error opening interface \n", netdev->name);
++ free_irq(netdev->irq, netdev);
++ return -EBUSY;
++ }
++
++ spin_unlock_irq(&(titan_ge_eth->lock));
++
++ return 0;
++}
++
++/*
++ * Allocate the SKBs for the Rx ring. Also used
++ * for refilling the queue
++ */
++static int titan_ge_rx_task(struct net_device *netdev,
++ titan_ge_port_info *titan_ge_port)
++{
++ struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev;
++ volatile titan_ge_rx_desc *rx_desc;
++ struct sk_buff *skb;
++ int rx_used_desc;
++ int count = 0;
++
++ while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) {
++
++ /* First try to get the skb from the recycler */
++#ifdef TITAN_GE_JUMBO_FRAMES
++ skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC);
++#else
++ skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC);
++#endif
++ if (unlikely(!skb)) {
++ /* OOM, set the flag */
++ printk("OOM \n");
++ oom_flag = 1;
++ break;
++ }
++ count++;
++ skb->dev = netdev;
++
++ titan_ge_port->rx_ring_skbs++;
++
++ rx_used_desc = titan_ge_port->rx_used_desc_q;
++ rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]);
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++ rx_desc->buffer_addr = dma_map_single(device, skb->data,
++ TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE);
++#else
++ rx_desc->buffer_addr = dma_map_single(device, skb->data,
++ TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE);
++#endif
++
++ titan_ge_port->rx_skb[rx_used_desc] = skb;
++ rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED;
++
++ titan_ge_port->rx_used_desc_q =
++ (rx_used_desc + 1) % TITAN_GE_RX_QUEUE;
++ }
++
++ return count;
++}
++
++/*
++ * Actual init of the Tital GE port. There is one register for
++ * the channel configuration
++ */
++static void titan_port_init(struct net_device *netdev,
++ titan_ge_port_info * titan_ge_eth)
++{
++ unsigned long reg_data;
++
++ titan_ge_port_reset(titan_ge_eth->port_num);
++
++ /* First reset the TMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data |= 0x80000000;
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++ udelay(30);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data &= ~(0xc0000000);
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++ /* Now reset the RMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data |= 0x00080000;
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++ udelay(30);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++ reg_data &= ~(0x000c0000);
++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++}
++
++/*
++ * Start the port. All the hardware specific configuration
++ * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX
++ * go here
++ */
++static int titan_ge_port_start(struct net_device *netdev,
++ titan_ge_port_info * titan_port)
++{
++ volatile unsigned long reg_data, reg_data1;
++ int port_num = titan_port->port_num;
++ int count = 0;
++ unsigned long reg_data_1;
++
++ if (config_done == 0) {
++ reg_data = TITAN_GE_READ(0x0004);
++ reg_data |= 0x100;
++ TITAN_GE_WRITE(0x0004, reg_data);
++
++ reg_data &= ~(0x100);
++ TITAN_GE_WRITE(0x0004, reg_data);
++
++ /* Turn on GMII/MII mode and turn off TBI mode */
++ reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
++ reg_data |= 0x00000700;
++ reg_data &= ~(0x00800000); /* Fencing */
++
++ TITAN_GE_WRITE(0x000c, 0x00001100);
++
++ TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
++
++ /* Set the CPU Resource Limit register */
++ TITAN_GE_WRITE(0x00f8, 0x8);
++
++ /* Be conservative when using the BIU buffers */
++ TITAN_GE_WRITE(0x0068, 0x4);
++ }
++
++ titan_port->tx_threshold = 0;
++ titan_port->rx_threshold = 0;
++
++ /* We need to write the descriptors for Tx and Rx */
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
++ (unsigned long) titan_port->tx_dma);
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
++ (unsigned long) titan_port->rx_dma);
++
++ if (config_done == 0) {
++ /* Step 1: XDMA config */
++ reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
++ reg_data &= ~(0x80000000); /* clear reset */
++ reg_data |= 0x1 << 29; /* sparse tx descriptor spacing */
++ reg_data |= 0x1 << 28; /* sparse rx descriptor spacing */
++ reg_data |= (0x1 << 23) | (0x1 << 24); /* Descriptor Coherency */
++ reg_data |= (0x1 << 21) | (0x1 << 22); /* Data Coherency */
++ TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
++ }
++
++ /* IR register for the XDMA */
++ reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
++ reg_data |= 0x80068000; /* No Rx_OOD */
++ TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
++
++ /* Start the Tx and Rx XDMA controller */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
++ reg_data &= 0x4fffffff; /* Clear tx reset */
++ reg_data &= 0xfff4ffff; /* Clear rx reset */
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++ reg_data |= 0xa0 | 0x30030000;
++#else
++ reg_data |= 0x40 | 0x20030000;
++#endif
++
++#ifndef CONFIG_SMP
++ reg_data &= ~(0x10);
++ reg_data |= 0x0f; /* All of the packet */
++#endif
++
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
++
++ /* Rx desc count */
++ count = titan_ge_rx_task(netdev, titan_port);
++ TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
++ count = TITAN_GE_READ(0x5048 + (port_num << 8));
++
++ udelay(30);
++
++ /*
++ * Step 2: Configure the SDQPF, i.e. FIFO
++ */
++ if (config_done == 0) {
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
++ reg_data = 0x1;
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++ reg_data &= ~(0x1);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
++ reg_data = 0x1;
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++ reg_data &= ~(0x1);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++ }
++ /*
++ * Enable RX FIFO 0, 4 and 8
++ */
++ if (port_num == 0) {
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10);
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4844);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x4844, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
++
++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++ reg_data |= (0xff << 10);
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4944);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x4944, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++ }
++
++ if (port_num == 1) {
++ reg_data = TITAN_GE_READ(0x4870);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10) | (0xff + 1);
++
++ TITAN_GE_WRITE(0x4870, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4874);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x4874, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x4870, reg_data);
++
++ reg_data = TITAN_GE_READ(0x494c);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(0x494c, reg_data);
++ reg_data |= (0xff << 10) | (0xff + 1);
++ TITAN_GE_WRITE(0x494c, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x4950);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x4950, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x494c, reg_data);
++ }
++
++ /*
++ * Titan 1.2 revision does support port #2
++ */
++ if (port_num == 2) {
++ /*
++ * Put the descriptors in the SRAM
++ */
++ reg_data = TITAN_GE_READ(0x48a0);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x48a4);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x48a4, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++
++ reg_data = TITAN_GE_READ(0x4958);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++ TITAN_GE_WRITE(0x4958, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x495c);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x495c, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ }
++
++ if (port_num == 2) {
++ reg_data = TITAN_GE_READ(0x48a0);
++
++ reg_data |= 0x100000;
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++ /*
++ * BAV2,BAV and DAV settings for the Rx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x48a4);
++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++ TITAN_GE_WRITE(0x48a4, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x48a0, reg_data);
++
++ reg_data = TITAN_GE_READ(0x4958);
++ reg_data |= 0x100000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ reg_data |= (0xff << 10) | (2*(0xff + 1));
++ TITAN_GE_WRITE(0x4958, reg_data);
++
++ /*
++ * BAV2, BAV and DAV settings for the Tx FIFO
++ */
++ reg_data1 = TITAN_GE_READ(0x495c);
++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++ TITAN_GE_WRITE(0x495c, reg_data1);
++
++ reg_data &= ~(0x00100000);
++ reg_data |= 0x200000;
++
++ TITAN_GE_WRITE(0x4958, reg_data);
++ }
++
++ /*
++ * Step 3: TRTG block enable
++ */
++ reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
++
++ /*
++ * This is the 1.2 revision of the chip. It has fix for the
++ * IP header alignment. Now, the IP header begins at an
++ * aligned address and this wont need an extra copy in the
++ * driver. This performance drawback existed in the previous
++ * versions of the silicon
++ */
++ reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
++ reg_data_1 |= 0x40000000;
++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++ reg_data_1 |= 0x04000000;
++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++ mdelay(5);
++
++ reg_data_1 &= ~(0x04000000);
++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++ mdelay(5);
++
++ reg_data |= 0x0001;
++ TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
++
++ /*
++ * Step 4: Start the Tx activity
++ */
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
++#ifdef TITAN_GE_JUMBO_FRAMES
++ TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
++#endif
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
++ reg_data |= 0x0001; /* Enable TMAC */
++ reg_data |= 0x6c70; /* PAUSE also set */
++
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++ udelay(30);
++
++ /* Destination Address drop bit */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
++ reg_data |= 0x218; /* DA_DROP bit and pause */
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
++
++ TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++ TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
++#endif
++ /* Start the Rx activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
++ reg_data |= 0x0001; /* RMAC Enable */
++ reg_data |= 0x0010; /* CRC Check enable */
++ reg_data |= 0x0040; /* Min Frame check enable */
++ reg_data |= 0x4400; /* Max Frame check enable */
++
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++ udelay(30);
++
++ /*
++ * Enable the Interrupts for Tx and Rx
++ */
++ reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++
++ if (port_num == 0) {
++ reg_data1 |= 0x3;
++#ifdef CONFIG_SMP
++ TITAN_GE_WRITE(0x0038, 0x003);
++#else
++ TITAN_GE_WRITE(0x0038, 0x303);
++#endif
++ }
++
++ if (port_num == 1) {
++ reg_data1 |= 0x300;
++ }
++
++ if (port_num == 2)
++ reg_data1 |= 0x30000;
++
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
++ TITAN_GE_WRITE(0x003c, 0x300);
++
++ if (config_done == 0) {
++ TITAN_GE_WRITE(0x0024, 0x04000024); /* IRQ vector */
++ TITAN_GE_WRITE(0x0020, 0x000fb000); /* INTMSG base */
++ }
++
++ /* Priority */
++ reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
++ reg_data &= ~(0x00f00000);
++ TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
++
++ /* Step 5: GMII config */
++ titan_ge_gmii_config(port_num);
++
++ if (config_done == 0) {
++ TITAN_GE_WRITE(0x1a80, 0);
++ config_done = 1;
++ }
++
++ return TITAN_OK;
++}
++
++/*
++ * Function to queue the packet for the Ethernet device
++ */
++static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth,
++ struct sk_buff * skb)
++{
++ struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev;
++ unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q;
++ volatile titan_ge_tx_desc *tx_curr;
++ int port_num = titan_ge_eth->port_num;
++
++ tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]);
++ tx_curr->buffer_addr =
++ dma_map_single(device, skb->data, skb_headlen(skb),
++ DMA_TO_DEVICE);
++
++ titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb;
++ tx_curr->buffer_len = skb_headlen(skb);
++
++ /* Last descriptor enables interrupt and changes ownership */
++ tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5);
++
++ /* Kick the XDMA to start the transfer from memory to the FIFO */
++ TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
++
++ /* Current descriptor updated */
++ titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE;
++
++ /* Prefetch the next descriptor */
++ prefetch((const void *)
++ &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]);
++}
++
++/*
++ * Actually does the open of the Ethernet device
++ */
++static int titan_ge_eth_open(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ struct device *device = &titan_ge_device[port_num]->dev;
++ unsigned long reg_data;
++ unsigned int phy_reg;
++ int err = 0;
++
++ /* Stop the Rx activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
++ reg_data &= ~(0x00000001);
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++ /* Clear the port interrupts */
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0);
++
++ if (config_done == 0) {
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
++ }
++
++ /* Set the MAC Address */
++ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
++
++ if (config_done == 0)
++ titan_port_init(netdev, titan_ge_eth);
++
++ titan_ge_update_afx(titan_ge_eth);
++
++ /* Allocate the Tx ring now */
++ titan_ge_eth->tx_ring_skbs = 0;
++ titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE;
++
++ /* Allocate space in the SRAM for the descriptors */
++ titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *)
++ (titan_ge_sram + TITAN_TX_RING_BYTES * port_num);
++ titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num;
++
++ if (!titan_ge_eth->tx_desc_area) {
++ printk(KERN_ERR
++ "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n",
++ netdev->name, TITAN_TX_RING_BYTES, port_num);
++ return -ENOMEM;
++ }
++
++ memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size);
++
++ /* Now initialize the Tx descriptor ring */
++ titan_ge_init_tx_desc_ring(titan_ge_eth,
++ titan_ge_eth->tx_ring_size,
++ (unsigned long) titan_ge_eth->tx_desc_area,
++ (unsigned long) titan_ge_eth->tx_dma);
++
++ /* Allocate the Rx ring now */
++ titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE;
++ titan_ge_eth->rx_ring_skbs = 0;
++
++ titan_ge_eth->rx_desc_area =
++ (titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num);
++
++ titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num;
++
++ if (!titan_ge_eth->rx_desc_area) {
++ printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
++ netdev->name, TITAN_RX_RING_BYTES);
++
++ printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
++ netdev->name);
++
++ dma_free_coherent(device, titan_ge_eth->tx_desc_area_size,
++ (void *) titan_ge_eth->tx_desc_area,
++ titan_ge_eth->tx_dma);
++
++ return -ENOMEM;
++ }
++
++ memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size);
++
++ /* Now initialize the Rx ring */
++#ifdef TITAN_GE_JUMBO_FRAMES
++ if ((titan_ge_init_rx_desc_ring
++ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE,
++ (unsigned long) titan_ge_eth->rx_desc_area, 0,
++ (unsigned long) titan_ge_eth->rx_dma)) == 0)
++#else
++ if ((titan_ge_init_rx_desc_ring
++ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE,
++ (unsigned long) titan_ge_eth->rx_desc_area, 0,
++ (unsigned long) titan_ge_eth->rx_dma)) == 0)
++#endif
++ panic("%s: Error initializing RX Ring\n", netdev->name);
++
++ /* Fill the Rx ring with the SKBs */
++ titan_ge_port_start(netdev, titan_ge_eth);
++
++ /*
++ * Check if Interrupt Coalscing needs to be turned on. The
++ * values specified in the register is multiplied by
++ * (8 x 64 nanoseconds) to determine when an interrupt should
++ * be sent to the CPU.
++ */
++
++ if (TITAN_GE_TX_COAL) {
++ titan_ge_eth->tx_int_coal =
++ titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num);
++ }
++
++ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
++ if (err == TITAN_GE_MDIO_ERROR) {
++ printk(KERN_ERR
++ "Could not read PHY control register 0x11 \n");
++ return TITAN_ERROR;
++ }
++ if (!(phy_reg & 0x0400)) {
++ netif_carrier_off(netdev);
++ netif_stop_queue(netdev);
++ return TITAN_ERROR;
++ } else {
++ netif_carrier_on(netdev);
++ netif_start_queue(netdev);
++ }
++
++ return TITAN_OK;
++}
++
++/*
++ * Queue the packet for Tx. Currently no support for zero copy,
++ * checksum offload and Scatter Gather. The chip does support
++ * Scatter Gather only. But, that wont help here since zero copy
++ * requires support for Tx checksumming also.
++ */
++int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned long flags;
++ struct net_device_stats *stats;
++//printk("titan_ge_start_xmit\n");
++
++ stats = &titan_ge_eth->stats;
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++ if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <=
++ (skb_shinfo(skb)->nr_frags + 1)) {
++ netif_stop_queue(netdev);
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ printk(KERN_ERR "Tx OOD \n");
++ return 1;
++ }
++
++ titan_ge_tx_queue(titan_ge_eth, skb);
++ titan_ge_eth->tx_ring_skbs++;
++
++ if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) {
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++ titan_ge_free_tx_queue(titan_ge_eth);
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++ }
++
++ stats->tx_bytes += skb->len;
++ stats->tx_packets++;
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++ netdev->trans_start = jiffies;
++
++ return 0;
++}
++
++/*
++ * Actually does the Rx. Rx side checksumming supported.
++ */
++static int titan_ge_rx(struct net_device *netdev, int port_num,
++ titan_ge_port_info * titan_ge_port,
++ titan_ge_packet * packet)
++{
++ int rx_curr_desc, rx_used_desc;
++ volatile titan_ge_rx_desc *rx_desc;
++
++ rx_curr_desc = titan_ge_port->rx_curr_desc_q;
++ rx_used_desc = titan_ge_port->rx_used_desc_q;
++
++ if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc)
++ return TITAN_ERROR;
++
++ rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]);
++
++ if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED)
++ return TITAN_ERROR;
++
++ packet->skb = titan_ge_port->rx_skb[rx_curr_desc];
++ packet->len = (rx_desc->cmd_sts & 0x7fff);
++
++ /*
++ * At this point, we dont know if the checksumming
++ * actually helps relieve CPU. So, keep it for
++ * port 0 only
++ */
++ packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16);
++ packet->cmd_sts = rx_desc->cmd_sts;
++
++ titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE;
++
++ /* Prefetch the next descriptor */
++ prefetch((const void *)
++ &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]);
++
++ return TITAN_OK;
++}
++
++/*
++ * Free the Tx queue of the used SKBs
++ */
++static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth)
++{
++ unsigned long flags;
++
++ /* Take the lock */
++ spin_lock_irqsave(&(titan_ge_eth->lock), flags);
++
++ while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0)
++ if (titan_ge_eth->tx_ring_skbs != 1)
++ titan_ge_eth->tx_ring_skbs--;
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++ return TITAN_OK;
++}
++
++/*
++ * Threshold beyond which we do the cleaning of
++ * Tx queue and new allocation for the Rx
++ * queue
++ */
++#define TX_THRESHOLD 4
++#define RX_THRESHOLD 10
++
++/*
++ * Receive the packets and send it to the kernel.
++ */
++static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ titan_ge_packet packet;
++ struct net_device_stats *stats;
++ struct sk_buff *skb;
++ unsigned long received_packets = 0;
++ unsigned int ack;
++
++ stats = &titan_ge_eth->stats;
++
++ while ((--max)
++ && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) {
++ skb = (struct sk_buff *) packet.skb;
++
++ titan_ge_eth->rx_ring_skbs--;
++
++ if (--titan_ge_eth->rx_work_limit < 0)
++ break;
++ received_packets++;
++
++ stats->rx_packets++;
++ stats->rx_bytes += packet.len;
++
++ if ((packet.cmd_sts & TITAN_GE_RX_PERR) ||
++ (packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) ||
++ (packet.cmd_sts & TITAN_GE_RX_TRUNC) ||
++ (packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) {
++ stats->rx_dropped++;
++ dev_kfree_skb_any(skb);
++
++ continue;
++ }
++ /*
++ * Either support fast path or slow path. Decision
++ * making can really slow down the performance. The
++ * idea is to cut down the number of checks and improve
++ * the fastpath.
++ */
++
++ skb_put(skb, packet.len - 2);
++
++ /*
++ * Increment data pointer by two since thats where
++ * the MAC starts
++ */
++ skb_reserve(skb, 2);
++ skb->protocol = eth_type_trans(skb, netdev);
++ netif_receive_skb(skb);
++
++ if (titan_ge_eth->rx_threshold > RX_THRESHOLD) {
++ ack = titan_ge_rx_task(netdev, titan_ge_eth);
++ TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
++ titan_ge_eth->rx_threshold = 0;
++ } else
++ titan_ge_eth->rx_threshold++;
++
++ if (titan_ge_eth->tx_threshold > TX_THRESHOLD) {
++ titan_ge_eth->tx_threshold = 0;
++ titan_ge_free_tx_queue(titan_ge_eth);
++ }
++ else
++ titan_ge_eth->tx_threshold++;
++
++ }
++ return received_packets;
++}
++
++
++/*
++ * Enable the Rx side interrupts
++ */
++static void titan_ge_enable_int(unsigned int port_num,
++ titan_ge_port_info *titan_ge_eth,
++ struct net_device *netdev)
++{
++ unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++
++ if (port_num == 0)
++ reg_data |= 0x3;
++ if (port_num == 1)
++ reg_data |= 0x300;
++ if (port_num == 2)
++ reg_data |= 0x30000;
++
++ /* Re-enable interrupts */
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
++}
++
++/*
++ * Main function to handle the polling for Rx side NAPI.
++ * Receive interrupts have been disabled at this point.
++ * The poll schedules the transmit followed by receive.
++ */
++static int titan_ge_poll(struct net_device *netdev, int *budget)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ int port_num = titan_ge_eth->port_num;
++ int work_done = 0;
++ unsigned long flags, status;
++
++ titan_ge_eth->rx_work_limit = *budget;
++ if (titan_ge_eth->rx_work_limit > netdev->quota)
++ titan_ge_eth->rx_work_limit = netdev->quota;
++
++ do {
++ /* Do the transmit cleaning work here */
++ titan_ge_free_tx_queue(titan_ge_eth);
++
++ /* Ack the Rx interrupts */
++ if (port_num == 0)
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
++ if (port_num == 1)
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
++ if (port_num == 2)
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
++
++ work_done += titan_ge_receive_queue(netdev, 0);
++
++ /* Out of quota and there is work to be done */
++ if (titan_ge_eth->rx_work_limit < 0)
++ goto not_done;
++
++ /* Receive alloc_skb could lead to OOM */
++ if (oom_flag == 1) {
++ oom_flag = 0;
++ goto oom;
++ }
++
++ status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
++ } while (status & 0x30300);
++
++ /* If we are here, then no more interrupts to process */
++ goto done;
++
++not_done:
++ *budget -= work_done;
++ netdev->quota -= work_done;
++ return 1;
++
++oom:
++ printk(KERN_ERR "OOM \n");
++ netif_rx_complete(netdev);
++ return 0;
++
++done:
++ /*
++ * No more packets on the poll list. Turn the interrupts
++ * back on and we should be able to catch the new
++ * packets in the interrupt handler
++ */
++ if (!work_done)
++ work_done = 1;
++
++ *budget -= work_done;
++ netdev->quota -= work_done;
++
++ spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++ /* Remove us from the poll list */
++ netif_rx_complete(netdev);
++
++ /* Re-enable interrupts */
++ titan_ge_enable_int(port_num, titan_ge_eth, netdev);
++
++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++ return 0;
++}
++
++/*
++ * Close the network device
++ */
++int titan_ge_stop(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ spin_lock_irq(&(titan_ge_eth->lock));
++ titan_ge_eth_stop(netdev);
++ free_irq(netdev->irq, netdev);
++ spin_unlock_irq(&titan_ge_eth->lock);
++
++ return TITAN_OK;
++}
++
++/*
++ * Free the Tx ring
++ */
++static void titan_ge_free_tx_rings(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int curr;
++ unsigned long reg_data;
++
++ /* Stop the Tx DMA */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8));
++ reg_data |= 0xc0000000;
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8)), reg_data);
++
++ /* Disable the TMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x00000001);
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ for (curr = 0;
++ (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE);
++ curr++) {
++ if (titan_ge_eth->tx_skb[curr]) {
++ dev_kfree_skb(titan_ge_eth->tx_skb[curr]);
++ titan_ge_eth->tx_ring_skbs--;
++ }
++ }
++
++ if (titan_ge_eth->tx_ring_skbs != 0)
++ printk
++ ("%s: Error on Tx descriptor free - could not free %d"
++ " descriptors\n", netdev->name,
++ titan_ge_eth->tx_ring_skbs);
++
++#ifndef TITAN_RX_RING_IN_SRAM
++ dma_free_coherent(&titan_ge_device[port_num]->dev,
++ titan_ge_eth->tx_desc_area_size,
++ (void *) titan_ge_eth->tx_desc_area,
++ titan_ge_eth->tx_dma);
++#endif
++}
++
++/*
++ * Free the Rx ring
++ */
++static void titan_ge_free_rx_rings(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ unsigned int curr;
++ unsigned long reg_data;
++
++ /* Stop the Rx DMA */
++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8));
++ reg_data |= 0x000c0000;
++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
++ (port_num << 8)), reg_data);
++
++ /* Disable the RMAC */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x00000001);
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ for (curr = 0;
++ titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE);
++ curr++) {
++ if (titan_ge_eth->rx_skb[curr]) {
++ dev_kfree_skb(titan_ge_eth->rx_skb[curr]);
++ titan_ge_eth->rx_ring_skbs--;
++ }
++ }
++
++ if (titan_ge_eth->rx_ring_skbs != 0)
++ printk(KERN_ERR
++ "%s: Error in freeing Rx Ring. %d skb's still"
++ " stuck in RX Ring - ignoring them\n", netdev->name,
++ titan_ge_eth->rx_ring_skbs);
++
++#ifndef TITAN_RX_RING_IN_SRAM
++ dma_free_coherent(&titan_ge_device[port_num]->dev,
++ titan_ge_eth->rx_desc_area_size,
++ (void *) titan_ge_eth->rx_desc_area,
++ titan_ge_eth->rx_dma);
++#endif
++}
++
++/*
++ * Actually does the stop of the Ethernet device
++ */
++static void titan_ge_eth_stop(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ netif_stop_queue(netdev);
++
++ titan_ge_port_reset(titan_ge_eth->port_num);
++
++ titan_ge_free_tx_rings(netdev);
++ titan_ge_free_rx_rings(netdev);
++
++ /* Disable the Tx and Rx Interrupts for all channels */
++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
++}
++
++/*
++ * Update the MAC address. Note that we have to write the
++ * address in three station registers, 16 bits each. And this
++ * has to be done for TMAC and RMAC
++ */
++static void titan_ge_update_mac_address(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++ unsigned int port_num = titan_ge_eth->port_num;
++ u8 p_addr[6];
++
++ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
++ memcpy(p_addr, netdev->dev_addr, 6);
++
++ /* Update the Address Filtering Match tables */
++ titan_ge_update_afx(titan_ge_eth);
++
++ printk("Station MAC : %d %d %d %d %d %d \n",
++ p_addr[5], p_addr[4], p_addr[3],
++ p_addr[2], p_addr[1], p_addr[0]);
++
++ /* Set the MAC address here for TMAC and RMAC */
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
++ ((p_addr[5] << 8) | p_addr[4]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
++ ((p_addr[3] << 8) | p_addr[2]));
++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
++ ((p_addr[1] << 8) | p_addr[0]));
++}
++
++/*
++ * Set the MAC address of the Ethernet device
++ */
++static int titan_ge_set_mac_address(struct net_device *dev, void *addr)
++{
++ titan_ge_port_info *tp = netdev_priv(dev);
++ struct sockaddr *sa = addr;
++
++ memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
++
++ spin_lock_irq(&tp->lock);
++ titan_ge_update_mac_address(dev);
++ spin_unlock_irq(&tp->lock);
++
++ return 0;
++}
++
++/*
++ * Get the Ethernet device stats
++ */
++static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev)
++{
++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++ return &titan_ge_eth->stats;
++}
++
++/*
++ * Initialize the Rx descriptor ring for the Titan Ge
++ */
++static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port,
++ int rx_desc_num,
++ int rx_buff_size,
++ unsigned long rx_desc_base_addr,
++ unsigned long rx_buff_base_addr,
++ unsigned long rx_dma)
++{
++ volatile titan_ge_rx_desc *rx_desc;
++ unsigned long buffer_addr;
++ int index;
++ unsigned long titan_ge_rx_desc_bus = rx_dma;
++
++ buffer_addr = rx_buff_base_addr;
++ rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr;
++
++ /* Check alignment */
++ if (rx_buff_base_addr & 0xF)
++ return 0;
++
++ /* Check Rx buffer size */
++ if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER))
++ return 0;
++
++ /* 64-bit alignment
++ if ((rx_buff_base_addr + rx_buff_size) & 0x7)
++ return 0; */
++
++ /* Initialize the Rx desc ring */
++ for (index = 0; index < rx_desc_num; index++) {
++ titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc);
++ rx_desc[index].cmd_sts = 0;
++ rx_desc[index].buffer_addr = buffer_addr;
++ titan_eth_port->rx_skb[index] = NULL;
++ buffer_addr += rx_buff_size;
++ }
++
++ titan_eth_port->rx_curr_desc_q = 0;
++ titan_eth_port->rx_used_desc_q = 0;
++
++ titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr;
++ titan_eth_port->rx_desc_area_size =
++ rx_desc_num * sizeof(titan_ge_rx_desc);
++
++ titan_eth_port->rx_dma = rx_dma;
++
++ return TITAN_OK;
++}
++
++/*
++ * Initialize the Tx descriptor ring. Descriptors in the SRAM
++ */
++static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port,
++ int tx_desc_num,
++ unsigned long tx_desc_base_addr,
++ unsigned long tx_dma)
++{
++ titan_ge_tx_desc *tx_desc;
++ int index;
++ unsigned long titan_ge_tx_desc_bus = tx_dma;
++
++ if (tx_desc_base_addr & 0xF)
++ return 0;
++
++ tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr;
++
++ for (index = 0; index < tx_desc_num; index++) {
++ titan_ge_port->tx_dma_array[index] =
++ (dma_addr_t) titan_ge_tx_desc_bus;
++ titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc);
++ tx_desc[index].cmd_sts = 0x0000;
++ tx_desc[index].buffer_len = 0;
++ tx_desc[index].buffer_addr = 0x00000000;
++ titan_ge_port->tx_skb[index] = NULL;
++ }
++
++ titan_ge_port->tx_curr_desc_q = 0;
++ titan_ge_port->tx_used_desc_q = 0;
++
++ titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr;
++ titan_ge_port->tx_desc_area_size =
++ tx_desc_num * sizeof(titan_ge_tx_desc);
++
++ titan_ge_port->tx_dma = tx_dma;
++ return TITAN_OK;
++}
++
++/*
++ * Initialize the device as an Ethernet device
++ */
++static int __init titan_ge_probe(struct device *device)
++{
++ titan_ge_port_info *titan_ge_eth;
++ struct net_device *netdev;
++ int port = to_platform_device(device)->id;
++ int err;
++
++ netdev = alloc_etherdev(sizeof(titan_ge_port_info));
++ if (!netdev) {
++ err = -ENODEV;
++ goto out;
++ }
++
++ netdev->open = titan_ge_open;
++ netdev->stop = titan_ge_stop;
++ netdev->hard_start_xmit = titan_ge_start_xmit;
++ netdev->get_stats = titan_ge_get_stats;
++ netdev->set_multicast_list = titan_ge_set_multi;
++ netdev->set_mac_address = titan_ge_set_mac_address;
++
++ /* Tx timeout */
++ netdev->tx_timeout = titan_ge_tx_timeout;
++ netdev->watchdog_timeo = 2 * HZ;
++
++ /* Set these to very high values */
++ netdev->poll = titan_ge_poll;
++ netdev->weight = 64;
++
++ netdev->tx_queue_len = TITAN_GE_TX_QUEUE;
++ netif_carrier_off(netdev);
++ netdev->base_addr = 0;
++
++ netdev->change_mtu = titan_ge_change_mtu;
++
++ titan_ge_eth = netdev_priv(netdev);
++ /* Allocation of memory for the driver structures */
++
++ titan_ge_eth->port_num = port;
++
++ /* Configure the Tx timeout handler */
++ INIT_WORK(&titan_ge_eth->tx_timeout_task,
++ (void (*)(void *)) titan_ge_tx_timeout_task, netdev);
++
++ spin_lock_init(&titan_ge_eth->lock);
++
++ /* set MAC addresses */
++ memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6);
++ netdev->dev_addr[5] += port;
++
++ err = register_netdev(netdev);
++
++ if (err)
++ goto out_free_netdev;
++
++ printk(KERN_NOTICE
++ "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
++ netdev->name, port, netdev->dev_addr[0],
++ netdev->dev_addr[1], netdev->dev_addr[2],
++ netdev->dev_addr[3], netdev->dev_addr[4],
++ netdev->dev_addr[5]);
++
++ printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n");
++
++ return 0;
++
++out_free_netdev:
++ kfree(netdev);
++
++out:
++ return err;
++}
++
++static void __devexit titan_device_remove(struct device *device)
++{
++}
++
++/*
++ * Reset the Ethernet port
++ */
++static void titan_ge_port_reset(unsigned int port_num)
++{
++ unsigned int reg_data;
++
++ /* Stop the Tx port activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x0001);
++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ /* Stop the Rx port activity */
++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12));
++ reg_data &= ~(0x0001);
++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
++ (port_num << 12)), reg_data);
++
++ return;
++}
++
++/*
++ * Return the Tx desc after use by the XDMA
++ */
++static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port)
++{
++ int tx_desc_used;
++ struct sk_buff *skb;
++
++ tx_desc_used = titan_ge_eth->tx_used_desc_q;
++
++ /* return right away */
++ if (tx_desc_used == titan_ge_eth->tx_curr_desc_q)
++ return TITAN_ERROR;
++
++ /* Now the critical stuff */
++ skb = titan_ge_eth->tx_skb[tx_desc_used];
++
++ dev_kfree_skb_any(skb);
++
++ titan_ge_eth->tx_skb[tx_desc_used] = NULL;
++ titan_ge_eth->tx_used_desc_q =
++ (tx_desc_used + 1) % TITAN_GE_TX_QUEUE;
++
++ return 0;
++}
++
++/*
++ * Coalescing for the Tx path
++ */
++static unsigned long titan_ge_tx_coal(unsigned long delay, int port)
++{
++ unsigned long rx_delay;
++
++ rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING);
++ delay = (delay << 16) | rx_delay;
++
++ TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
++ TITAN_GE_WRITE(0x5038, delay);
++
++ return delay;
++}
++
++static struct device_driver titan_soc_driver = {
++ .name = titan_string,
++ .bus = &platform_bus_type,
++ .probe = titan_ge_probe,
++ .remove = __devexit_p(titan_device_remove),
++};
++
++static void titan_platform_release (struct device *device)
++{
++ struct platform_device *pldev;
++
++ /* free device */
++ pldev = to_platform_device (device);
++ kfree (pldev);
++}
++
++/*
++ * Register the Titan GE with the kernel
++ */
++static int __init titan_ge_init_module(void)
++{
++ struct platform_device *pldev;
++ unsigned int version, device;
++ int i;
++
++ printk(KERN_NOTICE
++ "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n");
++
++ titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE);
++ if (!titan_ge_base) {
++ printk("Mapping Titan GE failed\n");
++ goto out;
++ }
++
++ device = TITAN_GE_READ(TITAN_GE_DEVICE_ID);
++ version = (device & 0x000f0000) >> 16;
++ device &= 0x0000ffff;
++
++ printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version);
++
++#ifdef TITAN_RX_RING_IN_SRAM
++ titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE,
++ TITAN_SRAM_SIZE);
++ if (!titan_ge_sram) {
++ printk("Mapping Titan SRAM failed\n");
++ goto out_unmap_ge;
++ }
++#endif
++
++ if (driver_register(&titan_soc_driver)) {
++ printk(KERN_ERR "Driver registration failed\n");
++ goto out_unmap_sram;
++ }
++
++ for (i = 0; i < 3; i++) {
++ titan_ge_device[i] = NULL;
++
++ if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL)))
++ continue;
++
++ memset (pldev, 0, sizeof (*pldev));
++ pldev->name = titan_string;
++ pldev->id = i;
++ pldev->dev.release = titan_platform_release;
++ titan_ge_device[i] = pldev;
++
++ if (platform_device_register (pldev)) {
++ kfree (pldev);
++ titan_ge_device[i] = NULL;
++ continue;
++ }
++
++ if (!pldev->dev.driver) {
++ /*
++ * The driver was not bound to this device, there was
++ * no hardware at this address. Unregister it, as the
++ * release fuction will take care of freeing the
++ * allocated structure
++ */
++ titan_ge_device[i] = NULL;
++ platform_device_unregister (pldev);
++ }
++ }
++
++ return 0;
++
++out_unmap_sram:
++ iounmap((void *)titan_ge_sram);
++
++out_unmap_ge:
++ iounmap((void *)titan_ge_base);
++
++out:
++ return -ENOMEM;
++}
++
++/*
++ * Unregister the Titan GE from the kernel
++ */
++static void __exit titan_ge_cleanup_module(void)
++{
++ int i;
++
++ driver_unregister(&titan_soc_driver);
++
++ for (i = 0; i < 3; i++) {
++ if (titan_ge_device[i]) {
++ platform_device_unregister (titan_ge_device[i]);
++ titan_ge_device[i] = NULL;
++ }
++ }
++
++ iounmap((void *)titan_ge_sram);
++ iounmap((void *)titan_ge_base);
++}
++
++MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
++MODULE_DESCRIPTION("Titan GE Ethernet driver");
++MODULE_LICENSE("GPL");
++
++module_init(titan_ge_init_module);
++module_exit(titan_ge_cleanup_module);
+diff -Nurd linux-2.6.24/drivers/net/titan_ge.h mer-smartq-kernel/drivers/net/titan_ge.h
+--- linux-2.6.24/drivers/net/titan_ge.h 1970-01-01 01:00:00.000000000 +0100
++++ mer-smartq-kernel/drivers/net/titan_ge.h 2009-11-17 12:13:31.000000000 +0100
+@@ -0,0 +1,415 @@
++#ifndef _TITAN_GE_H_
++#define _TITAN_GE_H_
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <asm/byteorder.h>
++
++/*
++ * These functions should be later moved to a more generic location since there
++ * will be others accessing it also
++ */
++
++/*
++ * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in
++ * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5
++ * register.
++ */
++
++#define TITAN_GE_BASE 0xfe000000UL
++#define TITAN_GE_SIZE 0x10000UL
++
++extern unsigned long titan_ge_base;
++
++#define TITAN_GE_WRITE(offset, data) \
++ *(volatile u32 *)(titan_ge_base + (offset)) = (data)
++
++#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset))
++
++#ifndef msec_delay
++#define msec_delay(x) do { if(in_interrupt()) { \
++ /* Don't mdelay in interrupt context! */ \
++ BUG(); \
++ } else { \
++ set_current_state(TASK_UNINTERRUPTIBLE); \
++ schedule_timeout((x * HZ)/1000); \
++ } } while(0)
++#endif
++
++#define TITAN_GE_PORT_0
++
++#define TITAN_SRAM_BASE ((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4)
++#define TITAN_SRAM_SIZE 0x2000UL
++
++/*
++ * We may need these constants
++ */
++#define TITAN_BIT0 0x00000001
++#define TITAN_BIT1 0x00000002
++#define TITAN_BIT2 0x00000004
++#define TITAN_BIT3 0x00000008
++#define TITAN_BIT4 0x00000010
++#define TITAN_BIT5 0x00000020
++#define TITAN_BIT6 0x00000040
++#define TITAN_BIT7 0x00000080
++#define TITAN_BIT8 0x00000100
++#define TITAN_BIT9 0x00000200
++#define TITAN_BIT10 0x00000400
++#define TITAN_BIT11 0x00000800
++#define TITAN_BIT12 0x00001000
++#define TITAN_BIT13 0x00002000
++#define TITAN_BIT14 0x00004000
++#define TITAN_BIT15 0x00008000
++#define TITAN_BIT16 0x00010000
++#define TITAN_BIT17 0x00020000
++#define TITAN_BIT18 0x00040000
++#define TITAN_BIT19 0x00080000
++#define TITAN_BIT20 0x00100000
++#define TITAN_BIT21 0x00200000
++#define TITAN_BIT22 0x00400000
++#define TITAN_BIT23 0x00800000
++#define TITAN_BIT24 0x01000000
++#define TITAN_BIT25 0x02000000
++#define TITAN_BIT26 0x04000000
++#define TITAN_BIT27 0x08000000
++#define TITAN_BIT28 0x10000000
++#define TITAN_BIT29 0x20000000
++#define TITAN_BIT30 0x40000000
++#define TITAN_BIT31 0x80000000
++
++/* Flow Control */
++#define TITAN_GE_FC_NONE 0x0
++#define TITAN_GE_FC_FULL 0x1
++#define TITAN_GE_FC_TX_PAUSE 0x2
++#define TITAN_GE_FC_RX_PAUSE 0x3
++
++/* Duplex Settings */
++#define TITAN_GE_FULL_DUPLEX 0x1
++#define TITAN_GE_HALF_DUPLEX 0x2
++
++/* Speed settings */
++#define TITAN_GE_SPEED_1000 0x1
++#define TITAN_GE_SPEED_100 0x2
++#define TITAN_GE_SPEED_10 0x3
++
++/* Debugging info only */
++#undef TITAN_DEBUG
++
++/* Keep the rings in the Titan's SSRAM */
++#define TITAN_RX_RING_IN_SRAM
++
++#ifdef CONFIG_64BIT
++#define TITAN_GE_IE_MASK 0xfffffffffb001b64
++#define TITAN_GE_IE_STATUS 0xfffffffffb001b60
++#else
++#define TITAN_GE_IE_MASK 0xfb001b64
++#define TITAN_GE_IE_STATUS 0xfb001b60
++#endif
++
++/* Support for Jumbo Frames */
++#undef TITAN_GE_JUMBO_FRAMES
++
++/* Rx buffer size */
++#ifdef TITAN_GE_JUMBO_FRAMES
++#define TITAN_GE_JUMBO_BUFSIZE 9080
++#else
++#define TITAN_GE_STD_BUFSIZE 1580
++#endif
++
++/*
++ * Tx and Rx Interrupt Coalescing parameter. These values are
++ * for 1 Ghz processor. Rx coalescing can be taken care of
++ * by NAPI. NAPI is adaptive and hence useful. Tx coalescing
++ * is not adaptive. Hence, these values need to be adjusted
++ * based on load, CPU speed etc.
++ */
++#define TITAN_GE_RX_COAL 150
++#define TITAN_GE_TX_COAL 300
++
++#if defined(__BIG_ENDIAN)
++
++/* Define the Rx descriptor */
++typedef struct eth_rx_desc {
++ u32 reserved; /* Unused */
++ u32 buffer_addr; /* CPU buffer address */
++ u32 cmd_sts; /* Command and Status */
++ u32 buffer; /* XDMA buffer address */
++} titan_ge_rx_desc;
++
++/* Define the Tx descriptor */
++typedef struct eth_tx_desc {
++ u16 cmd_sts; /* Command, Status and Buffer count */
++ u16 buffer_len; /* Length of the buffer */
++ u32 buffer_addr; /* Physical address of the buffer */
++} titan_ge_tx_desc;
++
++#elif defined(__LITTLE_ENDIAN)
++
++/* Define the Rx descriptor */
++typedef struct eth_rx_desc {
++ u32 buffer_addr; /* CPU buffer address */
++ u32 reserved; /* Unused */
++ u32 buffer; /* XDMA buffer address */
++ u32 cmd_sts; /* Command and Status */
++} titan_ge_rx_desc;
++
++/* Define the Tx descriptor */
++typedef struct eth_tx_desc {
++ u32 buffer_addr; /* Physical address of the buffer */
++ u16 buffer_len; /* Length of the buffer */
++ u16 cmd_sts; /* Command, Status and Buffer count */
++} titan_ge_tx_desc;
++#endif
++
++/* Default Tx Queue Size */
++#define TITAN_GE_TX_QUEUE 128
++#define TITAN_TX_RING_BYTES (TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc))
++
++/* Default Rx Queue Size */
++#define TITAN_GE_RX_QUEUE 64
++#define TITAN_RX_RING_BYTES (TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc))
++
++/* Packet Structure */
++typedef struct _pkt_info {
++ unsigned int len;
++ unsigned int cmd_sts;
++ unsigned int buffer;
++ struct sk_buff *skb;
++ unsigned int checksum;
++} titan_ge_packet;
++
++
++#define PHYS_CNT 3
++
++/* Titan Port specific data structure */
++typedef struct _eth_port_ctrl {
++ unsigned int port_num;
++ u8 port_mac_addr[6];
++
++ /* Rx descriptor pointers */
++ int rx_curr_desc_q, rx_used_desc_q;
++
++ /* Tx descriptor pointers */
++ int tx_curr_desc_q, tx_used_desc_q;
++
++ /* Rx descriptor area */
++ volatile titan_ge_rx_desc *rx_desc_area;
++ unsigned int rx_desc_area_size;
++ struct sk_buff* rx_skb[TITAN_GE_RX_QUEUE];
++
++ /* Tx Descriptor area */
++ volatile titan_ge_tx_desc *tx_desc_area;
++ unsigned int tx_desc_area_size;
++ struct sk_buff* tx_skb[TITAN_GE_TX_QUEUE];
++
++ /* Timeout task */
++ struct work_struct tx_timeout_task;
++
++ /* DMA structures and handles */
++ dma_addr_t tx_dma;
++ dma_addr_t rx_dma;
++ dma_addr_t tx_dma_array[TITAN_GE_TX_QUEUE];
++
++ /* Device lock */
++ spinlock_t lock;
++
++ unsigned int tx_ring_skbs;
++ unsigned int rx_ring_size;
++ unsigned int tx_ring_size;
++ unsigned int rx_ring_skbs;
++
++ struct net_device_stats stats;
++
++ /* Tx and Rx coalescing */
++ unsigned long rx_int_coal;
++ unsigned long tx_int_coal;
++
++ /* Threshold for replenishing the Rx and Tx rings */
++ unsigned int tx_threshold;
++ unsigned int rx_threshold;
++
++ /* NAPI work limit */
++ unsigned int rx_work_limit;
++} titan_ge_port_info;
++
++/* Titan specific constants */
++#define TITAN_ETH_PORT_IRQ 3
++
++/* Max Rx buffer */
++#define TITAN_GE_MAX_RX_BUFFER 65536
++
++/* Tx and Rx Error */
++#define TITAN_GE_ERROR
++
++/* Rx Descriptor Command and Status */
++
++#define TITAN_GE_RX_CRC_ERROR TITAN_BIT27 /* crc error */
++#define TITAN_GE_RX_OVERFLOW_ERROR TITAN_BIT15 /* overflow */
++#define TITAN_GE_RX_BUFFER_OWNED TITAN_BIT21 /* buffer ownership */
++#define TITAN_GE_RX_STP TITAN_BIT31 /* start of packet */
++#define TITAN_GE_RX_BAM TITAN_BIT30 /* broadcast address match */
++#define TITAN_GE_RX_PAM TITAN_BIT28 /* physical address match */
++#define TITAN_GE_RX_LAFM TITAN_BIT29 /* logical address filter match */
++#define TITAN_GE_RX_VLAN TITAN_BIT26 /* virtual lans */
++#define TITAN_GE_RX_PERR TITAN_BIT19 /* packet error */
++#define TITAN_GE_RX_TRUNC TITAN_BIT20 /* packet size greater than 32 buffers */
++
++/* Tx Descriptor Command */
++#define TITAN_GE_TX_BUFFER_OWNED TITAN_BIT5 /* buffer ownership */
++#define TITAN_GE_TX_ENABLE_INTERRUPT TITAN_BIT15 /* Interrupt Enable */
++
++/* Return Status */
++#define TITAN_OK 0x1 /* Good Status */
++#define TITAN_ERROR 0x2 /* Error Status */
++
++/* MIB specific register offset */
++#define TITAN_GE_MSTATX_STATS_BASE_LOW 0x0800 /* MSTATX COUNTL[15:0] */
++#define TITAN_GE_MSTATX_STATS_BASE_MID 0x0804 /* MSTATX COUNTM[15:0] */
++#define TITAN_GE_MSTATX_STATS_BASE_HI 0x0808 /* MSTATX COUNTH[7:0] */
++#define TITAN_GE_MSTATX_CONTROL 0x0828 /* MSTATX Control */
++#define TITAN_GE_MSTATX_VARIABLE_SELECT 0x082C /* MSTATX Variable Select */
++
++/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */
++#define TITAN_GE_MSTATX_RXFRAMESOK 0x0040
++#define TITAN_GE_MSTATX_RXOCTETSOK 0x0050
++#define TITAN_GE_MSTATX_RXFRAMES 0x0060
++#define TITAN_GE_MSTATX_RXOCTETS 0x0070
++#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK 0x0080
++#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK 0x0090
++#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK 0x00A0
++#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK 0x00B0
++#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK 0x00C0
++#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK 0x00D0
++#define TITAN_GE_MSTATX_RXFCSERROR 0x00E0
++#define TITAN_GE_MSTATX_RXALIGNMENTERROR 0x00F0
++#define TITAN_GE_MSTATX_RXSYMBOLERROR 0x0100
++#define TITAN_GE_MSTATX_RXLAYER1ERROR 0x0110
++#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR 0x0120
++#define TITAN_GE_MSTATX_RXLONGLENGTHERROR 0x0130
++#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR 0x0140
++#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR 0x0150
++#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR 0x0160
++#define TITAN_GE_MSTATX_RXFRAMES64OCTETS 0x0170
++#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS 0x0180
++#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS 0x0190
++#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS 0x01A0
++#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS 0x01B0
++#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS 0x01C0
++#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE 0x01D0
++#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED 0x01E0
++#define TITAN_GE_MSTATX_RXVARIABLE 0x01F0
++#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED 0x0200
++#define TITAN_GE_MSTATX_UNICASTFILTERED 0x0210
++#define TITAN_GE_MSTATX_MULTICASTFILTERED 0x0220
++#define TITAN_GE_MSTATX_BROADCASTFILTERED 0x0230
++#define TITAN_GE_MSTATX_HASHFILTERED 0x0240
++#define TITAN_GE_MSTATX_TXFRAMESOK 0x0250
++#define TITAN_GE_MSTATX_TXOCTETSOK 0x0260
++#define TITAN_GE_MSTATX_TXOCTETS 0x0270
++#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK 0x0280
++#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK 0x0290
++#define TITAN_GE_MSTATX_TXFCSERROR 0x02A0
++#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR 0x02B0
++#define TITAN_GE_MSTATX_TXLONGLENGTHERROR 0x02C0
++#define TITAN_GE_MSTATX_TXSYSTEMERROR 0x02D0
++#define TITAN_GE_MSTATX_TXMACERROR 0x02E0
++#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR 0x02F0
++#define TITAN_GE_MSTATX_TXSQETESTERROR 0x0300
++#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK 0x0310
++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK 0x0320
++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK 0x0330
++#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED 0x0340
++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED 0x0350
++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED 0x0360
++#define TITAN_GE_MSTATX_TXFRAMES64OCTETS 0x0370
++#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS 0x0380
++#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS 0x0390
++#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS 0x03A0
++#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS 0x03B0
++#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS 0x03C0
++#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE 0x03D0
++#define TITAN_GE_MSTATX_TXVARIABLE 0x03E0
++#define TITAN_GE_MSTATX_RXSYSTEMERROR 0x03F0
++#define TITAN_GE_MSTATX_SINGLECOLLISION 0x0400
++#define TITAN_GE_MSTATX_MULTIPLECOLLISION 0x0410
++#define TITAN_GE_MSTATX_DEFERREDXMISSIONS 0x0420
++#define TITAN_GE_MSTATX_LATECOLLISIONS 0x0430
++#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS 0x0440
++
++/* Interrupt specific defines */
++#define TITAN_GE_DEVICE_ID 0x0000 /* Device ID */
++#define TITAN_GE_RESET 0x0004 /* Reset reg */
++#define TITAN_GE_TSB_CTRL_0 0x000C /* TSB Control reg 0 */
++#define TITAN_GE_TSB_CTRL_1 0x0010 /* TSB Control reg 1 */
++#define TITAN_GE_INTR_GRP0_STATUS 0x0040 /* General Interrupt Group 0 Status */
++#define TITAN_GE_INTR_XDMA_CORE_A 0x0048 /* XDMA Channel Interrupt Status, Core A*/
++#define TITAN_GE_INTR_XDMA_CORE_B 0x004C /* XDMA Channel Interrupt Status, Core B*/
++#define TITAN_GE_INTR_XDMA_IE 0x0058 /* XDMA Channel Interrupt Enable */
++#define TITAN_GE_SDQPF_ECC_INTR 0x480C /* SDQPF ECC Interrupt Status */
++#define TITAN_GE_SDQPF_RXFIFO_CTL 0x4828 /* SDQPF RxFifo Control and Interrupt Enb*/
++#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C /* SDQPF RxFifo Interrupt Status */
++#define TITAN_GE_SDQPF_TXFIFO_CTL 0x4928 /* SDQPF TxFifo Control and Interrupt Enb*/
++#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C /* SDQPF TxFifo Interrupt Status */
++#define TITAN_GE_SDQPF_RXFIFO_0 0x4840 /* SDQPF RxFIFO Enable */
++#define TITAN_GE_SDQPF_TXFIFO_0 0x4940 /* SDQPF TxFIFO Enable */
++#define TITAN_GE_XDMA_CONFIG 0x5000 /* XDMA Global Configuration */
++#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010 /* XDMA Interrupt Summary */
++#define TITAN_GE_XDMA_BUFADDRPRE 0x5018 /* XDMA Buffer Address Prefix */
++#define TITAN_GE_XDMA_DESCADDRPRE 0x501C /* XDMA Descriptor Address Prefix */
++#define TITAN_GE_XDMA_PORTWEIGHT 0x502C /* XDMA Port Weight Configuration */
++
++/* Rx MAC defines */
++#define TITAN_GE_RMAC_CONFIG_1 0x1200 /* RMAC Configuration 1 */
++#define TITAN_GE_RMAC_CONFIG_2 0x1204 /* RMAC Configuration 2 */
++#define TITAN_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */
++#define TITAN_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */
++#define TITAN_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */
++#define TITAN_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */
++#define TITAN_GE_RMAC_LINK_CONFIG 0x1218 /* RMAC Link Configuration */
++
++/* Tx MAC defines */
++#define TITAN_GE_TMAC_CONFIG_1 0x1240 /* TMAC Configuration 1 */
++#define TITAN_GE_TMAC_CONFIG_2 0x1244 /* TMAC Configuration 2 */
++#define TITAN_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */
++#define TITAN_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */
++#define TITAN_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */
++#define TITAN_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */
++#define TITAN_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */
++#define TITAN_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */
++#define TITAN_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */
++#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */
++
++/* GMII register */
++#define TITAN_GE_GMII_INTERRUPT_STATUS 0x1348 /* GMII Interrupt Status */
++#define TITAN_GE_GMII_CONFIG_GENERAL 0x134C /* GMII Configuration General */
++#define TITAN_GE_GMII_CONFIG_MODE 0x1350 /* GMII Configuration Mode */
++
++/* Tx and Rx XDMA defines */
++#define TITAN_GE_INT_COALESCING 0x5030 /* Interrupt Coalescing */
++#define TITAN_GE_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */
++#define TITAN_GE_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */
++#define TITAN_GE_GDI_INTERRUPT_ENABLE 0x5050 /* IE for the GDI Errors */
++#define TITAN_GE_CHANNEL0_PACKET 0x5060 /* Channel 0 Packet count */
++#define TITAN_GE_CHANNEL0_BYTE 0x5064 /* Channel 0 Byte count */
++#define TITAN_GE_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */
++#define TITAN_GE_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */
++
++/* AFX (Address Filter Exact) register offsets for Slice 0 */
++#define TITAN_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/
++#define TITAN_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/
++#define TITAN_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */
++#define TITAN_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */
++#define TITAN_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */
++#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */
++#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */
++#define TITAN_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */
++
++/* Traffic Groomer block */
++#define TITAN_GE_TRTG_CONFIG 0x1000 /* TRTG Config */
++
++#endif /* _TITAN_GE_H_ */
++
+diff -Nurd linux-2.6.24/drivers/net/titan_mdio.c mer-smartq-kernel/drivers/net/titan_mdio.c
+--- linux-2.6.24/drivers/net/titan_mdio.c 1970-01-01 01:00:00.000000000 +0100
++++ mer-smartq-kernel/drivers/net/titan_mdio.c 2009-11-17 12:13:31.000000000 +0100
+@@ -0,0 +1,217 @@
++/*
++ * drivers/net/titan_mdio.c - Driver for Titan ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY
++ * on the Titan. No support for the TBI as yet.
++ *
++ */
++
++#include "titan_mdio.h"
++
++#define MDIO_DEBUG
++
++/*
++ * Local constants
++ */
++#define MAX_CLKA 1023
++#define MAX_PHY_DEV 31
++#define MAX_PHY_REG 31
++#define WRITEADDRS_OPCODE 0x0
++#define READ_OPCODE 0x2
++#define WRITE_OPCODE 0x1
++#define MAX_MDIO_POLL 100
++
++/*
++ * Titan MDIO and SCMB registers
++ */
++#define TITAN_GE_SCMB_CONTROL 0x01c0 /* SCMB Control */
++#define TITAN_GE_SCMB_CLKA 0x01c4 /* SCMB Clock A */
++#define TITAN_GE_MDIO_COMMAND 0x01d0 /* MDIO Command */
++#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS 0x01d4 /* MDIO Device and Port addrs */
++#define TITAN_GE_MDIO_DATA 0x01d8 /* MDIO Data */
++#define TITAN_GE_MDIO_INTERRUPTS 0x01dC /* MDIO Interrupts */
++
++/*
++ * Function to poll the MDIO
++ */
++static int titan_ge_mdio_poll(void)
++{
++ int i, val;
++
++ for (i = 0; i < MAX_MDIO_POLL; i++) {
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++
++ if (!(val & 0x8000))
++ return TITAN_GE_MDIO_GOOD;
++ }
++
++ return TITAN_GE_MDIO_ERROR;
++}
++
++
++/*
++ * Initialize and configure the MDIO
++ */
++int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio)
++{
++ unsigned long val;
++
++ /* Reset the SCMB and program into MDIO mode*/
++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000);
++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000);
++
++ /* CLK A */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA);
++ val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val);
++
++ /* Preamble Suppresion */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++ /* MDIO mode */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++ return TITAN_GE_MDIO_GOOD;
++}
++
++/*
++ * Set the PHY address in indirect mode
++ */
++int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr)
++{
++ volatile unsigned long val;
++
++ /* Setup the PHY device */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++ /* Write the new address */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++ return TITAN_GE_MDIO_GOOD;
++}
++
++/*
++ * Read the MDIO register. This is what the individual parametes mean:
++ *
++ * dev_addr : PHY ID
++ * reg_addr : register offset
++ *
++ * See the spec for the Titan MAC. We operate in the Direct Mode.
++ */
++
++#define MAX_RETRIES 2
++
++int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata)
++{
++ volatile unsigned long val;
++ int retries = 0;
++
++ /* Setup the PHY device */
++
++again:
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++ val |= 0x4000;
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++ udelay(30);
++
++ /* Issue the read command */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++ udelay(30);
++
++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++ return TITAN_GE_MDIO_ERROR;
++
++ *pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA);
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
++
++ udelay(30);
++
++ if (val & 0x2) {
++ if (retries == MAX_RETRIES)
++ return TITAN_GE_MDIO_ERROR;
++ else {
++ retries++;
++ goto again;
++ }
++ }
++
++ return TITAN_GE_MDIO_GOOD;
++}
++
++/*
++ * Write to the MDIO register
++ *
++ * dev_addr : PHY ID
++ * reg_addr : register that needs to be written to
++ *
++ */
++int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data)
++{
++ volatile unsigned long val;
++
++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++ return TITAN_GE_MDIO_ERROR;
++
++ /* Setup the PHY device */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++ val |= 0x4000;
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++ udelay(30);
++
++ /* Setup the data to write */
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data);
++
++ udelay(30);
++
++ /* Issue the write command */
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++ val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300));
++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++ udelay(30);
++
++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++ return TITAN_GE_MDIO_ERROR;
++
++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
++ if (val & 0x2)
++ return TITAN_GE_MDIO_ERROR;
++
++ return TITAN_GE_MDIO_GOOD;
++}
++
+diff -Nurd linux-2.6.24/drivers/net/titan_mdio.h mer-smartq-kernel/drivers/net/titan_mdio.h
+--- linux-2.6.24/drivers/net/titan_mdio.h 1970-01-01 01:00:00.000000000 +0100
++++ mer-smartq-kernel/drivers/net/titan_mdio.h 2009-11-17 12:13:31.000000000 +0100
+@@ -0,0 +1,56 @@
++/*
++ * MDIO used to interact with the PHY when using GMII/MII
++ */
++#ifndef _TITAN_MDIO_H
++#define _TITAN_MDIO_H
++
++#include <linux/netdevice.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include "titan_ge.h"
++
++
++#define TITAN_GE_MDIO_ERROR (-9000)
++#define TITAN_GE_MDIO_GOOD 0
++
++#define TITAN_GE_MDIO_BASE titan_ge_base
++
++#define TITAN_GE_MDIO_READ(offset) \
++ *(volatile u32 *)(titan_ge_base + (offset))
++
++#define TITAN_GE_MDIO_WRITE(offset, data) \
++ *(volatile u32 *)(titan_ge_base + (offset)) = (data)
++
++
++/* GMII specific registers */
++#define TITAN_GE_MARVEL_PHY_ID 0x00
++#define TITAN_PHY_AUTONEG_ADV 0x04
++#define TITAN_PHY_LP_ABILITY 0x05
++#define TITAN_GE_MDIO_MII_CTRL 0x09
++#define TITAN_GE_MDIO_MII_EXTENDED 0x0f
++#define TITAN_GE_MDIO_PHY_CTRL 0x10
++#define TITAN_GE_MDIO_PHY_STATUS 0x11
++#define TITAN_GE_MDIO_PHY_IE 0x12
++#define TITAN_GE_MDIO_PHY_IS 0x13
++#define TITAN_GE_MDIO_PHY_LED 0x18
++#define TITAN_GE_MDIO_PHY_LED_OVER 0x19
++#define PHY_ANEG_TIME_WAIT 45 /* 45 seconds wait time */
++
++/*
++ * MDIO Config Structure
++ */
++typedef struct {
++ unsigned int clka;
++ int mdio_spre;
++ int mdio_mode;
++} titan_ge_mdio_config;
++
++/*
++ * Function Prototypes
++ */
++int titan_ge_mdio_setup(titan_ge_mdio_config *);
++int titan_ge_mdio_inaddrs(int, int);
++int titan_ge_mdio_read(int, int, unsigned int *);
++int titan_ge_mdio_write(int, int, unsigned int);
++
++#endif /* _TITAN_MDIO_H */
+diff -Nurd linux-2.6.24/drivers/scsi/NCR53C9x.h mer-smartq-kernel/drivers/scsi/NCR53C9x.h
+--- linux-2.6.24/drivers/scsi/NCR53C9x.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/drivers/scsi/NCR53C9x.h 2009-11-17 12:13:32.000000000 +0100
+@@ -144,12 +144,7 @@
+
+ #ifndef MULTIPLE_PAD_SIZES
+
+-#ifdef CONFIG_CPU_HAS_WB
+-#include <asm/wbflush.h>
+-#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
+-#else
+-#define esp_write(__reg, __val) ((__reg) = (__val))
+-#endif
++#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0)
+ #define esp_read(__reg) (__reg)
+
+ struct ESP_regs {
+diff -Nurd linux-2.6.24/include/asm-mips/asmmacro.h mer-smartq-kernel/include/asm-mips/asmmacro.h
+--- linux-2.6.24/include/asm-mips/asmmacro.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/asmmacro.h 2009-11-17 12:13:38.000000000 +0100
+@@ -35,6 +35,16 @@
+ mtc0 \reg, CP0_TCSTATUS
+ _ehb
+ .endm
++#elif defined(CONFIG_CPU_MIPSR2)
++ .macro local_irq_enable reg=t0
++ ei
++ irq_enable_hazard
++ .endm
++
++ .macro local_irq_disable reg=t0
++ di
++ irq_disable_hazard
++ .endm
+ #else
+ .macro local_irq_enable reg=t0
+ mfc0 \reg, CP0_STATUS
+diff -Nurd linux-2.6.24/include/asm-mips/atomic.h mer-smartq-kernel/include/asm-mips/atomic.h
+--- linux-2.6.24/include/asm-mips/atomic.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/atomic.h 2009-11-17 12:13:38.000000000 +0100
+@@ -283,10 +283,10 @@
+ " beqz %0, 2f \n"
+ " subu %0, %1, %3 \n"
+ " .set reorder \n"
+- "1: \n"
+ " .subsection 2 \n"
+ "2: b 1b \n"
+ " .previous \n"
++ "1: \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+@@ -664,10 +664,10 @@
+ " beqz %0, 2f \n"
+ " dsubu %0, %1, %3 \n"
+ " .set reorder \n"
+- "1: \n"
+ " .subsection 2 \n"
+ "2: b 1b \n"
+ " .previous \n"
++ "1: \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+diff -Nurd linux-2.6.24/include/asm-mips/byteorder.h mer-smartq-kernel/include/asm-mips/byteorder.h
+--- linux-2.6.24/include/asm-mips/byteorder.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/byteorder.h 2009-11-17 12:13:38.000000000 +0100
+@@ -43,9 +43,8 @@
+ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+ {
+ __asm__(
+- " dsbh %0, %1 \n"
+- " dshd %0, %0 \n"
+- " drotr %0, %0, 32 \n"
++ " dsbh %0, %1\n"
++ " dshd %0, %0"
+ : "=r" (x)
+ : "r" (x));
+
+diff -Nurd linux-2.6.24/include/asm-mips/cacheflush.h mer-smartq-kernel/include/asm-mips/cacheflush.h
+--- linux-2.6.24/include/asm-mips/cacheflush.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/cacheflush.h 2009-11-17 12:13:38.000000000 +0100
+@@ -63,8 +63,22 @@
+ }
+
+ extern void (*flush_icache_range)(unsigned long start, unsigned long end);
+-#define flush_cache_vmap(start, end) flush_cache_all()
+-#define flush_cache_vunmap(start, end) flush_cache_all()
++
++extern void (*__flush_cache_vmap)(void);
++
++static inline void flush_cache_vmap(unsigned long start, unsigned long end)
++{
++ if (cpu_has_dc_aliases)
++ __flush_cache_vmap();
++}
++
++extern void (*__flush_cache_vunmap)(void);
++
++static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
++{
++ if (cpu_has_dc_aliases)
++ __flush_cache_vunmap();
++}
+
+ extern void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+@@ -93,7 +107,7 @@
+ clear_bit(PG_dcache_dirty, &(page)->flags)
+
+ /* Run kernel code uncached, useful for cache probing functions. */
+-unsigned long __init run_uncached(void *func);
++unsigned long run_uncached(void *func);
+
+ extern void *kmap_coherent(struct page *page, unsigned long addr);
+ extern void kunmap_coherent(void);
+diff -Nurd linux-2.6.24/include/asm-mips/cevt-r4k.h mer-smartq-kernel/include/asm-mips/cevt-r4k.h
+--- linux-2.6.24/include/asm-mips/cevt-r4k.h 1970-01-01 01:00:00.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/cevt-r4k.h 2009-11-17 12:13:38.000000000 +0100
+@@ -0,0 +1,46 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Kevin D. Kissell
++ */
++
++/*
++ * Definitions used for common event timer implementation
++ * for MIPS 4K-type processors and their MIPS MT variants.
++ * Avoids unsightly extern declarations in C files.
++ */
++#ifndef __ASM_CEVT_R4K_H
++#define __ASM_CEVT_R4K_H
++
++DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
++
++void mips_event_handler(struct clock_event_device *dev);
++int c0_compare_int_usable(void);
++void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *);
++irqreturn_t c0_compare_interrupt(int, void *);
++
++extern struct irqaction c0_compare_irqaction;
++extern int cp0_timer_irq_installed;
++
++/*
++ * Possibly handle a performance counter interrupt.
++ * Return true if the timer interrupt should not be checked
++ */
++
++static inline int handle_perf_irq(int r2)
++{
++ /*
++ * The performance counter overflow interrupt may be shared with the
++ * timer interrupt (cp0_perfcount_irq < 0). If it is and a
++ * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
++ * and we can't reliably determine if a counter interrupt has also
++ * happened (!r2) then don't check for a timer interrupt.
++ */
++ return (cp0_perfcount_irq < 0) &&
++ perf_irq() == IRQ_HANDLED &&
++ !r2;
++}
++
++#endif /* __ASM_CEVT_R4K_H */
+diff -Nurd linux-2.6.24/include/asm-mips/elf.h mer-smartq-kernel/include/asm-mips/elf.h
+--- linux-2.6.24/include/asm-mips/elf.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/elf.h 2009-11-17 12:13:38.000000000 +0100
+@@ -232,7 +232,7 @@
+ */
+ #ifdef __MIPSEB__
+ #define ELF_DATA ELFDATA2MSB
+-#elif __MIPSEL__
++#elif defined(__MIPSEL__)
+ #define ELF_DATA ELFDATA2LSB
+ #endif
+ #define ELF_ARCH EM_MIPS
+diff -Nurd linux-2.6.24/include/asm-mips/gdb-stub.h mer-smartq-kernel/include/asm-mips/gdb-stub.h
+--- linux-2.6.24/include/asm-mips/gdb-stub.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/gdb-stub.h 2009-11-17 12:13:38.000000000 +0100
+@@ -4,148 +4,33 @@
+ * for more details.
+ *
+ * Copyright (C) 1995 Andreas Busse
+- * Copyright (C) 2003 Ralf Baechle
++ * Copyright (C) 2003, 2008 Ralf Baechle (ralf@linux-mips.org)
++ * Copyright (C) 2008 Wind River Systems, Inc.
++ * written by Ralf Baechle
+ */
+ #ifndef _ASM_GDB_STUB_H
+ #define _ASM_GDB_STUB_H
+
+-
+ /*
+- * important register numbers
++ * GDB interface constants.
+ */
+-
+-#define REG_EPC 37
+-#define REG_FP 72
+-#define REG_SP 29
++#define REG_EPC 37
++#define REG_FP 72
++#define REG_SP 29
+
+ /*
+ * Stack layout for the GDB exception handler
+ * Derived from the stack layout described in asm-mips/stackframe.h
+- *
+- * The first PTRSIZE*6 bytes are argument save space for C subroutines.
+- */
+-#define NUMREGS 90
+-
+-#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
+-#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
+-#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
+-#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
+-#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
+-#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
+-#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
+-#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
+-#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
+-#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
+-#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
+-#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
+-#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
+-#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
+-#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
+-#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
+-#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
+-#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
+-#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
+-#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
+-#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
+-#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
+-#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
+-#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
+-#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
+-#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
+-#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
+-#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
+-#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
+-#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
+-#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
+-#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
+-
+-/*
+- * Saved special registers
+- */
+-#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
+-#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
+-#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
+-#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
+-#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
+-#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
+-
+-/*
+- * Saved floating point registers
+- */
+-#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
+-#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
+-#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
+-#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
+-#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
+-#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
+-#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
+-#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
+-#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
+-#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
+-#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
+-#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
+-#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
+-#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
+-#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
+-#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
+-#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
+-#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
+-#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
+-#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
+-#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
+-#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
+-#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
+-#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
+-#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
+-#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
+-#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
+-#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
+-#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
+-#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
+-#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
+-#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
+-
+-#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
+-#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
+-#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
+-
+-#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
+-
+-/*
+- * Again, CP0 registers
+- */
+-#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
+-#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
+-#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
+-#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
+-#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
+-#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
+-#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
+-#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
+-#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
+-#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
+-#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
+-#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
+-#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
+-#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
+-#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
+-#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
+-
+-#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
+-
+-#ifndef __ASSEMBLY__
+-
+-/*
+- * This is the same as above, but for the high-level
+- * part of the GDB stub.
+ */
+
+ struct gdb_regs {
++#ifdef CONFIG_32BIT
+ /*
+ * Pad bytes for argument save space on the stack
+ * 24/48 Bytes for 32/64 bit code
+ */
+ unsigned long pad0[6];
++#endif
+
+ /*
+ * saved main processor registers
+@@ -159,8 +44,11 @@
+ * Saved special registers
+ */
+ long cp0_status;
+- long lo;
+ long hi;
++ long lo;
++#ifdef CONFIG_CPU_HAS_SMARTMIPS
++ long acx
++#endif
+ long cp0_badvaddr;
+ long cp0_cause;
+ long cp0_epc;
+@@ -183,7 +71,7 @@
+ long dummy; /* unused */
+
+ /*
+- * saved cp0 registers
++ * Saved cp0 registers
+ */
+ long cp0_index;
+ long cp0_random;
+@@ -203,13 +91,8 @@
+ long cp0_prid;
+ };
+
+-/*
+- * Prototypes
+- */
+-
+ extern int kgdb_enabled;
+-void set_debug_traps(void);
+-void set_async_breakpoint(unsigned long *epc);
++extern void set_debug_traps(void);
++extern void set_async_breakpoint(unsigned long *epc);
+
+-#endif /* !__ASSEMBLY__ */
+ #endif /* _ASM_GDB_STUB_H */
+diff -Nurd linux-2.6.24/include/asm-mips/irqflags.h mer-smartq-kernel/include/asm-mips/irqflags.h
+--- linux-2.6.24/include/asm-mips/irqflags.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/irqflags.h 2009-11-17 12:13:38.000000000 +0100
+@@ -38,8 +38,17 @@
+ " .set pop \n"
+ " .endm");
+
++extern void smtc_ipi_replay(void);
++
+ static inline void raw_local_irq_enable(void)
+ {
++#ifdef CONFIG_MIPS_MT_SMTC
++ /*
++ * SMTC kernel needs to do a software replay of queued
++ * IPIs, at the cost of call overhead on each local_irq_enable()
++ */
++ smtc_ipi_replay();
++#endif
+ __asm__ __volatile__(
+ "raw_local_irq_enable"
+ : /* no outputs */
+@@ -47,6 +56,7 @@
+ : "memory");
+ }
+
++
+ /*
+ * For cli() we have to insert nops to make sure that the new value
+ * has actually arrived in the status register before the end of this
+@@ -185,15 +195,14 @@
+ " .set pop \n"
+ " .endm \n");
+
+-extern void smtc_ipi_replay(void);
+
+ static inline void raw_local_irq_restore(unsigned long flags)
+ {
+ unsigned long __tmp1;
+
+-#ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
++#ifdef CONFIG_MIPS_MT_SMTC
+ /*
+- * CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred
++ * SMTC kernel needs to do a software replay of queued
+ * IPIs, at the cost of branch and call overhead on each
+ * local_irq_restore()
+ */
+@@ -208,6 +217,17 @@
+ : "memory");
+ }
+
++static inline void __raw_local_irq_restore(unsigned long flags)
++{
++ unsigned long __tmp1;
++
++ __asm__ __volatile__(
++ "raw_local_irq_restore\t%0"
++ : "=r" (__tmp1)
++ : "0" (flags)
++ : "memory");
++}
++
+ static inline int raw_irqs_disabled_flags(unsigned long flags)
+ {
+ #ifdef CONFIG_MIPS_MT_SMTC
+diff -Nurd linux-2.6.24/include/asm-mips/lasat/serial.h mer-smartq-kernel/include/asm-mips/lasat/serial.h
+--- linux-2.6.24/include/asm-mips/lasat/serial.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/lasat/serial.h 2009-11-17 12:13:38.000000000 +0100
+@@ -4,10 +4,10 @@
+ #define LASAT_BASE_BAUD_100 (7372800 / 16)
+ #define LASAT_UART_REGS_BASE_100 0x1c8b0000
+ #define LASAT_UART_REGS_SHIFT_100 2
+-#define LASATINT_UART_100 8
++#define LASATINT_UART_100 16
+
+ /* * LASAT 200 boards serial configuration */
+ #define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
+ #define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
+ #define LASAT_UART_REGS_SHIFT_200 3
+-#define LASATINT_UART_200 13
++#define LASATINT_UART_200 21
+diff -Nurd linux-2.6.24/include/asm-mips/mach-au1x00/au1000.h mer-smartq-kernel/include/asm-mips/mach-au1x00/au1000.h
+--- linux-2.6.24/include/asm-mips/mach-au1x00/au1000.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mach-au1x00/au1000.h 2009-11-17 12:13:38.000000000 +0100
+@@ -1786,6 +1786,7 @@
+ char *cpu_name;
+ unsigned char cpu_od; /* Set Config[OD] */
+ unsigned char cpu_bclk; /* Enable BCLK switching */
++ unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
+ };
+
+ extern struct cpu_spec cpu_specs[];
+diff -Nurd linux-2.6.24/include/asm-mips/mach-ip27/cpu-feature-overrides.h mer-smartq-kernel/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+--- linux-2.6.24/include/asm-mips/mach-ip27/cpu-feature-overrides.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mach-ip27/cpu-feature-overrides.h 2009-11-17 12:13:38.000000000 +0100
+@@ -34,7 +34,11 @@
+ #define cpu_has_64bits 1
+
+ #define cpu_has_4kex 1
++#define cpu_has_3k_cache 0
++#define cpu_has_6k_cache 0
+ #define cpu_has_4k_cache 1
++#define cpu_has_8k_cache 0
++#define cpu_has_tx39_cache 0
+
+ #define cpu_has_inclusive_pcaches 1
+
+diff -Nurd linux-2.6.24/include/asm-mips/mach-ip27/dma-coherence.h mer-smartq-kernel/include/asm-mips/mach-ip27/dma-coherence.h
+--- linux-2.6.24/include/asm-mips/mach-ip27/dma-coherence.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mach-ip27/dma-coherence.h 2009-11-17 12:13:38.000000000 +0100
+@@ -35,7 +35,7 @@
+
+ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+ {
+- return dma_addr & (0xffUL << 56);
++ return dma_addr & ~(0xffUL << 56);
+ }
+
+ static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+diff -Nurd linux-2.6.24/include/asm-mips/mach-jmr3927/ioremap.h mer-smartq-kernel/include/asm-mips/mach-jmr3927/ioremap.h
+--- linux-2.6.24/include/asm-mips/mach-jmr3927/ioremap.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mach-jmr3927/ioremap.h 2009-11-17 12:13:38.000000000 +0100
+@@ -25,7 +25,7 @@
+ {
+ #define TXX9_DIRECTMAP_BASE 0xff000000ul
+ if (offset >= TXX9_DIRECTMAP_BASE &&
+- offset < TXX9_DIRECTMAP_BASE + 0xf0000)
++ offset < TXX9_DIRECTMAP_BASE + 0xff0000)
+ return (void __iomem *)offset;
+ return NULL;
+ }
+diff -Nurd linux-2.6.24/include/asm-mips/mach-lasat/irq.h mer-smartq-kernel/include/asm-mips/mach-lasat/irq.h
+--- linux-2.6.24/include/asm-mips/mach-lasat/irq.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mach-lasat/irq.h 2009-11-17 12:13:38.000000000 +0100
+@@ -1,7 +1,7 @@
+ #ifndef _ASM_MACH_LASAT_IRQ_H
+ #define _ASM_MACH_LASAT_IRQ_H
+
+-#define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 0)
++#define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
+
+ #define LASAT_IRQ_BASE 8
+ #define LASAT_IRQ_END 23
+diff -Nurd linux-2.6.24/include/asm-mips/mach-pb1x00/pb1200.h mer-smartq-kernel/include/asm-mips/mach-pb1x00/pb1200.h
+--- linux-2.6.24/include/asm-mips/mach-pb1x00/pb1200.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mach-pb1x00/pb1200.h 2009-11-17 12:13:38.000000000 +0100
+@@ -244,7 +244,7 @@
+ PB1200_SD1_INSERT_INT,
+ PB1200_SD1_EJECT_INT,
+
+- PB1200_INT_END (PB1200_INT_BEGIN + 15)
++ PB1200_INT_END = PB1200_INT_BEGIN + 15
+ };
+
+ /* For drivers/pcmcia/au1000_db1x00.c */
+diff -Nurd linux-2.6.24/include/asm-mips/mach-qemu/cpu-feature-overrides.h mer-smartq-kernel/include/asm-mips/mach-qemu/cpu-feature-overrides.h
+--- linux-2.6.24/include/asm-mips/mach-qemu/cpu-feature-overrides.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mach-qemu/cpu-feature-overrides.h 2009-11-17 12:13:38.000000000 +0100
+@@ -12,7 +12,7 @@
+ * QEMU only comes with a hazard-free MIPS32 processor, so things are easy.
+ */
+ #define cpu_has_mips16 0
+-#define cpu_has_divec 0
++#define cpu_has_divec 1
+ #define cpu_has_cache_cdex_p 0
+ #define cpu_has_prefetch 0
+ #define cpu_has_mcheck 0
+diff -Nurd linux-2.6.24/include/asm-mips/mipsregs.h mer-smartq-kernel/include/asm-mips/mipsregs.h
+--- linux-2.6.24/include/asm-mips/mipsregs.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/mipsregs.h 2009-11-17 12:13:38.000000000 +0100
+@@ -1459,7 +1459,7 @@
+ { \
+ unsigned int res; \
+ unsigned int omt; \
+- unsigned int flags; \
++ unsigned long flags; \
+ \
+ local_irq_save(flags); \
+ omt = __dmt(); \
+@@ -1477,7 +1477,7 @@
+ { \
+ unsigned int res; \
+ unsigned int omt; \
+- unsigned int flags; \
++ unsigned long flags; \
+ \
+ local_irq_save(flags); \
+ omt = __dmt(); \
+@@ -1495,7 +1495,7 @@
+ { \
+ unsigned int res; \
+ unsigned int omt; \
+- unsigned int flags; \
++ unsigned long flags; \
+ \
+ local_irq_save(flags); \
+ \
+diff -Nurd linux-2.6.24/include/asm-mips/pgtable-32.h mer-smartq-kernel/include/asm-mips/pgtable-32.h
+--- linux-2.6.24/include/asm-mips/pgtable-32.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/pgtable-32.h 2009-11-17 12:13:38.000000000 +0100
+@@ -57,7 +57,7 @@
+ #define PMD_ORDER 1
+ #define PTE_ORDER 0
+
+-#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
++#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
+ #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+
+ #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
+diff -Nurd linux-2.6.24/include/asm-mips/pgtable.h mer-smartq-kernel/include/asm-mips/pgtable.h
+--- linux-2.6.24/include/asm-mips/pgtable.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/pgtable.h 2009-11-17 12:13:38.000000000 +0100
+@@ -232,9 +232,10 @@
+ static inline pte_t pte_mkyoung(pte_t pte)
+ {
+ pte.pte_low |= _PAGE_ACCESSED;
+- if (pte.pte_low & _PAGE_READ)
++ if (pte.pte_low & _PAGE_READ) {
+ pte.pte_low |= _PAGE_SILENT_READ;
+ pte.pte_high |= _PAGE_SILENT_READ;
++ }
+ return pte;
+ }
+ #else
+diff -Nurd linux-2.6.24/include/asm-mips/rtlx.h mer-smartq-kernel/include/asm-mips/rtlx.h
+--- linux-2.6.24/include/asm-mips/rtlx.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/rtlx.h 2009-11-17 12:13:38.000000000 +0100
+@@ -3,7 +3,7 @@
+ *
+ */
+
+-#ifndef __ASM_RTLX_H
++#ifndef __ASM_RTLX_H_
+ #define __ASM_RTLX_H_
+
+ #include <irq.h>
+@@ -29,13 +29,13 @@
+ extern unsigned int rtlx_write_poll(int index);
+
+ enum rtlx_state {
+- RTLX_STATE_UNUSED,
++ RTLX_STATE_UNUSED = 0,
+ RTLX_STATE_INITIALISED,
+ RTLX_STATE_REMOTE_READY,
+ RTLX_STATE_OPENED
+ };
+
+-#define RTLX_BUFFER_SIZE 1024
++#define RTLX_BUFFER_SIZE 2048
+
+ /* each channel supports read and write.
+ linux (vpe0) reads lx_buffer and writes rt_buffer
+diff -Nurd linux-2.6.24/include/asm-mips/smtc.h mer-smartq-kernel/include/asm-mips/smtc.h
+--- linux-2.6.24/include/asm-mips/smtc.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/smtc.h 2009-11-17 12:13:38.000000000 +0100
+@@ -6,6 +6,7 @@
+ */
+
+ #include <asm/mips_mt.h>
++#include <asm/smtc_ipi.h>
+
+ /*
+ * System-wide SMTC status information
+@@ -38,13 +39,14 @@
+ struct task_struct;
+
+ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
+-
++void self_ipi(struct smtc_ipi *);
+ void smtc_flush_tlb_asid(unsigned long asid);
+-extern int mipsmt_build_cpu_map(int startslot);
+-extern void mipsmt_prepare_cpus(void);
++extern int smtc_build_cpu_map(int startslot);
++extern void smtc_prepare_cpus(int cpus);
+ extern void smtc_smp_finish(void);
+ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
+
++
+ /*
+ * Sharing the TLB between multiple VPEs means that the
+ * "random" index selection function is not allowed to
+diff -Nurd linux-2.6.24/include/asm-mips/sn/mapped_kernel.h mer-smartq-kernel/include/asm-mips/sn/mapped_kernel.h
+--- linux-2.6.24/include/asm-mips/sn/mapped_kernel.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/sn/mapped_kernel.h 2009-11-17 12:13:38.000000000 +0100
+@@ -5,6 +5,8 @@
+ #ifndef __ASM_SN_MAPPED_KERNEL_H
+ #define __ASM_SN_MAPPED_KERNEL_H
+
++#include <linux/mmzone.h>
++
+ /*
+ * Note on how mapped kernels work: the text and data section is
+ * compiled at cksseg segment (LOADADDR = 0xc001c000), and the
+@@ -29,10 +31,8 @@
+ #define MAPPED_ADDR_RO_TO_PHYS(x) (x - REP_BASE)
+ #define MAPPED_ADDR_RW_TO_PHYS(x) (x - REP_BASE - 16777216)
+
+-#define MAPPED_KERN_RO_PHYSBASE(n) \
+- (PLAT_NODE_DATA(n)->kern_vars.kv_ro_baseaddr)
+-#define MAPPED_KERN_RW_PHYSBASE(n) \
+- (PLAT_NODE_DATA(n)->kern_vars.kv_rw_baseaddr)
++#define MAPPED_KERN_RO_PHYSBASE(n) (hub_data(n)->kern_vars.kv_ro_baseaddr)
++#define MAPPED_KERN_RW_PHYSBASE(n) (hub_data(n)->kern_vars.kv_rw_baseaddr)
+
+ #define MAPPED_KERN_RO_TO_PHYS(x) \
+ ((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
+diff -Nurd linux-2.6.24/include/asm-mips/stackframe.h mer-smartq-kernel/include/asm-mips/stackframe.h
+--- linux-2.6.24/include/asm-mips/stackframe.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/stackframe.h 2009-11-17 12:13:39.000000000 +0100
+@@ -288,14 +288,31 @@
+ #ifdef CONFIG_MIPS_MT_SMTC
+ .set mips32r2
+ /*
+- * This may not really be necessary if ints are already
+- * inhibited here.
++ * We need to make sure the read-modify-write
++ * of Status below isn't perturbed by an interrupt
++ * or cross-TC access, so we need to do at least a DMT,
++ * protected by an interrupt-inhibit. But setting IXMT
++ * also creates a few-cycle window where an IPI could
++ * be queued and not be detected before potentially
++ * returning to a WAIT or user-mode loop. It must be
++ * replayed.
++ *
++ * We're in the middle of a context switch, and
++ * we can't dispatch it directly without trashing
++ * some registers, so we'll try to detect this unlikely
++ * case and program a software interrupt in the VPE,
++ * as would be done for a cross-VPE IPI. To accomodate
++ * the handling of that case, we're doing a DVPE instead
++ * of just a DMT here to protect against other threads.
++ * This is a lot of cruft to cover a tiny window.
++ * If you can find a better design, implement it!
++ *
+ */
+ mfc0 v0, CP0_TCSTATUS
+ ori v0, TCSTATUS_IXMT
+ mtc0 v0, CP0_TCSTATUS
+ _ehb
+- DMT 5 # dmt a1
++ DVPE 5 # dvpe a1
+ jal mips_ihb
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ mfc0 a0, CP0_STATUS
+@@ -316,17 +333,50 @@
+ */
+ LONG_L v1, PT_TCSTATUS(sp)
+ _ehb
+- mfc0 v0, CP0_TCSTATUS
++ mfc0 a0, CP0_TCSTATUS
+ andi v1, TCSTATUS_IXMT
+- /* We know that TCStatua.IXMT should be set from above */
+- xori v0, v0, TCSTATUS_IXMT
+- or v0, v0, v1
+- mtc0 v0, CP0_TCSTATUS
+- _ehb
+- andi a1, a1, VPECONTROL_TE
++ bnez v1, 0f
++
++/*
++ * We'd like to detect any IPIs queued in the tiny window
++ * above and request an software interrupt to service them
++ * when we ERET.
++ *
++ * Computing the offset into the IPIQ array of the executing
++ * TC's IPI queue in-line would be tedious. We use part of
++ * the TCContext register to hold 16 bits of offset that we
++ * can add in-line to find the queue head.
++ */
++ mfc0 v0, CP0_TCCONTEXT
++ la a2, IPIQ
++ srl v0, v0, 16
++ addu a2, a2, v0
++ LONG_L v0, 0(a2)
++ beqz v0, 0f
++/*
++ * If we have a queue, provoke dispatch within the VPE by setting C_SW1
++ */
++ mfc0 v0, CP0_CAUSE
++ ori v0, v0, C_SW1
++ mtc0 v0, CP0_CAUSE
++0:
++ /*
++ * This test should really never branch but
++ * let's be prudent here. Having atomized
++ * the shared register modifications, we can
++ * now EVPE, and must do so before interrupts
++ * are potentially re-enabled.
++ */
++ andi a1, a1, MVPCONTROL_EVP
+ beqz a1, 1f
+- emt
++ evpe
+ 1:
++ /* We know that TCStatua.IXMT should be set from above */
++ xori a0, a0, TCSTATUS_IXMT
++ or a0, a0, v1
++ mtc0 a0, CP0_TCSTATUS
++ _ehb
++
+ .set mips0
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ LONG_L v1, PT_EPC(sp)
+diff -Nurd linux-2.6.24/include/asm-mips/time.h mer-smartq-kernel/include/asm-mips/time.h
+--- linux-2.6.24/include/asm-mips/time.h 2008-01-24 23:58:37.000000000 +0100
++++ mer-smartq-kernel/include/asm-mips/time.h 2009-11-17 12:13:39.000000000 +0100
+@@ -70,11 +70,12 @@
+ /*
+ * Initialize the count register as a clocksource
+ */
+-#ifdef CONFIG_CEVT_R4K
+-extern void init_mips_clocksource(void);
++#ifdef CONFIG_CSRC_R4K
++extern int init_mips_clocksource(void);
+ #else
+-static inline void init_mips_clocksource(void)
++static inline int init_mips_clocksource(void)
+ {
++ return 0;
+ }
+ #endif
+
+diff -Nurd linux-2.6.24/Makefile mer-smartq-kernel/Makefile
+--- linux-2.6.24/Makefile 2009-11-17 21:04:50.000000000 +0100
++++ mer-smartq-kernel/Makefile 2009-11-17 18:05:54.000000000 +0100
+@@ -190,7 +190,7 @@
+ # Default value for CROSS_COMPILE is not to prefix executables
+ # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
+ export KBUILD_BUILDHOST := $(SUBARCH)
+-ARCH ?= $(SUBARCH)
++ARCH ?= mips
+ CROSS_COMPILE ?=
+
+ # Architecture as present in compile.h
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-24 01:08:57 +0000