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authorRoy Li <rongqing.li@windriver.com>2013-09-24 13:20:08 +0000
committerRichard Purdie <richard.purdie@linuxfoundation.org>2013-09-25 17:48:13 +0100
commit2cc9106da45a14d41a5269d91d7f79b6ccd8597f (patch)
treed9c2df49f7ceb070cecb9856625840ee00492dd3 /meta/recipes-connectivity
parent821037700ae61fff6a63d4cdb68559c5fcc96fde (diff)
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bind: port a patch to fix a build failure
Signed-off-by: Roy Li <rongqing.li@windriver.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-connectivity')
-rw-r--r--meta/recipes-connectivity/bind/bind-9.8.1/mips1-not-support-opcode.diff104
-rw-r--r--meta/recipes-connectivity/bind/bind_9.8.1.bb1
2 files changed, 105 insertions, 0 deletions
diff --git a/meta/recipes-connectivity/bind/bind-9.8.1/mips1-not-support-opcode.diff b/meta/recipes-connectivity/bind/bind-9.8.1/mips1-not-support-opcode.diff
new file mode 100644
index 0000000000..2930796b6a
--- /dev/null
+++ b/meta/recipes-connectivity/bind/bind-9.8.1/mips1-not-support-opcode.diff
@@ -0,0 +1,104 @@
+bind: port a patch to fix a build failure
+
+mips1 does not support ll and sc instructions, and lead to below error, now
+we port a patch from debian to fix it
+[http://security.debian.org/debian-security/pool/updates/main/b/bind9/bind9_9.8.4.dfsg.P1-6+nmu2+deb7u1.diff.gz]
+
+| {standard input}: Assembler messages:
+| {standard input}:47: Error: Opcode not supported on this processor: mips1 (mips1) `ll $3,0($6)'
+| {standard input}:50: Error: Opcode not supported on this processor: mips1 (mips1) `sc $3,0($6)'
+
+Upstream-Status: Pending
+
+Signed-off-by: Roy Li <rongqing.li@windriver.com>
+
+--- bind9-9.8.4.dfsg.P1.orig/lib/isc/mips/include/isc/atomic.h
++++ bind9-9.8.4.dfsg.P1/lib/isc/mips/include/isc/atomic.h
+@@ -31,18 +31,20 @@
+ isc_atomic_xadd(isc_int32_t *p, int val) {
+ isc_int32_t orig;
+
+- /* add is a cheat, since MIPS has no mov instruction */
+- __asm__ volatile (
+- "1:"
+- "ll $3, %1\n"
+- "add %0, $0, $3\n"
+- "add $3, $3, %2\n"
+- "sc $3, %1\n"
+- "beq $3, 0, 1b"
+- : "=&r"(orig)
+- : "m"(*p), "r"(val)
+- : "memory", "$3"
+- );
++ __asm__ __volatile__ (
++ " .set push \n"
++ " .set mips2 \n"
++ " .set noreorder \n"
++ " .set noat \n"
++ "1: ll $1, %1 \n"
++ " addu %0, $1, %2 \n"
++ " sc %0, %1 \n"
++ " beqz %0, 1b \n"
++ " move %0, $1 \n"
++ " .set pop \n"
++ : "=&r" (orig), "+R" (*p)
++ : "r" (val)
++ : "memory");
+
+ return (orig);
+ }
+@@ -52,16 +54,7 @@
+ */
+ static inline void
+ isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
+- __asm__ volatile (
+- "1:"
+- "ll $3, %0\n"
+- "add $3, $0, %1\n"
+- "sc $3, %0\n"
+- "beq $3, 0, 1b"
+- :
+- : "m"(*p), "r"(val)
+- : "memory", "$3"
+- );
++ *p = val;
+ }
+
+ /*
+@@ -72,20 +65,23 @@
+ static inline isc_int32_t
+ isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) {
+ isc_int32_t orig;
++ isc_int32_t tmp;
+
+- __asm__ volatile(
+- "1:"
+- "ll $3, %1\n"
+- "add %0, $0, $3\n"
+- "bne $3, %2, 2f\n"
+- "add $3, $0, %3\n"
+- "sc $3, %1\n"
+- "beq $3, 0, 1b\n"
+- "2:"
+- : "=&r"(orig)
+- : "m"(*p), "r"(cmpval), "r"(val)
+- : "memory", "$3"
+- );
++ __asm__ __volatile__ (
++ " .set push \n"
++ " .set mips2 \n"
++ " .set noreorder \n"
++ " .set noat \n"
++ "1: ll $1, %1 \n"
++ " bne $1, %3, 2f \n"
++ " move %2, %4 \n"
++ " sc %2, %1 \n"
++ " beqz %2, 1b \n"
++ "2: move %0, $1 \n"
++ " .set pop \n"
++ : "=&r"(orig), "+R" (*p), "=r" (tmp)
++ : "r"(cmpval), "r"(val)
++ : "memory");
+
+ return (orig);
+ }
diff --git a/meta/recipes-connectivity/bind/bind_9.8.1.bb b/meta/recipes-connectivity/bind/bind_9.8.1.bb
index 3c5d600944..5919c21b9f 100644
--- a/meta/recipes-connectivity/bind/bind_9.8.1.bb
+++ b/meta/recipes-connectivity/bind/bind_9.8.1.bb
@@ -18,6 +18,7 @@ SRC_URI = "ftp://ftp.isc.org/isc/bind9/${PV}/${BPN}-${PV}.tar.gz \
file://bind-CVE-2012-3817.patch \
file://bind-CVE-2013-2266.patch \
file://bind-Fix-CVE-2012-4244.patch \
+ file://mips1-not-support-opcode.diff \
"
SRC_URI[md5sum] = "cf31117c5d35af34d4c0702970ad9fb7"