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authorAlexander Kanavin <alex.kanavin@gmail.com>2022-10-25 20:44:26 +0200
committerSteve Sakoman <steve@sakoman.com>2022-11-04 09:16:52 -1000
commit2daa8d76369cd06e5c357e393e3145e08f3d6760 (patch)
treeebe6c81957d9ac655bd19de50f5f793efe4fb447
parentdda8017274e71daa7aa4d8a3a15e128df213b0de (diff)
downloadopenembedded-core-2daa8d76369cd06e5c357e393e3145e08f3d6760.tar.gz
rust-target-config: match riscv target names with what rust expects
Official rust risc-v targets are prefixed with riscv32gc- and riscv64gc-: https://doc.rust-lang.org/nightly/rustc/platform-support.html Particularly crossbeam-utils make important build time decisions for atomics based on those names, and so we need to match ours with official targets. On the other hand, the actual definitions for those targets do not use the 'gc' suffix in 'arch' and 'llvm-target' fields, and so we need to follow that too, to avoid cryptic mismatch errors from rust-llvm: https://github.com/rust-lang/rust/blob/master/compiler/rustc_target/src/spec/riscv32gc_unknown_linux_gnu.rs Signed-off-by: Alexander Kanavin <alex@linutronix.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> (cherry picked from commit 1cfb9c8a59d98ccc9b0510cd28fb933f72fb6b6c) Signed-off-by: Steve Sakoman <steve@sakoman.com>
-rw-r--r--meta/classes-recipe/rust-target-config.bbclass40
-rw-r--r--meta/lib/oe/rust.py2
2 files changed, 28 insertions, 14 deletions
diff --git a/meta/classes-recipe/rust-target-config.bbclass b/meta/classes-recipe/rust-target-config.bbclass
index 9e1d81bf5c..2710b4325d 100644
--- a/meta/classes-recipe/rust-target-config.bbclass
+++ b/meta/classes-recipe/rust-target-config.bbclass
@@ -231,19 +231,19 @@ TARGET_POINTER_WIDTH[powerpc64le] = "64"
TARGET_C_INT_WIDTH[powerpc64le] = "64"
MAX_ATOMIC_WIDTH[powerpc64le] = "64"
-## riscv32-unknown-linux-{gnu, musl}
-DATA_LAYOUT[riscv32] = "e-m:e-p:32:32-i64:64-n32-S128"
-TARGET_ENDIAN[riscv32] = "little"
-TARGET_POINTER_WIDTH[riscv32] = "32"
-TARGET_C_INT_WIDTH[riscv32] = "32"
-MAX_ATOMIC_WIDTH[riscv32] = "32"
-
-## riscv64-unknown-linux-{gnu, musl}
-DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
-TARGET_ENDIAN[riscv64] = "little"
-TARGET_POINTER_WIDTH[riscv64] = "64"
-TARGET_C_INT_WIDTH[riscv64] = "64"
-MAX_ATOMIC_WIDTH[riscv64] = "64"
+## riscv32gc-unknown-linux-{gnu, musl}
+DATA_LAYOUT[riscv32gc] = "e-m:e-p:32:32-i64:64-n32-S128"
+TARGET_ENDIAN[riscv32gc] = "little"
+TARGET_POINTER_WIDTH[riscv32gc] = "32"
+TARGET_C_INT_WIDTH[riscv32gc] = "32"
+MAX_ATOMIC_WIDTH[riscv32gc] = "32"
+
+## riscv64gc-unknown-linux-{gnu, musl}
+DATA_LAYOUT[riscv64gc] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+TARGET_ENDIAN[riscv64gc] = "little"
+TARGET_POINTER_WIDTH[riscv64gc] = "64"
+TARGET_C_INT_WIDTH[riscv64gc] = "64"
+MAX_ATOMIC_WIDTH[riscv64gc] = "64"
# Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something
# rust's internals won't choke on.
@@ -258,9 +258,21 @@ def arch_to_rust_target_arch(arch):
return "arm"
elif arch == "powerpc64le":
return "powerpc64"
+ elif arch == "riscv32gc":
+ return "riscv32"
+ elif arch == "riscv64gc":
+ return "riscv64"
else:
return arch
+# Convert a rust target string to a llvm-compatible triplet
+def rust_sys_to_llvm_target(sys):
+ if sys.startswith('riscv32gc-'):
+ return sys.replace('riscv32gc-', 'riscv32-', 1)
+ if sys.startswith('riscv64gc-'):
+ return sys.replace('riscv64gc-', 'riscv64-', 1)
+ return sys
+
# generates our target CPU value
def llvm_cpu(d):
cpu = d.getVar('PACKAGE_ARCH')
@@ -334,7 +346,7 @@ def rust_gen_target(d, thing, wd, arch):
# build tspec
tspec = {}
- tspec['llvm-target'] = rustsys
+ tspec['llvm-target'] = rust_sys_to_llvm_target(rustsys)
tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch_abi)
if tspec['data-layout'] is None:
bb.fatal("No rust target defined for %s" % arch_abi)
diff --git a/meta/lib/oe/rust.py b/meta/lib/oe/rust.py
index 1dc9cf150d..185553eeeb 100644
--- a/meta/lib/oe/rust.py
+++ b/meta/lib/oe/rust.py
@@ -8,4 +8,6 @@
def arch_to_rust_arch(arch):
if arch == "ppc64le":
return "powerpc64le"
+ if arch in ('riscv32', 'riscv64'):
+ return arch + 'gc'
return arch