From 26a7f6b1e4c5f715c03e59a623f0d620498b92cf Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Sun, 13 Feb 2022 21:11:31 -0800 Subject: [PATCH] riscv: fix build with binutils 2.38 From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. The fix is to specify those extensions explicitely in -march. However as older binutils version do not support this, we first need to detect that. Fixes arch/riscv/lib/cache.c: Assembler messages: arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i' Upstream-Status: Submitted [] Signed-off-by: Khem Raj --- arch/riscv/Makefile | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -28,7 +28,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) -mabi=$(ABI) \ +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)_zicsr_zifencei) +zicsr_zifencei-$(toolchain-need-zicsr-zifencei) := _zicsr_zifencei + +ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)$(zicsr_zifencei-y) -mabi=$(ABI) \ -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS)