diff options
Diffstat (limited to 'recipes-bsp/u-boot/u-boot/0030-OMAP3-apply-Cortex-A8-errata-workarounds-only-on-aff.patch')
| -rw-r--r-- | recipes-bsp/u-boot/u-boot/0030-OMAP3-apply-Cortex-A8-errata-workarounds-only-on-aff.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot/0030-OMAP3-apply-Cortex-A8-errata-workarounds-only-on-aff.patch b/recipes-bsp/u-boot/u-boot/0030-OMAP3-apply-Cortex-A8-errata-workarounds-only-on-aff.patch new file mode 100644 index 0000000000..af669ec07e --- /dev/null +++ b/recipes-bsp/u-boot/u-boot/0030-OMAP3-apply-Cortex-A8-errata-workarounds-only-on-aff.patch @@ -0,0 +1,46 @@ +From 4e7bc59affc2a71de40259330e27e62181993968 Mon Sep 17 00:00:00 2001 +From: Mans Rullgard <mans@mansr.com> +Date: Wed, 14 Apr 2010 17:10:28 +0100 +Subject: [PATCH 30/37] OMAP3: apply Cortex-A8 errata workarounds only on affected revisions + +The workarounds for errata 621766 and 725233 should only be applied +on affected Cortex-A8 revisions. Recent chips use r3px cores where +these have been fixed. + +Signed-off-by: Mans Rullgard <mans@mansr.com> +--- + cpu/arm_cortexa8/omap3/cache.S | 13 ++++++++++--- + 1 files changed, 10 insertions(+), 3 deletions(-) + +diff --git a/cpu/arm_cortexa8/omap3/cache.S b/cpu/arm_cortexa8/omap3/cache.S +index 61e6946..932e4eb 100644 +--- a/cpu/arm_cortexa8/omap3/cache.S ++++ b/cpu/arm_cortexa8/omap3/cache.S +@@ -163,14 +163,21 @@ l2_cache_disable: + * general use. + *****************************************************************************/ + setup_auxcr: ++ mrc p15, 0, r0, c0, c0, 0 @ read main ID register ++ and r2, r0, #0x00f00000 @ variant ++ and r3, r0, #0x0000000f @ revision ++ orr r1, r3, r2, lsr #20-4 @ combine variant and revision + mov r12, #0x3 + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x10 @ Enable ASA +- orr r0, r0, #1 << 5 @ Enable L1NEON ++ @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround) ++ cmp r1, #0x21 ++ orrlt r0, r0, #1 << 5 + .word 0xE1600070 @ SMC + mov r12, #0x2 + mrc p15, 1, r0, c9, c0, 2 +- @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) +- orr r0, r0, #1 << 27 ++ @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround) ++ cmp r1, #0x21 ++ orrlt r0, r0, #1 << 27 + .word 0xE1600070 @ SMC + bx lr +-- +1.6.6.1 + |