diff options
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch')
-rw-r--r-- | meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch index 1fefb680f8..4d64bd53f8 100644 --- a/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch +++ b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch @@ -1,4 +1,4 @@ -From 3b40bf584615f794b85fd50d4d0a5c0a1d2ee7bf Mon Sep 17 00:00:00 2001 +From 96ff7570c29f792c466a933529fefda9b8e97994 Mon Sep 17 00:00:00 2001 From: Khem Raj <raj.khem@gmail.com> Date: Sun, 14 Feb 2016 17:06:19 +0000 Subject: [PATCH 12/15] Add support for Netlogic XLP @@ -34,10 +34,10 @@ Signed-off-by: Mark Hatle <mark.hatle@windriver.com> 14 files changed, 61 insertions(+), 21 deletions(-) diff --git a/bfd/aoutx.h b/bfd/aoutx.h -index eec9c4ad2a..3bf0a71e63 100644 +index 023843b0be..46246fec2d 100644 --- a/bfd/aoutx.h +++ b/bfd/aoutx.h -@@ -814,6 +814,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, +@@ -798,6 +798,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, case bfd_mach_mipsisa64r6: case bfd_mach_mips_sb1: case bfd_mach_mips_xlr: @@ -46,10 +46,10 @@ index eec9c4ad2a..3bf0a71e63 100644 arch_flags = M_MIPS2; break; diff --git a/bfd/archures.c b/bfd/archures.c -index e83c57a2f3..3016ea1bae 100644 +index 282e983086..b38b05d132 100644 --- a/bfd/archures.c +++ b/bfd/archures.c -@@ -201,6 +201,7 @@ DESCRIPTION +@@ -183,6 +183,7 @@ DESCRIPTION .#define bfd_mach_mips_octeon3 6503 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *} .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *} @@ -58,10 +58,10 @@ index e83c57a2f3..3016ea1bae 100644 .#define bfd_mach_mipsisa32r2 33 .#define bfd_mach_mipsisa32r3 34 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index 42991e7848..27abc5d5a8 100644 +index 93745bd3fd..326e9e49ed 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h -@@ -2062,6 +2062,7 @@ enum bfd_architecture +@@ -2054,6 +2054,7 @@ enum bfd_architecture #define bfd_mach_mips_octeon3 6503 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */ #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */ @@ -70,10 +70,10 @@ index 42991e7848..27abc5d5a8 100644 #define bfd_mach_mipsisa32r2 33 #define bfd_mach_mipsisa32r3 34 diff --git a/bfd/config.bfd b/bfd/config.bfd -index 8777f96bd2..7b80bda8c9 100644 +index 8a11c0680a..c882421343 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd -@@ -1172,6 +1172,11 @@ case "${targ}" in +@@ -896,6 +896,11 @@ case "${targ}" in targ_defvec=mips_elf32_le_vec targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec" ;; @@ -110,10 +110,10 @@ index cb50c64371..2b9d1d6ecf 100644 /* The default architecture is mips:3000, but with a machine number of diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c -index 285401367d..14ebb5f175 100644 +index d91942301c..5d1bd3f0b1 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c -@@ -6806,6 +6806,9 @@ _bfd_elf_mips_mach (flagword flags) +@@ -6805,6 +6805,9 @@ _bfd_elf_mips_mach (flagword flags) case E_MIPS_MACH_IAMR2: return bfd_mach_mips_interaptiv_mr2; @@ -123,7 +123,7 @@ index 285401367d..14ebb5f175 100644 default: switch (flags & EF_MIPS_ARCH) { -@@ -11963,6 +11966,10 @@ mips_set_isa_flags (bfd *abfd) +@@ -12003,6 +12006,10 @@ mips_set_isa_flags (bfd *abfd) val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; break; @@ -134,7 +134,7 @@ index 285401367d..14ebb5f175 100644 case bfd_mach_mipsisa32: val = E_MIPS_ARCH_32; break; -@@ -13936,6 +13943,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = +@@ -13992,6 +13999,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, @@ -143,10 +143,10 @@ index 285401367d..14ebb5f175 100644 /* MIPS64 extensions. */ { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, diff --git a/binutils/readelf.c b/binutils/readelf.c -index ae1cda9a7b..fed0387a94 100644 +index 2b78db219b..7a7178925f 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c -@@ -3370,6 +3370,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) +@@ -3403,6 +3403,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break; @@ -155,7 +155,7 @@ index ae1cda9a7b..fed0387a94 100644 /* We simply ignore the field in this case to avoid confusion: MIPS ELF does not specify EF_MIPS_MACH, it is a GNU diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c -index c135131b59..d8fbda8e31 100644 +index 59df787155..48537226c0 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -552,6 +552,7 @@ static int mips_32bitmode = 0; @@ -174,7 +174,7 @@ index c135131b59..d8fbda8e31 100644 ) /* Whether the processor uses hardware interlocks to protect reads -@@ -19737,7 +19739,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = +@@ -19778,7 +19780,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = /* Broadcom XLP. XLP is mostly like XLR, with the prominent exception that it is MIPS64R2 rather than MIPS64. */ @@ -184,10 +184,10 @@ index c135131b59..d8fbda8e31 100644 /* MIPS 64 Release 6 */ { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, diff --git a/gas/configure b/gas/configure -index a40ac2144f..65a6995243 100755 +index 134278fa25..2fdca147a1 100755 --- a/gas/configure +++ b/gas/configure -@@ -12989,6 +12989,9 @@ _ACEOF +@@ -13336,6 +13336,9 @@ _ACEOF mipsisa64r6 | mipsisa64r6el) mips_cpu=mips64r6 ;; @@ -198,7 +198,7 @@ index a40ac2144f..65a6995243 100755 mips_cpu=r3900 ;; diff --git a/include/elf/mips.h b/include/elf/mips.h -index 9de0b4e175..74fc4f7e55 100644 +index 4e2cde3279..c329f38929 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) @@ -210,10 +210,10 @@ index 9de0b4e175..74fc4f7e55 100644 #define E_MIPS_MACH_OCTEON3 0x008e0000 #define E_MIPS_MACH_5400 0x00910000 diff --git a/include/opcode/mips.h b/include/opcode/mips.h -index 5eea72f139..90f6d57e15 100644 +index 1ab1780567..74f457b579 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h -@@ -1259,6 +1259,8 @@ static const unsigned int mips_isa_table[] = { +@@ -1262,6 +1262,8 @@ static const unsigned int mips_isa_table[] = { #define INSN_XLR 0x00000020 /* Imagination interAptiv MR2. */ #define INSN_INTERAPTIV_MR2 0x04000000 @@ -222,7 +222,7 @@ index 5eea72f139..90f6d57e15 100644 /* DSP ASE */ #define ASE_DSP 0x00000001 -@@ -1365,6 +1367,7 @@ static const unsigned int mips_isa_table[] = { +@@ -1373,6 +1375,7 @@ static const unsigned int mips_isa_table[] = { #define CPU_OCTEON3 6503 #define CPU_XLR 887682 /* decimal 'XLR' */ #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ @@ -230,7 +230,7 @@ index 5eea72f139..90f6d57e15 100644 /* Return true if the given CPU is included in INSN_* mask MASK. */ -@@ -1445,6 +1448,9 @@ cpu_is_member (int cpu, unsigned int mask) +@@ -1453,6 +1456,9 @@ cpu_is_member (int cpu, unsigned int mask) return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); @@ -241,10 +241,10 @@ index 5eea72f139..90f6d57e15 100644 return FALSE; } diff --git a/ld/configure.tgt b/ld/configure.tgt -index 1d78465590..307e787b64 100644 +index 7fb2168503..a1db7adfe2 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt -@@ -521,6 +521,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*) +@@ -450,6 +450,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*) mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) targ_emul=elf32btsmip targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; @@ -254,10 +254,10 @@ index 1d78465590..307e787b64 100644 targ_extra_emuls="elf32lr5900" targ_extra_libpath=$targ_extra_emuls ;; diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c -index 984fcbb802..95b107d216 100644 +index bbf21328e8..38e487c16f 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c -@@ -655,13 +655,11 @@ const struct mips_arch_choice mips_arch_choices[] = +@@ -656,13 +656,11 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), mips_cp1_names_mips3264, mips_hwr_names_numeric }, @@ -277,10 +277,10 @@ index 984fcbb802..95b107d216 100644 /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c -index 180d613c93..65b7b8cc23 100644 +index 1cbcbc6abc..e1fbdc89de 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c -@@ -328,6 +328,7 @@ decode_mips_operand (const char *p) +@@ -329,6 +329,7 @@ decode_mips_operand (const char *p) #define IOCT3 INSN_OCTEON3 #define XLR INSN_XLR #define IAMR2 INSN_INTERAPTIV_MR2 @@ -288,7 +288,7 @@ index 180d613c93..65b7b8cc23 100644 #define IVIRT ASE_VIRT #define IVIRT64 ASE_VIRT64 -@@ -966,6 +967,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -974,6 +975,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, @@ -296,7 +296,7 @@ index 180d613c93..65b7b8cc23 100644 /* ctc0 is at the bottom of the table. */ {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, -@@ -998,12 +1000,13 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1006,12 +1008,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, @@ -311,7 +311,7 @@ index 180d613c93..65b7b8cc23 100644 /* dctr and dctw are used on the r5000. */ {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, -@@ -1075,6 +1078,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1083,6 +1086,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, @@ -319,7 +319,7 @@ index 180d613c93..65b7b8cc23 100644 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, -@@ -1090,6 +1094,8 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1098,6 +1102,8 @@ const struct mips_opcode mips_builtin_opcodes[] = /* dmfc3 is at the bottom of the table. */ /* dmtc3 is at the bottom of the table. */ {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, @@ -328,7 +328,7 @@ index 180d613c93..65b7b8cc23 100644 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, -@@ -1243,9 +1249,9 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1251,9 +1257,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, @@ -341,7 +341,7 @@ index 180d613c93..65b7b8cc23 100644 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, -@@ -1410,7 +1416,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1418,7 +1424,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, @@ -350,7 +350,7 @@ index 180d613c93..65b7b8cc23 100644 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -@@ -1455,10 +1461,13 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1463,10 +1469,13 @@ const struct mips_opcode mips_builtin_opcodes[] = /* move is at the top of the table. */ {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, @@ -366,7 +366,7 @@ index 180d613c93..65b7b8cc23 100644 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -@@ -1508,7 +1517,7 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1516,7 +1525,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, @@ -375,7 +375,7 @@ index 180d613c93..65b7b8cc23 100644 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, -@@ -1945,9 +1954,9 @@ const struct mips_opcode mips_builtin_opcodes[] = +@@ -1953,9 +1962,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, @@ -389,5 +389,5 @@ index 180d613c93..65b7b8cc23 100644 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, -- -2.16.1 +2.18.0 |