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-rw-r--r--meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch99
1 files changed, 34 insertions, 65 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch b/meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch
index 20c5ed6308..b710752245 100644
--- a/meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch
+++ b/meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch
@@ -1,7 +1,7 @@
-From e4a0cd30c7e9334ed507c93014a8b2d1315ff937 Mon Sep 17 00:00:00 2001
+From 97e0fdbf8e85a7e690ac09d01a2ae93ba00cfb5d Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Sun, 14 Feb 2016 17:06:19 +0000
-Subject: [PATCH 11/15] Add support for Netlogic XLP
+Subject: [PATCH] Add support for Netlogic XLP
Patch From: Nebu Philips <nphilips@netlogicmicro.com>
@@ -28,16 +28,14 @@ Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
gas/configure | 3 +++
include/elf/mips.h | 1 +
include/opcode/mips.h | 6 ++++++
- ld/configure.tgt | 2 ++
+ ld/configure.tgt | 3 +++
opcodes/mips-dis.c | 12 +++++-------
opcodes/mips-opc.c | 31 ++++++++++++++++++++-----------
- 14 files changed, 61 insertions(+), 21 deletions(-)
+ 14 files changed, 62 insertions(+), 21 deletions(-)
-diff --git a/bfd/aoutx.h b/bfd/aoutx.h
-index e5d8dcf390..2cc74a2d61 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
-@@ -799,6 +799,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
+@@ -799,6 +799,7 @@ NAME (aout, machine_type) (enum bfd_arch
case bfd_mach_mipsisa64r6:
case bfd_mach_mips_sb1:
case bfd_mach_mips_xlr:
@@ -45,8 +43,6 @@ index e5d8dcf390..2cc74a2d61 100644
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;
-diff --git a/bfd/archures.c b/bfd/archures.c
-index 647cf0d8d4..7e1d0c810f 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -185,6 +185,7 @@ DESCRIPTION
@@ -57,11 +53,9 @@ index 647cf0d8d4..7e1d0c810f 100644
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa32r3 34
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index e25da50aaf..e251d7e7aa 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
-@@ -2084,6 +2084,7 @@ enum bfd_architecture
+@@ -2125,6 +2125,7 @@ enum bfd_architecture
#define bfd_mach_mips_octeon3 6503
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */
#define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */
@@ -69,11 +63,9 @@ index e25da50aaf..e251d7e7aa 100644
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa32r3 34
-diff --git a/bfd/config.bfd b/bfd/config.bfd
-index cc65547588..3614ff79d4 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
-@@ -902,6 +902,11 @@ case "${targ}" in
+@@ -898,6 +898,11 @@ case "${targ}" in
targ_defvec=mips_elf32_le_vec
targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
;;
@@ -85,8 +77,6 @@ index cc65547588..3614ff79d4 100644
mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none)
targ_defvec=mips_elf32_be_vec
targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
-diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
-index b359491305..61a3e7aaca 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -107,7 +107,8 @@ enum
@@ -99,21 +89,19 @@ index b359491305..61a3e7aaca 100644
};
#define NN(index) (&arch_info_struct[(index) + 1])
-@@ -162,7 +163,8 @@ static const bfd_arch_info_type arch_info_struct[] =
+@@ -162,7 +163,8 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", FALSE,
NN(I_interaptiv_mr2)),
- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
-+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
-+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
++ N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NN(I_micromips)),
++ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, NULL)
};
/* The default architecture is mips:3000, but with a machine number of
-diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
-index 5998bc43a8..0d5795222b 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
-@@ -6919,6 +6919,9 @@ _bfd_elf_mips_mach (flagword flags)
+@@ -6999,6 +6999,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_IAMR2:
return bfd_mach_mips_interaptiv_mr2;
@@ -123,7 +111,7 @@ index 5998bc43a8..0d5795222b 100644
default:
switch (flags & EF_MIPS_ARCH)
{
-@@ -12199,6 +12202,10 @@ mips_set_isa_flags (bfd *abfd)
+@@ -12360,6 +12363,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
break;
@@ -134,7 +122,7 @@ index 5998bc43a8..0d5795222b 100644
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
-@@ -14214,6 +14221,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
+@@ -14394,6 +14401,7 @@ static const struct mips_mach_extension
{ bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
{ bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
{ bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
@@ -142,11 +130,9 @@ index 5998bc43a8..0d5795222b 100644
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
-diff --git a/binutils/readelf.c b/binutils/readelf.c
-index b13eb6a43b..9df3742682 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
-@@ -3412,6 +3412,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
+@@ -3446,6 +3446,7 @@ get_machine_flags (Filedata * filedata,
case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break;
@@ -154,11 +140,9 @@ index b13eb6a43b..9df3742682 100644
case 0:
/* We simply ignore the field in this case to avoid confusion:
MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
-diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
-index ae55904229..d6882712f5 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
-@@ -554,6 +554,7 @@ static int mips_32bitmode = 0;
+@@ -568,6 +568,7 @@ static int mips_32bitmode = 0;
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_VR5500 \
|| mips_opts.micromips \
@@ -166,7 +150,7 @@ index ae55904229..d6882712f5 100644
)
/* Whether the processor uses hardware interlocks to protect reads
-@@ -583,6 +584,7 @@ static int mips_32bitmode = 0;
+@@ -597,6 +598,7 @@ static int mips_32bitmode = 0;
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
|| mips_opts.micromips \
@@ -174,20 +158,18 @@ index ae55904229..d6882712f5 100644
)
/* Whether the processor uses hardware interlocks to protect reads
-@@ -19867,7 +19869,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
+@@ -20138,7 +20140,7 @@ static const struct mips_cpu_info mips_c
/* Broadcom XLP.
XLP is mostly like XLR, with the prominent exception that it is
MIPS64R2 rather than MIPS64. */
- { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
- /* MIPS 64 Release 6 */
- { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
-diff --git a/gas/configure b/gas/configure
-index a82fde7fa8..afc77c347a 100755
+ /* MIPS 64 Release 6. */
+ { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
--- a/gas/configure
+++ b/gas/configure
-@@ -13364,6 +13364,9 @@ _ACEOF
+@@ -13377,6 +13377,9 @@ _ACEOF
mipsisa64r6 | mipsisa64r6el)
mips_cpu=mips64r6
;;
@@ -197,8 +179,6 @@ index a82fde7fa8..afc77c347a 100755
mipstx39 | mipstx39el)
mips_cpu=r3900
;;
-diff --git a/include/elf/mips.h b/include/elf/mips.h
-index b76d450ae2..7cddb365ad 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
@@ -209,11 +189,9 @@ index b76d450ae2..7cddb365ad 100644
#define E_MIPS_MACH_OCTEON2 0x008d0000
#define E_MIPS_MACH_OCTEON3 0x008e0000
#define E_MIPS_MACH_5400 0x00910000
-diff --git a/include/opcode/mips.h b/include/opcode/mips.h
-index abd52c8980..53b6752a1c 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
-@@ -1260,6 +1260,8 @@ static const unsigned int mips_isa_table[] = {
+@@ -1260,6 +1260,8 @@ static const unsigned int mips_isa_table
#define INSN_XLR 0x00000020
/* Imagination interAptiv MR2. */
#define INSN_INTERAPTIV_MR2 0x04000000
@@ -222,7 +200,7 @@ index abd52c8980..53b6752a1c 100644
/* DSP ASE */
#define ASE_DSP 0x00000001
-@@ -1381,6 +1383,7 @@ static const unsigned int mips_isa_table[] = {
+@@ -1384,6 +1386,7 @@ static const unsigned int mips_isa_table
#define CPU_OCTEON3 6503
#define CPU_XLR 887682 /* decimal 'XLR' */
#define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
@@ -230,7 +208,7 @@ index abd52c8980..53b6752a1c 100644
/* Return true if the given CPU is included in INSN_* mask MASK. */
-@@ -1458,6 +1461,9 @@ cpu_is_member (int cpu, unsigned int mask)
+@@ -1461,6 +1464,9 @@ cpu_is_member (int cpu, unsigned int mas
return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
|| ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
@@ -240,11 +218,9 @@ index abd52c8980..53b6752a1c 100644
default:
return FALSE;
}
-diff --git a/ld/configure.tgt b/ld/configure.tgt
-index 917be6f8eb..347df6c3f6 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
-@@ -454,6 +454,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*)
+@@ -454,6 +454,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mi
mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
targ_emul=elf32btsmip
targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
@@ -253,11 +229,9 @@ index 917be6f8eb..347df6c3f6 100644
mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
targ_extra_emuls="elf32lr5900"
targ_extra_libpath=$targ_extra_emuls ;;
-diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
-index 0dd85e3779..1ea708dde7 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
-@@ -673,13 +673,11 @@ const struct mips_arch_choice mips_arch_choices[] =
+@@ -673,13 +673,11 @@ const struct mips_arch_choice mips_arch_
mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
mips_cp1_names_mips3264, mips_hwr_names_numeric },
@@ -276,8 +250,6 @@ index 0dd85e3779..1ea708dde7 100644
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
-diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
-index 837da6bd99..d3ea5b8877 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -328,6 +328,7 @@ decode_mips_operand (const char *p)
@@ -288,7 +260,7 @@ index 837da6bd99..d3ea5b8877 100644
#define IVIRT ASE_VIRT
#define IVIRT64 ASE_VIRT64
-@@ -989,6 +990,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -990,6 +991,7 @@ const struct mips_opcode mips_builtin_op
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
{"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
@@ -296,7 +268,7 @@ index 837da6bd99..d3ea5b8877 100644
/* ctc0 is at the bottom of the table. */
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
-@@ -1021,12 +1023,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1022,12 +1024,13 @@ const struct mips_opcode mips_builtin_op
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
@@ -311,7 +283,7 @@ index 837da6bd99..d3ea5b8877 100644
/* dctr and dctw are used on the r5000. */
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
-@@ -1098,6 +1101,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1099,6 +1102,7 @@ const struct mips_opcode mips_builtin_op
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
{"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
{"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
@@ -319,7 +291,7 @@ index 837da6bd99..d3ea5b8877 100644
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
-@@ -1113,6 +1117,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1114,6 +1118,8 @@ const struct mips_opcode mips_builtin_op
/* dmfc3 is at the bottom of the table. */
/* dmtc3 is at the bottom of the table. */
{"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
@@ -328,7 +300,7 @@ index 837da6bd99..d3ea5b8877 100644
{"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
-@@ -1266,9 +1272,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1267,9 +1273,9 @@ const struct mips_opcode mips_builtin_op
{"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
@@ -341,7 +313,7 @@ index 837da6bd99..d3ea5b8877 100644
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
-@@ -1433,7 +1439,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1438,7 +1444,7 @@ const struct mips_opcode mips_builtin_op
{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
{"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
@@ -350,7 +322,7 @@ index 837da6bd99..d3ea5b8877 100644
{"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
{"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
-@@ -1478,10 +1484,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1483,10 +1489,13 @@ const struct mips_opcode mips_builtin_op
/* move is at the top of the table. */
{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
{"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
@@ -366,7 +338,7 @@ index 837da6bd99..d3ea5b8877 100644
{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
{"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
-@@ -1531,7 +1540,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1536,7 +1545,7 @@ const struct mips_opcode mips_builtin_op
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
@@ -375,7 +347,7 @@ index 837da6bd99..d3ea5b8877 100644
{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
{"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
-@@ -1968,9 +1977,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1978,9 +1987,9 @@ const struct mips_opcode mips_builtin_op
{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
{"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
@@ -388,6 +360,3 @@ index 837da6bd99..d3ea5b8877 100644
{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
---
-2.20.1
-
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-18 18:51:29 +0000