2010-09-02 Marcus Shawcroft * config/arm/predicates.md (arm_sync_memory_operand): New. * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate to arm_sync_memory_operand and constraint to Q. (arm_sync_compare_and_swap): Likewise. (arm_sync_compare_and_swap): Likewise. (arm_sync_lock_test_and_setsi): Likewise. (arm_sync_lock_test_and_set): Likewise. (arm_sync_new_si): Likewise. (arm_sync_new_nandsi): Likewise. (arm_sync_new_): Likewise. (arm_sync_new_nand): Likewise. (arm_sync_old_si): Likewise. (arm_sync_old_nandsi): Likewise. (arm_sync_old_): Likewise. (arm_sync_old_nand): Likewise. 2010-09-09 Andrew Stubbs Backport from mainline: 2010-08-18 Marcus Shawcroft === modified file 'gcc/config/arm/predicates.md' --- old/gcc/config/arm/predicates.md 2010-09-09 14:11:34 +0000 +++ new/gcc/config/arm/predicates.md 2010-09-09 15:18:16 +0000 @@ -573,6 +573,11 @@ (and (match_test "TARGET_32BIT") (match_operand 0 "arm_di_operand")))) +;; True if the operand is memory reference suitable for a ldrex/strex. +(define_predicate "arm_sync_memory_operand" + (and (match_operand 0 "memory_operand") + (match_code "reg" "0"))) + ;; Predicates for parallel expanders based on mode. (define_special_predicate "vect_par_constant_high" (match_code "parallel") === modified file 'gcc/config/arm/sync.md' --- old/gcc/config/arm/sync.md 2010-09-09 15:03:00 +0000 +++ new/gcc/config/arm/sync.md 2010-09-09 15:18:16 +0000 @@ -280,7 +280,7 @@ (define_insn "arm_sync_compare_and_swapsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "+m") + [(match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "s_register_operand" "r")] VUNSPEC_SYNC_COMPARE_AND_SWAP)) @@ -307,7 +307,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (zero_extend:SI (unspec_volatile:NARROW - [(match_operand:NARROW 1 "memory_operand" "+m") + [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "s_register_operand" "r")] VUNSPEC_SYNC_COMPARE_AND_SWAP))) @@ -332,7 +332,7 @@ (define_insn "arm_sync_lock_test_and_setsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") - (match_operand:SI 1 "memory_operand" "+m")) + (match_operand:SI 1 "arm_sync_memory_operand" "+Q")) (set (match_dup 1) (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] VUNSPEC_SYNC_LOCK)) @@ -353,7 +353,7 @@ (define_insn "arm_sync_lock_test_and_set" [(set (match_operand:SI 0 "s_register_operand" "=&r") - (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m"))) + (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))) (set (match_dup 1) (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] VUNSPEC_SYNC_LOCK)) @@ -375,7 +375,7 @@ (define_insn "arm_sync_new_si" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_NEW_OP)) @@ -400,7 +400,7 @@ (define_insn "arm_sync_new_nandsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(not:SI (and:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_NEW_OP)) @@ -426,7 +426,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_NEW_OP)) @@ -454,7 +454,7 @@ [(not:SI (and:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_NEW_OP)) (set (match_dup 1) @@ -478,7 +478,7 @@ (define_insn "arm_sync_old_si" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_OLD_OP)) @@ -504,7 +504,7 @@ (define_insn "arm_sync_old_nandsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(not:SI (and:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_OLD_OP)) @@ -531,7 +531,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_OLD_OP)) @@ -558,7 +558,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(not:SI (and:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_OLD_OP))