diff options
Diffstat (limited to 'toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch')
| -rw-r--r-- | toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch new file mode 100644 index 0000000000..5b0735b004 --- /dev/null +++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch @@ -0,0 +1,25 @@ +2012-01-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> + + Backport from mainline + 2012-01-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> + + PR target/51819 + * config/arm/arm.c (arm_print_operand): Correct output of alignment + hints for neon loads and stores. + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2012-01-23 00:06:27 +0000 ++++ new/gcc/config/arm/arm.c 2012-01-23 18:54:21 +0000 +@@ -17463,9 +17463,9 @@ + /* Only certain alignment specifiers are supported by the hardware. */ + if (memsize == 16 && (align % 32) == 0) + align_bits = 256; +- else if ((memsize == 8 || memsize == 16) && (align % 16) == 0) ++ else if (memsize == 16 && (align % 16) == 0) + align_bits = 128; +- else if ((align % 8) == 0) ++ else if (memsize >= 8 && (align % 8) == 0) + align_bits = 64; + else + align_bits = 0; + |