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diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
new file mode 100644
index 0000000000..395c08cab7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
@@ -0,0 +1,6125 @@
+2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/testsuite/
+ From Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/46329
+ * gcc.target/arm/pr46329.c: New test.
+
+ gcc/
+ PR target/46329
+ * config/arm/arm.c (arm_legitimate_constant_p_1): Return false
+ for all Neon struct constants.
+
+2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/
+ * targhooks.h (default_legitimate_constant_p); Declare.
+ * targhooks.c (default_legitimate_constant_p): New function.
+
+ Backport from mainline:
+ 2011-04-21 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * target.def (legitimate_constant_p): New hook.
+ * doc/tm.texi.in (LEGITIMATE_CONSTANT_P): Replace with...
+ (TARGET_LEGITIMATE_CONSTANT_P): ...this.
+ * doc/tm.texi: Regenerate.
+ * calls.c (precompute_register_parameters): Replace uses of
+ LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p.
+ (emit_library_call_value_1): Likewise.
+ * expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn)
+ (compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise.
+ * recog.c (general_operand, immediate_operand): Likewise.
+ * reload.c (find_reloads_toplev, find_reloads_address_part): Likewise.
+ * reload1.c (init_eliminable_invariants): Likewise.
+
+ * config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete.
+ * config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise.
+ (THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise.
+ * config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define.
+ (arm_legitimate_constant_p_1, thumb_legitimate_constant_p)
+ (arm_legitimate_constant_p): New functions.
+ (arm_cannot_force_const_mem): Make static.
+
+2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/
+ Backport from mainline:
+
+ 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * hooks.h (hook_bool_mode_uhwi_false): Declare.
+ * hooks.c (hook_bool_mode_uhwi_false): New function.
+ * target.def (array_mode_supported_p): New hook.
+ * doc/tm.texi.in (TARGET_ARRAY_MODE_SUPPORTED_P): Add @hook.
+ * doc/tm.texi: Regenerate.
+ * stor-layout.c (mode_for_array): New function.
+ (layout_type): Use it.
+ * config/arm/arm.c (arm_array_mode_supported_p): New function.
+ (TARGET_ARRAY_MODE_SUPPORTED_P): Define.
+
+2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/
+ Backport from mainline:
+
+ 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
+ size of a '%A' memory reference.
+ (T_DREG, T_QREG): New neon_builtin_type_bits.
+ (arm_init_neon_builtins): Assert that the load and store operands
+ are neon_struct_operands.
+ (locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
+ (NEON_ARG_MEMORY): New builtin_arg.
+ (neon_dereference_pointer): New function.
+ (arm_expand_neon_args): Add a neon_builtin_type_bits argument.
+ Handle NEON_ARG_MEMORY.
+ (arm_expand_neon_builtin): Update after above interface changes.
+ Use NEON_ARG_MEMORY for loads and stores.
+ * config/arm/predicates.md (neon_struct_operand): New predicate.
+ * config/arm/iterators.md (V_two_elem): Tweak formatting.
+ (V_three_elem): Use BLKmode for accesses that have no associated mode.
+ (V_four_elem): Tweak formatting.
+ * config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
+ (neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
+ (neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
+ (neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
+ (neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
+ (neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
+ (neon_vst4<mode>): Replace pointer operand with a memory operand.
+ Use %A in the output template.
+ (neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
+ (neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
+ (neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
+ the width of the memory access. Remove post-increment.
+ * config/arm/neon-testgen.ml: Allow addresses to have an alignment.
+
+ gcc/testsuite/
+ Backport from mainline:
+
+ 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * gcc.target/arm/neon-vld3-1.c: New test.
+ * gcc.target/arm/neon-vst3-1.c: New test.
+ * gcc.target/arm/neon/v*.c: Regenerate.
+
+2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/
+ Backport from mainline:
+
+ 2011-03-30 Richard Sandiford <richard.sandiford@linaro.org>
+ Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
+
+ PR target/43590
+ * config/arm/neon.md (neon_vld3qa<mode>, neon_vld4qa<mode>): Remove
+ operand 1 and reshuffle the operands to match.
+ (neon_vld3<mode>, neon_vld4<mode>): Update accordingly.
+
+=== modified file 'gcc/calls.c'
+Index: gcc-4_6-branch/gcc/calls.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/calls.c 2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/calls.c 2011-09-16 20:16:00.217564705 -0700
+@@ -686,7 +686,7 @@
+ /* If the value is a non-legitimate constant, force it into a
+ pseudo now. TLS symbols sometimes need a call to resolve. */
+ if (CONSTANT_P (args[i].value)
+- && !LEGITIMATE_CONSTANT_P (args[i].value))
++ && !targetm.legitimate_constant_p (args[i].mode, args[i].value))
+ args[i].value = force_reg (args[i].mode, args[i].value);
+
+ /* If we are to promote the function arg to a wider mode,
+@@ -3449,7 +3449,8 @@
+
+ /* Make sure it is a reasonable operand for a move or push insn. */
+ if (!REG_P (addr) && !MEM_P (addr)
+- && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr)))
++ && !(CONSTANT_P (addr)
++ && targetm.legitimate_constant_p (Pmode, addr)))
+ addr = force_operand (addr, NULL_RTX);
+
+ argvec[count].value = addr;
+@@ -3490,7 +3491,7 @@
+
+ /* Make sure it is a reasonable operand for a move or push insn. */
+ if (!REG_P (val) && !MEM_P (val)
+- && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val)))
++ && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val)))
+ val = force_operand (val, NULL_RTX);
+
+ if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1))
+Index: gcc-4_6-branch/gcc/config/arm/arm-protos.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm-protos.h 2011-06-24 08:33:37.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/arm-protos.h 2011-09-16 20:16:00.217564705 -0700
+@@ -81,7 +81,6 @@
+ extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
+ bool);
+ extern bool arm_tls_referenced_p (rtx);
+-extern bool arm_cannot_force_const_mem (rtx);
+
+ extern int cirrus_memory_offset (rtx);
+ extern int arm_coproc_mem_operand (rtx, bool);
+Index: gcc-4_6-branch/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2011-09-16 20:14:34.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/arm.c 2011-09-16 20:16:00.237564275 -0700
+@@ -143,6 +143,8 @@
+ static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
+ tree);
+ static bool arm_have_conditional_execution (void);
++static bool arm_cannot_force_const_mem (rtx);
++static bool arm_legitimate_constant_p (enum machine_mode, rtx);
+ static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
+ static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+ static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
+@@ -241,6 +243,8 @@
+ static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
+ static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
+ static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *);
++static bool arm_array_mode_supported_p (enum machine_mode,
++ unsigned HOST_WIDE_INT);
+ static enum machine_mode arm_preferred_simd_mode (enum machine_mode);
+ static bool arm_class_likely_spilled_p (reg_class_t);
+ static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
+@@ -394,6 +398,8 @@
+ #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
+ #undef TARGET_VECTOR_MODE_SUPPORTED_P
+ #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
++#undef TARGET_ARRAY_MODE_SUPPORTED_P
++#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
+ #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
+ #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
+ #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
+@@ -523,6 +529,9 @@
+ #undef TARGET_HAVE_CONDITIONAL_EXECUTION
+ #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
+
++#undef TARGET_LEGITIMATE_CONSTANT_P
++#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
++
+ #undef TARGET_CANNOT_FORCE_CONST_MEM
+ #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
+
+@@ -6539,9 +6548,47 @@
+ return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
+ }
+
++/* Implement TARGET_LEGITIMATE_CONSTANT_P.
++
++ On the ARM, allow any integer (invalid ones are removed later by insn
++ patterns), nice doubles and symbol_refs which refer to the function's
++ constant pool XXX.
++
++ When generating pic allow anything. */
++
++static bool
++arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
++{
++ /* At present, we have no support for Neon structure constants, so forbid
++ them here. It might be possible to handle simple cases like 0 and -1
++ in future. */
++ if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
++ return false;
++
++ return flag_pic || !label_mentioned_p (x);
++}
++
++static bool
++thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
++{
++ return (GET_CODE (x) == CONST_INT
++ || GET_CODE (x) == CONST_DOUBLE
++ || CONSTANT_ADDRESS_P (x)
++ || flag_pic);
++}
++
++static bool
++arm_legitimate_constant_p (enum machine_mode mode, rtx x)
++{
++ return (!arm_cannot_force_const_mem (x)
++ && (TARGET_32BIT
++ ? arm_legitimate_constant_p_1 (mode, x)
++ : thumb_legitimate_constant_p (mode, x)));
++}
++
+ /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
+
+-bool
++static bool
+ arm_cannot_force_const_mem (rtx x)
+ {
+ rtx base, offset;
+@@ -16598,7 +16645,7 @@
+ {
+ rtx addr;
+ bool postinc = FALSE;
+- unsigned align, modesize, align_bits;
++ unsigned align, memsize, align_bits;
+
+ gcc_assert (GET_CODE (x) == MEM);
+ addr = XEXP (x, 0);
+@@ -16613,12 +16660,12 @@
+ instruction (for some alignments) as an aid to the memory subsystem
+ of the target. */
+ align = MEM_ALIGN (x) >> 3;
+- modesize = GET_MODE_SIZE (GET_MODE (x));
++ memsize = INTVAL (MEM_SIZE (x));
+
+ /* Only certain alignment specifiers are supported by the hardware. */
+- if (modesize == 16 && (align % 32) == 0)
++ if (memsize == 16 && (align % 32) == 0)
+ align_bits = 256;
+- else if ((modesize == 8 || modesize == 16) && (align % 16) == 0)
++ else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
+ align_bits = 128;
+ else if ((align % 8) == 0)
+ align_bits = 64;
+@@ -18278,12 +18325,14 @@
+ T_V2SI = 0x0004,
+ T_V2SF = 0x0008,
+ T_DI = 0x0010,
++ T_DREG = 0x001F,
+ T_V16QI = 0x0020,
+ T_V8HI = 0x0040,
+ T_V4SI = 0x0080,
+ T_V4SF = 0x0100,
+ T_V2DI = 0x0200,
+ T_TI = 0x0400,
++ T_QREG = 0x07E0,
+ T_EI = 0x0800,
+ T_OI = 0x1000
+ };
+@@ -18929,10 +18978,9 @@
+ if (is_load && k == 1)
+ {
+ /* Neon load patterns always have the memory operand
+- (a SImode pointer) in the operand 1 position. We
+- want a const pointer to the element type in that
+- position. */
+- gcc_assert (insn_data[icode].operand[k].mode == SImode);
++ in the operand 1 position. */
++ gcc_assert (insn_data[icode].operand[k].predicate
++ == neon_struct_operand);
+
+ switch (1 << j)
+ {
+@@ -18967,10 +19015,9 @@
+ else if (is_store && k == 0)
+ {
+ /* Similarly, Neon store patterns use operand 0 as
+- the memory location to store to (a SImode pointer).
+- Use a pointer to the element type of the store in
+- that position. */
+- gcc_assert (insn_data[icode].operand[k].mode == SImode);
++ the memory location to store to. */
++ gcc_assert (insn_data[icode].operand[k].predicate
++ == neon_struct_operand);
+
+ switch (1 << j)
+ {
+@@ -19290,12 +19337,13 @@
+ }
+
+ static enum insn_code
+-locate_neon_builtin_icode (int fcode, neon_itype *itype)
++locate_neon_builtin_icode (int fcode, neon_itype *itype,
++ enum neon_builtin_type_bits *type_bit)
+ {
+ neon_builtin_datum key
+ = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
+ neon_builtin_datum *found;
+- int idx;
++ int idx, type, ntypes;
+
+ key.base_fcode = fcode;
+ found = (neon_builtin_datum *)
+@@ -19308,20 +19356,84 @@
+ if (itype)
+ *itype = found->itype;
+
++ if (type_bit)
++ {
++ ntypes = 0;
++ for (type = 0; type < T_MAX; type++)
++ if (found->bits & (1 << type))
++ {
++ if (ntypes == idx)
++ break;
++ ntypes++;
++ }
++ gcc_assert (type < T_MAX);
++ *type_bit = (enum neon_builtin_type_bits) (1 << type);
++ }
+ return found->codes[idx];
+ }
+
+ typedef enum {
+ NEON_ARG_COPY_TO_REG,
+ NEON_ARG_CONSTANT,
++ NEON_ARG_MEMORY,
+ NEON_ARG_STOP
+ } builtin_arg;
+
+ #define NEON_MAX_BUILTIN_ARGS 5
+
++/* EXP is a pointer argument to a Neon load or store intrinsic. Derive
++ and return an expression for the accessed memory.
++
++ The intrinsic function operates on a block of registers that has
++ mode REG_MODE. This block contains vectors of type TYPE_BIT.
++ The function references the memory at EXP in mode MEM_MODE;
++ this mode may be BLKmode if no more suitable mode is available. */
++
++static tree
++neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
++ enum machine_mode reg_mode,
++ enum neon_builtin_type_bits type_bit)
++{
++ HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
++ tree elem_type, upper_bound, array_type;
++
++ /* Work out the size of the register block in bytes. */
++ reg_size = GET_MODE_SIZE (reg_mode);
++
++ /* Work out the size of each vector in bytes. */
++ gcc_assert (type_bit & (T_DREG | T_QREG));
++ vector_size = (type_bit & T_QREG ? 16 : 8);
++
++ /* Work out how many vectors there are. */
++ gcc_assert (reg_size % vector_size == 0);
++ nvectors = reg_size / vector_size;
++
++ /* Work out how many elements are being loaded or stored.
++ MEM_MODE == REG_MODE implies a one-to-one mapping between register
++ and memory elements; anything else implies a lane load or store. */
++ if (mem_mode == reg_mode)
++ nelems = vector_size * nvectors;
++ else
++ nelems = nvectors;
++
++ /* Work out the type of each element. */
++ gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
++ elem_type = TREE_TYPE (TREE_TYPE (exp));
++
++ /* Create a type that describes the full access. */
++ upper_bound = build_int_cst (size_type_node, nelems - 1);
++ array_type = build_array_type (elem_type, build_index_type (upper_bound));
++
++ /* Dereference EXP using that type. */
++ exp = convert (build_pointer_type (array_type), exp);
++ return fold_build2 (MEM_REF, array_type, exp,
++ build_int_cst (TREE_TYPE (exp), 0));
++}
++
+ /* Expand a Neon builtin. */
+ static rtx
+ arm_expand_neon_args (rtx target, int icode, int have_retval,
++ enum neon_builtin_type_bits type_bit,
+ tree exp, ...)
+ {
+ va_list ap;
+@@ -19330,7 +19442,9 @@
+ rtx op[NEON_MAX_BUILTIN_ARGS];
+ enum machine_mode tmode = insn_data[icode].operand[0].mode;
+ enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
++ enum machine_mode other_mode;
+ int argc = 0;
++ int opno;
+
+ if (have_retval
+ && (!target
+@@ -19348,26 +19462,46 @@
+ break;
+ else
+ {
++ opno = argc + have_retval;
++ mode[argc] = insn_data[icode].operand[opno].mode;
+ arg[argc] = CALL_EXPR_ARG (exp, argc);
++ if (thisarg == NEON_ARG_MEMORY)
++ {
++ other_mode = insn_data[icode].operand[1 - opno].mode;
++ arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
++ other_mode, type_bit);
++ }
+ op[argc] = expand_normal (arg[argc]);
+- mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
+
+ switch (thisarg)
+ {
+ case NEON_ARG_COPY_TO_REG:
+ /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
+- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
++ if (!(*insn_data[icode].operand[opno].predicate)
+ (op[argc], mode[argc]))
+ op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
+ break;
+
+ case NEON_ARG_CONSTANT:
+ /* FIXME: This error message is somewhat unhelpful. */
+- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
++ if (!(*insn_data[icode].operand[opno].predicate)
+ (op[argc], mode[argc]))
+ error ("argument must be a constant");
+ break;
+
++ case NEON_ARG_MEMORY:
++ gcc_assert (MEM_P (op[argc]));
++ PUT_MODE (op[argc], mode[argc]);
++ /* ??? arm_neon.h uses the same built-in functions for signed
++ and unsigned accesses, casting where necessary. This isn't
++ alias safe. */
++ set_mem_alias_set (op[argc], 0);
++ if (!(*insn_data[icode].operand[opno].predicate)
++ (op[argc], mode[argc]))
++ op[argc] = (replace_equiv_address
++ (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
++ break;
++
+ case NEON_ARG_STOP:
+ gcc_unreachable ();
+ }
+@@ -19446,14 +19580,15 @@
+ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
+ {
+ neon_itype itype;
+- enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
++ enum neon_builtin_type_bits type_bit;
++ enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
+
+ switch (itype)
+ {
+ case NEON_UNOP:
+ case NEON_CONVERT:
+ case NEON_DUPLANE:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+
+ case NEON_BINOP:
+@@ -19463,90 +19598,90 @@
+ case NEON_SCALARMULH:
+ case NEON_SHIFTINSERT:
+ case NEON_LOGICBINOP:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ NEON_ARG_STOP);
+
+ case NEON_TERNOP:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+ NEON_ARG_CONSTANT, NEON_ARG_STOP);
+
+ case NEON_GETLANE:
+ case NEON_FIXCONV:
+ case NEON_SHIFTIMM:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
+ NEON_ARG_STOP);
+
+ case NEON_CREATE:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+
+ case NEON_DUP:
+ case NEON_SPLIT:
+ case NEON_REINTERP:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+
+ case NEON_COMBINE:
+ case NEON_VTBL:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+
+ case NEON_RESULTPAIR:
+- return arm_expand_neon_args (target, icode, 0, exp,
++ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+ NEON_ARG_STOP);
+
+ case NEON_LANEMUL:
+ case NEON_LANEMULL:
+ case NEON_LANEMULH:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ NEON_ARG_CONSTANT, NEON_ARG_STOP);
+
+ case NEON_LANEMAC:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+ NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
+
+ case NEON_SHIFTACC:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ NEON_ARG_CONSTANT, NEON_ARG_STOP);
+
+ case NEON_SCALARMAC:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+ NEON_ARG_CONSTANT, NEON_ARG_STOP);
+
+ case NEON_SELECT:
+ case NEON_VTBX:
+- return arm_expand_neon_args (target, icode, 1, exp,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
+ NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
+ NEON_ARG_STOP);
+
+ case NEON_LOAD1:
+ case NEON_LOADSTRUCT:
+- return arm_expand_neon_args (target, icode, 1, exp,
+- NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++ NEON_ARG_MEMORY, NEON_ARG_STOP);
+
+ case NEON_LOAD1LANE:
+ case NEON_LOADSTRUCTLANE:
+- return arm_expand_neon_args (target, icode, 1, exp,
+- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
++ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
++ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ NEON_ARG_STOP);
+
+ case NEON_STORE1:
+ case NEON_STORESTRUCT:
+- return arm_expand_neon_args (target, icode, 0, exp,
+- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
++ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
+
+ case NEON_STORE1LANE:
+ case NEON_STORESTRUCTLANE:
+- return arm_expand_neon_args (target, icode, 0, exp,
+- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
++ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
++ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
+ NEON_ARG_STOP);
+ }
+
+@@ -22265,6 +22400,20 @@
+ return true;
+
+ return false;
++}
++
++/* Implements target hook array_mode_supported_p. */
++
++static bool
++arm_array_mode_supported_p (enum machine_mode mode,
++ unsigned HOST_WIDE_INT nelems)
++{
++ if (TARGET_NEON
++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
++ && (nelems >= 2 && nelems <= 4))
++ return true;
++
++ return false;
+ }
+
+ /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
+Index: gcc-4_6-branch/gcc/config/arm/arm.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/arm.h 2011-09-16 20:14:33.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/arm.h 2011-09-16 20:16:00.237564275 -0700
+@@ -1777,27 +1777,6 @@
+ #define TARGET_DEFAULT_WORD_RELOCATIONS 0
+ #endif
+
+-/* Nonzero if the constant value X is a legitimate general operand.
+- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
+-
+- On the ARM, allow any integer (invalid ones are removed later by insn
+- patterns), nice doubles and symbol_refs which refer to the function's
+- constant pool XXX.
+-
+- When generating pic allow anything. */
+-#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
+-
+-#define THUMB_LEGITIMATE_CONSTANT_P(X) \
+- ( GET_CODE (X) == CONST_INT \
+- || GET_CODE (X) == CONST_DOUBLE \
+- || CONSTANT_ADDRESS_P (X) \
+- || flag_pic)
+-
+-#define LEGITIMATE_CONSTANT_P(X) \
+- (!arm_cannot_force_const_mem (X) \
+- && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
+- : THUMB_LEGITIMATE_CONSTANT_P (X)))
+-
+ #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
+ #define SUBTARGET_NAME_ENCODING_LENGTHS
+ #endif
+Index: gcc-4_6-branch/gcc/config/arm/iterators.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/iterators.md 2011-06-24 08:33:37.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/iterators.md 2011-09-16 20:16:00.237564275 -0700
+@@ -194,24 +194,22 @@
+
+ ;; Mode of pair of elements for each vector mode, to define transfer
+ ;; size for structure lane/dup loads and stores.
+-(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
+- (V4HI "SI") (V8HI "SI")
++(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
++ (V4HI "SI") (V8HI "SI")
+ (V2SI "V2SI") (V4SI "V2SI")
+ (V2SF "V2SF") (V4SF "V2SF")
+ (DI "V2DI") (V2DI "V2DI")])
+
+ ;; Similar, for three elements.
+-;; ??? Should we define extra modes so that sizes of all three-element
+-;; accesses can be accurately represented?
+-(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI")
+- (V4HI "V4HI") (V8HI "V4HI")
+- (V2SI "V4SI") (V4SI "V4SI")
+- (V2SF "V4SF") (V4SF "V4SF")
+- (DI "EI") (V2DI "EI")])
++(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
++ (V4HI "BLK") (V8HI "BLK")
++ (V2SI "BLK") (V4SI "BLK")
++ (V2SF "BLK") (V4SF "BLK")
++ (DI "EI") (V2DI "EI")])
+
+ ;; Similar, for four elements.
+ (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
+- (V4HI "V4HI") (V8HI "V4HI")
++ (V4HI "V4HI") (V8HI "V4HI")
+ (V2SI "V4SI") (V4SI "V4SI")
+ (V2SF "V4SF") (V4SF "V4SF")
+ (DI "OI") (V2DI "OI")])
+Index: gcc-4_6-branch/gcc/config/arm/neon-testgen.ml
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/neon-testgen.ml 2011-06-24 08:33:37.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/neon-testgen.ml 2011-09-16 20:16:00.237564275 -0700
+@@ -177,7 +177,7 @@
+ let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
+ "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
+ | (PtrTo elt | CstPtrTo elt) ->
+- "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]"
++ "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
+ | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+ | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+ | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
+Index: gcc-4_6-branch/gcc/config/arm/neon.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/neon.md 2011-07-19 21:50:44.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/neon.md 2011-09-16 20:16:00.247564269 -0700
+@@ -4250,16 +4250,16 @@
+
+ (define_insn "neon_vld1<mode>"
+ [(set (match_operand:VDQX 0 "s_register_operand" "=w")
+- (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))]
++ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
+ UNSPEC_VLD1))]
+ "TARGET_NEON"
+- "vld1.<V_sz_elem>\t%h0, [%1]"
++ "vld1.<V_sz_elem>\t%h0, %A1"
+ [(set_attr "neon_type" "neon_vld1_1_2_regs")]
+ )
+
+ (define_insn "neon_vld1_lane<mode>"
+ [(set (match_operand:VDX 0 "s_register_operand" "=w")
+- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:VDX 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")]
+ UNSPEC_VLD1_LANE))]
+@@ -4270,9 +4270,9 @@
+ if (lane < 0 || lane >= max)
+ error ("lane out of range");
+ if (max == 1)
+- return "vld1.<V_sz_elem>\t%P0, [%1]";
++ return "vld1.<V_sz_elem>\t%P0, %A1";
+ else
+- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
++ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
+@@ -4282,7 +4282,7 @@
+
+ (define_insn "neon_vld1_lane<mode>"
+ [(set (match_operand:VQX 0 "s_register_operand" "=w")
+- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:VQX 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")]
+ UNSPEC_VLD1_LANE))]
+@@ -4301,9 +4301,9 @@
+ }
+ operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
+ if (max == 2)
+- return "vld1.<V_sz_elem>\t%P0, [%1]";
++ return "vld1.<V_sz_elem>\t%P0, %A1";
+ else
+- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
++ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
+@@ -4313,14 +4313,14 @@
+
+ (define_insn "neon_vld1_dup<mode>"
+ [(set (match_operand:VDX 0 "s_register_operand" "=w")
+- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
++ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
+ UNSPEC_VLD1_DUP))]
+ "TARGET_NEON"
+ {
+ if (GET_MODE_NUNITS (<MODE>mode) > 1)
+- return "vld1.<V_sz_elem>\t{%P0[]}, [%1]";
++ return "vld1.<V_sz_elem>\t{%P0[]}, %A1";
+ else
+- return "vld1.<V_sz_elem>\t%h0, [%1]";
++ return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4330,14 +4330,14 @@
+
+ (define_insn "neon_vld1_dup<mode>"
+ [(set (match_operand:VQX 0 "s_register_operand" "=w")
+- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
++ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
+ UNSPEC_VLD1_DUP))]
+ "TARGET_NEON"
+ {
+ if (GET_MODE_NUNITS (<MODE>mode) > 2)
+- return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
++ return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
+ else
+- return "vld1.<V_sz_elem>\t%h0, [%1]";
++ return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4346,15 +4346,15 @@
+ )
+
+ (define_insn "neon_vst1<mode>"
+- [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
+ (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
+ UNSPEC_VST1))]
+ "TARGET_NEON"
+- "vst1.<V_sz_elem>\t%h1, [%0]"
++ "vst1.<V_sz_elem>\t%h1, %A0"
+ [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
+
+ (define_insn "neon_vst1_lane<mode>"
+- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
+ (vec_select:<V_elem>
+ (match_operand:VDX 1 "s_register_operand" "w")
+ (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
+@@ -4365,9 +4365,9 @@
+ if (lane < 0 || lane >= max)
+ error ("lane out of range");
+ if (max == 1)
+- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
++ return "vst1.<V_sz_elem>\t{%P1}, %A0";
+ else
+- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
++ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
+@@ -4375,7 +4375,7 @@
+ (const_string "neon_vst1_vst2_lane")))])
+
+ (define_insn "neon_vst1_lane<mode>"
+- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
+ (vec_select:<V_elem>
+ (match_operand:VQX 1 "s_register_operand" "w")
+ (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
+@@ -4394,24 +4394,24 @@
+ }
+ operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
+ if (max == 2)
+- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
++ return "vst1.<V_sz_elem>\t{%P1}, %A0";
+ else
+- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
++ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
+ }
+ [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+
+ (define_insn "neon_vld2<mode>"
+ [(set (match_operand:TI 0 "s_register_operand" "=w")
+- (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD2))]
+ "TARGET_NEON"
+ {
+ if (<V_sz_elem> == 64)
+- return "vld1.64\t%h0, [%1]";
++ return "vld1.64\t%h0, %A1";
+ else
+- return "vld2.<V_sz_elem>\t%h0, [%1]";
++ return "vld2.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4421,16 +4421,16 @@
+
+ (define_insn "neon_vld2<mode>"
+ [(set (match_operand:OI 0 "s_register_operand" "=w")
+- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD2))]
+ "TARGET_NEON"
+- "vld2.<V_sz_elem>\t%h0, [%1]"
++ "vld2.<V_sz_elem>\t%h0, %A1"
+ [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
+
+ (define_insn "neon_vld2_lane<mode>"
+ [(set (match_operand:TI 0 "s_register_operand" "=w")
+- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:TI 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4447,7 +4447,7 @@
+ ops[1] = gen_rtx_REG (DImode, regno + 2);
+ ops[2] = operands[1];
+ ops[3] = operands[3];
+- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
++ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+@@ -4455,7 +4455,7 @@
+
+ (define_insn "neon_vld2_lane<mode>"
+ [(set (match_operand:OI 0 "s_register_operand" "=w")
+- (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:OI 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4477,7 +4477,7 @@
+ ops[1] = gen_rtx_REG (DImode, regno + 4);
+ ops[2] = operands[1];
+ ops[3] = GEN_INT (lane);
+- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
++ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vld1_vld2_lane")]
+@@ -4485,15 +4485,15 @@
+
+ (define_insn "neon_vld2_dup<mode>"
+ [(set (match_operand:TI 0 "s_register_operand" "=w")
+- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD2_DUP))]
+ "TARGET_NEON"
+ {
+ if (GET_MODE_NUNITS (<MODE>mode) > 1)
+- return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
++ return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
+ else
+- return "vld1.<V_sz_elem>\t%h0, [%1]";
++ return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4502,16 +4502,16 @@
+ )
+
+ (define_insn "neon_vst2<mode>"
+- [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
+ (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST2))]
+ "TARGET_NEON"
+ {
+ if (<V_sz_elem> == 64)
+- return "vst1.64\t%h1, [%0]";
++ return "vst1.64\t%h1, %A0";
+ else
+- return "vst2.<V_sz_elem>\t%h1, [%0]";
++ return "vst2.<V_sz_elem>\t%h1, %A0";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4520,17 +4520,17 @@
+ )
+
+ (define_insn "neon_vst2<mode>"
+- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST2))]
+ "TARGET_NEON"
+- "vst2.<V_sz_elem>\t%h1, [%0]"
++ "vst2.<V_sz_elem>\t%h1, %A0"
+ [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
+ )
+
+ (define_insn "neon_vst2_lane<mode>"
+- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
+ (unspec:<V_two_elem>
+ [(match_operand:TI 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")
+@@ -4548,14 +4548,14 @@
+ ops[1] = gen_rtx_REG (DImode, regno);
+ ops[2] = gen_rtx_REG (DImode, regno + 2);
+ ops[3] = operands[2];
+- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
++ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+ )
+
+ (define_insn "neon_vst2_lane<mode>"
+- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
+ (unspec:<V_two_elem>
+ [(match_operand:OI 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")
+@@ -4578,7 +4578,7 @@
+ ops[1] = gen_rtx_REG (DImode, regno);
+ ops[2] = gen_rtx_REG (DImode, regno + 4);
+ ops[3] = GEN_INT (lane);
+- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
++ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vst1_vst2_lane")]
+@@ -4586,15 +4586,15 @@
+
+ (define_insn "neon_vld3<mode>"
+ [(set (match_operand:EI 0 "s_register_operand" "=w")
+- (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD3))]
+ "TARGET_NEON"
+ {
+ if (<V_sz_elem> == 64)
+- return "vld1.64\t%h0, [%1]";
++ return "vld1.64\t%h0, %A1";
+ else
+- return "vld3.<V_sz_elem>\t%h0, [%1]";
++ return "vld3.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4603,27 +4603,25 @@
+ )
+
+ (define_expand "neon_vld3<mode>"
+- [(match_operand:CI 0 "s_register_operand" "=w")
+- (match_operand:SI 1 "s_register_operand" "+r")
++ [(match_operand:CI 0 "s_register_operand")
++ (match_operand:CI 1 "neon_struct_operand")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+ {
+- emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0],
+- operands[1], operands[1]));
+- emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
+- operands[1], operands[1]));
++ rtx mem;
++
++ mem = adjust_address (operands[1], EImode, 0);
++ emit_insn (gen_neon_vld3qa<mode> (operands[0], mem));
++ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
++ emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0]));
+ DONE;
+ })
+
+ (define_insn "neon_vld3qa<mode>"
+ [(set (match_operand:CI 0 "s_register_operand" "=w")
+- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
+- (match_operand:CI 1 "s_register_operand" "0")
++ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VLD3A))
+- (set (match_operand:SI 2 "s_register_operand" "=r")
+- (plus:SI (match_dup 3)
+- (const_int 24)))]
++ UNSPEC_VLD3A))]
+ "TARGET_NEON"
+ {
+ int regno = REGNO (operands[0]);
+@@ -4631,8 +4629,8 @@
+ ops[0] = gen_rtx_REG (DImode, regno);
+ ops[1] = gen_rtx_REG (DImode, regno + 4);
+ ops[2] = gen_rtx_REG (DImode, regno + 8);
+- ops[3] = operands[2];
+- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
++ ops[3] = operands[1];
++ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4640,13 +4638,10 @@
+
+ (define_insn "neon_vld3qb<mode>"
+ [(set (match_operand:CI 0 "s_register_operand" "=w")
+- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
+- (match_operand:CI 1 "s_register_operand" "0")
++ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
++ (match_operand:CI 2 "s_register_operand" "0")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VLD3B))
+- (set (match_operand:SI 2 "s_register_operand" "=r")
+- (plus:SI (match_dup 3)
+- (const_int 24)))]
++ UNSPEC_VLD3B))]
+ "TARGET_NEON"
+ {
+ int regno = REGNO (operands[0]);
+@@ -4654,8 +4649,8 @@
+ ops[0] = gen_rtx_REG (DImode, regno + 2);
+ ops[1] = gen_rtx_REG (DImode, regno + 6);
+ ops[2] = gen_rtx_REG (DImode, regno + 10);
+- ops[3] = operands[2];
+- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
++ ops[3] = operands[1];
++ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4663,7 +4658,7 @@
+
+ (define_insn "neon_vld3_lane<mode>"
+ [(set (match_operand:EI 0 "s_register_operand" "=w")
+- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:EI 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4681,7 +4676,7 @@
+ ops[2] = gen_rtx_REG (DImode, regno + 4);
+ ops[3] = operands[1];
+ ops[4] = operands[3];
+- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
++ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+ ops);
+ return "";
+ }
+@@ -4690,7 +4685,7 @@
+
+ (define_insn "neon_vld3_lane<mode>"
+ [(set (match_operand:CI 0 "s_register_operand" "=w")
+- (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:CI 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4713,7 +4708,7 @@
+ ops[2] = gen_rtx_REG (DImode, regno + 8);
+ ops[3] = operands[1];
+ ops[4] = GEN_INT (lane);
+- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
++ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+ ops);
+ return "";
+ }
+@@ -4722,7 +4717,7 @@
+
+ (define_insn "neon_vld3_dup<mode>"
+ [(set (match_operand:EI 0 "s_register_operand" "=w")
+- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD3_DUP))]
+ "TARGET_NEON"
+@@ -4735,11 +4730,11 @@
+ ops[1] = gen_rtx_REG (DImode, regno + 2);
+ ops[2] = gen_rtx_REG (DImode, regno + 4);
+ ops[3] = operands[1];
+- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops);
++ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
+ return "";
+ }
+ else
+- return "vld1.<V_sz_elem>\t%h0, [%1]";
++ return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -4747,16 +4742,16 @@
+ (const_string "neon_vld1_1_2_regs")))])
+
+ (define_insn "neon_vst3<mode>"
+- [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
+ (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST3))]
+ "TARGET_NEON"
+ {
+ if (<V_sz_elem> == 64)
+- return "vst1.64\t%h1, [%0]";
++ return "vst1.64\t%h1, %A0";
+ else
+- return "vst3.<V_sz_elem>\t%h1, [%0]";
++ return "vst3.<V_sz_elem>\t%h1, %A0";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4764,62 +4759,60 @@
+ (const_string "neon_vst2_4_regs_vst3_vst4")))])
+
+ (define_expand "neon_vst3<mode>"
+- [(match_operand:SI 0 "s_register_operand" "+r")
+- (match_operand:CI 1 "s_register_operand" "w")
++ [(match_operand:CI 0 "neon_struct_operand")
++ (match_operand:CI 1 "s_register_operand")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+ {
+- emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1]));
+- emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
++ rtx mem;
++
++ mem = adjust_address (operands[0], EImode, 0);
++ emit_insn (gen_neon_vst3qa<mode> (mem, operands[1]));
++ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
++ emit_insn (gen_neon_vst3qb<mode> (mem, operands[1]));
+ DONE;
+ })
+
+ (define_insn "neon_vst3qa<mode>"
+- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
+- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
++ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
++ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VST3A))
+- (set (match_operand:SI 0 "s_register_operand" "=r")
+- (plus:SI (match_dup 1)
+- (const_int 24)))]
++ UNSPEC_VST3A))]
+ "TARGET_NEON"
+ {
+- int regno = REGNO (operands[2]);
++ int regno = REGNO (operands[1]);
+ rtx ops[4];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (DImode, regno);
+ ops[2] = gen_rtx_REG (DImode, regno + 4);
+ ops[3] = gen_rtx_REG (DImode, regno + 8);
+- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
++ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+
+ (define_insn "neon_vst3qb<mode>"
+- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
+- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
++ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
++ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VST3B))
+- (set (match_operand:SI 0 "s_register_operand" "=r")
+- (plus:SI (match_dup 1)
+- (const_int 24)))]
++ UNSPEC_VST3B))]
+ "TARGET_NEON"
+ {
+- int regno = REGNO (operands[2]);
++ int regno = REGNO (operands[1]);
+ rtx ops[4];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (DImode, regno + 2);
+ ops[2] = gen_rtx_REG (DImode, regno + 6);
+ ops[3] = gen_rtx_REG (DImode, regno + 10);
+- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
++ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+
+ (define_insn "neon_vst3_lane<mode>"
+- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
+ (unspec:<V_three_elem>
+ [(match_operand:EI 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")
+@@ -4838,7 +4831,7 @@
+ ops[2] = gen_rtx_REG (DImode, regno + 2);
+ ops[3] = gen_rtx_REG (DImode, regno + 4);
+ ops[4] = operands[2];
+- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
++ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+ ops);
+ return "";
+ }
+@@ -4846,7 +4839,7 @@
+ )
+
+ (define_insn "neon_vst3_lane<mode>"
+- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
+ (unspec:<V_three_elem>
+ [(match_operand:CI 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")
+@@ -4870,7 +4863,7 @@
+ ops[2] = gen_rtx_REG (DImode, regno + 4);
+ ops[3] = gen_rtx_REG (DImode, regno + 8);
+ ops[4] = GEN_INT (lane);
+- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
++ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+ ops);
+ return "";
+ }
+@@ -4878,15 +4871,15 @@
+
+ (define_insn "neon_vld4<mode>"
+ [(set (match_operand:OI 0 "s_register_operand" "=w")
+- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD4))]
+ "TARGET_NEON"
+ {
+ if (<V_sz_elem> == 64)
+- return "vld1.64\t%h0, [%1]";
++ return "vld1.64\t%h0, %A1";
+ else
+- return "vld4.<V_sz_elem>\t%h0, [%1]";
++ return "vld4.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -4895,27 +4888,25 @@
+ )
+
+ (define_expand "neon_vld4<mode>"
+- [(match_operand:XI 0 "s_register_operand" "=w")
+- (match_operand:SI 1 "s_register_operand" "+r")
++ [(match_operand:XI 0 "s_register_operand")
++ (match_operand:XI 1 "neon_struct_operand")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+ {
+- emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0],
+- operands[1], operands[1]));
+- emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
+- operands[1], operands[1]));
++ rtx mem;
++
++ mem = adjust_address (operands[1], OImode, 0);
++ emit_insn (gen_neon_vld4qa<mode> (operands[0], mem));
++ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
++ emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0]));
+ DONE;
+ })
+
+ (define_insn "neon_vld4qa<mode>"
+ [(set (match_operand:XI 0 "s_register_operand" "=w")
+- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
+- (match_operand:XI 1 "s_register_operand" "0")
++ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VLD4A))
+- (set (match_operand:SI 2 "s_register_operand" "=r")
+- (plus:SI (match_dup 3)
+- (const_int 32)))]
++ UNSPEC_VLD4A))]
+ "TARGET_NEON"
+ {
+ int regno = REGNO (operands[0]);
+@@ -4924,8 +4915,8 @@
+ ops[1] = gen_rtx_REG (DImode, regno + 4);
+ ops[2] = gen_rtx_REG (DImode, regno + 8);
+ ops[3] = gen_rtx_REG (DImode, regno + 12);
+- ops[4] = operands[2];
+- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
++ ops[4] = operands[1];
++ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4933,13 +4924,10 @@
+
+ (define_insn "neon_vld4qb<mode>"
+ [(set (match_operand:XI 0 "s_register_operand" "=w")
+- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
+- (match_operand:XI 1 "s_register_operand" "0")
++ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
++ (match_operand:XI 2 "s_register_operand" "0")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VLD4B))
+- (set (match_operand:SI 2 "s_register_operand" "=r")
+- (plus:SI (match_dup 3)
+- (const_int 32)))]
++ UNSPEC_VLD4B))]
+ "TARGET_NEON"
+ {
+ int regno = REGNO (operands[0]);
+@@ -4948,8 +4936,8 @@
+ ops[1] = gen_rtx_REG (DImode, regno + 6);
+ ops[2] = gen_rtx_REG (DImode, regno + 10);
+ ops[3] = gen_rtx_REG (DImode, regno + 14);
+- ops[4] = operands[2];
+- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
++ ops[4] = operands[1];
++ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vld3_vld4")]
+@@ -4957,7 +4945,7 @@
+
+ (define_insn "neon_vld4_lane<mode>"
+ [(set (match_operand:OI 0 "s_register_operand" "=w")
+- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:OI 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -4976,7 +4964,7 @@
+ ops[3] = gen_rtx_REG (DImode, regno + 6);
+ ops[4] = operands[1];
+ ops[5] = operands[3];
+- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
++ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
+ ops);
+ return "";
+ }
+@@ -4985,7 +4973,7 @@
+
+ (define_insn "neon_vld4_lane<mode>"
+ [(set (match_operand:XI 0 "s_register_operand" "=w")
+- (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+ (match_operand:XI 2 "s_register_operand" "0")
+ (match_operand:SI 3 "immediate_operand" "i")
+ (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+@@ -5009,7 +4997,7 @@
+ ops[3] = gen_rtx_REG (DImode, regno + 12);
+ ops[4] = operands[1];
+ ops[5] = GEN_INT (lane);
+- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
++ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
+ ops);
+ return "";
+ }
+@@ -5018,7 +5006,7 @@
+
+ (define_insn "neon_vld4_dup<mode>"
+ [(set (match_operand:OI 0 "s_register_operand" "=w")
+- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
++ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VLD4_DUP))]
+ "TARGET_NEON"
+@@ -5032,12 +5020,12 @@
+ ops[2] = gen_rtx_REG (DImode, regno + 4);
+ ops[3] = gen_rtx_REG (DImode, regno + 6);
+ ops[4] = operands[1];
+- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]",
++ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4",
+ ops);
+ return "";
+ }
+ else
+- return "vld1.<V_sz_elem>\t%h0, [%1]";
++ return "vld1.<V_sz_elem>\t%h0, %A1";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
+@@ -5046,16 +5034,16 @@
+ )
+
+ (define_insn "neon_vst4<mode>"
+- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
+ (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST4))]
+ "TARGET_NEON"
+ {
+ if (<V_sz_elem> == 64)
+- return "vst1.64\t%h1, [%0]";
++ return "vst1.64\t%h1, %A0";
+ else
+- return "vst4.<V_sz_elem>\t%h1, [%0]";
++ return "vst4.<V_sz_elem>\t%h1, %A0";
+ }
+ [(set (attr "neon_type")
+ (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
+@@ -5064,64 +5052,62 @@
+ )
+
+ (define_expand "neon_vst4<mode>"
+- [(match_operand:SI 0 "s_register_operand" "+r")
+- (match_operand:XI 1 "s_register_operand" "w")
++ [(match_operand:XI 0 "neon_struct_operand")
++ (match_operand:XI 1 "s_register_operand")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ "TARGET_NEON"
+ {
+- emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1]));
+- emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
++ rtx mem;
++
++ mem = adjust_address (operands[0], OImode, 0);
++ emit_insn (gen_neon_vst4qa<mode> (mem, operands[1]));
++ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
++ emit_insn (gen_neon_vst4qb<mode> (mem, operands[1]));
+ DONE;
+ })
+
+ (define_insn "neon_vst4qa<mode>"
+- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
+- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
++ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VST4A))
+- (set (match_operand:SI 0 "s_register_operand" "=r")
+- (plus:SI (match_dup 1)
+- (const_int 32)))]
++ UNSPEC_VST4A))]
+ "TARGET_NEON"
+ {
+- int regno = REGNO (operands[2]);
++ int regno = REGNO (operands[1]);
+ rtx ops[5];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (DImode, regno);
+ ops[2] = gen_rtx_REG (DImode, regno + 4);
+ ops[3] = gen_rtx_REG (DImode, regno + 8);
+ ops[4] = gen_rtx_REG (DImode, regno + 12);
+- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
++ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+
+ (define_insn "neon_vst4qb<mode>"
+- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
+- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
++ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+- UNSPEC_VST4B))
+- (set (match_operand:SI 0 "s_register_operand" "=r")
+- (plus:SI (match_dup 1)
+- (const_int 32)))]
++ UNSPEC_VST4B))]
+ "TARGET_NEON"
+ {
+- int regno = REGNO (operands[2]);
++ int regno = REGNO (operands[1]);
+ rtx ops[5];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (DImode, regno + 2);
+ ops[2] = gen_rtx_REG (DImode, regno + 6);
+ ops[3] = gen_rtx_REG (DImode, regno + 10);
+ ops[4] = gen_rtx_REG (DImode, regno + 14);
+- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
++ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+ return "";
+ }
+ [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
+ )
+
+ (define_insn "neon_vst4_lane<mode>"
+- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
+ (unspec:<V_four_elem>
+ [(match_operand:OI 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")
+@@ -5141,7 +5127,7 @@
+ ops[3] = gen_rtx_REG (DImode, regno + 4);
+ ops[4] = gen_rtx_REG (DImode, regno + 6);
+ ops[5] = operands[2];
+- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
++ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
+ ops);
+ return "";
+ }
+@@ -5149,7 +5135,7 @@
+ )
+
+ (define_insn "neon_vst4_lane<mode>"
+- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
++ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
+ (unspec:<V_four_elem>
+ [(match_operand:XI 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")
+@@ -5174,7 +5160,7 @@
+ ops[3] = gen_rtx_REG (DImode, regno + 8);
+ ops[4] = gen_rtx_REG (DImode, regno + 12);
+ ops[5] = GEN_INT (lane);
+- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
++ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
+ ops);
+ return "";
+ }
+Index: gcc-4_6-branch/gcc/config/arm/predicates.md
+===================================================================
+--- gcc-4_6-branch.orig/gcc/config/arm/predicates.md 2011-09-16 19:58:21.000000000 -0700
++++ gcc-4_6-branch/gcc/config/arm/predicates.md 2011-09-16 20:19:03.967834108 -0700
+@@ -686,3 +686,8 @@
+
+ (define_special_predicate "add_operator"
+ (match_code "plus"))
++
++(define_special_predicate "neon_struct_operand"
++ (and (match_code "mem")
++ (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
++
+Index: gcc-4_6-branch/gcc/doc/tm.texi
+===================================================================
+--- gcc-4_6-branch.orig/gcc/doc/tm.texi 2011-06-24 08:13:00.000000000 -0700
++++ gcc-4_6-branch/gcc/doc/tm.texi 2011-09-16 20:16:00.257564628 -0700
+@@ -2533,7 +2533,7 @@
+ register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant. If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+ of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+
+ If an insn has pseudos in it after register allocation, reload will go
+@@ -2570,8 +2570,8 @@
+ register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant. If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+-of using @code{PREFERRED_RELOAD_CLASS}.
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+
+ If an insn has pseudos in it after register allocation, reload will go
+ through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
+@@ -4319,6 +4319,34 @@
+ must have move patterns for this mode.
+ @end deftypefn
+
++@deftypefn {Target Hook} bool TARGET_ARRAY_MODE_SUPPORTED_P (enum machine_mode @var{mode}, unsigned HOST_WIDE_INT @var{nelems})
++Return true if GCC should try to use a scalar mode to store an array
++of @var{nelems} elements, given that each element has mode @var{mode}.
++Returning true here overrides the usual @code{MAX_FIXED_MODE} limit
++and allows GCC to use any defined integer mode.
++
++One use of this hook is to support vector load and store operations
++that operate on several homogeneous vectors. For example, ARM NEON
++has operations like:
++
++@smallexample
++int8x8x3_t vld3_s8 (const int8_t *)
++@end smallexample
++
++where the return type is defined as:
++
++@smallexample
++typedef struct int8x8x3_t
++@{
++ int8x8_t val[3];
++@} int8x8x3_t;
++@end smallexample
++
++If this hook allows @code{val} to have a scalar mode, then
++@code{int8x8x3_t} can have the same mode. GCC can then store
++@code{int8x8x3_t}s in registers rather than forcing them onto the stack.
++@end deftypefn
++
+ @deftypefn {Target Hook} bool TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P (enum machine_mode @var{mode})
+ Define this to return nonzero for machine modes for which the port has
+ small register classes. If this target hook returns nonzero for a given
+@@ -5577,13 +5605,13 @@
+ @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
+ @end defmac
+
+-@defmac LEGITIMATE_CONSTANT_P (@var{x})
+-A C expression that is nonzero if @var{x} is a legitimate constant for
+-an immediate operand on the target machine. You can assume that
+-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact,
+-@samp{1} is a suitable definition for this macro on machines where
+-anything @code{CONSTANT_P} is valid.
+-@end defmac
++@deftypefn {Target Hook} bool TARGET_LEGITIMATE_CONSTANT_P (enum machine_mode @var{mode}, rtx @var{x})
++This hook returns true if @var{x} is a legitimate constant for a
++@var{mode}-mode immediate operand on the target machine. You can assume that
++@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
++
++The default definition returns true.
++@end deftypefn
+
+ @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x})
+ This hook is used to undo the possibly obfuscating effects of the
+Index: gcc-4_6-branch/gcc/doc/tm.texi.in
+===================================================================
+--- gcc-4_6-branch.orig/gcc/doc/tm.texi.in 2011-06-24 08:13:00.000000000 -0700
++++ gcc-4_6-branch/gcc/doc/tm.texi.in 2011-09-16 20:16:00.257564628 -0700
+@@ -2521,7 +2521,7 @@
+ register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant. If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+ of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+
+ If an insn has pseudos in it after register allocation, reload will go
+@@ -2558,8 +2558,8 @@
+ register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
+ @var{x} is a floating-point constant. If the constant can't be loaded
+ into any kind of register, code generation will be better if
+-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
+-of using @code{PREFERRED_RELOAD_CLASS}.
++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
++of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
+
+ If an insn has pseudos in it after register allocation, reload will go
+ through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
+@@ -4305,6 +4305,8 @@
+ must have move patterns for this mode.
+ @end deftypefn
+
++@hook TARGET_ARRAY_MODE_SUPPORTED_P
++
+ @hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
+ Define this to return nonzero for machine modes for which the port has
+ small register classes. If this target hook returns nonzero for a given
+@@ -5555,13 +5557,13 @@
+ @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
+ @end defmac
+
+-@defmac LEGITIMATE_CONSTANT_P (@var{x})
+-A C expression that is nonzero if @var{x} is a legitimate constant for
+-an immediate operand on the target machine. You can assume that
+-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact,
+-@samp{1} is a suitable definition for this macro on machines where
+-anything @code{CONSTANT_P} is valid.
+-@end defmac
++@hook TARGET_LEGITIMATE_CONSTANT_P
++This hook returns true if @var{x} is a legitimate constant for a
++@var{mode}-mode immediate operand on the target machine. You can assume that
++@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
++
++The default definition returns true.
++@end deftypefn
+
+ @hook TARGET_DELEGITIMIZE_ADDRESS
+ This hook is used to undo the possibly obfuscating effects of the
+Index: gcc-4_6-branch/gcc/expr.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/expr.c 2011-09-16 20:14:32.000000000 -0700
++++ gcc-4_6-branch/gcc/expr.c 2011-09-16 20:16:00.267564792 -0700
+@@ -1497,7 +1497,7 @@
+ if (nregs == 0)
+ return;
+
+- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
++ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
+ x = validize_mem (force_const_mem (mode, x));
+
+ /* See if the machine can do this with a load multiple insn. */
+@@ -2308,7 +2308,7 @@
+ offset -= size;
+
+ cst = (*constfun) (constfundata, offset, mode);
+- if (!LEGITIMATE_CONSTANT_P (cst))
++ if (!targetm.legitimate_constant_p (mode, cst))
+ return 0;
+
+ if (!reverse)
+@@ -3363,7 +3363,7 @@
+
+ y_cst = y;
+
+- if (!LEGITIMATE_CONSTANT_P (y))
++ if (!targetm.legitimate_constant_p (mode, y))
+ {
+ y = force_const_mem (mode, y);
+
+@@ -3419,7 +3419,7 @@
+
+ REAL_VALUE_FROM_CONST_DOUBLE (r, y);
+
+- if (LEGITIMATE_CONSTANT_P (y))
++ if (targetm.legitimate_constant_p (dstmode, y))
+ oldcost = rtx_cost (y, SET, speed);
+ else
+ oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed);
+@@ -3442,7 +3442,7 @@
+
+ trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode);
+
+- if (LEGITIMATE_CONSTANT_P (trunc_y))
++ if (targetm.legitimate_constant_p (srcmode, trunc_y))
+ {
+ /* Skip if the target needs extra instructions to perform
+ the extension. */
+@@ -3855,7 +3855,7 @@
+ by setting SKIP to 0. */
+ skip = (reg_parm_stack_space == 0) ? 0 : not_stack;
+
+- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
++ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
+ x = validize_mem (force_const_mem (mode, x));
+
+ /* If X is a hard register in a non-integer mode, copy it into a pseudo;
+@@ -9108,7 +9108,7 @@
+ constant and we don't need a memory reference. */
+ if (CONSTANT_P (op0)
+ && mode2 != BLKmode
+- && LEGITIMATE_CONSTANT_P (op0)
++ && targetm.legitimate_constant_p (mode2, op0)
+ && !must_force_mem)
+ op0 = force_reg (mode2, op0);
+
+Index: gcc-4_6-branch/gcc/hooks.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/hooks.c 2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/hooks.c 2011-09-16 20:16:00.267564792 -0700
+@@ -101,6 +101,15 @@
+ return true;
+ }
+
++/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT)
++ and returns false. */
++bool
++hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED,
++ unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED)
++{
++ return false;
++}
++
+ /* Generic hook that takes (FILE *, const char *) and does nothing. */
+ void
+ hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED)
+Index: gcc-4_6-branch/gcc/hooks.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/hooks.h 2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/hooks.h 2011-09-16 20:16:00.267564792 -0700
+@@ -34,6 +34,8 @@
+ extern bool hook_bool_mode_true (enum machine_mode);
+ extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx);
+ extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx);
++extern bool hook_bool_mode_uhwi_false (enum machine_mode,
++ unsigned HOST_WIDE_INT);
+ extern bool hook_bool_tree_false (tree);
+ extern bool hook_bool_const_tree_false (const_tree);
+ extern bool hook_bool_tree_true (tree);
+Index: gcc-4_6-branch/gcc/recog.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/recog.c 2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/recog.c 2011-09-16 20:16:00.277564886 -0700
+@@ -930,7 +930,9 @@
+ return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
+ || mode == VOIDmode)
+ && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+- && LEGITIMATE_CONSTANT_P (op));
++ && targetm.legitimate_constant_p (mode == VOIDmode
++ ? GET_MODE (op)
++ : mode, op));
+
+ /* Except for certain constants with VOIDmode, already checked for,
+ OP's mode must match MODE if MODE specifies a mode. */
+@@ -1107,7 +1109,9 @@
+ && (GET_MODE (op) == mode || mode == VOIDmode
+ || GET_MODE (op) == VOIDmode)
+ && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
+- && LEGITIMATE_CONSTANT_P (op));
++ && targetm.legitimate_constant_p (mode == VOIDmode
++ ? GET_MODE (op)
++ : mode, op));
+ }
+
+ /* Returns 1 if OP is an operand that is a CONST_INT. */
+Index: gcc-4_6-branch/gcc/reload.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/reload.c 2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/reload.c 2011-09-16 20:16:00.277564886 -0700
+@@ -4721,7 +4721,8 @@
+ simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
+ GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
+ gcc_assert (tem);
+- if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem))
++ if (CONSTANT_P (tem)
++ && !targetm.legitimate_constant_p (GET_MODE (x), tem))
+ {
+ tem = force_const_mem (GET_MODE (x), tem);
+ i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
+@@ -6049,7 +6050,7 @@
+ enum reload_type type, int ind_levels)
+ {
+ if (CONSTANT_P (x)
+- && (! LEGITIMATE_CONSTANT_P (x)
++ && (!targetm.legitimate_constant_p (mode, x)
+ || targetm.preferred_reload_class (x, rclass) == NO_REGS))
+ {
+ x = force_const_mem (mode, x);
+@@ -6059,7 +6060,7 @@
+
+ else if (GET_CODE (x) == PLUS
+ && CONSTANT_P (XEXP (x, 1))
+- && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
++ && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1))
+ || targetm.preferred_reload_class (XEXP (x, 1), rclass)
+ == NO_REGS))
+ {
+Index: gcc-4_6-branch/gcc/reload1.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/reload1.c 2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/reload1.c 2011-09-16 20:16:00.277564886 -0700
+@@ -4155,6 +4155,9 @@
+ }
+ else if (function_invariant_p (x))
+ {
++ enum machine_mode mode;
++
++ mode = GET_MODE (SET_DEST (set));
+ if (GET_CODE (x) == PLUS)
+ {
+ /* This is PLUS of frame pointer and a constant,
+@@ -4167,12 +4170,11 @@
+ reg_equiv_invariant[i] = x;
+ num_eliminable_invariants++;
+ }
+- else if (LEGITIMATE_CONSTANT_P (x))
++ else if (targetm.legitimate_constant_p (mode, x))
+ reg_equiv_constant[i] = x;
+ else
+ {
+- reg_equiv_memory_loc[i]
+- = force_const_mem (GET_MODE (SET_DEST (set)), x);
++ reg_equiv_memory_loc[i] = force_const_mem (mode, x);
+ if (! reg_equiv_memory_loc[i])
+ reg_equiv_init[i] = NULL_RTX;
+ }
+Index: gcc-4_6-branch/gcc/stor-layout.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/stor-layout.c 2011-06-24 08:33:49.000000000 -0700
++++ gcc-4_6-branch/gcc/stor-layout.c 2011-09-16 20:16:00.287564867 -0700
+@@ -546,6 +546,34 @@
+ return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT));
+ }
+
++/* Return the natural mode of an array, given that it is SIZE bytes in
++ total and has elements of type ELEM_TYPE. */
++
++static enum machine_mode
++mode_for_array (tree elem_type, tree size)
++{
++ tree elem_size;
++ unsigned HOST_WIDE_INT int_size, int_elem_size;
++ bool limit_p;
++
++ /* One-element arrays get the component type's mode. */
++ elem_size = TYPE_SIZE (elem_type);
++ if (simple_cst_equal (size, elem_size))
++ return TYPE_MODE (elem_type);
++
++ limit_p = true;
++ if (host_integerp (size, 1) && host_integerp (elem_size, 1))
++ {
++ int_size = tree_low_cst (size, 1);
++ int_elem_size = tree_low_cst (elem_size, 1);
++ if (int_elem_size > 0
++ && int_size % int_elem_size == 0
++ && targetm.array_mode_supported_p (TYPE_MODE (elem_type),
++ int_size / int_elem_size))
++ limit_p = false;
++ }
++ return mode_for_size_tree (size, MODE_INT, limit_p);
++}
+
+ /* Subroutine of layout_decl: Force alignment required for the data type.
+ But if the decl itself wants greater alignment, don't override that. */
+@@ -2039,14 +2067,8 @@
+ && (TYPE_MODE (TREE_TYPE (type)) != BLKmode
+ || TYPE_NO_FORCE_BLK (TREE_TYPE (type))))
+ {
+- /* One-element arrays get the component type's mode. */
+- if (simple_cst_equal (TYPE_SIZE (type),
+- TYPE_SIZE (TREE_TYPE (type))))
+- SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type)));
+- else
+- SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type),
+- MODE_INT, 1));
+-
++ SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type),
++ TYPE_SIZE (type)));
+ if (TYPE_MODE (type) != BLKmode
+ && STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT
+ && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type)))
+Index: gcc-4_6-branch/gcc/target.def
+===================================================================
+--- gcc-4_6-branch.orig/gcc/target.def 2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/target.def 2011-09-16 20:16:00.287564867 -0700
+@@ -1344,6 +1344,13 @@
+ unsigned, (unsigned nunroll, struct loop *loop),
+ NULL)
+
++/* True if X is a legitimate MODE-mode immediate operand. */
++DEFHOOK
++(legitimate_constant_p,
++ "",
++ bool, (enum machine_mode mode, rtx x),
++ default_legitimate_constant_p)
++
+ /* True if the constant X cannot be placed in the constant pool. */
+ DEFHOOK
+ (cannot_force_const_mem,
+@@ -1611,6 +1618,38 @@
+ bool, (enum machine_mode mode),
+ hook_bool_mode_false)
+
++/* True if we should try to use a scalar mode to represent an array,
++ overriding the usual MAX_FIXED_MODE limit. */
++DEFHOOK
++(array_mode_supported_p,
++ "Return true if GCC should try to use a scalar mode to store an array\n\
++of @var{nelems} elements, given that each element has mode @var{mode}.\n\
++Returning true here overrides the usual @code{MAX_FIXED_MODE} limit\n\
++and allows GCC to use any defined integer mode.\n\
++\n\
++One use of this hook is to support vector load and store operations\n\
++that operate on several homogeneous vectors. For example, ARM NEON\n\
++has operations like:\n\
++\n\
++@smallexample\n\
++int8x8x3_t vld3_s8 (const int8_t *)\n\
++@end smallexample\n\
++\n\
++where the return type is defined as:\n\
++\n\
++@smallexample\n\
++typedef struct int8x8x3_t\n\
++@{\n\
++ int8x8_t val[3];\n\
++@} int8x8x3_t;\n\
++@end smallexample\n\
++\n\
++If this hook allows @code{val} to have a scalar mode, then\n\
++@code{int8x8x3_t} can have the same mode. GCC can then store\n\
++@code{int8x8x3_t}s in registers rather than forcing them onto the stack.",
++ bool, (enum machine_mode mode, unsigned HOST_WIDE_INT nelems),
++ hook_bool_mode_uhwi_false)
++
+ /* Compute cost of moving data from a register of class FROM to one of
+ TO, using MODE. */
+ DEFHOOK
+Index: gcc-4_6-branch/gcc/targhooks.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/targhooks.c 2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/targhooks.c 2011-09-16 20:16:00.287564867 -0700
+@@ -1519,4 +1519,15 @@
+ { OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
+
++bool
++default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
++ rtx x ATTRIBUTE_UNUSED)
++{
++#ifdef LEGITIMATE_CONSTANT_P
++ return LEGITIMATE_CONSTANT_P (x);
++#else
++ return true;
++#endif
++}
++
+ #include "gt-targhooks.h"
+Index: gcc-4_6-branch/gcc/targhooks.h
+===================================================================
+--- gcc-4_6-branch.orig/gcc/targhooks.h 2011-06-24 08:33:48.000000000 -0700
++++ gcc-4_6-branch/gcc/targhooks.h 2011-09-16 20:16:00.287564867 -0700
+@@ -183,3 +183,4 @@
+
+ extern void *default_get_pch_validity (size_t *);
+ extern const char *default_pch_valid_p (const void *, size_t);
++extern bool default_legitimate_constant_p (enum machine_mode, rtx);
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 2011-09-16 20:16:00.287564867 -0700
+@@ -0,0 +1,27 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++uint32_t buffer[12];
++
++void __attribute__((noinline))
++foo (uint32_t *a)
++{
++ uint32x4x3_t x;
++
++ x = vld3q_u32 (a);
++ x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
++ vst3q_u32 (a, x);
++}
++
++int
++main (void)
++{
++ buffer[0] = 1;
++ buffer[1] = 2;
++ foo (buffer);
++ return buffer[0] != 3;
++}
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 2011-09-16 20:16:00.287564867 -0700
+@@ -0,0 +1,25 @@
++/* { dg-do run } */
++/* { dg-require-effective-target arm_neon_hw } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++#include "arm_neon.h"
++
++uint32_t buffer[64];
++
++void __attribute__((noinline))
++foo (uint32_t *a)
++{
++ uint32x4x3_t x;
++
++ x = vld3q_u32 (a);
++ a[35] = 1;
++ vst3q_lane_u32 (a + 32, x, 1);
++}
++
++int
++main (void)
++{
++ foo (buffer);
++ return buffer[35] != 1;
++}
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+ out_float32x4_t = vld1q_dup_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x8_t = vld1q_dup_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x16_t = vld1q_dup_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+ out_int16x8_t = vld1q_dup_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-09-16 20:16:00.297564810 -0700
+@@ -15,5 +15,5 @@
+ out_int32x4_t = vld1q_dup_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+ out_int64x2_t = vld1q_dup_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+ out_int8x16_t = vld1q_dup_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x8_t = vld1q_dup_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x4_t = vld1q_dup_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x2_t = vld1q_dup_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-09-16 20:16:00.347564808 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x16_t = vld1q_dup_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-09-16 20:16:00.347564808 -0700
+@@ -16,5 +16,5 @@
+ out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_float32x4_t = vld1q_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x8_t = vld1q_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x16_t = vld1q_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int16x8_t = vld1q_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int32x4_t = vld1q_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int64x2_t = vld1q_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int8x16_t = vld1q_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x8_t = vld1q_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x4_t = vld1q_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x2_t = vld1q_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x16_t = vld1q_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2_t = vld1_dup_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4_t = vld1_dup_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8_t = vld1_dup_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4_t = vld1_dup_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2_t = vld1_dup_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1_t = vld1_dup_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8_t = vld1_dup_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4_t = vld1_dup_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-09-16 20:16:00.357564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2_t = vld1_dup_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-09-16 20:16:00.367564848 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1_t = vld1_dup_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-09-16 20:16:00.367564848 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8_t = vld1_dup_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-09-16 20:16:00.367564848 -0700
+@@ -16,5 +16,5 @@
+ out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-09-16 20:16:00.367564848 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2_t = vld1_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4_t = vld1_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8_t = vld1_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4_t = vld1_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2_t = vld1_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1_t = vld1_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8_t = vld1_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4_t = vld1_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2_t = vld1_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-09-16 20:16:00.377564842 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1_t = vld1_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-09-16 20:16:00.387564830 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8_t = vld1_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+ out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+ out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-09-16 20:16:00.387564830 -0700
+@@ -16,5 +16,5 @@
+ out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-09-16 20:16:00.397564843 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-09-16 20:16:00.397564843 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+ out_float32x4x2_t = vld2q_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+ out_poly16x8x2_t = vld2q_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+ out_poly8x16x2_t = vld2q_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+ out_int16x8x2_t = vld2q_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+ out_int32x4x2_t = vld2q_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+ out_int8x16x2_t = vld2q_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-09-16 20:16:00.397564843 -0700
+@@ -15,6 +15,6 @@
+ out_uint16x8x2_t = vld2q_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,6 +15,6 @@
+ out_uint32x4x2_t = vld2q_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,6 +15,6 @@
+ out_uint8x16x2_t = vld2q_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2x2_t = vld2_dup_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4x2_t = vld2_dup_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8x2_t = vld2_dup_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4x2_t = vld2_dup_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2x2_t = vld2_dup_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-09-16 20:16:00.407564879 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1x2_t = vld2_dup_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8x2_t = vld2_dup_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4x2_t = vld2_dup_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2x2_t = vld2_dup_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1x2_t = vld2_dup_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-09-16 20:16:00.417564906 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8x2_t = vld2_dup_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-09-16 20:16:00.417564906 -0700
+@@ -16,5 +16,5 @@
+ out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2x2_t = vld2_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4x2_t = vld2_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8x2_t = vld2_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4x2_t = vld2_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2x2_t = vld2_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-09-16 20:16:00.427564921 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1x2_t = vld2_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8x2_t = vld2_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4x2_t = vld2_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2x2_t = vld2_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1x2_t = vld2_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-09-16 20:16:00.437564924 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8x2_t = vld2_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-09-16 20:16:00.437564924 -0700
+@@ -16,5 +16,5 @@
+ out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-09-16 20:16:00.437564924 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+ out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+ out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-09-16 20:16:00.447564932 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_float32x4x3_t = vld3q_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_poly16x8x3_t = vld3q_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_poly8x16x3_t = vld3q_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_int16x8x3_t = vld3q_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_int32x4x3_t = vld3q_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_int8x16x3_t = vld3q_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_uint16x8x3_t = vld3q_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-09-16 20:16:00.447564932 -0700
+@@ -15,6 +15,6 @@
+ out_uint32x4x3_t = vld3q_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,6 +15,6 @@
+ out_uint8x16x3_t = vld3q_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2x3_t = vld3_dup_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4x3_t = vld3_dup_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8x3_t = vld3_dup_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4x3_t = vld3_dup_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2x3_t = vld3_dup_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1x3_t = vld3_dup_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8x3_t = vld3_dup_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4x3_t = vld3_dup_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2x3_t = vld3_dup_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1x3_t = vld3_dup_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8x3_t = vld3_dup_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -16,5 +16,5 @@
+ out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2x3_t = vld3_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4x3_t = vld3_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8x3_t = vld3_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4x3_t = vld3_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2x3_t = vld3_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-09-16 20:16:00.457564944 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1x3_t = vld3_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8x3_t = vld3_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4x3_t = vld3_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2x3_t = vld3_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1x3_t = vld3_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8x3_t = vld3_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+ out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+ out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+ out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-09-16 20:16:00.467564964 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,6 +15,6 @@
+ out_float32x4x4_t = vld4q_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,6 +15,6 @@
+ out_poly16x8x4_t = vld4q_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-09-16 20:16:00.467564964 -0700
+@@ -15,6 +15,6 @@
+ out_poly8x16x4_t = vld4q_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+ out_int16x8x4_t = vld4q_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+ out_int32x4x4_t = vld4q_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+ out_int8x16x4_t = vld4q_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+ out_uint16x8x4_t = vld4q_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+ out_uint32x4x4_t = vld4q_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,6 +15,6 @@
+ out_uint8x16x4_t = vld4q_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2x4_t = vld4_dup_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4x4_t = vld4_dup_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8x4_t = vld4_dup_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4x4_t = vld4_dup_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-09-16 20:16:00.477564991 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2x4_t = vld4_dup_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1x4_t = vld4_dup_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8x4_t = vld4_dup_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4x4_t = vld4_dup_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2x4_t = vld4_dup_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1x4_t = vld4_dup_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-09-16 20:16:00.487565006 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8x4_t = vld4_dup_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-09-16 20:16:00.487565006 -0700
+@@ -16,5 +16,5 @@
+ out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-09-16 20:16:00.487565006 -0700
+@@ -16,5 +16,5 @@
+ out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-09-16 20:16:00.487565006 -0700
+@@ -16,5 +16,5 @@
+ out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+ out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+ out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+ out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+ out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+ out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-09-16 20:16:00.497565009 -0700
+@@ -16,5 +16,5 @@
+ out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_float32x2x4_t = vld4_f32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_poly16x4x4_t = vld4_p16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_poly8x8x4_t = vld4_p8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_int16x4x4_t = vld4_s16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_int32x2x4_t = vld4_s32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_int64x1x4_t = vld4_s64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_int8x8x4_t = vld4_s8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-09-16 20:16:00.497565009 -0700
+@@ -15,5 +15,5 @@
+ out_uint16x4x4_t = vld4_u16 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-09-16 20:16:00.507565013 -0700
+@@ -15,5 +15,5 @@
+ out_uint32x2x4_t = vld4_u32 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-09-16 20:16:00.507565013 -0700
+@@ -15,5 +15,5 @@
+ out_uint64x1x4_t = vld4_u64 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-09-16 20:16:00.507565013 -0700
+@@ -15,5 +15,5 @@
+ out_uint8x8x4_t = vld4_u8 (0);
+ }
+
+-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-09-16 20:16:00.507565013 -0700
+@@ -16,5 +16,5 @@
+ vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-09-16 20:16:00.517565031 -0700
+@@ -16,5 +16,5 @@
+ vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,5 +16,5 @@
+ vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-09-16 20:16:00.527565060 -0700
+@@ -16,6 +16,6 @@
+ vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,6 +16,6 @@
+ vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-09-16 20:16:00.537565077 -0700
+@@ -16,5 +16,5 @@
+ vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+ vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+ vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+ vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+ vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+ vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+ vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-09-16 20:16:00.547565082 -0700
+@@ -16,5 +16,5 @@
+ vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+ }
+
+-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,5 +16,5 @@
+ vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-09-16 20:16:00.557565092 -0700
+@@ -16,6 +16,6 @@
+ vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,6 +16,6 @@
+ vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-09-16 20:16:00.567565108 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-09-16 20:16:00.577565135 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-09-16 20:16:00.587565144 -0700
+@@ -16,5 +16,5 @@
+ vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+ }
+
+-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+ vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+ vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+ vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+ vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+ vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,5 +16,5 @@
+ vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+ vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+ vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+ vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+ vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-09-16 20:16:00.597565156 -0700
+@@ -16,6 +16,6 @@
+ vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+ vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+ vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+ vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,6 +16,6 @@
+ vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
+===================================================================
+--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-06-24 08:13:40.000000000 -0700
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-09-16 20:16:00.607565171 -0700
+@@ -16,5 +16,5 @@
+ vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+ }
+
+-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+ /* { dg-final { cleanup-saved-temps } } */
+Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c 2011-09-16 20:16:00.617565191 -0700
+@@ -0,0 +1,9 @@
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_neon } */
++
++int __attribute__ ((vector_size (32))) x;
++void
++foo (void)
++{
++ x <<= x;
++}