diff options
Diffstat (limited to 'toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch')
-rw-r--r-- | toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch new file mode 100644 index 0000000000..3f873e7fe6 --- /dev/null +++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch @@ -0,0 +1,26 @@ +2010-10-13 Chung-Lin Tang <cltang@codesourcery.com> + + Backport from mainline: + + 2010-04-20 James E. Wilson <wilson@codesourcery.com> + + gcc/ + PR rtl-optimization/43520 + * ira-lives.c (ira_implicitly_set_insn_hard_regs): Exclude classes with + zero available registers. + +=== modified file 'gcc/ira-lives.c' +Index: gcc-4.5/gcc/ira-lives.c +=================================================================== +--- gcc-4.5.orig/gcc/ira-lives.c ++++ gcc-4.5/gcc/ira-lives.c +@@ -805,6 +805,9 @@ ira_implicitly_set_insn_hard_regs (HARD_ + ? GENERAL_REGS + : REG_CLASS_FROM_CONSTRAINT (c, p)); + if (cl != NO_REGS ++ /* There is no register pressure problem if all of the ++ regs in this class are fixed. */ ++ && ira_available_class_regs[cl] != 0 + && (ira_available_class_regs[cl] + <= ira_reg_class_nregs[cl][mode])) + IOR_HARD_REG_SET (*set, reg_class_contents[cl]); |