diff options
Diffstat (limited to 'meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch')
-rw-r--r-- | meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch | 101 |
1 files changed, 0 insertions, 101 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch deleted file mode 100644 index 2920466d8f..0000000000 --- a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch +++ /dev/null @@ -1,101 +0,0 @@ -2011-02-24 Chung-Lin Tang <cltang@codesourcery.com> - - Backport from FSF mainline: - - 2010-08-10 Bernd Schmidt <bernds@codesourcery.com> - - PR bootstrap/45177 - * config/arm/arm.c (multiple_operation_profitable_p): Move xscale - test here from arm_gen_load_multiple_1. - (arm_gen_load_multiple_1, arm_gen_store_multiple_1): Use - multiple_operation_profitable_p. - -=== modified file 'gcc/config/arm/arm.c' ---- old/gcc/config/arm/arm.c 2011-02-22 11:38:56 +0000 -+++ new/gcc/config/arm/arm.c 2011-02-24 17:30:32 +0000 -@@ -9728,6 +9728,36 @@ - if (nops == 2 && arm_ld_sched && add_offset != 0) - return false; - -+ /* XScale has load-store double instructions, but they have stricter -+ alignment requirements than load-store multiple, so we cannot -+ use them. -+ -+ For XScale ldm requires 2 + NREGS cycles to complete and blocks -+ the pipeline until completion. -+ -+ NREGS CYCLES -+ 1 3 -+ 2 4 -+ 3 5 -+ 4 6 -+ -+ An ldr instruction takes 1-3 cycles, but does not block the -+ pipeline. -+ -+ NREGS CYCLES -+ 1 1-3 -+ 2 2-6 -+ 3 3-9 -+ 4 4-12 -+ -+ Best case ldr will always win. However, the more ldr instructions -+ we issue, the less likely we are to be able to schedule them well. -+ Using ldr instructions also increases code size. -+ -+ As a compromise, we use ldr for counts of 1 or 2 regs, and ldm -+ for counts of 3 or 4 regs. */ -+ if (nops <= 2 && arm_tune_xscale && !optimize_size) -+ return false; - return true; - } - -@@ -10086,35 +10116,7 @@ - int i = 0, j; - rtx result; - -- /* XScale has load-store double instructions, but they have stricter -- alignment requirements than load-store multiple, so we cannot -- use them. -- -- For XScale ldm requires 2 + NREGS cycles to complete and blocks -- the pipeline until completion. -- -- NREGS CYCLES -- 1 3 -- 2 4 -- 3 5 -- 4 6 -- -- An ldr instruction takes 1-3 cycles, but does not block the -- pipeline. -- -- NREGS CYCLES -- 1 1-3 -- 2 2-6 -- 3 3-9 -- 4 4-12 -- -- Best case ldr will always win. However, the more ldr instructions -- we issue, the less likely we are to be able to schedule them well. -- Using ldr instructions also increases code size. -- -- As a compromise, we use ldr for counts of 1 or 2 regs, and ldm -- for counts of 3 or 4 regs. */ -- if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) -+ if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0)) - { - rtx seq; - -@@ -10166,9 +10168,7 @@ - if (GET_CODE (basereg) == PLUS) - basereg = XEXP (basereg, 0); - -- /* See arm_gen_load_multiple_1 for discussion of -- the pros/cons of ldm/stm usage for XScale. */ -- if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) -+ if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0)) - { - rtx seq; - - |