diff options
Diffstat (limited to 'meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch')
| -rw-r--r-- | meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch new file mode 100644 index 0000000000..02db2b4e7e --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch @@ -0,0 +1,76 @@ + 2010-05-25 Julian Brown <julian@codesourcery.com> + + gcc/ + * config/arm/arm.c (arm_tune_cortex_a5): New. + (arm_override_options): Set above. Set max_insns_skipped to 1 for + Cortex-A5. + * config/arm/arm.h (arm_tune_cortex_a5): Add declaration. + (BRANCH_COST): Set to zero for Cortex-A5 unless optimising for + size. + +2010-07-26 Julian Brown <julian@codesourcery.com> + + Merge from Sourcery G++ 4.4: + + 2009-08-26 Julian Brown <julian@codesourcery.com> + + gcc/config/arm/ + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2010-08-12 14:08:29 +0000 ++++ new/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000 +@@ -671,6 +671,9 @@ + This typically means an ARM6 or ARM7 with MMU or MPU. */ + int arm_tune_wbuf = 0; + ++/* Nonzero if tuning for Cortex-A5. */ ++int arm_tune_cortex_a5 = 0; ++ + /* Nonzero if tuning for Cortex-A9. */ + int arm_tune_cortex_a9 = 0; + +@@ -1582,6 +1585,7 @@ + arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; + arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; + arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; ++ arm_tune_cortex_a5 = (arm_tune == cortexa5) != 0; + arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; + + /* If we are not using the default (ARM mode) section anchor offset +@@ -1880,6 +1884,11 @@ + that is worth skipping is shorter. */ + if (arm_tune_strongarm) + max_insns_skipped = 3; ++ ++ /* Branches can be dual-issued on Cortex-A5, so conditional execution is ++ less appealing. */ ++ if (arm_tune_cortex_a5) ++ max_insns_skipped = 1; + } + + /* Hot/Cold partitioning is not currently supported, since we can't + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000 ++++ new/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000 +@@ -435,6 +435,9 @@ + /* Nonzero if tuning for stores via the write buffer. */ + extern int arm_tune_wbuf; + ++/* Nonzero if tuning for Cortex-A5. */ ++extern int arm_tune_cortex_a5; ++ + /* Nonzero if tuning for Cortex-A9. */ + extern int arm_tune_cortex_a9; + +@@ -2222,7 +2225,8 @@ + /* Try to generate sequences that don't involve branches, we can then use + conditional instructions */ + #define BRANCH_COST(speed_p, predictable_p) \ +- (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \ ++ (TARGET_32BIT ? ((arm_tune_cortex_a5 && !optimize_size) ? 0 \ ++ : (TARGET_THUMB2 && optimize_size ? 1 : 4)) \ + : (optimize > 0 ? 2 : 0)) + + /* Position Independent Code. */ + |