pixman 0.23.6: refresh patches with versions for pixman master

Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>

9 files changed, 93 insertions, 93 deletions

diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0003-ARM-NEON-Some-cleanup-of-bilinear-scanline-functions.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0001-ARM-NEON-Some-cleanup-of-bilinear-scanline-functions.patch
index 338e2ad83e..53ce218da4 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0003-ARM-NEON-Some-cleanup-of-bilinear-scanline-functions.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0001-ARM-NEON-Some-cleanup-of-bilinear-scanline-functions.patch
@@ -1,7 +1,7 @@
-From ed7580525054e6a543694088c561dee525b4ae28 Mon Sep 17 00:00:00 2001
+From 809b8d4e3707c8617cafafb8a16b1b48e2477311 Mon Sep 17 00:00:00 2001
 From: Taekyun Kim <tkq.kim@samsung.com>
 Date: Tue, 20 Sep 2011 19:46:25 +0900
-Subject: [PATCH 3/8] ARM: NEON: Some cleanup of bilinear scanline functions
+Subject: [PATCH 1/8] ARM: NEON: Some cleanup of bilinear scanline functions
 
 Use STRIDE and initial horizontal weight update is done before
 entering interpolation loop. Cache preload for mask and dst.
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0004-ARM-NEON-Bilinear-macro-template-for-instruction-sch.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0002-ARM-NEON-Bilinear-macro-template-for-instruction-sch.patch
index dc8a69f749..4ec821240c 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0004-ARM-NEON-Bilinear-macro-template-for-instruction-sch.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0002-ARM-NEON-Bilinear-macro-template-for-instruction-sch.patch
@@ -1,7 +1,7 @@
-From 524d1cc7acb753167fffdd08d8c10bf71e0634ba Mon Sep 17 00:00:00 2001
+From ce2fd2ac6aab2c14916d332ade47d72b06d504c1 Mon Sep 17 00:00:00 2001
 From: Taekyun Kim <tkq.kim@samsung.com>
 Date: Tue, 20 Sep 2011 21:32:35 +0900
-Subject: [PATCH 4/8] ARM: NEON: Bilinear macro template for instruction scheduling
+Subject: [PATCH 2/8] ARM: NEON: Bilinear macro template for instruction scheduling
 
 This macro template takes 6 code blocks.
 
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0005-ARM-NEON-Replace-old-bilinear-scanline-generator-wit.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0003-ARM-NEON-Replace-old-bilinear-scanline-generator-wit.patch
index 77c43f5f91..7c6f501ac3 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0005-ARM-NEON-Replace-old-bilinear-scanline-generator-wit.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0003-ARM-NEON-Replace-old-bilinear-scanline-generator-wit.patch
@@ -1,7 +1,7 @@
-From 10b257b46f379d9c79483acd55c9a13fff130843 Mon Sep 17 00:00:00 2001
+From 8d0460c4f1b23f3a13e9ff7282b30dd06f10aee1 Mon Sep 17 00:00:00 2001
 From: Taekyun Kim <tkq.kim@samsung.com>
 Date: Fri, 23 Sep 2011 00:03:22 +0900
-Subject: [PATCH 5/8] ARM: NEON: Replace old bilinear scanline generator with new template
+Subject: [PATCH 3/8] ARM: NEON: Replace old bilinear scanline generator with new template
 
 Bilinear scanline functions in pixman-arm-neon-asm-bilinear.S can
 be replaced with new template just by wrapping existing macros.
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0006-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0004-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch
index d982b5ba74..d6c94ba2c9 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0006-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0004-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch
@@ -1,7 +1,7 @@
-From c8f7edaebd510ba120d74102a93ad4d202b0e806 Mon Sep 17 00:00:00 2001
+From b9009d108277b42ebb4c0ea03eb3fb5845106497 Mon Sep 17 00:00:00 2001
 From: Taekyun Kim <tkq.kim@samsung.com>
 Date: Wed, 21 Sep 2011 15:52:13 +0900
-Subject: [PATCH 6/8] ARM: NEON: Instruction scheduling of bilinear over_8888_8888
+Subject: [PATCH 4/8] ARM: NEON: Instruction scheduling of bilinear over_8888_8888
 
 Instructions are reordered to eliminate pipeline stalls and get
 better memory access.
@@ -16,7 +16,7 @@ after  : 61.09 Mpix/s
  1 files changed, 146 insertions(+), 3 deletions(-)
 
 diff --git a/pixman/pixman-arm-neon-asm-bilinear.S b/pixman/pixman-arm-neon-asm-bilinear.S
-index 25bcb24..76937e0 100644
+index 25bcb24..82d248e 100644
 --- a/pixman/pixman-arm-neon-asm-bilinear.S
 +++ b/pixman/pixman-arm-neon-asm-bilinear.S
 @@ -893,15 +893,158 @@ pixman_asm_function fname
@@ -108,31 +108,31 @@ index 25bcb24..76937e0 100644
  .macro bilinear_over_8888_8888_process_pixblock_tail_head
 -    bilinear_over_8888_8888_process_pixblock_tail
 -    bilinear_over_8888_8888_process_pixblock_head
-+        vshll.u16   q2, d20, #8
++                                            vshll.u16   q2, d20, #8
 +    mov         TMP1, X, asr #16
 +    add         X, X, UX
 +    add         TMP1, TOP, TMP1, asl #2
-+        vmlsl.u16   q2, d20, d30
++                                            vmlsl.u16   q2, d20, d30
 +    mov         TMP2, X, asr #16
 +    add         X, X, UX
 +    add         TMP2, TOP, TMP2, asl #2
-+        vmlal.u16   q2, d21, d30
-+        vshll.u16   q3, d22, #8
++                                            vmlal.u16   q2, d21, d30
++                                            vshll.u16   q3, d22, #8
 +    vld1.32     {d20}, [TMP1], STRIDE
-+        vmlsl.u16   q3, d22, d31
-+        vmlal.u16   q3, d23, d31
++                                            vmlsl.u16   q3, d22, d31
++                                            vmlal.u16   q3, d23, d31
 +    vld1.32     {d21}, [TMP1]
 +    vmull.u8    q8, d20, d28
 +    vmlal.u8    q8, d21, d29
-+        vshrn.u32   d0, q0, #16
-+        vshrn.u32   d1, q1, #16
-+        vld1.32     {d2, d3}, [OUT, :128]
-+        pld         [OUT, PF_OFFS]
-+        vshrn.u32   d4, q2, #16
-+        vshr.u16    q15, q12, #8
++                                            vshrn.u32   d0, q0, #16
++                                            vshrn.u32   d1, q1, #16
++                                            vld1.32     {d2, d3}, [OUT, :128]
++                                            pld         [OUT, PF_OFFS]
++                                            vshrn.u32   d4, q2, #16
++                                            vshr.u16    q15, q12, #8
 +    vld1.32     {d22}, [TMP2], STRIDE
-+        vshrn.u32   d5, q3, #16
-+        vmovn.u16   d6, q0
++                                            vshrn.u32   d5, q3, #16
++                                            vmovn.u16   d6, q0
 +    vld1.32     {d23}, [TMP2]
 +    vmull.u8    q9, d22, d28
 +    mov         TMP3, X, asr #16
@@ -142,42 +142,42 @@ index 25bcb24..76937e0 100644
 +    add         X, X, UX
 +    add         TMP4, TOP, TMP4, asl #2
 +    vmlal.u8    q9, d23, d29
-+        vmovn.u16   d7, q2
++                                            vmovn.u16   d7, q2
 +    vld1.32     {d22}, [TMP3], STRIDE
-+        vuzp.8      d6, d7
-+        vuzp.8      d2, d3
-+        vuzp.8      d6, d7
-+        vuzp.8      d2, d3
-+        vdup.32     d4, d7[1]
++                                            vuzp.8      d6, d7
++                                            vuzp.8      d2, d3
++                                            vuzp.8      d6, d7
++                                            vuzp.8      d2, d3
++                                            vdup.32     d4, d7[1]
 +    vld1.32     {d23}, [TMP3]
-+        vmvn.8      d4, d4
++                                            vmvn.8      d4, d4
 +    vmull.u8    q10, d22, d28
 +    vmlal.u8    q10, d23, d29
-+        vmull.u8    q11, d2, d4
-+        vmull.u8    q2, d3, d4
++                                            vmull.u8    q11, d2, d4
++                                            vmull.u8    q2, d3, d4
 +    vshll.u16   q0, d16, #8
 +    vmlsl.u16   q0, d16, d30
-+        vrshr.u16   q1, q11, #8
++                                            vrshr.u16   q1, q11, #8
 +    vmlal.u16   q0, d17, d30
-+        vrshr.u16   q8, q2, #8
-+        vraddhn.u16 d2, q1, q11
-+        vraddhn.u16 d3, q8, q2
++                                            vrshr.u16   q8, q2, #8
++                                            vraddhn.u16 d2, q1, q11
++                                            vraddhn.u16 d3, q8, q2
 +    pld         [TMP4, PF_OFFS]
 +    vld1.32     {d16}, [TMP4], STRIDE
-+        vqadd.u8    q3, q1, q3
++                                            vqadd.u8    q3, q1, q3
 +    vld1.32     {d17}, [TMP4]
 +    pld         [TMP4, PF_OFFS]
 +    vmull.u8    q11, d16, d28
 +    vmlal.u8    q11, d17, d29
-+        vuzp.8      d6, d7
++                                            vuzp.8      d6, d7
 +    vshll.u16   q1, d18, #8
-+        vuzp.8      d6, d7
++                                            vuzp.8      d6, d7
 +    vmlsl.u16   q1, d18, d31
-+        vadd.u16    q12, q12, q13
++                                            vadd.u16    q12, q12, q13
 +    vmlal.u16   q1, d19, d31
 +    vshr.u16    q15, q12, #8
 +    vadd.u16    q12, q12, q13
-+        vst1.32     {d6, d7}, [OUT, :128]!
++                                            vst1.32     {d6, d7}, [OUT, :128]!
  .endm
  
  /* over_8888_8_8888 */
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0007-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0005-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch
index e4e741f906..03b27ac146 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0007-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0005-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch
@@ -1,7 +1,7 @@
-From 94585f9a618821a5c06c3a497902579b4a08b05f Mon Sep 17 00:00:00 2001
+From c98ce663e2a5dd1e65013053f461c3aac9a3922e Mon Sep 17 00:00:00 2001
 From: Taekyun Kim <tkq.kim@samsung.com>
 Date: Mon, 26 Sep 2011 19:04:53 +0900
-Subject: [PATCH 7/8] ARM: NEON: Instruction scheduling of bilinear over_8888_8_8888
+Subject: [PATCH 5/8] ARM: NEON: Instruction scheduling of bilinear over_8888_8_8888
 
 Instructions are reordered to eliminate pipeline stalls and get
 better memory access.
@@ -16,7 +16,7 @@ after  : 50.76 Mpix/s
  1 files changed, 158 insertions(+), 4 deletions(-)
 
 diff --git a/pixman/pixman-arm-neon-asm-bilinear.S b/pixman/pixman-arm-neon-asm-bilinear.S
-index 76937e0..4ab46e1 100644
+index 82d248e..f7913ad 100644
 --- a/pixman/pixman-arm-neon-asm-bilinear.S
 +++ b/pixman/pixman-arm-neon-asm-bilinear.S
 @@ -949,7 +949,7 @@ pixman_asm_function fname
@@ -120,84 +120,84 @@ index 76937e0..4ab46e1 100644
  .macro bilinear_over_8888_8_8888_process_pixblock_tail_head
 -    bilinear_over_8888_8_8888_process_pixblock_tail
 -    bilinear_over_8888_8_8888_process_pixblock_head
-+                                        vshll.u16   q9, d6, #8
++                                            vshll.u16   q9, d6, #8
 +    mov         TMP1, X, asr #16
 +    add         X, X, UX
 +    add         TMP1, TOP, TMP1, asl #2
-+                                        vshll.u16   q10, d2, #8
++                                            vshll.u16   q10, d2, #8
 +    vld1.32     {d0}, [TMP1], STRIDE
 +    mov         TMP2, X, asr #16
 +    add         X, X, UX
 +    add         TMP2, TOP, TMP2, asl #2
-+                                        vmlsl.u16   q9, d6, d30
-+                                        vmlsl.u16   q10, d2, d31
++                                            vmlsl.u16   q9, d6, d30
++                                            vmlsl.u16   q10, d2, d31
 +    vld1.32     {d1}, [TMP1]
 +    mov         TMP3, X, asr #16
 +    add         X, X, UX
 +    add         TMP3, TOP, TMP3, asl #2
-+                                        vmlal.u16   q9, d7, d30
-+                                        vmlal.u16   q10, d3, d31
++                                            vmlal.u16   q9, d7, d30
++                                            vmlal.u16   q10, d3, d31
 +    vld1.32     {d2}, [TMP2], STRIDE
 +    mov         TMP4, X, asr #16
 +    add         X, X, UX
 +    add         TMP4, TOP, TMP4, asl #2
-+                                        vshr.u16    q15, q12, #8
-+                                        vadd.u16    q12, q12, q13
++                                            vshr.u16    q15, q12, #8
++                                            vadd.u16    q12, q12, q13
 +    vld1.32     {d3}, [TMP2]
-+                                        vdup.32     d22, d22[0]
-+                                        vshrn.u32   d18, q9, #16
-+                                        vshrn.u32   d19, q10, #16
++                                            vdup.32     d22, d22[0]
++                                            vshrn.u32   d18, q9, #16
++                                            vshrn.u32   d19, q10, #16
 +    vmull.u8    q2, d0, d28
 +    vmull.u8    q3, d2, d28
-+                                        vmovn.u16   d17, q9
-+                                        vld1.32     {d18, d19}, [OUT, :128]
-+                                        pld         [OUT, #(prefetch_offset * 4)]
++                                            vmovn.u16   d17, q9
++                                            vld1.32     {d18, d19}, [OUT, :128]
++                                            pld         [OUT, #(prefetch_offset * 4)]
 +    vmlal.u8    q2, d1, d29
 +    vmlal.u8    q3, d3, d29
-+                                        vuzp.8      d16, d17
-+                                        vuzp.8      d18, d19
++                                            vuzp.8      d16, d17
++                                            vuzp.8      d18, d19
 +    vshll.u16   q0, d4, #8
 +    vshll.u16   q1, d6, #8
-+                                        vuzp.8      d16, d17
-+                                        vuzp.8      d18, d19
++                                            vuzp.8      d16, d17
++                                            vuzp.8      d18, d19
 +    vmlsl.u16   q0, d4, d30
 +    vmlsl.u16   q1, d6, d31
-+                                        vmull.u8    q10, d16, d22
-+                                        vmull.u8    q11, d17, d22
++                                            vmull.u8    q10, d16, d22
++                                            vmull.u8    q11, d17, d22
 +    vmlal.u16   q0, d5, d30
 +    vmlal.u16   q1, d7, d31
-+                                        vrsra.u16   q10, q10, #8
-+                                        vrsra.u16   q11, q11, #8
++                                            vrsra.u16   q10, q10, #8
++                                            vrsra.u16   q11, q11, #8
 +    vshrn.u32   d0, q0, #16
 +    vshrn.u32   d1, q1, #16
-+                                        vrshrn.u16  d16, q10, #8
-+                                        vrshrn.u16  d17, q11, #8
++                                            vrshrn.u16  d16, q10, #8
++                                            vrshrn.u16  d17, q11, #8
 +    vld1.32     {d2}, [TMP3], STRIDE
-+                                        vdup.32     d22, d17[1]
++                                            vdup.32     d22, d17[1]
 +    vld1.32     {d3}, [TMP3]
-+                                        vmvn.8      d22, d22
++                                            vmvn.8      d22, d22
 +    pld         [TMP4, PF_OFFS]
 +    vld1.32     {d4}, [TMP4], STRIDE
-+                                        vmull.u8    q10, d18, d22
-+                                        vmull.u8    q11, d19, d22
++                                            vmull.u8    q10, d18, d22
++                                            vmull.u8    q11, d19, d22
 +    vld1.32     {d5}, [TMP4]
 +    pld         [TMP4, PF_OFFS]
 +    vmull.u8    q3, d2, d28
-+                                        vrshr.u16   q9, q10, #8
-+                                        vrshr.u16   q15, q11, #8
++                                            vrshr.u16   q9, q10, #8
++                                            vrshr.u16   q15, q11, #8
 +    vmlal.u8    q3, d3, d29
 +    vmull.u8    q1, d4, d28
-+                                        vraddhn.u16 d18, q9, q10
-+                                        vraddhn.u16 d19, q15, q11
++                                            vraddhn.u16 d18, q9, q10
++                                            vraddhn.u16 d19, q15, q11
 +    vmlal.u8    q1, d5, d29
 +    vshr.u16    q15, q12, #8
-+                                        vqadd.u8    q9, q8, q9
++                                            vqadd.u8    q9, q8, q9
 +    vld1.32     {d22[0]}, [MASK]!
-+                                        vuzp.8      d18, d19
++                                            vuzp.8      d18, d19
 +    vadd.u16    q12, q12, q13
-+                                        vuzp.8      d18, d19
++                                            vuzp.8      d18, d19
 +    vmovn.u16   d16, q0
-+                                        vst1.32     {d18, d19}, [OUT, :128]!
++                                            vst1.32     {d18, d19}, [OUT, :128]!
  .endm
  
  /* add_8888_8888 */
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0001-ARM-NEON-Standard-fast-path-src_n_8_8888.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0006-ARM-NEON-Standard-fast-path-src_n_8_8888.patch
index 53e9d72cd2..9588e33682 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0001-ARM-NEON-Standard-fast-path-src_n_8_8888.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0006-ARM-NEON-Standard-fast-path-src_n_8_8888.patch
@@ -1,7 +1,7 @@
-From f7d1d45e30b59b513d48294de50dc86af60ea68c Mon Sep 17 00:00:00 2001
+From 2851a24d4562437cfb333568fcab1ce9861033a8 Mon Sep 17 00:00:00 2001
 From: Taekyun Kim <tkq.kim@samsung.com>
 Date: Mon, 26 Sep 2011 17:03:54 +0900
-Subject: [PATCH 1/8] ARM: NEON: Standard fast path src_n_8_8888
+Subject: [PATCH 6/8] ARM: NEON: Standard fast path src_n_8_8888
 
 Performance numbers of before/after on cortex-a8 @ 1GHz
 
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0002-ARM-NEON-Standard-fast-path-src_n_8_8.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0007-ARM-NEON-Standard-fast-path-src_n_8_8.patch
index d0a4b45462..7c67001cc5 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0002-ARM-NEON-Standard-fast-path-src_n_8_8.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0007-ARM-NEON-Standard-fast-path-src_n_8_8.patch
@@ -1,7 +1,7 @@
-From fc92ad56c5218157a097f6ed0c06196be9f74906 Mon Sep 17 00:00:00 2001
+From 34ce640914e06f2e23a0a93a3a49ec0bfff7497b Mon Sep 17 00:00:00 2001
 From: Taekyun Kim <tkq.kim@samsung.com>
 Date: Mon, 26 Sep 2011 18:33:27 +0900
-Subject: [PATCH 2/8] ARM: NEON: Standard fast path src_n_8_8
+Subject: [PATCH 7/8] ARM: NEON: Standard fast path src_n_8_8
 
 Performance numbers of before/after on cortex-a8 @ 1GHz
 
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0008-Generic-C-implementation-of-pixman_blt-with-overlapp.patch b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0008-Generic-C-implementation-of-pixman_blt-with-overlapp.patch
index 903f1f7f19..34f96ed1d8 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0008-Generic-C-implementation-of-pixman_blt-with-overlapp.patch
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman-0.23.6/0008-Generic-C-implementation-of-pixman_blt-with-overlapp.patch
@@ -1,4 +1,4 @@
-From d65a08904857d87dcd74b87681c9b94390b76eff Mon Sep 17 00:00:00 2001
+From 0c7aa6a3ebc29d7986d2417371df210f3e9a65b4 Mon Sep 17 00:00:00 2001
 From: Siarhei Siamashka <siarhei.siamashka@nokia.com>
 Date: Tue, 16 Mar 2010 16:55:28 +0100
 Subject: [PATCH 8/8] Generic C implementation of pixman_blt with overlapping support
@@ -19,7 +19,7 @@ unrealistic case anyway).
  2 files changed, 61 insertions(+), 3 deletions(-)
 
 diff --git a/pixman/pixman-general.c b/pixman/pixman-general.c
-index 2ccdfcd..6f7bb34 100644
+index 2ccdfcd..90461b6 100644
 --- a/pixman/pixman-general.c
 +++ b/pixman/pixman-general.c
 @@ -227,9 +227,24 @@ general_blt (pixman_implementation_t *imp,
diff --git a/meta-oe/recipes-graphics/xorg-lib/pixman_0.23.6.bb b/meta-oe/recipes-graphics/xorg-lib/pixman_0.23.6.bb
index bbdffef1dd..10bf6e1194 100644
--- a/meta-oe/recipes-graphics/xorg-lib/pixman_0.23.6.bb
+++ b/meta-oe/recipes-graphics/xorg-lib/pixman_0.23.6.bb
@@ -9,16 +9,16 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=14096c769ae0cbb5fcb94ec468be11b3\
                     file://pixman/pixman-arm-neon-asm.h;endline=24;md5=9a9cc1e51abbf1da58f4d9528ec9d49b \
                    "
 
-PR = "${INC_PR}.0"
+PR = "${INC_PR}.1"
 
 SRC_URI = "http://xorg.freedesktop.org/archive/individual/lib/${BPN}-${PV}.tar.gz \
-           file://0003-ARM-NEON-Some-cleanup-of-bilinear-scanline-functions.patch \
-           file://0004-ARM-NEON-Bilinear-macro-template-for-instruction-sch.patch \
-           file://0005-ARM-NEON-Replace-old-bilinear-scanline-generator-wit.patch \
-           file://0006-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch \
-           file://0007-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch \
+           file://0001-ARM-NEON-Some-cleanup-of-bilinear-scanline-functions.patch \
+           file://0002-ARM-NEON-Bilinear-macro-template-for-instruction-sch.patch \
+           file://0003-ARM-NEON-Replace-old-bilinear-scanline-generator-wit.patch \
+           file://0004-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch \
+           file://0005-ARM-NEON-Instruction-scheduling-of-bilinear-over_888.patch \
            file://0008-Generic-C-implementation-of-pixman_blt-with-overlapp.patch \
-"
+          "
 
 SRC_URI[md5sum] = "27eb7a0ec440c89cccd7c396c3581041"
 SRC_URI[sha256sum] = "4e35f49474e78a9430d93caaaea8bbf7e30b65f0da33c31f15a988c25a3ac369"