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author | Koen Kooi <koen@dominion.thruhere.net> | 2011-03-17 21:41:22 +0100 |
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committer | Koen Kooi <koen@dominion.thruhere.net> | 2011-03-17 21:41:22 +0100 |
commit | c58cc7d3796dcee6e93885c835ed04cb566abeb2 (patch) | |
tree | 3eea4d4ef6a4ef79e0f4e025d7012c1a5cc38835 /meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch | |
parent | eec6ab97f712e06eb52c9f7c99e19ffab3ce9d74 (diff) | |
download | meta-openembedded-contrib-c58cc7d3796dcee6e93885c835ed04cb566abeb2.tar.gz |
move layer into meta-oe in preparation for future splits
As per TSC decision
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Diffstat (limited to 'meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch')
-rw-r--r-- | meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch new file mode 100644 index 0000000000..cf06e1ff74 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch @@ -0,0 +1,41 @@ + Backport from mainline: + + gcc/ + 2010-10-26 Jie Zhang <jie@codesourcery.com> + + * doc/invoke.texi: Improve documentation of + -fstrict-volatile-bitfields. + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2010-11-04 12:43:52 +0000 ++++ new/gcc/doc/invoke.texi 2010-11-04 14:29:09 +0000 +@@ -17633,8 +17633,8 @@ + @opindex fstrict-volatile-bitfields + This option should be used if accesses to volatile bitfields (or other + structure fields, although the compiler usually honors those types +-anyway) should use a single access in a mode of the same size as the +-container's type, aligned to a natural alignment if possible. For ++anyway) should use a single access of the width of the ++field's type, aligned to a natural alignment if possible. For + example, targets with memory-mapped peripheral registers might require + all such accesses to be 16 bits wide; with this flag the user could + declare all peripheral bitfields as ``unsigned short'' (assuming short +@@ -17647,11 +17647,13 @@ + any portion of the bitfield, or memory-mapped registers unrelated to + the one being updated. + +-If the target requires strict alignment, and honoring the container ++If the target requires strict alignment, and honoring the field + type would require violating this alignment, a warning is issued. +-However, the access happens as the user requested, under the +-assumption that the user knows something about the target hardware +-that GCC is unaware of. ++If the field has @code{packed} attribute, the access is done without ++honoring the field type. If the field doesn't have @code{packed} ++attribute, the access is done honoring the field type. In both cases, ++GCC assumes that the user knows something about the target hardware ++that it is unaware of. + + The default value of this option is determined by the application binary + interface for the target processor. + |