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authorJuro Bystricky <juro.bystricky@intel.com>2018-03-01 10:32:43 -0800
committerMartin Jansa <Martin.Jansa@gmail.com>2018-03-11 01:14:35 +0000
commit155936a8e5d29d26ef80333920a056f7c3211657 (patch)
tree98ce0ae20e871a0318839dc5ba8fe47a34888546 /meta/recipes-devtools/gcc/gcc-6.4.inc
parent9923939703d918461d789712e14420a38ebf978b (diff)
downloadopenembedded-core-155936a8e5d29d26ef80333920a056f7c3211657.tar.gz
gcc6: Backport few more patches
Backported series of patches from https://github.com/hjl-tools/gcc.git branch /hjl/indirect/gcc-6-branch/master which contains an IA patch series for security related issues Signed-off-by: Juro Bystricky <juro.bystricky@intel.com> Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
Diffstat (limited to 'meta/recipes-devtools/gcc/gcc-6.4.inc')
-rw-r--r--meta/recipes-devtools/gcc/gcc-6.4.inc13
1 files changed, 13 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-6.4.inc b/meta/recipes-devtools/gcc/gcc-6.4.inc
index 66654e62a9..1803917f01 100644
--- a/meta/recipes-devtools/gcc/gcc-6.4.inc
+++ b/meta/recipes-devtools/gcc/gcc-6.4.inc
@@ -88,7 +88,20 @@ BACKPORTS = "\
file://CVE-2016-6131.patch \
file://0057-ARM-PR-82445-suppress-32-bit-aligned-ldrd-strd-peeph.patch \
file://0001-enable-FL_LPAE-flag-for-armv7ve-cores.patch \
+ file://0001-i386-Move-struct-ix86_frame-to-machine_function.patch \
+ file://0002-i386-Use-reference-of-struct-ix86_frame-to-avoid-cop.patch \
+ file://0003-i386-Use-const-reference-of-struct-ix86_frame-to-avo.patch \
+ file://0004-x86-Add-mindirect-branch.patch \
+ file://0005-x86-Add-mfunction-return.patch \
+ file://0006-x86-Add-mindirect-branch-register.patch \
+ file://0007-x86-Add-V-register-operand-modifier.patch \
+ file://0008-x86-Disallow-mindirect-branch-mfunction-return-with-.patch \
+ file://0009-Use-INVALID_REGNUM-in-indirect-thunk-processing.patch \
+ file://0010-i386-Pass-INVALID_REGNUM-as-invalid-register-number.patch \
+ file://0011-i386-Update-mfunction-return-for-return-with-pop.patch \
+ file://0012-i386-Add-TARGET_INDIRECT_BRANCH_REGISTER.patch \
"
+
SRC_URI[md5sum] = "11ba51a0cfb8471927f387c8895fe232"
SRC_URI[sha256sum] = "850bf21eafdfe5cd5f6827148184c08c4a0852a37ccf36ce69855334d2c914d4"