From f72a8257388f3df1d9b1f7ae516295afe227d3e3 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Sun, 12 May 2013 22:42:24 -0700 Subject: binutils: Add broadcom XLP support Signed-off-by: Khem Raj Signed-off-by: Saul Wold --- meta/recipes-devtools/binutils/binutils-2.23.2.inc | 1 + .../binutils-2.23.2/binutils-xlp-support.patch | 398 +++++++++++++++++++++ 2 files changed, 399 insertions(+) create mode 100644 meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch (limited to 'meta/recipes-devtools/binutils') diff --git a/meta/recipes-devtools/binutils/binutils-2.23.2.inc b/meta/recipes-devtools/binutils/binutils-2.23.2.inc index ddbe522c9c..07bc7e0f7f 100644 --- a/meta/recipes-devtools/binutils/binutils-2.23.2.inc +++ b/meta/recipes-devtools/binutils/binutils-2.23.2.inc @@ -29,6 +29,7 @@ SRC_URI = "\ file://mips64-default-ld-emulation.patch \ ${BACKPORT} \ file://binutils-fix-over-array-bounds-issue.patch \ + file://binutils-xlp-support.patch \ " BACKPORT = "\ diff --git a/meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch b/meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch new file mode 100644 index 0000000000..b0f727ac64 --- /dev/null +++ b/meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch @@ -0,0 +1,398 @@ +Upstream-Status: Unknown +Signed-off-by: Khem Raj + +From 26adb06ce515aadfec08ce13109b4b98287f677b Mon Sep 17 00:00:00 2001 +From: Nebu Philips +Date: Fri, 30 Jul 2010 15:10:03 -0700 +Subject: [PATCH] Add support for Netlogic XLP + +Using the mipsisa64r2nlm target, add support for XLP from +Netlogic. Also, update vendor name to NLM wherever applicable. +--- + bfd/aoutx.h | 1 + + bfd/archures.c | 1 + + bfd/bfd-in2.h | 1 + + bfd/config.bfd | 5 +++++ + bfd/cpu-mips.c | 6 ++++-- + bfd/elfxx-mips.c | 8 ++++++++ + binutils/readelf.c | 1 + + config.sub | 6 ++++++ + gas/config/tc-mips.c | 7 ++++++- + gas/configure | 3 +++ + gas/configure.tgt | 2 +- + gas/doc/c-mips.texi | 3 ++- + include/elf/mips.h | 1 + + include/opcode/mips.h | 6 +++++- + ld/configure.tgt | 2 ++ + opcodes/mips-dis.c | 6 ++++++ + opcodes/mips-opc.c | 31 ++++++++++++++++++++----------- + 17 files changed, 73 insertions(+), 17 deletions(-) + +Index: binutils-2.23.2/bfd/aoutx.h +=================================================================== +--- binutils-2.23.2.orig/bfd/aoutx.h 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/bfd/aoutx.h 2013-04-16 04:19:52.741282087 -0700 +@@ -798,6 +798,7 @@ + case bfd_mach_mipsisa64r2: + case bfd_mach_mips_sb1: + case bfd_mach_mips_xlr: ++ case bfd_mach_mips_xlp: + /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ + arch_flags = M_MIPS2; + break; +Index: binutils-2.23.2/bfd/archures.c +=================================================================== +--- binutils-2.23.2.orig/bfd/archures.c 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/bfd/archures.c 2013-04-16 04:19:52.741282087 -0700 +@@ -179,6 +179,7 @@ + .#define bfd_mach_mips_octeonp 6601 + .#define bfd_mach_mips_octeon2 6502 + .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} ++.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *} + .#define bfd_mach_mipsisa32 32 + .#define bfd_mach_mipsisa32r2 33 + .#define bfd_mach_mipsisa64 64 +Index: binutils-2.23.2/bfd/bfd-in2.h +=================================================================== +--- binutils-2.23.2.orig/bfd/bfd-in2.h 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/bfd/bfd-in2.h 2013-04-16 04:19:52.745282088 -0700 +@@ -1908,6 +1908,7 @@ + #define bfd_mach_mips_octeonp 6601 + #define bfd_mach_mips_octeon2 6502 + #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ ++#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */ + #define bfd_mach_mipsisa32 32 + #define bfd_mach_mipsisa32r2 33 + #define bfd_mach_mipsisa64 64 +Index: binutils-2.23.2/bfd/config.bfd +=================================================================== +--- binutils-2.23.2.orig/bfd/config.bfd 2013-04-16 04:19:50.897282052 -0700 ++++ binutils-2.23.2/bfd/config.bfd 2013-04-16 04:19:52.745282088 -0700 +@@ -992,6 +992,11 @@ + targ_defvec=bfd_elf32_littlemips_vec + targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec" + ;; ++ mipsisa64*-*-elf*) ++ targ_defvec=bfd_elf32_tradbigmips_vec ++ targ_selvecs="bfd_elf32_tradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec" ++ want64=true ++ ;; + mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss) + targ_defvec=bfd_elf32_bigmips_vec + targ_selvecs="bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec" +Index: binutils-2.23.2/bfd/cpu-mips.c +=================================================================== +--- binutils-2.23.2.orig/bfd/cpu-mips.c 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/bfd/cpu-mips.c 2013-04-16 04:27:21.097290918 -0700 +@@ -97,7 +97,8 @@ + I_mipsocteonp, + I_mipsocteon2, + I_xlr, +- I_micromips ++ I_micromips, ++ I_xlp + }; + + #define NN(index) (&arch_info_struct[(index) + 1]) +@@ -140,7 +141,8 @@ + N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)), + N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)), + N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), +- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0) ++ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)), ++ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0) + }; + + /* The default architecture is mips:3000, but with a machine number of +Index: binutils-2.23.2/bfd/elfxx-mips.c +=================================================================== +--- binutils-2.23.2.orig/bfd/elfxx-mips.c 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/bfd/elfxx-mips.c 2013-04-16 04:19:52.749282089 -0700 +@@ -6293,6 +6293,9 @@ + case E_MIPS_MACH_XLR: + return bfd_mach_mips_xlr; + ++ case E_MIPS_MACH_XLP: ++ return bfd_mach_mips_xlp; ++ + default: + switch (flags & EF_MIPS_ARCH) + { +@@ -11048,6 +11051,10 @@ + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; + break; + ++ case bfd_mach_mips_xlp: ++ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP; ++ break; ++ + case bfd_mach_mipsisa32: + val = E_MIPS_ARCH_32; + break; +@@ -13639,6 +13646,7 @@ + { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp }, + { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, + { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, ++ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 }, + + /* MIPS64 extensions. */ + { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, +Index: binutils-2.23.2/binutils/readelf.c +=================================================================== +--- binutils-2.23.2.orig/binutils/readelf.c 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/binutils/readelf.c 2013-04-16 04:19:52.753282089 -0700 +@@ -2435,6 +2435,7 @@ + case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break; + case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; + case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; ++ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break; + case 0: + /* We simply ignore the field in this case to avoid confusion: + MIPS ELF does not specify EF_MIPS_MACH, it is a GNU +Index: binutils-2.23.2/gas/config/tc-mips.c +=================================================================== +--- binutils-2.23.2.orig/gas/config/tc-mips.c 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/gas/config/tc-mips.c 2013-04-16 04:19:52.761282087 -0700 +@@ -530,6 +530,7 @@ + || mips_opts.arch == CPU_RM7000 \ + || mips_opts.arch == CPU_VR5500 \ + || mips_opts.micromips \ ++ || mips_opts.arch == CPU_XLP \ + ) + + /* Whether the processor uses hardware interlocks to protect reads +@@ -558,6 +559,7 @@ + && mips_opts.isa != ISA_MIPS3) \ + || mips_opts.arch == CPU_R4300 \ + || mips_opts.micromips \ ++ || mips_opts.arch == CPU_XLP \ + ) + + /* Whether the processor uses hardware interlocks to protect reads +@@ -19176,9 +19178,12 @@ + { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, + { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, + +- /* RMI Xlr */ ++ /* Netlogic Xlr */ + { "xlr", 0, ISA_MIPS64, CPU_XLR }, + ++ /* Netlogic Xlp */ ++ { "xlp", 0, ISA_MIPS64R2, CPU_XLP }, ++ + /* Broadcom XLP. + XLP is mostly like XLR, with the prominent exception that it is + MIPS64R2 rather than MIPS64. */ +Index: binutils-2.23.2/gas/configure +=================================================================== +--- binutils-2.23.2.orig/gas/configure 2013-04-16 04:19:50.353282044 -0700 ++++ binutils-2.23.2/gas/configure 2013-04-16 04:19:52.765282087 -0700 +@@ -12695,6 +12695,9 @@ + mipsisa64r2 | mipsisa64r2el) + mips_cpu=mips64r2 + ;; ++ mipsisa64r2nlm | mipsisa64r2nlmel) ++ mips_cpu=xlp ++ ;; + mipstx39 | mipstx39el) + mips_cpu=r3900 + ;; +Index: binutils-2.23.2/gas/configure.tgt +=================================================================== +--- binutils-2.23.2.orig/gas/configure.tgt 2013-04-16 04:19:50.097282037 -0700 ++++ binutils-2.23.2/gas/configure.tgt 2013-04-16 04:19:52.765282087 -0700 +@@ -310,7 +310,7 @@ + mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;; + mips*-sde-elf*) fmt=elf em=tmips ;; + mips-*-sysv*) fmt=ecoff ;; +- mips-*-elf* | mips-*-rtems*) fmt=elf ;; ++ mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;; + mips-*-netbsd*) fmt=elf em=tmips ;; + mips-*-openbsd*) fmt=elf em=tmips ;; + +Index: binutils-2.23.2/include/elf/mips.h +=================================================================== +--- binutils-2.23.2.orig/include/elf/mips.h 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/include/elf/mips.h 2013-04-16 04:19:52.765282087 -0700 +@@ -268,6 +268,7 @@ + #define E_MIPS_MACH_SB1 0x008a0000 + #define E_MIPS_MACH_OCTEON 0x008b0000 + #define E_MIPS_MACH_XLR 0x008c0000 ++#define E_MIPS_MACH_XLP 0x008e0000 + #define E_MIPS_MACH_OCTEON2 0x008d0000 + #define E_MIPS_MACH_5400 0x00910000 + #define E_MIPS_MACH_5500 0x00980000 +Index: binutils-2.23.2/include/opcode/mips.h +=================================================================== +--- binutils-2.23.2.orig/include/opcode/mips.h 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/include/opcode/mips.h 2013-04-16 04:19:52.769282089 -0700 +@@ -772,8 +772,10 @@ + #define INSN_LOONGSON_2F 0x80000000 + /* Loongson 3A. */ + #define INSN_LOONGSON_3A 0x00000400 +-/* RMI Xlr instruction */ ++/* Netlogic Xlr instruction */ + #define INSN_XLR 0x00000020 ++/* Netlogic Xlp instruction */ ++#define INSN_XLP 0x00000040 + + /* MCU (MicroController) ASE */ + #define INSN_MCU 0x00000010 +@@ -833,6 +835,7 @@ + #define CPU_OCTEONP 6601 + #define CPU_OCTEON2 6502 + #define CPU_XLR 887682 /* decimal 'XLR' */ ++#define CPU_XLP 887680 /* decimal 'XLP' */ + + /* Return true if the given CPU is included in INSN_* mask MASK. */ + +@@ -897,6 +900,9 @@ + case CPU_XLR: + return (mask & INSN_XLR) != 0; + ++ case CPU_XLP: ++ return (mask & INSN_XLP) != 0; ++ + default: + return FALSE; + } +Index: binutils-2.23.2/ld/configure.tgt +=================================================================== +--- binutils-2.23.2.orig/ld/configure.tgt 2013-04-16 04:19:50.897282052 -0700 ++++ binutils-2.23.2/ld/configure.tgt 2013-04-16 04:19:52.769282089 -0700 +@@ -426,6 +426,8 @@ + targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" ;; + mips*-sde-elf*) targ_emul=elf32btsmip + targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; ++mipsisa64*-*-elf*) targ_emul=elf32btsmip ++ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;; + mips*el-*-elf*) targ_emul=elf32elmip ;; + mips*-*-elf*) targ_emul=elf32ebmip ;; + mips*-*-rtems*) targ_emul=elf32ebmip ;; +Index: binutils-2.23.2/opcodes/mips-dis.c +=================================================================== +--- binutils-2.23.2.orig/opcodes/mips-dis.c 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/opcodes/mips-dis.c 2013-04-16 04:19:52.769282089 -0700 +@@ -627,6 +627,12 @@ + mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), + mips_hwr_names_numeric }, + ++ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP, ++ (ISA_MIPS64R2 | INSN_XLP), ++ mips_cp0_names_mips3264r2, ++ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), ++ mips_hwr_names_mips3264r2 }, ++ + /* This entry, mips16, is here only for ISA/processor selection; do + not print its name. */ + { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, +Index: binutils-2.23.2/opcodes/mips-opc.c +=================================================================== +--- binutils-2.23.2.orig/opcodes/mips-opc.c 2013-04-16 04:19:48.241282004 -0700 ++++ binutils-2.23.2/opcodes/mips-opc.c 2013-04-16 04:19:52.773282090 -0700 +@@ -126,6 +126,7 @@ + #define IOCTP (INSN_OCTEONP | INSN_OCTEON2) + #define IOCT2 INSN_OCTEON2 + #define XLR INSN_XLR ++#define XLP INSN_XLP + + #define G1 (T3 \ + ) +@@ -606,6 +607,7 @@ + {"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT }, + {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, + {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, ++{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, XLP }, + {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 }, + {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, + {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, +@@ -638,10 +640,11 @@ + {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, + {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, + {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, +-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR }, ++{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0,0, XLR|XLP }, + {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, + {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, + {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, ++{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, XLP }, + /* dctr and dctw are used on the r5000. */ + {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, + {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, +@@ -697,6 +700,7 @@ + {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, + {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, + {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, ++{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_t, 0, XLP}, + {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, + {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, + {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, +@@ -710,6 +714,8 @@ + /* dmtc2 is at the bottom of the table. */ + /* dmfc3 is at the bottom of the table. */ + /* dmtc3 is at the bottom of the table. */ ++{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_t, 0, XLP}, ++{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_d|RD_s|RD_t, 0, XLP}, + {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCT }, + {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, + {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, +@@ -848,9 +854,9 @@ + {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, + {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, + {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, +-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, ++{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP }, ++{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP }, ++{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP }, + {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, + {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, + {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +@@ -985,7 +991,7 @@ + {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, + {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, + {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, +-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR }, ++{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR|XLP }, + {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, + {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, + {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +@@ -1029,10 +1035,13 @@ + /* move is at the top of the table. */ + {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, + {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR }, ++{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_d|RD_t|RD_C0|WR_C0, 0, XLP }, + {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR }, + {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR }, +-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR }, +-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR }, ++{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_d|RD_t|RD_C0|WR_C0, 0, XLP }, ++{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP }, ++{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP }, ++{"msgsync", "", 0x4a000004, 0xffffffff, 0, 0, XLP }, + {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, + {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, + {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +@@ -1066,7 +1075,7 @@ + {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, + {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, + {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, +-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR }, ++{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR|XLP }, + {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCT }, + {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCT }, + {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCT }, +@@ -1425,9 +1434,9 @@ + {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55}, + {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, + {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, +-{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +-{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, ++{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP }, ++{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP }, ++{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP }, + {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, IOCT|IOCTP|IOCT2 }, + {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 }, + {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, -- cgit 1.2.3-korg