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Various += were used, refactor these to be either = or .= depending on
usuage.
CONFLICTS should be '=', as no leading space is required and they are not
amending any other conflict settings.
The TUNE_CCARGS should be .= so that if the feature does not define a CCARG
blank spaces are not added to the CFLAGS. This is consistent to how the arm
tuning is implemented.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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64-bit is not yet available in Linux, but some non-Linux uses exist.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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We want to allow no version to be configured. This should use the GCC default
which is the latest defined version, currently 11.0.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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Using microblazeeb breaks a number of autoconf recipes, including newlib
components. 'microblaze' is defined as the big-endian version, while
microblazeel is defined as the little-endian version.
config.sub: 2018-07-03
...
| maxq | mb | microblaze | microblazeel | mcore | mep | metag \
...
| microblaze-* | microblazeel-* \
...
microblaze*)
basic_machine=microblaze-xilinx
...
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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Update the Microblaze to v11.0
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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Add architecture and tune includes for MicroBlaze. This covers
architecture configuration as well as tune configuration and features.
The Xilinx MicroBlaze architecture is a soft-core CPU architecture
designed for implementation on Xilinx FPGAs. Because the CPU is a
soft-core it can be configured differently depending on resource and
performance constraints which affect the ABI and supported instructions.
The architecture is also used in other Xilinx products where the core is
implemented as part of fixed silicon (e.g. Xilinx ZynqMP).
The default tune include 'tune-microblaze.inc' provides the baseline (no
features enabled) tune configuration for a target machine. This is
similar to other architectures such that the machine.conf includes a
tune-*.inc. However due to the customizability configuration is
specifically handled on a per machine basis. A machine should configure
the available tune features by setting the available features directly
by appending to the 'TUNE_FEATURES_tune-microblaze' variable.
This tune configuration approach is preferred to avoid the definition of
an otherwise large set of possible tune configurations for the available
features (14 CPU versions and 11 feature configurations), which would
otherwise require >1024 predefined tune configurations.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
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Mark Hatle
Manjukumar Matha
Nathan Rossi