diff options
Diffstat (limited to 'meta/recipes-devtools/qemu/qemu/0001-target-mips-add-24KEc-CPU-definition.patch')
| -rw-r--r-- | meta/recipes-devtools/qemu/qemu/0001-target-mips-add-24KEc-CPU-definition.patch | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/meta/recipes-devtools/qemu/qemu/0001-target-mips-add-24KEc-CPU-definition.patch b/meta/recipes-devtools/qemu/qemu/0001-target-mips-add-24KEc-CPU-definition.patch deleted file mode 100644 index c4dbee7d71..0000000000 --- a/meta/recipes-devtools/qemu/qemu/0001-target-mips-add-24KEc-CPU-definition.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 926bc194f918d46bd93557b15da8153b6a94a1d5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Andr=C3=A9=20Draszik?= <git@andred.net> -Date: Mon, 25 Jul 2016 23:58:22 +0100 -Subject: [PATCH] target-mips: add 24KEc CPU definition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Define a new CPU definition supporting 24KEc cores, similar to -the existing 24Kc, but with added support for DSP instructions -and MIPS16e (and without FPU). - -Signed-off-by: André Draszik <git@andred.net> ---- -Upstream-Status: Submitted [http://lists.nongnu.org/archive/html/qemu-devel/2016-07/msg05778.html] - target-mips/translate_init.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c -index 39ed5c4..6ae23e4 100644 ---- a/target-mips/translate_init.c -+++ b/target-mips/translate_init.c -@@ -256,6 +256,28 @@ static const mips_def_t mips_defs[] = - .mmu_type = MMU_TYPE_R4000, - }, - { -+ .name = "24KEc", -+ .CP0_PRid = 0x00019600, -+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | -+ (MMU_TYPE_R4000 << CP0C0_MT), -+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | -+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | -+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | -+ (1 << CP0C1_CA), -+ .CP0_Config2 = MIPS_CONFIG2, -+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), -+ .CP0_LLAddr_rw_bitmask = 0, -+ .CP0_LLAddr_shift = 4, -+ .SYNCI_Step = 32, -+ .CCRes = 2, -+ /* we have a DSP, but no FPU */ -+ .CP0_Status_rw_bitmask = 0x1378FF1F, -+ .SEGBITS = 32, -+ .PABITS = 32, -+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, -+ .mmu_type = MMU_TYPE_R4000, -+ }, -+ { - .name = "24Kf", - .CP0_PRid = 0x00019300, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | --- -2.8.1 - |