diff options
Diffstat (limited to 'meta/recipes-bsp/u-boot/u-boot/0006-Replace-extern-inline-with-static-inline.patch')
| -rw-r--r-- | meta/recipes-bsp/u-boot/u-boot/0006-Replace-extern-inline-with-static-inline.patch | 1184 |
1 files changed, 1184 insertions, 0 deletions
diff --git a/meta/recipes-bsp/u-boot/u-boot/0006-Replace-extern-inline-with-static-inline.patch b/meta/recipes-bsp/u-boot/u-boot/0006-Replace-extern-inline-with-static-inline.patch new file mode 100644 index 0000000000..52ef687cc6 --- /dev/null +++ b/meta/recipes-bsp/u-boot/u-boot/0006-Replace-extern-inline-with-static-inline.patch @@ -0,0 +1,1184 @@ +From 69ce393f6ef57a8a0029df78dbdc9f9def2dbb8c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?M=C3=A5ns=20Rullg=C3=A5rd?= <mans@mansr.com> +Date: Fri, 6 Nov 2015 12:44:01 +0000 +Subject: [PATCH 6/6] Replace "extern inline" with "static inline" +Organization: O.S. Systems Software LTDA. + +A number of headers define functions as "extern inline" which is +causing problems with gcc5. The reason is that starting with +version 5.1, gcc defaults to the standard C99 semantics for the +inline keyword. + +Under the traditional GNU inline semantics, an "extern inline" +function would never create an external definition, the same +as inline *without* extern in C99. In C99, and "extern inline" +definition is simply an external definition with an inline hint. +In short, the meanings of inline with and without extern are +swapped between GNU and C99. + +The upshot is that all these definitions in header files create +an external definition wherever those headers are included, +resulting in multiple definition errors at link time. + +Changing all these functions to "static inline" fixes the problem +since this works as desired in all gcc versions. Although the +semantics are slightly different (a static inline definition may +result in an actual function being emitted), it works as intended +in practice. + +This patch also removes extern prototype declarations for the +changed functions where they existed. + +Upstream-Status: Submitted [https://patchwork.ozlabs.org/patch/540952/] + +Signed-off-by: Mans Rullgard <mans@mansr.com> +Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> +--- + arch/blackfin/include/asm/delay.h | 4 +-- + arch/m68k/include/asm/bitops.h | 5 ++-- + arch/m68k/include/asm/byteorder.h | 8 +++--- + arch/m68k/include/asm/io.h | 40 ++++++++++++++--------------- + arch/powerpc/include/asm/atomic.h | 8 +++--- + arch/powerpc/include/asm/bitops.h | 35 ++++++++++--------------- + arch/powerpc/include/asm/byteorder.h | 8 +++--- + arch/powerpc/include/asm/io.h | 20 +++++++-------- + arch/powerpc/include/asm/iopin_8260.h | 40 ++++++++++++++--------------- + arch/powerpc/include/asm/iopin_8xx.h | 48 +++++++++++++++++------------------ + arch/sparc/include/asm/irq.h | 4 +-- + arch/sparc/include/asm/psr.h | 6 ++--- + arch/sparc/include/asm/srmmu.h | 30 +++++++++++----------- + include/mpc8260.h | 2 +- + 14 files changed, 125 insertions(+), 133 deletions(-) + +diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h +index 97401a7..f146efd 100644 +--- a/arch/blackfin/include/asm/delay.h ++++ b/arch/blackfin/include/asm/delay.h +@@ -16,7 +16,7 @@ + * Delay routines, using a pre-computed "loops_per_second" value. + */ + +-extern __inline__ void __delay(unsigned long loops) ++static __inline__ void __delay(unsigned long loops) + { + __asm__ __volatile__("1:\t%0 += -1;\n\t" + "cc = %0 == 0;\n\t" +@@ -31,7 +31,7 @@ extern __inline__ void __delay(unsigned long loops) + * first constant multiplications gets optimized away if the delay is + * a constant) + */ +-extern __inline__ void __udelay(unsigned long usecs) ++static __inline__ void __udelay(unsigned long usecs) + { + __delay(usecs); + } +diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h +index f9c434b..6b79a0d 100644 +--- a/arch/m68k/include/asm/bitops.h ++++ b/arch/m68k/include/asm/bitops.h +@@ -10,21 +10,20 @@ + extern void set_bit(int nr, volatile void *addr); + extern void clear_bit(int nr, volatile void *addr); + extern void change_bit(int nr, volatile void *addr); +-extern int test_and_set_bit(int nr, volatile void *addr); + extern int test_and_clear_bit(int nr, volatile void *addr); + extern int test_and_change_bit(int nr, volatile void *addr); + + #ifdef __KERNEL__ + + +-extern inline int test_bit(int nr, __const__ volatile void *addr) ++static inline int test_bit(int nr, __const__ volatile void *addr) + { + __const__ unsigned int *p = (__const__ unsigned int *) addr; + + return (p[nr >> 5] & (1UL << (nr & 31))) != 0; + } + +-extern inline int test_and_set_bit(int nr, volatile void *vaddr) ++static inline int test_and_set_bit(int nr, volatile void *vaddr) + { + char retval; + +diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h +index 908a99b..7244b75 100644 +--- a/arch/m68k/include/asm/byteorder.h ++++ b/arch/m68k/include/asm/byteorder.h +@@ -22,25 +22,25 @@ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x)) >> 24) )) + +-extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) ++static __inline__ unsigned ld_le16(const volatile unsigned short *addr) + { + unsigned result = *addr; + return __sw16(result); + } + +-extern __inline__ void st_le16(volatile unsigned short *addr, ++static __inline__ void st_le16(volatile unsigned short *addr, + const unsigned val) + { + *addr = __sw16(val); + } + +-extern __inline__ unsigned ld_le32(const volatile unsigned *addr) ++static __inline__ unsigned ld_le32(const volatile unsigned *addr) + { + unsigned result = *addr; + return __sw32(result); + } + +-extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) ++static __inline__ void st_le32(volatile unsigned *addr, const unsigned val) + { + *addr = __sw32(val); + } +diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h +index 2d2a519..384308b 100644 +--- a/arch/m68k/include/asm/io.h ++++ b/arch/m68k/include/asm/io.h +@@ -67,28 +67,28 @@ + + #define mb() __asm__ __volatile__ ("" : : : "memory") + +-extern inline void _insb(volatile u8 * port, void *buf, int ns) ++static inline void _insb(volatile u8 * port, void *buf, int ns) + { + u8 *data = (u8 *) buf; + while (ns--) + *data++ = *port; + } + +-extern inline void _outsb(volatile u8 * port, const void *buf, int ns) ++static inline void _outsb(volatile u8 * port, const void *buf, int ns) + { + u8 *data = (u8 *) buf; + while (ns--) + *port = *data++; + } + +-extern inline void _insw(volatile u16 * port, void *buf, int ns) ++static inline void _insw(volatile u16 * port, void *buf, int ns) + { + u16 *data = (u16 *) buf; + while (ns--) + *data++ = __sw16(*port); + } + +-extern inline void _outsw(volatile u16 * port, const void *buf, int ns) ++static inline void _outsw(volatile u16 * port, const void *buf, int ns) + { + u16 *data = (u16 *) buf; + while (ns--) { +@@ -97,14 +97,14 @@ extern inline void _outsw(volatile u16 * port, const void *buf, int ns) + } + } + +-extern inline void _insl(volatile u32 * port, void *buf, int nl) ++static inline void _insl(volatile u32 * port, void *buf, int nl) + { + u32 *data = (u32 *) buf; + while (nl--) + *data++ = __sw32(*port); + } + +-extern inline void _outsl(volatile u32 * port, const void *buf, int nl) ++static inline void _outsl(volatile u32 * port, const void *buf, int nl) + { + u32 *data = (u32 *) buf; + while (nl--) { +@@ -113,14 +113,14 @@ extern inline void _outsl(volatile u32 * port, const void *buf, int nl) + } + } + +-extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) ++static inline void _insw_ns(volatile u16 * port, void *buf, int ns) + { + u16 *data = (u16 *) buf; + while (ns--) + *data++ = *port; + } + +-extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) ++static inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) + { + u16 *data = (u16 *) buf; + while (ns--) { +@@ -128,14 +128,14 @@ extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) + } + } + +-extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) ++static inline void _insl_ns(volatile u32 * port, void *buf, int nl) + { + u32 *data = (u32 *) buf; + while (nl--) + *data++ = *port; + } + +-extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) ++static inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) + { + u32 *data = (u32 *) buf; + while (nl--) { +@@ -159,52 +159,52 @@ extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) + /* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +-extern inline int in_8(volatile u8 * addr) ++static inline int in_8(volatile u8 * addr) + { + return (int)*addr; + } + +-extern inline void out_8(volatile u8 * addr, int val) ++static inline void out_8(volatile u8 * addr, int val) + { + *addr = (u8) val; + } + +-extern inline int in_le16(volatile u16 * addr) ++static inline int in_le16(volatile u16 * addr) + { + return __sw16(*addr); + } + +-extern inline int in_be16(volatile u16 * addr) ++static inline int in_be16(volatile u16 * addr) + { + return (*addr & 0xFFFF); + } + +-extern inline void out_le16(volatile u16 * addr, int val) ++static inline void out_le16(volatile u16 * addr, int val) + { + *addr = __sw16(val); + } + +-extern inline void out_be16(volatile u16 * addr, int val) ++static inline void out_be16(volatile u16 * addr, int val) + { + *addr = (u16) val; + } + +-extern inline unsigned in_le32(volatile u32 * addr) ++static inline unsigned in_le32(volatile u32 * addr) + { + return __sw32(*addr); + } + +-extern inline unsigned in_be32(volatile u32 * addr) ++static inline unsigned in_be32(volatile u32 * addr) + { + return (*addr); + } + +-extern inline void out_le32(volatile unsigned *addr, int val) ++static inline void out_le32(volatile unsigned *addr, int val) + { + *addr = __sw32(val); + } + +-extern inline void out_be32(volatile unsigned *addr, int val) ++static inline void out_be32(volatile unsigned *addr, int val) + { + *addr = val; + } +diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h +index 43a2bb2..87efcca 100644 +--- a/arch/powerpc/include/asm/atomic.h ++++ b/arch/powerpc/include/asm/atomic.h +@@ -19,7 +19,7 @@ typedef struct { int counter; } atomic_t; + extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); + extern void atomic_set_mask(unsigned long mask, unsigned long *addr); + +-extern __inline__ int atomic_add_return(int a, atomic_t *v) ++static __inline__ int atomic_add_return(int a, atomic_t *v) + { + int t; + +@@ -35,7 +35,7 @@ extern __inline__ int atomic_add_return(int a, atomic_t *v) + return t; + } + +-extern __inline__ int atomic_sub_return(int a, atomic_t *v) ++static __inline__ int atomic_sub_return(int a, atomic_t *v) + { + int t; + +@@ -51,7 +51,7 @@ extern __inline__ int atomic_sub_return(int a, atomic_t *v) + return t; + } + +-extern __inline__ int atomic_inc_return(atomic_t *v) ++static __inline__ int atomic_inc_return(atomic_t *v) + { + int t; + +@@ -67,7 +67,7 @@ extern __inline__ int atomic_inc_return(atomic_t *v) + return t; + } + +-extern __inline__ int atomic_dec_return(atomic_t *v) ++static __inline__ int atomic_dec_return(atomic_t *v) + { + int t; + +diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h +index a6bcf3c..986ca96 100644 +--- a/arch/powerpc/include/asm/bitops.h ++++ b/arch/powerpc/include/asm/bitops.h +@@ -7,13 +7,6 @@ + + #include <asm/byteorder.h> + +-extern void set_bit(int nr, volatile void *addr); +-extern void clear_bit(int nr, volatile void *addr); +-extern void change_bit(int nr, volatile void *addr); +-extern int test_and_set_bit(int nr, volatile void *addr); +-extern int test_and_clear_bit(int nr, volatile void *addr); +-extern int test_and_change_bit(int nr, volatile void *addr); +- + /* + * Arguably these bit operations don't imply any memory barrier or + * SMP ordering, but in fact a lot of drivers expect them to imply +@@ -34,7 +27,7 @@ extern int test_and_change_bit(int nr, volatile void *addr); + * These used to be if'd out here because using : "cc" as a constraint + * resulted in errors from egcs. Things may be OK with gcc-2.95. + */ +-extern __inline__ void set_bit(int nr, volatile void * addr) ++static __inline__ void set_bit(int nr, volatile void * addr) + { + unsigned long old; + unsigned long mask = 1 << (nr & 0x1f); +@@ -51,7 +44,7 @@ extern __inline__ void set_bit(int nr, volatile void * addr) + : "cc" ); + } + +-extern __inline__ void clear_bit(int nr, volatile void *addr) ++static __inline__ void clear_bit(int nr, volatile void *addr) + { + unsigned long old; + unsigned long mask = 1 << (nr & 0x1f); +@@ -68,7 +61,7 @@ extern __inline__ void clear_bit(int nr, volatile void *addr) + : "cc"); + } + +-extern __inline__ void change_bit(int nr, volatile void *addr) ++static __inline__ void change_bit(int nr, volatile void *addr) + { + unsigned long old; + unsigned long mask = 1 << (nr & 0x1f); +@@ -85,7 +78,7 @@ extern __inline__ void change_bit(int nr, volatile void *addr) + : "cc"); + } + +-extern __inline__ int test_and_set_bit(int nr, volatile void *addr) ++static __inline__ int test_and_set_bit(int nr, volatile void *addr) + { + unsigned int old, t; + unsigned int mask = 1 << (nr & 0x1f); +@@ -104,7 +97,7 @@ extern __inline__ int test_and_set_bit(int nr, volatile void *addr) + return (old & mask) != 0; + } + +-extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) ++static __inline__ int test_and_clear_bit(int nr, volatile void *addr) + { + unsigned int old, t; + unsigned int mask = 1 << (nr & 0x1f); +@@ -123,7 +116,7 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) + return (old & mask) != 0; + } + +-extern __inline__ int test_and_change_bit(int nr, volatile void *addr) ++static __inline__ int test_and_change_bit(int nr, volatile void *addr) + { + unsigned int old, t; + unsigned int mask = 1 << (nr & 0x1f); +@@ -143,7 +136,7 @@ extern __inline__ int test_and_change_bit(int nr, volatile void *addr) + } + #endif /* __INLINE_BITOPS */ + +-extern __inline__ int test_bit(int nr, __const__ volatile void *addr) ++static __inline__ int test_bit(int nr, __const__ volatile void *addr) + { + __const__ unsigned int *p = (__const__ unsigned int *) addr; + +@@ -152,7 +145,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr) + + /* Return the bit position of the most significant 1 bit in a word */ + /* - the result is undefined when x == 0 */ +-extern __inline__ int __ilog2(unsigned int x) ++static __inline__ int __ilog2(unsigned int x) + { + int lz; + +@@ -160,7 +153,7 @@ extern __inline__ int __ilog2(unsigned int x) + return 31 - lz; + } + +-extern __inline__ int ffz(unsigned int x) ++static __inline__ int ffz(unsigned int x) + { + if ((x = ~x) == 0) + return 32; +@@ -226,7 +219,7 @@ static inline int ffs64(u64 x) + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +-extern __inline__ int ffs(int x) ++static __inline__ int ffs(int x) + { + return __ilog2(x & -x) + 1; + } +@@ -250,7 +243,7 @@ extern __inline__ int ffs(int x) + #define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +-extern __inline__ unsigned long find_next_zero_bit(void * addr, ++static __inline__ unsigned long find_next_zero_bit(void * addr, + unsigned long size, unsigned long offset) + { + unsigned int * p = ((unsigned int *) addr) + (offset >> 5); +@@ -298,7 +291,7 @@ found_middle: + #define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) + + #else +-extern __inline__ int ext2_set_bit(int nr, void * addr) ++static __inline__ int ext2_set_bit(int nr, void * addr) + { + int mask; + unsigned char *ADDR = (unsigned char *) addr; +@@ -311,7 +304,7 @@ extern __inline__ int ext2_set_bit(int nr, void * addr) + return oldbit; + } + +-extern __inline__ int ext2_clear_bit(int nr, void * addr) ++static __inline__ int ext2_clear_bit(int nr, void * addr) + { + int mask; + unsigned char *ADDR = (unsigned char *) addr; +@@ -325,7 +318,7 @@ extern __inline__ int ext2_clear_bit(int nr, void * addr) + } + #endif /* __KERNEL__ */ + +-extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) ++static __inline__ int ext2_test_bit(int nr, __const__ void * addr) + { + __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; + +diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h +index 3f5bcf6..f731d18 100644 +--- a/arch/powerpc/include/asm/byteorder.h ++++ b/arch/powerpc/include/asm/byteorder.h +@@ -5,7 +5,7 @@ + + #ifdef __GNUC__ + +-extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) ++static __inline__ unsigned ld_le16(const volatile unsigned short *addr) + { + unsigned val; + +@@ -13,12 +13,12 @@ extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) + return val; + } + +-extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) ++static __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) + { + __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); + } + +-extern __inline__ unsigned ld_le32(const volatile unsigned *addr) ++static __inline__ unsigned ld_le32(const volatile unsigned *addr) + { + unsigned val; + +@@ -26,7 +26,7 @@ extern __inline__ unsigned ld_le32(const volatile unsigned *addr) + return val; + } + +-extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) ++static __inline__ void st_le32(volatile unsigned *addr, const unsigned val) + { + __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); + } +diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h +index a5257e9..a54fc46 100644 +--- a/arch/powerpc/include/asm/io.h ++++ b/arch/powerpc/include/asm/io.h +@@ -163,7 +163,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) + * is actually performed (i.e. the data has come back) before we start + * executing any following instructions. + */ +-extern inline u8 in_8(const volatile unsigned char __iomem *addr) ++static inline u8 in_8(const volatile unsigned char __iomem *addr) + { + u8 ret; + +@@ -174,7 +174,7 @@ extern inline u8 in_8(const volatile unsigned char __iomem *addr) + return ret; + } + +-extern inline void out_8(volatile unsigned char __iomem *addr, u8 val) ++static inline void out_8(volatile unsigned char __iomem *addr, u8 val) + { + __asm__ __volatile__("sync;\n" + "stb%U0%X0 %1,%0;\n" +@@ -182,7 +182,7 @@ extern inline void out_8(volatile unsigned char __iomem *addr, u8 val) + : "r" (val)); + } + +-extern inline u16 in_le16(const volatile unsigned short __iomem *addr) ++static inline u16 in_le16(const volatile unsigned short __iomem *addr) + { + u16 ret; + +@@ -193,7 +193,7 @@ extern inline u16 in_le16(const volatile unsigned short __iomem *addr) + return ret; + } + +-extern inline u16 in_be16(const volatile unsigned short __iomem *addr) ++static inline u16 in_be16(const volatile unsigned short __iomem *addr) + { + u16 ret; + +@@ -203,18 +203,18 @@ extern inline u16 in_be16(const volatile unsigned short __iomem *addr) + return ret; + } + +-extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val) ++static inline void out_le16(volatile unsigned short __iomem *addr, u16 val) + { + __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); + } + +-extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val) ++static inline void out_be16(volatile unsigned short __iomem *addr, u16 val) + { + __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); + } + +-extern inline u32 in_le32(const volatile unsigned __iomem *addr) ++static inline u32 in_le32(const volatile unsigned __iomem *addr) + { + u32 ret; + +@@ -225,7 +225,7 @@ extern inline u32 in_le32(const volatile unsigned __iomem *addr) + return ret; + } + +-extern inline u32 in_be32(const volatile unsigned __iomem *addr) ++static inline u32 in_be32(const volatile unsigned __iomem *addr) + { + u32 ret; + +@@ -235,13 +235,13 @@ extern inline u32 in_be32(const volatile unsigned __iomem *addr) + return ret; + } + +-extern inline void out_le32(volatile unsigned __iomem *addr, u32 val) ++static inline void out_le32(volatile unsigned __iomem *addr, u32 val) + { + __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); + } + +-extern inline void out_be32(volatile unsigned __iomem *addr, u32 val) ++static inline void out_be32(volatile unsigned __iomem *addr, u32 val) + { + __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); + } +diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h +index 619f3a8..617584d 100644 +--- a/arch/powerpc/include/asm/iopin_8260.h ++++ b/arch/powerpc/include/asm/iopin_8260.h +@@ -23,140 +23,140 @@ iopin_t; + #define IOPIN_PORTC 2 + #define IOPIN_PORTD 3 + +-extern __inline__ void ++static __inline__ void + iopin_set_high(iopin_t *iopin) + { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; + datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); + } + +-extern __inline__ void ++static __inline__ void + iopin_set_low(iopin_t *iopin) + { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; + datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_high(iopin_t *iopin) + { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; + return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_low(iopin_t *iopin) + { + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; + return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_out(iopin_t *iopin) + { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; + dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); + } + +-extern __inline__ void ++static __inline__ void + iopin_set_in(iopin_t *iopin) + { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; + dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_out(iopin_t *iopin) + { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; + return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_in(iopin_t *iopin) + { + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; + return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_odr(iopin_t *iopin) + { + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; + odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); + } + +-extern __inline__ void ++static __inline__ void + iopin_set_act(iopin_t *iopin) + { + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; + odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_odr(iopin_t *iopin) + { + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; + return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_act(iopin_t *iopin) + { + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; + return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_ded(iopin_t *iopin) + { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; + parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); + } + +-extern __inline__ void ++static __inline__ void + iopin_set_gen(iopin_t *iopin) + { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; + parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_ded(iopin_t *iopin) + { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; + return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_gen(iopin_t *iopin) + { + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; + return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_opt2(iopin_t *iopin) + { + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; + sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); + } + +-extern __inline__ void ++static __inline__ void + iopin_set_opt1(iopin_t *iopin) + { + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; + sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_opt2(iopin_t *iopin) + { + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; + return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_opt1(iopin_t *iopin) + { + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; +diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h +index 0123baf..8db0fa2 100644 +--- a/arch/powerpc/include/asm/iopin_8xx.h ++++ b/arch/powerpc/include/asm/iopin_8xx.h +@@ -26,7 +26,7 @@ typedef struct { + #define IOPIN_PORTC 2 + #define IOPIN_PORTD 3 + +-extern __inline__ void ++static __inline__ void + iopin_set_high(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -44,7 +44,7 @@ iopin_set_high(iopin_t *iopin) + } + } + +-extern __inline__ void ++static __inline__ void + iopin_set_low(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -62,7 +62,7 @@ iopin_set_low(iopin_t *iopin) + } + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_high(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -81,7 +81,7 @@ iopin_is_high(iopin_t *iopin) + return 0; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_low(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -100,7 +100,7 @@ iopin_is_low(iopin_t *iopin) + return 0; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_out(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -118,7 +118,7 @@ iopin_set_out(iopin_t *iopin) + } + } + +-extern __inline__ void ++static __inline__ void + iopin_set_in(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -136,7 +136,7 @@ iopin_set_in(iopin_t *iopin) + } + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_out(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -155,7 +155,7 @@ iopin_is_out(iopin_t *iopin) + return 0; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_in(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -174,7 +174,7 @@ iopin_is_in(iopin_t *iopin) + return 0; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_odr(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -186,7 +186,7 @@ iopin_set_odr(iopin_t *iopin) + } + } + +-extern __inline__ void ++static __inline__ void + iopin_set_act(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -198,7 +198,7 @@ iopin_set_act(iopin_t *iopin) + } + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_odr(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -211,7 +211,7 @@ iopin_is_odr(iopin_t *iopin) + return 0; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_act(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -224,7 +224,7 @@ iopin_is_act(iopin_t *iopin) + return 0; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_ded(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -242,7 +242,7 @@ iopin_set_ded(iopin_t *iopin) + } + } + +-extern __inline__ void ++static __inline__ void + iopin_set_gen(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -260,7 +260,7 @@ iopin_set_gen(iopin_t *iopin) + } + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_ded(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -279,7 +279,7 @@ iopin_is_ded(iopin_t *iopin) + return 0; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_gen(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTA) { +@@ -298,7 +298,7 @@ iopin_is_gen(iopin_t *iopin) + return 0; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_opt2(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +@@ -307,7 +307,7 @@ iopin_set_opt2(iopin_t *iopin) + } + } + +-extern __inline__ void ++static __inline__ void + iopin_set_opt1(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +@@ -316,7 +316,7 @@ iopin_set_opt1(iopin_t *iopin) + } + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_opt2(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +@@ -326,7 +326,7 @@ iopin_is_opt2(iopin_t *iopin) + return 0; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_opt1(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +@@ -336,7 +336,7 @@ iopin_is_opt1(iopin_t *iopin) + return 0; + } + +-extern __inline__ void ++static __inline__ void + iopin_set_falledge(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +@@ -345,7 +345,7 @@ iopin_set_falledge(iopin_t *iopin) + } + } + +-extern __inline__ void ++static __inline__ void + iopin_set_anyedge(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +@@ -354,7 +354,7 @@ iopin_set_anyedge(iopin_t *iopin) + } + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_falledge(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +@@ -364,7 +364,7 @@ iopin_is_falledge(iopin_t *iopin) + return 0; + } + +-extern __inline__ uint ++static __inline__ uint + iopin_is_anyedge(iopin_t *iopin) + { + if (iopin->port == IOPIN_PORTC) { +diff --git a/arch/sparc/include/asm/irq.h b/arch/sparc/include/asm/irq.h +index bbe0204..2faf7a0 100644 +--- a/arch/sparc/include/asm/irq.h ++++ b/arch/sparc/include/asm/irq.h +@@ -12,7 +12,7 @@ + #include <asm/psr.h> + + /* Set SPARC Processor Interrupt Level */ +-extern inline void set_pil(unsigned int level) ++static inline void set_pil(unsigned int level) + { + unsigned int psr = get_psr(); + +@@ -20,7 +20,7 @@ extern inline void set_pil(unsigned int level) + } + + /* Get SPARC Processor Interrupt Level */ +-extern inline unsigned int get_pil(void) ++static inline unsigned int get_pil(void) + { + unsigned int psr = get_psr(); + return (psr & PSR_PIL) >> PSR_PIL_OFS; +diff --git a/arch/sparc/include/asm/psr.h b/arch/sparc/include/asm/psr.h +index 70af8e0..a91bdc9 100644 +--- a/arch/sparc/include/asm/psr.h ++++ b/arch/sparc/include/asm/psr.h +@@ -42,7 +42,7 @@ + + #ifndef __ASSEMBLY__ + /* Get the %psr register. */ +-extern __inline__ unsigned int get_psr(void) ++static __inline__ unsigned int get_psr(void) + { + unsigned int psr; + __asm__ __volatile__("rd %%psr, %0\n\t" +@@ -53,7 +53,7 @@ extern __inline__ unsigned int get_psr(void) + return psr; + } + +-extern __inline__ void put_psr(unsigned int new_psr) ++static __inline__ void put_psr(unsigned int new_psr) + { + __asm__ __volatile__("wr %0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t": /* no outputs */ + :"r"(new_psr) +@@ -67,7 +67,7 @@ extern __inline__ void put_psr(unsigned int new_psr) + + extern unsigned int fsr_storage; + +-extern __inline__ unsigned int get_fsr(void) ++static __inline__ unsigned int get_fsr(void) + { + unsigned int fsr = 0; + +diff --git a/arch/sparc/include/asm/srmmu.h b/arch/sparc/include/asm/srmmu.h +index 74b1554..8da2f67 100644 +--- a/arch/sparc/include/asm/srmmu.h ++++ b/arch/sparc/include/asm/srmmu.h +@@ -148,7 +148,7 @@ extern void *srmmu_nocache_pool; + #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR)) + + /* Accessing the MMU control register. */ +-extern __inline__ unsigned int srmmu_get_mmureg(void) ++static __inline__ unsigned int srmmu_get_mmureg(void) + { + unsigned int retval; + __asm__ __volatile__("lda [%%g0] %1, %0\n\t": +@@ -156,14 +156,14 @@ extern __inline__ unsigned int srmmu_get_mmureg(void) + return retval; + } + +-extern __inline__ void srmmu_set_mmureg(unsigned long regval) ++static __inline__ void srmmu_set_mmureg(unsigned long regval) + { + __asm__ __volatile__("sta %0, [%%g0] %1\n\t"::"r"(regval), + "i"(ASI_M_MMUREGS):"memory"); + + } + +-extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) ++static __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) + { + paddr = ((paddr >> 4) & SRMMU_CTX_PMASK); + __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(paddr), +@@ -171,7 +171,7 @@ extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr) + "i"(ASI_M_MMUREGS):"memory"); + } + +-extern __inline__ unsigned long srmmu_get_ctable_ptr(void) ++static __inline__ unsigned long srmmu_get_ctable_ptr(void) + { + unsigned int retval; + +@@ -181,13 +181,13 @@ extern __inline__ unsigned long srmmu_get_ctable_ptr(void) + return (retval & SRMMU_CTX_PMASK) << 4; + } + +-extern __inline__ void srmmu_set_context(int context) ++static __inline__ void srmmu_set_context(int context) + { + __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(context), + "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS):"memory"); + } + +-extern __inline__ int srmmu_get_context(void) ++static __inline__ int srmmu_get_context(void) + { + register int retval; + __asm__ __volatile__("lda [%1] %2, %0\n\t": +@@ -196,7 +196,7 @@ extern __inline__ int srmmu_get_context(void) + return retval; + } + +-extern __inline__ unsigned int srmmu_get_fstatus(void) ++static __inline__ unsigned int srmmu_get_fstatus(void) + { + unsigned int retval; + +@@ -206,7 +206,7 @@ extern __inline__ unsigned int srmmu_get_fstatus(void) + return retval; + } + +-extern __inline__ unsigned int srmmu_get_faddr(void) ++static __inline__ unsigned int srmmu_get_faddr(void) + { + unsigned int retval; + +@@ -217,7 +217,7 @@ extern __inline__ unsigned int srmmu_get_faddr(void) + } + + /* This is guaranteed on all SRMMU's. */ +-extern __inline__ void srmmu_flush_whole_tlb(void) ++static __inline__ void srmmu_flush_whole_tlb(void) + { + __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400), /* Flush entire TLB!! */ + "i"(ASI_M_FLUSH_PROBE):"memory"); +@@ -225,14 +225,14 @@ extern __inline__ void srmmu_flush_whole_tlb(void) + } + + /* These flush types are not available on all chips... */ +-extern __inline__ void srmmu_flush_tlb_ctx(void) ++static __inline__ void srmmu_flush_tlb_ctx(void) + { + __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x300), /* Flush TLB ctx.. */ + "i"(ASI_M_FLUSH_PROBE):"memory"); + + } + +-extern __inline__ void srmmu_flush_tlb_region(unsigned long addr) ++static __inline__ void srmmu_flush_tlb_region(unsigned long addr) + { + addr &= SRMMU_PGDIR_MASK; + __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x200), /* Flush TLB region.. */ +@@ -240,7 +240,7 @@ extern __inline__ void srmmu_flush_tlb_region(unsigned long addr) + + } + +-extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr) ++static __inline__ void srmmu_flush_tlb_segment(unsigned long addr) + { + addr &= SRMMU_REAL_PMD_MASK; + __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x100), /* Flush TLB segment.. */ +@@ -248,7 +248,7 @@ extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr) + + } + +-extern __inline__ void srmmu_flush_tlb_page(unsigned long page) ++static __inline__ void srmmu_flush_tlb_page(unsigned long page) + { + page &= PAGE_MASK; + __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(page), /* Flush TLB page.. */ +@@ -256,7 +256,7 @@ extern __inline__ void srmmu_flush_tlb_page(unsigned long page) + + } + +-extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) ++static __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) + { + unsigned long retval; + +@@ -268,7 +268,7 @@ extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr) + return retval; + } + +-extern __inline__ int srmmu_get_pte(unsigned long addr) ++static __inline__ int srmmu_get_pte(unsigned long addr) + { + register unsigned long entry; + +diff --git a/include/mpc8260.h b/include/mpc8260.h +index 9980c74..75f1b0c 100644 +--- a/include/mpc8260.h ++++ b/include/mpc8260.h +@@ -892,7 +892,7 @@ + #define UPMC 3 + + #if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG) +-extern __inline__ void ++static __inline__ void + reset_8260_watchdog(volatile immap_t *immr) + { + immr->im_siu_conf.sc_swsr = 0x556c; +-- +2.6.2 + |