diff options
| -rw-r--r-- | meta/recipes-devtools/qemu/qemu.inc | 1 | ||||
| -rw-r--r-- | meta/recipes-devtools/qemu/qemu/CVE-2020-13791.patch | 53 |
2 files changed, 54 insertions, 0 deletions
diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc index 618cc50180..57619e8668 100644 --- a/meta/recipes-devtools/qemu/qemu.inc +++ b/meta/recipes-devtools/qemu/qemu.inc @@ -35,6 +35,7 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \ file://CVE-2020-13362.patch \ file://CVE-2020-13659.patch \ file://CVE-2020-13800.patch \ + file://CVE-2020-13791.patch \ " UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar" diff --git a/meta/recipes-devtools/qemu/qemu/CVE-2020-13791.patch b/meta/recipes-devtools/qemu/qemu/CVE-2020-13791.patch new file mode 100644 index 0000000000..049dab914d --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/CVE-2020-13791.patch @@ -0,0 +1,53 @@ +From f7d6a635fa3b7797f9d072e280f065bf3cfcd24d Mon Sep 17 00:00:00 2001 +From: Prasad J Pandit <pjp@fedoraproject.org> +Date: Thu, 4 Jun 2020 17:05:25 +0530 +Subject: [PATCH] pci: assert configuration access is within bounds +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +While accessing PCI configuration bytes, assert that +'address + len' is within PCI configuration space. + +Generally it is within bounds. This is more of a defensive +assert, in case a buggy device was to send 'address' which +may go out of bounds. + +Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> +Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> +Message-Id: <20200604113525.58898-1-ppandit@redhat.com> +Reviewed-by: Michael S. Tsirkin <mst@redhat.com> +Signed-off-by: Michael S. Tsirkin <mst@redhat.com> + +Upstream-Status: Backport [f7d6a635fa3b7797f9d072e280f065bf3cfcd24d] +CVE: CVE-2020-13791 +Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> +--- + hw/pci/pci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/hw/pci/pci.c b/hw/pci/pci.c +index 70c66965f5..7bf2ae6d92 100644 +--- a/hw/pci/pci.c ++++ b/hw/pci/pci.c +@@ -1381,6 +1381,8 @@ uint32_t pci_default_read_config(PCIDevice *d, + { + uint32_t val = 0; + ++ assert(address + len <= pci_config_size(d)); ++ + if (pci_is_express_downstream_port(d) && + ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { + pcie_sync_bridge_lnk(d); +@@ -1394,6 +1396,8 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int + int i, was_irq_disabled = pci_irq_disabled(d); + uint32_t val = val_in; + ++ assert(addr + l <= pci_config_size(d)); ++ + for (i = 0; i < l; val >>= 8, ++i) { + uint8_t wmask = d->wmask[addr + i]; + uint8_t w1cmask = d->w1cmask[addr + i]; +-- +2.20.1 + |