path: root/meta-skeleton
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authorBruce Ashfield <bruce.ashfield@windriver.com>2015-05-11 12:18:27 -0400
committerRichard Purdie <richard.purdie@linuxfoundation.org>2015-05-22 13:34:28 +0100
commit5eaa3c2c57dad400305e5ca64c62b2507fd96a54 (patch)
tree31399b8d37d844500cbd494212ee11b327aa9479 /meta-skeleton
parentdf552f18cf9852e0f04780399b78605c8085d935 (diff)
linux-yocto/3.19: braswell DRM/i915 Graphics fixes
Updating the SRCREVs to integrate the following fixes: 0befa35f4099 drm/i915/chv: Remove DPIO force latency causing interpair skew issue 184e0374e4eb drm/i915: Fix chv cdclk support e2a99b9cd086 drm/i915: Increase the range of sideband address. 9d5d55ede53b drm/i915: Disable DDR DVFS on CHV 96cce945ac97 drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV b5005319da56 drm/i915: Program PFI credits for VLV c7aa33eb3697 drm/i915: Rewrite VLV/CHV watermark code a421d8bcaa6d drm/i915: Make sure PND deadline mode is enabled on VLV/CHV 631afc98c4b5 drm/i915: Read out display FIFO size on VLV/CHV e0dcdc019b8a drm/i915: Pass plane to vlv_compute_drain_latency() a6a5562b7754 drm/i915: Reorganize VLV DDL setup bb662a47ec0c drm/i915: Hide VLV DDL precision handling 3d2d93239cd7 drm/i915: Simplify VLV drain latency computation f68614743b92 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines 86c658c06ede drm/i915: Reduce CHV DDL multiplier to 16/8 8c4cdd96a3f2 drm/i915: Allow pixel clock up to 95% of cdclk on CHV d9d4fb889c2a drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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