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authorAlistair Francis <alistair.francis@wdc.com>2018-07-09 17:04:33 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2018-07-13 16:32:38 +0100
commiteade50afbc267f2e4c6065745cd786e48332086b (patch)
tree5864c0db659dde3cf9cb59d5fd5b7174d6dbe7b4
parent98e8146553c912e869c174674c53e96d8ff01e57 (diff)
downloadopenembedded-core-contrib-eade50afbc267f2e4c6065745cd786e48332086b.tar.gz
openembedded-core-contrib-eade50afbc267f2e4c6065745cd786e48332086b.tar.bz2
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liburcu: Add RISC-V support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Ross Burton <ross.burton@intel.com>
-rw-r--r--meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch157
-rw-r--r--meta/recipes-support/liburcu/liburcu_0.10.1.bb1
2 files changed, 158 insertions, 0 deletions
diff --git a/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch b/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch
new file mode 100644
index 00000000000..b026782bd5e
--- /dev/null
+++ b/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch
@@ -0,0 +1,157 @@
+From fdfad81006c2c964781b616f0a75578507be809c Mon Sep 17 00:00:00 2001
+From: Michael Jeanson <mjeanson@efficios.com>
+Date: Wed, 21 Mar 2018 17:38:41 -0400
+Subject: [PATCH] Add support for the RISC-V architecture
+
+Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go
+through the benchmarks reliably.
+
+Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
+Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
+Upstream-Status: Backport
+---
+ configure.ac | 1 +
+ include/Makefile.am | 2 ++
+ include/urcu/arch/riscv.h | 49 ++++++++++++++++++++++++++++++++++++++++++++
+ include/urcu/uatomic/riscv.h | 44 +++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 96 insertions(+)
+ create mode 100644 include/urcu/arch/riscv.h
+ create mode 100644 include/urcu/uatomic/riscv.h
+
+diff --git a/configure.ac b/configure.ac
+index d0b4a9ac..9145081a 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -151,6 +151,7 @@ AS_CASE([$host_cpu],
+ [tile*], [ARCHTYPE="tile"],
+ [hppa*], [ARCHTYPE="hppa"],
+ [m68k], [ARCHTYPE="m68k"],
++ [riscv*], [ARCHTYPE="riscv"],
+ [ARCHTYPE="unknown"]
+ )
+
+diff --git a/include/Makefile.am b/include/Makefile.am
+index dcdf304b..36667b43 100644
+--- a/include/Makefile.am
++++ b/include/Makefile.am
+@@ -27,6 +27,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \
+ urcu/arch/mips.h \
+ urcu/arch/nios2.h \
+ urcu/arch/ppc.h \
++ urcu/arch/riscv.h \
+ urcu/arch/s390.h \
+ urcu/arch/sparc64.h \
+ urcu/arch/tile.h \
+@@ -43,6 +44,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \
+ urcu/uatomic/mips.h \
+ urcu/uatomic/nios2.h \
+ urcu/uatomic/ppc.h \
++ urcu/uatomic/riscv.h \
+ urcu/uatomic/s390.h \
+ urcu/uatomic/sparc64.h \
+ urcu/uatomic/tile.h \
+diff --git a/include/urcu/arch/riscv.h b/include/urcu/arch/riscv.h
+new file mode 100644
+index 00000000..1fd7d62b
+--- /dev/null
++++ b/include/urcu/arch/riscv.h
+@@ -0,0 +1,49 @@
++#ifndef _URCU_ARCH_RISCV_H
++#define _URCU_ARCH_RISCV_H
++
++/*
++ * arch/riscv.h: definitions for the RISC-V architecture
++ *
++ * Copyright (c) 2018 Michael Jeanson <mjeanson@efficios.com>
++ *
++ * This library is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU Lesser General Public
++ * License as published by the Free Software Foundation; either
++ * version 2.1 of the License, or (at your option) any later version.
++ *
++ * This library is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * Lesser General Public License for more details.
++ *
++ * You should have received a copy of the GNU Lesser General Public
++ * License along with this library; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
++ */
++
++#include <urcu/compiler.h>
++#include <urcu/config.h>
++#include <urcu/syscall-compat.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include <stdlib.h>
++#include <sys/time.h>
++
++/*
++ * On Linux, define the membarrier system call number if not yet available in
++ * the system headers.
++ */
++#if (defined(__linux__) && !defined(__NR_membarrier))
++#define __NR_membarrier 283
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#include <urcu/arch/generic.h>
++
++#endif /* _URCU_ARCH_RISCV_H */
+diff --git a/include/urcu/uatomic/riscv.h b/include/urcu/uatomic/riscv.h
+new file mode 100644
+index 00000000..a6700e17
+--- /dev/null
++++ b/include/urcu/uatomic/riscv.h
+@@ -0,0 +1,44 @@
++/*
++ * Atomic exchange operations for the RISC-V architecture. Let GCC do it.
++ *
++ * Copyright (c) 2018 Michael Jeanson <mjeanson@efficios.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * of this software and associated documentation files (the "Software"), to
++ * deal in the Software without restriction, including without limitation the
++ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
++ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
++ * IN THE SOFTWARE.
++ */
++
++#ifndef _URCU_ARCH_UATOMIC_RISCV_H
++#define _URCU_ARCH_UATOMIC_RISCV_H
++
++#include <urcu/compiler.h>
++#include <urcu/system.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define UATOMIC_HAS_ATOMIC_BYTE
++#define UATOMIC_HAS_ATOMIC_SHORT
++
++#ifdef __cplusplus
++}
++#endif
++
++#include <urcu/uatomic/generic.h>
++
++#endif /* _URCU_ARCH_UATOMIC_RISCV_H */
diff --git a/meta/recipes-support/liburcu/liburcu_0.10.1.bb b/meta/recipes-support/liburcu/liburcu_0.10.1.bb
index 9d5b28b33d1..5eb91e144b6 100644
--- a/meta/recipes-support/liburcu/liburcu_0.10.1.bb
+++ b/meta/recipes-support/liburcu/liburcu_0.10.1.bb
@@ -8,6 +8,7 @@ LIC_FILES_CHKSUM = "file://LICENSE;md5=e548d28737289d75a8f1e01ba2fd7825 \
file://include/urcu/uatomic/x86.h;beginline=4;endline=21;md5=58e50bbd8a2f073bb5500e6554af0d0b"
SRC_URI = "http://lttng.org/files/urcu/userspace-rcu-${PV}.tar.bz2 \
+ file://Add-support-for-the-RISC-V-architecture.patch \
"
SRC_URI[md5sum] = "281a2f92fdc39c40ad6b76f6631fdbd7"