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authorKhem Raj <raj.khem@gmail.com>2016-01-30 06:28:37 +0000
committerRichard Purdie <richard.purdie@linuxfoundation.org>2016-01-30 11:40:41 +0000
commit7a51776a830167e43cbd185505f62f328704e271 (patch)
tree9c79eaf2e68d9d2646fed17551918587755ed489
parent5174b53b33fe6b2f9d71f7c414e2c83bda9f6c94 (diff)
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gcc, qemuppc: Explicitly disable forcing SPE flags
G4 does not have SPE, so we make that explicit in the tune files and since we emulate G4 when building Qemu, we ensure it for qemuppc as well. GCC config for powerpc-linux is made to include SPE by default which is equivalent if the tripet was powerpc-linux*spe, this forces gcc to configure assembler to enable -mspe by default, when we do that then the kernel fails to compile with binutils 2.26, since newer assembler is smart to detect the tlbia instructions are not compatible with SPE and hence the kernel build breaks rightly. We configure the kernel for G4 as well where it enables tlbia instrucitons rightly so because it thinks its being configured for power4. So we keep the options but do not force -mspe down to assembler as default. Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
-rw-r--r--meta/conf/machine/include/tune-ppc7400.inc2
-rw-r--r--meta/conf/machine/qemuppc.conf2
-rw-r--r--meta/recipes-devtools/gcc/gcc-5.3/0030-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch24
3 files changed, 19 insertions, 9 deletions
diff --git a/meta/conf/machine/include/tune-ppc7400.inc b/meta/conf/machine/include/tune-ppc7400.inc
index 8bfda56c25..425e8bd215 100644
--- a/meta/conf/machine/include/tune-ppc7400.inc
+++ b/meta/conf/machine/include/tune-ppc7400.inc
@@ -3,7 +3,7 @@ DEFAULTTUNE ?= "ppc7400"
require conf/machine/include/powerpc/arch-powerpc.inc
TUNEVALID[ppc7400] = "Enable ppc7400 specific processor optimizations"
-TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'ppc7400', ' -mcpu=7400', '', d)}"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'ppc7400', ' -mcpu=7400 -mno-spe', '', d)}"
AVAILTUNES += "ppc7400"
TUNE_FEATURES_tune-ppc7400 = "m32 fpu-hard ppc7400 altivec"
diff --git a/meta/conf/machine/qemuppc.conf b/meta/conf/machine/qemuppc.conf
index 85cbbf798d..bf0038ddba 100644
--- a/meta/conf/machine/qemuppc.conf
+++ b/meta/conf/machine/qemuppc.conf
@@ -5,6 +5,8 @@
require conf/machine/include/qemu.inc
require conf/machine/include/tune-ppc7400.inc
+TARGET_CC_KERNEL_ARCH = "-mno-spe"
+
KERNEL_IMAGETYPE = "vmlinux"
SERIAL_CONSOLES = "115200;ttyS0 115200;ttyS1"
diff --git a/meta/recipes-devtools/gcc/gcc-5.3/0030-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch b/meta/recipes-devtools/gcc/gcc-5.3/0030-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch
index e7ca360ae5..57051871b3 100644
--- a/meta/recipes-devtools/gcc/gcc-5.3/0030-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch
+++ b/meta/recipes-devtools/gcc/gcc-5.3/0030-Enable-SPE-AltiVec-generation-on-powepc-linux-target.patch
@@ -19,11 +19,11 @@ Signed-off-by: Alexandru-Cezar Sardan <alexandru.sardan@freescale.com>
gcc/config.gcc | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
-diff --git a/gcc/config.gcc b/gcc/config.gcc
-index dd0739d..3825bd5 100644
---- a/gcc/config.gcc
-+++ b/gcc/config.gcc
-@@ -2343,7 +2343,14 @@ powerpc-*-rtems*)
+Index: gcc-5.3.0/gcc/config.gcc
+===================================================================
+--- gcc-5.3.0.orig/gcc/config.gcc
++++ gcc-5.3.0/gcc/config.gcc
+@@ -2346,7 +2346,14 @@ powerpc-*-rtems*)
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-rtems rs6000/t-ppccomm"
;;
powerpc*-*-linux*)
@@ -39,6 +39,14 @@ index dd0739d..3825bd5 100644
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-ppccomm"
extra_objs="$extra_objs rs6000-linux.o"
---
-2.6.3
-
+Index: gcc-5.3.0/gcc/config/rs6000/linuxspe.h
+===================================================================
+--- gcc-5.3.0.orig/gcc/config/rs6000/linuxspe.h
++++ gcc-5.3.0/gcc/config/rs6000/linuxspe.h
+@@ -27,6 +27,3 @@
+ #undef TARGET_DEFAULT
+ #define TARGET_DEFAULT MASK_STRICT_ALIGN
+ #endif
+-
+-#undef ASM_DEFAULT_SPEC
+-#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"